Update psoc6hal to 1.1.1.11145.

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal.h

@@ -18,7 +18,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -35,7 +35,13 @@
 *******************************************************************************/
 
 /**
-* \defgroup group_hal HAL Drivers
+* \addtogroup group_hal HAL Drivers
+* This section documents the drivers which form the stable API of the Cypress HAL.
+* In order to remain portable across platforms and HAL versions, applications should
+* rely only on functionality documented in this section.
+* \{
+* \defgroup group_result Result Type
+* \}
 */
 
 #pragma once
@@ -46,10 +52,12 @@
 #include "cyhal_adc.h"
 #include "cyhal_crc.h"
 #include "cyhal_dac.h"
+#include "cyhal_dma.h"
 #include "cyhal_flash.h"
 #include "cyhal_gpio.h"
 #include "cyhal_hwmgr.h"
 #include "cyhal_i2c.h"
+#include "cyhal_ezi2c.h"
 #include "cyhal_interconnect.h"
 #include "cyhal_lptimer.h"
 #include "cyhal_pwm.h"

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc.h

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -29,8 +29,21 @@
 * \addtogroup group_hal_adc ADC (Analog to Digital Converter)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress ADC.
+* High level interface for interacting with the analog to digital converter (ADC).
 *
+* Each ADC instance supports one or more selectable channels, each
+* of which can perform conversions on a different pin.
+* See the device datasheet for details about which pins support ADC conversion.
+*
+* In order to use the ADC, first call cyhal_adc_init to initialize an ADC instance.
+* Then call cyhal_adc_channel_init to initialize one or more channels associated with
+* that instance.
+*
+* All channels are single-ended.
+* The values returned by the read API are relative to the ADC's voltage range, which
+* is device specific.
+*
+* \defgroup group_hal_adc_common Common
 * \defgroup group_hal_adc_functions ADC Functions
 * \defgroup group_hal_adc_channel_functions ADC Channel Functions
 */
@@ -59,12 +72,6 @@ extern "C" {
 /** No channels available */
 #define CYHAL_ADC_RSLT_NO_CHANNELS (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_ADC, 3))
 
-
-/**
-* \addtogroup group_hal_adc_functions
-* \{
-*/
-
 /** Initialize ADC peripheral
  *
  * @param[out] obj The adc object to initialize
@@ -84,13 +91,6 @@ cy_rslt_t cyhal_adc_init(cyhal_adc_t *obj, cyhal_gpio_t pin, const cyhal_clock_d
  */
 void cyhal_adc_free(cyhal_adc_t *obj);
 
-/** \} group_hal_adc_functions */
-
-/**
-* \addtogroup group_hal_adc_channel_functions
-* \{
-*/
-
 /** Initialize a single-ended ADC channel.
  *
  * Configures the pin used by ADC.
@@ -116,8 +116,6 @@ void cyhal_adc_channel_free(cyhal_adc_channel_t *obj);
  */
 uint16_t cyhal_adc_read_u16(const cyhal_adc_channel_t *obj);
 
-/** \} group_hal_adc_channel_functions */
-
 #if defined(__cplusplus)
 }
 #endif

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_analog_common.h

@@ -7,7 +7,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -29,13 +29,13 @@
 extern "C" {
 #endif
 
-/** 
+/**
  * Initialize the programmable analog. This utilizes reference counting to avoid
  * repeatedly initializing the analog subsystem when multiple analog blocks are in use
  * */
 void cyhal_analog_init();
 
-/** 
+/**
  * Uninitialize the programmable analog. This utilizes reference counting to avoid
  * disabling the analog subsystem until all blocks which require it have been freed.
  */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc.h

@@ -2,14 +2,14 @@
 * \file cyhal_crc.h
 *
 * \brief
-* Provides a high level interface for interacting with the Cypress CRC accelerator. 
+* Provides a high level interface for interacting with the Cypress CRC accelerator.
 * This interface abstracts out the chip specific details. If any chip specific
 * functionality is necessary, or performance is critical the low level functions
 * can be used directly.
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -29,8 +29,15 @@
 * \addtogroup group_hal_crc CRC (Cyclic Redundancy Check)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress CRC.
+* High level interface for interacting with the cyclic redundancy check (CRC), which provides hardware
+* accelerated CRC computations.
+* The CRC APIs are structured to enable usage in situations where the entire input data
+* set is not available in memory at one time. Therefore, each conversion consists of three steps:
+* * A single call to cyhal_crc_start, to initialize data structures for this computation
+* * One or more calls to cyhal_crc_compute, to provide chunks of data.
+* * A single call to cyhal_crc_finish, to finalize the computation and retrieve the result.
 *
+* Many of the algorithm parameters can be customized; see crc_algorithm_t for more details.
 */
 
 #pragma once

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc_impl.h

@@ -1,13 +1,13 @@
-/***************************************************************************//** 
+/***************************************************************************//**
  * \file cyhal_crc_impl.h
 *
 * Description:
-* Provides a high level interface for interacting with the Cypress CRC accelerator. 
+* Provides a high level interface for interacting with the Cypress CRC accelerator.
 * This is a wrapper around the lower level PDL API.
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crypto_common.h

@@ -2,12 +2,12 @@
 * \file cyhal_crypto_common.h
 *
 * Description:
-* This file provides common defines, addresses, and functions required by drivers 
+* This file provides common defines, addresses, and functions required by drivers
 * using the Crypto block.
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dac.h

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -29,8 +29,13 @@
 * \addtogroup group_hal_dac DAC (Digital to Analog Converter)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress DAC.
+* High level interface for interacting with the digital to analog converter (DAC).
 *
+* This block drives a pin with a firmware configurable voltage. See the device datasheet
+* for details on which pins support DAC output.
+*
+* The cyhal_dac_write and cyhal_dac_read APIs are defined relative to the DAC's output
+* voltage range, which is device dependent.
 */
 
 #pragma once

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma.h

@@ -0,0 +1,185 @@
+/***************************************************************************//**
+* \file cyhal_dma.h
+*
+* \brief
+* Provides a high level interface for interacting with the Cypress DMA.
+* This interface abstracts out the chip specific details. If any chip specific
+* functionality is necessary, or performance is critical the low level functions
+* can be used directly.
+*
+********************************************************************************
+* \copyright
+<<<<<<< HEAD
+* Copyright 2018-2019 Cypress Semiconductor Corporation
+=======
+* Copyright 2018-2020 Cypress Semiconductor Corporation
+>>>>>>> Minor consistancy cleanup for HAL documentation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/**
+* \addtogroup group_hal_dma DMA (Direct Memory Access)
+* \ingroup group_hal
+* \{
+* High level interface for interacting with the direct memory access (DMA). Allows the user to
+* initialize and configure a DMA channel in order to trigger data transfers to
+* and from memory and peripherals. The transfers occur independently of the CPU
+* and are triggered in software. Multiple channels are available with
+* user-selectable priority and transfer characteristics.
+*/
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "cy_result.h"
+#include "cyhal_hw_types.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/** Invalid transfer width parameter error */
+#define CYHAL_DMA_RSLT_ERR_INVALID_TRANSFER_WIDTH    (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DMA, 0))
+/** Invalid parameter error */
+#define CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER         (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DMA, 1))
+/** Invalid priority parameter error */
+#define CYHAL_DMA_RSLT_ERR_INVALID_PRIORITY          (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DMA, 2))
+/** Invalid src or dst addr alignment error */
+#define CYHAL_DMA_RSLT_ERR_INVALID_ALIGNMENT         (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DMA, 3))
+/** Invalid burst_size paramenter error */
+#define CYHAL_DMA_RSLT_ERR_INVALID_BURST_SIZE        (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DMA, 4))
+/** Channel busy error */
+#define CYHAL_DMA_RSLT_ERR_CHANNEL_BUSY              (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DMA, 5))
+/** Transfer has already been started warning */
+#define CYHAL_DMA_RSLT_WARN_TRANSFER_ALREADY_STARTED (CY_RSLT_CREATE(CY_RSLT_TYPE_WARNING, CYHAL_RSLT_MODULE_DMA, 6))
+/** Unsupported hardware error */
+#define CYHAL_DMA_RSLT_FATAL_UNSUPPORTED_HARDWARE    (CY_RSLT_CREATE(CY_RSLT_TYPE_FATAL, CYHAL_RSLT_MODULE_DMA, 7))
+
+/** Direction for DMA transfers. */
+typedef enum
+{
+    CYHAL_DMA_DIRECTION_MEM2MEM,       //!< Memory to memory
+    CYHAL_DMA_DIRECTION_MEM2PERIPH,    //!< Memory to peripheral
+    CYHAL_DMA_DIRECTION_PERIPH2MEM,    //!< Peripheral to memory
+    CYHAL_DMA_DIRECTION_PERIPH2PERIPH, //!< Peripheral to peripheral
+} cyhal_dma_direction_t;
+
+/** Flags enum of DMA events. Multiple events can be enabled. */
+typedef enum
+{
+    CYHAL_DMA_NO_INTR             = 0,      //!< No interrupt
+    CYHAL_DMA_TRANSFER_COMPLETE   = 1 << 0, //!< Indicates that a burst or full transfer has completed
+    CYHAL_DMA_SRC_BUS_ERROR       = 1 << 1, //!< Indicates that there is a source bus error
+    CYHAL_DMA_DST_BUS_ERROR       = 1 << 2, //!< Indicates that there is a destination bus error
+    CYHAL_DMA_SRC_MISAL           = 1 << 3, //!< Indicates that the source address is not aligned
+    CYHAL_DMA_DST_MISAL           = 1 << 4, //!< Indicates that the destination address is not aligned
+    CYHAL_DMA_CURR_PTR_NULL       = 1 << 5, //!< Indicates that the current descriptor pointer is null
+    CYHAL_DMA_ACTIVE_CH_DISABLED  = 1 << 6, //!< Indicates that the active channel is disabled
+    CYHAL_DMA_DESCR_BUS_ERROR     = 1 << 7, //!< Indicates that there has been a descriptor bus error
+} cyhal_dma_event_t;
+
+/** If burst_size is used, selects whether a single trigger of the channel
+ * transfers a single burst of burst_size or a full transfer of size length
+ * (that is, every burst is triggered). This will also select when a trigger
+ * complete event will occur; after each burst or after the full transfer */
+typedef enum
+{
+    CYHAL_DMA_TRANSFER_BURST, //!< A single burst is triggered and a transfer completion event will occur after the burst
+    CYHAL_DMA_TRANSFER_FULL,  //!< All bursts are triggered and a single transfer completion event will occur at the end of all of them
+} cyhal_dma_transfer_action_t;
+
+/** \brief Configuration of a DMA channel. When configuring address,
+ * increments, and transfer width keep in mind your hardware may have more
+ * stringent address and data alignment requirements. */
+typedef struct
+{
+    uint32_t src_addr;                  //!< Source address
+    int16_t  src_increment;             //!< Source address auto increment amount in multiples of transfer_width
+    uint32_t dst_addr;                  //!< Destination address
+    int16_t  dst_increment;             //!< Destination address auto increment amount in multiples of transfer_width
+    uint8_t  transfer_width;            //!< Transfer width in bits. Valid values are: 8, 16, or 32
+    uint32_t length;                    //!< Number of elements to be transferred in total
+    uint32_t burst_size;                //!< Number of elements to be transferred per trigger. If set to 0 every element is transferred, otherwise burst_size must evenly divide length.
+    cyhal_dma_transfer_action_t action; //!< Sets the behavior of the channel when triggered (using start_transfer). Ignored if burst_size is not configured.
+} cyhal_dma_cfg_t;
+
+/** Event handler for DMA interrupts */
+typedef void (*cyhal_dma_event_callback_t)(void *callback_arg, cyhal_dma_event_t event);
+
+/** Initialize the DMA peripheral.
+ *
+ * @param[out] obj          The DMA object to initialize
+ * @param[in]  priority     The priority of this DMA operation relative to others. The number of priority levels which are supported is hardware dependent. All implementations define a CYHAL_DMA_PRIORITY_DEFAULT constant which is always valid. If supported, implementations will also define CYHAL_DMA_PRIORITY_HIGH, CYHAL_DMA_PRIORITY_MEDIUM, and CYHAL_DMA_PRIORITY_LOW. The behavior of any other value is implementation defined. See the implementation-specific DMA documentation for more details.
+ * @param[in]  direction    The direction memory is copied
+ * @return The status of the init request
+ */
+cy_rslt_t cyhal_dma_init(cyhal_dma_t *obj, uint8_t priority, cyhal_dma_direction_t direction);
+
+/** Free the DMA object. Freeing a DMA object while a transfer is in
+    progress (see @ref cyhal_dma_is_busy) is invalid.
+ *
+ * @param[in,out] obj The DMA object
+ */
+void cyhal_dma_free(cyhal_dma_t *obj);
+
+/** Setup a DMA descriptor for specified resource
+ *
+ * @param[in] obj    The DMA object
+ * @param[in] cfg    Configuration parameters for the transfer
+ * @return The status of the configure request
+ */
+cy_rslt_t cyhal_dma_configure(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg);
+
+/** Initiates DMA channel transfer for specified DMA object
+ *
+ * @param[in] obj    The DMA object
+ * @return The status of the start_transfer request
+ */
+cy_rslt_t cyhal_dma_start_transfer(cyhal_dma_t *obj);
+
+/** Checks whether a transfer is pending or running on the DMA channel
+ *
+ * @param[in] obj    The DMA object
+ * @return True if DMA channel is busy
+ */
+bool cyhal_dma_is_busy(cyhal_dma_t *obj);
+
+/** The DMA callback handler registration
+ *
+ * @param[in] obj          The DMA object
+ * @param[in] callback     The callback handler which will be invoked when an event triggers
+ * @param[in] callback_arg Generic argument that will be provided to the callback when called
+ */
+void cyhal_dma_register_callback(cyhal_dma_t *obj, cyhal_dma_event_callback_t callback, void *callback_arg);
+
+/** Configure DMA event enablement.
+ *
+ * @param[in] obj            The DMA object
+ * @param[in] event          The DMA event type
+ * @param[in] intr_priority  The priority for NVIC interrupt events. The priority from the most recent call will take precedence, i.e all events will have the same priority.
+ * @param[in] enable         True to turn on interrupts, False to turn off
+ */
+void cyhal_dma_enable_event(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intr_priority, bool enable);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#ifdef CYHAL_DMA_IMPL_HEADER
+#include CYHAL_DMA_IMPL_HEADER
+#endif /* CYHAL_DMA_IMPL_HEADER */
+
+/** \} group_hal_dma */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_dmac.h

@@ -0,0 +1,94 @@
+/***************************************************************************//**
+* \file cyhal_dma_dmac.h
+*
+* \brief
+* Defines a high level interface for interacting with the Cypress DMAC.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cyhal_dma.h"
+
+/**
+ * \addtogroup group_hal_psoc6_dma_dmac DMAC (Direct Memory Access Controller)
+ * \ingroup group_hal_psoc6_dma
+ * \{
+ * Implementation specific interface for using the DMAC DMA peripheral
+ */
+
+#pragma once
+
+#ifdef CY_IP_M4CPUSS_DMAC
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/** Initialize the DMAC peripheral
+ *
+ * @param[out] obj          The DMA object to initialize
+ * @param[in]  priority     The priority of this DMA operation relative to others. Values must be between 0-3 with 0 being the highest priority.
+ * @return The status of the init request
+ */
+cy_rslt_t cyhal_dma_init_dmac(cyhal_dma_t *obj, uint8_t priority);
+
+/** Frees the DMAC specific object 
+ *
+ * @param[in,out] obj The DMA object
+ */
+void cyhal_dma_free_dmac(cyhal_dma_t *obj);
+
+/** Setup a DMAC descriptor for the dma resource 
+ *
+ * @param[in] obj    The DMA object
+ * @param[in] cfg    Configuration parameters for the transfer
+ * @return The status of the configure request
+ */
+cy_rslt_t cyhal_dma_configure_dmac(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg);
+
+/** Start a DMAC transfer 
+ *
+ * Initiates DMA channel transfer for specified DMA object
+ * @param[in] obj    The DMA object
+ * @return The status of the start_transfer request
+ */
+cy_rslt_t cyhal_dma_start_transfer_dmac(cyhal_dma_t *obj);
+
+/** Configure DMAC event enablement.
+ *
+ * @param[in] obj           The DMA object
+ * @param[in] event         The DMA event type
+ * @param[in] intrPriority  The priority for NVIC interrupt events. The priority from the most recent call will take precedence, i.e all events will have the same priority.
+ * @param[in] enable        True to turn on interrupts, False to turn off
+ */
+void cyhal_dma_enable_event_dmac(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intrPriority, bool enable);
+
+/** Checks whether a transfer is pending or running on the DMA channel
+ *
+ * @param[in] obj    The DMA object
+ * @return True if DMA channel is busy
+ */
+bool cyhal_dma_is_busy_dmac(cyhal_dma_t *obj);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* CY_IP_M4CPUSS_DMAC */
+
+/** \} group_hal_psoc6_dma_dmac */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_dw.h

@@ -0,0 +1,94 @@
+/***************************************************************************//**
+* \file cyhal_dma_dw.h
+*
+* \brief
+* Defines a high level interface for interacting with the Cypress Datawire DMA.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cyhal_dma.h"
+
+/**
+ * \addtogroup group_hal_psoc6_dma_dw DW (Datawire)
+ * \ingroup group_hal_psoc6_dma
+ * \{
+ * Implementation specific interface for using the Datawire DMA peripheral
+ */
+
+#pragma once
+
+#ifdef CY_IP_M4CPUSS_DMA
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/** Initialize the Datawire peripheral. 
+ *
+ * @param[out] obj          The DMA object to initialize
+ * @param[in]  priority     The priority of this DMA operation relative to others. Values must be between 0-3 with 0 being the highest priority.
+ * @return The status of the init request
+ */
+cy_rslt_t cyhal_dma_init_dw(cyhal_dma_t *obj, uint8_t priority);
+
+/** Frees the Datawire specific DMA object 
+ *
+ * @param[in,out] obj The DMA object
+ */
+void cyhal_dma_free_dw(cyhal_dma_t *obj);
+
+/** Setup a Datawire descriptor for the dma resource
+ *
+ * @param[in] obj    The DMA object
+ * @param[in] cfg    Configuration prameters for the transfer
+ * @return The status of the configure request
+ */
+cy_rslt_t cyhal_dma_configure_dw(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg);
+
+/** Start a Datawire transfer 
+ *
+ * Initiates DMA channel transfer for specified DMA object
+ * @param[in] obj    The DMA object
+ * @return The status of the start_transfer request
+ */
+cy_rslt_t cyhal_dma_start_transfer_dw(cyhal_dma_t *obj);
+
+/** Configure Datawire event enablement.
+ *
+ * @param[in] obj           The DMA object
+ * @param[in] event         The DMA event type
+ * @param[in] intrPriority  The priority for NVIC interrupt events. The priority from the most recent call will take precedence, i.e all events will have the same priority.
+ * @param[in] enable        True to turn on interrupts, False to turn off
+ */
+void cyhal_dma_enable_event_dw(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intrPriority, bool enable);
+
+/** Checks whether a transfer is pending or running on the DMA channel
+ *
+ * @param[in] obj    The DMA object
+ * @return True if DMA channel is busy
+ */
+bool cyhal_dma_is_busy_dw(cyhal_dma_t *obj);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* CY_IP_M4CPUSS_DMA */
+
+/** \} group_hal_psoc6_dma_dw */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_impl.h

@@ -0,0 +1,73 @@
+/***************************************************************************//**
+* \file cyhal_dma_impl.h
+*
+* \brief
+* Implementation details of Cypress Datawire/DMAC DMA.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#pragma once
+
+#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/** \addtogroup group_hal_psoc6_dma DMA (Direct Memory Access)
+ * \ingroup group_hal_psoc6
+ * \{
+ * DW (DataWire) is one of two DMA hardware implementations for PSOC6. DW is
+ * designed for low latency memory to peripheral or peripheral to memory
+ * transfers but can also perform memory to memory transfers and peripheral to
+ * peripheral transfers.
+ *
+ * DMAC (Direct Memory Access Controller) is the second of two DMA hardware
+ * implementations for PSOC6. DMAC is designed with high memory bandwidth for
+ * large memory to memory transfers but can perform peripheral to memory,
+ * memory to peripheral, and peripheral to peripheral transfers.
+ *
+ * Which DMA type is used is dependent on the exact hardware and number of DMA
+ * channels already in use. This implementation will attempt to use DMAC first
+ * for memory to memory transfers and Datawire otherwise but either type may be
+ * used. */
+
+/** Default DMA channel priority */
+#define CYHAL_DMA_PRIORITY_DEFAULT    CYHAL_DMA_PRIORITY_LOW
+/** High DMA channel priority */
+#define CYHAL_DMA_PRIORITY_HIGH       0
+/** Medium DMA channel priority */
+#define CYHAL_DMA_PRIORITY_MEDIUM     1
+/** Low DMA channel priority */
+#define CYHAL_DMA_PRIORITY_LOW        3
+
+/** \cond INTERNAL */
+/** Hal-Triggers uses bit 8 to denote a one to one trigger, whereas, the PDL
+ * SwTrigger function uses bit 5 to denote a one to one trigger. */
+#define HAL_TRIGGERS_1TO1_MASK (0x80)
+#define PDL_TRIGGERS_1TO1_MASK (0x10)
+/** \endcond */
+
+/** \} group_hal_psoc6_dma */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_ezi2c.h

@@ -0,0 +1,186 @@
+/***************************************************************************//**
+* \file cyhal_ezi2c.h
+*
+* \brief
+* Provides a high level interface for interacting with the Cypress EZI2C.
+* This interface abstracts out the chip specific details. If any chip specific
+* functionality is necessary, or performance is critical the low level functions
+* can be used directly.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/******************************************************************************
+* Provides a high level Cypress EZI2C Slave interface for interacting with
+* an I2C master.
+* This interface abstracts out the chip specific details. If any chip specific
+* functionality is necessary, or performance is critical the low level functions
+* can be used directly.
+*
+* Cypress EZI2C emulates a common I2C EEPROM interface that acts like dual-port
+* memory between the external master and your code. Once the interface is setup,
+* your code can read/write freely from the specified buffer(s).
+* All I2C transactions to/from the master are handled automatically.
+*******************************************************************************/
+
+/**
+* \addtogroup group_hal_ezi2c EZI2C (Inter-Integrated Circuit)
+* \ingroup group_hal
+* \{
+* High level interface for interacting with the Cypress EZ Inter-Integrated Circuit (EZI2C).
+*/
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "cy_result.h"
+#include "cyhal_hw_types.h"
+#include "cyhal_modules.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/** The requested resource type is invalid */
+#define CYHAL_EZI2C_RSLT_ERR_INVALID_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_EZI2C, 0))
+/** Can not reach desired data rate */
+#define CYHAL_EZI2C_RSLT_ERR_CAN_NOT_REACH_DR (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_EZI2C, 1))
+/** Number of addresses is not valid */
+#define CYHAL_EZI2C_RSLT_ERR_NUM_ADDR_NOT_VALID (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_EZI2C, 2))
+/** Number of addresses is not valid */
+#define CYHAL_EZI2C_RSLT_ERR_CHECK_USER_CONFIG (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_EZI2C, 3))
+
+/** Size of Sub-Address */
+typedef enum
+{
+    CYHAL_EZI2C_SUB_ADDR8_BITS,    /**< Sub-address is 8 bits  */
+    CYHAL_EZI2C_SUB_ADDR16_BITS    /**< Sub-address is 16 bits */
+} cyhal_ezi2c_sub_addr_size_t;
+
+/** Size of Sub-Address */
+typedef enum
+{
+    CYHAL_EZI2C_DATA_RATE_100KHZ = 100000,
+    CYHAL_EZI2C_DATA_RATE_400KHZ = 400000,
+    CYHAL_EZI2C_DATA_RATE_1MHZ   = 1000000
+} cyhal_ezi2c_data_rate_t;
+
+/** Return codes of ezi2c */
+typedef enum
+{
+    /** Each EZI2C slave status is encoded in a separate bit, therefore multiple bits may be set to indicate the current status */
+    CYHAL_EZI2C_STATUS_OK     = 0x0UL,   /**< Operation completed successfully */
+    CYHAL_EZI2C_STATUS_READ1  = 0x01UL,  /**< The Read transfer intended for the primary slave address is complete */
+    CYHAL_EZI2C_STATUS_WRITE1 = 0x02UL,  /**< The Write transfer intended for the primary slave address is complete */
+    CYHAL_EZI2C_STATUS_READ2  = 0x04UL,  /**< The Read transfer intended for the secondary slave address is complete */
+    CYHAL_EZI2C_STATUS_WRITE2 = 0x08UL,  /**< The Write transfer intended for the secondary slave address is complete */
+    CYHAL_EZI2C_STATUS_BUSY   = 0x10UL,  /**< A transfer intended for the primary address or secondary address is in progress */
+    CYHAL_EZI2C_STATUS_ERR    = 0x20UL   /**< An error occurred during a transfer intended for the primary or secondary slave address */
+
+} cyhal_ezi2c_status_t;
+
+/** Enum to enable/disable/report interrupt cause flags. When an event is triggered
+ * the status can be obtained by calling \ref cyhal_ezi2c_get_activity_status.
+ * \note This is a placeholder for now. It may be extended in the future.
+ */
+typedef enum
+{
+    CYHAL_EZI2C_EVENT_NONE                     = 0,       /* No event */
+} cyhal_ezi2c_event_t;
+
+/** Handler for I2C events */
+typedef void (*cyhal_ezi2c_event_callback_t)(void *callback_arg, cyhal_ezi2c_event_t event);
+
+/** Initial EZI2C sub configuration */
+typedef struct
+{
+    /** The 7-bit right justified primary slave address */
+    uint8_t slave_address;
+    /** A pointer to the data buffer for the primary/secondary slave address */
+    uint8_t *buf;
+    /** The size of the buffer assigned to the primary/secondary slave address */
+    uint32_t buf_size;
+    /** The Read/Write boundary within the buffer assigned to the primary/secondary slave address.
+    * This specifies the number of data bytes from the beginning of the buffer with
+    * read and write access for the master. Data bytes at this value or greater are read
+    * only by the master */
+    uint32_t buf_rw_boundary;
+} cyhal_ezi2c_slave_cfg_t;
+
+/** Initial EZI2C configuration */
+typedef struct
+{
+    /** Number of addresses (one or two). If set "true" - use two addresses otherwise ("false") one */
+    bool two_addresses;
+    /** When set, the slave will wake the device from Deep Sleep on an address match */
+    bool enable_wake_from_sleep;
+    /** Maximum frequency that the I2C Slave bus runs at. Supports standard data rates of 100/400/1000 kbps */
+    cyhal_ezi2c_data_rate_t data_rate;
+    /** Refer to cyhal_ezi2c_slave_cfg_t for details. This config structure is mandatory. */
+    cyhal_ezi2c_slave_cfg_t slave1_cfg;
+    /** Refer to cyhal_ezi2c_slave_cfg_t for details. This config structure is optional. */
+    /** Set it if user want to use dual-port addressing otherwise leave blank */
+    cyhal_ezi2c_slave_cfg_t slave2_cfg;
+    /** The size of the sub-address, can either be 8 or 16 bits */
+    cyhal_ezi2c_sub_addr_size_t sub_address_size;
+} cyhal_ezi2c_cfg_t;
+
+/** Initialize the EZI2C (slave), and configures its specifieds pins and clock.
+ *
+ * @param[out] obj The I2C object
+ * @param[in]  sda The sda pin
+ * @param[in]  scl The scl pin
+ * @param[in]  clk The clock to use can be shared, if NULL a new clock will be allocated
+ * @param[in]  cfg The ezi2c configuration (refer to cyhal_ezi2c_cfg_t for details)
+ * @return The status of the init request
+ */
+cy_rslt_t cyhal_ezi2c_init(cyhal_ezi2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, const cyhal_clock_divider_t *clk, const cyhal_ezi2c_cfg_t *cfg);
+
+/** Deinitialize the ezi2c object
+ *
+ * @param[in,out] obj The ezi2c object
+ */
+void cyhal_ezi2c_free(cyhal_ezi2c_t *obj);
+
+/**
+ * EZI2C slave get activity status
+ * This function returns a non-zero value if an I2C Read or Write
+ * cycle has occurred since the last time this function was called.
+ *
+ * @param[in] obj The EZI2C object
+ *
+ * @return The status of the EZI2C (see cyhal_ezi2c_status_t for details)
+ */
+cyhal_ezi2c_status_t cyhal_ezi2c_get_activity_status(cyhal_ezi2c_t *obj);
+
+/** The EZI2C event callback handler registration
+ *
+ * @param[in] obj          The EZI2C object
+ * @param[in] callback     The callback handler which will be invoked when an event triggers
+ * @param[in] callback_arg Generic argument that will be provided to the callback when called
+ */
+void cyhal_ezi2c_register_callback(cyhal_ezi2c_t *obj, cyhal_ezi2c_event_callback_t callback, void *callback_arg);
+
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** \} group_hal_ezi2c */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_flash.h

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -29,7 +29,11 @@
 * \addtogroup group_hal_flash Flash
 * \ingroup group_hal
 * \{
-* Flash HAL high-level description
+* High level interface for interacting with internal flash memory.
+*
+* This driver allows data to be read from and written to flash. It also
+* provides the ability to obtain information about the address and
+* characteristics of the flash block(s) contained on the device.
 */
 
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio.h

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -29,7 +29,54 @@
 * \addtogroup group_hal_gpio GPIO (General Purpose Input Output)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress GPIO.
+* High level interface for configuring and interacting with general purpose input/outputs (GPIO).
+*
+* The GPIO driver provides functions to configure and initialize GPIO, and to read and write data to the pin.
+* The driver also supports interrupt generation on GPIO signals with rising, falling or both edges.
+*
+* \note The APIs in this driver need not be used if a GPIO is to be used as an input or output of peripherals like I2C or PWM.
+* The respective peripheral's driver will utilize the GPIO interface to configure and initialize its GPIO pins.
+*
+* \section subsection_gpio_features Features
+* * Configurable GPIO pin direction - \ref cyhal_gpio_direction_t
+* * Configurable GPIO pin drive modes - \ref cyhal_gpio_drive_mode_t
+* * Configurable analog and digital characteristics
+* * Configurable edge-triggered interrupts and callback assignment on GPIO events - \ref cyhal_gpio_event_t
+*
+* \section subsection_gpio_quickstart Quick Start
+* \ref cyhal_gpio_init can be used for a simple GPIO initialization by providing the pin number (<b>pin</b>), pin direction (<b>direction</b>),
+* pin drive mode (<b>drive_mode</b>) and the initial value on the pin (<b>init_val</b>).
+*
+* \section subsection_gpio_sample_snippets Code Snippets
+*
+* \subsection subsection_gpio_snippet_1 Snippet 1: Reading value from GPIO
+* The following snippet initializes GPIO pin \ref P0_0 as an input with high impedance digital drive mode and initial value = <b>false</b> (low). A value is read
+* from the pin and stored to a uint8_t variable (<b>read_val</b>).
+
+* \snippet gpio.c snippet_cyhal_gpio_read
+
+* \subsection subsection_gpio_snippet_2 Snippet 2: Writing value to a GPIO
+* The following snippet initializes GPIO pin \ref P0_0 as an output pin with strong drive mode and initial value = <b>false</b> (low).
+* A value = <b>true</b> (high) is written to the output driver.
+
+* \snippet gpio.c snippet_cyhal_gpio_write
+
+* \subsection subsection_gpio_snippet_3 Snippet 3: Reconfiguring a GPIO
+* The following snippet shows how to reconfigure a GPIO pin during run-time using the firmware. The GPIO pin \ref P0_0
+* is first initialized as an output pin with strong drive mode. The pin is then reconfigured as an input with high impedance digital drive mode.
+* \note \ref cyhal_gpio_configure only changes the <b>direction</b> and the <b>drive_mode</b>
+* of the pin. Previously set pin value is retained.
+*
+* \snippet gpio.c snippet_cyhal_gpio_reconfigure
+
+* \subsection subsection_gpio_snippet_4 Snippet 4: Interrupts on GPIO events
+* GPIO events can be mapped to an interrupt and assigned to a callback function. The callback function needs to be first registered and
+* then the event needs to be enabled.
+** The following snippet initializes GPIO pin \ref P0_0 as an input pin. It registers a callback function and enables detection
+* of a falling edge event to trigger the callback.
+* \note If no argument needs to be passed to the callback function then a NULL can be passed during registering. <br>
+*
+* \snippet gpio.c snippet_cyhal_gpio_interrupt
 */
 
 #pragma once
@@ -43,6 +90,7 @@
 extern "C" {
 #endif /* __cplusplus */
 
+
 /*******************************************************************************
 *       Defines
 *******************************************************************************/
@@ -70,8 +118,14 @@ typedef enum {
 } cyhal_gpio_direction_t;
 
 /** Pin drive mode */
+
+/** \note When the <b> drive_mode </b> of the <b> pin </b> is set to <b> CYHAL_GPIO_DRIVE_PULL_NONE </b>,
+ * it is set to <b> CYHAL_GPIO_DRIVE_STRONG </b> if the <b> direction </b>
+ * of the <b> pin </b> is <b> CYHAL_GPIO_DIR_OUTPUT </b> or <b> CYHAL_GPIO_DIR_BIDIRECTIONAL</b>.
+ * If not, the <b> drive_mode </b> of the <b> pin </b> is set to <b> CYHAL_GPIO_DRIVE_NONE</b>.
+ */
 typedef enum {
-    CYHAL_GPIO_DRIVE_NONE,                /**< No drive; Hi-Z */
+    CYHAL_GPIO_DRIVE_NONE,                /**< Digital Hi-Z */
     CYHAL_GPIO_DRIVE_ANALOG,              /**< Analog Hi-Z */
     CYHAL_GPIO_DRIVE_PULLUP,              /**< Pull-up resistor */
     CYHAL_GPIO_DRIVE_PULLDOWN,            /**< Pull-down resistor */
@@ -89,16 +143,17 @@ typedef void (*cyhal_gpio_event_callback_t)(void *callback_arg, cyhal_gpio_event
 *       Functions
 *******************************************************************************/
 
-/** Initialize the GPIO pin
+/** Initialize the GPIO pin <br>
+ * See \ref subsection_gpio_snippet_1.
  *
- * @param[in] pin       The GPIO pin to initialize
+ * @param[in] pin         The GPIO pin to initialize
- * @param[in] direction The pin direction
+ * @param[in] direction   The pin direction
- * @param[in] drvMode   The pin drive mode
+ * @param[in] drive_mode  The pin drive mode
- * @param[in] initVal   Initial value on the pin
+ * @param[in] init_val    Initial value on the pin
  *
  * @return The status of the init request
  */
-cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drvMode, bool initVal);
+cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drive_mode, bool init_val);
 
 /** Uninitialize the gpio peripheral and the cyhal_gpio_t object
  *
@@ -106,7 +161,8 @@ cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cy
  */
 void cyhal_gpio_free(cyhal_gpio_t pin);
 
-/** Configure the GPIO pin
+/** Configure the GPIO pin <br>
+ * See \ref subsection_gpio_snippet_3.
  *
  * @param[in] pin       The GPIO pin
  * @param[in] direction The pin direction
@@ -116,27 +172,30 @@ void cyhal_gpio_free(cyhal_gpio_t pin);
  */
 cy_rslt_t cyhal_gpio_configure(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drvMode);
 
-/** Set the output value for the pin. This only works for output & in_out pins.
+/** Set the output value for the pin. This only works for output & in_out pins. <br>
+ * See \ref subsection_gpio_snippet_2.
  *
  * @param[in] pin   The GPIO object
  * @param[in] value The value to be set (high = true, low = false)
  */
 void cyhal_gpio_write(cyhal_gpio_t pin, bool value);
 
-/** Read the input value.  This only works for input & in_out pins.
+/** Read the input value.  This only works for \ref CYHAL_GPIO_DIR_INPUT & \ref CYHAL_GPIO_DIR_BIDIRECTIONAL pins. <br>
+ * See \ref subsection_gpio_snippet_1.
  *
  * @param[in]  pin   The GPIO object
  * @return The value of the IO (true = high, false = low)
  */
 bool cyhal_gpio_read(cyhal_gpio_t pin);
 
-/** Toggle the output value
+/** Toggle the output value <br>
- *
+ * See \ref subsection_gpio_snippet_4.
  * @param[in]  pin   The GPIO object
  */
 void cyhal_gpio_toggle(cyhal_gpio_t pin);
 
-/** Register/clear a callback handler for pin events
+/** Register/clear a callback handler for pin events <br>
+ * See \ref subsection_gpio_snippet_4.
  *
  * @param[in] pin            The pin number
  * @param[in] callback       The function to call when the specified event happens. Pass NULL to unregister the handler.
@@ -144,17 +203,18 @@ void cyhal_gpio_toggle(cyhal_gpio_t pin);
  */
 void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t callback, void *callback_arg);
 
-/** Enable or Disable the specified GPIO event
+/** Enable or Disable the specified GPIO event <br>
+ * See \ref subsection_gpio_snippet_4.
  *
  * @param[in] pin           The GPIO object
  * @param[in] event         The GPIO event
- * @param[in] intrPriority  The priority for NVIC interrupt events
+ * @param[in] intr_priority The priority for NVIC interrupt events
  * @param[in] enable        True to turn on interrupts, False to turn off
  */
-void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intrPriority, bool enable);
+void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intr_priority, bool enable);
 
 /*******************************************************************************
-* Backward compatibility macro. The following code is DEPRECATED and must 
+* Backward compatibility macro. The following code is DEPRECATED and must
 * not be used in new projects
 *******************************************************************************/
 /** \cond INTERNAL */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio_impl.h

@@ -7,7 +7,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_resources.h

@@ -6,7 +6,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -23,7 +23,7 @@
 *******************************************************************************/
 
 /**
-* \addtogroup group_hal_psoc6_hw_types 
+* \addtogroup group_hal_psoc6_hw_types
 * \ingroup group_hal_psoc6
 * \{
 */
@@ -46,6 +46,7 @@ typedef enum
     CYHAL_RSC_CRYPTO,    /*!< Crypto hardware accelerator */
     CYHAL_RSC_DAC,       /*!< Digital to analog converter */
     CYHAL_RSC_DMA,       /*!< DMA controller */
+    CYHAL_RSC_DW,        /*!< Datawire DMA controller */
     CYHAL_RSC_GPIO,      /*!< General purpose I/O pin */
     CYHAL_RSC_I2S,       /*!< I2S communications block */
     CYHAL_RSC_LCD,       /*!< Segment LCD controller */
@@ -63,8 +64,8 @@ typedef enum
     CYHAL_RSC_INVALID,   /*!< Placeholder for invalid type */
 } cyhal_resource_t;
 
-/** 
+/**
-  * @brief Represents a particular instance of a resource on the chip 
+  * @brief Represents a particular instance of a resource on the chip
   */
 typedef struct
 {
@@ -74,7 +75,7 @@ typedef struct
       * The channel number, if the resource type defines multiple channels
       * per block instance. Otherwise, 0 */
     uint8_t          channel_num;
-} cyhal_resource_inst_t; 
+} cyhal_resource_inst_t;
 
 #if defined(__cplusplus)
 }

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h

@@ -6,7 +6,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -23,10 +23,18 @@
 *******************************************************************************/
 
 /**
-* \addtogroup group_hal_psoc6_hw_types Implementation-defined types
+* \addtogroup group_hal_psoc6 PSoC 6 Implementation Specific
-* \ingroup group_hal_psoc6
 * \{
-* Aliases for types which are part of the public HAL interface but whose  representations are 
+* This section provides details about the PSoC 6 implementation of the Cypress HAL.
+* All information within this section is platform specific and is provided for reference.
+* Portable application code should depend only on the APIs and types which are documented
+* in the @ref group_hal section.
+*/
+
+/**
+* \addtogroup group_hal_psoc6_hw_types PSoC6 Specific Hardware Types
+* \{
+* Aliases for types which are part of the public HAL interface but whose representations
 * need to vary per HAL implementation
 */
 
@@ -35,6 +43,7 @@
 #include "cy_pdl.h"
 #include "cyhal_hw_resources.h"
 #include "cyhal_pin_package.h"
+#include "cyhal_triggers.h"
 #include <stdbool.h>
 
 #if defined(CYHAL_UDB_SDIO)
@@ -47,7 +56,9 @@ extern "C" {
 
 
 #ifndef CYHAL_ISR_PRIORITY_DEFAULT
-/** Default priority for interrupts */
+/** Priority that is applied by default to all drivers when initalized. Priorities can be
+ * overridden on each driver as part of enabling events.
+ */
 #define CYHAL_ISR_PRIORITY_DEFAULT  (7)
 #endif
 
@@ -56,6 +67,7 @@ extern "C" {
 */
 
 #define CYHAL_CRC_IMPL_HEADER       "cyhal_crc_impl.h"      //!< Implementation specific header for CRC
+#define CYHAL_DMA_IMPL_HEADER       "cyhal_dma_impl.h"      //!< Implementation specific header for DMA
 #define CYHAL_GPIO_IMPL_HEADER      "cyhal_gpio_impl.h"     //!< Implementation specific header for GPIO
 #define CYHAL_PWM_IMPL_HEADER       "cyhal_pwm_impl.h"      //!< Implementation specific header for PWM
 #define CYHAL_SYSTEM_IMPL_HEADER    "cyhal_system_impl.h"   //!< Implementation specific header for System
@@ -67,7 +79,6 @@ extern "C" {
 /**
 */
 typedef uint32_t cyhal_source_t; //!< Routable signal source
-typedef uint32_t cyhal_dest_t; //!< Routable signal destination
 
 /** Callbacks for Sleep and Deepsleep APIs */
 #define cyhal_system_callback_t cy_stc_syspm_callback_t
@@ -98,13 +109,6 @@ typedef struct {
     void*         callback_arg;
 } cyhal_event_callback_data_t;
 
-/**
-* \addtogroup group_hal_psoc6_hw_types_handle Instance Handles
-* \{
-* Structs which retain data which needs to persist across HAL API calls. From the perspective of the 
-* generic HAL interface, these are opaque; the contents are specific to this implementation.
-*/
-
 /** @brief ADC object */
 typedef struct {
 #ifdef CY_IP_MXS40PASS_SAR
@@ -131,16 +135,6 @@ typedef struct {
 #endif
 } cyhal_adc_channel_t;
 
-/** @brief Comparator object */
-typedef struct {
-#if defined(CY_IP_MXLPCOMP_INSTANCES) || defined(PASS_NR_CTBS)
-    /* TODO: define */
-    void * TODO_define;
-#else
-    void *empty;
-#endif
-} cyhal_comp_t;
-
 /** @brief CRC object */
 typedef struct {
 #if defined(CY_IP_MXCRYPTO_INSTANCES) || defined(CPUSS_CRYPTO_PRESENT)
@@ -163,8 +157,37 @@ typedef struct {
 
 /** @brief DMA object */
 typedef struct {
-#if defined(CY_IP_M4CPUSS_DMAC_INSTANCES) || defined(CY_IP_M4CPUSS_DMA_INSTANCES)
+#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA)
-    cyhal_resource_inst_t     resource;
+    cyhal_resource_inst_t          resource;
+    union
+    {
+#ifdef CY_IP_M4CPUSS_DMA
+        cy_stc_dma_channel_config_t    dw;
+#endif
+#ifdef CY_IP_M4CPUSS_DMAC
+        cy_stc_dmac_channel_config_t   dmac;
+#endif
+    } channel_config;
+    union
+    {
+#ifdef CY_IP_M4CPUSS_DMA
+        cy_stc_dma_descriptor_config_t dw;
+#endif
+#ifdef CY_IP_M4CPUSS_DMAC
+        cy_stc_dmac_descriptor_config_t dmac;
+#endif
+    } descriptor_config;
+    union
+    {
+#ifdef CY_IP_M4CPUSS_DMA
+        cy_stc_dma_descriptor_t        dw;
+#endif
+#ifdef CY_IP_M4CPUSS_DMAC
+        cy_stc_dmac_descriptor_t        dmac;
+#endif
+    } descriptor;
+    uint32_t                       irq_cause;
+    cyhal_event_callback_data_t    callback_data;
 #else
     void *empty;
 #endif
@@ -199,53 +222,41 @@ typedef struct {
 #endif
 } cyhal_i2c_t;
 
-/** @brief I2S object */
+/** @brief EZI2C object */
 typedef struct {
-#ifdef CY_IP_MXAUDIOSS_INSTANCES
+#ifdef CY_IP_MXSCB
-    /* TODO: define */
+    CySCB_Type*                         base;
-    void * TODO_define;
+    cyhal_resource_inst_t               resource;
+    cyhal_gpio_t                        pin_sda;
+    cyhal_gpio_t                        pin_scl;
+    cyhal_clock_divider_t               clock;
+    bool                                is_shared_clock;
+    cy_stc_scb_ezi2c_context_t          context;
+    uint32_t                            irq_cause;
+    cyhal_event_callback_data_t         callback_data;
 #else
     void *empty;
 #endif
-} cyhal_i2s_t;
+} cyhal_ezi2c_t;
 
 /** @brief LPTIMER object */
 typedef struct {
 #ifdef CY_IP_MXS40SRSS_MCWDT_INSTANCES
-    MCWDT_STRUCT_Type           *base;
+    MCWDT_STRUCT_Type                *base;
-    cyhal_resource_inst_t       resource;
+    cyhal_resource_inst_t            resource;
-    cyhal_event_callback_data_t callback_data;
+    cyhal_event_callback_data_t      callback_data;
 #else
     void *empty;
 #endif
 } cyhal_lptimer_t;
 
-/** @brief OpAmp object */
-typedef struct {
-#ifdef PASS_NR_CTBS
-    /* TODO: define */
-    void * TODO_define;
-#else
-    void *empty;
-#endif
-} cyhal_opamp_t;
-
-/** @brief PDM-PCM object */
-typedef struct {
-#ifdef CY_IP_MXAUDIOSS_INSTANCES
-    /* TODO: define */
-    void * TODO_define;
-#else
-    void *empty;
-#endif
-} cyhal_pdm_pcm_t;
-
 /** @brief PWM object */
 typedef struct {
 #ifdef CY_IP_MXTCPWM
     TCPWM_Type*                     base;
     cyhal_resource_inst_t           resource;
     cyhal_gpio_t                    pin;
+    cyhal_gpio_t                    pin_compl;
     cyhal_clock_divider_t           clock;
     uint32_t                        clock_hz;
     bool                            dedicated_clock;
@@ -280,12 +291,18 @@ typedef struct {
 #if defined(CY_IP_MXCRYPTO_INSTANCES) || defined(CPUSS_CRYPTO_PRESENT)
     CRYPTO_Type*                base;
     cyhal_resource_inst_t       resource;
+#else
+    void *empty;
 #endif
 } cyhal_trng_t;
 
 /** @brief RTC object */
 typedef struct {
-    uint8_t placeholder;
+#ifdef CY_IP_MXS40SRSS_RTC
+    cy_stc_rtc_dst_t dst;
+#else
+    void *empty;
+#endif
 } cyhal_rtc_t;
 
 /** @brief SDHC object */
@@ -457,10 +474,9 @@ typedef struct {
     uint8_t placeholder;
 } cyhal_wdt_t;
 
-/** \} group_hal_psoc6_hw_types_handles */
-
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
 /** \} group_hal_psoc6_hw_types */
+/** \} group_hal_psoc6 */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr.h

@@ -8,7 +8,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -28,7 +28,14 @@
 * \addtogroup group_hal_hwmgr HWMGR (Hardware Manager)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress Hardware Manager.
+* High level interface for interacting with the Hardware Manager.
+*
+* This provides two related functions:
+* * Allows HAL drivers (or application firmware) to mark specific hardware blocks
+*   as consumed, so that other firmware will not accidentally try to use the block
+*   for a conflicting purpose.
+* * For resources which are interchangeable, such as clock dividers, provides allocation
+*   and reservation of an available instance (if one exists).
 */
 
 #pragma once
@@ -80,13 +87,6 @@ void cyhal_hwmgr_free(const cyhal_resource_inst_t* obj);
  */
 cy_rslt_t cyhal_hwmgr_allocate(cyhal_resource_t type, cyhal_resource_inst_t* obj);
 
-/** Allocate (pick and reserve) an DMA resource and provide a reference to it.
- *
- * @param[out] obj The resource object that was allocated
- * @return The status of the reserve request
- */
-cy_rslt_t cyhal_hwmgr_allocate_dma(cyhal_resource_inst_t* obj);
-
 /** Allocate (pick and reserve) an Clock Divider resource and provide a reference to it.
  *
  * @param[out] obj           The resource object that was allocated

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2c.h

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -29,10 +29,63 @@
 * \addtogroup group_hal_i2c I2C (Inter-Integrated Circuit)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress I2C.
+* High level interface for interacting with the I2C resource.
-* 
+*
-* \defgroup group_hal_i2c_master Master
+* The I2C protocol is a synchronous serial interface protocol. This driver supports
-* \defgroup group_hal_i2c_slave Slave
+* both master and slave mode of operation. The communication frequency and address (for slave operation) can be
+* configured.
+*
+* \section section_i2c_features Features
+*
+* * Master or slave functionality
+* * Configurable slave address
+* * Configurable data rates
+* * Configurable interrupt and callback assignment from I2C events - \ref cyhal_i2c_event_t
+*
+* \section section_i2c_quickstart Quick Start
+* Initialize an I2C instance using the \ref cyhal_i2c_init and provide <b>sda</b> (I2C data) and <b>scl</b> (I2C clock) pins.<br>
+* By default, this initializes the resource as an I2C master.<br>
+* Configure the behavior (master/slave) and the interface (bus frequency, slave address) using the  \ref cyhal_i2c_configure function. <br>
+* See \ref subsection_i2c_snippet_1 for example initialization as master or slave.
+* \note The clock parameter (const cyhal_clock_divider_t *clk) is optional and can be set
+* to NULL to generate and use an available clock resource with a default frequency (CYHAL_I2C_MASTER_DEFAULT_FREQ).
+*
+* \section section_i2c_snippets Code Snippets
+*
+* \subsection subsection_i2c_snippet_1 Snippet 1: I2C Initialization and Configuration
+* This snippet initializes an I2C resource as master or slave and assigns
+* the <b>sda</b> and <b>scl</b> pins.
+*
+* Initializing as I2C master
+* \snippet i2c.c snippet_cyhal_i2c_master_init
+*
+* Initializing as I2C slave
+* \snippet i2c.c snippet_cyhal_i2c_slave_init
+*
+* \subsection subsection_i2c_snippet_2 Snippet 2: Handling events
+* This snippet shows how to enable and handle I2C events using \ref cyhal_i2c_enable_event and \ref cyhal_i2c_register_callback.<br>
+* The <b>callback</b> parameter of \ref cyhal_i2c_register_callback is used to pass the callback handler that will be invoked when an event occurs.<br>
+* The <b>event</b> parameter of \ref cyhal_i2c_enable_event is used to pass the bitmasks of events ( \ref cyhal_i2c_event_t) to be enabled.
+*
+* \snippet i2c.c snippet_cyhal_handle_i2c_events
+*
+* \subsection subsection_i2c_snippet_3 Snippet 3: I2C Master Asynchronous Transfer
+* This snippet shows how to implement asynchronous transfers using \ref cyhal_i2c_master_transfer_async.<br>
+* \ref cyhal_i2c_abort_async is used to stop the transfer, in this case when an error occurs.
+*
+* \snippet i2c.c snippet_cyhal_async_transfer
+*
+* \section subsection_i2c_moreinformation More Information
+*
+* <b>Peripheral Driver Library (PDL)</b>
+* * <a href="https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__scb.html"><b>
+PSoC 6 PDL: SCB (Serial Communication Block)</b></a>
+*
+* <b>Code examples (Github)</b>
+* * <a href="https://github.com/cypresssemiconductorco/mtb-example-psoc6-i2c-master" ><b>
+PSoC 6 MCU: I2C Master</b></a>
+* * <a href="https://github.com/cypresssemiconductorco/mtb-example-psoc6-i2c-slave-callback" ><b>
+PSoC 6 MCU: I2C Slave Using Callbacks</b></a>
 */
 
 #pragma once
@@ -47,6 +100,7 @@
 extern "C" {
 #endif
 
+
 /** The requested resource type is invalid */
 #define CYHAL_I2C_RSLT_ERR_INVALID_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_I2C, 0))
 /** Can not reach desired data rate */
@@ -57,42 +111,48 @@ extern "C" {
 /** Enum to enable/disable/report interrupt cause flags. */
 typedef enum
 {
-    CYHAL_I2C_EVENT_NONE               = 0,       /* No event */
+    CYHAL_I2C_EVENT_NONE               = 0,       /**< No event */
-    CYHAL_I2C_SLAVE_READ_EVENT         = 1 << 1,  /* Indicates that the slave was addressed and the master wants to read data. */
+    CYHAL_I2C_SLAVE_READ_EVENT         = 1 << 1,  /**< Indicates that the slave was addressed and the master wants to read data. */
-    CYHAL_I2C_SLAVE_WRITE_EVENT        = 1 << 2,  /* Indicates that the slave was addressed and the master wants to write data. */
+    CYHAL_I2C_SLAVE_WRITE_EVENT        = 1 << 2,  /**< Indicates that the slave was addressed and the master wants to write data. */
-    CYHAL_I2C_SLAVE_RD_IN_FIFO_EVENT   = 1 << 3,  /* All slave data from the configured Read buffer has been loaded into the TX FIFO. */
+    CYHAL_I2C_SLAVE_RD_IN_FIFO_EVENT   = 1 << 3,  /**< All slave data from the configured Read buffer has been loaded into the TX FIFO. */
-    CYHAL_I2C_SLAVE_RD_BUF_EMPTY_EVENT = 1 << 4,  /* The master has read all data out of the configured Read buffer. */
+    CYHAL_I2C_SLAVE_RD_BUF_EMPTY_EVENT = 1 << 4,  /**< The master has read all data out of the configured Read buffer. */
-    CYHAL_I2C_SLAVE_RD_CMPLT_EVENT     = 1 << 5,  /* Indicates the master completed reading from the slave (set by the master NAK or Stop) */
+    CYHAL_I2C_SLAVE_RD_CMPLT_EVENT     = 1 << 5,  /**< Indicates the master completed reading from the slave (set by the master NAK or Stop) */
-    CYHAL_I2C_SLAVE_WR_CMPLT_EVENT     = 1 << 6,  /* Indicates the master completed writing to the slave (set by the master Stop or Restart)*/
+    CYHAL_I2C_SLAVE_WR_CMPLT_EVENT     = 1 << 6,  /**< Indicates the master completed writing to the slave (set by the master Stop or Restart)*/
-    CYHAL_I2C_SLAVE_ERR_EVENT          = 1 << 7,  /* Indicates the I2C hardware detected an error. */
+    CYHAL_I2C_SLAVE_ERR_EVENT          = 1 << 7,  /**< Indicates the I2C hardware detected an error. */
-    CYHAL_I2C_MASTER_WR_IN_FIFO_EVENT  = 1 << 17, /* All data specified by Cy_SCB_I2C_MasterWrite has been loaded into the TX FIFO. */
+    CYHAL_I2C_MASTER_WR_IN_FIFO_EVENT  = 1 << 17, /**< All data specified by cyhal_i2c_master_transfer_async has been loaded into the TX FIFO. */
-    CYHAL_I2C_MASTER_WR_CMPLT_EVENT    = 1 << 18, /* The master write started by Cy_SCB_I2C_MasterWrite is complete.*/
+    CYHAL_I2C_MASTER_WR_CMPLT_EVENT    = 1 << 18, /**< The master write started by cyhal_i2c_master_transfer_async is complete.*/
-    CYHAL_I2C_MASTER_RD_CMPLT_EVENT    = 1 << 19, /* The master read started by Cy_SCB_I2C_MasterRead is complete.*/
+    CYHAL_I2C_MASTER_RD_CMPLT_EVENT    = 1 << 19, /**< The master read started by cyhal_i2c_master_transfer_async is complete.*/
-    CYHAL_I2C_MASTER_ERR_EVENT         = 1 << 20, /* Indicates the I2C hardware has detected an error. */
+    CYHAL_I2C_MASTER_ERR_EVENT         = 1 << 20, /**< Indicates the I2C hardware has detected an error. */
 } cyhal_i2c_event_t;
 
+
 /** Handler for I2C events */
 typedef void (*cyhal_i2c_event_callback_t)(void *callback_arg, cyhal_i2c_event_t event);
 
+
 /** @brief Initial I2C configuration */
 typedef struct
 {
-    bool is_slave;            /* I2C mode, is the device a master or slave */
+    bool is_slave;            /**<  Operates as a slave when set to (<b>true</b>), else as a master (<b>false</b>) */
-    uint16_t address;         /* Address of this slave device (7-bit), should be set to 0 for master */
+    uint16_t address;         /**<  Address of this slave resource (7-bit), should be set to 0 for master */
-    uint32_t frequencyhal_hz; /* Frequency that the I2C bus runs at */
+    uint32_t frequencyhal_hz; /**<  Frequency that the I2C bus runs at (I2C data rate in bits per second) <br>
+                                    Refer to the device datasheet for the supported I2C data rates */
 } cyhal_i2c_cfg_t;
 
-/** Initialize the I2C peripheral, and configures its specifieds pins. By default
+
- * it is setup as a Master running at 400kHz. This can be changed by calling
+/** Initialize the I2C peripheral, and configures its specified pins. By default
- * cyhal_i2c_configure().
+ * it is configured as a Master with a bus frequency = CYHAL_I2C_MASTER_DEFAULT_FREQ.
+ * Use \ref cyhal_i2c_configure() to change the default behavior.<br>
  * NOTE: Master/Slave specific functions only work when the block is configured
- * to be in that mode.
+ * to be in that mode.<br>
+ * See \ref subsection_i2c_snippet_1
  *
  * @param[out] obj The I2C object
  * @param[in]  sda The sda pin
  * @param[in]  scl The scl pin
  * @param[in]  clk The clock to use can be shared, if not provided a new clock will be allocated
  * @return The status of the init request
+ *
  */
 cy_rslt_t cyhal_i2c_init(cyhal_i2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, const cyhal_clock_divider_t *clk);
 
@@ -102,27 +162,27 @@ cy_rslt_t cyhal_i2c_init(cyhal_i2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, c
  */
 void cyhal_i2c_free(cyhal_i2c_t *obj);
 
-/** Configure the I2C block
+/** Configure the I2C block.
+ * NOTE: Master/Slave specific functions only work when the block is configured
+ * to be in that mode.<br>
+ * See \ref subsection_i2c_snippet_1
  *
  * @param[in] obj     The I2C object
  * @param[in] cfg     Configuration settings to apply
  * @return The status of the configure request
+ *
  */
 cy_rslt_t cyhal_i2c_configure(cyhal_i2c_t *obj, const cyhal_i2c_cfg_t *cfg);
 
-/**
-* \addtogroup group_hal_i2c_master
-* \{
-*/
 
 /**
  * I2C master write
  *
  * @param[in]  obj        The I2C object
  * @param[in]  dev_addr   device address (7-bit)
- * @param[in]  data       i2c send data
+ * @param[in]  data       I2C send data
- * @param[in]  size       i2c send data size
+ * @param[in]  size       I2C send data size
- * @param[in]  timeout    timeout in milisecond, set this value to 0 if you want to wait forever
+ * @param[in]  timeout    timeout in millisecond, set this value to 0 if you want to wait forever
  * @param[in]  send_stop  whether the stop should be send, used to support repeat start conditions
  *
  * @return The status of the master_write request
@@ -134,110 +194,108 @@ cy_rslt_t cyhal_i2c_master_write(cyhal_i2c_t *obj, uint16_t dev_addr, const uint
  *
  * @param[in]   obj        The I2C object
  * @param[in]   dev_addr   device address (7-bit)
- * @param[out]  data       i2c receive data
+ * @param[out]  data       I2C receive data
- * @param[in]   size       i2c receive data size
+ * @param[in]   size       I2C receive data size
- * @param[in]   timeout    timeout in milisecond, set this value to 0 if you want to wait forever
+ * @param[in]   timeout    timeout in millisecond, set this value to 0 if you want to wait forever
  * @param[in]   send_stop  whether the stop should be send, used to support repeat start conditions
  *
  * @return The status of the master_read request
  */
 cy_rslt_t cyhal_i2c_master_read(cyhal_i2c_t *obj, uint16_t dev_addr, uint8_t *data, uint16_t size, uint32_t timeout, bool send_stop);
 
-/** \} group_hal_i2c_master */
-
 /**
-* \addtogroup group_hal_i2c_slave
+ * The function configures the read buffer on an I2C Slave. This is the buffer from which the master reads data from.
-* \{
+ * The user needs to setup a new buffer every time (i.e. call slave_send and slave_recv every time the buffer has been used up)<br>
-*/
+ * See related code example: <a href="https://github.com/cypresssemiconductorco/mtb-example-psoc6-i2c-master" ><b>PSoC 6 MCU: I2C Master</b></a>
-
-/**
- * I2C slave config write buffer
- * The user needs to setup a new buffer every time (i.e. call slave_send and slave_recv every time the buffer has been used up)
  *
  * @param[in]  obj      The I2C object
- * @param[in]  data     i2c slave send data
+ * @param[in]  data     I2C slave send data
- * @param[in]  size     i2c slave send data size
+ * @param[in]  size     I2C slave send data size
  *
  * @return The status of the slave_config_write_buff request
  */
 cy_rslt_t cyhal_i2c_slave_config_write_buff(cyhal_i2c_t *obj, const uint8_t *data, uint16_t size);
 
 /**
- * I2C slave config read buffer
+ * The function configures the write buffer on an I2C Slave. This is the buffer to which the master writes data to.
- * The user needs to setup a new buffer every time (i.e. call slave_send and slave_recv every time the buffer has been used up)
+ * The user needs to setup a new buffer every time (i.e. call slave_send and slave_recv every time the buffer has been used up)<br>
+ * See related code example: <a href="https://github.com/cypresssemiconductorco/mtb-example-psoc6-i2c-master" ><b>PSoC 6 MCU: I2C Master</b></a>
  *
  * @param[in]   obj      The I2C object
- * @param[out]  data     i2c slave receive data
+ * @param[out]  data     I2C slave receive data
- * @param[in]   size     i2c slave receive data size
+ * @param[in]   size     I2C slave receive data size
  *
  * @return The status of the slave_config_read_buff request
  */
 cy_rslt_t cyhal_i2c_slave_config_read_buff(cyhal_i2c_t *obj, uint8_t *data, uint16_t size);
 
-/** \} group_hal_i2c_slave */
 
-/**
+/** Perform an I2C write using a block of data stored at the specified memory location
-* \addtogroup group_hal_i2c_master
-* \{
-*/
-
-/** Perform an i2c write using a block of data stored at the specified memory location
  *
  * @param[in]  obj            The I2C object
  * @param[in]  address        device address (7-bit)
  * @param[in]  mem_addr       mem address to store the written data
  * @param[in]  mem_addr_size  number of bytes in the mem address
- * @param[in]  data           i2c master send data
+ * @param[in]  data           I2C master send data
- * @param[in]  size           i2c master send data size
+ * @param[in]  size           I2C master send data size
- * @param[in]  timeout        timeout in milisecond, set this value to 0 if you want to wait forever
+ * @param[in]  timeout        timeout in millisecond, set this value to 0 if you want to wait forever
  * @return The status of the write request
  */
+
 cy_rslt_t cyhal_i2c_master_mem_write(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, const uint8_t *data, uint16_t size, uint32_t timeout);
 
-/** Perform an i2c read using a block of data stored at the specified memory location
+/** Perform an I2C read using a block of data stored at the specified memory location
  *
  * @param[in]  obj            The I2C object
  * @param[in]  address        device address (7-bit)
  * @param[in]  mem_addr       mem address to store the written data
  * @param[in]  mem_addr_size  number of bytes in the mem address
- * @param[out] data           i2c master send data
+ * @param[out] data           I2C master send data
- * @param[in]  size           i2c master send data size
+ * @param[in]  size           I2C master send data size
- * @param[in]  timeout        timeout in milisecond, set this value to 0 if you want to wait forever
+ * @param[in]  timeout        timeout in millisecond, set this value to 0 if you want to wait forever
  * @return The status of the read request
  */
 cy_rslt_t cyhal_i2c_master_mem_read(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, uint8_t *data, uint16_t size, uint32_t timeout);
 
-/** Start I2C master asynchronous transfer
+/** Initiate a non-blocking I2C master asynchronous transfer. Supports simultaneous write and read operation.<br>
+ * Use callback handler to handle the events until data transfer is complete.<br>
+ * If either of <b>tx_size</b> or <b>rx_size</b> is '0', the respective write or read operation is not performed.
+ * See \ref subsection_i2c_snippet_3
  *
  * @param[in]  obj      The I2C object
  * @param[in]  address  device address (7-bit)
  * @param[in]  tx       The transmit buffer
- * @param[in]  tx_size  The number of bytes to transmit
+ * @param[in]  tx_size  The number of bytes to transmit. Use '0' if write operation is not required.
  * @param[out] rx       The receive buffer
- * @param[in]  rx_size  The number of bytes to receive
+ * @param[in]  rx_size  The number of bytes to receive. Use '0' if read operation is not required.
  * @return The status of the master_transfer_async request
+ *
  */
 cy_rslt_t cyhal_i2c_master_transfer_async(cyhal_i2c_t *obj, uint16_t address, const void *tx, size_t tx_size, void *rx, size_t rx_size);
 
-/** \} group_hal_i2c_master */
 
-/** Abort asynchronous transfer
+/** Abort asynchronous transfer.<br>
+ *This function aborts the ongoing transfer by generating a stop condition.<br>
+ * See \ref subsection_i2c_snippet_3
  *
- * This function does not perform any check - that should happen in upper layers.
  * @param[in] obj The I2C object
  * @return The status of the abort_async request
+ *
  */
 cy_rslt_t cyhal_i2c_abort_async(cyhal_i2c_t *obj);
 
-/** The I2C event callback handler registration
+/** The I2C event callback handler registration<br>
+ * See \ref subsection_i2c_snippet_2
  *
  * @param[in] obj          The I2C object
  * @param[in] callback     The callback handler which will be invoked when an event triggers
  * @param[in] callback_arg Generic argument that will be provided to the callback when called
+ *
  */
 void cyhal_i2c_register_callback(cyhal_i2c_t *obj, cyhal_i2c_event_callback_t callback, void *callback_arg);
 
 /** Configure and Enable or Disable I2C Interrupt.
+ * See \ref subsection_i2c_snippet_2
  *
  * @param[in] obj           The I2C object
  * @param[in] event         The I2C event type
@@ -246,8 +304,9 @@ void cyhal_i2c_register_callback(cyhal_i2c_t *obj, cyhal_i2c_event_callback_t ca
  */
 void cyhal_i2c_enable_event(cyhal_i2c_t *obj, cyhal_i2c_event_t event, uint8_t intrPriority, bool enable);
 
+
 /*******************************************************************************
-* Backward compatibility macro. The following code is DEPRECATED and must 
+* Backward compatibility macro. The following code is DEPRECATED and must
 * not be used in new projects
 *******************************************************************************/
 /** \cond INTERNAL */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_interconnect.h

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -29,7 +29,13 @@
 * \addtogroup group_hal_interconnect INTERCONNECT (Internal digital routing)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress digital routing.
+* High level interface for interacting with the digital routing.
+*
+* This provides limited facilities for runtime manipulation of the on chip routing.
+* The following types of connections are supported:
+* * Connection from a peripheral to a pin. (A dedicated connection must exist
+    between the pin and the peripheral; see the device datasheet for more details)
+* * Experimental support for connecting between two on-chip "trigger" terminals.
 */
 
 #pragma once

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -29,9 +29,9 @@
 * \addtogroup group_hal_lptimer LPTIMER (Low-Power Timer)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress LPTIMER.
+* High level interface for interacting with the low-power timer (LPTIMER).
-* 
+*
-* This can be used to measure timing between events, or to perform 
+* This can be used to measure timing between events, or to perform
 * some action the ability after a set interval. It continues to operate
 * in some low power modes; see the device datasheet for details.
 */
@@ -93,12 +93,12 @@ cy_rslt_t cyhal_lptimer_reload(cyhal_lptimer_t *obj);
 #define cyhal_lptimer_set_time cyhal_lptimer_set_match
 
 /** Update the match/compare value
- * 
+ *
  * Update the match value of an already configured LPTIMER set up
  * to generate an interrupt on match. Note that this function does not
  * reinitialize the counter or the associated peripheral initialization
  * sequence.
- * 
+ *
  * @param[in] obj   The LPTIMER object
  * @param[in] value The tick value to match
  *
@@ -107,13 +107,13 @@ cy_rslt_t cyhal_lptimer_reload(cyhal_lptimer_t *obj);
 cy_rslt_t cyhal_lptimer_set_match(cyhal_lptimer_t *obj, uint32_t value);
 
 /** Update the match/compare value
- * 
+ *
  * Update the match value of an already configured LPTIMER set up
  * to generate an interrupt on match delay from the current counter value.
- * Note that this function does not reinitialize the counter or the 
+ * Note that this function does not reinitialize the counter or the
  * associated peripheral initialization
  * sequence.
- * 
+ *
  * @param[in] obj   The LPTIMER object
  * @param[in] delay The ticks to wait
  *

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_modules.h

@@ -7,7 +7,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -24,8 +24,9 @@
 *******************************************************************************/
 
 /**
-* \ingroup group_hal
+* \ingroup group_result
 * \{
+* Enum definition for all HAL resource modules.
 */
 
 #pragma once
@@ -37,6 +38,11 @@ extern "C" {
 #endif
 
 /** Enum to in indicate which module an errors occurred in. */
+/**
+ * @brief Enum to specify module IDs for @ref cy_rslt_t values returned from the HAL.
+ *
+ */
+
 enum cyhal_rslt_module_chip
 {
     CYHAL_RSLT_MODULE_CHIP_HWMGR = CY_RSLT_MODULE_ABSTRACTION_HAL_BASE, //!< An error occurred in hardware management module
@@ -64,10 +70,11 @@ enum cyhal_rslt_module_chip
     CYHAL_RSLT_MODULE_UART,                                             //!< An error occurred in UART module
     CYHAL_RSLT_MODULE_USB,                                              //!< An error occurred in USB module
     CYHAL_RSLT_MODULE_WDT,                                              //!< An error occurred in WDT module
+    CYHAL_RSLT_MODULE_EZI2C,                                            //!< An error occurred in EZI2C module
 };
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
-/** \} group_hal */
+/** \} group_hal_modules */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pin_package.h

@@ -3,10 +3,10 @@
 *
 * Description:
 * Provides definitions for the pinout for each supported device.
-* 
+*
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -37,24 +37,29 @@
 extern "C" {
 #endif /* __cplusplus */
 
-/** Port names */
+/** Port definitions that individual pins can belong to. */
 typedef enum {
-    CYHAL_PORT_0  = 0x0,
+    CYHAL_PORT_0  = 0x00,
-    CYHAL_PORT_1  = 0x1,
+    CYHAL_PORT_1  = 0x01,
-    CYHAL_PORT_2  = 0x2,
+    CYHAL_PORT_2  = 0x02,
-    CYHAL_PORT_3  = 0x3,
+    CYHAL_PORT_3  = 0x03,
-    CYHAL_PORT_4  = 0x4,
+    CYHAL_PORT_4  = 0x04,
-    CYHAL_PORT_5  = 0x5,
+    CYHAL_PORT_5  = 0x05,
-    CYHAL_PORT_6  = 0x6,
+    CYHAL_PORT_6  = 0x06,
-    CYHAL_PORT_7  = 0x7,
+    CYHAL_PORT_7  = 0x07,
-    CYHAL_PORT_8  = 0x8,
+    CYHAL_PORT_8  = 0x08,
-    CYHAL_PORT_9  = 0x9,
+    CYHAL_PORT_9  = 0x09,
-    CYHAL_PORT_10 = 0xA,
+    CYHAL_PORT_10 = 0x0A,
-    CYHAL_PORT_11 = 0xB,
+    CYHAL_PORT_11 = 0x0B,
-    CYHAL_PORT_12 = 0xC,
+    CYHAL_PORT_12 = 0x0C,
-    CYHAL_PORT_13 = 0xD,
+    CYHAL_PORT_13 = 0x0D,
-    CYHAL_PORT_14 = 0xE,
+    CYHAL_PORT_14 = 0x0E,
-    CYHAL_PORT_15 = 0xF,
+    CYHAL_PORT_15 = 0x0F,
+    CYHAL_PORT_16 = 0x10,
+    CYHAL_PORT_17 = 0x11,
+    CYHAL_PORT_18 = 0x12,
+    CYHAL_PORT_19 = 0x13,
+    CYHAL_PORT_20 = 0x14,
 } cyhal_port_t;
 
 /** Bitfield representing the configuration of a GPIO (hsiom selection and mode).
@@ -115,6 +120,8 @@ typedef uint16_t cyhal_gpio_mapping_cfg_t; // 8bit hsiom, 8bit mode
 #include "pin_packages/cyhal_psoc6_03_49_wlcsp.h"
 #elif defined(_GPIO_PSOC6_03_68_QFN_H_)
 #include "pin_packages/cyhal_psoc6_03_68_qfn.h"
+#elif defined(_GPIO_PLAYER_128_TQFP_H_)
+#include "pin_packages/cyhal_mxs28playermcuss_128_tqfp.h"
 #else
 #error "Unhandled Device/PinPackage combination"
 #endif
@@ -123,4 +130,4 @@ typedef uint16_t cyhal_gpio_mapping_cfg_t; // 8bit hsiom, 8bit mode
 }
 #endif /* __cplusplus */
 
-/** \} group_hal_adc */
+/** \} group_hal_psoc6 */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm.h

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -29,12 +29,61 @@
 * \addtogroup group_hal_pwm PWM (Pulse Width Modulator)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress PWM.
+ * High level interface for interacting with the pulse width modulator (PWM) hardware resource
+ *
+ * The PWM driver can be used to generate periodic digital waveforms with configurable frequency and duty cycle.
+ * The driver allows assigning the PWM output and an optional inverted output to supplied pins.
+ * The driver supports interrupt generation on PWM terminal count and capture/compare events.
+ *
+ * \section section_pwm_features Features
+ * * Configurable pin assignment for the PWM output
+ * * Optional complementary (inverted) PWM output to a second pin
+ * * Configurable dead time between normal and inverted PWM outputs
+ * * Configurable alignment: left, right or center
+ * * Continuous or One-shot operation
+ * * Option to instantiate and use a new clock or use pre-allocated clock for clock input
+ * * Configurable interrupt and callback assignment on PWM events: terminal count, capture/compare match or combination of both
+ *
+ * \section section_pwm_quickstart Quick Start
+ *
+ * See \ref subsection_pwm_snippet_1 for a code snippet that generates a signal with the specified frequency and duty cycle on the specified pin.
+ *
+ * \section section_pwm_snippets Code snippets
+ *
+ * \subsection subsection_pwm_snippet_1 Snippet 1: Simple PWM initialization and output to pin
+ * The following snippet initializes a PWM resource and assigns the output to the supplied <b>pin</b> using \ref cyhal_pwm_init. <br>
+ * The clock parameter <b>clk</b> is optional and need not be provided (NULL), to generate and use an available clock resource with a default frequency. <br>
+ * The clock frequency and the duty cycle is set using \ref cyhal_pwm_set_duty_cycle. <br>
+ * \ref cyhal_pwm_start starts the PWM output on the pin.
+ *
+ * \snippet pwm.c snippet_cyhal_pwm_simple_init
+ *
+ *
+ * \subsection subsection_pwm_snippet_2 Snippet 2: Starting and stopping the PWM output
+ * \ref cyhal_pwm_start and \ref cyhal_pwm_stop functions can be used after PWM initialization to start and stop the PWM output.
+ *
+ * \snippet pwm.c snippet_cyhal_pwm_start_stop
+ *
+ *
+ * \subsection subsection_pwm_snippet_3 Snippet 3: Advanced PWM output to pin
+ * \ref cyhal_pwm_init_adv can be used to specify advanced PWM options like an additional inverted PWM output, pulse alignment
+ * (left, right, center) and run mode (one-shot or continuous). The following snippet initializes a left-aligned, continuous running PWM
+ * assigned to the supplied pin. The inverted output is assigned to a second pin (<b>compl_pin</b>).
+ *
+ * \snippet pwm.c snippet_cyhal_pwm_adv_init
+ *
+ *
+ * \subsection subsection_pwm_snippet_4 Snippet 4: Interrupts on PWM events
+ * PWM events like hitting the terminal count or a capture/compare event can be used to trigger a callback function. <br>
+ * \ref cyhal_pwm_enable_event() can be used to enable one or more events to trigger the callback function.
+ *
+ * \snippet pwm.c snippet_cyhal_pwm_events
 */
 
 #pragma once
 
 #include <stdint.h>
+#include <stdbool.h>
 #include "cy_result.h"
 #include "cyhal_hw_types.h"
 #include "cyhal_modules.h"
@@ -43,6 +92,17 @@
 extern "C" {
 #endif
 
+/** Initialize the PWM out peripheral and configure the pin
+ * This is similar to the \ref cyhal_pwm_init_adv() but uses defaults for some of the
+ * more advanced setup options. See \ref subsection_pwm_snippet_1.
+ *
+ * @param[out] obj  The PWM object to initialize
+ * @param[in]  pin  The PWM pin to initialize
+ * @param[in]  clk  An optional, pre-allocated clock to use, if NULL a new clock will be allocated
+ * @return The status of the init request.
+ */
+#define cyhal_pwm_init(obj, pin, clk) (cyhal_pwm_init_adv(obj, pin, NC, CYHAL_PWM_LEFT_ALIGN, true, 0u, (bool)(pin & 1), clk))
+
 /** Bad argument */
 #define CYHAL_PWM_RSLT_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_PWM, 0))
 /** Failed to initialize PWM clock */
@@ -52,23 +112,44 @@ extern "C" {
 
 /** PWM interrupt triggers */
 typedef enum {
-    CYHAL_PWM_IRQ_NONE            =  0,
+    CYHAL_PWM_IRQ_NONE            =  0,             /**< No interrupts */
-    CYHAL_PWM_IRQ_TERMINAL_COUNT  =  1 << 0,
+    CYHAL_PWM_IRQ_TERMINAL_COUNT  =  1 << 0,        /**< Interrupt on terminal count match event */
-    CYHAL_PWM_IRQ_CAPTURE_COMPARE =  1 << 1,
+    CYHAL_PWM_IRQ_CAPTURE_COMPARE =  1 << 1,        /**< Interrupt on capture/compare match event */
-    CYHAL_PWM_IRQ_ALL             = (1 << 2) - 1,
+    CYHAL_PWM_IRQ_ALL             = (1 << 2) - 1,   /**< Interrupt on any events */
 } cyhal_pwm_event_t;
 
+/** PWM alignment */
+typedef enum {
+    CYHAL_PWM_LEFT_ALIGN       = 0, /**< PWM is left aligned (signal starts high and goes low after capture/compare match) */
+    CYHAL_PWM_RIGHT_ALIGN      = 1, /**< PWM is right aligned (signal starts low and goes high after capture/compare match) */
+    CYHAL_PWM_CENTER_ALIGN     = 2, /**< PWM is centered aligned (signal starts and ends low with a center aligned pulse) */
+} cyhal_pwm_alignment_t;
+
 /** Handler for PWM interrupts */
 typedef void(*cyhal_pwm_event_callback_t)(void *callback_arg, cyhal_pwm_event_t event);
 
-/** Initialize the PWM out peripheral and configure the pin
+/** Initialize the PWM out peripheral and configure the pin.
+ * This is similar to the \ref cyhal_pwm_init() but provides additional setup options. <br>
+ * See \ref subsection_pwm_snippet_3.
  *
- * @param[out] obj The PWM object to initialize
+ * @param[out] obj              The PWM object to initialize.
- * @param[in]  pin The PWM pin to initialize
+ * @param[in]  pin              The PWM pin to initialize.
- * @param[in]  clk The clock to use can be shared, if not provided a new clock will be allocated
+ * @param[in]  compl_pin        An optional, additional inverted output pin. <br>
+ * If supplied, this must be connected to the same PWM instance as <b>pin</b>, for
+ * PSoC 6 see \ref section_psoc6_pwm_compl_pins.<br>
+ * If this output is not needed, use \ref NC (No Connect).
+ * @param[in]  pwm_alignment    PWM alignment: left, right, or center.
+ * @param[in]  continuous       PWM run type: continuous (true) or one shot (false).
+ * @param[in]  dead_time_us     The number of micro-seconds for dead time. This is
+ * only meaningful if both <b>pin</b> and <b>compl_pin</b> are provided.
+ * @param[in]  invert      An option for the user to invert the PWM output
+ * @param[in]  clk              An optional, pre-allocated clock to use, if NULL a
+ * new clock will be allocated.
  * @return The status of the init request
+ *
+ * @note In some cases, it is possible to use a pin designated for non-inverting output as an inverting output and vice versa. Whether this is possible is dependent on the HAL implementation and operating mode. See the implementation specific documentation for details.
  */
-cy_rslt_t cyhal_pwm_init(cyhal_pwm_t *obj, cyhal_gpio_t pin, const cyhal_clock_divider_t *clk);
+cy_rslt_t cyhal_pwm_init_adv(cyhal_pwm_t *obj, cyhal_gpio_t pin, cyhal_gpio_t compl_pin, cyhal_pwm_alignment_t pwm_alignment, bool continuous, uint32_t dead_time_us, bool invert, const cyhal_clock_divider_t *clk);
 
 /** Deinitialize the PWM object
  *
@@ -85,26 +166,26 @@ void cyhal_pwm_free(cyhal_pwm_t *obj);
  */
 cy_rslt_t cyhal_pwm_set_period(cyhal_pwm_t *obj, uint32_t period_us, uint32_t pulse_width_us);
 
-/** Set the PWM pulsewidth specified in microseconds, keeping the period the same.
+/** Set the PWM duty cycle and frequency
  *
- * @param[in] obj          The PWM object
+ * @param[in] obj             The PWM object
- * @param[in] duty_cycle   The percentage of time the output is high
+ * @param[in] duty_cycle      The percentage of time the output is high
- * @param[in] frequencyhal_hz The frequency of the PWM
+ * @param[in] frequencyhal_hz The frequency of the PWM in Hz
- * @return The status of the pulsewidth request
+ * @return                    The status of the duty cycle request
  */
 cy_rslt_t cyhal_pwm_set_duty_cycle(cyhal_pwm_t *obj, float duty_cycle, uint32_t frequencyhal_hz);
 
-/** Starts the PWM with the provided period and pulsewidth
+/** Starts the PWM generation and outputs on <b>pin</b> and <b>compl_pin</b>.
  *
  * @param[in] obj           The PWM object
- * @return The status of the start request
+ * @return                  The status of the start request
  */
 cy_rslt_t cyhal_pwm_start(cyhal_pwm_t *obj);
 
-/** Stops the PWM from running
+/** Stops the PWM generation and outputs on <b>pin</b> and <b>compl_pin</b>.
  *
- * @param[in] obj The PWM object
+ * @param[in] obj          The PWM object
- * @return The status of the stop request
+ * @return                 The status of the stop request
  */
 cy_rslt_t cyhal_pwm_stop(cyhal_pwm_t *obj);
 
@@ -118,12 +199,12 @@ void cyhal_pwm_register_callback(cyhal_pwm_t *obj, cyhal_pwm_event_callback_t ca
 
 /** Configure PWM event enablement.
  *
- * @param[in] obj           The PWM object
+ * @param[in] obj            The PWM object
- * @param[in] event         The PWM event type
+ * @param[in] event          The PWM event type
- * @param[in] intrPriority  The priority for NVIC interrupt events
+ * @param[in] intr_priority  The priority for NVIC interrupt events
- * @param[in] enable        True to turn on events, False to turn off
+ * @param[in] enable         True to turn on events, False to turn off
  */
-void cyhal_pwm_enable_event(cyhal_pwm_t *obj, cyhal_pwm_event_t event, uint8_t intrPriority, bool enable);
+void cyhal_pwm_enable_event(cyhal_pwm_t *obj, cyhal_pwm_event_t event, uint8_t intr_priority, bool enable);
 
 #if defined(__cplusplus)
 }

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm_impl.h

@@ -6,7 +6,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2019 Cypress Semiconductor Corporation
+* Copyright 2019-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -29,7 +29,10 @@
 * \addtogroup group_hal_qspi QSPI (Quad Serial Peripheral Interface)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress Quad-SPI.
+* High level interface for interacting with the Quad Serial Peripheral Interface (QSPI) interface.
+*
+* The QSPI block supports sending commands to and receiving commands from an
+* another device (often an external memory) via single, dual, quad, or octal SPI.
 */
 
 #pragma once
@@ -71,12 +74,10 @@ typedef enum {
 } cyhal_qspi_event_t;
 
 #define CYHAL_QSPI_RSLT_ERR_BUS_WIDTH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 0)) /**< Bus width Error. >*/
-#define CYHAL_QSPI_RSLT_ERR_SIZE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 1)) /**< Size Error. >*/
+#define CYHAL_QSPI_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 1)) /**< Pin related Error. >*/
-#define CYHAL_QSPI_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 2)) /**< Pin related Error. >*/
+#define CYHAL_QSPI_RSLT_ERR_DATA_SEL (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 2)) /**< Data select Error. >*/
-#define CYHAL_QSPI_RSLT_ERR_DATA_SEL (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 3)) /**< Data select Error. >*/
+#define CYHAL_QSPI_RSLT_ERR_INSTANCE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 3)) /**< QSPI instance related Error. >*/
-#define CYHAL_QSPI_RSLT_ERR_INSTANCE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 4)) /**< QSPI instance related Error. >*/
+#define CYHAL_QSPI_RSLT_ERR_FREQUENCY (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 4)) /**< Clock frequency error. >*/
-#define CYHAL_QSPI_RSLT_ERR_ALT_SIZE_WIDTH_MISMATCH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 5)) /**< Provided alt size is incompatible with provided alt width. >*/
-#define CYHAL_QSPI_RSLT_ERR_ALT_SIZE_DUMMY_CYCLES_MISMATCH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 6)) /**< Provided alt size is incompatible with provided number of dummy cycles (due to device-specific restrictions). >*/
 
 /** @brief QSPI command settings */
 typedef struct cyhal_qspi_command {
@@ -93,7 +94,7 @@ typedef struct cyhal_qspi_command {
     }  address;
     struct {
         cyhal_qspi_bus_width_t bus_width;               /**< Bus width for mode bits  >*/
-        uint8_t size;                                   /**< Mode bits size >*/
+        cyhal_qspi_size_t size;                         /**< Mode bits size >*/
         uint32_t value;                                 /**< Mode bits value >*/
         bool disabled;                                  /**< Mode bits phase skipped if disabled is set to true >*/
     } mode_bits;

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_rtc.h

@@ -2,14 +2,14 @@
 * \file cyhal_rtc.h
 *
 * \brief
-* Provides a high level interface for interacting with the Real Time Clock on 
+* Provides a high level interface for interacting with the Real Time Clock on
-* Cypress devices.  This interface abstracts out the chip specific details. 
+* Cypress devices.  This interface abstracts out the chip specific details.
-* If any chip specific functionality is necessary, or performance is critical 
+* If any chip specific functionality is necessary, or performance is critical
 * the low level functions can be used directly.
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -29,7 +29,14 @@
 * \addtogroup group_hal_rtc RTC (Real-Time Clock)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress RTC.
+* High level interface for interacting with the real-time clock (RTC).
+*
+* The real time clock provides tracking of the current time and date, as
+* well as the ability to trigger a callback at a specific time in the future.
+*
+* If a suitable clock source is available, the RTC can continue timekeeping
+* operations even when the device is in a low power operating mode. See the
+* device datasheet for more details.
 */
 
 #pragma once
@@ -43,6 +50,8 @@
 
 /** RTC not initialized */
 #define CY_RSLT_RTC_NOT_INITIALIZED CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_RTC, 0)
+/** Bad argument */
+#define CY_RSLT_RTC_BAD_ARGUMENT CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_RTC, 1)
 
 #if defined(__cplusplus)
 extern "C" {
@@ -64,6 +73,35 @@ typedef struct
     uint8_t en_month : 1; /** !< Enable match of month */
 } cyhal_alarm_active_t;
 
+/** Enumeration used to configure the DST format */
+typedef enum
+{
+    CYHAL_RTC_DST_RELATIVE,        /**< Relative DST format */
+    CYHAL_RTC_DST_FIXED            /**< Fixed DST format */
+} cyhal_rtc_dst_format_t;
+
+/**
+* Day Light Savings Time (DST) structure for setting when to apply. It allows to
+* set the DST time and date using a fixed or relative time format.
+*/
+typedef struct
+{
+    cyhal_rtc_dst_format_t format;   /**< DST format. See /ref cyhal_rtc_dst_format_t.
+                                          Based on this value other structure elements
+                                          should be filled or could be ignored */
+    uint32_t hour;                   /**< Hour in 24hour format, range[0-23] */
+    union
+    {
+        uint32_t dayOfMonth;         /**< Day of Month, range[1-31]. */
+        struct /* format = CYHAL_RTC_DST_FIXED */
+        {
+            uint32_t dayOfWeek;      /**< Day of the week, starting on Sunday, range[0-6] */
+            uint32_t weekOfMonth;    /**< Week of month, range[0-5]. Where 5 => Last week of month */
+        };
+    };
+    uint32_t month;                  /**< Month value, range[1-12]. */
+} cyhal_rtc_dst_t;
+
 /** Handler for RTC events */
 typedef void (*cyhal_rtc_event_callback_t)(void *callback_arg, cyhal_rtc_event_t event);
 
@@ -83,7 +121,7 @@ cy_rslt_t cyhal_rtc_init(cyhal_rtc_t *obj);
 
 /** Deinitialize RTC
  *
- * Frees resources associated with the RTC and disables CPU access. This 
+ * Frees resources associated with the RTC and disables CPU access. This
  * only affects the CPU domain and not the time keeping logic.
  * After this function is called no other RTC functions should be called
  * except for rtc_init.
@@ -115,6 +153,23 @@ cy_rslt_t cyhal_rtc_read(cyhal_rtc_t *obj, struct tm *time);
  */
 cy_rslt_t cyhal_rtc_write(cyhal_rtc_t *obj, const struct tm *time);
 
+/** Set the start and end time for Day Light Savings
+ *
+ * @param[in] obj  RTC object
+ * @param[in] start When Day Light Savings time should start
+ * @param[in] stop When Day Light Savings time should end
+ * @return The status of the set_dst request
+ */
+cy_rslt_t cyhal_rtc_set_dst(cyhal_rtc_t *obj, const cyhal_rtc_dst_t *start, const cyhal_rtc_dst_t *stop);
+
+/** Checks to see if Day Light Savings Time is currently active. This should only be called after
+ * \ref cyhal_rtc_set_dst().
+ *
+ * @param[in] obj  RTC object
+ * @return Boolean indicating whether the current date/time is within the specified DST start/stop window.
+ */
+bool cyhal_rtc_is_dst(cyhal_rtc_t *obj);
+
 /** Set an alarm for the specified time in seconds to the RTC peripheral
  *
  * @param[in] obj    RTC object

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h

@@ -6,7 +6,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -22,6 +22,7 @@
 * limitations under the License.
 *******************************************************************************/
 
+/** \cond INTERNAL */
 /**
  * \addtogroup group_hal_psoc6_scb_common SCB Common Functionality
  * \ingroup group_hal_psoc6
@@ -71,3 +72,4 @@ __STATIC_INLINE void *cyhal_scb_get_irq_obj(void)
 #endif
 
 /** \} group_hal_psoc6_scb_common */
+/** \endcond */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -29,7 +29,10 @@
 * \addtogroup group_hal_sdhc SDHC (SD Host Controller)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress SDHC.
+* High level interface for interacting with the SD Host Controller (SDHC).
+*
+* The SD Host Controller allows data to be read from and written to several types
+* of memory cards, including SD and eMMC (see cyhal_sdhc_card_type_t for a full list).
 */
 
 #pragma once
@@ -44,12 +47,13 @@ extern "C" {
 #endif
 
 #define CYHAL_SDHC_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDHC, 0)) /**< Pin related Error. >*/
+#define CYHAL_SDHC_RSLT_ERR_UNSUPPORTED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDHC, 1)) /**< Requested feature is not supported on this hardware. >*/
 
 /** Card types */
 typedef enum
 {
     CYHAL_SDHC_SD, //!< Secure Digital card
-    CYHAL_SDHC_SDIO, //!< CD Input Output card
+    CYHAL_SDHC_SDIO, //!< SD Input Output card
     CYHAL_SDHC_EMMC, //!< Embedded Multimedia card
     CYHAL_SDHC_COMBO, //!< Combo Card (SD + SDIO)
     CYHAL_SDHC_UNUSABLE, //!< Unusable card or unsupported type

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdio.h

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -29,8 +29,14 @@
 * \addtogroup group_hal_sdio SDIO (Secure Digital Input Output)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress SDIO interface.
+* High level interface for interacting with the Secure Digital Input Output (SDIO) interface.
 *
+* The Secure Digital Input Output (SDIO) protocol is an extension of the SD
+* interface for general I/O functions.
+*
+* This driver allows commands to be sent over the SDIO bus; the supported commands
+* can be found in cyhal_sdio_command_t. Bulk data transfer is also supported
+* via cyhal_sdio_bulk_transfer().
 */
 
 #pragma once
@@ -44,11 +50,6 @@
 extern "C" {
 #endif
 
-/**
-  * \addtogroup group_hal_sdio_errors Error Codes
-  * \{
-  */
-
 #define CYHAL_SDIO_RET_NO_ERRORS           (0x00)    /**< No error*/
 #define CYHAL_SDIO_RET_NO_SP_ERRORS        (0x01)    /**< Non-specific error code*/
 #define CYHAL_SDIO_RET_CMD_CRC_ERROR       (0x02)    /**< There was a CRC error on the Command/Response*/
@@ -91,8 +92,6 @@ extern "C" {
                                                             CYHAL_RSLT_MODULE_SDIO, \
                                                             CYHAL_SDIO_CANCELED)
 
-/** \} group_hal_sdio_errors */
-
 /** Commands that can be issued */
 typedef enum
 {
@@ -115,7 +114,7 @@ typedef enum
 /** Types of events that could be asserted by SDIO */
 typedef enum {
     /* Interrupt-based thread events */
-    CYHAL_SDIO_CMD_COMPLETE   = 0x00001,  //!> Command Complete 
+    CYHAL_SDIO_CMD_COMPLETE   = 0x00001,  //!> Command Complete
     CYHAL_SDIO_XFER_COMPLETE  = 0x00002,  //!> Host read/write transfer is complete
     CYHAL_SDIO_BGAP_EVENT     = 0x00004,  //!> This bit is set when both read/write transaction is stopped
     CYHAL_SDIO_DMA_INTERRUPT  = 0x00008,  //!> Host controller detects an SDMA Buffer Boundary during transfer
@@ -131,11 +130,11 @@ typedef enum {
     CYHAL_SDIO_FX_EVENT       = 0x02000,  //!> This status is set when R[14] of response register is set to 1
     CYHAL_SDIO_CQE_EVENT      = 0x04000,  //!> This status is set if Command Queuing/Crypto event has occurred
     CYHAL_SDIO_ERR_INTERRUPT  = 0x08000,  //!> If any of the bits in the Error Interrupt Status register are set
-    
+
     /* Non-interrupt-based thread events */
     CYHAL_SDIO_GOING_DOWN     = 0x10000, //!> The interface is going away (eg: powering down for some period of time)
     CYHAL_SDIO_COMING_UP      = 0x20000, //!> The interface is back up (eg: came back from a low power state)
-    
+
     CYHAL_SDIO_ALL_INTERRUPTS = 0x0E1FF,  //!> Is used to enable/disable all interrupts events
 } cyhal_sdio_event_t;
 
@@ -193,9 +192,13 @@ cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t directio
  * @param[in,out] obj       The SDIO object
  * @param[in]     direction The direction of transfer (read/write)
  * @param[in]     argument  The argument to the command
- * @param[in]     data      The data to send to the SDIO device. The data buffer 
+ * @param[in]     data      The data to send to the SDIO device. A bulk transfer is done in block
- *                          should be aligned to the block size (64 bytes) if data 
+ *                          size (default: 64 bytes) chunks for better performance. Therefore,
- *                          size is greater that block size (64 bytes).
+ *                          the size of the data buffer passed into this function must be at least
+ *                          `length` bytes and a multiple of the block size. For example, when
+ *                          requesting to read 100 bytes of data with a block size 64 bytes, the
+ *                          data buffer needs to be at least 128 bytes. The first 100 bytes of data
+ *                          in the buffer will be the requested data.
  * @param[in]     length    The number of bytes to send
  * @param[out]    response  The response from the SDIO device
  * @return The status of the configure request
@@ -245,7 +248,7 @@ void cyhal_sdio_register_callback(cyhal_sdio_t *obj, cyhal_sdio_event_callback_t
 void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_event_t event, uint8_t intrPriority, bool enable);
 
 /*******************************************************************************
-* Backward compatibility macro. The following code is DEPRECATED and must 
+* Backward compatibility macro. The following code is DEPRECATED and must
 * not be used in new projects
 *******************************************************************************/
 /** \cond INTERNAL */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_spi.h

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -29,7 +29,59 @@
 * \addtogroup group_hal_spi SPI (Serial Peripheral Interface)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress SPI.
+* High level interface for interacting with the Serial Peripheral Interface (SPI).
+*
+* The SPI protocol is a synchronous serial interface protocol. Devices operate
+* in either master or slave mode. The master initiates the data transfer.
+*
+* Motorola SPI modes 0, 1, 2, and 3 are supported, with either MSB or LSB first.
+* The operating mode and data frame size can be configured via \ref cyhal_spi_cfg_t.
+*
+* \section section_spi_features Features
+* * Supports master and slave functionality.
+* * Supports Motorola modes - 0, 1, 2 and 3 - \ref cyhal_spi_mode_t
+* * MSb or LSb first shift direction - \ref cyhal_spi_mode_t
+* * Master supports up to four slave select lines
+* * Supports data frame size of 8 or 16 bits
+* * Configurable interrupt and callback assignment on SPI events:
+* Data transfer to FIFO complete, Transfer complete and Transmission error - \ref cyhal_spi_event_t
+* * Supports changing baud rate of the transaction in run time.
+* * Provides functions to send/receive a single byte or block of data.
+*
+* \section section_spi_quickstart Quick Start
+*
+* Initialise a SPI master or slave interface using \ref cyhal_spi_init() and provide the SPI pins (<b>mosi</b>, <b>miso</b>, <b>sclk</b>, <b>ssel</b>),
+* number of bits per frame (<b>data_bits</b>) and SPI Motorola <b>mode</b>. The data rate can be set using \ref cyhal_spi_set_frequency(). <br>
+* See \ref section_spi_snippets for code snippets to send or receive the data.
+*
+* \section section_spi_snippets Code snippets
+*
+* \subsection subsection_spi_snippet_1 Snippet 1: SPI Master - Single byte transfer operation (Read and Write)
+* The following code snippet initialises an SPI Master interface using the \ref cyhal_spi_init(). The data rate of transfer is set using \ref cyhal_spi_set_frequency().
+* The code snippet shows how to transfer a single byte of data using \ref cyhal_spi_send() and \ref cyhal_spi_recv().
+* \snippet spi.c snippet_cyhal_spi_master_byte_operation
+*
+* \subsection subsection_spi_snippet_2 Snippet 2: SPI Slave - Single byte transfer operation (Read and Write)
+* The following code snippet initialises an SPI Slave interface using the \ref cyhal_spi_init(). The data rate of transfer is set using \ref cyhal_spi_set_frequency.
+* The code snippet shows how to transfer a single byte of data using \ref cyhal_spi_send() and \ref cyhal_spi_recv.
+* \snippet spi.c snippet_cyhal_spi_slave_byte_operation
+*
+* \subsection subsection_spi_snippet_3 Snippet 3: SPI Block Data transfer
+* The following snippet sends and receives an array of data in a single SPI transaction using \ref cyhal_spi_transfer(). The example
+* uses SPI master to transmit 5 bytes of data and receive 5 bytes of data in a single transaction.
+* \snippet spi.c snippet_cyhal_spi_block_data_transfer
+*
+* \subsection subsection_spi_snippet_4 Snippet 4: Interrupts on SPI events
+* SPI interrupt events ( \ref cyhal_spi_event_t) can be mapped to an interrupt and assigned to a callback function.
+* The callback function needs to be first registered and then the event needs to be enabled.
+* The following snippet initialises a SPI master to perform a block transfer using \ref cyhal_spi_transfer_async(). This is a non-blocking function.
+*  A callback function is registered using \ref cyhal_spi_register_callback to notify whenever the SPI transfer is complete.
+* \snippet spi.c snippet_cyhal_spi_interrupt_callback_events
+
+* \section subsection_spi_moreinfor More Information
+*
+* * <a href="https://github.com/cypresssemiconductorco/mtb-example-psoc6-spi-master"><b>mtb-example-psoc6-spi-master</b></a>: This example project demonstrates
+* use of SPI (HAL) resource in PSoC® 6 MCU in Master mode to write data to an SPI slave.
 */
 
 #pragma once
@@ -44,7 +96,6 @@
 extern "C" {
 #endif
 
-
 /** Bad argument */
 #define CYHAL_SPI_RSLT_BAD_ARGUMENT                    (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 0))
 /** Failed to initialize SPI clock */
@@ -105,7 +156,6 @@ typedef struct
     bool is_slave; //!< Whether the peripheral is operating as slave or master
 } cyhal_spi_cfg_t;
 
-
 /** Initialize the SPI peripheral
  *
  * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
@@ -232,7 +282,7 @@ void cyhal_spi_register_callback(cyhal_spi_t *obj, cyhal_spi_event_callback_t ca
 void cyhal_spi_enable_event(cyhal_spi_t *obj, cyhal_spi_event_t event, uint8_t intrPriority, bool enable);
 
 /*******************************************************************************
-* Backward compatibility macro. The following code is DEPRECATED and must 
+* Backward compatibility macro. The following code is DEPRECATED and must
 * not be used in new projects
 *******************************************************************************/
 /** \cond INTERNAL */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system.h

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -26,11 +26,16 @@
 *******************************************************************************/
 
 /**
-* \addtogroup group_hal_system SYSTEM (Power Management and System Clock)
+* \addtogroup group_hal_system System (Power Management and System Clock)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress power management
+* High level interface for interacting with the power management
 * and system clock configuration.
+*
+* This driver provides three categories of functionality:
+* * Retrieval and adjustment of system clock frequencies.
+* * Control over low power operating modes.
+* * The ability to disable interrupts during a critical section, and to renable them afterwards.
 */
 
 #pragma once
@@ -56,6 +61,19 @@ extern "C" {
 /** An error occurred in System module */
 #define CYHAL_SYSTEM_RSLT_NO_VALID_DIVIDER (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SYSTEM , 4))
 
+/** Flags enum of possible system reset causes */
+typedef enum
+{
+    CYHAL_SYSTEM_RESET_NONE            = 0,      /** No cause */
+    CYHAL_SYSTEM_RESET_WDT             = 1 << 0, /** A watchdog timer (WDT) reset has occurred */
+    CYHAL_SYSTEM_RESET_ACTIVE_FAULT    = 1 << 1, /** The fault logging system requested a reset from its Active logic. */
+    CYHAL_SYSTEM_RESET_DEEPSLEEP_FAULT = 1 << 2, /** The fault logging system requested a reset from its Deep-Sleep logic. */
+    CYHAL_SYSTEM_RESET_SOFT            = 1 << 3, /** The CPU requested a system reset through it's SYSRESETREQ. */
+    CYHAL_SYSTEM_RESET_HIB_WAKEUP      = 1 << 4, /** A reset has occurred due to a a wakeup from hibernate power mode. */
+    CYHAL_SYSTEM_RESET_WCO_ERR         = 1 << 5, /** A reset has occurred due to a watch-crystal clock error */
+    CYHAL_SYSTEM_RESET_SYS_CLK_ERR     = 1 << 6, /** A reset has occurred due to a system clock error */
+} cyhal_reset_reason_t;
+
 /** Enter a critical section
  *
  * Disables interrupts and returns a value indicating whether the interrupts were previously
@@ -113,6 +131,32 @@ cy_rslt_t cyhal_system_register_callback(cyhal_system_callback_t *callback);
  */
 cy_rslt_t cyhal_system_unregister_callback(cyhal_system_callback_t const *callback);
 
+/**
+ * Requests that the current operation delays for at least the specified length of time.
+ * If this is running in an RTOS aware environment (-DCY_RTOS_AWARE) it will attempt to
+ * have the RTOS suspend the current task so others can continue to run. If this is not
+ * run under an RTOS it will then defer to the standard system delay which is likely to
+ * be a busy loop.
+ * If this is part of an application that is build with RTOS awareness, but the delay
+ * should not depend on the RTOS for whatever reason, use cyhal_system_delay_us() with
+ * the appropriate 1000x multiplier to the delay time.
+ *
+ * @param[in] milliseconds The number of milliseconds to delay for
+ * @return Returns CY_RSLT_SUCCESS if the delay request was successful, otherwise error
+ */
+cy_rslt_t cyhal_system_delay_ms(uint32_t milliseconds);
+
+/**
+ * Requests that the current operation delay for at least the specified number of
+ * micro-seconds. This will generally keep the processor active in a loop for the
+ * specified length of time. If this is running under an RTOS, it will NOT attempt to
+ * run any other RTOS tasks, however if the scheduler or a high priority interrupt
+ * comes it they can take over anyway.
+ *
+ * @param[in] microseconds The number of micro-seconds to delay for
+ */
+void cyhal_system_delay_us(uint16_t microseconds);
+
 /** Gets the specified clock's current frequency.
  *
  * @param[in]  clock        ID of clock to configure
@@ -138,6 +182,15 @@ cy_rslt_t cyhal_system_clock_set_frequency(uint8_t clock, uint32_t frequency_hz)
  */
 cy_rslt_t cyhal_system_clock_set_divider(cyhal_system_clock_t clock, cyhal_system_divider_t divider);
 
+/** Gets the cause of the latest reset or resets that occured in the system.
+ *
+ * @return Returns an enum of flags with the cause of the last reset(s)
+ */
+cyhal_reset_reason_t cyhal_system_get_reset_reason(void);
+
+/** Clears the reset cause registers */
+void cyhal_system_clear_reset_reason(void);
+
 #if defined(__cplusplus)
 }
 #endif

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system_impl.h

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -31,7 +31,7 @@
 
 #ifdef CY_IP_MXS40SRSS
 
-#define cyhal_system_critical_section_enter()     Cy_SysLib_EnterCriticalSection()
+#define cyhal_system_critical_section_enter()   Cy_SysLib_EnterCriticalSection()
 
 #define cyhal_system_critical_section_exit(x)   Cy_SysLib_ExitCriticalSection(x)
 
@@ -39,4 +39,6 @@
 
 #define cyhal_system_deepsleep()                Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT)
 
+#define cyhal_system_delay_us(microseconds)     Cy_SysLib_DelayUs(microseconds)
+
 #endif /* CY_IP_MXS40SRSS */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_tcpwm_common.h

@@ -6,7 +6,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2019 Cypress Semiconductor Corporation
+* Copyright 2019-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -22,6 +22,7 @@
 * limitations under the License.
 *******************************************************************************/
 
+/** \cond INTERNAL */
 /**
  * \addtogroup group_hal_psoc6_tcpwm_common TCPWM Common Functionality
  * \ingroup group_hal_psoc6
@@ -77,3 +78,4 @@ void cyhal_tcpwm_register_callback(cyhal_resource_inst_t *resource, cy_israddres
 void cyhal_tcpwm_enable_event(TCPWM_Type *type, cyhal_resource_inst_t *resource, uint32_t event, uint8_t intrPriority, bool enable);
 
 /** \} group_hal_psoc6_tcpwm_common */
+/** \endcond */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer.h

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -26,10 +26,57 @@
 *******************************************************************************/
 
 /**
-* \addtogroup group_hal_timer TIMER (Timer/Counter)
+* \addtogroup group_hal_timer Timer (Timer/Counter)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress Timer.
+* High level interface for interacting with the Timer/Counter hardware resource.
+*
+* The timer block is commonly used to measure the time of occurrence of an event,
+* to measure the time difference between two events or perform an action after
+* a specified period of time. The driver also allows the user to invoke a callback function
+* when a particular event occurs.
+*
+* Some use case scenarios of timer -
+*
+* * Creating a periodic interrupt for executing periodic tasks
+* * Measuring time between two events
+* * Triggering other system resources after a certain number of events
+* * Capturing time stamps when events occur
+*
+* \section subsection_timer_features Features
+* * Runtime configurable parameters like period and compare value - \ref cyhal_timer_cfg_t
+* * Configurable counting direction - \ref cyhal_timer_direction_t
+* * Interrupt on various events - \ref cyhal_timer_event_t
+* * Continuous or One Shot run modes
+*
+* \section subsection_timer_quickstart Quick Start
+*
+* \ref cyhal_timer_init can be used for timer initialization by providing the timer object - \ref cyhal_timer_t,
+* and shared clock source - <b> clk </b> (optional). The timer parameters needs to be populated in \ref cyhal_timer_cfg_t structure.
+* The timer then needs to be configured by using the \ref cyhal_timer_configure function.
+*
+* \note A default frequency is set when an existing clock divider - <b> clk </b> is not provided to \ref cyhal_timer_init which is
+* defined by the macro - \ref CYHAL_TIMER_DEFAULT_FREQ.
+*
+* \warning Currently there is no support for pin connections to Timer using this driver. So, the <b> pin </b> should be
+* assigned as \ref NC while using the \ref cyhal_timer_init to initialize the timer.
+*
+*
+* See \ref subsection_timer_snippet_1.
+*
+* \section subsection_timer_sample_snippets Code Snippets
+*
+* \subsection subsection_timer_snippet_1 Snippet 1: Measuring time between two events
+* The following snippet initializes a Timer and measures the time between two events.
+* The <b>clk</b> need not be provided, in which case a clock resource is assigned.
+* \snippet timer.c snippet_cyhal_timer_event_measure
+*
+* \subsection subsection_timer_snippet_2 Snippet 2: Handling an event in a callback function
+* The following snippet initializes a Timer and triggers an event after every one second.
+* The <b>clk</b> need not be provided (NULL), in which
+* case a clock resource is assigned.
+* \snippet timer.c snippet_cyhal_timer_event_interrupt
+*
 */
 
 #pragma once
@@ -44,6 +91,10 @@
 extern "C" {
 #endif
 
+/*******************************************************************************
+*       Enumerations
+*******************************************************************************/
+
 /** Timer directions */
 typedef enum
 {
@@ -54,17 +105,21 @@ typedef enum
 
 /** Timer/counter interrupt triggers */
 typedef enum {
-    CYHAL_TIMER_IRQ_NONE            =  0,
+    CYHAL_TIMER_IRQ_NONE            =  0, /**< No interrupt handled **/
-    CYHAL_TIMER_IRQ_TERMINAL_COUNT  =  1 << 0,
+    CYHAL_TIMER_IRQ_TERMINAL_COUNT  =  1 << 0, /**< Interrupt when terminal count is reached **/
-    CYHAL_TIMER_IRQ_CAPTURE_COMPARE =  1 << 1,
+    CYHAL_TIMER_IRQ_CAPTURE_COMPARE =  1 << 1, /**< Interrupt when Compare/Capture value is reached **/
-    CYHAL_TIMER_IRQ_ALL             = (1 << 2) - 1,
+    CYHAL_TIMER_IRQ_ALL             = (1 << 2) - 1, /**< Interrupt on terminal count and Compare/Capture values **/
 } cyhal_timer_event_t;
 
+/*******************************************************************************
+*       Data Structures
+*******************************************************************************/
+
 /** @brief Describes the current configuration of a timer/counter */
 typedef struct
 {
     /**
-      * Whether the timer is set to continously run.
+      * Whether the timer is set to continuously run.
       * If true, the timer will run forever.
       * Otherwise, the timer will run once and stop (one shot).
       */
@@ -76,6 +131,10 @@ typedef struct
     uint32_t value; //!< Current value of the timer/counter
 } cyhal_timer_cfg_t;
 
+/*******************************************************************************
+*       Typedefs
+*******************************************************************************/
+
 /** Handler for timer events */
 typedef void(*cyhal_timer_event_callback_t)(void *callback_arg, cyhal_timer_event_t event);
 
@@ -91,7 +150,12 @@ typedef void(*cyhal_timer_event_callback_t)(void *callback_arg, cyhal_timer_even
 /** Default timer frequency, used when an existing clock divider is not provided to init */
 #define CYHAL_TIMER_DEFAULT_FREQ (1000000u)
 
-/** Initialize the timer/counter peripheral and configure the pin.
+/*******************************************************************************
+*       Functions
+*******************************************************************************/
+
+/** Initialize the timer/counter peripheral and configure the pin. <br>
+ * See \ref subsection_timer_snippet_1.
  *
  * @param[out] obj The timer/counter object to initialize
  * @param[in]  pin optional - The timer/counter compare/capture pin to initialize
@@ -107,38 +171,51 @@ cy_rslt_t cyhal_timer_init(cyhal_timer_t *obj, cyhal_gpio_t pin, const cyhal_clo
  */
 void cyhal_timer_free(cyhal_timer_t *obj);
 
-/** Updates the configuration of the timer/counter object
+/** Updates the configuration of the timer/counter object <br>
- *
+ * See \ref subsection_timer_snippet_1.
  * @param[in] obj  The timer/counter object
  * @param[in] cfg  The configuration of the timer/counter
  * @return The status of the configure request
  */
 cy_rslt_t cyhal_timer_configure(cyhal_timer_t *obj, const cyhal_timer_cfg_t *cfg);
 
-/** Configures the timer frequency. This is not valid to call if a non-null clock divider 
+/** Configures the timer frequency.
- *  was provided to cyhal_timer_init
+ * \note This is only valid to call if a null clock divider was provided to \ref cyhal_timer_init.
+ * If a custom clock was provided its frequency should be adjusted directly.
  *
+ * See \ref subsection_timer_snippet_1.
  * @param[in] obj  The timer/counter object
  * @param[in] hz   The frequency rate in Hz
  * @return The status of the set_frequency request
  */
 cy_rslt_t cyhal_timer_set_frequency(cyhal_timer_t *obj, uint32_t hz);
 
-/** Starts the timer/counter with the pre-set configuration.
+/** Starts the timer/counter with the pre-set configuration <br>
+ * See \ref subsection_timer_snippet_1.
  *
  * @param[in] obj     The timer/counter object
  * @return The status of the start request
  */
 cy_rslt_t cyhal_timer_start(cyhal_timer_t *obj);
 
-/** Stops the timer/counter.
+/** Stops the timer/counter <br>
+ * See \ref subsection_timer_snippet_1.
  *
  * @param[in] obj     The timer/counter object
  * @return The status of the stop request
  */
 cy_rslt_t cyhal_timer_stop(cyhal_timer_t *obj);
 
-/** The timer/counter callback handler registration
+/** Reads the current value from the timer/counter <br>
+ * See \ref subsection_timer_snippet_1.
+ *
+ * @param[in] obj     The timer/counter object
+ * @return The current value of the timer/counter
+ */
+uint32_t cyhal_timer_read(const cyhal_timer_t *obj);
+
+/** The timer/counter callback handler registration <br>
+ * See \ref subsection_timer_snippet_2.
  *
  * @param[in] obj          The timer/counter object
  * @param[in] callback     The callback handler which will be invoked when the event occurs
@@ -146,14 +223,15 @@ cy_rslt_t cyhal_timer_stop(cyhal_timer_t *obj);
  */
 void cyhal_timer_register_callback(cyhal_timer_t *obj, cyhal_timer_event_callback_t callback, void *callback_arg);
 
-/** Configure timer/counter event enablement.
+/** Configure timer/counter event enablement <br>
+ * See \ref subsection_timer_snippet_2.
  *
  * @param[in] obj           The timer/counter object
  * @param[in] event         The timer/counter event type
- * @param[in] intrPriority  The priority for NVIC interrupt events
+ * @param[in] intr_priority  The priority for NVIC interrupt events
  * @param[in] enable        True to turn on interrupts, False to turn off
  */
-void cyhal_timer_enable_event(cyhal_timer_t *obj, cyhal_timer_event_t event, uint8_t intrPriority, bool enable);
+void cyhal_timer_enable_event(cyhal_timer_t *obj, cyhal_timer_event_t event, uint8_t intr_priority, bool enable);
 
 #if defined(__cplusplus)
 }

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer_impl.h

@@ -6,7 +6,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2019 Cypress Semiconductor Corporation
+* Copyright 2019-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_triggers.h

@@ -0,0 +1,56 @@
+/***************************************************************************//**
+* \file cyhal_triggers.h
+*
+* Description:
+* Provides definitions for the triggers for each supported device family.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/**
+* \addtogroup group_hal_psoc6_triggers Triggers
+* \ingroup group_hal_psoc6
+* \{
+* Trigger connections for supported device families
+*/
+
+#pragma once
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+#include "cy_device.h"
+
+#ifdef CY_DEVICE_PSOC6ABLE2
+#include "triggers/cyhal_triggers_psoc6_01.h"
+#endif
+
+#ifdef CY_DEVICE_PSOC6A2M
+#include "triggers/cyhal_triggers_psoc6_02.h"
+#endif
+
+#ifdef CY_DEVICE_PSOC6A512K
+#include "triggers/cyhal_triggers_psoc6_03.h"
+#endif
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/** \} group_hal_psoc6_triggers */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng.h

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -29,7 +29,9 @@
 * \addtogroup group_hal_trng TRNG (True Random Number Generator)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress TRNG.
+* High level interface for interacting with the true random number generator (TRNG).
+*
+* This block uses dedicated hardware to efficiently generate truly random numbers.
 */
 
 #pragma once

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng_impl.h

@@ -6,7 +6,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_uart.h

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -29,7 +29,27 @@
 * \addtogroup group_hal_uart UART (Universal Asynchronous Receiver-Transmitter)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress UART.
+* High level interface for interacting with the Universal Asynchronous Receiver-Transmitter (UART).
+*
+* The Universal Asynchronous Receiver/Transmitter (UART) protocol is an
+* asynchronous serial interface protocol. UART communication is typically
+* point-to-point. The UART interface consists of two signals:
+* * TX: Transmitter output
+* * RX: Receiver input
+*
+* Additionally, two side-band signals are used to implement flow control in
+* UART. Note that the flow control applies only to TX functionality.
+* * Clear to Send (CTS): This is an input signal to the transmitter.
+*   When active, it indicates that the slave is ready for the master to
+*   transmit data.
+* * Ready to Send (RTS): This is an output signal from the receiver. When
+*   active, it indicates that the receiver is ready to receive data
+*
+* Flow control can be configured via cyhal_uart_set_flow_control()
+*
+* The data frame size, STOP bits, and parity can be configured via cyhal_uart_cfg_t.
+* The UART contains dedicated hardware buffers for transmit and receive. Optionally,
+* either these can be augmented with a software buffer.
 */
 
 #pragma once

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_usb_dev.h

@@ -29,8 +29,16 @@
 * \addtogroup group_hal_usb_dev USB Device
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress USB Device.
+* High level interface for interacting with the USB Device interface.
-* 
+*
+* This block supports one control endpoint (EP0) and one or more data endpoints
+* see the device datasheet for the number of data endpoints supported.
+*
+* Four transfer types are supported (cyhal_usb_dev_ep_type_t):
+* * Bulk
+* * Interrupt
+* * Isochronous
+* * Control
 */
 
 #pragma once
@@ -45,6 +53,10 @@
 extern "C" {
 #endif
 
+/**
+  * \addtogroup group_hal_usb_dev_common Common
+  * \{
+  */
 /** The usb error */
 #define CYHAL_USB_DEV_RSLT_ERR (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_USB, 0))
 
@@ -54,7 +66,9 @@ extern "C" {
 /** The configuration of USB clock failed */
 #define CYHAL_USB_DEV_RSLT_ERR_CLK_CFG   (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_USB, 2))
 
-/** 
+/** \} group_hal_usb_dev_common */
+
+/**
   * \addtogroup group_hal_usb_dev_endpoint Endpoint
   * \{
   * APIs relating to endpoint management
@@ -79,6 +93,11 @@ typedef enum
 
 /** \} group_hal_usb_dev_endpoint */
 
+/**
+  * \addtogroup group_hal_usb_dev_common Common
+  * \{
+  */
+
 /** Service Callback Events */
 typedef enum
 {
@@ -88,20 +107,22 @@ typedef enum
     CYHAL_USB_DEV_EVENT_EP0_OUT,    /**< Callback hooked to endpoint 0 OUT packet interrupt */
 } cyhal_usb_dev_event_t;
 
-/** 
+/**
-  * USB endpoint address (consists from endpoint number and direction) 
+  * USB endpoint address (consists from endpoint number and direction)
-  * 
+  *
-  * \ingroup group_hal_usb_dev_endpoint 
+  * \ingroup group_hal_usb_dev_endpoint
   */
 typedef uint8_t cyhal_usb_dev_ep_t;
 
-/** Callback handler for USB Device interrupt  */
+/**
+  * Callback handler for USB Device interrupt
+  */
 typedef void (*cyhal_usb_dev_irq_callback_t)(void);
 
-/** 
+/**
   * Callback handler for the transfer completion event for data endpoints (not applicable for endpoint 0)
-  * 
+  *
-  * \ingroup group_hal_usb_dev_endpoint 
+  * \ingroup group_hal_usb_dev_endpoint
   */
 typedef void (* cyhal_usb_dev_endpoint_callback_t)(cyhal_usb_dev_ep_t endpoint);
 
@@ -190,7 +211,9 @@ typedef void (*cyhal_usb_dev_sof_callback_t)(uint32_t frame_number);
  */
  void cyhal_usb_dev_set_address(cyhal_usb_dev_t *obj, uint8_t address);
 
-/** 
+/** \} group_hal_usb_dev_common */
+
+/**
   * \addtogroup group_hal_usb_dev_ep0 EP0
   * \{
   * APIs relating specifically to management of endpoint zero
@@ -257,7 +280,7 @@ uint32_t cyhal_usb_dev_ep0_get_max_packet(cyhal_usb_dev_t *obj);
 /** \} group_hal_usb_dev_ep0 */
 
 /**
-  * \addtogroup group_hal_usb_dev_endpoint 
+  * \addtogroup group_hal_usb_dev_endpoint
   * \{
   */
 
@@ -382,6 +405,11 @@ cy_rslt_t cyhal_usb_dev_endpoint_add(cyhal_usb_dev_t *obj, bool alloc, bool enab
 
 /** \} group_hal_usb_dev_endpoint */
 
+/**
+  * \addtogroup group_hal_usb_dev_common Common
+  * \{
+  */
+
  /** The USB Device callback handler registration
  *
  * @param[in,out] obj The usb device object
@@ -412,8 +440,8 @@ void cyhal_usb_dev_process_irq(cyhal_usb_dev_t *obj);
  * @param[in,out] obj  The usb device object
  * @param[in] endpoint Endpoint to registers handler
  * @param[in] callback  The callback handler which will be invoked when the endpoint comp
- * 
+ *
- * \ingroup group_hal_usb_dev_endpoint 
+ * \ingroup group_hal_usb_dev_endpoint
  */
 void cyhal_usb_dev_register_endpoint_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint, cyhal_usb_dev_endpoint_callback_t callback);
 
@@ -434,6 +462,8 @@ void cyhal_usb_dev_register_event_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_e
  */
 void cyhal_usb_dev_register_sof_callback( cyhal_usb_dev_t *obj, cyhal_usb_dev_sof_callback_t callback);
 
+/** \} group_hal_usb_dev_common */
+
 #if defined(__cplusplus)
 }
 #endif

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h

@@ -6,7 +6,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -22,13 +22,16 @@
 * limitations under the License.
 *******************************************************************************/
 
+/** \cond INTERNAL */
 /**
-* \addtogroup group_hal_psoc6 PSoC 6 Implementation 
+* \addtogroup group_hal_psoc6 PSoC 6 Implementation Specific
 * \{
+* Common utility macros & functions used by multiple HAL drivers.
 */
 
 #pragma once
 
+#include "cy_result.h"
 #include "cyhal_hw_types.h"
 #include "cy_utils.h"
 
@@ -37,16 +40,9 @@ extern "C" {
 #endif
 
 
-/** 
-  * \addtogroup group_hal_psoc6_interrupts Interrupts
-  * \{
-  */
 #define CYHAL_IRQN_OFFSET          16 /**< Offset for implementation-defined ISR type numbers (IRQ0 = 16) */
 #define CYHAL_GET_CURRENT_IRQN()   ((IRQn_Type) (__get_IPSR() - CYHAL_IRQN_OFFSET)) /**< Macro to get the IRQn of the current ISR */
 
-/** \} group_hal_psoc6_interrupts  */
-
-
 /**
 * \addtogroup group_hal_psoc6_pin_package
 * \{
@@ -84,21 +80,30 @@ static inline cyhal_resource_inst_t cyhal_utils_get_gpio_resource(cyhal_gpio_t p
  */
 const cyhal_resource_pin_mapping_t *cyhal_utils_get_resource(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t* mappings, size_t count);
 
+/** Attempts to reserve the specified pin and then initialize it to connect to the item defined by the provided mapping object.
+ * @param[in] pin        The pin to reserve and connect
+ * @param[in] mapping    The pin/hardware block connection mapping information
+ * @return CY_RSLT_SUCCESS if everything was ok, else an error.
+ */
+cy_rslt_t cyhal_utils_reserve_and_connect(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *mapping);
+
 /** Disconnects any routing for the pin from the interconnect driver and then free's the pin from the hwmgr.
  *
  * @param[in] pin       The pin to disconnect and free
  */
 void cyhal_utils_disconnect_and_free(cyhal_gpio_t pin);
 
+/** Checks to see if the provided pin is a no-connect (CYHAL_NC_PIN_VALUE). If not, calls
+ * cyhal_utils_disconnect_and_free().
+ *
+ * @param[in] pin       The pin to disconnect and free
+ */
+void cyhal_utils_release_if_used(cyhal_gpio_t *pin);
+
 /** \} group_hal_psoc6_pin_package */
 
-/**
-* \addtogroup group_hal_psoc6_clocks Clocks
-* \{
-*/
-
 /** Calculate the peri clock divider value that need to be set to reach frequency closest to the input frequency
- * 
+ *
  * @param[in] frequency The desired frequency
  * @param[in] frac_bits The number of fractional bits that the divider has
  * @return The calculate divider value to set, NOTE a divider value of x divide the frequency by (x+1)
@@ -108,7 +113,13 @@ static inline uint32_t cyhal_divider_value(uint32_t frequency, uint32_t frac_bit
     return ((Cy_SysClk_ClkPeriGetFrequency() * (1 << frac_bits)) + (frequency / 2)) / frequency - 1;
 }
 
-/** \} group_hal_psoc6_clocks */
+/** Determine if two resources are the same
+ *
+ * @param[in] resource1 First resource to compare
+ * @param[in] resource2 Second resource to compare
+ * @return Boolean indicating whether two resources are the same
+ */
+bool cyhal_utils_resources_equal(const cyhal_resource_inst_t *resource1, const cyhal_resource_inst_t *resource2);
 
 #if defined(__cplusplus)
 }
@@ -116,3 +127,4 @@ static inline uint32_t cyhal_divider_value(uint32_t frequency, uint32_t frac_bit
 
 /** \} group_hal_psoc6_utils */
 /** \} group_hal_psoc6 */
+/** \endcond */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt.h

@@ -29,7 +29,35 @@
 * \addtogroup group_hal_wdt WDT (Watchdog Timer)
 * \ingroup group_hal
 * \{
-* High level interface for interacting with the Cypress WDT.
+* High level interface to the Watchdog Timer (WDT).
+*
+* cyhal_wdt_init() initializes the WDT and passes a pointer to the WDT block through obj.
+* The timeout_ms parameter takes in the timeout in milliseconds.
+* It can be used for recovering from a CPU or firmware failure.
+  The watchdog timer is initialized with a timeout interval. Once the WDT is started,
+  if cyhal_wdt_kick() must be called at least once within the timeout interval. In case
+  the firmware fails to do so, it is considered to be a CPU crash or firmware failure and the device
+  will be reset.
+*
+*
+*\section subsection_wdt_features Features
+* WDT supports Device Reset generation if not serviced within the configured timeout interval.
+*
+*
+* \section subsection_wdt_quickstart Quick Start
+*
+* \ref cyhal_wdt_init() can be used for initialization by providing the WDT object (obj) and the timeout parameter
+* (timeout period in ms).
+* The timeout parameter can have a minimum value of 1ms. The maximum value of the timeout
+* parameter can be obtained using the cyhal_wdt_get_max_timeout_ms().
+*
+*
+* \section subsection_wdt_sample_use_case Sample use case
+*
+* \subsection subsection_wdt_use_case Use Case: Initialization and reset functionality
+* The following snippet initializes the WDT and depicts the reset functionality of WDT in case of CPU or
+* firmware failure.
+* \snippet wdt.c snippet_cyhal_wdt_init_and_reset
 */
 
 #pragma once
@@ -54,6 +82,8 @@ extern "C" {
 * @param[out] obj The WDT object
 * @param[in] timeout_ms The time in milliseconds before the WDT times out (1ms - max) (see cyhal_wdt_get_max_timeout_ms())
 * @return The status of the init request
+*
+* Returns \ref CY_RSLT_SUCCESS if the operation was successfull.
 */
 cy_rslt_t cyhal_wdt_init(cyhal_wdt_t *obj, uint32_t timeout_ms);
 
@@ -65,7 +95,9 @@ cy_rslt_t cyhal_wdt_init(cyhal_wdt_t *obj, uint32_t timeout_ms);
 * undefined.
 *
 * @param[inout] obj The WDT object
+*
 */
+
 void cyhal_wdt_free(cyhal_wdt_t *obj);
 
 /** Refresh the WDT
@@ -74,11 +106,13 @@ void cyhal_wdt_free(cyhal_wdt_t *obj);
 * In the event of a timeout, the WDT resets the system.
 *
 * @param[inout] obj The WDT object
+*
+* See \ref subsection_wdt_use_case
 */
 void cyhal_wdt_kick(cyhal_wdt_t *obj);
 
 /** Start the WDT
-* 
+*
 * Enables the WDT.
 *
 * @param[inout] obj The WDT object
@@ -87,7 +121,7 @@ void cyhal_wdt_kick(cyhal_wdt_t *obj);
 void cyhal_wdt_start(cyhal_wdt_t *obj);
 
 /** Stop the WDT
-* 
+*
 * Disables the WDT.
 *
 * @param[inout] obj The WDT object
@@ -98,13 +132,13 @@ void cyhal_wdt_stop(cyhal_wdt_t *obj);
 /** Get the WDT timeout
 *
 * Gets the time in milliseconds before the WDT times out.
-* 
+*
 * @param[inout] obj The WDT object
 * @return The time in milliseconds before the WDT times out
 */
 uint32_t cyhal_wdt_get_timeout_ms(cyhal_wdt_t *obj);
 
-/** Gets the maximum WDT timeout 
+/** Gets the maximum WDT timeout
 *
 * Gets the maximum timeout for the WDT.
 *

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble.h

@@ -5,11 +5,11 @@
 * PSoC6_01 device GPIO HAL header for 104-M-CSP-BLE package
 *
 * \note
-* Generator version: 1.4.7153.30079
+* Generator version: 1.5.7254.21430
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,97 +30,107 @@
 
 #include "cyhal_hw_resources.h"
 
+/**
+ * \addtogroup group_hal_psoc6_pin_package_psoc6_01_104_m_csp_ble PSoC6_01 104-M-CSP-BLE
+ * \ingroup group_hal_psoc6_pin_package
+ * \{
+ */
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
 
+/** Gets a pin definition from the provided port and pin numbers */
 #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
 
-/* Pin names */
+/** Definitions for all of the pins that are bonded out on in the 104-M-CSP-BLE package for the PSoC6_01 series. */
 typedef enum {
-    NC = (int)0xFFFFFFFF,
+    NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin
 
-    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
+    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
-    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
+    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
-    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
+    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2
-    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
+    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3
-    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
+    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4
-    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
+    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5
 
-    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
+    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0
-    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
+    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1
-    P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3),
+    P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3
-    P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),
+    P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4
-    P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),
+    P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5
 
-    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
+    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0
-    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
+    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1
-    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
+    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2
-    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
+    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3
-    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
+    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4
-    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
+    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5
-    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
+    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6
-    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
+    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7
 
-    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
+    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0
-    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
+    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1
-    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
+    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2
-    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
+    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3
-    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
+    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4
-    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
+    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
-    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
+    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6
-    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
+    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7
 
-    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
+    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0
-    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
+    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
-    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
+    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2
-    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
+    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3
-    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
+    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4
-    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
+    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5
-    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
+    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6
-    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
+    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7
 
-    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
+    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0
-    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
+    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1
-    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
+    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2
-    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
+    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3
-    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
+    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4
-    P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5),
+    P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5
-    P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6),
+    P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6
-    P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7),
+    P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7
 
-    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
+    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0
-    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
+    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1
-    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
+    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2
-    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
+    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3
 
-    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
+    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0
-    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
+    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1
-    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
+    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2
-    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
+    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3
-    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
+    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4
-    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
+    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5
-    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
+    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6
-    P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7),
+    P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7
 
-    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
+    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0
-    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
+    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1
-    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
+    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2
-    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
+    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3
-    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
+    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4
-    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
+    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5
-    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
+    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6
-    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
+    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7
 
-    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
+    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0
-    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
+    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1
-    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
+    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2
-    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
+    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3
-    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
+    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4
 
-    P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0),
+    P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0
-    P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1),
+    P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1
-} cyhal_gpio_t;
+} cyhal_gpio_psoc6_01_104_m_csp_ble_t;
+
+/** Create generic name for the series/package specific type. */
+typedef cyhal_gpio_psoc6_01_104_m_csp_ble_t cyhal_gpio_t;
 
 /* Connection type definition */
 /** Represents an association between a pin and a resource */
@@ -132,90 +142,171 @@ typedef struct
 } cyhal_resource_pin_mapping_t;
 
 /* Pin connections */
+/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1];
+/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
+/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1];
+/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1];
+/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1];
+/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1];
+/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1];
+/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1];
+/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
+/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1];
+/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1];
+/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4];
+/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1];
+/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1];
+/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1];
+/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
+/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14];
+/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[12];
+/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[13];
+/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9];
+/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8];
+/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[6];
+/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[12];
+/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14];
+/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14];
+/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[13];
+/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9];
+/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8];
+/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[6];
+/** List of valid pin to peripheral connections for the scb_uart_cts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[11];
+/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[10];
+/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12];
+/** List of valid pin to peripheral connections for the scb_uart_tx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12];
+/** List of valid pin to peripheral connections for the smif_spi_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
+/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
+/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
+/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
+/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
+/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
+/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
+/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
+/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
+/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
+/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
+/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
+/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
+/** List of valid pin to peripheral connections for the tcpwm_line signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[68];
+/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[68];
+/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
+/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
+/** \} group_hal_psoc6 */
+
 #endif /* _CYHAL_PSOC6_01_104_M_CSP_BLE_H_ */
 
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h

@@ -5,11 +5,11 @@
 * PSoC6_01 device GPIO HAL header for 104-M-CSP-BLE-USB package
 *
 * \note
-* Generator version: 1.4.7153.30079
+* Generator version: 1.5.7254.21430
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,99 +30,109 @@
 
 #include "cyhal_hw_resources.h"
 
+/**
+ * \addtogroup group_hal_psoc6_pin_package_psoc6_01_104_m_csp_ble_usb PSoC6_01 104-M-CSP-BLE-USB
+ * \ingroup group_hal_psoc6_pin_package
+ * \{
+ */
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
 
+/** Gets a pin definition from the provided port and pin numbers */
 #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
 
-/* Pin names */
+/** Definitions for all of the pins that are bonded out on in the 104-M-CSP-BLE-USB package for the PSoC6_01 series. */
 typedef enum {
-    NC = (int)0xFFFFFFFF,
+    NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin
 
-    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
+    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
-    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
+    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
-    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
+    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2
-    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
+    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3
-    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
+    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4
-    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
+    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5
 
-    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
+    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0
-    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
+    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1
-    P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),
+    P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4
-    P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),
+    P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5
 
-    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
+    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0
-    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
+    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1
-    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
+    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2
-    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
+    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3
-    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
+    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4
-    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
+    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5
-    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
+    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6
-    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
+    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7
 
-    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
+    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0
-    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
+    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1
-    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
+    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2
-    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
+    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3
-    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
+    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4
-    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
+    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
-    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
+    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6
-    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
+    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7
 
-    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
+    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0
-    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
+    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
-    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
+    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2
-    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
+    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3
-    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
+    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4
-    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
+    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5
-    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
+    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6
-    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
+    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7
 
-    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
+    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0
-    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
+    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1
-    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
+    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2
-    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
+    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3
-    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
+    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4
-    P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5),
+    P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5
-    P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6),
+    P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6
-    P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7),
+    P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7
 
-    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
+    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0
-    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
+    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1
-    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
+    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2
-    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
+    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3
 
-    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
+    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0
-    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
+    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1
-    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
+    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2
-    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
+    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3
-    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
+    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4
-    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
+    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5
-    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
+    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6
-    P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7),
+    P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7
 
-    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
+    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0
-    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
+    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1
-    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
+    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2
-    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
+    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3
-    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
+    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4
-    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
+    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5
-    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
+    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6
-    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
+    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7
 
-    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
+    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0
-    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
+    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1
-    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
+    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2
-    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
+    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3
-    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
+    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4
 
-    P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0),
+    P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0
-    P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1),
+    P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1
 
-    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
+    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0
-    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
+    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1
-} cyhal_gpio_t;
+} cyhal_gpio_psoc6_01_104_m_csp_ble_usb_t;
+
+/** Create generic name for the series/package specific type. */
+typedef cyhal_gpio_psoc6_01_104_m_csp_ble_usb_t cyhal_gpio_t;
 
 /* Connection type definition */
 /** Represents an association between a pin and a resource */
@@ -134,90 +144,171 @@ typedef struct
 } cyhal_resource_pin_mapping_t;
 
 /* Pin connections */
+/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1];
+/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
+/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1];
+/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1];
+/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1];
+/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1];
+/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1];
+/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1];
+/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
+/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1];
+/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1];
+/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4];
+/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1];
+/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1];
+/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1];
+/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
+/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14];
+/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[12];
+/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[12];
+/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9];
+/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8];
+/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[6];
+/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[12];
+/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14];
+/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14];
+/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[12];
+/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9];
+/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8];
+/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[6];
+/** List of valid pin to peripheral connections for the scb_uart_cts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10];
+/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[10];
+/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12];
+/** List of valid pin to peripheral connections for the scb_uart_tx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12];
+/** List of valid pin to peripheral connections for the smif_spi_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
+/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
+/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
+/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
+/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
+/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
+/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
+/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
+/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
+/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
+/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
+/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
+/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
+/** List of valid pin to peripheral connections for the tcpwm_line signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[68];
+/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[66];
+/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
+/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
+/** \} group_hal_psoc6 */
+
 #endif /* _CYHAL_PSOC6_01_104_M_CSP_BLE_USB_H_ */
 
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_ble.h

@@ -5,11 +5,11 @@
 * PSoC6_01 device GPIO HAL header for 116-BGA-BLE package
 *
 * \note
-* Generator version: 1.4.7153.30079
+* Generator version: 1.5.7254.21430
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,105 +30,115 @@
 
 #include "cyhal_hw_resources.h"
 
+/**
+ * \addtogroup group_hal_psoc6_pin_package_psoc6_01_116_bga_ble PSoC6_01 116-BGA-BLE
+ * \ingroup group_hal_psoc6_pin_package
+ * \{
+ */
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
 
+/** Gets a pin definition from the provided port and pin numbers */
 #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
 
-/* Pin names */
+/** Definitions for all of the pins that are bonded out on in the 116-BGA-BLE package for the PSoC6_01 series. */
 typedef enum {
-    NC = (int)0xFFFFFFFF,
+    NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin
 
-    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
+    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
-    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
+    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
-    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
+    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2
-    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
+    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3
-    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
+    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4
-    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
+    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5
 
-    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
+    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0
-    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
+    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1
-    P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2),
+    P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2
-    P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3),
+    P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3
-    P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),
+    P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4
-    P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),
+    P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5
 
-    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
+    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0
-    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
+    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1
-    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
+    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2
-    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
+    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3
-    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
+    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4
-    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
+    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5
-    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
+    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6
 
-    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
+    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0
-    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
+    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1
-    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
+    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2
-    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
+    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3
-    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
+    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4
-    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
+    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
-    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
+    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6
-    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
+    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7
 
-    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
+    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0
-    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
+    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
-    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
+    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2
-    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
+    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3
-    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
+    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4
-    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
+    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5
-    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
+    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6
-    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
+    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7
 
-    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
+    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0
-    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
+    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1
-    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
+    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2
-    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
+    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3
-    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
+    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4
-    P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5),
+    P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5
-    P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6),
+    P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6
-    P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7),
+    P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7
 
-    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
+    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0
-    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
+    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1
-    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
+    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2
-    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
+    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3
-    P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4),
+    P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4
-    P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5),
+    P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5
-    P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6),
+    P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6
-    P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7),
+    P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7
 
-    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
+    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0
-    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
+    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1
-    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
+    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2
-    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
+    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3
-    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
+    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4
-    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
+    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5
-    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
+    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6
 
-    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
+    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0
-    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
+    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1
-    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
+    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2
-    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
+    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3
-    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
+    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4
-    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
+    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5
-    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
+    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6
-    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
+    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7
 
-    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
+    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0
-    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
+    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1
-    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
+    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2
-    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
+    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3
-    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
+    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4
-    P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5),
+    P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5
-    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
+    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6
-    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
+    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7
 
-    P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0),
+    P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0
-    P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1),
+    P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1
-    P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6),
+    P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6
-    P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7),
+    P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7
-} cyhal_gpio_t;
+} cyhal_gpio_psoc6_01_116_bga_ble_t;
+
+/** Create generic name for the series/package specific type. */
+typedef cyhal_gpio_psoc6_01_116_bga_ble_t cyhal_gpio_t;
 
 /* Connection type definition */
 /** Represents an association between a pin and a resource */
@@ -140,90 +150,171 @@ typedef struct
 } cyhal_resource_pin_mapping_t;
 
 /* Pin connections */
+/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1];
+/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
+/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2];
+/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1];
+/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1];
+/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1];
+/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1];
+/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1];
+/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
+/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1];
+/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1];
+/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8];
+/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1];
+/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1];
+/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1];
+/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7];
+/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14];
+/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[13];
+/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[13];
+/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[10];
+/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[10];
+/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[8];
+/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[13];
+/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14];
+/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14];
+/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[13];
+/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[10];
+/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[10];
+/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[8];
+/** List of valid pin to peripheral connections for the scb_uart_cts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[11];
+/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[11];
+/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12];
+/** List of valid pin to peripheral connections for the scb_uart_tx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12];
+/** List of valid pin to peripheral connections for the smif_spi_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
+/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
+/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
+/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
+/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
+/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
+/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
+/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
+/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
+/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
+/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
+/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
+/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
+/** List of valid pin to peripheral connections for the tcpwm_line signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[78];
+/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[74];
+/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
+/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
+/** \} group_hal_psoc6 */
+
 #endif /* _CYHAL_PSOC6_01_116_BGA_BLE_H_ */
 
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_usb.h

@@ -5,11 +5,11 @@
 * PSoC6_01 device GPIO HAL header for 116-BGA-USB package
 *
 * \note
-* Generator version: 1.4.7153.30079
+* Generator version: 1.5.7254.21430
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,105 +30,115 @@
 
 #include "cyhal_hw_resources.h"
 
+/**
+ * \addtogroup group_hal_psoc6_pin_package_psoc6_01_116_bga_usb PSoC6_01 116-BGA-USB
+ * \ingroup group_hal_psoc6_pin_package
+ * \{
+ */
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
 
+/** Gets a pin definition from the provided port and pin numbers */
 #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
 
-/* Pin names */
+/** Definitions for all of the pins that are bonded out on in the 116-BGA-USB package for the PSoC6_01 series. */
 typedef enum {
-    NC = (int)0xFFFFFFFF,
+    NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin
 
-    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
+    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
-    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
+    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
-    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
+    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2
-    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
+    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3
-    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
+    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4
-    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
+    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5
 
-    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
+    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0
-    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
+    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1
-    P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2),
+    P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2
 
-    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
+    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0
-    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
+    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1
-    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
+    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2
-    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
+    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3
-    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
+    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4
-    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
+    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5
-    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
+    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6
 
-    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
+    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0
-    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
+    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1
-    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
+    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2
-    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
+    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3
-    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
+    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4
-    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
+    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
-    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
+    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6
-    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
+    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7
 
-    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
+    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0
-    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
+    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
-    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
+    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2
-    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
+    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3
-    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
+    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4
-    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
+    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5
-    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
+    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6
-    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
+    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7
 
-    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
+    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0
-    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
+    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1
-    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
+    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2
-    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
+    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3
-    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
+    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4
-    P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5),
+    P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5
-    P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6),
+    P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6
-    P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7),
+    P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7
 
-    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
+    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0
-    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
+    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1
-    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
+    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2
-    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
+    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3
-    P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4),
+    P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4
-    P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5),
+    P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5
-    P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6),
+    P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6
-    P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7),
+    P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7
 
-    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
+    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0
-    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
+    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1
-    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
+    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2
-    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
+    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3
-    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
+    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4
-    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
+    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5
-    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
+    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6
 
-    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
+    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0
-    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
+    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1
-    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
+    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2
-    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
+    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3
-    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
+    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4
-    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
+    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5
-    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
+    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6
-    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
+    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7
 
-    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
+    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0
-    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
+    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1
-    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
+    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2
-    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
+    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3
-    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
+    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4
-    P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5),
+    P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5
-    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
+    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6
-    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
+    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7
 
-    P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0),
+    P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0
-    P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1),
+    P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1
-    P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6),
+    P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6
-    P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7),
+    P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7
 
-    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
+    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0
-    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
+    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1
-} cyhal_gpio_t;
+} cyhal_gpio_psoc6_01_116_bga_usb_t;
+
+/** Create generic name for the series/package specific type. */
+typedef cyhal_gpio_psoc6_01_116_bga_usb_t cyhal_gpio_t;
 
 /* Connection type definition */
 /** Represents an association between a pin and a resource */
@@ -140,90 +150,171 @@ typedef struct
 } cyhal_resource_pin_mapping_t;
 
 /* Pin connections */
+/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1];
+/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
+/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2];
+/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1];
+/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1];
+/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1];
+/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1];
+/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1];
+/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
+/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1];
+/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1];
+/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8];
+/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1];
+/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1];
+/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1];
+/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7];
+/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14];
+/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[13];
+/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[12];
+/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9];
+/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[9];
+/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[8];
+/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[13];
+/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14];
+/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14];
+/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[12];
+/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9];
+/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[9];
+/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[8];
+/** List of valid pin to peripheral connections for the scb_uart_cts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10];
+/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[11];
+/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12];
+/** List of valid pin to peripheral connections for the scb_uart_tx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12];
+/** List of valid pin to peripheral connections for the smif_spi_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
+/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
+/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
+/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
+/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
+/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
+/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
+/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
+/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
+/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
+/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
+/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
+/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
+/** List of valid pin to peripheral connections for the tcpwm_line signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[76];
+/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[70];
+/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
+/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
+/** \} group_hal_psoc6 */
+
 #endif /* _CYHAL_PSOC6_01_116_BGA_USB_H_ */
 
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga.h

@@ -5,11 +5,11 @@
 * PSoC6_01 device GPIO HAL header for 124-BGA package
 *
 * \note
-* Generator version: 1.4.7153.30079
+* Generator version: 1.5.7254.21430
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,133 +30,143 @@
 
 #include "cyhal_hw_resources.h"
 
+/**
+ * \addtogroup group_hal_psoc6_pin_package_psoc6_01_124_bga PSoC6_01 124-BGA
+ * \ingroup group_hal_psoc6_pin_package
+ * \{
+ */
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
 
+/** Gets a pin definition from the provided port and pin numbers */
 #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
 
-/* Pin names */
+/** Definitions for all of the pins that are bonded out on in the 124-BGA package for the PSoC6_01 series. */
 typedef enum {
-    NC = (int)0xFFFFFFFF,
+    NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin
 
-    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
+    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
-    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
+    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
-    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
+    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2
-    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
+    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3
-    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
+    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4
-    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
+    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5
 
-    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
+    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0
-    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
+    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1
-    P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2),
+    P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2
-    P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3),
+    P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3
-    P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),
+    P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4
-    P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),
+    P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5
 
-    P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0),
+    P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0
-    P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1),
+    P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1
-    P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2),
+    P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2
-    P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3),
+    P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3
-    P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4),
+    P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4
-    P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5),
+    P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5
-    P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6),
+    P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6
-    P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7),
+    P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7
 
-    P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0),
+    P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0
-    P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1),
+    P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1
-    P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2),
+    P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2
-    P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3),
+    P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3
-    P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4),
+    P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4
-    P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5),
+    P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), //!< Port 3 Pin 5
 
-    P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0),
+    P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0
-    P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1),
+    P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1
 
-    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
+    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0
-    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
+    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1
-    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
+    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2
-    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
+    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3
-    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
+    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4
-    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
+    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5
-    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
+    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6
-    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
+    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7
 
-    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
+    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0
-    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
+    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1
-    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
+    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2
-    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
+    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3
-    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
+    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4
-    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
+    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
-    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
+    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6
-    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
+    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7
 
-    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
+    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0
-    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
+    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
-    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
+    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2
-    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
+    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3
-    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
+    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4
-    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
+    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5
-    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
+    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6
-    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
+    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7
 
-    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
+    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0
-    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
+    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1
-    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
+    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2
-    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
+    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3
-    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
+    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4
-    P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5),
+    P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5
-    P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6),
+    P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6
-    P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7),
+    P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7
 
-    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
+    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0
-    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
+    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1
-    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
+    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2
-    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
+    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3
-    P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4),
+    P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4
-    P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5),
+    P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5
-    P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6),
+    P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6
-    P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7),
+    P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7
 
-    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
+    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0
-    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
+    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1
-    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
+    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2
-    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
+    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3
-    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
+    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4
-    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
+    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5
-    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
+    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6
-    P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7),
+    P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7
 
-    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
+    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0
-    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
+    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1
-    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
+    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2
-    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
+    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3
-    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
+    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4
-    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
+    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5
-    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
+    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6
-    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
+    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7
 
-    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
+    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0
-    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
+    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1
-    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
+    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2
-    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
+    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3
-    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
+    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4
-    P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5),
+    P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5
-    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
+    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6
-    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
+    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7
 
-    P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0),
+    P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0
-    P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1),
+    P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1
-    P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2),
+    P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2
-    P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3),
+    P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3
-    P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4),
+    P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4
-    P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5),
+    P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5
-    P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6),
+    P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6
-    P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7),
+    P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7
 
-    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
+    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0
-    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
+    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1
-} cyhal_gpio_t;
+} cyhal_gpio_psoc6_01_124_bga_t;
+
+/** Create generic name for the series/package specific type. */
+typedef cyhal_gpio_psoc6_01_124_bga_t cyhal_gpio_t;
 
 /* Connection type definition */
 /** Represents an association between a pin and a resource */
@@ -168,90 +178,171 @@ typedef struct
 } cyhal_resource_pin_mapping_t;
 
 /* Pin connections */
+/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1];
+/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
+/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2];
+/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1];
+/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1];
+/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1];
+/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1];
+/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1];
+/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
+/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1];
+/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1];
+/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8];
+/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1];
+/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1];
+/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1];
+/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
+/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[17];
+/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[17];
+/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[16];
+/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[17];
+/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[17];
+/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[16];
+/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[13];
+/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[13];
+/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[10];
+/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[16];
+/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[17];
+/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[17];
+/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[16];
+/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[13];
+/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[13];
+/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[10];
+/** List of valid pin to peripheral connections for the scb_uart_cts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[14];
+/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[14];
+/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[15];
+/** List of valid pin to peripheral connections for the scb_uart_tx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[15];
+/** List of valid pin to peripheral connections for the smif_spi_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
+/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
+/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
+/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
+/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
+/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
+/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
+/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
+/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
+/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
+/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
+/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
+/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
+/** List of valid pin to peripheral connections for the tcpwm_line signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[98];
+/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[98];
+/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
+/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
+/** \} group_hal_psoc6 */
+
 #endif /* _CYHAL_PSOC6_01_124_BGA_H_ */
 
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga_sip.h

@@ -5,11 +5,11 @@
 * PSoC6_01 device GPIO HAL header for 124-BGA-SIP package
 *
 * \note
-* Generator version: 1.4.7153.30079
+* Generator version: 1.5.7254.21430
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,114 +30,124 @@
 
 #include "cyhal_hw_resources.h"
 
+/**
+ * \addtogroup group_hal_psoc6_pin_package_psoc6_01_124_bga_sip PSoC6_01 124-BGA-SIP
+ * \ingroup group_hal_psoc6_pin_package
+ * \{
+ */
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
 
+/** Gets a pin definition from the provided port and pin numbers */
 #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
 
-/* Pin names */
+/** Definitions for all of the pins that are bonded out on in the 124-BGA-SIP package for the PSoC6_01 series. */
 typedef enum {
-    NC = (int)0xFFFFFFFF,
+    NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin
 
-    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
+    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
-    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
+    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
-    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
+    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2
-    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
+    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3
-    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
+    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4
-    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
+    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5
 
-    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
+    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0
-    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
+    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1
-    P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2),
+    P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2
-    P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3),
+    P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3
-    P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),
+    P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4
-    P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),
+    P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5
 
-    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
+    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0
-    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
+    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1
-    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
+    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2
-    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
+    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3
-    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
+    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4
-    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
+    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5
-    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
+    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6
-    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
+    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7
 
-    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
+    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0
-    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
+    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1
-    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
+    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2
-    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
+    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3
-    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
+    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4
-    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
+    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
-    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
+    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6
-    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
+    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7
 
-    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
+    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0
-    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
+    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
-    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
+    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2
-    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
+    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3
-    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
+    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4
-    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
+    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5
-    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
+    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6
-    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
+    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7
 
-    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
+    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0
-    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
+    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1
-    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
+    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2
-    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
+    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3
-    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
+    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4
-    P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5),
+    P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5
-    P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6),
+    P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6
-    P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7),
+    P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7
 
-    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
+    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0
-    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
+    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1
-    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
+    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2
-    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
+    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3
-    P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4),
+    P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4
-    P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5),
+    P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5
-    P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6),
+    P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6
-    P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7),
+    P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7
 
-    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
+    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0
-    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
+    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1
-    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
+    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2
-    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
+    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3
-    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
+    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4
-    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
+    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5
-    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
+    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6
-    P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7),
+    P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7
 
-    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
+    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0
-    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
+    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1
-    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
+    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2
-    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
+    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3
-    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
+    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4
-    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
+    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5
-    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
+    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6
-    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
+    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7
 
-    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
+    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0
-    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
+    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1
-    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
+    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2
-    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
+    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3
-    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
+    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4
-    P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5),
+    P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5
-    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
+    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6
-    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
+    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7
 
-    P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0),
+    P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0
-    P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1),
+    P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1
-    P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2),
+    P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2
-    P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3),
+    P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3
-    P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4),
+    P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4
-    P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5),
+    P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5
-    P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6),
+    P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6
-    P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7),
+    P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7
 
-    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
+    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0
-    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
+    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1
-} cyhal_gpio_t;
+} cyhal_gpio_psoc6_01_124_bga_sip_t;
+
+/** Create generic name for the series/package specific type. */
+typedef cyhal_gpio_psoc6_01_124_bga_sip_t cyhal_gpio_t;
 
 /* Connection type definition */
 /** Represents an association between a pin and a resource */
@@ -149,90 +159,171 @@ typedef struct
 } cyhal_resource_pin_mapping_t;
 
 /* Pin connections */
+/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1];
+/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
+/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2];
+/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1];
+/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1];
+/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1];
+/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1];
+/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1];
+/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
+/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1];
+/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1];
+/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8];
+/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1];
+/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1];
+/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1];
+/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
+/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14];
+/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[11];
+/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[11];
+/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[9];
+/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[14];
+/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14];
+/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14];
+/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[14];
+/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[11];
+/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[11];
+/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[9];
+/** List of valid pin to peripheral connections for the scb_uart_cts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[12];
+/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[12];
+/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12];
+/** List of valid pin to peripheral connections for the scb_uart_tx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12];
+/** List of valid pin to peripheral connections for the smif_spi_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
+/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
+/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
+/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
+/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
+/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
+/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
+/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
+/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
+/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
+/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
+/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
+/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
+/** List of valid pin to peripheral connections for the tcpwm_line signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[82];
+/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[82];
+/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
+/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
+/** \} group_hal_psoc6 */
+
 #endif /* _CYHAL_PSOC6_01_124_BGA_SIP_H_ */
 
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_43_smt.h

@@ -5,11 +5,11 @@
 * PSoC6_01 device GPIO HAL header for 43-SMT package
 *
 * \note
-* Generator version: 1.4.7153.30079
+* Generator version: 1.5.7254.21430
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,59 +30,69 @@
 
 #include "cyhal_hw_resources.h"
 
+/**
+ * \addtogroup group_hal_psoc6_pin_package_psoc6_01_43_smt PSoC6_01 43-SMT
+ * \ingroup group_hal_psoc6_pin_package
+ * \{
+ */
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
 
+/** Gets a pin definition from the provided port and pin numbers */
 #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
 
-/* Pin names */
+/** Definitions for all of the pins that are bonded out on in the 43-SMT package for the PSoC6_01 series. */
 typedef enum {
-    NC = (int)0xFFFFFFFF,
+    NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin
 
-    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
+    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
-    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
+    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
-    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
+    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4
-    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
+    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5
 
-    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
+    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0
-    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
+    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1
-    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
+    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2
-    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
+    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3
-    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
+    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4
-    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
+    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5
-    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
+    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6
 
-    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
+    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2
-    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
+    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3
-    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
+    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4
-    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
+    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
-    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
+    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6
-    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
+    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7
 
-    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
+    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
-    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
+    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2
-    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
+    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7
 
-    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
+    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0
-    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
+    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1
-    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
+    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2
-    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
+    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3
-    P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4),
+    P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4
-    P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5),
+    P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5
-    P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6),
+    P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6
 
-    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
+    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0
-    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
+    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1
-    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
+    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2
-    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
+    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3
-    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
+    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4
-    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
+    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5
-    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
+    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6
 
-    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
+    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6
-    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
+    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7
-} cyhal_gpio_t;
+} cyhal_gpio_psoc6_01_43_smt_t;
+
+/** Create generic name for the series/package specific type. */
+typedef cyhal_gpio_psoc6_01_43_smt_t cyhal_gpio_t;
 
 /* Connection type definition */
 /** Represents an association between a pin and a resource */
@@ -94,90 +104,171 @@ typedef struct
 } cyhal_resource_pin_mapping_t;
 
 /* Pin connections */
+/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1];
+/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[1];
+/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1];
+/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1];
+/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1];
+/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1];
+/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1];
+/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1];
+/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
+/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1];
+/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1];
+/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[7];
+/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1];
+/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1];
+/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1];
+/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7];
+/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[5];
+/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[6];
+/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9];
+/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[6];
+/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[5];
+/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[8];
+/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5];
+/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4];
+/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4];
+/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9];
+/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[6];
+/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[5];
+/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[8];
+/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5];
+/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4];
+/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4];
+/** List of valid pin to peripheral connections for the scb_uart_cts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6];
+/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[7];
+/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[4];
+/** List of valid pin to peripheral connections for the scb_uart_tx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[5];
+/** List of valid pin to peripheral connections for the smif_spi_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
+/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
+/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
+/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
+/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
+/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
+/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
+/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
+/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
+/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
+/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
+/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
+/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
+/** List of valid pin to peripheral connections for the tcpwm_line signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[38];
+/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[34];
+/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
+/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
+/** \} group_hal_psoc6 */
+
 #endif /* _CYHAL_PSOC6_01_43_SMT_H_ */
 
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_68_qfn_ble.h

@@ -5,11 +5,11 @@
 * PSoC6_01 device GPIO HAL header for 68-QFN-BLE package
 *
 * \note
-* Generator version: 1.4.7153.30079
+* Generator version: 1.5.7254.21430
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,65 +30,75 @@
 
 #include "cyhal_hw_resources.h"
 
+/**
+ * \addtogroup group_hal_psoc6_pin_package_psoc6_01_68_qfn_ble PSoC6_01 68-QFN-BLE
+ * \ingroup group_hal_psoc6_pin_package
+ * \{
+ */
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
 
+/** Gets a pin definition from the provided port and pin numbers */
 #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
 
-/* Pin names */
+/** Definitions for all of the pins that are bonded out on in the 68-QFN-BLE package for the PSoC6_01 series. */
 typedef enum {
-    NC = (int)0xFFFFFFFF,
+    NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin
 
-    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
+    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
-    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
+    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
-    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
+    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2
-    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
+    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3
-    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
+    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4
-    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
+    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5
 
-    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
+    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0
-    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
+    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1
-    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
+    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2
-    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
+    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3
-    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
+    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4
-    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
+    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
-    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
+    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6
-    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
+    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7
 
-    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
+    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0
-    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
+    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
-    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
+    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2
-    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
+    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3
-    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
+    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4
-    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
+    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5
-    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
+    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6
-    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
+    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7
 
-    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
+    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0
-    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
+    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1
-    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
+    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2
 
-    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
+    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0
-    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
+    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1
-    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
+    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2
-    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
+    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3
 
-    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
+    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0
-    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
+    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1
 
-    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
+    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0
-    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
+    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1
-    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
+    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2
-    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
+    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3
-    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
+    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4
-    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
+    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5
-    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
+    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6
-    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
+    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7
 
-    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
+    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6
-    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
+    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7
-} cyhal_gpio_t;
+} cyhal_gpio_psoc6_01_68_qfn_ble_t;
+
+/** Create generic name for the series/package specific type. */
+typedef cyhal_gpio_psoc6_01_68_qfn_ble_t cyhal_gpio_t;
 
 /* Connection type definition */
 /** Represents an association between a pin and a resource */
@@ -100,90 +110,171 @@ typedef struct
 } cyhal_resource_pin_mapping_t;
 
 /* Pin connections */
+/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1];
+/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[1];
+/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1];
+/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1];
+/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1];
+/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1];
+/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1];
+/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1];
+/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
+/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1];
+/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1];
+/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4];
+/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1];
+/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1];
+/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1];
+/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[2];
+/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[10];
+/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[10];
+/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9];
+/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[10];
+/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[10];
+/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[8];
+/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[4];
+/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[3];
+/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[3];
+/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9];
+/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[10];
+/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[10];
+/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[8];
+/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[4];
+/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[3];
+/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[3];
+/** List of valid pin to peripheral connections for the scb_uart_cts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6];
+/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[7];
+/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[8];
+/** List of valid pin to peripheral connections for the scb_uart_tx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[8];
+/** List of valid pin to peripheral connections for the smif_spi_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
+/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
+/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
+/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
+/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
+/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
+/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
+/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
+/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
+/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
+/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
+/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
+/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
+/** List of valid pin to peripheral connections for the tcpwm_line signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[40];
+/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[38];
+/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
+/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
+/** \} group_hal_psoc6 */
+
 #endif /* _CYHAL_PSOC6_01_68_QFN_BLE_H_ */
 
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_80_wlcsp.h

@@ -5,11 +5,11 @@
 * PSoC6_01 device GPIO HAL header for 80-WLCSP package
 *
 * \note
-* Generator version: 1.4.7153.30079
+* Generator version: 1.5.7254.21430
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,91 +30,101 @@
 
 #include "cyhal_hw_resources.h"
 
+/**
+ * \addtogroup group_hal_psoc6_pin_package_psoc6_01_80_wlcsp PSoC6_01 80-WLCSP
+ * \ingroup group_hal_psoc6_pin_package
+ * \{
+ */
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
 
+/** Gets a pin definition from the provided port and pin numbers */
 #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
 
-/* Pin names */
+/** Definitions for all of the pins that are bonded out on in the 80-WLCSP package for the PSoC6_01 series. */
 typedef enum {
-    NC = (int)0xFFFFFFFF,
+    NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin
 
-    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
+    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
-    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
+    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
-    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
+    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2
-    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
+    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3
-    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
+    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4
-    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
+    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5
 
-    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
+    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0
-    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
+    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1
-    P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),
+    P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4
-    P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),
+    P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5
 
-    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
+    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0
-    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
+    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1
-    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
+    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2
-    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
+    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3
-    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
+    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4
-    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
+    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5
-    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
+    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6
-    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
+    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7
 
-    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
+    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0
-    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
+    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1
-    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
+    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2
-    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
+    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3
-    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
+    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4
-    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
+    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
-    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
+    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6
-    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
+    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7
 
-    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
+    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0
-    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
+    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
-    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
+    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2
-    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
+    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3
-    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
+    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7
 
-    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
+    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0
-    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
+    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1
-    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
+    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2
-    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
+    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3
-    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
+    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4
 
-    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
+    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0
-    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
+    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1
-    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
+    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2
-    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
+    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3
-    P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4),
+    P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4
-    P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7),
+    P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7
 
-    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
+    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0
-    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
+    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1
-    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
+    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4
-    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
+    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5
 
-    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
+    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0
-    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
+    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1
-    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
+    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2
-    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
+    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3
-    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
+    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4
-    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
+    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5
-    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
+    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6
-    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
+    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7
 
-    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
+    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0
-    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
+    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1
-    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
+    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2
-    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
+    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3
-    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
+    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4
-    P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5),
+    P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5
-    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
+    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6
-    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
+    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7
 
-    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
+    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0
-    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
+    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1
-} cyhal_gpio_t;
+} cyhal_gpio_psoc6_01_80_wlcsp_t;
+
+/** Create generic name for the series/package specific type. */
+typedef cyhal_gpio_psoc6_01_80_wlcsp_t cyhal_gpio_t;
 
 /* Connection type definition */
 /** Represents an association between a pin and a resource */
@@ -126,90 +136,171 @@ typedef struct
 } cyhal_resource_pin_mapping_t;
 
 /* Pin connections */
+/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1];
+/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
+/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2];
+/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1];
+/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1];
+/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1];
+/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1];
+/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1];
+/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1];
+/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
+/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1];
+/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1];
+/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[6];
+/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1];
+/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1];
+/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1];
+/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[4];
+/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[13];
+/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[13];
+/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[11];
+/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[13];
+/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[13];
+/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[11];
+/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9];
+/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[6];
+/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4];
+/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[11];
+/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[13];
+/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[13];
+/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[11];
+/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9];
+/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[6];
+/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4];
+/** List of valid pin to peripheral connections for the scb_uart_cts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[9];
+/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[9];
+/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[11];
+/** List of valid pin to peripheral connections for the scb_uart_tx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[11];
+/** List of valid pin to peripheral connections for the smif_spi_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
+/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
+/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
+/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
+/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
+/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
+/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
+/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
+/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
+/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
+/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
+/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
+/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
+/** List of valid pin to peripheral connections for the tcpwm_line signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[60];
+/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[60];
+/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
+/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
+/** \} group_hal_psoc6 */
+
 #endif /* _CYHAL_PSOC6_01_80_WLCSP_H_ */
 
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_100_wlcsp.h

@@ -5,11 +5,11 @@
 * PSoC6_02 device GPIO HAL header for 100-WLCSP package
 *
 * \note
-* Generator version: 1.4.7153.30079
+* Generator version: 1.5.7254.21305
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,113 +30,123 @@
 
 #include "cyhal_hw_resources.h"
 
+/**
+ * \addtogroup group_hal_psoc6_pin_package_psoc6_02_100_wlcsp PSoC6_02 100-WLCSP
+ * \ingroup group_hal_psoc6_pin_package
+ * \{
+ */
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
 
+/** Gets a pin definition from the provided port and pin numbers */
 #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
 
-/* Pin names */
+/** Definitions for all of the pins that are bonded out on in the 100-WLCSP package for the PSoC6_02 series. */
 typedef enum {
-    NC = (int)0xFFFFFFFF,
+    NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin
 
-    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
+    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
-    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
+    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
-    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
+    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2
-    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
+    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3
-    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
+    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4
-    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
+    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5
 
-    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
+    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0
-    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
+    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1
-    P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),
+    P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4
-    P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),
+    P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5
 
-    P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0),
+    P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0
-    P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1),
+    P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1
-    P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2),
+    P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2
-    P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3),
+    P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3
-    P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4),
+    P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4
-    P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5),
+    P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5
-    P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6),
+    P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6
-    P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7),
+    P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7
 
-    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
+    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0
-    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
+    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1
-    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
+    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2
-    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
+    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3
-    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
+    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4
-    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
+    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5
-    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
+    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6
-    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
+    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7
 
-    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
+    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0
-    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
+    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1
-    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
+    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2
-    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
+    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3
-    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
+    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4
-    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
+    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
-    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
+    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6
-    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
+    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7
 
-    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
+    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0
-    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
+    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
-    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
+    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2
-    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
+    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3
-    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
+    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7
 
-    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
+    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0
-    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
+    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1
-    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
+    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2
-    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
+    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3
-    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
+    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4
 
-    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
+    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0
-    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
+    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1
-    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
+    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2
-    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
+    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3
-    P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4),
+    P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4
-    P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7),
+    P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7
 
-    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
+    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0
-    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
+    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1
-    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
+    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2
-    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
+    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3
-    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
+    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4
-    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
+    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5
-    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
+    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6
-    P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7),
+    P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7
 
-    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
+    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0
-    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
+    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1
-    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
+    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2
-    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
+    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3
-    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
+    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4
-    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
+    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5
-    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
+    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6
-    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
+    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7
 
-    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
+    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0
-    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
+    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1
-    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
+    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2
-    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
+    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3
-    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
+    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4
-    P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5),
+    P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5
-    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
+    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6
-    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
+    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7
 
-    P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0),
+    P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0
-    P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1),
+    P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1
-    P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2),
+    P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2
-    P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3),
+    P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3
-    P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4),
+    P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4
-    P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5),
+    P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5
-    P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6),
+    P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6
-    P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7),
+    P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7
 
-    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
+    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0
-    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
+    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1
-} cyhal_gpio_t;
+} cyhal_gpio_psoc6_02_100_wlcsp_t;
+
+/** Create generic name for the series/package specific type. */
+typedef cyhal_gpio_psoc6_02_100_wlcsp_t cyhal_gpio_t;
 
 /* Connection type definition */
 /** Represents an association between a pin and a resource */
@@ -148,74 +158,139 @@ typedef struct
 } cyhal_resource_pin_mapping_t;
 
 /* Pin connections */
+/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[4];
+/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
+/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2];
+/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[4];
+/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[3];
+/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[3];
+/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[4];
+/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[4];
+/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[4];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
+/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
+/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[19];
+/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[18];
+/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[15];
+/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[15];
+/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[14];
+/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[11];
+/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8];
+/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[7];
+/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[14];
+/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[15];
+/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[15];
+/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[14];
+/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[11];
+/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8];
+/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[7];
+/** List of valid pin to peripheral connections for the scb_uart_cts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[15];
+/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[15];
+/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[17];
+/** List of valid pin to peripheral connections for the scb_uart_tx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[16];
+/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2];
+/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8];
+/** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4];
+/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2];
+/** List of valid pin to peripheral connections for the sdhc_card_emmc_reset_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1];
+/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1];
+/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2];
+/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2];
+/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1];
+/** List of valid pin to peripheral connections for the sdhc_led_ctrl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1];
+/** List of valid pin to peripheral connections for the smif_spi_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
+/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
+/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
+/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
+/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
+/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
+/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
+/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
+/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
+/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
+/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
+/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
+/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
+/** List of valid pin to peripheral connections for the tcpwm_line signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[80];
+/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[80];
+/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
+/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
+/** \} group_hal_psoc6 */
+
 #endif /* _CYHAL_PSOC6_02_100_WLCSP_H_ */
 
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_124_bga.h

@@ -5,11 +5,11 @@
 * PSoC6_02 device GPIO HAL header for 124-BGA package
 *
 * \note
-* Generator version: 1.4.7153.30079
+* Generator version: 1.5.7254.21305
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,133 +30,143 @@
 
 #include "cyhal_hw_resources.h"
 
+/**
+ * \addtogroup group_hal_psoc6_pin_package_psoc6_02_124_bga PSoC6_02 124-BGA
+ * \ingroup group_hal_psoc6_pin_package
+ * \{
+ */
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
 
+/** Gets a pin definition from the provided port and pin numbers */
 #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
 
-/* Pin names */
+/** Definitions for all of the pins that are bonded out on in the 124-BGA package for the PSoC6_02 series. */
 typedef enum {
-    NC = (int)0xFFFFFFFF,
+    NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin
 
-    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
+    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
-    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
+    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
-    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
+    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2
-    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
+    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3
-    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
+    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4
-    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
+    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5
 
-    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
+    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0
-    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
+    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1
-    P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2),
+    P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2
-    P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3),
+    P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3
-    P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),
+    P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4
-    P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),
+    P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5
 
-    P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0),
+    P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0
-    P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1),
+    P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1
-    P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2),
+    P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2
-    P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3),
+    P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3
-    P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4),
+    P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4
-    P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5),
+    P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5
-    P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6),
+    P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6
-    P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7),
+    P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7
 
-    P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0),
+    P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0
-    P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1),
+    P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1
-    P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2),
+    P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2
-    P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3),
+    P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3
-    P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4),
+    P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4
-    P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5),
+    P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), //!< Port 3 Pin 5
 
-    P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0),
+    P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0
-    P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1),
+    P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1
 
-    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
+    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0
-    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
+    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1
-    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
+    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2
-    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
+    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3
-    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
+    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4
-    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
+    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5
-    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
+    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6
-    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
+    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7
 
-    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
+    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0
-    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
+    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1
-    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
+    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2
-    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
+    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3
-    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
+    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4
-    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
+    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
-    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
+    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6
-    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
+    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7
 
-    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
+    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0
-    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
+    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
-    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
+    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2
-    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
+    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3
-    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
+    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4
-    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
+    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5
-    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
+    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6
-    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
+    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7
 
-    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
+    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0
-    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
+    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1
-    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
+    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2
-    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
+    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3
-    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
+    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4
-    P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5),
+    P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5
-    P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6),
+    P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6
-    P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7),
+    P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7
 
-    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
+    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0
-    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
+    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1
-    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
+    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2
-    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
+    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3
-    P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4),
+    P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4
-    P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5),
+    P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5
-    P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6),
+    P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6
-    P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7),
+    P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7
 
-    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
+    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0
-    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
+    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1
-    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
+    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2
-    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
+    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3
-    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
+    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4
-    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
+    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5
-    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
+    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6
-    P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7),
+    P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7
 
-    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
+    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0
-    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
+    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1
-    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
+    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2
-    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
+    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3
-    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
+    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4
-    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
+    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5
-    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
+    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6
-    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
+    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7
 
-    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
+    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0
-    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
+    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1
-    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
+    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2
-    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
+    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3
-    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
+    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4
-    P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5),
+    P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5
-    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
+    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6
-    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
+    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7
 
-    P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0),
+    P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0
-    P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1),
+    P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1
-    P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2),
+    P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2
-    P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3),
+    P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3
-    P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4),
+    P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4
-    P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5),
+    P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5
-    P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6),
+    P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6
-    P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7),
+    P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7
 
-    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
+    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0
-    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
+    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1
-} cyhal_gpio_t;
+} cyhal_gpio_psoc6_02_124_bga_t;
+
+/** Create generic name for the series/package specific type. */
+typedef cyhal_gpio_psoc6_02_124_bga_t cyhal_gpio_t;
 
 /* Connection type definition */
 /** Represents an association between a pin and a resource */
@@ -168,74 +178,139 @@ typedef struct
 } cyhal_resource_pin_mapping_t;
 
 /* Pin connections */
+/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[4];
+/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
+/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2];
+/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[4];
+/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[4];
+/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[4];
+/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[4];
+/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[4];
+/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[4];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
+/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
+/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[21];
+/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[21];
+/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[16];
+/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[17];
+/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[17];
+/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[16];
+/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[13];
+/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[13];
+/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[10];
+/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[16];
+/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[17];
+/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[17];
+/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[16];
+/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[13];
+/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[13];
+/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[10];
+/** List of valid pin to peripheral connections for the scb_uart_cts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[18];
+/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[18];
+/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[19];
+/** List of valid pin to peripheral connections for the scb_uart_tx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[19];
+/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2];
+/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8];
+/** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4];
+/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2];
+/** List of valid pin to peripheral connections for the sdhc_card_emmc_reset_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1];
+/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2];
+/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2];
+/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2];
+/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[2];
+/** List of valid pin to peripheral connections for the sdhc_led_ctrl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1];
+/** List of valid pin to peripheral connections for the smif_spi_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
+/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
+/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
+/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
+/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
+/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
+/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
+/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
+/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
+/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
+/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
+/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
+/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
+/** List of valid pin to peripheral connections for the tcpwm_line signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[98];
+/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[98];
+/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
+/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
+/** \} group_hal_psoc6 */
+
 #endif /* _CYHAL_PSOC6_02_124_BGA_H_ */
 
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_128_tqfp.h

@@ -5,11 +5,11 @@
 * PSoC6_02 device GPIO HAL header for 128-TQFP package
 *
 * \note
-* Generator version: 1.4.7153.30079
+* Generator version: 1.5.7254.21305
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,135 +30,145 @@
 
 #include "cyhal_hw_resources.h"
 
+/**
+ * \addtogroup group_hal_psoc6_pin_package_psoc6_02_128_tqfp PSoC6_02 128-TQFP
+ * \ingroup group_hal_psoc6_pin_package
+ * \{
+ */
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
 
+/** Gets a pin definition from the provided port and pin numbers */
 #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
 
-/* Pin names */
+/** Definitions for all of the pins that are bonded out on in the 128-TQFP package for the PSoC6_02 series. */
 typedef enum {
-    NC = (int)0xFFFFFFFF,
+    NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin
 
-    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
+    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
-    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
+    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
-    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
+    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2
-    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
+    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3
-    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
+    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4
-    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
+    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5
 
-    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
+    P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0
-    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
+    P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1
-    P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2),
+    P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2
-    P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3),
+    P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3
-    P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),
+    P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4
-    P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),
+    P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5
 
-    P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0),
+    P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0
-    P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1),
+    P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1
-    P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2),
+    P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2
-    P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3),
+    P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3
-    P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4),
+    P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4
-    P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5),
+    P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5
-    P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6),
+    P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6
-    P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7),
+    P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7
 
-    P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0),
+    P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0
-    P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1),
+    P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1
-    P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2),
+    P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2
-    P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3),
+    P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3
-    P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4),
+    P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4
-    P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5),
+    P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), //!< Port 3 Pin 5
 
-    P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0),
+    P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0
-    P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1),
+    P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1
-    P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2),
+    P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2), //!< Port 4 Pin 2
-    P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3),
+    P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3), //!< Port 4 Pin 3
 
-    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
+    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0
-    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
+    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1
-    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
+    P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2
-    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
+    P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3
-    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
+    P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4
-    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
+    P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5
-    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
+    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6
-    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
+    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7
 
-    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
+    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0
-    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
+    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1
-    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
+    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2
-    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
+    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3
-    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
+    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4
-    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
+    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
-    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
+    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6
-    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
+    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7
 
-    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
+    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0
-    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
+    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
-    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
+    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2
-    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
+    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3
-    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
+    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4
-    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
+    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5
-    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
+    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6
-    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
+    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7
 
-    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
+    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0
-    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
+    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1
-    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
+    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2
-    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
+    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3
-    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
+    P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4
-    P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5),
+    P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5
-    P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6),
+    P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6
-    P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7),
+    P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7
 
-    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
+    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0
-    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
+    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1
-    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
+    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2
-    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
+    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3
-    P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4),
+    P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4
-    P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5),
+    P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5
-    P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6),
+    P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6
-    P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7),
+    P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7
 
-    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
+    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0
-    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
+    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1
-    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
+    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2
-    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
+    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3
-    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
+    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4
-    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
+    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5
-    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
+    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6
-    P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7),
+    P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7
 
-    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
+    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0
-    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
+    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1
-    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
+    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2
-    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
+    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3
-    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
+    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4
-    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
+    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5
-    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
+    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6
-    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
+    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7
 
-    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
+    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0
-    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
+    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1
-    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
+    P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2
-    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
+    P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3
-    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
+    P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4
-    P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5),
+    P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5
-    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
+    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6
-    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
+    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7
 
-    P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0),
+    P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0
-    P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1),
+    P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1
-    P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2),
+    P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2
-    P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3),
+    P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3
-    P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4),
+    P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4
-    P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5),
+    P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5
-    P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6),
+    P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6
-    P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7),
+    P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7
 
-    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
+    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0
-    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
+    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1
-} cyhal_gpio_t;
+} cyhal_gpio_psoc6_02_128_tqfp_t;
+
+/** Create generic name for the series/package specific type. */
+typedef cyhal_gpio_psoc6_02_128_tqfp_t cyhal_gpio_t;
 
 /* Connection type definition */
 /** Represents an association between a pin and a resource */
@@ -170,74 +180,139 @@ typedef struct
 } cyhal_resource_pin_mapping_t;
 
 /* Pin connections */
+/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[4];
+/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
+/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2];
+/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[4];
+/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[4];
+/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[4];
+/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[4];
+/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[4];
+/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[4];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
+/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
+/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[21];
+/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[21];
+/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[17];
+/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[17];
+/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[17];
+/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[17];
+/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[13];
+/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[13];
+/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[10];
+/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[17];
+/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[17];
+/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[17];
+/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[17];
+/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[13];
+/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[13];
+/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[10];
+/** List of valid pin to peripheral connections for the scb_uart_cts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[19];
+/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[19];
+/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[19];
+/** List of valid pin to peripheral connections for the scb_uart_tx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[19];
+/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2];
+/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8];
+/** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4];
+/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2];
+/** List of valid pin to peripheral connections for the sdhc_card_emmc_reset_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1];
+/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2];
+/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2];
+/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2];
+/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[2];
+/** List of valid pin to peripheral connections for the sdhc_led_ctrl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1];
+/** List of valid pin to peripheral connections for the smif_spi_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
+/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
+/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
+/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
+/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
+/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
+/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
+/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
+/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
+/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
+/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
+/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
+/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
+/** List of valid pin to peripheral connections for the tcpwm_line signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[100];
+/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[100];
+/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
+/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
+/** \} group_hal_psoc6 */
+
 #endif /* _CYHAL_PSOC6_02_128_TQFP_H_ */
 
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_68_qfn.h

@@ -5,11 +5,11 @@
 * PSoC6_02 device GPIO HAL header for 68-QFN package
 *
 * \note
-* Generator version: 1.4.7153.30079
+* Generator version: 1.5.7254.21305
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,83 +30,93 @@
 
 #include "cyhal_hw_resources.h"
 
+/**
+ * \addtogroup group_hal_psoc6_pin_package_psoc6_02_68_qfn PSoC6_02 68-QFN
+ * \ingroup group_hal_psoc6_pin_package
+ * \{
+ */
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
 
+/** Gets a pin definition from the provided port and pin numbers */
 #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
 
-/* Pin names */
+/** Definitions for all of the pins that are bonded out on in the 68-QFN package for the PSoC6_02 series. */
 typedef enum {
-    NC = (int)0xFFFFFFFF,
+    NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin
 
-    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
+    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
-    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
+    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
-    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
+    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2
-    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
+    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3
-    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
+    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4
-    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
+    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5
 
-    P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0),
+    P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0
-    P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1),
+    P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1
-    P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2),
+    P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2
-    P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3),
+    P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3
-    P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4),
+    P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4
-    P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5),
+    P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5
-    P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6),
+    P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6
-    P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7),
+    P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7
 
-    P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0),
+    P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0
-    P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1),
+    P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1
 
-    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
+    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0
-    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
+    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1
-    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
+    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6
-    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
+    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7
 
-    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
+    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2
-    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
+    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3
-    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
+    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4
-    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
+    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
-    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
+    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6
-    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
+    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7
 
-    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
+    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0
-    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
+    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
-    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
+    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2
-    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
+    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3
-    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
+    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7
 
-    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
+    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0
-    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
+    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1
 
-    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
+    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0
-    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
+    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1
-    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
+    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2
-    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
+    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3
 
-    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
+    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0
-    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
+    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1
-    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
+    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2
-    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
+    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3
-    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
+    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4
-    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
+    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5
 
-    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
+    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0
-    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
+    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1
-    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
+    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2
-    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
+    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3
-    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
+    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4
-    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
+    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5
-    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
+    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6
-    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
+    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7
 
-    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
+    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6
-    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
+    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7
 
-    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
+    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0
-    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
+    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1
-} cyhal_gpio_t;
+} cyhal_gpio_psoc6_02_68_qfn_t;
+
+/** Create generic name for the series/package specific type. */
+typedef cyhal_gpio_psoc6_02_68_qfn_t cyhal_gpio_t;
 
 /* Connection type definition */
 /** Represents an association between a pin and a resource */
@@ -118,74 +128,139 @@ typedef struct
 } cyhal_resource_pin_mapping_t;
 
 /* Pin connections */
+/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[3];
+/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[1];
+/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1];
+/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
+/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[2];
+/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
+/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[3];
+/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[2];
+/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[2];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
+/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[6];
+/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[12];
+/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[12];
+/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[10];
+/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[11];
+/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[11];
+/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[10];
+/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5];
+/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4];
+/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[5];
+/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[10];
+/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[11];
+/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[11];
+/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[10];
+/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5];
+/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4];
+/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[5];
+/** List of valid pin to peripheral connections for the scb_uart_cts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10];
+/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[10];
+/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[11];
+/** List of valid pin to peripheral connections for the scb_uart_tx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[11];
+/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1];
+/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4];
+/** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[1];
+/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1];
+/** List of valid pin to peripheral connections for the sdhc_card_emmc_reset_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1];
+/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2];
+/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1];
+/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1];
+/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[2];
+/** List of valid pin to peripheral connections for the sdhc_led_ctrl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1];
+/** List of valid pin to peripheral connections for the smif_spi_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
+/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
+/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
+/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
+/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
+/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
+/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
+/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
+/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
+/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
+/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
+/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
+/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
+/** List of valid pin to peripheral connections for the tcpwm_line signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[50];
+/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[52];
+/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
+/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
+/** \} group_hal_psoc6 */
+
 #endif /* _CYHAL_PSOC6_02_68_QFN_H_ */
 
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_100_tqfp.h

@@ -5,11 +5,11 @@
 * PSoC6_03 device GPIO HAL header for 100-TQFP package
 *
 * \note
-* Generator version: 1.4.7153.30079
+* Generator version: 1.5.7254.21421
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,94 +30,104 @@
 
 #include "cyhal_hw_resources.h"
 
+/**
+ * \addtogroup group_hal_psoc6_pin_package_psoc6_03_100_tqfp PSoC6_03 100-TQFP
+ * \ingroup group_hal_psoc6_pin_package
+ * \{
+ */
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
 
+/** Gets a pin definition from the provided port and pin numbers */
 #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
 
-/* Pin names */
+/** Definitions for all of the pins that are bonded out on in the 100-TQFP package for the PSoC6_03 series. */
 typedef enum {
-    NC = (int)0xFFFFFFFF,
+    NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin
 
-    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
+    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
-    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
+    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
-    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
+    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2
-    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
+    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3
-    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
+    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4
-    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
+    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5
 
-    P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0),
+    P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0
-    P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1),
+    P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1
-    P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2),
+    P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2
-    P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3),
+    P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3
-    P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4),
+    P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4
-    P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5),
+    P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5
-    P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6),
+    P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6
-    P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7),
+    P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7
 
-    P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0),
+    P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0
-    P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1),
+    P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1
 
-    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
+    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0
-    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
+    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1
-    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
+    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6
-    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
+    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7
 
-    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
+    P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0
-    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
+    P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1
-    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
+    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2
-    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
+    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3
-    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
+    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4
-    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
+    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
-    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
+    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6
-    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
+    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7
 
-    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
+    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0
-    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
+    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
-    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
+    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2
-    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
+    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3
-    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
+    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4
-    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
+    P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5
-    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
+    P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6
-    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
+    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7
 
-    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
+    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0
-    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
+    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1
-    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
+    P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2
-    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
+    P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3
 
-    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
+    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0
-    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
+    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1
-    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
+    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2
-    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
+    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3
 
-    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
+    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0
-    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
+    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1
-    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
+    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2
-    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
+    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3
-    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
+    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4
-    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
+    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5
-    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
+    P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6
-    P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7),
+    P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7
 
-    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
+    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0
-    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
+    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1
-    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
+    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2
-    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
+    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3
-    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
+    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4
-    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
+    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5
-    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
+    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6
-    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
+    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7
 
-    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
+    P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0
-    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
+    P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1
-    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
+    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6
-    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
+    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7
 
-    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
+    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0
-    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
+    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1
-} cyhal_gpio_t;
+} cyhal_gpio_psoc6_03_100_tqfp_t;
+
+/** Create generic name for the series/package specific type. */
+typedef cyhal_gpio_psoc6_03_100_tqfp_t cyhal_gpio_t;
 
 /* Connection type definition */
 /** Represents an association between a pin and a resource */
@@ -129,59 +139,109 @@ typedef struct
 } cyhal_resource_pin_mapping_t;
 
 /* Pin connections */
-extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_rx[1];
+/** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */
-extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_tx[1];
+extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1];
+/** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */
+extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
+/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
+/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[12];
+/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[12];
+/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9];
+/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[11];
+/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[11];
+/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[9];
+/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5];
+/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[5];
+/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4];
+/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9];
+/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[11];
+/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[11];
+/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[9];
+/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5];
+/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[5];
+/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4];
+/** List of valid pin to peripheral connections for the scb_uart_cts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[8];
+/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[8];
+/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[10];
+/** List of valid pin to peripheral connections for the scb_uart_tx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[10];
+/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1];
+/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4];
+/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1];
+/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1];
+/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1];
+/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1];
+/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1];
+/** List of valid pin to peripheral connections for the smif_spi_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
+/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
+/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
+/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
+/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
+/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
+/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
+/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
+/** List of valid pin to peripheral connections for the tcpwm_line signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[64];
+/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[64];
+/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
+/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
+/** \} group_hal_psoc6 */
+
 #endif /* _CYHAL_PSOC6_03_100_TQFP_H_ */
 
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_49_wlcsp.h

@@ -5,11 +5,11 @@
 * PSoC6_03 device GPIO HAL header for 49-WLCSP package
 *
 * \note
-* Generator version: 1.4.7153.30079
+* Generator version: 1.5.7254.21421
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,61 +30,71 @@
 
 #include "cyhal_hw_resources.h"
 
+/**
+ * \addtogroup group_hal_psoc6_pin_package_psoc6_03_49_wlcsp PSoC6_03 49-WLCSP
+ * \ingroup group_hal_psoc6_pin_package
+ * \{
+ */
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
 
+/** Gets a pin definition from the provided port and pin numbers */
 #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
 
-/* Pin names */
+/** Definitions for all of the pins that are bonded out on in the 50-WLCSP package for the PSoC6_03 series. */
 typedef enum {
-    NC = (int)0xFFFFFFFF,
+    NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin
 
-    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
+    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
-    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
+    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
 
-    P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0),
+    P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0
-    P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1),
+    P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1
-    P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2),
+    P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2
-    P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3),
+    P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3
-    P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4),
+    P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4
-    P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5),
+    P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5
 
-    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
+    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0
-    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
+    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1
 
-    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
+    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2
-    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
+    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3
-    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
+    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4
-    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
+    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
-    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
+    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6
-    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
+    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7
 
-    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
+    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0
-    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
+    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
-    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
+    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2
-    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
+    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3
-    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
+    P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4
 
-    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
+    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0
-    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
+    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1
-    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
+    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2
-    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
+    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3
 
-    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
+    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0
-    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
+    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1
-    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
+    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2
-    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
+    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3
-    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
+    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4
-    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
+    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5
 
-    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
+    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2
-    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
+    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3
-    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
+    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4
-    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
+    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5
-    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
+    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6
-    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
+    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7
-} cyhal_gpio_t;
+} cyhal_gpio_psoc6_03_49_wlcsp_t;
+
+/** Create generic name for the series/package specific type. */
+typedef cyhal_gpio_psoc6_03_49_wlcsp_t cyhal_gpio_t;
 
 /* Connection type definition */
 /** Represents an association between a pin and a resource */
@@ -96,59 +106,109 @@ typedef struct
 } cyhal_resource_pin_mapping_t;
 
 /* Pin connections */
-extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_rx[1];
+/** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */
-extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_tx[1];
+extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1];
+/** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */
+extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
+/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[6];
+/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[6];
+/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[6];
+/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[7];
+/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[6];
+/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[6];
+/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[7];
+/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5];
+/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4];
+/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[1];
+/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[7];
+/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[6];
+/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[6];
+/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[7];
+/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5];
+/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4];
+/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[1];
+/** List of valid pin to peripheral connections for the scb_uart_cts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6];
+/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[6];
+/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[5];
+/** List of valid pin to peripheral connections for the scb_uart_tx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[5];
+/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1];
+/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4];
+/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1];
+/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1];
+/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1];
+/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1];
+/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1];
+/** List of valid pin to peripheral connections for the smif_spi_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
+/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
+/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
+/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
+/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
+/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
+/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
+/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
+/** List of valid pin to peripheral connections for the tcpwm_line signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[38];
+/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[36];
+/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
+/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
+/** \} group_hal_psoc6 */
+
 #endif /* _CYHAL_PSOC6_03_49_WLCSP_H_ */
 
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_68_qfn.h

@@ -5,11 +5,11 @@
 * PSoC6_03 device GPIO HAL header for 68-QFN package
 *
 * \note
-* Generator version: 1.4.7153.30079
+* Generator version: 1.5.7254.21421
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,83 +30,93 @@
 
 #include "cyhal_hw_resources.h"
 
+/**
+ * \addtogroup group_hal_psoc6_pin_package_psoc6_03_68_qfn PSoC6_03 68-QFN
+ * \ingroup group_hal_psoc6_pin_package
+ * \{
+ */
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
 
+/** Gets a pin definition from the provided port and pin numbers */
 #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
 
-/* Pin names */
+/** Definitions for all of the pins that are bonded out on in the 68-QFN package for the PSoC6_03 series. */
 typedef enum {
-    NC = (int)0xFFFFFFFF,
+    NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin
 
-    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
+    P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
-    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
+    P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
-    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
+    P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2
-    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
+    P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3
-    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
+    P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4
-    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
+    P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5
 
-    P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0),
+    P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0
-    P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1),
+    P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1
-    P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2),
+    P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2
-    P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3),
+    P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3
-    P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4),
+    P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4
-    P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5),
+    P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5
-    P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6),
+    P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6
-    P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7),
+    P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7
 
-    P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0),
+    P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0
-    P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1),
+    P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1
 
-    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
+    P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0
-    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
+    P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1
-    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
+    P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6
-    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
+    P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7
 
-    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
+    P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2
-    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
+    P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3
-    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
+    P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4
-    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
+    P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
-    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
+    P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6
-    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
+    P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7
 
-    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
+    P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0
-    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
+    P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
-    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
+    P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2
-    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
+    P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3
-    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
+    P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7
 
-    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
+    P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0
-    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
+    P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1
 
-    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
+    P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0
-    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
+    P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1
-    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
+    P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2
-    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
+    P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3
 
-    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
+    P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0
-    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
+    P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1
-    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
+    P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2
-    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
+    P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3
-    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
+    P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4
-    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
+    P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5
 
-    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
+    P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0
-    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
+    P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1
-    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
+    P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2
-    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
+    P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3
-    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
+    P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4
-    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
+    P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5
-    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
+    P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6
-    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
+    P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7
 
-    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
+    P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6
-    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
+    P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7
 
-    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
+    USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0
-    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
+    USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1
-} cyhal_gpio_t;
+} cyhal_gpio_psoc6_03_68_qfn_t;
+
+/** Create generic name for the series/package specific type. */
+typedef cyhal_gpio_psoc6_03_68_qfn_t cyhal_gpio_t;
 
 /* Connection type definition */
 /** Represents an association between a pin and a resource */
@@ -118,59 +128,109 @@ typedef struct
 } cyhal_resource_pin_mapping_t;
 
 /* Pin connections */
-extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_rx[1];
+/** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */
-extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_tx[1];
+extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1];
+/** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */
+extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
+/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
+/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[6];
+/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[10];
+/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[10];
+/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[8];
+/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[10];
+/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[10];
+/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[8];
+/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[4];
+/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4];
+/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[2];
+/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[8];
+/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[10];
+/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[10];
+/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[8];
+/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[4];
+/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4];
+/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[2];
+/** List of valid pin to peripheral connections for the scb_uart_cts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[7];
+/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[7];
+/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[9];
+/** List of valid pin to peripheral connections for the scb_uart_tx signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[9];
+/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1];
+/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4];
+/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1];
+/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1];
+/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1];
+/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1];
+/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1];
+/** List of valid pin to peripheral connections for the smif_spi_clk signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
+/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
+/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
+/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
+/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
+/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
+/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
+/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
+/** List of valid pin to peripheral connections for the tcpwm_line signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[52];
+/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[54];
+/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
+/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */
 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
+/** \} group_hal_psoc6 */
+
 #endif /* _CYHAL_PSOC6_03_68_QFN_H_ */
 
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_01.h

@@ -0,0 +1,547 @@
+/***************************************************************************//**
+* \file cyhal_triggers_psoc6_01.h
+*
+* \brief
+* PSoC6_01 family HAL triggers header
+*
+* \note
+* Generator version: 1.5.7254.19579
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYHAL_TRIGGERS_PSOC6_01_H_
+#define _CYHAL_TRIGGERS_PSOC6_01_H_
+
+/**
+ * \addtogroup group_hal_psoc6_triggers_psoc6_01 PSOC6_01
+ * \ingroup group_hal_psoc6_triggers
+ * \{
+ * Trigger connections for psoc6_01
+ */
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/** @brief Name of each output trigger. */
+typedef enum
+{
+    TRIGGER_CPUSS_CTI_TR_IN0 = 0, //!< CPUSS Cross-Triggering-Interface trigger multiplexer (CTI) - cpuss.cti_tr_in[0]
+    TRIGGER_CPUSS_CTI_TR_IN1 = 1, //!< CPUSS Cross-Triggering-Interface trigger multiplexer (CTI) - cpuss.cti_tr_in[1]
+    TRIGGER_CPUSS_DW0_TR_IN0 = 2, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[0]
+    TRIGGER_CPUSS_DW0_TR_IN1 = 3, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[1]
+    TRIGGER_CPUSS_DW0_TR_IN2 = 4, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[2]
+    TRIGGER_CPUSS_DW0_TR_IN3 = 5, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[3]
+    TRIGGER_CPUSS_DW0_TR_IN4 = 6, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[4]
+    TRIGGER_CPUSS_DW0_TR_IN5 = 7, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[5]
+    TRIGGER_CPUSS_DW0_TR_IN6 = 8, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[6]
+    TRIGGER_CPUSS_DW0_TR_IN7 = 9, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[7]
+    TRIGGER_CPUSS_DW0_TR_IN8 = 10, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[8]
+    TRIGGER_CPUSS_DW0_TR_IN9 = 11, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[9]
+    TRIGGER_CPUSS_DW0_TR_IN10 = 12, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[10]
+    TRIGGER_CPUSS_DW0_TR_IN11 = 13, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[11]
+    TRIGGER_CPUSS_DW0_TR_IN12 = 14, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[12]
+    TRIGGER_CPUSS_DW0_TR_IN13 = 15, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[13]
+    TRIGGER_CPUSS_DW0_TR_IN14 = 16, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[14]
+    TRIGGER_CPUSS_DW0_TR_IN15 = 17, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[15]
+    TRIGGER_CPUSS_DW1_TR_IN0 = 18, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[0]
+    TRIGGER_CPUSS_DW1_TR_IN1 = 19, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[1]
+    TRIGGER_CPUSS_DW1_TR_IN2 = 20, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[2]
+    TRIGGER_CPUSS_DW1_TR_IN3 = 21, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[3]
+    TRIGGER_CPUSS_DW1_TR_IN4 = 22, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[4]
+    TRIGGER_CPUSS_DW1_TR_IN5 = 23, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[5]
+    TRIGGER_CPUSS_DW1_TR_IN6 = 24, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[6]
+    TRIGGER_CPUSS_DW1_TR_IN7 = 25, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[7]
+    TRIGGER_CPUSS_DW1_TR_IN8 = 26, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[8]
+    TRIGGER_CPUSS_DW1_TR_IN9 = 27, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[9]
+    TRIGGER_CPUSS_DW1_TR_IN10 = 28, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[10]
+    TRIGGER_CPUSS_DW1_TR_IN11 = 29, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[11]
+    TRIGGER_CPUSS_DW1_TR_IN12 = 30, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[12]
+    TRIGGER_CPUSS_DW1_TR_IN13 = 31, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[13]
+    TRIGGER_CPUSS_DW1_TR_IN14 = 32, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[14]
+    TRIGGER_CPUSS_DW1_TR_IN15 = 33, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[15]
+    TRIGGER_PASS_TR_SAR_IN = 34, //!< PASS trigger multiplexer - pass.tr_sar_in
+    TRIGGER_PERI_TR_IO_OUTPUT0 = 35, //!< GPIO/HSIOM trigger multiplexer - peri.tr_io_output[0]
+    TRIGGER_PERI_TR_IO_OUTPUT1 = 36, //!< GPIO/HSIOM trigger multiplexer - peri.tr_io_output[1]
+    TRIGGER_PROFILE_TR_START = 37, //!< PROFILE trigger multiplexer - profile.tr_start
+    TRIGGER_PROFILE_TR_STOP = 38, //!< PROFILE trigger multiplexer - profile.tr_stop
+    TRIGGER_TCPWM0_TR_IN0 = 39, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[0]
+    TRIGGER_TCPWM0_TR_IN1 = 40, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[1]
+    TRIGGER_TCPWM0_TR_IN2 = 41, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[2]
+    TRIGGER_TCPWM0_TR_IN3 = 42, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[3]
+    TRIGGER_TCPWM0_TR_IN4 = 43, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[4]
+    TRIGGER_TCPWM0_TR_IN5 = 44, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[5]
+    TRIGGER_TCPWM0_TR_IN6 = 45, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[6]
+    TRIGGER_TCPWM0_TR_IN7 = 46, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[7]
+    TRIGGER_TCPWM0_TR_IN8 = 47, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[8]
+    TRIGGER_TCPWM0_TR_IN9 = 48, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[9]
+    TRIGGER_TCPWM0_TR_IN10 = 49, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[10]
+    TRIGGER_TCPWM0_TR_IN11 = 50, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[11]
+    TRIGGER_TCPWM0_TR_IN12 = 51, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[12]
+    TRIGGER_TCPWM0_TR_IN13 = 52, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[13]
+    TRIGGER_TCPWM1_TR_IN0 = 53, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[0]
+    TRIGGER_TCPWM1_TR_IN1 = 54, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[1]
+    TRIGGER_TCPWM1_TR_IN2 = 55, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[2]
+    TRIGGER_TCPWM1_TR_IN3 = 56, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[3]
+    TRIGGER_TCPWM1_TR_IN4 = 57, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[4]
+    TRIGGER_TCPWM1_TR_IN5 = 58, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[5]
+    TRIGGER_TCPWM1_TR_IN6 = 59, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[6]
+    TRIGGER_TCPWM1_TR_IN7 = 60, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[7]
+    TRIGGER_TCPWM1_TR_IN8 = 61, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[8]
+    TRIGGER_TCPWM1_TR_IN9 = 62, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[9]
+    TRIGGER_TCPWM1_TR_IN10 = 63, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[10]
+    TRIGGER_TCPWM1_TR_IN11 = 64, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[11]
+    TRIGGER_TCPWM1_TR_IN12 = 65, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[12]
+    TRIGGER_TCPWM1_TR_IN13 = 66, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[13]
+    TRIGGER_TR_GROUP0_INPUT1 = 67, //!< Datawire output trigger reduction mux - tr_group[0].input[1]
+    TRIGGER_TR_GROUP0_INPUT2 = 68, //!< Datawire output trigger reduction mux - tr_group[0].input[2]
+    TRIGGER_TR_GROUP0_INPUT3 = 69, //!< Datawire output trigger reduction mux - tr_group[0].input[3]
+    TRIGGER_TR_GROUP0_INPUT4 = 70, //!< Datawire output trigger reduction mux - tr_group[0].input[4]
+    TRIGGER_TR_GROUP0_INPUT5 = 71, //!< Datawire output trigger reduction mux - tr_group[0].input[5]
+    TRIGGER_TR_GROUP0_INPUT6 = 72, //!< Datawire output trigger reduction mux - tr_group[0].input[6]
+    TRIGGER_TR_GROUP0_INPUT7 = 73, //!< Datawire output trigger reduction mux - tr_group[0].input[7]
+    TRIGGER_TR_GROUP0_INPUT8 = 74, //!< Datawire output trigger reduction mux - tr_group[0].input[8]
+    TRIGGER_TR_GROUP0_INPUT9 = 75, //!< TCPWM trigger output reduction mux - tr_group[0].input[9]
+    TRIGGER_TR_GROUP0_INPUT10 = 76, //!< TCPWM trigger output reduction mux - tr_group[0].input[10]
+    TRIGGER_TR_GROUP0_INPUT11 = 77, //!< TCPWM trigger output reduction mux - tr_group[0].input[11]
+    TRIGGER_TR_GROUP0_INPUT12 = 78, //!< TCPWM trigger output reduction mux - tr_group[0].input[12]
+    TRIGGER_TR_GROUP0_INPUT13 = 79, //!< TCPWM trigger output reduction mux - tr_group[0].input[13]
+    TRIGGER_TR_GROUP0_INPUT14 = 80, //!< TCPWM trigger output reduction mux - tr_group[0].input[14]
+    TRIGGER_TR_GROUP0_INPUT15 = 81, //!< TCPWM trigger output reduction mux - tr_group[0].input[15]
+    TRIGGER_TR_GROUP0_INPUT16 = 82, //!< TCPWM trigger output reduction mux - tr_group[0].input[16]
+    TRIGGER_TR_GROUP0_INPUT17 = 83, //!< TCPWM trigger output reduction mux - tr_group[0].input[17]
+    TRIGGER_TR_GROUP0_INPUT18 = 84, //!< TCPWM trigger output reduction mux - tr_group[0].input[18]
+    TRIGGER_TR_GROUP0_INPUT19 = 85, //!< TCPWM trigger output reduction mux - tr_group[0].input[19]
+    TRIGGER_TR_GROUP0_INPUT20 = 86, //!< TCPWM trigger output reduction mux - tr_group[0].input[20]
+    TRIGGER_TR_GROUP0_INPUT21 = 87, //!< TCPWM trigger output reduction mux - tr_group[0].input[21]
+    TRIGGER_TR_GROUP0_INPUT22 = 88, //!< TCPWM trigger output reduction mux - tr_group[0].input[22]
+    TRIGGER_TR_GROUP0_INPUT23 = 89, //!< TCPWM trigger output reduction mux - tr_group[0].input[23]
+    TRIGGER_TR_GROUP0_INPUT24 = 90, //!< TCPWM trigger output reduction mux - tr_group[0].input[24]
+    TRIGGER_TR_GROUP0_INPUT25 = 91, //!< HSIOM Pin input reduction mux - tr_group[0].input[25]
+    TRIGGER_TR_GROUP0_INPUT26 = 92, //!< HSIOM Pin input reduction mux - tr_group[0].input[26]
+    TRIGGER_TR_GROUP0_INPUT27 = 93, //!< DMA request reduction mux - tr_group[0].input[27]
+    TRIGGER_TR_GROUP0_INPUT28 = 94, //!< DMA request reduction mux - tr_group[0].input[28]
+    TRIGGER_TR_GROUP0_INPUT29 = 95, //!< DMA request reduction mux - tr_group[0].input[29]
+    TRIGGER_TR_GROUP0_INPUT30 = 96, //!< DMA request reduction mux - tr_group[0].input[30]
+    TRIGGER_TR_GROUP0_INPUT31 = 97, //!< DMA request reduction mux - tr_group[0].input[31]
+    TRIGGER_TR_GROUP0_INPUT32 = 98, //!< DMA request reduction mux - tr_group[0].input[32]
+    TRIGGER_TR_GROUP0_INPUT33 = 99, //!< DMA request reduction mux - tr_group[0].input[33]
+    TRIGGER_TR_GROUP0_INPUT34 = 100, //!< DMA request reduction mux - tr_group[0].input[34]
+    TRIGGER_TR_GROUP0_INPUT35 = 101, //!< DMA request reduction mux - tr_group[0].input[35]
+    TRIGGER_TR_GROUP0_INPUT36 = 102, //!< DMA request reduction mux - tr_group[0].input[36]
+    TRIGGER_TR_GROUP0_INPUT37 = 103, //!< DMA request reduction mux - tr_group[0].input[37]
+    TRIGGER_TR_GROUP0_INPUT38 = 104, //!< DMA request reduction mux - tr_group[0].input[38]
+    TRIGGER_TR_GROUP0_INPUT39 = 105, //!< DMA request reduction mux - tr_group[0].input[39]
+    TRIGGER_TR_GROUP0_INPUT40 = 106, //!< DMA request reduction mux - tr_group[0].input[40]
+    TRIGGER_TR_GROUP0_INPUT41 = 107, //!< DMA request reduction mux - tr_group[0].input[41]
+    TRIGGER_TR_GROUP0_INPUT42 = 108, //!< DMA request reduction mux - tr_group[0].input[42]
+    TRIGGER_TR_GROUP0_INPUT43 = 109, //!< Trigger input reduction mux - tr_group[0].input[43]
+    TRIGGER_TR_GROUP0_INPUT44 = 110, //!< Trigger input reduction mux - tr_group[0].input[44]
+    TRIGGER_TR_GROUP0_INPUT45 = 111, //!< Trigger input reduction mux - tr_group[0].input[45]
+    TRIGGER_TR_GROUP0_INPUT46 = 112, //!< Trigger input reduction mux - tr_group[0].input[46]
+    TRIGGER_TR_GROUP0_INPUT47 = 113, //!< Trigger input reduction mux - tr_group[0].input[47]
+    TRIGGER_TR_GROUP0_INPUT48 = 114, //!< Trigger input reduction mux - tr_group[0].input[48]
+    TRIGGER_TR_GROUP0_INPUT49 = 115, //!< Trigger input reduction mux - tr_group[0].input[49]
+    TRIGGER_TR_GROUP0_INPUT50 = 116, //!< Trigger input reduction mux - tr_group[0].input[50]
+    TRIGGER_TR_GROUP1_INPUT1 = 117, //!< Datawire output trigger reduction mux - tr_group[1].input[1]
+    TRIGGER_TR_GROUP1_INPUT2 = 118, //!< Datawire output trigger reduction mux - tr_group[1].input[2]
+    TRIGGER_TR_GROUP1_INPUT3 = 119, //!< Datawire output trigger reduction mux - tr_group[1].input[3]
+    TRIGGER_TR_GROUP1_INPUT4 = 120, //!< Datawire output trigger reduction mux - tr_group[1].input[4]
+    TRIGGER_TR_GROUP1_INPUT5 = 121, //!< Datawire output trigger reduction mux - tr_group[1].input[5]
+    TRIGGER_TR_GROUP1_INPUT6 = 122, //!< Datawire output trigger reduction mux - tr_group[1].input[6]
+    TRIGGER_TR_GROUP1_INPUT7 = 123, //!< Datawire output trigger reduction mux - tr_group[1].input[7]
+    TRIGGER_TR_GROUP1_INPUT8 = 124, //!< Datawire output trigger reduction mux - tr_group[1].input[8]
+    TRIGGER_TR_GROUP1_INPUT9 = 125, //!< TCPWM trigger output reduction mux - tr_group[1].input[9]
+    TRIGGER_TR_GROUP1_INPUT10 = 126, //!< TCPWM trigger output reduction mux - tr_group[1].input[10]
+    TRIGGER_TR_GROUP1_INPUT11 = 127, //!< TCPWM trigger output reduction mux - tr_group[1].input[11]
+    TRIGGER_TR_GROUP1_INPUT12 = 128, //!< TCPWM trigger output reduction mux - tr_group[1].input[12]
+    TRIGGER_TR_GROUP1_INPUT13 = 129, //!< TCPWM trigger output reduction mux - tr_group[1].input[13]
+    TRIGGER_TR_GROUP1_INPUT14 = 130, //!< TCPWM trigger output reduction mux - tr_group[1].input[14]
+    TRIGGER_TR_GROUP1_INPUT15 = 131, //!< TCPWM trigger output reduction mux - tr_group[1].input[15]
+    TRIGGER_TR_GROUP1_INPUT16 = 132, //!< TCPWM trigger output reduction mux - tr_group[1].input[16]
+    TRIGGER_TR_GROUP1_INPUT17 = 133, //!< TCPWM trigger output reduction mux - tr_group[1].input[17]
+    TRIGGER_TR_GROUP1_INPUT18 = 134, //!< TCPWM trigger output reduction mux - tr_group[1].input[18]
+    TRIGGER_TR_GROUP1_INPUT19 = 135, //!< TCPWM trigger output reduction mux - tr_group[1].input[19]
+    TRIGGER_TR_GROUP1_INPUT20 = 136, //!< TCPWM trigger output reduction mux - tr_group[1].input[20]
+    TRIGGER_TR_GROUP1_INPUT21 = 137, //!< TCPWM trigger output reduction mux - tr_group[1].input[21]
+    TRIGGER_TR_GROUP1_INPUT22 = 138, //!< TCPWM trigger output reduction mux - tr_group[1].input[22]
+    TRIGGER_TR_GROUP1_INPUT23 = 139, //!< TCPWM trigger output reduction mux - tr_group[1].input[23]
+    TRIGGER_TR_GROUP1_INPUT24 = 140, //!< TCPWM trigger output reduction mux - tr_group[1].input[24]
+    TRIGGER_TR_GROUP1_INPUT25 = 141, //!< HSIOM Pin input reduction mux - tr_group[1].input[25]
+    TRIGGER_TR_GROUP1_INPUT26 = 142, //!< HSIOM Pin input reduction mux - tr_group[1].input[26]
+    TRIGGER_TR_GROUP1_INPUT27 = 143, //!< DMA request reduction mux - tr_group[1].input[27]
+    TRIGGER_TR_GROUP1_INPUT28 = 144, //!< DMA request reduction mux - tr_group[1].input[28]
+    TRIGGER_TR_GROUP1_INPUT29 = 145, //!< DMA request reduction mux - tr_group[1].input[29]
+    TRIGGER_TR_GROUP1_INPUT30 = 146, //!< DMA request reduction mux - tr_group[1].input[30]
+    TRIGGER_TR_GROUP1_INPUT31 = 147, //!< DMA request reduction mux - tr_group[1].input[31]
+    TRIGGER_TR_GROUP1_INPUT32 = 148, //!< DMA request reduction mux - tr_group[1].input[32]
+    TRIGGER_TR_GROUP1_INPUT33 = 149, //!< DMA request reduction mux - tr_group[1].input[33]
+    TRIGGER_TR_GROUP1_INPUT34 = 150, //!< DMA request reduction mux - tr_group[1].input[34]
+    TRIGGER_TR_GROUP1_INPUT35 = 151, //!< DMA request reduction mux - tr_group[1].input[35]
+    TRIGGER_TR_GROUP1_INPUT36 = 152, //!< DMA request reduction mux - tr_group[1].input[36]
+    TRIGGER_TR_GROUP1_INPUT37 = 153, //!< DMA request reduction mux - tr_group[1].input[37]
+    TRIGGER_TR_GROUP1_INPUT38 = 154, //!< DMA request reduction mux - tr_group[1].input[38]
+    TRIGGER_TR_GROUP1_INPUT39 = 155, //!< DMA request reduction mux - tr_group[1].input[39]
+    TRIGGER_TR_GROUP1_INPUT40 = 156, //!< DMA request reduction mux - tr_group[1].input[40]
+    TRIGGER_TR_GROUP1_INPUT41 = 157, //!< DMA request reduction mux - tr_group[1].input[41]
+    TRIGGER_TR_GROUP1_INPUT42 = 158, //!< DMA request reduction mux - tr_group[1].input[42]
+    TRIGGER_TR_GROUP1_INPUT43 = 159, //!< Trigger input reduction mux - tr_group[1].input[43]
+    TRIGGER_TR_GROUP1_INPUT44 = 160, //!< Trigger input reduction mux - tr_group[1].input[44]
+    TRIGGER_TR_GROUP1_INPUT45 = 161, //!< Trigger input reduction mux - tr_group[1].input[45]
+    TRIGGER_TR_GROUP1_INPUT46 = 162, //!< Trigger input reduction mux - tr_group[1].input[46]
+    TRIGGER_TR_GROUP1_INPUT47 = 163, //!< Trigger input reduction mux - tr_group[1].input[47]
+    TRIGGER_TR_GROUP1_INPUT48 = 164, //!< Trigger input reduction mux - tr_group[1].input[48]
+    TRIGGER_TR_GROUP1_INPUT49 = 165, //!< Trigger input reduction mux - tr_group[1].input[49]
+    TRIGGER_TR_GROUP1_INPUT50 = 166, //!< Trigger input reduction mux - tr_group[1].input[50]
+    TRIGGER_TR_GROUP2_INPUT1 = 167, //!< Datawire output trigger reduction mux - tr_group[2].input[1]
+    TRIGGER_TR_GROUP2_INPUT2 = 168, //!< Datawire output trigger reduction mux - tr_group[2].input[2]
+    TRIGGER_TR_GROUP2_INPUT3 = 169, //!< Datawire output trigger reduction mux - tr_group[2].input[3]
+    TRIGGER_TR_GROUP2_INPUT4 = 170, //!< Datawire output trigger reduction mux - tr_group[2].input[4]
+    TRIGGER_TR_GROUP2_INPUT5 = 171, //!< Datawire output trigger reduction mux - tr_group[2].input[5]
+    TRIGGER_TR_GROUP2_INPUT6 = 172, //!< Datawire output trigger reduction mux - tr_group[2].input[6]
+    TRIGGER_TR_GROUP2_INPUT7 = 173, //!< Datawire output trigger reduction mux - tr_group[2].input[7]
+    TRIGGER_TR_GROUP2_INPUT8 = 174, //!< Datawire output trigger reduction mux - tr_group[2].input[8]
+    TRIGGER_TR_GROUP2_INPUT9 = 175, //!< TCPWM trigger output reduction mux - tr_group[2].input[9]
+    TRIGGER_TR_GROUP2_INPUT10 = 176, //!< TCPWM trigger output reduction mux - tr_group[2].input[10]
+    TRIGGER_TR_GROUP2_INPUT11 = 177, //!< TCPWM trigger output reduction mux - tr_group[2].input[11]
+    TRIGGER_TR_GROUP2_INPUT12 = 178, //!< TCPWM trigger output reduction mux - tr_group[2].input[12]
+    TRIGGER_TR_GROUP2_INPUT13 = 179, //!< TCPWM trigger output reduction mux - tr_group[2].input[13]
+    TRIGGER_TR_GROUP2_INPUT14 = 180, //!< TCPWM trigger output reduction mux - tr_group[2].input[14]
+    TRIGGER_TR_GROUP2_INPUT15 = 181, //!< TCPWM trigger output reduction mux - tr_group[2].input[15]
+    TRIGGER_TR_GROUP2_INPUT16 = 182, //!< TCPWM trigger output reduction mux - tr_group[2].input[16]
+    TRIGGER_TR_GROUP2_INPUT17 = 183, //!< TCPWM trigger output reduction mux - tr_group[2].input[17]
+    TRIGGER_TR_GROUP2_INPUT18 = 184, //!< TCPWM trigger output reduction mux - tr_group[2].input[18]
+    TRIGGER_TR_GROUP2_INPUT19 = 185, //!< TCPWM trigger output reduction mux - tr_group[2].input[19]
+    TRIGGER_TR_GROUP2_INPUT20 = 186, //!< TCPWM trigger output reduction mux - tr_group[2].input[20]
+    TRIGGER_TR_GROUP2_INPUT21 = 187, //!< TCPWM trigger output reduction mux - tr_group[2].input[21]
+    TRIGGER_TR_GROUP2_INPUT22 = 188, //!< TCPWM trigger output reduction mux - tr_group[2].input[22]
+    TRIGGER_TR_GROUP2_INPUT23 = 189, //!< TCPWM trigger output reduction mux - tr_group[2].input[23]
+    TRIGGER_TR_GROUP2_INPUT24 = 190, //!< TCPWM trigger output reduction mux - tr_group[2].input[24]
+    TRIGGER_TR_GROUP2_INPUT25 = 191, //!< HSIOM Pin input reduction mux - tr_group[2].input[25]
+    TRIGGER_TR_GROUP2_INPUT26 = 192, //!< HSIOM Pin input reduction mux - tr_group[2].input[26]
+    TRIGGER_TR_GROUP2_INPUT27 = 193, //!< HSIOM Pin input reduction mux - tr_group[2].input[27]
+    TRIGGER_TR_GROUP2_INPUT28 = 194, //!< HSIOM Pin input reduction mux - tr_group[2].input[28]
+    TRIGGER_TR_GROUP2_INPUT29 = 195, //!< HSIOM Pin input reduction mux - tr_group[2].input[29]
+    TRIGGER_TR_GROUP2_INPUT30 = 196, //!< HSIOM Pin input reduction mux - tr_group[2].input[30]
+    TRIGGER_TR_GROUP2_INPUT31 = 197, //!< HSIOM Pin input reduction mux - tr_group[2].input[31]
+    TRIGGER_TR_GROUP2_INPUT32 = 198, //!< HSIOM Pin input reduction mux - tr_group[2].input[32]
+    TRIGGER_TR_GROUP2_INPUT33 = 199, //!< DMA request reduction mux - tr_group[2].input[33]
+    TRIGGER_TR_GROUP2_INPUT34 = 200, //!< DMA request reduction mux - tr_group[2].input[34]
+    TRIGGER_TR_GROUP2_INPUT35 = 201, //!< Trigger input reduction mux - tr_group[2].input[35]
+    TRIGGER_TR_GROUP2_INPUT36 = 202, //!< Trigger input reduction mux - tr_group[2].input[36]
+    TRIGGER_TR_GROUP2_INPUT37 = 203, //!< Trigger input reduction mux - tr_group[2].input[37]
+    TRIGGER_TR_GROUP2_INPUT38 = 204, //!< Trigger input reduction mux - tr_group[2].input[38]
+    TRIGGER_TR_GROUP2_INPUT39 = 205, //!< Trigger input reduction mux - tr_group[2].input[39]
+    TRIGGER_TR_GROUP2_INPUT40 = 206, //!< Trigger input reduction mux - tr_group[2].input[40]
+    TRIGGER_TR_GROUP2_INPUT41 = 207, //!< Trigger input reduction mux - tr_group[2].input[41]
+    TRIGGER_TR_GROUP2_INPUT42 = 208, //!< Trigger input reduction mux - tr_group[2].input[42]
+    TRIGGER_TR_GROUP3_INPUT1 = 209, //!< Datawire output trigger reduction mux - tr_group[3].input[1]
+    TRIGGER_TR_GROUP3_INPUT2 = 210, //!< Datawire output trigger reduction mux - tr_group[3].input[2]
+    TRIGGER_TR_GROUP3_INPUT3 = 211, //!< Datawire output trigger reduction mux - tr_group[3].input[3]
+    TRIGGER_TR_GROUP3_INPUT4 = 212, //!< Datawire output trigger reduction mux - tr_group[3].input[4]
+    TRIGGER_TR_GROUP3_INPUT5 = 213, //!< Datawire output trigger reduction mux - tr_group[3].input[5]
+    TRIGGER_TR_GROUP3_INPUT6 = 214, //!< Datawire output trigger reduction mux - tr_group[3].input[6]
+    TRIGGER_TR_GROUP3_INPUT7 = 215, //!< Datawire output trigger reduction mux - tr_group[3].input[7]
+    TRIGGER_TR_GROUP3_INPUT8 = 216, //!< Datawire output trigger reduction mux - tr_group[3].input[8]
+    TRIGGER_TR_GROUP3_INPUT9 = 217, //!< TCPWM trigger output reduction mux - tr_group[3].input[9]
+    TRIGGER_TR_GROUP3_INPUT10 = 218, //!< TCPWM trigger output reduction mux - tr_group[3].input[10]
+    TRIGGER_TR_GROUP3_INPUT11 = 219, //!< TCPWM trigger output reduction mux - tr_group[3].input[11]
+    TRIGGER_TR_GROUP3_INPUT12 = 220, //!< TCPWM trigger output reduction mux - tr_group[3].input[12]
+    TRIGGER_TR_GROUP3_INPUT13 = 221, //!< TCPWM trigger output reduction mux - tr_group[3].input[13]
+    TRIGGER_TR_GROUP3_INPUT14 = 222, //!< TCPWM trigger output reduction mux - tr_group[3].input[14]
+    TRIGGER_TR_GROUP3_INPUT15 = 223, //!< TCPWM trigger output reduction mux - tr_group[3].input[15]
+    TRIGGER_TR_GROUP3_INPUT16 = 224, //!< TCPWM trigger output reduction mux - tr_group[3].input[16]
+    TRIGGER_TR_GROUP3_INPUT17 = 225, //!< TCPWM trigger output reduction mux - tr_group[3].input[17]
+    TRIGGER_TR_GROUP3_INPUT18 = 226, //!< TCPWM trigger output reduction mux - tr_group[3].input[18]
+    TRIGGER_TR_GROUP3_INPUT19 = 227, //!< TCPWM trigger output reduction mux - tr_group[3].input[19]
+    TRIGGER_TR_GROUP3_INPUT20 = 228, //!< TCPWM trigger output reduction mux - tr_group[3].input[20]
+    TRIGGER_TR_GROUP3_INPUT21 = 229, //!< TCPWM trigger output reduction mux - tr_group[3].input[21]
+    TRIGGER_TR_GROUP3_INPUT22 = 230, //!< TCPWM trigger output reduction mux - tr_group[3].input[22]
+    TRIGGER_TR_GROUP3_INPUT23 = 231, //!< TCPWM trigger output reduction mux - tr_group[3].input[23]
+    TRIGGER_TR_GROUP3_INPUT24 = 232, //!< TCPWM trigger output reduction mux - tr_group[3].input[24]
+    TRIGGER_TR_GROUP3_INPUT25 = 233, //!< HSIOM Pin input reduction mux - tr_group[3].input[25]
+    TRIGGER_TR_GROUP3_INPUT26 = 234, //!< HSIOM Pin input reduction mux - tr_group[3].input[26]
+    TRIGGER_TR_GROUP3_INPUT27 = 235, //!< HSIOM Pin input reduction mux - tr_group[3].input[27]
+    TRIGGER_TR_GROUP3_INPUT28 = 236, //!< HSIOM Pin input reduction mux - tr_group[3].input[28]
+    TRIGGER_TR_GROUP3_INPUT29 = 237, //!< HSIOM Pin input reduction mux - tr_group[3].input[29]
+    TRIGGER_TR_GROUP3_INPUT30 = 238, //!< HSIOM Pin input reduction mux - tr_group[3].input[30]
+    TRIGGER_TR_GROUP3_INPUT31 = 239, //!< HSIOM Pin input reduction mux - tr_group[3].input[31]
+    TRIGGER_TR_GROUP3_INPUT32 = 240, //!< HSIOM Pin input reduction mux - tr_group[3].input[32]
+    TRIGGER_TR_GROUP3_INPUT33 = 241, //!< DMA request reduction mux - tr_group[3].input[33]
+    TRIGGER_TR_GROUP3_INPUT34 = 242, //!< DMA request reduction mux - tr_group[3].input[34]
+    TRIGGER_TR_GROUP3_INPUT35 = 243, //!< Trigger input reduction mux - tr_group[3].input[35]
+    TRIGGER_TR_GROUP3_INPUT36 = 244, //!< Trigger input reduction mux - tr_group[3].input[36]
+    TRIGGER_TR_GROUP3_INPUT37 = 245, //!< Trigger input reduction mux - tr_group[3].input[37]
+    TRIGGER_TR_GROUP3_INPUT38 = 246, //!< Trigger input reduction mux - tr_group[3].input[38]
+    TRIGGER_TR_GROUP3_INPUT39 = 247, //!< Trigger input reduction mux - tr_group[3].input[39]
+    TRIGGER_TR_GROUP3_INPUT40 = 248, //!< Trigger input reduction mux - tr_group[3].input[40]
+    TRIGGER_TR_GROUP3_INPUT41 = 249, //!< Trigger input reduction mux - tr_group[3].input[41]
+    TRIGGER_TR_GROUP3_INPUT42 = 250, //!< Trigger input reduction mux - tr_group[3].input[42]
+    TRIGGER_TR_GROUP4_INPUT1 = 251, //!< Datawire output trigger reduction mux - tr_group[4].input[1]
+    TRIGGER_TR_GROUP4_INPUT2 = 252, //!< Datawire output trigger reduction mux - tr_group[4].input[2]
+    TRIGGER_TR_GROUP4_INPUT3 = 253, //!< Datawire output trigger reduction mux - tr_group[4].input[3]
+    TRIGGER_TR_GROUP4_INPUT4 = 254, //!< Datawire output trigger reduction mux - tr_group[4].input[4]
+    TRIGGER_TR_GROUP4_INPUT5 = 255, //!< Datawire output trigger reduction mux - tr_group[4].input[5]
+    TRIGGER_TR_GROUP4_INPUT6 = 256, //!< Datawire output trigger reduction mux - tr_group[4].input[6]
+    TRIGGER_TR_GROUP4_INPUT7 = 257, //!< Datawire output trigger reduction mux - tr_group[4].input[7]
+    TRIGGER_TR_GROUP4_INPUT8 = 258, //!< Datawire output trigger reduction mux - tr_group[4].input[8]
+    TRIGGER_TR_GROUP4_INPUT9 = 259, //!< TCPWM trigger output reduction mux - tr_group[4].input[9]
+    TRIGGER_TR_GROUP4_INPUT10 = 260, //!< TCPWM trigger output reduction mux - tr_group[4].input[10]
+    TRIGGER_TR_GROUP4_INPUT11 = 261, //!< TCPWM trigger output reduction mux - tr_group[4].input[11]
+    TRIGGER_TR_GROUP4_INPUT12 = 262, //!< TCPWM trigger output reduction mux - tr_group[4].input[12]
+    TRIGGER_TR_GROUP4_INPUT13 = 263, //!< TCPWM trigger output reduction mux - tr_group[4].input[13]
+    TRIGGER_TR_GROUP4_INPUT14 = 264, //!< TCPWM trigger output reduction mux - tr_group[4].input[14]
+    TRIGGER_TR_GROUP4_INPUT15 = 265, //!< TCPWM trigger output reduction mux - tr_group[4].input[15]
+    TRIGGER_TR_GROUP4_INPUT16 = 266, //!< TCPWM trigger output reduction mux - tr_group[4].input[16]
+    TRIGGER_TR_GROUP4_INPUT17 = 267, //!< TCPWM trigger output reduction mux - tr_group[4].input[17]
+    TRIGGER_TR_GROUP4_INPUT18 = 268, //!< TCPWM trigger output reduction mux - tr_group[4].input[18]
+    TRIGGER_TR_GROUP4_INPUT19 = 269, //!< TCPWM trigger output reduction mux - tr_group[4].input[19]
+    TRIGGER_TR_GROUP4_INPUT20 = 270, //!< TCPWM trigger output reduction mux - tr_group[4].input[20]
+    TRIGGER_TR_GROUP4_INPUT21 = 271, //!< TCPWM trigger output reduction mux - tr_group[4].input[21]
+    TRIGGER_TR_GROUP4_INPUT22 = 272, //!< TCPWM trigger output reduction mux - tr_group[4].input[22]
+    TRIGGER_TR_GROUP4_INPUT23 = 273, //!< TCPWM trigger output reduction mux - tr_group[4].input[23]
+    TRIGGER_TR_GROUP4_INPUT24 = 274, //!< TCPWM trigger output reduction mux - tr_group[4].input[24]
+    TRIGGER_TR_GROUP4_INPUT25 = 275, //!< HSIOM Pin input reduction mux - tr_group[4].input[25]
+    TRIGGER_TR_GROUP4_INPUT26 = 276, //!< HSIOM Pin input reduction mux - tr_group[4].input[26]
+    TRIGGER_TR_GROUP4_INPUT27 = 277, //!< HSIOM Pin input reduction mux - tr_group[4].input[27]
+    TRIGGER_TR_GROUP4_INPUT28 = 278, //!< HSIOM Pin input reduction mux - tr_group[4].input[28]
+    TRIGGER_TR_GROUP4_INPUT29 = 279, //!< HSIOM Pin input reduction mux - tr_group[4].input[29]
+    TRIGGER_TR_GROUP4_INPUT30 = 280, //!< HSIOM Pin input reduction mux - tr_group[4].input[30]
+    TRIGGER_TR_GROUP4_INPUT31 = 281, //!< HSIOM Pin input reduction mux - tr_group[4].input[31]
+    TRIGGER_TR_GROUP4_INPUT32 = 282, //!< HSIOM Pin input reduction mux - tr_group[4].input[32]
+    TRIGGER_TR_GROUP4_INPUT33 = 283, //!< DMA request reduction mux - tr_group[4].input[33]
+    TRIGGER_TR_GROUP4_INPUT34 = 284, //!< DMA request reduction mux - tr_group[4].input[34]
+    TRIGGER_TR_GROUP4_INPUT35 = 285, //!< Trigger input reduction mux - tr_group[4].input[35]
+    TRIGGER_TR_GROUP4_INPUT36 = 286, //!< Trigger input reduction mux - tr_group[4].input[36]
+    TRIGGER_TR_GROUP4_INPUT37 = 287, //!< Trigger input reduction mux - tr_group[4].input[37]
+    TRIGGER_TR_GROUP4_INPUT38 = 288, //!< Trigger input reduction mux - tr_group[4].input[38]
+    TRIGGER_TR_GROUP4_INPUT39 = 289, //!< Trigger input reduction mux - tr_group[4].input[39]
+    TRIGGER_TR_GROUP4_INPUT40 = 290, //!< Trigger input reduction mux - tr_group[4].input[40]
+    TRIGGER_TR_GROUP4_INPUT41 = 291, //!< Trigger input reduction mux - tr_group[4].input[41]
+    TRIGGER_TR_GROUP4_INPUT42 = 292, //!< Trigger input reduction mux - tr_group[4].input[42]
+    TRIGGER_TR_GROUP5_INPUT1 = 293, //!< Datawire output trigger reduction mux - tr_group[5].input[1]
+    TRIGGER_TR_GROUP5_INPUT2 = 294, //!< Datawire output trigger reduction mux - tr_group[5].input[2]
+    TRIGGER_TR_GROUP5_INPUT3 = 295, //!< Datawire output trigger reduction mux - tr_group[5].input[3]
+    TRIGGER_TR_GROUP5_INPUT4 = 296, //!< Datawire output trigger reduction mux - tr_group[5].input[4]
+    TRIGGER_TR_GROUP5_INPUT5 = 297, //!< Datawire output trigger reduction mux - tr_group[5].input[5]
+    TRIGGER_TR_GROUP5_INPUT6 = 298, //!< Datawire output trigger reduction mux - tr_group[5].input[6]
+    TRIGGER_TR_GROUP5_INPUT7 = 299, //!< Datawire output trigger reduction mux - tr_group[5].input[7]
+    TRIGGER_TR_GROUP5_INPUT8 = 300, //!< Datawire output trigger reduction mux - tr_group[5].input[8]
+    TRIGGER_TR_GROUP5_INPUT9 = 301, //!< TCPWM trigger output reduction mux - tr_group[5].input[9]
+    TRIGGER_TR_GROUP5_INPUT10 = 302, //!< TCPWM trigger output reduction mux - tr_group[5].input[10]
+    TRIGGER_TR_GROUP5_INPUT11 = 303, //!< TCPWM trigger output reduction mux - tr_group[5].input[11]
+    TRIGGER_TR_GROUP5_INPUT12 = 304, //!< TCPWM trigger output reduction mux - tr_group[5].input[12]
+    TRIGGER_TR_GROUP5_INPUT13 = 305, //!< TCPWM trigger output reduction mux - tr_group[5].input[13]
+    TRIGGER_TR_GROUP5_INPUT14 = 306, //!< TCPWM trigger output reduction mux - tr_group[5].input[14]
+    TRIGGER_TR_GROUP5_INPUT15 = 307, //!< TCPWM trigger output reduction mux - tr_group[5].input[15]
+    TRIGGER_TR_GROUP5_INPUT16 = 308, //!< TCPWM trigger output reduction mux - tr_group[5].input[16]
+    TRIGGER_TR_GROUP5_INPUT17 = 309, //!< TCPWM trigger output reduction mux - tr_group[5].input[17]
+    TRIGGER_TR_GROUP5_INPUT18 = 310, //!< TCPWM trigger output reduction mux - tr_group[5].input[18]
+    TRIGGER_TR_GROUP5_INPUT19 = 311, //!< TCPWM trigger output reduction mux - tr_group[5].input[19]
+    TRIGGER_TR_GROUP5_INPUT20 = 312, //!< TCPWM trigger output reduction mux - tr_group[5].input[20]
+    TRIGGER_TR_GROUP5_INPUT21 = 313, //!< TCPWM trigger output reduction mux - tr_group[5].input[21]
+    TRIGGER_TR_GROUP5_INPUT22 = 314, //!< TCPWM trigger output reduction mux - tr_group[5].input[22]
+    TRIGGER_TR_GROUP5_INPUT23 = 315, //!< TCPWM trigger output reduction mux - tr_group[5].input[23]
+    TRIGGER_TR_GROUP5_INPUT24 = 316, //!< TCPWM trigger output reduction mux - tr_group[5].input[24]
+    TRIGGER_TR_GROUP5_INPUT25 = 317, //!< HSIOM Pin input reduction mux - tr_group[5].input[25]
+    TRIGGER_TR_GROUP5_INPUT26 = 318, //!< HSIOM Pin input reduction mux - tr_group[5].input[26]
+    TRIGGER_TR_GROUP5_INPUT27 = 319, //!< HSIOM Pin input reduction mux - tr_group[5].input[27]
+    TRIGGER_TR_GROUP5_INPUT28 = 320, //!< HSIOM Pin input reduction mux - tr_group[5].input[28]
+    TRIGGER_TR_GROUP5_INPUT29 = 321, //!< HSIOM Pin input reduction mux - tr_group[5].input[29]
+    TRIGGER_TR_GROUP5_INPUT30 = 322, //!< HSIOM Pin input reduction mux - tr_group[5].input[30]
+    TRIGGER_TR_GROUP5_INPUT31 = 323, //!< HSIOM Pin input reduction mux - tr_group[5].input[31]
+    TRIGGER_TR_GROUP5_INPUT32 = 324, //!< HSIOM Pin input reduction mux - tr_group[5].input[32]
+    TRIGGER_TR_GROUP5_INPUT33 = 325, //!< DMA request reduction mux - tr_group[5].input[33]
+    TRIGGER_TR_GROUP5_INPUT34 = 326, //!< DMA request reduction mux - tr_group[5].input[34]
+    TRIGGER_TR_GROUP5_INPUT35 = 327, //!< Trigger input reduction mux - tr_group[5].input[35]
+    TRIGGER_TR_GROUP5_INPUT36 = 328, //!< Trigger input reduction mux - tr_group[5].input[36]
+    TRIGGER_TR_GROUP5_INPUT37 = 329, //!< Trigger input reduction mux - tr_group[5].input[37]
+    TRIGGER_TR_GROUP5_INPUT38 = 330, //!< Trigger input reduction mux - tr_group[5].input[38]
+    TRIGGER_TR_GROUP5_INPUT39 = 331, //!< Trigger input reduction mux - tr_group[5].input[39]
+    TRIGGER_TR_GROUP5_INPUT40 = 332, //!< Trigger input reduction mux - tr_group[5].input[40]
+    TRIGGER_TR_GROUP5_INPUT41 = 333, //!< Trigger input reduction mux - tr_group[5].input[41]
+    TRIGGER_TR_GROUP5_INPUT42 = 334, //!< Trigger input reduction mux - tr_group[5].input[42]
+    TRIGGER_TR_GROUP6_INPUT1 = 335, //!< Datawire output trigger reduction mux - tr_group[6].input[1]
+    TRIGGER_TR_GROUP6_INPUT2 = 336, //!< Datawire output trigger reduction mux - tr_group[6].input[2]
+    TRIGGER_TR_GROUP6_INPUT3 = 337, //!< Datawire output trigger reduction mux - tr_group[6].input[3]
+    TRIGGER_TR_GROUP6_INPUT4 = 338, //!< Datawire output trigger reduction mux - tr_group[6].input[4]
+    TRIGGER_TR_GROUP6_INPUT5 = 339, //!< Datawire output trigger reduction mux - tr_group[6].input[5]
+    TRIGGER_TR_GROUP6_INPUT6 = 340, //!< Datawire output trigger reduction mux - tr_group[6].input[6]
+    TRIGGER_TR_GROUP6_INPUT7 = 341, //!< Datawire output trigger reduction mux - tr_group[6].input[7]
+    TRIGGER_TR_GROUP6_INPUT8 = 342, //!< Datawire output trigger reduction mux - tr_group[6].input[8]
+    TRIGGER_TR_GROUP6_INPUT9 = 343, //!< TCPWM trigger output reduction mux - tr_group[6].input[9]
+    TRIGGER_TR_GROUP6_INPUT10 = 344, //!< TCPWM trigger output reduction mux - tr_group[6].input[10]
+    TRIGGER_TR_GROUP6_INPUT11 = 345, //!< TCPWM trigger output reduction mux - tr_group[6].input[11]
+    TRIGGER_TR_GROUP6_INPUT12 = 346, //!< TCPWM trigger output reduction mux - tr_group[6].input[12]
+    TRIGGER_TR_GROUP6_INPUT13 = 347, //!< TCPWM trigger output reduction mux - tr_group[6].input[13]
+    TRIGGER_TR_GROUP6_INPUT14 = 348, //!< TCPWM trigger output reduction mux - tr_group[6].input[14]
+    TRIGGER_TR_GROUP6_INPUT15 = 349, //!< TCPWM trigger output reduction mux - tr_group[6].input[15]
+    TRIGGER_TR_GROUP6_INPUT16 = 350, //!< TCPWM trigger output reduction mux - tr_group[6].input[16]
+    TRIGGER_TR_GROUP6_INPUT17 = 351, //!< TCPWM trigger output reduction mux - tr_group[6].input[17]
+    TRIGGER_TR_GROUP6_INPUT18 = 352, //!< TCPWM trigger output reduction mux - tr_group[6].input[18]
+    TRIGGER_TR_GROUP6_INPUT19 = 353, //!< TCPWM trigger output reduction mux - tr_group[6].input[19]
+    TRIGGER_TR_GROUP6_INPUT20 = 354, //!< TCPWM trigger output reduction mux - tr_group[6].input[20]
+    TRIGGER_TR_GROUP6_INPUT21 = 355, //!< TCPWM trigger output reduction mux - tr_group[6].input[21]
+    TRIGGER_TR_GROUP6_INPUT22 = 356, //!< TCPWM trigger output reduction mux - tr_group[6].input[22]
+    TRIGGER_TR_GROUP6_INPUT23 = 357, //!< TCPWM trigger output reduction mux - tr_group[6].input[23]
+    TRIGGER_TR_GROUP6_INPUT24 = 358, //!< TCPWM trigger output reduction mux - tr_group[6].input[24]
+    TRIGGER_TR_GROUP6_INPUT25 = 359, //!< HSIOM Pin input reduction mux - tr_group[6].input[25]
+    TRIGGER_TR_GROUP6_INPUT26 = 360, //!< HSIOM Pin input reduction mux - tr_group[6].input[26]
+    TRIGGER_TR_GROUP6_INPUT27 = 361, //!< HSIOM Pin input reduction mux - tr_group[6].input[27]
+    TRIGGER_TR_GROUP6_INPUT28 = 362, //!< HSIOM Pin input reduction mux - tr_group[6].input[28]
+    TRIGGER_TR_GROUP6_INPUT29 = 363, //!< HSIOM Pin input reduction mux - tr_group[6].input[29]
+    TRIGGER_TR_GROUP6_INPUT30 = 364, //!< HSIOM Pin input reduction mux - tr_group[6].input[30]
+    TRIGGER_TR_GROUP6_INPUT31 = 365, //!< HSIOM Pin input reduction mux - tr_group[6].input[31]
+    TRIGGER_TR_GROUP6_INPUT32 = 366, //!< HSIOM Pin input reduction mux - tr_group[6].input[32]
+    TRIGGER_TR_GROUP6_INPUT33 = 367, //!< DMA request reduction mux - tr_group[6].input[33]
+    TRIGGER_TR_GROUP6_INPUT34 = 368, //!< DMA request reduction mux - tr_group[6].input[34]
+    TRIGGER_TR_GROUP6_INPUT35 = 369, //!< Trigger input reduction mux - tr_group[6].input[35]
+    TRIGGER_TR_GROUP6_INPUT36 = 370, //!< Trigger input reduction mux - tr_group[6].input[36]
+    TRIGGER_TR_GROUP6_INPUT37 = 371, //!< Trigger input reduction mux - tr_group[6].input[37]
+    TRIGGER_TR_GROUP6_INPUT38 = 372, //!< Trigger input reduction mux - tr_group[6].input[38]
+    TRIGGER_TR_GROUP6_INPUT39 = 373, //!< Trigger input reduction mux - tr_group[6].input[39]
+    TRIGGER_TR_GROUP6_INPUT40 = 374, //!< Trigger input reduction mux - tr_group[6].input[40]
+    TRIGGER_TR_GROUP6_INPUT41 = 375, //!< Trigger input reduction mux - tr_group[6].input[41]
+    TRIGGER_TR_GROUP6_INPUT42 = 376, //!< Trigger input reduction mux - tr_group[6].input[42]
+    TRIGGER_TR_GROUP7_INPUT1 = 377, //!< Datawire output trigger reduction mux - tr_group[7].input[1]
+    TRIGGER_TR_GROUP7_INPUT2 = 378, //!< Datawire output trigger reduction mux - tr_group[7].input[2]
+    TRIGGER_TR_GROUP7_INPUT3 = 379, //!< Datawire output trigger reduction mux - tr_group[7].input[3]
+    TRIGGER_TR_GROUP7_INPUT4 = 380, //!< Datawire output trigger reduction mux - tr_group[7].input[4]
+    TRIGGER_TR_GROUP7_INPUT5 = 381, //!< Datawire output trigger reduction mux - tr_group[7].input[5]
+    TRIGGER_TR_GROUP7_INPUT6 = 382, //!< Datawire output trigger reduction mux - tr_group[7].input[6]
+    TRIGGER_TR_GROUP7_INPUT7 = 383, //!< Datawire output trigger reduction mux - tr_group[7].input[7]
+    TRIGGER_TR_GROUP7_INPUT8 = 384, //!< Datawire output trigger reduction mux - tr_group[7].input[8]
+    TRIGGER_TR_GROUP7_INPUT9 = 385, //!< TCPWM trigger output reduction mux - tr_group[7].input[9]
+    TRIGGER_TR_GROUP7_INPUT10 = 386, //!< TCPWM trigger output reduction mux - tr_group[7].input[10]
+    TRIGGER_TR_GROUP7_INPUT11 = 387, //!< TCPWM trigger output reduction mux - tr_group[7].input[11]
+    TRIGGER_TR_GROUP7_INPUT12 = 388, //!< TCPWM trigger output reduction mux - tr_group[7].input[12]
+    TRIGGER_TR_GROUP7_INPUT13 = 389, //!< TCPWM trigger output reduction mux - tr_group[7].input[13]
+    TRIGGER_TR_GROUP7_INPUT14 = 390, //!< TCPWM trigger output reduction mux - tr_group[7].input[14]
+    TRIGGER_TR_GROUP7_INPUT15 = 391, //!< TCPWM trigger output reduction mux - tr_group[7].input[15]
+    TRIGGER_TR_GROUP7_INPUT16 = 392, //!< TCPWM trigger output reduction mux - tr_group[7].input[16]
+    TRIGGER_TR_GROUP7_INPUT17 = 393, //!< TCPWM trigger output reduction mux - tr_group[7].input[17]
+    TRIGGER_TR_GROUP7_INPUT18 = 394, //!< TCPWM trigger output reduction mux - tr_group[7].input[18]
+    TRIGGER_TR_GROUP7_INPUT19 = 395, //!< TCPWM trigger output reduction mux - tr_group[7].input[19]
+    TRIGGER_TR_GROUP7_INPUT20 = 396, //!< TCPWM trigger output reduction mux - tr_group[7].input[20]
+    TRIGGER_TR_GROUP7_INPUT21 = 397, //!< TCPWM trigger output reduction mux - tr_group[7].input[21]
+    TRIGGER_TR_GROUP7_INPUT22 = 398, //!< TCPWM trigger output reduction mux - tr_group[7].input[22]
+    TRIGGER_TR_GROUP7_INPUT23 = 399, //!< TCPWM trigger output reduction mux - tr_group[7].input[23]
+    TRIGGER_TR_GROUP7_INPUT24 = 400, //!< TCPWM trigger output reduction mux - tr_group[7].input[24]
+    TRIGGER_TR_GROUP7_INPUT25 = 401, //!< HSIOM Pin input reduction mux - tr_group[7].input[25]
+    TRIGGER_TR_GROUP7_INPUT26 = 402, //!< HSIOM Pin input reduction mux - tr_group[7].input[26]
+    TRIGGER_TR_GROUP7_INPUT27 = 403, //!< HSIOM Pin input reduction mux - tr_group[7].input[27]
+    TRIGGER_TR_GROUP7_INPUT28 = 404, //!< HSIOM Pin input reduction mux - tr_group[7].input[28]
+    TRIGGER_TR_GROUP7_INPUT29 = 405, //!< HSIOM Pin input reduction mux - tr_group[7].input[29]
+    TRIGGER_TR_GROUP7_INPUT30 = 406, //!< HSIOM Pin input reduction mux - tr_group[7].input[30]
+    TRIGGER_TR_GROUP7_INPUT31 = 407, //!< HSIOM Pin input reduction mux - tr_group[7].input[31]
+    TRIGGER_TR_GROUP7_INPUT32 = 408, //!< HSIOM Pin input reduction mux - tr_group[7].input[32]
+    TRIGGER_TR_GROUP7_INPUT33 = 409, //!< DMA request reduction mux - tr_group[7].input[33]
+    TRIGGER_TR_GROUP7_INPUT34 = 410, //!< DMA request reduction mux - tr_group[7].input[34]
+    TRIGGER_TR_GROUP7_INPUT35 = 411, //!< Trigger input reduction mux - tr_group[7].input[35]
+    TRIGGER_TR_GROUP7_INPUT36 = 412, //!< Trigger input reduction mux - tr_group[7].input[36]
+    TRIGGER_TR_GROUP7_INPUT37 = 413, //!< Trigger input reduction mux - tr_group[7].input[37]
+    TRIGGER_TR_GROUP7_INPUT38 = 414, //!< Trigger input reduction mux - tr_group[7].input[38]
+    TRIGGER_TR_GROUP7_INPUT39 = 415, //!< Trigger input reduction mux - tr_group[7].input[39]
+    TRIGGER_TR_GROUP7_INPUT40 = 416, //!< Trigger input reduction mux - tr_group[7].input[40]
+    TRIGGER_TR_GROUP7_INPUT41 = 417, //!< Trigger input reduction mux - tr_group[7].input[41]
+    TRIGGER_TR_GROUP7_INPUT42 = 418, //!< Trigger input reduction mux - tr_group[7].input[42]
+    TRIGGER_TR_GROUP8_INPUT1 = 419, //!< Datawire output trigger reduction mux - tr_group[8].input[1]
+    TRIGGER_TR_GROUP8_INPUT2 = 420, //!< Datawire output trigger reduction mux - tr_group[8].input[2]
+    TRIGGER_TR_GROUP8_INPUT3 = 421, //!< Datawire output trigger reduction mux - tr_group[8].input[3]
+    TRIGGER_TR_GROUP8_INPUT4 = 422, //!< Datawire output trigger reduction mux - tr_group[8].input[4]
+    TRIGGER_TR_GROUP8_INPUT5 = 423, //!< Datawire output trigger reduction mux - tr_group[8].input[5]
+    TRIGGER_TR_GROUP8_INPUT6 = 424, //!< Datawire output trigger reduction mux - tr_group[8].input[6]
+    TRIGGER_TR_GROUP8_INPUT7 = 425, //!< Datawire output trigger reduction mux - tr_group[8].input[7]
+    TRIGGER_TR_GROUP8_INPUT8 = 426, //!< Datawire output trigger reduction mux - tr_group[8].input[8]
+    TRIGGER_TR_GROUP8_INPUT9 = 427, //!< TCPWM trigger output reduction mux - tr_group[8].input[9]
+    TRIGGER_TR_GROUP8_INPUT10 = 428, //!< TCPWM trigger output reduction mux - tr_group[8].input[10]
+    TRIGGER_TR_GROUP8_INPUT11 = 429, //!< TCPWM trigger output reduction mux - tr_group[8].input[11]
+    TRIGGER_TR_GROUP8_INPUT12 = 430, //!< TCPWM trigger output reduction mux - tr_group[8].input[12]
+    TRIGGER_TR_GROUP8_INPUT13 = 431, //!< TCPWM trigger output reduction mux - tr_group[8].input[13]
+    TRIGGER_TR_GROUP8_INPUT14 = 432, //!< TCPWM trigger output reduction mux - tr_group[8].input[14]
+    TRIGGER_TR_GROUP8_INPUT15 = 433, //!< TCPWM trigger output reduction mux - tr_group[8].input[15]
+    TRIGGER_TR_GROUP8_INPUT16 = 434, //!< TCPWM trigger output reduction mux - tr_group[8].input[16]
+    TRIGGER_TR_GROUP8_INPUT17 = 435, //!< TCPWM trigger output reduction mux - tr_group[8].input[17]
+    TRIGGER_TR_GROUP8_INPUT18 = 436, //!< TCPWM trigger output reduction mux - tr_group[8].input[18]
+    TRIGGER_TR_GROUP8_INPUT19 = 437, //!< TCPWM trigger output reduction mux - tr_group[8].input[19]
+    TRIGGER_TR_GROUP8_INPUT20 = 438, //!< TCPWM trigger output reduction mux - tr_group[8].input[20]
+    TRIGGER_TR_GROUP8_INPUT21 = 439, //!< TCPWM trigger output reduction mux - tr_group[8].input[21]
+    TRIGGER_TR_GROUP8_INPUT22 = 440, //!< TCPWM trigger output reduction mux - tr_group[8].input[22]
+    TRIGGER_TR_GROUP8_INPUT23 = 441, //!< TCPWM trigger output reduction mux - tr_group[8].input[23]
+    TRIGGER_TR_GROUP8_INPUT24 = 442, //!< TCPWM trigger output reduction mux - tr_group[8].input[24]
+    TRIGGER_TR_GROUP8_INPUT25 = 443, //!< HSIOM Pin input reduction mux - tr_group[8].input[25]
+    TRIGGER_TR_GROUP8_INPUT26 = 444, //!< HSIOM Pin input reduction mux - tr_group[8].input[26]
+    TRIGGER_TR_GROUP8_INPUT27 = 445, //!< HSIOM Pin input reduction mux - tr_group[8].input[27]
+    TRIGGER_TR_GROUP8_INPUT28 = 446, //!< HSIOM Pin input reduction mux - tr_group[8].input[28]
+    TRIGGER_TR_GROUP8_INPUT29 = 447, //!< HSIOM Pin input reduction mux - tr_group[8].input[29]
+    TRIGGER_TR_GROUP8_INPUT30 = 448, //!< HSIOM Pin input reduction mux - tr_group[8].input[30]
+    TRIGGER_TR_GROUP8_INPUT31 = 449, //!< HSIOM Pin input reduction mux - tr_group[8].input[31]
+    TRIGGER_TR_GROUP8_INPUT32 = 450, //!< HSIOM Pin input reduction mux - tr_group[8].input[32]
+    TRIGGER_TR_GROUP8_INPUT33 = 451, //!< DMA request reduction mux - tr_group[8].input[33]
+    TRIGGER_TR_GROUP8_INPUT34 = 452, //!< DMA request reduction mux - tr_group[8].input[34]
+    TRIGGER_TR_GROUP8_INPUT35 = 453, //!< Trigger input reduction mux - tr_group[8].input[35]
+    TRIGGER_TR_GROUP8_INPUT36 = 454, //!< Trigger input reduction mux - tr_group[8].input[36]
+    TRIGGER_TR_GROUP8_INPUT37 = 455, //!< Trigger input reduction mux - tr_group[8].input[37]
+    TRIGGER_TR_GROUP8_INPUT38 = 456, //!< Trigger input reduction mux - tr_group[8].input[38]
+    TRIGGER_TR_GROUP8_INPUT39 = 457, //!< Trigger input reduction mux - tr_group[8].input[39]
+    TRIGGER_TR_GROUP8_INPUT40 = 458, //!< Trigger input reduction mux - tr_group[8].input[40]
+    TRIGGER_TR_GROUP8_INPUT41 = 459, //!< Trigger input reduction mux - tr_group[8].input[41]
+    TRIGGER_TR_GROUP8_INPUT42 = 460, //!< Trigger input reduction mux - tr_group[8].input[42]
+    TRIGGER_UDB_TR_DW_ACK0 = 461, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[0]
+    TRIGGER_UDB_TR_DW_ACK1 = 462, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[1]
+    TRIGGER_UDB_TR_DW_ACK2 = 463, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[2]
+    TRIGGER_UDB_TR_DW_ACK3 = 464, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[3]
+    TRIGGER_UDB_TR_DW_ACK4 = 465, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[4]
+    TRIGGER_UDB_TR_DW_ACK5 = 466, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[5]
+    TRIGGER_UDB_TR_DW_ACK6 = 467, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[6]
+    TRIGGER_UDB_TR_DW_ACK7 = 468, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[7]
+    TRIGGER_UDB_TR_IN0 = 469, //!< UDB trigger multiplexer - udb.tr_in[0]
+    TRIGGER_UDB_TR_IN1 = 470, //!< UDB trigger multiplexer - udb.tr_in[1]
+    TRIGGER_USB_DMA_BURSTEND0 = 471, //!< USB DMA burstend multiplexer - usb.dma_burstend[0]
+    TRIGGER_USB_DMA_BURSTEND1 = 472, //!< USB DMA burstend multiplexer - usb.dma_burstend[1]
+    TRIGGER_USB_DMA_BURSTEND2 = 473, //!< USB DMA burstend multiplexer - usb.dma_burstend[2]
+    TRIGGER_USB_DMA_BURSTEND3 = 474, //!< USB DMA burstend multiplexer - usb.dma_burstend[3]
+    TRIGGER_USB_DMA_BURSTEND4 = 475, //!< USB DMA burstend multiplexer - usb.dma_burstend[4]
+    TRIGGER_USB_DMA_BURSTEND5 = 476, //!< USB DMA burstend multiplexer - usb.dma_burstend[5]
+    TRIGGER_USB_DMA_BURSTEND6 = 477, //!< USB DMA burstend multiplexer - usb.dma_burstend[6]
+    TRIGGER_USB_DMA_BURSTEND7 = 478, //!< USB DMA burstend multiplexer - usb.dma_burstend[7]
+} cyhal_trigger_dest_psoc6_01_t;
+
+/** Typedef from device family specific trigger dest to generic trigger dest */
+typedef cyhal_trigger_dest_psoc6_01_t cyhal_dest_t;
+
+/** \cond INTERNAL */
+/** Maps each cyhal_destination_t to a mux index.
+ * If bit 8 of the mux index is set, this denotes that the trigger is a
+ * one to one trigger.
+ */
+extern const uint8_t cyhal_dest_to_mux[479];
+
+/* Maps each cyhal_destination_t to a specific output in its mux */
+extern const uint8_t cyhal_mux_dest_index[479];
+/** \endcond */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+/** \} group_hal_psoc6_triggers_psoc6_01 */
+#endif /* _CYHAL_TRIGGERS_PSOC6_01_H_ */
+
+
+/* [] END OF FILE */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_02.h

@@ -0,0 +1,175 @@
+/***************************************************************************//**
+* \file cyhal_triggers_psoc6_02.h
+*
+* \brief
+* PSoC6_02 family HAL triggers header
+*
+* \note
+* Generator version: 1.5.7254.19579
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYHAL_TRIGGERS_PSOC6_02_H_
+#define _CYHAL_TRIGGERS_PSOC6_02_H_
+
+/**
+ * \addtogroup group_hal_psoc6_triggers_psoc6_02 PSOC6_02
+ * \ingroup group_hal_psoc6_triggers
+ * \{
+ * Trigger connections for psoc6_02
+ */
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/** @brief Name of each output trigger. */
+typedef enum
+{
+    TRIGGER_CPUSS_CTI_TR_IN0 = 0, //!< CPUSS Debug and Profiler trigger multiplexer - cpuss.cti_tr_in[0]
+    TRIGGER_CPUSS_CTI_TR_IN1 = 1, //!< CPUSS Debug and Profiler trigger multiplexer - cpuss.cti_tr_in[1]
+    TRIGGER_CPUSS_DMAC_TR_IN0 = 2, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[0]
+    TRIGGER_CPUSS_DMAC_TR_IN1 = 3, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[1]
+    TRIGGER_CPUSS_DMAC_TR_IN2 = 4, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[2]
+    TRIGGER_CPUSS_DMAC_TR_IN3 = 5, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[3]
+    TRIGGER_CPUSS_DW0_TR_IN0 = 6, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[0]
+    TRIGGER_CPUSS_DW0_TR_IN1 = 7, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[1]
+    TRIGGER_CPUSS_DW0_TR_IN2 = 8, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[2]
+    TRIGGER_CPUSS_DW0_TR_IN3 = 9, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[3]
+    TRIGGER_CPUSS_DW0_TR_IN4 = 10, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[4]
+    TRIGGER_CPUSS_DW0_TR_IN5 = 11, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[5]
+    TRIGGER_CPUSS_DW0_TR_IN6 = 12, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[6]
+    TRIGGER_CPUSS_DW0_TR_IN7 = 13, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[7]
+    TRIGGER_CPUSS_DW0_TR_IN8 = 14, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[8]
+    TRIGGER_CPUSS_DW0_TR_IN9 = 15, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[9]
+    TRIGGER_CPUSS_DW0_TR_IN10 = 16, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[10]
+    TRIGGER_CPUSS_DW0_TR_IN11 = 17, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[11]
+    TRIGGER_CPUSS_DW0_TR_IN12 = 18, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[12]
+    TRIGGER_CPUSS_DW0_TR_IN13 = 19, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[13]
+    TRIGGER_CPUSS_DW0_TR_IN14 = 20, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[14]
+    TRIGGER_CPUSS_DW0_TR_IN15 = 21, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[15]
+    TRIGGER_CPUSS_DW0_TR_IN16 = 22, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[16]
+    TRIGGER_CPUSS_DW0_TR_IN17 = 23, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[17]
+    TRIGGER_CPUSS_DW0_TR_IN18 = 24, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[18]
+    TRIGGER_CPUSS_DW0_TR_IN19 = 25, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[19]
+    TRIGGER_CPUSS_DW0_TR_IN20 = 26, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[20]
+    TRIGGER_CPUSS_DW0_TR_IN21 = 27, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[21]
+    TRIGGER_CPUSS_DW0_TR_IN22 = 28, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[22]
+    TRIGGER_CPUSS_DW0_TR_IN23 = 29, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[23]
+    TRIGGER_CPUSS_DW0_TR_IN24 = 30, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[24]
+    TRIGGER_CPUSS_DW0_TR_IN25 = 31, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[25]
+    TRIGGER_CPUSS_DW0_TR_IN26 = 32, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[26]
+    TRIGGER_CPUSS_DW0_TR_IN27 = 33, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[27]
+    TRIGGER_CPUSS_DW0_TR_IN28 = 34, //!< SAR to PDMA0 direct connect - cpuss.dw0_tr_in[28]
+    TRIGGER_CPUSS_DW1_TR_IN0 = 35, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[0]
+    TRIGGER_CPUSS_DW1_TR_IN1 = 36, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[1]
+    TRIGGER_CPUSS_DW1_TR_IN2 = 37, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[2]
+    TRIGGER_CPUSS_DW1_TR_IN3 = 38, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[3]
+    TRIGGER_CPUSS_DW1_TR_IN4 = 39, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[4]
+    TRIGGER_CPUSS_DW1_TR_IN5 = 40, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[5]
+    TRIGGER_CPUSS_DW1_TR_IN6 = 41, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[6]
+    TRIGGER_CPUSS_DW1_TR_IN7 = 42, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[7]
+    TRIGGER_CPUSS_DW1_TR_IN8 = 43, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[8]
+    TRIGGER_CPUSS_DW1_TR_IN9 = 44, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[9]
+    TRIGGER_CPUSS_DW1_TR_IN10 = 45, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[10]
+    TRIGGER_CPUSS_DW1_TR_IN11 = 46, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[11]
+    TRIGGER_CPUSS_DW1_TR_IN12 = 47, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[12]
+    TRIGGER_CPUSS_DW1_TR_IN13 = 48, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[13]
+    TRIGGER_CPUSS_DW1_TR_IN14 = 49, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[14]
+    TRIGGER_CPUSS_DW1_TR_IN15 = 50, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[15]
+    TRIGGER_CPUSS_DW1_TR_IN16 = 51, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[16]
+    TRIGGER_CPUSS_DW1_TR_IN17 = 52, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[17]
+    TRIGGER_CPUSS_DW1_TR_IN18 = 53, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[18]
+    TRIGGER_CPUSS_DW1_TR_IN19 = 54, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[19]
+    TRIGGER_CPUSS_DW1_TR_IN20 = 55, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[20]
+    TRIGGER_CPUSS_DW1_TR_IN21 = 56, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[21]
+    TRIGGER_CPUSS_DW1_TR_IN22 = 57, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[22]
+    TRIGGER_CPUSS_DW1_TR_IN23 = 58, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[23]
+    TRIGGER_CPUSS_DW1_TR_IN24 = 59, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[24]
+    TRIGGER_CPUSS_DW1_TR_IN25 = 60, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[25]
+    TRIGGER_CPUSS_DW1_TR_IN26 = 61, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[26]
+    TRIGGER_CPUSS_DW1_TR_IN27 = 62, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[27]
+    TRIGGER_CPUSS_DW1_TR_IN28 = 63, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[28]
+    TRIGGER_CSD_DSI_START = 64, //!< Capsense trigger multiplexer - csd.dsi_start
+    TRIGGER_PASS_TR_SAR_IN = 65, //!< ADC trigger multiplexer - pass.tr_sar_in
+    TRIGGER_PERI_TR_DBG_FREEZE = 66, //!< PERI Freeze trigger multiplexer - peri.tr_dbg_freeze
+    TRIGGER_PERI_TR_IO_OUTPUT0 = 67, //!< HSIOM trigger multiplexer - peri.tr_io_output[0]
+    TRIGGER_PERI_TR_IO_OUTPUT1 = 68, //!< HSIOM trigger multiplexer - peri.tr_io_output[1]
+    TRIGGER_PROFILE_TR_START = 69, //!< CPUSS Debug and Profiler trigger multiplexer - profile.tr_start
+    TRIGGER_PROFILE_TR_STOP = 70, //!< CPUSS Debug and Profiler trigger multiplexer - profile.tr_stop
+    TRIGGER_TCPWM0_TR_IN0 = 71, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[0]
+    TRIGGER_TCPWM0_TR_IN1 = 72, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[1]
+    TRIGGER_TCPWM0_TR_IN2 = 73, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[2]
+    TRIGGER_TCPWM0_TR_IN3 = 74, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[3]
+    TRIGGER_TCPWM0_TR_IN4 = 75, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[4]
+    TRIGGER_TCPWM0_TR_IN5 = 76, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[5]
+    TRIGGER_TCPWM0_TR_IN6 = 77, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[6]
+    TRIGGER_TCPWM0_TR_IN7 = 78, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[7]
+    TRIGGER_TCPWM0_TR_IN8 = 79, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[8]
+    TRIGGER_TCPWM0_TR_IN9 = 80, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[9]
+    TRIGGER_TCPWM0_TR_IN10 = 81, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[10]
+    TRIGGER_TCPWM0_TR_IN11 = 82, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[11]
+    TRIGGER_TCPWM0_TR_IN12 = 83, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[12]
+    TRIGGER_TCPWM0_TR_IN13 = 84, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[13]
+    TRIGGER_TCPWM1_TR_IN0 = 85, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[0]
+    TRIGGER_TCPWM1_TR_IN1 = 86, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[1]
+    TRIGGER_TCPWM1_TR_IN2 = 87, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[2]
+    TRIGGER_TCPWM1_TR_IN3 = 88, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[3]
+    TRIGGER_TCPWM1_TR_IN4 = 89, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[4]
+    TRIGGER_TCPWM1_TR_IN5 = 90, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[5]
+    TRIGGER_TCPWM1_TR_IN6 = 91, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[6]
+    TRIGGER_TCPWM1_TR_IN7 = 92, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[7]
+    TRIGGER_TCPWM1_TR_IN8 = 93, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[8]
+    TRIGGER_TCPWM1_TR_IN9 = 94, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[9]
+    TRIGGER_TCPWM1_TR_IN10 = 95, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[10]
+    TRIGGER_TCPWM1_TR_IN11 = 96, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[11]
+    TRIGGER_TCPWM1_TR_IN12 = 97, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[12]
+    TRIGGER_TCPWM1_TR_IN13 = 98, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[13]
+    TRIGGER_USB_DMA_BURSTEND0 = 99, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[0]
+    TRIGGER_USB_DMA_BURSTEND1 = 100, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[1]
+    TRIGGER_USB_DMA_BURSTEND2 = 101, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[2]
+    TRIGGER_USB_DMA_BURSTEND3 = 102, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[3]
+    TRIGGER_USB_DMA_BURSTEND4 = 103, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[4]
+    TRIGGER_USB_DMA_BURSTEND5 = 104, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[5]
+    TRIGGER_USB_DMA_BURSTEND6 = 105, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[6]
+    TRIGGER_USB_DMA_BURSTEND7 = 106, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[7]
+} cyhal_trigger_dest_psoc6_02_t;
+
+/** Typedef from device family specific trigger dest to generic trigger dest */
+typedef cyhal_trigger_dest_psoc6_02_t cyhal_dest_t;
+
+/** \cond INTERNAL */
+/** Maps each cyhal_destination_t to a mux index.
+ * If bit 8 of the mux index is set, this denotes that the trigger is a
+ * one to one trigger.
+ */
+extern const uint8_t cyhal_dest_to_mux[107];
+
+/* Maps each cyhal_destination_t to a specific output in its mux */
+extern const uint8_t cyhal_mux_dest_index[107];
+/** \endcond */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+/** \} group_hal_psoc6_triggers_psoc6_02 */
+#endif /* _CYHAL_TRIGGERS_PSOC6_02_H_ */
+
+
+/* [] END OF FILE */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_03.h

@@ -0,0 +1,176 @@
+/***************************************************************************//**
+* \file cyhal_triggers_psoc6_03.h
+*
+* \brief
+* PSoC6_03 family HAL triggers header
+*
+* \note
+* Generator version: 1.5.7254.19579
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYHAL_TRIGGERS_PSOC6_03_H_
+#define _CYHAL_TRIGGERS_PSOC6_03_H_
+
+/**
+ * \addtogroup group_hal_psoc6_triggers_psoc6_03 PSOC6_03
+ * \ingroup group_hal_psoc6_triggers
+ * \{
+ * Trigger connections for psoc6_03
+ */
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/** @brief Name of each output trigger. */
+typedef enum
+{
+    TRIGGER_CANFD0_TR_DBG_DMA_ACK0 = 0, //!< CAN DW0 triggers (from DW back to CAN) - canfd[0].tr_dbg_dma_ack[0]
+    TRIGGER_CANFD0_TR_EVT_SWT_IN0 = 1, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[0]
+    TRIGGER_CPUSS_CTI_TR_IN0 = 2, //!< CPUSS Debug trigger multiplexer - cpuss.cti_tr_in[0]
+    TRIGGER_CPUSS_CTI_TR_IN1 = 3, //!< CPUSS Debug trigger multiplexer - cpuss.cti_tr_in[1]
+    TRIGGER_CPUSS_DMAC_TR_IN0 = 4, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[0]
+    TRIGGER_CPUSS_DMAC_TR_IN1 = 5, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[1]
+    TRIGGER_CPUSS_DW0_TR_IN0 = 6, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[0]
+    TRIGGER_CPUSS_DW0_TR_IN1 = 7, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[1]
+    TRIGGER_CPUSS_DW0_TR_IN2 = 8, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[2]
+    TRIGGER_CPUSS_DW0_TR_IN3 = 9, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[3]
+    TRIGGER_CPUSS_DW0_TR_IN4 = 10, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[4]
+    TRIGGER_CPUSS_DW0_TR_IN5 = 11, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[5]
+    TRIGGER_CPUSS_DW0_TR_IN6 = 12, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[6]
+    TRIGGER_CPUSS_DW0_TR_IN7 = 13, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[7]
+    TRIGGER_CPUSS_DW0_TR_IN8 = 14, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[8]
+    TRIGGER_CPUSS_DW0_TR_IN9 = 15, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[9]
+    TRIGGER_CPUSS_DW0_TR_IN10 = 16, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[10]
+    TRIGGER_CPUSS_DW0_TR_IN11 = 17, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[11]
+    TRIGGER_CPUSS_DW0_TR_IN12 = 18, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[12]
+    TRIGGER_CPUSS_DW0_TR_IN13 = 19, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[13]
+    TRIGGER_CPUSS_DW0_TR_IN14 = 20, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[14]
+    TRIGGER_CPUSS_DW0_TR_IN15 = 21, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[15]
+    TRIGGER_CPUSS_DW0_TR_IN16 = 22, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[16]
+    TRIGGER_CPUSS_DW0_TR_IN17 = 23, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[17]
+    TRIGGER_CPUSS_DW0_TR_IN18 = 24, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[18]
+    TRIGGER_CPUSS_DW0_TR_IN19 = 25, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[19]
+    TRIGGER_CPUSS_DW0_TR_IN20 = 26, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[20]
+    TRIGGER_CPUSS_DW0_TR_IN21 = 27, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[21]
+    TRIGGER_CPUSS_DW0_TR_IN22 = 28, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[22]
+    TRIGGER_CPUSS_DW0_TR_IN23 = 29, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[23]
+    TRIGGER_CPUSS_DW0_TR_IN24 = 30, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[24]
+    TRIGGER_CPUSS_DW0_TR_IN25 = 31, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[25]
+    TRIGGER_CPUSS_DW0_TR_IN26 = 32, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[26]
+    TRIGGER_CPUSS_DW0_TR_IN27 = 33, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[27]
+    TRIGGER_CPUSS_DW0_TR_IN28 = 34, //!< SAR to PDMA1 direct connect - cpuss.dw0_tr_in[28]
+    TRIGGER_CPUSS_DW1_TR_IN0 = 35, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[0]
+    TRIGGER_CPUSS_DW1_TR_IN1 = 36, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[1]
+    TRIGGER_CPUSS_DW1_TR_IN2 = 37, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[2]
+    TRIGGER_CPUSS_DW1_TR_IN3 = 38, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[3]
+    TRIGGER_CPUSS_DW1_TR_IN4 = 39, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[4]
+    TRIGGER_CPUSS_DW1_TR_IN5 = 40, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[5]
+    TRIGGER_CPUSS_DW1_TR_IN6 = 41, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[6]
+    TRIGGER_CPUSS_DW1_TR_IN7 = 42, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[7]
+    TRIGGER_CPUSS_DW1_TR_IN8 = 43, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[8]
+    TRIGGER_CPUSS_DW1_TR_IN9 = 44, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[9]
+    TRIGGER_CPUSS_DW1_TR_IN10 = 45, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[10]
+    TRIGGER_CPUSS_DW1_TR_IN11 = 46, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[11]
+    TRIGGER_CPUSS_DW1_TR_IN12 = 47, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[12]
+    TRIGGER_CPUSS_DW1_TR_IN13 = 48, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[13]
+    TRIGGER_CPUSS_DW1_TR_IN14 = 49, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[14]
+    TRIGGER_CPUSS_DW1_TR_IN15 = 50, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[15]
+    TRIGGER_CPUSS_DW1_TR_IN16 = 51, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[16]
+    TRIGGER_CPUSS_DW1_TR_IN17 = 52, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[17]
+    TRIGGER_CPUSS_DW1_TR_IN18 = 53, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[18]
+    TRIGGER_CPUSS_DW1_TR_IN19 = 54, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[19]
+    TRIGGER_CPUSS_DW1_TR_IN20 = 55, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[20]
+    TRIGGER_CPUSS_DW1_TR_IN21 = 56, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[21]
+    TRIGGER_CPUSS_DW1_TR_IN22 = 57, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[22]
+    TRIGGER_CPUSS_DW1_TR_IN23 = 58, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[23]
+    TRIGGER_CPUSS_DW1_TR_IN24 = 59, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[24]
+    TRIGGER_CPUSS_DW1_TR_IN25 = 60, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[25]
+    TRIGGER_CPUSS_DW1_TR_IN26 = 61, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[26]
+    TRIGGER_CPUSS_DW1_TR_IN27 = 62, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[27]
+    TRIGGER_CPUSS_DW1_TR_IN28 = 63, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[28]
+    TRIGGER_CPUSS_DW1_TR_IN29 = 64, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[29]
+    TRIGGER_CPUSS_DW1_TR_IN30 = 65, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[30]
+    TRIGGER_CPUSS_DW1_TR_IN31 = 66, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[31]
+    TRIGGER_CSD_DSI_START = 67, //!< Capsense trigger multiplexer - csd.dsi_start
+    TRIGGER_PASS_TR_SAR_IN = 68, //!< ADC trigger multiplexer - pass.tr_sar_in
+    TRIGGER_PERI_TR_DBG_FREEZE = 69, //!< PERI Freeze trigger multiplexer - peri.tr_dbg_freeze
+    TRIGGER_PERI_TR_IO_OUTPUT0 = 70, //!< HSIOM trigger multiplexer - peri.tr_io_output[0]
+    TRIGGER_PERI_TR_IO_OUTPUT1 = 71, //!< HSIOM trigger multiplexer - peri.tr_io_output[1]
+    TRIGGER_TCPWM0_TR_IN0 = 72, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[0]
+    TRIGGER_TCPWM0_TR_IN1 = 73, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[1]
+    TRIGGER_TCPWM0_TR_IN2 = 74, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[2]
+    TRIGGER_TCPWM0_TR_IN3 = 75, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[3]
+    TRIGGER_TCPWM0_TR_IN4 = 76, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[4]
+    TRIGGER_TCPWM0_TR_IN5 = 77, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[5]
+    TRIGGER_TCPWM0_TR_IN6 = 78, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[6]
+    TRIGGER_TCPWM0_TR_IN7 = 79, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[7]
+    TRIGGER_TCPWM0_TR_IN8 = 80, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[8]
+    TRIGGER_TCPWM0_TR_IN9 = 81, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[9]
+    TRIGGER_TCPWM0_TR_IN10 = 82, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[10]
+    TRIGGER_TCPWM0_TR_IN11 = 83, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[11]
+    TRIGGER_TCPWM0_TR_IN12 = 84, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[12]
+    TRIGGER_TCPWM0_TR_IN13 = 85, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[13]
+    TRIGGER_TCPWM1_TR_IN0 = 86, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[0]
+    TRIGGER_TCPWM1_TR_IN1 = 87, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[1]
+    TRIGGER_TCPWM1_TR_IN2 = 88, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[2]
+    TRIGGER_TCPWM1_TR_IN3 = 89, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[3]
+    TRIGGER_TCPWM1_TR_IN4 = 90, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[4]
+    TRIGGER_TCPWM1_TR_IN5 = 91, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[5]
+    TRIGGER_TCPWM1_TR_IN6 = 92, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[6]
+    TRIGGER_TCPWM1_TR_IN7 = 93, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[7]
+    TRIGGER_TCPWM1_TR_IN8 = 94, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[8]
+    TRIGGER_TCPWM1_TR_IN9 = 95, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[9]
+    TRIGGER_TCPWM1_TR_IN10 = 96, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[10]
+    TRIGGER_TCPWM1_TR_IN11 = 97, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[11]
+    TRIGGER_TCPWM1_TR_IN12 = 98, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[12]
+    TRIGGER_TCPWM1_TR_IN13 = 99, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[13]
+    TRIGGER_USB_DMA_BURSTEND0 = 100, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[0]
+    TRIGGER_USB_DMA_BURSTEND1 = 101, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[1]
+    TRIGGER_USB_DMA_BURSTEND2 = 102, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[2]
+    TRIGGER_USB_DMA_BURSTEND3 = 103, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[3]
+    TRIGGER_USB_DMA_BURSTEND4 = 104, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[4]
+    TRIGGER_USB_DMA_BURSTEND5 = 105, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[5]
+    TRIGGER_USB_DMA_BURSTEND6 = 106, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[6]
+    TRIGGER_USB_DMA_BURSTEND7 = 107, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[7]
+} cyhal_trigger_dest_psoc6_03_t;
+
+/** Typedef from device family specific trigger dest to generic trigger dest */
+typedef cyhal_trigger_dest_psoc6_03_t cyhal_dest_t;
+
+/** \cond INTERNAL */
+/** Maps each cyhal_destination_t to a mux index.
+ * If bit 8 of the mux index is set, this denotes that the trigger is a
+ * one to one trigger.
+ */
+extern const uint8_t cyhal_dest_to_mux[108];
+
+/* Maps each cyhal_destination_t to a specific output in its mux */
+extern const uint8_t cyhal_mux_dest_index[108];
+/** \endcond */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+/** \} group_hal_psoc6_triggers_psoc6_03 */
+#endif /* _CYHAL_TRIGGERS_PSOC6_03_H_ */
+
+
+/* [] END OF FILE */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_adc.c

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -185,7 +185,7 @@ cy_rslt_t cyhal_adc_init(cyhal_adc_t *obj, cyhal_gpio_t pin, const cyhal_clock_d
 
     cy_rslt_t result = CY_RSLT_SUCCESS;
 
-    if (CYHAL_NC_PIN_VALUE == pin)    
+    if (CYHAL_NC_PIN_VALUE == pin)
         result = CYHAL_ADC_RSLT_BAD_ARGUMENT;
 
     if (CY_RSLT_SUCCESS == result)
@@ -228,7 +228,7 @@ cy_rslt_t cyhal_adc_init(cyhal_adc_t *obj, cyhal_gpio_t pin, const cyhal_clock_d
     }
 
     if (CY_RSLT_SUCCESS == result)
-    {    
+    {
         if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, obj->clock.div_type, obj->clock.div_num))
             result = CYHAL_ADC_RSLT_FAILED_CLOCK;
     }
@@ -355,7 +355,7 @@ void cyhal_adc_channel_free(cyhal_adc_channel_t *obj)
         Cy_SAR_SetSwitchSarSeqCtrl(obj->adc->base, mux_ctrl, CY_SAR_SWITCH_SEQ_CTRL_DISABLE);
 
         obj->adc->base->CHAN_CONFIG[obj->channel_idx] = 0;
-        cyhal_gpio_free(obj->pin);
+        cyhal_utils_release_if_used(&(obj->pin));
         obj->adc = NULL;
     }
 }

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_analog_common.c

@@ -7,7 +7,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_crc.c

@@ -7,7 +7,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_crypto_common.c

@@ -7,7 +7,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dac.c

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -148,11 +148,7 @@ void cyhal_dac_free(cyhal_dac_t *obj)
 
         cyhal_hwmgr_free(&obj->resource);
 
-        if(obj->pin != CYHAL_NC_PIN_VALUE)
+        cyhal_utils_release_if_used(&(obj->pin));
-        {
-            cyhal_gpio_free(obj->pin);
-            obj->pin = CYHAL_NC_PIN_VALUE;
-        }
 
         obj->base = NULL;
     }

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma.c

@@ -0,0 +1,206 @@
+/***************************************************************************//**
+* \file cyhal_dma.c
+*
+* \brief
+* Implements a high level interface for interacting with the Cypress DMA.
+* This implementation abstracts out the chip specific details. If any chip specific
+* functionality is necessary, or performance is critical the low level functions
+* can be used directly.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cyhal_dma_dmac.h"
+#include "cyhal_dma_dw.h"
+#include "cyhal_hwmgr.h"
+#include "cyhal_system.h"
+#include "cyhal_utils.h"
+
+/**
+* \addtogroup group_hal_dma DMA (Direct Memory Access)
+* \ingroup group_hal
+* \{
+*/
+
+#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+cy_rslt_t cyhal_dma_init(cyhal_dma_t *obj, uint8_t priority, cyhal_dma_direction_t direction)
+{
+    CY_ASSERT(NULL != obj);
+
+#if !defined(CY_IP_M4CPUSS_DMAC) && defined(CY_IP_M4CPUSS_DMA)
+    /* Only DW available. Ignore direction for purpose of choosing DMA type. */
+    CY_UNUSED_PARAMETER(direction);
+    return cyhal_dma_init_dw(obj, priority);
+#elif defined(CY_IP_M4CPUSS_DMAC) && !defined(CY_IP_M4CPUSS_DMA)
+    /* Only DMAC available. Ignore direction for purpose of choosing DMA type. */
+    CY_UNUSED_PARAMETER(direction);
+    return cyhal_dma_init_dmac(obj, priority);
+#else
+    /* DMAC is designed with high memory bandwidth for memory to memory
+     * transfers so prefer it when direction is MEM2MEM. Otherwise prefer
+     * Datawire as it is designed for low latency memory to peripheral or
+     * peripheral to memory transfers. Note: Both DMA types can handle any
+     * direction value so using a non-ideal DMA type is ok.*/
+    cy_rslt_t rslt;
+    if(direction == CYHAL_DMA_DIRECTION_MEM2MEM)
+    {
+        rslt = cyhal_dma_init_dmac(obj, priority);
+        /* If no DMAC channels are available fall back on DW. */
+        if(CYHAL_HWMGR_RSLT_ERR_NONE_FREE == rslt)
+            rslt = cyhal_dma_init_dw(obj, priority);
+    }
+    else
+    {
+        rslt = cyhal_dma_init_dw(obj, priority);
+        /* If no DW channels are available fall back on DMAC. */
+        if(CYHAL_HWMGR_RSLT_ERR_NONE_FREE == rslt)
+            rslt = cyhal_dma_init_dmac(obj, priority);
+    }
+    return rslt;
+#endif
+}
+
+void cyhal_dma_free(cyhal_dma_t *obj)
+{
+    CY_ASSERT(NULL != obj);
+
+    CY_ASSERT(!cyhal_dma_is_busy(obj));
+
+#ifdef CY_IP_M4CPUSS_DMAC
+    if(obj->resource.type == CYHAL_RSC_DMA)
+    {
+        cyhal_dma_free_dmac(obj);
+    }
+#endif
+#ifdef CY_IP_M4CPUSS_DMA
+    if(obj->resource.type == CYHAL_RSC_DW)
+    {
+        cyhal_dma_free_dw(obj);
+    }
+#endif
+}
+
+cy_rslt_t cyhal_dma_configure(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg)
+{
+    CY_ASSERT(NULL != obj);
+
+#ifdef CY_IP_M4CPUSS_DMAC
+    if(obj->resource.type == CYHAL_RSC_DMA)
+    {
+        return cyhal_dma_configure_dmac(obj, cfg);
+    }
+#endif
+#ifdef CY_IP_M4CPUSS_DMA
+    if(obj->resource.type == CYHAL_RSC_DW)
+    {
+        return cyhal_dma_configure_dw(obj, cfg);
+    }
+#endif
+
+    /* Control should never reach here but return value anyway to appease
+     * compilers */
+    CY_ASSERT(false);
+    return CYHAL_DMA_RSLT_FATAL_UNSUPPORTED_HARDWARE;
+}
+
+cy_rslt_t cyhal_dma_start_transfer(cyhal_dma_t *obj)
+{
+    CY_ASSERT(NULL != obj);
+
+#ifdef CY_IP_M4CPUSS_DMAC
+    if(obj->resource.type == CYHAL_RSC_DMA)
+    {
+        return cyhal_dma_start_transfer_dmac(obj);
+    }
+#endif
+#ifdef CY_IP_M4CPUSS_DMA
+    if(obj->resource.type == CYHAL_RSC_DW)
+    {
+        return cyhal_dma_start_transfer_dw(obj);
+    }
+#endif
+
+    /* Control should never reach here but return value anyway to appease
+     * compilers */
+    CY_ASSERT(false);
+    return CYHAL_DMA_RSLT_FATAL_UNSUPPORTED_HARDWARE;
+}
+
+bool cyhal_dma_is_busy(cyhal_dma_t *obj)
+{
+    CY_ASSERT(NULL != obj);
+
+#ifdef CY_IP_M4CPUSS_DMAC
+    if(obj->resource.type == CYHAL_RSC_DMA)
+    {
+        return cyhal_dma_is_busy_dmac(obj);
+    }
+#endif
+#ifdef CY_IP_M4CPUSS_DMA
+    if(obj->resource.type == CYHAL_RSC_DW)
+    {
+        return cyhal_dma_is_busy_dw(obj);
+    }
+#endif
+
+    /* Control should never reach here but return value anyway to appease
+     * compilers */
+    CY_ASSERT(false);
+    return CYHAL_DMA_RSLT_FATAL_UNSUPPORTED_HARDWARE;
+}
+
+void cyhal_dma_register_callback(cyhal_dma_t *obj, cyhal_dma_event_callback_t callback, void *callback_arg)
+{
+    CY_ASSERT(NULL != obj);
+
+    uint32_t saved_intr_status = cyhal_system_critical_section_enter();
+    obj->callback_data.callback = (cy_israddress)callback;
+    obj->callback_data.callback_arg = callback_arg;
+    cyhal_system_critical_section_exit(saved_intr_status);
+}
+
+void cyhal_dma_enable_event(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intrPriority, bool enable)
+{
+    CY_ASSERT(NULL != obj);
+
+#ifdef CY_IP_M4CPUSS_DMAC
+    if(obj->resource.type == CYHAL_RSC_DMA)
+    {
+        cyhal_dma_enable_event_dmac(obj, event, intrPriority, enable);
+    }
+#endif
+#ifdef CY_IP_M4CPUSS_DMA
+    if(obj->resource.type == CYHAL_RSC_DW)
+    {
+        cyhal_dma_enable_event_dw(obj, event, intrPriority, enable);
+    }
+#endif
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) */
+
+/** \} group_hal_dma */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma_dmac.c

@@ -0,0 +1,364 @@
+/***************************************************************************//**
+* \file cyhal_dma_dmac.c
+*
+* \brief
+* Implements a high level interface for interacting with the Cypress DMAC.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cyhal_dma.h"
+#include "cyhal_dma_dmac.h"
+#include "cyhal_dma_impl.h"
+#include "cyhal_hwmgr.h"
+#include "cyhal_system.h"
+#include "cyhal_utils.h"
+#include "cyhal_triggers.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#ifdef CY_IP_M4CPUSS_DMAC
+
+static cyhal_dma_t* cyhal_dmac_config_structs[CPUSS_DMAC_CH_NR];
+
+/** Default dmac descriptor config */
+static const cy_stc_dmac_descriptor_config_t default_descriptor_config_dmac =
+{
+    .retrigger = CY_DMAC_RETRIG_IM,
+    .interruptType = CY_DMAC_DESCR,
+    .triggerOutType = CY_DMAC_DESCR_CHAIN,
+    .channelState = CY_DMAC_CHANNEL_ENABLED,
+    .triggerInType = CY_DMAC_DESCR,
+    .dataPrefetch = false,
+    .dataSize = CY_DMAC_WORD,
+    .srcTransferSize = CY_DMAC_TRANSFER_SIZE_DATA,
+    .dstTransferSize = CY_DMAC_TRANSFER_SIZE_DATA,
+    .descriptorType = CY_DMAC_1D_TRANSFER,
+    .srcAddress = 0,
+    .dstAddress = 0,
+    .srcXincrement = 1U,
+    .dstXincrement = 1U,
+    .xCount = 1UL,
+    .srcYincrement = 0U,
+    .dstYincrement = 0U,
+    .yCount = 1UL,
+    .nextDescriptor = 0,
+};
+
+/** Default dmac channel config */
+static const cy_stc_dmac_channel_config_t default_channel_config_dmac =
+{
+    .descriptor = 0,
+    .priority = 1,
+    .enable = false,
+    .bufferable = false,
+};
+
+/** Sets the dmac configuration struct */
+static inline void cyhal_dma_set_dmac_obj(cyhal_dma_t *obj)
+{
+    cyhal_dmac_config_structs[obj->resource.block_num * CPUSS_DMAC_CH_NR + obj->resource.channel_num] = obj;
+}
+
+/** Zeros the dmac configuration struct */
+static inline void cyhal_dma_free_dmac_obj(cyhal_dma_t *obj)
+{
+    cyhal_dmac_config_structs[obj->resource.block_num * CPUSS_DMAC_CH_NR + obj->resource.channel_num] = NULL;
+}
+
+/** Gets the dmac configuration struct from block and channel */
+static inline cyhal_dma_t* cyhal_dma_get_dmac_obj(uint8_t block, uint8_t channel)
+{
+    return cyhal_dmac_config_structs[block * CPUSS_DMAC_CH_NR + channel];
+}
+
+/** Gets the dmac block number from irq number */
+/** This should never be called from a non-dma IRQn */
+static inline uint8_t cyhal_dma_get_dmac_block_from_irqn(IRQn_Type irqn)
+{
+    /* Since there is only one dmac block this function always returns 0. diff
+     * is calculated here only to verify that this was called from a valid
+     * IRQn. */
+    CY_UNUSED uint8_t diff = irqn - cpuss_interrupts_dmac_0_IRQn;
+
+    CY_ASSERT(diff < CPUSS_DMAC_CH_NR);
+
+    return 0;
+}
+
+/** Gets the dmac channel number from irq number */
+/** This should never be called from a non-dma IRQn */
+static inline uint8_t cyhal_dma_get_dmac_channel_from_irqn(IRQn_Type irqn)
+{
+    uint8_t diff = irqn - cpuss_interrupts_dmac_0_IRQn;
+
+    CY_ASSERT(diff < CPUSS_DMAC_CH_NR);
+
+    return diff;
+}
+
+/** Gets the irqn corresponding to a particular cyhal_dma_t config struct */
+static inline IRQn_Type cyhal_dma_get_dmac_irqn(cyhal_dma_t *obj)
+{
+    return (IRQn_Type)((uint8_t)cpuss_interrupts_dmac_0_IRQn + (obj->resource.block_num * CPUSS_DMAC_CH_NR + obj->resource.channel_num));
+}
+
+/** Gets the dmac base pointer from block number */
+static inline DMAC_Type* cyhal_dma_get_dmac_base(uint8_t block_num)
+{
+    return DMAC;
+}
+
+/** Uses tables provided as part of the hal interconnect driver to determine mux
+ * trigger group and mux trigger index and then construct the trigger line
+ * input parameter to Cy_TrigMux_SwTrigger. */
+static inline uint32_t cyhal_dma_get_dmac_trigger_line(uint8_t block_num, uint8_t channel_num)
+{
+    /* cyhal_dest_t triggers are guaranteed to be sorted by trigger type, block
+     * num, then channel num, therefore, we can just directly find the proper
+     * trigger by calculating an offset. */
+    cyhal_dest_t trigger = (cyhal_dest_t)(TRIGGER_CPUSS_DMAC_TR_IN0 + (block_num * CPUSS_DMAC_CH_NR) + channel_num);
+
+    /* One to one triggers have bit 8 set in cyhal_dest_to_mux but
+     * Cy_TrigMux_SwTrigger wants the trigger group field to have bit 5 set to
+     * denote one to one triggers. */
+    uint8_t trig_group = cyhal_dest_to_mux[trigger];
+    /* If hal one to one triggers bit is set: mask it out and set pdl one to
+     * one bit */
+    if(trig_group & HAL_TRIGGERS_1TO1_MASK)
+        trig_group = (trig_group & ~HAL_TRIGGERS_1TO1_MASK) | PDL_TRIGGERS_1TO1_MASK;
+
+    /* Construct trigger line which consists of three fields packed into a
+     * uint32_t:
+     * Bits   30: Input/output bit. Set to 1 for output.
+     * Bits 12-8: Trigger group selection.
+     * Bits  7-0: Select the output trigger number in the trigger group. */
+    return PERI_TR_CMD_OUT_SEL_Msk | trig_group << 8 | cyhal_mux_dest_index[trigger];
+}
+
+/** Convert PDL interrupt cause to hal dma event */
+static inline cyhal_dma_event_t cyhal_dma_convert_dmac_interrupt_cause(uint32_t cause)
+{
+    switch(cause)
+    {
+        case CY_DMAC_INTR_COMPLETION:
+            return CYHAL_DMA_TRANSFER_COMPLETE;
+        case CY_DMAC_INTR_SRC_BUS_ERROR:
+            return CYHAL_DMA_SRC_BUS_ERROR;
+        case CY_DMAC_INTR_DST_BUS_ERROR:
+            return CYHAL_DMA_DST_BUS_ERROR;
+        case CY_DMAC_INTR_SRC_MISAL:
+            return CYHAL_DMA_SRC_MISAL;
+        case CY_DMAC_INTR_DST_MISAL:
+            return CYHAL_DMA_DST_MISAL;
+        case CY_DMAC_INTR_CURR_PTR_NULL:
+            return CYHAL_DMA_CURR_PTR_NULL;
+        case CY_DMAC_INTR_ACTIVE_CH_DISABLED:
+            return CYHAL_DMA_ACTIVE_CH_DISABLED;
+        case CY_DMAC_INTR_DESCR_BUS_ERROR:
+            return CYHAL_DMA_DESCR_BUS_ERROR;
+        default:
+            return CYHAL_DMA_NO_INTR;
+    }
+}
+
+/** DMAC irq handler */
+static void cyhal_dma_irq_handler_dmac(void)
+{
+    /* Use irqn to get appropriate config structure */
+    uint8_t block = cyhal_dma_get_dmac_block_from_irqn(CYHAL_GET_CURRENT_IRQN());
+    uint8_t channel = cyhal_dma_get_dmac_channel_from_irqn(CYHAL_GET_CURRENT_IRQN());
+    cyhal_dma_t *obj = cyhal_dma_get_dmac_obj(block, channel);
+
+    /* Get interrupt type and call users event callback if they have enabled that event */
+    uint32_t cause = Cy_DMAC_Channel_GetInterruptStatusMasked(cyhal_dma_get_dmac_base(block), channel);
+    cyhal_dma_event_t event_type = cyhal_dma_convert_dmac_interrupt_cause(cause);
+    uint32_t events_to_callback = event_type && obj->irq_cause;
+    if(obj->callback_data.callback != NULL && events_to_callback)
+    {
+        ((cyhal_dma_event_callback_t)obj->callback_data.callback)(obj->callback_data.callback_arg, (cyhal_dma_event_t)events_to_callback);
+    }
+
+    /* Clear all interrupts */
+    Cy_DMAC_Channel_ClearInterrupt(cyhal_dma_get_dmac_base(block), channel, CY_DMAC_INTR_MASK);
+}
+
+cy_rslt_t cyhal_dma_init_dmac(cyhal_dma_t *obj, uint8_t priority)
+{
+    if(!CY_DMAC_IS_PRIORITY_VALID(priority))
+        return CYHAL_DMA_RSLT_ERR_INVALID_PRIORITY;
+
+    cy_rslt_t rslt = cyhal_hwmgr_allocate(CYHAL_RSC_DMA, &obj->resource);
+    if(rslt != CY_RSLT_SUCCESS)
+        return rslt;
+
+    /* Setup descriptor and channel configs */
+    obj->descriptor_config.dmac = default_descriptor_config_dmac;
+    obj->channel_config.dmac = default_channel_config_dmac;
+    obj->channel_config.dmac.descriptor = &obj->descriptor.dmac;
+    obj->channel_config.dmac.priority = priority;
+
+    obj->callback_data.callback = NULL;
+    obj->callback_data.callback_arg = NULL;
+    obj->irq_cause = 0;
+
+    cyhal_dma_set_dmac_obj(obj);
+
+    return CY_RSLT_SUCCESS;
+}
+
+void cyhal_dma_free_dmac(cyhal_dma_t *obj)
+{
+    Cy_DMAC_Descriptor_DeInit(&obj->descriptor.dmac);
+    Cy_DMAC_Channel_DeInit(cyhal_dma_get_dmac_base(obj->resource.block_num), obj->resource.channel_num);
+
+    NVIC_DisableIRQ(cyhal_dma_get_dmac_irqn(obj));
+
+    cyhal_dma_free_dmac_obj(obj);
+    cyhal_hwmgr_free(&obj->resource);
+}
+
+/* Initalize descriptor, initialize channel, enable channel, enable channel
+ * interrupt, and enable DMAC controller */
+cy_rslt_t cyhal_dma_configure_dmac(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg)
+{
+    /* Do not reconfigure if transfer is pending/active already */
+    if(cyhal_dma_is_busy_dmac(obj))
+        return CYHAL_DMA_RSLT_ERR_CHANNEL_BUSY;
+
+    obj->descriptor_config.dmac.srcAddress = (void*)cfg->src_addr;
+    obj->descriptor_config.dmac.dstAddress = (void*)cfg->dst_addr;
+    obj->descriptor_config.dmac.nextDescriptor = &obj->descriptor.dmac;
+
+    if(cfg->transfer_width == 8)
+        obj->descriptor_config.dmac.dataSize = CY_DMAC_BYTE;
+    else if(cfg->transfer_width == 16)
+        obj->descriptor_config.dmac.dataSize = CY_DMAC_HALFWORD;
+    else if(cfg->transfer_width == 32)
+        obj->descriptor_config.dmac.dataSize = CY_DMAC_WORD;
+    else
+        return CYHAL_DMA_RSLT_ERR_INVALID_TRANSFER_WIDTH;
+
+    /* Length must be a multiple of burst_size */
+    if(cfg->burst_size != 0 && cfg->length % cfg->burst_size != 0)
+        return CYHAL_DMA_RSLT_ERR_INVALID_BURST_SIZE;
+
+    /* Setup 2D transfer if burst_size is being used otherwise set up 1D
+     * transfer */
+    if(cfg->burst_size != 0)
+    {
+        obj->descriptor_config.dmac.descriptorType = CY_DMAC_2D_TRANSFER;
+        obj->descriptor_config.dmac.xCount = cfg->burst_size;
+        obj->descriptor_config.dmac.yCount = cfg->length / cfg->burst_size;
+        obj->descriptor_config.dmac.srcXincrement = cfg->src_increment;
+        obj->descriptor_config.dmac.dstXincrement = cfg->dst_increment;
+        obj->descriptor_config.dmac.srcYincrement = cfg->src_increment * cfg->burst_size;
+        obj->descriptor_config.dmac.dstYincrement = cfg->dst_increment * cfg->burst_size;
+
+        /* If burst action, configure trigger and interrupt actions */
+        if(cfg->action == CYHAL_DMA_TRANSFER_BURST)
+        {
+            obj->descriptor_config.dmac.interruptType = CY_DMAC_X_LOOP;
+            obj->descriptor_config.dmac.triggerInType = CY_DMAC_X_LOOP;
+        }
+    }
+    else
+    {
+        obj->descriptor_config.dmac.descriptorType = CY_DMAC_1D_TRANSFER;
+        obj->descriptor_config.dmac.xCount = cfg->length;
+        obj->descriptor_config.dmac.srcXincrement = cfg->src_increment;
+        obj->descriptor_config.dmac.dstXincrement = cfg->dst_increment;
+
+        obj->descriptor_config.dmac.interruptType = CY_DMAC_DESCR;
+        obj->descriptor_config.dmac.triggerInType = CY_DMAC_DESCR;
+    }
+
+    if(CY_DMAC_SUCCESS != Cy_DMAC_Descriptor_Init(&obj->descriptor.dmac, &obj->descriptor_config.dmac))
+        return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
+
+    /* Setup channel and enable */
+    DMAC_Type* base = cyhal_dma_get_dmac_base(obj->resource.block_num);
+    if(CY_DMAC_SUCCESS != Cy_DMAC_Channel_Init(base, obj->resource.channel_num, &obj->channel_config.dmac))
+        return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
+    Cy_DMAC_Channel_SetDescriptor(base, obj->resource.channel_num, &obj->descriptor.dmac);
+    Cy_DMAC_Channel_SetPriority(base, obj->resource.channel_num, obj->channel_config.dmac.priority);
+    Cy_DMAC_Channel_Enable(base, obj->resource.channel_num);
+    Cy_DMAC_Channel_SetInterruptMask (base, obj->resource.channel_num, CY_DMAC_INTR_MASK);
+
+    Cy_DMAC_Enable(base);
+
+    /* src_misal and dst_misal interrupts are triggered immediately on enable
+     * so return those errors here */
+    uint32_t status = Cy_DMAC_Channel_GetInterruptStatus(base, obj->resource.channel_num);
+    if((status & CY_DMAC_INTR_SRC_MISAL) ||
+       (status & CY_DMAC_INTR_DST_MISAL))
+    {
+        /* Clear all interrupts and return error */
+        Cy_DMAC_Channel_ClearInterrupt(base, obj->resource.channel_num, CY_DMAC_INTR_MASK);
+        return CYHAL_DMA_RSLT_ERR_INVALID_ALIGNMENT;
+    }
+
+    /* Enable interrupt for this channel */
+    cy_stc_sysint_t irqCfg = { cyhal_dma_get_dmac_irqn(obj), CYHAL_ISR_PRIORITY_DEFAULT };
+    if(CY_SYSINT_SUCCESS != Cy_SysInt_Init(&irqCfg, cyhal_dma_irq_handler_dmac))
+        return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
+    NVIC_EnableIRQ(irqCfg.intrSrc);
+
+    return CY_RSLT_SUCCESS;
+}
+
+cy_rslt_t cyhal_dma_start_transfer_dmac(cyhal_dma_t *obj)
+{
+    /* Return warning if channel is busy */
+    if(cyhal_dma_is_busy_dmac(obj))
+        return CYHAL_DMA_RSLT_WARN_TRANSFER_ALREADY_STARTED;
+
+    uint32_t trigline = cyhal_dma_get_dmac_trigger_line(obj->resource.block_num, obj->resource.channel_num);
+    cy_en_trigmux_status_t trig_status = Cy_TrigMux_SwTrigger(trigline, CY_TRIGGER_TWO_CYCLES);
+
+    /* Also return warning if SW trigger is already initated but DMA hardware
+     * has not seen it yet */
+    if(trig_status == CY_TRIGMUX_INVALID_STATE)
+        return CYHAL_DMA_RSLT_WARN_TRANSFER_ALREADY_STARTED;
+    else
+        return CY_RSLT_SUCCESS;
+}
+
+void cyhal_dma_enable_event_dmac(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intrPriority, bool enable)
+{
+    if(enable)
+        obj->irq_cause |= event;
+    else
+        obj->irq_cause &= ~event;
+
+    NVIC_SetPriority(cyhal_dma_get_dmac_irqn(obj), intrPriority);
+}
+
+bool cyhal_dma_is_busy_dmac(cyhal_dma_t *obj)
+{
+    /* The ACTIVE register is a bit field of all pending or active channels */
+    return cyhal_dma_get_dmac_base(obj->resource.block_num)->ACTIVE & (1 << obj->resource.channel_num);
+}
+
+#endif /* CY_IP_M4CPUSS_DMAC */
+
+#if defined(__cplusplus)
+}
+#endif

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma_dw.c

@@ -0,0 +1,402 @@
+/***************************************************************************//**
+* \file cyhal_dma_dw.c
+*
+* \brief
+* Implements a high level interface for interacting with the Cypress Datawire DMA.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cyhal_dma.h"
+#include "cyhal_dma_dw.h"
+#include "cyhal_dma_impl.h"
+#include "cyhal_hwmgr.h"
+#include "cyhal_system.h"
+#include "cyhal_utils.h"
+#include "cyhal_triggers.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#ifdef CY_IP_M4CPUSS_DMA
+
+#if (CPUSS_DW0_PRESENT==1) && (CPUSS_DW1_PRESENT==1)
+#define NUM_DW_CHANNELS (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR)
+#elif (CPUSS_DW0_PRESENT==1)
+#define NUM_DW_CHANNELS (CPUSS_DW0_CH_NR)
+#endif
+
+static cyhal_dma_t* cyhal_dw_config_structs[NUM_DW_CHANNELS];
+
+/** Default dw descriptor config */
+static const cy_stc_dma_descriptor_config_t default_descriptor_config_dw =
+{
+    .retrigger = CY_DMA_RETRIG_IM,
+    .interruptType = CY_DMA_DESCR,
+    .triggerOutType = CY_DMA_DESCR_CHAIN,
+    .channelState = CY_DMA_CHANNEL_ENABLED,
+    .triggerInType = CY_DMA_DESCR,
+    .dataSize = CY_DMA_WORD,
+    .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
+    .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
+    .descriptorType = CY_DMA_1D_TRANSFER,
+    .srcAddress = 0,
+    .dstAddress = 0,
+    .srcXincrement = 1U,
+    .dstXincrement = 1U,
+    .xCount = 1UL,
+    .srcYincrement = 0U,
+    .dstYincrement = 0U,
+    .yCount = 1UL,
+    .nextDescriptor = 0,
+};
+
+/** Default dw channel config */
+static const cy_stc_dma_channel_config_t default_channel_config_dw =
+{
+    .descriptor = 0,
+    .preemptable = false,
+    .priority = 1,
+    .enable = false,
+    .bufferable = false,
+};
+
+/** Sets the dw configuration struct */
+static inline void cyhal_dma_set_dw_obj(cyhal_dma_t *obj)
+{
+    cyhal_dw_config_structs[obj->resource.block_num * CPUSS_DW0_CH_NR + obj->resource.channel_num] = obj;
+}
+
+/** Zeros the dw configuration struct */
+static inline void cyhal_dma_free_dw_obj(cyhal_dma_t *obj)
+{
+    cyhal_dw_config_structs[obj->resource.block_num * CPUSS_DW0_CH_NR + obj->resource.channel_num] = NULL;
+}
+
+/** Gets the dw configuration struct from block and channel */
+static inline cyhal_dma_t* cyhal_dma_get_dw_obj(uint8_t block, uint8_t channel)
+{
+    return cyhal_dw_config_structs[block * CPUSS_DW0_CH_NR + channel];
+}
+
+/** Gets the dw block number from irq number */
+/** This should never be called from a non-dma IRQn */
+static inline uint8_t cyhal_dma_get_dw_block_from_irqn(IRQn_Type irqn)
+{
+    uint8_t diff = irqn - cpuss_interrupts_dw0_0_IRQn;
+#if defined(CPUSS_DW0_CH_NR) && !defined(CPUSS_DW1_CH_NR)
+    CY_ASSERT(diff < CPUSS_DW0_CH_NR);
+
+    if(diff < CPUSS_DW0_CH_NR)
+        return 0;
+#elif defined(CPUSS_DW0_CH_NR) && defined(CPUSS_DW1_CH_NR)
+    CY_ASSERT(diff < CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR);
+
+    if(diff < CPUSS_DW0_CH_NR)
+        return 0;
+    if(diff < CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR)
+        return 1;
+#endif
+
+    // Should never reach here. Just silencing compiler warnings.
+    CY_ASSERT(false);
+    return 255;
+}
+
+/** Gets the dw channel number from irq number */
+/** This should never be called from a non-dma IRQn */
+static inline uint8_t cyhal_dma_get_dw_channel_from_irqn(IRQn_Type irqn)
+{
+    uint8_t diff = irqn - cpuss_interrupts_dw0_0_IRQn;
+#if defined(CPUSS_DW0_CH_NR) && !defined(CPUSS_DW1_CH_NR)
+    CY_ASSERT(diff < CPUSS_DW0_CH_NR);
+
+    if(diff < CPUSS_DW0_CH_NR)
+        return diff;
+#elif defined(CPUSS_DW0_CH_NR) && defined(CPUSS_DW1_CH_NR)
+    CY_ASSERT(diff < CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR);
+
+    if(diff < CPUSS_DW0_CH_NR)
+        return diff;
+    else
+        return diff - CPUSS_DW0_CH_NR;
+#endif
+}
+
+/** Gets the irqn corresponding to a particular cyhal_dma_t config struct */
+static inline IRQn_Type cyhal_dma_get_dw_irqn(cyhal_dma_t *obj)
+{
+    return (IRQn_Type)((uint8_t)cpuss_interrupts_dw0_0_IRQn + (obj->resource.block_num * CPUSS_DW0_CH_NR + obj->resource.channel_num));
+}
+
+/** Gets the dw base pointer from block number */
+static inline DW_Type* cyhal_dma_get_dw_base(uint8_t block_num)
+{
+    return block_num == 0 ? DW0 : DW1;
+}
+
+/** Uses tables provided as part of the hal interconnect driver to determine mux
+ * trigger group and mux trigger index and then construct the trigger line
+ * input parameter to Cy_TrigMux_SwTrigger. */
+static inline uint32_t cyhal_dma_get_dw_trigger_line(uint8_t block_num, uint8_t channel_num)
+{
+    /* cyhal_dest_t triggers are guaranteed to be sorted by trigger type, block
+     * num, then channel num, therefore, we can just directly find the proper
+     * trigger by calculating an offset. */
+    cyhal_dest_t trigger = (cyhal_dest_t)(TRIGGER_CPUSS_DW0_TR_IN0 + (block_num * CPUSS_DW0_CH_NR) + channel_num);
+
+    /* One to one triggers have bit 8 set in cyhal_dest_to_mux but
+     * Cy_TrigMux_SwTrigger wants the trigger group field to have bit 5 set to
+     * denote one to one triggers. */
+    uint8_t trig_group = cyhal_dest_to_mux[trigger];
+    /* If hal one to one triggers bit is set: mask it out and set pdl one to
+     * one bit */
+    if(trig_group & HAL_TRIGGERS_1TO1_MASK)
+        trig_group = (trig_group & ~HAL_TRIGGERS_1TO1_MASK) | PDL_TRIGGERS_1TO1_MASK;
+
+    /* Construct trigger line which consists of three fields packed into a
+     * uint32_t:
+     * Bits   30: Input/output bit. Set to 1 for output.
+     * Bits 12-8: Trigger group selection.
+     * Bits  7-0: Select the output trigger number in the trigger group. */
+    return PERI_TR_CMD_OUT_SEL_Msk | trig_group << 8 | cyhal_mux_dest_index[trigger];
+}
+
+/** Convert PDL interrupt cause to hal dma event */
+static inline cyhal_dma_event_t cyhal_dma_convert_dw_interrupt_cause(cy_en_dma_intr_cause_t cause)
+{
+    switch(cause)
+    {
+        case CY_DMA_INTR_CAUSE_NO_INTR:
+            return CYHAL_DMA_NO_INTR;
+        case CY_DMA_INTR_CAUSE_COMPLETION:
+            return CYHAL_DMA_TRANSFER_COMPLETE;
+        case CY_DMA_INTR_CAUSE_SRC_BUS_ERROR:
+            return CYHAL_DMA_SRC_BUS_ERROR;
+        case CY_DMA_INTR_CAUSE_DST_BUS_ERROR:
+            return CYHAL_DMA_DST_BUS_ERROR;
+        case CY_DMA_INTR_CAUSE_SRC_MISAL:
+            return CYHAL_DMA_SRC_MISAL;
+        case CY_DMA_INTR_CAUSE_DST_MISAL:
+            return CYHAL_DMA_DST_MISAL;
+        case CY_DMA_INTR_CAUSE_CURR_PTR_NULL:
+            return CYHAL_DMA_CURR_PTR_NULL;
+        case CY_DMA_INTR_CAUSE_ACTIVE_CH_DISABLED:
+            return CYHAL_DMA_ACTIVE_CH_DISABLED;
+        case CY_DMA_INTR_CAUSE_DESCR_BUS_ERROR:
+            return CYHAL_DMA_DESCR_BUS_ERROR;
+        default:
+            return CYHAL_DMA_NO_INTR;
+    }
+}
+
+/** DW irq handler */
+static void cyhal_dma_irq_handler_dw(void)
+{
+    /* Use irqn to get appropriate config structure */
+    uint8_t block = cyhal_dma_get_dw_block_from_irqn(CYHAL_GET_CURRENT_IRQN());
+    uint8_t channel = cyhal_dma_get_dw_channel_from_irqn(CYHAL_GET_CURRENT_IRQN());
+    cyhal_dma_t *obj = cyhal_dma_get_dw_obj(block, channel);
+
+    /* Get interrupt type and call users event callback if they have enabled that event */
+    cy_en_dma_intr_cause_t cause = Cy_DMA_Channel_GetStatus(cyhal_dma_get_dw_base(block), channel);
+    cyhal_dma_event_t event_type = cyhal_dma_convert_dw_interrupt_cause(cause);
+    uint32_t events_to_callback = event_type && obj->irq_cause;
+    if(obj->callback_data.callback != NULL && events_to_callback)
+    {
+        ((cyhal_dma_event_callback_t)obj->callback_data.callback)(obj->callback_data.callback_arg, (cyhal_dma_event_t)events_to_callback);
+    }
+
+    /* Clear all interrupts */
+    Cy_DMA_Channel_ClearInterrupt(cyhal_dma_get_dw_base(block), channel);
+}
+
+cy_rslt_t cyhal_dma_init_dw(cyhal_dma_t *obj, uint8_t priority)
+{
+    if(!CY_DMA_IS_PRIORITY_VALID(priority))
+        return CYHAL_DMA_RSLT_ERR_INVALID_PRIORITY;
+
+    cy_rslt_t rslt = cyhal_hwmgr_allocate(CYHAL_RSC_DW, &obj->resource);
+    if(rslt != CY_RSLT_SUCCESS)
+        return rslt;
+
+    /* Setup descriptor and channel configs */
+    obj->descriptor_config.dw = default_descriptor_config_dw;
+    obj->channel_config.dw = default_channel_config_dw;
+    obj->channel_config.dw.descriptor = &obj->descriptor.dw;
+    obj->channel_config.dw.priority = priority;
+
+    obj->callback_data.callback = NULL;
+    obj->callback_data.callback_arg = NULL;
+    obj->irq_cause = 0;
+
+    cyhal_dma_set_dw_obj(obj);
+
+    return CY_RSLT_SUCCESS;
+}
+
+void cyhal_dma_free_dw(cyhal_dma_t *obj)
+{
+    Cy_DMA_Descriptor_DeInit(&obj->descriptor.dw);
+    Cy_DMA_Channel_DeInit(cyhal_dma_get_dw_base(obj->resource.block_num), obj->resource.channel_num);
+
+    NVIC_DisableIRQ(cyhal_dma_get_dw_irqn(obj));
+
+    cyhal_dma_free_dw_obj(obj);
+    cyhal_hwmgr_free(&obj->resource);
+}
+
+/* Initalize descriptor, initialize channel, enable channel, enable channel
+ * interrupt, and enable DW controller */
+cy_rslt_t cyhal_dma_configure_dw(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg)
+{
+    /* Do not reconfigure if transfer is pending/active already */
+    if(cyhal_dma_is_busy_dw(obj))
+        return CYHAL_DMA_RSLT_ERR_CHANNEL_BUSY;
+
+    obj->descriptor_config.dw.srcAddress = (void*)cfg->src_addr;
+    obj->descriptor_config.dw.dstAddress = (void*)cfg->dst_addr;
+    obj->descriptor_config.dw.nextDescriptor = &obj->descriptor.dw;
+
+    if(cfg->transfer_width == 8)
+        obj->descriptor_config.dw.dataSize = CY_DMA_BYTE;
+    else if(cfg->transfer_width == 16)
+        obj->descriptor_config.dw.dataSize = CY_DMA_HALFWORD;
+    else if(cfg->transfer_width == 32)
+        obj->descriptor_config.dw.dataSize = CY_DMA_WORD;
+    else
+        return CYHAL_DMA_RSLT_ERR_INVALID_TRANSFER_WIDTH;
+
+    /* Length must be a multiple of burst_size */
+    if(cfg->burst_size != 0 && cfg->length % cfg->burst_size != 0)
+        return CYHAL_DMA_RSLT_ERR_INVALID_BURST_SIZE;
+
+    /* Setup 2D transfer if burst_size is being used otherwise set up 1D
+     * transfer */
+    if(cfg->burst_size != 0)
+    {
+        obj->descriptor_config.dw.descriptorType = CY_DMA_2D_TRANSFER;
+        obj->descriptor_config.dw.xCount = cfg->burst_size;
+        obj->descriptor_config.dw.yCount = cfg->length / cfg->burst_size;
+        obj->descriptor_config.dw.srcXincrement = cfg->src_increment;
+        obj->descriptor_config.dw.dstXincrement = cfg->dst_increment;
+        obj->descriptor_config.dw.srcYincrement = cfg->src_increment * cfg->burst_size;
+        obj->descriptor_config.dw.dstYincrement = cfg->dst_increment * cfg->burst_size;
+
+        /* If burst action, configure trigger and interrupt actions */
+        if(cfg->action == CYHAL_DMA_TRANSFER_BURST)
+        {
+            obj->descriptor_config.dw.interruptType = CY_DMA_X_LOOP;
+            obj->descriptor_config.dw.triggerInType = CY_DMA_X_LOOP;
+        }
+    }
+    else
+    {
+        obj->descriptor_config.dw.descriptorType = CY_DMA_1D_TRANSFER;
+        obj->descriptor_config.dw.xCount = cfg->length;
+        obj->descriptor_config.dw.srcXincrement = cfg->src_increment;
+        obj->descriptor_config.dw.dstXincrement = cfg->dst_increment;
+
+        obj->descriptor_config.dw.interruptType = CY_DMA_DESCR;
+        obj->descriptor_config.dw.triggerInType = CY_DMA_DESCR;
+    }
+
+    if(CY_DMA_SUCCESS != Cy_DMA_Descriptor_Init(&obj->descriptor.dw, &obj->descriptor_config.dw))
+        return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
+
+    /* Setup channel and enable */
+    DW_Type* base = cyhal_dma_get_dw_base(obj->resource.block_num);
+    if(CY_DMA_SUCCESS != Cy_DMA_Channel_Init(base, obj->resource.channel_num, &obj->channel_config.dw))
+        return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
+    Cy_DMA_Channel_SetDescriptor(base, obj->resource.channel_num, &obj->descriptor.dw);
+    Cy_DMA_Channel_SetPriority(base, obj->resource.channel_num, obj->channel_config.dw.priority);
+    Cy_DMA_Channel_Enable(base, obj->resource.channel_num);
+    Cy_DMA_Channel_SetInterruptMask (base, obj->resource.channel_num, CY_DMA_INTR_MASK);
+
+    Cy_DMA_Enable(base);
+
+    /* src_misal and dst_misal interrupts are triggered immediately on enable
+     * so return those errors here */
+    uint32_t status = Cy_DMA_Channel_GetInterruptStatus(base, obj->resource.channel_num);
+    if((status & CY_DMA_INTR_CAUSE_SRC_MISAL) ||
+       (status & CY_DMA_INTR_CAUSE_DST_MISAL))
+    {
+        Cy_DMA_Channel_ClearInterrupt(base, obj->resource.channel_num);
+        return CYHAL_DMA_RSLT_ERR_INVALID_ALIGNMENT;
+    }
+
+    /* Enable interrupt for this channel */
+    cy_stc_sysint_t irqCfg = { cyhal_dma_get_dw_irqn(obj), CYHAL_ISR_PRIORITY_DEFAULT };
+    if(CY_SYSINT_SUCCESS != Cy_SysInt_Init(&irqCfg, cyhal_dma_irq_handler_dw))
+        return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
+    NVIC_EnableIRQ(irqCfg.intrSrc);
+
+    return CY_RSLT_SUCCESS;
+}
+
+cy_rslt_t cyhal_dma_start_transfer_dw(cyhal_dma_t *obj)
+{
+    /* Return warning if channel is busy */
+    if(cyhal_dma_is_busy_dw(obj))
+        return CYHAL_DMA_RSLT_WARN_TRANSFER_ALREADY_STARTED;
+
+    uint32_t trigline = cyhal_dma_get_dw_trigger_line(obj->resource.block_num, obj->resource.channel_num);
+    cy_en_trigmux_status_t trig_status = Cy_TrigMux_SwTrigger(trigline, CY_TRIGGER_TWO_CYCLES);
+
+    /* Also return warning if SW trigger is already initated but DMA hardware
+     * has not seen it yet */
+    if(trig_status == CY_TRIGMUX_INVALID_STATE)
+        return CYHAL_DMA_RSLT_WARN_TRANSFER_ALREADY_STARTED;
+    else
+        return CY_RSLT_SUCCESS;
+}
+
+void cyhal_dma_enable_event_dw(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intrPriority, bool enable)
+{
+    if(enable)
+        obj->irq_cause |= event;
+    else
+        obj->irq_cause &= ~event;
+
+    NVIC_SetPriority(cyhal_dma_get_dw_irqn(obj), intrPriority);
+}
+
+bool cyhal_dma_is_busy_dw(cyhal_dma_t *obj)
+{
+#if CY_IP_M4CPUSS_DMA_VERSION == 1
+    /* In DW_V1 the pending channel information is stored in the PENDING
+     * register of the DW block and is a bit field of all pending or active
+     * channels */
+    return cyhal_dma_get_dw_base(obj->resource.block_num)->PENDING & (1 << obj->resource.channel_num);
+#elif CY_IP_M4CPUSS_DMA_VERSION == 2
+    /* In DW_V2 the pending channel information is stored in the STATUS
+     * register of the channel itself */
+    return DW_CH_STATUS(cyhal_dma_get_dw_base(obj->resource.block_num), obj->resource.channel_num) & (1UL << DW_CH_STRUCT_V2_CH_STATUS_PENDING_Pos);
+#else
+    // Should never reach here. Just silencing compiler warnings.
+    CY_ASSERT(false);
+    return false;
+#endif
+}
+
+#endif /* CY_IP_M4CPUSS_DMA */
+
+#if defined(__cplusplus)
+}
+#endif

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_ezi2c.c

@@ -0,0 +1,289 @@
+/*******************************************************************************
+* File Name: cyhal_ezi2c.c
+*
+* Description:
+* Provides a high level interface for interacting with the Cypress I2C. This is
+* a wrapper around the lower level PDL API.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <stdlib.h>
+#include "cyhal_ezi2c.h"
+#include "cyhal_scb_common.h"
+#include "cyhal_gpio.h"
+#include "cyhal_interconnect.h"
+#include "cyhal_system_impl.h"
+#include "cyhal_hwmgr.h"
+
+#ifdef CY_IP_MXSCB
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/* Peripheral clock values for different EZI2C speeds according PDL API Reference Guide */
+#define SCB_PERI_CLOCK_SLAVE_STD      8000000
+#define SCB_PERI_CLOCK_SLAVE_FST      12500000
+#define SCB_PERI_CLOCK_SLAVE_FSTP     50000000
+#define SCB_PERI_CLOCK_MASTER_STD     2000000
+#define SCB_PERI_CLOCK_MASTER_FST     8500000
+#define SCB_PERI_CLOCK_MASTER_FSTP    20000000
+
+/* Implement ISR for EZI2C */
+static void cyhal_ezi2c_irq_handler(void)
+{
+    cyhal_ezi2c_t *obj = (cyhal_ezi2c_t*) cyhal_scb_get_irq_obj();
+    Cy_SCB_EZI2C_Interrupt(obj->base, &(obj->context));
+
+    /* Call if registered callback here */
+    cyhal_ezi2c_event_callback_t callback = (cyhal_ezi2c_event_callback_t) obj->callback_data.callback;
+    if (callback != NULL)
+    {
+        callback(obj->callback_data.callback_arg, CYHAL_EZI2C_EVENT_NONE);
+    }
+}
+
+static uint32_t cyhal_set_peri_divider(cyhal_ezi2c_t *obj, uint32_t freq)
+{
+    /* Return the actual data rate on success, 0 otherwise */
+    uint32_t peri_freq = 0;
+    if (freq == 0)
+    {
+        return 0;
+    }
+    if (freq <= CY_SCB_I2C_STD_DATA_RATE)
+    {
+        peri_freq = SCB_PERI_CLOCK_SLAVE_STD;
+    }
+    else if (freq <= CY_SCB_I2C_FST_DATA_RATE)
+    {
+        peri_freq = SCB_PERI_CLOCK_SLAVE_FST;
+    }
+    else if (freq <= CY_SCB_I2C_FSTP_DATA_RATE)
+    {
+        peri_freq = SCB_PERI_CLOCK_SLAVE_FSTP;
+    }
+    else
+    {
+        return 0;
+    }
+
+    /* Connect assigned divider to be a clock source for EZI2C */
+    cy_en_sysclk_status_t status = Cy_SysClk_PeriphAssignDivider((en_clk_dst_t)((uint8_t)PCLK_SCB0_CLOCK + obj->resource.block_num), obj->clock.div_type, obj->clock.div_num);
+    if (status == CY_SYSCLK_SUCCESS)
+        status = Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num);
+    if (status == CY_SYSCLK_SUCCESS)
+        status = Cy_SysClk_PeriphSetDivider   (obj->clock.div_type, obj->clock.div_num, cyhal_divider_value(peri_freq, 0u));
+    if (status == CY_SYSCLK_SUCCESS)
+        status = Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num);
+    CY_ASSERT(CY_SYSCLK_SUCCESS == status);
+
+    return Cy_SCB_I2C_SetDataRate(obj->base, freq, Cy_SysClk_PeriphGetFrequency(obj->clock.div_type, obj->clock.div_num));
+}
+
+cy_rslt_t cyhal_ezi2c_init(cyhal_ezi2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, const cyhal_clock_divider_t *clk, const cyhal_ezi2c_cfg_t *cfg)
+{
+    /* Validate input configuration structure */
+    if ((0 == cfg->slave1_cfg.slave_address) || ((cfg->two_addresses) && (0 == cfg->slave2_cfg.slave_address)))
+    {
+        return CYHAL_EZI2C_RSLT_ERR_CHECK_USER_CONFIG;
+    }
+
+    CY_ASSERT(NULL != obj);
+
+    /* Populate configuration structure */
+    const cy_stc_scb_ezi2c_config_t ezI2cConfig =
+    {
+        .numberOfAddresses   = cfg->two_addresses ? CY_SCB_EZI2C_TWO_ADDRESSES : CY_SCB_EZI2C_ONE_ADDRESS,
+        .slaveAddress1       = cfg->slave1_cfg.slave_address,
+        .slaveAddress2       = cfg->slave2_cfg.slave_address,
+        .subAddressSize      = (cy_en_scb_ezi2c_sub_addr_size_t)cfg->sub_address_size,
+        .enableWakeFromSleep = cfg->enable_wake_from_sleep,
+    };
+
+    /* Explicitly marked not allocated resources as invalid to prevent freeing them. */
+    obj->resource.type = CYHAL_RSC_INVALID;
+    obj->pin_scl = CYHAL_NC_PIN_VALUE;
+    obj->pin_sda = CYHAL_NC_PIN_VALUE;
+    obj->is_shared_clock = true;
+
+    cy_rslt_t result;
+
+    /* Reserve the I2C */
+    const cyhal_resource_pin_mapping_t *sda_map = CY_UTILS_GET_RESOURCE(sda, cyhal_pin_map_scb_i2c_sda);
+    const cyhal_resource_pin_mapping_t *scl_map = CY_UTILS_GET_RESOURCE(scl, cyhal_pin_map_scb_i2c_scl);
+    if ((NULL == sda_map) || (NULL == scl_map) || (sda_map->inst->block_num != scl_map->inst->block_num))
+    {
+        return CYHAL_EZI2C_RSLT_ERR_INVALID_PIN;
+    }
+
+    result = cyhal_hwmgr_reserve(scl_map->inst);
+
+    /* Reserve the SDA pin */
+    if (result == CY_RSLT_SUCCESS)
+    {
+        cyhal_resource_inst_t pin_rsc = cyhal_utils_get_gpio_resource(sda);
+        result = cyhal_hwmgr_reserve(&pin_rsc);
+        if (result == CY_RSLT_SUCCESS)
+        {
+            obj->pin_sda = sda;
+            /* Configures the HSIOM connection to the pin */
+            Cy_GPIO_SetHSIOM(CYHAL_GET_PORTADDR(sda), CYHAL_GET_PIN(sda), CY_GPIO_CFG_GET_HSIOM(scl_map->cfg));
+            /* Configures the pin output buffer drive mode and input buffer enable */
+            Cy_GPIO_SetDrivemode(CYHAL_GET_PORTADDR(sda), CYHAL_GET_PIN(sda), CY_GPIO_DM_OD_DRIVESLOW);
+        }
+    }
+
+    /* Reserve the SCL pin */
+    if (result == CY_RSLT_SUCCESS)
+    {
+        cyhal_resource_inst_t pin_rsc = cyhal_utils_get_gpio_resource(scl);
+        /* Connect SCB I2C function to pins */
+        cy_rslt_t result = cyhal_hwmgr_reserve(&pin_rsc);
+        if (result == CY_RSLT_SUCCESS)
+        {
+            obj->pin_scl = scl;
+            /* Configures the HSIOM connection to the pin */
+            Cy_GPIO_SetHSIOM(CYHAL_GET_PORTADDR(scl), CYHAL_GET_PIN(scl), CY_GPIO_CFG_GET_HSIOM(scl_map->cfg));
+            /* Configures the pin output buffer drive mode and input buffer enable */
+            Cy_GPIO_SetDrivemode(CYHAL_GET_PORTADDR(scl), CYHAL_GET_PIN(scl), CY_GPIO_DM_OD_DRIVESLOW);
+        }
+    }
+
+    if (result == CY_RSLT_SUCCESS)
+    {
+        obj->is_shared_clock = (clk != NULL);
+        if (clk == NULL)
+        {
+            result = cyhal_hwmgr_allocate_clock(&(obj->clock), CY_SYSCLK_DIV_16_BIT, false);
+        }
+        else
+        {
+            obj->clock = *clk;
+        }
+    }
+
+    obj->resource = *(scl_map->inst);
+    obj->base = CYHAL_SCB_BASE_ADDRESSES[obj->resource.block_num];
+
+    if (result == CY_RSLT_SUCCESS)
+    {
+        /* Configure I2C to operate */
+        result = Cy_SCB_EZI2C_Init(obj->base, &ezI2cConfig, &(obj->context));
+    }
+
+    int32_t ezi2c_freq;
+    switch(cfg->data_rate)
+    {
+       	case CYHAL_EZI2C_DATA_RATE_100KHZ:
+       		ezi2c_freq = 100000;
+            break;
+      	case CYHAL_EZI2C_DATA_RATE_400KHZ:
+      	    ezi2c_freq = 400000;
+       	    break;
+       	case CYHAL_EZI2C_DATA_RATE_1MHZ:
+       		ezi2c_freq = 1000000;
+       	    break;
+        default:
+           	return CYHAL_EZI2C_RSLT_ERR_CHECK_USER_CONFIG;
+    }
+
+    /* Set data rate */
+    int32_t dataRate = cyhal_set_peri_divider(obj, ezi2c_freq);
+    if (dataRate == 0)
+    {
+        /* Can not reach desired data rate */
+        return CYHAL_EZI2C_RSLT_ERR_CAN_NOT_REACH_DR;
+    }
+
+    if (result == CY_RSLT_SUCCESS)
+    {
+        /* Configure buffer for communication with master */
+        Cy_SCB_EZI2C_SetBuffer1(obj->base, cfg->slave1_cfg.buf, cfg->slave1_cfg.buf_size, cfg->slave1_cfg.buf_rw_boundary, &(obj->context));
+        /* Check if user set one or two addresses */
+        if(cfg->two_addresses)
+        {
+            Cy_SCB_EZI2C_SetBuffer2(obj->base, cfg->slave2_cfg.buf, cfg->slave2_cfg.buf_size, cfg->slave2_cfg.buf_rw_boundary, &(obj->context));
+        }
+    }
+
+    if (result == CY_RSLT_SUCCESS)
+    {
+        obj->callback_data.callback = NULL;
+        obj->callback_data.callback_arg = NULL;
+        obj->irq_cause = 0;
+        cyhal_scb_config_structs[obj->resource.block_num] = obj;
+
+        cy_stc_sysint_t irqCfg = { CYHAL_SCB_IRQ_N[obj->resource.block_num], CYHAL_ISR_PRIORITY_DEFAULT };
+        Cy_SysInt_Init(&irqCfg, cyhal_ezi2c_irq_handler);
+        NVIC_EnableIRQ(CYHAL_SCB_IRQ_N[obj->resource.block_num]);
+
+        /* Enable EZI2C to operate */
+        (void)Cy_SCB_EZI2C_Enable(obj->base);
+    }
+
+    if (result != CY_RSLT_SUCCESS)
+    {
+        cyhal_ezi2c_free(obj);
+    }
+    return result;
+}
+
+void cyhal_ezi2c_free(cyhal_ezi2c_t *obj)
+{
+    CY_ASSERT(NULL != obj);
+
+    if (CYHAL_RSC_INVALID != obj->resource.type)
+    {
+        IRQn_Type irqn = CYHAL_SCB_IRQ_N[obj->resource.block_num];
+        NVIC_DisableIRQ(irqn);
+
+        cyhal_hwmgr_free(&(obj->resource));
+        obj->base = NULL;
+        obj->resource.type = CYHAL_RSC_INVALID;
+    }
+
+    cyhal_utils_release_if_used(&(obj->pin_sda));
+    cyhal_utils_release_if_used(&(obj->pin_scl));
+
+    if (!obj->is_shared_clock)
+    {
+        cyhal_hwmgr_free_clock(&(obj->clock));
+    }
+}
+
+cyhal_ezi2c_status_t cyhal_ezi2c_get_activity_status(cyhal_ezi2c_t *obj)
+{
+    return (cyhal_ezi2c_status_t)Cy_SCB_EZI2C_GetActivity(obj->base, &(obj->context));
+}
+
+void cyhal_ezi2c_register_callback(cyhal_ezi2c_t *obj, cyhal_ezi2c_event_callback_t callback, void *callback_arg)
+{
+    uint32_t savedIntrStatus = cyhal_system_critical_section_enter();
+    obj->callback_data.callback = (cy_israddress) callback;
+    obj->callback_data.callback_arg = callback_arg;
+    cyhal_system_critical_section_exit(savedIntrStatus);
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_IP_MXSCB */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_flash.c

@@ -7,7 +7,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_gpio.c

@@ -7,7 +7,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -83,10 +83,15 @@ static uint32_t cyhal_gpio_convert_drive_mode(cyhal_gpio_drive_mode_t drive_mode
     uint32_t drvMode;
     switch (drive_mode)
     {
+        /* For DRIVE_NONE and DRIVE_ANALOG: Return immediately so drvMode is
+         * not modified after switch statement based on direction as direction
+         * does not make sense for input only drive modes */
         case CYHAL_GPIO_DRIVE_NONE:
-        case CYHAL_GPIO_DRIVE_ANALOG:
             drvMode = CY_GPIO_DM_HIGHZ;
-            break;
+            return drvMode;
+        case CYHAL_GPIO_DRIVE_ANALOG:
+            drvMode = CY_GPIO_DM_ANALOG;
+            return drvMode;
         case CYHAL_GPIO_DRIVE_PULLUP:
             drvMode = CY_GPIO_DM_PULLUP;
             break;
@@ -155,6 +160,8 @@ void cyhal_gpio_free(cyhal_gpio_t pin)
     if (pin != CYHAL_NC_PIN_VALUE)
     {
         Cy_GPIO_SetInterruptMask(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), 0);
+        hal_gpio_callbacks[CYHAL_GET_PORT(pin)][CYHAL_GET_PIN(pin)] = NULL;
+        hal_gpio_callback_args[CYHAL_GET_PORT(pin)][CYHAL_GET_PIN(pin)] = NULL;
 
         Cy_GPIO_Pin_FastInit(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), CY_GPIO_DM_ANALOG, 0UL, HSIOM_SEL_GPIO);
         /* Do not attempt to free the resource we don't reserve in mbed. */
@@ -183,9 +190,10 @@ void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t
 
 void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intrPriority, bool enable)
 {
+    Cy_GPIO_ClearInterrupt(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin));
     Cy_GPIO_SetInterruptEdge(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), (uint32_t)event);
     Cy_GPIO_SetInterruptMask(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), (uint32_t)enable);
-    
+
     /* Only enable if it's not already enabled */
     IRQn_Type irqn = (IRQn_Type)(ioss_interrupts_gpio_0_IRQn + CYHAL_GET_PORT(pin));
     if (NVIC_GetEnableIRQ(irqn) == 0)

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_hwmgr.c

@@ -8,7 +8,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -105,18 +105,22 @@ extern "C"
     #define CY_BLOCK_COUNT_DAC      0
 #endif
 
-#if defined(CY_IP_M4CPUSS_DMAC_INSTANCES) || defined(CY_IP_M4CPUSS_DMA_INSTANCES)
+#if defined(CY_IP_M4CPUSS_DMAC_INSTANCES)
-    #ifndef CPUSS_DMAC_CH_NR
+    #define CY_BLOCK_COUNT_DMA      (CY_IP_M4CPUSS_DMAC_INSTANCES)
-        #define CPUSS_DMAC_CH_NR (0u)
+    #define CY_CHANNEL_COUNT_DMA    (CPUSS_DMAC_CH_NR)
-    #endif
-
-    #define CY_BLOCK_COUNT_DMA      3
-    #define CY_CHANNEL_COUNT_DMA    (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR + CPUSS_DMAC_CH_NR)
 #else
     #define CY_BLOCK_COUNT_DMA      0
     #define CY_CHANNEL_COUNT_DMA    0
 #endif
 
+#if defined(CY_IP_M4CPUSS_DMA_INSTANCES)
+    #define CY_BLOCK_COUNT_DW      (CY_IP_M4CPUSS_DMA_INSTANCES)
+    #define CY_CHANNEL_COUNT_DW    (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR)
+#else
+    #define CY_BLOCK_COUNT_DW      0
+    #define CY_CHANNEL_COUNT_DW    0
+#endif
+
 #ifdef IOSS_GPIO_GPIO_PORT_NR
     #define CY_BLOCK_COUNT_GPIO IOSS_GPIO_GPIO_PORT_NR
     #define CY_CHANNEL_COUNT_GPIO   (8 * IOSS_GPIO_GPIO_PORT_NR)
@@ -259,7 +263,9 @@ extern "C"
 #define CY_SIZE_DAC        CY_BLOCK_COUNT_DAC
 #define CY_OFFSET_DMA      (CY_OFFSET_DAC + CY_SIZE_DAC)
 #define CY_SIZE_DMA        CY_CHANNEL_COUNT_DMA
-#define CY_OFFSET_GPIO     (CY_OFFSET_DMA + CY_SIZE_DMA)
+#define CY_OFFSET_DW       (CY_OFFSET_DMA + CY_SIZE_DMA)
+#define CY_SIZE_DW         CY_CHANNEL_COUNT_DW
+#define CY_OFFSET_GPIO     (CY_OFFSET_DW + CY_SIZE_DW)
 #define CY_SIZE_GPIO       CY_CHANNEL_COUNT_GPIO
 #define CY_OFFSET_I2S      (CY_OFFSET_GPIO + CY_SIZE_GPIO)
 #define CY_SIZE_I2S        CY_BLOCK_COUNT_I2S
@@ -306,10 +312,14 @@ static const uint8_t cyhal_block_offsets_clock[4] =
 };
 
 static const uint8_t cyhal_block_offsets_dma[] =
+{
+    0,
+};
+
+static const uint8_t cyhal_block_offsets_dw[] =
 {
     0,
     CPUSS_DW0_CH_NR,
-    CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR,
 };
 
 static const uint8_t cyhal_block_offsets_gpio[] =
@@ -415,6 +425,7 @@ static const uint16_t cyhal_resource_offsets[] =
     CY_OFFSET_CRYPTO,
     CY_OFFSET_DAC,
     CY_OFFSET_DMA,
+    CY_OFFSET_DW,
     CY_OFFSET_GPIO,
     CY_OFFSET_I2S,
     CY_OFFSET_LCD,
@@ -435,6 +446,7 @@ static const uint32_t cyhal_has_channels =
     (1 << CYHAL_RSC_CAN)   |
     (1 << CYHAL_RSC_CLOCK) |
     (1 << CYHAL_RSC_DMA)   |
+    (1 << CYHAL_RSC_DW)    |
     (1 << CYHAL_RSC_GPIO)  |
     (1 << CYHAL_RSC_TCPWM) ;
 
@@ -449,6 +461,9 @@ static const uint32_t cyhal_has_channels =
 static inline void check_array_size() __attribute__ ((deprecated));
 #if __ICCARM__
 #pragma diag_suppress=Pe177
+#elif __clang__
+#pragma clang diagnostic push
+#pragma clang diagnostic ignored "-Wunused-function"
 #endif
 static inline void check_array_size()
 {
@@ -457,6 +472,8 @@ static inline void check_array_size()
 }
 #if __ICCARM__
 #pragma diag_default=Pe177
+#elif __clang__
+#pragma clang diagnostic pop
 #endif
 
 /*******************************************************************************
@@ -483,6 +500,8 @@ static inline const uint8_t* cyhal_get_block_offsets(cyhal_resource_t type)
             return cyhal_block_offsets_clock;
         case CYHAL_RSC_DMA:
             return cyhal_block_offsets_dma;
+        case CYHAL_RSC_DW:
+            return cyhal_block_offsets_dw;
         case CYHAL_RSC_GPIO:
             return cyhal_block_offsets_gpio;
         case CYHAL_RSC_TCPWM:
@@ -504,6 +523,8 @@ static inline uint8_t cyhal_get_block_offset_length(cyhal_resource_t type)
             return sizeof(cyhal_block_offsets_clock)/sizeof(cyhal_block_offsets_clock[0]);
         case CYHAL_RSC_DMA:
             return sizeof(cyhal_block_offsets_dma)/sizeof(cyhal_block_offsets_dma[0]);
+        case CYHAL_RSC_DW:
+            return sizeof(cyhal_block_offsets_dw)/sizeof(cyhal_block_offsets_dw[0]);
         case CYHAL_RSC_GPIO:
             return sizeof(cyhal_block_offsets_gpio)/sizeof(cyhal_block_offsets_gpio[0]);
         case CYHAL_RSC_TCPWM:
@@ -708,11 +729,6 @@ void cyhal_hwmgr_free_clock(cyhal_clock_divider_t* obj)
     cyhal_hwmgr_free(&res);
 }
 
-cy_rslt_t cyhal_hwmgr_allocate_dma(cyhal_resource_inst_t* obj)
-{
-    return cyhal_hwmgr_allocate(CYHAL_RSC_DMA, obj);
-}
-
 #if defined(__cplusplus)
 }
 #endif

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_i2c.c

@@ -7,7 +7,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -134,10 +134,14 @@ static uint32_t cyhal_set_peri_divider(cyhal_i2c_t *obj, uint32_t freq, bool is_
     {
         return 0;
     }
-    Cy_SysClk_PeriphAssignDivider((en_clk_dst_t)((uint8_t)PCLK_SCB0_CLOCK + obj->resource.block_num), obj->clock.div_type, obj->clock.div_num);
+    cy_en_sysclk_status_t status = Cy_SysClk_PeriphAssignDivider((en_clk_dst_t)((uint8_t)PCLK_SCB0_CLOCK + obj->resource.block_num), obj->clock.div_type, obj->clock.div_num);
-    Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num);
+    if (status == CY_SYSCLK_SUCCESS)
-    Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, cyhal_divider_value(peri_freq, 0u));
+        status = Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num);
-    Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num);
+    if (status == CY_SYSCLK_SUCCESS)
+        status = Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, cyhal_divider_value(peri_freq, 0u));
+    if (status == CY_SYSCLK_SUCCESS)
+        status = Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num);
+    CY_ASSERT(CY_SYSCLK_SUCCESS == status);
 
     /* According to PDL API Reference Guide - Cy_SysClk_PeriphGetFrequency() use only for i2c master role */
     if(!is_slave)
@@ -148,7 +152,6 @@ static uint32_t cyhal_set_peri_divider(cyhal_i2c_t *obj, uint32_t freq, bool is_
     {
     	return Cy_SCB_I2C_GetDataRate(obj->base, Cy_SysClk_PeriphGetFrequency(obj->clock.div_type, obj->clock.div_num));
     }
-
 }
 
 /* Start API implementing */
@@ -268,16 +271,9 @@ void cyhal_i2c_free(cyhal_i2c_t *obj)
         obj->base = NULL;
         obj->resource.type = CYHAL_RSC_INVALID;
     }
-    if (CYHAL_NC_PIN_VALUE != obj->pin_sda)
+
-    {
+    cyhal_utils_release_if_used(&(obj->pin_sda));
-        cyhal_utils_disconnect_and_free(obj->pin_sda);
+    cyhal_utils_release_if_used(&(obj->pin_scl));
-        obj->pin_sda = CYHAL_NC_PIN_VALUE;
-    }
-    if (CYHAL_NC_PIN_VALUE != obj->pin_scl)
-    {
-        cyhal_utils_disconnect_and_free(obj->pin_scl);
-        obj->pin_scl = CYHAL_NC_PIN_VALUE;
-    }
 
     if (!obj->is_shared_clock)
     {
@@ -417,7 +413,7 @@ cy_rslt_t cyhal_i2c_master_mem_write(cyhal_i2c_t *obj, uint16_t address, uint16_
     }
 
     cy_rslt_t status = cyhal_i2c_master_write(obj, address, mem_addr_buf, mem_addr_size, timeout, false);
-    
+
     if (status == CY_RSLT_SUCCESS)
     {
         while (size > 0)

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_interconnect.c

@@ -7,7 +7,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_lptimer.c

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -110,7 +110,7 @@ cy_rslt_t cyhal_lptimer_init(cyhal_lptimer_t *obj)
         obj->callback_data.callback_arg = NULL;
         cyhal_lptimer_config_structs[obj->resource.block_num] = obj;
     }
-    
+
     if (CY_RSLT_SUCCESS == rslt)
     {
         IRQn_Type irqn = (IRQn_Type) (srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num);
@@ -167,7 +167,7 @@ cy_rslt_t cyhal_lptimer_set_delay(cyhal_lptimer_t *obj, uint32_t delay)
      * 16 bit C0/C1 are cascaded to generated a 32 bit counter.
      * Counter0 continues counting after reaching its match value
      * Interrupt is generated on Counter1 match.
-     * 
+     *
      * Supposed T=C0=C1=0, and we need to trigger an interrupt at T=0x28000.
      * We set C0_match to 0x8000 and C1 match to 1.
      * At T = 0x8000, C0_value matches C0_match so C1 get incremented. C1/C0=0x18000.
@@ -189,7 +189,7 @@ cy_rslt_t cyhal_lptimer_set_delay(cyhal_lptimer_t *obj, uint32_t delay)
     uint16_t c1_increment = (uint16_t)(delay >> 16);
 
     Cy_MCWDT_ClearInterrupt(obj->base, CY_MCWDT_CTR1);
-    
+
     uint16_t c0_old_match = Cy_MCWDT_GetMatch(obj->base, CY_MCWDT_COUNTER0);
 
     uint32_t critical_section = cyhal_system_critical_section_enter();
@@ -244,7 +244,7 @@ void cyhal_lptimer_enable_event(cyhal_lptimer_t *obj, cyhal_lptimer_event_t even
     CY_ASSERT(event == CYHAL_LPTIMER_COMPARE_MATCH);
     Cy_MCWDT_ClearInterrupt(obj->base, CY_MCWDT_CTR1);
     Cy_MCWDT_SetInterruptMask(obj->base, enable ? CY_MCWDT_CTR1 : 0);
-    
+
     IRQn_Type irqn = (IRQn_Type)(srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num);
     NVIC_SetPriority(irqn, intrPriority);
 }

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_not_implemented.c

@@ -10,7 +10,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -27,6 +27,8 @@
 *******************************************************************************/
 
 #include "cyhal_interconnect.h"
+#include "cyhal_triggers.h"
+#include "cy_utils.h"
 
 #if defined(__cplusplus)
 extern "C"
@@ -46,12 +48,13 @@ typedef enum
 } cyhal_trigger_src;
 
 /* Trigger type for each output                                    ~100b */
+/* Note: Non-fake version implemented in cyhal_triggers */
 typedef enum
 {
     DEST0,
     DEST1,
     MUX_IN1,
-} cyhal_trigger_dest;
+} cyhal_trigger_dest_fake;
 
 // Two fake muxes.
 // Mux0
@@ -62,7 +65,8 @@ typedef enum
 //  Outputs: DEST1
 
 /* Maps each cyhal_destination_t to a mux index                    ~100b */
-const uint8_t cyhal_dest_to_mux[] =
+/* Note: Non-fake version implemented in cyhal_triggers */
+const uint8_t cyhal_dest_to_mux_fake[] =
 {
     0, // DEST0
     1, // DEST1
@@ -70,7 +74,8 @@ const uint8_t cyhal_dest_to_mux[] =
 };
 
 /* Maps each cyhal_destination_t to a specific output in its mux    ~100b */
-const uint8_t cyhal_mux_dest_index[] =
+/* Note: Non-fake version implemented in cyhal_triggers */
+const uint8_t cyhal_mux_dest_index_fake[] =
 {
     0, // DEST0
     0, // DEST1
@@ -87,10 +92,10 @@ const cyhal_source_t* cyhal_mux_to_sources[] = { cyhal_mux0_sources, cyhal_mux1_
 /* Mapping from cyhal_source_t to cyhal_destination_t for intra mux connections     ~80b*/
 const cyhal_dest_t cyhal_intra_trigger_source[] =
 {
-    CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC0
+    (cyhal_dest_t)CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC0
-    CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC1,
+    (cyhal_dest_t)CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC1,
-    CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC2,
+    (cyhal_dest_t)CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC2,
-    MUX_IN1 // MUX_OUT0
+    (cyhal_dest_t)MUX_IN1 // MUX_OUT0
 };
 
 
@@ -111,7 +116,7 @@ typedef enum
 #define ONE_TO_ONE_IDENT 0x80
 /** Determines whether a mux is one-to-one */
 #define IS_1TO1(muxId) (ONE_TO_ONE_IDENT == (muxId & ONE_TO_ONE_IDENT))
-#define WRITE_REGISTER(muxIdx, sourceId, destId) /* TODO */
+#define WRITE_REGISTER(muxIdx, sourceId, destId)
 
 /* Maps each cyhal_destination_t to a mux index */
 //extern uint8_t cyhal_dest_to_mux[];
@@ -126,7 +131,8 @@ typedef enum
 
 bool cyhal_has_connection(uint8_t mux, uint8_t outputIdx)
 {
-    // TODO
+    CY_UNUSED_PARAMETER(mux);
+    CY_UNUSED_PARAMETER(outputIdx);
     return false;
 }
 
@@ -138,8 +144,8 @@ bool cyhal_has_connection(uint8_t mux, uint8_t outputIdx)
  */
 cy_rslt_t cyhal_connect_trigger(cyhal_source_t source, cyhal_dest_t dest)
 {
-    uint8_t muxIdx = cyhal_dest_to_mux[dest];
+    uint8_t muxIdx = cyhal_dest_to_mux_fake[dest];
-    uint8_t destId = dest - cyhal_mux_dest_index[dest];
+    uint8_t destId = dest - cyhal_mux_dest_index_fake[dest];
     uint8_t sourceCount = cyhal_source_count_per_mux[muxIdx];
 
     if (cyhal_has_connection(muxIdx, destId))
@@ -166,8 +172,8 @@ cy_rslt_t cyhal_connect_trigger(cyhal_source_t source, cyhal_dest_t dest)
             if (CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION != intraDest)
             {
                 // This destination can be driven by the output of another mux.
-                uint8_t upstreamMuxIdx = cyhal_dest_to_mux[intraDest];
+                uint8_t upstreamMuxIdx = cyhal_dest_to_mux_fake[intraDest];
-                uint8_t intraDestId = intraDest - cyhal_mux_dest_index[intraDest];
+                uint8_t intraDestId = intraDest - cyhal_mux_dest_index_fake[intraDest];
                 uint8_t upstreamMuxSourceCount = cyhal_source_count_per_mux[upstreamMuxIdx];
                 cy_rslt_t result = CYHAL_CONNECT_RSLT_NO_CONNECTION;
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_pwm.c

@@ -0,0 +1,340 @@
+/***************************************************************************//**
+* \file cyhal_pwm.c
+*
+* \brief
+* Provides a high level interface for interacting with the Cypress PWM. This is
+* a wrapper around the lower level PDL API.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/**
+ * \addtogroup group_hal_psoc6_pwm PWM (Pulse Width Modulator)
+ * \ingroup group_hal_psoc6
+ * \{
+ * \section section_psoc6_pwm_compl_pins Complementary PWM output
+ * The PWM HAL driver allows generation of a normal and an inverted output. PSoC 6 devices support complementary pin pairs to which the normal and
+ * inverted signals can be routed. To identify the complementary pin for a given pin, open the PSoC 6 device datasheet and navigate to the 'Multiple Alternate Functions' table. Each
+ * column represents an alternate function of the pin in the corresponding row. Find your pin and make a note of the tcpwm[X].line[Y]:Z. The
+ * complementary pin is found by looking up the pin against tcpwm[X].line_<b>compl</b>[Y]:Z from the same column.
+ * For example, the image below shows a pair of complementary pins (P0.0 and P0.1) identified by the tcpwm[0].line[0]:0 and tcpwm[0].line_compl[0]:0 mapping.
+ * These complementary pins can be supplied to \ref cyhal_pwm_init_adv using <b>pin</b> and <b>compl_pin</b> parameters in any order.
+ * \image html pwm_compl_pins.png "Complementary PWM pins"
+ *
+ * \} group_hal_psoc6_pwm
+ */
+
+#include <string.h>
+#include "cyhal_pwm_impl.h"
+#include "cyhal_gpio.h"
+#include "cyhal_hwmgr.h"
+#include "cyhal_interconnect.h"
+#include "cyhal_utils.h"
+
+#ifdef CY_IP_MXTCPWM
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define TCPWM_MAX_WIDTH         32
+#define MAX_DEAD_TIME_CYCLES    255
+static const uint32_t US_PER_SEC = 1000000u;
+
+/** The configuration of PWM output signal for Center and Asymmetric alignment with overflow and underflow swapped */
+#define CY_TCPWM_PWM_MODE_CNTR_OR_ASYMM_UO_SWAPPED (_VAL2FLD(TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE, CY_TCPWM_PWM_TR_CTRL2_INVERT) | \
+                                         _VAL2FLD(TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_CLEAR) | \
+                                         _VAL2FLD(TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_SET))
+
+static const cyhal_resource_pin_mapping_t* try_alloc_pwm(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *pin_map, size_t count)
+{
+    for (uint32_t i = 0; i < count; i++)
+    {
+        if (pin == pin_map[i].pin)
+        {
+            if (CY_RSLT_SUCCESS == cyhal_hwmgr_reserve(pin_map[i].inst))
+            {
+                return &pin_map[i];
+            }
+        }
+    }
+    return NULL;
+}
+
+static cy_rslt_t convert_alignment(cyhal_pwm_alignment_t hal_alignment, uint32_t *pdl_alignment, bool swapped)
+{
+    switch (hal_alignment)
+    {
+        case CYHAL_PWM_LEFT_ALIGN:
+            *pdl_alignment = (swapped) ? CY_TCPWM_PWM_RIGHT_ALIGN : CY_TCPWM_PWM_LEFT_ALIGN;
+            return CY_RSLT_SUCCESS;
+        case CYHAL_PWM_RIGHT_ALIGN:
+            *pdl_alignment = (swapped) ? CY_TCPWM_PWM_LEFT_ALIGN : CY_TCPWM_PWM_RIGHT_ALIGN;
+            return CY_RSLT_SUCCESS;
+        case CYHAL_PWM_CENTER_ALIGN:
+            *pdl_alignment = CY_TCPWM_PWM_CENTER_ALIGN;
+            return CY_RSLT_SUCCESS;
+        default:
+            return CYHAL_PWM_RSLT_BAD_ARGUMENT;
+    }
+}
+
+cy_rslt_t cyhal_pwm_init_adv(cyhal_pwm_t *obj, cyhal_gpio_t pin, cyhal_gpio_t pin_compl, cyhal_pwm_alignment_t pwm_alignment, bool continuous, uint32_t dead_time_us, bool invert, const cyhal_clock_divider_t *clk)
+{
+    CY_ASSERT(NULL != obj);
+
+    cy_rslt_t result = CY_RSLT_SUCCESS;
+    bool swapped = false;
+
+    const cyhal_resource_pin_mapping_t* map = try_alloc_pwm(pin, cyhal_pin_map_tcpwm_line, sizeof(cyhal_pin_map_tcpwm_line) / sizeof(cyhal_resource_pin_mapping_t));
+    if (map == NULL)
+    {
+        swapped = true;
+        map = try_alloc_pwm(pin, cyhal_pin_map_tcpwm_line_compl, sizeof(cyhal_pin_map_tcpwm_line_compl) / sizeof(cyhal_resource_pin_mapping_t));
+    }
+    if (map == NULL)
+    {
+        return CYHAL_PWM_RSLT_BAD_ARGUMENT;
+    }
+    else
+    {
+        /* Explicitly marked not allocated resources as invalid to prevent freeing them. */
+        obj->resource.type = CYHAL_RSC_INVALID;
+        obj->dedicated_clock = false;
+        obj->resource = *map->inst;
+        obj->base = CYHAL_TCPWM_DATA[obj->resource.block_num].base;
+        obj->pin = CYHAL_NC_PIN_VALUE;
+        obj->pin_compl = CYHAL_NC_PIN_VALUE;
+
+        result = cyhal_utils_reserve_and_connect(pin, map);
+        if (CY_RSLT_SUCCESS == result)
+        {
+            obj->pin = pin;
+        }
+    }
+
+    if (CY_RSLT_SUCCESS == result && NC != pin_compl)
+    {
+        const cyhal_resource_pin_mapping_t *map_compl = swapped
+            ? CY_UTILS_GET_RESOURCE(pin_compl, cyhal_pin_map_tcpwm_line)
+            : CY_UTILS_GET_RESOURCE(pin_compl, cyhal_pin_map_tcpwm_line_compl);
+
+        if ((NULL == map_compl) || !cyhal_utils_resources_equal(map->inst, map_compl->inst))
+        {
+            result = CYHAL_PWM_RSLT_BAD_ARGUMENT;
+        }
+        else
+        {
+            result = cyhal_utils_reserve_and_connect(pin_compl, map_compl);
+            if (CY_RSLT_SUCCESS == result)
+            {
+                obj->pin_compl = pin_compl;
+            }
+        }
+    }
+
+    if (CY_RSLT_SUCCESS == result)
+    {
+        uint32_t source_hz = Cy_SysClk_ClkPeriGetFrequency();
+        en_clk_dst_t pclk = (en_clk_dst_t)(CYHAL_TCPWM_DATA[obj->resource.block_num].clock_dst + obj->resource.channel_num);
+        if (NULL != clk)
+        {
+            obj->clock_hz = source_hz / (1 + Cy_SysClk_PeriphGetDivider(clk->div_type, clk->div_num));
+            if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, clk->div_type, clk->div_num))
+            {
+                result = CYHAL_PWM_RSLT_FAILED_CLOCK_INIT;
+            }
+        }
+        else
+        {
+            if (CY_RSLT_SUCCESS == (result = cyhal_hwmgr_allocate_clock(&(obj->clock), CY_SYSCLK_DIV_16_BIT, false)))
+            {
+                obj->dedicated_clock = true;
+                uint32_t div = (dead_time_us > 0)
+                    ? (((uint64_t)source_hz * dead_time_us) / (US_PER_SEC * MAX_DEAD_TIME_CYCLES)) + 1
+                    : (uint32_t)(1 << (TCPWM_MAX_WIDTH - CYHAL_TCPWM_DATA[obj->resource.block_num].max_count));
+
+                if (0 == div ||
+                    CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) ||
+                    CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num) ||
+                    CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, obj->clock.div_type, obj->clock.div_num))
+                {
+                    result = CYHAL_PWM_RSLT_FAILED_CLOCK_INIT;
+                }
+                else
+                {
+                    obj->clock_hz = source_hz / div;
+                }
+            }
+        }
+    }
+
+    uint32_t pdl_alignment = CY_TCPWM_PWM_LEFT_ALIGN;
+    if (CY_RSLT_SUCCESS == result)
+    {
+        result = convert_alignment(pwm_alignment, &pdl_alignment, swapped);
+    }
+
+    if (CY_RSLT_SUCCESS == result)
+    {
+        uint8_t dead_time = dead_time_us * obj->clock_hz / US_PER_SEC;
+
+        cy_stc_tcpwm_pwm_config_t config =
+        {
+            .pwmMode           = (dead_time == 0) ? CY_TCPWM_PWM_MODE_PWM : CY_TCPWM_PWM_MODE_DEADTIME,
+            .clockPrescaler    = CY_TCPWM_PWM_PRESCALER_DIVBY_1,
+            .pwmAlignment      = pdl_alignment,
+            .deadTimeClocks    = dead_time,
+            .runMode           = (continuous) ? CY_TCPWM_PWM_CONTINUOUS : CY_TCPWM_PWM_ONESHOT,
+            .period0           = 0UL,
+            .period1           = 0UL,
+            .enablePeriodSwap  = false,
+            .compare0          = 0UL,
+            .compare1          = 0UL,
+            .enableCompareSwap = false,
+            .interruptSources  = CY_TCPWM_INT_NONE,
+            .invertPWMOut      = (invert) ? CY_TCPWM_PWM_INVERT_ENABLE : CY_TCPWM_PWM_INVERT_DISABLE,
+            .invertPWMOutN     = (invert) ? CY_TCPWM_PWM_INVERT_ENABLE : CY_TCPWM_PWM_INVERT_DISABLE,
+            .killMode          = CY_TCPWM_PWM_STOP_ON_KILL,
+            .swapInputMode     = CY_TCPWM_INPUT_RISINGEDGE,
+            .swapInput         = CY_TCPWM_INPUT_0,
+            .reloadInputMode   = CY_TCPWM_INPUT_RISINGEDGE,
+            .reloadInput       = CY_TCPWM_INPUT_0,
+            .startInputMode    = CY_TCPWM_INPUT_RISINGEDGE,
+            .startInput        = CY_TCPWM_INPUT_0,
+            .killInputMode     = CY_TCPWM_INPUT_RISINGEDGE,
+            .killInput         = CY_TCPWM_INPUT_0,
+            .countInputMode    = CY_TCPWM_INPUT_LEVEL,
+            .countInput        = CY_TCPWM_INPUT_1
+        };
+        result = Cy_TCPWM_PWM_Init(obj->base, obj->resource.channel_num, &config);
+        if ((swapped) && (pwm_alignment == CYHAL_PWM_CENTER_ALIGN))
+        {
+            TCPWM_CNT_TR_CTRL2(obj->base, obj->resource.channel_num) = CY_TCPWM_PWM_MODE_CNTR_OR_ASYMM_UO_SWAPPED;
+        }
+    }
+
+    if (CY_RSLT_SUCCESS == result)
+    {
+        cyhal_tcpwm_init_callback_data(&(obj->resource), &(obj->callback_data));
+        Cy_TCPWM_PWM_Enable(obj->base, obj->resource.channel_num);
+    }
+    else
+    {
+        cyhal_pwm_free(obj);
+    }
+
+    return result;
+}
+
+void cyhal_pwm_free(cyhal_pwm_t *obj)
+{
+    CY_ASSERT(NULL != obj);
+
+    IRQn_Type irqn = (IRQn_Type)(CYHAL_TCPWM_DATA[obj->resource.block_num].isr_offset + obj->resource.channel_num);
+    NVIC_DisableIRQ(irqn);
+
+    cyhal_utils_release_if_used(&(obj->pin));
+    cyhal_utils_release_if_used(&(obj->pin_compl));
+
+    if (NULL != obj->base)
+    {
+        Cy_TCPWM_PWM_Disable(obj->base, obj->resource.channel_num);
+
+        cyhal_hwmgr_free(&(obj->resource));
+        obj->base = NULL;
+        obj->resource.type = CYHAL_RSC_INVALID;
+    }
+
+    if (obj->dedicated_clock)
+    {
+        cy_en_sysclk_status_t rslt = Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num);
+        CY_UNUSED_PARAMETER(rslt); /* CY_ASSERT only processes in DEBUG, ignores for others */
+        CY_ASSERT(CY_SYSCLK_SUCCESS == rslt);
+        cyhal_hwmgr_free_clock(&(obj->clock));
+        obj->dedicated_clock = false;
+    }
+}
+
+static cy_rslt_t cyhal_pwm_set_period_and_compare(cyhal_pwm_t *obj, uint32_t period, uint32_t compare)
+{
+    if (period < 1 || period > (uint32_t)((1 << CYHAL_TCPWM_DATA[obj->resource.block_num].max_count)) - 1)
+        return CYHAL_PWM_RSLT_BAD_ARGUMENT;
+    if (compare > period)
+        compare = period;
+
+    cyhal_gpio_t pin = obj->pin;
+    cyhal_gpio_t pin_compl = obj->pin_compl;
+
+    Cy_TCPWM_PWM_SetCompare0(obj->base, obj->resource.channel_num, 0u);
+    Cy_TCPWM_PWM_SetPeriod0(obj->base, obj->resource.channel_num, period - 1u);
+
+    bool swapped_pins = (CY_UTILS_GET_RESOURCE(pin, cyhal_pin_map_tcpwm_line_compl) != NULL) && (CY_UTILS_GET_RESOURCE(pin_compl, cyhal_pin_map_tcpwm_line) != NULL);
+    bool is_center_aligned = (TCPWM_CNT_TR_CTRL2(obj->base, obj->resource.channel_num) == CY_TCPWM_PWM_MODE_CNTR_OR_ASYMM) ||
+                                (TCPWM_CNT_TR_CTRL2(obj->base, obj->resource.channel_num) == CY_TCPWM_PWM_MODE_CNTR_OR_ASYMM_UO_SWAPPED);
+
+    if ((swapped_pins) && (!is_center_aligned))
+    {
+        Cy_TCPWM_PWM_SetCompare0(obj->base, obj->resource.channel_num, period - compare);
+    }
+    else
+    {
+        Cy_TCPWM_PWM_SetCompare0(obj->base, obj->resource.channel_num, compare);
+    }
+
+
+    return CY_RSLT_SUCCESS;
+}
+
+cy_rslt_t cyhal_pwm_set_period(cyhal_pwm_t *obj, uint32_t period_us, uint32_t pulse_width_us)
+{
+    CY_ASSERT(NULL != obj);
+    uint32_t period = (uint32_t)((uint64_t)period_us * obj->clock_hz / US_PER_SEC);
+    uint32_t width = (uint32_t)((uint64_t)pulse_width_us * obj->clock_hz / US_PER_SEC);
+    return cyhal_pwm_set_period_and_compare(obj, period, width);
+}
+
+cy_rslt_t cyhal_pwm_set_duty_cycle(cyhal_pwm_t *obj, float duty_cycle, uint32_t frequencyhal_hz)
+{
+    CY_ASSERT(NULL != obj);
+    if (duty_cycle < 0.0f || duty_cycle > 100.0f || frequencyhal_hz < 1)
+        return CYHAL_PWM_RSLT_BAD_ARGUMENT;
+    uint32_t period = obj->clock_hz / frequencyhal_hz;
+    uint32_t width = (uint32_t)(duty_cycle * 0.01f * period);
+    return cyhal_pwm_set_period_and_compare(obj, period, width);
+}
+
+cy_rslt_t cyhal_pwm_start(cyhal_pwm_t *obj)
+{
+    CY_ASSERT(NULL != obj);
+    Cy_TCPWM_TriggerReloadOrIndex(obj->base, 1u << obj->resource.channel_num);
+    return CY_RSLT_SUCCESS;
+}
+
+cy_rslt_t cyhal_pwm_stop(cyhal_pwm_t *obj)
+{
+    CY_ASSERT(NULL != obj);
+    Cy_TCPWM_TriggerStopOrKill(obj->base, 1u << obj->resource.channel_num);
+    return CY_RSLT_SUCCESS;
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_IP_MXTCPWM */

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_qspi.c

@@ -7,7 +7,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -207,30 +207,6 @@ static cy_rslt_t make_pin_reservations(cyhal_qspi_t *obj)
 
 #endif
 
-/* Free all QSPI pins */
-static void free_pin_connections(cyhal_qspi_t *obj)
-{
-    if (CYHAL_NC_PIN_VALUE != obj->pin_sclk)
-    {
-        cyhal_utils_disconnect_and_free(obj->pin_sclk);
-        obj->pin_sclk = CYHAL_NC_PIN_VALUE;
-    }
-    if (CYHAL_NC_PIN_VALUE != obj->pin_ssel)
-    {
-        cyhal_utils_disconnect_and_free(obj->pin_ssel);
-        obj->pin_ssel = CYHAL_NC_PIN_VALUE;
-    }
-
-    for (uint8_t i = 0; (i < MAX_DATA_PINS); i++)
-    {
-        if (CYHAL_NC_PIN_VALUE != obj->pin_ios[i])
-        {
-            cyhal_utils_disconnect_and_free(obj->pin_ios[i]);
-            obj->pin_ios[i] = CYHAL_NC_PIN_VALUE;
-        }
-    }
-}
-
 /*******************************************************************************
 *       (Internal) QSPI Config Related Functions
 *******************************************************************************/
@@ -292,45 +268,16 @@ static inline uint32_t get_size(cyhal_qspi_size_t hal_size)
     return ((uint32_t)hal_size >> 3); /* convert bits to bytes */
 }
 
-/* cyhal_qspi_bus_width_t to number of bus lines used */
-static uint8_t get_lines(cyhal_qspi_bus_width_t hal_width)
-{
-    uint8_t lines;
-
-    switch (hal_width)
-    {
-        case CYHAL_QSPI_CFG_BUS_SINGLE:
-            lines = 1;
-            break;
-        case CYHAL_QSPI_CFG_BUS_DUAL:
-            lines = 2;
-            break;
-        case CYHAL_QSPI_CFG_BUS_QUAD:
-            lines = 4;
-            break;
-        case CYHAL_QSPI_CFG_BUS_OCTAL:
-            lines = 8;
-            break;
-        default:
-            lines = 0;
-    }
-
-    return lines;
-}
-
 /* Sends QSPI command with certain set of data */
 /* Address passed through 'command' is not used, instead the value in 'addr' is used. */
 static cy_rslt_t qspi_command_transfer(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command,
-    uint32_t addr, bool endOfTransfer, uint8_t *dummy_cycles)
+    uint32_t addr, bool endOfTransfer)
 {
     /* max address size is 4 bytes and max mode bits size is 4 bytes */
     uint8_t cmd_param[8] = {0};
     uint32_t start_pos = 0;
     uint32_t addr_size = 0;
-    uint32_t mode_size = 0;
+    uint32_t mode_bits_size = 0;
-    uint8_t leftover_bits = 0;
-    uint8_t lines = 0;
-    uint8_t integrated_dummy_cycles = 0;
     cy_en_smif_txfr_width_t bus_width = CY_SMIF_WIDTH_SINGLE;
     cy_stc_smif_mem_cmd_t cyhal_cmd_config;
     cy_rslt_t result = CY_RSLT_SUCCESS;
@@ -361,67 +308,22 @@ static cy_rslt_t qspi_command_transfer(cyhal_qspi_t *obj, const cyhal_qspi_comma
         if (!command->address.disabled)
         {
             addr_size = get_size(command->address.size);
-            if (addr_size == 0)
+            uint32_to_byte_array(addr, cmd_param, start_pos, addr_size);
-            {
+            start_pos += addr_size;
-                result = CYHAL_QSPI_RSLT_ERR_SIZE;
+            bus_width = cyhal_cmd_config.addrWidth;
-            }
-            else
-            {
-                uint32_to_byte_array(addr, cmd_param, start_pos, addr_size);
-                start_pos += addr_size;
-                bus_width = cyhal_cmd_config.addrWidth;
-            }
         }
 
         if (!command->mode_bits.disabled)
         {
-            // Mode size must be a multiple of the number of bus lines used (i.e. a whole number of cycles)
+            mode_bits_size = get_size(command->mode_bits.size);
-            lines = get_lines(command->mode_bits.bus_width);
+            uint32_to_byte_array(cyhal_cmd_config.mode, cmd_param, start_pos, mode_bits_size);
-            if (lines == 0)
+            bus_width = cyhal_cmd_config.modeWidth;
-            {
-                result = CYHAL_QSPI_RSLT_ERR_BUS_WIDTH;
-            }
-            else if (command->mode_bits.size % lines != 0)
-            {
-                result = CYHAL_QSPI_RSLT_ERR_ALT_SIZE_WIDTH_MISMATCH;
-            }
-            else
-            {
-                // Round mode size up to nearest byte - unused parts of byte act as dummy cycles
-                mode_size = get_size(command->mode_bits.size - 1) + 1;
-                
-                // Unused bits in most significant byte of mode
-                leftover_bits = (mode_size << 3) - command->mode_bits.size;
-                if (leftover_bits != 0)
-                {
-                    // Account for dummy cycles that will be spent in the mode portion of the command
-                    integrated_dummy_cycles = (8 - (command->mode_bits.size % 8)) / lines;
-                    if (*dummy_cycles < integrated_dummy_cycles)
-                    {
-                        // Not enough dummy cycles to account for a short mode
-                        result = CYHAL_QSPI_RSLT_ERR_ALT_SIZE_DUMMY_CYCLES_MISMATCH;
-                    }
-                    else
-                    {
-                        *dummy_cycles -= integrated_dummy_cycles;
-                    }
-
-                    // Align mode value to the end of the most significant byte
-                    cyhal_cmd_config.mode <<= leftover_bits;
-                }
-
-                uint32_to_byte_array(cyhal_cmd_config.mode, cmd_param, start_pos, mode_size);
-                bus_width = cyhal_cmd_config.modeWidth;
-            }
         }
 
-        if (CY_RSLT_SUCCESS == result)
+        uint32_t cmpltTxfr = ((endOfTransfer) ? 1UL : 0UL);
-        {
+        result = (cy_rslt_t)Cy_SMIF_TransmitCommand(obj->base, cyhal_cmd_config.command,
-            uint32_t cmpltTxfr = ((endOfTransfer) ? 1UL : 0UL);
+                                                         cyhal_cmd_config.cmdWidth, cmd_param, (addr_size + mode_bits_size),
-            result = (cy_rslt_t)Cy_SMIF_TransmitCommand(obj->base, cyhal_cmd_config.command,
+                                                         bus_width, obj->slave_select, cmpltTxfr, &obj->context);
-                                                             cyhal_cmd_config.cmdWidth, cmd_param, (addr_size + mode_size),
-                                                             bus_width, obj->slave_select, cmpltTxfr, &obj->context);
-        }
     }
     return result;
 }
@@ -817,10 +719,10 @@ cy_rslt_t cyhal_qspi_init(
         }
     }
 
-    if (CY_RSLT_SUCCESS == result)
+    /* cyhal_qspi_set_frequency should be called here.
-    {
+       Changing clock frequency is not supported on this device.
-        result = cyhal_qspi_set_frequency(obj, hz);
+    */
-    }
+   (void)hz;
 
     if (CY_RSLT_SUCCESS == result)
     {
@@ -866,15 +768,20 @@ void cyhal_qspi_free(cyhal_qspi_t *obj)
         obj->resource.type = CYHAL_RSC_INVALID;
     }
 
-    free_pin_connections(obj);
+    cyhal_utils_release_if_used(&(obj->pin_sclk));
+    cyhal_utils_release_if_used(&(obj->pin_ssel));
+    for (uint8_t i = 0; (i < MAX_DATA_PINS); i++)
+    {
+        cyhal_utils_release_if_used(&(obj->pin_ios[i]));
+    }
 }
 
 cy_rslt_t cyhal_qspi_set_frequency(cyhal_qspi_t *obj, uint32_t hz)
 {
-    /* TODO after HAL clock management implemented JIRA: BSP-510 */
+    /* Changing clock frequency is not supported on this device. */
     (void) obj;
     (void) hz;
-    return CY_RSLT_SUCCESS;
+    return CYHAL_QSPI_RSLT_ERR_FREQUENCY;
 }
 
 /* no restriction on the value of length. This function splits the read into multiple chunked transfers. */
@@ -884,7 +791,6 @@ cy_rslt_t cyhal_qspi_read(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command
     uint32_t chunk = 0;
     size_t read_bytes = *length;
     uint32_t addr = command->address.value;
-    uint8_t dummy_cycles = command->dummy_count;
 
     /* SMIF can read only up to 65536 bytes in one go. Split the larger read into multiple chunks */
     while (read_bytes > 0)
@@ -898,11 +804,11 @@ cy_rslt_t cyhal_qspi_read(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command
          * to create a copy of the command object. Instead of copying the object, the address is
          * passed separately.
          */
-        status = qspi_command_transfer(obj, command, addr, false, &dummy_cycles);
+        status = qspi_command_transfer(obj, command, addr, false);
 
         if (CY_RSLT_SUCCESS == status)
         {
-            if (dummy_cycles > 0u)
+            if (command->dummy_count > 0u)
             {
                 status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, command->dummy_count);
             }
@@ -927,15 +833,13 @@ cy_rslt_t cyhal_qspi_read(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command
 
 cy_rslt_t cyhal_qspi_read_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, void *data, size_t *length)
 {
-    cy_rslt_t status = CY_RSLT_SUCCESS;
+    cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false);
-    uint32_t addr = command->address.value;
+
-    uint8_t dummy_cycles = command->dummy_count;
-    status = qspi_command_transfer(obj, command, addr, false, &dummy_cycles);
     if (CY_RSLT_SUCCESS == status)
     {
         if (command->dummy_count > 0u)
         {
-            status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, dummy_cycles);
+            status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, command->dummy_count);
         }
 
         if (CY_RSLT_SUCCESS == status)
@@ -950,14 +854,13 @@ cy_rslt_t cyhal_qspi_read_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t *c
 /* length can be up to 65536. */
 cy_rslt_t cyhal_qspi_write(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, const void *data, size_t *length)
 {
-    uint8_t dummy_cycles = command->dummy_count;
+    cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false);
-    cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false, &dummy_cycles);
 
     if (CY_RSLT_SUCCESS == status)
     {
         if (command->dummy_count > 0u)
         {
-            status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, dummy_cycles);
+            status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, command->dummy_count);
         }
 
         if ((CY_SMIF_SUCCESS == status) && (*length > 0))
@@ -973,14 +876,13 @@ cy_rslt_t cyhal_qspi_write(cyhal_qspi_t *obj, const cyhal_qspi_command_t *comman
 /* length can be up to 65536. */
 cy_rslt_t cyhal_qspi_write_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, const void *data, size_t *length)
 {
-    uint8_t dummy_cycles = command->dummy_count;
+    cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false);
-    cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false, &dummy_cycles);
 
     if (CY_RSLT_SUCCESS == status)
     {
         if (command->dummy_count > 0u)
         {
-            status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, dummy_cycles);
+            status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, command->dummy_count);
         }
 
         if ((CY_SMIF_SUCCESS == status) && (*length > 0))
@@ -1001,7 +903,7 @@ cy_rslt_t cyhal_qspi_transfer(
     if ((tx_data == NULL || tx_size == 0) && (rx_data == NULL || rx_size == 0))
     {
         /* only command, no rx or tx */
-        status = qspi_command_transfer(obj, command, command->address.value, true, NULL);
+        status = qspi_command_transfer(obj, command, command->address.value, true);
     }
     else
     {

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_rtc.c

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -26,6 +26,7 @@
 *******************************************************************************/
 
 #include "cy_rtc.h"
+#include "cy_utils.h"
 #include "cyhal_rtc.h"
 #include "cyhal_system.h"
 
@@ -39,7 +40,7 @@ extern "C" {
 #define CYHAL_RTC_STATE_ENABLED 1
 #define CYHAL_RTC_STATE_TIME_SET 2
 #define CYHAL_RTC_DEFAULT_PRIORITY 5
-#define CYHAL_RTC_INIT_CENTURY 2000
+#define CYHAL_RTC_CENTURY 2000
 #define CYHAL_TM_YEAR_BASE 1900
 
 /** Wrapper around the PDL Cy_RTC_DeepSleepCallback to adapt the function signature */
@@ -48,24 +49,25 @@ static cy_en_syspm_status_t cyhal_rtc_syspm_callback(cy_stc_syspm_callback_param
     return Cy_RTC_DeepSleepCallback(params, mode);
 }
 
+static cy_stc_rtc_dst_t *dst;
 static cy_stc_syspm_callback_params_t cyhal_rtc_pm_cb_params = {NULL, NULL};
 static cy_stc_syspm_callback_t cyhal_rtc_pm_cb = {
     .callback = &cyhal_rtc_syspm_callback,
     .type = CY_SYSPM_DEEPSLEEP,
     .callbackParams = &cyhal_rtc_pm_cb_params,
 };
+
 static cyhal_rtc_event_callback_t cyhal_rtc_user_handler;
 static void *cyhal_rtc_handler_arg;
-#define CYHAL_RTC_INITIAL_CENTURY 1900
-static uint16_t cyhal_rtc_century = CYHAL_RTC_INITIAL_CENTURY;
 static uint8_t cyhal_rtc_initialized = CYHAL_RTC_STATE_UNINITIALIZED;
 
 /** Wrapper around the PDL RTC interrupt handler to adapt the function signature */
 static void cyhal_rtc_internal_handler(void)
 {
-    Cy_RTC_Interrupt(NULL, false);
+    Cy_RTC_Interrupt(dst, NULL != dst);
 }
 
+/* Override weak function from PDL */
 void Cy_RTC_Alarm1Interrupt(void)
 {
     if (NULL != cyhal_rtc_user_handler)
@@ -74,64 +76,56 @@ void Cy_RTC_Alarm1Interrupt(void)
     }
 }
 
-void Cy_RTC_CenturyInterrupt(void)
-{
-    cyhal_rtc_century += 100;
-}
-
 cy_rslt_t cyhal_rtc_init(cyhal_rtc_t *obj)
 {
     CY_ASSERT(NULL != obj);
     cy_rslt_t rslt = CY_RSLT_SUCCESS;
     if (cyhal_rtc_initialized == CYHAL_RTC_STATE_UNINITIALIZED)
     {
-        if (Cy_RTC_IsExternalResetOccurred())
+        static const cy_stc_sysint_t irqCfg = {.intrSrc = srss_interrupt_backup_IRQn, .intrPriority = CYHAL_RTC_DEFAULT_PRIORITY};
+        Cy_SysInt_Init(&irqCfg, &cyhal_rtc_internal_handler);
+
+        if (Cy_SysPm_RegisterCallback(&cyhal_rtc_pm_cb))
         {
-            // Reset to default time
+            cyhal_rtc_initialized = CYHAL_RTC_STATE_ENABLED;
-            static const cy_stc_rtc_config_t defaultTime = {
-                .dayOfWeek = CY_RTC_THURSDAY,
-                .date = 1,
-                .month = 1,
-                .year = 70
-            };
-            Cy_RTC_SetDateAndTime(&defaultTime);
         }
         else
         {
-            // Time is already set (possibly after sw reset). Assume century.
+            rslt = CY_RSLT_RTC_NOT_INITIALIZED;
-            cyhal_rtc_century = CYHAL_RTC_INIT_CENTURY;
         }
-        Cy_RTC_ClearInterrupt(CY_RTC_INTR_CENTURY);
-        Cy_RTC_SetInterruptMask(CY_RTC_INTR_CENTURY);
-        static const cy_stc_sysint_t irqCfg = {.intrSrc = srss_interrupt_backup_IRQn, .intrPriority = CYHAL_RTC_DEFAULT_PRIORITY};
-        Cy_SysInt_Init(&irqCfg, &cyhal_rtc_internal_handler);
-        Cy_SysPm_RegisterCallback(&cyhal_rtc_pm_cb);
-        cyhal_rtc_initialized = CYHAL_RTC_STATE_ENABLED;
     }
-    NVIC_EnableIRQ(srss_interrupt_backup_IRQn);
+    if (rslt == CY_RSLT_SUCCESS)
+    {
+        dst = NULL;
+        NVIC_EnableIRQ(srss_interrupt_backup_IRQn);
+    }
+
     return rslt;
 }
 
 void cyhal_rtc_free(cyhal_rtc_t *obj)
 {
+    CY_ASSERT(NULL != obj);
     NVIC_DisableIRQ(srss_interrupt_backup_IRQn);
 
-    Cy_RTC_SetInterruptMask(CY_RTC_INTR_CENTURY);
+    dst = NULL;
 }
 
 bool cyhal_rtc_is_enabled(cyhal_rtc_t *obj)
 {
+    CY_ASSERT(NULL != obj);
     return (cyhal_rtc_initialized == CYHAL_RTC_STATE_TIME_SET);
 }
 
 cy_rslt_t cyhal_rtc_read(cyhal_rtc_t *obj, struct tm *time)
 {
     // The number of days that precede each month of the year, not including Feb 29
+    CY_ASSERT(NULL != obj);
     static const uint16_t CUMULATIVE_DAYS[] = {0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334};
     cy_stc_rtc_config_t dateTime;
     uint32_t savedIntrStatus = cyhal_system_critical_section_enter();
     Cy_RTC_GetDateAndTime(&dateTime);
-    int year = dateTime.year + cyhal_rtc_century;
+    int year = dateTime.year + CYHAL_RTC_CENTURY;
     cyhal_system_critical_section_exit(savedIntrStatus);
     time->tm_sec = dateTime.sec;
     time->tm_min = dateTime.min;
@@ -148,6 +142,11 @@ cy_rslt_t cyhal_rtc_read(cyhal_rtc_t *obj, struct tm *time)
 
 cy_rslt_t cyhal_rtc_write(cyhal_rtc_t *obj, const struct tm *time)
 {
+    CY_ASSERT(NULL != obj);
+    int year = CYHAL_TM_YEAR_BASE + time->tm_year;
+    if (year < 2000 || year > 2099) {
+        return CY_RSLT_RTC_BAD_ARGUMENT;
+    }
     uint32_t year2digit = time->tm_year % 100;
     cy_stc_rtc_config_t newtime = {
     .sec = time->tm_sec,
@@ -165,11 +164,7 @@ cy_rslt_t cyhal_rtc_write(cyhal_rtc_t *obj, const struct tm *time)
     do {
         if (retry != 0)
             Cy_SysLib_Delay(RETRY_DELAY_MS);
-        uint32_t savedIntrStatus = cyhal_system_critical_section_enter();
         rslt = (cy_rslt_t)Cy_RTC_SetDateAndTime(&newtime);
-        if (rslt == CY_RSLT_SUCCESS)
-            cyhal_rtc_century = time->tm_year - year2digit + CYHAL_TM_YEAR_BASE;
-        cyhal_system_critical_section_exit(savedIntrStatus);
         ++retry;
     } while (rslt == CY_RTC_INVALID_STATE && retry < MAX_RETRY);
     while (CY_RTC_BUSY == Cy_RTC_GetSyncStatus()) { }
@@ -178,9 +173,46 @@ cy_rslt_t cyhal_rtc_write(cyhal_rtc_t *obj, const struct tm *time)
     return rslt;
 }
 
+static void initialize_dst(const cyhal_rtc_dst_t *hal, cy_stc_rtc_dst_format_t *pdl)
+{
+    pdl->format = (hal->format == CYHAL_RTC_DST_FIXED) ? CY_RTC_DST_FIXED : CY_RTC_DST_RELATIVE;
+    pdl->hour = hal->hour;
+    pdl->dayOfMonth = (hal->format == CYHAL_RTC_DST_FIXED) ? hal->dayOfMonth : 1;
+    pdl->weekOfMonth = (hal->format == CYHAL_RTC_DST_FIXED) ? 1 : hal->weekOfMonth + 1;
+    pdl->dayOfWeek = (hal->format == CYHAL_RTC_DST_FIXED) ? 1 : hal->dayOfWeek + 1;
+    pdl->month = hal->month;
+}
+
+cy_rslt_t cyhal_rtc_set_dst(cyhal_rtc_t *obj, const cyhal_rtc_dst_t *start, const cyhal_rtc_dst_t *stop)
+{
+    CY_ASSERT(NULL != obj);
+    CY_ASSERT(NULL != start);
+    CY_ASSERT(NULL != stop);
+
+    initialize_dst(start, &(obj->dst.startDst));
+    initialize_dst(stop, &(obj->dst.stopDst));
+
+    cy_stc_rtc_config_t dateTime;
+    Cy_RTC_GetDateAndTime(&dateTime);
+    cy_rslt_t rslt = Cy_RTC_EnableDstTime(&(obj->dst), &dateTime);
+    if (rslt == CY_RSLT_SUCCESS)
+        dst = &(obj->dst);
+    return rslt;
+}
+
+bool cyhal_rtc_is_dst(cyhal_rtc_t *obj)
+{
+    CY_ASSERT(NULL != obj);
+
+    cy_stc_rtc_config_t dateTime;
+    Cy_RTC_GetDateAndTime(&dateTime);
+    return Cy_RTC_GetDstStatus(&(obj->dst), &dateTime);
+}
+
 cy_rslt_t cyhal_rtc_set_alarm(cyhal_rtc_t *obj, const struct tm *time, cyhal_alarm_active_t active)
 {
     // Note: the hardware does not support year matching
+    CY_ASSERT(NULL != obj);
     cy_stc_rtc_alarm_t alarm = {
     .sec = time->tm_sec,
     .secEn = active.en_sec ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE,
@@ -201,6 +233,7 @@ cy_rslt_t cyhal_rtc_set_alarm(cyhal_rtc_t *obj, const struct tm *time, cyhal_ala
 
 void cyhal_rtc_register_callback(cyhal_rtc_t *obj, cyhal_rtc_event_callback_t callback, void *callback_arg)
 {
+    CY_ASSERT(NULL != obj);
     uint32_t savedIntrStatus = cyhal_system_critical_section_enter();
     cyhal_rtc_handler_arg = callback_arg;
     cyhal_rtc_user_handler = callback;
@@ -209,8 +242,11 @@ void cyhal_rtc_register_callback(cyhal_rtc_t *obj, cyhal_rtc_event_callback_t ca
 
 void cyhal_rtc_enable_event(cyhal_rtc_t *obj, cyhal_rtc_event_t event, uint8_t intrPriority, bool enable)
 {
+    CY_ASSERT(NULL != obj);
+    CY_ASSERT(CYHAL_RTC_ALARM == event);
     Cy_RTC_ClearInterrupt(CY_RTC_INTR_ALARM1 | CY_RTC_INTR_ALARM2);
-    Cy_RTC_SetInterruptMask((enable ? CY_RTC_INTR_ALARM1 : 0) | CY_RTC_INTR_CENTURY);
+    Cy_RTC_SetInterruptMask(enable ? CY_RTC_INTR_ALARM1 : 0);
+    NVIC_SetPriority(srss_interrupt_backup_IRQn, intrPriority);
 }
 
 #if defined(__cplusplus)

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_scb_common.c

@@ -6,7 +6,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_sdhc.c

@@ -7,7 +7,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -26,6 +26,7 @@
 #include <string.h> /* For memcpy */
 #include <stdlib.h>
 #include "cy_pdl.h"
+#include "cy_utils.h"
 #include "cy_result.h"
 #include "cyhal_sdhc.h"
 #include "cyhal_sdio.h"
@@ -71,12 +72,9 @@ extern "C"
 
 #define BIT_MASK( x )                       (( 1 << x ) - 1 )
 
-#define SDIO_PINS_NC                        ((cyhal_gpio_t) CYHAL_NC_PIN_VALUE)
-
 /* Macro-function to calculate pin mapping number */
 #define COUNT(pin_mapping)    (sizeof(pin_mapping)/sizeof(cyhal_resource_pin_mapping_t))
 
-
 #if (defined(SDHC_CHIP_TOP_DATA8_PRESENT) && (SDHC_CHIP_TOP_DATA8_PRESENT))   || \
     (defined(SDHC0_CHIP_TOP_DATA8_PRESENT) && (SDHC0_CHIP_TOP_DATA8_PRESENT)) || \
     (defined(SDHC1_CHIP_TOP_DATA8_PRESENT) && (SDHC1_CHIP_TOP_DATA8_PRESENT))
@@ -224,20 +222,11 @@ static const uint32_t eventMap[SDHC_EVENTS_NUM][SDHC_EVENTS_MAP_NUM] =
     { (uint32_t)CYHAL_SDHC_ERR_INTERRUPT,   (uint32_t)CY_SD_HOST_ERR_INTERRUPT },
 };
 
-static void release_pin_if_used(cyhal_gpio_t *pin)
-{
-    if (CYHAL_NC_PIN_VALUE != *pin)
-    {
-        cyhal_utils_disconnect_and_free(*pin);
-        *pin = CYHAL_NC_PIN_VALUE;
-    }
-}
-
 static cy_rslt_t setup_pin(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *pinmap, size_t count, cyhal_gpio_t *objRef)
 {
     cyhal_resource_inst_t pin_rsc = cyhal_utils_get_gpio_resource(pin);
     cy_rslt_t result = cyhal_hwmgr_reserve(&pin_rsc);
-    
+
     if (result == CY_RSLT_SUCCESS)
     {
         const cyhal_resource_pin_mapping_t *map = cyhal_utils_get_resource(pin, pinmap, count);
@@ -269,9 +258,9 @@ static cy_rslt_t setup_pin(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t
 static bool isTransferInProcess = false;
 
 /* Internal functions */
-static cy_en_sd_host_status_t Cy_SD_Host_PollTransferComplete(SDHC_Type *base, const uint16_t delay);
+static cy_en_sd_host_status_t cyhal_sd_host_polltransfercomplete(SDHC_Type *base, const uint16_t delay);
-static cy_en_sd_host_status_t Cy_SD_Host_PollCmdComplete(SDHC_Type *base);
+static cy_en_sd_host_status_t cyhal_sd_host_pollcmdcomplete(SDHC_Type *base);
-static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint32_t instance_num, uint32_t frequency);
+static cy_en_sd_host_status_t cyhal_sd_host_sdcardchangeclock(SDHC_Type *base, uint32_t instance_num, uint32_t frequency);
 static cy_en_sd_host_bus_width_t convert_buswidth(uint8_t stopbits);
 static cy_en_syspm_status_t cyhal_sdio_syspm_callback(cy_stc_syspm_callback_params_t *params,
                                                       cy_en_syspm_callback_mode_t mode);
@@ -363,7 +352,7 @@ static cy_en_sd_host_bus_width_t convert_buswidth(uint8_t stopbits)
 
 
 /*******************************************************************************
-* Function Name: Cy_SD_Host_SdCardChangeClock
+* Function Name: cyhal_sd_host_sdcardchangeclock
 ****************************************************************************//**
 *
 *  Changes the Host controller SD clock.
@@ -380,19 +369,19 @@ static cy_en_sd_host_bus_width_t convert_buswidth(uint8_t stopbits)
 * \return \ref cy_en_sd_host_status_t
 *
 *******************************************************************************/
-static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint32_t instance_num, uint32_t frequency)
+static cy_en_sd_host_status_t cyhal_sd_host_sdcardchangeclock(SDHC_Type *base, uint32_t instance_num, uint32_t frequency)
 {
     cy_en_sd_host_status_t ret = CY_SD_HOST_ERROR_INVALID_PARAMETER;
     uint32_t clockInput = 0;
-    
+
-    cy_rslt_t get_frequency_result = 
+    cy_rslt_t get_frequency_result =
     cyhal_system_clock_get_frequency(CYHAL_SDHC_HF_CLOCKS[instance_num], &clockInput);
 
     if ((NULL != base) && (get_frequency_result == CY_RSLT_SUCCESS) && (0U != clockInput))
     {
         /* Update SD Host clock divider */
         uint16_t clkDiv = (uint16_t) ((clockInput / frequency) >> 1UL);
-        
+
         Cy_SD_Host_DisableSdClk(base);
         ret = Cy_SD_Host_SetSdClkDiv(base, clkDiv);
         Cy_SD_Host_EnableSdClk(base);
@@ -424,7 +413,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint
 
 
 /*******************************************************************************
-* Function Name: Cy_SD_Host_PollCmdComplete
+* Function Name: cyhal_sd_host_pollcmdcomplete
 ****************************************************************************//**
 *
 *  Waits for the command complete event.
@@ -435,7 +424,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint
 * \return \ref cy_en_sd_host_status_t
 *
 *******************************************************************************/
-static cy_en_sd_host_status_t Cy_SD_Host_PollCmdComplete(SDHC_Type *base)
+static cy_en_sd_host_status_t cyhal_sd_host_pollcmdcomplete(SDHC_Type *base)
 {
     cy_en_sd_host_status_t ret = CY_SD_HOST_ERROR_TIMEOUT;
     uint32_t               retry = SDHC_RETRY_TIMES;
@@ -461,7 +450,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_PollCmdComplete(SDHC_Type *base)
 
 
 /*******************************************************************************
-* Function Name: Cy_SD_Host_PollTransferComplete
+* Function Name: cyhal_sd_host_polltransfercomplete
 ****************************************************************************//**
 *
 *  Waits for the command complete event.
@@ -477,7 +466,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_PollCmdComplete(SDHC_Type *base)
 *      If the pointer is NULL, returns error.
 *
 *******************************************************************************/
-static cy_en_sd_host_status_t Cy_SD_Host_PollTransferComplete(SDHC_Type *base, const uint16_t delay)
+static cy_en_sd_host_status_t cyhal_sd_host_polltransfercomplete(SDHC_Type *base, const uint16_t delay)
 {
     cy_en_sd_host_status_t ret = CY_SD_HOST_ERROR_TIMEOUT;
     uint32_t               retry = SDHC_RW_RETRY_CYCLES;
@@ -578,9 +567,9 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj,
     CY_ASSERT(NULL != obj);
 
     cy_rslt_t result = CY_RSLT_SUCCESS;
-    
+
     obj->base = NULL;
-    
+
     obj->pin_clk = CYHAL_NC_PIN_VALUE;
     obj->pin_cmd = CYHAL_NC_PIN_VALUE;
     obj->pin_data[0] = CYHAL_NC_PIN_VALUE;
@@ -655,8 +644,8 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj,
     if ((NC != cardDetect) && (CY_RSLT_SUCCESS == result))
     {
 #if CARD_DETECT_PRESENT
-        result = setup_pin(cardDetect, cyhal_pin_map_sdhc_card_detect_n, 
+        result = setup_pin(cardDetect, cyhal_pin_map_sdhc_card_detect_n,
-                                       COUNT(cyhal_pin_map_sdhc_card_detect_n), &(obj->pin_cardDetect));
+            COUNT(cyhal_pin_map_sdhc_card_detect_n), &(obj->pin_cardDetect));
 #else
         result = CYHAL_SDHC_RSLT_ERR_PIN;
 #endif
@@ -665,8 +654,8 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj,
     if ((NC != ioVoltSel) && (CY_RSLT_SUCCESS == result))
     {
 #if IO_VOLT_SEL_PRESENT
-        result = setup_pin(ioVoltSel, cyhal_pin_map_sdhc_io_volt_sel, 
+        result = setup_pin(ioVoltSel, cyhal_pin_map_sdhc_io_volt_sel,
-                            COUNT(cyhal_pin_map_sdhc_io_volt_sel), &(obj->pin_ioVoltSel));
+            COUNT(cyhal_pin_map_sdhc_io_volt_sel), &(obj->pin_ioVoltSel));
 #else
         result = CYHAL_SDHC_RSLT_ERR_PIN;
 #endif
@@ -675,8 +664,8 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj,
     if ((NC != cardIfPwrEn) && (CY_RSLT_SUCCESS == result))
     {
 #if CARD_IF_PWR_EN_PRESENT
-        result = setup_pin(cardIfPwrEn, cyhal_pin_map_sdhc_card_if_pwr_en, 
+        result = setup_pin(cardIfPwrEn, cyhal_pin_map_sdhc_card_if_pwr_en,
-                            COUNT(cyhal_pin_map_sdhc_card_if_pwr_en), &(obj->pin_cardIfPwrEn));
+            COUNT(cyhal_pin_map_sdhc_card_if_pwr_en), &(obj->pin_cardIfPwrEn));
 #else
         result = CYHAL_SDHC_RSLT_ERR_PIN;
 #endif
@@ -685,8 +674,8 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj,
     if ((NC != cardMechWriteProt) && (CY_RSLT_SUCCESS == result))
     {
 #if CARD_WRITE_PROT_PRESENT
-        result = setup_pin(cardMechWriteProt, cyhal_pin_map_sdhc_card_mech_write_prot, 
+        result = setup_pin(cardMechWriteProt, cyhal_pin_map_sdhc_card_mech_write_prot,
-                            COUNT(cyhal_pin_map_sdhc_card_mech_write_prot), &(obj->pin_cardMechWriteProt));
+            COUNT(cyhal_pin_map_sdhc_card_mech_write_prot), &(obj->pin_cardMechWriteProt));
 #else
         result = CYHAL_SDHC_RSLT_ERR_PIN;
 #endif
@@ -695,8 +684,8 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj,
     if ((NC != ledCtrl) && (CY_RSLT_SUCCESS == result))
     {
 #if LED_CTRL_PRESENT
-        result = setup_pin(ledCtrl, cyhal_pin_map_sdhc_led_ctrl, 
+        result = setup_pin(ledCtrl, cyhal_pin_map_sdhc_led_ctrl,
-                            COUNT(cyhal_pin_map_sdhc_led_ctrl), &(obj->pin_ledCtrl));
+            COUNT(cyhal_pin_map_sdhc_led_ctrl), &(obj->pin_ledCtrl));
 #else
         result = CYHAL_SDHC_RSLT_ERR_PIN;
 #endif
@@ -705,8 +694,8 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj,
     if ((NC != cardEmmcReset) && (CY_RSLT_SUCCESS == result))
     {
 #if CARD_EMMC_RESET_PRESENT
-        result = setup_pin(cardEmmcReset, cyhal_pin_map_sdhc_card_emmc_reset_n, 
+        result = setup_pin(cardEmmcReset, cyhal_pin_map_sdhc_card_emmc_reset_n,
-                            COUNT(cyhal_pin_map_sdhc_card_emmc_reset_n), &(obj->pin_cardEmmcReset));
+            COUNT(cyhal_pin_map_sdhc_card_emmc_reset_n), &(obj->pin_cardEmmcReset));
 #else
         result = CYHAL_SDHC_RSLT_ERR_PIN;
 #endif
@@ -755,7 +744,7 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj,
             cy_stc_sysint_t irqCfg = { irqn, CYHAL_ISR_PRIORITY_DEFAULT };
             Cy_SysInt_Init(&irqCfg, cyhal_sdhc_irq_handler);
             NVIC_EnableIRQ(irqn);
-            
+
             result = (cy_rslt_t) Cy_SD_Host_Init(obj->base, &hostConfig, &obj->context);
         }
 
@@ -776,11 +765,11 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj,
 
             /* Initialize the card */
             result = (cy_rslt_t)Cy_SD_Host_InitCard(obj->base, &stcSdcardCfg, &obj->context);
-            
+
             if (result == CY_RSLT_SUCCESS)
             {
                 /* Update SD Card frequency to be 25 Mhz */
-                result = (cy_rslt_t) Cy_SD_Host_SdCardChangeClock(obj->base, obj->resource.block_num, CY_SD_HOST_CLK_25M);
+                result = (cy_rslt_t) cyhal_sd_host_sdcardchangeclock(obj->base, obj->resource.block_num, CY_SD_HOST_CLK_25M);
             }
         }
     }
@@ -803,15 +792,15 @@ void cyhal_sdhc_free(cyhal_sdhc_t *obj)
         NVIC_DisableIRQ(irqn);
 
         Cy_SD_Host_DeInit(obj->base);
-        
+
         cyhal_hwmgr_free(&(obj->resource));
         obj->base = NULL;
         obj->resource.type = CYHAL_RSC_INVALID;
     }
 
     /* Free pins */
-    release_pin_if_used(&obj->pin_cmd);
+    cyhal_utils_release_if_used(&(obj->pin_cmd));
-    release_pin_if_used(&obj->pin_clk);
+    cyhal_utils_release_if_used(&(obj->pin_clk));
 
 #if DATA8_PRESENT
     const uint8_t max_idx = 8;
@@ -820,31 +809,31 @@ void cyhal_sdhc_free(cyhal_sdhc_t *obj)
 #endif
     for (uint8_t i = 0; i < max_idx; i++)
     {
-        release_pin_if_used(&obj->pin_data[i]);
+        cyhal_utils_release_if_used(&(obj->pin_data[i]));
     }
 
 #if CARD_DETECT_PRESENT
-    release_pin_if_used(&obj->pin_cardDetect);
+    cyhal_utils_release_if_used(&(obj->pin_cardDetect));
 #endif
 
 #if IO_VOLT_SEL_PRESENT
-    release_pin_if_used(&obj->pin_ioVoltSel);
+    cyhal_utils_release_if_used(&(obj->pin_ioVoltSel));
 #endif
 
 #if CARD_IF_PWR_EN_PRESENT
-    release_pin_if_used(&obj->pin_cardIfPwrEn);
+    cyhal_utils_release_if_used(&(obj->pin_cardIfPwrEn));
 #endif
 
 #if CARD_WRITE_PROT_PRESENT
-    release_pin_if_used(&obj->pin_cardMechWriteProt);
+    cyhal_utils_release_if_used(&(obj->pin_cardMechWriteProt));
 #endif
 
 #if LED_CTRL_PRESENT
-    release_pin_if_used(&obj->pin_ledCtrl);
+    cyhal_utils_release_if_used(&(obj->pin_ledCtrl));
 #endif
 
 #if CARD_EMMC_RESET_PRESENT
-    release_pin_if_used(&obj->pin_cardEmmcReset);
+    cyhal_utils_release_if_used(&(obj->pin_cardEmmcReset));
 #endif
 }
 
@@ -879,14 +868,14 @@ cy_rslt_t cyhal_sdhc_read(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *da
     }
     else
     {
-        driverRet = Cy_SD_Host_PollTransferComplete(obj->base, SDHC_RW_TIMEOUT_US);
+        driverRet = cyhal_sd_host_polltransfercomplete(obj->base, SDHC_RW_TIMEOUT_US);
-    
+
         if (CY_SD_HOST_SUCCESS != driverRet)
         {
             ret = CY_RSLT_TYPE_ERROR;
         }
     }
-    
+
     /* Restore interrupts after transition */
     Cy_SD_Host_SetNormalInterruptMask(obj->base, regIntrSts);
 
@@ -933,7 +922,7 @@ cy_rslt_t cyhal_sdhc_write(const cyhal_sdhc_t *obj, uint32_t address, const uint
     }
     else
     {
-        driverRet = Cy_SD_Host_PollTransferComplete(obj->base, SDHC_RW_TIMEOUT_US);
+        driverRet = cyhal_sd_host_polltransfercomplete(obj->base, SDHC_RW_TIMEOUT_US);
 
         if (CY_SD_HOST_SUCCESS != driverRet)
         {
@@ -984,7 +973,7 @@ cy_rslt_t cyhal_sdhc_erase(const cyhal_sdhc_t *obj, uint32_t startAddr, size_t l
     }
     else
     {
-        driverRet = Cy_SD_Host_PollCmdComplete(obj->base);
+        driverRet = cyhal_sd_host_pollcmdcomplete(obj->base);
     }
 
     if (CY_SD_HOST_SUCCESS != driverRet)
@@ -1037,15 +1026,23 @@ cy_rslt_t cyhal_sdhc_erase(const cyhal_sdhc_t *obj, uint32_t startAddr, size_t l
 
 cy_rslt_t cyhal_sdhc_read_async(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *data, size_t *length)
 {
-    cy_rslt_t ret = CY_RSLT_SUCCESS;
+    /* Not yet implemented for this device. */
-    //TODO: implement
+    CY_UNUSED_PARAMETER(obj);
+    CY_UNUSED_PARAMETER(address);
+    CY_UNUSED_PARAMETER(data);
+    CY_UNUSED_PARAMETER(length);
+    cy_rslt_t ret = CYHAL_SDHC_RSLT_ERR_UNSUPPORTED;
     return ret;
 }
 
 cy_rslt_t cyhal_sdhc_write_async(const cyhal_sdhc_t *obj, uint32_t address, const uint8_t *data, size_t *length)
 {
-    cy_rslt_t ret = CY_RSLT_SUCCESS;
+    /* Not yet implemented for this device. */
-    //TODO: implement
+    CY_UNUSED_PARAMETER(obj);
+    CY_UNUSED_PARAMETER(address);
+    CY_UNUSED_PARAMETER(data);
+    CY_UNUSED_PARAMETER(length);
+    cy_rslt_t ret = CYHAL_SDHC_RSLT_ERR_UNSUPPORTED;
     return ret;
 }
 
@@ -1186,37 +1183,37 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk,
     obj->pin_data2 = CYHAL_NC_PIN_VALUE;
     obj->pin_data3 = CYHAL_NC_PIN_VALUE;
 
-    result = setup_pin(
+    result = setup_pin(cmd, cyhal_pin_map_sdhc_card_cmd,
-        cmd, cyhal_pin_map_sdhc_card_cmd, COUNT(cyhal_pin_map_sdhc_card_cmd), &(obj->pin_cmd));
+        COUNT(cyhal_pin_map_sdhc_card_cmd), &(obj->pin_cmd));
 
     if (CY_RSLT_SUCCESS == result)
     {
-        result = setup_pin(
+        result = setup_pin(clk, cyhal_pin_map_sdhc_clk_card,
-            clk, cyhal_pin_map_sdhc_clk_card, COUNT(cyhal_pin_map_sdhc_clk_card), &(obj->pin_clk));
+            COUNT(cyhal_pin_map_sdhc_clk_card), &(obj->pin_clk));
     }
 
     if (CY_RSLT_SUCCESS == result)
     {
-        result = setup_pin(
+        result = setup_pin(data0, cyhal_pin_map_sdhc_card_dat_3to0,
-            data0, cyhal_pin_map_sdhc_card_dat_3to0, COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data0));
+            COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data0));
     }
-    
+
     if (CY_RSLT_SUCCESS == result)
     {
-        result = setup_pin(
+        result = setup_pin(data1, cyhal_pin_map_sdhc_card_dat_3to0,
-            data1, cyhal_pin_map_sdhc_card_dat_3to0, COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data1));
+            COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data1));
     }
-    
+
     if (CY_RSLT_SUCCESS == result)
     {
-        result = setup_pin(
+        result = setup_pin(data2, cyhal_pin_map_sdhc_card_dat_3to0,
-            data2, cyhal_pin_map_sdhc_card_dat_3to0, COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data2));
+            COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data2));
     }
-    
+
     if (CY_RSLT_SUCCESS == result)
     {
-        result = setup_pin(
+        result = setup_pin(data3, cyhal_pin_map_sdhc_card_dat_3to0,
-            data3, cyhal_pin_map_sdhc_card_dat_3to0, COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data3));
+            COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data3));
     }
 
     if (result == CY_RSLT_SUCCESS)
@@ -1228,7 +1225,7 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk,
         if (result == CY_RSLT_SUCCESS)
         {
             obj->resource = sdhc;
-            
+
             if (result == CY_RSLT_SUCCESS)
             {
                 obj->base = CYHAL_SDHC_BASE_ADDRESSES[obj->resource.block_num];
@@ -1265,9 +1262,6 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk,
 
                 if (result == CY_RSLT_SUCCESS)
                 {
-                    /* Only enable the SDMA interrupt */
-                    Cy_SD_Host_SetNormalInterruptMask(obj->base, CY_SD_HOST_DMA_INTERRUPT);
-
                     /* Don't enable any error interrupts for now */
                     Cy_SD_Host_SetErrorInterruptMask(obj->base, 0UL);
 
@@ -1290,7 +1284,7 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk,
                     (void)Cy_SD_Host_SetHostBusWidth(obj->base, CY_SD_HOST_BUS_WIDTH_4_BIT);
 
                     /* Change the host SD clock to 400 kHz */
-                    (void) Cy_SD_Host_SdCardChangeClock(obj->base, obj->resource.block_num, SDIO_HOST_CLK_400K);
+                    (void) cyhal_sd_host_sdcardchangeclock(obj->base, obj->resource.block_num, SDIO_HOST_CLK_400K);
 
                     obj->frequencyhal_hz = SDIO_HOST_CLK_400K;
                     obj->block_size = SDIO_64B_BLOCK;
@@ -1327,27 +1321,26 @@ void cyhal_sdio_free(cyhal_sdio_t *obj)
     }
 
     /* Free pins */
-    release_pin_if_used(&obj->pin_clk);
+    cyhal_utils_release_if_used(&obj->pin_clk);
-    release_pin_if_used(&obj->pin_cmd);
+    cyhal_utils_release_if_used(&obj->pin_cmd);
-    release_pin_if_used(&obj->pin_data0);
+    cyhal_utils_release_if_used(&obj->pin_data0);
-    release_pin_if_used(&obj->pin_data1);
+    cyhal_utils_release_if_used(&obj->pin_data1);
-    release_pin_if_used(&obj->pin_data2);
+    cyhal_utils_release_if_used(&obj->pin_data2);
-    release_pin_if_used(&obj->pin_data3);
+    cyhal_utils_release_if_used(&obj->pin_data3);
 }
 
-
 cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config)
 {
     cy_en_sd_host_status_t result = CY_SD_HOST_ERROR_TIMEOUT;
 
-    if ((NULL == obj) && (config == NULL))
+    if ((NULL == obj) || (config == NULL))
     {
         return CYHAL_SDIO_RSLT_ERR_BAD_PARAM;
     }
 
     if (config->frequencyhal_hz != 0U)
     {
-        result = Cy_SD_Host_SdCardChangeClock(obj->base, obj->resource.block_num, config->frequencyhal_hz);
+        result = cyhal_sd_host_sdcardchangeclock(obj->base, obj->resource.block_num, config->frequencyhal_hz);
         obj->frequencyhal_hz = config->frequencyhal_hz;
     }
 
@@ -1371,6 +1364,7 @@ cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config
 cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t direction, \
                               cyhal_sdio_command_t command, uint32_t argument, uint32_t* response)
 {
+    (void)direction;
     if (NULL == obj)
     {
         return CYHAL_SDIO_RSLT_ERR_BAD_PARAM;
@@ -1423,7 +1417,7 @@ cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t directio
 
         if (CY_SD_HOST_SUCCESS == result)
         {
-            result = Cy_SD_Host_PollCmdComplete(obj->base);
+            result = cyhal_sd_host_pollcmdcomplete(obj->base);
         }
     }
 
@@ -1480,7 +1474,7 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction
         *response = 0UL;
     }
 
-    while ((CY_SD_HOST_SUCCESS != result) && (retry-- > 0UL))
+    while ((CY_SD_HOST_SUCCESS != result) && (retry > 0UL))
     {
         /* Add SDIO Error Handling
          * SDIO write timeout is expected when doing first write to register
@@ -1544,13 +1538,14 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction
         result = Cy_SD_Host_SendCommand(obj->base, &cmd);
         if ( CY_SD_HOST_SUCCESS == result )
         {
-            result = Cy_SD_Host_PollCmdComplete(obj->base);
+            result = cyhal_sd_host_pollcmdcomplete(obj->base);
 
             if ( CY_SD_HOST_SUCCESS == result )
             {
-                result = Cy_SD_Host_PollTransferComplete(obj->base, SDIO_RW_TIMEOUT_US);
+                result = cyhal_sd_host_polltransfercomplete(obj->base, SDIO_RW_TIMEOUT_US);
             }
         }
+        retry--;
     }
 
     if (response != NULL )
@@ -1621,7 +1616,7 @@ cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t directio
     dat.enReliableWrite     = false;
     dat.enableDma           = true;
 
-    while ((CY_SD_HOST_SUCCESS != result) && (retry-- > 0UL))
+    while ((CY_SD_HOST_SUCCESS != result) && (retry > 0UL))
     {
         /* Check if an error occurred on any previous transactions or reset after the first unsuccessful bulk transfer try */
         if( (Cy_SD_Host_GetNormalInterruptStatus(obj->base) & CY_SD_HOST_ERR_INTERRUPT) ||
@@ -1671,6 +1666,7 @@ cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t directio
         (void)Cy_SD_Host_InitDataTransfer(obj->base, &dat);
 
         result = Cy_SD_Host_SendCommand(obj->base, &cmd);
+        retry--;
     }
 
     if (CY_SD_HOST_SUCCESS != result)
@@ -1702,7 +1698,7 @@ bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj)
 
         if (!isCmdComplete)
         {
-            result = Cy_SD_Host_PollCmdComplete(obj->base);
+            result = cyhal_sd_host_pollcmdcomplete(obj->base);
 
             if (CY_SD_HOST_SUCCESS == result)
             {
@@ -1712,7 +1708,7 @@ bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj)
 
         if (isCmdComplete)
         {
-            result = Cy_SD_Host_PollTransferComplete(obj->base, SDIO_RW_TIMEOUT_US);
+            result = cyhal_sd_host_polltransfercomplete(obj->base, SDIO_RW_TIMEOUT_US);
 
             if (CY_SD_HOST_SUCCESS == result)
             {
@@ -1785,6 +1781,7 @@ void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_irq_event_t event, ui
             obj->irq_cause  &= ~event;
         }
 
+        Cy_SD_Host_ClearNormalInterruptStatus(obj->base, interruptMask);
         Cy_SD_Host_SetNormalInterruptMask(obj->base, interruptMask);
     }
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_spi.c

@@ -7,7 +7,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -203,6 +203,7 @@ cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso,
                         uint8_t bits, cyhal_spi_mode_t mode, bool is_slave)
 {
     CY_ASSERT(NULL != obj);
+    memset(obj, 0, sizeof(cyhal_spi_t));
 
     cy_rslt_t result = CY_RSLT_SUCCESS;
     cyhal_resource_inst_t pin_rsc;
@@ -436,33 +437,12 @@ void cyhal_spi_free(cyhal_spi_t *obj)
         cyhal_hwmgr_free(&(obj->resource));
         obj->resource.type = CYHAL_RSC_INVALID;
     }
-    if (CYHAL_NC_PIN_VALUE != obj->pin_miso)
+
-    {
+    cyhal_utils_release_if_used(&(obj->pin_miso));
-        cyhal_utils_disconnect_and_free(obj->pin_miso);
+    cyhal_utils_release_if_used(&(obj->pin_mosi));
-        obj->pin_miso = CYHAL_NC_PIN_VALUE;
+    cyhal_utils_release_if_used(&(obj->pin_sclk));
-    }
+    cyhal_utils_release_if_used(&(obj->pin_ssel));
-    if (CYHAL_NC_PIN_VALUE != obj->pin_mosi)
+
-    {
-        cyhal_utils_disconnect_and_free(obj->pin_mosi);
-        obj->pin_mosi = CYHAL_NC_PIN_VALUE;
-    }
-    if (CYHAL_NC_PIN_VALUE != obj->pin_sclk)
-    {
-        cyhal_utils_disconnect_and_free(obj->pin_sclk);
-        obj->pin_sclk = CYHAL_NC_PIN_VALUE;
-    }
-    if (CYHAL_NC_PIN_VALUE != obj->pin_ssel)
-    {
-        if (obj->is_slave)
-        {
-            cyhal_utils_disconnect_and_free(obj->pin_ssel);
-            obj->pin_ssel = CYHAL_NC_PIN_VALUE;
-        }
-        else
-        {
-            cyhal_gpio_free(obj->pin_ssel);
-        }
-    }
     if (obj->alloc_clock)
     {
        cyhal_hwmgr_free_clock(&(obj->clock));

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_system.c

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -27,6 +27,9 @@
 
 #include "cyhal_system.h"
 #include "cyhal_hwmgr.h"
+#ifdef CY_RTOS_AWARE
+#include "cyabs_rtos.h"
+#endif
 
 #ifdef CY_IP_MXS40SRSS
 
@@ -51,6 +54,16 @@ cy_rslt_t cyhal_system_unregister_callback(cyhal_system_callback_t const *handle
         : CYHAL_SYSTEM_RSLT_ERROR;
 }
 
+cy_rslt_t cyhal_system_delay_ms(uint32_t milliseconds)
+{
+#ifdef CY_RTOS_AWARE
+    return cy_rtos_delay_milliseconds(milliseconds);
+#else
+    Cy_SysLib_Delay(milliseconds);
+    return CY_RSLT_SUCCESS;
+#endif
+}
+
 uint32_t get_src_freq(cy_en_clkpath_in_sources_t source)
 {
     /* get the frequency of the source, i.e., the path mux input */
@@ -67,7 +80,7 @@ uint32_t get_src_freq(cy_en_clkpath_in_sources_t source)
     }
 }
 
-uint32_t get_clkpath_freq(cy_en_clkhf_in_sources_t path, uint32_t freq, uint8_t *fll_pll_used)
+static uint32_t get_clkpath_freq(cy_en_clkhf_in_sources_t path, uint32_t freq, uint8_t *fll_pll_used)
 {
     *fll_pll_used = 0xff;
     if (path == CY_SYSCLK_CLKHF_IN_CLKPATH0)
@@ -97,7 +110,7 @@ uint32_t get_clkpath_freq(cy_en_clkhf_in_sources_t path, uint32_t freq, uint8_t
     return freq;
 }
 
-cy_rslt_t try_set_hf_divider(uint8_t clock, uint32_t input_freq, uint32_t target_freq)
+static cy_rslt_t try_set_hf_divider(uint8_t clock, uint32_t input_freq, uint32_t target_freq)
 {
     bool divider_found = false;
     cy_en_clkhf_dividers_t divider;
@@ -134,7 +147,7 @@ cy_rslt_t try_set_hf_divider(uint8_t clock, uint32_t input_freq, uint32_t target
     }
 }
 
-cy_rslt_t try_set_fll(uint8_t clock, uint32_t target_freq)
+static cy_rslt_t try_set_fll(uint8_t clock, uint32_t target_freq)
 {
     Cy_SysClk_FllDisable();
     Cy_SysClk_ClkHfSetSource(clock, CY_SYSCLK_CLKHF_IN_CLKPATH0);
@@ -153,7 +166,7 @@ cy_rslt_t try_set_fll(uint8_t clock, uint32_t target_freq)
     return rslt;
 }
 
-cy_rslt_t try_set_pll(uint8_t clock, uint8_t pll, uint32_t target_freq)
+static cy_rslt_t try_set_pll(uint8_t clock, uint8_t pll, uint32_t target_freq)
 {
     Cy_SysClk_PllDisable(pll);
     Cy_SysClk_ClkHfSetSource(clock, (cy_en_clkhf_in_sources_t)(pll));
@@ -180,7 +193,7 @@ cy_rslt_t try_set_pll(uint8_t clock, uint8_t pll, uint32_t target_freq)
 }
 
 /* This should be part of the PDL */
-static inline bool Cy_SysClk_ClkHfIsEnabled(uint32_t clkHf)
+static inline bool cyhal_sysclk_clkhfisenabled(uint32_t clkHf)
 {
     bool retVal = false;
     if (clkHf < CY_SRSS_NUM_HFROOT)
@@ -216,7 +229,7 @@ cy_rslt_t cyhal_system_clock_set_frequency(uint8_t clock, uint32_t frequency_hz)
         return rslt;
     }
 
-    bool enabled = Cy_SysClk_ClkHfIsEnabled(clock);
+    bool enabled = cyhal_sysclk_clkhfisenabled(clock);
     if (enabled && fll_pll_used == 0)
     {
         return try_set_fll(clock, frequency_hz);
@@ -292,6 +305,39 @@ cy_rslt_t cyhal_system_clock_set_divider(cyhal_system_clock_t clock, cyhal_syste
     return CY_RSLT_SUCCESS;
 }
 
+cyhal_reset_reason_t cyhal_system_get_reset_reason(void)
+{
+    uint32_t pdl_reason = Cy_SysLib_GetResetReason();
+    cyhal_reset_reason_t reason = CYHAL_SYSTEM_RESET_NONE;
+
+    if (CY_SYSLIB_RESET_ACT_FAULT & pdl_reason)
+        reason |= CYHAL_SYSTEM_RESET_ACTIVE_FAULT;
+    if (CY_SYSLIB_RESET_DPSLP_FAULT & pdl_reason)
+        reason |= CYHAL_SYSTEM_RESET_DEEPSLEEP_FAULT;
+    if (CY_SYSLIB_RESET_SOFT & pdl_reason)
+        reason |= CYHAL_SYSTEM_RESET_SOFT;
+    if (CY_SYSLIB_RESET_HIB_WAKEUP & pdl_reason)
+        reason |= CYHAL_SYSTEM_RESET_HIB_WAKEUP;
+    if ((CY_SYSLIB_RESET_HWWDT | CY_SYSLIB_RESET_SWWDT0 | CY_SYSLIB_RESET_SWWDT1 |
+        CY_SYSLIB_RESET_SWWDT2 | CY_SYSLIB_RESET_SWWDT3) & pdl_reason)
+        reason |= CYHAL_SYSTEM_RESET_WDT;
+#if (SRSS_WCOCSV_PRESENT != 0U)
+    if (CY_SYSLIB_RESET_CSV_WCO_LOSS & pdl_reason)
+        reason |= CYHAL_SYSTEM_RESET_WCO_ERR;
+#endif
+#if (SRSS_MASK_HFCSV != 0)
+    if ((CY_SYSLIB_RESET_HFCLK_LOSS | CY_SYSLIB_RESET_HFCLK_ERR) & pdl_reason)
+        reason |= CYHAL_SYSTEM_RESET_SYS_CLK_ERR;
+#endif
+
+    return reason;
+}
+
+void cyhal_system_clear_reset_reason(void)
+{
+    Cy_SysLib_ClearResetReason();
+}
+
 #if defined(__cplusplus)
 }
 #endif

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_tcpwm_common.c

@@ -6,7 +6,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -79,24 +79,27 @@ void cyhal_tcpwm_irq_handler()
             channel = irqn - CYHAL_TCPWM_DATA[block].isr_offset;
             break;
         }
-        else
-        {
-            CY_ASSERT(block != CY_IP_MXTCPWM_INSTANCES - 1); // IRQn should always be in one of those ranges
-        }
     }
 
-    TCPWM_Type *blockAddr = CYHAL_TCPWM_DATA[block].base;
+    if (block < CY_IP_MXTCPWM_INSTANCES)
-    uint32_t index = GET_ARRAY_INDEX(block, channel);
-
-    cyhal_event_callback_data_t *callback_data = cyhal_tcpwm_callback_data_structs[index];
-    if (callback_data->callback != NULL)
     {
-        cyhal_tcpwm_event_callback_t callback = (cyhal_tcpwm_event_callback_t) callback_data->callback;
+        TCPWM_Type *blockAddr = CYHAL_TCPWM_DATA[block].base;
-        /* Call registered callbacks here */
+        uint32_t index = GET_ARRAY_INDEX(block, channel);
-        (void) (callback) (callback_data->callback_arg, Cy_TCPWM_GetInterruptStatus(blockAddr, channel));
-    }
 
-    Cy_TCPWM_ClearInterrupt(blockAddr, channel, CY_TCPWM_INT_ON_CC_OR_TC);
+        cyhal_event_callback_data_t *callback_data = cyhal_tcpwm_callback_data_structs[index];
+        if (callback_data->callback != NULL)
+        {
+            cyhal_tcpwm_event_callback_t callback = (cyhal_tcpwm_event_callback_t) callback_data->callback;
+            /* Call registered callbacks here */
+            (void) (callback) (callback_data->callback_arg, Cy_TCPWM_GetInterruptStatus(blockAddr, channel));
+        }
+
+        Cy_TCPWM_ClearInterrupt(blockAddr, channel, CY_TCPWM_INT_ON_CC_OR_TC);
+    }
+    else
+    {
+        CY_HALT(); // Could not determine the block/channel for IRQn
+    }
 }
 
 /*******************************************************************************

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_timer.c

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -59,7 +59,7 @@ static const cy_stc_tcpwm_counter_config_t default_config =
 };
 
 /** Convert timer direction from the HAL enum to the corresponding PDL constant
-  * 
+  *
   * @param[in] direction The direction, as a HAL enum value
   * @return The direction, as a PDL constant
   */
@@ -85,7 +85,7 @@ cy_rslt_t cyhal_timer_init(cyhal_timer_t *obj, cyhal_gpio_t pin, const cyhal_clo
 {
     CY_ASSERT(NULL != obj);
 
-    //TODO: Handle Trigger mux pin assignments
+    // No support currently for pin connections on this device
     if (CYHAL_NC_PIN_VALUE != pin)
         return CYHAL_TIMER_RSLT_ERR_BAD_ARGUMENT;
 
@@ -148,7 +148,7 @@ void cyhal_timer_free(cyhal_timer_t *obj)
     IRQn_Type irqn = (IRQn_Type)(CYHAL_TCPWM_DATA[obj->resource.block_num].isr_offset + obj->resource.channel_num);
     NVIC_DisableIRQ(irqn);
 
-    if (NULL != obj && NULL != obj->base)
+    if (NULL != obj->base)
     {
         Cy_TCPWM_Counter_Disable(obj->base, obj->resource.channel_num);
 
@@ -159,6 +159,7 @@ void cyhal_timer_free(cyhal_timer_t *obj)
         if (obj->dedicated_clock)
         {
             cy_en_sysclk_status_t rslt = Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num);
+            CY_UNUSED_PARAMETER(rslt); /* CY_ASSERT only processes in DEBUG, ignores for others */
             CY_ASSERT(CY_SYSCLK_SUCCESS == rslt);
             cyhal_hwmgr_free_clock(&(obj->clock));
             obj->dedicated_clock = false;
@@ -217,6 +218,7 @@ cy_rslt_t cyhal_timer_set_frequency(cyhal_timer_t *obj, uint32_t hz)
     {
         uint32_t div = Cy_SysClk_ClkPeriGetFrequency() / hz;
         if (0 == div ||
+            CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num) ||
             CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) ||
             CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num))
         {
@@ -245,6 +247,12 @@ cy_rslt_t cyhal_timer_stop(cyhal_timer_t *obj)
     return CY_RSLT_SUCCESS;
 }
 
+uint32_t cyhal_timer_read(const cyhal_timer_t *obj)
+{
+    CY_ASSERT(NULL != obj);
+    return Cy_TCPWM_Counter_GetCounter(obj->base, obj->resource.channel_num);
+}
+
 #if defined(__cplusplus)
 }
 #endif

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_trng.c

@@ -7,7 +7,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_uart.c

@@ -7,7 +7,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -322,22 +322,12 @@ void cyhal_uart_free(cyhal_uart_t *obj)
         cyhal_hwmgr_free(&(obj->resource));
         Cy_SysPm_UnregisterCallback(&(obj->pm_callback));
     }
-    if (CYHAL_NC_PIN_VALUE != obj->pin_rx)
+
-    {
+    cyhal_utils_release_if_used(&(obj->pin_rx));
-        cyhal_utils_disconnect_and_free(obj->pin_rx);
+    cyhal_utils_release_if_used(&(obj->pin_tx));
-    }
+    cyhal_utils_release_if_used(&(obj->pin_rts));
-    if (CYHAL_NC_PIN_VALUE != obj->pin_tx)
+    cyhal_utils_release_if_used(&(obj->pin_cts));
-    {
+
-        cyhal_utils_disconnect_and_free(obj->pin_tx);
-    }
-    if (CYHAL_NC_PIN_VALUE != obj->pin_rts)
-    {
-        cyhal_utils_disconnect_and_free(obj->pin_rts);
-    }
-    if (CYHAL_NC_PIN_VALUE != obj->pin_cts)
-    {
-        cyhal_utils_disconnect_and_free(obj->pin_cts);
-    }
     if (!(obj->is_user_clock))
     {
         cyhal_hwmgr_free_clock(&(obj->clock));
@@ -634,7 +624,7 @@ cy_rslt_t cyhal_uart_read_async(cyhal_uart_t *obj, void *rx, size_t length)
 
 bool cyhal_uart_is_tx_active(cyhal_uart_t *obj)
 {
-    return (0UL != (obj->context.txStatus & CY_SCB_UART_TRANSMIT_ACTIVE)) || !Cy_SCB_IsTxComplete(obj->base);
+    return (0UL != (obj->context.txStatus & CY_SCB_UART_TRANSMIT_ACTIVE));
 }
 
 bool cyhal_uart_is_rx_active(cyhal_uart_t *obj)
@@ -708,10 +698,12 @@ void cyhal_uart_enable_event(cyhal_uart_t *obj, cyhal_uart_event_t event, uint8_
         obj->irq_cause |= event;
         if (event & CYHAL_UART_IRQ_RX_NOT_EMPTY)
         {
+            Cy_SCB_ClearRxInterrupt(obj->base, CY_SCB_RX_INTR_NOT_EMPTY);
             Cy_SCB_SetRxInterruptMask(obj->base, Cy_SCB_GetRxInterruptMask(obj->base) | CY_SCB_RX_INTR_NOT_EMPTY);
         }
         if (event & CYHAL_UART_IRQ_TX_EMPTY)
         {
+            Cy_SCB_ClearTxInterrupt(obj->base, CY_SCB_UART_TX_EMPTY);
             Cy_SCB_SetTxInterruptMask(obj->base, Cy_SCB_GetTxInterruptMask(obj->base) | CY_SCB_UART_TX_EMPTY);
         }
     }
@@ -720,12 +712,10 @@ void cyhal_uart_enable_event(cyhal_uart_t *obj, cyhal_uart_event_t event, uint8_
         obj->irq_cause &= ~event;
         if (event & CYHAL_UART_IRQ_RX_NOT_EMPTY)
         {
-            Cy_SCB_ClearRxInterrupt(obj->base, CY_SCB_RX_INTR_NOT_EMPTY);
             Cy_SCB_SetRxInterruptMask(obj->base, Cy_SCB_GetRxInterruptMask(obj->base) & ~CY_SCB_RX_INTR_NOT_EMPTY);
         }
         if (event & CYHAL_UART_IRQ_TX_EMPTY)
         {
-            Cy_SCB_ClearTxInterrupt(obj->base, CY_SCB_UART_TX_EMPTY);
             Cy_SCB_SetTxInterruptMask(obj->base, Cy_SCB_GetTxInterruptMask(obj->base) & ~CY_SCB_UART_TX_EMPTY);
         }
     }

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_udb_sdio.c

@@ -7,7 +7,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -24,6 +24,7 @@
 *******************************************************************************/
 
 #include "cyhal_hwmgr.h"
+#include "cy_utils.h"
 
 #if defined(CYHAL_UDB_SDIO)
 
@@ -39,9 +40,6 @@ extern "C"
 #include "cyhal_gpio.h"
 #include "cyhal_interconnect.h"
 
-/* Not connected pin define */
-#define SDIO_PINS_NC    ((cyhal_gpio_t) CYHAL_NC_PIN_VALUE)
-
 #define CY_HAL_SDIO_CLK_DIV_VALUE   ((uint8_t) 0xFF)
 
 /* Not configured clock divider define*/
@@ -128,7 +126,6 @@ static const cy_stc_gpio_pin_config_t pin_clk_config =
 /*******************************************************************************
 *       Internal functions
 *******************************************************************************/
-static void cyhal_free_pins(cyhal_sdio_t *obj);
 static cy_en_syspm_status_t cyhal_sdio_ds_callback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
 
 /******************************************************************************
@@ -235,22 +232,6 @@ static void cyhal_sdio_interrupts_dispatcher_IRQHandler(void)
     }
 }
 
-static void cyhal_free_pins(cyhal_sdio_t *obj)
-{
-    cyhal_gpio_free(obj->pin_clk);
-    obj->pin_clk = SDIO_PINS_NC;
-    cyhal_gpio_free(obj->pin_cmd);
-    obj->pin_cmd = SDIO_PINS_NC;
-    cyhal_gpio_free(obj->pin_data0);
-    obj->pin_data0 = SDIO_PINS_NC;
-    cyhal_gpio_free(obj->pin_data1);
-    obj->pin_data1 = SDIO_PINS_NC;
-    cyhal_gpio_free(obj->pin_data2);
-    obj->pin_data2 = SDIO_PINS_NC;
-    cyhal_gpio_free(obj->pin_data3);
-    obj->pin_data3 = SDIO_PINS_NC;
-}
-
 static void cyhal_free_clocks(cyhal_sdio_t *obj)
 {
     cyhal_resource_inst_t udbClkRsc;
@@ -260,10 +241,10 @@ static void cyhal_free_clocks(cyhal_sdio_t *obj)
     cyhal_hwmgr_free(&udbClkRsc);
 }
 
-static void cyhal_free_dmas(cyhal_sdio_t *obj)
+static void cyhal_free_dmas()
 {
     cyhal_resource_inst_t dmaRsc;
-    dmaRsc.type = CYHAL_RSC_DMA;
+    dmaRsc.type = CYHAL_RSC_DW;
 
     dmaRsc.block_num = 0;
     dmaRsc.channel_num = 0;
@@ -295,12 +276,12 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk,
     *  SDIO.
     */
     obj->resource.type = CYHAL_RSC_INVALID;
-    obj->pin_cmd = SDIO_PINS_NC;
+    obj->pin_cmd = CYHAL_NC_PIN_VALUE;
-    obj->pin_clk = SDIO_PINS_NC;
+    obj->pin_clk = CYHAL_NC_PIN_VALUE;
-    obj->pin_data0 = SDIO_PINS_NC;
+    obj->pin_data0 = CYHAL_NC_PIN_VALUE;
-    obj->pin_data1 = SDIO_PINS_NC;
+    obj->pin_data1 = CYHAL_NC_PIN_VALUE;
-    obj->pin_data2 = SDIO_PINS_NC;
+    obj->pin_data2 = CYHAL_NC_PIN_VALUE;
-    obj->pin_data3 = SDIO_PINS_NC;
+    obj->pin_data3 = CYHAL_NC_PIN_VALUE;
     obj->dma0Ch0.resource.type = CYHAL_RSC_INVALID;
     obj->dma0Ch1.resource.type = CYHAL_RSC_INVALID;
     obj->dma1Ch1.resource.type = CYHAL_RSC_INVALID;
@@ -336,28 +317,28 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk,
     if (retVal == CY_RSLT_SUCCESS)
     {
         /* Reserve DMA0 CH0 */
-        cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DMA, 0, 0 };
+        cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DW, 0, 0 };
         retVal = cyhal_hwmgr_reserve(&dmaRsc);
     }
 
     if (retVal == CY_RSLT_SUCCESS)
     {
         /* Reserve DMA0 CH1 */
-        cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DMA, 0, 1 };
+        cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DW, 0, 1 };
         retVal = cyhal_hwmgr_reserve(&dmaRsc);
     }
 
     if (retVal == CY_RSLT_SUCCESS)
     {
         /* Reserve DMA1 CH1 */
-        cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DMA, 1, 1 };
+        cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DW, 1, 1 };
         retVal = cyhal_hwmgr_reserve(&dmaRsc);
     }
 
     if (retVal == CY_RSLT_SUCCESS)
     {
         /* Reserve DMA1 CH3 */
-        cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DMA, 1, 3 };
+        cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DW, 1, 3 };
         retVal = cyhal_hwmgr_reserve(&dmaRsc);
     }
 
@@ -502,9 +483,15 @@ void cyhal_sdio_free(cyhal_sdio_t *obj)
     NVIC_DisableIRQ(cpuss_interrupts_dw1_1_IRQn);
     NVIC_DisableIRQ(cpuss_interrupts_dw1_3_IRQn);
 
-    cyhal_free_pins(obj);
+    cyhal_utils_release_if_used(&(obj->pin_clk));
+    cyhal_utils_release_if_used(&(obj->pin_cmd));
+    cyhal_utils_release_if_used(&(obj->pin_data0));
+    cyhal_utils_release_if_used(&(obj->pin_data1));
+    cyhal_utils_release_if_used(&(obj->pin_data2));
+    cyhal_utils_release_if_used(&(obj->pin_data3));
+
     cyhal_free_clocks(obj);
-    cyhal_free_dmas(obj);
+    cyhal_free_dmas();
     cyhal_hwmgr_free(&(obj->resource));
     SDIO_Free();
 
@@ -675,12 +662,14 @@ cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t directio
 bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj)
 {
     /* UDB SDIO does not support async transfers */
+    CY_UNUSED_PARAMETER(obj);
     return false;
 }
 
 cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj)
 {
     /* Reset UDB SDIO */
+    CY_UNUSED_PARAMETER(obj);
     SDIO_Reset();
     return CY_RSLT_SUCCESS;
 }

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_usb_dev.c

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2019 Cypress Semiconductor Corporation
+* Copyright 2019-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -470,15 +470,8 @@ static void cyhal_usb_dev_free_resources(cyhal_usb_dev_t *obj)
         cyhal_hwmgr_free_clock(&(obj->clock));
     }
 
-    if (CYHAL_NC_PIN_VALUE != obj->pin_dp)
+    cyhal_utils_release_if_used(&(obj->pin_dp));
-    {
+    cyhal_utils_release_if_used(&(obj->pin_dm));
-        cyhal_utils_disconnect_and_free(obj->pin_dp);
-    }
-
-    if (CYHAL_NC_PIN_VALUE != obj->pin_dm)
-    {
-        cyhal_utils_disconnect_and_free(obj->pin_dm);
-    }
 }
 
 cy_rslt_t cyhal_usb_dev_init(cyhal_usb_dev_t *obj, cyhal_gpio_t dp, cyhal_gpio_t dm, const cyhal_clock_divider_t *clk)

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_utils.c

@@ -6,7 +6,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -22,10 +22,10 @@
 * limitations under the License.
 *******************************************************************************/
 
-#include "cy_result.h"
 #include "cyhal_utils.h"
 #include "cyhal_hwmgr.h"
 #include "cyhal_interconnect.h"
+#include "cyhal_gpio.h"
 
 #if defined(__cplusplus)
 extern "C"
@@ -44,14 +44,46 @@ const cyhal_resource_pin_mapping_t *cyhal_utils_get_resource(cyhal_gpio_t pin, c
     return NULL;
 }
 
+cy_rslt_t cyhal_utils_reserve_and_connect(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *mapping)
+{
+    cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(pin);
+    cy_rslt_t status = cyhal_hwmgr_reserve(&pinRsc);
+    if (CY_RSLT_SUCCESS == status)
+    {
+        status = cyhal_connect_pin(mapping);
+        if (CY_RSLT_SUCCESS != status)
+        {
+            cyhal_hwmgr_free(&pinRsc);
+        }
+    }
+    return status;
+}
+
 void cyhal_utils_disconnect_and_free(cyhal_gpio_t pin)
 {
     cy_rslt_t rslt = cyhal_disconnect_pin(pin);
+    CY_UNUSED_PARAMETER(rslt); /* CY_ASSERT only processes in DEBUG, ignores for others */
     CY_ASSERT(CY_RSLT_SUCCESS == rslt);
     cyhal_resource_inst_t rsc = cyhal_utils_get_gpio_resource(pin);
     cyhal_hwmgr_free(&rsc);
 }
 
+void cyhal_utils_release_if_used(cyhal_gpio_t *pin)
+{
+    if (CYHAL_NC_PIN_VALUE != *pin)
+    {
+        cyhal_utils_disconnect_and_free(*pin);
+        *pin = CYHAL_NC_PIN_VALUE;
+    }
+}
+
+bool cyhal_utils_resources_equal(const cyhal_resource_inst_t *resource1, const cyhal_resource_inst_t *resource2)
+{
+    return (resource1->type == resource2->type) &&
+        (resource1->block_num == resource2->block_num) &&
+        (resource1->channel_num == resource2->channel_num);
+}
+
 #if defined(__cplusplus)
 }
 #endif

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_wdt.c

@@ -10,7 +10,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2019 Cypress Semiconductor Corporation
+* Copyright 2019-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -27,8 +27,8 @@
 *******************************************************************************/
 
 /**
-* \addtogroup group_hal_psoc6_wdt (WDT) Watchdog Timer
+* \addtogroup group_hal_psoc6_wdt WDT (Watchdog Timer)
-* \ingroup group_hal_psoc6 
+* \ingroup group_hal_psoc6
 * \{
 * The PSoC 6 WDT is only capable of supporting certain timeout ranges below its maximum timeout of 6000ms.
 * As a result, any unsupported timeouts given to the HAL WDT are rounded up to the nearest supported value.
@@ -87,6 +87,7 @@
 #include "cyhal_wdt.h"
 #include "cy_wdt.h"
 #include "cy_lvd.h"
+#include "cy_utils.h"
 
 #if defined(__cplusplus)
 extern "C" {
@@ -187,6 +188,7 @@ cy_rslt_t cyhal_wdt_init(cyhal_wdt_t *obj, uint32_t timeout_ms)
 
 void cyhal_wdt_free(cyhal_wdt_t *obj)
 {
+    CY_UNUSED_PARAMETER(obj);
     cyhal_wdt_stop(obj);
 
     cyhal_wdt_initialized = false;
@@ -194,11 +196,13 @@ void cyhal_wdt_free(cyhal_wdt_t *obj)
 
 void cyhal_wdt_kick(cyhal_wdt_t *obj)
 {
+    CY_UNUSED_PARAMETER(obj);
     Cy_WDT_ClearWatchdog();
 }
 
 void cyhal_wdt_start(cyhal_wdt_t *obj)
 {
+    CY_UNUSED_PARAMETER(obj);
     Cy_WDT_Unlock();
     Cy_WDT_Enable();
     Cy_WDT_Lock();
@@ -206,12 +210,14 @@ void cyhal_wdt_start(cyhal_wdt_t *obj)
 
 void cyhal_wdt_stop(cyhal_wdt_t *obj)
 {
+    CY_UNUSED_PARAMETER(obj);
     Cy_WDT_Unlock();
     Cy_WDT_Disable();
 }
 
 uint32_t cyhal_wdt_get_timeout_ms(cyhal_wdt_t *obj)
 {
+    CY_UNUSED_PARAMETER(obj);
     return cyhal_wdt_initial_timeout_ms;
 }
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_116_bga_ble.c

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_116_bga_usb.c

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_124_bga.c

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_124_bga_sip.c

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_43_smt.c

@@ -9,7 +9,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");