mirror of https://github.com/ARMmbed/mbed-os.git
Fixed system clock setup for XTAL and/or internal source on stm32f743 chips.
parent
33a538ab6c
commit
3f83163a63
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@ -72,7 +72,7 @@ void SetSysClock(void)
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#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
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#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
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/* 2- If fail try to start with HSE and external xtal */
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/* 2- If fail try to start with HSE and external xtal */
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if (SetSysClock_PLL_HSE(0) == 0)
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if (SetSysClock_PLL_HSE(0) == 0)
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#endif
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#endif
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{
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{
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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/* 3- If fail start with HSI clock */
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/* 3- If fail start with HSI clock */
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@ -109,11 +109,18 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
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} else {
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} else {
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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}
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}
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#if HSE_VALUE==8000000
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RCC_OscInitStruct.PLL.PLLM = 4; // 2 MHz
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RCC_OscInitStruct.PLL.PLLN = 480; // 960 MHz
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#elif HSE_VALUE==25000000
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RCC_OscInitStruct.PLL.PLLM = 5; // 5 MHz
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RCC_OscInitStruct.PLL.PLLN = 192; // 960 MHz
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#else
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error("Unsupported externall clock value, check hse_value define\n")
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#endif
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 4; // 2 MHz
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RCC_OscInitStruct.PLL.PLLN = 480; // 960 MHz
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RCC_OscInitStruct.PLL.PLLP = 2; // PLLCLK = SYSCLK = 480 MHz
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RCC_OscInitStruct.PLL.PLLP = 2; // PLLCLK = SYSCLK = 480 MHz
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RCC_OscInitStruct.PLL.PLLQ = 96; // PLL1Q used for FDCAN = 10 MHz
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RCC_OscInitStruct.PLL.PLLQ = 96; // PLL1Q used for FDCAN = 10 MHz
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RCC_OscInitStruct.PLL.PLLR = 2;
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RCC_OscInitStruct.PLL.PLLR = 2;
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@ -178,7 +185,7 @@ uint8_t SetSysClock_PLL_HSI(void)
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLM = 8;
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RCC_OscInitStruct.PLL.PLLM = 8;
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RCC_OscInitStruct.PLL.PLLN = 100;
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RCC_OscInitStruct.PLL.PLLN = 120;
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLQ = 2;
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RCC_OscInitStruct.PLL.PLLQ = 2;
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RCC_OscInitStruct.PLL.PLLR = 2;
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RCC_OscInitStruct.PLL.PLLR = 2;
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