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Fixed system clock setup for XTAL and/or internal source on stm32f743 chips.

pull/13640/head
Dmitriy Isaev 2020-09-20 16:26:25 +03:00
parent 33a538ab6c
commit 3f83163a63
1 changed files with 11 additions and 4 deletions
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15
targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/system_clock.c
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@ -72,7 +72,7 @@ void SetSysClock(void)
#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
/* 2- If fail try to start with HSE and external xtal */
if (SetSysClock_PLL_HSE(0) == 0)
#endif
#endif
{
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
/* 3- If fail start with HSI clock */
@ -109,11 +109,18 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
} else {
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
}
#if HSE_VALUE==8000000
RCC_OscInitStruct.PLL.PLLM = 4; // 2 MHz
RCC_OscInitStruct.PLL.PLLN = 480; // 960 MHz
#elif HSE_VALUE==25000000
RCC_OscInitStruct.PLL.PLLM = 5; // 5 MHz
RCC_OscInitStruct.PLL.PLLN = 192; // 960 MHz
#else
error("Unsupported externall clock value, check hse_value define\n")
#endif
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 4; // 2 MHz
RCC_OscInitStruct.PLL.PLLN = 480; // 960 MHz
RCC_OscInitStruct.PLL.PLLP = 2; // PLLCLK = SYSCLK = 480 MHz
RCC_OscInitStruct.PLL.PLLQ = 96; // PLL1Q used for FDCAN = 10 MHz
RCC_OscInitStruct.PLL.PLLR = 2;
@ -178,7 +185,7 @@ uint8_t SetSysClock_PLL_HSI(void)
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8;
RCC_OscInitStruct.PLL.PLLN = 100;
RCC_OscInitStruct.PLL.PLLN = 120;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 2;
RCC_OscInitStruct.PLL.PLLR = 2;