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Synchronize upstream changes - May 2023 edition (#160) 

* fix STM32L1 FLASH_SIZE for cat.3 devices with DEV_ID 0x436

* Fix mesh connect semaphore not releasing causing blockage

* Add support of NSAPI_ICMP sockets in Nanostack

* STM32F1: add MCU_STM32F103xD support

* STM32F1: add MCU_STM32F103xG support

* test: Disable failing tests due to echo server

Some tests are failing as echo.mbedcloudtesting.com is not serving TLS
requests anymore.

Signed-off-by: Saheer Babu <saheer.babu@arm.com>

* Check CAN DLC length value

* Fix default interface ID only being used partially

If user sets the default interface ID for a socket (e.g. using setsockopt
with SOCKET_INTERFACE_SELECT), the default interface should take over
other interface selection mechanisms as a interface is bound to the socket.
This applies for both IPv6 local and global scopes for unicast messages
but not for multicast messages as these are bound to a multicast interface
using SOCKET_IPV6_MULTICAST_IF socket option.

* Targets: NXP: IMXRT: Fixed GCC_ARM lds syntax.

Signed-off-by: Yilin Sun <imi415@imi.moe>

* CAN: read only up to 8 bytes

If HAL implementation writes more than 8 bytes of data, error immediately.
CANMessage defines only 8 bytes of data, lenght cannot be > 8.

This fixes https://github.com/ARMmbed/mbed-os/issues/15361

Signed-off-by: Martin Kojtal <martin.kojtal@arm.com>

* STM32F303xC: add RAM_CCM in GCC linker script

* fix(drivers/emac): Remove incorrect RMII RX ER initialization

* fix(drivers/emac): Add missing SPDX indetifier to ST driver files

* fixed compiler inline issue

* Update Mbed version block

* removed HSE speed limitation for STM32G431RB

* Added HSE range validation for STM32g431xB

* added support for 4, 8 and 16MHz

* M487: Remove unused variable 'u32EscapeFrame'

Remove unused variable 'u32EscapeFrame' in BSP m480_ccap.h to avoid warnings

* force FIFO IRQ for FDCan RX on H7

* Add hardware CRC support to STM32G4

* add support for Nucleo-H745ZI

* Update MAX32670 peripheral drivers with final ones that use by SDK

Signed-off-by: Sadik.Ozer <sadik.ozer@analog.com>

* MAX32670 apply mbed required changes on peripheral drivers

Signed-off-by: Sadik.Ozer <sadik.ozer@analog.com>

* M467: Support CAN bus

1.  Update BSP CANFD driver
2.  Notes for implementation
    (1) Each CANFD instance supports two IRQ lines. Use only line 0. Line 1 is not used.
    (2) For Rx disabling multiple filter handles,
        1)  Map all filter handles to filter handle 0
        2)  Use Rx FIFO 0 for filter handle 0
    (3) For Rx enabling multiple filter handles,
        1)  Use Rx FIFO 0 for filter handle 0
        2)  Use Rx FIFO 1 for filter handle through first invoking can_filter()
        3)  Use dedicated Rx Buffer for other filter handles
        NOTE: H/W supports mask on Rx FIFO 0/1 but not on dedicated Rx Buffer.
    (4) For Tx, use only dedicated Tx Buffer. BSP CANFD driver doesn't support Tx FIFO/Queue.
    (5) Support no CAN FD.

* Fix 'new[]' array freed with 'delete'

The array _scratch_buf is allocated using new[] in line 761 of
mbed-os/storage/kvstore/securestore/source/SecureStore.cpp.
But it was freed using delete.

* Define default parameters of functions of derived class the same as the base class

The member function bringup() of class ThreadInterface redefines
parameter stack's default value to IPV6_STACK from the inherited default value
DEFAULT_STACK (in Interface).
The default value will be resolved statically, not by dispatch, so this
can cause confusion.
Similar arguments apply to LoWPANNDInterface and WisunInterface.

* Avoid calling virtual functions from constructors and destructors

Virtual functions are resolved statically (not dynamically) in
constructors and destructors for the same class. The call should be made
explicitly static by qualifying it using the scope resolution operator.

* Fix potentially overrunning write of sprintf

Format string "%d" requires 12 bytes (including the null terminator).
Also, use snprintf instead of sprintf to prevent buffer overflow.

* Fix system_clock.c location

Signed-off-by: Jasper Jonker <jasper.jonker@wingtra.com>

* Fix variable name

Signed-off-by: Jasper <jasper.jonker@wingtra.com>

* Change storage-class of secret_buf to static

Storing the address of a local variable (`secret_buf`)
in non-local memory (`prf_ptr->secret`) can cause a
dangling pointer bug if the address is used after the function returns.

* fix compiling errors of FATFileSystem when exFAT was enabled

* Add OSPI support for STM32H7

* Nuvoton: Enable extending sampling time for ADC/EADC

For all Nuvoton targets, enable extending sampling time in ADC/EADC clocks on per-pin basis.

---------

Signed-off-by: Saheer Babu <saheer.babu@arm.com>
Signed-off-by: Yilin Sun <imi415@imi.moe>
Signed-off-by: Martin Kojtal <martin.kojtal@arm.com>
Signed-off-by: Sadik.Ozer <sadik.ozer@analog.com>
Signed-off-by: Jasper Jonker <jasper.jonker@wingtra.com>
Signed-off-by: Jasper <jasper.jonker@wingtra.com>
Co-authored-by: caodd <caodd1993@qq.com>
Co-authored-by: YannCharbon <yann.charbon@ik.me>
Co-authored-by: Jerome Coutant <jerome.coutant@st.com>
Co-authored-by: Saheer Babu <saheer.babu@arm.com>
Co-authored-by: Martyx00 <martin.petran@protonmail.com>
Co-authored-by: Yilin Sun <imi415@imi.moe>
Co-authored-by: Martin Kojtal <martin.kojtal@arm.com>
Co-authored-by: akiroz <akiroz.vectis@gmail.com>
Co-authored-by: Charles <hallard04@free.fr>
Co-authored-by: Leonard Chiang <leochiang2002@gmail.com>
Co-authored-by: Chun-Chieh Li <ccli8@nuvoton.com>
Co-authored-by: jmcloud <jmcloud@tesla.com>
Co-authored-by: Augusto Zanellato <augusto.zanellato@gmail.com>
Co-authored-by: Sadik.Ozer <sadik.ozer@analog.com>
Co-authored-by: Mingjie Shen <shen497@purdue.edu>
Co-authored-by: Jasper Jonker <jasper.jonker@wingtra.com>
Co-authored-by: wdx04 <wdx04@outlook.com>
pull/15437/head
Jamie Smith 2023-05-17 01:18:28 -07:00 committed by GitHub
parent 6e2e7b9414
commit 3f7d67c64c
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
196 changed files with 14224 additions and 9699 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp
View File

@ -186,8 +186,8 @@ retry_open:
}
}
if (strcmp(paramTag, "conId") == 0) {
char buf[10];
std::sprintf(buf, "%d", _cid);
char buf[12];
std::snprintf(buf, sizeof(buf), "%d", _cid);
if (strcmp(paramValue, buf) == 0) {
foundConIdType = true;
}

11
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/stm32f2_eth_init.c
View File

@ -1,6 +1,7 @@
/* mbed Microcontroller Library
* Copyright (c) 2022, STMicroelectronics
* All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* SPDX-License-Identifier: Apache-2.0
*
@ -53,7 +54,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13
@ -74,8 +75,8 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PG2, PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13;
/* Configure PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
/* Enable the Ethernet global Interrupt */
@ -103,7 +104,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13
@ -111,7 +112,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13);
/* Disable the Ethernet global Interrupt */
NVIC_DisableIRQ(ETH_IRQn);

6
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/stm32f4_eth_init.c
View File

@ -2,7 +2,7 @@
* Copyright (c) 2022, STMicroelectronics
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: BSD-3-Clause
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -50,7 +50,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER --------------------->
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PB11
RMII_MII_TXD0 ---------------------> PB12
RMII_MII_TXD1 ---------------------> PB13
@ -96,7 +96,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER --------------------->
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PB11
RMII_MII_TXD0 ---------------------> PB12
RMII_MII_TXD1 ---------------------> PB13

11
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_init.c
View File

@ -1,6 +1,7 @@
/* mbed Microcontroller Library
* Copyright (c) 2022, STMicroelectronics
* All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* SPDX-License-Identifier: Apache-2.0
*
@ -53,7 +54,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13
@ -74,8 +75,8 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PG2, PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13;
/* Configure PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
/* Enable the Ethernet global Interrupt */
@ -103,7 +104,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13
@ -111,7 +112,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13);
/* Disable the Ethernet global Interrupt */
NVIC_DisableIRQ(ETH_IRQn);

11
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/stm32f4_eth_init.c
View File

@ -1,6 +1,7 @@
/* mbed Microcontroller Library
* Copyright (c) 2022, STMicroelectronics
* All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* SPDX-License-Identifier: Apache-2.0
*
@ -53,7 +54,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13
@ -74,8 +75,8 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PG2, PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13;
/* Configure PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
/* Enable the Ethernet global Interrupt */
@ -103,7 +104,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13
@ -111,7 +112,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13);
/* Disable the Ethernet global Interrupt */
NVIC_DisableIRQ(ETH_IRQn);

11
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7_eth_init.c
View File

@ -1,6 +1,7 @@
/* mbed Microcontroller Library
* Copyright (c) 2022, STMicroelectronics
* All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* SPDX-License-Identifier: Apache-2.0
*
@ -57,7 +58,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PG14
@ -74,8 +75,8 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PG2, PG11, PG13 and PG14 */
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14;
/* Configure PG11, PG13 and PG14 */
GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14;
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
/* Enable the Ethernet global Interrupt */
@ -103,14 +104,14 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PG14
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14);
/* Disable the Ethernet global Interrupt */
NVIC_DisableIRQ(ETH_IRQn);

11
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7_eth_init.c
View File

@ -1,6 +1,7 @@
/* mbed Microcontroller Library
* Copyright (c) 2022, STMicroelectronics
* All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* SPDX-License-Identifier: Apache-2.0
*
@ -48,7 +49,6 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
/* Enable GPIOs clocks */
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
/** ETH GPIO Configuration
@ -58,7 +58,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PD5
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PG14
@ -75,10 +75,6 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PD5 */
GPIO_InitStructure.Pin = GPIO_PIN_5;
HAL_GPIO_Init(GPIOD, &GPIO_InitStructure);
/* Configure PG11, PG13 and PG14 */
GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14;
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
@ -108,14 +104,13 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PD5
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PG14
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14);
/* Disable the Ethernet global Interrupt */

11
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7_eth_init.c
View File

@ -1,6 +1,7 @@
/* mbed Microcontroller Library
* Copyright (c) 2022, STMicroelectronics
* All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* SPDX-License-Identifier: Apache-2.0
*
@ -58,7 +59,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13
@ -79,8 +80,8 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PG2, PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13;
/* Configure PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
/* Enable the Ethernet global Interrupt */
@ -108,7 +109,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13
@ -116,7 +117,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13);
/* Disable the Ethernet global Interrupt */
NVIC_DisableIRQ(ETH_IRQn);

11
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F756ZG/stm32f7_eth_init.c
View File

@ -1,6 +1,7 @@
/* mbed Microcontroller Library
* Copyright (c) 2022, STMicroelectronics
* All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* SPDX-License-Identifier: Apache-2.0
*
@ -58,7 +59,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13
@ -79,8 +80,8 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PG2, PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13;
/* Configure PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
/* Enable the Ethernet global Interrupt */
@ -108,7 +109,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13
@ -116,7 +117,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13);
/* Disable the Ethernet global Interrupt */
NVIC_DisableIRQ(ETH_IRQn);

11
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f7_eth_init.c
View File

@ -1,6 +1,7 @@
/* mbed Microcontroller Library
* Copyright (c) 2022, STMicroelectronics
* All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* SPDX-License-Identifier: Apache-2.0
*
@ -57,7 +58,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13
@ -78,8 +79,8 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PG2, PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13;
/* Configure PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
/* Enable the Ethernet global Interrupt */
@ -107,7 +108,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13
@ -115,7 +116,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13);
/* Disable the Ethernet global Interrupt */
NVIC_DisableIRQ(ETH_IRQn);

2
connectivity/nanostack/include/nanostack-interface/Nanostack.h
View File

@ -122,7 +122,7 @@ protected:
* NSAPI_ERROR_NO_SOCKET is returned if no socket is available.
*
* @param handle Destination for the handle to a newly created socket
* @param proto Protocol of socket to open, NSAPI_TCP or NSAPI_UDP
* @param proto Protocol of socket to open, NSAPI_TCP, NSAPI_UDP or NSAPI_ICMP
* @return 0 on success, negative error code on failure
*/
nsapi_error_t socket_open(void **handle, nsapi_protocol_t proto) override;

2
connectivity/nanostack/mbed-mesh-api/source/LoWPANNDInterface.cpp
View File

@ -28,7 +28,7 @@ class Nanostack::LoWPANNDInterface final : public Nanostack::MeshInterface {
public:
nsapi_error_t bringup(bool dhcp, const char *ip,
const char *netmask, const char *gw,
nsapi_ip_stack_t stack = IPV6_STACK,
nsapi_ip_stack_t stack = DEFAULT_STACK,
bool blocking = true) override;
nsapi_error_t bringdown() override;
nsapi_error_t get_gateway(SocketAddress *sockAddr) override;

1
connectivity/nanostack/mbed-mesh-api/source/MeshInterfaceNanostack.cpp
View File

@ -174,6 +174,7 @@ void Nanostack::Interface::network_handler(mesh_connection_status_t status)
connect_semaphore.release();
} else if (status == MESH_DISCONNECTED) {
disconnect_semaphore.release();
connect_semaphore.release();
}
}

2
connectivity/nanostack/mbed-mesh-api/source/ThreadInterface.cpp
View File

@ -27,7 +27,7 @@ class Nanostack::ThreadInterface : public Nanostack::MeshInterface {
public:
nsapi_error_t bringup(bool dhcp, const char *ip,
const char *netmask, const char *gw,
nsapi_ip_stack_t stack = IPV6_STACK,
nsapi_ip_stack_t stack = DEFAULT_STACK,
bool blocking = true) override;
nsapi_error_t bringdown() override;
friend class Nanostack;

2
connectivity/nanostack/mbed-mesh-api/source/WisunInterface.cpp
View File

@ -34,7 +34,7 @@ class Nanostack::WisunInterface final : public Nanostack::MeshInterface {
public:
nsapi_error_t bringup(bool dhcp, const char *ip,
const char *netmask, const char *gw,
nsapi_ip_stack_t stack = IPV6_STACK,
nsapi_ip_stack_t stack = DEFAULT_STACK,
bool blocking = true) override;
nsapi_error_t bringdown() override;
nsapi_error_t get_gateway(SocketAddress *address) override;

11
connectivity/nanostack/sal-stack-nanostack/source/Core/ns_socket.c
View File

@ -1570,8 +1570,17 @@ struct protocol_interface_info_entry *socket_interface_determine(const socket_t
}
}
/* Try a routing table entry for greater-than-realm scope */
/* For greater-than-realm scope, use default interface if a default interface ID */
/* has been set (e.g. using setsockopt), else try a routing table entry */
if (addr_ipv6_scope(buf->dst_sa.address, NULL) > IPV6_SCOPE_REALM_LOCAL) {
if (socket_ptr->default_interface_id != -1) {
cur_interface = protocol_stack_interface_info_get_by_id(socket_ptr->default_interface_id);
if (cur_interface) {
return cur_interface;
} else {
return NULL;
}
}
if (ipv6_buffer_route(buf)) {
return buf->interface;
}

2
connectivity/nanostack/sal-stack-nanostack/source/Security/TLS/tls_lib.c
View File

@ -2095,7 +2095,7 @@ void tls_master_key_cal(tls_heap_t *heap_ptr, sec_suite_t *tls_suite)
{
uint8_t *ptr;
prf_sec_param_t *prf_ptr = shalib_prf_param_get();
uint8_t secret_buf[2 + 16 + 2 + 16];
static uint8_t secret_buf[2 + 16 + 2 + 16];
tr_debug("CAL Master secret:");
//Her have to to be set check is
#ifdef ECC

2
connectivity/nanostack/source/Nanostack.cpp
View File

@ -678,6 +678,8 @@ nsapi_error_t Nanostack::socket_open(void **handle, nsapi_protocol_t protocol)
ns_proto = SOCKET_UDP;
} else if (NSAPI_TCP == protocol) {
ns_proto = SOCKET_TCP;
} else if (NSAPI_ICMP == protocol) {
ns_proto = SOCKET_ICMP;
} else {
MBED_ASSERT(false);
return NSAPI_ERROR_UNSUPPORTED;

2
connectivity/netsocket/source/TLSSocketWrapper.cpp
View File

@ -77,7 +77,7 @@ TLSSocketWrapper::TLSSocketWrapper(Socket *transport, const char *hostname, cont
TLSSocketWrapper::~TLSSocketWrapper()
{
if (_transport) {
close();
TLSSocketWrapper::close();
}
mbedtls_entropy_free(&_entropy);

21
connectivity/netsocket/tests/TESTS/netsocket/tls/main.cpp
View File

@ -218,22 +218,23 @@ static void test_failure_handler(const failure_t failure)
Case cases[] = {
Case("TLSSOCKET_ECHOTEST", TLSSOCKET_ECHOTEST),
Case("TLSSOCKET_ECHOTEST_NONBLOCK", TLSSOCKET_ECHOTEST_NONBLOCK),
// Disable tests temporarily till echo server is back on
// Case("TLSSOCKET_ECHOTEST", TLSSOCKET_ECHOTEST),
// Case("TLSSOCKET_ECHOTEST_NONBLOCK", TLSSOCKET_ECHOTEST_NONBLOCK),
Case("TLSSOCKET_CONNECT_INVALID", TLSSOCKET_CONNECT_INVALID),
Case("TLSSOCKET_ECHOTEST_BURST", TLSSOCKET_ECHOTEST_BURST),
Case("TLSSOCKET_ECHOTEST_BURST_NONBLOCK", TLSSOCKET_ECHOTEST_BURST_NONBLOCK),
Case("TLSSOCKET_RECV_TIMEOUT", TLSSOCKET_RECV_TIMEOUT),
Case("TLSSOCKET_ENDPOINT_CLOSE", TLSSOCKET_ENDPOINT_CLOSE),
// Case("TLSSOCKET_ECHOTEST_BURST", TLSSOCKET_ECHOTEST_BURST),
// Case("TLSSOCKET_ECHOTEST_BURST_NONBLOCK", TLSSOCKET_ECHOTEST_BURST_NONBLOCK),
// Case("TLSSOCKET_RECV_TIMEOUT", TLSSOCKET_RECV_TIMEOUT),
// Case("TLSSOCKET_ENDPOINT_CLOSE", TLSSOCKET_ENDPOINT_CLOSE),
Case("TLSSOCKET_HANDSHAKE_INVALID", TLSSOCKET_HANDSHAKE_INVALID),
Case("TLSSOCKET_OPEN_TWICE", TLSSOCKET_OPEN_TWICE),
Case("TLSSOCKET_OPEN_LIMIT", TLSSOCKET_OPEN_LIMIT),
Case("TLSSOCKET_OPEN_DESTRUCT", TLSSOCKET_OPEN_DESTRUCT),
Case("TLSSOCKET_SEND_UNCONNECTED", TLSSOCKET_SEND_UNCONNECTED),
Case("TLSSOCKET_SEND_CLOSED", TLSSOCKET_SEND_CLOSED),
Case("TLSSOCKET_SEND_REPEAT", TLSSOCKET_SEND_REPEAT),
Case("TLSSOCKET_SEND_TIMEOUT", TLSSOCKET_SEND_TIMEOUT),
Case("TLSSOCKET_NO_CERT", TLSSOCKET_NO_CERT),
// Case("TLSSOCKET_SEND_CLOSED", TLSSOCKET_SEND_CLOSED),
// Case("TLSSOCKET_SEND_REPEAT", TLSSOCKET_SEND_REPEAT),
// Case("TLSSOCKET_SEND_TIMEOUT", TLSSOCKET_SEND_TIMEOUT),
// Case("TLSSOCKET_NO_CERT", TLSSOCKET_NO_CERT),
// Temporarily removing this test, as TLS library consumes too much memory
// and we see frequent memory allocation failures on architectures with less
// RAM such as DISCO_L475VG_IOT1A and NUCLEO_F207ZG (both have 128 kB RAM)

8
drivers/source/CAN.cpp
View File

@ -19,6 +19,7 @@
#if DEVICE_CAN
#include "platform/mbed_power_mgmt.h"
#include "platform/mbed_error.h"
namespace mbed {
@ -82,6 +83,9 @@ int CAN::read(CANMessage &msg, int handle)
{
lock();
int ret = can_read(&_can, &msg, handle);
if (msg.len > 8) {
MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_CAN, MBED_ERROR_CODE_READ_FAILED), "Read tried to write more than 8 bytes");
}
unlock();
return ret;
}
@ -134,7 +138,7 @@ int CAN::filter(unsigned int id, unsigned int mask, CANFormat format, int handle
void CAN::attach(Callback<void()> func, IrqType type)
{
lock();
CAN::lock();
if (func) {
// lock deep sleep only the first time
if (!_irq[(CanIrqType)type]) {
@ -150,7 +154,7 @@ void CAN::attach(Callback<void()> func, IrqType type)
_irq[(CanIrqType)type] = nullptr;
can_irq_set(&_can, (CanIrqType)type, 0);
}
unlock();
CAN::unlock();
}
void CAN::_irq_handler(uintptr_t context, CanIrqType type)

4
drivers/source/SPI.cpp
View File

@ -148,12 +148,12 @@ void SPI::_do_construct()
SPI::~SPI()
{
lock();
SPI::lock();
/* Make sure a stale pointer isn't left in peripheral's owner field */
if (_peripheral->owner == this) {
_peripheral->owner = nullptr;
}
unlock();
SPI::unlock();
}
SPI::spi_peripheral_s *SPI::_lookup(SPI::SPIName name)

2
platform/include/platform/mbed_version.h
View File

@ -38,7 +38,7 @@
*
* @note 99 is default value for development version (master branch)
*/
#define MBED_MINOR_VERSION 16
#define MBED_MINOR_VERSION 17
/** MBED_PATCH_VERSION
* Mbed OS patch version

3
storage/filesystem/fat/ChaN/ff.cpp
View File

@ -537,7 +537,7 @@ static WCHAR LfnBuf[FF_MAX_LFN + 1]; /* LFN working buffer */
#elif FF_USE_LFN == 3 /* LFN enabled with dynamic working buffer on the heap */
#if FF_FS_EXFAT
#define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer and directory entry block scratchpad buffer */
#define INIT_NAMBUF(fs) { lfn = ff_memalloc((FF_MAX_LFN+1)*2 + MAXDIRB(FF_MAX_LFN)); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+FF_MAX_LFN+1); }
#define INIT_NAMBUF(fs) { lfn = (WCHAR *)(ff_memalloc((FF_MAX_LFN+1)*2 + MAXDIRB(FF_MAX_LFN))); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+FF_MAX_LFN+1); }
#define FREE_NAMBUF() ff_memfree(lfn)
#else
#define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer */
@ -555,6 +555,7 @@ static WCHAR LfnBuf[FF_MAX_LFN + 1]; /* LFN working buffer */
/*--------------------------------*/
/* Code conversion tables */
/*--------------------------------*/

2
storage/filesystem/source/Dir.cpp
View File

@ -34,7 +34,7 @@ Dir::Dir(FileSystem *fs, const char *path)
Dir::~Dir()
{
if (_fs) {
close();
Dir::close();
}
}

2
storage/filesystem/source/File.cpp
View File

@ -34,7 +34,7 @@ File::File(FileSystem *fs, const char *path, int flags)
File::~File()
{
if (_fs) {
close();
File::close();
}
}

2
storage/kvstore/securestore/source/SecureStore.cpp
View File

@ -789,7 +789,7 @@ int SecureStore::deinit()
mbedtls_entropy_free(_entropy);
delete _entropy;
delete _ih;
delete _scratch_buf;
delete[] _scratch_buf;
_entropy = nullptr;
}
ret = _underlying_kv->deinit();

1
targets/TARGET_Maxim/TARGET_MAX32670/CMakeLists.txt
View File

@ -84,7 +84,6 @@ target_sources(mbed-max32670
${MXM_SOURCE_DIR}/FLC/flc_common.c
${MXM_SOURCE_DIR}/FLC/flc_me15.c
${MXM_SOURCE_DIR}/FLC/flc_reva.c
${MXM_SOURCE_DIR}/FLC/flc_revb.c
${MXM_SOURCE_DIR}/GPIO/gpio_common.c
${MXM_SOURCE_DIR}/GPIO/gpio_me15.c

21
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_key_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file aes_key_regs.h
* @brief Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module.
* @note This file is @deprecated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,12 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _AES_KEY_REGS_H_
#define _AES_KEY_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AES_KEY_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AES_KEY_REGS_H_
#warning "DEPRECATED(1-10-2023): aes_key_regs.h - Scheduled for removal. Please use aeskeys_regs.h."
/* **** Includes **** */
#include <stdint.h>
@ -82,6 +84,11 @@ extern "C" {
* @ingroup aes_key_registers
* Structure type to access the AES_KEY Registers.
*/
#if defined(__GNUC__)
__attribute__((deprecated("mxc_aes_key_regs_t struct and aes_key_regs.h no longer supported. Use aeskeys_regs.h and MXC_AESKEYS (mxc_aeskeys_regs_t) for AES Key Access. 1-10-2023")))
#else
#warning "mxc_aes_key_regs_t struct and aes_key_regs.h no longer supported. Use aeskeys_regs.h and MXC_AESKEYS (mxc_aeskeys_regs_t) for AES Key Access. 1-10-2023"
#endif
typedef struct {
__IO uint32_t aes_key0; /**< <tt>\b 0x00:</tt> AES_KEY AES_KEY0 Register */
__IO uint32_t aes_key1; /**< <tt>\b 0x04:</tt> AES_KEY AES_KEY1 Register */
@ -114,4 +121,4 @@ typedef struct {
}
#endif
#endif /* _AES_KEY_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AES_KEY_REGS_H_

20
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file aes_regs.h
* @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _AES_REGS_H_
#define _AES_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AES_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AES_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -183,6 +183,9 @@ typedef struct {
#define MXC_F_AES_INTFL_OV_POS 3 /**< INTFL_OV Position */
#define MXC_F_AES_INTFL_OV ((uint32_t)(0x1UL << MXC_F_AES_INTFL_OV_POS)) /**< INTFL_OV Mask */
#define MXC_F_AES_INTFL_KEY_ONE_POS 4 /**< INTFL_KEY_ONE Position */
#define MXC_F_AES_INTFL_KEY_ONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ONE_POS)) /**< INTFL_KEY_ONE Mask */
/**@} end of group AES_INTFL_Register */
/**
@ -203,6 +206,9 @@ typedef struct {
#define MXC_F_AES_INTEN_OV_POS 3 /**< INTEN_OV Position */
#define MXC_F_AES_INTEN_OV ((uint32_t)(0x1UL << MXC_F_AES_INTEN_OV_POS)) /**< INTEN_OV Mask */
#define MXC_F_AES_INTEN_KEY_ONE_POS 4 /**< INTEN_KEY_ONE Position */
#define MXC_F_AES_INTEN_KEY_ONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ONE_POS)) /**< INTEN_KEY_ONE Mask */
/**@} end of group AES_INTEN_Register */
/**
@ -220,4 +226,4 @@ typedef struct {
}
#endif
#endif /* _AES_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AES_REGS_H_

117
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aeskeys_regs.h Normal file
View File

@ -0,0 +1,117 @@
/**
* @file aeskeys_regs.h
* @brief Registers, Bit Masks and Bit Positions for the AESKEYS Peripheral Module.
* @note This file is @generated.
*/
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
******************************************************************************/
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AESKEYS_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AESKEYS_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup aeskeys
* @defgroup aeskeys_registers AESKEYS_Registers
* @brief Registers, Bit Masks and Bit Positions for the AESKEYS Peripheral Module.
* @details AES Key Registers.
*/
/**
* @ingroup aeskeys_registers
* Structure type to access the AESKEYS Registers.
*/
typedef struct {
__IO uint32_t key0; /**< <tt>\b 0x00:</tt> AESKEYS KEY0 Register */
__IO uint32_t key1; /**< <tt>\b 0x04:</tt> AESKEYS KEY1 Register */
__IO uint32_t key2; /**< <tt>\b 0x08:</tt> AESKEYS KEY2 Register */
__IO uint32_t key3; /**< <tt>\b 0x0C:</tt> AESKEYS KEY3 Register */
__IO uint32_t key4; /**< <tt>\b 0x10:</tt> AESKEYS KEY4 Register */
__IO uint32_t key5; /**< <tt>\b 0x14:</tt> AESKEYS KEY5 Register */
__IO uint32_t key6; /**< <tt>\b 0x18:</tt> AESKEYS KEY6 Register */
__IO uint32_t key7; /**< <tt>\b 0x1C:</tt> AESKEYS KEY7 Register */
} mxc_aeskeys_regs_t;
/* Register offsets for module AESKEYS */
/**
* @ingroup aeskeys_registers
* @defgroup AESKEYS_Register_Offsets Register Offsets
* @brief AESKEYS Peripheral Register Offsets from the AESKEYS Base Peripheral Address.
* @{
*/
#define MXC_R_AESKEYS_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AESKEYS Base Address: <tt> 0x0000</tt> */
#define MXC_R_AESKEYS_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AESKEYS Base Address: <tt> 0x0004</tt> */
#define MXC_R_AESKEYS_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AESKEYS Base Address: <tt> 0x0008</tt> */
#define MXC_R_AESKEYS_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AESKEYS Base Address: <tt> 0x000C</tt> */
#define MXC_R_AESKEYS_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AESKEYS Base Address: <tt> 0x0010</tt> */
#define MXC_R_AESKEYS_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AESKEYS Base Address: <tt> 0x0014</tt> */
#define MXC_R_AESKEYS_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AESKEYS Base Address: <tt> 0x0018</tt> */
#define MXC_R_AESKEYS_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AESKEYS Base Address: <tt> 0x001C</tt> */
/**@} end of group aeskeys_registers */
#ifdef __cplusplus
}
#endif
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AESKEYS_REGS_H_

14
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/crc_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file crc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the CRC Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _CRC_REGS_H_
#define _CRC_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_CRC_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_CRC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -193,4 +193,4 @@ typedef struct {
}
#endif
#endif /* _CRC_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_CRC_REGS_H_

56
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/dma_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file dma_regs.h
* @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _DMA_REGS_H_
#define _DMA_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_DMA_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_DMA_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -78,25 +78,21 @@ extern "C" {
* @details DMA Controller Fully programmable, chaining capable DMA channels.
*/
/**
* @ingroup dma_registers
* Structure type to access the DMA Channel Registers.
*/
typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x100:</tt> DMA CTRL Register */
__IO uint32_t status; /**< <tt>\b 0x104:</tt> DMA STATUS Register */
__IO uint32_t src; /**< <tt>\b 0x108:</tt> DMA SRC Register */
__IO uint32_t dst; /**< <tt>\b 0x10C:</tt> DMA DST Register */
__IO uint32_t cnt; /**< <tt>\b 0x110:</tt> DMA CNT Register */
__IO uint32_t srcrld; /**< <tt>\b 0x114:</tt> DMA SRCRLD Register */
__IO uint32_t dstrld; /**< <tt>\b 0x118:</tt> DMA DSTRLD Register */
__IO uint32_t cntrld; /**< <tt>\b 0x11C:</tt> DMA CNTRLD Register */
} mxc_dma_ch_regs_t;
/**
* @ingroup dma_registers
* Structure type to access the DMA Registers.
*/
typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x000:</tt> DMA CTRL Register */
__IO uint32_t status; /**< <tt>\b 0x004:</tt> DMA STATUS Register */
__IO uint32_t src; /**< <tt>\b 0x008:</tt> DMA SRC Register */
__IO uint32_t dst; /**< <tt>\b 0x00C:</tt> DMA DST Register */
__IO uint32_t cnt; /**< <tt>\b 0x010:</tt> DMA CNT Register */
__IO uint32_t srcrld; /**< <tt>\b 0x014:</tt> DMA SRCRLD Register */
__IO uint32_t dstrld; /**< <tt>\b 0x018:</tt> DMA DSTRLD Register */
__IO uint32_t cntrld; /**< <tt>\b 0x01C:</tt> DMA CNTRLD Register */
} mxc_dma_ch_regs_t;
typedef struct {
__IO uint32_t inten; /**< <tt>\b 0x000:</tt> DMA INTEN Register */
__I uint32_t intfl; /**< <tt>\b 0x004:</tt> DMA INTFL Register */
@ -111,14 +107,14 @@ typedef struct {
* @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address.
* @{
*/
#define MXC_R_DMA_CTRL ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
#define MXC_R_DMA_STATUS ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */
#define MXC_R_DMA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */
#define MXC_R_DMA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */
#define MXC_R_DMA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */
#define MXC_R_DMA_SRCRLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */
#define MXC_R_DMA_DSTRLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */
#define MXC_R_DMA_CNTRLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */
#define MXC_R_DMA_CTRL ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */
#define MXC_R_DMA_STATUS ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */
#define MXC_R_DMA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: <tt> 0x0008</tt> */
#define MXC_R_DMA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: <tt> 0x000C</tt> */
#define MXC_R_DMA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: <tt> 0x0010</tt> */
#define MXC_R_DMA_SRCRLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: <tt> 0x0014</tt> */
#define MXC_R_DMA_DSTRLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: <tt> 0x0018</tt> */
#define MXC_R_DMA_CNTRLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: <tt> 0x001C</tt> */
#define MXC_R_DMA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */
#define MXC_R_DMA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */
#define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
@ -450,4 +446,4 @@ typedef struct {
}
#endif
#endif /* _DMA_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_DMA_REGS_H_

26
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/ecc_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file ecc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the ECC Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _ECC_REGS_H_
#define _ECC_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_ECC_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_ECC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup ecc
* @defgroup ecc_registers ECC_Registers
* @brief Registers, Bit Masks and Bit Positions for the ECC Peripheral Module.
* @details Error Correction Code
* @details Trim System Initilazation Registers. ECC Registers for MAX32670.
*/
/**
@ -100,14 +100,14 @@ typedef struct {
/**
* @ingroup ecc_registers
* @defgroup ECC_EN ECC_EN
* @brief ECC Enable Register
* @brief ECC Enable Register.
* @{
*/
#define MXC_F_ECC_EN_RAM_POS 8 /**< EN_RAM Position */
#define MXC_F_ECC_EN_RAM ((uint32_t)(0x1UL << MXC_F_ECC_EN_RAM_POS)) /**< EN_RAM Mask */
#define MXC_F_ECC_EN_SRAM_POS 8 /**< EN_SRAM Position */
#define MXC_F_ECC_EN_SRAM ((uint32_t)(0x1UL << MXC_F_ECC_EN_SRAM_POS)) /**< EN_SRAM Mask */
#define MXC_F_ECC_EN_ICC0_POS 9 /**< EN_ICC0 Position */
#define MXC_F_ECC_EN_ICC0 ((uint32_t)(0x1UL << MXC_F_ECC_EN_ICC0_POS)) /**< EN_ICC0 Mask */
#define MXC_F_ECC_EN_ICC_POS 9 /**< EN_ICC Position */
#define MXC_F_ECC_EN_ICC ((uint32_t)(0x1UL << MXC_F_ECC_EN_ICC_POS)) /**< EN_ICC Mask */
#define MXC_F_ECC_EN_FLASH_POS 10 /**< EN_FLASH Position */
#define MXC_F_ECC_EN_FLASH ((uint32_t)(0x1UL << MXC_F_ECC_EN_FLASH_POS)) /**< EN_FLASH Mask */
@ -118,4 +118,4 @@ typedef struct {
}
#endif
#endif /* _ECC_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_ECC_REGS_H_

180
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/emcc_regs.h
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@ -1,180 +0,0 @@
/**
* @file emcc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the EMCC Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _EMCC_REGS_H_
#define _EMCC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup emcc
* @defgroup emcc_registers EMCC_Registers
* @brief Registers, Bit Masks and Bit Positions for the EMCC Peripheral Module.
* @details External Memory Cache Controller Registers.
*/
/**
* @ingroup emcc_registers
* Structure type to access the EMCC Registers.
*/
typedef struct {
__I uint32_t cache_id; /**< <tt>\b 0x0000:</tt> EMCC CACHE_ID Register */
__I uint32_t memcfg; /**< <tt>\b 0x0004:</tt> EMCC MEMCFG Register */
__I uint32_t rsv_0x8_0xff[62];
__IO uint32_t cache_ctrl; /**< <tt>\b 0x0100:</tt> EMCC CACHE_CTRL Register */
__I uint32_t rsv_0x104_0x6ff[383];
__IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> EMCC INVALIDATE Register */
} mxc_emcc_regs_t;
/* Register offsets for module EMCC */
/**
* @ingroup emcc_registers
* @defgroup EMCC_Register_Offsets Register Offsets
* @brief EMCC Peripheral Register Offsets from the EMCC Base Peripheral Address.
* @{
*/
#define MXC_R_EMCC_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from EMCC Base Address: <tt> 0x0000</tt> */
#define MXC_R_EMCC_MEMCFG ((uint32_t)0x00000004UL) /**< Offset from EMCC Base Address: <tt> 0x0004</tt> */
#define MXC_R_EMCC_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from EMCC Base Address: <tt> 0x0100</tt> */
#define MXC_R_EMCC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from EMCC Base Address: <tt> 0x0700</tt> */
/**@} end of group emcc_registers */
/**
* @ingroup emcc_registers
* @defgroup EMCC_CACHE_ID EMCC_CACHE_ID
* @brief Cache ID Register.
* @{
*/
#define MXC_F_EMCC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */
#define MXC_F_EMCC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_EMCC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */
#define MXC_F_EMCC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */
#define MXC_F_EMCC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_EMCC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */
#define MXC_F_EMCC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */
#define MXC_F_EMCC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_EMCC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */
/**@} end of group EMCC_CACHE_ID_Register */
/**
* @ingroup emcc_registers
* @defgroup EMCC_MEMCFG EMCC_MEMCFG
* @brief Memory Configuration Register.
* @{
*/
#define MXC_F_EMCC_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */
#define MXC_F_EMCC_MEMCFG_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_EMCC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */
#define MXC_F_EMCC_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */
#define MXC_F_EMCC_MEMCFG_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_EMCC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */
/**@} end of group EMCC_MEMCFG_Register */
/**
* @ingroup emcc_registers
* @defgroup EMCC_CACHE_CTRL EMCC_CACHE_CTRL
* @brief Cache Control and Status Register.
* @{
*/
#define MXC_F_EMCC_CACHE_CTRL_CACHE_EN_POS 0 /**< CACHE_CTRL_CACHE_EN Position */
#define MXC_F_EMCC_CACHE_CTRL_CACHE_EN ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CACHE_EN_POS)) /**< CACHE_CTRL_CACHE_EN Mask */
#define MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_EN_POS 1 /**< CACHE_CTRL_WRITE_ALLOC_EN Position */
#define MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_EN ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_EN_POS)) /**< CACHE_CTRL_WRITE_ALLOC_EN Mask */
#define MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS 2 /**< CACHE_CTRL_CWFST_DIS Position */
#define MXC_F_EMCC_CACHE_CTRL_CWFST_DIS ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS)) /**< CACHE_CTRL_CWFST_DIS Mask */
#define MXC_F_EMCC_CACHE_CTRL_CACHE_RDY_POS 16 /**< CACHE_CTRL_CACHE_RDY Position */
#define MXC_F_EMCC_CACHE_CTRL_CACHE_RDY ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CACHE_RDY_POS)) /**< CACHE_CTRL_CACHE_RDY Mask */
/**@} end of group EMCC_CACHE_CTRL_Register */
/**
* @ingroup emcc_registers
* @defgroup EMCC_INVALIDATE EMCC_INVALIDATE
* @brief Invalidate All Cache Contents. Any time this register location is written
* (regardless of the data value), the cache controller immediately begins
* invalidating the entire contents of the cache memory. The cache will be in
* bypass mode until the invalidate operation is complete. System software can
* examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the
* invalidate operation is complete. Note that it is not necessary to disable the
* cache controller prior to beginning this operation. Reads from this register
* always return 0.
* @{
*/
#define MXC_F_EMCC_INVALIDATE_IA_POS 0 /**< INVALIDATE_IA Position */
#define MXC_F_EMCC_INVALIDATE_IA ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMCC_INVALIDATE_IA_POS)) /**< INVALIDATE_IA Mask */
/**@} end of group EMCC_INVALIDATE_Register */
#ifdef __cplusplus
}
#endif
#endif /* _EMCC_REGS_H_ */

14
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/fcr_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file fcr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _FCR_REGS_H_
#define _FCR_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FCR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FCR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -189,4 +189,4 @@ typedef struct {
}
#endif
#endif /* _FCR_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FCR_REGS_H_

14
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/flc_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file flc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _FLC_REGS_H_
#define _FLC_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FLC_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FLC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -292,4 +292,4 @@ typedef struct {
}
#endif
#endif /* _FLC_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FLC_REGS_H_

189
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcfr_regs.h
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@ -1,189 +0,0 @@
/**
* @file gcfr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the GCFR Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _GCFR_REGS_H_
#define _GCFR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup gcfr
* @defgroup gcfr_registers GCFR_Registers
* @brief Registers, Bit Masks and Bit Positions for the GCFR Peripheral Module.
* @details Global Control Function Register.
*/
/**
* @ingroup gcfr_registers
* Structure type to access the GCFR Registers.
*/
typedef struct {
__IO uint32_t reg0; /**< <tt>\b 0x00:</tt> GCFR REG0 Register */
__IO uint32_t reg1; /**< <tt>\b 0x04:</tt> GCFR REG1 Register */
__IO uint32_t reg2; /**< <tt>\b 0x08:</tt> GCFR REG2 Register */
__IO uint32_t reg3; /**< <tt>\b 0x0C:</tt> GCFR REG3 Register */
} mxc_gcfr_regs_t;
/* Register offsets for module GCFR */
/**
* @ingroup gcfr_registers
* @defgroup GCFR_Register_Offsets Register Offsets
* @brief GCFR Peripheral Register Offsets from the GCFR Base Peripheral Address.
* @{
*/
#define MXC_R_GCFR_REG0 ((uint32_t)0x00000000UL) /**< Offset from GCFR Base Address: <tt> 0x0000</tt> */
#define MXC_R_GCFR_REG1 ((uint32_t)0x00000004UL) /**< Offset from GCFR Base Address: <tt> 0x0004</tt> */
#define MXC_R_GCFR_REG2 ((uint32_t)0x00000008UL) /**< Offset from GCFR Base Address: <tt> 0x0008</tt> */
#define MXC_R_GCFR_REG3 ((uint32_t)0x0000000CUL) /**< Offset from GCFR Base Address: <tt> 0x000C</tt> */
/**@} end of group gcfr_registers */
/**
* @ingroup gcfr_registers
* @defgroup GCFR_REG0 GCFR_REG0
* @brief Register 0.
* @{
*/
#define MXC_F_GCFR_REG0_CNNX16_0_PWR_EN_POS 0 /**< REG0_CNNX16_0_PWR_EN Position */
#define MXC_F_GCFR_REG0_CNNX16_0_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_0_PWR_EN_POS)) /**< REG0_CNNX16_0_PWR_EN Mask */
#define MXC_F_GCFR_REG0_CNNX16_1_PWR_EN_POS 1 /**< REG0_CNNX16_1_PWR_EN Position */
#define MXC_F_GCFR_REG0_CNNX16_1_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_1_PWR_EN_POS)) /**< REG0_CNNX16_1_PWR_EN Mask */
#define MXC_F_GCFR_REG0_CNNX16_2_PWR_EN_POS 2 /**< REG0_CNNX16_2_PWR_EN Position */
#define MXC_F_GCFR_REG0_CNNX16_2_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_2_PWR_EN_POS)) /**< REG0_CNNX16_2_PWR_EN Mask */
#define MXC_F_GCFR_REG0_CNNX16_3_PWR_EN_POS 3 /**< REG0_CNNX16_3_PWR_EN Position */
#define MXC_F_GCFR_REG0_CNNX16_3_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_3_PWR_EN_POS)) /**< REG0_CNNX16_3_PWR_EN Mask */
/**@} end of group GCFR_REG0_Register */
/**
* @ingroup gcfr_registers
* @defgroup GCFR_REG1 GCFR_REG1
* @brief Register 1.
* @{
*/
#define MXC_F_GCFR_REG1_CNNX16_0_RAM_EN_POS 0 /**< REG1_CNNX16_0_RAM_EN Position */
#define MXC_F_GCFR_REG1_CNNX16_0_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_0_RAM_EN_POS)) /**< REG1_CNNX16_0_RAM_EN Mask */
#define MXC_F_GCFR_REG1_CNNX16_1_RAM_EN_POS 1 /**< REG1_CNNX16_1_RAM_EN Position */
#define MXC_F_GCFR_REG1_CNNX16_1_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_1_RAM_EN_POS)) /**< REG1_CNNX16_1_RAM_EN Mask */
#define MXC_F_GCFR_REG1_CNNX16_2_RAM_EN_POS 2 /**< REG1_CNNX16_2_RAM_EN Position */
#define MXC_F_GCFR_REG1_CNNX16_2_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_2_RAM_EN_POS)) /**< REG1_CNNX16_2_RAM_EN Mask */
#define MXC_F_GCFR_REG1_CNNX16_3_RAM_EN_POS 3 /**< REG1_CNNX16_3_RAM_EN Position */
#define MXC_F_GCFR_REG1_CNNX16_3_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_3_RAM_EN_POS)) /**< REG1_CNNX16_3_RAM_EN Mask */
/**@} end of group GCFR_REG1_Register */
/**
* @ingroup gcfr_registers
* @defgroup GCFR_REG2 GCFR_REG2
* @brief Register 2.
* @{
*/
#define MXC_F_GCFR_REG2_CNNX16_0_ISO_POS 0 /**< REG2_CNNX16_0_ISO Position */
#define MXC_F_GCFR_REG2_CNNX16_0_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_0_ISO_POS)) /**< REG2_CNNX16_0_ISO Mask */
#define MXC_F_GCFR_REG2_CNNX16_1_ISO_POS 1 /**< REG2_CNNX16_1_ISO Position */
#define MXC_F_GCFR_REG2_CNNX16_1_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_1_ISO_POS)) /**< REG2_CNNX16_1_ISO Mask */
#define MXC_F_GCFR_REG2_CNNX16_2_ISO_POS 2 /**< REG2_CNNX16_2_ISO Position */
#define MXC_F_GCFR_REG2_CNNX16_2_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_2_ISO_POS)) /**< REG2_CNNX16_2_ISO Mask */
#define MXC_F_GCFR_REG2_CNNX16_3_ISO_POS 3 /**< REG2_CNNX16_3_ISO Position */
#define MXC_F_GCFR_REG2_CNNX16_3_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_3_ISO_POS)) /**< REG2_CNNX16_3_ISO Mask */
/**@} end of group GCFR_REG2_Register */
/**
* @ingroup gcfr_registers
* @defgroup GCFR_REG3 GCFR_REG3
* @brief Register 3.
* @{
*/
#define MXC_F_GCFR_REG3_CNNX16_0_RST_POS 0 /**< REG3_CNNX16_0_RST Position */
#define MXC_F_GCFR_REG3_CNNX16_0_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_0_RST_POS)) /**< REG3_CNNX16_0_RST Mask */
#define MXC_F_GCFR_REG3_CNNX16_1_RST_POS 1 /**< REG3_CNNX16_1_RST Position */
#define MXC_F_GCFR_REG3_CNNX16_1_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_1_RST_POS)) /**< REG3_CNNX16_1_RST Mask */
#define MXC_F_GCFR_REG3_CNNX16_2_RST_POS 2 /**< REG3_CNNX16_2_RST Position */
#define MXC_F_GCFR_REG3_CNNX16_2_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_2_RST_POS)) /**< REG3_CNNX16_2_RST Mask */
#define MXC_F_GCFR_REG3_CNNX16_3_RST_POS 3 /**< REG3_CNNX16_3_RST Position */
#define MXC_F_GCFR_REG3_CNNX16_3_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_3_RST_POS)) /**< REG3_CNNX16_3_RST Mask */
/**@} end of group GCFR_REG3_Register */
#ifdef __cplusplus
}
#endif
#endif /* _GCFR_REGS_H_ */

16
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcr_regs.h
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@ -1,10 +1,11 @@
/**
* @file gcr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _GCR_REGS_H_
#define _GCR_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GCR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GCR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -354,7 +354,7 @@ typedef struct {
#define MXC_F_GCR_PM_LPUART0_WE_POS 8 /**< PM_LPUART0_WE Position */
#define MXC_F_GCR_PM_LPUART0_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPUART0_WE_POS)) /**< PM_LPUART0_WE Mask */
#define MXC_F_GCR_PM_ERFO_PD_POS 14 /**< PM_ERFO_PD Position */
#define MXC_F_GCR_PM_ERFO_PD_POS 12 /**< PM_ERFO_PD Position */
#define MXC_F_GCR_PM_ERFO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_PD_POS)) /**< PM_ERFO_PD Mask */
#define MXC_F_GCR_PM_IPO_PD_POS 16 /**< PM_IPO_PD Position */
@ -687,4 +687,4 @@ typedef struct {
}
#endif
#endif /* _GCR_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GCR_REGS_H_

14
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gpio_regs.h
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@ -1,10 +1,11 @@
/**
* @file gpio_regs.h
* @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _GPIO_REGS_H_
#define _GPIO_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GPIO_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GPIO_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -670,4 +670,4 @@ typedef struct {
}
#endif
#endif /* _GPIO_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GPIO_REGS_H_

20
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2c_regs.h
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@ -1,10 +1,11 @@
/**
* @file i2c_regs.h
* @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _I2C_REGS_H_
#define _I2C_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_I2C_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_I2C_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -550,6 +550,12 @@ typedef struct {
#define MXC_F_I2C_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR Position */
#define MXC_F_I2C_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_POS)) /**< SLAVE_ADDR Mask */
#define MXC_F_I2C_SLAVE_DIS_POS 10 /**< SLAVE_DIS Position */
#define MXC_F_I2C_SLAVE_DIS ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_DIS_POS)) /**< SLAVE_DIS Mask */
#define MXC_F_I2C_SLAVE_IDX_POS 11 /**< SLAVE_IDX Position */
#define MXC_F_I2C_SLAVE_IDX ((uint32_t)(0xFUL << MXC_F_I2C_SLAVE_IDX_POS)) /**< SLAVE_IDX Mask */
#define MXC_F_I2C_SLAVE_EXT_ADDR_EN_POS 15 /**< SLAVE_EXT_ADDR_EN Position */
#define MXC_F_I2C_SLAVE_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_EXT_ADDR_EN_POS)) /**< SLAVE_EXT_ADDR_EN Mask */
@ -573,4 +579,4 @@ typedef struct {
}
#endif
#endif /* _I2C_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_I2C_REGS_H_

16
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2s_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file i2s_regs.h
* @brief Registers, Bit Masks and Bit Positions for the I2S Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _I2S_REGS_H_
#define _I2S_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_I2S_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_I2S_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -154,7 +154,7 @@ typedef struct {
#define MXC_F_I2S_CTRL0CH0_RST_POS 19 /**< CTRL0CH0_RST Position */
#define MXC_F_I2S_CTRL0CH0_RST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RST_POS)) /**< CTRL0CH0_RST Mask */
#define MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS 19 /**< CTRL0CH0_FIFO_LSB Position */
#define MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS 20 /**< CTRL0CH0_FIFO_LSB Position */
#define MXC_F_I2S_CTRL0CH0_FIFO_LSB ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS)) /**< CTRL0CH0_FIFO_LSB Mask */
#define MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS 24 /**< CTRL0CH0_RX_THD_VAL Position */
@ -277,4 +277,4 @@ typedef struct {
}
#endif
#endif /* _I2S_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_I2S_REGS_H_

14
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/icc_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file icc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _ICC_REGS_H_
#define _ICC_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_ICC_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_ICC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -164,4 +164,4 @@ typedef struct {
}
#endif
#endif /* _ICC_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_ICC_REGS_H_

186
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.h
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,10 +29,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
******************************************************************************/
#ifndef _MAX32670_REGS_H_
#define _MAX32670_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MAX32670_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MAX32670_H_
#ifndef TARGET_NUM
#define TARGET_NUM 32670
@ -183,7 +183,6 @@ typedef enum {
#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
@ -198,7 +197,6 @@ typedef enum {
#include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
#include "system_max32670.h" /*!< System Header */
/* ================================================================================ */
/* ================== Device Specific Memory Section ================== */
/* ================================================================================ */
@ -242,9 +240,24 @@ typedef enum {
#define MXC_BASE_FCR ((uint32_t)0x40000800UL)
#define MXC_FCR ((mxc_fcr_regs_t *)MXC_BASE_FCR)
/******************************************************************************/
/* AES Keys */
#define MXC_BASE_AESKEYS ((uint32_t)0x40005000UL)
#define MXC_AESKEYS ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS)
// DEPRECATED(1-10-2023): Scheduled for removal.
#define MXC_BASE_AESKEY MXC_BASE_AESKEYS
#define MXC_AESKEY ((mxc_aes_key_regs_t *)MXC_BASE_AESKEY)
/******************************************************************************/
/* Error Correcting Code */
/* ECC registers is a subset of TRIMSIR registers */
#define MXC_BASE_ECC ((uint32_t)0x40105400UL)
#define MXC_ECC ((mxc_ecc_regs_t *)MXC_BASE_ECC)
/******************************************************************************/
/* Trim System Initalization Register */
#define MXC_BASE_TRIMSIR ((uint32_t)0x40005400UL)
#define MXC_BASE_TRIMSIR ((uint32_t)0x400105400UL)
#define MXC_TRIMSIR ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR)
/******************************************************************************/
@ -269,12 +282,10 @@ typedef enum {
#define MXC_BASE_MCR ((uint32_t)0x40106C00UL)
#define MXC_MCR ((mxc_mcr_regs_t *)MXC_BASE_MCR)
/******************************************************************************/
/* Error Correcting Code */
#define MXC_BASE_ECC ((uint32_t)0x40105400UL)
#define MXC_ECC ((mxc_ecc_regs_t*)MXC_BASE_ECC)
/* AES */
#define MXC_BASE_AES ((uint32_t)0x40007400UL)
#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
/******************************************************************************/
/* GPIO */
@ -286,24 +297,23 @@ typedef enum {
#define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL)
#define MXC_GPIO1 ((mxc_gpio_regs_t *)MXC_BASE_GPIO1)
#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : \
(p) == MXC_GPIO1 ? 1 : -1)
#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : (p) == MXC_GPIO1 ? 1 : -1)
#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : \
(i) == 1 ? MXC_GPIO1 : 0)
#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : (i) == 1 ? MXC_GPIO1 : 0)
#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : \
(i) == 1 ? GPIO1_IRQn : 0)
#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : (i) == 1 ? GPIO1_IRQn : 0)
/******************************************************************************/
/* CRC */
#define MXC_BASE_CRC ((uint32_t)0x4000F000UL)
#define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC)
#define SEC(s) (((unsigned long)s) * 1000000UL)
/******************************************************************************/
/* Timer */
#define SEC(s) (((uint32_t)s) * 1000000UL)
#define MSEC(ms) (ms * 1000UL)
#define USEC(us) (us)
/* Timer */
#define MXC_CFG_TMR_INSTANCES (6)
#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
@ -319,37 +329,46 @@ typedef enum {
#define MXC_BASE_TMR5 ((uint32_t)0x40115000UL)
#define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5)
#define MXC_TMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? TMR0_IRQn : \
#define MXC_TMR_GET_IRQ(i) \
(IRQn_Type)((i) == 0 ? TMR0_IRQn : \
(i) == 1 ? TMR1_IRQn : \
(i) == 2 ? TMR2_IRQn : \
(i) == 3 ? TMR3_IRQn : \
(i) == 4 ? TMR4_IRQn : \
(i) == 5 ? TMR5_IRQn : 0)
(i) == 5 ? TMR5_IRQn : \
0)
#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
#define MXC_TMR_GET_BASE(i) \
((i) == 0 ? MXC_BASE_TMR0 : \
(i) == 1 ? MXC_BASE_TMR1 : \
(i) == 2 ? MXC_BASE_TMR2 : \
(i) == 3 ? MXC_BASE_TMR3 : \
(i) == 4 ? MXC_BASE_TMR4 : \
(i) == 5 ? MXC_BASE_TMR5 : 0)
(i) == 5 ? MXC_BASE_TMR5 : \
0)
#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
#define MXC_TMR_GET_TMR(i) \
((i) == 0 ? MXC_TMR0 : \
(i) == 1 ? MXC_TMR1 : \
(i) == 2 ? MXC_TMR2 : \
(i) == 3 ? MXC_TMR3 : \
(i) == 4 ? MXC_TMR4 : \
(i) == 5 ? MXC_TMR5 : 0)
(i) == 5 ? MXC_TMR5 : \
0)
#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
#define MXC_TMR_GET_IDX(p) \
((p) == MXC_TMR0 ? 0 : \
(p) == MXC_TMR1 ? 1 : \
(p) == MXC_TMR2 ? 2 : \
(p) == MXC_TMR3 ? 3 : \
(p) == MXC_TMR4 ? 4 : \
(p) == MXC_TMR5 ? 5 : -1)
(p) == MXC_TMR5 ? 5 : \
-1)
/******************************************************************************/
/* I2C */
#define MXC_I2C_INSTANCES (3)
#define MXC_I2C_FIFO_DEPTH (8)
#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL)
#define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0)
@ -358,24 +377,15 @@ typedef enum {
#define MXC_BASE_I2C2 ((uint32_t)0x4001F000UL)
#define MXC_I2C2 ((mxc_i2c_regs_t *)MXC_BASE_I2C2)
#define MXC_I2C_GET_IRQ(i) \
(IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : (i) == 2 ? I2C2_IRQn : 0)
#define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : \
(i) == 1 ? I2C1_IRQn : \
(i) == 2 ? I2C2_IRQn : 0)
#define MXC_I2C_GET_BASE(i) \
((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : (i) == 2 ? MXC_BASE_I2C2 : 0)
#define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : \
(i) == 1 ? MXC_BASE_I2C1 : \
(i) == 2 ? MXC_BASE_I2C2 : 0)
#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : \
(i) == 1 ? MXC_I2C1 : \
(i) == 2 ? MXC_I2C2 : 0)
#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : \
(p) == MXC_I2C1 ? 1 : \
(p) == MXC_I2C2 ? 2 : -1)
#define MXC_I2C_FIFO_DEPTH (8)
#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : (i) == 2 ? MXC_I2C2 : 0)
#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : (p) == MXC_I2C2 ? 2 : -1)
/******************************************************************************/
/* DMA */
@ -394,7 +404,6 @@ typedef enum {
#define MXC_BASE_FLC0 ((uint32_t)0x40029000UL)
#define MXC_FLC0 ((mxc_flc_regs_t *)MXC_BASE_FLC0)
#define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : 0)
#define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : 0)
@ -402,9 +411,9 @@ typedef enum {
#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : 0)
#define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : -1)
/******************************************************************************/
/* Instruction Cache */
#define MXC_BASE_ICC ((uint32_t)0x4002A000UL)
#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
@ -424,7 +433,6 @@ typedef enum {
/******************************************************************************/
/* UART / Serial Port Interface */
#define MXC_UART_INSTANCES (4)
#define MXC_UART_FIFO_DEPTH (8)
@ -437,29 +445,28 @@ typedef enum {
#define MXC_BASE_UART3 ((uint32_t)0x40145000UL)
#define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3)
#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
#define MXC_UART_GET_IRQ(i) \
(IRQn_Type)((i) == 0 ? UART0_IRQn : \
(i) == 1 ? UART1_IRQn : \
(i) == 2 ? UART2_IRQn : \
(i) == 3 ? UART3_IRQn : 0)
(i) == 3 ? UART3_IRQn : \
0)
#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
#define MXC_UART_GET_BASE(i) \
((i) == 0 ? MXC_BASE_UART0 : \
(i) == 1 ? MXC_BASE_UART1 : \
(i) == 2 ? MXC_BASE_UART2 : \
(i) == 3 ? MXC_BASE_UART3 : 0)
(i) == 3 ? MXC_BASE_UART3 : \
0)
#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
(i) == 1 ? MXC_UART1 : \
(i) == 2 ? MXC_UART2 : \
(i) == 3 ? MXC_UART3 : 0)
#define MXC_UART_GET_UART(i) \
((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : (i) == 2 ? MXC_UART2 : (i) == 3 ? MXC_UART3 : 0)
#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
(p) == MXC_UART1 ? 1 : \
(p) == MXC_UART2 ? 2 : \
(p) == MXC_UART3 ? 3 : -1)
#define MXC_UART_GET_IDX(p) \
((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : (p) == MXC_UART2 ? 2 : (p) == MXC_UART3 ? 3 : -1)
/******************************************************************************/
/* SPI */
#define MXC_SPI_INSTANCES (3)
#define MXC_SPI_SS_INSTANCES (4)
#define MXC_SPI_FIFO_DEPTH (32)
@ -471,58 +478,27 @@ typedef enum {
#define MXC_BASE_SPI2 ((uint32_t)0x40048000UL)
#define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2)
#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : (p) == MXC_SPI1 ? 1 : (p) == MXC_SPI2 ? 2 : -1)
#define MXC_SPI_GET_BASE(i) \
((i) == 0 ? MXC_BASE_SPI0 : (i) == 1 ? MXC_BASE_SPI1 : (i) == 2 ? MXC_BASE_SPI2 : 0)
#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : \
(p) == MXC_SPI1 ? 1 : \
(p) == MXC_SPI2 ? 2 : -1)
#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : \
(i) == 1 ? MXC_BASE_SPI1 : \
(i) == 2 ? MXC_BASE_SPI2 : 0)
#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : \
(i) == 1 ? MXC_SPI1 : \
(i) == 2 ? MXC_SPI2 : 0)
#define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI0_IRQn : \
(i) == 1 ? SPI1_IRQn : \
(i) == 2 ? SPI2_IRQn : 0)
#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : (i) == 1 ? MXC_SPI1 : (i) == 2 ? MXC_SPI2 : 0)
#define MXC_SPI_GET_IRQ(i) \
(IRQn_Type)((i) == 0 ? SPI0_IRQn : (i) == 1 ? SPI1_IRQn : (i) == 2 ? SPI2_IRQn : 0)
/******************************************************************************/
/* TRNG */
#define MXC_BASE_TRNG ((uint32_t)0x4004D000UL)
#define MXC_TRNG ((mxc_trng_regs_t *)MXC_BASE_TRNG)
/******************************************************************************/
/* AES */
#define MXC_BASE_AES ((uint32_t)0x40007400UL)
#define MXC_AES ((mxc_aes_regs_t*)MXC_BASE_AES)
/******************************************************************************/
/* AES Keys */
#define MXC_BASE_AESKEY ((uint32_t)0x40005000UL)
#define MXC_AESKEY ((mxc_aes_key_regs_t*)MXC_BASE_AESKEY)
/******************************************************************************/
/* CRC */
#define MXC_BASE_CRC ((uint32_t)0x4000F000UL)
#define MXC_CRC ((mxc_crc_regs_t*)MXC_BASE_CRC)
/******************************************************************************/
#define MXC_BASE_I2S ((uint32_t)0x40060000UL)
#define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S)
/******************************************************************************/
/* BBFC */
#define MXC_BASE_BBFC ((uint32_t)0x40005800UL)
#define MXC_BBFC ((mxc_bbfc_regs_t*)MXC_BASE_BBFC)
/******************************************************************************/
/* Bit Shifting */
#define MXC_F_BIT_0 (1 << 0)
#define MXC_F_BIT_1 (1 << 1)
#define MXC_F_BIT_2 (1 << 2)
@ -559,15 +535,15 @@ typedef enum {
/******************************************************************************/
/* Bit Banding */
#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \
(((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
#define BITBAND(reg, bit) \
((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \
((bit) << 2))
#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
#define MXC_SETFIELD(reg, mask, setting) (reg = (reg & ~mask) | (setting & mask))
#define MXC_SETFIELD(reg, mask, setting) (reg = ((reg) & ~(mask)) | ((setting) & (mask)))
/******************************************************************************/
/* SCB CPACR */
@ -578,4 +554,4 @@ typedef enum {
#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */
#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */
#endif /* _MAX32670_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MAX32670_H_

60
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/mcr_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file mcr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _MCR_REGS_H_
#define _MCR_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MCR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MCR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup mcr
* @defgroup mcr_registers MCR_Registers
* @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module.
* @details Misc Control.
* @details Miscellaneous Control Registers.
*/
/**
@ -85,7 +85,9 @@ extern "C" {
typedef struct {
__I uint32_t rsv_0x0;
__IO uint32_t rst; /**< <tt>\b 0x04:</tt> MCR RST Register */
__I uint32_t rsv_0x8_0x23[7];
__I uint32_t rsv_0x8_0xf[2];
__IO uint32_t lppioctrl; /**< <tt>\b 0x10:</tt> MCR LPPIOCTRL Register */
__I uint32_t rsv_0x14_0x23[4];
__IO uint32_t clkdis; /**< <tt>\b 0x24:</tt> MCR CLKDIS Register */
} mxc_mcr_regs_t;
@ -97,13 +99,14 @@ typedef struct {
* @{
*/
#define MXC_R_MCR_RST ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: <tt> 0x0004</tt> */
#define MXC_R_MCR_LPPIOCTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: <tt> 0x0010</tt> */
#define MXC_R_MCR_CLKDIS ((uint32_t)0x00000024UL) /**< Offset from MCR Base Address: <tt> 0x0024</tt> */
/**@} end of group mcr_registers */
/**
* @ingroup mcr_registers
* @defgroup MCR_RST MCR_RST
* @brief Reset Control Register
* @brief Reset control register 0.
* @{
*/
#define MXC_F_MCR_RST_LPTMR0_POS 0 /**< RST_LPTMR0 Position */
@ -115,12 +118,47 @@ typedef struct {
#define MXC_F_MCR_RST_LPUART0_POS 2 /**< RST_LPUART0 Position */
#define MXC_F_MCR_RST_LPUART0 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPUART0_POS)) /**< RST_LPUART0 Mask */
#define MXC_F_MCR_RST_RTC_POS 3 /**< RST_RTC Position */
#define MXC_F_MCR_RST_RTC ((uint32_t)(0x1UL << MXC_F_MCR_RST_RTC_POS)) /**< RST_RTC Mask */
/**@} end of group MCR_RST_Register */
/**
* @ingroup mcr_registers
* @defgroup MCR_LPPIOCTRL MCR_LPPIOCTRL
* @brief Low-power peripheral IO control.
* @{
*/
#define MXC_F_MCR_LPPIOCTRL_LPTMR0_I_POS 0 /**< LPPIOCTRL_LPTMR0_I Position */
#define MXC_F_MCR_LPPIOCTRL_LPTMR0_I ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR0_I_POS)) /**< LPPIOCTRL_LPTMR0_I Mask */
#define MXC_F_MCR_LPPIOCTRL_LPTMR0_O_POS 1 /**< LPPIOCTRL_LPTMR0_O Position */
#define MXC_F_MCR_LPPIOCTRL_LPTMR0_O ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR0_O_POS)) /**< LPPIOCTRL_LPTMR0_O Mask */
#define MXC_F_MCR_LPPIOCTRL_LPTMR1_I_POS 2 /**< LPPIOCTRL_LPTMR1_I Position */
#define MXC_F_MCR_LPPIOCTRL_LPTMR1_I ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR1_I_POS)) /**< LPPIOCTRL_LPTMR1_I Mask */
#define MXC_F_MCR_LPPIOCTRL_LPTMR1_O_POS 3 /**< LPPIOCTRL_LPTMR1_O Position */
#define MXC_F_MCR_LPPIOCTRL_LPTMR1_O ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR1_O_POS)) /**< LPPIOCTRL_LPTMR1_O Mask */
#define MXC_F_MCR_LPPIOCTRL_LPUART0_RX_POS 4 /**< LPPIOCTRL_LPUART0_RX Position */
#define MXC_F_MCR_LPPIOCTRL_LPUART0_RX ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_RX_POS)) /**< LPPIOCTRL_LPUART0_RX Mask */
#define MXC_F_MCR_LPPIOCTRL_LPUART0_TX_POS 5 /**< LPPIOCTRL_LPUART0_TX Position */
#define MXC_F_MCR_LPPIOCTRL_LPUART0_TX ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_TX_POS)) /**< LPPIOCTRL_LPUART0_TX Mask */
#define MXC_F_MCR_LPPIOCTRL_LPUART0_CTS_POS 6 /**< LPPIOCTRL_LPUART0_CTS Position */
#define MXC_F_MCR_LPPIOCTRL_LPUART0_CTS ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_CTS_POS)) /**< LPPIOCTRL_LPUART0_CTS Mask */
#define MXC_F_MCR_LPPIOCTRL_LPUART0_RTS_POS 7 /**< LPPIOCTRL_LPUART0_RTS Position */
#define MXC_F_MCR_LPPIOCTRL_LPUART0_RTS ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_RTS_POS)) /**< LPPIOCTRL_LPUART0_RTS Mask */
/**@} end of group MCR_LPPIOCTRL_Register */
/**
* @ingroup mcr_registers
* @defgroup MCR_CLKDIS MCR_CLKDIS
* @brief Low Power Peripheral Clock Disable.
* @brief Peripheral clock control register.
* @{
*/
#define MXC_F_MCR_CLKDIS_LPTMR0_POS 0 /**< CLKDIS_LPTMR0 Position */
@ -138,4 +176,4 @@ typedef struct {
}
#endif
#endif /* _MCR_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MCR_REGS_H_

26
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/pwrseq_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file pwrseq_regs.h
* @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _PWRSEQ_REGS_H_
#define _PWRSEQ_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_PWRSEQ_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_PWRSEQ_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -93,6 +93,9 @@ typedef struct {
__IO uint32_t lppwken; /**< <tt>\b 0x34:</tt> PWRSEQ LPPWKEN Register */
__I uint32_t rsv_0x38_0x3f[2];
__IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
__I uint32_t rsv_0x44;
__IO uint32_t gp0; /**< <tt>\b 0x48:</tt> PWRSEQ GP0 Register */
__IO uint32_t gp1; /**< <tt>\b 0x4C:</tt> PWRSEQ GP1 Register */
} mxc_pwrseq_regs_t;
/* Register offsets for module PWRSEQ */
@ -110,6 +113,8 @@ typedef struct {
#define MXC_R_PWRSEQ_LPPWKST ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0030</tt> */
#define MXC_R_PWRSEQ_LPPWKEN ((uint32_t)0x00000034UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0034</tt> */
#define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */
#define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0048</tt> */
#define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x004C</tt> */
/**@} end of group pwrseq_registers */
/**
@ -178,11 +183,8 @@ typedef struct {
#define MXC_F_PWRSEQ_LPCN_ERTCO_EN_POS 29 /**< LPCN_ERTCO_EN Position */
#define MXC_F_PWRSEQ_LPCN_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_ERTCO_EN_POS)) /**< LPCN_ERTCO_EN Mask */
#define MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS 30 /**< LPCN_TM_LPMODE Position */
#define MXC_F_PWRSEQ_LPCN_TM_LPMODE ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS)) /**< LPCN_TM_LPMODE Mask */
#define MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS 31 /**< LPCN_TM_PWRSEQ Position */
#define MXC_F_PWRSEQ_LPCN_TM_PWRSEQ ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS)) /**< LPCN_TM_PWRSEQ Mask */
#define MXC_F_PWRSEQ_LPCN_ERTCO_PD_POS 31 /**< LPCN_ERTCO_PD Position */
#define MXC_F_PWRSEQ_LPCN_ERTCO_PD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_ERTCO_PD_POS)) /**< LPCN_ERTCO_PD Mask */
/**@} end of group PWRSEQ_LPCN_Register */
@ -268,4 +270,4 @@ typedef struct {
}
#endif
#endif /* _PWRSEQ_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_PWRSEQ_REGS_H_

14
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/rtc_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file rtc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _RTC_REGS_H_
#define _RTC_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_RTC_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_RTC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -238,4 +238,4 @@ typedef struct {
}
#endif
#endif /* _RTC_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_RTC_REGS_H_

14
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/sir_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file sir_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _SIR_REGS_H_
#define _SIR_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SIR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SIR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -129,4 +129,4 @@ typedef struct {
}
#endif
#endif /* _SIR_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SIR_REGS_H_

14
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/spi_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file spi_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _SPI_REGS_H_
#define _SPI_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SPI_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SPI_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -480,4 +480,4 @@ typedef struct {
}
#endif
#endif /* _SPI_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SPI_REGS_H_

13
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/system_max32670.h
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,11 +29,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
******************************************************************************/
#ifndef _SYSTEM_MAX32670_H_
#define _SYSTEM_MAX32670_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SYSTEM_MAX32670_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SYSTEM_MAX32670_H_
#ifdef __cplusplus
extern "C" {
@ -53,7 +52,7 @@ extern "C" {
/* NOTE: EXTCLK needs to be defined by user based on the clock they supply */
#ifndef EXTCLK_FREQ
#define EXTCLK_FREQ 75000000
#define EXTCLK_FREQ 12500000
#endif
/* NOTE: This is the nominal value for INRO. The actual value may vary from chip to chip.
@ -111,4 +110,4 @@ void SystemCoreClockUpdate(void);
}
#endif
#endif /* _SYSTEM_MAX32670_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SYSTEM_MAX32670_H_

14
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file tmr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _TMR_REGS_H_
#define _TMR_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_TMR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_TMR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -438,4 +438,4 @@ typedef struct {
}
#endif
#endif /* _TMR_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_TMR_REGS_H_

44
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/trng_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file trng_regs.h
* @brief Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _TRNG_REGS_H_
#define _TRNG_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_TRNG_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_TRNG_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -84,7 +84,7 @@ extern "C" {
*/
typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> TRNG CTRL Register */
__I uint32_t status; /**< <tt>\b 0x04:</tt> TRNG STATUS Register */
__IO uint32_t status; /**< <tt>\b 0x04:</tt> TRNG STATUS Register */
__I uint32_t data; /**< <tt>\b 0x08:</tt> TRNG DATA Register */
} mxc_trng_regs_t;
@ -106,11 +106,20 @@ typedef struct {
* @brief TRNG Control Register.
* @{
*/
#define MXC_F_TRNG_CTRL_ODHT_POS 0 /**< CTRL_ODHT Position */
#define MXC_F_TRNG_CTRL_ODHT ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_ODHT_POS)) /**< CTRL_ODHT Mask */
#define MXC_F_TRNG_CTRL_RND_IE_POS 1 /**< CTRL_RND_IE Position */
#define MXC_F_TRNG_CTRL_RND_IE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_RND_IE_POS)) /**< CTRL_RND_IE Mask */
#define MXC_F_TRNG_CTRL_KEYGEN_POS 3 /**< CTRL_KEYGEN Position */
#define MXC_F_TRNG_CTRL_KEYGEN ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_KEYGEN_POS)) /**< CTRL_KEYGEN Mask */
#define MXC_F_TRNG_CTRL_HEALTH_EN_POS 2 /**< CTRL_HEALTH_EN Position */
#define MXC_F_TRNG_CTRL_HEALTH_EN ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_HEALTH_EN_POS)) /**< CTRL_HEALTH_EN Mask */
#define MXC_F_TRNG_CTRL_AESKG_USR_POS 3 /**< CTRL_AESKG_USR Position */
#define MXC_F_TRNG_CTRL_AESKG_USR ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_AESKG_USR_POS)) /**< CTRL_AESKG_USR Mask */
#define MXC_F_TRNG_CTRL_AESKG_SYS_POS 4 /**< CTRL_AESKG_SYS Position */
#define MXC_F_TRNG_CTRL_AESKG_SYS ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_AESKG_SYS_POS)) /**< CTRL_AESKG_SYS Mask */
#define MXC_F_TRNG_CTRL_KEYWIPE_POS 15 /**< CTRL_KEYWIPE Position */
#define MXC_F_TRNG_CTRL_KEYWIPE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_KEYWIPE_POS)) /**< CTRL_KEYWIPE Mask */
@ -127,6 +136,21 @@ typedef struct {
#define MXC_F_TRNG_STATUS_RDY_POS 0 /**< STATUS_RDY Position */
#define MXC_F_TRNG_STATUS_RDY ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_RDY_POS)) /**< STATUS_RDY Mask */
#define MXC_F_TRNG_STATUS_ODHT_POS 1 /**< STATUS_ODHT Position */
#define MXC_F_TRNG_STATUS_ODHT ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ODHT_POS)) /**< STATUS_ODHT Mask */
#define MXC_F_TRNG_STATUS_HT_POS 2 /**< STATUS_HT Position */
#define MXC_F_TRNG_STATUS_HT ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_HT_POS)) /**< STATUS_HT Mask */
#define MXC_F_TRNG_STATUS_SRCFAIL_POS 3 /**< STATUS_SRCFAIL Position */
#define MXC_F_TRNG_STATUS_SRCFAIL ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_SRCFAIL_POS)) /**< STATUS_SRCFAIL Mask */
#define MXC_F_TRNG_STATUS_AESKGD_POS 4 /**< STATUS_AESKGD Position */
#define MXC_F_TRNG_STATUS_AESKGD ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_AESKGD_POS)) /**< STATUS_AESKGD Mask */
#define MXC_F_TRNG_STATUS_LD_CNT_POS 24 /**< STATUS_LD_CNT Position */
#define MXC_F_TRNG_STATUS_LD_CNT ((uint32_t)(0xFFUL << MXC_F_TRNG_STATUS_LD_CNT_POS)) /**< STATUS_LD_CNT Mask */
/**@} end of group TRNG_STATUS_Register */
/**
@ -145,4 +169,4 @@ typedef struct {
}
#endif
#endif /* _TRNG_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_TRNG_REGS_H_

14
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/uart_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file uart_regs.h
* @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _UART_REGS_H_
#define _UART_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_UART_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_UART_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -400,4 +400,4 @@ typedef struct {
}
#endif
#endif /* _UART_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_UART_REGS_H_

14
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/wdt_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file wdt_regs.h
* @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _WDT_REGS_H_
#define _WDT_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_WDT_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_WDT_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -321,4 +321,4 @@ typedef struct {
}
#endif
#endif /* _WDT_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_WDT_REGS_H_

17
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,6 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
******************************************************************************/
#include <string.h>
@ -37,9 +36,9 @@
#include <stdlib.h>
#include "max32670.h"
#include "gcr_regs.h"
#include "pwrseq_regs.h"
#include "mxc_sys.h"
uint32_t SystemCoreClock = HIRC_FREQ;
__weak void SystemCoreClockUpdate(void)
@ -48,8 +47,7 @@ __weak void SystemCoreClockUpdate(void)
// Get the clock source and frequency
clk_src = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL);
switch (clk_src)
{
switch (clk_src) {
case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK:
base_freq = EXTCLK_FREQ;
break;
@ -75,9 +73,9 @@ __weak void SystemCoreClockUpdate(void)
break;
}
// Get the clock divider
if (clk_src == MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO)
{
base_freq = base_freq >> ((MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IPO_DIV)>> MXC_F_GCR_CLKCTRL_IPO_DIV_POS);
if (clk_src == MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO) {
base_freq = base_freq >> ((MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IPO_DIV) >>
MXC_F_GCR_CLKCTRL_IPO_DIV_POS);
}
div = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_DIV) >> MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS;
@ -109,7 +107,6 @@ __weak int Board_Init(void)
__weak void low_level_init(void)
{
/* Do nothing */
return;
}
/* This function is called just before control is transferred to main().

17
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/crc.h
View File

@ -3,8 +3,8 @@
* @brief cyclic redundancy check driver.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,10 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef _CRC_H_
#define _CRC_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_CRC_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_CRC_H_
/***** Includes *****/
#include "crc_regs.h"
@ -67,10 +67,7 @@ typedef struct _mxc_crc_req_t {
* @brief CRC data bit order
*
*/
typedef enum {
CRC_LSB_FIRST,
CRC_MSB_FIRST
} mxc_crc_bitorder_t;
typedef enum { CRC_LSB_FIRST, CRC_MSB_FIRST } mxc_crc_bitorder_t;
/***** Function Prototypes *****/
@ -182,4 +179,4 @@ int MXC_CRC_ComputeAsync (mxc_crc_req_t* req);
#endif
/**@} end of group crc */
#endif /* _CRC_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_CRC_H_

42
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/dma.h
View File

@ -3,8 +3,8 @@
* @brief Direct Memory Access (DMA) driver function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,10 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef _DMA_H_
#define _DMA_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_DMA_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_DMA_H_
/* **** Includes **** */
#include <stdbool.h>
@ -69,31 +69,40 @@ typedef enum {
/** @brief DMA request select */
typedef enum {
MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection
MXC_DMA_REQUEST_MEMTOMEM =
MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection
MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CTRL_REQUEST_SPI0RX, ///< SPI0 Receive DMA Request Selection
MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CTRL_REQUEST_SPI1RX, ///< SPI1 Receive DMA Request Selection
MXC_DMA_REQUEST_SPI2RX = MXC_S_DMA_CTRL_REQUEST_SPI2RX, ///< SPI2 Receive DMA Request Selection
MXC_DMA_REQUEST_UART0RX = MXC_S_DMA_CTRL_REQUEST_UART0RX, ///< UART0 Receive DMA Request Selection
MXC_DMA_REQUEST_UART1RX = MXC_S_DMA_CTRL_REQUEST_UART1RX, ///< UART1 Receive DMA Request Selection
MXC_DMA_REQUEST_UART0RX =
MXC_S_DMA_CTRL_REQUEST_UART0RX, ///< UART0 Receive DMA Request Selection
MXC_DMA_REQUEST_UART1RX =
MXC_S_DMA_CTRL_REQUEST_UART1RX, ///< UART1 Receive DMA Request Selection
MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CTRL_REQUEST_I2C0RX, ///< I2C0 Receive DMA Request Selection
MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CTRL_REQUEST_I2C1RX, ///< I2C1 Receive DMA Request Selection
MXC_DMA_REQUEST_I2C2RX = MXC_S_DMA_CTRL_REQUEST_I2C2RX, ///< I2C2 Receive DMA Request Selection
MXC_DMA_REQUEST_UART2RX = MXC_S_DMA_CTRL_REQUEST_UART2RX, ///< UART2 Receive DMA Request Selection
MXC_DMA_REQUEST_UART2RX =
MXC_S_DMA_CTRL_REQUEST_UART2RX, ///< UART2 Receive DMA Request Selection
MXC_DMA_REQUEST_AESRX = MXC_S_DMA_CTRL_REQUEST_AESRX, ///< AES Receive DMA Request Selection
MXC_DMA_REQUEST_UART3RX = MXC_S_DMA_CTRL_REQUEST_UART3RX, ///< UART3 Receive DMA Request Selection
MXC_DMA_REQUEST_UART3RX =
MXC_S_DMA_CTRL_REQUEST_UART3RX, ///< UART3 Receive DMA Request Selection
MXC_DMA_REQUEST_I2SRX = MXC_S_DMA_CTRL_REQUEST_I2SRX, ///< I2S Receive DMA Request Selection
MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CTRL_REQUEST_SPI0TX, ///< SPI0 Transmit DMA Request Selection
MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CTRL_REQUEST_SPI1TX, ///< SPI1 Transmit DMA Request Selection
MXC_DMA_REQUEST_SPI2TX = MXC_S_DMA_CTRL_REQUEST_SPI2TX, ///< SPI2 Transmit DMA Request Selection
MXC_DMA_REQUEST_UART0TX = MXC_S_DMA_CTRL_REQUEST_UART0TX, ///< UART0 Transmit DMA Request Selection
MXC_DMA_REQUEST_UART1TX = MXC_S_DMA_CTRL_REQUEST_UART1TX, ///< UART1 Transmit DMA Request Selection
MXC_DMA_REQUEST_UART0TX =
MXC_S_DMA_CTRL_REQUEST_UART0TX, ///< UART0 Transmit DMA Request Selection
MXC_DMA_REQUEST_UART1TX =
MXC_S_DMA_CTRL_REQUEST_UART1TX, ///< UART1 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CTRL_REQUEST_I2C0TX, ///< I2C0 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CTRL_REQUEST_I2C1TX, ///< I2C1 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2C2TX = MXC_S_DMA_CTRL_REQUEST_I2C2TX, ///< I2C2 Transmit DMA Request Selection
MXC_DMA_REQUEST_CRCTX = MXC_S_DMA_CTRL_REQUEST_CRCTX, ///< CRC Transmit DMA Request Selection
MXC_DMA_REQUEST_UART2TX = MXC_S_DMA_CTRL_REQUEST_UART2TX, ///< UART2 Transmit DMA Request Selection
MXC_DMA_REQUEST_UART2TX =
MXC_S_DMA_CTRL_REQUEST_UART2TX, ///< UART2 Transmit DMA Request Selection
MXC_DMA_REQUEST_AESTX = MXC_S_DMA_CTRL_REQUEST_AESTX, ///< AES Transmit DMA Request Selection
MXC_DMA_REQUEST_UART3TX = MXC_S_DMA_CTRL_REQUEST_UART3TX, ///< UART3 Transmit DMA Request Selection
MXC_DMA_REQUEST_UART3TX =
MXC_S_DMA_CTRL_REQUEST_UART3TX, ///< UART3 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2STX = MXC_S_DMA_CTRL_REQUEST_I2STX, ///< I2S Transmit DMA Request Selection
} mxc_dma_reqsel_t;
@ -424,7 +433,8 @@ int MXC_DMA_MemCpy (void* dest, void* src, int len, mxc_dma_complete_cb_t callba
*
* @return see \ref MXC_Error_Codes
*/
int MXC_DMA_DoTransfer (mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback);
int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst,
mxc_dma_trans_chain_t callback);
/**
* For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver
*/
@ -434,4 +444,4 @@ int MXC_DMA_DoTransfer (mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, m
}
#endif
#endif /* _DMA_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_DMA_H_

34
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/flc.h
View File

@ -4,8 +4,8 @@
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -35,10 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef _FLC_H_
#define _FLC_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_FLC_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_FLC_H_
/* **** Includes **** */
#include "flc_regs.h"
@ -60,7 +60,7 @@ extern "C" {
#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1)
/// Calculate the address of a page in flash from the page number
#define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE))
#define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((uint32_t)page * MXC_FLASH_PAGE_SIZE))
/***** Function Prototypes *****/
@ -179,10 +179,30 @@ int MXC_FLC_UnlockInfoBlock (uint32_t address);
*/
int MXC_FLC_LockInfoBlock(uint32_t address);
/**
* @brief Blocks write operations to the flash page associated with the 'address' argument
* @note Flash pages cannot be unblocked except for on POR and external resets
*
* @param address Absolute address located anywhere in the flash page to be locked (does not need to be word-aligned)
*
* @return #E_NO_ERROR If function is successful.
*/
int MXC_FLC_BlockPageWrite(uint32_t address);
/**
* @brief Blocks read operations from the flash page associated with the 'address' argument
* @note Flash pages cannot be unblocked except for on POR and external resets
*
* @param address Absolute address located anywhere in the flash page to be locked (does not need to be word-aligned)
*
* @return #E_NO_ERROR If function is successful.
*/
int MXC_FLC_BlockPageRead(uint32_t address);
/**@} end of group flc */
#ifdef __cplusplus
}
#endif
#endif /* _FLC_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_FLC_H_

15
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/gpio.h
View File

@ -3,8 +3,8 @@
* @brief General-Purpose Input/Output (GPIO) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _GPIO_H_
#define _GPIO_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_GPIO_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_GPIO_H_
/* **** Includes **** */
#include "gpio_regs.h"
@ -300,7 +300,8 @@ void MXC_GPIO_ClearFlags (mxc_gpio_regs_t* port, uint32_t flags);
* @param cbdata The parameter to be passed to the callback function, #callback_fn, when an interrupt occurs.
*
*/
void MXC_GPIO_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, void *cbdata);
void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback,
void *cbdata);
/**
* @brief GPIO IRQ Handler. @note If a callback is registered for a given
@ -328,4 +329,4 @@ int MXC_GPIO_SetVSSEL (mxc_gpio_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t m
}
#endif
#endif /* _GPIO_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_GPIO_H_

117
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/i2s.h
View File

@ -3,8 +3,8 @@
* @brief I2S (Inter-Integrated Sound) driver function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,10 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef _I2S_H_
#define _I2S_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_I2S_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_I2S_H_
/* **** Includes **** */
#include "mxc_sys.h"
@ -58,27 +58,19 @@ extern "C" {
/** @brief I2S stereo mode select */
typedef enum {
MXC_I2S_STEREO = 0,
MXC_I2S_MONO_LEFT_CH = 2,
MXC_I2S_MONO_RIGHT_CH = 3
} mxc_i2s_stereo_t;
/** @brief I2S polarity configuration */
typedef enum {
MXC_I2S_POL_NORMAL,
MXC_I2S_POL_INVERSE
} mxc_i2s_polarity_t;
typedef enum { MXC_I2S_POL_NORMAL, MXC_I2S_POL_INVERSE } mxc_i2s_polarity_t;
/** @brief I2S transaction bit order */
typedef enum {
MXC_I2S_MSB_FIRST,
MXC_I2S_LSB_FIRST
} mxc_i2s_bitorder_t;
typedef enum { MXC_I2S_MSB_FIRST, MXC_I2S_LSB_FIRST } mxc_i2s_bitorder_t;
/** @brief I2S transaction justify order */
typedef enum {
MXC_I2S_MSB_JUSTIFY,
MXC_I2S_LSB_JUSTIFY
} mxc_i2s_justify_t;
typedef enum { MXC_I2S_MSB_JUSTIFY, MXC_I2S_LSB_JUSTIFY } mxc_i2s_justify_t;
/** @brief I2S transaction word size */
typedef enum {
@ -182,12 +174,63 @@ int MXC_I2S_SetRXThreshold(uint8_t threshold);
*/
int MXC_I2S_SetFrequency(mxc_i2s_ch_mode_t mode, uint16_t clkdiv);
/**
* @brief Sets the clock divider to provide the desired sampling rate.
*
* @param smpl_rate The desired sampling rate.
* @param smpl_sz The size of each sample.
*
* @return If successful, the actual sampling rate. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_SetSampleRate(uint32_t smpl_rate, mxc_i2s_wsize_t smpl_sz);
/**
* @brief Returns the current sampling rate.
*
* @return If successful, sampling rate. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_GetSampleRate(void);
/**
* @brief Calculates the value of the clock divider that should be used in order to get the desired sampling frequency.
*
* @param smpl_rate Desired sampling rate.
* @param smple_sz The size of each I2S word.
*
* @return If successful, the clock divider value. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_CalculateClockDiv(uint32_t smpl_rate, mxc_i2s_wsize_t smpl_sz);
/**
* @brief Flush I2S FIFO
*
*/
void MXC_I2S_Flush(void);
/**
* @brief Fill I2S FIFO with data to transmit
*
* @param txData Pointer to base address of the data buffer
* @param wordSize Size of the data samples
* @param len Number of samples in the data buffer
* @param smpl_cnt Number of samples already sent from the data buffer
*
* @returns If successful the number of samples successfuly written to the FIFO. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_FillTXFIFO(void *txData, mxc_i2s_wsize_t wordSize, int len, int smpl_cnt);
/**
* @brief Read audio samples from I2S receive buffer
*
* @param rxData Pointer to data buffer that will store the audio samples
* @param wordSize Size of the samples in the FIFO
* @param len Number of samples to read
* @param smpl_cnt Number of samples already received in the data buffer
*
* @returns If successful, the number of samples actually read from the buffer. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_ReadRXFIFO(void *rxData, mxc_i2s_wsize_t wordSize, int len, int smpl_cnt);
/**
* @brief Enable Interrupts
*
@ -216,21 +259,48 @@ int MXC_I2S_GetFlags(void);
*/
void MXC_I2S_ClearFlags(uint32_t flags);
/**
* @brief Performs a blocking I2S transaction.
*
* @param Pointer to transaction request structure
*
* @returns If successful, E_NO_ERROR. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_Transaction(mxc_i2s_req_t *i2s_req);
/**
* @brief Sets up an asynchronous I2S transaction.
*
* @param Pointer to transaction request structure
*
* @returns If successful, E_NO_ERROR. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_TransactionAsync(mxc_i2s_req_t *i2s_req);
/**
* @brief Configure TX DMA transaction
*
* @param src_addr source address of data
* @param len length od the data to be transmitted
*
* @return If successful, the DMA channel number used for the request. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes.
*/
void MXC_I2S_TXDMAConfig(void *src_addr, int len);
int MXC_I2S_TXDMAConfig(void *src_addr, int len);
/**
* @brief Configure RX DMA transaction
*
* @param dest_addr destination address
* @param len length of the data to be received
*
* @return If successful, the DMA channel number used for the request. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes.
*/
void MXC_I2S_RXDMAConfig(void *dest_addr, int len);
int MXC_I2S_RXDMAConfig(void *dest_addr, int len);
/**
* @brief Handler for asynchronous I2S transactions.
*/
void MXC_I2S_Handler(void);
/**
* @brief Set the callback function pointer for I2S DMA transactions
@ -239,8 +309,15 @@ void MXC_I2S_RXDMAConfig(void *dest_addr, int len);
*/
void MXC_I2S_RegisterDMACallback(void (*callback)(int, int));
/**
* @brief Sets the callback function for asynchronous I2S transactions
*
* @param callback Function pointer to the asynchronous transaction callback
*/
void MXC_I2S_RegisterAsyncCallback(void (*callback)(int));
#ifdef __cplusplus
}
#endif
#endif /* _I2S_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_I2S_H_

12
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/icc.h
View File

@ -3,8 +3,8 @@
* @brief Instruction Controller Cache(ICC) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _ICC_H_
#define _ICC_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_ICC_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_ICC_H_
/* **** Includes **** */
#include <stdint.h>
@ -91,4 +91,4 @@ void MXC_ICC_Flush (void);
}
#endif
#endif /* _ICC_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_ICC_H_

28
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/lp.h
View File

@ -3,8 +3,8 @@
* @brief Low Power(LP) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _LP_H_
#define _LP_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_LP_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_LP_H_
/* **** Includes **** */
#include <stdint.h>
@ -62,11 +62,7 @@ extern "C" {
* @brief Enumeration type for voltage selection
*
*/
typedef enum {
MXC_LP_V0_9 = 0,
MXC_LP_V1_0,
MXC_LP_V1_1
} mxc_lp_ovr_t;
typedef enum { MXC_LP_V0_9 = 0, MXC_LP_V1_0, MXC_LP_V1_1 } mxc_lp_ovr_t;
/**
* @brief Enumeration type for PM Mode
@ -244,6 +240,16 @@ void MXC_LP_EnableTimerWakeup(mxc_tmr_regs_t* tmr);
*/
void MXC_LP_DisableTimerWakeup(mxc_tmr_regs_t *tmr);
/**
* @brief Enables LPUART0 to wake up the device from any low power mode.
*/
void MXC_LP_EnableUARTWakeup(void);
/**
* @brief Disables LPUART0 from waking up the device.
*/
void MXC_LP_DisableUARTWakeup(void);
/**
* @brief Enables the USB to wake up the device from any low power mode.
*/
@ -538,4 +544,4 @@ void MXC_LP_ROMPowerUp (void);
}
#endif
#endif /* _LP_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_LP_H_

17
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_aes.h
View File

@ -1,10 +1,10 @@
/**
* @file
* @brief Trust Protection Unit driver.
* @brief AES driver.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,14 +34,14 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef _MXC_AES_H_
#define _MXC_AES_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_AES_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_AES_H_
/***** Includes *****/
#include "aes_regs.h"
#include "aes_key_regs.h"
#include "aeskeys_regs.h"
#ifdef __cplusplus
extern "C" {
@ -309,10 +309,9 @@ void MXC_AES_CopyPORKeyToKeyRegisters(mxc_aes_keys_t len);
*/
int MXC_AES_HasPORKey();
#ifdef __cplusplus
}
#endif
/**@} end of group aes */
#endif /* _MXC_AES_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_AES_H_

16
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_assert.h
View File

@ -3,8 +3,8 @@
* @brief Assertion checks for debugging.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,15 +34,14 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _MXC_ASSERT_H_
#define _MXC_ASSERT_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_ASSERT_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_ASSERT_H_
/* **** Includes **** */
#ifdef __cplusplus
extern "C" {
#endif
@ -66,8 +65,7 @@ extern "C" {
* defined.
*/
#define MXC_ASSERT(expr) \
if (!(expr)) \
{ \
if (!(expr)) { \
mxc_assert(#expr, __FILE__, __LINE__); \
}
/**
@ -106,4 +104,4 @@ void mxc_assert (const char *expr, const char *file, int line);
}
#endif
#endif /* _MXC_ASSERT_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_ASSERT_H_

28
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_delay.h
View File

@ -3,8 +3,8 @@
* @brief Asynchronous delay routines based on the SysTick Timer.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,17 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _DELAY_H_
#define _DELAY_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_DELAY_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_DELAY_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @ingroup devicelibs
@ -54,7 +60,7 @@
* x = SEC(3) // 3 seconds -> x = 3,000,000
* \endcode
*/
#define MXC_DELAY_SEC(s) (((unsigned long)s) * 1000000UL)
#define MXC_DELAY_SEC(s) (((uint32_t)s) * 1000000UL)
/**
* Macro used to specify a microsecond timing parameter in milliseconds.
* \code
@ -88,7 +94,7 @@ typedef void (*mxc_delay_complete_t) (int result);
* @param us microseconds to delay
* @return #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful.
*/
int MXC_Delay (unsigned long us);
int MXC_Delay(uint32_t us);
/**
* @brief Starts a non-blocking delay for the specified number of
@ -103,7 +109,7 @@ int MXC_Delay (unsigned long us);
* @return #E_NO_ERROR if no errors, #E_BUSY if currently servicing another
* delay request.
*/
int MXC_DelayAsync (unsigned long us, mxc_delay_complete_t callback);
int MXC_DelayAsync(uint32_t us, mxc_delay_complete_t callback);
/**
* @brief Returns the status of a non-blocking delay request
@ -127,4 +133,8 @@ void MXC_DelayHandler (void);
/**@} end of group MXC_delay */
#endif /* _DELAY_H_ */
#ifdef __cplusplus
}
#endif
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_DELAY_H_

10
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_device.h
View File

@ -3,8 +3,8 @@
* @brief Device specific header file.
*/
/*******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -36,8 +36,8 @@
*
******************************************************************************/
#ifndef _MXC_DEVICE_H_
#define _MXC_DEVICE_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_DEVICE_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_DEVICE_H_
#include "max32670.h"
#include "mxc_errors.h"
@ -73,4 +73,4 @@
#endif /* if(TARGET_REV == ...) */
#endif /* _MXC_DEVICE_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_DEVICE_H_

14
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_errors.h
View File

@ -3,8 +3,8 @@
* @brief List of common error return codes for Maxim Integrated libraries.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _MXC_ERRORS_H_
#define _MXC_ERRORS_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_ERRORS_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_ERRORS_H_
/**
* @ingroup syscfg
@ -87,6 +87,8 @@
#define E_ABORT -16
/** The requested operation is not supported */
#define E_NOT_SUPPORTED -17
/** The requested operation is failed */
#define E_FAIL -255
/**@} end of MXC_Error_Codes group */
#endif /* _MXC_ERRORS_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_ERRORS_H_

38
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_i2c.h
View File

@ -3,8 +3,8 @@
* @brief Inter-integrated circuit (I2C) communications interface driver.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _MXC_I2C_H_
#define _MXC_I2C_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_I2C_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_I2C_H_
#include <stdint.h>
#include "mxc_sys.h"
@ -165,8 +165,8 @@ typedef enum {
* non-zero to not acknowledge. The return value is ignored for all
* other event types.
*/
typedef int (*mxc_i2c_slave_handler_t) (mxc_i2c_regs_t* i2c,
mxc_i2c_slave_event_t event, void* data);
typedef int (*mxc_i2c_slave_handler_t)(mxc_i2c_regs_t *i2c, mxc_i2c_slave_event_t event,
void *data);
/***** Function Prototypes *****/
@ -360,8 +360,7 @@ int MXC_I2C_ReadByte (mxc_i2c_regs_t* i2c, unsigned char* byte, int ack);
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_ReadByteInteractive (mxc_i2c_regs_t* i2c, unsigned char* byte,
mxc_i2c_getAck_t getAck);
int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t *i2c, unsigned char *byte, mxc_i2c_getAck_t getAck);
/**
* @brief Write multiple bytes to the I2C bus.
@ -399,8 +398,7 @@ int MXC_I2C_Write (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len)
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_Read (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len,
int ack);
int MXC_I2C_Read(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack);
/**
* @brief Unloads bytes from the receive FIFO.
@ -411,8 +409,7 @@ int MXC_I2C_Read (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len,
*
* @return The number of bytes actually read.
*/
int MXC_I2C_ReadRXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes,
unsigned int len);
int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len);
/**
* @brief Unloads bytes from the receive FIFO using DMA for longer reads.
@ -426,8 +423,8 @@ int MXC_I2C_ReadRXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes,
*
* @return See \ref MXC_Error_Codes for a list of return values.
*/
int MXC_I2C_ReadRXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes,
unsigned int len, mxc_i2c_dma_complete_cb_t callback);
int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len,
mxc_i2c_dma_complete_cb_t callback);
/**
* @brief Get the number of bytes currently available in the receive FIFO.
@ -447,8 +444,7 @@ int MXC_I2C_GetRXFIFOAvailable (mxc_i2c_regs_t* i2c);
*
* @return The number of bytes actually written.
*/
int MXC_I2C_WriteTXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes,
unsigned int len);
int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len);
/**
* @brief Loads bytes into the transmit FIFO using DMA for longer writes.
@ -461,8 +457,8 @@ int MXC_I2C_WriteTXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes,
*
* @return See \ref MXC_Error_Codes for a list of return values
*/
int MXC_I2C_WriteTXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes,
unsigned int len, mxc_i2c_dma_complete_cb_t callback);
int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len,
mxc_i2c_dma_complete_cb_t callback);
/**
* @brief Get the amount of free space available in the transmit FIFO.
@ -868,12 +864,10 @@ void MXC_I2C_AsyncHandler (mxc_i2c_regs_t* i2c);
*/
void MXC_I2C_DMACallback(int ch, int error);
/**@} end of group i2c */
#ifdef __cplusplus
}
#endif
#endif /* _MXC_I2C_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_I2C_H_

25
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_lock.h
View File

@ -3,8 +3,8 @@
* @brief Exclusive access lock utility functions.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,17 +34,15 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _MXC_LOCK_H_
#define _MXC_LOCK_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_LOCK_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_LOCK_H_
// To enable disable this module
#define USE_LOCK_IN_DRIVERS 0
#if USE_LOCK_IN_DRIVERS
/* **** Includes **** */
#include "mxc_device.h"
@ -52,6 +50,8 @@
extern "C" {
#endif
#if USE_LOCK_IN_DRIVERS
/**
* @ingroup syscfg
* @defgroup mxc_lock_utilities Exclusive Access Locks
@ -89,11 +89,6 @@ void MXC_FreeLock (uint32_t *lock);
/**@} end of group mxc_lock_utilities */
#ifdef __cplusplus
}
#endif
#else // USE_LOCK_IN_DRIVERS
#define MXC_GetLock(x, y) E_NO_ERROR
@ -101,4 +96,8 @@ void MXC_FreeLock (uint32_t *lock);
#endif // USE_LOCK_IN_DRIVERS
#endif /* _MXC_LOCK_H_ */
#ifdef __cplusplus
}
#endif
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_LOCK_H_

23
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_pins.h
View File

@ -4,7 +4,7 @@
*/
/******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,30 +34,25 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
#ifndef _MXC_PINS_H_
#define _MXC_PINS_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_PINS_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_PINS_H_
#include "gpio.h"
typedef enum {
MAP_A,
MAP_B,
MAP_C
} sys_map_t;
typedef enum { MAP_A, MAP_B, MAP_C } sys_map_t;
/***** Global Variables *****/
// Predefined GPIO Configurations
extern const mxc_gpio_cfg_t gpio_cfg_extclk;
extern const mxc_gpio_cfg_t gpio_cfg_lpextclk;
extern const mxc_gpio_cfg_t gpio_cfg_hfextclk;
extern const mxc_gpio_cfg_t gpio_cfg_i2c0;
extern const mxc_gpio_cfg_t gpio_cfg_i2c1;
extern const mxc_gpio_cfg_t gpio_cfg_i2c2;
extern const mxc_gpio_cfg_t gpio_cfg_i2c2b;
extern const mxc_gpio_cfg_t gpio_cfg_i2c2c;
extern const mxc_gpio_cfg_t gpio_cfg_uart0a;
extern const mxc_gpio_cfg_t gpio_cfg_uart0a_flow;
extern const mxc_gpio_cfg_t gpio_cfg_uart0a_flow_disable;
@ -80,7 +75,6 @@ extern const mxc_gpio_cfg_t gpio_cfg_uart3;
extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow;
extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow_disable;
extern const mxc_gpio_cfg_t gpio_cfg_spi0;
// NOTE: SPI1 definied here with SS1 only, SS0 is on port0 by itself.
extern const mxc_gpio_cfg_t gpio_cfg_spi1;
@ -112,5 +106,4 @@ extern const mxc_gpio_cfg_t gpio_cfg_mon_lc2;
extern const mxc_gpio_cfg_t gpio_cfg_cmd_rs_lc2;
extern const mxc_gpio_cfg_t gpio_cfg_chrg_lc2;
#endif /* _MXC_PINS_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_PINS_H_

20
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_spi.h
View File

@ -3,8 +3,8 @@
* @brief Serial Peripheral Interface (SPI) communications driver.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,9 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#ifndef _SPI_H_
#define _SPI_H_
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_SPI_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_SPI_H_
/***** includes *******/
#include "spi_regs.h"
@ -250,7 +251,6 @@ int MXC_SPI_SetDataSize (mxc_spi_regs_t* spi, int dataSize);
*/
int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi);
/* ************************************************************************* */
/* Low-level functions */
/* ************************************************************************* */
@ -361,8 +361,7 @@ int MXC_SPI_AbortTransmission (mxc_spi_regs_t* spi);
*
* @return The number of bytes actually read.
*/
unsigned int MXC_SPI_ReadRXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes,
unsigned int len);
unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len);
/**
* @brief Get the number of bytes currently available in the receive FIFO.
@ -382,8 +381,7 @@ unsigned int MXC_SPI_GetRXFIFOAvailable (mxc_spi_regs_t* spi);
*
* @return The number of bytes actually written.
*/
unsigned int MXC_SPI_WriteTXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes,
unsigned int len);
unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len);
/**
* @brief Get the amount of free space available in the transmit FIFO.
@ -653,4 +651,4 @@ void MXC_SPI_AsyncHandler (mxc_spi_regs_t* spi);
}
#endif
#endif /* _PT_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_SPI_H_

183
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_sys.h
View File

@ -3,8 +3,8 @@
* @brief System level header file.
*/
/*******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -36,8 +36,8 @@
*
******************************************************************************/
#ifndef _MXC_MXC_SYS_H_
#define _MXC_MXC_SYS_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_SYS_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_SYS_H_
#include "mxc_device.h"
#include "gcr_regs.h"
@ -63,7 +63,6 @@ typedef enum {
MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */
MXC_SYS_RESET0_SPI2 = MXC_F_GCR_RST0_SPI2_POS, /**< Reset SPI2 */
MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */
MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */
MXC_SYS_RESET0_TRNG = MXC_F_GCR_RST0_TRNG_POS, /**< Reset TRNG */
MXC_SYS_RESET0_UART2 = MXC_F_GCR_RST0_UART2_POS, /**< Reset UART2 */
MXC_SYS_RESET0_SRST = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */
@ -72,46 +71,73 @@ typedef enum {
/* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */
MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */
MXC_SYS_RESET1_WDT1 = (MXC_F_GCR_RST1_WDT1_POS + 32), /**< Reset WDT1 */
MXC_SYS_RESET1_AES = (MXC_F_GCR_RST1_AES_POS + 32), /**< Reset WDT1 */
MXC_SYS_RESET1_CRC = (MXC_F_GCR_RST1_CRC_POS + 32), /**< Reset WDT1 */
MXC_SYS_RESET1_I2C2 = (MXC_F_GCR_RST1_I2C2_POS + 32), /**< Reset */
MXC_SYS_RESET1_I2S = (MXC_F_GCR_RST1_I2S_POS + 32), /**< Reset */
MXC_SYS_RESET1_AES = (MXC_F_GCR_RST1_AES_POS + 32), /**< Reset AES */
MXC_SYS_RESET1_CRC = (MXC_F_GCR_RST1_CRC_POS + 32), /**< Reset CRC */
MXC_SYS_RESET1_I2C2 = (MXC_F_GCR_RST1_I2C2_POS + 32), /**< Reset I2C2*/
MXC_SYS_RESET1_I2S = (MXC_F_GCR_RST1_I2S_POS + 32), /**< Reset I2S*/
/* LPGCR RESET Below this line we add 64 to separate LPGCR and GCR */
MXC_SYS_RESET_TMR4 = (MXC_F_MCR_RST_LPTMR0_POS + 64), /**< Reset TMR4 */
MXC_SYS_RESET_TMR5 = (MXC_F_MCR_RST_LPTMR1_POS + 64), /**< Reset TMR5 */
MXC_SYS_RESET_UART3 = (MXC_F_MCR_RST_LPUART0_POS + 64), /**< Reset UART3 */
MXC_SYS_RESET_RTC = (MXC_F_MCR_RST_RTC_POS + 64), /**< Reset RTC */
} mxc_sys_reset_t;
/** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */
typedef enum {
MXC_SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */
MXC_SYS_PERIPH_CLOCK_GPIO1 = MXC_F_GCR_PCLKDIS0_GPIO1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO1 clock */
MXC_SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PCLKDIS0_DMA_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */
MXC_SYS_PERIPH_CLOCK_SPI0 = MXC_F_GCR_PCLKDIS0_SPI0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI0 clock */
MXC_SYS_PERIPH_CLOCK_SPI1 = MXC_F_GCR_PCLKDIS0_SPI1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */
MXC_SYS_PERIPH_CLOCK_SPI2 = MXC_F_GCR_PCLKDIS0_SPI2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI2 clock */
MXC_SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PCLKDIS0_UART0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */
MXC_SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PCLKDIS0_UART1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */
MXC_SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PCLKDIS0_I2C0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */
MXC_SYS_PERIPH_CLOCK_TMR0 = MXC_F_GCR_PCLKDIS0_TMR0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T0 clock */
MXC_SYS_PERIPH_CLOCK_TMR1 = MXC_F_GCR_PCLKDIS0_TMR1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T1 clock */
MXC_SYS_PERIPH_CLOCK_TMR2 = MXC_F_GCR_PCLKDIS0_TMR2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T2 clock */
MXC_SYS_PERIPH_CLOCK_TMR3 = MXC_F_GCR_PCLKDIS0_TMR3_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T3 clock */
MXC_SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PCLKDIS0_I2C1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */
MXC_SYS_PERIPH_CLOCK_GPIO0 =
MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */
MXC_SYS_PERIPH_CLOCK_GPIO1 =
MXC_F_GCR_PCLKDIS0_GPIO1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO1 clock */
MXC_SYS_PERIPH_CLOCK_DMA =
MXC_F_GCR_PCLKDIS0_DMA_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */
MXC_SYS_PERIPH_CLOCK_SPI0 =
MXC_F_GCR_PCLKDIS0_SPI0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI0 clock */
MXC_SYS_PERIPH_CLOCK_SPI1 =
MXC_F_GCR_PCLKDIS0_SPI1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */
MXC_SYS_PERIPH_CLOCK_SPI2 =
MXC_F_GCR_PCLKDIS0_SPI2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI2 clock */
MXC_SYS_PERIPH_CLOCK_UART0 =
MXC_F_GCR_PCLKDIS0_UART0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */
MXC_SYS_PERIPH_CLOCK_UART1 =
MXC_F_GCR_PCLKDIS0_UART1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */
MXC_SYS_PERIPH_CLOCK_I2C0 =
MXC_F_GCR_PCLKDIS0_I2C0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */
MXC_SYS_PERIPH_CLOCK_TMR0 =
MXC_F_GCR_PCLKDIS0_TMR0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T0 clock */
MXC_SYS_PERIPH_CLOCK_TMR1 =
MXC_F_GCR_PCLKDIS0_TMR1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T1 clock */
MXC_SYS_PERIPH_CLOCK_TMR2 =
MXC_F_GCR_PCLKDIS0_TMR2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T2 clock */
MXC_SYS_PERIPH_CLOCK_TMR3 =
MXC_F_GCR_PCLKDIS0_TMR3_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T3 clock */
MXC_SYS_PERIPH_CLOCK_I2C1 =
MXC_F_GCR_PCLKDIS0_I2C1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */
/* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */
MXC_SYS_PERIPH_CLOCK_UART2 = (MXC_F_GCR_PCLKDIS1_UART2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_UART2 clock */
MXC_SYS_PERIPH_CLOCK_TRNG = (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_TRNG clock */
MXC_SYS_PERIPH_CLOCK_WDT0 = (MXC_F_GCR_PCLKDIS1_WWDT0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT0 clock */
MXC_SYS_PERIPH_CLOCK_WDT1 = (MXC_F_GCR_PCLKDIS1_WWDT1_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT1 clock */
MXC_SYS_PERIPH_CLOCK_ICACHE = (MXC_F_GCR_PCLKDIS1_ICC0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_ICACHE clock */
MXC_SYS_PERIPH_CLOCK_CRC = (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CRC clock */
MXC_SYS_PERIPH_CLOCK_AES = (MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_AES clock */
MXC_SYS_PERIPH_CLOCK_I2C2 = (MXC_F_GCR_PCLKDIS1_I2C2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2C2 clock */
MXC_SYS_PERIPH_CLOCK_I2S = (MXC_F_GCR_PCLKDIS1_I2S_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */
MXC_SYS_PERIPH_CLOCK_UART2 =
(MXC_F_GCR_PCLKDIS1_UART2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_UART2 clock */
MXC_SYS_PERIPH_CLOCK_TRNG =
(MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_TRNG clock */
MXC_SYS_PERIPH_CLOCK_WDT0 =
(MXC_F_GCR_PCLKDIS1_WWDT0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT0 clock */
MXC_SYS_PERIPH_CLOCK_WDT1 =
(MXC_F_GCR_PCLKDIS1_WWDT1_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT1 clock */
MXC_SYS_PERIPH_CLOCK_ICACHE =
(MXC_F_GCR_PCLKDIS1_ICC0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_ICACHE clock */
MXC_SYS_PERIPH_CLOCK_CRC =
(MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CRC clock */
MXC_SYS_PERIPH_CLOCK_AES =
(MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_AES clock */
MXC_SYS_PERIPH_CLOCK_I2C2 =
(MXC_F_GCR_PCLKDIS1_I2C2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2C2 clock */
MXC_SYS_PERIPH_CLOCK_I2S =
(MXC_F_GCR_PCLKDIS1_I2S_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */
/* LPGCR PCLKDIS Below this line we add 64 to seperate GCR and LPGCR registers */
MXC_SYS_PERIPH_CLOCK_TMR4 = (MXC_F_MCR_CLKDIS_LPTMR0_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR4 clock */
MXC_SYS_PERIPH_CLOCK_TMR5 = (MXC_F_MCR_CLKDIS_LPTMR1_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR5 clock */
MXC_SYS_PERIPH_CLOCK_UART3 = (MXC_F_MCR_CLKDIS_LPUART0_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_UART3 clock */
MXC_SYS_PERIPH_CLOCK_TMR4 =
(MXC_F_MCR_CLKDIS_LPTMR0_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR4 clock */
MXC_SYS_PERIPH_CLOCK_TMR5 =
(MXC_F_MCR_CLKDIS_LPTMR1_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR5 clock */
MXC_SYS_PERIPH_CLOCK_UART3 =
(MXC_F_MCR_CLKDIS_LPUART0_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_UART3 clock */
} mxc_sys_periph_clock_t;
/** @brief Enumeration to select System Clock source */
@ -128,6 +154,91 @@ typedef enum {
/***** Function Prototypes *****/
typedef struct {
int ie_status;
int in_critical;
} mxc_crit_state_t;
static mxc_crit_state_t _state = { .ie_status = (int)0xFFFFFFFF, .in_critical = 0 };
static inline void _mxc_crit_get_state()
{
#ifdef __CORTEX_M
/*
On ARM M the 0th bit of the Priority Mask register indicates
whether interrupts are enabled or not.
0 = enabled
1 = disabled
*/
uint32_t primask = __get_PRIMASK();
_state.ie_status = (primask == 0);
#endif
#ifdef __riscv
/*
On RISC-V bit position 3 (Machine Interrupt Enable) of the
mstatus register indicates whether interrupts are enabled.
0 = disabled
1 = enabled
*/
uint32_t mstatus = get_mstatus();
_state.ie_status = ((mstatus & (1 << 3)) != 0);
#endif
}
/**
* @brief Enter a critical section of code that cannot be interrupted.
*/
static inline void MXC_SYS_Crit_Enter(void)
{
_mxc_crit_get_state();
if (_state.ie_status)
__disable_irq();
_state.in_critical = 1;
}
/**
* @brief Exit a critical section of code, re-enabling interrupts if they
* were previously.
*/
static inline void MXC_SYS_Crit_Exit(void)
{
if (_state.ie_status) {
__enable_irq();
}
_state.in_critical = 0;
_mxc_crit_get_state();
/*
^ Reset the state again to prevent edge case
where interrupts get disabled, then Crit_Exit() gets
called, which would inadvertently re-enable interrupts
from old state.
*/
}
/**
* @brief Polls whether code is currently executing from a critical section.
* @returns 1 if code is currently in a critical section (interrupts are disabled).
* 0 if code is not in a critical section.
*/
static inline int MXC_SYS_In_Crit_Section(void)
{
return _state.in_critical;
}
/**
* @brief Macro for wrapping a section of code to make it critical. Note: this macro
* does not support nesting.
*/
// clang-format off
#define MXC_CRITICAL(code) { \
MXC_SYS_Crit_Enter();\
code;\
MXC_SYS_Crit_Exit();\
}
// clang-format on
/**
* @brief Reads the device USN.
* @param usn Pointer to store the USN.
@ -205,4 +316,4 @@ void MXC_SYS_Reset_Periph (mxc_sys_reset_t reset);
}
#endif
#endif /* _MXC_MXC_SYS_H_*/
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_SYS_H_

35
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/rtc.h
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@ -3,8 +3,8 @@
* @brief Real Time Clock (RTC) functions and prototypes.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,17 +34,19 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _RTC_H_
#define _RTC_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_RTC_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_RTC_H_
/* **** Includes **** */
#include <stdint.h>
#include "mxc_device.h"
#include "rtc_regs.h"
#include "mxc_sys.h"
#include "rtc_regs.h"
#include "tmr_regs.h"
#ifdef __cplusplus
extern "C" {
@ -56,6 +58,9 @@ extern "C" {
* @{
*/
#define MXC_RTC_MAX_SSEC (MXC_F_RTC_SSEC_SSEC + 1)
#define MXC_RTC_TRIM_TMR_IRQ MXC_F_TMR_INTFL_IRQ_A
/* **** Definitions **** */
/**
* @brief Bitmasks for each of the RTC's Frequency.
@ -114,10 +119,10 @@ int MXC_RTC_Stop (void);
/**
* @brief Initialize the sec and ssec registers and enable RTC (Blocking function)
* @param sec set the RTC Sec counter (32-bit)
* @param ssec set the RTC Sub-second counter (8-bit)
* @param ssec set the RTC Sub-second counter (12-bit)
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_Init (uint32_t sec, uint8_t ssec);
int MXC_RTC_Init(uint32_t sec, uint16_t ssec);
/**
* @brief Allow generation of Square Wave on the SQW pin (Blocking function)
@ -197,9 +202,21 @@ int MXC_RTC_GetTime (uint32_t* sec, uint32_t* subsec);
*/
int MXC_RTC_GetBusyFlag(void);
/**
* @brief Calculate and set the appropriate RTC trim value based on an accurate reference clock
*
* @param tmr Timer available to be used to measure known time periods over which the RTC ticks are counted
*
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*
* @note If RTC running before calling this function and interrupts enabled, accuracy of trimming could be affected
* @note External 32MHz must be installed and calibrated properly for this function to be successful
*/
int MXC_RTC_TrimCrystal(mxc_tmr_regs_t *tmr);
/**@} end of group rtc */
#ifdef __cplusplus
}
#endif
#endif /* _RTC_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_RTC_H_

22
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/tmr.h
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@ -3,8 +3,8 @@
* @brief Timer (TMR) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,19 +34,20 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _TMR_H_
#define _TMR_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_TMR_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_TMR_H_
/* **** Includes **** */
#include <stdint.h>
#include <stdbool.h>
#include "mxc_device.h"
#include "tmr_regs.h"
#include "mxc_sys.h"
#include "gcr_regs.h"
#include "mcr_regs.h"
#include "stdbool.h"
#ifdef __cplusplus
extern "C" {
@ -209,7 +210,8 @@ uint32_t MXC_TMR_GetCount (mxc_tmr_regs_t* tmr);
* @param frequency required frequency.
* @return Returns the period count.
*/
uint32_t MXC_TMR_GetPeriod (mxc_tmr_regs_t* tmr, mxc_tmr_clock_t clock, uint32_t prescalar, uint32_t frequency);
uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, mxc_tmr_clock_t clock, uint32_t prescalar,
uint32_t frequency);
/**
* @brief Clear the timer interrupt.
@ -275,7 +277,7 @@ void MXC_TMR_SetCount (mxc_tmr_regs_t *tmr, uint32_t cnt);
* @param tmr The timer
* @param us microseconds to delay for
*/
void MXC_TMR_Delay (mxc_tmr_regs_t *tmr, unsigned long us);
void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us);
/**
* @brief Start a timer that will time out after a certain number of microseconds
@ -284,7 +286,7 @@ void MXC_TMR_Delay (mxc_tmr_regs_t *tmr, unsigned long us);
* @param tmr The timer
* @param us microseconds to time out after
*/
void MXC_TMR_TO_Start (mxc_tmr_regs_t *tmr, unsigned long us);
void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us);
/**
* @brief Check on time out timer
@ -361,4 +363,4 @@ int MXC_TMR_GetTime (mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tm
}
#endif
#endif /* _TMR_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_TMR_H_

22
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/trng.h
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@ -3,8 +3,8 @@
* @brief Random number generator driver.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,10 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef _TRNG_H_
#define _TRNG_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_TRNG_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_TRNG_H_
/***** Includes *****/
#include "trng_regs.h"
@ -52,7 +52,6 @@ extern "C" {
* @{
*/
/***** Function Prototypes *****/
typedef void (*mxc_trng_complete_t)(void *req, int result);
@ -129,9 +128,18 @@ void MXC_TRNG_RandomAsync (uint8_t* data, uint32_t len, mxc_trng_complete_t call
*/
void MXC_TRNG_GenerateKey(void);
/**
* @brief Perform health test of the TRNG entropy source
*
* @return If test fails the function will return E_BAD_STATE (-7), otherwise it will return E_NO_ERROR.
*
* @warning MAX32670 with Rev. A Silicon does not support health tests. (Check MXC_GCR->revision to see which revision your chip is.)
*/
int MXC_TRNG_HealthTest(void);
#ifdef __cplusplus
}
#endif
/**@} end of group trng */
#endif /* _TRNG_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_TRNG_H_

25
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/uart.h
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@ -3,8 +3,8 @@
* @brief Serial Peripheral Interface (UART) communications driver.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,16 +34,18 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _MXC_UART_H_
#define _MXC_UART_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_UART_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_UART_H_
/***** Definitions *****/
#include "uart_regs.h"
#include "mxc_sys.h"
#define UART_EXTCLK_FREQ EXTCLK_FREQ
#ifdef __cplusplus
extern "C" {
#endif
@ -361,8 +363,7 @@ int MXC_UART_Write(mxc_uart_regs_t* uart, const uint8_t* byte, int* len);
*
* @return The number of bytes actually read.
*/
unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len);
unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len);
/**
* @brief Unloads bytes from the receive FIFO user DMA for longer reads.
@ -374,8 +375,8 @@ unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t* uart, unsigned char* bytes,
*
* @return See \ref MXC_ERROR_CODES for a list of return values
*/
int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len, mxc_uart_dma_complete_cb_t callback);
int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len,
mxc_uart_dma_complete_cb_t callback);
/**
* @brief Get the number of bytes currently available in the receive FIFO.
@ -408,8 +409,8 @@ unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t* uart, const unsigned char* by
*
* @return See \ref MXC_ERROR_CODES for a list of return values
*/
int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t* uart, const unsigned char* bytes,
unsigned int len, mxc_uart_dma_complete_cb_t callback);
int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, unsigned int len,
mxc_uart_dma_complete_cb_t callback);
/**
* @brief Get the amount of free space available in the transmit FIFO.
@ -678,4 +679,4 @@ uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t* req);
}
#endif
#endif /* _MXC_UART_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_UART_H_

16
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/wdt.h
View File

@ -3,8 +3,8 @@
* @brief Watchdog timer (WDT) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,15 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _WDT_H_
#define _WDT_H_
#ifdef __CC_ARM
#pragma diag_suppress 66 // enumeration value is out of "int" range
#endif
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_WDT_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_WDT_H_
/* **** Includes **** */
#include <stdint.h>
@ -221,4 +217,4 @@ void MXC_WDT_ClearIntFlag (mxc_wdt_regs_t* wdt);
}
#endif
#endif /* _WDT_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_WDT_H_

120
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_key_revb_regs.h
View File

@ -1,120 +0,0 @@
/**
* @file aes_key_revb_regs.h
* @brief Registers, Bit Masks and Bit Positions for the AES_KEY_REVB Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _AES_KEY_REVB_REGS_H_
#define _AES_KEY_REVB_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup aes_key_revb
* @defgroup aes_key_revb_registers AES_KEY_REVB_Registers
* @brief Registers, Bit Masks and Bit Positions for the AES_KEY_REVB Peripheral Module.
* @details AES Key Registers.
*/
/**
* @ingroup aes_key_revb_registers
* Structure type to access the AES_KEY_REVB Registers.
*/
typedef struct {
__IO uint32_t aes_key0; /**< <tt>\b 0x00:</tt> AES_KEY_REVB AES_KEY0 Register */
__IO uint32_t aes_key1; /**< <tt>\b 0x04:</tt> AES_KEY_REVB AES_KEY1 Register */
__IO uint32_t aes_key2; /**< <tt>\b 0x08:</tt> AES_KEY_REVB AES_KEY2 Register */
__IO uint32_t aes_key3; /**< <tt>\b 0x0C:</tt> AES_KEY_REVB AES_KEY3 Register */
__IO uint32_t aes_key4; /**< <tt>\b 0x10:</tt> AES_KEY_REVB AES_KEY4 Register */
__IO uint32_t aes_key5; /**< <tt>\b 0x14:</tt> AES_KEY_REVB AES_KEY5 Register */
__IO uint32_t aes_key6; /**< <tt>\b 0x18:</tt> AES_KEY_REVB AES_KEY6 Register */
__IO uint32_t aes_key7; /**< <tt>\b 0x1C:</tt> AES_KEY_REVB AES_KEY7 Register */
} mxc_aes_key_revb_regs_t;
/* Register offsets for module AES_KEY_REVB */
/**
* @ingroup aes_key_revb_registers
* @defgroup AES_KEY_REVB_Register_Offsets Register Offsets
* @brief AES_KEY_REVB Peripheral Register Offsets from the AES_KEY_REVB Base Peripheral Address.
* @{
*/
#define MXC_R_AES_KEY_REVB_AES_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x0000</tt> */
#define MXC_R_AES_KEY_REVB_AES_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x0004</tt> */
#define MXC_R_AES_KEY_REVB_AES_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x0008</tt> */
#define MXC_R_AES_KEY_REVB_AES_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x000C</tt> */
#define MXC_R_AES_KEY_REVB_AES_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x0010</tt> */
#define MXC_R_AES_KEY_REVB_AES_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x0014</tt> */
#define MXC_R_AES_KEY_REVB_AES_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x0018</tt> */
#define MXC_R_AES_KEY_REVB_AES_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x001C</tt> */
/**@} end of group aes_key_revb_registers */
#ifdef __cplusplus
}
#endif
#endif /* _AES_KEY_REVB_REGS_H_ */

26
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_me15.c
View File

@ -3,8 +3,8 @@
* @brief Trust Protection Unit driver.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,7 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#include "mxc_device.h"
#include "mxc_errors.h"
@ -54,8 +54,7 @@ static void reverse_key(const void* key, uint8_t* keyr, int len)
int i;
uint8_t tmp;
uint8_t *k = (uint8_t *)key;
for(i = 0; i < len; i++)
{
for (i = 0; i < len; i++) {
tmp = k[i];
k[i] = keyr[len - i - 1];
keyr[len - i - 1] = tmp;
@ -177,7 +176,8 @@ int MXC_AES_RXDMAConfig(void* dest_addr, int len)
int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc)
{
return MXC_AES_RevB_GenericAsync((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req, enc);
return MXC_AES_RevB_GenericAsync((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req,
enc);
}
int MXC_AES_EncryptAsync(mxc_aes_req_t *req)
@ -192,7 +192,7 @@ int MXC_AES_DecryptAsync(mxc_aes_req_t* req)
void MXC_AES_SetExtKey(const void *key, mxc_aes_keys_t len)
{
MXC_AES_RevB_SetExtKey((mxc_aes_key_revb_regs_t*) MXC_AESKEY, key, len);
MXC_AES_RevB_SetExtKey((mxc_aeskeys_revb_regs_t *)MXC_AESKEYS, key, len);
}
int MXC_AES_SetPORKey(const void *key, mxc_aes_keys_t len)
@ -204,8 +204,7 @@ int MXC_AES_SetPORKey(const void* key, mxc_aes_keys_t len)
MXC_FLC_UnlockInfoBlock(KEY_ADDR);
// Write the key
switch(len)
{
switch (len) {
case MXC_AES_128BITS:
reverse_key(key, keyr, 16);
err = MXC_FLC_Write(KEY_ADDR, 16, (uint32_t *)keyr);
@ -271,16 +270,15 @@ void MXC_AES_CopyPORKeyToKeyRegisters(mxc_aes_keys_t len)
MXC_FLC_UnlockInfoBlock(KEY_ADDR);
// Copy the values to the key register
switch(len)
{
switch (len) {
case MXC_AES_128BITS:
memcpy(MXC_AESKEY, (uint8_t*)KEY_ADDR, 16);
memcpy(MXC_AESKEYS, (uint8_t *)KEY_ADDR, 16);
break;
case MXC_AES_192BITS:
memcpy(MXC_AESKEY, (uint8_t*)KEY_ADDR, 24);
memcpy(MXC_AESKEYS, (uint8_t *)KEY_ADDR, 24);
break;
case MXC_AES_256BITS:
memcpy(MXC_AESKEY, (uint8_t*)KEY_ADDR, 32);
memcpy(MXC_AESKEYS, (uint8_t *)KEY_ADDR, 32);
break;
}

81
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb.c
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,10 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#ifdef __CC_ARM // Keil
#pragma diag_suppress 188 // enumerated type mixed with another type
#endif
******************************************************************************/
#include <stdlib.h>
#include <string.h>
@ -44,7 +41,7 @@
#include "dma.h"
#include "aes_regs.h"
#include "aes_key_regs.h"
#include "aeskeys_regs.h"
#include "aes_revb.h"
#include "trng_revb.h"
@ -60,9 +57,13 @@ typedef struct {
static mxc_aes_revb_dma_req_t dma_state;
#define SWAP_BYTES(x) ((((x) >> 24) & 0x000000FF) | (((x) >> 8) & 0x0000FF00) | (((x) << 8) & 0x00FF0000) | (((x) << 24) & 0xFF000000))
#define SWAP_BYTES(x) \
((((x) >> 24) & 0x000000FF) | (((x) >> 8) & 0x0000FF00) | (((x) << 8) & 0x00FF0000) | \
(((x) << 24) & 0xFF000000))
static void memcpy32r(uint32_t * dst, const uint32_t * src, unsigned int len)
/* Prevent GCC from optimimzing this function to memcpy */
static void __attribute__((optimize("no-tree-loop-distribute-patterns")))
memcpy32r(uint32_t *dst, const uint32_t *src, unsigned int len)
{
uint32_t *dstr = dst + (len / 4) - 1;
while (len) {
@ -77,7 +78,7 @@ int MXC_AES_RevB_Init(mxc_aes_revb_regs_t* aes)
{
aes->ctrl = 0x00;
while (MXC_AES_RevB_IsBusy(aes) != E_NO_ERROR);
while (MXC_AES_RevB_IsBusy(aes) != E_NO_ERROR) {}
aes->ctrl |= MXC_F_AES_REVB_CTRL_EN;
@ -89,7 +90,7 @@ int MXC_AES_RevB_Shutdown (mxc_aes_revb_regs_t* aes)
MXC_AES_RevB_FlushInputFIFO(aes);
MXC_AES_RevB_FlushOutputFIFO(aes);
while(MXC_AES_RevB_IsBusy(aes) != E_NO_ERROR) ;
while (MXC_AES_RevB_IsBusy(aes) != E_NO_ERROR) {}
aes->ctrl = 0x00;
@ -98,8 +99,7 @@ int MXC_AES_RevB_Shutdown (mxc_aes_revb_regs_t* aes)
int MXC_AES_RevB_IsBusy(mxc_aes_revb_regs_t *aes)
{
if(aes->status & MXC_F_AES_REVB_STATUS_BUSY)
{
if (aes->status & MXC_F_AES_REVB_STATUS_BUSY) {
return E_BUSY;
}
@ -108,7 +108,7 @@ int MXC_AES_RevB_IsBusy (mxc_aes_revb_regs_t* aes)
void MXC_AES_RevB_SetKeySize(mxc_aes_revb_regs_t *aes, mxc_aes_revb_keys_t key)
{
while(MXC_AES_IsBusy() != E_NO_ERROR);
while (MXC_AES_IsBusy() != E_NO_ERROR) {}
aes->ctrl |= key;
}
@ -119,31 +119,31 @@ mxc_aes_keys_t MXC_AES_RevB_GetKeySize(mxc_aes_revb_regs_t* aes)
void MXC_AES_RevB_FlushInputFIFO(mxc_aes_revb_regs_t *aes)
{
while(MXC_AES_IsBusy() != E_NO_ERROR);
while (MXC_AES_IsBusy() != E_NO_ERROR) {}
aes->ctrl |= MXC_F_AES_REVB_CTRL_INPUT_FLUSH;
}
void MXC_AES_RevB_FlushOutputFIFO(mxc_aes_revb_regs_t *aes)
{
while(MXC_AES_IsBusy() != E_NO_ERROR);
while (MXC_AES_IsBusy() != E_NO_ERROR) {}
aes->ctrl |= MXC_F_AES_REVB_CTRL_OUTPUT_FLUSH;
}
void MXC_AES_RevB_Start(mxc_aes_revb_regs_t *aes)
{
while(MXC_AES_IsBusy() != E_NO_ERROR);
while (MXC_AES_IsBusy() != E_NO_ERROR) {}
aes->ctrl |= MXC_F_AES_REVB_CTRL_START;
}
void MXC_AES_RevB_EnableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt)
{
aes->inten |= (interrupt & (MXC_F_AES_REVB_INTEN_DONE | MXC_F_AES_REVB_INTEN_KEY_CHANGE | \
aes->inten |= (interrupt & (MXC_F_AES_REVB_INTEN_DONE | MXC_F_AES_REVB_INTEN_KEY_CHANGE |
MXC_F_AES_REVB_INTEN_KEY_ZERO | MXC_F_AES_REVB_INTEN_OV));
}
void MXC_AES_RevB_DisableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt)
{
aes->inten &= ~(interrupt & (MXC_F_AES_REVB_INTEN_DONE | MXC_F_AES_REVB_INTEN_KEY_CHANGE | \
aes->inten &= ~(interrupt & (MXC_F_AES_REVB_INTEN_DONE | MXC_F_AES_REVB_INTEN_KEY_CHANGE |
MXC_F_AES_REVB_INTEN_KEY_ZERO | MXC_F_AES_REVB_INTEN_OV));
}
@ -154,7 +154,7 @@ uint32_t MXC_AES_RevB_GetFlags(mxc_aes_revb_regs_t* aes)
void MXC_AES_RevB_ClearFlags(mxc_aes_revb_regs_t *aes, uint32_t flags)
{
aes->intfl = (flags & (MXC_F_AES_REVB_INTFL_DONE | MXC_F_AES_REVB_INTFL_KEY_CHANGE | \
aes->intfl = (flags & (MXC_F_AES_REVB_INTFL_DONE | MXC_F_AES_REVB_INTFL_KEY_CHANGE |
MXC_F_AES_REVB_INTFL_KEY_ZERO | MXC_F_AES_REVB_INTFL_OV));
}
@ -182,18 +182,18 @@ int MXC_AES_RevB_Generic(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req)
MXC_AES_RevB_SetKeySize(aes, req->keySize);
while(MXC_AES_IsBusy() != E_NO_ERROR);
while (MXC_AES_IsBusy() != E_NO_ERROR) {}
MXC_SETFIELD (aes->ctrl, MXC_F_AES_REVB_CTRL_TYPE, req->encryption << MXC_F_AES_REVB_CTRL_TYPE_POS);
MXC_SETFIELD(aes->ctrl, MXC_F_AES_REVB_CTRL_TYPE,
req->encryption << MXC_F_AES_REVB_CTRL_TYPE_POS);
while(remain/4)
{
while (remain / 4) {
for (i = 0; i < 4; i++) {
aes->fifo = SWAP_BYTES(req->inputData[3 - i]);
}
req->inputData += 4;
while(!(aes->intfl & MXC_F_AES_REVB_INTFL_DONE));
while (!(aes->intfl & MXC_F_AES_REVB_INTFL_DONE)) {}
aes->intfl |= MXC_F_AES_REVB_INTFL_DONE;
for (i = 0; i < 4; i++) {
@ -205,8 +205,7 @@ int MXC_AES_RevB_Generic(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req)
remain -= 4;
}
if(remain%4)
{
if (remain % 4) {
for (i = 0; i < remain; i++) {
aes->fifo = SWAP_BYTES(req->inputData[remain - 1 - i]);
}
@ -217,7 +216,7 @@ int MXC_AES_RevB_Generic(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req)
aes->fifo = 0;
}
while(!(aes->intfl & MXC_F_AES_REVB_INTFL_DONE));
while (!(aes->intfl & MXC_F_AES_REVB_INTFL_DONE)) {}
aes->intfl |= MXC_F_AES_REVB_INTFL_DONE;
for (i = 0; i < 4; i++) {
@ -273,11 +272,9 @@ int MXC_AES_RevB_TXDMAConfig(void* src_addr, int len)
if (dma_state.enc == 1) {
srcdst.len = 4;
}
else if(len > 4) {
} else if (len > 4) {
srcdst.len = 4;
}
else{
} else {
srcdst.len = len;
}
@ -326,11 +323,9 @@ int MXC_AES_RevB_RXDMAConfig(void* dest_addr, int len)
if (dma_state.enc == 0) {
srcdst.len = 4;
}
else if(len > 4) {
} else if (len > 4) {
srcdst.len = 4;
}
else{
} else {
srcdst.len = len;
}
@ -365,7 +360,8 @@ int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req,
MXC_AES_RevB_SetKeySize(aes, req->keySize);
MXC_AES_IsBusy();
MXC_SETFIELD (aes->ctrl, MXC_F_AES_REVB_CTRL_TYPE, req->encryption << MXC_F_AES_REVB_CTRL_TYPE_POS);
MXC_SETFIELD(aes->ctrl, MXC_F_AES_REVB_CTRL_TYPE,
req->encryption << MXC_F_AES_REVB_CTRL_TYPE_POS);
dma_state.enc = enc;
dma_state.remain = req->length;
@ -395,17 +391,14 @@ int MXC_AES_RevB_DecryptAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req)
void MXC_AES_RevB_DMACallback(int ch, int error)
{
if (error != E_NO_ERROR) {
}
else {
} else {
if (dma_state.channelTX == ch) {
MXC_DMA_ReleaseChannel(dma_state.channelTX);
if (dma_state.remain < 4) {
MXC_AES_Start();
}
MXC_AES_RevB_RXDMAConfig(dma_state.outputText, dma_state.remain);
}
else if (dma_state.channelRX == ch) {
} else if (dma_state.channelRX == ch) {
if (dma_state.remain > 4) {
dma_state.remain -= 4;
} else if (dma_state.remain > 0) {
@ -419,7 +412,7 @@ void MXC_AES_RevB_DMACallback(int ch, int error)
}
}
void MXC_AES_RevB_SetExtKey(mxc_aes_key_revb_regs_t* aeskey, const void* key, mxc_aes_keys_t len)
void MXC_AES_RevB_SetExtKey(mxc_aeskeys_revb_regs_t *aeskeys, const void *key, mxc_aes_keys_t len)
{
int numBytes;
@ -432,5 +425,5 @@ void MXC_AES_RevB_SetExtKey(mxc_aes_key_revb_regs_t* aeskey, const void* key, mx
}
/* TODO: Figure out if this is the correct byte ordering */
memcpy32r((void*)&(aeskey->aes_key0), key, numBytes);
memcpy32r((void *)&(aeskeys->key0), key, numBytes);
}

16
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb.h
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,12 +29,15 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_AES_AES_REVB_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_AES_AES_REVB_H_
#include <stdint.h>
#include "mxc_aes.h"
#include "aes_revb_regs.h"
#include "aes_key_revb_regs.h"
#include "aeskeys_revb_regs.h"
#include "trng_revb_regs.h"
/**
@ -70,7 +73,6 @@ typedef struct _mxc_aes_revb_cipher_req_t {
mxc_aes_complete_t callback; ///< Callback function
} mxc_aes_revb_req_t;
int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes);
void MXC_AES_RevB_EnableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt);
void MXC_AES_RevB_DisableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt);
@ -93,4 +95,6 @@ int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req,
int MXC_AES_RevB_EncryptAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req);
int MXC_AES_RevB_DecryptAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req);
void MXC_AES_RevB_DMACallback(int ch, int error);
void MXC_AES_RevB_SetExtKey(mxc_aes_key_revb_regs_t* aeskey, const void* key, mxc_aes_keys_t len);
void MXC_AES_RevB_SetExtKey(mxc_aeskeys_revb_regs_t *aeskey, const void *key, mxc_aes_keys_t len);
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_AES_AES_REVB_H_

10
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb_regs.h
View File

@ -3,8 +3,8 @@
* @brief Registers, Bit Masks and Bit Positions for the AES_REVB Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _AES_REVB_REGS_H_
#define _AES_REVB_REGS_H_
@ -67,9 +66,6 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */

117
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aeskeys_revb_regs.h Normal file
View File

@ -0,0 +1,117 @@
/**
* @file aeskeys_revb_regs.h
* @brief Registers, Bit Masks and Bit Positions for the AESKEYS_REVB Peripheral Module.
* @note This file is @generated.
*/
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_AESKEYS_AESKEYS_REVB_REGS_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_AESKEYS_AESKEYS_REVB_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup aeskeys_revb
* @defgroup aeskeys_revb_registers AESKEYS_REVB_Registers
* @brief Registers, Bit Masks and Bit Positions for the AESKEYS_REVB Peripheral Module.
* @details AES Key Registers.
*/
/**
* @ingroup aeskeys_revb_registers
* Structure type to access the AESKEYS_REVB Registers.
*/
typedef struct {
__IO uint32_t key0; /**< <tt>\b 0x00:</tt> AESKEYS_REVB KEY0 Register */
__IO uint32_t key1; /**< <tt>\b 0x04:</tt> AESKEYS_REVB KEY1 Register */
__IO uint32_t key2; /**< <tt>\b 0x08:</tt> AESKEYS_REVB KEY2 Register */
__IO uint32_t key3; /**< <tt>\b 0x0C:</tt> AESKEYS_REVB KEY3 Register */
__IO uint32_t key4; /**< <tt>\b 0x10:</tt> AESKEYS_REVB KEY4 Register */
__IO uint32_t key5; /**< <tt>\b 0x14:</tt> AESKEYS_REVB KEY5 Register */
__IO uint32_t key6; /**< <tt>\b 0x18:</tt> AESKEYS_REVB KEY6 Register */
__IO uint32_t key7; /**< <tt>\b 0x1C:</tt> AESKEYS_REVB KEY7 Register */
} mxc_aeskeys_revb_regs_t;
/* Register offsets for module AESKEYS_REVB */
/**
* @ingroup aeskeys_revb_registers
* @defgroup AESKEYS_REVB_Register_Offsets Register Offsets
* @brief AESKEYS_REVB Peripheral Register Offsets from the AESKEYS_REVB Base Peripheral Address.
* @{
*/
#define MXC_R_AESKEYS_REVB_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AESKEYS_REVB Base Address: <tt> 0x0000</tt> */
#define MXC_R_AESKEYS_REVB_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AESKEYS_REVB Base Address: <tt> 0x0004</tt> */
#define MXC_R_AESKEYS_REVB_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AESKEYS_REVB Base Address: <tt> 0x0008</tt> */
#define MXC_R_AESKEYS_REVB_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AESKEYS_REVB Base Address: <tt> 0x000C</tt> */
#define MXC_R_AESKEYS_REVB_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AESKEYS_REVB Base Address: <tt> 0x0010</tt> */
#define MXC_R_AESKEYS_REVB_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AESKEYS_REVB Base Address: <tt> 0x0014</tt> */
#define MXC_R_AESKEYS_REVB_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AESKEYS_REVB Base Address: <tt> 0x0018</tt> */
#define MXC_R_AESKEYS_REVB_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AESKEYS_REVB Base Address: <tt> 0x001C</tt> */
/**@} end of group aeskeys_revb_registers */
#ifdef __cplusplus
}
#endif
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_AESKEYS_AESKEYS_REVB_REGS_H_

7
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_me15.c
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#include "mxc_device.h"
#include "mxc_errors.h"
@ -39,7 +39,6 @@
#include "crc.h"
#include "crc_reva.h"
/* ************************************************************************* */
/* Global Control/Configuration functions */
/* ************************************************************************* */

24
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva.c
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,11 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#ifdef __CC_ARM
#pragma diag_suppress 188
#endif
******************************************************************************/
#include <stdlib.h>
#include <string.h>
@ -48,7 +44,6 @@
#include "crc_regs.h"
#include "crc_reva.h"
/***** Global Variables *****/
static mxc_crc_reva_req_t *CRCreq;
@ -97,12 +92,14 @@ mxc_crc_bitorder_t MXC_CRC_RevA_GetDirection(mxc_crc_reva_regs_t* crc)
void MXC_CRC_RevA_SwapDataIn(mxc_crc_reva_regs_t *crc, mxc_crc_reva_bitorder_t bitOrder)
{
MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_BYTE_SWAP_IN, bitOrder << MXC_F_CRC_REVA_CTRL_BYTE_SWAP_IN_POS);
MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_BYTE_SWAP_IN,
bitOrder << MXC_F_CRC_REVA_CTRL_BYTE_SWAP_IN_POS);
}
void MXC_CRC_RevA_SwapDataOut(mxc_crc_reva_regs_t *crc, mxc_crc_reva_bitorder_t bitOrder)
{
MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_BYTE_SWAP_OUT, bitOrder << MXC_F_CRC_REVA_CTRL_BYTE_SWAP_OUT_POS);
MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_BYTE_SWAP_OUT,
bitOrder << MXC_F_CRC_REVA_CTRL_BYTE_SWAP_OUT_POS);
}
void MXC_CRC_RevA_SetPoly(mxc_crc_reva_regs_t *crc, uint32_t poly)
@ -145,10 +142,9 @@ int MXC_CRC_RevA_Compute(mxc_crc_reva_regs_t* crc, mxc_crc_reva_req_t* req)
length = req->dataLen;
while(length--)
{
while (length--) {
crc->datain32 = req->dataBuffer[i++];
while(crc->ctrl & MXC_F_CRC_REVA_CTRL_BUSY);
while (crc->ctrl & MXC_F_CRC_REVA_CTRL_BUSY) {}
}
// Store the crc value
@ -199,7 +195,7 @@ int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t* crc, mxc_crc_reva_req_t* req)
MXC_CRC->ctrl |= MXC_F_CRC_CTRL_EN;
MXC_DMA_ConfigChannel(config, srcdst);
MXC_DMA_SetCallback(channel,(void *) MXC_CRC_Handler);
MXC_DMA_SetCallback(channel, MXC_CRC_Handler);
MXC_DMA_EnableInt(channel);
MXC_DMA_Start(channel);
//MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE;

18
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva.h
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,12 +29,14 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_CRC_CRC_REVA_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_CRC_CRC_REVA_H_
#include "crc.h"
#include "crc_reva_regs.h"
/***** CRC Definitions *****/
/**
* @brief Structure used to set up CRC request
@ -50,11 +52,7 @@ typedef struct _mxc_crc_reva_req_t {
* @brief CRC data bit order
*
*/
typedef enum {
CRC_REVA_LSB_FIRST,
CRC_REVA_MSB_FIRST
} mxc_crc_reva_bitorder_t;
typedef enum { CRC_REVA_LSB_FIRST, CRC_REVA_MSB_FIRST } mxc_crc_reva_bitorder_t;
int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc);
int MXC_CRC_RevA_Shutdown(mxc_crc_reva_regs_t *crc);
@ -68,3 +66,5 @@ uint32_t MXC_CRC_RevA_GetPoly(mxc_crc_reva_regs_t* crc);
uint32_t MXC_CRC_RevA_GetResult(mxc_crc_reva_regs_t *crc);
int MXC_CRC_RevA_Compute(mxc_crc_reva_regs_t *crc, mxc_crc_reva_req_t *req);
int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t *crc, mxc_crc_reva_req_t *req);
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_CRC_CRC_REVA_H_

7
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva_regs.h
View File

@ -3,8 +3,8 @@
* @brief Registers, Bit Masks and Bit Positions for the CRC_REVA Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _CRC_REVA_REGS_H_
#define _CRC_REVA_REGS_H_

9
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_me15.c
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/****** Includes *******/
#include <stddef.h>
@ -158,7 +158,8 @@ int MXC_DMA_MemCpy(void* dest, void* src, int len, mxc_dma_complete_cb_t callbac
return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)MXC_DMA, dest, src, len, callback);
}
int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback)
int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst,
mxc_dma_trans_chain_t callback)
{
return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t *)MXC_DMA, config, firstSrcDst, callback);
}

109
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva.c
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,10 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#ifdef __CC_ARM // Keil
#pragma diag_suppress 68 // integer conversion resulted in a change of sign
#endif
******************************************************************************/
/****** Includes *******/
#include <stddef.h>
@ -65,9 +62,7 @@ typedef struct {
static unsigned int dma_initialized[MXC_DMA_INSTANCES] = { 0 };
static mxc_dma_channel_t dma_resource[MXC_DMA_CHANNELS];
static mxc_dma_highlevel_t memcpy_resource[MXC_DMA_CHANNELS];
#if USE_LOCK_IN_DRIVERS
static uint32_t dma_lock;
#endif
/****** Functions ******/
static void memcpy_callback(int ch, int error);
@ -173,8 +168,7 @@ int MXC_DMA_RevA_ReleaseChannel(int ch)
dma_resource[ch].regs->ctrl = 0;
dma_resource[ch].regs->status = dma_resource[ch].regs->status;
MXC_FreeLock(&dma_lock);
}
else {
} else {
return E_BAD_PARAM;
}
@ -187,67 +181,59 @@ int MXC_DMA_RevA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst)
/* Designed to be safe, not speedy. Should not be called often */
dma_resource[config.ch].regs->ctrl =
((config.srcinc_en ? MXC_F_DMA_REVA_CTRL_SRCINC : 0) |
(config.dstinc_en ? MXC_F_DMA_REVA_CTRL_DSTINC : 0) |
config.reqsel |
(config.dstinc_en ? MXC_F_DMA_REVA_CTRL_DSTINC : 0) | config.reqsel |
(config.srcwd << MXC_F_DMA_REVA_CTRL_SRCWD_POS) |
(config.dstwd << MXC_F_DMA_REVA_CTRL_DSTWD_POS));
}
else {
} else {
return E_BAD_PARAM;
}
return MXC_DMA_RevA_SetSrcDst(srcdst);
}
int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig)
{
if (CHECK_HANDLE(advConfig.ch) && (advConfig.burst_size > 0)) {
dma_resource[advConfig.ch].regs->ctrl &= ~(0x1F00FC0C); // Clear all fields we set here
/* Designed to be safe, not speedy. Should not be called often */
dma_resource[advConfig.ch].regs->ctrl |=
((advConfig.reqwait_en ? MXC_F_DMA_REVA_CTRL_TO_WAIT : 0) |
advConfig.prio | advConfig.tosel | advConfig.pssel |
(((advConfig.burst_size - 1) << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS) & MXC_F_DMA_REVA_CTRL_BURST_SIZE));
}
else {
((advConfig.reqwait_en ? MXC_F_DMA_REVA_CTRL_TO_WAIT : 0) | advConfig.prio |
advConfig.tosel | advConfig.pssel |
(((advConfig.burst_size - 1) << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS) &
MXC_F_DMA_REVA_CTRL_BURST_SIZE));
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_SetSrcDst(mxc_dma_srcdst_t srcdst)
{
if (CHECK_HANDLE(srcdst.ch)) {
dma_resource[srcdst.ch].regs->src = (unsigned int)srcdst.source;
dma_resource[srcdst.ch].regs->dst = (unsigned int)srcdst.dest;
dma_resource[srcdst.ch].regs->cnt = srcdst.len;
}
else {
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t *srcdst)
{
if (CHECK_HANDLE(srcdst->ch)) {
srcdst->source = (void *)dma_resource[srcdst->ch].regs->src;
srcdst->dest = (void *)dma_resource[srcdst->ch].regs->dst;
srcdst->len = (dma_resource[srcdst->ch].regs->cnt) & ~MXC_F_DMA_REVA_CNTRLD_EN;
}
else {
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst)
{
if (CHECK_HANDLE(srcdst.ch)) {
@ -257,42 +243,36 @@ int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst)
if (dma_resource[srcdst.ch].regs->ctrl & MXC_F_DMA_REVA_CTRL_EN) {
/* If channel is already running, set RLDEN to enable next reload */
dma_resource[srcdst.ch].regs->cntrld = MXC_F_DMA_REVA_CNTRLD_EN | srcdst.len;
}
else {
} else {
/* Otherwise, this is the initial setup, so DMA_Start() will handle setting that bit */
dma_resource[srcdst.ch].regs->cntrld = srcdst.len;
}
}
else {
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t *srcdst)
{
if (CHECK_HANDLE(srcdst->ch)) {
srcdst->source = (void *)dma_resource[srcdst->ch].regs->srcrld;
srcdst->dest = (void *)dma_resource[srcdst->ch].regs->dstrld;
srcdst->len = (dma_resource[srcdst->ch].regs->cntrld) & ~MXC_F_DMA_REVA_CNTRLD_EN;
}
else {
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_SetCallback(int ch, void (*callback)(int, int))
{
if (CHECK_HANDLE(ch)) {
/* Callback for interrupt handler, no checking is done, as NULL is valid for(none) */
dma_resource[ch].cb = callback;
}
else {
} else {
return E_BAD_PARAM;
}
@ -308,15 +288,13 @@ int MXC_DMA_RevA_SetChannelInterruptEn(int ch, bool chdis, bool ctz)
if (ctz) {
dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_CTZ_IE);
}
}
else {
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_GetChannelInterruptEn(int ch)
{
return E_NOT_SUPPORTED;
@ -325,9 +303,9 @@ int MXC_DMA_RevA_GetChannelInterruptEn(int ch)
int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags)
{
if (CHECK_HANDLE(ch)) {
dma_resource[ch].regs->ctrl |= (flags &(MXC_F_DMA_REVA_CTRL_DIS_IE|MXC_F_DMA_REVA_CTRL_CTZ_IE));
}
else {
dma_resource[ch].regs->ctrl |=
(flags & (MXC_F_DMA_REVA_CTRL_DIS_IE | MXC_F_DMA_REVA_CTRL_CTZ_IE));
} else {
return E_BAD_PARAM;
}
@ -337,9 +315,9 @@ int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags)
int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags)
{
if (CHECK_HANDLE(ch)) {
dma_resource[ch].regs->ctrl &= ~(flags &(MXC_F_DMA_REVA_CTRL_DIS_IE|MXC_F_DMA_REVA_CTRL_CTZ_IE));
}
else {
dma_resource[ch].regs->ctrl &=
~(flags & (MXC_F_DMA_REVA_CTRL_DIS_IE | MXC_F_DMA_REVA_CTRL_CTZ_IE));
} else {
return E_BAD_PARAM;
}
@ -353,8 +331,7 @@ int MXC_DMA_RevA_EnableInt(mxc_dma_reva_regs_t *dma, int ch)
ch %= MXC_DMA_CH_OFFSET;
#endif
dma->inten |= (1 << ch);
}
else {
} else {
return E_BAD_PARAM;
}
@ -368,8 +345,7 @@ int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch)
ch %= MXC_DMA_CH_OFFSET;
#endif
dma->inten &= ~(1 << ch);
}
else {
} else {
return E_BAD_PARAM;
}
@ -380,8 +356,7 @@ int MXC_DMA_RevA_ChannelGetFlags(int ch)
{
if (CHECK_HANDLE(ch)) {
return dma_resource[ch].regs->status;
}
else {
} else {
return E_BAD_PARAM;
}
@ -392,8 +367,7 @@ int MXC_DMA_RevA_ChannelClearFlags(int ch, int flags)
{
if (CHECK_HANDLE(ch)) {
dma_resource[ch].regs->status |= (flags & 0x5F); // Mask for Interrupt flags
}
else {
} else {
return E_BAD_PARAM;
}
@ -407,12 +381,10 @@ int MXC_DMA_RevA_Start(int ch)
if (dma_resource[ch].regs->cntrld) {
dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_EN | MXC_F_DMA_REVA_CTRL_RLDEN);
}
else {
} else {
dma_resource[ch].regs->ctrl |= MXC_F_DMA_REVA_CTRL_EN;
}
}
else {
} else {
return E_BAD_PARAM;
}
@ -423,8 +395,7 @@ int MXC_DMA_RevA_Stop(int ch)
{
if (CHECK_HANDLE(ch)) {
dma_resource[ch].regs->ctrl &= ~MXC_F_DMA_REVA_CTRL_EN;
}
else {
} else {
return E_BAD_PARAM;
}
@ -435,8 +406,7 @@ mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch)
{
if (CHECK_HANDLE(ch)) {
return (mxc_dma_ch_regs_t *)dma_resource[ch].regs;
}
else {
} else {
return NULL;
}
}
@ -454,11 +424,15 @@ void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma)
}
MXC_DMA_ChannelClearFlags(i, MXC_DMA_RevA_ChannelGetFlags(i));
// No need to check rest of the channels if no interrupt flags set.
if (dma->intfl == 0) {
break;
}
}
}
}
}
void memcpy_callback(int ch, int error)
{
@ -471,11 +445,15 @@ void memcpy_callback(int ch, int error)
callback(memcpy_resource[ch].dest);
// Release global objects and local resources
callback = NULL;
memcpy_resource[ch].userCallback = NULL;
memcpy_resource[ch].dest = NULL;
MXC_DMA_ReleaseChannel(ch);
}
int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len, mxc_dma_complete_cb_t callback)
int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len,
mxc_dma_complete_cb_t callback)
{
int retval;
mxc_dma_config_t config;
@ -539,10 +517,11 @@ void transfer_callback(int ch, int error)
// Call user callback for next transfer
// determine whether to load into the transfer slot or reload slot
// continue on or stop
while(1);
while (1) {}
}
int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback)
int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config,
mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback)
{
int retval, channel;

17
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva.h
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVA_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVA_H_
/****** Includes *******/
#include "dma_reva_regs.h"
@ -61,5 +64,9 @@ int MXC_DMA_RevA_Start(int ch);
int MXC_DMA_RevA_Stop(int ch);
mxc_dma_ch_regs_t *MXC_DMA_RevA_GetCHRegs(int ch);
void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma);
int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len, mxc_dma_complete_cb_t callback);
int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback);
int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len,
mxc_dma_complete_cb_t callback);
int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config,
mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback);
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVA_H_

39
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva_regs.h
View File

@ -3,8 +3,8 @@
* @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _DMA_REVA_REGS_H_
#define _DMA_REVA_REGS_H_
@ -86,14 +85,14 @@ extern "C" {
* Structure type to access the DMA Registers.
*/
typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x100:</tt> DMA CTRL Register */
__IO uint32_t status; /**< <tt>\b 0x104:</tt> DMA STATUS Register */
__IO uint32_t src; /**< <tt>\b 0x108:</tt> DMA SRC Register */
__IO uint32_t dst; /**< <tt>\b 0x10C:</tt> DMA DST Register */
__IO uint32_t cnt; /**< <tt>\b 0x110:</tt> DMA CNT Register */
__IO uint32_t srcrld; /**< <tt>\b 0x114:</tt> DMA SRCRLD Register */
__IO uint32_t dstrld; /**< <tt>\b 0x118:</tt> DMA DSTRLD Register */
__IO uint32_t cntrld; /**< <tt>\b 0x11C:</tt> DMA CNTRLD Register */
__IO uint32_t ctrl; /**< <tt>\b 0x000:</tt> DMA CTRL Register */
__IO uint32_t status; /**< <tt>\b 0x004:</tt> DMA STATUS Register */
__IO uint32_t src; /**< <tt>\b 0x008:</tt> DMA SRC Register */
__IO uint32_t dst; /**< <tt>\b 0x00C:</tt> DMA DST Register */
__IO uint32_t cnt; /**< <tt>\b 0x010:</tt> DMA CNT Register */
__IO uint32_t srcrld; /**< <tt>\b 0x014:</tt> DMA SRCRLD Register */
__IO uint32_t dstrld; /**< <tt>\b 0x018:</tt> DMA DSTRLD Register */
__IO uint32_t cntrld; /**< <tt>\b 0x01C:</tt> DMA CNTRLD Register */
} mxc_dma_reva_ch_regs_t;
typedef struct {
@ -110,14 +109,14 @@ typedef struct {
* @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address.
* @{
*/
#define MXC_R_DMA_REVA_CTRL ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
#define MXC_R_DMA_REVA_STATUS ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */
#define MXC_R_DMA_REVA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */
#define MXC_R_DMA_REVA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */
#define MXC_R_DMA_REVA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */
#define MXC_R_DMA_REVA_SRCRLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */
#define MXC_R_DMA_REVA_DSTRLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */
#define MXC_R_DMA_REVA_CNTRLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */
#define MXC_R_DMA_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
#define MXC_R_DMA_REVA_STATUS ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */
#define MXC_R_DMA_REVA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */
#define MXC_R_DMA_REVA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */
#define MXC_R_DMA_REVA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */
#define MXC_R_DMA_REVA_SRCRLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */
#define MXC_R_DMA_REVA_DSTRLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */
#define MXC_R_DMA_REVA_CNTRLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */
#define MXC_R_DMA_REVA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */
#define MXC_R_DMA_REVA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */
#define MXC_R_DMA_REVA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */

16
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_common.c
View File

@ -1,10 +1,10 @@
/**
* @file flc.h
* @brief Flash Controler driver.
* @file flc_common.c
* @brief Common functions for the flash controller drivers.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include <string.h>
@ -43,6 +42,7 @@
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "flc.h"
#include "flc_common.h"
#include "stdlib.h"
//******************************************************************************
@ -56,7 +56,6 @@ int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t* data)
{
volatile uint32_t *ptr;
for (ptr = (uint32_t *)address; ptr < (((uint32_t *)(address)) + length); ptr++, data++) {
if (*ptr != *data) {
return E_BAD_STATE;
@ -84,7 +83,6 @@ int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t* buffer)
// Align the address to a word boundary and read/write if we have to
if (address & 0x3) {
// Figure out how many bytes we have to write to round up the address
bytes_written = 4 - (address & 0x3);
@ -128,7 +126,6 @@ int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t* buffer)
length -= 16;
buffer8 += 16;
}
}
while (length >= 4) {
@ -167,4 +164,3 @@ void MXC_FLC_Com_Read(int address, void* buffer, int len)
{
memcpy(buffer, (void *)address, len);
}

22
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_common.h
View File

@ -1,11 +1,11 @@
/**
* @file flc.h
* @brief Flash Controller driver.
* @file flc_common.h
* @brief Common functions for the flash controller driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -35,9 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_COMMON_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_COMMON_H_
/* **** Includes **** */
#include "mxc_sys.h"
@ -54,8 +55,6 @@ extern "C" {
/***** Definitions *****/
/***** Function Prototypes *****/
int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t *data);
@ -64,9 +63,14 @@ int MXC_FLC_Com_Write (uint32_t address, uint32_t length, uint32_t *buffer);
void MXC_FLC_Com_Read(int address, void *buffer, int len);
/**@} end of group flc */
volatile uint32_t *MXC_FLC_GetWELR(uint32_t address, uint32_t page_num);
volatile uint32_t *MXC_FLC_GetRLR(uint32_t address, uint32_t page_num);
/**@} end of group flc */
#ifdef __cplusplus
}
#endif
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_COMMON_H_

162
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_me15.c
View File

@ -1,10 +1,10 @@
/**
* @file flc.h
* @file flc_me15.c
* @brief Flash Controler driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include <string.h>
@ -43,7 +42,7 @@
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "flc.h"
#include "flc_revb.h"
#include "flc_reva.h"
#include "flc_common.h"
#include "ecc_regs.h" // For ECCEN registers.
#include "mcr_regs.h" // For ECCEN registers.
@ -55,21 +54,17 @@ void MXC_FLC_ME15_Flash_Operation(void)
MXC_GCR->sysctrl |= MXC_F_GCR_SYSCTRL_ICC0_FLUSH;
/* Wait for flush to complete */
while (MXC_GCR->sysctrl & MXC_F_GCR_SYSCTRL_ICC0_FLUSH) {
}
while (MXC_GCR->sysctrl & MXC_F_GCR_SYSCTRL_ICC0_FLUSH) {}
}
//******************************************************************************
int MXC_FLC_ME15_GetByAddress(mxc_flc_regs_t **flc, uint32_t addr)
{
if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) {
*flc = MXC_FLC0;
}
else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
} else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
*flc = MXC_FLC0;
}
else {
} else {
return E_BAD_PARAM;
}
@ -81,13 +76,11 @@ int MXC_FLC_ME15_GetPhysicalAddress (uint32_t addr, uint32_t *result)
{
if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) {
*result = addr - MXC_FLASH_MEM_BASE;
}
else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
} else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
/* For ME15, the info block base was located at the next power of 2 address beyond the main flash.
The ME15 ends at 0x5FFFF, so the info block starts at 0x80000. */
*result = (addr & (MXC_INFO_MEM_SIZE - 1)) + 0x80000;
}
else {
} else {
return E_BAD_PARAM;
}
@ -95,12 +88,12 @@ int MXC_FLC_ME15_GetPhysicalAddress (uint32_t addr, uint32_t *result)
}
//******************************************************************************
int MXC_FLC_Init()
{
return E_NO_ERROR;
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section = ".flashprog"
#else
@ -108,15 +101,16 @@ __attribute__((section(".flashprog")))
#endif
int MXC_FLC_Busy(void)
{
return MXC_FLC_RevB_Busy();
return MXC_FLC_RevA_Busy();
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section = ".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
int MXC_FLC_ME15_PageErase(uint32_t address)
int MXC_FLC_PageErase(uint32_t address)
{
int err;
uint32_t addr;
@ -131,20 +125,21 @@ int MXC_FLC_ME15_PageErase(uint32_t address)
return err;
}
err = MXC_FLC_RevB_PageErase ((mxc_flc_revb_regs_t*) flc, addr);
err = MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t *)flc, addr);
// Flush the cache
MXC_FLC_ME15_Flash_Operation();
return err;
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section = ".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
// make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_ME15_Write128(uint32_t address, uint32_t* data)
int MXC_FLC_Write128(uint32_t address, uint32_t *data)
{
int err;
mxc_flc_regs_t *flc = NULL;
@ -164,7 +159,7 @@ int MXC_FLC_ME15_Write128(uint32_t address, uint32_t* data)
return err;
}
if((err= MXC_FLC_RevB_Write128 ((mxc_flc_revb_regs_t*) flc, addr, data)) != E_NO_ERROR) {
if ((err = MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t *)flc, addr, data)) != E_NO_ERROR) {
return err;
}
@ -179,7 +174,7 @@ int MXC_FLC_ME15_Write128(uint32_t address, uint32_t* data)
}
//******************************************************************************
int MXC_FLC_ME15_Write32(uint32_t address, uint32_t data)
int MXC_FLC_Write32(uint32_t address, uint32_t data)
{
uint32_t addr, aligned;
int err;
@ -203,22 +198,21 @@ int MXC_FLC_ME15_Write32(uint32_t address, uint32_t data)
}
if (MXC_ECC->en & MXC_F_ECC_EN_FLASH) {
return E_BAD_STATE;
}
return MXC_FLC_RevB_Write32 ((mxc_flc_revb_regs_t*) flc, address, data, addr);
return MXC_FLC_RevA_Write32Using128((mxc_flc_reva_regs_t *)flc, address, data, addr);
}
int MXC_FLC_ME15_MassErase(void)
//******************************************************************************
int MXC_FLC_MassErase(void)
{
int err, i;
mxc_flc_regs_t *flc;
for (i = 0; i < MXC_FLC_INSTANCES; i++) {
flc = MXC_FLC_GET_FLC(i);
err = MXC_FLC_RevB_MassErase((mxc_flc_revb_regs_t*) flc);
err = MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t *)flc);
if (err != E_NO_ERROR) {
return err;
@ -228,10 +222,10 @@ int MXC_FLC_ME15_MassErase(void)
}
return E_NO_ERROR;
}
int MXC_FLC_ME15_UnlockInfoBlock(uint32_t address)
//******************************************************************************
int MXC_FLC_UnlockInfoBlock(uint32_t address)
{
int err;
mxc_flc_regs_t *flc;
@ -240,9 +234,11 @@ int MXC_FLC_ME15_UnlockInfoBlock(uint32_t address)
return err;
}
return MXC_FLC_RevB_UnlockInfoBlock ((mxc_flc_revb_regs_t*) flc, address);
return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t *)flc, address);
}
int MXC_FLC_ME15_LockInfoBlock(uint32_t address)
//******************************************************************************
int MXC_FLC_LockInfoBlock(uint32_t address)
{
int err;
mxc_flc_regs_t *flc;
@ -251,64 +247,102 @@ int MXC_FLC_ME15_LockInfoBlock(uint32_t address)
return err;
}
return MXC_FLC_RevB_LockInfoBlock ((mxc_flc_revb_regs_t*) flc, address);
}
/* ****************************************************************************** */
int MXC_FLC_MassErase(void)
{
return MXC_FLC_ME15_MassErase();
}
int MXC_FLC_PageErase(uint32_t address)
{
return MXC_FLC_ME15_PageErase(address);
}
int MXC_FLC_Write32(uint32_t address, uint32_t data)
{
return MXC_FLC_ME15_Write32(address, data);
}
int MXC_FLC_Write128(uint32_t address, uint32_t* data)
{
return MXC_FLC_ME15_Write128(address, data);
return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t *)flc, address);
}
//******************************************************************************
int MXC_FLC_Write(uint32_t address, uint32_t length, uint32_t *buffer)
{
return MXC_FLC_Com_Write(address, length, buffer);
}
//******************************************************************************
void MXC_FLC_Read(int address, void *buffer, int len)
{
MXC_FLC_Com_Read(address, buffer, len);
}
//******************************************************************************
int MXC_FLC_EnableInt(uint32_t flags)
{
return MXC_FLC_RevB_EnableInt(flags);
return MXC_FLC_RevA_EnableInt(flags);
}
//******************************************************************************
int MXC_FLC_DisableInt(uint32_t flags)
{
return MXC_FLC_RevB_DisableInt(flags);
return MXC_FLC_RevA_DisableInt(flags);
}
//******************************************************************************
int MXC_FLC_GetFlags(void)
{
return MXC_FLC_RevB_GetFlags();
return MXC_FLC_RevA_GetFlags();
}
//******************************************************************************
int MXC_FLC_ClearFlags(uint32_t flags)
{
return MXC_FLC_RevB_ClearFlags(flags);
return MXC_FLC_RevA_ClearFlags(flags);
}
int MXC_FLC_UnlockInfoBlock(uint32_t address)
//******************************************************************************
int MXC_FLC_BlockPageWrite(uint32_t address)
{
return MXC_FLC_ME15_UnlockInfoBlock(address);
if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) {
return E_INVALID;
}
int MXC_FLC_LockInfoBlock(uint32_t address)
{
return MXC_FLC_ME15_LockInfoBlock(address);
return MXC_FLC_RevA_BlockPageWrite(address, MXC_FLASH_MEM_BASE);
}
//******************************************************************************
int MXC_FLC_BlockPageRead(uint32_t address)
{
if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) {
return E_INVALID;
}
return MXC_FLC_RevA_BlockPageRead(address, MXC_FLASH_MEM_BASE);
}
//******************************************************************************
volatile uint32_t *MXC_FLC_GetWELR(uint32_t address, uint32_t page_num)
{
uint32_t reg_num;
reg_num = page_num >>
5; // Divide by 32 to get WELR register number containing the page lock bit
if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) {
return NULL;
}
switch (reg_num) {
case 0:
return &(MXC_FLC0->welr0);
case 1:
return &(MXC_FLC0->welr1);
}
return NULL;
}
//******************************************************************************
volatile uint32_t *MXC_FLC_GetRLR(uint32_t address, uint32_t page_num)
{
uint32_t reg_num;
reg_num = page_num >> 5; // Divide by 32 to get RLR register number containing the page lock bit
if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) {
return NULL;
}
switch (reg_num) {
case 0:
return &(MXC_FLC0->rlr0);
case 1:
return &(MXC_FLC0->rlr1);
}
return NULL;
}

126
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva.c
View File

@ -3,8 +3,8 @@
* @brief Flash Controler driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include <string.h>
@ -69,7 +68,8 @@ __attribute__((section(".flashprog")))
#endif
static int MXC_busy_flc(mxc_flc_reva_regs_t *flc)
{
return (flc->ctrl & (MXC_F_FLC_REVA_CTRL_WR | MXC_F_FLC_REVA_CTRL_ME | MXC_F_FLC_REVA_CTRL_PGE));
return (flc->ctrl &
(MXC_F_FLC_REVA_CTRL_WR | MXC_F_FLC_REVA_CTRL_ME | MXC_F_FLC_REVA_CTRL_PGE));
}
//******************************************************************************
@ -137,13 +137,14 @@ int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc)
}
/* Write mass erase code */
flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL;
flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) |
MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL;
/* Issue mass erase command */
flc->ctrl |= MXC_F_FLC_REVA_CTRL_ME;
/* Wait until flash operation is complete */
while (MXC_busy_flc(flc));
while (MXC_busy_flc(flc)) {}
/* Lock flash */
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
@ -172,13 +173,14 @@ int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc, uint32_t addr)
}
/* Write page erase code */
flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE;
flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) |
MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE;
/* Issue page erase command */
flc->addr = addr;
flc->ctrl |= MXC_F_FLC_REVA_CTRL_PGE;
/* Wait until flash operation is complete */
while (MXC_FLC_Busy());
while (MXC_busy_flc(flc)) {}
/* Lock flash */
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
@ -192,7 +194,58 @@ int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc, uint32_t addr)
return E_NO_ERROR;
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section = ".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
// make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_RevA_Write32(mxc_flc_reva_regs_t *flc, uint32_t logicAddr, uint32_t data,
uint32_t physicalAddr)
{
int err;
// Address checked if it is byte addressable
if (logicAddr & 0x3) {
return E_BAD_PARAM;
}
// Check if the location trying to be written has 1's in to be written to 0's
if ((*(uint32_t *)logicAddr & data) != data) {
return E_BAD_STATE;
}
// Align address to 32-bit word
logicAddr = logicAddr & 0xfffffffc;
if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) {
return err;
}
// write 32-bits
flc->ctrl |= MXC_F_FLC_REVA_CTRL_WDTH;
// write the data
flc->addr = logicAddr;
flc->data[0] = data;
flc->ctrl |= MXC_F_FLC_REVA_CTRL_WR;
/* Wait until flash operation is complete */
while ((flc->ctrl & MXC_F_FLC_REVA_CTRL_PEND) != 0) {}
while (MXC_busy_flc(flc)) {}
/* Lock flash */
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
/* Check access violations */
if (flc->intr & MXC_F_FLC_REVA_INTR_AF) {
flc->intr &= ~MXC_F_FLC_REVA_INTR_AF;
return E_BAD_STATE;
}
return E_NO_ERROR;
}
//******************************************************************************
#if IAR_PRAGMAS
@ -201,7 +254,8 @@ int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc, uint32_t addr)
__attribute__((section(".flashprog")))
#endif
// make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t* flc, uint32_t logicAddr, uint32_t data, uint32_t physicalAddr)
int MXC_FLC_RevA_Write32Using128(mxc_flc_reva_regs_t *flc, uint32_t logicAddr, uint32_t data,
uint32_t physicalAddr)
{
int err, i = 0;
uint32_t byte;
@ -237,14 +291,11 @@ int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t* flc, uint32_t logicAddr, uint32_t
if (byte < 4) {
current_data[0] = data;
}
else if (byte < 8) {
} else if (byte < 8) {
current_data[1] = data;
}
else if (byte < 12) {
} else if (byte < 12) {
current_data[2] = data;
}
else {
} else {
current_data[3] = data;
}
@ -367,7 +418,8 @@ int MXC_FLC_RevA_ClearFlags(uint32_t mask)
//******************************************************************************
int MXC_FLC_RevA_UnlockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address)
{
if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
if ((address < MXC_INFO_MEM_BASE) ||
(address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
return E_BAD_PARAM;
}
@ -385,11 +437,49 @@ int MXC_FLC_RevA_UnlockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address)
//******************************************************************************
int MXC_FLC_RevA_LockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address)
{
if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
if ((address < MXC_INFO_MEM_BASE) ||
(address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
return E_BAD_PARAM;
}
flc->actrl = 0xDEADBEEF;
return E_NO_ERROR;
}
//******************************************************************************
int MXC_FLC_RevA_BlockPageWrite(uint32_t address, uint32_t bank_base)
{
uint32_t page_num;
page_num = address - bank_base; // Get page number in flash bank
page_num /= MXC_FLASH_PAGE_SIZE;
volatile uint32_t *welr = MXC_FLC_GetWELR(
address, page_num); // Get pointer to WELR register containing corresponding page bit
while (page_num > 31) { // Set corresponding bit in WELR register
page_num -= 32;
}
*welr = (1 << page_num);
return E_NO_ERROR;
}
//******************************************************************************
int MXC_FLC_RevA_BlockPageRead(uint32_t address, uint32_t bank_base)
{
uint32_t page_num;
page_num = address - bank_base; // Get page number in flash bank
page_num /= MXC_FLASH_PAGE_SIZE;
volatile uint32_t *rlr = MXC_FLC_GetRLR(
address, page_num); // Get pointer to RLR register containing corresponding page bit
while (page_num > 31) { // Set corresponding bit in WELR register
page_num -= 32;
}
*rlr = (1 << page_num);
return E_NO_ERROR;
}
/**@} end of group flc */

29
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva.h
View File

@ -1,10 +1,10 @@
/**
* @file flc.h
* @brief Flash Controler driver.
* @file flc_reva.h
* @brief Flash RevA Controller driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_H_
/* **** Includes **** */
#include <string.h>
@ -43,6 +45,7 @@
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "flc.h"
#include "flc_common.h"
#include "flc_reva_regs.h"
/**
@ -62,7 +65,11 @@ int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc);
int MXC_FLC_RevA_PageErase(mxc_flc_reva_regs_t *flc, uint32_t addr);
int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data, uint32_t physicalAddr);
int MXC_FLC_RevA_Write32(mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data,
uint32_t physicalAddr);
int MXC_FLC_RevA_Write32Using128(mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data,
uint32_t physicalAddr);
int MXC_FLC_RevA_Write128(mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data);
@ -81,9 +88,15 @@ int MXC_FLC_RevA_ClearFlags (uint32_t mask);
int MXC_FLC_RevA_UnlockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address);
int MXC_FLC_RevA_LockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address);
/**@} end of group flc */
int MXC_FLC_RevA_BlockPageWrite(uint32_t address, uint32_t bank_base);
int MXC_FLC_RevA_BlockPageRead(uint32_t address, uint32_t bank_base);
/**@} end of group flc */
#ifdef __cplusplus
}
#endif
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_H_

13
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva_regs.h
View File

@ -3,8 +3,8 @@
* @brief Registers, Bit Masks and Bit Positions for the FLC_REVA Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _FLC_REVA_REGS_H_
#define _FLC_REVA_REGS_H_
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -243,4 +242,4 @@ typedef struct {
}
#endif
#endif /* _FLC_REVA_REGS_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_

154
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_revb.c
View File

@ -1,154 +0,0 @@
/**
* @file flc.h
* @brief Flash Controler driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
/* **** Includes **** */
#include <string.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "flc.h"
#include "flc_revb.h"
#include "flc_reva.h"
/**
* @ingroup flc
* @{
*/
/* **** Definitions **** */
/* **** Globals **** */
/* **** Functions **** */
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
int MXC_FLC_RevB_Busy(void)
{
return MXC_FLC_RevA_Busy();
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
int MXC_FLC_RevB_MassErase(mxc_flc_revb_regs_t* flc)
{
return MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t*)flc);
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
int MXC_FLC_RevB_PageErase(mxc_flc_revb_regs_t* flc, uint32_t addr)
{
return MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t*)flc,addr);
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
// make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_RevB_Write32(mxc_flc_revb_regs_t* flc, uint32_t logicAddr, uint32_t data, uint32_t physicalAddr)
{
return MXC_FLC_RevA_Write32((mxc_flc_reva_regs_t*)flc, logicAddr, data, physicalAddr);
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
// make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_RevB_Write128(mxc_flc_revb_regs_t* flc, uint32_t addr, uint32_t* data)
{
return MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t*)flc, addr, data);
}
//******************************************************************************
int MXC_FLC_RevB_EnableInt(uint32_t mask)
{
return MXC_FLC_RevA_EnableInt(mask);
}
//******************************************************************************
int MXC_FLC_RevB_DisableInt(uint32_t mask)
{
return MXC_FLC_RevA_DisableInt(mask);
}
//******************************************************************************
int MXC_FLC_RevB_GetFlags(void)
{
return MXC_FLC_RevA_GetFlags();
}
//******************************************************************************
int MXC_FLC_RevB_ClearFlags(uint32_t mask)
{
return MXC_FLC_RevA_ClearFlags(mask);
}
//******************************************************************************
int MXC_FLC_RevB_UnlockInfoBlock(mxc_flc_revb_regs_t* flc, uint32_t address)
{
return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t*)flc, address);
}
//******************************************************************************
int MXC_FLC_RevB_LockInfoBlock(mxc_flc_revb_regs_t* flc, uint32_t address)
{
return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t*)flc, address);
}
/**@} end of group flc */

85
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_revb.h
View File

@ -1,85 +0,0 @@
/**
* @file flc.h
* @brief Flash Controler driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
/* **** Includes **** */
#include <string.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "flc_revb_regs.h"
#include "mcr_regs.h" // For ECCEN registers.
/**
* @ingroup flc
* @{
*/
/* **** Definitions **** */
/* **** Globals **** */
/* **** Functions **** */
int MXC_FLC_RevB_Busy (void);
int MXC_FLC_RevB_MassErase (mxc_flc_revb_regs_t *flc);
int MXC_FLC_RevB_PageErase (mxc_flc_revb_regs_t *flc,uint32_t addr);
int MXC_FLC_RevB_Write32 (mxc_flc_revb_regs_t *flc, uint32_t locgialAddr, uint32_t data, uint32_t physicalAddr);
int MXC_FLC_RevB_Write128 (mxc_flc_revb_regs_t *flc, uint32_t addr, uint32_t *data);
int MXC_FLC_RevB_EnableInt (uint32_t mask);
int MXC_FLC_RevB_DisableInt (uint32_t mask);
int MXC_FLC_RevB_GetFlags (void);
int MXC_FLC_RevB_ClearFlags (uint32_t mask);
int MXC_FLC_RevB_UnlockInfoBlock (mxc_flc_revb_regs_t *flc, uint32_t address);
int MXC_FLC_RevB_LockInfoBlock (mxc_flc_revb_regs_t *flc, uint32_t address);
/**@} end of group flc */
#ifdef __cplusplus
}
#endif

301
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_revb_regs.h
View File

@ -1,301 +0,0 @@
/**
* @file flc_revb_regs.h
* @brief Registers, Bit Masks and Bit Positions for the FLC_REVB Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _FLC_REVB_REGS_H_
#define _FLC_REVB_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup flc_revb
* @defgroup flc_revb_registers FLC_REVB_Registers
* @brief Registers, Bit Masks and Bit Positions for the FLC_REVB Peripheral Module.
* @details Flash Memory Control.
*/
/**
* @ingroup flc_revb_registers
* Structure type to access the FLC_REVB Registers.
*/
typedef struct {
__IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC_REVB ADDR Register */
__IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC_REVB CLKDIV Register */
__IO uint32_t ctrl; /**< <tt>\b 0x08:</tt> FLC_REVB CTRL Register */
__R uint32_t rsv_0xc_0x23[6];
__IO uint32_t intr; /**< <tt>\b 0x024:</tt> FLC_REVB INTR Register */
__IO uint32_t eccdata; /**< <tt>\b 0x028:</tt> FLC_REVB ECCDATA Register */
__R uint32_t rsv_0x2c;
__IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC_REVB DATA Register */
__O uint32_t actrl; /**< <tt>\b 0x40:</tt> FLC_REVB ACTRL Register */
__R uint32_t rsv_0x44_0x7f[15];
__IO uint32_t welr0; /**< <tt>\b 0x80:</tt> FLC_REVB WELR0 Register */
__R uint32_t rsv_0x84;
__IO uint32_t welr1; /**< <tt>\b 0x88:</tt> FLC_REVB WELR1 Register */
__R uint32_t rsv_0x8c;
__IO uint32_t rlr0; /**< <tt>\b 0x90:</tt> FLC_REVB RLR0 Register */
__R uint32_t rsv_0x94;
__IO uint32_t rlr1; /**< <tt>\b 0x98:</tt> FLC_REVB RLR1 Register */
} mxc_flc_revb_regs_t;
/* Register offsets for module FLC_REVB */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_Register_Offsets Register Offsets
* @brief FLC_REVB Peripheral Register Offsets from the FLC_REVB Base Peripheral Address.
* @{
*/
#define MXC_R_FLC_REVB_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0000</tt> */
#define MXC_R_FLC_REVB_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0004</tt> */
#define MXC_R_FLC_REVB_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0008</tt> */
#define MXC_R_FLC_REVB_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0024</tt> */
#define MXC_R_FLC_REVB_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0028</tt> */
#define MXC_R_FLC_REVB_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0030</tt> */
#define MXC_R_FLC_REVB_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0040</tt> */
#define MXC_R_FLC_REVB_WELR0 ((uint32_t)0x00000080UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0080</tt> */
#define MXC_R_FLC_REVB_WELR1 ((uint32_t)0x00000088UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0088</tt> */
#define MXC_R_FLC_REVB_RLR0 ((uint32_t)0x00000090UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0090</tt> */
#define MXC_R_FLC_REVB_RLR1 ((uint32_t)0x00000098UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0098</tt> */
/**@} end of group flc_revb_registers */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_ADDR FLC_REVB_ADDR
* @brief Flash Write Address.
* @{
*/
#define MXC_F_FLC_REVB_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
#define MXC_F_FLC_REVB_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
/**@} end of group FLC_REVB_ADDR_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_CLKDIV FLC_REVB_CLKDIV
* @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1
* MHz clock for Flash controller.
* @{
*/
#define MXC_F_FLC_REVB_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
#define MXC_F_FLC_REVB_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_REVB_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
/**@} end of group FLC_REVB_CLKDIV_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_CTRL FLC_REVB_CTRL
* @brief Flash Control Register.
* @{
*/
#define MXC_F_FLC_REVB_CTRL_WR_POS 0 /**< CTRL_WR Position */
#define MXC_F_FLC_REVB_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_WR_POS)) /**< CTRL_WR Mask */
#define MXC_F_FLC_REVB_CTRL_ME_POS 1 /**< CTRL_ME Position */
#define MXC_F_FLC_REVB_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_ME_POS)) /**< CTRL_ME Mask */
#define MXC_F_FLC_REVB_CTRL_PGE_POS 2 /**< CTRL_PGE Position */
#define MXC_F_FLC_REVB_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_PGE_POS)) /**< CTRL_PGE Mask */
#define MXC_F_FLC_REVB_CTRL_WDTH_POS 4 /**< CTRL_WDTH Position */
#define MXC_F_FLC_REVB_CTRL_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_WDTH_POS)) /**< CTRL_WDTH Mask */
#define MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */
#define MXC_F_FLC_REVB_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */
#define MXC_V_FLC_REVB_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */
#define MXC_S_FLC_REVB_CTRL_ERASE_CODE_NOP (MXC_V_FLC_REVB_CTRL_ERASE_CODE_NOP << MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */
#define MXC_V_FLC_REVB_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */
#define MXC_S_FLC_REVB_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_REVB_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */
#define MXC_V_FLC_REVB_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */
#define MXC_S_FLC_REVB_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_REVB_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */
#define MXC_F_FLC_REVB_CTRL_PEND_POS 24 /**< CTRL_PEND Position */
#define MXC_F_FLC_REVB_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_PEND_POS)) /**< CTRL_PEND Mask */
#define MXC_F_FLC_REVB_CTRL_LVE_POS 25 /**< CTRL_LVE Position */
#define MXC_F_FLC_REVB_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_LVE_POS)) /**< CTRL_LVE Mask */
#define MXC_F_FLC_REVB_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */
#define MXC_F_FLC_REVB_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_REVB_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */
#define MXC_V_FLC_REVB_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */
#define MXC_S_FLC_REVB_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_REVB_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_REVB_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */
#define MXC_V_FLC_REVB_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */
#define MXC_S_FLC_REVB_CTRL_UNLOCK_LOCKED (MXC_V_FLC_REVB_CTRL_UNLOCK_LOCKED << MXC_F_FLC_REVB_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */
/**@} end of group FLC_REVB_CTRL_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_INTR FLC_REVB_INTR
* @brief Flash Interrupt Register.
* @{
*/
#define MXC_F_FLC_REVB_INTR_DONE_POS 0 /**< INTR_DONE Position */
#define MXC_F_FLC_REVB_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_REVB_INTR_DONE_POS)) /**< INTR_DONE Mask */
#define MXC_F_FLC_REVB_INTR_AF_POS 1 /**< INTR_AF Position */
#define MXC_F_FLC_REVB_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_REVB_INTR_AF_POS)) /**< INTR_AF Mask */
#define MXC_F_FLC_REVB_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */
#define MXC_F_FLC_REVB_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_REVB_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
#define MXC_F_FLC_REVB_INTR_AFIE_POS 9 /**< INTR_AFIE Position */
#define MXC_F_FLC_REVB_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_REVB_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
/**@} end of group FLC_REVB_INTR_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_ECCDATA FLC_REVB_ECCDATA
* @brief ECC Data Register.
* @{
*/
#define MXC_F_FLC_REVB_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */
#define MXC_F_FLC_REVB_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_REVB_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */
#define MXC_F_FLC_REVB_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */
#define MXC_F_FLC_REVB_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_REVB_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */
/**@} end of group FLC_REVB_ECCDATA_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_DATA FLC_REVB_DATA
* @brief Flash Write Data.
* @{
*/
#define MXC_F_FLC_REVB_DATA_DATA_POS 0 /**< DATA_DATA Position */
#define MXC_F_FLC_REVB_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_DATA_DATA_POS)) /**< DATA_DATA Mask */
/**@} end of group FLC_REVB_DATA_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_ACTRL FLC_REVB_ACTRL
* @brief Access Control Register. Writing the ACTRL register with the following values in
* the order shown, allows read and write access to the system and user Information
* block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = 0xa1e34f20; pflc-actrl
* = 0x9608b2c1. When unlocked, a write of any word will disable access to system
* and user information block. Readback of this register is always zero.
* @{
*/
#define MXC_F_FLC_REVB_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */
#define MXC_F_FLC_REVB_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */
/**@} end of group FLC_REVB_ACTRL_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_WELR0 FLC_REVB_WELR0
* @brief WELR0
* @{
*/
#define MXC_F_FLC_REVB_WELR0_WELR0_POS 0 /**< WELR0_WELR0 Position */
#define MXC_F_FLC_REVB_WELR0_WELR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_WELR0_WELR0_POS)) /**< WELR0_WELR0 Mask */
/**@} end of group FLC_REVB_WELR0_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_WELR1 FLC_REVB_WELR1
* @brief WELR1
* @{
*/
#define MXC_F_FLC_REVB_WELR1_WELR1_POS 0 /**< WELR1_WELR1 Position */
#define MXC_F_FLC_REVB_WELR1_WELR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_WELR1_WELR1_POS)) /**< WELR1_WELR1 Mask */
/**@} end of group FLC_REVB_WELR1_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_RLR0 FLC_REVB_RLR0
* @brief RLR0
* @{
*/
#define MXC_F_FLC_REVB_RLR0_RLR0_POS 0 /**< RLR0_RLR0 Position */
#define MXC_F_FLC_REVB_RLR0_RLR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_RLR0_RLR0_POS)) /**< RLR0_RLR0 Mask */
/**@} end of group FLC_REVB_RLR0_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_RLR1 FLC_REVB_RLR1
* @brief RLR1
* @{
*/
#define MXC_F_FLC_REVB_RLR1_RLR1_POS 0 /**< RLR1_RLR1 Position */
#define MXC_F_FLC_REVB_RLR1_RLR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_RLR1_RLR1_POS)) /**< RLR1_RLR1 Mask */
/**@} end of group FLC_REVB_RLR1_Register */
#ifdef __cplusplus
}
#endif
#endif /* _FLC_REVB_REGS_H_ */

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