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Synchronize upstream changes - May 2023 edition (#160) 

* fix STM32L1 FLASH_SIZE for cat.3 devices with DEV_ID 0x436

* Fix mesh connect semaphore not releasing causing blockage

* Add support of NSAPI_ICMP sockets in Nanostack

* STM32F1: add MCU_STM32F103xD support

* STM32F1: add MCU_STM32F103xG support

* test: Disable failing tests due to echo server

Some tests are failing as echo.mbedcloudtesting.com is not serving TLS
requests anymore.

Signed-off-by: Saheer Babu <saheer.babu@arm.com>

* Check CAN DLC length value

* Fix default interface ID only being used partially

If user sets the default interface ID for a socket (e.g. using setsockopt
with SOCKET_INTERFACE_SELECT), the default interface should take over
other interface selection mechanisms as a interface is bound to the socket.
This applies for both IPv6 local and global scopes for unicast messages
but not for multicast messages as these are bound to a multicast interface
using SOCKET_IPV6_MULTICAST_IF socket option.

* Targets: NXP: IMXRT: Fixed GCC_ARM lds syntax.

Signed-off-by: Yilin Sun <imi415@imi.moe>

* CAN: read only up to 8 bytes

If HAL implementation writes more than 8 bytes of data, error immediately.
CANMessage defines only 8 bytes of data, lenght cannot be > 8.

This fixes https://github.com/ARMmbed/mbed-os/issues/15361

Signed-off-by: Martin Kojtal <martin.kojtal@arm.com>

* STM32F303xC: add RAM_CCM in GCC linker script

* fix(drivers/emac): Remove incorrect RMII RX ER initialization

* fix(drivers/emac): Add missing SPDX indetifier to ST driver files

* fixed compiler inline issue

* Update Mbed version block

* removed HSE speed limitation for STM32G431RB

* Added HSE range validation for STM32g431xB

* added support for 4, 8 and 16MHz

* M487: Remove unused variable 'u32EscapeFrame'

Remove unused variable 'u32EscapeFrame' in BSP m480_ccap.h to avoid warnings

* force FIFO IRQ for FDCan RX on H7

* Add hardware CRC support to STM32G4

* add support for Nucleo-H745ZI

* Update MAX32670 peripheral drivers with final ones that use by SDK

Signed-off-by: Sadik.Ozer <sadik.ozer@analog.com>

* MAX32670 apply mbed required changes on peripheral drivers

Signed-off-by: Sadik.Ozer <sadik.ozer@analog.com>

* M467: Support CAN bus

1.  Update BSP CANFD driver
2.  Notes for implementation
    (1) Each CANFD instance supports two IRQ lines. Use only line 0. Line 1 is not used.
    (2) For Rx disabling multiple filter handles,
        1)  Map all filter handles to filter handle 0
        2)  Use Rx FIFO 0 for filter handle 0
    (3) For Rx enabling multiple filter handles,
        1)  Use Rx FIFO 0 for filter handle 0
        2)  Use Rx FIFO 1 for filter handle through first invoking can_filter()
        3)  Use dedicated Rx Buffer for other filter handles
        NOTE: H/W supports mask on Rx FIFO 0/1 but not on dedicated Rx Buffer.
    (4) For Tx, use only dedicated Tx Buffer. BSP CANFD driver doesn't support Tx FIFO/Queue.
    (5) Support no CAN FD.

* Fix 'new[]' array freed with 'delete'

The array _scratch_buf is allocated using new[] in line 761 of
mbed-os/storage/kvstore/securestore/source/SecureStore.cpp.
But it was freed using delete.

* Define default parameters of functions of derived class the same as the base class

The member function bringup() of class ThreadInterface redefines
parameter stack's default value to IPV6_STACK from the inherited default value
DEFAULT_STACK (in Interface).
The default value will be resolved statically, not by dispatch, so this
can cause confusion.
Similar arguments apply to LoWPANNDInterface and WisunInterface.

* Avoid calling virtual functions from constructors and destructors

Virtual functions are resolved statically (not dynamically) in
constructors and destructors for the same class. The call should be made
explicitly static by qualifying it using the scope resolution operator.

* Fix potentially overrunning write of sprintf

Format string "%d" requires 12 bytes (including the null terminator).
Also, use snprintf instead of sprintf to prevent buffer overflow.

* Fix system_clock.c location

Signed-off-by: Jasper Jonker <jasper.jonker@wingtra.com>

* Fix variable name

Signed-off-by: Jasper <jasper.jonker@wingtra.com>

* Change storage-class of secret_buf to static

Storing the address of a local variable (`secret_buf`)
in non-local memory (`prf_ptr->secret`) can cause a
dangling pointer bug if the address is used after the function returns.

* fix compiling errors of FATFileSystem when exFAT was enabled

* Add OSPI support for STM32H7

* Nuvoton: Enable extending sampling time for ADC/EADC

For all Nuvoton targets, enable extending sampling time in ADC/EADC clocks on per-pin basis.

---------

Signed-off-by: Saheer Babu <saheer.babu@arm.com>
Signed-off-by: Yilin Sun <imi415@imi.moe>
Signed-off-by: Martin Kojtal <martin.kojtal@arm.com>
Signed-off-by: Sadik.Ozer <sadik.ozer@analog.com>
Signed-off-by: Jasper Jonker <jasper.jonker@wingtra.com>
Signed-off-by: Jasper <jasper.jonker@wingtra.com>
Co-authored-by: caodd <caodd1993@qq.com>
Co-authored-by: YannCharbon <yann.charbon@ik.me>
Co-authored-by: Jerome Coutant <jerome.coutant@st.com>
Co-authored-by: Saheer Babu <saheer.babu@arm.com>
Co-authored-by: Martyx00 <martin.petran@protonmail.com>
Co-authored-by: Yilin Sun <imi415@imi.moe>
Co-authored-by: Martin Kojtal <martin.kojtal@arm.com>
Co-authored-by: akiroz <akiroz.vectis@gmail.com>
Co-authored-by: Charles <hallard04@free.fr>
Co-authored-by: Leonard Chiang <leochiang2002@gmail.com>
Co-authored-by: Chun-Chieh Li <ccli8@nuvoton.com>
Co-authored-by: jmcloud <jmcloud@tesla.com>
Co-authored-by: Augusto Zanellato <augusto.zanellato@gmail.com>
Co-authored-by: Sadik.Ozer <sadik.ozer@analog.com>
Co-authored-by: Mingjie Shen <shen497@purdue.edu>
Co-authored-by: Jasper Jonker <jasper.jonker@wingtra.com>
Co-authored-by: wdx04 <wdx04@outlook.com>
pull/15437/head
Jamie Smith 2023-05-17 01:18:28 -07:00 committed by GitHub
parent 6e2e7b9414
commit 3f7d67c64c
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
196 changed files with 14224 additions and 9699 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp
View File

@ -186,8 +186,8 @@ retry_open:
} }
} }
if (strcmp(paramTag, "conId") == 0) { if (strcmp(paramTag, "conId") == 0) {
char buf[10]; char buf[12];
std::sprintf(buf, "%d", _cid); std::snprintf(buf, sizeof(buf), "%d", _cid);
if (strcmp(paramValue, buf) == 0) { if (strcmp(paramValue, buf) == 0) {
foundConIdType = true; foundConIdType = true;
} }

11
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/stm32f2_eth_init.c
View File

@ -1,6 +1,7 @@
/* mbed Microcontroller Library /* mbed Microcontroller Library
* Copyright (c) 2022, STMicroelectronics * Copyright (c) 2022, STMicroelectronics
* All rights reserved. * All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -53,7 +54,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7 RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5 RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2 RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11 RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13 RMII_MII_TXD1 ---------------------> PB13
@ -74,8 +75,8 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PG2, PG11 and PG13 */ /* Configure PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13; GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
/* Enable the Ethernet global Interrupt */ /* Enable the Ethernet global Interrupt */
@ -103,7 +104,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7 RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5 RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2 RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11 RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13 RMII_MII_TXD1 ---------------------> PB13
@ -111,7 +112,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13); HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13);
/* Disable the Ethernet global Interrupt */ /* Disable the Ethernet global Interrupt */
NVIC_DisableIRQ(ETH_IRQn); NVIC_DisableIRQ(ETH_IRQn);

6
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/stm32f4_eth_init.c
View File

@ -2,7 +2,7 @@
* Copyright (c) 2022, STMicroelectronics * Copyright (c) 2022, STMicroelectronics
* All rights reserved. * All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: BSD-3-Clause
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
@ -50,7 +50,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7 RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5 RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PB11 RMII_MII_TX_EN --------------------> PB11
RMII_MII_TXD0 ---------------------> PB12 RMII_MII_TXD0 ---------------------> PB12
RMII_MII_TXD1 ---------------------> PB13 RMII_MII_TXD1 ---------------------> PB13
@ -96,7 +96,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7 RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5 RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PB11 RMII_MII_TX_EN --------------------> PB11
RMII_MII_TXD0 ---------------------> PB12 RMII_MII_TXD0 ---------------------> PB12
RMII_MII_TXD1 ---------------------> PB13 RMII_MII_TXD1 ---------------------> PB13

11
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_init.c
View File

@ -1,6 +1,7 @@
/* mbed Microcontroller Library /* mbed Microcontroller Library
* Copyright (c) 2022, STMicroelectronics * Copyright (c) 2022, STMicroelectronics
* All rights reserved. * All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -53,7 +54,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7 RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5 RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2 RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11 RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13 RMII_MII_TXD1 ---------------------> PB13
@ -74,8 +75,8 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PG2, PG11 and PG13 */ /* Configure PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13; GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
/* Enable the Ethernet global Interrupt */ /* Enable the Ethernet global Interrupt */
@ -103,7 +104,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7 RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5 RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2 RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11 RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13 RMII_MII_TXD1 ---------------------> PB13
@ -111,7 +112,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13); HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13);
/* Disable the Ethernet global Interrupt */ /* Disable the Ethernet global Interrupt */
NVIC_DisableIRQ(ETH_IRQn); NVIC_DisableIRQ(ETH_IRQn);

11
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/stm32f4_eth_init.c
View File

@ -1,6 +1,7 @@
/* mbed Microcontroller Library /* mbed Microcontroller Library
* Copyright (c) 2022, STMicroelectronics * Copyright (c) 2022, STMicroelectronics
* All rights reserved. * All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -53,7 +54,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7 RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5 RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2 RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11 RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13 RMII_MII_TXD1 ---------------------> PB13
@ -74,8 +75,8 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PG2, PG11 and PG13 */ /* Configure PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13; GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
/* Enable the Ethernet global Interrupt */ /* Enable the Ethernet global Interrupt */
@ -103,7 +104,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7 RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5 RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2 RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11 RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13 RMII_MII_TXD1 ---------------------> PB13
@ -111,7 +112,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13); HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13);
/* Disable the Ethernet global Interrupt */ /* Disable the Ethernet global Interrupt */
NVIC_DisableIRQ(ETH_IRQn); NVIC_DisableIRQ(ETH_IRQn);

11
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7_eth_init.c
View File

@ -1,6 +1,7 @@
/* mbed Microcontroller Library /* mbed Microcontroller Library
* Copyright (c) 2022, STMicroelectronics * Copyright (c) 2022, STMicroelectronics
* All rights reserved. * All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -57,7 +58,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7 RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5 RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2 RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11 RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PG14 RMII_MII_TXD1 ---------------------> PG14
@ -74,8 +75,8 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PG2, PG11, PG13 and PG14 */ /* Configure PG11, PG13 and PG14 */
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14; GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14;
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
/* Enable the Ethernet global Interrupt */ /* Enable the Ethernet global Interrupt */
@ -103,14 +104,14 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7 RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5 RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2 RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11 RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PG14 RMII_MII_TXD1 ---------------------> PG14
*/ */
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14); HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14);
/* Disable the Ethernet global Interrupt */ /* Disable the Ethernet global Interrupt */
NVIC_DisableIRQ(ETH_IRQn); NVIC_DisableIRQ(ETH_IRQn);

11
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7_eth_init.c
View File

@ -1,6 +1,7 @@
/* mbed Microcontroller Library /* mbed Microcontroller Library
* Copyright (c) 2022, STMicroelectronics * Copyright (c) 2022, STMicroelectronics
* All rights reserved. * All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -48,7 +49,6 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
/* Enable GPIOs clocks */ /* Enable GPIOs clocks */
__HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE();
/** ETH GPIO Configuration /** ETH GPIO Configuration
@ -58,7 +58,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7 RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5 RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PD5 RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11 RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PG14 RMII_MII_TXD1 ---------------------> PG14
@ -75,10 +75,6 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PD5 */
GPIO_InitStructure.Pin = GPIO_PIN_5;
HAL_GPIO_Init(GPIOD, &GPIO_InitStructure);
/* Configure PG11, PG13 and PG14 */ /* Configure PG11, PG13 and PG14 */
GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14; GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14;
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
@ -108,14 +104,13 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7 RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5 RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PD5 RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11 RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PG14 RMII_MII_TXD1 ---------------------> PG14
*/ */
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14); HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14);
/* Disable the Ethernet global Interrupt */ /* Disable the Ethernet global Interrupt */

11
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7_eth_init.c
View File

@ -1,6 +1,7 @@
/* mbed Microcontroller Library /* mbed Microcontroller Library
* Copyright (c) 2022, STMicroelectronics * Copyright (c) 2022, STMicroelectronics
* All rights reserved. * All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -58,7 +59,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7 RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5 RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2 RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11 RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13 RMII_MII_TXD1 ---------------------> PB13
@ -79,8 +80,8 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PG2, PG11 and PG13 */ /* Configure PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13; GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
/* Enable the Ethernet global Interrupt */ /* Enable the Ethernet global Interrupt */
@ -108,7 +109,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7 RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5 RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2 RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11 RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13 RMII_MII_TXD1 ---------------------> PB13
@ -116,7 +117,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13); HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13);
/* Disable the Ethernet global Interrupt */ /* Disable the Ethernet global Interrupt */
NVIC_DisableIRQ(ETH_IRQn); NVIC_DisableIRQ(ETH_IRQn);

11
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F756ZG/stm32f7_eth_init.c
View File

@ -1,6 +1,7 @@
/* mbed Microcontroller Library /* mbed Microcontroller Library
* Copyright (c) 2022, STMicroelectronics * Copyright (c) 2022, STMicroelectronics
* All rights reserved. * All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -58,7 +59,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7 RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5 RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2 RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11 RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13 RMII_MII_TXD1 ---------------------> PB13
@ -79,8 +80,8 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PG2, PG11 and PG13 */ /* Configure PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13; GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
/* Enable the Ethernet global Interrupt */ /* Enable the Ethernet global Interrupt */
@ -108,7 +109,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7 RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5 RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2 RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11 RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13 RMII_MII_TXD1 ---------------------> PB13
@ -116,7 +117,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13); HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13);
/* Disable the Ethernet global Interrupt */ /* Disable the Ethernet global Interrupt */
NVIC_DisableIRQ(ETH_IRQn); NVIC_DisableIRQ(ETH_IRQn);

11
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f7_eth_init.c
View File

@ -1,6 +1,7 @@
/* mbed Microcontroller Library /* mbed Microcontroller Library
* Copyright (c) 2022, STMicroelectronics * Copyright (c) 2022, STMicroelectronics
* All rights reserved. * All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -57,7 +58,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7 RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5 RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2 RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11 RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13 RMII_MII_TXD1 ---------------------> PB13
@ -78,8 +79,8 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PG2, PG11 and PG13 */ /* Configure PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13; GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
/* Enable the Ethernet global Interrupt */ /* Enable the Ethernet global Interrupt */
@ -107,7 +108,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
RMII_MII_CRS_DV -------------------> PA7 RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5 RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> PG2 RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11 RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13 RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PB13 RMII_MII_TXD1 ---------------------> PB13
@ -115,7 +116,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13); HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13);
/* Disable the Ethernet global Interrupt */ /* Disable the Ethernet global Interrupt */
NVIC_DisableIRQ(ETH_IRQn); NVIC_DisableIRQ(ETH_IRQn);

2
connectivity/nanostack/include/nanostack-interface/Nanostack.h
View File

@ -122,7 +122,7 @@ protected:
* NSAPI_ERROR_NO_SOCKET is returned if no socket is available. * NSAPI_ERROR_NO_SOCKET is returned if no socket is available.
* *
* @param handle Destination for the handle to a newly created socket * @param handle Destination for the handle to a newly created socket
* @param proto Protocol of socket to open, NSAPI_TCP or NSAPI_UDP * @param proto Protocol of socket to open, NSAPI_TCP, NSAPI_UDP or NSAPI_ICMP
* @return 0 on success, negative error code on failure * @return 0 on success, negative error code on failure
*/ */
nsapi_error_t socket_open(void **handle, nsapi_protocol_t proto) override; nsapi_error_t socket_open(void **handle, nsapi_protocol_t proto) override;

2
connectivity/nanostack/mbed-mesh-api/source/LoWPANNDInterface.cpp
View File

@ -28,7 +28,7 @@ class Nanostack::LoWPANNDInterface final : public Nanostack::MeshInterface {
public: public:
nsapi_error_t bringup(bool dhcp, const char *ip, nsapi_error_t bringup(bool dhcp, const char *ip,
const char *netmask, const char *gw, const char *netmask, const char *gw,
nsapi_ip_stack_t stack = IPV6_STACK, nsapi_ip_stack_t stack = DEFAULT_STACK,
bool blocking = true) override; bool blocking = true) override;
nsapi_error_t bringdown() override; nsapi_error_t bringdown() override;
nsapi_error_t get_gateway(SocketAddress *sockAddr) override; nsapi_error_t get_gateway(SocketAddress *sockAddr) override;

1
connectivity/nanostack/mbed-mesh-api/source/MeshInterfaceNanostack.cpp
View File

@ -174,6 +174,7 @@ void Nanostack::Interface::network_handler(mesh_connection_status_t status)
connect_semaphore.release(); connect_semaphore.release();
} else if (status == MESH_DISCONNECTED) { } else if (status == MESH_DISCONNECTED) {
disconnect_semaphore.release(); disconnect_semaphore.release();
connect_semaphore.release();
} }
} }

2
connectivity/nanostack/mbed-mesh-api/source/ThreadInterface.cpp
View File

@ -27,7 +27,7 @@ class Nanostack::ThreadInterface : public Nanostack::MeshInterface {
public: public:
nsapi_error_t bringup(bool dhcp, const char *ip, nsapi_error_t bringup(bool dhcp, const char *ip,
const char *netmask, const char *gw, const char *netmask, const char *gw,
nsapi_ip_stack_t stack = IPV6_STACK, nsapi_ip_stack_t stack = DEFAULT_STACK,
bool blocking = true) override; bool blocking = true) override;
nsapi_error_t bringdown() override; nsapi_error_t bringdown() override;
friend class Nanostack; friend class Nanostack;

2
connectivity/nanostack/mbed-mesh-api/source/WisunInterface.cpp
View File

@ -34,7 +34,7 @@ class Nanostack::WisunInterface final : public Nanostack::MeshInterface {
public: public:
nsapi_error_t bringup(bool dhcp, const char *ip, nsapi_error_t bringup(bool dhcp, const char *ip,
const char *netmask, const char *gw, const char *netmask, const char *gw,
nsapi_ip_stack_t stack = IPV6_STACK, nsapi_ip_stack_t stack = DEFAULT_STACK,
bool blocking = true) override; bool blocking = true) override;
nsapi_error_t bringdown() override; nsapi_error_t bringdown() override;
nsapi_error_t get_gateway(SocketAddress *address) override; nsapi_error_t get_gateway(SocketAddress *address) override;

11
connectivity/nanostack/sal-stack-nanostack/source/Core/ns_socket.c
View File

@ -1570,8 +1570,17 @@ struct protocol_interface_info_entry *socket_interface_determine(const socket_t
} }
} }
/* Try a routing table entry for greater-than-realm scope */ /* For greater-than-realm scope, use default interface if a default interface ID */
/* has been set (e.g. using setsockopt), else try a routing table entry */
if (addr_ipv6_scope(buf->dst_sa.address, NULL) > IPV6_SCOPE_REALM_LOCAL) { if (addr_ipv6_scope(buf->dst_sa.address, NULL) > IPV6_SCOPE_REALM_LOCAL) {
if (socket_ptr->default_interface_id != -1) {
cur_interface = protocol_stack_interface_info_get_by_id(socket_ptr->default_interface_id);
if (cur_interface) {
return cur_interface;
} else {
return NULL;
}
}
if (ipv6_buffer_route(buf)) { if (ipv6_buffer_route(buf)) {
return buf->interface; return buf->interface;
} }

2
connectivity/nanostack/sal-stack-nanostack/source/Security/TLS/tls_lib.c
View File

@ -2095,7 +2095,7 @@ void tls_master_key_cal(tls_heap_t *heap_ptr, sec_suite_t *tls_suite)
{ {
uint8_t *ptr; uint8_t *ptr;
prf_sec_param_t *prf_ptr = shalib_prf_param_get(); prf_sec_param_t *prf_ptr = shalib_prf_param_get();
uint8_t secret_buf[2 + 16 + 2 + 16]; static uint8_t secret_buf[2 + 16 + 2 + 16];
tr_debug("CAL Master secret:"); tr_debug("CAL Master secret:");
//Her have to to be set check is //Her have to to be set check is
#ifdef ECC #ifdef ECC

2
connectivity/nanostack/source/Nanostack.cpp
View File

@ -678,6 +678,8 @@ nsapi_error_t Nanostack::socket_open(void **handle, nsapi_protocol_t protocol)
ns_proto = SOCKET_UDP; ns_proto = SOCKET_UDP;
} else if (NSAPI_TCP == protocol) { } else if (NSAPI_TCP == protocol) {
ns_proto = SOCKET_TCP; ns_proto = SOCKET_TCP;
} else if (NSAPI_ICMP == protocol) {
ns_proto = SOCKET_ICMP;
} else { } else {
MBED_ASSERT(false); MBED_ASSERT(false);
return NSAPI_ERROR_UNSUPPORTED; return NSAPI_ERROR_UNSUPPORTED;

2
connectivity/netsocket/source/TLSSocketWrapper.cpp
View File

@ -77,7 +77,7 @@ TLSSocketWrapper::TLSSocketWrapper(Socket *transport, const char *hostname, cont
TLSSocketWrapper::~TLSSocketWrapper() TLSSocketWrapper::~TLSSocketWrapper()
{ {
if (_transport) { if (_transport) {
close(); TLSSocketWrapper::close();
} }
mbedtls_entropy_free(&_entropy); mbedtls_entropy_free(&_entropy);

21
connectivity/netsocket/tests/TESTS/netsocket/tls/main.cpp
View File

@ -218,22 +218,23 @@ static void test_failure_handler(const failure_t failure)
Case cases[] = { Case cases[] = {
Case("TLSSOCKET_ECHOTEST", TLSSOCKET_ECHOTEST), // Disable tests temporarily till echo server is back on
Case("TLSSOCKET_ECHOTEST_NONBLOCK", TLSSOCKET_ECHOTEST_NONBLOCK), // Case("TLSSOCKET_ECHOTEST", TLSSOCKET_ECHOTEST),
// Case("TLSSOCKET_ECHOTEST_NONBLOCK", TLSSOCKET_ECHOTEST_NONBLOCK),
Case("TLSSOCKET_CONNECT_INVALID", TLSSOCKET_CONNECT_INVALID), Case("TLSSOCKET_CONNECT_INVALID", TLSSOCKET_CONNECT_INVALID),
Case("TLSSOCKET_ECHOTEST_BURST", TLSSOCKET_ECHOTEST_BURST), // Case("TLSSOCKET_ECHOTEST_BURST", TLSSOCKET_ECHOTEST_BURST),
Case("TLSSOCKET_ECHOTEST_BURST_NONBLOCK", TLSSOCKET_ECHOTEST_BURST_NONBLOCK), // Case("TLSSOCKET_ECHOTEST_BURST_NONBLOCK", TLSSOCKET_ECHOTEST_BURST_NONBLOCK),
Case("TLSSOCKET_RECV_TIMEOUT", TLSSOCKET_RECV_TIMEOUT), // Case("TLSSOCKET_RECV_TIMEOUT", TLSSOCKET_RECV_TIMEOUT),
Case("TLSSOCKET_ENDPOINT_CLOSE", TLSSOCKET_ENDPOINT_CLOSE), // Case("TLSSOCKET_ENDPOINT_CLOSE", TLSSOCKET_ENDPOINT_CLOSE),
Case("TLSSOCKET_HANDSHAKE_INVALID", TLSSOCKET_HANDSHAKE_INVALID), Case("TLSSOCKET_HANDSHAKE_INVALID", TLSSOCKET_HANDSHAKE_INVALID),
Case("TLSSOCKET_OPEN_TWICE", TLSSOCKET_OPEN_TWICE), Case("TLSSOCKET_OPEN_TWICE", TLSSOCKET_OPEN_TWICE),
Case("TLSSOCKET_OPEN_LIMIT", TLSSOCKET_OPEN_LIMIT), Case("TLSSOCKET_OPEN_LIMIT", TLSSOCKET_OPEN_LIMIT),
Case("TLSSOCKET_OPEN_DESTRUCT", TLSSOCKET_OPEN_DESTRUCT), Case("TLSSOCKET_OPEN_DESTRUCT", TLSSOCKET_OPEN_DESTRUCT),
Case("TLSSOCKET_SEND_UNCONNECTED", TLSSOCKET_SEND_UNCONNECTED), Case("TLSSOCKET_SEND_UNCONNECTED", TLSSOCKET_SEND_UNCONNECTED),
Case("TLSSOCKET_SEND_CLOSED", TLSSOCKET_SEND_CLOSED), // Case("TLSSOCKET_SEND_CLOSED", TLSSOCKET_SEND_CLOSED),
Case("TLSSOCKET_SEND_REPEAT", TLSSOCKET_SEND_REPEAT), // Case("TLSSOCKET_SEND_REPEAT", TLSSOCKET_SEND_REPEAT),
Case("TLSSOCKET_SEND_TIMEOUT", TLSSOCKET_SEND_TIMEOUT), // Case("TLSSOCKET_SEND_TIMEOUT", TLSSOCKET_SEND_TIMEOUT),
Case("TLSSOCKET_NO_CERT", TLSSOCKET_NO_CERT), // Case("TLSSOCKET_NO_CERT", TLSSOCKET_NO_CERT),
// Temporarily removing this test, as TLS library consumes too much memory // Temporarily removing this test, as TLS library consumes too much memory
// and we see frequent memory allocation failures on architectures with less // and we see frequent memory allocation failures on architectures with less
// RAM such as DISCO_L475VG_IOT1A and NUCLEO_F207ZG (both have 128 kB RAM) // RAM such as DISCO_L475VG_IOT1A and NUCLEO_F207ZG (both have 128 kB RAM)

8
drivers/source/CAN.cpp
View File

@ -19,6 +19,7 @@
#if DEVICE_CAN #if DEVICE_CAN
#include "platform/mbed_power_mgmt.h" #include "platform/mbed_power_mgmt.h"
#include "platform/mbed_error.h"
namespace mbed { namespace mbed {
@ -82,6 +83,9 @@ int CAN::read(CANMessage &msg, int handle)
{ {
lock(); lock();
int ret = can_read(&_can, &msg, handle); int ret = can_read(&_can, &msg, handle);
if (msg.len > 8) {
MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_CAN, MBED_ERROR_CODE_READ_FAILED), "Read tried to write more than 8 bytes");
}
unlock(); unlock();
return ret; return ret;
} }
@ -134,7 +138,7 @@ int CAN::filter(unsigned int id, unsigned int mask, CANFormat format, int handle
void CAN::attach(Callback<void()> func, IrqType type) void CAN::attach(Callback<void()> func, IrqType type)
{ {
lock(); CAN::lock();
if (func) { if (func) {
// lock deep sleep only the first time // lock deep sleep only the first time
if (!_irq[(CanIrqType)type]) { if (!_irq[(CanIrqType)type]) {
@ -150,7 +154,7 @@ void CAN::attach(Callback<void()> func, IrqType type)
_irq[(CanIrqType)type] = nullptr; _irq[(CanIrqType)type] = nullptr;
can_irq_set(&_can, (CanIrqType)type, 0); can_irq_set(&_can, (CanIrqType)type, 0);
} }
unlock(); CAN::unlock();
} }
void CAN::_irq_handler(uintptr_t context, CanIrqType type) void CAN::_irq_handler(uintptr_t context, CanIrqType type)

4
drivers/source/SPI.cpp
View File

@ -148,12 +148,12 @@ void SPI::_do_construct()
SPI::~SPI() SPI::~SPI()
{ {
lock(); SPI::lock();
/* Make sure a stale pointer isn't left in peripheral's owner field */ /* Make sure a stale pointer isn't left in peripheral's owner field */
if (_peripheral->owner == this) { if (_peripheral->owner == this) {
_peripheral->owner = nullptr; _peripheral->owner = nullptr;
} }
unlock(); SPI::unlock();
} }
SPI::spi_peripheral_s *SPI::_lookup(SPI::SPIName name) SPI::spi_peripheral_s *SPI::_lookup(SPI::SPIName name)

2
platform/include/platform/mbed_version.h
View File

@ -38,7 +38,7 @@
* *
* @note 99 is default value for development version (master branch) * @note 99 is default value for development version (master branch)
*/ */
#define MBED_MINOR_VERSION 16 #define MBED_MINOR_VERSION 17
/** MBED_PATCH_VERSION /** MBED_PATCH_VERSION
* Mbed OS patch version * Mbed OS patch version

3
storage/filesystem/fat/ChaN/ff.cpp
View File

@ -537,7 +537,7 @@ static WCHAR LfnBuf[FF_MAX_LFN + 1]; /* LFN working buffer */
#elif FF_USE_LFN == 3 /* LFN enabled with dynamic working buffer on the heap */ #elif FF_USE_LFN == 3 /* LFN enabled with dynamic working buffer on the heap */
#if FF_FS_EXFAT #if FF_FS_EXFAT
#define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer and directory entry block scratchpad buffer */ #define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer and directory entry block scratchpad buffer */
#define INIT_NAMBUF(fs) { lfn = ff_memalloc((FF_MAX_LFN+1)*2 + MAXDIRB(FF_MAX_LFN)); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+FF_MAX_LFN+1); } #define INIT_NAMBUF(fs) { lfn = (WCHAR *)(ff_memalloc((FF_MAX_LFN+1)*2 + MAXDIRB(FF_MAX_LFN))); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+FF_MAX_LFN+1); }
#define FREE_NAMBUF() ff_memfree(lfn) #define FREE_NAMBUF() ff_memfree(lfn)
#else #else
#define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer */ #define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer */
@ -555,6 +555,7 @@ static WCHAR LfnBuf[FF_MAX_LFN + 1]; /* LFN working buffer */
/*--------------------------------*/ /*--------------------------------*/
/* Code conversion tables */ /* Code conversion tables */
/*--------------------------------*/ /*--------------------------------*/

2
storage/filesystem/source/Dir.cpp
View File

@ -34,7 +34,7 @@ Dir::Dir(FileSystem *fs, const char *path)
Dir::~Dir() Dir::~Dir()
{ {
if (_fs) { if (_fs) {
close(); Dir::close();
} }
} }

2
storage/filesystem/source/File.cpp
View File

@ -34,7 +34,7 @@ File::File(FileSystem *fs, const char *path, int flags)
File::~File() File::~File()
{ {
if (_fs) { if (_fs) {
close(); File::close();
} }
} }

2
storage/kvstore/securestore/source/SecureStore.cpp
View File

@ -789,7 +789,7 @@ int SecureStore::deinit()
mbedtls_entropy_free(_entropy); mbedtls_entropy_free(_entropy);
delete _entropy; delete _entropy;
delete _ih; delete _ih;
delete _scratch_buf; delete[] _scratch_buf;
_entropy = nullptr; _entropy = nullptr;
} }
ret = _underlying_kv->deinit(); ret = _underlying_kv->deinit();

1
targets/TARGET_Maxim/TARGET_MAX32670/CMakeLists.txt
View File

@ -84,7 +84,6 @@ target_sources(mbed-max32670
${MXM_SOURCE_DIR}/FLC/flc_common.c ${MXM_SOURCE_DIR}/FLC/flc_common.c
${MXM_SOURCE_DIR}/FLC/flc_me15.c ${MXM_SOURCE_DIR}/FLC/flc_me15.c
${MXM_SOURCE_DIR}/FLC/flc_reva.c ${MXM_SOURCE_DIR}/FLC/flc_reva.c
${MXM_SOURCE_DIR}/FLC/flc_revb.c
${MXM_SOURCE_DIR}/GPIO/gpio_common.c ${MXM_SOURCE_DIR}/GPIO/gpio_common.c
${MXM_SOURCE_DIR}/GPIO/gpio_me15.c ${MXM_SOURCE_DIR}/GPIO/gpio_me15.c

39
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_key_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file aes_key_regs.h * @file aes_key_regs.h
* @brief Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module.
* @note This file is @deprecated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,12 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _AES_KEY_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AES_KEY_REGS_H_
#define _AES_KEY_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AES_KEY_REGS_H_
#warning "DEPRECATED(1-10-2023): aes_key_regs.h - Scheduled for removal. Please use aeskeys_regs.h."
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,13 +77,18 @@ extern "C" {
* @ingroup aes_key * @ingroup aes_key
* @defgroup aes_key_registers AES_KEY_Registers * @defgroup aes_key_registers AES_KEY_Registers
* @brief Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module.
* @details AES Key Registers. * @details AES Key Registers.
*/ */
/** /**
* @ingroup aes_key_registers * @ingroup aes_key_registers
* Structure type to access the AES_KEY Registers. * Structure type to access the AES_KEY Registers.
*/ */
#if defined(__GNUC__)
__attribute__((deprecated("mxc_aes_key_regs_t struct and aes_key_regs.h no longer supported. Use aeskeys_regs.h and MXC_AESKEYS (mxc_aeskeys_regs_t) for AES Key Access. 1-10-2023")))
#else
#warning "mxc_aes_key_regs_t struct and aes_key_regs.h no longer supported. Use aeskeys_regs.h and MXC_AESKEYS (mxc_aeskeys_regs_t) for AES Key Access. 1-10-2023"
#endif
typedef struct { typedef struct {
__IO uint32_t aes_key0; /**< <tt>\b 0x00:</tt> AES_KEY AES_KEY0 Register */ __IO uint32_t aes_key0; /**< <tt>\b 0x00:</tt> AES_KEY AES_KEY0 Register */
__IO uint32_t aes_key1; /**< <tt>\b 0x04:</tt> AES_KEY AES_KEY1 Register */ __IO uint32_t aes_key1; /**< <tt>\b 0x04:</tt> AES_KEY AES_KEY1 Register */
@ -100,18 +107,18 @@ typedef struct {
* @brief AES_KEY Peripheral Register Offsets from the AES_KEY Base Peripheral Address. * @brief AES_KEY Peripheral Register Offsets from the AES_KEY Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_AES_KEY_AES_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AES_KEY Base Address: <tt> 0x0000</tt> */ #define MXC_R_AES_KEY_AES_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AES_KEY Base Address: <tt> 0x0000</tt> */
#define MXC_R_AES_KEY_AES_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AES_KEY Base Address: <tt> 0x0004</tt> */ #define MXC_R_AES_KEY_AES_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AES_KEY Base Address: <tt> 0x0004</tt> */
#define MXC_R_AES_KEY_AES_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AES_KEY Base Address: <tt> 0x0008</tt> */ #define MXC_R_AES_KEY_AES_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AES_KEY Base Address: <tt> 0x0008</tt> */
#define MXC_R_AES_KEY_AES_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AES_KEY Base Address: <tt> 0x000C</tt> */ #define MXC_R_AES_KEY_AES_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AES_KEY Base Address: <tt> 0x000C</tt> */
#define MXC_R_AES_KEY_AES_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AES_KEY Base Address: <tt> 0x0010</tt> */ #define MXC_R_AES_KEY_AES_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AES_KEY Base Address: <tt> 0x0010</tt> */
#define MXC_R_AES_KEY_AES_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AES_KEY Base Address: <tt> 0x0014</tt> */ #define MXC_R_AES_KEY_AES_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AES_KEY Base Address: <tt> 0x0014</tt> */
#define MXC_R_AES_KEY_AES_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AES_KEY Base Address: <tt> 0x0018</tt> */ #define MXC_R_AES_KEY_AES_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AES_KEY Base Address: <tt> 0x0018</tt> */
#define MXC_R_AES_KEY_AES_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AES_KEY Base Address: <tt> 0x001C</tt> */ #define MXC_R_AES_KEY_AES_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AES_KEY Base Address: <tt> 0x001C</tt> */
/**@} end of group aes_key_registers */ /**@} end of group aes_key_registers */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* _AES_KEY_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AES_KEY_REGS_H_

132
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file aes_regs.h * @file aes_regs.h
* @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _AES_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AES_REGS_H_
#define _AES_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AES_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup aes * @ingroup aes
* @defgroup aes_registers AES_Registers * @defgroup aes_registers AES_Registers
* @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module.
* @details AES Keys. * @details AES Keys.
*/ */
/** /**
@ -97,11 +97,11 @@ typedef struct {
* @brief AES Peripheral Register Offsets from the AES Base Peripheral Address. * @brief AES Peripheral Register Offsets from the AES Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_AES_CTRL ((uint32_t)0x00000000UL) /**< Offset from AES Base Address: <tt> 0x0000</tt> */ #define MXC_R_AES_CTRL ((uint32_t)0x00000000UL) /**< Offset from AES Base Address: <tt> 0x0000</tt> */
#define MXC_R_AES_STATUS ((uint32_t)0x00000004UL) /**< Offset from AES Base Address: <tt> 0x0004</tt> */ #define MXC_R_AES_STATUS ((uint32_t)0x00000004UL) /**< Offset from AES Base Address: <tt> 0x0004</tt> */
#define MXC_R_AES_INTFL ((uint32_t)0x00000008UL) /**< Offset from AES Base Address: <tt> 0x0008</tt> */ #define MXC_R_AES_INTFL ((uint32_t)0x00000008UL) /**< Offset from AES Base Address: <tt> 0x0008</tt> */
#define MXC_R_AES_INTEN ((uint32_t)0x0000000CUL) /**< Offset from AES Base Address: <tt> 0x000C</tt> */ #define MXC_R_AES_INTEN ((uint32_t)0x0000000CUL) /**< Offset from AES Base Address: <tt> 0x000C</tt> */
#define MXC_R_AES_FIFO ((uint32_t)0x00000010UL) /**< Offset from AES Base Address: <tt> 0x0010</tt> */ #define MXC_R_AES_FIFO ((uint32_t)0x00000010UL) /**< Offset from AES Base Address: <tt> 0x0010</tt> */
/**@} end of group aes_registers */ /**@} end of group aes_registers */
/** /**
@ -110,35 +110,35 @@ typedef struct {
* @brief AES Control Register * @brief AES Control Register
* @{ * @{
*/ */
#define MXC_F_AES_CTRL_EN_POS 0 /**< CTRL_EN Position */ #define MXC_F_AES_CTRL_EN_POS 0 /**< CTRL_EN Position */
#define MXC_F_AES_CTRL_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_EN_POS)) /**< CTRL_EN Mask */ #define MXC_F_AES_CTRL_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_EN_POS)) /**< CTRL_EN Mask */
#define MXC_F_AES_CTRL_DMA_RX_EN_POS 1 /**< CTRL_DMA_RX_EN Position */ #define MXC_F_AES_CTRL_DMA_RX_EN_POS 1 /**< CTRL_DMA_RX_EN Position */
#define MXC_F_AES_CTRL_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_RX_EN_POS)) /**< CTRL_DMA_RX_EN Mask */ #define MXC_F_AES_CTRL_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_RX_EN_POS)) /**< CTRL_DMA_RX_EN Mask */
#define MXC_F_AES_CTRL_DMA_TX_EN_POS 2 /**< CTRL_DMA_TX_EN Position */ #define MXC_F_AES_CTRL_DMA_TX_EN_POS 2 /**< CTRL_DMA_TX_EN Position */
#define MXC_F_AES_CTRL_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_TX_EN_POS)) /**< CTRL_DMA_TX_EN Mask */ #define MXC_F_AES_CTRL_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_TX_EN_POS)) /**< CTRL_DMA_TX_EN Mask */
#define MXC_F_AES_CTRL_START_POS 3 /**< CTRL_START Position */ #define MXC_F_AES_CTRL_START_POS 3 /**< CTRL_START Position */
#define MXC_F_AES_CTRL_START ((uint32_t)(0x1UL << MXC_F_AES_CTRL_START_POS)) /**< CTRL_START Mask */ #define MXC_F_AES_CTRL_START ((uint32_t)(0x1UL << MXC_F_AES_CTRL_START_POS)) /**< CTRL_START Mask */
#define MXC_F_AES_CTRL_INPUT_FLUSH_POS 4 /**< CTRL_INPUT_FLUSH Position */ #define MXC_F_AES_CTRL_INPUT_FLUSH_POS 4 /**< CTRL_INPUT_FLUSH Position */
#define MXC_F_AES_CTRL_INPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_INPUT_FLUSH_POS)) /**< CTRL_INPUT_FLUSH Mask */ #define MXC_F_AES_CTRL_INPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_INPUT_FLUSH_POS)) /**< CTRL_INPUT_FLUSH Mask */
#define MXC_F_AES_CTRL_OUTPUT_FLUSH_POS 5 /**< CTRL_OUTPUT_FLUSH Position */ #define MXC_F_AES_CTRL_OUTPUT_FLUSH_POS 5 /**< CTRL_OUTPUT_FLUSH Position */
#define MXC_F_AES_CTRL_OUTPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_OUTPUT_FLUSH_POS)) /**< CTRL_OUTPUT_FLUSH Mask */ #define MXC_F_AES_CTRL_OUTPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_OUTPUT_FLUSH_POS)) /**< CTRL_OUTPUT_FLUSH Mask */
#define MXC_F_AES_CTRL_KEY_SIZE_POS 6 /**< CTRL_KEY_SIZE Position */ #define MXC_F_AES_CTRL_KEY_SIZE_POS 6 /**< CTRL_KEY_SIZE Position */
#define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< CTRL_KEY_SIZE Mask */ #define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< CTRL_KEY_SIZE Mask */
#define MXC_V_AES_CTRL_KEY_SIZE_AES128 ((uint32_t)0x0UL) /**< CTRL_KEY_SIZE_AES128 Value */ #define MXC_V_AES_CTRL_KEY_SIZE_AES128 ((uint32_t)0x0UL) /**< CTRL_KEY_SIZE_AES128 Value */
#define MXC_S_AES_CTRL_KEY_SIZE_AES128 (MXC_V_AES_CTRL_KEY_SIZE_AES128 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES128 Setting */ #define MXC_S_AES_CTRL_KEY_SIZE_AES128 (MXC_V_AES_CTRL_KEY_SIZE_AES128 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES128 Setting */
#define MXC_V_AES_CTRL_KEY_SIZE_AES192 ((uint32_t)0x1UL) /**< CTRL_KEY_SIZE_AES192 Value */ #define MXC_V_AES_CTRL_KEY_SIZE_AES192 ((uint32_t)0x1UL) /**< CTRL_KEY_SIZE_AES192 Value */
#define MXC_S_AES_CTRL_KEY_SIZE_AES192 (MXC_V_AES_CTRL_KEY_SIZE_AES192 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES192 Setting */ #define MXC_S_AES_CTRL_KEY_SIZE_AES192 (MXC_V_AES_CTRL_KEY_SIZE_AES192 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES192 Setting */
#define MXC_V_AES_CTRL_KEY_SIZE_AES256 ((uint32_t)0x2UL) /**< CTRL_KEY_SIZE_AES256 Value */ #define MXC_V_AES_CTRL_KEY_SIZE_AES256 ((uint32_t)0x2UL) /**< CTRL_KEY_SIZE_AES256 Value */
#define MXC_S_AES_CTRL_KEY_SIZE_AES256 (MXC_V_AES_CTRL_KEY_SIZE_AES256 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES256 Setting */ #define MXC_S_AES_CTRL_KEY_SIZE_AES256 (MXC_V_AES_CTRL_KEY_SIZE_AES256 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES256 Setting */
#define MXC_F_AES_CTRL_TYPE_POS 8 /**< CTRL_TYPE Position */ #define MXC_F_AES_CTRL_TYPE_POS 8 /**< CTRL_TYPE Position */
#define MXC_F_AES_CTRL_TYPE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_TYPE_POS)) /**< CTRL_TYPE Mask */ #define MXC_F_AES_CTRL_TYPE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_TYPE_POS)) /**< CTRL_TYPE Mask */
/**@} end of group AES_CTRL_Register */ /**@} end of group AES_CTRL_Register */
@ -148,20 +148,20 @@ typedef struct {
* @brief AES Status Register * @brief AES Status Register
* @{ * @{
*/ */
#define MXC_F_AES_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ #define MXC_F_AES_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */
#define MXC_F_AES_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_AES_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ #define MXC_F_AES_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_AES_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */
#define MXC_F_AES_STATUS_INPUT_EM_POS 1 /**< STATUS_INPUT_EM Position */ #define MXC_F_AES_STATUS_INPUT_EM_POS 1 /**< STATUS_INPUT_EM Position */
#define MXC_F_AES_STATUS_INPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_EM_POS)) /**< STATUS_INPUT_EM Mask */ #define MXC_F_AES_STATUS_INPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_EM_POS)) /**< STATUS_INPUT_EM Mask */
#define MXC_F_AES_STATUS_INPUT_FULL_POS 2 /**< STATUS_INPUT_FULL Position */ #define MXC_F_AES_STATUS_INPUT_FULL_POS 2 /**< STATUS_INPUT_FULL Position */
#define MXC_F_AES_STATUS_INPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_FULL_POS)) /**< STATUS_INPUT_FULL Mask */ #define MXC_F_AES_STATUS_INPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_FULL_POS)) /**< STATUS_INPUT_FULL Mask */
#define MXC_F_AES_STATUS_OUTPUT_EM_POS 3 /**< STATUS_OUTPUT_EM Position */ #define MXC_F_AES_STATUS_OUTPUT_EM_POS 3 /**< STATUS_OUTPUT_EM Position */
#define MXC_F_AES_STATUS_OUTPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_EM_POS)) /**< STATUS_OUTPUT_EM Mask */ #define MXC_F_AES_STATUS_OUTPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_EM_POS)) /**< STATUS_OUTPUT_EM Mask */
#define MXC_F_AES_STATUS_OUTPUT_FULL_POS 4 /**< STATUS_OUTPUT_FULL Position */ #define MXC_F_AES_STATUS_OUTPUT_FULL_POS 4 /**< STATUS_OUTPUT_FULL Position */
#define MXC_F_AES_STATUS_OUTPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_FULL_POS)) /**< STATUS_OUTPUT_FULL Mask */ #define MXC_F_AES_STATUS_OUTPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_FULL_POS)) /**< STATUS_OUTPUT_FULL Mask */
/**@} end of group AES_STATUS_Register */ /**@} end of group AES_STATUS_Register */
@ -171,17 +171,20 @@ typedef struct {
* @brief AES Interrupt Flag Register * @brief AES Interrupt Flag Register
* @{ * @{
*/ */
#define MXC_F_AES_INTFL_DONE_POS 0 /**< INTFL_DONE Position */ #define MXC_F_AES_INTFL_DONE_POS 0 /**< INTFL_DONE Position */
#define MXC_F_AES_INTFL_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_DONE_POS)) /**< INTFL_DONE Mask */ #define MXC_F_AES_INTFL_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_DONE_POS)) /**< INTFL_DONE Mask */
#define MXC_F_AES_INTFL_KEY_CHANGE_POS 1 /**< INTFL_KEY_CHANGE Position */ #define MXC_F_AES_INTFL_KEY_CHANGE_POS 1 /**< INTFL_KEY_CHANGE Position */
#define MXC_F_AES_INTFL_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_CHANGE_POS)) /**< INTFL_KEY_CHANGE Mask */ #define MXC_F_AES_INTFL_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_CHANGE_POS)) /**< INTFL_KEY_CHANGE Mask */
#define MXC_F_AES_INTFL_KEY_ZERO_POS 2 /**< INTFL_KEY_ZERO Position */ #define MXC_F_AES_INTFL_KEY_ZERO_POS 2 /**< INTFL_KEY_ZERO Position */
#define MXC_F_AES_INTFL_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ZERO_POS)) /**< INTFL_KEY_ZERO Mask */ #define MXC_F_AES_INTFL_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ZERO_POS)) /**< INTFL_KEY_ZERO Mask */
#define MXC_F_AES_INTFL_OV_POS 3 /**< INTFL_OV Position */ #define MXC_F_AES_INTFL_OV_POS 3 /**< INTFL_OV Position */
#define MXC_F_AES_INTFL_OV ((uint32_t)(0x1UL << MXC_F_AES_INTFL_OV_POS)) /**< INTFL_OV Mask */ #define MXC_F_AES_INTFL_OV ((uint32_t)(0x1UL << MXC_F_AES_INTFL_OV_POS)) /**< INTFL_OV Mask */
#define MXC_F_AES_INTFL_KEY_ONE_POS 4 /**< INTFL_KEY_ONE Position */
#define MXC_F_AES_INTFL_KEY_ONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ONE_POS)) /**< INTFL_KEY_ONE Mask */
/**@} end of group AES_INTFL_Register */ /**@} end of group AES_INTFL_Register */
@ -191,17 +194,20 @@ typedef struct {
* @brief AES Interrupt Enable Register * @brief AES Interrupt Enable Register
* @{ * @{
*/ */
#define MXC_F_AES_INTEN_DONE_POS 0 /**< INTEN_DONE Position */ #define MXC_F_AES_INTEN_DONE_POS 0 /**< INTEN_DONE Position */
#define MXC_F_AES_INTEN_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_DONE_POS)) /**< INTEN_DONE Mask */ #define MXC_F_AES_INTEN_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_DONE_POS)) /**< INTEN_DONE Mask */
#define MXC_F_AES_INTEN_KEY_CHANGE_POS 1 /**< INTEN_KEY_CHANGE Position */ #define MXC_F_AES_INTEN_KEY_CHANGE_POS 1 /**< INTEN_KEY_CHANGE Position */
#define MXC_F_AES_INTEN_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_CHANGE_POS)) /**< INTEN_KEY_CHANGE Mask */ #define MXC_F_AES_INTEN_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_CHANGE_POS)) /**< INTEN_KEY_CHANGE Mask */
#define MXC_F_AES_INTEN_KEY_ZERO_POS 2 /**< INTEN_KEY_ZERO Position */ #define MXC_F_AES_INTEN_KEY_ZERO_POS 2 /**< INTEN_KEY_ZERO Position */
#define MXC_F_AES_INTEN_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ZERO_POS)) /**< INTEN_KEY_ZERO Mask */ #define MXC_F_AES_INTEN_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ZERO_POS)) /**< INTEN_KEY_ZERO Mask */
#define MXC_F_AES_INTEN_OV_POS 3 /**< INTEN_OV Position */ #define MXC_F_AES_INTEN_OV_POS 3 /**< INTEN_OV Position */
#define MXC_F_AES_INTEN_OV ((uint32_t)(0x1UL << MXC_F_AES_INTEN_OV_POS)) /**< INTEN_OV Mask */ #define MXC_F_AES_INTEN_OV ((uint32_t)(0x1UL << MXC_F_AES_INTEN_OV_POS)) /**< INTEN_OV Mask */
#define MXC_F_AES_INTEN_KEY_ONE_POS 4 /**< INTEN_KEY_ONE Position */
#define MXC_F_AES_INTEN_KEY_ONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ONE_POS)) /**< INTEN_KEY_ONE Mask */
/**@} end of group AES_INTEN_Register */ /**@} end of group AES_INTEN_Register */
@ -211,8 +217,8 @@ typedef struct {
* @brief AES Data Register * @brief AES Data Register
* @{ * @{
*/ */
#define MXC_F_AES_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ #define MXC_F_AES_FIFO_DATA_POS 0 /**< FIFO_DATA Position */
#define MXC_F_AES_FIFO_DATA ((uint32_t)(0x1UL << MXC_F_AES_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ #define MXC_F_AES_FIFO_DATA ((uint32_t)(0x1UL << MXC_F_AES_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
/**@} end of group AES_FIFO_Register */ /**@} end of group AES_FIFO_Register */
@ -220,4 +226,4 @@ typedef struct {
} }
#endif #endif
#endif /* _AES_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AES_REGS_H_

117
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aeskeys_regs.h Normal file
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@ -0,0 +1,117 @@
/**
* @file aeskeys_regs.h
* @brief Registers, Bit Masks and Bit Positions for the AESKEYS Peripheral Module.
* @note This file is @generated.
*/
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
******************************************************************************/
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AESKEYS_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AESKEYS_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup aeskeys
* @defgroup aeskeys_registers AESKEYS_Registers
* @brief Registers, Bit Masks and Bit Positions for the AESKEYS Peripheral Module.
* @details AES Key Registers.
*/
/**
* @ingroup aeskeys_registers
* Structure type to access the AESKEYS Registers.
*/
typedef struct {
__IO uint32_t key0; /**< <tt>\b 0x00:</tt> AESKEYS KEY0 Register */
__IO uint32_t key1; /**< <tt>\b 0x04:</tt> AESKEYS KEY1 Register */
__IO uint32_t key2; /**< <tt>\b 0x08:</tt> AESKEYS KEY2 Register */
__IO uint32_t key3; /**< <tt>\b 0x0C:</tt> AESKEYS KEY3 Register */
__IO uint32_t key4; /**< <tt>\b 0x10:</tt> AESKEYS KEY4 Register */
__IO uint32_t key5; /**< <tt>\b 0x14:</tt> AESKEYS KEY5 Register */
__IO uint32_t key6; /**< <tt>\b 0x18:</tt> AESKEYS KEY6 Register */
__IO uint32_t key7; /**< <tt>\b 0x1C:</tt> AESKEYS KEY7 Register */
} mxc_aeskeys_regs_t;
/* Register offsets for module AESKEYS */
/**
* @ingroup aeskeys_registers
* @defgroup AESKEYS_Register_Offsets Register Offsets
* @brief AESKEYS Peripheral Register Offsets from the AESKEYS Base Peripheral Address.
* @{
*/
#define MXC_R_AESKEYS_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AESKEYS Base Address: <tt> 0x0000</tt> */
#define MXC_R_AESKEYS_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AESKEYS Base Address: <tt> 0x0004</tt> */
#define MXC_R_AESKEYS_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AESKEYS Base Address: <tt> 0x0008</tt> */
#define MXC_R_AESKEYS_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AESKEYS Base Address: <tt> 0x000C</tt> */
#define MXC_R_AESKEYS_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AESKEYS Base Address: <tt> 0x0010</tt> */
#define MXC_R_AESKEYS_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AESKEYS Base Address: <tt> 0x0014</tt> */
#define MXC_R_AESKEYS_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AESKEYS Base Address: <tt> 0x0018</tt> */
#define MXC_R_AESKEYS_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AESKEYS Base Address: <tt> 0x001C</tt> */
/**@} end of group aeskeys_registers */
#ifdef __cplusplus
}
#endif
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_AESKEYS_REGS_H_

82
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/crc_regs.h
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@ -1,10 +1,11 @@
/** /**
* @file crc_regs.h * @file crc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the CRC Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the CRC Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _CRC_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_CRC_REGS_H_
#define _CRC_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_CRC_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup crc * @ingroup crc
* @defgroup crc_registers CRC_Registers * @defgroup crc_registers CRC_Registers
* @brief Registers, Bit Masks and Bit Positions for the CRC Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the CRC Peripheral Module.
* @details CRC Registers. * @details CRC Registers.
*/ */
/** /**
@ -84,11 +84,11 @@ extern "C" {
*/ */
typedef struct { typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> CRC CTRL Register */ __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> CRC CTRL Register */
union{ union {
__IO uint32_t datain32; /**< <tt>\b 0x0004:</tt> CRC DATAIN32 Register */ __IO uint32_t datain32; /**< <tt>\b 0x0004:</tt> CRC DATAIN32 Register */
__IO uint16_t datain16[2]; /**< <tt>\b 0x0004:</tt> CRC DATAIN16 Register */ __IO uint16_t datain16[2]; /**< <tt>\b 0x0004:</tt> CRC DATAIN16 Register */
__IO uint8_t datain8[4]; /**< <tt>\b 0x0004:</tt> CRC DATAIN8 Register */ __IO uint8_t datain8[4]; /**< <tt>\b 0x0004:</tt> CRC DATAIN8 Register */
}; };
__IO uint32_t poly; /**< <tt>\b 0x0008:</tt> CRC POLY Register */ __IO uint32_t poly; /**< <tt>\b 0x0008:</tt> CRC POLY Register */
__IO uint32_t val; /**< <tt>\b 0x000C:</tt> CRC VAL Register */ __IO uint32_t val; /**< <tt>\b 0x000C:</tt> CRC VAL Register */
} mxc_crc_regs_t; } mxc_crc_regs_t;
@ -100,12 +100,12 @@ typedef struct {
* @brief CRC Peripheral Register Offsets from the CRC Base Peripheral Address. * @brief CRC Peripheral Register Offsets from the CRC Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_CRC_CTRL ((uint32_t)0x00000000UL) /**< Offset from CRC Base Address: <tt> 0x0000</tt> */ #define MXC_R_CRC_CTRL ((uint32_t)0x00000000UL) /**< Offset from CRC Base Address: <tt> 0x0000</tt> */
#define MXC_R_CRC_DATAIN32 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: <tt> 0x0004</tt> */ #define MXC_R_CRC_DATAIN32 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: <tt> 0x0004</tt> */
#define MXC_R_CRC_DATAIN16 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: <tt> 0x0004</tt> */ #define MXC_R_CRC_DATAIN16 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: <tt> 0x0004</tt> */
#define MXC_R_CRC_DATAIN8 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: <tt> 0x0004</tt> */ #define MXC_R_CRC_DATAIN8 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: <tt> 0x0004</tt> */
#define MXC_R_CRC_POLY ((uint32_t)0x00000008UL) /**< Offset from CRC Base Address: <tt> 0x0008</tt> */ #define MXC_R_CRC_POLY ((uint32_t)0x00000008UL) /**< Offset from CRC Base Address: <tt> 0x0008</tt> */
#define MXC_R_CRC_VAL ((uint32_t)0x0000000CUL) /**< Offset from CRC Base Address: <tt> 0x000C</tt> */ #define MXC_R_CRC_VAL ((uint32_t)0x0000000CUL) /**< Offset from CRC Base Address: <tt> 0x000C</tt> */
/**@} end of group crc_registers */ /**@} end of group crc_registers */
/** /**
@ -114,23 +114,23 @@ typedef struct {
* @brief CRC Control * @brief CRC Control
* @{ * @{
*/ */
#define MXC_F_CRC_CTRL_EN_POS 0 /**< CTRL_EN Position */ #define MXC_F_CRC_CTRL_EN_POS 0 /**< CTRL_EN Position */
#define MXC_F_CRC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_EN_POS)) /**< CTRL_EN Mask */ #define MXC_F_CRC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_EN_POS)) /**< CTRL_EN Mask */
#define MXC_F_CRC_CTRL_DMA_EN_POS 1 /**< CTRL_DMA_EN Position */ #define MXC_F_CRC_CTRL_DMA_EN_POS 1 /**< CTRL_DMA_EN Position */
#define MXC_F_CRC_CTRL_DMA_EN ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_DMA_EN_POS)) /**< CTRL_DMA_EN Mask */ #define MXC_F_CRC_CTRL_DMA_EN ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_DMA_EN_POS)) /**< CTRL_DMA_EN Mask */
#define MXC_F_CRC_CTRL_MSB_POS 2 /**< CTRL_MSB Position */ #define MXC_F_CRC_CTRL_MSB_POS 2 /**< CTRL_MSB Position */
#define MXC_F_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_MSB_POS)) /**< CTRL_MSB Mask */ #define MXC_F_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_MSB_POS)) /**< CTRL_MSB Mask */
#define MXC_F_CRC_CTRL_BYTE_SWAP_IN_POS 3 /**< CTRL_BYTE_SWAP_IN Position */ #define MXC_F_CRC_CTRL_BYTE_SWAP_IN_POS 3 /**< CTRL_BYTE_SWAP_IN Position */
#define MXC_F_CRC_CTRL_BYTE_SWAP_IN ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BYTE_SWAP_IN_POS)) /**< CTRL_BYTE_SWAP_IN Mask */ #define MXC_F_CRC_CTRL_BYTE_SWAP_IN ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BYTE_SWAP_IN_POS)) /**< CTRL_BYTE_SWAP_IN Mask */
#define MXC_F_CRC_CTRL_BYTE_SWAP_OUT_POS 4 /**< CTRL_BYTE_SWAP_OUT Position */ #define MXC_F_CRC_CTRL_BYTE_SWAP_OUT_POS 4 /**< CTRL_BYTE_SWAP_OUT Position */
#define MXC_F_CRC_CTRL_BYTE_SWAP_OUT ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BYTE_SWAP_OUT_POS)) /**< CTRL_BYTE_SWAP_OUT Mask */ #define MXC_F_CRC_CTRL_BYTE_SWAP_OUT ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BYTE_SWAP_OUT_POS)) /**< CTRL_BYTE_SWAP_OUT Mask */
#define MXC_F_CRC_CTRL_BUSY_POS 16 /**< CTRL_BUSY Position */ #define MXC_F_CRC_CTRL_BUSY_POS 16 /**< CTRL_BUSY Position */
#define MXC_F_CRC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ #define MXC_F_CRC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */
/**@} end of group CRC_CTRL_Register */ /**@} end of group CRC_CTRL_Register */
@ -140,8 +140,8 @@ typedef struct {
* @brief CRC Data Input * @brief CRC Data Input
* @{ * @{
*/ */
#define MXC_F_CRC_DATAIN32_DATA_POS 0 /**< DATAIN32_DATA Position */ #define MXC_F_CRC_DATAIN32_DATA_POS 0 /**< DATAIN32_DATA Position */
#define MXC_F_CRC_DATAIN32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_DATAIN32_DATA_POS)) /**< DATAIN32_DATA Mask */ #define MXC_F_CRC_DATAIN32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_DATAIN32_DATA_POS)) /**< DATAIN32_DATA Mask */
/**@} end of group CRC_DATAIN32_Register */ /**@} end of group CRC_DATAIN32_Register */
@ -151,8 +151,8 @@ typedef struct {
* @brief CRC Data Input * @brief CRC Data Input
* @{ * @{
*/ */
#define MXC_F_CRC_DATAIN16_DATA_POS 0 /**< DATAIN16_DATA Position */ #define MXC_F_CRC_DATAIN16_DATA_POS 0 /**< DATAIN16_DATA Position */
#define MXC_F_CRC_DATAIN16_DATA ((uint16_t)(0xFFFFUL << MXC_F_CRC_DATAIN16_DATA_POS)) /**< DATAIN16_DATA Mask */ #define MXC_F_CRC_DATAIN16_DATA ((uint16_t)(0xFFFFUL << MXC_F_CRC_DATAIN16_DATA_POS)) /**< DATAIN16_DATA Mask */
/**@} end of group CRC_DATAIN16_Register */ /**@} end of group CRC_DATAIN16_Register */
@ -162,8 +162,8 @@ typedef struct {
* @brief CRC Data Input * @brief CRC Data Input
* @{ * @{
*/ */
#define MXC_F_CRC_DATAIN8_DATA_POS 0 /**< DATAIN8_DATA Position */ #define MXC_F_CRC_DATAIN8_DATA_POS 0 /**< DATAIN8_DATA Position */
#define MXC_F_CRC_DATAIN8_DATA ((uint8_t)(0xFFUL << MXC_F_CRC_DATAIN8_DATA_POS)) /**< DATAIN8_DATA Mask */ #define MXC_F_CRC_DATAIN8_DATA ((uint8_t)(0xFFUL << MXC_F_CRC_DATAIN8_DATA_POS)) /**< DATAIN8_DATA Mask */
/**@} end of group CRC_DATAIN8_Register */ /**@} end of group CRC_DATAIN8_Register */
@ -173,8 +173,8 @@ typedef struct {
* @brief CRC Polynomial * @brief CRC Polynomial
* @{ * @{
*/ */
#define MXC_F_CRC_POLY_POLY_POS 0 /**< POLY_POLY Position */ #define MXC_F_CRC_POLY_POLY_POS 0 /**< POLY_POLY Position */
#define MXC_F_CRC_POLY_POLY ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_POLY_POLY_POS)) /**< POLY_POLY Mask */ #define MXC_F_CRC_POLY_POLY ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_POLY_POLY_POS)) /**< POLY_POLY Mask */
/**@} end of group CRC_POLY_Register */ /**@} end of group CRC_POLY_Register */
@ -184,8 +184,8 @@ typedef struct {
* @brief Current CRC Value * @brief Current CRC Value
* @{ * @{
*/ */
#define MXC_F_CRC_VAL_VALUE_POS 0 /**< VAL_VALUE Position */ #define MXC_F_CRC_VAL_VALUE_POS 0 /**< VAL_VALUE Position */
#define MXC_F_CRC_VAL_VALUE ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_VAL_VALUE_POS)) /**< VAL_VALUE Mask */ #define MXC_F_CRC_VAL_VALUE ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_VAL_VALUE_POS)) /**< VAL_VALUE Mask */
/**@} end of group CRC_VAL_Register */ /**@} end of group CRC_VAL_Register */
@ -193,4 +193,4 @@ typedef struct {
} }
#endif #endif
#endif /* _CRC_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_CRC_REGS_H_

436
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/dma_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file dma_regs.h * @file dma_regs.h
* @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _DMA_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_DMA_REGS_H_
#define _DMA_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_DMA_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,28 +75,24 @@ extern "C" {
* @ingroup dma * @ingroup dma
* @defgroup dma_registers DMA_Registers * @defgroup dma_registers DMA_Registers
* @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
* @details DMA Controller Fully programmable, chaining capable DMA channels. * @details DMA Controller Fully programmable, chaining capable DMA channels.
*/ */
/**
* @ingroup dma_registers
* Structure type to access the DMA Channel Registers.
*/
typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x100:</tt> DMA CTRL Register */
__IO uint32_t status; /**< <tt>\b 0x104:</tt> DMA STATUS Register */
__IO uint32_t src; /**< <tt>\b 0x108:</tt> DMA SRC Register */
__IO uint32_t dst; /**< <tt>\b 0x10C:</tt> DMA DST Register */
__IO uint32_t cnt; /**< <tt>\b 0x110:</tt> DMA CNT Register */
__IO uint32_t srcrld; /**< <tt>\b 0x114:</tt> DMA SRCRLD Register */
__IO uint32_t dstrld; /**< <tt>\b 0x118:</tt> DMA DSTRLD Register */
__IO uint32_t cntrld; /**< <tt>\b 0x11C:</tt> DMA CNTRLD Register */
} mxc_dma_ch_regs_t;
/** /**
* @ingroup dma_registers * @ingroup dma_registers
* Structure type to access the DMA Registers. * Structure type to access the DMA Registers.
*/ */
typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x000:</tt> DMA CTRL Register */
__IO uint32_t status; /**< <tt>\b 0x004:</tt> DMA STATUS Register */
__IO uint32_t src; /**< <tt>\b 0x008:</tt> DMA SRC Register */
__IO uint32_t dst; /**< <tt>\b 0x00C:</tt> DMA DST Register */
__IO uint32_t cnt; /**< <tt>\b 0x010:</tt> DMA CNT Register */
__IO uint32_t srcrld; /**< <tt>\b 0x014:</tt> DMA SRCRLD Register */
__IO uint32_t dstrld; /**< <tt>\b 0x018:</tt> DMA DSTRLD Register */
__IO uint32_t cntrld; /**< <tt>\b 0x01C:</tt> DMA CNTRLD Register */
} mxc_dma_ch_regs_t;
typedef struct { typedef struct {
__IO uint32_t inten; /**< <tt>\b 0x000:</tt> DMA INTEN Register */ __IO uint32_t inten; /**< <tt>\b 0x000:</tt> DMA INTEN Register */
__I uint32_t intfl; /**< <tt>\b 0x004:</tt> DMA INTFL Register */ __I uint32_t intfl; /**< <tt>\b 0x004:</tt> DMA INTFL Register */
@ -111,17 +107,17 @@ typedef struct {
* @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_DMA_CTRL ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */ #define MXC_R_DMA_CTRL ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */
#define MXC_R_DMA_STATUS ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */ #define MXC_R_DMA_STATUS ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */
#define MXC_R_DMA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */ #define MXC_R_DMA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: <tt> 0x0008</tt> */
#define MXC_R_DMA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */ #define MXC_R_DMA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: <tt> 0x000C</tt> */
#define MXC_R_DMA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */ #define MXC_R_DMA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: <tt> 0x0010</tt> */
#define MXC_R_DMA_SRCRLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */ #define MXC_R_DMA_SRCRLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: <tt> 0x0014</tt> */
#define MXC_R_DMA_DSTRLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */ #define MXC_R_DMA_DSTRLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: <tt> 0x0018</tt> */
#define MXC_R_DMA_CNTRLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */ #define MXC_R_DMA_CNTRLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: <tt> 0x001C</tt> */
#define MXC_R_DMA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */ #define MXC_R_DMA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */
#define MXC_R_DMA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */ #define MXC_R_DMA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */
#define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */ #define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
/**@} end of group dma_registers */ /**@} end of group dma_registers */
/** /**
@ -130,29 +126,29 @@ typedef struct {
* @brief DMA Control Register. * @brief DMA Control Register.
* @{ * @{
*/ */
#define MXC_F_DMA_INTEN_CH0_POS 0 /**< INTEN_CH0 Position */ #define MXC_F_DMA_INTEN_CH0_POS 0 /**< INTEN_CH0 Position */
#define MXC_F_DMA_INTEN_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH0_POS)) /**< INTEN_CH0 Mask */ #define MXC_F_DMA_INTEN_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH0_POS)) /**< INTEN_CH0 Mask */
#define MXC_F_DMA_INTEN_CH1_POS 1 /**< INTEN_CH1 Position */ #define MXC_F_DMA_INTEN_CH1_POS 1 /**< INTEN_CH1 Position */
#define MXC_F_DMA_INTEN_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH1_POS)) /**< INTEN_CH1 Mask */ #define MXC_F_DMA_INTEN_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH1_POS)) /**< INTEN_CH1 Mask */
#define MXC_F_DMA_INTEN_CH2_POS 2 /**< INTEN_CH2 Position */ #define MXC_F_DMA_INTEN_CH2_POS 2 /**< INTEN_CH2 Position */
#define MXC_F_DMA_INTEN_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH2_POS)) /**< INTEN_CH2 Mask */ #define MXC_F_DMA_INTEN_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH2_POS)) /**< INTEN_CH2 Mask */
#define MXC_F_DMA_INTEN_CH3_POS 3 /**< INTEN_CH3 Position */ #define MXC_F_DMA_INTEN_CH3_POS 3 /**< INTEN_CH3 Position */
#define MXC_F_DMA_INTEN_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH3_POS)) /**< INTEN_CH3 Mask */ #define MXC_F_DMA_INTEN_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH3_POS)) /**< INTEN_CH3 Mask */
#define MXC_F_DMA_INTEN_CH4_POS 4 /**< INTEN_CH4 Position */ #define MXC_F_DMA_INTEN_CH4_POS 4 /**< INTEN_CH4 Position */
#define MXC_F_DMA_INTEN_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH4_POS)) /**< INTEN_CH4 Mask */ #define MXC_F_DMA_INTEN_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH4_POS)) /**< INTEN_CH4 Mask */
#define MXC_F_DMA_INTEN_CH5_POS 5 /**< INTEN_CH5 Position */ #define MXC_F_DMA_INTEN_CH5_POS 5 /**< INTEN_CH5 Position */
#define MXC_F_DMA_INTEN_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH5_POS)) /**< INTEN_CH5 Mask */ #define MXC_F_DMA_INTEN_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH5_POS)) /**< INTEN_CH5 Mask */
#define MXC_F_DMA_INTEN_CH6_POS 6 /**< INTEN_CH6 Position */ #define MXC_F_DMA_INTEN_CH6_POS 6 /**< INTEN_CH6 Position */
#define MXC_F_DMA_INTEN_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH6_POS)) /**< INTEN_CH6 Mask */ #define MXC_F_DMA_INTEN_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH6_POS)) /**< INTEN_CH6 Mask */
#define MXC_F_DMA_INTEN_CH7_POS 7 /**< INTEN_CH7 Position */ #define MXC_F_DMA_INTEN_CH7_POS 7 /**< INTEN_CH7 Position */
#define MXC_F_DMA_INTEN_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH7_POS)) /**< INTEN_CH7 Mask */ #define MXC_F_DMA_INTEN_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH7_POS)) /**< INTEN_CH7 Mask */
/**@} end of group DMA_INTEN_Register */ /**@} end of group DMA_INTEN_Register */
@ -162,29 +158,29 @@ typedef struct {
* @brief DMA Interrupt Register. * @brief DMA Interrupt Register.
* @{ * @{
*/ */
#define MXC_F_DMA_INTFL_CH0_POS 0 /**< INTFL_CH0 Position */ #define MXC_F_DMA_INTFL_CH0_POS 0 /**< INTFL_CH0 Position */
#define MXC_F_DMA_INTFL_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH0_POS)) /**< INTFL_CH0 Mask */ #define MXC_F_DMA_INTFL_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH0_POS)) /**< INTFL_CH0 Mask */
#define MXC_F_DMA_INTFL_CH1_POS 1 /**< INTFL_CH1 Position */ #define MXC_F_DMA_INTFL_CH1_POS 1 /**< INTFL_CH1 Position */
#define MXC_F_DMA_INTFL_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH1_POS)) /**< INTFL_CH1 Mask */ #define MXC_F_DMA_INTFL_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH1_POS)) /**< INTFL_CH1 Mask */
#define MXC_F_DMA_INTFL_CH2_POS 2 /**< INTFL_CH2 Position */ #define MXC_F_DMA_INTFL_CH2_POS 2 /**< INTFL_CH2 Position */
#define MXC_F_DMA_INTFL_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH2_POS)) /**< INTFL_CH2 Mask */ #define MXC_F_DMA_INTFL_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH2_POS)) /**< INTFL_CH2 Mask */
#define MXC_F_DMA_INTFL_CH3_POS 3 /**< INTFL_CH3 Position */ #define MXC_F_DMA_INTFL_CH3_POS 3 /**< INTFL_CH3 Position */
#define MXC_F_DMA_INTFL_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH3_POS)) /**< INTFL_CH3 Mask */ #define MXC_F_DMA_INTFL_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH3_POS)) /**< INTFL_CH3 Mask */
#define MXC_F_DMA_INTFL_CH4_POS 4 /**< INTFL_CH4 Position */ #define MXC_F_DMA_INTFL_CH4_POS 4 /**< INTFL_CH4 Position */
#define MXC_F_DMA_INTFL_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH4_POS)) /**< INTFL_CH4 Mask */ #define MXC_F_DMA_INTFL_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH4_POS)) /**< INTFL_CH4 Mask */
#define MXC_F_DMA_INTFL_CH5_POS 5 /**< INTFL_CH5 Position */ #define MXC_F_DMA_INTFL_CH5_POS 5 /**< INTFL_CH5 Position */
#define MXC_F_DMA_INTFL_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH5_POS)) /**< INTFL_CH5 Mask */ #define MXC_F_DMA_INTFL_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH5_POS)) /**< INTFL_CH5 Mask */
#define MXC_F_DMA_INTFL_CH6_POS 6 /**< INTFL_CH6 Position */ #define MXC_F_DMA_INTFL_CH6_POS 6 /**< INTFL_CH6 Position */
#define MXC_F_DMA_INTFL_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH6_POS)) /**< INTFL_CH6 Mask */ #define MXC_F_DMA_INTFL_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH6_POS)) /**< INTFL_CH6 Mask */
#define MXC_F_DMA_INTFL_CH7_POS 7 /**< INTFL_CH7 Position */ #define MXC_F_DMA_INTFL_CH7_POS 7 /**< INTFL_CH7 Position */
#define MXC_F_DMA_INTFL_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH7_POS)) /**< INTFL_CH7 Mask */ #define MXC_F_DMA_INTFL_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH7_POS)) /**< INTFL_CH7 Mask */
/**@} end of group DMA_INTFL_Register */ /**@} end of group DMA_INTFL_Register */
@ -194,147 +190,147 @@ typedef struct {
* @brief DMA Channel Control Register. * @brief DMA Channel Control Register.
* @{ * @{
*/ */
#define MXC_F_DMA_CTRL_EN_POS 0 /**< CTRL_EN Position */ #define MXC_F_DMA_CTRL_EN_POS 0 /**< CTRL_EN Position */
#define MXC_F_DMA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_EN_POS)) /**< CTRL_EN Mask */ #define MXC_F_DMA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_EN_POS)) /**< CTRL_EN Mask */
#define MXC_F_DMA_CTRL_RLDEN_POS 1 /**< CTRL_RLDEN Position */ #define MXC_F_DMA_CTRL_RLDEN_POS 1 /**< CTRL_RLDEN Position */
#define MXC_F_DMA_CTRL_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_RLDEN_POS)) /**< CTRL_RLDEN Mask */ #define MXC_F_DMA_CTRL_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_RLDEN_POS)) /**< CTRL_RLDEN Mask */
#define MXC_F_DMA_CTRL_PRI_POS 2 /**< CTRL_PRI Position */ #define MXC_F_DMA_CTRL_PRI_POS 2 /**< CTRL_PRI Position */
#define MXC_F_DMA_CTRL_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_PRI_POS)) /**< CTRL_PRI Mask */ #define MXC_F_DMA_CTRL_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_PRI_POS)) /**< CTRL_PRI Mask */
#define MXC_V_DMA_CTRL_PRI_HIGH ((uint32_t)0x0UL) /**< CTRL_PRI_HIGH Value */ #define MXC_V_DMA_CTRL_PRI_HIGH ((uint32_t)0x0UL) /**< CTRL_PRI_HIGH Value */
#define MXC_S_DMA_CTRL_PRI_HIGH (MXC_V_DMA_CTRL_PRI_HIGH << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_HIGH Setting */ #define MXC_S_DMA_CTRL_PRI_HIGH (MXC_V_DMA_CTRL_PRI_HIGH << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_HIGH Setting */
#define MXC_V_DMA_CTRL_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CTRL_PRI_MEDHIGH Value */ #define MXC_V_DMA_CTRL_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CTRL_PRI_MEDHIGH Value */
#define MXC_S_DMA_CTRL_PRI_MEDHIGH (MXC_V_DMA_CTRL_PRI_MEDHIGH << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_MEDHIGH Setting */ #define MXC_S_DMA_CTRL_PRI_MEDHIGH (MXC_V_DMA_CTRL_PRI_MEDHIGH << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_MEDHIGH Setting */
#define MXC_V_DMA_CTRL_PRI_MEDLOW ((uint32_t)0x2UL) /**< CTRL_PRI_MEDLOW Value */ #define MXC_V_DMA_CTRL_PRI_MEDLOW ((uint32_t)0x2UL) /**< CTRL_PRI_MEDLOW Value */
#define MXC_S_DMA_CTRL_PRI_MEDLOW (MXC_V_DMA_CTRL_PRI_MEDLOW << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_MEDLOW Setting */ #define MXC_S_DMA_CTRL_PRI_MEDLOW (MXC_V_DMA_CTRL_PRI_MEDLOW << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_MEDLOW Setting */
#define MXC_V_DMA_CTRL_PRI_LOW ((uint32_t)0x3UL) /**< CTRL_PRI_LOW Value */ #define MXC_V_DMA_CTRL_PRI_LOW ((uint32_t)0x3UL) /**< CTRL_PRI_LOW Value */
#define MXC_S_DMA_CTRL_PRI_LOW (MXC_V_DMA_CTRL_PRI_LOW << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_LOW Setting */ #define MXC_S_DMA_CTRL_PRI_LOW (MXC_V_DMA_CTRL_PRI_LOW << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_LOW Setting */
#define MXC_F_DMA_CTRL_REQUEST_POS 4 /**< CTRL_REQUEST Position */ #define MXC_F_DMA_CTRL_REQUEST_POS 4 /**< CTRL_REQUEST Position */
#define MXC_F_DMA_CTRL_REQUEST ((uint32_t)(0x3FUL << MXC_F_DMA_CTRL_REQUEST_POS)) /**< CTRL_REQUEST Mask */ #define MXC_F_DMA_CTRL_REQUEST ((uint32_t)(0x3FUL << MXC_F_DMA_CTRL_REQUEST_POS)) /**< CTRL_REQUEST Mask */
#define MXC_V_DMA_CTRL_REQUEST_MEMTOMEM ((uint32_t)0x0UL) /**< CTRL_REQUEST_MEMTOMEM Value */ #define MXC_V_DMA_CTRL_REQUEST_MEMTOMEM ((uint32_t)0x0UL) /**< CTRL_REQUEST_MEMTOMEM Value */
#define MXC_S_DMA_CTRL_REQUEST_MEMTOMEM (MXC_V_DMA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_MEMTOMEM Setting */ #define MXC_S_DMA_CTRL_REQUEST_MEMTOMEM (MXC_V_DMA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_MEMTOMEM Setting */
#define MXC_V_DMA_CTRL_REQUEST_SPI0RX ((uint32_t)0x1UL) /**< CTRL_REQUEST_SPI0RX Value */ #define MXC_V_DMA_CTRL_REQUEST_SPI0RX ((uint32_t)0x1UL) /**< CTRL_REQUEST_SPI0RX Value */
#define MXC_S_DMA_CTRL_REQUEST_SPI0RX (MXC_V_DMA_CTRL_REQUEST_SPI0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0RX Setting */ #define MXC_S_DMA_CTRL_REQUEST_SPI0RX (MXC_V_DMA_CTRL_REQUEST_SPI0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0RX Setting */
#define MXC_V_DMA_CTRL_REQUEST_SPI1RX ((uint32_t)0x2UL) /**< CTRL_REQUEST_SPI1RX Value */ #define MXC_V_DMA_CTRL_REQUEST_SPI1RX ((uint32_t)0x2UL) /**< CTRL_REQUEST_SPI1RX Value */
#define MXC_S_DMA_CTRL_REQUEST_SPI1RX (MXC_V_DMA_CTRL_REQUEST_SPI1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1RX Setting */ #define MXC_S_DMA_CTRL_REQUEST_SPI1RX (MXC_V_DMA_CTRL_REQUEST_SPI1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1RX Setting */
#define MXC_V_DMA_CTRL_REQUEST_SPI2RX ((uint32_t)0x3UL) /**< CTRL_REQUEST_SPI2RX Value */ #define MXC_V_DMA_CTRL_REQUEST_SPI2RX ((uint32_t)0x3UL) /**< CTRL_REQUEST_SPI2RX Value */
#define MXC_S_DMA_CTRL_REQUEST_SPI2RX (MXC_V_DMA_CTRL_REQUEST_SPI2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2RX Setting */ #define MXC_S_DMA_CTRL_REQUEST_SPI2RX (MXC_V_DMA_CTRL_REQUEST_SPI2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2RX Setting */
#define MXC_V_DMA_CTRL_REQUEST_UART0RX ((uint32_t)0x4UL) /**< CTRL_REQUEST_UART0RX Value */ #define MXC_V_DMA_CTRL_REQUEST_UART0RX ((uint32_t)0x4UL) /**< CTRL_REQUEST_UART0RX Value */
#define MXC_S_DMA_CTRL_REQUEST_UART0RX (MXC_V_DMA_CTRL_REQUEST_UART0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0RX Setting */ #define MXC_S_DMA_CTRL_REQUEST_UART0RX (MXC_V_DMA_CTRL_REQUEST_UART0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0RX Setting */
#define MXC_V_DMA_CTRL_REQUEST_UART1RX ((uint32_t)0x5UL) /**< CTRL_REQUEST_UART1RX Value */ #define MXC_V_DMA_CTRL_REQUEST_UART1RX ((uint32_t)0x5UL) /**< CTRL_REQUEST_UART1RX Value */
#define MXC_S_DMA_CTRL_REQUEST_UART1RX (MXC_V_DMA_CTRL_REQUEST_UART1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1RX Setting */ #define MXC_S_DMA_CTRL_REQUEST_UART1RX (MXC_V_DMA_CTRL_REQUEST_UART1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1RX Setting */
#define MXC_V_DMA_CTRL_REQUEST_I2C0RX ((uint32_t)0x7UL) /**< CTRL_REQUEST_I2C0RX Value */ #define MXC_V_DMA_CTRL_REQUEST_I2C0RX ((uint32_t)0x7UL) /**< CTRL_REQUEST_I2C0RX Value */
#define MXC_S_DMA_CTRL_REQUEST_I2C0RX (MXC_V_DMA_CTRL_REQUEST_I2C0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0RX Setting */ #define MXC_S_DMA_CTRL_REQUEST_I2C0RX (MXC_V_DMA_CTRL_REQUEST_I2C0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0RX Setting */
#define MXC_V_DMA_CTRL_REQUEST_I2C1RX ((uint32_t)0x8UL) /**< CTRL_REQUEST_I2C1RX Value */ #define MXC_V_DMA_CTRL_REQUEST_I2C1RX ((uint32_t)0x8UL) /**< CTRL_REQUEST_I2C1RX Value */
#define MXC_S_DMA_CTRL_REQUEST_I2C1RX (MXC_V_DMA_CTRL_REQUEST_I2C1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1RX Setting */ #define MXC_S_DMA_CTRL_REQUEST_I2C1RX (MXC_V_DMA_CTRL_REQUEST_I2C1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1RX Setting */
#define MXC_V_DMA_CTRL_REQUEST_I2C2RX ((uint32_t)0xAUL) /**< CTRL_REQUEST_I2C2RX Value */ #define MXC_V_DMA_CTRL_REQUEST_I2C2RX ((uint32_t)0xAUL) /**< CTRL_REQUEST_I2C2RX Value */
#define MXC_S_DMA_CTRL_REQUEST_I2C2RX (MXC_V_DMA_CTRL_REQUEST_I2C2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C2RX Setting */ #define MXC_S_DMA_CTRL_REQUEST_I2C2RX (MXC_V_DMA_CTRL_REQUEST_I2C2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C2RX Setting */
#define MXC_V_DMA_CTRL_REQUEST_UART2RX ((uint32_t)0xEUL) /**< CTRL_REQUEST_UART2RX Value */ #define MXC_V_DMA_CTRL_REQUEST_UART2RX ((uint32_t)0xEUL) /**< CTRL_REQUEST_UART2RX Value */
#define MXC_S_DMA_CTRL_REQUEST_UART2RX (MXC_V_DMA_CTRL_REQUEST_UART2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2RX Setting */ #define MXC_S_DMA_CTRL_REQUEST_UART2RX (MXC_V_DMA_CTRL_REQUEST_UART2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2RX Setting */
#define MXC_V_DMA_CTRL_REQUEST_SPI3RX ((uint32_t)0xFUL) /**< CTRL_REQUEST_SPI3RX Value */ #define MXC_V_DMA_CTRL_REQUEST_SPI3RX ((uint32_t)0xFUL) /**< CTRL_REQUEST_SPI3RX Value */
#define MXC_S_DMA_CTRL_REQUEST_SPI3RX (MXC_V_DMA_CTRL_REQUEST_SPI3RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3RX Setting */ #define MXC_S_DMA_CTRL_REQUEST_SPI3RX (MXC_V_DMA_CTRL_REQUEST_SPI3RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3RX Setting */
#define MXC_V_DMA_CTRL_REQUEST_AESRX ((uint32_t)0x10UL) /**< CTRL_REQUEST_AESRX Value */ #define MXC_V_DMA_CTRL_REQUEST_AESRX ((uint32_t)0x10UL) /**< CTRL_REQUEST_AESRX Value */
#define MXC_S_DMA_CTRL_REQUEST_AESRX (MXC_V_DMA_CTRL_REQUEST_AESRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESRX Setting */ #define MXC_S_DMA_CTRL_REQUEST_AESRX (MXC_V_DMA_CTRL_REQUEST_AESRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESRX Setting */
#define MXC_V_DMA_CTRL_REQUEST_UART3RX ((uint32_t)0x1CUL) /**< CTRL_REQUEST_UART3RX Value */ #define MXC_V_DMA_CTRL_REQUEST_UART3RX ((uint32_t)0x1CUL) /**< CTRL_REQUEST_UART3RX Value */
#define MXC_S_DMA_CTRL_REQUEST_UART3RX (MXC_V_DMA_CTRL_REQUEST_UART3RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART3RX Setting */ #define MXC_S_DMA_CTRL_REQUEST_UART3RX (MXC_V_DMA_CTRL_REQUEST_UART3RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART3RX Setting */
#define MXC_V_DMA_CTRL_REQUEST_I2SRX ((uint32_t)0x1EUL) /**< CTRL_REQUEST_I2SRX Value */ #define MXC_V_DMA_CTRL_REQUEST_I2SRX ((uint32_t)0x1EUL) /**< CTRL_REQUEST_I2SRX Value */
#define MXC_S_DMA_CTRL_REQUEST_I2SRX (MXC_V_DMA_CTRL_REQUEST_I2SRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2SRX Setting */ #define MXC_S_DMA_CTRL_REQUEST_I2SRX (MXC_V_DMA_CTRL_REQUEST_I2SRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2SRX Setting */
#define MXC_V_DMA_CTRL_REQUEST_SPI0TX ((uint32_t)0x21UL) /**< CTRL_REQUEST_SPI0TX Value */ #define MXC_V_DMA_CTRL_REQUEST_SPI0TX ((uint32_t)0x21UL) /**< CTRL_REQUEST_SPI0TX Value */
#define MXC_S_DMA_CTRL_REQUEST_SPI0TX (MXC_V_DMA_CTRL_REQUEST_SPI0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0TX Setting */ #define MXC_S_DMA_CTRL_REQUEST_SPI0TX (MXC_V_DMA_CTRL_REQUEST_SPI0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0TX Setting */
#define MXC_V_DMA_CTRL_REQUEST_SPI1TX ((uint32_t)0x22UL) /**< CTRL_REQUEST_SPI1TX Value */ #define MXC_V_DMA_CTRL_REQUEST_SPI1TX ((uint32_t)0x22UL) /**< CTRL_REQUEST_SPI1TX Value */
#define MXC_S_DMA_CTRL_REQUEST_SPI1TX (MXC_V_DMA_CTRL_REQUEST_SPI1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1TX Setting */ #define MXC_S_DMA_CTRL_REQUEST_SPI1TX (MXC_V_DMA_CTRL_REQUEST_SPI1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1TX Setting */
#define MXC_V_DMA_CTRL_REQUEST_SPI2TX ((uint32_t)0x23UL) /**< CTRL_REQUEST_SPI2TX Value */ #define MXC_V_DMA_CTRL_REQUEST_SPI2TX ((uint32_t)0x23UL) /**< CTRL_REQUEST_SPI2TX Value */
#define MXC_S_DMA_CTRL_REQUEST_SPI2TX (MXC_V_DMA_CTRL_REQUEST_SPI2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2TX Setting */ #define MXC_S_DMA_CTRL_REQUEST_SPI2TX (MXC_V_DMA_CTRL_REQUEST_SPI2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2TX Setting */
#define MXC_V_DMA_CTRL_REQUEST_UART0TX ((uint32_t)0x24UL) /**< CTRL_REQUEST_UART0TX Value */ #define MXC_V_DMA_CTRL_REQUEST_UART0TX ((uint32_t)0x24UL) /**< CTRL_REQUEST_UART0TX Value */
#define MXC_S_DMA_CTRL_REQUEST_UART0TX (MXC_V_DMA_CTRL_REQUEST_UART0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0TX Setting */ #define MXC_S_DMA_CTRL_REQUEST_UART0TX (MXC_V_DMA_CTRL_REQUEST_UART0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0TX Setting */
#define MXC_V_DMA_CTRL_REQUEST_UART1TX ((uint32_t)0x25UL) /**< CTRL_REQUEST_UART1TX Value */ #define MXC_V_DMA_CTRL_REQUEST_UART1TX ((uint32_t)0x25UL) /**< CTRL_REQUEST_UART1TX Value */
#define MXC_S_DMA_CTRL_REQUEST_UART1TX (MXC_V_DMA_CTRL_REQUEST_UART1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1TX Setting */ #define MXC_S_DMA_CTRL_REQUEST_UART1TX (MXC_V_DMA_CTRL_REQUEST_UART1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1TX Setting */
#define MXC_V_DMA_CTRL_REQUEST_I2C0TX ((uint32_t)0x27UL) /**< CTRL_REQUEST_I2C0TX Value */ #define MXC_V_DMA_CTRL_REQUEST_I2C0TX ((uint32_t)0x27UL) /**< CTRL_REQUEST_I2C0TX Value */
#define MXC_S_DMA_CTRL_REQUEST_I2C0TX (MXC_V_DMA_CTRL_REQUEST_I2C0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0TX Setting */ #define MXC_S_DMA_CTRL_REQUEST_I2C0TX (MXC_V_DMA_CTRL_REQUEST_I2C0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0TX Setting */
#define MXC_V_DMA_CTRL_REQUEST_I2C1TX ((uint32_t)0x28UL) /**< CTRL_REQUEST_I2C1TX Value */ #define MXC_V_DMA_CTRL_REQUEST_I2C1TX ((uint32_t)0x28UL) /**< CTRL_REQUEST_I2C1TX Value */
#define MXC_S_DMA_CTRL_REQUEST_I2C1TX (MXC_V_DMA_CTRL_REQUEST_I2C1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1TX Setting */ #define MXC_S_DMA_CTRL_REQUEST_I2C1TX (MXC_V_DMA_CTRL_REQUEST_I2C1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1TX Setting */
#define MXC_V_DMA_CTRL_REQUEST_I2C2TX ((uint32_t)0x2AUL) /**< CTRL_REQUEST_I2C2TX Value */ #define MXC_V_DMA_CTRL_REQUEST_I2C2TX ((uint32_t)0x2AUL) /**< CTRL_REQUEST_I2C2TX Value */
#define MXC_S_DMA_CTRL_REQUEST_I2C2TX (MXC_V_DMA_CTRL_REQUEST_I2C2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C2TX Setting */ #define MXC_S_DMA_CTRL_REQUEST_I2C2TX (MXC_V_DMA_CTRL_REQUEST_I2C2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C2TX Setting */
#define MXC_V_DMA_CTRL_REQUEST_CRCTX ((uint32_t)0x2CUL) /**< CTRL_REQUEST_CRCTX Value */ #define MXC_V_DMA_CTRL_REQUEST_CRCTX ((uint32_t)0x2CUL) /**< CTRL_REQUEST_CRCTX Value */
#define MXC_S_DMA_CTRL_REQUEST_CRCTX (MXC_V_DMA_CTRL_REQUEST_CRCTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_CRCTX Setting */ #define MXC_S_DMA_CTRL_REQUEST_CRCTX (MXC_V_DMA_CTRL_REQUEST_CRCTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_CRCTX Setting */
#define MXC_V_DMA_CTRL_REQUEST_UART2TX ((uint32_t)0x2EUL) /**< CTRL_REQUEST_UART2TX Value */ #define MXC_V_DMA_CTRL_REQUEST_UART2TX ((uint32_t)0x2EUL) /**< CTRL_REQUEST_UART2TX Value */
#define MXC_S_DMA_CTRL_REQUEST_UART2TX (MXC_V_DMA_CTRL_REQUEST_UART2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2TX Setting */ #define MXC_S_DMA_CTRL_REQUEST_UART2TX (MXC_V_DMA_CTRL_REQUEST_UART2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2TX Setting */
#define MXC_V_DMA_CTRL_REQUEST_SPI3TX ((uint32_t)0x2FUL) /**< CTRL_REQUEST_SPI3TX Value */ #define MXC_V_DMA_CTRL_REQUEST_SPI3TX ((uint32_t)0x2FUL) /**< CTRL_REQUEST_SPI3TX Value */
#define MXC_S_DMA_CTRL_REQUEST_SPI3TX (MXC_V_DMA_CTRL_REQUEST_SPI3TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3TX Setting */ #define MXC_S_DMA_CTRL_REQUEST_SPI3TX (MXC_V_DMA_CTRL_REQUEST_SPI3TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3TX Setting */
#define MXC_V_DMA_CTRL_REQUEST_AESTX ((uint32_t)0x30UL) /**< CTRL_REQUEST_AESTX Value */ #define MXC_V_DMA_CTRL_REQUEST_AESTX ((uint32_t)0x30UL) /**< CTRL_REQUEST_AESTX Value */
#define MXC_S_DMA_CTRL_REQUEST_AESTX (MXC_V_DMA_CTRL_REQUEST_AESTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESTX Setting */ #define MXC_S_DMA_CTRL_REQUEST_AESTX (MXC_V_DMA_CTRL_REQUEST_AESTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESTX Setting */
#define MXC_V_DMA_CTRL_REQUEST_UART3TX ((uint32_t)0x3CUL) /**< CTRL_REQUEST_UART3TX Value */ #define MXC_V_DMA_CTRL_REQUEST_UART3TX ((uint32_t)0x3CUL) /**< CTRL_REQUEST_UART3TX Value */
#define MXC_S_DMA_CTRL_REQUEST_UART3TX (MXC_V_DMA_CTRL_REQUEST_UART3TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART3TX Setting */ #define MXC_S_DMA_CTRL_REQUEST_UART3TX (MXC_V_DMA_CTRL_REQUEST_UART3TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART3TX Setting */
#define MXC_V_DMA_CTRL_REQUEST_I2STX ((uint32_t)0x3EUL) /**< CTRL_REQUEST_I2STX Value */ #define MXC_V_DMA_CTRL_REQUEST_I2STX ((uint32_t)0x3EUL) /**< CTRL_REQUEST_I2STX Value */
#define MXC_S_DMA_CTRL_REQUEST_I2STX (MXC_V_DMA_CTRL_REQUEST_I2STX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2STX Setting */ #define MXC_S_DMA_CTRL_REQUEST_I2STX (MXC_V_DMA_CTRL_REQUEST_I2STX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2STX Setting */
#define MXC_F_DMA_CTRL_TO_WAIT_POS 10 /**< CTRL_TO_WAIT Position */ #define MXC_F_DMA_CTRL_TO_WAIT_POS 10 /**< CTRL_TO_WAIT Position */
#define MXC_F_DMA_CTRL_TO_WAIT ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_TO_WAIT_POS)) /**< CTRL_TO_WAIT Mask */ #define MXC_F_DMA_CTRL_TO_WAIT ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_TO_WAIT_POS)) /**< CTRL_TO_WAIT Mask */
#define MXC_F_DMA_CTRL_TO_PER_POS 11 /**< CTRL_TO_PER Position */ #define MXC_F_DMA_CTRL_TO_PER_POS 11 /**< CTRL_TO_PER Position */
#define MXC_F_DMA_CTRL_TO_PER ((uint32_t)(0x7UL << MXC_F_DMA_CTRL_TO_PER_POS)) /**< CTRL_TO_PER Mask */ #define MXC_F_DMA_CTRL_TO_PER ((uint32_t)(0x7UL << MXC_F_DMA_CTRL_TO_PER_POS)) /**< CTRL_TO_PER Mask */
#define MXC_V_DMA_CTRL_TO_PER_TO4 ((uint32_t)0x0UL) /**< CTRL_TO_PER_TO4 Value */ #define MXC_V_DMA_CTRL_TO_PER_TO4 ((uint32_t)0x0UL) /**< CTRL_TO_PER_TO4 Value */
#define MXC_S_DMA_CTRL_TO_PER_TO4 (MXC_V_DMA_CTRL_TO_PER_TO4 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO4 Setting */ #define MXC_S_DMA_CTRL_TO_PER_TO4 (MXC_V_DMA_CTRL_TO_PER_TO4 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO4 Setting */
#define MXC_V_DMA_CTRL_TO_PER_TO8 ((uint32_t)0x1UL) /**< CTRL_TO_PER_TO8 Value */ #define MXC_V_DMA_CTRL_TO_PER_TO8 ((uint32_t)0x1UL) /**< CTRL_TO_PER_TO8 Value */
#define MXC_S_DMA_CTRL_TO_PER_TO8 (MXC_V_DMA_CTRL_TO_PER_TO8 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO8 Setting */ #define MXC_S_DMA_CTRL_TO_PER_TO8 (MXC_V_DMA_CTRL_TO_PER_TO8 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO8 Setting */
#define MXC_V_DMA_CTRL_TO_PER_TO16 ((uint32_t)0x2UL) /**< CTRL_TO_PER_TO16 Value */ #define MXC_V_DMA_CTRL_TO_PER_TO16 ((uint32_t)0x2UL) /**< CTRL_TO_PER_TO16 Value */
#define MXC_S_DMA_CTRL_TO_PER_TO16 (MXC_V_DMA_CTRL_TO_PER_TO16 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO16 Setting */ #define MXC_S_DMA_CTRL_TO_PER_TO16 (MXC_V_DMA_CTRL_TO_PER_TO16 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO16 Setting */
#define MXC_V_DMA_CTRL_TO_PER_TO32 ((uint32_t)0x3UL) /**< CTRL_TO_PER_TO32 Value */ #define MXC_V_DMA_CTRL_TO_PER_TO32 ((uint32_t)0x3UL) /**< CTRL_TO_PER_TO32 Value */
#define MXC_S_DMA_CTRL_TO_PER_TO32 (MXC_V_DMA_CTRL_TO_PER_TO32 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO32 Setting */ #define MXC_S_DMA_CTRL_TO_PER_TO32 (MXC_V_DMA_CTRL_TO_PER_TO32 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO32 Setting */
#define MXC_V_DMA_CTRL_TO_PER_TO64 ((uint32_t)0x4UL) /**< CTRL_TO_PER_TO64 Value */ #define MXC_V_DMA_CTRL_TO_PER_TO64 ((uint32_t)0x4UL) /**< CTRL_TO_PER_TO64 Value */
#define MXC_S_DMA_CTRL_TO_PER_TO64 (MXC_V_DMA_CTRL_TO_PER_TO64 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO64 Setting */ #define MXC_S_DMA_CTRL_TO_PER_TO64 (MXC_V_DMA_CTRL_TO_PER_TO64 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO64 Setting */
#define MXC_V_DMA_CTRL_TO_PER_TO128 ((uint32_t)0x5UL) /**< CTRL_TO_PER_TO128 Value */ #define MXC_V_DMA_CTRL_TO_PER_TO128 ((uint32_t)0x5UL) /**< CTRL_TO_PER_TO128 Value */
#define MXC_S_DMA_CTRL_TO_PER_TO128 (MXC_V_DMA_CTRL_TO_PER_TO128 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO128 Setting */ #define MXC_S_DMA_CTRL_TO_PER_TO128 (MXC_V_DMA_CTRL_TO_PER_TO128 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO128 Setting */
#define MXC_V_DMA_CTRL_TO_PER_TO256 ((uint32_t)0x6UL) /**< CTRL_TO_PER_TO256 Value */ #define MXC_V_DMA_CTRL_TO_PER_TO256 ((uint32_t)0x6UL) /**< CTRL_TO_PER_TO256 Value */
#define MXC_S_DMA_CTRL_TO_PER_TO256 (MXC_V_DMA_CTRL_TO_PER_TO256 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO256 Setting */ #define MXC_S_DMA_CTRL_TO_PER_TO256 (MXC_V_DMA_CTRL_TO_PER_TO256 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO256 Setting */
#define MXC_V_DMA_CTRL_TO_PER_TO512 ((uint32_t)0x7UL) /**< CTRL_TO_PER_TO512 Value */ #define MXC_V_DMA_CTRL_TO_PER_TO512 ((uint32_t)0x7UL) /**< CTRL_TO_PER_TO512 Value */
#define MXC_S_DMA_CTRL_TO_PER_TO512 (MXC_V_DMA_CTRL_TO_PER_TO512 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO512 Setting */ #define MXC_S_DMA_CTRL_TO_PER_TO512 (MXC_V_DMA_CTRL_TO_PER_TO512 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO512 Setting */
#define MXC_F_DMA_CTRL_TO_CLKDIV_POS 14 /**< CTRL_TO_CLKDIV Position */ #define MXC_F_DMA_CTRL_TO_CLKDIV_POS 14 /**< CTRL_TO_CLKDIV Position */
#define MXC_F_DMA_CTRL_TO_CLKDIV ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_TO_CLKDIV_POS)) /**< CTRL_TO_CLKDIV Mask */ #define MXC_F_DMA_CTRL_TO_CLKDIV ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_TO_CLKDIV_POS)) /**< CTRL_TO_CLKDIV Mask */
#define MXC_V_DMA_CTRL_TO_CLKDIV_DIS ((uint32_t)0x0UL) /**< CTRL_TO_CLKDIV_DIS Value */ #define MXC_V_DMA_CTRL_TO_CLKDIV_DIS ((uint32_t)0x0UL) /**< CTRL_TO_CLKDIV_DIS Value */
#define MXC_S_DMA_CTRL_TO_CLKDIV_DIS (MXC_V_DMA_CTRL_TO_CLKDIV_DIS << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIS Setting */ #define MXC_S_DMA_CTRL_TO_CLKDIV_DIS (MXC_V_DMA_CTRL_TO_CLKDIV_DIS << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIS Setting */
#define MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 ((uint32_t)0x1UL) /**< CTRL_TO_CLKDIV_DIV256 Value */ #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 ((uint32_t)0x1UL) /**< CTRL_TO_CLKDIV_DIV256 Value */
#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV256 (MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV256 Setting */ #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV256 (MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV256 Setting */
#define MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K ((uint32_t)0x2UL) /**< CTRL_TO_CLKDIV_DIV64K Value */ #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K ((uint32_t)0x2UL) /**< CTRL_TO_CLKDIV_DIV64K Value */
#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K (MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV64K Setting */ #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K (MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV64K Setting */
#define MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M ((uint32_t)0x3UL) /**< CTRL_TO_CLKDIV_DIV16M Value */ #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M ((uint32_t)0x3UL) /**< CTRL_TO_CLKDIV_DIV16M Value */
#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M (MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV16M Setting */ #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M (MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV16M Setting */
#define MXC_F_DMA_CTRL_SRCWD_POS 16 /**< CTRL_SRCWD Position */ #define MXC_F_DMA_CTRL_SRCWD_POS 16 /**< CTRL_SRCWD Position */
#define MXC_F_DMA_CTRL_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_SRCWD_POS)) /**< CTRL_SRCWD Mask */ #define MXC_F_DMA_CTRL_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_SRCWD_POS)) /**< CTRL_SRCWD Mask */
#define MXC_V_DMA_CTRL_SRCWD_BYTE ((uint32_t)0x0UL) /**< CTRL_SRCWD_BYTE Value */ #define MXC_V_DMA_CTRL_SRCWD_BYTE ((uint32_t)0x0UL) /**< CTRL_SRCWD_BYTE Value */
#define MXC_S_DMA_CTRL_SRCWD_BYTE (MXC_V_DMA_CTRL_SRCWD_BYTE << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_BYTE Setting */ #define MXC_S_DMA_CTRL_SRCWD_BYTE (MXC_V_DMA_CTRL_SRCWD_BYTE << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_BYTE Setting */
#define MXC_V_DMA_CTRL_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_SRCWD_HALFWORD Value */ #define MXC_V_DMA_CTRL_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_SRCWD_HALFWORD Value */
#define MXC_S_DMA_CTRL_SRCWD_HALFWORD (MXC_V_DMA_CTRL_SRCWD_HALFWORD << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_HALFWORD Setting */ #define MXC_S_DMA_CTRL_SRCWD_HALFWORD (MXC_V_DMA_CTRL_SRCWD_HALFWORD << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_HALFWORD Setting */
#define MXC_V_DMA_CTRL_SRCWD_WORD ((uint32_t)0x2UL) /**< CTRL_SRCWD_WORD Value */ #define MXC_V_DMA_CTRL_SRCWD_WORD ((uint32_t)0x2UL) /**< CTRL_SRCWD_WORD Value */
#define MXC_S_DMA_CTRL_SRCWD_WORD (MXC_V_DMA_CTRL_SRCWD_WORD << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_WORD Setting */ #define MXC_S_DMA_CTRL_SRCWD_WORD (MXC_V_DMA_CTRL_SRCWD_WORD << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_WORD Setting */
#define MXC_F_DMA_CTRL_SRCINC_POS 18 /**< CTRL_SRCINC Position */ #define MXC_F_DMA_CTRL_SRCINC_POS 18 /**< CTRL_SRCINC Position */
#define MXC_F_DMA_CTRL_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_SRCINC_POS)) /**< CTRL_SRCINC Mask */ #define MXC_F_DMA_CTRL_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_SRCINC_POS)) /**< CTRL_SRCINC Mask */
#define MXC_F_DMA_CTRL_DSTWD_POS 20 /**< CTRL_DSTWD Position */ #define MXC_F_DMA_CTRL_DSTWD_POS 20 /**< CTRL_DSTWD Position */
#define MXC_F_DMA_CTRL_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_DSTWD_POS)) /**< CTRL_DSTWD Mask */ #define MXC_F_DMA_CTRL_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_DSTWD_POS)) /**< CTRL_DSTWD Mask */
#define MXC_V_DMA_CTRL_DSTWD_BYTE ((uint32_t)0x0UL) /**< CTRL_DSTWD_BYTE Value */ #define MXC_V_DMA_CTRL_DSTWD_BYTE ((uint32_t)0x0UL) /**< CTRL_DSTWD_BYTE Value */
#define MXC_S_DMA_CTRL_DSTWD_BYTE (MXC_V_DMA_CTRL_DSTWD_BYTE << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_BYTE Setting */ #define MXC_S_DMA_CTRL_DSTWD_BYTE (MXC_V_DMA_CTRL_DSTWD_BYTE << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_BYTE Setting */
#define MXC_V_DMA_CTRL_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_DSTWD_HALFWORD Value */ #define MXC_V_DMA_CTRL_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_DSTWD_HALFWORD Value */
#define MXC_S_DMA_CTRL_DSTWD_HALFWORD (MXC_V_DMA_CTRL_DSTWD_HALFWORD << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_HALFWORD Setting */ #define MXC_S_DMA_CTRL_DSTWD_HALFWORD (MXC_V_DMA_CTRL_DSTWD_HALFWORD << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_HALFWORD Setting */
#define MXC_V_DMA_CTRL_DSTWD_WORD ((uint32_t)0x2UL) /**< CTRL_DSTWD_WORD Value */ #define MXC_V_DMA_CTRL_DSTWD_WORD ((uint32_t)0x2UL) /**< CTRL_DSTWD_WORD Value */
#define MXC_S_DMA_CTRL_DSTWD_WORD (MXC_V_DMA_CTRL_DSTWD_WORD << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_WORD Setting */ #define MXC_S_DMA_CTRL_DSTWD_WORD (MXC_V_DMA_CTRL_DSTWD_WORD << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_WORD Setting */
#define MXC_F_DMA_CTRL_DSTINC_POS 22 /**< CTRL_DSTINC Position */ #define MXC_F_DMA_CTRL_DSTINC_POS 22 /**< CTRL_DSTINC Position */
#define MXC_F_DMA_CTRL_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DSTINC_POS)) /**< CTRL_DSTINC Mask */ #define MXC_F_DMA_CTRL_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DSTINC_POS)) /**< CTRL_DSTINC Mask */
#define MXC_F_DMA_CTRL_BURST_SIZE_POS 24 /**< CTRL_BURST_SIZE Position */ #define MXC_F_DMA_CTRL_BURST_SIZE_POS 24 /**< CTRL_BURST_SIZE Position */
#define MXC_F_DMA_CTRL_BURST_SIZE ((uint32_t)(0x1FUL << MXC_F_DMA_CTRL_BURST_SIZE_POS)) /**< CTRL_BURST_SIZE Mask */ #define MXC_F_DMA_CTRL_BURST_SIZE ((uint32_t)(0x1FUL << MXC_F_DMA_CTRL_BURST_SIZE_POS)) /**< CTRL_BURST_SIZE Mask */
#define MXC_F_DMA_CTRL_DIS_IE_POS 30 /**< CTRL_DIS_IE Position */ #define MXC_F_DMA_CTRL_DIS_IE_POS 30 /**< CTRL_DIS_IE Position */
#define MXC_F_DMA_CTRL_DIS_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DIS_IE_POS)) /**< CTRL_DIS_IE Mask */ #define MXC_F_DMA_CTRL_DIS_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DIS_IE_POS)) /**< CTRL_DIS_IE Mask */
#define MXC_F_DMA_CTRL_CTZ_IE_POS 31 /**< CTRL_CTZ_IE Position */ #define MXC_F_DMA_CTRL_CTZ_IE_POS 31 /**< CTRL_CTZ_IE Position */
#define MXC_F_DMA_CTRL_CTZ_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_CTZ_IE_POS)) /**< CTRL_CTZ_IE Mask */ #define MXC_F_DMA_CTRL_CTZ_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_CTZ_IE_POS)) /**< CTRL_CTZ_IE Mask */
/**@} end of group DMA_CTRL_Register */ /**@} end of group DMA_CTRL_Register */
@ -344,23 +340,23 @@ typedef struct {
* @brief DMA Channel Status Register. * @brief DMA Channel Status Register.
* @{ * @{
*/ */
#define MXC_F_DMA_STATUS_STATUS_POS 0 /**< STATUS_STATUS Position */ #define MXC_F_DMA_STATUS_STATUS_POS 0 /**< STATUS_STATUS Position */
#define MXC_F_DMA_STATUS_STATUS ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */ #define MXC_F_DMA_STATUS_STATUS ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */
#define MXC_F_DMA_STATUS_IPEND_POS 1 /**< STATUS_IPEND Position */ #define MXC_F_DMA_STATUS_IPEND_POS 1 /**< STATUS_IPEND Position */
#define MXC_F_DMA_STATUS_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_IPEND_POS)) /**< STATUS_IPEND Mask */ #define MXC_F_DMA_STATUS_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_IPEND_POS)) /**< STATUS_IPEND Mask */
#define MXC_F_DMA_STATUS_CTZ_IF_POS 2 /**< STATUS_CTZ_IF Position */ #define MXC_F_DMA_STATUS_CTZ_IF_POS 2 /**< STATUS_CTZ_IF Position */
#define MXC_F_DMA_STATUS_CTZ_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_CTZ_IF_POS)) /**< STATUS_CTZ_IF Mask */ #define MXC_F_DMA_STATUS_CTZ_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_CTZ_IF_POS)) /**< STATUS_CTZ_IF Mask */
#define MXC_F_DMA_STATUS_RLD_IF_POS 3 /**< STATUS_RLD_IF Position */ #define MXC_F_DMA_STATUS_RLD_IF_POS 3 /**< STATUS_RLD_IF Position */
#define MXC_F_DMA_STATUS_RLD_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_RLD_IF_POS)) /**< STATUS_RLD_IF Mask */ #define MXC_F_DMA_STATUS_RLD_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_RLD_IF_POS)) /**< STATUS_RLD_IF Mask */
#define MXC_F_DMA_STATUS_BUS_ERR_POS 4 /**< STATUS_BUS_ERR Position */ #define MXC_F_DMA_STATUS_BUS_ERR_POS 4 /**< STATUS_BUS_ERR Position */
#define MXC_F_DMA_STATUS_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_BUS_ERR_POS)) /**< STATUS_BUS_ERR Mask */ #define MXC_F_DMA_STATUS_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_BUS_ERR_POS)) /**< STATUS_BUS_ERR Mask */
#define MXC_F_DMA_STATUS_TO_IF_POS 6 /**< STATUS_TO_IF Position */ #define MXC_F_DMA_STATUS_TO_IF_POS 6 /**< STATUS_TO_IF Position */
#define MXC_F_DMA_STATUS_TO_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_TO_IF_POS)) /**< STATUS_TO_IF Mask */ #define MXC_F_DMA_STATUS_TO_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_TO_IF_POS)) /**< STATUS_TO_IF Mask */
/**@} end of group DMA_STATUS_Register */ /**@} end of group DMA_STATUS_Register */
@ -374,8 +370,8 @@ typedef struct {
* register is reloaded with the contents of DMA_SRC_RLD. * register is reloaded with the contents of DMA_SRC_RLD.
* @{ * @{
*/ */
#define MXC_F_DMA_SRC_ADDR_POS 0 /**< SRC_ADDR Position */ #define MXC_F_DMA_SRC_ADDR_POS 0 /**< SRC_ADDR Position */
#define MXC_F_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */ #define MXC_F_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */
/**@} end of group DMA_SRC_Register */ /**@} end of group DMA_SRC_Register */
@ -389,8 +385,8 @@ typedef struct {
* while RLDEN=1, the register is reloaded with DMA_DST_RLD. * while RLDEN=1, the register is reloaded with DMA_DST_RLD.
* @{ * @{
*/ */
#define MXC_F_DMA_DST_ADDR_POS 0 /**< DST_ADDR Position */ #define MXC_F_DMA_DST_ADDR_POS 0 /**< DST_ADDR Position */
#define MXC_F_DMA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS)) /**< DST_ADDR Mask */ #define MXC_F_DMA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS)) /**< DST_ADDR Mask */
/**@} end of group DMA_DST_Register */ /**@} end of group DMA_DST_Register */
@ -403,8 +399,8 @@ typedef struct {
* reaches 0, a count-to-zero condition is triggered. * reaches 0, a count-to-zero condition is triggered.
* @{ * @{
*/ */
#define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */ #define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */
#define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */ #define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */
/**@} end of group DMA_CNT_Register */ /**@} end of group DMA_CNT_Register */
@ -415,8 +411,8 @@ typedef struct {
* upon a count-to-zero condition. * upon a count-to-zero condition.
* @{ * @{
*/ */
#define MXC_F_DMA_SRCRLD_ADDR_POS 0 /**< SRCRLD_ADDR Position */ #define MXC_F_DMA_SRCRLD_ADDR_POS 0 /**< SRCRLD_ADDR Position */
#define MXC_F_DMA_SRCRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRCRLD_ADDR_POS)) /**< SRCRLD_ADDR Mask */ #define MXC_F_DMA_SRCRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRCRLD_ADDR_POS)) /**< SRCRLD_ADDR Mask */
/**@} end of group DMA_SRCRLD_Register */ /**@} end of group DMA_SRCRLD_Register */
@ -427,8 +423,8 @@ typedef struct {
* DMA0_DST upon a count-to-zero condition. * DMA0_DST upon a count-to-zero condition.
* @{ * @{
*/ */
#define MXC_F_DMA_DSTRLD_ADDR_POS 0 /**< DSTRLD_ADDR Position */ #define MXC_F_DMA_DSTRLD_ADDR_POS 0 /**< DSTRLD_ADDR Position */
#define MXC_F_DMA_DSTRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DSTRLD_ADDR_POS)) /**< DSTRLD_ADDR Mask */ #define MXC_F_DMA_DSTRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DSTRLD_ADDR_POS)) /**< DSTRLD_ADDR Mask */
/**@} end of group DMA_DSTRLD_Register */ /**@} end of group DMA_DSTRLD_Register */
@ -438,11 +434,11 @@ typedef struct {
* @brief DMA Channel Count Reload Register. * @brief DMA Channel Count Reload Register.
* @{ * @{
*/ */
#define MXC_F_DMA_CNTRLD_CNT_POS 0 /**< CNTRLD_CNT Position */ #define MXC_F_DMA_CNTRLD_CNT_POS 0 /**< CNTRLD_CNT Position */
#define MXC_F_DMA_CNTRLD_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNTRLD_CNT_POS)) /**< CNTRLD_CNT Mask */ #define MXC_F_DMA_CNTRLD_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNTRLD_CNT_POS)) /**< CNTRLD_CNT Mask */
#define MXC_F_DMA_CNTRLD_EN_POS 31 /**< CNTRLD_EN Position */ #define MXC_F_DMA_CNTRLD_EN_POS 31 /**< CNTRLD_EN Position */
#define MXC_F_DMA_CNTRLD_EN ((uint32_t)(0x1UL << MXC_F_DMA_CNTRLD_EN_POS)) /**< CNTRLD_EN Mask */ #define MXC_F_DMA_CNTRLD_EN ((uint32_t)(0x1UL << MXC_F_DMA_CNTRLD_EN_POS)) /**< CNTRLD_EN Mask */
/**@} end of group DMA_CNTRLD_Register */ /**@} end of group DMA_CNTRLD_Register */
@ -450,4 +446,4 @@ typedef struct {
} }
#endif #endif
#endif /* _DMA_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_DMA_REGS_H_

32
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/ecc_regs.h
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@ -1,10 +1,11 @@
/** /**
* @file ecc_regs.h * @file ecc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the ECC Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the ECC Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _ECC_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_ECC_REGS_H_
#define _ECC_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_ECC_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup ecc * @ingroup ecc
* @defgroup ecc_registers ECC_Registers * @defgroup ecc_registers ECC_Registers
* @brief Registers, Bit Masks and Bit Positions for the ECC Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the ECC Peripheral Module.
* @details Error Correction Code * @details Trim System Initilazation Registers. ECC Registers for MAX32670.
*/ */
/** /**
@ -94,23 +94,23 @@ typedef struct {
* @brief ECC Peripheral Register Offsets from the ECC Base Peripheral Address. * @brief ECC Peripheral Register Offsets from the ECC Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_ECC_EN ((uint32_t)0x00000008UL) /**< Offset from ECC Base Address: <tt> 0x0008</tt> */ #define MXC_R_ECC_EN ((uint32_t)0x00000008UL) /**< Offset from ECC Base Address: <tt> 0x0008</tt> */
/**@} end of group ecc_registers */ /**@} end of group ecc_registers */
/** /**
* @ingroup ecc_registers * @ingroup ecc_registers
* @defgroup ECC_EN ECC_EN * @defgroup ECC_EN ECC_EN
* @brief ECC Enable Register * @brief ECC Enable Register.
* @{ * @{
*/ */
#define MXC_F_ECC_EN_RAM_POS 8 /**< EN_RAM Position */ #define MXC_F_ECC_EN_SRAM_POS 8 /**< EN_SRAM Position */
#define MXC_F_ECC_EN_RAM ((uint32_t)(0x1UL << MXC_F_ECC_EN_RAM_POS)) /**< EN_RAM Mask */ #define MXC_F_ECC_EN_SRAM ((uint32_t)(0x1UL << MXC_F_ECC_EN_SRAM_POS)) /**< EN_SRAM Mask */
#define MXC_F_ECC_EN_ICC0_POS 9 /**< EN_ICC0 Position */ #define MXC_F_ECC_EN_ICC_POS 9 /**< EN_ICC Position */
#define MXC_F_ECC_EN_ICC0 ((uint32_t)(0x1UL << MXC_F_ECC_EN_ICC0_POS)) /**< EN_ICC0 Mask */ #define MXC_F_ECC_EN_ICC ((uint32_t)(0x1UL << MXC_F_ECC_EN_ICC_POS)) /**< EN_ICC Mask */
#define MXC_F_ECC_EN_FLASH_POS 10 /**< EN_FLASH Position */ #define MXC_F_ECC_EN_FLASH_POS 10 /**< EN_FLASH Position */
#define MXC_F_ECC_EN_FLASH ((uint32_t)(0x1UL << MXC_F_ECC_EN_FLASH_POS)) /**< EN_FLASH Mask */ #define MXC_F_ECC_EN_FLASH ((uint32_t)(0x1UL << MXC_F_ECC_EN_FLASH_POS)) /**< EN_FLASH Mask */
/**@} end of group ECC_EN_Register */ /**@} end of group ECC_EN_Register */
@ -118,4 +118,4 @@ typedef struct {
} }
#endif #endif
#endif /* _ECC_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_ECC_REGS_H_

180
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/emcc_regs.h
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@ -1,180 +0,0 @@
/**
* @file emcc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the EMCC Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _EMCC_REGS_H_
#define _EMCC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup emcc
* @defgroup emcc_registers EMCC_Registers
* @brief Registers, Bit Masks and Bit Positions for the EMCC Peripheral Module.
* @details External Memory Cache Controller Registers.
*/
/**
* @ingroup emcc_registers
* Structure type to access the EMCC Registers.
*/
typedef struct {
__I uint32_t cache_id; /**< <tt>\b 0x0000:</tt> EMCC CACHE_ID Register */
__I uint32_t memcfg; /**< <tt>\b 0x0004:</tt> EMCC MEMCFG Register */
__I uint32_t rsv_0x8_0xff[62];
__IO uint32_t cache_ctrl; /**< <tt>\b 0x0100:</tt> EMCC CACHE_CTRL Register */
__I uint32_t rsv_0x104_0x6ff[383];
__IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> EMCC INVALIDATE Register */
} mxc_emcc_regs_t;
/* Register offsets for module EMCC */
/**
* @ingroup emcc_registers
* @defgroup EMCC_Register_Offsets Register Offsets
* @brief EMCC Peripheral Register Offsets from the EMCC Base Peripheral Address.
* @{
*/
#define MXC_R_EMCC_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from EMCC Base Address: <tt> 0x0000</tt> */
#define MXC_R_EMCC_MEMCFG ((uint32_t)0x00000004UL) /**< Offset from EMCC Base Address: <tt> 0x0004</tt> */
#define MXC_R_EMCC_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from EMCC Base Address: <tt> 0x0100</tt> */
#define MXC_R_EMCC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from EMCC Base Address: <tt> 0x0700</tt> */
/**@} end of group emcc_registers */
/**
* @ingroup emcc_registers
* @defgroup EMCC_CACHE_ID EMCC_CACHE_ID
* @brief Cache ID Register.
* @{
*/
#define MXC_F_EMCC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */
#define MXC_F_EMCC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_EMCC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */
#define MXC_F_EMCC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */
#define MXC_F_EMCC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_EMCC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */
#define MXC_F_EMCC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */
#define MXC_F_EMCC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_EMCC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */
/**@} end of group EMCC_CACHE_ID_Register */
/**
* @ingroup emcc_registers
* @defgroup EMCC_MEMCFG EMCC_MEMCFG
* @brief Memory Configuration Register.
* @{
*/
#define MXC_F_EMCC_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */
#define MXC_F_EMCC_MEMCFG_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_EMCC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */
#define MXC_F_EMCC_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */
#define MXC_F_EMCC_MEMCFG_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_EMCC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */
/**@} end of group EMCC_MEMCFG_Register */
/**
* @ingroup emcc_registers
* @defgroup EMCC_CACHE_CTRL EMCC_CACHE_CTRL
* @brief Cache Control and Status Register.
* @{
*/
#define MXC_F_EMCC_CACHE_CTRL_CACHE_EN_POS 0 /**< CACHE_CTRL_CACHE_EN Position */
#define MXC_F_EMCC_CACHE_CTRL_CACHE_EN ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CACHE_EN_POS)) /**< CACHE_CTRL_CACHE_EN Mask */
#define MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_EN_POS 1 /**< CACHE_CTRL_WRITE_ALLOC_EN Position */
#define MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_EN ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_EN_POS)) /**< CACHE_CTRL_WRITE_ALLOC_EN Mask */
#define MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS 2 /**< CACHE_CTRL_CWFST_DIS Position */
#define MXC_F_EMCC_CACHE_CTRL_CWFST_DIS ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS)) /**< CACHE_CTRL_CWFST_DIS Mask */
#define MXC_F_EMCC_CACHE_CTRL_CACHE_RDY_POS 16 /**< CACHE_CTRL_CACHE_RDY Position */
#define MXC_F_EMCC_CACHE_CTRL_CACHE_RDY ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CACHE_RDY_POS)) /**< CACHE_CTRL_CACHE_RDY Mask */
/**@} end of group EMCC_CACHE_CTRL_Register */
/**
* @ingroup emcc_registers
* @defgroup EMCC_INVALIDATE EMCC_INVALIDATE
* @brief Invalidate All Cache Contents. Any time this register location is written
* (regardless of the data value), the cache controller immediately begins
* invalidating the entire contents of the cache memory. The cache will be in
* bypass mode until the invalidate operation is complete. System software can
* examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the
* invalidate operation is complete. Note that it is not necessary to disable the
* cache controller prior to beginning this operation. Reads from this register
* always return 0.
* @{
*/
#define MXC_F_EMCC_INVALIDATE_IA_POS 0 /**< INVALIDATE_IA Position */
#define MXC_F_EMCC_INVALIDATE_IA ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMCC_INVALIDATE_IA_POS)) /**< INVALIDATE_IA Mask */
/**@} end of group EMCC_INVALIDATE_Register */
#ifdef __cplusplus
}
#endif
#endif /* _EMCC_REGS_H_ */

92
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/fcr_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file fcr_regs.h * @file fcr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _FCR_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FCR_REGS_H_
#define _FCR_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FCR_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup fcr * @ingroup fcr
* @defgroup fcr_registers FCR_Registers * @defgroup fcr_registers FCR_Registers
* @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module.
* @details Function Control Register. * @details Function Control Register.
*/ */
/** /**
@ -96,10 +96,10 @@ typedef struct {
* @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address. * @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_FCR_FCTRL0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: <tt> 0x0000</tt> */ #define MXC_R_FCR_FCTRL0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: <tt> 0x0000</tt> */
#define MXC_R_FCR_AUTOCAL0 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: <tt> 0x0004</tt> */ #define MXC_R_FCR_AUTOCAL0 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: <tt> 0x0004</tt> */
#define MXC_R_FCR_AUTOCAL1 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: <tt> 0x0008</tt> */ #define MXC_R_FCR_AUTOCAL1 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: <tt> 0x0008</tt> */
#define MXC_R_FCR_AUTOCAL2 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: <tt> 0x000C</tt> */ #define MXC_R_FCR_AUTOCAL2 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: <tt> 0x000C</tt> */
/**@} end of group fcr_registers */ /**@} end of group fcr_registers */
/** /**
@ -108,26 +108,26 @@ typedef struct {
* @brief Register 0. * @brief Register 0.
* @{ * @{
*/ */
#define MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL_POS 0 /**< FCTRL0_ERFO_RANGE_SEL Position */ #define MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL_POS 0 /**< FCTRL0_ERFO_RANGE_SEL Position */
#define MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL ((uint32_t)(0x7UL << MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL_POS)) /**< FCTRL0_ERFO_RANGE_SEL Mask */ #define MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL ((uint32_t)(0x7UL << MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL_POS)) /**< FCTRL0_ERFO_RANGE_SEL Mask */
#define MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS 20 /**< FCTRL0_I2C0_SDA_FILTER_EN Position */ #define MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS 20 /**< FCTRL0_I2C0_SDA_FILTER_EN Position */
#define MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C0_SDA_FILTER_EN Mask */ #define MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C0_SDA_FILTER_EN Mask */
#define MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS 21 /**< FCTRL0_I2C0_SCL_FILTER_EN Position */ #define MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS 21 /**< FCTRL0_I2C0_SCL_FILTER_EN Position */
#define MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C0_SCL_FILTER_EN Mask */ #define MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C0_SCL_FILTER_EN Mask */
#define MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS 22 /**< FCTRL0_I2C1_SDA_FILTER_EN Position */ #define MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS 22 /**< FCTRL0_I2C1_SDA_FILTER_EN Position */
#define MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C1_SDA_FILTER_EN Mask */ #define MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C1_SDA_FILTER_EN Mask */
#define MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS 23 /**< FCTRL0_I2C1_SCL_FILTER_EN Position */ #define MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS 23 /**< FCTRL0_I2C1_SCL_FILTER_EN Position */
#define MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C1_SCL_FILTER_EN Mask */ #define MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C1_SCL_FILTER_EN Mask */
#define MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN_POS 24 /**< FCTRL0_I2C2_SDA_FILTER_EN Position */ #define MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN_POS 24 /**< FCTRL0_I2C2_SDA_FILTER_EN Position */
#define MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C2_SDA_FILTER_EN Mask */ #define MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C2_SDA_FILTER_EN Mask */
#define MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN_POS 25 /**< FCTRL0_I2C2_SCL_FILTER_EN Position */ #define MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN_POS 25 /**< FCTRL0_I2C2_SCL_FILTER_EN Position */
#define MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C2_SCL_FILTER_EN Mask */ #define MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C2_SCL_FILTER_EN Mask */
/**@} end of group FCR_FCTRL0_Register */ /**@} end of group FCR_FCTRL0_Register */
@ -137,26 +137,26 @@ typedef struct {
* @brief Register 1. * @brief Register 1.
* @{ * @{
*/ */
#define MXC_F_FCR_AUTOCAL0_SEL_POS 0 /**< AUTOCAL0_SEL Position */ #define MXC_F_FCR_AUTOCAL0_SEL_POS 0 /**< AUTOCAL0_SEL Position */
#define MXC_F_FCR_AUTOCAL0_SEL ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_SEL_POS)) /**< AUTOCAL0_SEL Mask */ #define MXC_F_FCR_AUTOCAL0_SEL ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_SEL_POS)) /**< AUTOCAL0_SEL Mask */
#define MXC_F_FCR_AUTOCAL0_EN_POS 1 /**< AUTOCAL0_EN Position */ #define MXC_F_FCR_AUTOCAL0_EN_POS 1 /**< AUTOCAL0_EN Position */
#define MXC_F_FCR_AUTOCAL0_EN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_EN_POS)) /**< AUTOCAL0_EN Mask */ #define MXC_F_FCR_AUTOCAL0_EN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_EN_POS)) /**< AUTOCAL0_EN Mask */
#define MXC_F_FCR_AUTOCAL0_LOAD_POS 2 /**< AUTOCAL0_LOAD Position */ #define MXC_F_FCR_AUTOCAL0_LOAD_POS 2 /**< AUTOCAL0_LOAD Position */
#define MXC_F_FCR_AUTOCAL0_LOAD ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LOAD_POS)) /**< AUTOCAL0_LOAD Mask */ #define MXC_F_FCR_AUTOCAL0_LOAD ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LOAD_POS)) /**< AUTOCAL0_LOAD Mask */
#define MXC_F_FCR_AUTOCAL0_INVERT_POS 3 /**< AUTOCAL0_INVERT Position */ #define MXC_F_FCR_AUTOCAL0_INVERT_POS 3 /**< AUTOCAL0_INVERT Position */
#define MXC_F_FCR_AUTOCAL0_INVERT ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_INVERT_POS)) /**< AUTOCAL0_INVERT Mask */ #define MXC_F_FCR_AUTOCAL0_INVERT ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_INVERT_POS)) /**< AUTOCAL0_INVERT Mask */
#define MXC_F_FCR_AUTOCAL0_ATOMIC_POS 4 /**< AUTOCAL0_ATOMIC Position */ #define MXC_F_FCR_AUTOCAL0_ATOMIC_POS 4 /**< AUTOCAL0_ATOMIC Position */
#define MXC_F_FCR_AUTOCAL0_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) /**< AUTOCAL0_ATOMIC Mask */ #define MXC_F_FCR_AUTOCAL0_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) /**< AUTOCAL0_ATOMIC Mask */
#define MXC_F_FCR_AUTOCAL0_GAIN_POS 8 /**< AUTOCAL0_GAIN Position */ #define MXC_F_FCR_AUTOCAL0_GAIN_POS 8 /**< AUTOCAL0_GAIN Position */
#define MXC_F_FCR_AUTOCAL0_GAIN ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_GAIN_POS)) /**< AUTOCAL0_GAIN Mask */ #define MXC_F_FCR_AUTOCAL0_GAIN ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_GAIN_POS)) /**< AUTOCAL0_GAIN Mask */
#define MXC_F_FCR_AUTOCAL0_TRIM_POS 23 /**< AUTOCAL0_TRIM Position */ #define MXC_F_FCR_AUTOCAL0_TRIM_POS 23 /**< AUTOCAL0_TRIM Position */
#define MXC_F_FCR_AUTOCAL0_TRIM ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_TRIM_POS)) /**< AUTOCAL0_TRIM Mask */ #define MXC_F_FCR_AUTOCAL0_TRIM ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_TRIM_POS)) /**< AUTOCAL0_TRIM Mask */
/**@} end of group FCR_AUTOCAL0_Register */ /**@} end of group FCR_AUTOCAL0_Register */
@ -166,8 +166,8 @@ typedef struct {
* @brief Register 2. * @brief Register 2.
* @{ * @{
*/ */
#define MXC_F_FCR_AUTOCAL1_INITIAL_POS 0 /**< AUTOCAL1_INITIAL Position */ #define MXC_F_FCR_AUTOCAL1_INITIAL_POS 0 /**< AUTOCAL1_INITIAL Position */
#define MXC_F_FCR_AUTOCAL1_INITIAL ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL1_INITIAL_POS)) /**< AUTOCAL1_INITIAL Mask */ #define MXC_F_FCR_AUTOCAL1_INITIAL ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL1_INITIAL_POS)) /**< AUTOCAL1_INITIAL Mask */
/**@} end of group FCR_AUTOCAL1_Register */ /**@} end of group FCR_AUTOCAL1_Register */
@ -177,11 +177,11 @@ typedef struct {
* @brief Register 3. * @brief Register 3.
* @{ * @{
*/ */
#define MXC_F_FCR_AUTOCAL2_RUNTIME_POS 0 /**< AUTOCAL2_RUNTIME Position */ #define MXC_F_FCR_AUTOCAL2_RUNTIME_POS 0 /**< AUTOCAL2_RUNTIME Position */
#define MXC_F_FCR_AUTOCAL2_RUNTIME ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_RUNTIME_POS)) /**< AUTOCAL2_RUNTIME Mask */ #define MXC_F_FCR_AUTOCAL2_RUNTIME ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_RUNTIME_POS)) /**< AUTOCAL2_RUNTIME Mask */
#define MXC_F_FCR_AUTOCAL2_DIV_POS 8 /**< AUTOCAL2_DIV Position */ #define MXC_F_FCR_AUTOCAL2_DIV_POS 8 /**< AUTOCAL2_DIV Position */
#define MXC_F_FCR_AUTOCAL2_DIV ((uint32_t)(0x1FFFUL << MXC_F_FCR_AUTOCAL2_DIV_POS)) /**< AUTOCAL2_DIV Mask */ #define MXC_F_FCR_AUTOCAL2_DIV ((uint32_t)(0x1FFFUL << MXC_F_FCR_AUTOCAL2_DIV_POS)) /**< AUTOCAL2_DIV Mask */
/**@} end of group FCR_AUTOCAL2_Register */ /**@} end of group FCR_AUTOCAL2_Register */
@ -189,4 +189,4 @@ typedef struct {
} }
#endif #endif
#endif /* _FCR_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FCR_REGS_H_

142
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/flc_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file flc_regs.h * @file flc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _FLC_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FLC_REGS_H_
#define _FLC_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FLC_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup flc * @ingroup flc
* @defgroup flc_registers FLC_Registers * @defgroup flc_registers FLC_Registers
* @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
* @details Flash Memory Control. * @details Flash Memory Control.
*/ */
/** /**
@ -109,17 +109,17 @@ typedef struct {
* @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0000</tt> */ #define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0000</tt> */
#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */ #define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */
#define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */ #define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */
#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */ #define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */
#define MXC_R_FLC_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC Base Address: <tt> 0x0028</tt> */ #define MXC_R_FLC_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC Base Address: <tt> 0x0028</tt> */
#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */ #define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */
#define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0040</tt> */ #define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0040</tt> */
#define MXC_R_FLC_WELR0 ((uint32_t)0x00000080UL) /**< Offset from FLC Base Address: <tt> 0x0080</tt> */ #define MXC_R_FLC_WELR0 ((uint32_t)0x00000080UL) /**< Offset from FLC Base Address: <tt> 0x0080</tt> */
#define MXC_R_FLC_WELR1 ((uint32_t)0x00000088UL) /**< Offset from FLC Base Address: <tt> 0x0088</tt> */ #define MXC_R_FLC_WELR1 ((uint32_t)0x00000088UL) /**< Offset from FLC Base Address: <tt> 0x0088</tt> */
#define MXC_R_FLC_RLR0 ((uint32_t)0x00000090UL) /**< Offset from FLC Base Address: <tt> 0x0090</tt> */ #define MXC_R_FLC_RLR0 ((uint32_t)0x00000090UL) /**< Offset from FLC Base Address: <tt> 0x0090</tt> */
#define MXC_R_FLC_RLR1 ((uint32_t)0x00000098UL) /**< Offset from FLC Base Address: <tt> 0x0098</tt> */ #define MXC_R_FLC_RLR1 ((uint32_t)0x00000098UL) /**< Offset from FLC Base Address: <tt> 0x0098</tt> */
/**@} end of group flc_registers */ /**@} end of group flc_registers */
/** /**
@ -128,8 +128,8 @@ typedef struct {
* @brief Flash Write Address. * @brief Flash Write Address.
* @{ * @{
*/ */
#define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ #define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
#define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ #define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
/**@} end of group FLC_ADDR_Register */ /**@} end of group FLC_ADDR_Register */
@ -140,8 +140,8 @@ typedef struct {
* MHz clock for Flash controller. * MHz clock for Flash controller.
* @{ * @{
*/ */
#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ #define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ #define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
/**@} end of group FLC_CLKDIV_Register */ /**@} end of group FLC_CLKDIV_Register */
@ -151,36 +151,36 @@ typedef struct {
* @brief Flash Control Register. * @brief Flash Control Register.
* @{ * @{
*/ */
#define MXC_F_FLC_CTRL_WR_POS 0 /**< CTRL_WR Position */ #define MXC_F_FLC_CTRL_WR_POS 0 /**< CTRL_WR Position */
#define MXC_F_FLC_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WR_POS)) /**< CTRL_WR Mask */ #define MXC_F_FLC_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WR_POS)) /**< CTRL_WR Mask */
#define MXC_F_FLC_CTRL_ME_POS 1 /**< CTRL_ME Position */ #define MXC_F_FLC_CTRL_ME_POS 1 /**< CTRL_ME Position */
#define MXC_F_FLC_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_ME_POS)) /**< CTRL_ME Mask */ #define MXC_F_FLC_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_ME_POS)) /**< CTRL_ME Mask */
#define MXC_F_FLC_CTRL_PGE_POS 2 /**< CTRL_PGE Position */ #define MXC_F_FLC_CTRL_PGE_POS 2 /**< CTRL_PGE Position */
#define MXC_F_FLC_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PGE_POS)) /**< CTRL_PGE Mask */ #define MXC_F_FLC_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PGE_POS)) /**< CTRL_PGE Mask */
#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ #define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */
#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ #define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */
#define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ #define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */
#define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ #define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */
#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ #define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */
#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ #define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */
#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ #define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */
#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ #define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */
#define MXC_F_FLC_CTRL_PEND_POS 24 /**< CTRL_PEND Position */ #define MXC_F_FLC_CTRL_PEND_POS 24 /**< CTRL_PEND Position */
#define MXC_F_FLC_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PEND_POS)) /**< CTRL_PEND Mask */ #define MXC_F_FLC_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PEND_POS)) /**< CTRL_PEND Mask */
#define MXC_F_FLC_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ #define MXC_F_FLC_CTRL_LVE_POS 25 /**< CTRL_LVE Position */
#define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ #define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */
#define MXC_F_FLC_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */ #define MXC_F_FLC_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */
#define MXC_F_FLC_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */ #define MXC_F_FLC_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */
#define MXC_V_FLC_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */ #define MXC_V_FLC_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */
#define MXC_S_FLC_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */ #define MXC_S_FLC_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */
#define MXC_V_FLC_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */ #define MXC_V_FLC_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */
#define MXC_S_FLC_CTRL_UNLOCK_LOCKED (MXC_V_FLC_CTRL_UNLOCK_LOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */ #define MXC_S_FLC_CTRL_UNLOCK_LOCKED (MXC_V_FLC_CTRL_UNLOCK_LOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */
/**@} end of group FLC_CTRL_Register */ /**@} end of group FLC_CTRL_Register */
@ -190,17 +190,17 @@ typedef struct {
* @brief Flash Interrupt Register. * @brief Flash Interrupt Register.
* @{ * @{
*/ */
#define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */ #define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */
#define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */ #define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */
#define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */ #define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */
#define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */ #define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */
#define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ #define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */
#define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ #define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
#define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ #define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */
#define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ #define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
/**@} end of group FLC_INTR_Register */ /**@} end of group FLC_INTR_Register */
@ -210,11 +210,11 @@ typedef struct {
* @brief ECC Data Register. * @brief ECC Data Register.
* @{ * @{
*/ */
#define MXC_F_FLC_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */ #define MXC_F_FLC_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */
#define MXC_F_FLC_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */ #define MXC_F_FLC_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */
#define MXC_F_FLC_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */ #define MXC_F_FLC_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */
#define MXC_F_FLC_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */ #define MXC_F_FLC_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */
/**@} end of group FLC_ECCDATA_Register */ /**@} end of group FLC_ECCDATA_Register */
@ -224,8 +224,8 @@ typedef struct {
* @brief Flash Write Data. * @brief Flash Write Data.
* @{ * @{
*/ */
#define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ #define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */
#define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ #define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */
/**@} end of group FLC_DATA_Register */ /**@} end of group FLC_DATA_Register */
@ -239,8 +239,8 @@ typedef struct {
* and user information block. Readback of this register is always zero. * and user information block. Readback of this register is always zero.
* @{ * @{
*/ */
#define MXC_F_FLC_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ #define MXC_F_FLC_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */
#define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ #define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */
/**@} end of group FLC_ACTRL_Register */ /**@} end of group FLC_ACTRL_Register */
@ -250,8 +250,8 @@ typedef struct {
* @brief WELR0 * @brief WELR0
* @{ * @{
*/ */
#define MXC_F_FLC_WELR0_WELR0_POS 0 /**< WELR0_WELR0 Position */ #define MXC_F_FLC_WELR0_WELR0_POS 0 /**< WELR0_WELR0 Position */
#define MXC_F_FLC_WELR0_WELR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR0_WELR0_POS)) /**< WELR0_WELR0 Mask */ #define MXC_F_FLC_WELR0_WELR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR0_WELR0_POS)) /**< WELR0_WELR0 Mask */
/**@} end of group FLC_WELR0_Register */ /**@} end of group FLC_WELR0_Register */
@ -261,8 +261,8 @@ typedef struct {
* @brief WELR1 * @brief WELR1
* @{ * @{
*/ */
#define MXC_F_FLC_WELR1_WELR1_POS 0 /**< WELR1_WELR1 Position */ #define MXC_F_FLC_WELR1_WELR1_POS 0 /**< WELR1_WELR1 Position */
#define MXC_F_FLC_WELR1_WELR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR1_WELR1_POS)) /**< WELR1_WELR1 Mask */ #define MXC_F_FLC_WELR1_WELR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR1_WELR1_POS)) /**< WELR1_WELR1 Mask */
/**@} end of group FLC_WELR1_Register */ /**@} end of group FLC_WELR1_Register */
@ -272,8 +272,8 @@ typedef struct {
* @brief RLR0 * @brief RLR0
* @{ * @{
*/ */
#define MXC_F_FLC_RLR0_RLR0_POS 0 /**< RLR0_RLR0 Position */ #define MXC_F_FLC_RLR0_RLR0_POS 0 /**< RLR0_RLR0 Position */
#define MXC_F_FLC_RLR0_RLR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR0_RLR0_POS)) /**< RLR0_RLR0 Mask */ #define MXC_F_FLC_RLR0_RLR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR0_RLR0_POS)) /**< RLR0_RLR0 Mask */
/**@} end of group FLC_RLR0_Register */ /**@} end of group FLC_RLR0_Register */
@ -283,8 +283,8 @@ typedef struct {
* @brief RLR1 * @brief RLR1
* @{ * @{
*/ */
#define MXC_F_FLC_RLR1_RLR1_POS 0 /**< RLR1_RLR1 Position */ #define MXC_F_FLC_RLR1_RLR1_POS 0 /**< RLR1_RLR1 Position */
#define MXC_F_FLC_RLR1_RLR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR1_RLR1_POS)) /**< RLR1_RLR1 Mask */ #define MXC_F_FLC_RLR1_RLR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR1_RLR1_POS)) /**< RLR1_RLR1 Mask */
/**@} end of group FLC_RLR1_Register */ /**@} end of group FLC_RLR1_Register */
@ -292,4 +292,4 @@ typedef struct {
} }
#endif #endif
#endif /* _FLC_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FLC_REGS_H_

189
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcfr_regs.h
View File

@ -1,189 +0,0 @@
/**
* @file gcfr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the GCFR Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _GCFR_REGS_H_
#define _GCFR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup gcfr
* @defgroup gcfr_registers GCFR_Registers
* @brief Registers, Bit Masks and Bit Positions for the GCFR Peripheral Module.
* @details Global Control Function Register.
*/
/**
* @ingroup gcfr_registers
* Structure type to access the GCFR Registers.
*/
typedef struct {
__IO uint32_t reg0; /**< <tt>\b 0x00:</tt> GCFR REG0 Register */
__IO uint32_t reg1; /**< <tt>\b 0x04:</tt> GCFR REG1 Register */
__IO uint32_t reg2; /**< <tt>\b 0x08:</tt> GCFR REG2 Register */
__IO uint32_t reg3; /**< <tt>\b 0x0C:</tt> GCFR REG3 Register */
} mxc_gcfr_regs_t;
/* Register offsets for module GCFR */
/**
* @ingroup gcfr_registers
* @defgroup GCFR_Register_Offsets Register Offsets
* @brief GCFR Peripheral Register Offsets from the GCFR Base Peripheral Address.
* @{
*/
#define MXC_R_GCFR_REG0 ((uint32_t)0x00000000UL) /**< Offset from GCFR Base Address: <tt> 0x0000</tt> */
#define MXC_R_GCFR_REG1 ((uint32_t)0x00000004UL) /**< Offset from GCFR Base Address: <tt> 0x0004</tt> */
#define MXC_R_GCFR_REG2 ((uint32_t)0x00000008UL) /**< Offset from GCFR Base Address: <tt> 0x0008</tt> */
#define MXC_R_GCFR_REG3 ((uint32_t)0x0000000CUL) /**< Offset from GCFR Base Address: <tt> 0x000C</tt> */
/**@} end of group gcfr_registers */
/**
* @ingroup gcfr_registers
* @defgroup GCFR_REG0 GCFR_REG0
* @brief Register 0.
* @{
*/
#define MXC_F_GCFR_REG0_CNNX16_0_PWR_EN_POS 0 /**< REG0_CNNX16_0_PWR_EN Position */
#define MXC_F_GCFR_REG0_CNNX16_0_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_0_PWR_EN_POS)) /**< REG0_CNNX16_0_PWR_EN Mask */
#define MXC_F_GCFR_REG0_CNNX16_1_PWR_EN_POS 1 /**< REG0_CNNX16_1_PWR_EN Position */
#define MXC_F_GCFR_REG0_CNNX16_1_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_1_PWR_EN_POS)) /**< REG0_CNNX16_1_PWR_EN Mask */
#define MXC_F_GCFR_REG0_CNNX16_2_PWR_EN_POS 2 /**< REG0_CNNX16_2_PWR_EN Position */
#define MXC_F_GCFR_REG0_CNNX16_2_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_2_PWR_EN_POS)) /**< REG0_CNNX16_2_PWR_EN Mask */
#define MXC_F_GCFR_REG0_CNNX16_3_PWR_EN_POS 3 /**< REG0_CNNX16_3_PWR_EN Position */
#define MXC_F_GCFR_REG0_CNNX16_3_PWR_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_3_PWR_EN_POS)) /**< REG0_CNNX16_3_PWR_EN Mask */
/**@} end of group GCFR_REG0_Register */
/**
* @ingroup gcfr_registers
* @defgroup GCFR_REG1 GCFR_REG1
* @brief Register 1.
* @{
*/
#define MXC_F_GCFR_REG1_CNNX16_0_RAM_EN_POS 0 /**< REG1_CNNX16_0_RAM_EN Position */
#define MXC_F_GCFR_REG1_CNNX16_0_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_0_RAM_EN_POS)) /**< REG1_CNNX16_0_RAM_EN Mask */
#define MXC_F_GCFR_REG1_CNNX16_1_RAM_EN_POS 1 /**< REG1_CNNX16_1_RAM_EN Position */
#define MXC_F_GCFR_REG1_CNNX16_1_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_1_RAM_EN_POS)) /**< REG1_CNNX16_1_RAM_EN Mask */
#define MXC_F_GCFR_REG1_CNNX16_2_RAM_EN_POS 2 /**< REG1_CNNX16_2_RAM_EN Position */
#define MXC_F_GCFR_REG1_CNNX16_2_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_2_RAM_EN_POS)) /**< REG1_CNNX16_2_RAM_EN Mask */
#define MXC_F_GCFR_REG1_CNNX16_3_RAM_EN_POS 3 /**< REG1_CNNX16_3_RAM_EN Position */
#define MXC_F_GCFR_REG1_CNNX16_3_RAM_EN ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_3_RAM_EN_POS)) /**< REG1_CNNX16_3_RAM_EN Mask */
/**@} end of group GCFR_REG1_Register */
/**
* @ingroup gcfr_registers
* @defgroup GCFR_REG2 GCFR_REG2
* @brief Register 2.
* @{
*/
#define MXC_F_GCFR_REG2_CNNX16_0_ISO_POS 0 /**< REG2_CNNX16_0_ISO Position */
#define MXC_F_GCFR_REG2_CNNX16_0_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_0_ISO_POS)) /**< REG2_CNNX16_0_ISO Mask */
#define MXC_F_GCFR_REG2_CNNX16_1_ISO_POS 1 /**< REG2_CNNX16_1_ISO Position */
#define MXC_F_GCFR_REG2_CNNX16_1_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_1_ISO_POS)) /**< REG2_CNNX16_1_ISO Mask */
#define MXC_F_GCFR_REG2_CNNX16_2_ISO_POS 2 /**< REG2_CNNX16_2_ISO Position */
#define MXC_F_GCFR_REG2_CNNX16_2_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_2_ISO_POS)) /**< REG2_CNNX16_2_ISO Mask */
#define MXC_F_GCFR_REG2_CNNX16_3_ISO_POS 3 /**< REG2_CNNX16_3_ISO Position */
#define MXC_F_GCFR_REG2_CNNX16_3_ISO ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_3_ISO_POS)) /**< REG2_CNNX16_3_ISO Mask */
/**@} end of group GCFR_REG2_Register */
/**
* @ingroup gcfr_registers
* @defgroup GCFR_REG3 GCFR_REG3
* @brief Register 3.
* @{
*/
#define MXC_F_GCFR_REG3_CNNX16_0_RST_POS 0 /**< REG3_CNNX16_0_RST Position */
#define MXC_F_GCFR_REG3_CNNX16_0_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_0_RST_POS)) /**< REG3_CNNX16_0_RST Mask */
#define MXC_F_GCFR_REG3_CNNX16_1_RST_POS 1 /**< REG3_CNNX16_1_RST Position */
#define MXC_F_GCFR_REG3_CNNX16_1_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_1_RST_POS)) /**< REG3_CNNX16_1_RST Mask */
#define MXC_F_GCFR_REG3_CNNX16_2_RST_POS 2 /**< REG3_CNNX16_2_RST Position */
#define MXC_F_GCFR_REG3_CNNX16_2_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_2_RST_POS)) /**< REG3_CNNX16_2_RST Mask */
#define MXC_F_GCFR_REG3_CNNX16_3_RST_POS 3 /**< REG3_CNNX16_3_RST Position */
#define MXC_F_GCFR_REG3_CNNX16_3_RST ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_3_RST_POS)) /**< REG3_CNNX16_3_RST Mask */
/**@} end of group GCFR_REG3_Register */
#ifdef __cplusplus
}
#endif
#endif /* _GCFR_REGS_H_ */

628
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcr_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file gcr_regs.h * @file gcr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _GCR_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GCR_REGS_H_
#define _GCR_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GCR_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup gcr * @ingroup gcr
* @defgroup gcr_registers GCR_Registers * @defgroup gcr_registers GCR_Registers
* @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
* @details Global Control Registers. * @details Global Control Registers.
*/ */
/** /**
@ -114,24 +114,24 @@ typedef struct {
* @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_GCR_SYSCTRL ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */ #define MXC_R_GCR_SYSCTRL ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */
#define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */ #define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */
#define MXC_R_GCR_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */ #define MXC_R_GCR_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */
#define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */ #define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */
#define MXC_R_GCR_PCLKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> 0x0018</tt> */ #define MXC_R_GCR_PCLKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> 0x0018</tt> */
#define MXC_R_GCR_PCLKDIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */ #define MXC_R_GCR_PCLKDIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */
#define MXC_R_GCR_MEMCTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */ #define MXC_R_GCR_MEMCTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */
#define MXC_R_GCR_MEMZ ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */ #define MXC_R_GCR_MEMZ ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */
#define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */ #define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */
#define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */ #define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */
#define MXC_R_GCR_PCLKDIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */ #define MXC_R_GCR_PCLKDIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */
#define MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */ #define MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */
#define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */ #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */
#define MXC_R_GCR_SYSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */ #define MXC_R_GCR_SYSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */
#define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: <tt> 0x0064</tt> */ #define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: <tt> 0x0064</tt> */
#define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: <tt> 0x0068</tt> */ #define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: <tt> 0x0068</tt> */
#define MXC_R_GCR_ECCIE ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: <tt> 0x006C</tt> */ #define MXC_R_GCR_ECCIE ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: <tt> 0x006C</tt> */
#define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: <tt> 0x0070</tt> */ #define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: <tt> 0x0070</tt> */
/**@} end of group gcr_registers */ /**@} end of group gcr_registers */
/** /**
@ -140,30 +140,30 @@ typedef struct {
* @brief System Control. * @brief System Control.
* @{ * @{
*/ */
#define MXC_F_GCR_SYSCTRL_SBUSARB_POS 1 /**< SYSCTRL_SBUSARB Position */ #define MXC_F_GCR_SYSCTRL_SBUSARB_POS 1 /**< SYSCTRL_SBUSARB Position */
#define MXC_F_GCR_SYSCTRL_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_SBUSARB_POS)) /**< SYSCTRL_SBUSARB Mask */ #define MXC_F_GCR_SYSCTRL_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_SBUSARB_POS)) /**< SYSCTRL_SBUSARB Mask */
#define MXC_V_GCR_SYSCTRL_SBUSARB_FIX ((uint32_t)0x0UL) /**< SYSCTRL_SBUSARB_FIX Value */ #define MXC_V_GCR_SYSCTRL_SBUSARB_FIX ((uint32_t)0x0UL) /**< SYSCTRL_SBUSARB_FIX Value */
#define MXC_S_GCR_SYSCTRL_SBUSARB_FIX (MXC_V_GCR_SYSCTRL_SBUSARB_FIX << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_FIX Setting */ #define MXC_S_GCR_SYSCTRL_SBUSARB_FIX (MXC_V_GCR_SYSCTRL_SBUSARB_FIX << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_FIX Setting */
#define MXC_V_GCR_SYSCTRL_SBUSARB_ROUND ((uint32_t)0x1UL) /**< SYSCTRL_SBUSARB_ROUND Value */ #define MXC_V_GCR_SYSCTRL_SBUSARB_ROUND ((uint32_t)0x1UL) /**< SYSCTRL_SBUSARB_ROUND Value */
#define MXC_S_GCR_SYSCTRL_SBUSARB_ROUND (MXC_V_GCR_SYSCTRL_SBUSARB_ROUND << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_ROUND Setting */ #define MXC_S_GCR_SYSCTRL_SBUSARB_ROUND (MXC_V_GCR_SYSCTRL_SBUSARB_ROUND << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_ROUND Setting */
#define MXC_F_GCR_SYSCTRL_FPU_DIS_POS 5 /**< SYSCTRL_FPU_DIS Position */ #define MXC_F_GCR_SYSCTRL_FPU_DIS_POS 5 /**< SYSCTRL_FPU_DIS Position */
#define MXC_F_GCR_SYSCTRL_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FPU_DIS_POS)) /**< SYSCTRL_FPU_DIS Mask */ #define MXC_F_GCR_SYSCTRL_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FPU_DIS_POS)) /**< SYSCTRL_FPU_DIS Mask */
#define MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS 6 /**< SYSCTRL_ICC0_FLUSH Position */ #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS 6 /**< SYSCTRL_ICC0_FLUSH Position */
#define MXC_F_GCR_SYSCTRL_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS)) /**< SYSCTRL_ICC0_FLUSH Mask */ #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS)) /**< SYSCTRL_ICC0_FLUSH Mask */
#define MXC_F_GCR_SYSCTRL_ROMDONE_POS 12 /**< SYSCTRL_ROMDONE Position */ #define MXC_F_GCR_SYSCTRL_ROMDONE_POS 12 /**< SYSCTRL_ROMDONE Position */
#define MXC_F_GCR_SYSCTRL_ROMDONE ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ROMDONE_POS)) /**< SYSCTRL_ROMDONE Mask */ #define MXC_F_GCR_SYSCTRL_ROMDONE ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ROMDONE_POS)) /**< SYSCTRL_ROMDONE Mask */
#define MXC_F_GCR_SYSCTRL_CCHK_POS 13 /**< SYSCTRL_CCHK Position */ #define MXC_F_GCR_SYSCTRL_CCHK_POS 13 /**< SYSCTRL_CCHK Position */
#define MXC_F_GCR_SYSCTRL_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK_POS)) /**< SYSCTRL_CCHK Mask */ #define MXC_F_GCR_SYSCTRL_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK_POS)) /**< SYSCTRL_CCHK Mask */
#define MXC_F_GCR_SYSCTRL_SWD_DIS_POS 14 /**< SYSCTRL_SWD_DIS Position */ #define MXC_F_GCR_SYSCTRL_SWD_DIS_POS 14 /**< SYSCTRL_SWD_DIS Position */
#define MXC_F_GCR_SYSCTRL_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SWD_DIS_POS)) /**< SYSCTRL_SWD_DIS Mask */ #define MXC_F_GCR_SYSCTRL_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SWD_DIS_POS)) /**< SYSCTRL_SWD_DIS Mask */
#define MXC_F_GCR_SYSCTRL_CHKRES_POS 15 /**< SYSCTRL_CHKRES Position */ #define MXC_F_GCR_SYSCTRL_CHKRES_POS 15 /**< SYSCTRL_CHKRES Position */
#define MXC_F_GCR_SYSCTRL_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES_POS)) /**< SYSCTRL_CHKRES Mask */ #define MXC_F_GCR_SYSCTRL_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES_POS)) /**< SYSCTRL_CHKRES Mask */
/**@} end of group GCR_SYSCTRL_Register */ /**@} end of group GCR_SYSCTRL_Register */
@ -173,65 +173,65 @@ typedef struct {
* @brief Reset. * @brief Reset.
* @{ * @{
*/ */
#define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */ #define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */
#define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */ #define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */
#define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */ #define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */
#define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */ #define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */
#define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */ #define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */
#define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */ #define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */
#define MXC_F_GCR_RST0_GPIO1_POS 3 /**< RST0_GPIO1 Position */ #define MXC_F_GCR_RST0_GPIO1_POS 3 /**< RST0_GPIO1 Position */
#define MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS)) /**< RST0_GPIO1 Mask */ #define MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS)) /**< RST0_GPIO1 Mask */
#define MXC_F_GCR_RST0_TMR0_POS 5 /**< RST0_TMR0 Position */ #define MXC_F_GCR_RST0_TMR0_POS 5 /**< RST0_TMR0 Position */
#define MXC_F_GCR_RST0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR0_POS)) /**< RST0_TMR0 Mask */ #define MXC_F_GCR_RST0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR0_POS)) /**< RST0_TMR0 Mask */
#define MXC_F_GCR_RST0_TMR1_POS 6 /**< RST0_TMR1 Position */ #define MXC_F_GCR_RST0_TMR1_POS 6 /**< RST0_TMR1 Position */
#define MXC_F_GCR_RST0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR1_POS)) /**< RST0_TMR1 Mask */ #define MXC_F_GCR_RST0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR1_POS)) /**< RST0_TMR1 Mask */
#define MXC_F_GCR_RST0_TMR2_POS 7 /**< RST0_TMR2 Position */ #define MXC_F_GCR_RST0_TMR2_POS 7 /**< RST0_TMR2 Position */
#define MXC_F_GCR_RST0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR2_POS)) /**< RST0_TMR2 Mask */ #define MXC_F_GCR_RST0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR2_POS)) /**< RST0_TMR2 Mask */
#define MXC_F_GCR_RST0_TMR3_POS 8 /**< RST0_TMR3 Position */ #define MXC_F_GCR_RST0_TMR3_POS 8 /**< RST0_TMR3 Position */
#define MXC_F_GCR_RST0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR3_POS)) /**< RST0_TMR3 Mask */ #define MXC_F_GCR_RST0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR3_POS)) /**< RST0_TMR3 Mask */
#define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */ #define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */
#define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */ #define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */
#define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */ #define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */
#define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */ #define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */
#define MXC_F_GCR_RST0_SPI0_POS 13 /**< RST0_SPI0 Position */ #define MXC_F_GCR_RST0_SPI0_POS 13 /**< RST0_SPI0 Position */
#define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */ #define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */
#define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */ #define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */
#define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */ #define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */
#define MXC_F_GCR_RST0_SPI2_POS 15 /**< RST0_SPI2 Position */ #define MXC_F_GCR_RST0_SPI2_POS 15 /**< RST0_SPI2 Position */
#define MXC_F_GCR_RST0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI2_POS)) /**< RST0_SPI2 Mask */ #define MXC_F_GCR_RST0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI2_POS)) /**< RST0_SPI2 Mask */
#define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */ #define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */
#define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */ #define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */
#define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */ #define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */
#define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */ #define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */
#define MXC_F_GCR_RST0_TRNG_POS 24 /**< RST0_TRNG Position */ #define MXC_F_GCR_RST0_TRNG_POS 24 /**< RST0_TRNG Position */
#define MXC_F_GCR_RST0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS)) /**< RST0_TRNG Mask */ #define MXC_F_GCR_RST0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS)) /**< RST0_TRNG Mask */
#define MXC_F_GCR_RST0_UART2_POS 28 /**< RST0_UART2 Position */ #define MXC_F_GCR_RST0_UART2_POS 28 /**< RST0_UART2 Position */
#define MXC_F_GCR_RST0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS)) /**< RST0_UART2 Mask */ #define MXC_F_GCR_RST0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS)) /**< RST0_UART2 Mask */
#define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */ #define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */
#define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */ #define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */
#define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */ #define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */
#define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */ #define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */
#define MXC_F_GCR_RST0_SYS_POS 31 /**< RST0_SYS Position */ #define MXC_F_GCR_RST0_SYS_POS 31 /**< RST0_SYS Position */
#define MXC_F_GCR_RST0_SYS ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS)) /**< RST0_SYS Mask */ #define MXC_F_GCR_RST0_SYS ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS)) /**< RST0_SYS Mask */
/**@} end of group GCR_RST0_Register */ /**@} end of group GCR_RST0_Register */
@ -241,86 +241,86 @@ typedef struct {
* @brief Clock Control. * @brief Clock Control.
* @{ * @{
*/ */
#define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS 6 /**< CLKCTRL_SYSCLK_DIV Position */ #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS 6 /**< CLKCTRL_SYSCLK_DIV Position */
#define MXC_F_GCR_CLKCTRL_SYSCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)) /**< CLKCTRL_SYSCLK_DIV Mask */ #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)) /**< CLKCTRL_SYSCLK_DIV Mask */
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_DIV_DIV1 Value */ #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_DIV_DIV1 Value */
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV1 Setting */ #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV1 Setting */
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_SYSCLK_DIV_DIV2 Value */ #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_SYSCLK_DIV_DIV2 Value */
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV2 Setting */ #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV2 Setting */
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_DIV_DIV4 Value */ #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_DIV_DIV4 Value */
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV4 Setting */ #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV4 Setting */
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_DIV_DIV8 Value */ #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_DIV_DIV8 Value */
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV8 Setting */ #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV8 Setting */
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_DIV_DIV16 Value */ #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_DIV_DIV16 Value */
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV16 Setting */ #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV16 Setting */
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_DIV_DIV32 Value */ #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_DIV_DIV32 Value */
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV32 Setting */ #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV32 Setting */
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_DIV_DIV64 Value */ #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_DIV_DIV64 Value */
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV64 Setting */ #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV64 Setting */
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_DIV_DIV128 Value */ #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_DIV_DIV128 Value */
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV128 Setting */ #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV128 Setting */
#define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS 9 /**< CLKCTRL_SYSCLK_SEL Position */ #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS 9 /**< CLKCTRL_SYSCLK_SEL Position */
#define MXC_F_GCR_CLKCTRL_SYSCLK_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)) /**< CLKCTRL_SYSCLK_SEL Mask */ #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)) /**< CLKCTRL_SYSCLK_SEL Mask */
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_SEL_ERFO Value */ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_SEL_ERFO Value */
#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERFO Setting */ #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERFO Setting */
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_SEL_INRO Value */ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_SEL_INRO Value */
#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_INRO Setting */ #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_INRO Setting */
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_SEL_IPO Value */ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_SEL_IPO Value */
#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IPO Setting */ #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IPO Setting */
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_SEL_IBRO Value */ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_SEL_IBRO Value */
#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IBRO Setting */ #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IBRO Setting */
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_SEL_ERTCO Value */ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_SEL_ERTCO Value */
#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERTCO Setting */ #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERTCO Setting */
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Value */ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Value */
#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Setting */ #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Setting */
#define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13 /**< CLKCTRL_SYSCLK_RDY Position */ #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13 /**< CLKCTRL_SYSCLK_RDY Position */
#define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) /**< CLKCTRL_SYSCLK_RDY Mask */ #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) /**< CLKCTRL_SYSCLK_RDY Mask */
#define MXC_F_GCR_CLKCTRL_IPO_DIV_POS 14 /**< CLKCTRL_IPO_DIV Position */ #define MXC_F_GCR_CLKCTRL_IPO_DIV_POS 14 /**< CLKCTRL_IPO_DIV Position */
#define MXC_F_GCR_CLKCTRL_IPO_DIV ((uint32_t)(0x3UL << MXC_F_GCR_CLKCTRL_IPO_DIV_POS)) /**< CLKCTRL_IPO_DIV Mask */ #define MXC_F_GCR_CLKCTRL_IPO_DIV ((uint32_t)(0x3UL << MXC_F_GCR_CLKCTRL_IPO_DIV_POS)) /**< CLKCTRL_IPO_DIV Mask */
#define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_IPO_DIV_DIV1 Value */ #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_IPO_DIV_DIV1 Value */
#define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV1 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV1 Setting */ #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV1 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV1 Setting */
#define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_IPO_DIV_DIV2 Value */ #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_IPO_DIV_DIV2 Value */
#define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV2 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV2 Setting */ #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV2 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV2 Setting */
#define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_IPO_DIV_DIV4 Value */ #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_IPO_DIV_DIV4 Value */
#define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV4 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV4 Setting */ #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV4 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV4 Setting */
#define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_IPO_DIV_DIV8 Value */ #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_IPO_DIV_DIV8 Value */
#define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV8 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV8 Setting */ #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV8 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV8 Setting */
#define MXC_F_GCR_CLKCTRL_ERFO_EN_POS 16 /**< CLKCTRL_ERFO_EN Position */ #define MXC_F_GCR_CLKCTRL_ERFO_EN_POS 16 /**< CLKCTRL_ERFO_EN Position */
#define MXC_F_GCR_CLKCTRL_ERFO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_EN_POS)) /**< CLKCTRL_ERFO_EN Mask */ #define MXC_F_GCR_CLKCTRL_ERFO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_EN_POS)) /**< CLKCTRL_ERFO_EN Mask */
#define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */ #define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */
#define MXC_F_GCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */ #define MXC_F_GCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */
#define MXC_F_GCR_CLKCTRL_IPO_EN_POS 19 /**< CLKCTRL_IPO_EN Position */ #define MXC_F_GCR_CLKCTRL_IPO_EN_POS 19 /**< CLKCTRL_IPO_EN Position */
#define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) /**< CLKCTRL_IPO_EN Mask */ #define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) /**< CLKCTRL_IPO_EN Mask */
#define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20 /**< CLKCTRL_IBRO_EN Position */ #define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20 /**< CLKCTRL_IBRO_EN Position */
#define MXC_F_GCR_CLKCTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_EN_POS)) /**< CLKCTRL_IBRO_EN Mask */ #define MXC_F_GCR_CLKCTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_EN_POS)) /**< CLKCTRL_IBRO_EN Mask */
#define MXC_F_GCR_CLKCTRL_IBRO_VS_POS 21 /**< CLKCTRL_IBRO_VS Position */ #define MXC_F_GCR_CLKCTRL_IBRO_VS_POS 21 /**< CLKCTRL_IBRO_VS Position */
#define MXC_F_GCR_CLKCTRL_IBRO_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_VS_POS)) /**< CLKCTRL_IBRO_VS Mask */ #define MXC_F_GCR_CLKCTRL_IBRO_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_VS_POS)) /**< CLKCTRL_IBRO_VS Mask */
#define MXC_F_GCR_CLKCTRL_ERFO_RDY_POS 24 /**< CLKCTRL_ERFO_RDY Position */ #define MXC_F_GCR_CLKCTRL_ERFO_RDY_POS 24 /**< CLKCTRL_ERFO_RDY Position */
#define MXC_F_GCR_CLKCTRL_ERFO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_RDY_POS)) /**< CLKCTRL_ERFO_RDY Mask */ #define MXC_F_GCR_CLKCTRL_ERFO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_RDY_POS)) /**< CLKCTRL_ERFO_RDY Mask */
#define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS 25 /**< CLKCTRL_ERTCO_RDY Position */ #define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS 25 /**< CLKCTRL_ERTCO_RDY Position */
#define MXC_F_GCR_CLKCTRL_ERTCO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS)) /**< CLKCTRL_ERTCO_RDY Mask */ #define MXC_F_GCR_CLKCTRL_ERTCO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS)) /**< CLKCTRL_ERTCO_RDY Mask */
#define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 27 /**< CLKCTRL_IPO_RDY Position */ #define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 27 /**< CLKCTRL_IPO_RDY Position */
#define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) /**< CLKCTRL_IPO_RDY Mask */ #define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) /**< CLKCTRL_IPO_RDY Mask */
#define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS 28 /**< CLKCTRL_IBRO_RDY Position */ #define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS 28 /**< CLKCTRL_IBRO_RDY Position */
#define MXC_F_GCR_CLKCTRL_IBRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_RDY_POS)) /**< CLKCTRL_IBRO_RDY Mask */ #define MXC_F_GCR_CLKCTRL_IBRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_RDY_POS)) /**< CLKCTRL_IBRO_RDY Mask */
#define MXC_F_GCR_CLKCTRL_INRO_RDY_POS 29 /**< CLKCTRL_INRO_RDY Position */ #define MXC_F_GCR_CLKCTRL_INRO_RDY_POS 29 /**< CLKCTRL_INRO_RDY Position */
#define MXC_F_GCR_CLKCTRL_INRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS)) /**< CLKCTRL_INRO_RDY Mask */ #define MXC_F_GCR_CLKCTRL_INRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS)) /**< CLKCTRL_INRO_RDY Mask */
#define MXC_F_GCR_CLKCTRL_EXTCLK_RDY_POS 31 /**< CLKCTRL_EXTCLK_RDY Position */ #define MXC_F_GCR_CLKCTRL_EXTCLK_RDY_POS 31 /**< CLKCTRL_EXTCLK_RDY Position */
#define MXC_F_GCR_CLKCTRL_EXTCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_EXTCLK_RDY_POS)) /**< CLKCTRL_EXTCLK_RDY Mask */ #define MXC_F_GCR_CLKCTRL_EXTCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_EXTCLK_RDY_POS)) /**< CLKCTRL_EXTCLK_RDY Mask */
/**@} end of group GCR_CLKCTRL_Register */ /**@} end of group GCR_CLKCTRL_Register */
@ -330,41 +330,41 @@ typedef struct {
* @brief Power Management. * @brief Power Management.
* @{ * @{
*/ */
#define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */
#define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ #define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */
#define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */
#define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */
#define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ #define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */
#define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ #define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */
#define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ #define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */
#define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */
#define MXC_F_GCR_PM_GPIO_WE_POS 4 /**< PM_GPIO_WE Position */ #define MXC_F_GCR_PM_GPIO_WE_POS 4 /**< PM_GPIO_WE Position */
#define MXC_F_GCR_PM_GPIO_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIO_WE_POS)) /**< PM_GPIO_WE Mask */ #define MXC_F_GCR_PM_GPIO_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIO_WE_POS)) /**< PM_GPIO_WE Mask */
#define MXC_F_GCR_PM_RTC_WE_POS 5 /**< PM_RTC_WE Position */ #define MXC_F_GCR_PM_RTC_WE_POS 5 /**< PM_RTC_WE Position */
#define MXC_F_GCR_PM_RTC_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTC_WE_POS)) /**< PM_RTC_WE Mask */ #define MXC_F_GCR_PM_RTC_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTC_WE_POS)) /**< PM_RTC_WE Mask */
#define MXC_F_GCR_PM_LPTMR0_WE_POS 6 /**< PM_LPTMR0_WE Position */ #define MXC_F_GCR_PM_LPTMR0_WE_POS 6 /**< PM_LPTMR0_WE Position */
#define MXC_F_GCR_PM_LPTMR0_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPTMR0_WE_POS)) /**< PM_LPTMR0_WE Mask */ #define MXC_F_GCR_PM_LPTMR0_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPTMR0_WE_POS)) /**< PM_LPTMR0_WE Mask */
#define MXC_F_GCR_PM_LPTMR1_WE_POS 7 /**< PM_LPTMR1_WE Position */ #define MXC_F_GCR_PM_LPTMR1_WE_POS 7 /**< PM_LPTMR1_WE Position */
#define MXC_F_GCR_PM_LPTMR1_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPTMR1_WE_POS)) /**< PM_LPTMR1_WE Mask */ #define MXC_F_GCR_PM_LPTMR1_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPTMR1_WE_POS)) /**< PM_LPTMR1_WE Mask */
#define MXC_F_GCR_PM_LPUART0_WE_POS 8 /**< PM_LPUART0_WE Position */ #define MXC_F_GCR_PM_LPUART0_WE_POS 8 /**< PM_LPUART0_WE Position */
#define MXC_F_GCR_PM_LPUART0_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPUART0_WE_POS)) /**< PM_LPUART0_WE Mask */ #define MXC_F_GCR_PM_LPUART0_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPUART0_WE_POS)) /**< PM_LPUART0_WE Mask */
#define MXC_F_GCR_PM_ERFO_PD_POS 14 /**< PM_ERFO_PD Position */ #define MXC_F_GCR_PM_ERFO_PD_POS 12 /**< PM_ERFO_PD Position */
#define MXC_F_GCR_PM_ERFO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_PD_POS)) /**< PM_ERFO_PD Mask */ #define MXC_F_GCR_PM_ERFO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_PD_POS)) /**< PM_ERFO_PD Mask */
#define MXC_F_GCR_PM_IPO_PD_POS 16 /**< PM_IPO_PD Position */ #define MXC_F_GCR_PM_IPO_PD_POS 16 /**< PM_IPO_PD Position */
#define MXC_F_GCR_PM_IPO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IPO_PD_POS)) /**< PM_IPO_PD Mask */ #define MXC_F_GCR_PM_IPO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IPO_PD_POS)) /**< PM_IPO_PD Mask */
#define MXC_F_GCR_PM_IBRO_PD_POS 17 /**< PM_IBRO_PD Position */ #define MXC_F_GCR_PM_IBRO_PD_POS 17 /**< PM_IBRO_PD Position */
#define MXC_F_GCR_PM_IBRO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IBRO_PD_POS)) /**< PM_IBRO_PD Mask */ #define MXC_F_GCR_PM_IBRO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IBRO_PD_POS)) /**< PM_IBRO_PD Mask */
#define MXC_F_GCR_PM_ERFO_BP_POS 20 /**< PM_ERFO_BP Position */ #define MXC_F_GCR_PM_ERFO_BP_POS 20 /**< PM_ERFO_BP Position */
#define MXC_F_GCR_PM_ERFO_BP ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_BP_POS)) /**< PM_ERFO_BP Mask */ #define MXC_F_GCR_PM_ERFO_BP ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_BP_POS)) /**< PM_ERFO_BP Mask */
/**@} end of group GCR_PM_Register */ /**@} end of group GCR_PM_Register */
@ -374,22 +374,22 @@ typedef struct {
* @brief Peripheral Clock Divider. * @brief Peripheral Clock Divider.
* @{ * @{
*/ */
#define MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS 0 /**< PCLKDIV_AON_CLKDIV Position */ #define MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS 0 /**< PCLKDIV_AON_CLKDIV Position */
#define MXC_F_GCR_PCLKDIV_AON_CLKDIV ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS)) /**< PCLKDIV_AON_CLKDIV Mask */ #define MXC_F_GCR_PCLKDIV_AON_CLKDIV ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS)) /**< PCLKDIV_AON_CLKDIV Mask */
#define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV4 ((uint32_t)0x0UL) /**< PCLKDIV_AON_CLKDIV_DIV4 Value */ #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV4 ((uint32_t)0x0UL) /**< PCLKDIV_AON_CLKDIV_DIV4 Value */
#define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV4 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV4 Setting */ #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV4 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV4 Setting */
#define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV8 ((uint32_t)0x1UL) /**< PCLKDIV_AON_CLKDIV_DIV8 Value */ #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV8 ((uint32_t)0x1UL) /**< PCLKDIV_AON_CLKDIV_DIV8 Value */
#define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV8 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV8 Setting */ #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV8 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV8 Setting */
#define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV16 ((uint32_t)0x2UL) /**< PCLKDIV_AON_CLKDIV_DIV16 Value */ #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV16 ((uint32_t)0x2UL) /**< PCLKDIV_AON_CLKDIV_DIV16 Value */
#define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV16 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV16 Setting */ #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV16 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV16 Setting */
#define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV32 ((uint32_t)0x3UL) /**< PCLKDIV_AON_CLKDIV_DIV32 Value */ #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV32 ((uint32_t)0x3UL) /**< PCLKDIV_AON_CLKDIV_DIV32 Value */
#define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV32 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV32 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV32 Setting */ #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV32 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV32 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV32 Setting */
#define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS 14 /**< PCLKDIV_DIV_CLK_OUT_CTRL Position */ #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS 14 /**< PCLKDIV_DIV_CLK_OUT_CTRL Position */
#define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS)) /**< PCLKDIV_DIV_CLK_OUT_CTRL Mask */ #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS)) /**< PCLKDIV_DIV_CLK_OUT_CTRL Mask */
#define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN_POS 16 /**< PCLKDIV_DIV_CLK_OUT_EN Position */ #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN_POS 16 /**< PCLKDIV_DIV_CLK_OUT_EN Position */
#define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN_POS)) /**< PCLKDIV_DIV_CLK_OUT_EN Mask */ #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN_POS)) /**< PCLKDIV_DIV_CLK_OUT_EN Mask */
/**@} end of group GCR_PCLKDIV_Register */ /**@} end of group GCR_PCLKDIV_Register */
@ -399,47 +399,47 @@ typedef struct {
* @brief Peripheral Clock Disable. * @brief Peripheral Clock Disable.
* @{ * @{
*/ */
#define MXC_F_GCR_PCLKDIS0_GPIO0_POS 0 /**< PCLKDIS0_GPIO0 Position */ #define MXC_F_GCR_PCLKDIS0_GPIO0_POS 0 /**< PCLKDIS0_GPIO0 Position */
#define MXC_F_GCR_PCLKDIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO0_POS)) /**< PCLKDIS0_GPIO0 Mask */ #define MXC_F_GCR_PCLKDIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO0_POS)) /**< PCLKDIS0_GPIO0 Mask */
#define MXC_F_GCR_PCLKDIS0_GPIO1_POS 1 /**< PCLKDIS0_GPIO1 Position */ #define MXC_F_GCR_PCLKDIS0_GPIO1_POS 1 /**< PCLKDIS0_GPIO1 Position */
#define MXC_F_GCR_PCLKDIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO1_POS)) /**< PCLKDIS0_GPIO1 Mask */ #define MXC_F_GCR_PCLKDIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO1_POS)) /**< PCLKDIS0_GPIO1 Mask */
#define MXC_F_GCR_PCLKDIS0_DMA_POS 5 /**< PCLKDIS0_DMA Position */ #define MXC_F_GCR_PCLKDIS0_DMA_POS 5 /**< PCLKDIS0_DMA Position */
#define MXC_F_GCR_PCLKDIS0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA_POS)) /**< PCLKDIS0_DMA Mask */ #define MXC_F_GCR_PCLKDIS0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA_POS)) /**< PCLKDIS0_DMA Mask */
#define MXC_F_GCR_PCLKDIS0_SPI0_POS 6 /**< PCLKDIS0_SPI0 Position */ #define MXC_F_GCR_PCLKDIS0_SPI0_POS 6 /**< PCLKDIS0_SPI0 Position */
#define MXC_F_GCR_PCLKDIS0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI0_POS)) /**< PCLKDIS0_SPI0 Mask */ #define MXC_F_GCR_PCLKDIS0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI0_POS)) /**< PCLKDIS0_SPI0 Mask */
#define MXC_F_GCR_PCLKDIS0_SPI1_POS 7 /**< PCLKDIS0_SPI1 Position */ #define MXC_F_GCR_PCLKDIS0_SPI1_POS 7 /**< PCLKDIS0_SPI1 Position */
#define MXC_F_GCR_PCLKDIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI1_POS)) /**< PCLKDIS0_SPI1 Mask */ #define MXC_F_GCR_PCLKDIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI1_POS)) /**< PCLKDIS0_SPI1 Mask */
#define MXC_F_GCR_PCLKDIS0_SPI2_POS 8 /**< PCLKDIS0_SPI2 Position */ #define MXC_F_GCR_PCLKDIS0_SPI2_POS 8 /**< PCLKDIS0_SPI2 Position */
#define MXC_F_GCR_PCLKDIS0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI2_POS)) /**< PCLKDIS0_SPI2 Mask */ #define MXC_F_GCR_PCLKDIS0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI2_POS)) /**< PCLKDIS0_SPI2 Mask */
#define MXC_F_GCR_PCLKDIS0_UART0_POS 9 /**< PCLKDIS0_UART0 Position */ #define MXC_F_GCR_PCLKDIS0_UART0_POS 9 /**< PCLKDIS0_UART0 Position */
#define MXC_F_GCR_PCLKDIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART0_POS)) /**< PCLKDIS0_UART0 Mask */ #define MXC_F_GCR_PCLKDIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART0_POS)) /**< PCLKDIS0_UART0 Mask */
#define MXC_F_GCR_PCLKDIS0_UART1_POS 10 /**< PCLKDIS0_UART1 Position */ #define MXC_F_GCR_PCLKDIS0_UART1_POS 10 /**< PCLKDIS0_UART1 Position */
#define MXC_F_GCR_PCLKDIS0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART1_POS)) /**< PCLKDIS0_UART1 Mask */ #define MXC_F_GCR_PCLKDIS0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART1_POS)) /**< PCLKDIS0_UART1 Mask */
#define MXC_F_GCR_PCLKDIS0_I2C0_POS 13 /**< PCLKDIS0_I2C0 Position */ #define MXC_F_GCR_PCLKDIS0_I2C0_POS 13 /**< PCLKDIS0_I2C0 Position */
#define MXC_F_GCR_PCLKDIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C0_POS)) /**< PCLKDIS0_I2C0 Mask */ #define MXC_F_GCR_PCLKDIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C0_POS)) /**< PCLKDIS0_I2C0 Mask */
#define MXC_F_GCR_PCLKDIS0_TMR0_POS 15 /**< PCLKDIS0_TMR0 Position */ #define MXC_F_GCR_PCLKDIS0_TMR0_POS 15 /**< PCLKDIS0_TMR0 Position */
#define MXC_F_GCR_PCLKDIS0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS)) /**< PCLKDIS0_TMR0 Mask */ #define MXC_F_GCR_PCLKDIS0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS)) /**< PCLKDIS0_TMR0 Mask */
#define MXC_F_GCR_PCLKDIS0_TMR1_POS 16 /**< PCLKDIS0_TMR1 Position */ #define MXC_F_GCR_PCLKDIS0_TMR1_POS 16 /**< PCLKDIS0_TMR1 Position */
#define MXC_F_GCR_PCLKDIS0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR1_POS)) /**< PCLKDIS0_TMR1 Mask */ #define MXC_F_GCR_PCLKDIS0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR1_POS)) /**< PCLKDIS0_TMR1 Mask */
#define MXC_F_GCR_PCLKDIS0_TMR2_POS 17 /**< PCLKDIS0_TMR2 Position */ #define MXC_F_GCR_PCLKDIS0_TMR2_POS 17 /**< PCLKDIS0_TMR2 Position */
#define MXC_F_GCR_PCLKDIS0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR2_POS)) /**< PCLKDIS0_TMR2 Mask */ #define MXC_F_GCR_PCLKDIS0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR2_POS)) /**< PCLKDIS0_TMR2 Mask */
#define MXC_F_GCR_PCLKDIS0_TMR3_POS 18 /**< PCLKDIS0_TMR3 Position */ #define MXC_F_GCR_PCLKDIS0_TMR3_POS 18 /**< PCLKDIS0_TMR3 Position */
#define MXC_F_GCR_PCLKDIS0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR3_POS)) /**< PCLKDIS0_TMR3 Mask */ #define MXC_F_GCR_PCLKDIS0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR3_POS)) /**< PCLKDIS0_TMR3 Mask */
#define MXC_F_GCR_PCLKDIS0_I2C1_POS 28 /**< PCLKDIS0_I2C1 Position */ #define MXC_F_GCR_PCLKDIS0_I2C1_POS 28 /**< PCLKDIS0_I2C1 Position */
#define MXC_F_GCR_PCLKDIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C1_POS)) /**< PCLKDIS0_I2C1 Mask */ #define MXC_F_GCR_PCLKDIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C1_POS)) /**< PCLKDIS0_I2C1 Mask */
/**@} end of group GCR_PCLKDIS0_Register */ /**@} end of group GCR_PCLKDIS0_Register */
@ -449,29 +449,29 @@ typedef struct {
* @brief Memory Clock Control Register. * @brief Memory Clock Control Register.
* @{ * @{
*/ */
#define MXC_F_GCR_MEMCTRL_FWS_POS 0 /**< MEMCTRL_FWS Position */ #define MXC_F_GCR_MEMCTRL_FWS_POS 0 /**< MEMCTRL_FWS Position */
#define MXC_F_GCR_MEMCTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS)) /**< MEMCTRL_FWS Mask */ #define MXC_F_GCR_MEMCTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS)) /**< MEMCTRL_FWS Mask */
#define MXC_F_GCR_MEMCTRL_RAMWS_EN_POS 4 /**< MEMCTRL_RAMWS_EN Position */ #define MXC_F_GCR_MEMCTRL_RAMWS_EN_POS 4 /**< MEMCTRL_RAMWS_EN Position */
#define MXC_F_GCR_MEMCTRL_RAMWS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAMWS_EN_POS)) /**< MEMCTRL_RAMWS_EN Mask */ #define MXC_F_GCR_MEMCTRL_RAMWS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAMWS_EN_POS)) /**< MEMCTRL_RAMWS_EN Mask */
#define MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS 8 /**< MEMCTRL_RAM0LS_EN Position */ #define MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS 8 /**< MEMCTRL_RAM0LS_EN Position */
#define MXC_F_GCR_MEMCTRL_RAM0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS)) /**< MEMCTRL_RAM0LS_EN Mask */ #define MXC_F_GCR_MEMCTRL_RAM0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS)) /**< MEMCTRL_RAM0LS_EN Mask */
#define MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS 9 /**< MEMCTRL_RAM1LS_EN Position */ #define MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS 9 /**< MEMCTRL_RAM1LS_EN Position */
#define MXC_F_GCR_MEMCTRL_RAM1LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS)) /**< MEMCTRL_RAM1LS_EN Mask */ #define MXC_F_GCR_MEMCTRL_RAM1LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS)) /**< MEMCTRL_RAM1LS_EN Mask */
#define MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS 10 /**< MEMCTRL_RAM2LS_EN Position */ #define MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS 10 /**< MEMCTRL_RAM2LS_EN Position */
#define MXC_F_GCR_MEMCTRL_RAM2LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS)) /**< MEMCTRL_RAM2LS_EN Mask */ #define MXC_F_GCR_MEMCTRL_RAM2LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS)) /**< MEMCTRL_RAM2LS_EN Mask */
#define MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS 11 /**< MEMCTRL_RAM3LS_EN Position */ #define MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS 11 /**< MEMCTRL_RAM3LS_EN Position */
#define MXC_F_GCR_MEMCTRL_RAM3LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS)) /**< MEMCTRL_RAM3LS_EN Mask */ #define MXC_F_GCR_MEMCTRL_RAM3LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS)) /**< MEMCTRL_RAM3LS_EN Mask */
#define MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS 12 /**< MEMCTRL_ICC0LS_EN Position */ #define MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS 12 /**< MEMCTRL_ICC0LS_EN Position */
#define MXC_F_GCR_MEMCTRL_ICC0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS)) /**< MEMCTRL_ICC0LS_EN Mask */ #define MXC_F_GCR_MEMCTRL_ICC0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS)) /**< MEMCTRL_ICC0LS_EN Mask */
#define MXC_F_GCR_MEMCTRL_ROMLS_EN_POS 13 /**< MEMCTRL_ROMLS_EN Position */ #define MXC_F_GCR_MEMCTRL_ROMLS_EN_POS 13 /**< MEMCTRL_ROMLS_EN Position */
#define MXC_F_GCR_MEMCTRL_ROMLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROMLS_EN_POS)) /**< MEMCTRL_ROMLS_EN Mask */ #define MXC_F_GCR_MEMCTRL_ROMLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROMLS_EN_POS)) /**< MEMCTRL_ROMLS_EN Mask */
/**@} end of group GCR_MEMCTRL_Register */ /**@} end of group GCR_MEMCTRL_Register */
@ -481,14 +481,14 @@ typedef struct {
* @brief Memory Zeroize Control. * @brief Memory Zeroize Control.
* @{ * @{
*/ */
#define MXC_F_GCR_MEMZ_RAM_POS 0 /**< MEMZ_RAM Position */ #define MXC_F_GCR_MEMZ_RAM_POS 0 /**< MEMZ_RAM Position */
#define MXC_F_GCR_MEMZ_RAM ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM_POS)) /**< MEMZ_RAM Mask */ #define MXC_F_GCR_MEMZ_RAM ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM_POS)) /**< MEMZ_RAM Mask */
#define MXC_F_GCR_MEMZ_RAMCB_POS 1 /**< MEMZ_RAMCB Position */ #define MXC_F_GCR_MEMZ_RAMCB_POS 1 /**< MEMZ_RAMCB Position */
#define MXC_F_GCR_MEMZ_RAMCB ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAMCB_POS)) /**< MEMZ_RAMCB Mask */ #define MXC_F_GCR_MEMZ_RAMCB ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAMCB_POS)) /**< MEMZ_RAMCB Mask */
#define MXC_F_GCR_MEMZ_ICC0_POS 2 /**< MEMZ_ICC0 Position */ #define MXC_F_GCR_MEMZ_ICC0_POS 2 /**< MEMZ_ICC0 Position */
#define MXC_F_GCR_MEMZ_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC0_POS)) /**< MEMZ_ICC0 Mask */ #define MXC_F_GCR_MEMZ_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC0_POS)) /**< MEMZ_ICC0 Mask */
/**@} end of group GCR_MEMZ_Register */ /**@} end of group GCR_MEMZ_Register */
@ -498,8 +498,8 @@ typedef struct {
* @brief System Status Register. * @brief System Status Register.
* @{ * @{
*/ */
#define MXC_F_GCR_SYSST_ICELOCK_POS 0 /**< SYSST_ICELOCK Position */ #define MXC_F_GCR_SYSST_ICELOCK_POS 0 /**< SYSST_ICELOCK Position */
#define MXC_F_GCR_SYSST_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) /**< SYSST_ICELOCK Mask */ #define MXC_F_GCR_SYSST_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) /**< SYSST_ICELOCK Mask */
/**@} end of group GCR_SYSST_Register */ /**@} end of group GCR_SYSST_Register */
@ -509,26 +509,26 @@ typedef struct {
* @brief Reset 1. * @brief Reset 1.
* @{ * @{
*/ */
#define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */ #define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */
#define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */ #define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */
#define MXC_F_GCR_RST1_WDT1_POS 8 /**< RST1_WDT1 Position */ #define MXC_F_GCR_RST1_WDT1_POS 8 /**< RST1_WDT1 Position */
#define MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS)) /**< RST1_WDT1 Mask */ #define MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS)) /**< RST1_WDT1 Mask */
#define MXC_F_GCR_RST1_CRC_POS 9 /**< RST1_CRC Position */ #define MXC_F_GCR_RST1_CRC_POS 9 /**< RST1_CRC Position */
#define MXC_F_GCR_RST1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CRC_POS)) /**< RST1_CRC Mask */ #define MXC_F_GCR_RST1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CRC_POS)) /**< RST1_CRC Mask */
#define MXC_F_GCR_RST1_AES_POS 10 /**< RST1_AES Position */ #define MXC_F_GCR_RST1_AES_POS 10 /**< RST1_AES Position */
#define MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS)) /**< RST1_AES Mask */ #define MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS)) /**< RST1_AES Mask */
#define MXC_F_GCR_RST1_AC_POS 14 /**< RST1_AC Position */ #define MXC_F_GCR_RST1_AC_POS 14 /**< RST1_AC Position */
#define MXC_F_GCR_RST1_AC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AC_POS)) /**< RST1_AC Mask */ #define MXC_F_GCR_RST1_AC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AC_POS)) /**< RST1_AC Mask */
#define MXC_F_GCR_RST1_I2C2_POS 17 /**< RST1_I2C2 Position */ #define MXC_F_GCR_RST1_I2C2_POS 17 /**< RST1_I2C2 Position */
#define MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS)) /**< RST1_I2C2 Mask */ #define MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS)) /**< RST1_I2C2 Mask */
#define MXC_F_GCR_RST1_I2S_POS 23 /**< RST1_I2S Position */ #define MXC_F_GCR_RST1_I2S_POS 23 /**< RST1_I2S Position */
#define MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS)) /**< RST1_I2S Mask */ #define MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS)) /**< RST1_I2S Mask */
/**@} end of group GCR_RST1_Register */ /**@} end of group GCR_RST1_Register */
@ -538,32 +538,32 @@ typedef struct {
* @brief Peripheral Clock Disable. * @brief Peripheral Clock Disable.
* @{ * @{
*/ */
#define MXC_F_GCR_PCLKDIS1_UART2_POS 1 /**< PCLKDIS1_UART2 Position */ #define MXC_F_GCR_PCLKDIS1_UART2_POS 1 /**< PCLKDIS1_UART2 Position */
#define MXC_F_GCR_PCLKDIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS)) /**< PCLKDIS1_UART2 Mask */ #define MXC_F_GCR_PCLKDIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS)) /**< PCLKDIS1_UART2 Mask */
#define MXC_F_GCR_PCLKDIS1_TRNG_POS 2 /**< PCLKDIS1_TRNG Position */ #define MXC_F_GCR_PCLKDIS1_TRNG_POS 2 /**< PCLKDIS1_TRNG Position */
#define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) /**< PCLKDIS1_TRNG Mask */ #define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) /**< PCLKDIS1_TRNG Mask */
#define MXC_F_GCR_PCLKDIS1_WWDT0_POS 4 /**< PCLKDIS1_WWDT0 Position */ #define MXC_F_GCR_PCLKDIS1_WWDT0_POS 4 /**< PCLKDIS1_WWDT0 Position */
#define MXC_F_GCR_PCLKDIS1_WWDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WWDT0_POS)) /**< PCLKDIS1_WWDT0 Mask */ #define MXC_F_GCR_PCLKDIS1_WWDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WWDT0_POS)) /**< PCLKDIS1_WWDT0 Mask */
#define MXC_F_GCR_PCLKDIS1_WWDT1_POS 5 /**< PCLKDIS1_WWDT1 Position */ #define MXC_F_GCR_PCLKDIS1_WWDT1_POS 5 /**< PCLKDIS1_WWDT1 Position */
#define MXC_F_GCR_PCLKDIS1_WWDT1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WWDT1_POS)) /**< PCLKDIS1_WWDT1 Mask */ #define MXC_F_GCR_PCLKDIS1_WWDT1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WWDT1_POS)) /**< PCLKDIS1_WWDT1 Mask */
#define MXC_F_GCR_PCLKDIS1_ICC0_POS 11 /**< PCLKDIS1_ICC0 Position */ #define MXC_F_GCR_PCLKDIS1_ICC0_POS 11 /**< PCLKDIS1_ICC0 Position */
#define MXC_F_GCR_PCLKDIS1_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_ICC0_POS)) /**< PCLKDIS1_ICC0 Mask */ #define MXC_F_GCR_PCLKDIS1_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_ICC0_POS)) /**< PCLKDIS1_ICC0 Mask */
#define MXC_F_GCR_PCLKDIS1_CRC_POS 14 /**< PCLKDIS1_CRC Position */ #define MXC_F_GCR_PCLKDIS1_CRC_POS 14 /**< PCLKDIS1_CRC Position */
#define MXC_F_GCR_PCLKDIS1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CRC_POS)) /**< PCLKDIS1_CRC Mask */ #define MXC_F_GCR_PCLKDIS1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CRC_POS)) /**< PCLKDIS1_CRC Mask */
#define MXC_F_GCR_PCLKDIS1_AES_POS 15 /**< PCLKDIS1_AES Position */ #define MXC_F_GCR_PCLKDIS1_AES_POS 15 /**< PCLKDIS1_AES Position */
#define MXC_F_GCR_PCLKDIS1_AES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS)) /**< PCLKDIS1_AES Mask */ #define MXC_F_GCR_PCLKDIS1_AES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS)) /**< PCLKDIS1_AES Mask */
#define MXC_F_GCR_PCLKDIS1_I2C2_POS 21 /**< PCLKDIS1_I2C2 Position */ #define MXC_F_GCR_PCLKDIS1_I2C2_POS 21 /**< PCLKDIS1_I2C2 Position */
#define MXC_F_GCR_PCLKDIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS)) /**< PCLKDIS1_I2C2 Mask */ #define MXC_F_GCR_PCLKDIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS)) /**< PCLKDIS1_I2C2 Mask */
#define MXC_F_GCR_PCLKDIS1_I2S_POS 23 /**< PCLKDIS1_I2S Position */ #define MXC_F_GCR_PCLKDIS1_I2S_POS 23 /**< PCLKDIS1_I2S Position */
#define MXC_F_GCR_PCLKDIS1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2S_POS)) /**< PCLKDIS1_I2S Mask */ #define MXC_F_GCR_PCLKDIS1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2S_POS)) /**< PCLKDIS1_I2S Mask */
/**@} end of group GCR_PCLKDIS1_Register */ /**@} end of group GCR_PCLKDIS1_Register */
@ -573,14 +573,14 @@ typedef struct {
* @brief Event Enable Register. * @brief Event Enable Register.
* @{ * @{
*/ */
#define MXC_F_GCR_EVENTEN_DMA_POS 0 /**< EVENTEN_DMA Position */ #define MXC_F_GCR_EVENTEN_DMA_POS 0 /**< EVENTEN_DMA Position */
#define MXC_F_GCR_EVENTEN_DMA ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA_POS)) /**< EVENTEN_DMA Mask */ #define MXC_F_GCR_EVENTEN_DMA ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA_POS)) /**< EVENTEN_DMA Mask */
#define MXC_F_GCR_EVENTEN_RX_POS 1 /**< EVENTEN_RX Position */ #define MXC_F_GCR_EVENTEN_RX_POS 1 /**< EVENTEN_RX Position */
#define MXC_F_GCR_EVENTEN_RX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_RX_POS)) /**< EVENTEN_RX Mask */ #define MXC_F_GCR_EVENTEN_RX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_RX_POS)) /**< EVENTEN_RX Mask */
#define MXC_F_GCR_EVENTEN_TX_POS 2 /**< EVENTEN_TX Position */ #define MXC_F_GCR_EVENTEN_TX_POS 2 /**< EVENTEN_TX Position */
#define MXC_F_GCR_EVENTEN_TX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_TX_POS)) /**< EVENTEN_TX Mask */ #define MXC_F_GCR_EVENTEN_TX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_TX_POS)) /**< EVENTEN_TX Mask */
/**@} end of group GCR_EVENTEN_Register */ /**@} end of group GCR_EVENTEN_Register */
@ -590,8 +590,8 @@ typedef struct {
* @brief Revision Register. * @brief Revision Register.
* @{ * @{
*/ */
#define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */ #define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */
#define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */ #define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */
/**@} end of group GCR_REVISION_Register */ /**@} end of group GCR_REVISION_Register */
@ -601,8 +601,8 @@ typedef struct {
* @brief System Status Interrupt Enable Register. * @brief System Status Interrupt Enable Register.
* @{ * @{
*/ */
#define MXC_F_GCR_SYSIE_ICEUNLOCK_POS 0 /**< SYSIE_ICEUNLOCK Position */ #define MXC_F_GCR_SYSIE_ICEUNLOCK_POS 0 /**< SYSIE_ICEUNLOCK Position */
#define MXC_F_GCR_SYSIE_ICEUNLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_ICEUNLOCK_POS)) /**< SYSIE_ICEUNLOCK Mask */ #define MXC_F_GCR_SYSIE_ICEUNLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_ICEUNLOCK_POS)) /**< SYSIE_ICEUNLOCK Mask */
/**@} end of group GCR_SYSIE_Register */ /**@} end of group GCR_SYSIE_Register */
@ -612,14 +612,14 @@ typedef struct {
* @brief ECC Error Register * @brief ECC Error Register
* @{ * @{
*/ */
#define MXC_F_GCR_ECCERR_RAM_POS 0 /**< ECCERR_RAM Position */ #define MXC_F_GCR_ECCERR_RAM_POS 0 /**< ECCERR_RAM Position */
#define MXC_F_GCR_ECCERR_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM_POS)) /**< ECCERR_RAM Mask */ #define MXC_F_GCR_ECCERR_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM_POS)) /**< ECCERR_RAM Mask */
#define MXC_F_GCR_ECCERR_ICC0_POS 1 /**< ECCERR_ICC0 Position */ #define MXC_F_GCR_ECCERR_ICC0_POS 1 /**< ECCERR_ICC0 Position */
#define MXC_F_GCR_ECCERR_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_ICC0_POS)) /**< ECCERR_ICC0 Mask */ #define MXC_F_GCR_ECCERR_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_ICC0_POS)) /**< ECCERR_ICC0 Mask */
#define MXC_F_GCR_ECCERR_FLASH_POS 2 /**< ECCERR_FLASH Position */ #define MXC_F_GCR_ECCERR_FLASH_POS 2 /**< ECCERR_FLASH Position */
#define MXC_F_GCR_ECCERR_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_FLASH_POS)) /**< ECCERR_FLASH Mask */ #define MXC_F_GCR_ECCERR_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_FLASH_POS)) /**< ECCERR_FLASH Mask */
/**@} end of group GCR_ECCERR_Register */ /**@} end of group GCR_ECCERR_Register */
@ -629,14 +629,14 @@ typedef struct {
* @brief ECC Not Double Error Detect Register * @brief ECC Not Double Error Detect Register
* @{ * @{
*/ */
#define MXC_F_GCR_ECCCED_RAM_POS 0 /**< ECCCED_RAM Position */ #define MXC_F_GCR_ECCCED_RAM_POS 0 /**< ECCCED_RAM Position */
#define MXC_F_GCR_ECCCED_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM_POS)) /**< ECCCED_RAM Mask */ #define MXC_F_GCR_ECCCED_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM_POS)) /**< ECCCED_RAM Mask */
#define MXC_F_GCR_ECCCED_ICC0_POS 1 /**< ECCCED_ICC0 Position */ #define MXC_F_GCR_ECCCED_ICC0_POS 1 /**< ECCCED_ICC0 Position */
#define MXC_F_GCR_ECCCED_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_ICC0_POS)) /**< ECCCED_ICC0 Mask */ #define MXC_F_GCR_ECCCED_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_ICC0_POS)) /**< ECCCED_ICC0 Mask */
#define MXC_F_GCR_ECCCED_FLASH_POS 2 /**< ECCCED_FLASH Position */ #define MXC_F_GCR_ECCCED_FLASH_POS 2 /**< ECCCED_FLASH Position */
#define MXC_F_GCR_ECCCED_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_FLASH_POS)) /**< ECCCED_FLASH Mask */ #define MXC_F_GCR_ECCCED_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_FLASH_POS)) /**< ECCCED_FLASH Mask */
/**@} end of group GCR_ECCCED_Register */ /**@} end of group GCR_ECCCED_Register */
@ -646,14 +646,14 @@ typedef struct {
* @brief ECC IRQ Enable Register * @brief ECC IRQ Enable Register
* @{ * @{
*/ */
#define MXC_F_GCR_ECCIE_RAM_POS 0 /**< ECCIE_RAM Position */ #define MXC_F_GCR_ECCIE_RAM_POS 0 /**< ECCIE_RAM Position */
#define MXC_F_GCR_ECCIE_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM_POS)) /**< ECCIE_RAM Mask */ #define MXC_F_GCR_ECCIE_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM_POS)) /**< ECCIE_RAM Mask */
#define MXC_F_GCR_ECCIE_ICC0_POS 1 /**< ECCIE_ICC0 Position */ #define MXC_F_GCR_ECCIE_ICC0_POS 1 /**< ECCIE_ICC0 Position */
#define MXC_F_GCR_ECCIE_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_ICC0_POS)) /**< ECCIE_ICC0 Mask */ #define MXC_F_GCR_ECCIE_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_ICC0_POS)) /**< ECCIE_ICC0 Mask */
#define MXC_F_GCR_ECCIE_FLASH_POS 2 /**< ECCIE_FLASH Position */ #define MXC_F_GCR_ECCIE_FLASH_POS 2 /**< ECCIE_FLASH Position */
#define MXC_F_GCR_ECCIE_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_FLASH_POS)) /**< ECCIE_FLASH Mask */ #define MXC_F_GCR_ECCIE_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_FLASH_POS)) /**< ECCIE_FLASH Mask */
/**@} end of group GCR_ECCIE_Register */ /**@} end of group GCR_ECCIE_Register */
@ -663,23 +663,23 @@ typedef struct {
* @brief ECC Error Address Register * @brief ECC Error Address Register
* @{ * @{
*/ */
#define MXC_F_GCR_ECCADDR_DATARAMADDR_POS 0 /**< ECCADDR_DATARAMADDR Position */ #define MXC_F_GCR_ECCADDR_DATARAMADDR_POS 0 /**< ECCADDR_DATARAMADDR Position */
#define MXC_F_GCR_ECCADDR_DATARAMADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_DATARAMADDR_POS)) /**< ECCADDR_DATARAMADDR Mask */ #define MXC_F_GCR_ECCADDR_DATARAMADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_DATARAMADDR_POS)) /**< ECCADDR_DATARAMADDR Mask */
#define MXC_F_GCR_ECCADDR_DATARAMBANK_POS 14 /**< ECCADDR_DATARAMBANK Position */ #define MXC_F_GCR_ECCADDR_DATARAMBANK_POS 14 /**< ECCADDR_DATARAMBANK Position */
#define MXC_F_GCR_ECCADDR_DATARAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMBANK_POS)) /**< ECCADDR_DATARAMBANK Mask */ #define MXC_F_GCR_ECCADDR_DATARAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMBANK_POS)) /**< ECCADDR_DATARAMBANK Mask */
#define MXC_F_GCR_ECCADDR_DATARAMERR_POS 15 /**< ECCADDR_DATARAMERR Position */ #define MXC_F_GCR_ECCADDR_DATARAMERR_POS 15 /**< ECCADDR_DATARAMERR Position */
#define MXC_F_GCR_ECCADDR_DATARAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMERR_POS)) /**< ECCADDR_DATARAMERR Mask */ #define MXC_F_GCR_ECCADDR_DATARAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMERR_POS)) /**< ECCADDR_DATARAMERR Mask */
#define MXC_F_GCR_ECCADDR_TAGRAMADDR_POS 16 /**< ECCADDR_TAGRAMADDR Position */ #define MXC_F_GCR_ECCADDR_TAGRAMADDR_POS 16 /**< ECCADDR_TAGRAMADDR Position */
#define MXC_F_GCR_ECCADDR_TAGRAMADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_TAGRAMADDR_POS)) /**< ECCADDR_TAGRAMADDR Mask */ #define MXC_F_GCR_ECCADDR_TAGRAMADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_TAGRAMADDR_POS)) /**< ECCADDR_TAGRAMADDR Mask */
#define MXC_F_GCR_ECCADDR_TAGRAMBANK_POS 30 /**< ECCADDR_TAGRAMBANK Position */ #define MXC_F_GCR_ECCADDR_TAGRAMBANK_POS 30 /**< ECCADDR_TAGRAMBANK Position */
#define MXC_F_GCR_ECCADDR_TAGRAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMBANK_POS)) /**< ECCADDR_TAGRAMBANK Mask */ #define MXC_F_GCR_ECCADDR_TAGRAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMBANK_POS)) /**< ECCADDR_TAGRAMBANK Mask */
#define MXC_F_GCR_ECCADDR_TAGRAMERR_POS 31 /**< ECCADDR_TAGRAMERR Position */ #define MXC_F_GCR_ECCADDR_TAGRAMERR_POS 31 /**< ECCADDR_TAGRAMERR Position */
#define MXC_F_GCR_ECCADDR_TAGRAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMERR_POS)) /**< ECCADDR_TAGRAMERR Mask */ #define MXC_F_GCR_ECCADDR_TAGRAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMERR_POS)) /**< ECCADDR_TAGRAMERR Mask */
/**@} end of group GCR_ECCADDR_Register */ /**@} end of group GCR_ECCADDR_Register */
@ -687,4 +687,4 @@ typedef struct {
} }
#endif #endif
#endif /* _GCR_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GCR_REGS_H_

374
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gpio_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file gpio_regs.h * @file gpio_regs.h
* @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _GPIO_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GPIO_REGS_H_
#define _GPIO_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GPIO_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup gpio * @ingroup gpio
* @defgroup gpio_registers GPIO_Registers * @defgroup gpio_registers GPIO_Registers
* @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
* @details Individual I/O for each GPIO * @details Individual I/O for each GPIO
*/ */
/** /**
@ -130,41 +130,41 @@ typedef struct {
* @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> 0x0000</tt> */ #define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> 0x0000</tt> */
#define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> 0x0004</tt> */ #define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> 0x0004</tt> */
#define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> 0x0008</tt> */ #define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> 0x0008</tt> */
#define MXC_R_GPIO_OUTEN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> 0x000C</tt> */ #define MXC_R_GPIO_OUTEN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> 0x000C</tt> */
#define MXC_R_GPIO_OUTEN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> 0x0010</tt> */ #define MXC_R_GPIO_OUTEN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> 0x0010</tt> */
#define MXC_R_GPIO_OUTEN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> 0x0014</tt> */ #define MXC_R_GPIO_OUTEN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> 0x0014</tt> */
#define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> 0x0018</tt> */ #define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> 0x0018</tt> */
#define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> 0x001C</tt> */ #define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> 0x001C</tt> */
#define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> 0x0020</tt> */ #define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> 0x0020</tt> */
#define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */ #define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */
#define MXC_R_GPIO_INTMODE ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */ #define MXC_R_GPIO_INTMODE ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */
#define MXC_R_GPIO_INTPOL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */ #define MXC_R_GPIO_INTPOL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */
#define MXC_R_GPIO_INEN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt> 0x0030</tt> */ #define MXC_R_GPIO_INEN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt> 0x0030</tt> */
#define MXC_R_GPIO_INTEN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */ #define MXC_R_GPIO_INTEN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */
#define MXC_R_GPIO_INTEN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */ #define MXC_R_GPIO_INTEN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */
#define MXC_R_GPIO_INTEN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */ #define MXC_R_GPIO_INTEN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */
#define MXC_R_GPIO_INTFL ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> 0x0040</tt> */ #define MXC_R_GPIO_INTFL ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> 0x0040</tt> */
#define MXC_R_GPIO_INTFL_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> 0x0048</tt> */ #define MXC_R_GPIO_INTFL_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> 0x0048</tt> */
#define MXC_R_GPIO_WKEN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> 0x004C</tt> */ #define MXC_R_GPIO_WKEN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> 0x004C</tt> */
#define MXC_R_GPIO_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */ #define MXC_R_GPIO_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */
#define MXC_R_GPIO_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */ #define MXC_R_GPIO_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */
#define MXC_R_GPIO_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */ #define MXC_R_GPIO_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */
#define MXC_R_GPIO_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */ #define MXC_R_GPIO_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */
#define MXC_R_GPIO_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */ #define MXC_R_GPIO_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */
#define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */ #define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */
#define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */ #define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */
#define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */ #define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */
#define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> 0x0074</tt> */ #define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> 0x0074</tt> */
#define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> 0x0078</tt> */ #define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> 0x0078</tt> */
#define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> 0x007C</tt> */ #define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> 0x007C</tt> */
#define MXC_R_GPIO_HYSEN ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> 0x00A8</tt> */ #define MXC_R_GPIO_HYSEN ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> 0x00A8</tt> */
#define MXC_R_GPIO_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> 0x00AC</tt> */ #define MXC_R_GPIO_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> 0x00AC</tt> */
#define MXC_R_GPIO_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> 0x00B0</tt> */ #define MXC_R_GPIO_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> 0x00B0</tt> */
#define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> 0x00B4</tt> */ #define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> 0x00B4</tt> */
#define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> 0x00B8</tt> */ #define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> 0x00B8</tt> */
/**@} end of group gpio_registers */ /**@} end of group gpio_registers */
/** /**
@ -174,12 +174,12 @@ typedef struct {
* GPIO pin on the associated port. * GPIO pin on the associated port.
* @{ * @{
*/ */
#define MXC_F_GPIO_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */ #define MXC_F_GPIO_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */
#define MXC_F_GPIO_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */ #define MXC_F_GPIO_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */
#define MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */ #define MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */
#define MXC_S_GPIO_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */ #define MXC_S_GPIO_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */
#define MXC_V_GPIO_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */ #define MXC_V_GPIO_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */
#define MXC_S_GPIO_EN0_GPIO_EN_GPIO (MXC_V_GPIO_EN0_GPIO_EN_GPIO << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */ #define MXC_S_GPIO_EN0_GPIO_EN_GPIO (MXC_V_GPIO_EN0_GPIO_EN_GPIO << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */
/**@} end of group GPIO_EN0_Register */ /**@} end of group GPIO_EN0_Register */
@ -191,8 +191,8 @@ typedef struct {
* other bits in that register. * other bits in that register.
* @{ * @{
*/ */
#define MXC_F_GPIO_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ #define MXC_F_GPIO_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */
#define MXC_F_GPIO_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ #define MXC_F_GPIO_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */
/**@} end of group GPIO_EN0_SET_Register */ /**@} end of group GPIO_EN0_SET_Register */
@ -204,8 +204,8 @@ typedef struct {
* affecting other bits in that register. * affecting other bits in that register.
* @{ * @{
*/ */
#define MXC_F_GPIO_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ #define MXC_F_GPIO_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */
#define MXC_F_GPIO_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ #define MXC_F_GPIO_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */
/**@} end of group GPIO_EN0_CLR_Register */ /**@} end of group GPIO_EN0_CLR_Register */
@ -216,12 +216,12 @@ typedef struct {
* GPIO pin in the associated port. * GPIO pin in the associated port.
* @{ * @{
*/ */
#define MXC_F_GPIO_OUTEN_EN_POS 0 /**< OUTEN_EN Position */ #define MXC_F_GPIO_OUTEN_EN_POS 0 /**< OUTEN_EN Position */
#define MXC_F_GPIO_OUTEN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_EN_POS)) /**< OUTEN_EN Mask */ #define MXC_F_GPIO_OUTEN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_EN_POS)) /**< OUTEN_EN Mask */
#define MXC_V_GPIO_OUTEN_EN_DIS ((uint32_t)0x0UL) /**< OUTEN_EN_DIS Value */ #define MXC_V_GPIO_OUTEN_EN_DIS ((uint32_t)0x0UL) /**< OUTEN_EN_DIS Value */
#define MXC_S_GPIO_OUTEN_EN_DIS (MXC_V_GPIO_OUTEN_EN_DIS << MXC_F_GPIO_OUTEN_EN_POS) /**< OUTEN_EN_DIS Setting */ #define MXC_S_GPIO_OUTEN_EN_DIS (MXC_V_GPIO_OUTEN_EN_DIS << MXC_F_GPIO_OUTEN_EN_POS) /**< OUTEN_EN_DIS Setting */
#define MXC_V_GPIO_OUTEN_EN_EN ((uint32_t)0x1UL) /**< OUTEN_EN_EN Value */ #define MXC_V_GPIO_OUTEN_EN_EN ((uint32_t)0x1UL) /**< OUTEN_EN_EN Value */
#define MXC_S_GPIO_OUTEN_EN_EN (MXC_V_GPIO_OUTEN_EN_EN << MXC_F_GPIO_OUTEN_EN_POS) /**< OUTEN_EN_EN Setting */ #define MXC_S_GPIO_OUTEN_EN_EN (MXC_V_GPIO_OUTEN_EN_EN << MXC_F_GPIO_OUTEN_EN_POS) /**< OUTEN_EN_EN Setting */
/**@} end of group GPIO_OUTEN_Register */ /**@} end of group GPIO_OUTEN_Register */
@ -233,8 +233,8 @@ typedef struct {
* without affecting other bits in that register. * without affecting other bits in that register.
* @{ * @{
*/ */
#define MXC_F_GPIO_OUTEN_SET_ALL_POS 0 /**< OUTEN_SET_ALL Position */ #define MXC_F_GPIO_OUTEN_SET_ALL_POS 0 /**< OUTEN_SET_ALL Position */
#define MXC_F_GPIO_OUTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */ #define MXC_F_GPIO_OUTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */
/**@} end of group GPIO_OUTEN_SET_Register */ /**@} end of group GPIO_OUTEN_SET_Register */
@ -246,8 +246,8 @@ typedef struct {
* without affecting other bits in that register. * without affecting other bits in that register.
* @{ * @{
*/ */
#define MXC_F_GPIO_OUTEN_CLR_ALL_POS 0 /**< OUTEN_CLR_ALL Position */ #define MXC_F_GPIO_OUTEN_CLR_ALL_POS 0 /**< OUTEN_CLR_ALL Position */
#define MXC_F_GPIO_OUTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */ #define MXC_F_GPIO_OUTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */
/**@} end of group GPIO_OUTEN_CLR_Register */ /**@} end of group GPIO_OUTEN_CLR_Register */
@ -259,12 +259,12 @@ typedef struct {
* GPIO_OUT_SET and GPIO_OUT_CLR registers. * GPIO_OUT_SET and GPIO_OUT_CLR registers.
* @{ * @{
*/ */
#define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ #define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */
#define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ #define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */
#define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ #define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */
#define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ #define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */
#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ #define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */
#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ #define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */
/**@} end of group GPIO_OUT_Register */ /**@} end of group GPIO_OUT_Register */
@ -276,12 +276,12 @@ typedef struct {
* register. * register.
* @{ * @{
*/ */
#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */
#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */
#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */
#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */
#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */
#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */
/**@} end of group GPIO_OUT_SET_Register */ /**@} end of group GPIO_OUT_SET_Register */
@ -293,8 +293,8 @@ typedef struct {
* that register. * that register.
* @{ * @{
*/ */
#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */
#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */
/**@} end of group GPIO_OUT_CLR_Register */ /**@} end of group GPIO_OUT_CLR_Register */
@ -305,8 +305,8 @@ typedef struct {
* GPIO pins on this port. * GPIO pins on this port.
* @{ * @{
*/ */
#define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ #define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */
#define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ #define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */
/**@} end of group GPIO_IN_Register */ /**@} end of group GPIO_IN_Register */
@ -317,12 +317,12 @@ typedef struct {
* mode setting for the associated GPIO pin on this port. * mode setting for the associated GPIO pin on this port.
* @{ * @{
*/ */
#define MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS 0 /**< INTMODE_GPIO_INTMODE Position */ #define MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS 0 /**< INTMODE_GPIO_INTMODE Position */
#define MXC_F_GPIO_INTMODE_GPIO_INTMODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS)) /**< INTMODE_GPIO_INTMODE Mask */ #define MXC_F_GPIO_INTMODE_GPIO_INTMODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS)) /**< INTMODE_GPIO_INTMODE Mask */
#define MXC_V_GPIO_INTMODE_GPIO_INTMODE_LEVEL ((uint32_t)0x0UL) /**< INTMODE_GPIO_INTMODE_LEVEL Value */ #define MXC_V_GPIO_INTMODE_GPIO_INTMODE_LEVEL ((uint32_t)0x0UL) /**< INTMODE_GPIO_INTMODE_LEVEL Value */
#define MXC_S_GPIO_INTMODE_GPIO_INTMODE_LEVEL (MXC_V_GPIO_INTMODE_GPIO_INTMODE_LEVEL << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_LEVEL Setting */ #define MXC_S_GPIO_INTMODE_GPIO_INTMODE_LEVEL (MXC_V_GPIO_INTMODE_GPIO_INTMODE_LEVEL << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_LEVEL Setting */
#define MXC_V_GPIO_INTMODE_GPIO_INTMODE_EDGE ((uint32_t)0x1UL) /**< INTMODE_GPIO_INTMODE_EDGE Value */ #define MXC_V_GPIO_INTMODE_GPIO_INTMODE_EDGE ((uint32_t)0x1UL) /**< INTMODE_GPIO_INTMODE_EDGE Value */
#define MXC_S_GPIO_INTMODE_GPIO_INTMODE_EDGE (MXC_V_GPIO_INTMODE_GPIO_INTMODE_EDGE << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_EDGE Setting */ #define MXC_S_GPIO_INTMODE_GPIO_INTMODE_EDGE (MXC_V_GPIO_INTMODE_GPIO_INTMODE_EDGE << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_EDGE Setting */
/**@} end of group GPIO_INTMODE_Register */ /**@} end of group GPIO_INTMODE_Register */
@ -333,12 +333,12 @@ typedef struct {
* interrupt polarity setting for one GPIO pin in the associated port. * interrupt polarity setting for one GPIO pin in the associated port.
* @{ * @{
*/ */
#define MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS 0 /**< INTPOL_GPIO_INTPOL Position */ #define MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS 0 /**< INTPOL_GPIO_INTPOL Position */
#define MXC_F_GPIO_INTPOL_GPIO_INTPOL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS)) /**< INTPOL_GPIO_INTPOL Mask */ #define MXC_F_GPIO_INTPOL_GPIO_INTPOL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS)) /**< INTPOL_GPIO_INTPOL Mask */
#define MXC_V_GPIO_INTPOL_GPIO_INTPOL_FALLING ((uint32_t)0x0UL) /**< INTPOL_GPIO_INTPOL_FALLING Value */ #define MXC_V_GPIO_INTPOL_GPIO_INTPOL_FALLING ((uint32_t)0x0UL) /**< INTPOL_GPIO_INTPOL_FALLING Value */
#define MXC_S_GPIO_INTPOL_GPIO_INTPOL_FALLING (MXC_V_GPIO_INTPOL_GPIO_INTPOL_FALLING << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_FALLING Setting */ #define MXC_S_GPIO_INTPOL_GPIO_INTPOL_FALLING (MXC_V_GPIO_INTPOL_GPIO_INTPOL_FALLING << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_FALLING Setting */
#define MXC_V_GPIO_INTPOL_GPIO_INTPOL_RISING ((uint32_t)0x1UL) /**< INTPOL_GPIO_INTPOL_RISING Value */ #define MXC_V_GPIO_INTPOL_GPIO_INTPOL_RISING ((uint32_t)0x1UL) /**< INTPOL_GPIO_INTPOL_RISING Value */
#define MXC_S_GPIO_INTPOL_GPIO_INTPOL_RISING (MXC_V_GPIO_INTPOL_GPIO_INTPOL_RISING << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_RISING Setting */ #define MXC_S_GPIO_INTPOL_GPIO_INTPOL_RISING (MXC_V_GPIO_INTPOL_GPIO_INTPOL_RISING << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_RISING Setting */
/**@} end of group GPIO_INTPOL_Register */ /**@} end of group GPIO_INTPOL_Register */
@ -349,12 +349,12 @@ typedef struct {
* interrupt enable for the associated pin on the GPIO port. * interrupt enable for the associated pin on the GPIO port.
* @{ * @{
*/ */
#define MXC_F_GPIO_INTEN_GPIO_INTEN_POS 0 /**< INTEN_GPIO_INTEN Position */ #define MXC_F_GPIO_INTEN_GPIO_INTEN_POS 0 /**< INTEN_GPIO_INTEN Position */
#define MXC_F_GPIO_INTEN_GPIO_INTEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_GPIO_INTEN_POS)) /**< INTEN_GPIO_INTEN Mask */ #define MXC_F_GPIO_INTEN_GPIO_INTEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_GPIO_INTEN_POS)) /**< INTEN_GPIO_INTEN Mask */
#define MXC_V_GPIO_INTEN_GPIO_INTEN_DIS ((uint32_t)0x0UL) /**< INTEN_GPIO_INTEN_DIS Value */ #define MXC_V_GPIO_INTEN_GPIO_INTEN_DIS ((uint32_t)0x0UL) /**< INTEN_GPIO_INTEN_DIS Value */
#define MXC_S_GPIO_INTEN_GPIO_INTEN_DIS (MXC_V_GPIO_INTEN_GPIO_INTEN_DIS << MXC_F_GPIO_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_DIS Setting */ #define MXC_S_GPIO_INTEN_GPIO_INTEN_DIS (MXC_V_GPIO_INTEN_GPIO_INTEN_DIS << MXC_F_GPIO_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_DIS Setting */
#define MXC_V_GPIO_INTEN_GPIO_INTEN_EN ((uint32_t)0x1UL) /**< INTEN_GPIO_INTEN_EN Value */ #define MXC_V_GPIO_INTEN_GPIO_INTEN_EN ((uint32_t)0x1UL) /**< INTEN_GPIO_INTEN_EN Value */
#define MXC_S_GPIO_INTEN_GPIO_INTEN_EN (MXC_V_GPIO_INTEN_GPIO_INTEN_EN << MXC_F_GPIO_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_EN Setting */ #define MXC_S_GPIO_INTEN_GPIO_INTEN_EN (MXC_V_GPIO_INTEN_GPIO_INTEN_EN << MXC_F_GPIO_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_EN Setting */
/**@} end of group GPIO_INTEN_Register */ /**@} end of group GPIO_INTEN_Register */
@ -366,12 +366,12 @@ typedef struct {
* in that register. * in that register.
* @{ * @{
*/ */
#define MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS 0 /**< INTEN_SET_GPIO_INTEN_SET Position */ #define MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS 0 /**< INTEN_SET_GPIO_INTEN_SET Position */
#define MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS)) /**< INTEN_SET_GPIO_INTEN_SET Mask */ #define MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS)) /**< INTEN_SET_GPIO_INTEN_SET Mask */
#define MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_NO ((uint32_t)0x0UL) /**< INTEN_SET_GPIO_INTEN_SET_NO Value */ #define MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_NO ((uint32_t)0x0UL) /**< INTEN_SET_GPIO_INTEN_SET_NO Value */
#define MXC_S_GPIO_INTEN_SET_GPIO_INTEN_SET_NO (MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_NO << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_NO Setting */ #define MXC_S_GPIO_INTEN_SET_GPIO_INTEN_SET_NO (MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_NO << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_NO Setting */
#define MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_SET ((uint32_t)0x1UL) /**< INTEN_SET_GPIO_INTEN_SET_SET Value */ #define MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_SET ((uint32_t)0x1UL) /**< INTEN_SET_GPIO_INTEN_SET_SET Value */
#define MXC_S_GPIO_INTEN_SET_GPIO_INTEN_SET_SET (MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_SET << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_SET Setting */ #define MXC_S_GPIO_INTEN_SET_GPIO_INTEN_SET_SET (MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_SET << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_SET Setting */
/**@} end of group GPIO_INTEN_SET_Register */ /**@} end of group GPIO_INTEN_SET_Register */
@ -383,12 +383,12 @@ typedef struct {
* other bits in that register. * other bits in that register.
* @{ * @{
*/ */
#define MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS 0 /**< INTEN_CLR_GPIO_INTEN_CLR Position */ #define MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS 0 /**< INTEN_CLR_GPIO_INTEN_CLR Position */
#define MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS)) /**< INTEN_CLR_GPIO_INTEN_CLR Mask */ #define MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS)) /**< INTEN_CLR_GPIO_INTEN_CLR Mask */
#define MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO ((uint32_t)0x0UL) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Value */ #define MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO ((uint32_t)0x0UL) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Value */
#define MXC_S_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO (MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Setting */ #define MXC_S_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO (MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Setting */
#define MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Value */ #define MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Value */
#define MXC_S_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR (MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Setting */ #define MXC_S_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR (MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Setting */
/**@} end of group GPIO_INTEN_CLR_Register */ /**@} end of group GPIO_INTEN_CLR_Register */
@ -399,12 +399,12 @@ typedef struct {
* interrupt status for the associated GPIO pin in this port. * interrupt status for the associated GPIO pin in this port.
* @{ * @{
*/ */
#define MXC_F_GPIO_INTFL_GPIO_INTFL_POS 0 /**< INTFL_GPIO_INTFL Position */ #define MXC_F_GPIO_INTFL_GPIO_INTFL_POS 0 /**< INTFL_GPIO_INTFL Position */
#define MXC_F_GPIO_INTFL_GPIO_INTFL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_GPIO_INTFL_POS)) /**< INTFL_GPIO_INTFL Mask */ #define MXC_F_GPIO_INTFL_GPIO_INTFL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_GPIO_INTFL_POS)) /**< INTFL_GPIO_INTFL Mask */
#define MXC_V_GPIO_INTFL_GPIO_INTFL_NO ((uint32_t)0x0UL) /**< INTFL_GPIO_INTFL_NO Value */ #define MXC_V_GPIO_INTFL_GPIO_INTFL_NO ((uint32_t)0x0UL) /**< INTFL_GPIO_INTFL_NO Value */
#define MXC_S_GPIO_INTFL_GPIO_INTFL_NO (MXC_V_GPIO_INTFL_GPIO_INTFL_NO << MXC_F_GPIO_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_NO Setting */ #define MXC_S_GPIO_INTFL_GPIO_INTFL_NO (MXC_V_GPIO_INTFL_GPIO_INTFL_NO << MXC_F_GPIO_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_NO Setting */
#define MXC_V_GPIO_INTFL_GPIO_INTFL_PENDING ((uint32_t)0x1UL) /**< INTFL_GPIO_INTFL_PENDING Value */ #define MXC_V_GPIO_INTFL_GPIO_INTFL_PENDING ((uint32_t)0x1UL) /**< INTFL_GPIO_INTFL_PENDING Value */
#define MXC_S_GPIO_INTFL_GPIO_INTFL_PENDING (MXC_V_GPIO_INTFL_GPIO_INTFL_PENDING << MXC_F_GPIO_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_PENDING Setting */ #define MXC_S_GPIO_INTFL_GPIO_INTFL_PENDING (MXC_V_GPIO_INTFL_GPIO_INTFL_PENDING << MXC_F_GPIO_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_PENDING Setting */
/**@} end of group GPIO_INTFL_Register */ /**@} end of group GPIO_INTFL_Register */
@ -416,8 +416,8 @@ typedef struct {
* in that register. * in that register.
* @{ * @{
*/ */
#define MXC_F_GPIO_INTFL_CLR_ALL_POS 0 /**< INTFL_CLR_ALL Position */ #define MXC_F_GPIO_INTFL_CLR_ALL_POS 0 /**< INTFL_CLR_ALL Position */
#define MXC_F_GPIO_INTFL_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */ #define MXC_F_GPIO_INTFL_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */
/**@} end of group GPIO_INTFL_CLR_Register */ /**@} end of group GPIO_INTFL_CLR_Register */
@ -428,12 +428,12 @@ typedef struct {
* enable for the associated GPIO pin in this port. * enable for the associated GPIO pin in this port.
* @{ * @{
*/ */
#define MXC_F_GPIO_WKEN_GPIO_WKEN_POS 0 /**< WKEN_GPIO_WKEN Position */ #define MXC_F_GPIO_WKEN_GPIO_WKEN_POS 0 /**< WKEN_GPIO_WKEN Position */
#define MXC_F_GPIO_WKEN_GPIO_WKEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_GPIO_WKEN_POS)) /**< WKEN_GPIO_WKEN Mask */ #define MXC_F_GPIO_WKEN_GPIO_WKEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_GPIO_WKEN_POS)) /**< WKEN_GPIO_WKEN Mask */
#define MXC_V_GPIO_WKEN_GPIO_WKEN_DIS ((uint32_t)0x0UL) /**< WKEN_GPIO_WKEN_DIS Value */ #define MXC_V_GPIO_WKEN_GPIO_WKEN_DIS ((uint32_t)0x0UL) /**< WKEN_GPIO_WKEN_DIS Value */
#define MXC_S_GPIO_WKEN_GPIO_WKEN_DIS (MXC_V_GPIO_WKEN_GPIO_WKEN_DIS << MXC_F_GPIO_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_DIS Setting */ #define MXC_S_GPIO_WKEN_GPIO_WKEN_DIS (MXC_V_GPIO_WKEN_GPIO_WKEN_DIS << MXC_F_GPIO_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_DIS Setting */
#define MXC_V_GPIO_WKEN_GPIO_WKEN_EN ((uint32_t)0x1UL) /**< WKEN_GPIO_WKEN_EN Value */ #define MXC_V_GPIO_WKEN_GPIO_WKEN_EN ((uint32_t)0x1UL) /**< WKEN_GPIO_WKEN_EN Value */
#define MXC_S_GPIO_WKEN_GPIO_WKEN_EN (MXC_V_GPIO_WKEN_GPIO_WKEN_EN << MXC_F_GPIO_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_EN Setting */ #define MXC_S_GPIO_WKEN_GPIO_WKEN_EN (MXC_V_GPIO_WKEN_GPIO_WKEN_EN << MXC_F_GPIO_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_EN Setting */
/**@} end of group GPIO_WKEN_Register */ /**@} end of group GPIO_WKEN_Register */
@ -445,8 +445,8 @@ typedef struct {
* that register. * that register.
* @{ * @{
*/ */
#define MXC_F_GPIO_WKEN_SET_ALL_POS 0 /**< WKEN_SET_ALL Position */ #define MXC_F_GPIO_WKEN_SET_ALL_POS 0 /**< WKEN_SET_ALL Position */
#define MXC_F_GPIO_WKEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */ #define MXC_F_GPIO_WKEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */
/**@} end of group GPIO_WKEN_SET_Register */ /**@} end of group GPIO_WKEN_SET_Register */
@ -458,8 +458,8 @@ typedef struct {
* bits in that register. * bits in that register.
* @{ * @{
*/ */
#define MXC_F_GPIO_WKEN_CLR_ALL_POS 0 /**< WKEN_CLR_ALL Position */ #define MXC_F_GPIO_WKEN_CLR_ALL_POS 0 /**< WKEN_CLR_ALL Position */
#define MXC_F_GPIO_WKEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */ #define MXC_F_GPIO_WKEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */
/**@} end of group GPIO_WKEN_CLR_Register */ /**@} end of group GPIO_WKEN_CLR_Register */
@ -470,12 +470,12 @@ typedef struct {
* edge mode for the associated GPIO pin in this port. * edge mode for the associated GPIO pin in this port.
* @{ * @{
*/ */
#define MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS 0 /**< DUALEDGE_GPIO_DUALEDGE Position */ #define MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS 0 /**< DUALEDGE_GPIO_DUALEDGE Position */
#define MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS)) /**< DUALEDGE_GPIO_DUALEDGE Mask */ #define MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS)) /**< DUALEDGE_GPIO_DUALEDGE Mask */
#define MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_NO ((uint32_t)0x0UL) /**< DUALEDGE_GPIO_DUALEDGE_NO Value */ #define MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_NO ((uint32_t)0x0UL) /**< DUALEDGE_GPIO_DUALEDGE_NO Value */
#define MXC_S_GPIO_DUALEDGE_GPIO_DUALEDGE_NO (MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_NO << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_NO Setting */ #define MXC_S_GPIO_DUALEDGE_GPIO_DUALEDGE_NO (MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_NO << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_NO Setting */
#define MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_EN ((uint32_t)0x1UL) /**< DUALEDGE_GPIO_DUALEDGE_EN Value */ #define MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_EN ((uint32_t)0x1UL) /**< DUALEDGE_GPIO_DUALEDGE_EN Value */
#define MXC_S_GPIO_DUALEDGE_GPIO_DUALEDGE_EN (MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_EN << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_EN Setting */ #define MXC_S_GPIO_DUALEDGE_GPIO_DUALEDGE_EN (MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_EN << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_EN Setting */
/**@} end of group GPIO_DUALEDGE_Register */ /**@} end of group GPIO_DUALEDGE_Register */
@ -486,14 +486,14 @@ typedef struct {
* the associated GPIO pin in this port. * the associated GPIO pin in this port.
* @{ * @{
*/ */
#define MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS 0 /**< PADCTRL0_GPIO_PADCTRL0 Position */ #define MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS 0 /**< PADCTRL0_GPIO_PADCTRL0 Position */
#define MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS)) /**< PADCTRL0_GPIO_PADCTRL0 Mask */ #define MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS)) /**< PADCTRL0_GPIO_PADCTRL0 Mask */
#define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Value */ #define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Value */
#define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Setting */ #define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Setting */
#define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PU ((uint32_t)0x1UL) /**< PADCTRL0_GPIO_PADCTRL0_PU Value */ #define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PU ((uint32_t)0x1UL) /**< PADCTRL0_GPIO_PADCTRL0_PU Value */
#define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_PU (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PU << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PU Setting */ #define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_PU (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PU << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PU Setting */
#define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PD ((uint32_t)0x2UL) /**< PADCTRL0_GPIO_PADCTRL0_PD Value */ #define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PD ((uint32_t)0x2UL) /**< PADCTRL0_GPIO_PADCTRL0_PD Value */
#define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_PD (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PD << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PD Setting */ #define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_PD (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PD << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PD Setting */
/**@} end of group GPIO_PADCTRL0_Register */ /**@} end of group GPIO_PADCTRL0_Register */
@ -504,14 +504,14 @@ typedef struct {
* the associated GPIO pin in this port. * the associated GPIO pin in this port.
* @{ * @{
*/ */
#define MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS 0 /**< PADCTRL1_GPIO_PADCTRL1 Position */ #define MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS 0 /**< PADCTRL1_GPIO_PADCTRL1 Position */
#define MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS)) /**< PADCTRL1_GPIO_PADCTRL1 Mask */ #define MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS)) /**< PADCTRL1_GPIO_PADCTRL1 Mask */
#define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Value */ #define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Value */
#define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Setting */ #define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Setting */
#define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PU ((uint32_t)0x1UL) /**< PADCTRL1_GPIO_PADCTRL1_PU Value */ #define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PU ((uint32_t)0x1UL) /**< PADCTRL1_GPIO_PADCTRL1_PU Value */
#define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_PU (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PU << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PU Setting */ #define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_PU (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PU << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PU Setting */
#define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PD ((uint32_t)0x2UL) /**< PADCTRL1_GPIO_PADCTRL1_PD Value */ #define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PD ((uint32_t)0x2UL) /**< PADCTRL1_GPIO_PADCTRL1_PD Value */
#define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_PD (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PD << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PD Setting */ #define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_PD (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PD << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PD Setting */
/**@} end of group GPIO_PADCTRL1_Register */ /**@} end of group GPIO_PADCTRL1_Register */
@ -522,12 +522,12 @@ typedef struct {
* between primary/secondary functions for the associated GPIO pin in this port. * between primary/secondary functions for the associated GPIO pin in this port.
* @{ * @{
*/ */
#define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ #define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */
#define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ #define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */
#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ #define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */
#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ #define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */
#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ #define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */
#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ #define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */
/**@} end of group GPIO_EN1_Register */ /**@} end of group GPIO_EN1_Register */
@ -539,8 +539,8 @@ typedef struct {
* bits in that register. * bits in that register.
* @{ * @{
*/ */
#define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ #define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */
#define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ #define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */
/**@} end of group GPIO_EN1_SET_Register */ /**@} end of group GPIO_EN1_SET_Register */
@ -552,8 +552,8 @@ typedef struct {
* bits in that register. * bits in that register.
* @{ * @{
*/ */
#define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ #define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */
#define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ #define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */
/**@} end of group GPIO_EN1_CLR_Register */ /**@} end of group GPIO_EN1_CLR_Register */
@ -564,12 +564,12 @@ typedef struct {
* between primary/secondary functions for the associated GPIO pin in this port. * between primary/secondary functions for the associated GPIO pin in this port.
* @{ * @{
*/ */
#define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ #define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */
#define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ #define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */
#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ #define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */
#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ #define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */
#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ #define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */
#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ #define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */
/**@} end of group GPIO_EN2_Register */ /**@} end of group GPIO_EN2_Register */
@ -581,8 +581,8 @@ typedef struct {
* bits in that register. * bits in that register.
* @{ * @{
*/ */
#define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ #define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */
#define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ #define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */
/**@} end of group GPIO_EN2_SET_Register */ /**@} end of group GPIO_EN2_SET_Register */
@ -594,8 +594,8 @@ typedef struct {
* affecting other bits in that register. * affecting other bits in that register.
* @{ * @{
*/ */
#define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ #define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */
#define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ #define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */
/**@} end of group GPIO_EN2_CLR_Register */ /**@} end of group GPIO_EN2_CLR_Register */
@ -605,8 +605,8 @@ typedef struct {
* @brief GPIO Input Hysteresis Enable. * @brief GPIO Input Hysteresis Enable.
* @{ * @{
*/ */
#define MXC_F_GPIO_HYSEN_GPIO_HYSEN_POS 0 /**< HYSEN_GPIO_HYSEN Position */ #define MXC_F_GPIO_HYSEN_GPIO_HYSEN_POS 0 /**< HYSEN_GPIO_HYSEN Position */
#define MXC_F_GPIO_HYSEN_GPIO_HYSEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_HYSEN_GPIO_HYSEN_POS)) /**< HYSEN_GPIO_HYSEN Mask */ #define MXC_F_GPIO_HYSEN_GPIO_HYSEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_HYSEN_GPIO_HYSEN_POS)) /**< HYSEN_GPIO_HYSEN Mask */
/**@} end of group GPIO_HYSEN_Register */ /**@} end of group GPIO_HYSEN_Register */
@ -616,12 +616,12 @@ typedef struct {
* @brief GPIO Slew Rate Enable Register. * @brief GPIO Slew Rate Enable Register.
* @{ * @{
*/ */
#define MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS 0 /**< SRSEL_GPIO_SRSEL Position */ #define MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS 0 /**< SRSEL_GPIO_SRSEL Position */
#define MXC_F_GPIO_SRSEL_GPIO_SRSEL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS)) /**< SRSEL_GPIO_SRSEL Mask */ #define MXC_F_GPIO_SRSEL_GPIO_SRSEL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS)) /**< SRSEL_GPIO_SRSEL Mask */
#define MXC_V_GPIO_SRSEL_GPIO_SRSEL_FAST ((uint32_t)0x0UL) /**< SRSEL_GPIO_SRSEL_FAST Value */ #define MXC_V_GPIO_SRSEL_GPIO_SRSEL_FAST ((uint32_t)0x0UL) /**< SRSEL_GPIO_SRSEL_FAST Value */
#define MXC_S_GPIO_SRSEL_GPIO_SRSEL_FAST (MXC_V_GPIO_SRSEL_GPIO_SRSEL_FAST << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_FAST Setting */ #define MXC_S_GPIO_SRSEL_GPIO_SRSEL_FAST (MXC_V_GPIO_SRSEL_GPIO_SRSEL_FAST << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_FAST Setting */
#define MXC_V_GPIO_SRSEL_GPIO_SRSEL_SLOW ((uint32_t)0x1UL) /**< SRSEL_GPIO_SRSEL_SLOW Value */ #define MXC_V_GPIO_SRSEL_GPIO_SRSEL_SLOW ((uint32_t)0x1UL) /**< SRSEL_GPIO_SRSEL_SLOW Value */
#define MXC_S_GPIO_SRSEL_GPIO_SRSEL_SLOW (MXC_V_GPIO_SRSEL_GPIO_SRSEL_SLOW << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_SLOW Setting */ #define MXC_S_GPIO_SRSEL_GPIO_SRSEL_SLOW (MXC_V_GPIO_SRSEL_GPIO_SRSEL_SLOW << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_SLOW Setting */
/**@} end of group GPIO_SRSEL_Register */ /**@} end of group GPIO_SRSEL_Register */
@ -633,12 +633,12 @@ typedef struct {
* sink/source current of GPIO pins in each mode. * sink/source current of GPIO pins in each mode.
* @{ * @{
*/ */
#define MXC_F_GPIO_DS0_GPIO_DS0_POS 0 /**< DS0_GPIO_DS0 Position */ #define MXC_F_GPIO_DS0_GPIO_DS0_POS 0 /**< DS0_GPIO_DS0 Position */
#define MXC_F_GPIO_DS0_GPIO_DS0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_GPIO_DS0_POS)) /**< DS0_GPIO_DS0 Mask */ #define MXC_F_GPIO_DS0_GPIO_DS0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_GPIO_DS0_POS)) /**< DS0_GPIO_DS0 Mask */
#define MXC_V_GPIO_DS0_GPIO_DS0_LD ((uint32_t)0x0UL) /**< DS0_GPIO_DS0_LD Value */ #define MXC_V_GPIO_DS0_GPIO_DS0_LD ((uint32_t)0x0UL) /**< DS0_GPIO_DS0_LD Value */
#define MXC_S_GPIO_DS0_GPIO_DS0_LD (MXC_V_GPIO_DS0_GPIO_DS0_LD << MXC_F_GPIO_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_LD Setting */ #define MXC_S_GPIO_DS0_GPIO_DS0_LD (MXC_V_GPIO_DS0_GPIO_DS0_LD << MXC_F_GPIO_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_LD Setting */
#define MXC_V_GPIO_DS0_GPIO_DS0_HD ((uint32_t)0x1UL) /**< DS0_GPIO_DS0_HD Value */ #define MXC_V_GPIO_DS0_GPIO_DS0_HD ((uint32_t)0x1UL) /**< DS0_GPIO_DS0_HD Value */
#define MXC_S_GPIO_DS0_GPIO_DS0_HD (MXC_V_GPIO_DS0_GPIO_DS0_HD << MXC_F_GPIO_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_HD Setting */ #define MXC_S_GPIO_DS0_GPIO_DS0_HD (MXC_V_GPIO_DS0_GPIO_DS0_HD << MXC_F_GPIO_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_HD Setting */
/**@} end of group GPIO_DS0_Register */ /**@} end of group GPIO_DS0_Register */
@ -650,8 +650,8 @@ typedef struct {
* sink/source current of GPIO pins in each mode. * sink/source current of GPIO pins in each mode.
* @{ * @{
*/ */
#define MXC_F_GPIO_DS1_GPIO_DS1_POS 0 /**< DS1_GPIO_DS1 Position */ #define MXC_F_GPIO_DS1_GPIO_DS1_POS 0 /**< DS1_GPIO_DS1 Position */
#define MXC_F_GPIO_DS1_GPIO_DS1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_GPIO_DS1_POS)) /**< DS1_GPIO_DS1 Mask */ #define MXC_F_GPIO_DS1_GPIO_DS1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_GPIO_DS1_POS)) /**< DS1_GPIO_DS1 Mask */
/**@} end of group GPIO_DS1_Register */ /**@} end of group GPIO_DS1_Register */
@ -661,8 +661,8 @@ typedef struct {
* @brief GPIO Pull Select Mode. * @brief GPIO Pull Select Mode.
* @{ * @{
*/ */
#define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */ #define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */
#define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */ #define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */
/**@} end of group GPIO_PS_Register */ /**@} end of group GPIO_PS_Register */
@ -670,4 +670,4 @@ typedef struct {
} }
#endif #endif
#endif /* _GPIO_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GPIO_REGS_H_

440
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2c_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file i2c_regs.h * @file i2c_regs.h
* @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _I2C_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_I2C_REGS_H_
#define _I2C_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_I2C_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup i2c * @ingroup i2c
* @defgroup i2c_registers I2C_Registers * @defgroup i2c_registers I2C_Registers
* @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
* @details Inter-Integrated Circuit. * @details Inter-Integrated Circuit.
*/ */
/** /**
@ -111,25 +111,25 @@ typedef struct {
* @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> 0x0000</tt> */ #define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> 0x0000</tt> */
#define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> 0x0004</tt> */ #define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> 0x0004</tt> */
#define MXC_R_I2C_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> 0x0008</tt> */ #define MXC_R_I2C_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> 0x0008</tt> */
#define MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> 0x000C</tt> */ #define MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> 0x000C</tt> */
#define MXC_R_I2C_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> 0x0010</tt> */ #define MXC_R_I2C_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> 0x0010</tt> */
#define MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> 0x0014</tt> */ #define MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> 0x0014</tt> */
#define MXC_R_I2C_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> 0x0018</tt> */ #define MXC_R_I2C_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> 0x0018</tt> */
#define MXC_R_I2C_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> 0x001C</tt> */ #define MXC_R_I2C_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> 0x001C</tt> */
#define MXC_R_I2C_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> 0x0020</tt> */ #define MXC_R_I2C_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> 0x0020</tt> */
#define MXC_R_I2C_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> 0x0024</tt> */ #define MXC_R_I2C_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> 0x0024</tt> */
#define MXC_R_I2C_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> 0x0028</tt> */ #define MXC_R_I2C_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> 0x0028</tt> */
#define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> 0x002C</tt> */ #define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> 0x002C</tt> */
#define MXC_R_I2C_MSTCTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> 0x0030</tt> */ #define MXC_R_I2C_MSTCTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> 0x0030</tt> */
#define MXC_R_I2C_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> 0x0034</tt> */ #define MXC_R_I2C_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> 0x0034</tt> */
#define MXC_R_I2C_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> 0x0038</tt> */ #define MXC_R_I2C_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> 0x0038</tt> */
#define MXC_R_I2C_HSCLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt> 0x003C</tt> */ #define MXC_R_I2C_HSCLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt> 0x003C</tt> */
#define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> 0x0040</tt> */ #define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> 0x0040</tt> */
#define MXC_R_I2C_SLAVE ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: <tt> 0x0044</tt> */ #define MXC_R_I2C_SLAVE ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: <tt> 0x0044</tt> */
#define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> 0x0048</tt> */ #define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> 0x0048</tt> */
/**@} end of group i2c_registers */ /**@} end of group i2c_registers */
/** /**
@ -138,47 +138,47 @@ typedef struct {
* @brief Control Register0. * @brief Control Register0.
* @{ * @{
*/ */
#define MXC_F_I2C_CTRL_EN_POS 0 /**< CTRL_EN Position */ #define MXC_F_I2C_CTRL_EN_POS 0 /**< CTRL_EN Position */
#define MXC_F_I2C_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_EN_POS)) /**< CTRL_EN Mask */ #define MXC_F_I2C_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_EN_POS)) /**< CTRL_EN Mask */
#define MXC_F_I2C_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */ #define MXC_F_I2C_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */
#define MXC_F_I2C_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */ #define MXC_F_I2C_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */
#define MXC_F_I2C_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */ #define MXC_F_I2C_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */
#define MXC_F_I2C_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */ #define MXC_F_I2C_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */
#define MXC_F_I2C_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */ #define MXC_F_I2C_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */
#define MXC_F_I2C_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */ #define MXC_F_I2C_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */
#define MXC_F_I2C_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */ #define MXC_F_I2C_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */
#define MXC_F_I2C_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */ #define MXC_F_I2C_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */
#define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ #define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */
#define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ #define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */
#define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ #define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */
#define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ #define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */
#define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ #define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */
#define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ #define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */
#define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ #define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */
#define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ #define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */
#define MXC_F_I2C_CTRL_BB_MODE_POS 10 /**< CTRL_BB_MODE Position */ #define MXC_F_I2C_CTRL_BB_MODE_POS 10 /**< CTRL_BB_MODE Position */
#define MXC_F_I2C_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */ #define MXC_F_I2C_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */
#define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */ #define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */
#define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */ #define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */
#define MXC_F_I2C_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */ #define MXC_F_I2C_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */
#define MXC_F_I2C_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */ #define MXC_F_I2C_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */
#define MXC_F_I2C_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */ #define MXC_F_I2C_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */
#define MXC_F_I2C_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */ #define MXC_F_I2C_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */
#define MXC_F_I2C_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */ #define MXC_F_I2C_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */
#define MXC_F_I2C_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */ #define MXC_F_I2C_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */
/**@} end of group I2C_CTRL_Register */ /**@} end of group I2C_CTRL_Register */
@ -188,23 +188,23 @@ typedef struct {
* @brief Status Register. * @brief Status Register.
* @{ * @{
*/ */
#define MXC_F_I2C_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ #define MXC_F_I2C_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */
#define MXC_F_I2C_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ #define MXC_F_I2C_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */
#define MXC_F_I2C_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */ #define MXC_F_I2C_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */
#define MXC_F_I2C_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ #define MXC_F_I2C_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */
#define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ #define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */
#define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ #define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
#define MXC_F_I2C_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */ #define MXC_F_I2C_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */
#define MXC_F_I2C_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ #define MXC_F_I2C_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */
#define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ #define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */
#define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ #define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
#define MXC_F_I2C_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */ #define MXC_F_I2C_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */
#define MXC_F_I2C_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */ #define MXC_F_I2C_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */
/**@} end of group I2C_STATUS_Register */ /**@} end of group I2C_STATUS_Register */
@ -214,62 +214,62 @@ typedef struct {
* @brief Interrupt Status Register. * @brief Interrupt Status Register.
* @{ * @{
*/ */
#define MXC_F_I2C_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */ #define MXC_F_I2C_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */
#define MXC_F_I2C_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */ #define MXC_F_I2C_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */
#define MXC_F_I2C_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */ #define MXC_F_I2C_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */
#define MXC_F_I2C_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */ #define MXC_F_I2C_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */
#define MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */ #define MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */
#define MXC_F_I2C_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */ #define MXC_F_I2C_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */
#define MXC_F_I2C_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */ #define MXC_F_I2C_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */
#define MXC_F_I2C_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */ #define MXC_F_I2C_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */
#define MXC_F_I2C_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */ #define MXC_F_I2C_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */
#define MXC_F_I2C_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */ #define MXC_F_I2C_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */
#define MXC_F_I2C_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */ #define MXC_F_I2C_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */
#define MXC_F_I2C_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */ #define MXC_F_I2C_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */
#define MXC_F_I2C_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */ #define MXC_F_I2C_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */
#define MXC_F_I2C_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */ #define MXC_F_I2C_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */
#define MXC_F_I2C_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */ #define MXC_F_I2C_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */
#define MXC_F_I2C_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */ #define MXC_F_I2C_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */
#define MXC_F_I2C_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */ #define MXC_F_I2C_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */
#define MXC_F_I2C_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */ #define MXC_F_I2C_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */
#define MXC_F_I2C_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */ #define MXC_F_I2C_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */
#define MXC_F_I2C_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */ #define MXC_F_I2C_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */
#define MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */ #define MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */
#define MXC_F_I2C_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */ #define MXC_F_I2C_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */
#define MXC_F_I2C_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */ #define MXC_F_I2C_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */
#define MXC_F_I2C_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */ #define MXC_F_I2C_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */
#define MXC_F_I2C_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */ #define MXC_F_I2C_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */
#define MXC_F_I2C_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */ #define MXC_F_I2C_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */
#define MXC_F_I2C_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */ #define MXC_F_I2C_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */
#define MXC_F_I2C_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */ #define MXC_F_I2C_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */
#define MXC_F_I2C_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */ #define MXC_F_I2C_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */
#define MXC_F_I2C_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */ #define MXC_F_I2C_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */
#define MXC_F_I2C_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */ #define MXC_F_I2C_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */
#define MXC_F_I2C_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */ #define MXC_F_I2C_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */
#define MXC_F_I2C_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */ #define MXC_F_I2C_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */
#define MXC_F_I2C_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */ #define MXC_F_I2C_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */
#define MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */ #define MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */
#define MXC_F_I2C_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */ #define MXC_F_I2C_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */
#define MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */ #define MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */
#define MXC_F_I2C_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */ #define MXC_F_I2C_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */
/**@} end of group I2C_INTFL0_Register */ /**@} end of group I2C_INTFL0_Register */
@ -279,62 +279,62 @@ typedef struct {
* @brief Interrupt Enable Register. * @brief Interrupt Enable Register.
* @{ * @{
*/ */
#define MXC_F_I2C_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */ #define MXC_F_I2C_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */
#define MXC_F_I2C_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */ #define MXC_F_I2C_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */
#define MXC_F_I2C_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */ #define MXC_F_I2C_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */
#define MXC_F_I2C_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */ #define MXC_F_I2C_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */
#define MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */ #define MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */
#define MXC_F_I2C_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */ #define MXC_F_I2C_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */
#define MXC_F_I2C_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */ #define MXC_F_I2C_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */
#define MXC_F_I2C_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */ #define MXC_F_I2C_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */
#define MXC_F_I2C_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */ #define MXC_F_I2C_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */
#define MXC_F_I2C_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */ #define MXC_F_I2C_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */
#define MXC_F_I2C_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */ #define MXC_F_I2C_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */
#define MXC_F_I2C_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */ #define MXC_F_I2C_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */
#define MXC_F_I2C_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */ #define MXC_F_I2C_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */
#define MXC_F_I2C_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */ #define MXC_F_I2C_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */
#define MXC_F_I2C_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */ #define MXC_F_I2C_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */
#define MXC_F_I2C_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */ #define MXC_F_I2C_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */
#define MXC_F_I2C_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */ #define MXC_F_I2C_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */
#define MXC_F_I2C_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */ #define MXC_F_I2C_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */
#define MXC_F_I2C_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */ #define MXC_F_I2C_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */
#define MXC_F_I2C_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */ #define MXC_F_I2C_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */
#define MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */ #define MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */
#define MXC_F_I2C_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */ #define MXC_F_I2C_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */
#define MXC_F_I2C_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */ #define MXC_F_I2C_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */
#define MXC_F_I2C_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */ #define MXC_F_I2C_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */
#define MXC_F_I2C_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */ #define MXC_F_I2C_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */
#define MXC_F_I2C_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */ #define MXC_F_I2C_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */
#define MXC_F_I2C_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */ #define MXC_F_I2C_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */
#define MXC_F_I2C_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */ #define MXC_F_I2C_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */
#define MXC_F_I2C_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */ #define MXC_F_I2C_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */
#define MXC_F_I2C_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */ #define MXC_F_I2C_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */
#define MXC_F_I2C_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */ #define MXC_F_I2C_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */
#define MXC_F_I2C_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */ #define MXC_F_I2C_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */
#define MXC_F_I2C_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */ #define MXC_F_I2C_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */
#define MXC_F_I2C_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */ #define MXC_F_I2C_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */
#define MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */ #define MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */
#define MXC_F_I2C_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */ #define MXC_F_I2C_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */
#define MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */ #define MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */
#define MXC_F_I2C_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */ #define MXC_F_I2C_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */
/**@} end of group I2C_INTEN0_Register */ /**@} end of group I2C_INTEN0_Register */
@ -344,14 +344,14 @@ typedef struct {
* @brief Interrupt Status Register 1. * @brief Interrupt Status Register 1.
* @{ * @{
*/ */
#define MXC_F_I2C_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */ #define MXC_F_I2C_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */
#define MXC_F_I2C_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */ #define MXC_F_I2C_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */
#define MXC_F_I2C_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */ #define MXC_F_I2C_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */
#define MXC_F_I2C_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */ #define MXC_F_I2C_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */
#define MXC_F_I2C_INTFL1_START_POS 2 /**< INTFL1_START Position */ #define MXC_F_I2C_INTFL1_START_POS 2 /**< INTFL1_START Position */
#define MXC_F_I2C_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_START_POS)) /**< INTFL1_START Mask */ #define MXC_F_I2C_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_START_POS)) /**< INTFL1_START Mask */
/**@} end of group I2C_INTFL1_Register */ /**@} end of group I2C_INTFL1_Register */
@ -361,14 +361,14 @@ typedef struct {
* @brief Interrupt Staus Register 1. * @brief Interrupt Staus Register 1.
* @{ * @{
*/ */
#define MXC_F_I2C_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */ #define MXC_F_I2C_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */
#define MXC_F_I2C_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */ #define MXC_F_I2C_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */
#define MXC_F_I2C_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */ #define MXC_F_I2C_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */
#define MXC_F_I2C_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */ #define MXC_F_I2C_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */
#define MXC_F_I2C_INTEN1_START_POS 2 /**< INTEN1_START Position */ #define MXC_F_I2C_INTEN1_START_POS 2 /**< INTEN1_START Position */
#define MXC_F_I2C_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_START_POS)) /**< INTEN1_START Mask */ #define MXC_F_I2C_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_START_POS)) /**< INTEN1_START Mask */
/**@} end of group I2C_INTEN1_Register */ /**@} end of group I2C_INTEN1_Register */
@ -378,11 +378,11 @@ typedef struct {
* @brief FIFO Configuration Register. * @brief FIFO Configuration Register.
* @{ * @{
*/ */
#define MXC_F_I2C_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */ #define MXC_F_I2C_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */
#define MXC_F_I2C_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */ #define MXC_F_I2C_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */
#define MXC_F_I2C_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */ #define MXC_F_I2C_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */
#define MXC_F_I2C_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */ #define MXC_F_I2C_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */
/**@} end of group I2C_FIFOLEN_Register */ /**@} end of group I2C_FIFOLEN_Register */
@ -392,14 +392,14 @@ typedef struct {
* @brief Receive Control Register 0. * @brief Receive Control Register 0.
* @{ * @{
*/ */
#define MXC_F_I2C_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ #define MXC_F_I2C_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */
#define MXC_F_I2C_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ #define MXC_F_I2C_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */
#define MXC_F_I2C_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */ #define MXC_F_I2C_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */
#define MXC_F_I2C_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */ #define MXC_F_I2C_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */
#define MXC_F_I2C_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */ #define MXC_F_I2C_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */
#define MXC_F_I2C_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */ #define MXC_F_I2C_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */
/**@} end of group I2C_RXCTRL0_Register */ /**@} end of group I2C_RXCTRL0_Register */
@ -409,11 +409,11 @@ typedef struct {
* @brief Receive Control Register 1. * @brief Receive Control Register 1.
* @{ * @{
*/ */
#define MXC_F_I2C_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */ #define MXC_F_I2C_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */
#define MXC_F_I2C_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */ #define MXC_F_I2C_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */
#define MXC_F_I2C_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */ #define MXC_F_I2C_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */
#define MXC_F_I2C_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */ #define MXC_F_I2C_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */
/**@} end of group I2C_RXCTRL1_Register */ /**@} end of group I2C_RXCTRL1_Register */
@ -423,29 +423,29 @@ typedef struct {
* @brief Transmit Control Register 0. * @brief Transmit Control Register 0.
* @{ * @{
*/ */
#define MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */ #define MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */
#define MXC_F_I2C_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */ #define MXC_F_I2C_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */
#define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ #define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */
#define MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ #define MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */
#define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */ #define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */
#define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */ #define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */
#define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */ #define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */
#define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */ #define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */
#define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */ #define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */
#define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */ #define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */
#define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */ #define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */
#define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */ #define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */
#define MXC_F_I2C_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */ #define MXC_F_I2C_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */
#define MXC_F_I2C_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */ #define MXC_F_I2C_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */
#define MXC_F_I2C_TXCTRL0_THD_VAL_POS 8 /**< TXCTRL0_THD_VAL Position */ #define MXC_F_I2C_TXCTRL0_THD_VAL_POS 8 /**< TXCTRL0_THD_VAL Position */
#define MXC_F_I2C_TXCTRL0_THD_VAL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_THD_VAL_POS)) /**< TXCTRL0_THD_VAL Mask */ #define MXC_F_I2C_TXCTRL0_THD_VAL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_THD_VAL_POS)) /**< TXCTRL0_THD_VAL Mask */
/**@} end of group I2C_TXCTRL0_Register */ /**@} end of group I2C_TXCTRL0_Register */
@ -455,11 +455,11 @@ typedef struct {
* @brief Transmit Control Register 1. * @brief Transmit Control Register 1.
* @{ * @{
*/ */
#define MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */ #define MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */
#define MXC_F_I2C_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */ #define MXC_F_I2C_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */
#define MXC_F_I2C_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */ #define MXC_F_I2C_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */
#define MXC_F_I2C_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */ #define MXC_F_I2C_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */
/**@} end of group I2C_TXCTRL1_Register */ /**@} end of group I2C_TXCTRL1_Register */
@ -469,8 +469,8 @@ typedef struct {
* @brief Data Register. * @brief Data Register.
* @{ * @{
*/ */
#define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ #define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */
#define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ #define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
/**@} end of group I2C_FIFO_Register */ /**@} end of group I2C_FIFO_Register */
@ -480,17 +480,17 @@ typedef struct {
* @brief Master Control Register. * @brief Master Control Register.
* @{ * @{
*/ */
#define MXC_F_I2C_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */ #define MXC_F_I2C_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */
#define MXC_F_I2C_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */ #define MXC_F_I2C_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */
#define MXC_F_I2C_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */ #define MXC_F_I2C_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */
#define MXC_F_I2C_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */ #define MXC_F_I2C_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */
#define MXC_F_I2C_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */ #define MXC_F_I2C_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */
#define MXC_F_I2C_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */ #define MXC_F_I2C_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */
#define MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */ #define MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */
#define MXC_F_I2C_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */ #define MXC_F_I2C_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */
/**@} end of group I2C_MSTCTRL_Register */ /**@} end of group I2C_MSTCTRL_Register */
@ -500,8 +500,8 @@ typedef struct {
* @brief Clock Low Register. * @brief Clock Low Register.
* @{ * @{
*/ */
#define MXC_F_I2C_CLKLO_LO_POS 0 /**< CLKLO_LO Position */ #define MXC_F_I2C_CLKLO_LO_POS 0 /**< CLKLO_LO Position */
#define MXC_F_I2C_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_LO_POS)) /**< CLKLO_LO Mask */ #define MXC_F_I2C_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_LO_POS)) /**< CLKLO_LO Mask */
/**@} end of group I2C_CLKLO_Register */ /**@} end of group I2C_CLKLO_Register */
@ -511,8 +511,8 @@ typedef struct {
* @brief Clock high Register. * @brief Clock high Register.
* @{ * @{
*/ */
#define MXC_F_I2C_CLKHI_HI_POS 0 /**< CLKHI_HI Position */ #define MXC_F_I2C_CLKHI_HI_POS 0 /**< CLKHI_HI Position */
#define MXC_F_I2C_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_HI_POS)) /**< CLKHI_HI Mask */ #define MXC_F_I2C_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_HI_POS)) /**< CLKHI_HI Mask */
/**@} end of group I2C_CLKHI_Register */ /**@} end of group I2C_CLKHI_Register */
@ -522,11 +522,11 @@ typedef struct {
* @brief Clock high Register. * @brief Clock high Register.
* @{ * @{
*/ */
#define MXC_F_I2C_HSCLK_LO_POS 0 /**< HSCLK_LO Position */ #define MXC_F_I2C_HSCLK_LO_POS 0 /**< HSCLK_LO Position */
#define MXC_F_I2C_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_LO_POS)) /**< HSCLK_LO Mask */ #define MXC_F_I2C_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_LO_POS)) /**< HSCLK_LO Mask */
#define MXC_F_I2C_HSCLK_HI_POS 8 /**< HSCLK_HI Position */ #define MXC_F_I2C_HSCLK_HI_POS 8 /**< HSCLK_HI Position */
#define MXC_F_I2C_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_HI_POS)) /**< HSCLK_HI Mask */ #define MXC_F_I2C_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_HI_POS)) /**< HSCLK_HI Mask */
/**@} end of group I2C_HSCLK_Register */ /**@} end of group I2C_HSCLK_Register */
@ -536,8 +536,8 @@ typedef struct {
* @brief Timeout Register * @brief Timeout Register
* @{ * @{
*/ */
#define MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */ #define MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */
#define MXC_F_I2C_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */ #define MXC_F_I2C_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */
/**@} end of group I2C_TIMEOUT_Register */ /**@} end of group I2C_TIMEOUT_Register */
@ -547,11 +547,17 @@ typedef struct {
* @brief Slave Address Register. * @brief Slave Address Register.
* @{ * @{
*/ */
#define MXC_F_I2C_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR Position */ #define MXC_F_I2C_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR Position */
#define MXC_F_I2C_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_POS)) /**< SLAVE_ADDR Mask */ #define MXC_F_I2C_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_POS)) /**< SLAVE_ADDR Mask */
#define MXC_F_I2C_SLAVE_EXT_ADDR_EN_POS 15 /**< SLAVE_EXT_ADDR_EN Position */ #define MXC_F_I2C_SLAVE_DIS_POS 10 /**< SLAVE_DIS Position */
#define MXC_F_I2C_SLAVE_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_EXT_ADDR_EN_POS)) /**< SLAVE_EXT_ADDR_EN Mask */ #define MXC_F_I2C_SLAVE_DIS ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_DIS_POS)) /**< SLAVE_DIS Mask */
#define MXC_F_I2C_SLAVE_IDX_POS 11 /**< SLAVE_IDX Position */
#define MXC_F_I2C_SLAVE_IDX ((uint32_t)(0xFUL << MXC_F_I2C_SLAVE_IDX_POS)) /**< SLAVE_IDX Mask */
#define MXC_F_I2C_SLAVE_EXT_ADDR_EN_POS 15 /**< SLAVE_EXT_ADDR_EN Position */
#define MXC_F_I2C_SLAVE_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_EXT_ADDR_EN_POS)) /**< SLAVE_EXT_ADDR_EN Mask */
/**@} end of group I2C_SLAVE_Register */ /**@} end of group I2C_SLAVE_Register */
@ -561,11 +567,11 @@ typedef struct {
* @brief DMA Register. * @brief DMA Register.
* @{ * @{
*/ */
#define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ #define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */
#define MXC_F_I2C_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ #define MXC_F_I2C_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */
#define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ #define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */
#define MXC_F_I2C_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ #define MXC_F_I2C_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */
/**@} end of group I2C_DMA_Register */ /**@} end of group I2C_DMA_Register */
@ -573,4 +579,4 @@ typedef struct {
} }
#endif #endif
#endif /* _I2C_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_I2C_REGS_H_

170
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2s_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file i2s_regs.h * @file i2s_regs.h
* @brief Registers, Bit Masks and Bit Positions for the I2S Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the I2S Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _I2S_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_I2S_REGS_H_
#define _I2S_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_I2S_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup i2s * @ingroup i2s
* @defgroup i2s_registers I2S_Registers * @defgroup i2s_registers I2S_Registers
* @brief Registers, Bit Masks and Bit Positions for the I2S Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the I2S Peripheral Module.
* @details Inter-IC Sound Interface. * @details Inter-IC Sound Interface.
*/ */
/** /**
@ -103,13 +103,13 @@ typedef struct {
* @brief I2S Peripheral Register Offsets from the I2S Base Peripheral Address. * @brief I2S Peripheral Register Offsets from the I2S Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_I2S_CTRL0CH0 ((uint32_t)0x00000000UL) /**< Offset from I2S Base Address: <tt> 0x0000</tt> */ #define MXC_R_I2S_CTRL0CH0 ((uint32_t)0x00000000UL) /**< Offset from I2S Base Address: <tt> 0x0000</tt> */
#define MXC_R_I2S_CTRL1CH0 ((uint32_t)0x00000010UL) /**< Offset from I2S Base Address: <tt> 0x0010</tt> */ #define MXC_R_I2S_CTRL1CH0 ((uint32_t)0x00000010UL) /**< Offset from I2S Base Address: <tt> 0x0010</tt> */
#define MXC_R_I2S_DMACH0 ((uint32_t)0x00000030UL) /**< Offset from I2S Base Address: <tt> 0x0030</tt> */ #define MXC_R_I2S_DMACH0 ((uint32_t)0x00000030UL) /**< Offset from I2S Base Address: <tt> 0x0030</tt> */
#define MXC_R_I2S_FIFOCH0 ((uint32_t)0x00000040UL) /**< Offset from I2S Base Address: <tt> 0x0040</tt> */ #define MXC_R_I2S_FIFOCH0 ((uint32_t)0x00000040UL) /**< Offset from I2S Base Address: <tt> 0x0040</tt> */
#define MXC_R_I2S_INTFL ((uint32_t)0x00000050UL) /**< Offset from I2S Base Address: <tt> 0x0050</tt> */ #define MXC_R_I2S_INTFL ((uint32_t)0x00000050UL) /**< Offset from I2S Base Address: <tt> 0x0050</tt> */
#define MXC_R_I2S_INTEN ((uint32_t)0x00000054UL) /**< Offset from I2S Base Address: <tt> 0x0054</tt> */ #define MXC_R_I2S_INTEN ((uint32_t)0x00000054UL) /**< Offset from I2S Base Address: <tt> 0x0054</tt> */
#define MXC_R_I2S_EXTSETUP ((uint32_t)0x00000058UL) /**< Offset from I2S Base Address: <tt> 0x0058</tt> */ #define MXC_R_I2S_EXTSETUP ((uint32_t)0x00000058UL) /**< Offset from I2S Base Address: <tt> 0x0058</tt> */
/**@} end of group i2s_registers */ /**@} end of group i2s_registers */
/** /**
@ -118,47 +118,47 @@ typedef struct {
* @brief Global mode channel. * @brief Global mode channel.
* @{ * @{
*/ */
#define MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS 1 /**< CTRL0CH0_LSB_FIRST Position */ #define MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS 1 /**< CTRL0CH0_LSB_FIRST Position */
#define MXC_F_I2S_CTRL0CH0_LSB_FIRST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS)) /**< CTRL0CH0_LSB_FIRST Mask */ #define MXC_F_I2S_CTRL0CH0_LSB_FIRST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS)) /**< CTRL0CH0_LSB_FIRST Mask */
#define MXC_F_I2S_CTRL0CH0_CH_MODE_POS 6 /**< CTRL0CH0_CH_MODE Position */ #define MXC_F_I2S_CTRL0CH0_CH_MODE_POS 6 /**< CTRL0CH0_CH_MODE Position */
#define MXC_F_I2S_CTRL0CH0_CH_MODE ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_CH_MODE_POS)) /**< CTRL0CH0_CH_MODE Mask */ #define MXC_F_I2S_CTRL0CH0_CH_MODE ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_CH_MODE_POS)) /**< CTRL0CH0_CH_MODE Mask */
#define MXC_F_I2S_CTRL0CH0_WS_POL_POS 8 /**< CTRL0CH0_WS_POL Position */ #define MXC_F_I2S_CTRL0CH0_WS_POL_POS 8 /**< CTRL0CH0_WS_POL Position */
#define MXC_F_I2S_CTRL0CH0_WS_POL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_WS_POL_POS)) /**< CTRL0CH0_WS_POL Mask */ #define MXC_F_I2S_CTRL0CH0_WS_POL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_WS_POL_POS)) /**< CTRL0CH0_WS_POL Mask */
#define MXC_F_I2S_CTRL0CH0_MSB_LOC_POS 9 /**< CTRL0CH0_MSB_LOC Position */ #define MXC_F_I2S_CTRL0CH0_MSB_LOC_POS 9 /**< CTRL0CH0_MSB_LOC Position */
#define MXC_F_I2S_CTRL0CH0_MSB_LOC ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_MSB_LOC_POS)) /**< CTRL0CH0_MSB_LOC Mask */ #define MXC_F_I2S_CTRL0CH0_MSB_LOC ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_MSB_LOC_POS)) /**< CTRL0CH0_MSB_LOC Mask */
#define MXC_F_I2S_CTRL0CH0_ALIGN_POS 10 /**< CTRL0CH0_ALIGN Position */ #define MXC_F_I2S_CTRL0CH0_ALIGN_POS 10 /**< CTRL0CH0_ALIGN Position */
#define MXC_F_I2S_CTRL0CH0_ALIGN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_ALIGN_POS)) /**< CTRL0CH0_ALIGN Mask */ #define MXC_F_I2S_CTRL0CH0_ALIGN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_ALIGN_POS)) /**< CTRL0CH0_ALIGN Mask */
#define MXC_F_I2S_CTRL0CH0_EXT_SEL_POS 11 /**< CTRL0CH0_EXT_SEL Position */ #define MXC_F_I2S_CTRL0CH0_EXT_SEL_POS 11 /**< CTRL0CH0_EXT_SEL Position */
#define MXC_F_I2S_CTRL0CH0_EXT_SEL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_EXT_SEL_POS)) /**< CTRL0CH0_EXT_SEL Mask */ #define MXC_F_I2S_CTRL0CH0_EXT_SEL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_EXT_SEL_POS)) /**< CTRL0CH0_EXT_SEL Mask */
#define MXC_F_I2S_CTRL0CH0_STEREO_POS 12 /**< CTRL0CH0_STEREO Position */ #define MXC_F_I2S_CTRL0CH0_STEREO_POS 12 /**< CTRL0CH0_STEREO Position */
#define MXC_F_I2S_CTRL0CH0_STEREO ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_STEREO_POS)) /**< CTRL0CH0_STEREO Mask */ #define MXC_F_I2S_CTRL0CH0_STEREO ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_STEREO_POS)) /**< CTRL0CH0_STEREO Mask */
#define MXC_F_I2S_CTRL0CH0_WSIZE_POS 14 /**< CTRL0CH0_WSIZE Position */ #define MXC_F_I2S_CTRL0CH0_WSIZE_POS 14 /**< CTRL0CH0_WSIZE Position */
#define MXC_F_I2S_CTRL0CH0_WSIZE ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_WSIZE_POS)) /**< CTRL0CH0_WSIZE Mask */ #define MXC_F_I2S_CTRL0CH0_WSIZE ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_WSIZE_POS)) /**< CTRL0CH0_WSIZE Mask */
#define MXC_F_I2S_CTRL0CH0_TX_EN_POS 16 /**< CTRL0CH0_TX_EN Position */ #define MXC_F_I2S_CTRL0CH0_TX_EN_POS 16 /**< CTRL0CH0_TX_EN Position */
#define MXC_F_I2S_CTRL0CH0_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_TX_EN_POS)) /**< CTRL0CH0_TX_EN Mask */ #define MXC_F_I2S_CTRL0CH0_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_TX_EN_POS)) /**< CTRL0CH0_TX_EN Mask */
#define MXC_F_I2S_CTRL0CH0_RX_EN_POS 17 /**< CTRL0CH0_RX_EN Position */ #define MXC_F_I2S_CTRL0CH0_RX_EN_POS 17 /**< CTRL0CH0_RX_EN Position */
#define MXC_F_I2S_CTRL0CH0_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RX_EN_POS)) /**< CTRL0CH0_RX_EN Mask */ #define MXC_F_I2S_CTRL0CH0_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RX_EN_POS)) /**< CTRL0CH0_RX_EN Mask */
#define MXC_F_I2S_CTRL0CH0_FLUSH_POS 18 /**< CTRL0CH0_FLUSH Position */ #define MXC_F_I2S_CTRL0CH0_FLUSH_POS 18 /**< CTRL0CH0_FLUSH Position */
#define MXC_F_I2S_CTRL0CH0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FLUSH_POS)) /**< CTRL0CH0_FLUSH Mask */ #define MXC_F_I2S_CTRL0CH0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FLUSH_POS)) /**< CTRL0CH0_FLUSH Mask */
#define MXC_F_I2S_CTRL0CH0_RST_POS 19 /**< CTRL0CH0_RST Position */ #define MXC_F_I2S_CTRL0CH0_RST_POS 19 /**< CTRL0CH0_RST Position */
#define MXC_F_I2S_CTRL0CH0_RST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RST_POS)) /**< CTRL0CH0_RST Mask */ #define MXC_F_I2S_CTRL0CH0_RST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RST_POS)) /**< CTRL0CH0_RST Mask */
#define MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS 19 /**< CTRL0CH0_FIFO_LSB Position */ #define MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS 20 /**< CTRL0CH0_FIFO_LSB Position */
#define MXC_F_I2S_CTRL0CH0_FIFO_LSB ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS)) /**< CTRL0CH0_FIFO_LSB Mask */ #define MXC_F_I2S_CTRL0CH0_FIFO_LSB ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS)) /**< CTRL0CH0_FIFO_LSB Mask */
#define MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS 24 /**< CTRL0CH0_RX_THD_VAL Position */ #define MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS 24 /**< CTRL0CH0_RX_THD_VAL Position */
#define MXC_F_I2S_CTRL0CH0_RX_THD_VAL ((uint32_t)(0xFFUL << MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS)) /**< CTRL0CH0_RX_THD_VAL Mask */ #define MXC_F_I2S_CTRL0CH0_RX_THD_VAL ((uint32_t)(0xFFUL << MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS)) /**< CTRL0CH0_RX_THD_VAL Mask */
/**@} end of group I2S_CTRL0CH0_Register */ /**@} end of group I2S_CTRL0CH0_Register */
@ -168,20 +168,20 @@ typedef struct {
* @brief Local channel Setup. * @brief Local channel Setup.
* @{ * @{
*/ */
#define MXC_F_I2S_CTRL1CH0_BITS_WORD_POS 0 /**< CTRL1CH0_BITS_WORD Position */ #define MXC_F_I2S_CTRL1CH0_BITS_WORD_POS 0 /**< CTRL1CH0_BITS_WORD Position */
#define MXC_F_I2S_CTRL1CH0_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_BITS_WORD_POS)) /**< CTRL1CH0_BITS_WORD Mask */ #define MXC_F_I2S_CTRL1CH0_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_BITS_WORD_POS)) /**< CTRL1CH0_BITS_WORD Mask */
#define MXC_F_I2S_CTRL1CH0_EN_POS 8 /**< CTRL1CH0_EN Position */ #define MXC_F_I2S_CTRL1CH0_EN_POS 8 /**< CTRL1CH0_EN Position */
#define MXC_F_I2S_CTRL1CH0_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_EN_POS)) /**< CTRL1CH0_EN Mask */ #define MXC_F_I2S_CTRL1CH0_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_EN_POS)) /**< CTRL1CH0_EN Mask */
#define MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS 9 /**< CTRL1CH0_SMP_SIZE Position */ #define MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS 9 /**< CTRL1CH0_SMP_SIZE Position */
#define MXC_F_I2S_CTRL1CH0_SMP_SIZE ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS)) /**< CTRL1CH0_SMP_SIZE Mask */ #define MXC_F_I2S_CTRL1CH0_SMP_SIZE ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS)) /**< CTRL1CH0_SMP_SIZE Mask */
#define MXC_F_I2S_CTRL1CH0_ADJST_POS 15 /**< CTRL1CH0_ADJST Position */ #define MXC_F_I2S_CTRL1CH0_ADJST_POS 15 /**< CTRL1CH0_ADJST Position */
#define MXC_F_I2S_CTRL1CH0_ADJST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_ADJST_POS)) /**< CTRL1CH0_ADJST Mask */ #define MXC_F_I2S_CTRL1CH0_ADJST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_ADJST_POS)) /**< CTRL1CH0_ADJST Mask */
#define MXC_F_I2S_CTRL1CH0_CLKDIV_POS 16 /**< CTRL1CH0_CLKDIV Position */ #define MXC_F_I2S_CTRL1CH0_CLKDIV_POS 16 /**< CTRL1CH0_CLKDIV Position */
#define MXC_F_I2S_CTRL1CH0_CLKDIV ((uint32_t)(0xFFFFUL << MXC_F_I2S_CTRL1CH0_CLKDIV_POS)) /**< CTRL1CH0_CLKDIV Mask */ #define MXC_F_I2S_CTRL1CH0_CLKDIV ((uint32_t)(0xFFFFUL << MXC_F_I2S_CTRL1CH0_CLKDIV_POS)) /**< CTRL1CH0_CLKDIV Mask */
/**@} end of group I2S_CTRL1CH0_Register */ /**@} end of group I2S_CTRL1CH0_Register */
@ -191,23 +191,23 @@ typedef struct {
* @brief DMA Control. * @brief DMA Control.
* @{ * @{
*/ */
#define MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS 0 /**< DMACH0_DMA_TX_THD_VAL Position */ #define MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS 0 /**< DMACH0_DMA_TX_THD_VAL Position */
#define MXC_F_I2S_DMACH0_DMA_TX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS)) /**< DMACH0_DMA_TX_THD_VAL Mask */ #define MXC_F_I2S_DMACH0_DMA_TX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS)) /**< DMACH0_DMA_TX_THD_VAL Mask */
#define MXC_F_I2S_DMACH0_DMA_TX_EN_POS 7 /**< DMACH0_DMA_TX_EN Position */ #define MXC_F_I2S_DMACH0_DMA_TX_EN_POS 7 /**< DMACH0_DMA_TX_EN Position */
#define MXC_F_I2S_DMACH0_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_TX_EN_POS)) /**< DMACH0_DMA_TX_EN Mask */ #define MXC_F_I2S_DMACH0_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_TX_EN_POS)) /**< DMACH0_DMA_TX_EN Mask */
#define MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS 8 /**< DMACH0_DMA_RX_THD_VAL Position */ #define MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS 8 /**< DMACH0_DMA_RX_THD_VAL Position */
#define MXC_F_I2S_DMACH0_DMA_RX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS)) /**< DMACH0_DMA_RX_THD_VAL Mask */ #define MXC_F_I2S_DMACH0_DMA_RX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS)) /**< DMACH0_DMA_RX_THD_VAL Mask */
#define MXC_F_I2S_DMACH0_DMA_RX_EN_POS 15 /**< DMACH0_DMA_RX_EN Position */ #define MXC_F_I2S_DMACH0_DMA_RX_EN_POS 15 /**< DMACH0_DMA_RX_EN Position */
#define MXC_F_I2S_DMACH0_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_RX_EN_POS)) /**< DMACH0_DMA_RX_EN Mask */ #define MXC_F_I2S_DMACH0_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_RX_EN_POS)) /**< DMACH0_DMA_RX_EN Mask */
#define MXC_F_I2S_DMACH0_TX_LVL_POS 16 /**< DMACH0_TX_LVL Position */ #define MXC_F_I2S_DMACH0_TX_LVL_POS 16 /**< DMACH0_TX_LVL Position */
#define MXC_F_I2S_DMACH0_TX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_TX_LVL_POS)) /**< DMACH0_TX_LVL Mask */ #define MXC_F_I2S_DMACH0_TX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_TX_LVL_POS)) /**< DMACH0_TX_LVL Mask */
#define MXC_F_I2S_DMACH0_RX_LVL_POS 24 /**< DMACH0_RX_LVL Position */ #define MXC_F_I2S_DMACH0_RX_LVL_POS 24 /**< DMACH0_RX_LVL Position */
#define MXC_F_I2S_DMACH0_RX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_RX_LVL_POS)) /**< DMACH0_RX_LVL Mask */ #define MXC_F_I2S_DMACH0_RX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_RX_LVL_POS)) /**< DMACH0_RX_LVL Mask */
/**@} end of group I2S_DMACH0_Register */ /**@} end of group I2S_DMACH0_Register */
@ -217,8 +217,8 @@ typedef struct {
* @brief I2S Fifo. * @brief I2S Fifo.
* @{ * @{
*/ */
#define MXC_F_I2S_FIFOCH0_DATA_POS 0 /**< FIFOCH0_DATA Position */ #define MXC_F_I2S_FIFOCH0_DATA_POS 0 /**< FIFOCH0_DATA Position */
#define MXC_F_I2S_FIFOCH0_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_I2S_FIFOCH0_DATA_POS)) /**< FIFOCH0_DATA Mask */ #define MXC_F_I2S_FIFOCH0_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_I2S_FIFOCH0_DATA_POS)) /**< FIFOCH0_DATA Mask */
/**@} end of group I2S_FIFOCH0_Register */ /**@} end of group I2S_FIFOCH0_Register */
@ -228,17 +228,17 @@ typedef struct {
* @brief ISR Status. * @brief ISR Status.
* @{ * @{
*/ */
#define MXC_F_I2S_INTFL_RX_OV_CH0_POS 0 /**< INTFL_RX_OV_CH0 Position */ #define MXC_F_I2S_INTFL_RX_OV_CH0_POS 0 /**< INTFL_RX_OV_CH0 Position */
#define MXC_F_I2S_INTFL_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_OV_CH0_POS)) /**< INTFL_RX_OV_CH0 Mask */ #define MXC_F_I2S_INTFL_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_OV_CH0_POS)) /**< INTFL_RX_OV_CH0 Mask */
#define MXC_F_I2S_INTFL_RX_THD_CH0_POS 1 /**< INTFL_RX_THD_CH0 Position */ #define MXC_F_I2S_INTFL_RX_THD_CH0_POS 1 /**< INTFL_RX_THD_CH0 Position */
#define MXC_F_I2S_INTFL_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_THD_CH0_POS)) /**< INTFL_RX_THD_CH0 Mask */ #define MXC_F_I2S_INTFL_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_THD_CH0_POS)) /**< INTFL_RX_THD_CH0 Mask */
#define MXC_F_I2S_INTFL_TX_OB_CH0_POS 2 /**< INTFL_TX_OB_CH0 Position */ #define MXC_F_I2S_INTFL_TX_OB_CH0_POS 2 /**< INTFL_TX_OB_CH0 Position */
#define MXC_F_I2S_INTFL_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_OB_CH0_POS)) /**< INTFL_TX_OB_CH0 Mask */ #define MXC_F_I2S_INTFL_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_OB_CH0_POS)) /**< INTFL_TX_OB_CH0 Mask */
#define MXC_F_I2S_INTFL_TX_HE_CH0_POS 3 /**< INTFL_TX_HE_CH0 Position */ #define MXC_F_I2S_INTFL_TX_HE_CH0_POS 3 /**< INTFL_TX_HE_CH0 Position */
#define MXC_F_I2S_INTFL_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_HE_CH0_POS)) /**< INTFL_TX_HE_CH0 Mask */ #define MXC_F_I2S_INTFL_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_HE_CH0_POS)) /**< INTFL_TX_HE_CH0 Mask */
/**@} end of group I2S_INTFL_Register */ /**@} end of group I2S_INTFL_Register */
@ -248,17 +248,17 @@ typedef struct {
* @brief Interrupt Enable. * @brief Interrupt Enable.
* @{ * @{
*/ */
#define MXC_F_I2S_INTEN_RX_OV_CH0_POS 0 /**< INTEN_RX_OV_CH0 Position */ #define MXC_F_I2S_INTEN_RX_OV_CH0_POS 0 /**< INTEN_RX_OV_CH0 Position */
#define MXC_F_I2S_INTEN_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_OV_CH0_POS)) /**< INTEN_RX_OV_CH0 Mask */ #define MXC_F_I2S_INTEN_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_OV_CH0_POS)) /**< INTEN_RX_OV_CH0 Mask */
#define MXC_F_I2S_INTEN_RX_THD_CH0_POS 1 /**< INTEN_RX_THD_CH0 Position */ #define MXC_F_I2S_INTEN_RX_THD_CH0_POS 1 /**< INTEN_RX_THD_CH0 Position */
#define MXC_F_I2S_INTEN_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_THD_CH0_POS)) /**< INTEN_RX_THD_CH0 Mask */ #define MXC_F_I2S_INTEN_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_THD_CH0_POS)) /**< INTEN_RX_THD_CH0 Mask */
#define MXC_F_I2S_INTEN_TX_OB_CH0_POS 2 /**< INTEN_TX_OB_CH0 Position */ #define MXC_F_I2S_INTEN_TX_OB_CH0_POS 2 /**< INTEN_TX_OB_CH0 Position */
#define MXC_F_I2S_INTEN_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_OB_CH0_POS)) /**< INTEN_TX_OB_CH0 Mask */ #define MXC_F_I2S_INTEN_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_OB_CH0_POS)) /**< INTEN_TX_OB_CH0 Mask */
#define MXC_F_I2S_INTEN_TX_HE_CH0_POS 3 /**< INTEN_TX_HE_CH0 Position */ #define MXC_F_I2S_INTEN_TX_HE_CH0_POS 3 /**< INTEN_TX_HE_CH0 Position */
#define MXC_F_I2S_INTEN_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_HE_CH0_POS)) /**< INTEN_TX_HE_CH0 Mask */ #define MXC_F_I2S_INTEN_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_HE_CH0_POS)) /**< INTEN_TX_HE_CH0 Mask */
/**@} end of group I2S_INTEN_Register */ /**@} end of group I2S_INTEN_Register */
@ -268,8 +268,8 @@ typedef struct {
* @brief Ext Control. * @brief Ext Control.
* @{ * @{
*/ */
#define MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS 0 /**< EXTSETUP_EXT_BITS_WORD Position */ #define MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS 0 /**< EXTSETUP_EXT_BITS_WORD Position */
#define MXC_F_I2S_EXTSETUP_EXT_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS)) /**< EXTSETUP_EXT_BITS_WORD Mask */ #define MXC_F_I2S_EXTSETUP_EXT_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS)) /**< EXTSETUP_EXT_BITS_WORD Mask */
/**@} end of group I2S_EXTSETUP_Register */ /**@} end of group I2S_EXTSETUP_Register */
@ -277,4 +277,4 @@ typedef struct {
} }
#endif #endif
#endif /* _I2S_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_I2S_REGS_H_

56
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/icc_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file icc_regs.h * @file icc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _ICC_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_ICC_REGS_H_
#define _ICC_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_ICC_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup icc * @ingroup icc
* @defgroup icc_registers ICC_Registers * @defgroup icc_registers ICC_Registers
* @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module.
* @details Instruction Cache Controller Registers * @details Instruction Cache Controller Registers
*/ */
/** /**
@ -98,10 +98,10 @@ typedef struct {
* @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address. * @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_ICC_INFO ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt> 0x0000</tt> */ #define MXC_R_ICC_INFO ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt> 0x0000</tt> */
#define MXC_R_ICC_SZ ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt> 0x0004</tt> */ #define MXC_R_ICC_SZ ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt> 0x0004</tt> */
#define MXC_R_ICC_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt> 0x0100</tt> */ #define MXC_R_ICC_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt> 0x0100</tt> */
#define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt> 0x0700</tt> */ #define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt> 0x0700</tt> */
/**@} end of group icc_registers */ /**@} end of group icc_registers */
/** /**
@ -110,14 +110,14 @@ typedef struct {
* @brief Cache ID Register. * @brief Cache ID Register.
* @{ * @{
*/ */
#define MXC_F_ICC_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */ #define MXC_F_ICC_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */
#define MXC_F_ICC_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */ #define MXC_F_ICC_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */
#define MXC_F_ICC_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */ #define MXC_F_ICC_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */
#define MXC_F_ICC_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */ #define MXC_F_ICC_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */
#define MXC_F_ICC_INFO_ID_POS 10 /**< INFO_ID Position */ #define MXC_F_ICC_INFO_ID_POS 10 /**< INFO_ID Position */
#define MXC_F_ICC_INFO_ID ((uint32_t)(0x3FUL << MXC_F_ICC_INFO_ID_POS)) /**< INFO_ID Mask */ #define MXC_F_ICC_INFO_ID ((uint32_t)(0x3FUL << MXC_F_ICC_INFO_ID_POS)) /**< INFO_ID Mask */
/**@} end of group ICC_INFO_Register */ /**@} end of group ICC_INFO_Register */
@ -127,11 +127,11 @@ typedef struct {
* @brief Memory Configuration Register. * @brief Memory Configuration Register.
* @{ * @{
*/ */
#define MXC_F_ICC_SZ_CCH_POS 0 /**< SZ_CCH Position */ #define MXC_F_ICC_SZ_CCH_POS 0 /**< SZ_CCH Position */
#define MXC_F_ICC_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_ICC_SZ_CCH_POS)) /**< SZ_CCH Mask */ #define MXC_F_ICC_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_ICC_SZ_CCH_POS)) /**< SZ_CCH Mask */
#define MXC_F_ICC_SZ_MEM_POS 16 /**< SZ_MEM Position */ #define MXC_F_ICC_SZ_MEM_POS 16 /**< SZ_MEM Position */
#define MXC_F_ICC_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_ICC_SZ_MEM_POS)) /**< SZ_MEM Mask */ #define MXC_F_ICC_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_ICC_SZ_MEM_POS)) /**< SZ_MEM Mask */
/**@} end of group ICC_SZ_Register */ /**@} end of group ICC_SZ_Register */
@ -141,11 +141,11 @@ typedef struct {
* @brief Cache Control and Status Register. * @brief Cache Control and Status Register.
* @{ * @{
*/ */
#define MXC_F_ICC_CTRL_EN_POS 0 /**< CTRL_EN Position */ #define MXC_F_ICC_CTRL_EN_POS 0 /**< CTRL_EN Position */
#define MXC_F_ICC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_ICC_CTRL_EN_POS)) /**< CTRL_EN Mask */ #define MXC_F_ICC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_ICC_CTRL_EN_POS)) /**< CTRL_EN Mask */
#define MXC_F_ICC_CTRL_RDY_POS 16 /**< CTRL_RDY Position */ #define MXC_F_ICC_CTRL_RDY_POS 16 /**< CTRL_RDY Position */
#define MXC_F_ICC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_ICC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ #define MXC_F_ICC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_ICC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
/**@} end of group ICC_CTRL_Register */ /**@} end of group ICC_CTRL_Register */
@ -155,8 +155,8 @@ typedef struct {
* @brief Invalidate All Registers. * @brief Invalidate All Registers.
* @{ * @{
*/ */
#define MXC_F_ICC_INVALIDATE_INVALID_POS 0 /**< INVALIDATE_INVALID Position */ #define MXC_F_ICC_INVALIDATE_INVALID_POS 0 /**< INVALIDATE_INVALID Position */
#define MXC_F_ICC_INVALIDATE_INVALID ((uint32_t)(0xFFFFFFFFUL << MXC_F_ICC_INVALIDATE_INVALID_POS)) /**< INVALIDATE_INVALID Mask */ #define MXC_F_ICC_INVALIDATE_INVALID ((uint32_t)(0xFFFFFFFFUL << MXC_F_ICC_INVALIDATE_INVALID_POS)) /**< INVALIDATE_INVALID Mask */
/**@} end of group ICC_INVALIDATE_Register */ /**@} end of group ICC_INVALIDATE_Register */
@ -164,4 +164,4 @@ typedef struct {
} }
#endif #endif
#endif /* _ICC_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_ICC_REGS_H_

902
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.h
View File

@ -1,5 +1,5 @@
/******************************************************************************* /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -29,32 +29,32 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*
******************************************************************************/ ******************************************************************************/
#ifndef _MAX32670_REGS_H_
#define _MAX32670_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MAX32670_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MAX32670_H_
#ifndef TARGET_NUM #ifndef TARGET_NUM
#define TARGET_NUM 32670 #define TARGET_NUM 32670
#endif #endif
#define MXC_NUMCORES 1 #define MXC_NUMCORES 1
#include <stdint.h> #include <stdint.h>
#ifndef FALSE #ifndef FALSE
#define FALSE (0) #define FALSE (0)
#endif #endif
#ifndef TRUE #ifndef TRUE
#define TRUE (1) #define TRUE (1)
#endif #endif
/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
#if defined ( __GNUC__ ) #if defined(__GNUC__)
#define __weak __attribute__((weak)) #define __weak __attribute__((weak))
#elif defined ( __CC_ARM) #elif defined(__CC_ARM)
#define inline __inline #define inline __inline
#pragma anon_unions #pragma anon_unions
@ -62,15 +62,15 @@
#endif #endif
typedef enum { typedef enum {
NonMaskableInt_IRQn = -14, NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13, HardFault_IRQn = -13,
MemoryManagement_IRQn = -12, MemoryManagement_IRQn = -12,
BusFault_IRQn = -11, BusFault_IRQn = -11,
UsageFault_IRQn = -10, UsageFault_IRQn = -10,
SVCall_IRQn = -5, SVCall_IRQn = -5,
DebugMonitor_IRQn = -4, DebugMonitor_IRQn = -4,
PendSV_IRQn = -2, PendSV_IRQn = -2,
SysTick_IRQn = -1, SysTick_IRQn = -1,
/* Device-specific interrupt sources (external to ARM core) */ /* Device-specific interrupt sources (external to ARM core) */
/* table entry number */ /* table entry number */
@ -78,146 +78,144 @@ typedef enum {
/* |||| table offset address */ /* |||| table offset address */
/* vvvv vvvvvv */ /* vvvv vvvvvv */
PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */ PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */
WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */ WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */
RSV02_IRQn, /* 0x12 0x0048 18: Reserved */ RSV02_IRQn, /* 0x12 0x0048 18: Reserved */
RTC_IRQn, /* 0x13 0x004C 19: RTC */ RTC_IRQn, /* 0x13 0x004C 19: RTC */
TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */ TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */
TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */
TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */
TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */
TMR3_IRQn, /* 0x18 0x0060 24: Timer 3 */ TMR3_IRQn, /* 0x18 0x0060 24: Timer 3 */
TMR4_IRQn, /* 0x19 0x0064 25: Timer 4 */ TMR4_IRQn, /* 0x19 0x0064 25: Timer 4 */
TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 */ TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 */
RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */ RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */
RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */ RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */
I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */ I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */
UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */ UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */
UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */ UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */
SPI0_IRQn, /* 0x20 0x0080 32: SPI0 */ SPI0_IRQn, /* 0x20 0x0080 32: SPI0 */
SPI1_IRQn, /* 0x21 0x0084 33: SPI1 */ SPI1_IRQn, /* 0x21 0x0084 33: SPI1 */
SPI2_IRQn, /* 0x22 0x0088 34: SPI2 */ SPI2_IRQn, /* 0x22 0x0088 34: SPI2 */
RSV19_IRQn, /* 0x23 0x008C 35: Reserved */ RSV19_IRQn, /* 0x23 0x008C 35: Reserved */
RSV20_IRQn, /* 0x24 0x0090 36: Reserved */ RSV20_IRQn, /* 0x24 0x0090 36: Reserved */
RSV21_IRQn, /* 0x25 0x0094 37: Reserved */ RSV21_IRQn, /* 0x25 0x0094 37: Reserved */
RSV22_IRQn, /* 0x26 0x0098 38: Magstripe DSP */ RSV22_IRQn, /* 0x26 0x0098 38: Magstripe DSP */
FLC0_IRQn, /* 0x27 0x009C 39: Flash Controller 0 */ FLC0_IRQn, /* 0x27 0x009C 39: Flash Controller 0 */
GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */
GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO2 */ GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO2 */
RSV26_IRQn, /* 0x2A 0x00A8 42: Reserved */ RSV26_IRQn, /* 0x2A 0x00A8 42: Reserved */
RSV27_IRQn, /* 0x2B 0x00AC 43: Reserved */ RSV27_IRQn, /* 0x2B 0x00AC 43: Reserved */
DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */
DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */
DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */
DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */
RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */ RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */
RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */ RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */
UART2_IRQn, /* 0x32 0x00C8 50: UART 2 */ UART2_IRQn, /* 0x32 0x00C8 50: UART 2 */
RSV35_IRQn, /* 0x33 0x00CC 51: Contactless Link Control */ RSV35_IRQn, /* 0x33 0x00CC 51: Contactless Link Control */
I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */ I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */
RSV37_IRQn, /* 0x35 0x00D4 53: Smart Card 1 */ RSV37_IRQn, /* 0x35 0x00D4 53: Smart Card 1 */
RSV38_IRQn, /* 0x36 0x00D8 54: Reserved */ RSV38_IRQn, /* 0x36 0x00D8 54: Reserved */
RSV39_IRQn, /* 0x37 0x00DC 55: Reserved */ RSV39_IRQn, /* 0x37 0x00DC 55: Reserved */
RSV40_IRQn, /* 0x38 0x00E0 56: Reserved */ RSV40_IRQn, /* 0x38 0x00E0 56: Reserved */
RSV41_IRQn, /* 0x39 0x00E4 57: Reserved */ RSV41_IRQn, /* 0x39 0x00E4 57: Reserved */
RSV42_IRQn, /* 0x3A 0x00E8 58: Reserved */ RSV42_IRQn, /* 0x3A 0x00E8 58: Reserved */
RSV43_IRQn, /* 0x3B 0x00EC 59: Reserved */ RSV43_IRQn, /* 0x3B 0x00EC 59: Reserved */
RSV44_IRQn, /* 0x3C 0x00F0 60: Reserved */ RSV44_IRQn, /* 0x3C 0x00F0 60: Reserved */
RSV45_IRQn, /* 0x3D 0x00F4 61: Reserved */ RSV45_IRQn, /* 0x3D 0x00F4 61: Reserved */
RSV46_IRQn, /* 0x3E 0x00F8 62: Reserved */ RSV46_IRQn, /* 0x3E 0x00F8 62: Reserved */
RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */ RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */
RSV48_IRQn, /* 0x40 0x0100 64: Reserved */ RSV48_IRQn, /* 0x40 0x0100 64: Reserved */
RSV49_IRQn, /* 0x41 0x0104 65: Reserved */ RSV49_IRQn, /* 0x41 0x0104 65: Reserved */
RSV50_IRQn, /* 0x42 0x0108 66: Reserved */ RSV50_IRQn, /* 0x42 0x0108 66: Reserved */
RSV51_IRQn, /* 0x43 0x010C 67: Reserved */ RSV51_IRQn, /* 0x43 0x010C 67: Reserved */
RSV52_IRQn, /* 0x44 0x0110 68: Reserved */ RSV52_IRQn, /* 0x44 0x0110 68: Reserved */
RSV53_IRQn, /* 0x45 0x0114 69: Reserved */ RSV53_IRQn, /* 0x45 0x0114 69: Reserved */
GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIOWAKE */ GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIOWAKE */
RSV55_IRQn, /* 0x47 0x011C 71: Reserved */ RSV55_IRQn, /* 0x47 0x011C 71: Reserved */
RSV56_IRQn, /* 0x48 0x0120 72: Reserved */ RSV56_IRQn, /* 0x48 0x0120 72: Reserved */
WDT1_IRQn, /* 0x49 0x0124 73: Watchdog 1 */ WDT1_IRQn, /* 0x49 0x0124 73: Watchdog 1 */
RSV57_IRQn, /* 0x4A 0x0128 74: Reserved */ RSV57_IRQn, /* 0x4A 0x0128 74: Reserved */
RSV58_IRQn, /* 0x4B 0x012C 75: Reserved */ RSV58_IRQn, /* 0x4B 0x012C 75: Reserved */
RSV59_IRQn, /* 0x4C 0x0130 76: Reserved */ RSV59_IRQn, /* 0x4C 0x0130 76: Reserved */
RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */ RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */
I2C2_IRQn, /* 0x4E 0x0138 78: I2C 2 */ I2C2_IRQn, /* 0x4E 0x0138 78: I2C 2 */
RSV63_IRQn, /* 0x4F 0x013C 79: Reserved */ RSV63_IRQn, /* 0x4F 0x013C 79: Reserved */
RSV64_IRQn, /* 0x50 0x0140 80: Reserved */ RSV64_IRQn, /* 0x50 0x0140 80: Reserved */
RSV65_IRQn, /* 0x51 0x0144 81: Reserved */ RSV65_IRQn, /* 0x51 0x0144 81: Reserved */
RSV66_IRQn, /* 0x52 0x0148 82: Reserved */ RSV66_IRQn, /* 0x52 0x0148 82: Reserved */
RSV67_IRQn, /* 0x53 0x014C 83: One Wire Master */ RSV67_IRQn, /* 0x53 0x014C 83: One Wire Master */
DMA4_IRQn, /* 0x54 0x0150 84: DMA4 */ DMA4_IRQn, /* 0x54 0x0150 84: DMA4 */
DMA5_IRQn, /* 0x55 0x0154 85: DMA5 */ DMA5_IRQn, /* 0x55 0x0154 85: DMA5 */
DMA6_IRQn, /* 0x56 0x0158 86: DMA6 */ DMA6_IRQn, /* 0x56 0x0158 86: DMA6 */
DMA7_IRQn, /* 0x57 0x015C 87: DMA7 */ DMA7_IRQn, /* 0x57 0x015C 87: DMA7 */
DMA8_IRQn, /* 0x58 0x0160 88: DMA8 */ DMA8_IRQn, /* 0x58 0x0160 88: DMA8 */
DMA9_IRQn, /* 0x59 0x0164 89: DMA9 */ DMA9_IRQn, /* 0x59 0x0164 89: DMA9 */
DMA10_IRQn, /* 0x5A 0x0168 90: DMA10 */ DMA10_IRQn, /* 0x5A 0x0168 90: DMA10 */
DMA11_IRQn, /* 0x5B 0x016C 91: DMA11 */ DMA11_IRQn, /* 0x5B 0x016C 91: DMA11 */
DMA12_IRQn, /* 0x5C 0x0170 92: DMA12 */ DMA12_IRQn, /* 0x5C 0x0170 92: DMA12 */
DMA13_IRQn, /* 0x5D 0x0174 93: DMA13 */ DMA13_IRQn, /* 0x5D 0x0174 93: DMA13 */
DMA14_IRQn, /* 0x5E 0x0178 94: DMA14 */ DMA14_IRQn, /* 0x5E 0x0178 94: DMA14 */
DMA15_IRQn, /* 0x5F 0x017C 95: DMA15 */ DMA15_IRQn, /* 0x5F 0x017C 95: DMA15 */
RSV80_IRQn, /* 0x60 0x0180 96: Reserved */ RSV80_IRQn, /* 0x60 0x0180 96: Reserved */
RSV81_IRQn, /* 0x61 0x0184 97: Reserved */ RSV81_IRQn, /* 0x61 0x0184 97: Reserved */
ECC_IRQn, /* 0x62 0x0188 98: Error Correction */ ECC_IRQn, /* 0x62 0x0188 98: Error Correction */
RSV83_IRQn, /* 0x63 0x018C 99: Reserved */ RSV83_IRQn, /* 0x63 0x018C 99: Reserved */
RSV84_IRQn, /* 0x64 0x0190 100: Reserved */ RSV84_IRQn, /* 0x64 0x0190 100: Reserved */
RSV85_IRQn, /* 0x65 0x0194 101: Reserved */ RSV85_IRQn, /* 0x65 0x0194 101: Reserved */
RSV86_IRQn, /* 0x66 0x0198 102: Reserved */ RSV86_IRQn, /* 0x66 0x0198 102: Reserved */
RSV87_IRQn, /* 0x67 0x019C 103: Reserved */ RSV87_IRQn, /* 0x67 0x019C 103: Reserved */
UART3_IRQn, /* 0x68 0x01A0 104: UART 3 */ UART3_IRQn, /* 0x68 0x01A0 104: UART 3 */
RSV89_IRQn, /* 0x69 0x01A4 105: Reserved */ RSV89_IRQn, /* 0x69 0x01A4 105: Reserved */
RSV90_IRQn, /* 0x6A 0x01A8 106: Reserved */ RSV90_IRQn, /* 0x6A 0x01A8 106: Reserved */
RSV91_IRQn, /* 0x6B 0x01AC 107: Reserved */ RSV91_IRQn, /* 0x6B 0x01AC 107: Reserved */
RSV92_IRQn, /* 0x6C 0x01B0 108: Reserved */ RSV92_IRQn, /* 0x6C 0x01B0 108: Reserved */
RSV93_IRQn, /* 0x6D 0x01B4 109: Reserved */ RSV93_IRQn, /* 0x6D 0x01B4 109: Reserved */
RSV94_IRQn, /* 0x6E 0x01B8 110: Reserved */ RSV94_IRQn, /* 0x6E 0x01B8 110: Reserved */
RSV95_IRQn, /* 0x6F 0x01BC 111: Reserved */ RSV95_IRQn, /* 0x6F 0x01BC 111: Reserved */
RSV96_IRQn, /* 0x70 0x01C0 112: Reserved */ RSV96_IRQn, /* 0x70 0x01C0 112: Reserved */
AES_IRQn, /* 0x71 0x01C4 113: AES */ AES_IRQn, /* 0x71 0x01C4 113: AES */
CRC_IRQn, /* 0x72 0x01C8 114: CRC */ CRC_IRQn, /* 0x72 0x01C8 114: CRC */
I2S_IRQn, /* 0x73 0x01CC 115: I2S */ I2S_IRQn, /* 0x73 0x01CC 115: I2S */
MXC_IRQ_EXT_COUNT, MXC_IRQ_EXT_COUNT,
} IRQn_Type; } IRQn_Type;
#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
/* ================================================================================ */ /* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */ /* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */ /* ================================================================================ */
/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ #define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */
#define __MPU_PRESENT 1 /*!< MPU present or not */ #define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present or not */ #define __FPU_PRESENT 1 /*!< FPU present or not */
#include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
#include "system_max32670.h" /*!< System Header */
#include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
#include "system_max32670.h" /*!< System Header */
/* ================================================================================ */ /* ================================================================================ */
/* ================== Device Specific Memory Section ================== */ /* ================== Device Specific Memory Section ================== */
/* ================================================================================ */ /* ================================================================================ */
#define MXC_ROM_MEM_BASE 0x00000000UL #define MXC_ROM_MEM_BASE 0x00000000UL
#define MXC_ROM_MEM_SIZE 0x00020000UL #define MXC_ROM_MEM_SIZE 0x00020000UL
#define MXC_XIP_MEM_BASE 0x08000000UL #define MXC_XIP_MEM_BASE 0x08000000UL
#define MXC_XIP_MEM_SIZE 0x08000000UL #define MXC_XIP_MEM_SIZE 0x08000000UL
#define MXC_FLASH0_MEM_BASE 0x10000000UL #define MXC_FLASH0_MEM_BASE 0x10000000UL
#define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE #define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE
#define MXC_FLASH_PAGE_SIZE 0x00002000UL #define MXC_FLASH_PAGE_SIZE 0x00002000UL
#define MXC_FLASH_MEM_SIZE (0x00060000UL - MXC_FLASH_PAGE_SIZE) #define MXC_FLASH_MEM_SIZE (0x00060000UL - MXC_FLASH_PAGE_SIZE)
#define MXC_INFO0_MEM_BASE 0x10800000UL #define MXC_INFO0_MEM_BASE 0x10800000UL
#define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE #define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE
#define MXC_INFO_MEM_SIZE 0x00004000UL #define MXC_INFO_MEM_SIZE 0x00004000UL
#define MXC_SRAM_MEM_BASE 0x20000000UL #define MXC_SRAM_MEM_BASE 0x20000000UL
#define MXC_SRAM_MEM_SIZE 0x00028000UL #define MXC_SRAM_MEM_SIZE 0x00028000UL
#define MXC_XIP_DATA_MEM_BASE 0x80000000UL #define MXC_XIP_DATA_MEM_BASE 0x80000000UL
#define MXC_XIP_DATA_MEM_SIZE 0x20000000UL #define MXC_XIP_DATA_MEM_SIZE 0x20000000UL
/* ================================================================================ */ /* ================================================================================ */
/* ================ Device Specific Peripheral Section ================ */ /* ================ Device Specific Peripheral Section ================ */
@ -229,353 +227,331 @@ typedef enum {
/******************************************************************************/ /******************************************************************************/
/* Global control */ /* Global control */
#define MXC_BASE_GCR ((uint32_t)0x40000000UL) #define MXC_BASE_GCR ((uint32_t)0x40000000UL)
#define MXC_GCR ((mxc_gcr_regs_t*)MXC_BASE_GCR) #define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR)
/******************************************************************************/ /******************************************************************************/
/* Non-battery backed SI Registers */ /* Non-battery backed SI Registers */
#define MXC_BASE_SIR ((uint32_t)0x40000400UL) #define MXC_BASE_SIR ((uint32_t)0x40000400UL)
#define MXC_SIR ((mxc_sir_regs_t*)MXC_BASE_SIR) #define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR)
/******************************************************************************/ /******************************************************************************/
/* Non-battery backed Function Control */ /* Non-battery backed Function Control */
#define MXC_BASE_FCR ((uint32_t)0x40000800UL) #define MXC_BASE_FCR ((uint32_t)0x40000800UL)
#define MXC_FCR ((mxc_fcr_regs_t*)MXC_BASE_FCR) #define MXC_FCR ((mxc_fcr_regs_t *)MXC_BASE_FCR)
/******************************************************************************/
/* Trim System Initalization Register */
#define MXC_BASE_TRIMSIR ((uint32_t)0x40005400UL)
#define MXC_TRIMSIR ((mxc_trimsir_regs_t*)MXC_BASE_TRIMSIR)
/******************************************************************************/
/* Watchdog */
#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
#define MXC_WDT0 ((mxc_wdt_regs_t*)MXC_BASE_WDT0)
#define MXC_BASE_WDT1 ((uint32_t)0x40003400UL)
#define MXC_WDT1 ((mxc_wdt_regs_t*)MXC_BASE_WDT1)
/******************************************************************************/
/* Real Time Clock */
#define MXC_BASE_RTC ((uint32_t)0x40106000UL)
#define MXC_RTC ((mxc_rtc_regs_t*)MXC_BASE_RTC)
/******************************************************************************/
/* Power Sequencer */
#define MXC_BASE_PWRSEQ ((uint32_t)0x40106800UL)
#define MXC_PWRSEQ ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ)
/******************************************************************************/
/* MISC Control */
#define MXC_BASE_MCR ((uint32_t)0x40106C00UL)
#define MXC_MCR ((mxc_mcr_regs_t*)MXC_BASE_MCR)
/******************************************************************************/
/* Error Correcting Code */
#define MXC_BASE_ECC ((uint32_t)0x40105400UL)
#define MXC_ECC ((mxc_ecc_regs_t*)MXC_BASE_ECC)
/******************************************************************************/
/* GPIO */
#define MXC_CFG_GPIO_INSTANCES (2)
#define MXC_CFG_GPIO_PINS_PORT (32)
#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
#define MXC_GPIO0 ((mxc_gpio_regs_t*)MXC_BASE_GPIO0)
#define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL)
#define MXC_GPIO1 ((mxc_gpio_regs_t*)MXC_BASE_GPIO1)
#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : \
(p) == MXC_GPIO1 ? 1 : -1)
#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : \
(i) == 1 ? MXC_GPIO1 : 0)
#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : \
(i) == 1 ? GPIO1_IRQn : 0)
/******************************************************************************/
#define SEC(s) (((unsigned long)s) * 1000000UL)
#define MSEC(ms) (ms * 1000UL)
#define USEC(us) (us)
/* Timer */
#define MXC_CFG_TMR_INSTANCES (6)
#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
#define MXC_TMR0 ((mxc_tmr_regs_t*)MXC_BASE_TMR0)
#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
#define MXC_TMR1 ((mxc_tmr_regs_t*)MXC_BASE_TMR1)
#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
#define MXC_TMR2 ((mxc_tmr_regs_t*)MXC_BASE_TMR2)
#define MXC_BASE_TMR3 ((uint32_t)0x40013000UL)
#define MXC_TMR3 ((mxc_tmr_regs_t*)MXC_BASE_TMR3)
#define MXC_BASE_TMR4 ((uint32_t)0x40114000UL)
#define MXC_TMR4 ((mxc_tmr_regs_t*)MXC_BASE_TMR4)
#define MXC_BASE_TMR5 ((uint32_t)0x40115000UL)
#define MXC_TMR5 ((mxc_tmr_regs_t*)MXC_BASE_TMR5)
#define MXC_TMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? TMR0_IRQn : \
(i) == 1 ? TMR1_IRQn : \
(i) == 2 ? TMR2_IRQn : \
(i) == 3 ? TMR3_IRQn : \
(i) == 4 ? TMR4_IRQn : \
(i) == 5 ? TMR5_IRQn : 0)
#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
(i) == 1 ? MXC_BASE_TMR1 : \
(i) == 2 ? MXC_BASE_TMR2 : \
(i) == 3 ? MXC_BASE_TMR3 : \
(i) == 4 ? MXC_BASE_TMR4 : \
(i) == 5 ? MXC_BASE_TMR5 : 0)
#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
(i) == 1 ? MXC_TMR1 : \
(i) == 2 ? MXC_TMR2 : \
(i) == 3 ? MXC_TMR3 : \
(i) == 4 ? MXC_TMR4 : \
(i) == 5 ? MXC_TMR5 : 0)
#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
(p) == MXC_TMR1 ? 1 : \
(p) == MXC_TMR2 ? 2 : \
(p) == MXC_TMR3 ? 3 : \
(p) == MXC_TMR4 ? 4 : \
(p) == MXC_TMR5 ? 5 : -1)
/******************************************************************************/
/* I2C */
#define MXC_I2C_INSTANCES (3)
#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL)
#define MXC_I2C0 ((mxc_i2c_regs_t*)MXC_BASE_I2C0)
#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL)
#define MXC_I2C1 ((mxc_i2c_regs_t*)MXC_BASE_I2C1)
#define MXC_BASE_I2C2 ((uint32_t)0x4001F000UL)
#define MXC_I2C2 ((mxc_i2c_regs_t*)MXC_BASE_I2C2)
#define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : \
(i) == 1 ? I2C1_IRQn : \
(i) == 2 ? I2C2_IRQn : 0)
#define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : \
(i) == 1 ? MXC_BASE_I2C1 : \
(i) == 2 ? MXC_BASE_I2C2 : 0)
#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : \
(i) == 1 ? MXC_I2C1 : \
(i) == 2 ? MXC_I2C2 : 0)
#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : \
(p) == MXC_I2C1 ? 1 : \
(p) == MXC_I2C2 ? 2 : -1)
#define MXC_I2C_FIFO_DEPTH (8)
/******************************************************************************/
/* DMA */
#define MXC_DMA_CHANNELS (8)
#define MXC_DMA_INSTANCES (1)
#define MXC_BASE_DMA ((uint32_t)0x40028000UL)
#define MXC_DMA ((mxc_dma_regs_t*)MXC_BASE_DMA)
#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1)
/******************************************************************************/
/* FLC */
#define MXC_FLC_INSTANCES (1)
#define MXC_BASE_FLC0 ((uint32_t)0x40029000UL)
#define MXC_FLC0 ((mxc_flc_regs_t*)MXC_BASE_FLC0)
#define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : 0)
#define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : 0)
#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : 0)
#define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : -1)
/******************************************************************************/
/* Instruction Cache */
#define MXC_BASE_ICC ((uint32_t)0x4002A000UL)
#define MXC_ICC ((mxc_icc_regs_t*)MXC_BASE_ICC)
/******************************************************************************/
/* Data Cache */
#define MXC_BASE_EMCC ((uint32_t)0x40033000UL)
#define MXC_EMCC ((mxc_emcc_regs_t*)MXC_BASE_EMCC)
/******************************************************************************/
/* XXX Actually reserved! */
#define MXC_BASE_RESERVED ((uint32_t)0x40035000UL)
/******************************************************************************/
/* One Wire Master */
#define MXC_BASE_OWM ((uint32_t)0x4003D000UL)
#define MXC_OWM ((mxc_owm_regs_t*)MXC_BASE_OWM)
/******************************************************************************/
/* UART / Serial Port Interface */
#define MXC_UART_INSTANCES (4)
#define MXC_UART_FIFO_DEPTH (8)
#define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
#define MXC_UART0 ((mxc_uart_regs_t*)MXC_BASE_UART0)
#define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
#define MXC_UART1 ((mxc_uart_regs_t*)MXC_BASE_UART1)
#define MXC_BASE_UART2 ((uint32_t)0x40044000UL)
#define MXC_UART2 ((mxc_uart_regs_t*)MXC_BASE_UART2)
#define MXC_BASE_UART3 ((uint32_t)0x40145000UL)
#define MXC_UART3 ((mxc_uart_regs_t*)MXC_BASE_UART3)
#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
(i) == 1 ? UART1_IRQn : \
(i) == 2 ? UART2_IRQn : \
(i) == 3 ? UART3_IRQn : 0)
#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
(i) == 1 ? MXC_BASE_UART1 : \
(i) == 2 ? MXC_BASE_UART2 : \
(i) == 3 ? MXC_BASE_UART3 : 0)
#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
(i) == 1 ? MXC_UART1 : \
(i) == 2 ? MXC_UART2 : \
(i) == 3 ? MXC_UART3 : 0)
#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
(p) == MXC_UART1 ? 1 : \
(p) == MXC_UART2 ? 2 : \
(p) == MXC_UART3 ? 3 : -1)
/******************************************************************************/
/* SPI */
#define MXC_SPI_INSTANCES (3)
#define MXC_SPI_SS_INSTANCES (4)
#define MXC_SPI_FIFO_DEPTH (32)
#define MXC_BASE_SPI0 ((uint32_t)0x40046000UL)
#define MXC_SPI0 ((mxc_spi_regs_t*)MXC_BASE_SPI0)
#define MXC_BASE_SPI1 ((uint32_t)0x40047000UL)
#define MXC_SPI1 ((mxc_spi_regs_t*)MXC_BASE_SPI1)
#define MXC_BASE_SPI2 ((uint32_t)0x40048000UL)
#define MXC_SPI2 ((mxc_spi_regs_t*)MXC_BASE_SPI2)
#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : \
(p) == MXC_SPI1 ? 1 : \
(p) == MXC_SPI2 ? 2 : -1)
#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : \
(i) == 1 ? MXC_BASE_SPI1 : \
(i) == 2 ? MXC_BASE_SPI2 : 0)
#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : \
(i) == 1 ? MXC_SPI1 : \
(i) == 2 ? MXC_SPI2 : 0)
#define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI0_IRQn : \
(i) == 1 ? SPI1_IRQn : \
(i) == 2 ? SPI2_IRQn : 0)
/******************************************************************************/
/* TRNG */
#define MXC_BASE_TRNG ((uint32_t)0x4004D000UL)
#define MXC_TRNG ((mxc_trng_regs_t*)MXC_BASE_TRNG)
/******************************************************************************/
/* AES */
#define MXC_BASE_AES ((uint32_t)0x40007400UL)
#define MXC_AES ((mxc_aes_regs_t*)MXC_BASE_AES)
/******************************************************************************/ /******************************************************************************/
/* AES Keys */ /* AES Keys */
#define MXC_BASE_AESKEY ((uint32_t)0x40005000UL) #define MXC_BASE_AESKEYS ((uint32_t)0x40005000UL)
#define MXC_AESKEY ((mxc_aes_key_regs_t*)MXC_BASE_AESKEY) #define MXC_AESKEYS ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS)
// DEPRECATED(1-10-2023): Scheduled for removal.
#define MXC_BASE_AESKEY MXC_BASE_AESKEYS
#define MXC_AESKEY ((mxc_aes_key_regs_t *)MXC_BASE_AESKEY)
/******************************************************************************/
/* Error Correcting Code */
/* ECC registers is a subset of TRIMSIR registers */
#define MXC_BASE_ECC ((uint32_t)0x40105400UL)
#define MXC_ECC ((mxc_ecc_regs_t *)MXC_BASE_ECC)
/******************************************************************************/
/* Trim System Initalization Register */
#define MXC_BASE_TRIMSIR ((uint32_t)0x400105400UL)
#define MXC_TRIMSIR ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR)
/******************************************************************************/
/* Watchdog */
#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
#define MXC_BASE_WDT1 ((uint32_t)0x40003400UL)
#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
/******************************************************************************/
/* Real Time Clock */
#define MXC_BASE_RTC ((uint32_t)0x40106000UL)
#define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC)
/******************************************************************************/
/* Power Sequencer */
#define MXC_BASE_PWRSEQ ((uint32_t)0x40106800UL)
#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
/******************************************************************************/
/* MISC Control */
#define MXC_BASE_MCR ((uint32_t)0x40106C00UL)
#define MXC_MCR ((mxc_mcr_regs_t *)MXC_BASE_MCR)
/******************************************************************************/
/* AES */
#define MXC_BASE_AES ((uint32_t)0x40007400UL)
#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
/******************************************************************************/
/* GPIO */
#define MXC_CFG_GPIO_INSTANCES (2)
#define MXC_CFG_GPIO_PINS_PORT (32)
#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
#define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0)
#define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL)
#define MXC_GPIO1 ((mxc_gpio_regs_t *)MXC_BASE_GPIO1)
#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : (p) == MXC_GPIO1 ? 1 : -1)
#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : (i) == 1 ? MXC_GPIO1 : 0)
#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : (i) == 1 ? GPIO1_IRQn : 0)
/******************************************************************************/ /******************************************************************************/
/* CRC */ /* CRC */
#define MXC_BASE_CRC ((uint32_t)0x4000F000UL) #define MXC_BASE_CRC ((uint32_t)0x4000F000UL)
#define MXC_CRC ((mxc_crc_regs_t*)MXC_BASE_CRC) #define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC)
/******************************************************************************/ /******************************************************************************/
#define MXC_BASE_I2S ((uint32_t)0x40060000UL) /* Timer */
#define MXC_I2S ((mxc_i2s_regs_t*)MXC_BASE_I2S) #define SEC(s) (((uint32_t)s) * 1000000UL)
#define MSEC(ms) (ms * 1000UL)
#define USEC(us) (us)
#define MXC_CFG_TMR_INSTANCES (6)
#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0)
#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1)
#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
#define MXC_BASE_TMR3 ((uint32_t)0x40013000UL)
#define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3)
#define MXC_BASE_TMR4 ((uint32_t)0x40114000UL)
#define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4)
#define MXC_BASE_TMR5 ((uint32_t)0x40115000UL)
#define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5)
#define MXC_TMR_GET_IRQ(i) \
(IRQn_Type)((i) == 0 ? TMR0_IRQn : \
(i) == 1 ? TMR1_IRQn : \
(i) == 2 ? TMR2_IRQn : \
(i) == 3 ? TMR3_IRQn : \
(i) == 4 ? TMR4_IRQn : \
(i) == 5 ? TMR5_IRQn : \
0)
#define MXC_TMR_GET_BASE(i) \
((i) == 0 ? MXC_BASE_TMR0 : \
(i) == 1 ? MXC_BASE_TMR1 : \
(i) == 2 ? MXC_BASE_TMR2 : \
(i) == 3 ? MXC_BASE_TMR3 : \
(i) == 4 ? MXC_BASE_TMR4 : \
(i) == 5 ? MXC_BASE_TMR5 : \
0)
#define MXC_TMR_GET_TMR(i) \
((i) == 0 ? MXC_TMR0 : \
(i) == 1 ? MXC_TMR1 : \
(i) == 2 ? MXC_TMR2 : \
(i) == 3 ? MXC_TMR3 : \
(i) == 4 ? MXC_TMR4 : \
(i) == 5 ? MXC_TMR5 : \
0)
#define MXC_TMR_GET_IDX(p) \
((p) == MXC_TMR0 ? 0 : \
(p) == MXC_TMR1 ? 1 : \
(p) == MXC_TMR2 ? 2 : \
(p) == MXC_TMR3 ? 3 : \
(p) == MXC_TMR4 ? 4 : \
(p) == MXC_TMR5 ? 5 : \
-1)
/******************************************************************************/ /******************************************************************************/
/* BBFC */ /* I2C */
#define MXC_BASE_BBFC ((uint32_t)0x40005800UL) #define MXC_I2C_INSTANCES (3)
#define MXC_BBFC ((mxc_bbfc_regs_t*)MXC_BASE_BBFC) #define MXC_I2C_FIFO_DEPTH (8)
#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL)
#define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0)
#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL)
#define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1)
#define MXC_BASE_I2C2 ((uint32_t)0x4001F000UL)
#define MXC_I2C2 ((mxc_i2c_regs_t *)MXC_BASE_I2C2)
#define MXC_I2C_GET_IRQ(i) \
(IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : (i) == 2 ? I2C2_IRQn : 0)
#define MXC_I2C_GET_BASE(i) \
((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : (i) == 2 ? MXC_BASE_I2C2 : 0)
#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : (i) == 2 ? MXC_I2C2 : 0)
#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : (p) == MXC_I2C2 ? 2 : -1)
/******************************************************************************/
/* DMA */
#define MXC_DMA_CHANNELS (8)
#define MXC_DMA_INSTANCES (1)
#define MXC_BASE_DMA ((uint32_t)0x40028000UL)
#define MXC_DMA ((mxc_dma_regs_t *)MXC_BASE_DMA)
#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1)
/******************************************************************************/
/* FLC */
#define MXC_FLC_INSTANCES (1)
#define MXC_BASE_FLC0 ((uint32_t)0x40029000UL)
#define MXC_FLC0 ((mxc_flc_regs_t *)MXC_BASE_FLC0)
#define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : 0)
#define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : 0)
#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : 0)
#define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : -1)
/******************************************************************************/
/* Instruction Cache */
#define MXC_BASE_ICC ((uint32_t)0x4002A000UL)
#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
/******************************************************************************/
/* Data Cache */
#define MXC_BASE_EMCC ((uint32_t)0x40033000UL)
#define MXC_EMCC ((mxc_emcc_regs_t *)MXC_BASE_EMCC)
/******************************************************************************/
/* XXX Actually reserved! */
#define MXC_BASE_RESERVED ((uint32_t)0x40035000UL)
/******************************************************************************/
/* One Wire Master */
#define MXC_BASE_OWM ((uint32_t)0x4003D000UL)
#define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM)
/******************************************************************************/
/* UART / Serial Port Interface */
#define MXC_UART_INSTANCES (4)
#define MXC_UART_FIFO_DEPTH (8)
#define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
#define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
#define MXC_BASE_UART2 ((uint32_t)0x40044000UL)
#define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2)
#define MXC_BASE_UART3 ((uint32_t)0x40145000UL)
#define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3)
#define MXC_UART_GET_IRQ(i) \
(IRQn_Type)((i) == 0 ? UART0_IRQn : \
(i) == 1 ? UART1_IRQn : \
(i) == 2 ? UART2_IRQn : \
(i) == 3 ? UART3_IRQn : \
0)
#define MXC_UART_GET_BASE(i) \
((i) == 0 ? MXC_BASE_UART0 : \
(i) == 1 ? MXC_BASE_UART1 : \
(i) == 2 ? MXC_BASE_UART2 : \
(i) == 3 ? MXC_BASE_UART3 : \
0)
#define MXC_UART_GET_UART(i) \
((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : (i) == 2 ? MXC_UART2 : (i) == 3 ? MXC_UART3 : 0)
#define MXC_UART_GET_IDX(p) \
((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : (p) == MXC_UART2 ? 2 : (p) == MXC_UART3 ? 3 : -1)
/******************************************************************************/
/* SPI */
#define MXC_SPI_INSTANCES (3)
#define MXC_SPI_SS_INSTANCES (4)
#define MXC_SPI_FIFO_DEPTH (32)
#define MXC_BASE_SPI0 ((uint32_t)0x40046000UL)
#define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0)
#define MXC_BASE_SPI1 ((uint32_t)0x40047000UL)
#define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1)
#define MXC_BASE_SPI2 ((uint32_t)0x40048000UL)
#define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2)
#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : (p) == MXC_SPI1 ? 1 : (p) == MXC_SPI2 ? 2 : -1)
#define MXC_SPI_GET_BASE(i) \
((i) == 0 ? MXC_BASE_SPI0 : (i) == 1 ? MXC_BASE_SPI1 : (i) == 2 ? MXC_BASE_SPI2 : 0)
#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : (i) == 1 ? MXC_SPI1 : (i) == 2 ? MXC_SPI2 : 0)
#define MXC_SPI_GET_IRQ(i) \
(IRQn_Type)((i) == 0 ? SPI0_IRQn : (i) == 1 ? SPI1_IRQn : (i) == 2 ? SPI2_IRQn : 0)
/******************************************************************************/
/* TRNG */
#define MXC_BASE_TRNG ((uint32_t)0x4004D000UL)
#define MXC_TRNG ((mxc_trng_regs_t *)MXC_BASE_TRNG)
/******************************************************************************/
#define MXC_BASE_I2S ((uint32_t)0x40060000UL)
#define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S)
/******************************************************************************/ /******************************************************************************/
/* Bit Shifting */ /* Bit Shifting */
#define MXC_F_BIT_0 (1 << 0)
#define MXC_F_BIT_0 (1 << 0) #define MXC_F_BIT_1 (1 << 1)
#define MXC_F_BIT_1 (1 << 1) #define MXC_F_BIT_2 (1 << 2)
#define MXC_F_BIT_2 (1 << 2) #define MXC_F_BIT_3 (1 << 3)
#define MXC_F_BIT_3 (1 << 3) #define MXC_F_BIT_4 (1 << 4)
#define MXC_F_BIT_4 (1 << 4) #define MXC_F_BIT_5 (1 << 5)
#define MXC_F_BIT_5 (1 << 5) #define MXC_F_BIT_6 (1 << 6)
#define MXC_F_BIT_6 (1 << 6) #define MXC_F_BIT_7 (1 << 7)
#define MXC_F_BIT_7 (1 << 7) #define MXC_F_BIT_8 (1 << 8)
#define MXC_F_BIT_8 (1 << 8) #define MXC_F_BIT_9 (1 << 9)
#define MXC_F_BIT_9 (1 << 9) #define MXC_F_BIT_10 (1 << 10)
#define MXC_F_BIT_10 (1 << 10) #define MXC_F_BIT_11 (1 << 11)
#define MXC_F_BIT_11 (1 << 11) #define MXC_F_BIT_12 (1 << 12)
#define MXC_F_BIT_12 (1 << 12) #define MXC_F_BIT_13 (1 << 13)
#define MXC_F_BIT_13 (1 << 13) #define MXC_F_BIT_14 (1 << 14)
#define MXC_F_BIT_14 (1 << 14) #define MXC_F_BIT_15 (1 << 15)
#define MXC_F_BIT_15 (1 << 15) #define MXC_F_BIT_16 (1 << 16)
#define MXC_F_BIT_16 (1 << 16) #define MXC_F_BIT_17 (1 << 17)
#define MXC_F_BIT_17 (1 << 17) #define MXC_F_BIT_18 (1 << 18)
#define MXC_F_BIT_18 (1 << 18) #define MXC_F_BIT_19 (1 << 19)
#define MXC_F_BIT_19 (1 << 19) #define MXC_F_BIT_20 (1 << 20)
#define MXC_F_BIT_20 (1 << 20) #define MXC_F_BIT_21 (1 << 21)
#define MXC_F_BIT_21 (1 << 21) #define MXC_F_BIT_22 (1 << 22)
#define MXC_F_BIT_22 (1 << 22) #define MXC_F_BIT_23 (1 << 23)
#define MXC_F_BIT_23 (1 << 23) #define MXC_F_BIT_24 (1 << 24)
#define MXC_F_BIT_24 (1 << 24) #define MXC_F_BIT_25 (1 << 25)
#define MXC_F_BIT_25 (1 << 25) #define MXC_F_BIT_26 (1 << 26)
#define MXC_F_BIT_26 (1 << 26) #define MXC_F_BIT_27 (1 << 27)
#define MXC_F_BIT_27 (1 << 27) #define MXC_F_BIT_28 (1 << 28)
#define MXC_F_BIT_28 (1 << 28) #define MXC_F_BIT_29 (1 << 29)
#define MXC_F_BIT_29 (1 << 29) #define MXC_F_BIT_30 (1 << 30)
#define MXC_F_BIT_30 (1 << 30) #define MXC_F_BIT_31 (1 << 31)
#define MXC_F_BIT_31 (1 << 31)
/******************************************************************************/ /******************************************************************************/
/* Bit Banding */ /* Bit Banding */
#define BITBAND(reg, bit) \
((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \
((bit) << 2))
#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \ #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
(((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2)) #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) #define MXC_SETFIELD(reg, mask, setting) (reg = ((reg) & ~(mask)) | ((setting) & (mask)))
#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
#define MXC_SETFIELD(reg, mask, setting) (reg = (reg & ~mask) | (setting & mask))
/******************************************************************************/ /******************************************************************************/
/* SCB CPACR */ /* SCB CPACR */
/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ #define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */
#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */
#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ #define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */
#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */
#endif /* _MAX32670_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MAX32670_H_

90
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/mcr_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file mcr_regs.h * @file mcr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _MCR_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MCR_REGS_H_
#define _MCR_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MCR_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup mcr * @ingroup mcr
* @defgroup mcr_registers MCR_Registers * @defgroup mcr_registers MCR_Registers
* @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module.
* @details Misc Control. * @details Miscellaneous Control Registers.
*/ */
/** /**
@ -85,7 +85,9 @@ extern "C" {
typedef struct { typedef struct {
__I uint32_t rsv_0x0; __I uint32_t rsv_0x0;
__IO uint32_t rst; /**< <tt>\b 0x04:</tt> MCR RST Register */ __IO uint32_t rst; /**< <tt>\b 0x04:</tt> MCR RST Register */
__I uint32_t rsv_0x8_0x23[7]; __I uint32_t rsv_0x8_0xf[2];
__IO uint32_t lppioctrl; /**< <tt>\b 0x10:</tt> MCR LPPIOCTRL Register */
__I uint32_t rsv_0x14_0x23[4];
__IO uint32_t clkdis; /**< <tt>\b 0x24:</tt> MCR CLKDIS Register */ __IO uint32_t clkdis; /**< <tt>\b 0x24:</tt> MCR CLKDIS Register */
} mxc_mcr_regs_t; } mxc_mcr_regs_t;
@ -96,41 +98,77 @@ typedef struct {
* @brief MCR Peripheral Register Offsets from the MCR Base Peripheral Address. * @brief MCR Peripheral Register Offsets from the MCR Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_MCR_RST ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: <tt> 0x0004</tt> */ #define MXC_R_MCR_RST ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: <tt> 0x0004</tt> */
#define MXC_R_MCR_CLKDIS ((uint32_t)0x00000024UL) /**< Offset from MCR Base Address: <tt> 0x0024</tt> */ #define MXC_R_MCR_LPPIOCTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: <tt> 0x0010</tt> */
#define MXC_R_MCR_CLKDIS ((uint32_t)0x00000024UL) /**< Offset from MCR Base Address: <tt> 0x0024</tt> */
/**@} end of group mcr_registers */ /**@} end of group mcr_registers */
/** /**
* @ingroup mcr_registers * @ingroup mcr_registers
* @defgroup MCR_RST MCR_RST * @defgroup MCR_RST MCR_RST
* @brief Reset Control Register * @brief Reset control register 0.
* @{ * @{
*/ */
#define MXC_F_MCR_RST_LPTMR0_POS 0 /**< RST_LPTMR0 Position */ #define MXC_F_MCR_RST_LPTMR0_POS 0 /**< RST_LPTMR0 Position */
#define MXC_F_MCR_RST_LPTMR0 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPTMR0_POS)) /**< RST_LPTMR0 Mask */ #define MXC_F_MCR_RST_LPTMR0 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPTMR0_POS)) /**< RST_LPTMR0 Mask */
#define MXC_F_MCR_RST_LPTMR1_POS 1 /**< RST_LPTMR1 Position */ #define MXC_F_MCR_RST_LPTMR1_POS 1 /**< RST_LPTMR1 Position */
#define MXC_F_MCR_RST_LPTMR1 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPTMR1_POS)) /**< RST_LPTMR1 Mask */ #define MXC_F_MCR_RST_LPTMR1 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPTMR1_POS)) /**< RST_LPTMR1 Mask */
#define MXC_F_MCR_RST_LPUART0_POS 2 /**< RST_LPUART0 Position */ #define MXC_F_MCR_RST_LPUART0_POS 2 /**< RST_LPUART0 Position */
#define MXC_F_MCR_RST_LPUART0 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPUART0_POS)) /**< RST_LPUART0 Mask */ #define MXC_F_MCR_RST_LPUART0 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPUART0_POS)) /**< RST_LPUART0 Mask */
#define MXC_F_MCR_RST_RTC_POS 3 /**< RST_RTC Position */
#define MXC_F_MCR_RST_RTC ((uint32_t)(0x1UL << MXC_F_MCR_RST_RTC_POS)) /**< RST_RTC Mask */
/**@} end of group MCR_RST_Register */ /**@} end of group MCR_RST_Register */
/** /**
* @ingroup mcr_registers * @ingroup mcr_registers
* @defgroup MCR_CLKDIS MCR_CLKDIS * @defgroup MCR_LPPIOCTRL MCR_LPPIOCTRL
* @brief Low Power Peripheral Clock Disable. * @brief Low-power peripheral IO control.
* @{ * @{
*/ */
#define MXC_F_MCR_CLKDIS_LPTMR0_POS 0 /**< CLKDIS_LPTMR0 Position */ #define MXC_F_MCR_LPPIOCTRL_LPTMR0_I_POS 0 /**< LPPIOCTRL_LPTMR0_I Position */
#define MXC_F_MCR_CLKDIS_LPTMR0 ((uint32_t)(0x1UL << MXC_F_MCR_CLKDIS_LPTMR0_POS)) /**< CLKDIS_LPTMR0 Mask */ #define MXC_F_MCR_LPPIOCTRL_LPTMR0_I ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR0_I_POS)) /**< LPPIOCTRL_LPTMR0_I Mask */
#define MXC_F_MCR_CLKDIS_LPTMR1_POS 1 /**< CLKDIS_LPTMR1 Position */ #define MXC_F_MCR_LPPIOCTRL_LPTMR0_O_POS 1 /**< LPPIOCTRL_LPTMR0_O Position */
#define MXC_F_MCR_CLKDIS_LPTMR1 ((uint32_t)(0x1UL << MXC_F_MCR_CLKDIS_LPTMR1_POS)) /**< CLKDIS_LPTMR1 Mask */ #define MXC_F_MCR_LPPIOCTRL_LPTMR0_O ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR0_O_POS)) /**< LPPIOCTRL_LPTMR0_O Mask */
#define MXC_F_MCR_CLKDIS_LPUART0_POS 2 /**< CLKDIS_LPUART0 Position */ #define MXC_F_MCR_LPPIOCTRL_LPTMR1_I_POS 2 /**< LPPIOCTRL_LPTMR1_I Position */
#define MXC_F_MCR_CLKDIS_LPUART0 ((uint32_t)(0x1UL << MXC_F_MCR_CLKDIS_LPUART0_POS)) /**< CLKDIS_LPUART0 Mask */ #define MXC_F_MCR_LPPIOCTRL_LPTMR1_I ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR1_I_POS)) /**< LPPIOCTRL_LPTMR1_I Mask */
#define MXC_F_MCR_LPPIOCTRL_LPTMR1_O_POS 3 /**< LPPIOCTRL_LPTMR1_O Position */
#define MXC_F_MCR_LPPIOCTRL_LPTMR1_O ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR1_O_POS)) /**< LPPIOCTRL_LPTMR1_O Mask */
#define MXC_F_MCR_LPPIOCTRL_LPUART0_RX_POS 4 /**< LPPIOCTRL_LPUART0_RX Position */
#define MXC_F_MCR_LPPIOCTRL_LPUART0_RX ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_RX_POS)) /**< LPPIOCTRL_LPUART0_RX Mask */
#define MXC_F_MCR_LPPIOCTRL_LPUART0_TX_POS 5 /**< LPPIOCTRL_LPUART0_TX Position */
#define MXC_F_MCR_LPPIOCTRL_LPUART0_TX ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_TX_POS)) /**< LPPIOCTRL_LPUART0_TX Mask */
#define MXC_F_MCR_LPPIOCTRL_LPUART0_CTS_POS 6 /**< LPPIOCTRL_LPUART0_CTS Position */
#define MXC_F_MCR_LPPIOCTRL_LPUART0_CTS ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_CTS_POS)) /**< LPPIOCTRL_LPUART0_CTS Mask */
#define MXC_F_MCR_LPPIOCTRL_LPUART0_RTS_POS 7 /**< LPPIOCTRL_LPUART0_RTS Position */
#define MXC_F_MCR_LPPIOCTRL_LPUART0_RTS ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_RTS_POS)) /**< LPPIOCTRL_LPUART0_RTS Mask */
/**@} end of group MCR_LPPIOCTRL_Register */
/**
* @ingroup mcr_registers
* @defgroup MCR_CLKDIS MCR_CLKDIS
* @brief Peripheral clock control register.
* @{
*/
#define MXC_F_MCR_CLKDIS_LPTMR0_POS 0 /**< CLKDIS_LPTMR0 Position */
#define MXC_F_MCR_CLKDIS_LPTMR0 ((uint32_t)(0x1UL << MXC_F_MCR_CLKDIS_LPTMR0_POS)) /**< CLKDIS_LPTMR0 Mask */
#define MXC_F_MCR_CLKDIS_LPTMR1_POS 1 /**< CLKDIS_LPTMR1 Position */
#define MXC_F_MCR_CLKDIS_LPTMR1 ((uint32_t)(0x1UL << MXC_F_MCR_CLKDIS_LPTMR1_POS)) /**< CLKDIS_LPTMR1 Mask */
#define MXC_F_MCR_CLKDIS_LPUART0_POS 2 /**< CLKDIS_LPUART0 Position */
#define MXC_F_MCR_CLKDIS_LPUART0 ((uint32_t)(0x1UL << MXC_F_MCR_CLKDIS_LPUART0_POS)) /**< CLKDIS_LPUART0 Mask */
/**@} end of group MCR_CLKDIS_Register */ /**@} end of group MCR_CLKDIS_Register */
@ -138,4 +176,4 @@ typedef struct {
} }
#endif #endif
#endif /* _MCR_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MCR_REGS_H_

176
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/pwrseq_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file pwrseq_regs.h * @file pwrseq_regs.h
* @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _PWRSEQ_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_PWRSEQ_REGS_H_
#define _PWRSEQ_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_PWRSEQ_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup pwrseq * @ingroup pwrseq
* @defgroup pwrseq_registers PWRSEQ_Registers * @defgroup pwrseq_registers PWRSEQ_Registers
* @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module.
* @details Power Sequencer / Low Power Control Register. * @details Power Sequencer / Low Power Control Register.
*/ */
/** /**
@ -93,6 +93,9 @@ typedef struct {
__IO uint32_t lppwken; /**< <tt>\b 0x34:</tt> PWRSEQ LPPWKEN Register */ __IO uint32_t lppwken; /**< <tt>\b 0x34:</tt> PWRSEQ LPPWKEN Register */
__I uint32_t rsv_0x38_0x3f[2]; __I uint32_t rsv_0x38_0x3f[2];
__IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */ __IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
__I uint32_t rsv_0x44;
__IO uint32_t gp0; /**< <tt>\b 0x48:</tt> PWRSEQ GP0 Register */
__IO uint32_t gp1; /**< <tt>\b 0x4C:</tt> PWRSEQ GP1 Register */
} mxc_pwrseq_regs_t; } mxc_pwrseq_regs_t;
/* Register offsets for module PWRSEQ */ /* Register offsets for module PWRSEQ */
@ -102,14 +105,16 @@ typedef struct {
* @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_PWRSEQ_LPCN ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */ #define MXC_R_PWRSEQ_LPCN ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */
#define MXC_R_PWRSEQ_LPWKST0 ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */ #define MXC_R_PWRSEQ_LPWKST0 ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */
#define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */ #define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */
#define MXC_R_PWRSEQ_LPWKST1 ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x000C</tt> */ #define MXC_R_PWRSEQ_LPWKST1 ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x000C</tt> */
#define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0010</tt> */ #define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0010</tt> */
#define MXC_R_PWRSEQ_LPPWKST ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0030</tt> */ #define MXC_R_PWRSEQ_LPPWKST ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0030</tt> */
#define MXC_R_PWRSEQ_LPPWKEN ((uint32_t)0x00000034UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0034</tt> */ #define MXC_R_PWRSEQ_LPPWKEN ((uint32_t)0x00000034UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0034</tt> */
#define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */ #define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */
#define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0048</tt> */
#define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x004C</tt> */
/**@} end of group pwrseq_registers */ /**@} end of group pwrseq_registers */
/** /**
@ -118,71 +123,68 @@ typedef struct {
* @brief Low Power Control Register. * @brief Low Power Control Register.
* @{ * @{
*/ */
#define MXC_F_PWRSEQ_LPCN_RAM0RET_EN_POS 0 /**< LPCN_RAM0RET_EN Position */ #define MXC_F_PWRSEQ_LPCN_RAM0RET_EN_POS 0 /**< LPCN_RAM0RET_EN Position */
#define MXC_F_PWRSEQ_LPCN_RAM0RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM0RET_EN_POS)) /**< LPCN_RAM0RET_EN Mask */ #define MXC_F_PWRSEQ_LPCN_RAM0RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM0RET_EN_POS)) /**< LPCN_RAM0RET_EN Mask */
#define MXC_F_PWRSEQ_LPCN_RAM1RET_EN_POS 1 /**< LPCN_RAM1RET_EN Position */ #define MXC_F_PWRSEQ_LPCN_RAM1RET_EN_POS 1 /**< LPCN_RAM1RET_EN Position */
#define MXC_F_PWRSEQ_LPCN_RAM1RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM1RET_EN_POS)) /**< LPCN_RAM1RET_EN Mask */ #define MXC_F_PWRSEQ_LPCN_RAM1RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM1RET_EN_POS)) /**< LPCN_RAM1RET_EN Mask */
#define MXC_F_PWRSEQ_LPCN_RAM2RET_EN_POS 2 /**< LPCN_RAM2RET_EN Position */ #define MXC_F_PWRSEQ_LPCN_RAM2RET_EN_POS 2 /**< LPCN_RAM2RET_EN Position */
#define MXC_F_PWRSEQ_LPCN_RAM2RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM2RET_EN_POS)) /**< LPCN_RAM2RET_EN Mask */ #define MXC_F_PWRSEQ_LPCN_RAM2RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM2RET_EN_POS)) /**< LPCN_RAM2RET_EN Mask */
#define MXC_F_PWRSEQ_LPCN_RAM3RET_EN_POS 3 /**< LPCN_RAM3RET_EN Position */ #define MXC_F_PWRSEQ_LPCN_RAM3RET_EN_POS 3 /**< LPCN_RAM3RET_EN Position */
#define MXC_F_PWRSEQ_LPCN_RAM3RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM3RET_EN_POS)) /**< LPCN_RAM3RET_EN Mask */ #define MXC_F_PWRSEQ_LPCN_RAM3RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM3RET_EN_POS)) /**< LPCN_RAM3RET_EN Mask */
#define MXC_F_PWRSEQ_LPCN_OVR_POS 4 /**< LPCN_OVR Position */ #define MXC_F_PWRSEQ_LPCN_OVR_POS 4 /**< LPCN_OVR Position */
#define MXC_F_PWRSEQ_LPCN_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_OVR_POS)) /**< LPCN_OVR Mask */ #define MXC_F_PWRSEQ_LPCN_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_OVR_POS)) /**< LPCN_OVR Mask */
#define MXC_V_PWRSEQ_LPCN_OVR_0_9V ((uint32_t)0x0UL) /**< LPCN_OVR_0_9V Value */ #define MXC_V_PWRSEQ_LPCN_OVR_0_9V ((uint32_t)0x0UL) /**< LPCN_OVR_0_9V Value */
#define MXC_S_PWRSEQ_LPCN_OVR_0_9V (MXC_V_PWRSEQ_LPCN_OVR_0_9V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_0_9V Setting */ #define MXC_S_PWRSEQ_LPCN_OVR_0_9V (MXC_V_PWRSEQ_LPCN_OVR_0_9V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_0_9V Setting */
#define MXC_V_PWRSEQ_LPCN_OVR_1_0V ((uint32_t)0x1UL) /**< LPCN_OVR_1_0V Value */ #define MXC_V_PWRSEQ_LPCN_OVR_1_0V ((uint32_t)0x1UL) /**< LPCN_OVR_1_0V Value */
#define MXC_S_PWRSEQ_LPCN_OVR_1_0V (MXC_V_PWRSEQ_LPCN_OVR_1_0V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_1_0V Setting */ #define MXC_S_PWRSEQ_LPCN_OVR_1_0V (MXC_V_PWRSEQ_LPCN_OVR_1_0V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_1_0V Setting */
#define MXC_V_PWRSEQ_LPCN_OVR_1_1V ((uint32_t)0x2UL) /**< LPCN_OVR_1_1V Value */ #define MXC_V_PWRSEQ_LPCN_OVR_1_1V ((uint32_t)0x2UL) /**< LPCN_OVR_1_1V Value */
#define MXC_S_PWRSEQ_LPCN_OVR_1_1V (MXC_V_PWRSEQ_LPCN_OVR_1_1V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_1_1V Setting */ #define MXC_S_PWRSEQ_LPCN_OVR_1_1V (MXC_V_PWRSEQ_LPCN_OVR_1_1V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_1_1V Setting */
#define MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS_POS 6 /**< LPCN_VCORE_DET_BYPASS Position */ #define MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS_POS 6 /**< LPCN_VCORE_DET_BYPASS Position */
#define MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS_POS)) /**< LPCN_VCORE_DET_BYPASS Mask */ #define MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS_POS)) /**< LPCN_VCORE_DET_BYPASS Mask */
#define MXC_F_PWRSEQ_LPCN_RETREG_EN_POS 8 /**< LPCN_RETREG_EN Position */ #define MXC_F_PWRSEQ_LPCN_RETREG_EN_POS 8 /**< LPCN_RETREG_EN Position */
#define MXC_F_PWRSEQ_LPCN_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RETREG_EN_POS)) /**< LPCN_RETREG_EN Mask */ #define MXC_F_PWRSEQ_LPCN_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RETREG_EN_POS)) /**< LPCN_RETREG_EN Mask */
#define MXC_F_PWRSEQ_LPCN_STORAGE_EN_POS 9 /**< LPCN_STORAGE_EN Position */ #define MXC_F_PWRSEQ_LPCN_STORAGE_EN_POS 9 /**< LPCN_STORAGE_EN Position */
#define MXC_F_PWRSEQ_LPCN_STORAGE_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_STORAGE_EN_POS)) /**< LPCN_STORAGE_EN Mask */ #define MXC_F_PWRSEQ_LPCN_STORAGE_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_STORAGE_EN_POS)) /**< LPCN_STORAGE_EN Mask */
#define MXC_F_PWRSEQ_LPCN_FASTWK_EN_POS 10 /**< LPCN_FASTWK_EN Position */ #define MXC_F_PWRSEQ_LPCN_FASTWK_EN_POS 10 /**< LPCN_FASTWK_EN Position */
#define MXC_F_PWRSEQ_LPCN_FASTWK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FASTWK_EN_POS)) /**< LPCN_FASTWK_EN Mask */ #define MXC_F_PWRSEQ_LPCN_FASTWK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FASTWK_EN_POS)) /**< LPCN_FASTWK_EN Mask */
#define MXC_F_PWRSEQ_LPCN_BG_DIS_POS 11 /**< LPCN_BG_DIS Position */ #define MXC_F_PWRSEQ_LPCN_BG_DIS_POS 11 /**< LPCN_BG_DIS Position */
#define MXC_F_PWRSEQ_LPCN_BG_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BG_DIS_POS)) /**< LPCN_BG_DIS Mask */ #define MXC_F_PWRSEQ_LPCN_BG_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BG_DIS_POS)) /**< LPCN_BG_DIS Mask */
#define MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS_POS 12 /**< LPCN_VCOREPOR_DIS Position */ #define MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS_POS 12 /**< LPCN_VCOREPOR_DIS Position */
#define MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS_POS)) /**< LPCN_VCOREPOR_DIS Mask */ #define MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS_POS)) /**< LPCN_VCOREPOR_DIS Mask */
#define MXC_F_PWRSEQ_LPCN_LDO_DIS_POS 16 /**< LPCN_LDO_DIS Position */ #define MXC_F_PWRSEQ_LPCN_LDO_DIS_POS 16 /**< LPCN_LDO_DIS Position */
#define MXC_F_PWRSEQ_LPCN_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_LDO_DIS_POS)) /**< LPCN_LDO_DIS Mask */ #define MXC_F_PWRSEQ_LPCN_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_LDO_DIS_POS)) /**< LPCN_LDO_DIS Mask */
#define MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS 17 /**< LPCN_VCORE_EXT Position */ #define MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS 17 /**< LPCN_VCORE_EXT Position */
#define MXC_F_PWRSEQ_LPCN_VCORE_EXT ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS)) /**< LPCN_VCORE_EXT Mask */ #define MXC_F_PWRSEQ_LPCN_VCORE_EXT ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS)) /**< LPCN_VCORE_EXT Mask */
#define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS 20 /**< LPCN_VCOREMON_DIS Position */ #define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS 20 /**< LPCN_VCOREMON_DIS Position */
#define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS)) /**< LPCN_VCOREMON_DIS Mask */ #define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS)) /**< LPCN_VCOREMON_DIS Mask */
#define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS 22 /**< LPCN_VDDAMON_DIS Position */ #define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS 22 /**< LPCN_VDDAMON_DIS Position */
#define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS)) /**< LPCN_VDDAMON_DIS Mask */ #define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS)) /**< LPCN_VDDAMON_DIS Mask */
#define MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS_POS 25 /**< LPCN_PORVDDMON_DIS Position */ #define MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS_POS 25 /**< LPCN_PORVDDMON_DIS Position */
#define MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS_POS)) /**< LPCN_PORVDDMON_DIS Mask */ #define MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS_POS)) /**< LPCN_PORVDDMON_DIS Mask */
#define MXC_F_PWRSEQ_LPCN_INRO_EN_POS 28 /**< LPCN_INRO_EN Position */ #define MXC_F_PWRSEQ_LPCN_INRO_EN_POS 28 /**< LPCN_INRO_EN Position */
#define MXC_F_PWRSEQ_LPCN_INRO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_INRO_EN_POS)) /**< LPCN_INRO_EN Mask */ #define MXC_F_PWRSEQ_LPCN_INRO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_INRO_EN_POS)) /**< LPCN_INRO_EN Mask */
#define MXC_F_PWRSEQ_LPCN_ERTCO_EN_POS 29 /**< LPCN_ERTCO_EN Position */ #define MXC_F_PWRSEQ_LPCN_ERTCO_EN_POS 29 /**< LPCN_ERTCO_EN Position */
#define MXC_F_PWRSEQ_LPCN_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_ERTCO_EN_POS)) /**< LPCN_ERTCO_EN Mask */ #define MXC_F_PWRSEQ_LPCN_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_ERTCO_EN_POS)) /**< LPCN_ERTCO_EN Mask */
#define MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS 30 /**< LPCN_TM_LPMODE Position */ #define MXC_F_PWRSEQ_LPCN_ERTCO_PD_POS 31 /**< LPCN_ERTCO_PD Position */
#define MXC_F_PWRSEQ_LPCN_TM_LPMODE ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS)) /**< LPCN_TM_LPMODE Mask */ #define MXC_F_PWRSEQ_LPCN_ERTCO_PD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_ERTCO_PD_POS)) /**< LPCN_ERTCO_PD Mask */
#define MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS 31 /**< LPCN_TM_PWRSEQ Position */
#define MXC_F_PWRSEQ_LPCN_TM_PWRSEQ ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS)) /**< LPCN_TM_PWRSEQ Mask */
/**@} end of group PWRSEQ_LPCN_Register */ /**@} end of group PWRSEQ_LPCN_Register */
@ -193,8 +195,8 @@ typedef struct {
* wakeup status for GPIO0. * wakeup status for GPIO0.
* @{ * @{
*/ */
#define MXC_F_PWRSEQ_LPWKST0_ST_POS 0 /**< LPWKST0_ST Position */ #define MXC_F_PWRSEQ_LPWKST0_ST_POS 0 /**< LPWKST0_ST Position */
#define MXC_F_PWRSEQ_LPWKST0_ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPWKST0_ST_POS)) /**< LPWKST0_ST Mask */ #define MXC_F_PWRSEQ_LPWKST0_ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPWKST0_ST_POS)) /**< LPWKST0_ST Mask */
/**@} end of group PWRSEQ_LPWKST0_Register */ /**@} end of group PWRSEQ_LPWKST0_Register */
@ -205,8 +207,8 @@ typedef struct {
* functionality for GPIO0. * functionality for GPIO0.
* @{ * @{
*/ */
#define MXC_F_PWRSEQ_LPWKEN0_EN_POS 0 /**< LPWKEN0_EN Position */ #define MXC_F_PWRSEQ_LPWKEN0_EN_POS 0 /**< LPWKEN0_EN Position */
#define MXC_F_PWRSEQ_LPWKEN0_EN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_EN_POS)) /**< LPWKEN0_EN Mask */ #define MXC_F_PWRSEQ_LPWKEN0_EN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_EN_POS)) /**< LPWKEN0_EN Mask */
/**@} end of group PWRSEQ_LPWKEN0_Register */ /**@} end of group PWRSEQ_LPWKEN0_Register */
@ -216,14 +218,14 @@ typedef struct {
* @brief Low Power Peripheral Wakeup Status Register. * @brief Low Power Peripheral Wakeup Status Register.
* @{ * @{
*/ */
#define MXC_F_PWRSEQ_LPPWKST_LPTMR0_POS 0 /**< LPPWKST_LPTMR0 Position */ #define MXC_F_PWRSEQ_LPPWKST_LPTMR0_POS 0 /**< LPPWKST_LPTMR0 Position */
#define MXC_F_PWRSEQ_LPPWKST_LPTMR0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPTMR0_POS)) /**< LPPWKST_LPTMR0 Mask */ #define MXC_F_PWRSEQ_LPPWKST_LPTMR0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPTMR0_POS)) /**< LPPWKST_LPTMR0 Mask */
#define MXC_F_PWRSEQ_LPPWKST_LPTMR1_POS 1 /**< LPPWKST_LPTMR1 Position */ #define MXC_F_PWRSEQ_LPPWKST_LPTMR1_POS 1 /**< LPPWKST_LPTMR1 Position */
#define MXC_F_PWRSEQ_LPPWKST_LPTMR1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPTMR1_POS)) /**< LPPWKST_LPTMR1 Mask */ #define MXC_F_PWRSEQ_LPPWKST_LPTMR1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPTMR1_POS)) /**< LPPWKST_LPTMR1 Mask */
#define MXC_F_PWRSEQ_LPPWKST_LPUART0_POS 2 /**< LPPWKST_LPUART0 Position */ #define MXC_F_PWRSEQ_LPPWKST_LPUART0_POS 2 /**< LPPWKST_LPUART0 Position */
#define MXC_F_PWRSEQ_LPPWKST_LPUART0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPUART0_POS)) /**< LPPWKST_LPUART0 Mask */ #define MXC_F_PWRSEQ_LPPWKST_LPUART0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPUART0_POS)) /**< LPPWKST_LPUART0 Mask */
/**@} end of group PWRSEQ_LPPWKST_Register */ /**@} end of group PWRSEQ_LPPWKST_Register */
@ -233,14 +235,14 @@ typedef struct {
* @brief Low Power Peripheral Wakeup Enable Register. * @brief Low Power Peripheral Wakeup Enable Register.
* @{ * @{
*/ */
#define MXC_F_PWRSEQ_LPPWKEN_LPTMR0_POS 0 /**< LPPWKEN_LPTMR0 Position */ #define MXC_F_PWRSEQ_LPPWKEN_LPTMR0_POS 0 /**< LPPWKEN_LPTMR0 Position */
#define MXC_F_PWRSEQ_LPPWKEN_LPTMR0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPTMR0_POS)) /**< LPPWKEN_LPTMR0 Mask */ #define MXC_F_PWRSEQ_LPPWKEN_LPTMR0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPTMR0_POS)) /**< LPPWKEN_LPTMR0 Mask */
#define MXC_F_PWRSEQ_LPPWKEN_LPTMR1_POS 1 /**< LPPWKEN_LPTMR1 Position */ #define MXC_F_PWRSEQ_LPPWKEN_LPTMR1_POS 1 /**< LPPWKEN_LPTMR1 Position */
#define MXC_F_PWRSEQ_LPPWKEN_LPTMR1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPTMR1_POS)) /**< LPPWKEN_LPTMR1 Mask */ #define MXC_F_PWRSEQ_LPPWKEN_LPTMR1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPTMR1_POS)) /**< LPPWKEN_LPTMR1 Mask */
#define MXC_F_PWRSEQ_LPPWKEN_LPUART0_POS 2 /**< LPPWKEN_LPUART0 Position */ #define MXC_F_PWRSEQ_LPPWKEN_LPUART0_POS 2 /**< LPPWKEN_LPUART0 Position */
#define MXC_F_PWRSEQ_LPPWKEN_LPUART0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPUART0_POS)) /**< LPPWKEN_LPUART0 Mask */ #define MXC_F_PWRSEQ_LPPWKEN_LPUART0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPUART0_POS)) /**< LPPWKEN_LPUART0 Mask */
/**@} end of group PWRSEQ_LPPWKEN_Register */ /**@} end of group PWRSEQ_LPPWKEN_Register */
@ -250,17 +252,17 @@ typedef struct {
* @brief Low Power Memory Shutdown Control. * @brief Low Power Memory Shutdown Control.
* @{ * @{
*/ */
#define MXC_F_PWRSEQ_LPMEMSD_RAM0_POS 0 /**< LPMEMSD_RAM0 Position */ #define MXC_F_PWRSEQ_LPMEMSD_RAM0_POS 0 /**< LPMEMSD_RAM0 Position */
#define MXC_F_PWRSEQ_LPMEMSD_RAM0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM0_POS)) /**< LPMEMSD_RAM0 Mask */ #define MXC_F_PWRSEQ_LPMEMSD_RAM0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM0_POS)) /**< LPMEMSD_RAM0 Mask */
#define MXC_F_PWRSEQ_LPMEMSD_RAM1_POS 1 /**< LPMEMSD_RAM1 Position */ #define MXC_F_PWRSEQ_LPMEMSD_RAM1_POS 1 /**< LPMEMSD_RAM1 Position */
#define MXC_F_PWRSEQ_LPMEMSD_RAM1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM1_POS)) /**< LPMEMSD_RAM1 Mask */ #define MXC_F_PWRSEQ_LPMEMSD_RAM1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM1_POS)) /**< LPMEMSD_RAM1 Mask */
#define MXC_F_PWRSEQ_LPMEMSD_RAM2_POS 2 /**< LPMEMSD_RAM2 Position */ #define MXC_F_PWRSEQ_LPMEMSD_RAM2_POS 2 /**< LPMEMSD_RAM2 Position */
#define MXC_F_PWRSEQ_LPMEMSD_RAM2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM2_POS)) /**< LPMEMSD_RAM2 Mask */ #define MXC_F_PWRSEQ_LPMEMSD_RAM2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM2_POS)) /**< LPMEMSD_RAM2 Mask */
#define MXC_F_PWRSEQ_LPMEMSD_RAM3_POS 3 /**< LPMEMSD_RAM3 Position */ #define MXC_F_PWRSEQ_LPMEMSD_RAM3_POS 3 /**< LPMEMSD_RAM3 Position */
#define MXC_F_PWRSEQ_LPMEMSD_RAM3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM3_POS)) /**< LPMEMSD_RAM3 Mask */ #define MXC_F_PWRSEQ_LPMEMSD_RAM3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM3_POS)) /**< LPMEMSD_RAM3 Mask */
/**@} end of group PWRSEQ_LPMEMSD_Register */ /**@} end of group PWRSEQ_LPMEMSD_Register */
@ -268,4 +270,4 @@ typedef struct {
} }
#endif #endif
#endif /* _PWRSEQ_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_PWRSEQ_REGS_H_

126
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/rtc_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file rtc_regs.h * @file rtc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _RTC_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_RTC_REGS_H_
#define _RTC_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_RTC_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup rtc * @ingroup rtc
* @defgroup rtc_registers RTC_Registers * @defgroup rtc_registers RTC_Registers
* @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
* @details Real Time Clock and Alarm. * @details Real Time Clock and Alarm.
*/ */
/** /**
@ -99,13 +99,13 @@ typedef struct {
* @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address. * @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: <tt> 0x0000</tt> */ #define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: <tt> 0x0000</tt> */
#define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: <tt> 0x0004</tt> */ #define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: <tt> 0x0004</tt> */
#define MXC_R_RTC_TODA ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: <tt> 0x0008</tt> */ #define MXC_R_RTC_TODA ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: <tt> 0x0008</tt> */
#define MXC_R_RTC_SSECA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: <tt> 0x000C</tt> */ #define MXC_R_RTC_SSECA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: <tt> 0x000C</tt> */
#define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: <tt> 0x0010</tt> */ #define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: <tt> 0x0010</tt> */
#define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: <tt> 0x0014</tt> */ #define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: <tt> 0x0014</tt> */
#define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: <tt> 0x0018</tt> */ #define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: <tt> 0x0018</tt> */
/**@} end of group rtc_registers */ /**@} end of group rtc_registers */
/** /**
@ -114,8 +114,8 @@ typedef struct {
* @brief RTC Second Counter. This register contains the 32-bit second counter. * @brief RTC Second Counter. This register contains the 32-bit second counter.
* @{ * @{
*/ */
#define MXC_F_RTC_SEC_SEC_POS 0 /**< SEC_SEC Position */ #define MXC_F_RTC_SEC_SEC_POS 0 /**< SEC_SEC Position */
#define MXC_F_RTC_SEC_SEC ((uint32_t)(0xFFUL << MXC_F_RTC_SEC_SEC_POS)) /**< SEC_SEC Mask */ #define MXC_F_RTC_SEC_SEC ((uint32_t)(0xFFUL << MXC_F_RTC_SEC_SEC_POS)) /**< SEC_SEC Mask */
/**@} end of group RTC_SEC_Register */ /**@} end of group RTC_SEC_Register */
@ -126,8 +126,8 @@ typedef struct {
* when this register rolls over from 0xFF to 0x00. * when this register rolls over from 0xFF to 0x00.
* @{ * @{
*/ */
#define MXC_F_RTC_SSEC_SSEC_POS 0 /**< SSEC_SSEC Position */ #define MXC_F_RTC_SSEC_SSEC_POS 0 /**< SSEC_SSEC Position */
#define MXC_F_RTC_SSEC_SSEC ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_SSEC_POS)) /**< SSEC_SSEC Mask */ #define MXC_F_RTC_SSEC_SSEC ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_SSEC_POS)) /**< SSEC_SSEC Mask */
/**@} end of group RTC_SSEC_Register */ /**@} end of group RTC_SSEC_Register */
@ -137,8 +137,8 @@ typedef struct {
* @brief Time-of-day Alarm. * @brief Time-of-day Alarm.
* @{ * @{
*/ */
#define MXC_F_RTC_TODA_TOD_ALARM_POS 0 /**< TODA_TOD_ALARM Position */ #define MXC_F_RTC_TODA_TOD_ALARM_POS 0 /**< TODA_TOD_ALARM Position */
#define MXC_F_RTC_TODA_TOD_ALARM ((uint32_t)(0xFFFFFUL << MXC_F_RTC_TODA_TOD_ALARM_POS)) /**< TODA_TOD_ALARM Mask */ #define MXC_F_RTC_TODA_TOD_ALARM ((uint32_t)(0xFFFFFUL << MXC_F_RTC_TODA_TOD_ALARM_POS)) /**< TODA_TOD_ALARM Mask */
/**@} end of group RTC_TODA_Register */ /**@} end of group RTC_TODA_Register */
@ -149,8 +149,8 @@ typedef struct {
* second alarm. * second alarm.
* @{ * @{
*/ */
#define MXC_F_RTC_SSECA_SSEC_ALARM_POS 0 /**< SSECA_SSEC_ALARM Position */ #define MXC_F_RTC_SSECA_SSEC_ALARM_POS 0 /**< SSECA_SSEC_ALARM Position */
#define MXC_F_RTC_SSECA_SSEC_ALARM ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_SSECA_SSEC_ALARM_POS)) /**< SSECA_SSEC_ALARM Mask */ #define MXC_F_RTC_SSECA_SSEC_ALARM ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_SSECA_SSEC_ALARM_POS)) /**< SSECA_SSEC_ALARM Mask */
/**@} end of group RTC_SSECA_Register */ /**@} end of group RTC_SSECA_Register */
@ -160,49 +160,49 @@ typedef struct {
* @brief RTC Control Register. * @brief RTC Control Register.
* @{ * @{
*/ */
#define MXC_F_RTC_CTRL_EN_POS 0 /**< CTRL_EN Position */ #define MXC_F_RTC_CTRL_EN_POS 0 /**< CTRL_EN Position */
#define MXC_F_RTC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_EN_POS)) /**< CTRL_EN Mask */ #define MXC_F_RTC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_EN_POS)) /**< CTRL_EN Mask */
#define MXC_F_RTC_CTRL_TOD_ALARM_IE_POS 1 /**< CTRL_TOD_ALARM_IE Position */ #define MXC_F_RTC_CTRL_TOD_ALARM_IE_POS 1 /**< CTRL_TOD_ALARM_IE Position */
#define MXC_F_RTC_CTRL_TOD_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_IE_POS)) /**< CTRL_TOD_ALARM_IE Mask */ #define MXC_F_RTC_CTRL_TOD_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_IE_POS)) /**< CTRL_TOD_ALARM_IE Mask */
#define MXC_F_RTC_CTRL_SSEC_ALARM_IE_POS 2 /**< CTRL_SSEC_ALARM_IE Position */ #define MXC_F_RTC_CTRL_SSEC_ALARM_IE_POS 2 /**< CTRL_SSEC_ALARM_IE Position */
#define MXC_F_RTC_CTRL_SSEC_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_IE_POS)) /**< CTRL_SSEC_ALARM_IE Mask */ #define MXC_F_RTC_CTRL_SSEC_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_IE_POS)) /**< CTRL_SSEC_ALARM_IE Mask */
#define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ #define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */
#define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ #define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */
#define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ #define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */
#define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ #define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
#define MXC_F_RTC_CTRL_RDY_IE_POS 5 /**< CTRL_RDY_IE Position */ #define MXC_F_RTC_CTRL_RDY_IE_POS 5 /**< CTRL_RDY_IE Position */
#define MXC_F_RTC_CTRL_RDY_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_IE_POS)) /**< CTRL_RDY_IE Mask */ #define MXC_F_RTC_CTRL_RDY_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_IE_POS)) /**< CTRL_RDY_IE Mask */
#define MXC_F_RTC_CTRL_TOD_ALARM_POS 6 /**< CTRL_TOD_ALARM Position */ #define MXC_F_RTC_CTRL_TOD_ALARM_POS 6 /**< CTRL_TOD_ALARM Position */
#define MXC_F_RTC_CTRL_TOD_ALARM ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_POS)) /**< CTRL_TOD_ALARM Mask */ #define MXC_F_RTC_CTRL_TOD_ALARM ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_POS)) /**< CTRL_TOD_ALARM Mask */
#define MXC_F_RTC_CTRL_SSEC_ALARM_POS 7 /**< CTRL_SSEC_ALARM Position */ #define MXC_F_RTC_CTRL_SSEC_ALARM_POS 7 /**< CTRL_SSEC_ALARM Position */
#define MXC_F_RTC_CTRL_SSEC_ALARM ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_POS)) /**< CTRL_SSEC_ALARM Mask */ #define MXC_F_RTC_CTRL_SSEC_ALARM ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_POS)) /**< CTRL_SSEC_ALARM Mask */
#define MXC_F_RTC_CTRL_SQW_EN_POS 8 /**< CTRL_SQW_EN Position */ #define MXC_F_RTC_CTRL_SQW_EN_POS 8 /**< CTRL_SQW_EN Position */
#define MXC_F_RTC_CTRL_SQW_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQW_EN_POS)) /**< CTRL_SQW_EN Mask */ #define MXC_F_RTC_CTRL_SQW_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQW_EN_POS)) /**< CTRL_SQW_EN Mask */
#define MXC_F_RTC_CTRL_SQW_SEL_POS 9 /**< CTRL_SQW_SEL Position */ #define MXC_F_RTC_CTRL_SQW_SEL_POS 9 /**< CTRL_SQW_SEL Position */
#define MXC_F_RTC_CTRL_SQW_SEL ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_SQW_SEL_POS)) /**< CTRL_SQW_SEL Mask */ #define MXC_F_RTC_CTRL_SQW_SEL ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_SQW_SEL_POS)) /**< CTRL_SQW_SEL Mask */
#define MXC_V_RTC_CTRL_SQW_SEL_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_SQW_SEL_FREQ1HZ Value */ #define MXC_V_RTC_CTRL_SQW_SEL_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_SQW_SEL_FREQ1HZ Value */
#define MXC_S_RTC_CTRL_SQW_SEL_FREQ1HZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ1HZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ1HZ Setting */ #define MXC_S_RTC_CTRL_SQW_SEL_FREQ1HZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ1HZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ1HZ Setting */
#define MXC_V_RTC_CTRL_SQW_SEL_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_SQW_SEL_FREQ512HZ Value */ #define MXC_V_RTC_CTRL_SQW_SEL_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_SQW_SEL_FREQ512HZ Value */
#define MXC_S_RTC_CTRL_SQW_SEL_FREQ512HZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ512HZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ512HZ Setting */ #define MXC_S_RTC_CTRL_SQW_SEL_FREQ512HZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ512HZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ512HZ Setting */
#define MXC_V_RTC_CTRL_SQW_SEL_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_SQW_SEL_FREQ4KHZ Value */ #define MXC_V_RTC_CTRL_SQW_SEL_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_SQW_SEL_FREQ4KHZ Value */
#define MXC_S_RTC_CTRL_SQW_SEL_FREQ4KHZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ4KHZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ4KHZ Setting */ #define MXC_S_RTC_CTRL_SQW_SEL_FREQ4KHZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ4KHZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ4KHZ Setting */
#define MXC_V_RTC_CTRL_SQW_SEL_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_SQW_SEL_CLKDIV8 Value */ #define MXC_V_RTC_CTRL_SQW_SEL_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_SQW_SEL_CLKDIV8 Value */
#define MXC_S_RTC_CTRL_SQW_SEL_CLKDIV8 (MXC_V_RTC_CTRL_SQW_SEL_CLKDIV8 << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_CLKDIV8 Setting */ #define MXC_S_RTC_CTRL_SQW_SEL_CLKDIV8 (MXC_V_RTC_CTRL_SQW_SEL_CLKDIV8 << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_CLKDIV8 Setting */
#define MXC_F_RTC_CTRL_RD_EN_POS 14 /**< CTRL_RD_EN Position */ #define MXC_F_RTC_CTRL_RD_EN_POS 14 /**< CTRL_RD_EN Position */
#define MXC_F_RTC_CTRL_RD_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RD_EN_POS)) /**< CTRL_RD_EN Mask */ #define MXC_F_RTC_CTRL_RD_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RD_EN_POS)) /**< CTRL_RD_EN Mask */
#define MXC_F_RTC_CTRL_WR_EN_POS 15 /**< CTRL_WR_EN Position */ #define MXC_F_RTC_CTRL_WR_EN_POS 15 /**< CTRL_WR_EN Position */
#define MXC_F_RTC_CTRL_WR_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WR_EN_POS)) /**< CTRL_WR_EN Mask */ #define MXC_F_RTC_CTRL_WR_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WR_EN_POS)) /**< CTRL_WR_EN Mask */
/**@} end of group RTC_CTRL_Register */ /**@} end of group RTC_CTRL_Register */
@ -212,11 +212,11 @@ typedef struct {
* @brief RTC Trim Register. * @brief RTC Trim Register.
* @{ * @{
*/ */
#define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */ #define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */
#define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */ #define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */
#define MXC_F_RTC_TRIM_VRTC_TMR_POS 8 /**< TRIM_VRTC_TMR Position */ #define MXC_F_RTC_TRIM_VRTC_TMR_POS 8 /**< TRIM_VRTC_TMR Position */
#define MXC_F_RTC_TRIM_VRTC_TMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VRTC_TMR_POS)) /**< TRIM_VRTC_TMR Mask */ #define MXC_F_RTC_TRIM_VRTC_TMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VRTC_TMR_POS)) /**< TRIM_VRTC_TMR Mask */
/**@} end of group RTC_TRIM_Register */ /**@} end of group RTC_TRIM_Register */
@ -226,11 +226,11 @@ typedef struct {
* @brief RTC Oscillator Control Register. * @brief RTC Oscillator Control Register.
* @{ * @{
*/ */
#define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */ #define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */
#define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */ #define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */
#define MXC_F_RTC_OSCCTRL_SQW_32K_POS 5 /**< OSCCTRL_SQW_32K Position */ #define MXC_F_RTC_OSCCTRL_SQW_32K_POS 5 /**< OSCCTRL_SQW_32K Position */
#define MXC_F_RTC_OSCCTRL_SQW_32K ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_SQW_32K_POS)) /**< OSCCTRL_SQW_32K Mask */ #define MXC_F_RTC_OSCCTRL_SQW_32K ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_SQW_32K_POS)) /**< OSCCTRL_SQW_32K Mask */
/**@} end of group RTC_OSCCTRL_Register */ /**@} end of group RTC_OSCCTRL_Register */
@ -238,4 +238,4 @@ typedef struct {
} }
#endif #endif
#endif /* _RTC_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_RTC_REGS_H_

32
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/sir_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file sir_regs.h * @file sir_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _SIR_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SIR_REGS_H_
#define _SIR_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SIR_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup sir * @ingroup sir
* @defgroup sir_registers SIR_Registers * @defgroup sir_registers SIR_Registers
* @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module.
* @details System Initialization Registers. * @details System Initialization Registers.
*/ */
/** /**
@ -94,8 +94,8 @@ typedef struct {
* @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address. * @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_SIR_SIR_STATUS ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: <tt> 0x0000</tt> */ #define MXC_R_SIR_SIR_STATUS ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: <tt> 0x0000</tt> */
#define MXC_R_SIR_SIR_ADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: <tt> 0x0004</tt> */ #define MXC_R_SIR_SIR_ADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: <tt> 0x0004</tt> */
/**@} end of group sir_registers */ /**@} end of group sir_registers */
/** /**
@ -104,11 +104,11 @@ typedef struct {
* @brief System Initialization Status Register. * @brief System Initialization Status Register.
* @{ * @{
*/ */
#define MXC_F_SIR_SIR_STATUS_CFG_VALID_POS 0 /**< SIR_STATUS_CFG_VALID Position */ #define MXC_F_SIR_SIR_STATUS_CFG_VALID_POS 0 /**< SIR_STATUS_CFG_VALID Position */
#define MXC_F_SIR_SIR_STATUS_CFG_VALID ((uint32_t)(0x1UL << MXC_F_SIR_SIR_STATUS_CFG_VALID_POS)) /**< SIR_STATUS_CFG_VALID Mask */ #define MXC_F_SIR_SIR_STATUS_CFG_VALID ((uint32_t)(0x1UL << MXC_F_SIR_SIR_STATUS_CFG_VALID_POS)) /**< SIR_STATUS_CFG_VALID Mask */
#define MXC_F_SIR_SIR_STATUS_CFG_ERR_POS 1 /**< SIR_STATUS_CFG_ERR Position */ #define MXC_F_SIR_SIR_STATUS_CFG_ERR_POS 1 /**< SIR_STATUS_CFG_ERR Position */
#define MXC_F_SIR_SIR_STATUS_CFG_ERR ((uint32_t)(0x1UL << MXC_F_SIR_SIR_STATUS_CFG_ERR_POS)) /**< SIR_STATUS_CFG_ERR Mask */ #define MXC_F_SIR_SIR_STATUS_CFG_ERR ((uint32_t)(0x1UL << MXC_F_SIR_SIR_STATUS_CFG_ERR_POS)) /**< SIR_STATUS_CFG_ERR Mask */
/**@} end of group SIR_SIR_STATUS_Register */ /**@} end of group SIR_SIR_STATUS_Register */
@ -120,8 +120,8 @@ typedef struct {
* 1). * 1).
* @{ * @{
*/ */
#define MXC_F_SIR_SIR_ADDR_ADDR_POS 0 /**< SIR_ADDR_ADDR Position */ #define MXC_F_SIR_SIR_ADDR_ADDR_POS 0 /**< SIR_ADDR_ADDR Position */
#define MXC_F_SIR_SIR_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_SIR_ADDR_ADDR_POS)) /**< SIR_ADDR_ADDR Mask */ #define MXC_F_SIR_SIR_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_SIR_ADDR_ADDR_POS)) /**< SIR_ADDR_ADDR Mask */
/**@} end of group SIR_SIR_ADDR_Register */ /**@} end of group SIR_SIR_ADDR_Register */
@ -129,4 +129,4 @@ typedef struct {
} }
#endif #endif
#endif /* _SIR_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SIR_REGS_H_

394
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/spi_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file spi_regs.h * @file spi_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _SPI_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SPI_REGS_H_
#define _SPI_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SPI_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup spi * @ingroup spi
* @defgroup spi_registers SPI_Registers * @defgroup spi_registers SPI_Registers
* @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module.
* @details SPI peripheral. * @details SPI peripheral.
*/ */
/** /**
@ -83,11 +83,11 @@ extern "C" {
* Structure type to access the SPI Registers. * Structure type to access the SPI Registers.
*/ */
typedef struct { typedef struct {
union{ union {
__IO uint32_t fifo32; /**< <tt>\b 0x00:</tt> SPI FIFO32 Register */ __IO uint32_t fifo32; /**< <tt>\b 0x00:</tt> SPI FIFO32 Register */
__IO uint16_t fifo16[2]; /**< <tt>\b 0x00:</tt> SPI FIFO16 Register */ __IO uint16_t fifo16[2]; /**< <tt>\b 0x00:</tt> SPI FIFO16 Register */
__IO uint8_t fifo8[4]; /**< <tt>\b 0x00:</tt> SPI FIFO8 Register */ __IO uint8_t fifo8[4]; /**< <tt>\b 0x00:</tt> SPI FIFO8 Register */
}; };
__IO uint32_t ctrl0; /**< <tt>\b 0x04:</tt> SPI CTRL0 Register */ __IO uint32_t ctrl0; /**< <tt>\b 0x04:</tt> SPI CTRL0 Register */
__IO uint32_t ctrl1; /**< <tt>\b 0x08:</tt> SPI CTRL1 Register */ __IO uint32_t ctrl1; /**< <tt>\b 0x08:</tt> SPI CTRL1 Register */
__IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPI CTRL2 Register */ __IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPI CTRL2 Register */
@ -109,20 +109,20 @@ typedef struct {
* @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address. * @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_SPI_FIFO32 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ #define MXC_R_SPI_FIFO32 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPI_FIFO16 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ #define MXC_R_SPI_FIFO16 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPI_FIFO8 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ #define MXC_R_SPI_FIFO8 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: <tt> 0x0004</tt> */ #define MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: <tt> 0x0004</tt> */
#define MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: <tt> 0x0008</tt> */ #define MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: <tt> 0x0008</tt> */
#define MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: <tt> 0x000C</tt> */ #define MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: <tt> 0x000C</tt> */
#define MXC_R_SPI_SSTIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: <tt> 0x0010</tt> */ #define MXC_R_SPI_SSTIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: <tt> 0x0010</tt> */
#define MXC_R_SPI_CLKCTRL ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: <tt> 0x0014</tt> */ #define MXC_R_SPI_CLKCTRL ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: <tt> 0x0014</tt> */
#define MXC_R_SPI_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: <tt> 0x001C</tt> */ #define MXC_R_SPI_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: <tt> 0x001C</tt> */
#define MXC_R_SPI_INTFL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: <tt> 0x0020</tt> */ #define MXC_R_SPI_INTFL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: <tt> 0x0020</tt> */
#define MXC_R_SPI_INTEN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: <tt> 0x0024</tt> */ #define MXC_R_SPI_INTEN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: <tt> 0x0024</tt> */
#define MXC_R_SPI_WKFL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: <tt> 0x0028</tt> */ #define MXC_R_SPI_WKFL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: <tt> 0x0028</tt> */
#define MXC_R_SPI_WKEN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: <tt> 0x002C</tt> */ #define MXC_R_SPI_WKEN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: <tt> 0x002C</tt> */
#define MXC_R_SPI_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: <tt> 0x0030</tt> */ #define MXC_R_SPI_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: <tt> 0x0030</tt> */
/**@} end of group spi_registers */ /**@} end of group spi_registers */
/** /**
@ -131,8 +131,8 @@ typedef struct {
* @brief Register for reading and writing the FIFO. * @brief Register for reading and writing the FIFO.
* @{ * @{
*/ */
#define MXC_F_SPI_FIFO32_DATA_POS 0 /**< FIFO32_DATA Position */ #define MXC_F_SPI_FIFO32_DATA_POS 0 /**< FIFO32_DATA Position */
#define MXC_F_SPI_FIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI_FIFO32_DATA_POS)) /**< FIFO32_DATA Mask */ #define MXC_F_SPI_FIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI_FIFO32_DATA_POS)) /**< FIFO32_DATA Mask */
/**@} end of group SPI_FIFO32_Register */ /**@} end of group SPI_FIFO32_Register */
@ -142,8 +142,8 @@ typedef struct {
* @brief Register for reading and writing the FIFO. * @brief Register for reading and writing the FIFO.
* @{ * @{
*/ */
#define MXC_F_SPI_FIFO16_DATA_POS 0 /**< FIFO16_DATA Position */ #define MXC_F_SPI_FIFO16_DATA_POS 0 /**< FIFO16_DATA Position */
#define MXC_F_SPI_FIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPI_FIFO16_DATA_POS)) /**< FIFO16_DATA Mask */ #define MXC_F_SPI_FIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPI_FIFO16_DATA_POS)) /**< FIFO16_DATA Mask */
/**@} end of group SPI_FIFO16_Register */ /**@} end of group SPI_FIFO16_Register */
@ -153,8 +153,8 @@ typedef struct {
* @brief Register for reading and writing the FIFO. * @brief Register for reading and writing the FIFO.
* @{ * @{
*/ */
#define MXC_F_SPI_FIFO8_DATA_POS 0 /**< FIFO8_DATA Position */ #define MXC_F_SPI_FIFO8_DATA_POS 0 /**< FIFO8_DATA Position */
#define MXC_F_SPI_FIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_SPI_FIFO8_DATA_POS)) /**< FIFO8_DATA Mask */ #define MXC_F_SPI_FIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_SPI_FIFO8_DATA_POS)) /**< FIFO8_DATA Mask */
/**@} end of group SPI_FIFO8_Register */ /**@} end of group SPI_FIFO8_Register */
@ -164,31 +164,31 @@ typedef struct {
* @brief Register for controlling SPI peripheral. * @brief Register for controlling SPI peripheral.
* @{ * @{
*/ */
#define MXC_F_SPI_CTRL0_EN_POS 0 /**< CTRL0_EN Position */ #define MXC_F_SPI_CTRL0_EN_POS 0 /**< CTRL0_EN Position */
#define MXC_F_SPI_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_EN_POS)) /**< CTRL0_EN Mask */ #define MXC_F_SPI_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_EN_POS)) /**< CTRL0_EN Mask */
#define MXC_F_SPI_CTRL0_MST_MODE_POS 1 /**< CTRL0_MST_MODE Position */ #define MXC_F_SPI_CTRL0_MST_MODE_POS 1 /**< CTRL0_MST_MODE Position */
#define MXC_F_SPI_CTRL0_MST_MODE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MST_MODE_POS)) /**< CTRL0_MST_MODE Mask */ #define MXC_F_SPI_CTRL0_MST_MODE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MST_MODE_POS)) /**< CTRL0_MST_MODE Mask */
#define MXC_F_SPI_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */ #define MXC_F_SPI_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */
#define MXC_F_SPI_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */ #define MXC_F_SPI_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */
#define MXC_F_SPI_CTRL0_START_POS 5 /**< CTRL0_START Position */ #define MXC_F_SPI_CTRL0_START_POS 5 /**< CTRL0_START Position */
#define MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) /**< CTRL0_START Mask */ #define MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) /**< CTRL0_START Mask */
#define MXC_F_SPI_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */ #define MXC_F_SPI_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */
#define MXC_F_SPI_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */ #define MXC_F_SPI_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */
#define MXC_F_SPI_CTRL0_SS_ACTIVE_POS 16 /**< CTRL0_SS_ACTIVE Position */ #define MXC_F_SPI_CTRL0_SS_ACTIVE_POS 16 /**< CTRL0_SS_ACTIVE Position */
#define MXC_F_SPI_CTRL0_SS_ACTIVE ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)) /**< CTRL0_SS_ACTIVE Mask */ #define MXC_F_SPI_CTRL0_SS_ACTIVE ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)) /**< CTRL0_SS_ACTIVE Mask */
#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_ACTIVE_SS0 Value */ #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_ACTIVE_SS0 Value */
#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS0 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS0 Setting */ #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS0 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS0 Setting */
#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_ACTIVE_SS1 Value */ #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_ACTIVE_SS1 Value */
#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS1 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS1 Setting */ #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS1 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS1 Setting */
#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_ACTIVE_SS2 Value */ #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_ACTIVE_SS2 Value */
#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS2 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS2 Setting */ #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS2 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS2 Setting */
#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_ACTIVE_SS3 Value */ #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_ACTIVE_SS3 Value */
#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS3 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS3 Setting */ #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS3 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS3 Setting */
/**@} end of group SPI_CTRL0_Register */ /**@} end of group SPI_CTRL0_Register */
@ -198,11 +198,11 @@ typedef struct {
* @brief Register for controlling SPI peripheral. * @brief Register for controlling SPI peripheral.
* @{ * @{
*/ */
#define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */ #define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */
#define MXC_F_SPI_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */ #define MXC_F_SPI_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */
#define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */ #define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */
#define MXC_F_SPI_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */ #define MXC_F_SPI_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */
/**@} end of group SPI_CTRL1_Register */ /**@} end of group SPI_CTRL1_Register */
@ -212,39 +212,39 @@ typedef struct {
* @brief Register for controlling SPI peripheral. * @brief Register for controlling SPI peripheral.
* @{ * @{
*/ */
#define MXC_F_SPI_CTRL2_CLKPHA_POS 0 /**< CTRL2_CLKPHA Position */ #define MXC_F_SPI_CTRL2_CLKPHA_POS 0 /**< CTRL2_CLKPHA Position */
#define MXC_F_SPI_CTRL2_CLKPHA ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPHA_POS)) /**< CTRL2_CLKPHA Mask */ #define MXC_F_SPI_CTRL2_CLKPHA ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPHA_POS)) /**< CTRL2_CLKPHA Mask */
#define MXC_F_SPI_CTRL2_CLKPOL_POS 1 /**< CTRL2_CLKPOL Position */ #define MXC_F_SPI_CTRL2_CLKPOL_POS 1 /**< CTRL2_CLKPOL Position */
#define MXC_F_SPI_CTRL2_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPOL_POS)) /**< CTRL2_CLKPOL Mask */ #define MXC_F_SPI_CTRL2_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPOL_POS)) /**< CTRL2_CLKPOL Mask */
#define MXC_F_SPI_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */ #define MXC_F_SPI_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */
#define MXC_F_SPI_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */ #define MXC_F_SPI_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */
#define MXC_V_SPI_CTRL2_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_0 Value */ #define MXC_V_SPI_CTRL2_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_0 Value */
#define MXC_S_SPI_CTRL2_NUMBITS_0 (MXC_V_SPI_CTRL2_NUMBITS_0 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_0 Setting */ #define MXC_S_SPI_CTRL2_NUMBITS_0 (MXC_V_SPI_CTRL2_NUMBITS_0 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_0 Setting */
#define MXC_F_SPI_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */ #define MXC_F_SPI_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */
#define MXC_F_SPI_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */ #define MXC_F_SPI_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */
#define MXC_V_SPI_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */ #define MXC_V_SPI_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */
#define MXC_S_SPI_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */ #define MXC_S_SPI_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */
#define MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */ #define MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */
#define MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */ #define MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */
#define MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */ #define MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */
#define MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */ #define MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */
#define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ #define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */
#define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ #define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */
#define MXC_F_SPI_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */ #define MXC_F_SPI_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */
#define MXC_F_SPI_CTRL2_SS_POL ((uint32_t)(0xFFUL << MXC_F_SPI_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */ #define MXC_F_SPI_CTRL2_SS_POL ((uint32_t)(0xFFUL << MXC_F_SPI_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */
#define MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */ #define MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */
#define MXC_S_SPI_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */ #define MXC_S_SPI_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */
#define MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */ #define MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */
#define MXC_S_SPI_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */ #define MXC_S_SPI_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */
#define MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */ #define MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */
#define MXC_S_SPI_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */ #define MXC_S_SPI_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */
#define MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SS_POL_SS3_HIGH Value */ #define MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SS_POL_SS3_HIGH Value */
#define MXC_S_SPI_CTRL2_SS_POL_SS3_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS3_HIGH Setting */ #define MXC_S_SPI_CTRL2_SS_POL_SS3_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS3_HIGH Setting */
/**@} end of group SPI_CTRL2_Register */ /**@} end of group SPI_CTRL2_Register */
@ -254,20 +254,20 @@ typedef struct {
* @brief Register for controlling SPI peripheral/Slave Select Timing. * @brief Register for controlling SPI peripheral/Slave Select Timing.
* @{ * @{
*/ */
#define MXC_F_SPI_SSTIME_PRE_POS 0 /**< SSTIME_PRE Position */ #define MXC_F_SPI_SSTIME_PRE_POS 0 /**< SSTIME_PRE Position */
#define MXC_F_SPI_SSTIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_PRE_POS)) /**< SSTIME_PRE Mask */ #define MXC_F_SPI_SSTIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_PRE_POS)) /**< SSTIME_PRE Mask */
#define MXC_V_SPI_SSTIME_PRE_256 ((uint32_t)0x0UL) /**< SSTIME_PRE_256 Value */ #define MXC_V_SPI_SSTIME_PRE_256 ((uint32_t)0x0UL) /**< SSTIME_PRE_256 Value */
#define MXC_S_SPI_SSTIME_PRE_256 (MXC_V_SPI_SSTIME_PRE_256 << MXC_F_SPI_SSTIME_PRE_POS) /**< SSTIME_PRE_256 Setting */ #define MXC_S_SPI_SSTIME_PRE_256 (MXC_V_SPI_SSTIME_PRE_256 << MXC_F_SPI_SSTIME_PRE_POS) /**< SSTIME_PRE_256 Setting */
#define MXC_F_SPI_SSTIME_POST_POS 8 /**< SSTIME_POST Position */ #define MXC_F_SPI_SSTIME_POST_POS 8 /**< SSTIME_POST Position */
#define MXC_F_SPI_SSTIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_POST_POS)) /**< SSTIME_POST Mask */ #define MXC_F_SPI_SSTIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_POST_POS)) /**< SSTIME_POST Mask */
#define MXC_V_SPI_SSTIME_POST_256 ((uint32_t)0x0UL) /**< SSTIME_POST_256 Value */ #define MXC_V_SPI_SSTIME_POST_256 ((uint32_t)0x0UL) /**< SSTIME_POST_256 Value */
#define MXC_S_SPI_SSTIME_POST_256 (MXC_V_SPI_SSTIME_POST_256 << MXC_F_SPI_SSTIME_POST_POS) /**< SSTIME_POST_256 Setting */ #define MXC_S_SPI_SSTIME_POST_256 (MXC_V_SPI_SSTIME_POST_256 << MXC_F_SPI_SSTIME_POST_POS) /**< SSTIME_POST_256 Setting */
#define MXC_F_SPI_SSTIME_INACT_POS 16 /**< SSTIME_INACT Position */ #define MXC_F_SPI_SSTIME_INACT_POS 16 /**< SSTIME_INACT Position */
#define MXC_F_SPI_SSTIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_INACT_POS)) /**< SSTIME_INACT Mask */ #define MXC_F_SPI_SSTIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_INACT_POS)) /**< SSTIME_INACT Mask */
#define MXC_V_SPI_SSTIME_INACT_256 ((uint32_t)0x0UL) /**< SSTIME_INACT_256 Value */ #define MXC_V_SPI_SSTIME_INACT_256 ((uint32_t)0x0UL) /**< SSTIME_INACT_256 Value */
#define MXC_S_SPI_SSTIME_INACT_256 (MXC_V_SPI_SSTIME_INACT_256 << MXC_F_SPI_SSTIME_INACT_POS) /**< SSTIME_INACT_256 Setting */ #define MXC_S_SPI_SSTIME_INACT_256 (MXC_V_SPI_SSTIME_INACT_256 << MXC_F_SPI_SSTIME_INACT_POS) /**< SSTIME_INACT_256 Setting */
/**@} end of group SPI_SSTIME_Register */ /**@} end of group SPI_SSTIME_Register */
@ -277,18 +277,18 @@ typedef struct {
* @brief Register for controlling SPI clock rate. * @brief Register for controlling SPI clock rate.
* @{ * @{
*/ */
#define MXC_F_SPI_CLKCTRL_LO_POS 0 /**< CLKCTRL_LO Position */ #define MXC_F_SPI_CLKCTRL_LO_POS 0 /**< CLKCTRL_LO Position */
#define MXC_F_SPI_CLKCTRL_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_LO_POS)) /**< CLKCTRL_LO Mask */ #define MXC_F_SPI_CLKCTRL_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_LO_POS)) /**< CLKCTRL_LO Mask */
#define MXC_V_SPI_CLKCTRL_LO_DIS ((uint32_t)0x0UL) /**< CLKCTRL_LO_DIS Value */ #define MXC_V_SPI_CLKCTRL_LO_DIS ((uint32_t)0x0UL) /**< CLKCTRL_LO_DIS Value */
#define MXC_S_SPI_CLKCTRL_LO_DIS (MXC_V_SPI_CLKCTRL_LO_DIS << MXC_F_SPI_CLKCTRL_LO_POS) /**< CLKCTRL_LO_DIS Setting */ #define MXC_S_SPI_CLKCTRL_LO_DIS (MXC_V_SPI_CLKCTRL_LO_DIS << MXC_F_SPI_CLKCTRL_LO_POS) /**< CLKCTRL_LO_DIS Setting */
#define MXC_F_SPI_CLKCTRL_HI_POS 8 /**< CLKCTRL_HI Position */ #define MXC_F_SPI_CLKCTRL_HI_POS 8 /**< CLKCTRL_HI Position */
#define MXC_F_SPI_CLKCTRL_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_HI_POS)) /**< CLKCTRL_HI Mask */ #define MXC_F_SPI_CLKCTRL_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_HI_POS)) /**< CLKCTRL_HI Mask */
#define MXC_V_SPI_CLKCTRL_HI_DIS ((uint32_t)0x0UL) /**< CLKCTRL_HI_DIS Value */ #define MXC_V_SPI_CLKCTRL_HI_DIS ((uint32_t)0x0UL) /**< CLKCTRL_HI_DIS Value */
#define MXC_S_SPI_CLKCTRL_HI_DIS (MXC_V_SPI_CLKCTRL_HI_DIS << MXC_F_SPI_CLKCTRL_HI_POS) /**< CLKCTRL_HI_DIS Setting */ #define MXC_S_SPI_CLKCTRL_HI_DIS (MXC_V_SPI_CLKCTRL_HI_DIS << MXC_F_SPI_CLKCTRL_HI_POS) /**< CLKCTRL_HI_DIS Setting */
#define MXC_F_SPI_CLKCTRL_CLKDIV_POS 16 /**< CLKCTRL_CLKDIV Position */ #define MXC_F_SPI_CLKCTRL_CLKDIV_POS 16 /**< CLKCTRL_CLKDIV Position */
#define MXC_F_SPI_CLKCTRL_CLKDIV ((uint32_t)(0xFUL << MXC_F_SPI_CLKCTRL_CLKDIV_POS)) /**< CLKCTRL_CLKDIV Mask */ #define MXC_F_SPI_CLKCTRL_CLKDIV ((uint32_t)(0xFUL << MXC_F_SPI_CLKCTRL_CLKDIV_POS)) /**< CLKCTRL_CLKDIV Mask */
/**@} end of group SPI_CLKCTRL_Register */ /**@} end of group SPI_CLKCTRL_Register */
@ -298,35 +298,35 @@ typedef struct {
* @brief Register for controlling DMA. * @brief Register for controlling DMA.
* @{ * @{
*/ */
#define MXC_F_SPI_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */ #define MXC_F_SPI_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */
#define MXC_F_SPI_DMA_TX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */ #define MXC_F_SPI_DMA_TX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */
#define MXC_F_SPI_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ #define MXC_F_SPI_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */
#define MXC_F_SPI_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ #define MXC_F_SPI_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */
#define MXC_F_SPI_DMA_TX_FLUSH_POS 7 /**< DMA_TX_FLUSH Position */ #define MXC_F_SPI_DMA_TX_FLUSH_POS 7 /**< DMA_TX_FLUSH Position */
#define MXC_F_SPI_DMA_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FLUSH_POS)) /**< DMA_TX_FLUSH Mask */ #define MXC_F_SPI_DMA_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FLUSH_POS)) /**< DMA_TX_FLUSH Mask */
#define MXC_F_SPI_DMA_TX_LVL_POS 8 /**< DMA_TX_LVL Position */ #define MXC_F_SPI_DMA_TX_LVL_POS 8 /**< DMA_TX_LVL Position */
#define MXC_F_SPI_DMA_TX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_LVL_POS)) /**< DMA_TX_LVL Mask */ #define MXC_F_SPI_DMA_TX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_LVL_POS)) /**< DMA_TX_LVL Mask */
#define MXC_F_SPI_DMA_DMA_TX_EN_POS 15 /**< DMA_DMA_TX_EN Position */ #define MXC_F_SPI_DMA_DMA_TX_EN_POS 15 /**< DMA_DMA_TX_EN Position */
#define MXC_F_SPI_DMA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_DMA_TX_EN_POS)) /**< DMA_DMA_TX_EN Mask */ #define MXC_F_SPI_DMA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_DMA_TX_EN_POS)) /**< DMA_DMA_TX_EN Mask */
#define MXC_F_SPI_DMA_RX_THD_VAL_POS 16 /**< DMA_RX_THD_VAL Position */ #define MXC_F_SPI_DMA_RX_THD_VAL_POS 16 /**< DMA_RX_THD_VAL Position */
#define MXC_F_SPI_DMA_RX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */ #define MXC_F_SPI_DMA_RX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */
#define MXC_F_SPI_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ #define MXC_F_SPI_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */
#define MXC_F_SPI_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ #define MXC_F_SPI_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */
#define MXC_F_SPI_DMA_RX_FLUSH_POS 23 /**< DMA_RX_FLUSH Position */ #define MXC_F_SPI_DMA_RX_FLUSH_POS 23 /**< DMA_RX_FLUSH Position */
#define MXC_F_SPI_DMA_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FLUSH_POS)) /**< DMA_RX_FLUSH Mask */ #define MXC_F_SPI_DMA_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FLUSH_POS)) /**< DMA_RX_FLUSH Mask */
#define MXC_F_SPI_DMA_RX_LVL_POS 24 /**< DMA_RX_LVL Position */ #define MXC_F_SPI_DMA_RX_LVL_POS 24 /**< DMA_RX_LVL Position */
#define MXC_F_SPI_DMA_RX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_LVL_POS)) /**< DMA_RX_LVL Mask */ #define MXC_F_SPI_DMA_RX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_LVL_POS)) /**< DMA_RX_LVL Mask */
#define MXC_F_SPI_DMA_DMA_RX_EN_POS 31 /**< DMA_DMA_RX_EN Position */ #define MXC_F_SPI_DMA_DMA_RX_EN_POS 31 /**< DMA_DMA_RX_EN Position */
#define MXC_F_SPI_DMA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_DMA_RX_EN_POS)) /**< DMA_DMA_RX_EN Mask */ #define MXC_F_SPI_DMA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_DMA_RX_EN_POS)) /**< DMA_DMA_RX_EN Mask */
/**@} end of group SPI_DMA_Register */ /**@} end of group SPI_DMA_Register */
@ -337,44 +337,44 @@ typedef struct {
* clear. * clear.
* @{ * @{
*/ */
#define MXC_F_SPI_INTFL_TX_THD_POS 0 /**< INTFL_TX_THD Position */ #define MXC_F_SPI_INTFL_TX_THD_POS 0 /**< INTFL_TX_THD Position */
#define MXC_F_SPI_INTFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_THD_POS)) /**< INTFL_TX_THD Mask */ #define MXC_F_SPI_INTFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_THD_POS)) /**< INTFL_TX_THD Mask */
#define MXC_F_SPI_INTFL_TX_EM_POS 1 /**< INTFL_TX_EM Position */ #define MXC_F_SPI_INTFL_TX_EM_POS 1 /**< INTFL_TX_EM Position */
#define MXC_F_SPI_INTFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_EM_POS)) /**< INTFL_TX_EM Mask */ #define MXC_F_SPI_INTFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_EM_POS)) /**< INTFL_TX_EM Mask */
#define MXC_F_SPI_INTFL_RX_THD_POS 2 /**< INTFL_RX_THD Position */ #define MXC_F_SPI_INTFL_RX_THD_POS 2 /**< INTFL_RX_THD Position */
#define MXC_F_SPI_INTFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_THD_POS)) /**< INTFL_RX_THD Mask */ #define MXC_F_SPI_INTFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_THD_POS)) /**< INTFL_RX_THD Mask */
#define MXC_F_SPI_INTFL_RX_FULL_POS 3 /**< INTFL_RX_FULL Position */ #define MXC_F_SPI_INTFL_RX_FULL_POS 3 /**< INTFL_RX_FULL Position */
#define MXC_F_SPI_INTFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_FULL_POS)) /**< INTFL_RX_FULL Mask */ #define MXC_F_SPI_INTFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_FULL_POS)) /**< INTFL_RX_FULL Mask */
#define MXC_F_SPI_INTFL_SSA_POS 4 /**< INTFL_SSA Position */ #define MXC_F_SPI_INTFL_SSA_POS 4 /**< INTFL_SSA Position */
#define MXC_F_SPI_INTFL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSA_POS)) /**< INTFL_SSA Mask */ #define MXC_F_SPI_INTFL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSA_POS)) /**< INTFL_SSA Mask */
#define MXC_F_SPI_INTFL_SSD_POS 5 /**< INTFL_SSD Position */ #define MXC_F_SPI_INTFL_SSD_POS 5 /**< INTFL_SSD Position */
#define MXC_F_SPI_INTFL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSD_POS)) /**< INTFL_SSD Mask */ #define MXC_F_SPI_INTFL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSD_POS)) /**< INTFL_SSD Mask */
#define MXC_F_SPI_INTFL_FAULT_POS 8 /**< INTFL_FAULT Position */ #define MXC_F_SPI_INTFL_FAULT_POS 8 /**< INTFL_FAULT Position */
#define MXC_F_SPI_INTFL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_FAULT_POS)) /**< INTFL_FAULT Mask */ #define MXC_F_SPI_INTFL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_FAULT_POS)) /**< INTFL_FAULT Mask */
#define MXC_F_SPI_INTFL_ABORT_POS 9 /**< INTFL_ABORT Position */ #define MXC_F_SPI_INTFL_ABORT_POS 9 /**< INTFL_ABORT Position */
#define MXC_F_SPI_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */ #define MXC_F_SPI_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */
#define MXC_F_SPI_INTFL_MST_DONE_POS 11 /**< INTFL_MST_DONE Position */ #define MXC_F_SPI_INTFL_MST_DONE_POS 11 /**< INTFL_MST_DONE Position */
#define MXC_F_SPI_INTFL_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_MST_DONE_POS)) /**< INTFL_MST_DONE Mask */ #define MXC_F_SPI_INTFL_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_MST_DONE_POS)) /**< INTFL_MST_DONE Mask */
#define MXC_F_SPI_INTFL_TX_OV_POS 12 /**< INTFL_TX_OV Position */ #define MXC_F_SPI_INTFL_TX_OV_POS 12 /**< INTFL_TX_OV Position */
#define MXC_F_SPI_INTFL_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_OV_POS)) /**< INTFL_TX_OV Mask */ #define MXC_F_SPI_INTFL_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_OV_POS)) /**< INTFL_TX_OV Mask */
#define MXC_F_SPI_INTFL_TX_UN_POS 13 /**< INTFL_TX_UN Position */ #define MXC_F_SPI_INTFL_TX_UN_POS 13 /**< INTFL_TX_UN Position */
#define MXC_F_SPI_INTFL_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_UN_POS)) /**< INTFL_TX_UN Mask */ #define MXC_F_SPI_INTFL_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_UN_POS)) /**< INTFL_TX_UN Mask */
#define MXC_F_SPI_INTFL_RX_OV_POS 14 /**< INTFL_RX_OV Position */ #define MXC_F_SPI_INTFL_RX_OV_POS 14 /**< INTFL_RX_OV Position */
#define MXC_F_SPI_INTFL_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_OV_POS)) /**< INTFL_RX_OV Mask */ #define MXC_F_SPI_INTFL_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_OV_POS)) /**< INTFL_RX_OV Mask */
#define MXC_F_SPI_INTFL_RX_UN_POS 15 /**< INTFL_RX_UN Position */ #define MXC_F_SPI_INTFL_RX_UN_POS 15 /**< INTFL_RX_UN Position */
#define MXC_F_SPI_INTFL_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_UN_POS)) /**< INTFL_RX_UN Mask */ #define MXC_F_SPI_INTFL_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_UN_POS)) /**< INTFL_RX_UN Mask */
/**@} end of group SPI_INTFL_Register */ /**@} end of group SPI_INTFL_Register */
@ -384,44 +384,44 @@ typedef struct {
* @brief Register for enabling interrupts. * @brief Register for enabling interrupts.
* @{ * @{
*/ */
#define MXC_F_SPI_INTEN_TX_THD_POS 0 /**< INTEN_TX_THD Position */ #define MXC_F_SPI_INTEN_TX_THD_POS 0 /**< INTEN_TX_THD Position */
#define MXC_F_SPI_INTEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_THD_POS)) /**< INTEN_TX_THD Mask */ #define MXC_F_SPI_INTEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_THD_POS)) /**< INTEN_TX_THD Mask */
#define MXC_F_SPI_INTEN_TX_EM_POS 1 /**< INTEN_TX_EM Position */ #define MXC_F_SPI_INTEN_TX_EM_POS 1 /**< INTEN_TX_EM Position */
#define MXC_F_SPI_INTEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_EM_POS)) /**< INTEN_TX_EM Mask */ #define MXC_F_SPI_INTEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_EM_POS)) /**< INTEN_TX_EM Mask */
#define MXC_F_SPI_INTEN_RX_THD_POS 2 /**< INTEN_RX_THD Position */ #define MXC_F_SPI_INTEN_RX_THD_POS 2 /**< INTEN_RX_THD Position */
#define MXC_F_SPI_INTEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_THD_POS)) /**< INTEN_RX_THD Mask */ #define MXC_F_SPI_INTEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_THD_POS)) /**< INTEN_RX_THD Mask */
#define MXC_F_SPI_INTEN_RX_FULL_POS 3 /**< INTEN_RX_FULL Position */ #define MXC_F_SPI_INTEN_RX_FULL_POS 3 /**< INTEN_RX_FULL Position */
#define MXC_F_SPI_INTEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_FULL_POS)) /**< INTEN_RX_FULL Mask */ #define MXC_F_SPI_INTEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_FULL_POS)) /**< INTEN_RX_FULL Mask */
#define MXC_F_SPI_INTEN_SSA_POS 4 /**< INTEN_SSA Position */ #define MXC_F_SPI_INTEN_SSA_POS 4 /**< INTEN_SSA Position */
#define MXC_F_SPI_INTEN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSA_POS)) /**< INTEN_SSA Mask */ #define MXC_F_SPI_INTEN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSA_POS)) /**< INTEN_SSA Mask */
#define MXC_F_SPI_INTEN_SSD_POS 5 /**< INTEN_SSD Position */ #define MXC_F_SPI_INTEN_SSD_POS 5 /**< INTEN_SSD Position */
#define MXC_F_SPI_INTEN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSD_POS)) /**< INTEN_SSD Mask */ #define MXC_F_SPI_INTEN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSD_POS)) /**< INTEN_SSD Mask */
#define MXC_F_SPI_INTEN_FAULT_POS 8 /**< INTEN_FAULT Position */ #define MXC_F_SPI_INTEN_FAULT_POS 8 /**< INTEN_FAULT Position */
#define MXC_F_SPI_INTEN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_FAULT_POS)) /**< INTEN_FAULT Mask */ #define MXC_F_SPI_INTEN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_FAULT_POS)) /**< INTEN_FAULT Mask */
#define MXC_F_SPI_INTEN_ABORT_POS 9 /**< INTEN_ABORT Position */ #define MXC_F_SPI_INTEN_ABORT_POS 9 /**< INTEN_ABORT Position */
#define MXC_F_SPI_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */ #define MXC_F_SPI_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */
#define MXC_F_SPI_INTEN_MST_DONE_POS 11 /**< INTEN_MST_DONE Position */ #define MXC_F_SPI_INTEN_MST_DONE_POS 11 /**< INTEN_MST_DONE Position */
#define MXC_F_SPI_INTEN_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_MST_DONE_POS)) /**< INTEN_MST_DONE Mask */ #define MXC_F_SPI_INTEN_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_MST_DONE_POS)) /**< INTEN_MST_DONE Mask */
#define MXC_F_SPI_INTEN_TX_OV_POS 12 /**< INTEN_TX_OV Position */ #define MXC_F_SPI_INTEN_TX_OV_POS 12 /**< INTEN_TX_OV Position */
#define MXC_F_SPI_INTEN_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_OV_POS)) /**< INTEN_TX_OV Mask */ #define MXC_F_SPI_INTEN_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_OV_POS)) /**< INTEN_TX_OV Mask */
#define MXC_F_SPI_INTEN_TX_UN_POS 13 /**< INTEN_TX_UN Position */ #define MXC_F_SPI_INTEN_TX_UN_POS 13 /**< INTEN_TX_UN Position */
#define MXC_F_SPI_INTEN_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_UN_POS)) /**< INTEN_TX_UN Mask */ #define MXC_F_SPI_INTEN_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_UN_POS)) /**< INTEN_TX_UN Mask */
#define MXC_F_SPI_INTEN_RX_OV_POS 14 /**< INTEN_RX_OV Position */ #define MXC_F_SPI_INTEN_RX_OV_POS 14 /**< INTEN_RX_OV Position */
#define MXC_F_SPI_INTEN_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_OV_POS)) /**< INTEN_RX_OV Mask */ #define MXC_F_SPI_INTEN_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_OV_POS)) /**< INTEN_RX_OV Mask */
#define MXC_F_SPI_INTEN_RX_UN_POS 15 /**< INTEN_RX_UN Position */ #define MXC_F_SPI_INTEN_RX_UN_POS 15 /**< INTEN_RX_UN Position */
#define MXC_F_SPI_INTEN_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_UN_POS)) /**< INTEN_RX_UN Mask */ #define MXC_F_SPI_INTEN_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_UN_POS)) /**< INTEN_RX_UN Mask */
/**@} end of group SPI_INTEN_Register */ /**@} end of group SPI_INTEN_Register */
@ -431,17 +431,17 @@ typedef struct {
* @brief Register for wake up flags. All bits in this register are write 1 to clear. * @brief Register for wake up flags. All bits in this register are write 1 to clear.
* @{ * @{
*/ */
#define MXC_F_SPI_WKFL_TX_THD_POS 0 /**< WKFL_TX_THD Position */ #define MXC_F_SPI_WKFL_TX_THD_POS 0 /**< WKFL_TX_THD Position */
#define MXC_F_SPI_WKFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_THD_POS)) /**< WKFL_TX_THD Mask */ #define MXC_F_SPI_WKFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_THD_POS)) /**< WKFL_TX_THD Mask */
#define MXC_F_SPI_WKFL_TX_EM_POS 1 /**< WKFL_TX_EM Position */ #define MXC_F_SPI_WKFL_TX_EM_POS 1 /**< WKFL_TX_EM Position */
#define MXC_F_SPI_WKFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_EM_POS)) /**< WKFL_TX_EM Mask */ #define MXC_F_SPI_WKFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_EM_POS)) /**< WKFL_TX_EM Mask */
#define MXC_F_SPI_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */ #define MXC_F_SPI_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */
#define MXC_F_SPI_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */ #define MXC_F_SPI_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */
#define MXC_F_SPI_WKFL_RX_FULL_POS 3 /**< WKFL_RX_FULL Position */ #define MXC_F_SPI_WKFL_RX_FULL_POS 3 /**< WKFL_RX_FULL Position */
#define MXC_F_SPI_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */ #define MXC_F_SPI_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */
/**@} end of group SPI_WKFL_Register */ /**@} end of group SPI_WKFL_Register */
@ -451,17 +451,17 @@ typedef struct {
* @brief Register for wake up enable. * @brief Register for wake up enable.
* @{ * @{
*/ */
#define MXC_F_SPI_WKEN_TX_THD_POS 0 /**< WKEN_TX_THD Position */ #define MXC_F_SPI_WKEN_TX_THD_POS 0 /**< WKEN_TX_THD Position */
#define MXC_F_SPI_WKEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_THD_POS)) /**< WKEN_TX_THD Mask */ #define MXC_F_SPI_WKEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_THD_POS)) /**< WKEN_TX_THD Mask */
#define MXC_F_SPI_WKEN_TX_EM_POS 1 /**< WKEN_TX_EM Position */ #define MXC_F_SPI_WKEN_TX_EM_POS 1 /**< WKEN_TX_EM Position */
#define MXC_F_SPI_WKEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_EM_POS)) /**< WKEN_TX_EM Mask */ #define MXC_F_SPI_WKEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_EM_POS)) /**< WKEN_TX_EM Mask */
#define MXC_F_SPI_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */ #define MXC_F_SPI_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */
#define MXC_F_SPI_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */ #define MXC_F_SPI_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */
#define MXC_F_SPI_WKEN_RX_FULL_POS 3 /**< WKEN_RX_FULL Position */ #define MXC_F_SPI_WKEN_RX_FULL_POS 3 /**< WKEN_RX_FULL Position */
#define MXC_F_SPI_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */ #define MXC_F_SPI_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */
/**@} end of group SPI_WKEN_Register */ /**@} end of group SPI_WKEN_Register */
@ -471,8 +471,8 @@ typedef struct {
* @brief SPI Status register. * @brief SPI Status register.
* @{ * @{
*/ */
#define MXC_F_SPI_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ #define MXC_F_SPI_STAT_BUSY_POS 0 /**< STAT_BUSY Position */
#define MXC_F_SPI_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ #define MXC_F_SPI_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) /**< STAT_BUSY Mask */
/**@} end of group SPI_STAT_Register */ /**@} end of group SPI_STAT_Register */
@ -480,4 +480,4 @@ typedef struct {
} }
#endif #endif
#endif /* _SPI_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SPI_REGS_H_

29
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/system_max32670.h
View File

@ -1,5 +1,5 @@
/******************************************************************************* /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -29,11 +29,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*
******************************************************************************/ ******************************************************************************/
#ifndef _SYSTEM_MAX32670_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SYSTEM_MAX32670_H_
#define _SYSTEM_MAX32670_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SYSTEM_MAX32670_H_
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -53,42 +52,42 @@ extern "C" {
/* NOTE: EXTCLK needs to be defined by user based on the clock they supply */ /* NOTE: EXTCLK needs to be defined by user based on the clock they supply */
#ifndef EXTCLK_FREQ #ifndef EXTCLK_FREQ
#define EXTCLK_FREQ 75000000 #define EXTCLK_FREQ 12500000
#endif #endif
/* NOTE: This is the nominal value for INRO. The actual value may vary from chip to chip. /* NOTE: This is the nominal value for INRO. The actual value may vary from chip to chip.
Update if use of this oscillator requires precise timing.*/ Update if use of this oscillator requires precise timing.*/
/* NOTE: INRO was previously named NANORING */ /* NOTE: INRO was previously named NANORING */
#ifndef INRO_FREQ #ifndef INRO_FREQ
#define INRO_FREQ 80000 #define INRO_FREQ 80000
#endif #endif
//NOTE: IPO clock bit is documented as 96MHz, but SR says this will be 100. //NOTE: IPO clock bit is documented as 96MHz, but SR says this will be 100.
#ifndef IPO_FREQ #ifndef IPO_FREQ
#define IPO_FREQ 100000000 #define IPO_FREQ 100000000
#endif #endif
#ifndef IBRO_FREQ #ifndef IBRO_FREQ
#define IBRO_FREQ 7372800 #define IBRO_FREQ 7372800
#endif #endif
/* NOTE: ERFO_FREQ (16MHz-32MHz) needs to be defined by user based on the clock they supply */ /* NOTE: ERFO_FREQ (16MHz-32MHz) needs to be defined by user based on the clock they supply */
#ifndef ERFO_FREQ #ifndef ERFO_FREQ
#define ERFO_FREQ 32000000 #define ERFO_FREQ 32000000
#endif #endif
#ifndef ERTCO_FREQ #ifndef ERTCO_FREQ
#define ERTCO_FREQ 32768 #define ERTCO_FREQ 32768
#endif #endif
#ifndef HIRC_FREQ #ifndef HIRC_FREQ
#define HIRC_FREQ IPO_FREQ #define HIRC_FREQ IPO_FREQ
#endif #endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
#ifdef PeripheralClock #ifdef PeripheralClock
#warning PeripheralClock define is being overidden. #warning PeripheralClock define is being overidden.
#else #else
#define PeripheralClock (SystemCoreClock /2) /*!< Peripheral Clock Frequency */ #define PeripheralClock (SystemCoreClock / 2) /*!< Peripheral Clock Frequency */
#endif #endif
/* /*
@ -111,4 +110,4 @@ void SystemCoreClockUpdate(void);
} }
#endif #endif
#endif /* _SYSTEM_MAX32670_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_SYSTEM_MAX32670_H_

440
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file tmr_regs.h * @file tmr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _TMR_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_TMR_REGS_H_
#define _TMR_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_TMR_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup tmr * @ingroup tmr
* @defgroup tmr_registers TMR_Registers * @defgroup tmr_registers TMR_Registers
* @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
* @details Low-Power Configurable Timer * @details Low-Power Configurable Timer
*/ */
/** /**
@ -100,14 +100,14 @@ typedef struct {
* @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address. * @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_TMR_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> 0x0000</tt> */ #define MXC_R_TMR_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> 0x0000</tt> */
#define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> 0x0004</tt> */ #define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> 0x0004</tt> */
#define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> 0x0008</tt> */ #define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> 0x0008</tt> */
#define MXC_R_TMR_INTFL ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> 0x000C</tt> */ #define MXC_R_TMR_INTFL ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> 0x000C</tt> */
#define MXC_R_TMR_CTRL0 ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> 0x0010</tt> */ #define MXC_R_TMR_CTRL0 ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> 0x0010</tt> */
#define MXC_R_TMR_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt> 0x0014</tt> */ #define MXC_R_TMR_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt> 0x0014</tt> */
#define MXC_R_TMR_CTRL1 ((uint32_t)0x00000018UL) /**< Offset from TMR Base Address: <tt> 0x0018</tt> */ #define MXC_R_TMR_CTRL1 ((uint32_t)0x00000018UL) /**< Offset from TMR Base Address: <tt> 0x0018</tt> */
#define MXC_R_TMR_WKFL ((uint32_t)0x0000001CUL) /**< Offset from TMR Base Address: <tt> 0x001C</tt> */ #define MXC_R_TMR_WKFL ((uint32_t)0x0000001CUL) /**< Offset from TMR Base Address: <tt> 0x001C</tt> */
/**@} end of group tmr_registers */ /**@} end of group tmr_registers */
/** /**
@ -116,8 +116,8 @@ typedef struct {
* @brief Timer Counter Register. * @brief Timer Counter Register.
* @{ * @{
*/ */
#define MXC_F_TMR_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ #define MXC_F_TMR_CNT_COUNT_POS 0 /**< CNT_COUNT Position */
#define MXC_F_TMR_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ #define MXC_F_TMR_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CNT_COUNT_POS)) /**< CNT_COUNT Mask */
/**@} end of group TMR_CNT_Register */ /**@} end of group TMR_CNT_Register */
@ -127,8 +127,8 @@ typedef struct {
* @brief Timer Compare Register. * @brief Timer Compare Register.
* @{ * @{
*/ */
#define MXC_F_TMR_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */ #define MXC_F_TMR_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */
#define MXC_F_TMR_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */ #define MXC_F_TMR_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */
/**@} end of group TMR_CMP_Register */ /**@} end of group TMR_CMP_Register */
@ -138,8 +138,8 @@ typedef struct {
* @brief Timer PWM Register. * @brief Timer PWM Register.
* @{ * @{
*/ */
#define MXC_F_TMR_PWM_PWM_POS 0 /**< PWM_PWM Position */ #define MXC_F_TMR_PWM_PWM_POS 0 /**< PWM_PWM Position */
#define MXC_F_TMR_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_PWM_PWM_POS)) /**< PWM_PWM Mask */ #define MXC_F_TMR_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_PWM_PWM_POS)) /**< PWM_PWM Mask */
/**@} end of group TMR_PWM_Register */ /**@} end of group TMR_PWM_Register */
@ -149,23 +149,23 @@ typedef struct {
* @brief Timer Interrupt Status Register. * @brief Timer Interrupt Status Register.
* @{ * @{
*/ */
#define MXC_F_TMR_INTFL_IRQ_A_POS 0 /**< INTFL_IRQ_A Position */ #define MXC_F_TMR_INTFL_IRQ_A_POS 0 /**< INTFL_IRQ_A Position */
#define MXC_F_TMR_INTFL_IRQ_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_A_POS)) /**< INTFL_IRQ_A Mask */ #define MXC_F_TMR_INTFL_IRQ_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_A_POS)) /**< INTFL_IRQ_A Mask */
#define MXC_F_TMR_INTFL_WRDONE_A_POS 8 /**< INTFL_WRDONE_A Position */ #define MXC_F_TMR_INTFL_WRDONE_A_POS 8 /**< INTFL_WRDONE_A Position */
#define MXC_F_TMR_INTFL_WRDONE_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_A_POS)) /**< INTFL_WRDONE_A Mask */ #define MXC_F_TMR_INTFL_WRDONE_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_A_POS)) /**< INTFL_WRDONE_A Mask */
#define MXC_F_TMR_INTFL_WR_DIS_A_POS 9 /**< INTFL_WR_DIS_A Position */ #define MXC_F_TMR_INTFL_WR_DIS_A_POS 9 /**< INTFL_WR_DIS_A Position */
#define MXC_F_TMR_INTFL_WR_DIS_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_A_POS)) /**< INTFL_WR_DIS_A Mask */ #define MXC_F_TMR_INTFL_WR_DIS_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_A_POS)) /**< INTFL_WR_DIS_A Mask */
#define MXC_F_TMR_INTFL_IRQ_B_POS 16 /**< INTFL_IRQ_B Position */ #define MXC_F_TMR_INTFL_IRQ_B_POS 16 /**< INTFL_IRQ_B Position */
#define MXC_F_TMR_INTFL_IRQ_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_B_POS)) /**< INTFL_IRQ_B Mask */ #define MXC_F_TMR_INTFL_IRQ_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_B_POS)) /**< INTFL_IRQ_B Mask */
#define MXC_F_TMR_INTFL_WRDONE_B_POS 24 /**< INTFL_WRDONE_B Position */ #define MXC_F_TMR_INTFL_WRDONE_B_POS 24 /**< INTFL_WRDONE_B Position */
#define MXC_F_TMR_INTFL_WRDONE_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_B_POS)) /**< INTFL_WRDONE_B Mask */ #define MXC_F_TMR_INTFL_WRDONE_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_B_POS)) /**< INTFL_WRDONE_B Mask */
#define MXC_F_TMR_INTFL_WR_DIS_B_POS 25 /**< INTFL_WR_DIS_B Position */ #define MXC_F_TMR_INTFL_WR_DIS_B_POS 25 /**< INTFL_WR_DIS_B Position */
#define MXC_F_TMR_INTFL_WR_DIS_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_B_POS)) /**< INTFL_WR_DIS_B Mask */ #define MXC_F_TMR_INTFL_WR_DIS_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_B_POS)) /**< INTFL_WR_DIS_B Mask */
/**@} end of group TMR_INTFL_Register */ /**@} end of group TMR_INTFL_Register */
@ -175,157 +175,157 @@ typedef struct {
* @brief Timer Control Register. * @brief Timer Control Register.
* @{ * @{
*/ */
#define MXC_F_TMR_CTRL0_MODE_A_POS 0 /**< CTRL0_MODE_A Position */ #define MXC_F_TMR_CTRL0_MODE_A_POS 0 /**< CTRL0_MODE_A Position */
#define MXC_F_TMR_CTRL0_MODE_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_A_POS)) /**< CTRL0_MODE_A Mask */ #define MXC_F_TMR_CTRL0_MODE_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_A_POS)) /**< CTRL0_MODE_A Mask */
#define MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_A_ONE_SHOT Value */ #define MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_A_ONE_SHOT Value */
#define MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_ONE_SHOT Setting */ #define MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_ONE_SHOT Setting */
#define MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_A_CONTINUOUS Value */ #define MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_A_CONTINUOUS Value */
#define MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CONTINUOUS Setting */ #define MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CONTINUOUS Setting */
#define MXC_V_TMR_CTRL0_MODE_A_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_A_COUNTER Value */ #define MXC_V_TMR_CTRL0_MODE_A_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_A_COUNTER Value */
#define MXC_S_TMR_CTRL0_MODE_A_COUNTER (MXC_V_TMR_CTRL0_MODE_A_COUNTER << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COUNTER Setting */ #define MXC_S_TMR_CTRL0_MODE_A_COUNTER (MXC_V_TMR_CTRL0_MODE_A_COUNTER << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COUNTER Setting */
#define MXC_V_TMR_CTRL0_MODE_A_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_A_PWM Value */ #define MXC_V_TMR_CTRL0_MODE_A_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_A_PWM Value */
#define MXC_S_TMR_CTRL0_MODE_A_PWM (MXC_V_TMR_CTRL0_MODE_A_PWM << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_PWM Setting */ #define MXC_S_TMR_CTRL0_MODE_A_PWM (MXC_V_TMR_CTRL0_MODE_A_PWM << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_PWM Setting */
#define MXC_V_TMR_CTRL0_MODE_A_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_A_CAPTURE Value */ #define MXC_V_TMR_CTRL0_MODE_A_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_A_CAPTURE Value */
#define MXC_S_TMR_CTRL0_MODE_A_CAPTURE (MXC_V_TMR_CTRL0_MODE_A_CAPTURE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPTURE Setting */ #define MXC_S_TMR_CTRL0_MODE_A_CAPTURE (MXC_V_TMR_CTRL0_MODE_A_CAPTURE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPTURE Setting */
#define MXC_V_TMR_CTRL0_MODE_A_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_A_COMPARE Value */ #define MXC_V_TMR_CTRL0_MODE_A_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_A_COMPARE Value */
#define MXC_S_TMR_CTRL0_MODE_A_COMPARE (MXC_V_TMR_CTRL0_MODE_A_COMPARE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COMPARE Setting */ #define MXC_S_TMR_CTRL0_MODE_A_COMPARE (MXC_V_TMR_CTRL0_MODE_A_COMPARE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COMPARE Setting */
#define MXC_V_TMR_CTRL0_MODE_A_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_A_GATED Value */ #define MXC_V_TMR_CTRL0_MODE_A_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_A_GATED Value */
#define MXC_S_TMR_CTRL0_MODE_A_GATED (MXC_V_TMR_CTRL0_MODE_A_GATED << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_GATED Setting */ #define MXC_S_TMR_CTRL0_MODE_A_GATED (MXC_V_TMR_CTRL0_MODE_A_GATED << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_GATED Setting */
#define MXC_V_TMR_CTRL0_MODE_A_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_A_CAPCOMP Value */ #define MXC_V_TMR_CTRL0_MODE_A_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_A_CAPCOMP Value */
#define MXC_S_TMR_CTRL0_MODE_A_CAPCOMP (MXC_V_TMR_CTRL0_MODE_A_CAPCOMP << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPCOMP Setting */ #define MXC_S_TMR_CTRL0_MODE_A_CAPCOMP (MXC_V_TMR_CTRL0_MODE_A_CAPCOMP << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPCOMP Setting */
#define MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_A_DUAL_EDGE Value */ #define MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_A_DUAL_EDGE Value */
#define MXC_S_TMR_CTRL0_MODE_A_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_DUAL_EDGE Setting */ #define MXC_S_TMR_CTRL0_MODE_A_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_DUAL_EDGE Setting */
#define MXC_V_TMR_CTRL0_MODE_A_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_A_IGATED Value */ #define MXC_V_TMR_CTRL0_MODE_A_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_A_IGATED Value */
#define MXC_S_TMR_CTRL0_MODE_A_IGATED (MXC_V_TMR_CTRL0_MODE_A_IGATED << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_IGATED Setting */ #define MXC_S_TMR_CTRL0_MODE_A_IGATED (MXC_V_TMR_CTRL0_MODE_A_IGATED << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_IGATED Setting */
#define MXC_F_TMR_CTRL0_CLKDIV_A_POS 4 /**< CTRL0_CLKDIV_A Position */ #define MXC_F_TMR_CTRL0_CLKDIV_A_POS 4 /**< CTRL0_CLKDIV_A Position */
#define MXC_F_TMR_CTRL0_CLKDIV_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_A_POS)) /**< CTRL0_CLKDIV_A Mask */ #define MXC_F_TMR_CTRL0_CLKDIV_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_A_POS)) /**< CTRL0_CLKDIV_A Mask */
#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_A_DIV_BY_1 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_A_DIV_BY_1 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_A_DIV_BY_2 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_A_DIV_BY_2 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_A_DIV_BY_4 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_A_DIV_BY_4 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_A_DIV_BY_8 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_A_DIV_BY_8 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_8 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_8 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_A_DIV_BY_16 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_A_DIV_BY_16 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_16 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_16 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_A_DIV_BY_32 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_A_DIV_BY_32 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_32 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_32 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_A_DIV_BY_64 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_A_DIV_BY_64 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_64 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_64 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_A_DIV_BY_128 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_A_DIV_BY_128 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_128 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_128 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_A_DIV_BY_256 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_A_DIV_BY_256 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_256 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_256 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_A_DIV_BY_512 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_A_DIV_BY_512 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_512 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_512 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Setting */
#define MXC_F_TMR_CTRL0_POL_A_POS 8 /**< CTRL0_POL_A Position */ #define MXC_F_TMR_CTRL0_POL_A_POS 8 /**< CTRL0_POL_A Position */
#define MXC_F_TMR_CTRL0_POL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_A_POS)) /**< CTRL0_POL_A Mask */ #define MXC_F_TMR_CTRL0_POL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_A_POS)) /**< CTRL0_POL_A Mask */
#define MXC_F_TMR_CTRL0_PWMSYNC_A_POS 9 /**< CTRL0_PWMSYNC_A Position */ #define MXC_F_TMR_CTRL0_PWMSYNC_A_POS 9 /**< CTRL0_PWMSYNC_A Position */
#define MXC_F_TMR_CTRL0_PWMSYNC_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_A_POS)) /**< CTRL0_PWMSYNC_A Mask */ #define MXC_F_TMR_CTRL0_PWMSYNC_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_A_POS)) /**< CTRL0_PWMSYNC_A Mask */
#define MXC_F_TMR_CTRL0_NOLHPOL_A_POS 10 /**< CTRL0_NOLHPOL_A Position */ #define MXC_F_TMR_CTRL0_NOLHPOL_A_POS 10 /**< CTRL0_NOLHPOL_A Position */
#define MXC_F_TMR_CTRL0_NOLHPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_A_POS)) /**< CTRL0_NOLHPOL_A Mask */ #define MXC_F_TMR_CTRL0_NOLHPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_A_POS)) /**< CTRL0_NOLHPOL_A Mask */
#define MXC_F_TMR_CTRL0_NOLLPOL_A_POS 11 /**< CTRL0_NOLLPOL_A Position */ #define MXC_F_TMR_CTRL0_NOLLPOL_A_POS 11 /**< CTRL0_NOLLPOL_A Position */
#define MXC_F_TMR_CTRL0_NOLLPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_A_POS)) /**< CTRL0_NOLLPOL_A Mask */ #define MXC_F_TMR_CTRL0_NOLLPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_A_POS)) /**< CTRL0_NOLLPOL_A Mask */
#define MXC_F_TMR_CTRL0_PWMCKBD_A_POS 12 /**< CTRL0_PWMCKBD_A Position */ #define MXC_F_TMR_CTRL0_PWMCKBD_A_POS 12 /**< CTRL0_PWMCKBD_A Position */
#define MXC_F_TMR_CTRL0_PWMCKBD_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_A_POS)) /**< CTRL0_PWMCKBD_A Mask */ #define MXC_F_TMR_CTRL0_PWMCKBD_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_A_POS)) /**< CTRL0_PWMCKBD_A Mask */
#define MXC_F_TMR_CTRL0_RST_A_POS 13 /**< CTRL0_RST_A Position */ #define MXC_F_TMR_CTRL0_RST_A_POS 13 /**< CTRL0_RST_A Position */
#define MXC_F_TMR_CTRL0_RST_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_A_POS)) /**< CTRL0_RST_A Mask */ #define MXC_F_TMR_CTRL0_RST_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_A_POS)) /**< CTRL0_RST_A Mask */
#define MXC_F_TMR_CTRL0_CLKEN_A_POS 14 /**< CTRL0_CLKEN_A Position */ #define MXC_F_TMR_CTRL0_CLKEN_A_POS 14 /**< CTRL0_CLKEN_A Position */
#define MXC_F_TMR_CTRL0_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_A_POS)) /**< CTRL0_CLKEN_A Mask */ #define MXC_F_TMR_CTRL0_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_A_POS)) /**< CTRL0_CLKEN_A Mask */
#define MXC_F_TMR_CTRL0_EN_A_POS 15 /**< CTRL0_EN_A Position */ #define MXC_F_TMR_CTRL0_EN_A_POS 15 /**< CTRL0_EN_A Position */
#define MXC_F_TMR_CTRL0_EN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_A_POS)) /**< CTRL0_EN_A Mask */ #define MXC_F_TMR_CTRL0_EN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_A_POS)) /**< CTRL0_EN_A Mask */
#define MXC_F_TMR_CTRL0_MODE_B_POS 16 /**< CTRL0_MODE_B Position */ #define MXC_F_TMR_CTRL0_MODE_B_POS 16 /**< CTRL0_MODE_B Position */
#define MXC_F_TMR_CTRL0_MODE_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_B_POS)) /**< CTRL0_MODE_B Mask */ #define MXC_F_TMR_CTRL0_MODE_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_B_POS)) /**< CTRL0_MODE_B Mask */
#define MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_B_ONE_SHOT Value */ #define MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_B_ONE_SHOT Value */
#define MXC_S_TMR_CTRL0_MODE_B_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_ONE_SHOT Setting */ #define MXC_S_TMR_CTRL0_MODE_B_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_ONE_SHOT Setting */
#define MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_B_CONTINUOUS Value */ #define MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_B_CONTINUOUS Value */
#define MXC_S_TMR_CTRL0_MODE_B_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CONTINUOUS Setting */ #define MXC_S_TMR_CTRL0_MODE_B_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CONTINUOUS Setting */
#define MXC_V_TMR_CTRL0_MODE_B_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_B_COUNTER Value */ #define MXC_V_TMR_CTRL0_MODE_B_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_B_COUNTER Value */
#define MXC_S_TMR_CTRL0_MODE_B_COUNTER (MXC_V_TMR_CTRL0_MODE_B_COUNTER << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COUNTER Setting */ #define MXC_S_TMR_CTRL0_MODE_B_COUNTER (MXC_V_TMR_CTRL0_MODE_B_COUNTER << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COUNTER Setting */
#define MXC_V_TMR_CTRL0_MODE_B_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_B_PWM Value */ #define MXC_V_TMR_CTRL0_MODE_B_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_B_PWM Value */
#define MXC_S_TMR_CTRL0_MODE_B_PWM (MXC_V_TMR_CTRL0_MODE_B_PWM << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_PWM Setting */ #define MXC_S_TMR_CTRL0_MODE_B_PWM (MXC_V_TMR_CTRL0_MODE_B_PWM << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_PWM Setting */
#define MXC_V_TMR_CTRL0_MODE_B_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_B_CAPTURE Value */ #define MXC_V_TMR_CTRL0_MODE_B_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_B_CAPTURE Value */
#define MXC_S_TMR_CTRL0_MODE_B_CAPTURE (MXC_V_TMR_CTRL0_MODE_B_CAPTURE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPTURE Setting */ #define MXC_S_TMR_CTRL0_MODE_B_CAPTURE (MXC_V_TMR_CTRL0_MODE_B_CAPTURE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPTURE Setting */
#define MXC_V_TMR_CTRL0_MODE_B_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_B_COMPARE Value */ #define MXC_V_TMR_CTRL0_MODE_B_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_B_COMPARE Value */
#define MXC_S_TMR_CTRL0_MODE_B_COMPARE (MXC_V_TMR_CTRL0_MODE_B_COMPARE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COMPARE Setting */ #define MXC_S_TMR_CTRL0_MODE_B_COMPARE (MXC_V_TMR_CTRL0_MODE_B_COMPARE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COMPARE Setting */
#define MXC_V_TMR_CTRL0_MODE_B_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_B_GATED Value */ #define MXC_V_TMR_CTRL0_MODE_B_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_B_GATED Value */
#define MXC_S_TMR_CTRL0_MODE_B_GATED (MXC_V_TMR_CTRL0_MODE_B_GATED << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_GATED Setting */ #define MXC_S_TMR_CTRL0_MODE_B_GATED (MXC_V_TMR_CTRL0_MODE_B_GATED << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_GATED Setting */
#define MXC_V_TMR_CTRL0_MODE_B_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_B_CAPCOMP Value */ #define MXC_V_TMR_CTRL0_MODE_B_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_B_CAPCOMP Value */
#define MXC_S_TMR_CTRL0_MODE_B_CAPCOMP (MXC_V_TMR_CTRL0_MODE_B_CAPCOMP << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPCOMP Setting */ #define MXC_S_TMR_CTRL0_MODE_B_CAPCOMP (MXC_V_TMR_CTRL0_MODE_B_CAPCOMP << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPCOMP Setting */
#define MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_B_DUAL_EDGE Value */ #define MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_B_DUAL_EDGE Value */
#define MXC_S_TMR_CTRL0_MODE_B_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_DUAL_EDGE Setting */ #define MXC_S_TMR_CTRL0_MODE_B_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_DUAL_EDGE Setting */
#define MXC_V_TMR_CTRL0_MODE_B_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_B_IGATED Value */ #define MXC_V_TMR_CTRL0_MODE_B_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_B_IGATED Value */
#define MXC_S_TMR_CTRL0_MODE_B_IGATED (MXC_V_TMR_CTRL0_MODE_B_IGATED << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_IGATED Setting */ #define MXC_S_TMR_CTRL0_MODE_B_IGATED (MXC_V_TMR_CTRL0_MODE_B_IGATED << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_IGATED Setting */
#define MXC_F_TMR_CTRL0_CLKDIV_B_POS 20 /**< CTRL0_CLKDIV_B Position */ #define MXC_F_TMR_CTRL0_CLKDIV_B_POS 20 /**< CTRL0_CLKDIV_B Position */
#define MXC_F_TMR_CTRL0_CLKDIV_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_B_POS)) /**< CTRL0_CLKDIV_B Mask */ #define MXC_F_TMR_CTRL0_CLKDIV_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_B_POS)) /**< CTRL0_CLKDIV_B Mask */
#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_B_DIV_BY_1 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_B_DIV_BY_1 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_B_DIV_BY_2 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_B_DIV_BY_2 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_B_DIV_BY_4 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_B_DIV_BY_4 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_B_DIV_BY_8 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_B_DIV_BY_8 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_8 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_8 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_B_DIV_BY_16 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_B_DIV_BY_16 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_16 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_16 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_B_DIV_BY_32 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_B_DIV_BY_32 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_32 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_32 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_B_DIV_BY_64 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_B_DIV_BY_64 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_64 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_64 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_B_DIV_BY_128 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_B_DIV_BY_128 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_128 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_128 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_B_DIV_BY_256 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_B_DIV_BY_256 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_256 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_256 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_B_DIV_BY_512 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_B_DIV_BY_512 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_512 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_512 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Setting */
#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Value */ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Value */
#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Setting */ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Setting */
#define MXC_F_TMR_CTRL0_POL_B_POS 24 /**< CTRL0_POL_B Position */ #define MXC_F_TMR_CTRL0_POL_B_POS 24 /**< CTRL0_POL_B Position */
#define MXC_F_TMR_CTRL0_POL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_B_POS)) /**< CTRL0_POL_B Mask */ #define MXC_F_TMR_CTRL0_POL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_B_POS)) /**< CTRL0_POL_B Mask */
#define MXC_F_TMR_CTRL0_PWMSYNC_B_POS 25 /**< CTRL0_PWMSYNC_B Position */ #define MXC_F_TMR_CTRL0_PWMSYNC_B_POS 25 /**< CTRL0_PWMSYNC_B Position */
#define MXC_F_TMR_CTRL0_PWMSYNC_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_B_POS)) /**< CTRL0_PWMSYNC_B Mask */ #define MXC_F_TMR_CTRL0_PWMSYNC_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_B_POS)) /**< CTRL0_PWMSYNC_B Mask */
#define MXC_F_TMR_CTRL0_NOLHPOL_B_POS 26 /**< CTRL0_NOLHPOL_B Position */ #define MXC_F_TMR_CTRL0_NOLHPOL_B_POS 26 /**< CTRL0_NOLHPOL_B Position */
#define MXC_F_TMR_CTRL0_NOLHPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_B_POS)) /**< CTRL0_NOLHPOL_B Mask */ #define MXC_F_TMR_CTRL0_NOLHPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_B_POS)) /**< CTRL0_NOLHPOL_B Mask */
#define MXC_F_TMR_CTRL0_NOLLPOL_B_POS 27 /**< CTRL0_NOLLPOL_B Position */ #define MXC_F_TMR_CTRL0_NOLLPOL_B_POS 27 /**< CTRL0_NOLLPOL_B Position */
#define MXC_F_TMR_CTRL0_NOLLPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_B_POS)) /**< CTRL0_NOLLPOL_B Mask */ #define MXC_F_TMR_CTRL0_NOLLPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_B_POS)) /**< CTRL0_NOLLPOL_B Mask */
#define MXC_F_TMR_CTRL0_PWMCKBD_B_POS 28 /**< CTRL0_PWMCKBD_B Position */ #define MXC_F_TMR_CTRL0_PWMCKBD_B_POS 28 /**< CTRL0_PWMCKBD_B Position */
#define MXC_F_TMR_CTRL0_PWMCKBD_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_B_POS)) /**< CTRL0_PWMCKBD_B Mask */ #define MXC_F_TMR_CTRL0_PWMCKBD_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_B_POS)) /**< CTRL0_PWMCKBD_B Mask */
#define MXC_F_TMR_CTRL0_RST_B_POS 29 /**< CTRL0_RST_B Position */ #define MXC_F_TMR_CTRL0_RST_B_POS 29 /**< CTRL0_RST_B Position */
#define MXC_F_TMR_CTRL0_RST_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_B_POS)) /**< CTRL0_RST_B Mask */ #define MXC_F_TMR_CTRL0_RST_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_B_POS)) /**< CTRL0_RST_B Mask */
#define MXC_F_TMR_CTRL0_CLKEN_B_POS 30 /**< CTRL0_CLKEN_B Position */ #define MXC_F_TMR_CTRL0_CLKEN_B_POS 30 /**< CTRL0_CLKEN_B Position */
#define MXC_F_TMR_CTRL0_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_B_POS)) /**< CTRL0_CLKEN_B Mask */ #define MXC_F_TMR_CTRL0_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_B_POS)) /**< CTRL0_CLKEN_B Mask */
#define MXC_F_TMR_CTRL0_EN_B_POS 31 /**< CTRL0_EN_B Position */ #define MXC_F_TMR_CTRL0_EN_B_POS 31 /**< CTRL0_EN_B Position */
#define MXC_F_TMR_CTRL0_EN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_B_POS)) /**< CTRL0_EN_B Mask */ #define MXC_F_TMR_CTRL0_EN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_B_POS)) /**< CTRL0_EN_B Mask */
/**@} end of group TMR_CTRL0_Register */ /**@} end of group TMR_CTRL0_Register */
@ -335,17 +335,17 @@ typedef struct {
* @brief Timer Non-Overlapping Compare Register. * @brief Timer Non-Overlapping Compare Register.
* @{ * @{
*/ */
#define MXC_F_TMR_NOLCMP_LO_A_POS 0 /**< NOLCMP_LO_A Position */ #define MXC_F_TMR_NOLCMP_LO_A_POS 0 /**< NOLCMP_LO_A Position */
#define MXC_F_TMR_NOLCMP_LO_A ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_A_POS)) /**< NOLCMP_LO_A Mask */ #define MXC_F_TMR_NOLCMP_LO_A ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_A_POS)) /**< NOLCMP_LO_A Mask */
#define MXC_F_TMR_NOLCMP_HI_A_POS 8 /**< NOLCMP_HI_A Position */ #define MXC_F_TMR_NOLCMP_HI_A_POS 8 /**< NOLCMP_HI_A Position */
#define MXC_F_TMR_NOLCMP_HI_A ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_A_POS)) /**< NOLCMP_HI_A Mask */ #define MXC_F_TMR_NOLCMP_HI_A ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_A_POS)) /**< NOLCMP_HI_A Mask */
#define MXC_F_TMR_NOLCMP_LO_B_POS 16 /**< NOLCMP_LO_B Position */ #define MXC_F_TMR_NOLCMP_LO_B_POS 16 /**< NOLCMP_LO_B Position */
#define MXC_F_TMR_NOLCMP_LO_B ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_B_POS)) /**< NOLCMP_LO_B Mask */ #define MXC_F_TMR_NOLCMP_LO_B ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_B_POS)) /**< NOLCMP_LO_B Mask */
#define MXC_F_TMR_NOLCMP_HI_B_POS 24 /**< NOLCMP_HI_B Position */ #define MXC_F_TMR_NOLCMP_HI_B_POS 24 /**< NOLCMP_HI_B Position */
#define MXC_F_TMR_NOLCMP_HI_B ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_B_POS)) /**< NOLCMP_HI_B Mask */ #define MXC_F_TMR_NOLCMP_HI_B ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_B_POS)) /**< NOLCMP_HI_B Mask */
/**@} end of group TMR_NOLCMP_Register */ /**@} end of group TMR_NOLCMP_Register */
@ -355,68 +355,68 @@ typedef struct {
* @brief Timer Configuration Register. * @brief Timer Configuration Register.
* @{ * @{
*/ */
#define MXC_F_TMR_CTRL1_CLKSEL_A_POS 0 /**< CTRL1_CLKSEL_A Position */ #define MXC_F_TMR_CTRL1_CLKSEL_A_POS 0 /**< CTRL1_CLKSEL_A Position */
#define MXC_F_TMR_CTRL1_CLKSEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_A_POS)) /**< CTRL1_CLKSEL_A Mask */ #define MXC_F_TMR_CTRL1_CLKSEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_A_POS)) /**< CTRL1_CLKSEL_A Mask */
#define MXC_F_TMR_CTRL1_CLKEN_A_POS 2 /**< CTRL1_CLKEN_A Position */ #define MXC_F_TMR_CTRL1_CLKEN_A_POS 2 /**< CTRL1_CLKEN_A Position */
#define MXC_F_TMR_CTRL1_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_A_POS)) /**< CTRL1_CLKEN_A Mask */ #define MXC_F_TMR_CTRL1_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_A_POS)) /**< CTRL1_CLKEN_A Mask */
#define MXC_F_TMR_CTRL1_CLKRDY_A_POS 3 /**< CTRL1_CLKRDY_A Position */ #define MXC_F_TMR_CTRL1_CLKRDY_A_POS 3 /**< CTRL1_CLKRDY_A Position */
#define MXC_F_TMR_CTRL1_CLKRDY_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_A_POS)) /**< CTRL1_CLKRDY_A Mask */ #define MXC_F_TMR_CTRL1_CLKRDY_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_A_POS)) /**< CTRL1_CLKRDY_A Mask */
#define MXC_F_TMR_CTRL1_EVENT_SEL_A_POS 4 /**< CTRL1_EVENT_SEL_A Position */ #define MXC_F_TMR_CTRL1_EVENT_SEL_A_POS 4 /**< CTRL1_EVENT_SEL_A Position */
#define MXC_F_TMR_CTRL1_EVENT_SEL_A ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_A_POS)) /**< CTRL1_EVENT_SEL_A Mask */ #define MXC_F_TMR_CTRL1_EVENT_SEL_A ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_A_POS)) /**< CTRL1_EVENT_SEL_A Mask */
#define MXC_F_TMR_CTRL1_NEGTRIG_A_POS 7 /**< CTRL1_NEGTRIG_A Position */ #define MXC_F_TMR_CTRL1_NEGTRIG_A_POS 7 /**< CTRL1_NEGTRIG_A Position */
#define MXC_F_TMR_CTRL1_NEGTRIG_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_A_POS)) /**< CTRL1_NEGTRIG_A Mask */ #define MXC_F_TMR_CTRL1_NEGTRIG_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_A_POS)) /**< CTRL1_NEGTRIG_A Mask */
#define MXC_F_TMR_CTRL1_IE_A_POS 8 /**< CTRL1_IE_A Position */ #define MXC_F_TMR_CTRL1_IE_A_POS 8 /**< CTRL1_IE_A Position */
#define MXC_F_TMR_CTRL1_IE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_A_POS)) /**< CTRL1_IE_A Mask */ #define MXC_F_TMR_CTRL1_IE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_A_POS)) /**< CTRL1_IE_A Mask */
#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS 9 /**< CTRL1_CAPEVENT_SEL_A Position */ #define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS 9 /**< CTRL1_CAPEVENT_SEL_A Position */
#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS)) /**< CTRL1_CAPEVENT_SEL_A Mask */ #define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS)) /**< CTRL1_CAPEVENT_SEL_A Mask */
#define MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS 11 /**< CTRL1_SW_CAPEVENT_A Position */ #define MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS 11 /**< CTRL1_SW_CAPEVENT_A Position */
#define MXC_F_TMR_CTRL1_SW_CAPEVENT_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS)) /**< CTRL1_SW_CAPEVENT_A Mask */ #define MXC_F_TMR_CTRL1_SW_CAPEVENT_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS)) /**< CTRL1_SW_CAPEVENT_A Mask */
#define MXC_F_TMR_CTRL1_WE_A_POS 12 /**< CTRL1_WE_A Position */ #define MXC_F_TMR_CTRL1_WE_A_POS 12 /**< CTRL1_WE_A Position */
#define MXC_F_TMR_CTRL1_WE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_A_POS)) /**< CTRL1_WE_A Mask */ #define MXC_F_TMR_CTRL1_WE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_A_POS)) /**< CTRL1_WE_A Mask */
#define MXC_F_TMR_CTRL1_OUTEN_A_POS 13 /**< CTRL1_OUTEN_A Position */ #define MXC_F_TMR_CTRL1_OUTEN_A_POS 13 /**< CTRL1_OUTEN_A Position */
#define MXC_F_TMR_CTRL1_OUTEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTEN_A_POS)) /**< CTRL1_OUTEN_A Mask */ #define MXC_F_TMR_CTRL1_OUTEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTEN_A_POS)) /**< CTRL1_OUTEN_A Mask */
#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */ #define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */ #define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */
#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */ #define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */ #define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */
#define MXC_F_TMR_CTRL1_CLKEN_B_POS 18 /**< CTRL1_CLKEN_B Position */ #define MXC_F_TMR_CTRL1_CLKEN_B_POS 18 /**< CTRL1_CLKEN_B Position */
#define MXC_F_TMR_CTRL1_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_B_POS)) /**< CTRL1_CLKEN_B Mask */ #define MXC_F_TMR_CTRL1_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_B_POS)) /**< CTRL1_CLKEN_B Mask */
#define MXC_F_TMR_CTRL1_CLKRDY_B_POS 19 /**< CTRL1_CLKRDY_B Position */ #define MXC_F_TMR_CTRL1_CLKRDY_B_POS 19 /**< CTRL1_CLKRDY_B Position */
#define MXC_F_TMR_CTRL1_CLKRDY_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_B_POS)) /**< CTRL1_CLKRDY_B Mask */ #define MXC_F_TMR_CTRL1_CLKRDY_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_B_POS)) /**< CTRL1_CLKRDY_B Mask */
#define MXC_F_TMR_CTRL1_EVENT_SEL_B_POS 20 /**< CTRL1_EVENT_SEL_B Position */ #define MXC_F_TMR_CTRL1_EVENT_SEL_B_POS 20 /**< CTRL1_EVENT_SEL_B Position */
#define MXC_F_TMR_CTRL1_EVENT_SEL_B ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_B_POS)) /**< CTRL1_EVENT_SEL_B Mask */ #define MXC_F_TMR_CTRL1_EVENT_SEL_B ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_B_POS)) /**< CTRL1_EVENT_SEL_B Mask */
#define MXC_F_TMR_CTRL1_NEGTRIG_B_POS 23 /**< CTRL1_NEGTRIG_B Position */ #define MXC_F_TMR_CTRL1_NEGTRIG_B_POS 23 /**< CTRL1_NEGTRIG_B Position */
#define MXC_F_TMR_CTRL1_NEGTRIG_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_B_POS)) /**< CTRL1_NEGTRIG_B Mask */ #define MXC_F_TMR_CTRL1_NEGTRIG_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_B_POS)) /**< CTRL1_NEGTRIG_B Mask */
#define MXC_F_TMR_CTRL1_IE_B_POS 24 /**< CTRL1_IE_B Position */ #define MXC_F_TMR_CTRL1_IE_B_POS 24 /**< CTRL1_IE_B Position */
#define MXC_F_TMR_CTRL1_IE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_B_POS)) /**< CTRL1_IE_B Mask */ #define MXC_F_TMR_CTRL1_IE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_B_POS)) /**< CTRL1_IE_B Mask */
#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS 25 /**< CTRL1_CAPEVENT_SEL_B Position */ #define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS 25 /**< CTRL1_CAPEVENT_SEL_B Position */
#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS)) /**< CTRL1_CAPEVENT_SEL_B Mask */ #define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS)) /**< CTRL1_CAPEVENT_SEL_B Mask */
#define MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS 27 /**< CTRL1_SW_CAPEVENT_B Position */ #define MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS 27 /**< CTRL1_SW_CAPEVENT_B Position */
#define MXC_F_TMR_CTRL1_SW_CAPEVENT_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS)) /**< CTRL1_SW_CAPEVENT_B Mask */ #define MXC_F_TMR_CTRL1_SW_CAPEVENT_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS)) /**< CTRL1_SW_CAPEVENT_B Mask */
#define MXC_F_TMR_CTRL1_WE_B_POS 28 /**< CTRL1_WE_B Position */ #define MXC_F_TMR_CTRL1_WE_B_POS 28 /**< CTRL1_WE_B Position */
#define MXC_F_TMR_CTRL1_WE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_B_POS)) /**< CTRL1_WE_B Mask */ #define MXC_F_TMR_CTRL1_WE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_B_POS)) /**< CTRL1_WE_B Mask */
#define MXC_F_TMR_CTRL1_CASCADE_POS 31 /**< CTRL1_CASCADE Position */ #define MXC_F_TMR_CTRL1_CASCADE_POS 31 /**< CTRL1_CASCADE Position */
#define MXC_F_TMR_CTRL1_CASCADE ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CASCADE_POS)) /**< CTRL1_CASCADE Mask */ #define MXC_F_TMR_CTRL1_CASCADE ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CASCADE_POS)) /**< CTRL1_CASCADE Mask */
/**@} end of group TMR_CTRL1_Register */ /**@} end of group TMR_CTRL1_Register */
@ -426,11 +426,11 @@ typedef struct {
* @brief Timer Wakeup Status Register. * @brief Timer Wakeup Status Register.
* @{ * @{
*/ */
#define MXC_F_TMR_WKFL_A_POS 0 /**< WKFL_A Position */ #define MXC_F_TMR_WKFL_A_POS 0 /**< WKFL_A Position */
#define MXC_F_TMR_WKFL_A ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_A_POS)) /**< WKFL_A Mask */ #define MXC_F_TMR_WKFL_A ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_A_POS)) /**< WKFL_A Mask */
#define MXC_F_TMR_WKFL_B_POS 16 /**< WKFL_B Position */ #define MXC_F_TMR_WKFL_B_POS 16 /**< WKFL_B Position */
#define MXC_F_TMR_WKFL_B ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_B_POS)) /**< WKFL_B Mask */ #define MXC_F_TMR_WKFL_B ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_B_POS)) /**< WKFL_B Mask */
/**@} end of group TMR_WKFL_Register */ /**@} end of group TMR_WKFL_Register */
@ -438,4 +438,4 @@ typedef struct {
} }
#endif #endif
#endif /* _TMR_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_TMR_REGS_H_

68
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/trng_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file trng_regs.h * @file trng_regs.h
* @brief Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _TRNG_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_TRNG_REGS_H_
#define _TRNG_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_TRNG_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup trng * @ingroup trng
* @defgroup trng_registers TRNG_Registers * @defgroup trng_registers TRNG_Registers
* @brief Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module.
* @details Random Number Generator. * @details Random Number Generator.
*/ */
/** /**
@ -84,7 +84,7 @@ extern "C" {
*/ */
typedef struct { typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> TRNG CTRL Register */ __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> TRNG CTRL Register */
__I uint32_t status; /**< <tt>\b 0x04:</tt> TRNG STATUS Register */ __IO uint32_t status; /**< <tt>\b 0x04:</tt> TRNG STATUS Register */
__I uint32_t data; /**< <tt>\b 0x08:</tt> TRNG DATA Register */ __I uint32_t data; /**< <tt>\b 0x08:</tt> TRNG DATA Register */
} mxc_trng_regs_t; } mxc_trng_regs_t;
@ -95,9 +95,9 @@ typedef struct {
* @brief TRNG Peripheral Register Offsets from the TRNG Base Peripheral Address. * @brief TRNG Peripheral Register Offsets from the TRNG Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_TRNG_CTRL ((uint32_t)0x00000000UL) /**< Offset from TRNG Base Address: <tt> 0x0000</tt> */ #define MXC_R_TRNG_CTRL ((uint32_t)0x00000000UL) /**< Offset from TRNG Base Address: <tt> 0x0000</tt> */
#define MXC_R_TRNG_STATUS ((uint32_t)0x00000004UL) /**< Offset from TRNG Base Address: <tt> 0x0004</tt> */ #define MXC_R_TRNG_STATUS ((uint32_t)0x00000004UL) /**< Offset from TRNG Base Address: <tt> 0x0004</tt> */
#define MXC_R_TRNG_DATA ((uint32_t)0x00000008UL) /**< Offset from TRNG Base Address: <tt> 0x0008</tt> */ #define MXC_R_TRNG_DATA ((uint32_t)0x00000008UL) /**< Offset from TRNG Base Address: <tt> 0x0008</tt> */
/**@} end of group trng_registers */ /**@} end of group trng_registers */
/** /**
@ -106,14 +106,23 @@ typedef struct {
* @brief TRNG Control Register. * @brief TRNG Control Register.
* @{ * @{
*/ */
#define MXC_F_TRNG_CTRL_RND_IE_POS 1 /**< CTRL_RND_IE Position */ #define MXC_F_TRNG_CTRL_ODHT_POS 0 /**< CTRL_ODHT Position */
#define MXC_F_TRNG_CTRL_RND_IE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_RND_IE_POS)) /**< CTRL_RND_IE Mask */ #define MXC_F_TRNG_CTRL_ODHT ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_ODHT_POS)) /**< CTRL_ODHT Mask */
#define MXC_F_TRNG_CTRL_KEYGEN_POS 3 /**< CTRL_KEYGEN Position */ #define MXC_F_TRNG_CTRL_RND_IE_POS 1 /**< CTRL_RND_IE Position */
#define MXC_F_TRNG_CTRL_KEYGEN ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_KEYGEN_POS)) /**< CTRL_KEYGEN Mask */ #define MXC_F_TRNG_CTRL_RND_IE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_RND_IE_POS)) /**< CTRL_RND_IE Mask */
#define MXC_F_TRNG_CTRL_KEYWIPE_POS 15 /**< CTRL_KEYWIPE Position */ #define MXC_F_TRNG_CTRL_HEALTH_EN_POS 2 /**< CTRL_HEALTH_EN Position */
#define MXC_F_TRNG_CTRL_KEYWIPE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_KEYWIPE_POS)) /**< CTRL_KEYWIPE Mask */ #define MXC_F_TRNG_CTRL_HEALTH_EN ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_HEALTH_EN_POS)) /**< CTRL_HEALTH_EN Mask */
#define MXC_F_TRNG_CTRL_AESKG_USR_POS 3 /**< CTRL_AESKG_USR Position */
#define MXC_F_TRNG_CTRL_AESKG_USR ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_AESKG_USR_POS)) /**< CTRL_AESKG_USR Mask */
#define MXC_F_TRNG_CTRL_AESKG_SYS_POS 4 /**< CTRL_AESKG_SYS Position */
#define MXC_F_TRNG_CTRL_AESKG_SYS ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_AESKG_SYS_POS)) /**< CTRL_AESKG_SYS Mask */
#define MXC_F_TRNG_CTRL_KEYWIPE_POS 15 /**< CTRL_KEYWIPE Position */
#define MXC_F_TRNG_CTRL_KEYWIPE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_KEYWIPE_POS)) /**< CTRL_KEYWIPE Mask */
/**@} end of group TRNG_CTRL_Register */ /**@} end of group TRNG_CTRL_Register */
@ -124,8 +133,23 @@ typedef struct {
* disabled, read returns 0x0000 0000. * disabled, read returns 0x0000 0000.
* @{ * @{
*/ */
#define MXC_F_TRNG_STATUS_RDY_POS 0 /**< STATUS_RDY Position */ #define MXC_F_TRNG_STATUS_RDY_POS 0 /**< STATUS_RDY Position */
#define MXC_F_TRNG_STATUS_RDY ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_RDY_POS)) /**< STATUS_RDY Mask */ #define MXC_F_TRNG_STATUS_RDY ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_RDY_POS)) /**< STATUS_RDY Mask */
#define MXC_F_TRNG_STATUS_ODHT_POS 1 /**< STATUS_ODHT Position */
#define MXC_F_TRNG_STATUS_ODHT ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ODHT_POS)) /**< STATUS_ODHT Mask */
#define MXC_F_TRNG_STATUS_HT_POS 2 /**< STATUS_HT Position */
#define MXC_F_TRNG_STATUS_HT ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_HT_POS)) /**< STATUS_HT Mask */
#define MXC_F_TRNG_STATUS_SRCFAIL_POS 3 /**< STATUS_SRCFAIL Position */
#define MXC_F_TRNG_STATUS_SRCFAIL ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_SRCFAIL_POS)) /**< STATUS_SRCFAIL Mask */
#define MXC_F_TRNG_STATUS_AESKGD_POS 4 /**< STATUS_AESKGD Position */
#define MXC_F_TRNG_STATUS_AESKGD ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_AESKGD_POS)) /**< STATUS_AESKGD Mask */
#define MXC_F_TRNG_STATUS_LD_CNT_POS 24 /**< STATUS_LD_CNT Position */
#define MXC_F_TRNG_STATUS_LD_CNT ((uint32_t)(0xFFUL << MXC_F_TRNG_STATUS_LD_CNT_POS)) /**< STATUS_LD_CNT Mask */
/**@} end of group TRNG_STATUS_Register */ /**@} end of group TRNG_STATUS_Register */
@ -136,8 +160,8 @@ typedef struct {
* disabled, read returns 0x0000 0000. * disabled, read returns 0x0000 0000.
* @{ * @{
*/ */
#define MXC_F_TRNG_DATA_DATA_POS 0 /**< DATA_DATA Position */ #define MXC_F_TRNG_DATA_DATA_POS 0 /**< DATA_DATA Position */
#define MXC_F_TRNG_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TRNG_DATA_DATA_POS)) /**< DATA_DATA Mask */ #define MXC_F_TRNG_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TRNG_DATA_DATA_POS)) /**< DATA_DATA Mask */
/**@} end of group TRNG_DATA_Register */ /**@} end of group TRNG_DATA_Register */
@ -145,4 +169,4 @@ typedef struct {
} }
#endif #endif
#endif /* _TRNG_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_TRNG_REGS_H_

292
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/uart_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file uart_regs.h * @file uart_regs.h
* @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _UART_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_UART_REGS_H_
#define _UART_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_UART_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup uart * @ingroup uart
* @defgroup uart_registers UART_Registers * @defgroup uart_registers UART_Registers
* @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
* @details UART Low Power Registers * @details UART Low Power Registers
*/ */
/** /**
@ -105,18 +105,18 @@ typedef struct {
* @brief UART Peripheral Register Offsets from the UART Base Peripheral Address. * @brief UART Peripheral Register Offsets from the UART Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_UART_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt> 0x0000</tt> */ #define MXC_R_UART_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt> 0x0000</tt> */
#define MXC_R_UART_STATUS ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt> 0x0004</tt> */ #define MXC_R_UART_STATUS ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt> 0x0004</tt> */
#define MXC_R_UART_INT_EN ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt> 0x0008</tt> */ #define MXC_R_UART_INT_EN ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt> 0x0008</tt> */
#define MXC_R_UART_INT_FL ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt> 0x000C</tt> */ #define MXC_R_UART_INT_FL ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt> 0x000C</tt> */
#define MXC_R_UART_CLKDIV ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> 0x0010</tt> */ #define MXC_R_UART_CLKDIV ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> 0x0010</tt> */
#define MXC_R_UART_OSR ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> 0x0014</tt> */ #define MXC_R_UART_OSR ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> 0x0014</tt> */
#define MXC_R_UART_TXPEEK ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt> 0x0018</tt> */ #define MXC_R_UART_TXPEEK ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt> 0x0018</tt> */
#define MXC_R_UART_PNR ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt> 0x001C</tt> */ #define MXC_R_UART_PNR ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt> 0x001C</tt> */
#define MXC_R_UART_FIFO ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> 0x0020</tt> */ #define MXC_R_UART_FIFO ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> 0x0020</tt> */
#define MXC_R_UART_DMA ((uint32_t)0x00000030UL) /**< Offset from UART Base Address: <tt> 0x0030</tt> */ #define MXC_R_UART_DMA ((uint32_t)0x00000030UL) /**< Offset from UART Base Address: <tt> 0x0030</tt> */
#define MXC_R_UART_WKEN ((uint32_t)0x00000034UL) /**< Offset from UART Base Address: <tt> 0x0034</tt> */ #define MXC_R_UART_WKEN ((uint32_t)0x00000034UL) /**< Offset from UART Base Address: <tt> 0x0034</tt> */
#define MXC_R_UART_WKFL ((uint32_t)0x00000038UL) /**< Offset from UART Base Address: <tt> 0x0038</tt> */ #define MXC_R_UART_WKFL ((uint32_t)0x00000038UL) /**< Offset from UART Base Address: <tt> 0x0038</tt> */
/**@} end of group uart_registers */ /**@} end of group uart_registers */
/** /**
@ -125,75 +125,75 @@ typedef struct {
* @brief Control register * @brief Control register
* @{ * @{
*/ */
#define MXC_F_UART_CTRL_RX_THD_VAL_POS 0 /**< CTRL_RX_THD_VAL Position */ #define MXC_F_UART_CTRL_RX_THD_VAL_POS 0 /**< CTRL_RX_THD_VAL Position */
#define MXC_F_UART_CTRL_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_CTRL_RX_THD_VAL_POS)) /**< CTRL_RX_THD_VAL Mask */ #define MXC_F_UART_CTRL_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_CTRL_RX_THD_VAL_POS)) /**< CTRL_RX_THD_VAL Mask */
#define MXC_F_UART_CTRL_PAR_EN_POS 4 /**< CTRL_PAR_EN Position */ #define MXC_F_UART_CTRL_PAR_EN_POS 4 /**< CTRL_PAR_EN Position */
#define MXC_F_UART_CTRL_PAR_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_EN_POS)) /**< CTRL_PAR_EN Mask */ #define MXC_F_UART_CTRL_PAR_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_EN_POS)) /**< CTRL_PAR_EN Mask */
#define MXC_F_UART_CTRL_PAR_EO_POS 5 /**< CTRL_PAR_EO Position */ #define MXC_F_UART_CTRL_PAR_EO_POS 5 /**< CTRL_PAR_EO Position */
#define MXC_F_UART_CTRL_PAR_EO ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_EO_POS)) /**< CTRL_PAR_EO Mask */ #define MXC_F_UART_CTRL_PAR_EO ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_EO_POS)) /**< CTRL_PAR_EO Mask */
#define MXC_F_UART_CTRL_PAR_MD_POS 6 /**< CTRL_PAR_MD Position */ #define MXC_F_UART_CTRL_PAR_MD_POS 6 /**< CTRL_PAR_MD Position */
#define MXC_F_UART_CTRL_PAR_MD ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_MD_POS)) /**< CTRL_PAR_MD Mask */ #define MXC_F_UART_CTRL_PAR_MD ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_MD_POS)) /**< CTRL_PAR_MD Mask */
#define MXC_F_UART_CTRL_CTS_DIS_POS 7 /**< CTRL_CTS_DIS Position */ #define MXC_F_UART_CTRL_CTS_DIS_POS 7 /**< CTRL_CTS_DIS Position */
#define MXC_F_UART_CTRL_CTS_DIS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CTS_DIS_POS)) /**< CTRL_CTS_DIS Mask */ #define MXC_F_UART_CTRL_CTS_DIS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CTS_DIS_POS)) /**< CTRL_CTS_DIS Mask */
#define MXC_F_UART_CTRL_TX_FLUSH_POS 8 /**< CTRL_TX_FLUSH Position */ #define MXC_F_UART_CTRL_TX_FLUSH_POS 8 /**< CTRL_TX_FLUSH Position */
#define MXC_F_UART_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */ #define MXC_F_UART_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */
#define MXC_F_UART_CTRL_RX_FLUSH_POS 9 /**< CTRL_RX_FLUSH Position */ #define MXC_F_UART_CTRL_RX_FLUSH_POS 9 /**< CTRL_RX_FLUSH Position */
#define MXC_F_UART_CTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */ #define MXC_F_UART_CTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */
#define MXC_F_UART_CTRL_CHAR_SIZE_POS 10 /**< CTRL_CHAR_SIZE Position */ #define MXC_F_UART_CTRL_CHAR_SIZE_POS 10 /**< CTRL_CHAR_SIZE Position */
#define MXC_F_UART_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */ #define MXC_F_UART_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */
#define MXC_V_UART_CTRL_CHAR_SIZE_5BITS ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5BITS Value */ #define MXC_V_UART_CTRL_CHAR_SIZE_5BITS ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5BITS Value */
#define MXC_S_UART_CTRL_CHAR_SIZE_5BITS (MXC_V_UART_CTRL_CHAR_SIZE_5BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5BITS Setting */ #define MXC_S_UART_CTRL_CHAR_SIZE_5BITS (MXC_V_UART_CTRL_CHAR_SIZE_5BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5BITS Setting */
#define MXC_V_UART_CTRL_CHAR_SIZE_6BITS ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6BITS Value */ #define MXC_V_UART_CTRL_CHAR_SIZE_6BITS ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6BITS Value */
#define MXC_S_UART_CTRL_CHAR_SIZE_6BITS (MXC_V_UART_CTRL_CHAR_SIZE_6BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6BITS Setting */ #define MXC_S_UART_CTRL_CHAR_SIZE_6BITS (MXC_V_UART_CTRL_CHAR_SIZE_6BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6BITS Setting */
#define MXC_V_UART_CTRL_CHAR_SIZE_7BITS ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7BITS Value */ #define MXC_V_UART_CTRL_CHAR_SIZE_7BITS ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7BITS Value */
#define MXC_S_UART_CTRL_CHAR_SIZE_7BITS (MXC_V_UART_CTRL_CHAR_SIZE_7BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7BITS Setting */ #define MXC_S_UART_CTRL_CHAR_SIZE_7BITS (MXC_V_UART_CTRL_CHAR_SIZE_7BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7BITS Setting */
#define MXC_V_UART_CTRL_CHAR_SIZE_8BITS ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8BITS Value */ #define MXC_V_UART_CTRL_CHAR_SIZE_8BITS ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8BITS Value */
#define MXC_S_UART_CTRL_CHAR_SIZE_8BITS (MXC_V_UART_CTRL_CHAR_SIZE_8BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8BITS Setting */ #define MXC_S_UART_CTRL_CHAR_SIZE_8BITS (MXC_V_UART_CTRL_CHAR_SIZE_8BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8BITS Setting */
#define MXC_F_UART_CTRL_STOPBITS_POS 12 /**< CTRL_STOPBITS Position */ #define MXC_F_UART_CTRL_STOPBITS_POS 12 /**< CTRL_STOPBITS Position */
#define MXC_F_UART_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */ #define MXC_F_UART_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */
#define MXC_F_UART_CTRL_HFC_EN_POS 13 /**< CTRL_HFC_EN Position */ #define MXC_F_UART_CTRL_HFC_EN_POS 13 /**< CTRL_HFC_EN Position */
#define MXC_F_UART_CTRL_HFC_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_HFC_EN_POS)) /**< CTRL_HFC_EN Mask */ #define MXC_F_UART_CTRL_HFC_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_HFC_EN_POS)) /**< CTRL_HFC_EN Mask */
#define MXC_F_UART_CTRL_RTSDC_POS 14 /**< CTRL_RTSDC Position */ #define MXC_F_UART_CTRL_RTSDC_POS 14 /**< CTRL_RTSDC Position */
#define MXC_F_UART_CTRL_RTSDC ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RTSDC_POS)) /**< CTRL_RTSDC Mask */ #define MXC_F_UART_CTRL_RTSDC ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RTSDC_POS)) /**< CTRL_RTSDC Mask */
#define MXC_F_UART_CTRL_BCLKEN_POS 15 /**< CTRL_BCLKEN Position */ #define MXC_F_UART_CTRL_BCLKEN_POS 15 /**< CTRL_BCLKEN Position */
#define MXC_F_UART_CTRL_BCLKEN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BCLKEN_POS)) /**< CTRL_BCLKEN Mask */ #define MXC_F_UART_CTRL_BCLKEN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BCLKEN_POS)) /**< CTRL_BCLKEN Mask */
#define MXC_F_UART_CTRL_BCLKSRC_POS 16 /**< CTRL_BCLKSRC Position */ #define MXC_F_UART_CTRL_BCLKSRC_POS 16 /**< CTRL_BCLKSRC Position */
#define MXC_F_UART_CTRL_BCLKSRC ((uint32_t)(0x3UL << MXC_F_UART_CTRL_BCLKSRC_POS)) /**< CTRL_BCLKSRC Mask */ #define MXC_F_UART_CTRL_BCLKSRC ((uint32_t)(0x3UL << MXC_F_UART_CTRL_BCLKSRC_POS)) /**< CTRL_BCLKSRC Mask */
#define MXC_V_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK ((uint32_t)0x0UL) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Value */ #define MXC_V_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK ((uint32_t)0x0UL) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Value */
#define MXC_S_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK (MXC_V_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Setting */ #define MXC_S_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK (MXC_V_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Setting */
#define MXC_V_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK ((uint32_t)0x1UL) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Value */ #define MXC_V_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK ((uint32_t)0x1UL) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Value */
#define MXC_S_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK (MXC_V_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Setting */ #define MXC_S_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK (MXC_V_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Setting */
#define MXC_V_UART_CTRL_BCLKSRC_CLK2 ((uint32_t)0x2UL) /**< CTRL_BCLKSRC_CLK2 Value */ #define MXC_V_UART_CTRL_BCLKSRC_CLK2 ((uint32_t)0x2UL) /**< CTRL_BCLKSRC_CLK2 Value */
#define MXC_S_UART_CTRL_BCLKSRC_CLK2 (MXC_V_UART_CTRL_BCLKSRC_CLK2 << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK2 Setting */ #define MXC_S_UART_CTRL_BCLKSRC_CLK2 (MXC_V_UART_CTRL_BCLKSRC_CLK2 << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK2 Setting */
#define MXC_V_UART_CTRL_BCLKSRC_CLK3 ((uint32_t)0x3UL) /**< CTRL_BCLKSRC_CLK3 Value */ #define MXC_V_UART_CTRL_BCLKSRC_CLK3 ((uint32_t)0x3UL) /**< CTRL_BCLKSRC_CLK3 Value */
#define MXC_S_UART_CTRL_BCLKSRC_CLK3 (MXC_V_UART_CTRL_BCLKSRC_CLK3 << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK3 Setting */ #define MXC_S_UART_CTRL_BCLKSRC_CLK3 (MXC_V_UART_CTRL_BCLKSRC_CLK3 << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK3 Setting */
#define MXC_F_UART_CTRL_DPFE_EN_POS 18 /**< CTRL_DPFE_EN Position */ #define MXC_F_UART_CTRL_DPFE_EN_POS 18 /**< CTRL_DPFE_EN Position */
#define MXC_F_UART_CTRL_DPFE_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_DPFE_EN_POS)) /**< CTRL_DPFE_EN Mask */ #define MXC_F_UART_CTRL_DPFE_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_DPFE_EN_POS)) /**< CTRL_DPFE_EN Mask */
#define MXC_F_UART_CTRL_BCLKRDY_POS 19 /**< CTRL_BCLKRDY Position */ #define MXC_F_UART_CTRL_BCLKRDY_POS 19 /**< CTRL_BCLKRDY Position */
#define MXC_F_UART_CTRL_BCLKRDY ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BCLKRDY_POS)) /**< CTRL_BCLKRDY Mask */ #define MXC_F_UART_CTRL_BCLKRDY ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BCLKRDY_POS)) /**< CTRL_BCLKRDY Mask */
#define MXC_F_UART_CTRL_UCAGM_POS 20 /**< CTRL_UCAGM Position */ #define MXC_F_UART_CTRL_UCAGM_POS 20 /**< CTRL_UCAGM Position */
#define MXC_F_UART_CTRL_UCAGM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_UCAGM_POS)) /**< CTRL_UCAGM Mask */ #define MXC_F_UART_CTRL_UCAGM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_UCAGM_POS)) /**< CTRL_UCAGM Mask */
#define MXC_F_UART_CTRL_FDM_POS 21 /**< CTRL_FDM Position */ #define MXC_F_UART_CTRL_FDM_POS 21 /**< CTRL_FDM Position */
#define MXC_F_UART_CTRL_FDM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FDM_POS)) /**< CTRL_FDM Mask */ #define MXC_F_UART_CTRL_FDM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FDM_POS)) /**< CTRL_FDM Mask */
#define MXC_F_UART_CTRL_DESM_POS 22 /**< CTRL_DESM Position */ #define MXC_F_UART_CTRL_DESM_POS 22 /**< CTRL_DESM Position */
#define MXC_F_UART_CTRL_DESM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_DESM_POS)) /**< CTRL_DESM Mask */ #define MXC_F_UART_CTRL_DESM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_DESM_POS)) /**< CTRL_DESM Mask */
/**@} end of group UART_CTRL_Register */ /**@} end of group UART_CTRL_Register */
@ -203,29 +203,29 @@ typedef struct {
* @brief Status register * @brief Status register
* @{ * @{
*/ */
#define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */ #define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */
#define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */ #define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */
#define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */ #define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */
#define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */ #define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */
#define MXC_F_UART_STATUS_RX_EM_POS 4 /**< STATUS_RX_EM Position */ #define MXC_F_UART_STATUS_RX_EM_POS 4 /**< STATUS_RX_EM Position */
#define MXC_F_UART_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ #define MXC_F_UART_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */
#define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */ #define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */
#define MXC_F_UART_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ #define MXC_F_UART_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
#define MXC_F_UART_STATUS_TX_EM_POS 6 /**< STATUS_TX_EM Position */ #define MXC_F_UART_STATUS_TX_EM_POS 6 /**< STATUS_TX_EM Position */
#define MXC_F_UART_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ #define MXC_F_UART_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */
#define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */ #define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */
#define MXC_F_UART_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ #define MXC_F_UART_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
#define MXC_F_UART_STATUS_RX_LVL_POS 8 /**< STATUS_RX_LVL Position */ #define MXC_F_UART_STATUS_RX_LVL_POS 8 /**< STATUS_RX_LVL Position */
#define MXC_F_UART_STATUS_RX_LVL ((uint32_t)(0xFUL << MXC_F_UART_STATUS_RX_LVL_POS)) /**< STATUS_RX_LVL Mask */ #define MXC_F_UART_STATUS_RX_LVL ((uint32_t)(0xFUL << MXC_F_UART_STATUS_RX_LVL_POS)) /**< STATUS_RX_LVL Mask */
#define MXC_F_UART_STATUS_TX_LVL_POS 12 /**< STATUS_TX_LVL Position */ #define MXC_F_UART_STATUS_TX_LVL_POS 12 /**< STATUS_TX_LVL Position */
#define MXC_F_UART_STATUS_TX_LVL ((uint32_t)(0xFUL << MXC_F_UART_STATUS_TX_LVL_POS)) /**< STATUS_TX_LVL Mask */ #define MXC_F_UART_STATUS_TX_LVL ((uint32_t)(0xFUL << MXC_F_UART_STATUS_TX_LVL_POS)) /**< STATUS_TX_LVL Mask */
/**@} end of group UART_STATUS_Register */ /**@} end of group UART_STATUS_Register */
@ -235,23 +235,23 @@ typedef struct {
* @brief Interrupt Enable control register * @brief Interrupt Enable control register
* @{ * @{
*/ */
#define MXC_F_UART_INT_EN_RX_FERR_POS 0 /**< INT_EN_RX_FERR Position */ #define MXC_F_UART_INT_EN_RX_FERR_POS 0 /**< INT_EN_RX_FERR Position */
#define MXC_F_UART_INT_EN_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FERR_POS)) /**< INT_EN_RX_FERR Mask */ #define MXC_F_UART_INT_EN_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FERR_POS)) /**< INT_EN_RX_FERR Mask */
#define MXC_F_UART_INT_EN_RX_PAR_POS 1 /**< INT_EN_RX_PAR Position */ #define MXC_F_UART_INT_EN_RX_PAR_POS 1 /**< INT_EN_RX_PAR Position */
#define MXC_F_UART_INT_EN_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PAR_POS)) /**< INT_EN_RX_PAR Mask */ #define MXC_F_UART_INT_EN_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PAR_POS)) /**< INT_EN_RX_PAR Mask */
#define MXC_F_UART_INT_EN_CTS_EV_POS 2 /**< INT_EN_CTS_EV Position */ #define MXC_F_UART_INT_EN_CTS_EV_POS 2 /**< INT_EN_CTS_EV Position */
#define MXC_F_UART_INT_EN_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_EV_POS)) /**< INT_EN_CTS_EV Mask */ #define MXC_F_UART_INT_EN_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_EV_POS)) /**< INT_EN_CTS_EV Mask */
#define MXC_F_UART_INT_EN_RX_OV_POS 3 /**< INT_EN_RX_OV Position */ #define MXC_F_UART_INT_EN_RX_OV_POS 3 /**< INT_EN_RX_OV Position */
#define MXC_F_UART_INT_EN_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OV_POS)) /**< INT_EN_RX_OV Mask */ #define MXC_F_UART_INT_EN_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OV_POS)) /**< INT_EN_RX_OV Mask */
#define MXC_F_UART_INT_EN_RX_THD_POS 4 /**< INT_EN_RX_THD Position */ #define MXC_F_UART_INT_EN_RX_THD_POS 4 /**< INT_EN_RX_THD Position */
#define MXC_F_UART_INT_EN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_THD_POS)) /**< INT_EN_RX_THD Mask */ #define MXC_F_UART_INT_EN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_THD_POS)) /**< INT_EN_RX_THD Mask */
#define MXC_F_UART_INT_EN_TX_HE_POS 6 /**< INT_EN_TX_HE Position */ #define MXC_F_UART_INT_EN_TX_HE_POS 6 /**< INT_EN_TX_HE Position */
#define MXC_F_UART_INT_EN_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_HE_POS)) /**< INT_EN_TX_HE Mask */ #define MXC_F_UART_INT_EN_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_HE_POS)) /**< INT_EN_TX_HE Mask */
/**@} end of group UART_INT_EN_Register */ /**@} end of group UART_INT_EN_Register */
@ -261,23 +261,23 @@ typedef struct {
* @brief Interrupt status flags Control register * @brief Interrupt status flags Control register
* @{ * @{
*/ */
#define MXC_F_UART_INT_FL_RX_FERR_POS 0 /**< INT_FL_RX_FERR Position */ #define MXC_F_UART_INT_FL_RX_FERR_POS 0 /**< INT_FL_RX_FERR Position */
#define MXC_F_UART_INT_FL_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FERR_POS)) /**< INT_FL_RX_FERR Mask */ #define MXC_F_UART_INT_FL_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FERR_POS)) /**< INT_FL_RX_FERR Mask */
#define MXC_F_UART_INT_FL_RX_PAR_POS 1 /**< INT_FL_RX_PAR Position */ #define MXC_F_UART_INT_FL_RX_PAR_POS 1 /**< INT_FL_RX_PAR Position */
#define MXC_F_UART_INT_FL_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_PAR_POS)) /**< INT_FL_RX_PAR Mask */ #define MXC_F_UART_INT_FL_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_PAR_POS)) /**< INT_FL_RX_PAR Mask */
#define MXC_F_UART_INT_FL_CTS_EV_POS 2 /**< INT_FL_CTS_EV Position */ #define MXC_F_UART_INT_FL_CTS_EV_POS 2 /**< INT_FL_CTS_EV Position */
#define MXC_F_UART_INT_FL_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_EV_POS)) /**< INT_FL_CTS_EV Mask */ #define MXC_F_UART_INT_FL_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_EV_POS)) /**< INT_FL_CTS_EV Mask */
#define MXC_F_UART_INT_FL_RX_OV_POS 3 /**< INT_FL_RX_OV Position */ #define MXC_F_UART_INT_FL_RX_OV_POS 3 /**< INT_FL_RX_OV Position */
#define MXC_F_UART_INT_FL_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OV_POS)) /**< INT_FL_RX_OV Mask */ #define MXC_F_UART_INT_FL_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OV_POS)) /**< INT_FL_RX_OV Mask */
#define MXC_F_UART_INT_FL_RX_THD_POS 4 /**< INT_FL_RX_THD Position */ #define MXC_F_UART_INT_FL_RX_THD_POS 4 /**< INT_FL_RX_THD Position */
#define MXC_F_UART_INT_FL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_THD_POS)) /**< INT_FL_RX_THD Mask */ #define MXC_F_UART_INT_FL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_THD_POS)) /**< INT_FL_RX_THD Mask */
#define MXC_F_UART_INT_FL_TX_HE_POS 6 /**< INT_FL_TX_HE Position */ #define MXC_F_UART_INT_FL_TX_HE_POS 6 /**< INT_FL_TX_HE Position */
#define MXC_F_UART_INT_FL_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_HE_POS)) /**< INT_FL_TX_HE Mask */ #define MXC_F_UART_INT_FL_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_HE_POS)) /**< INT_FL_TX_HE Mask */
/**@} end of group UART_INT_FL_Register */ /**@} end of group UART_INT_FL_Register */
@ -287,8 +287,8 @@ typedef struct {
* @brief Clock Divider register * @brief Clock Divider register
* @{ * @{
*/ */
#define MXC_F_UART_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ #define MXC_F_UART_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
#define MXC_F_UART_CLKDIV_CLKDIV ((uint32_t)(0xFFFFFUL << MXC_F_UART_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ #define MXC_F_UART_CLKDIV_CLKDIV ((uint32_t)(0xFFFFFUL << MXC_F_UART_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
/**@} end of group UART_CLKDIV_Register */ /**@} end of group UART_CLKDIV_Register */
@ -298,8 +298,8 @@ typedef struct {
* @brief Over Sampling Rate register * @brief Over Sampling Rate register
* @{ * @{
*/ */
#define MXC_F_UART_OSR_OSR_POS 0 /**< OSR_OSR Position */ #define MXC_F_UART_OSR_OSR_POS 0 /**< OSR_OSR Position */
#define MXC_F_UART_OSR_OSR ((uint32_t)(0x7UL << MXC_F_UART_OSR_OSR_POS)) /**< OSR_OSR Mask */ #define MXC_F_UART_OSR_OSR ((uint32_t)(0x7UL << MXC_F_UART_OSR_OSR_POS)) /**< OSR_OSR Mask */
/**@} end of group UART_OSR_Register */ /**@} end of group UART_OSR_Register */
@ -309,8 +309,8 @@ typedef struct {
* @brief TX FIFO Output Peek register * @brief TX FIFO Output Peek register
* @{ * @{
*/ */
#define MXC_F_UART_TXPEEK_DATA_POS 0 /**< TXPEEK_DATA Position */ #define MXC_F_UART_TXPEEK_DATA_POS 0 /**< TXPEEK_DATA Position */
#define MXC_F_UART_TXPEEK_DATA ((uint32_t)(0xFFUL << MXC_F_UART_TXPEEK_DATA_POS)) /**< TXPEEK_DATA Mask */ #define MXC_F_UART_TXPEEK_DATA ((uint32_t)(0xFFUL << MXC_F_UART_TXPEEK_DATA_POS)) /**< TXPEEK_DATA Mask */
/**@} end of group UART_TXPEEK_Register */ /**@} end of group UART_TXPEEK_Register */
@ -320,11 +320,11 @@ typedef struct {
* @brief Pin register * @brief Pin register
* @{ * @{
*/ */
#define MXC_F_UART_PNR_CTS_POS 0 /**< PNR_CTS Position */ #define MXC_F_UART_PNR_CTS_POS 0 /**< PNR_CTS Position */
#define MXC_F_UART_PNR_CTS ((uint32_t)(0x1UL << MXC_F_UART_PNR_CTS_POS)) /**< PNR_CTS Mask */ #define MXC_F_UART_PNR_CTS ((uint32_t)(0x1UL << MXC_F_UART_PNR_CTS_POS)) /**< PNR_CTS Mask */
#define MXC_F_UART_PNR_RTS_POS 1 /**< PNR_RTS Position */ #define MXC_F_UART_PNR_RTS_POS 1 /**< PNR_RTS Position */
#define MXC_F_UART_PNR_RTS ((uint32_t)(0x1UL << MXC_F_UART_PNR_RTS_POS)) /**< PNR_RTS Mask */ #define MXC_F_UART_PNR_RTS ((uint32_t)(0x1UL << MXC_F_UART_PNR_RTS_POS)) /**< PNR_RTS Mask */
/**@} end of group UART_PNR_Register */ /**@} end of group UART_PNR_Register */
@ -334,11 +334,11 @@ typedef struct {
* @brief FIFO Read/Write register * @brief FIFO Read/Write register
* @{ * @{
*/ */
#define MXC_F_UART_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ #define MXC_F_UART_FIFO_DATA_POS 0 /**< FIFO_DATA Position */
#define MXC_F_UART_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ #define MXC_F_UART_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
#define MXC_F_UART_FIFO_RX_PAR_POS 8 /**< FIFO_RX_PAR Position */ #define MXC_F_UART_FIFO_RX_PAR_POS 8 /**< FIFO_RX_PAR Position */
#define MXC_F_UART_FIFO_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_FIFO_RX_PAR_POS)) /**< FIFO_RX_PAR Mask */ #define MXC_F_UART_FIFO_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_FIFO_RX_PAR_POS)) /**< FIFO_RX_PAR Mask */
/**@} end of group UART_FIFO_Register */ /**@} end of group UART_FIFO_Register */
@ -348,17 +348,17 @@ typedef struct {
* @brief DMA Configuration register * @brief DMA Configuration register
* @{ * @{
*/ */
#define MXC_F_UART_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */ #define MXC_F_UART_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */
#define MXC_F_UART_DMA_TX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */ #define MXC_F_UART_DMA_TX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */
#define MXC_F_UART_DMA_TX_EN_POS 4 /**< DMA_TX_EN Position */ #define MXC_F_UART_DMA_TX_EN_POS 4 /**< DMA_TX_EN Position */
#define MXC_F_UART_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ #define MXC_F_UART_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */
#define MXC_F_UART_DMA_RX_THD_VAL_POS 5 /**< DMA_RX_THD_VAL Position */ #define MXC_F_UART_DMA_RX_THD_VAL_POS 5 /**< DMA_RX_THD_VAL Position */
#define MXC_F_UART_DMA_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */ #define MXC_F_UART_DMA_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */
#define MXC_F_UART_DMA_RX_EN_POS 9 /**< DMA_RX_EN Position */ #define MXC_F_UART_DMA_RX_EN_POS 9 /**< DMA_RX_EN Position */
#define MXC_F_UART_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ #define MXC_F_UART_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */
/**@} end of group UART_DMA_Register */ /**@} end of group UART_DMA_Register */
@ -368,14 +368,14 @@ typedef struct {
* @brief Wake up enable Control register * @brief Wake up enable Control register
* @{ * @{
*/ */
#define MXC_F_UART_WKEN_RX_NE_POS 0 /**< WKEN_RX_NE Position */ #define MXC_F_UART_WKEN_RX_NE_POS 0 /**< WKEN_RX_NE Position */
#define MXC_F_UART_WKEN_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_NE_POS)) /**< WKEN_RX_NE Mask */ #define MXC_F_UART_WKEN_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_NE_POS)) /**< WKEN_RX_NE Mask */
#define MXC_F_UART_WKEN_RX_FULL_POS 1 /**< WKEN_RX_FULL Position */ #define MXC_F_UART_WKEN_RX_FULL_POS 1 /**< WKEN_RX_FULL Position */
#define MXC_F_UART_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */ #define MXC_F_UART_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */
#define MXC_F_UART_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */ #define MXC_F_UART_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */
#define MXC_F_UART_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */ #define MXC_F_UART_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */
/**@} end of group UART_WKEN_Register */ /**@} end of group UART_WKEN_Register */
@ -385,14 +385,14 @@ typedef struct {
* @brief Wake up Flags register * @brief Wake up Flags register
* @{ * @{
*/ */
#define MXC_F_UART_WKFL_RX_NE_POS 0 /**< WKFL_RX_NE Position */ #define MXC_F_UART_WKFL_RX_NE_POS 0 /**< WKFL_RX_NE Position */
#define MXC_F_UART_WKFL_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_NE_POS)) /**< WKFL_RX_NE Mask */ #define MXC_F_UART_WKFL_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_NE_POS)) /**< WKFL_RX_NE Mask */
#define MXC_F_UART_WKFL_RX_FULL_POS 1 /**< WKFL_RX_FULL Position */ #define MXC_F_UART_WKFL_RX_FULL_POS 1 /**< WKFL_RX_FULL Position */
#define MXC_F_UART_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */ #define MXC_F_UART_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */
#define MXC_F_UART_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */ #define MXC_F_UART_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */
#define MXC_F_UART_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */ #define MXC_F_UART_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */
/**@} end of group UART_WKFL_Register */ /**@} end of group UART_WKFL_Register */
@ -400,4 +400,4 @@ typedef struct {
} }
#endif #endif
#endif /* _UART_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_UART_REGS_H_

356
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/wdt_regs.h
View File

@ -1,10 +1,11 @@
/** /**
* @file wdt_regs.h * @file wdt_regs.h
* @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module.
* @note This file is @generated.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _WDT_REGS_H_ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_WDT_REGS_H_
#define _WDT_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_WDT_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -75,7 +75,7 @@ extern "C" {
* @ingroup wdt * @ingroup wdt
* @defgroup wdt_registers WDT_Registers * @defgroup wdt_registers WDT_Registers
* @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module.
* @details Windowed Watchdog Timer * @details Windowed Watchdog Timer
*/ */
/** /**
@ -96,10 +96,10 @@ typedef struct {
* @brief WDT Peripheral Register Offsets from the WDT Base Peripheral Address. * @brief WDT Peripheral Register Offsets from the WDT Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_WDT_CTRL ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: <tt> 0x0000</tt> */ #define MXC_R_WDT_CTRL ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: <tt> 0x0000</tt> */
#define MXC_R_WDT_RST ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: <tt> 0x0004</tt> */ #define MXC_R_WDT_RST ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: <tt> 0x0004</tt> */
#define MXC_R_WDT_CLKSEL ((uint32_t)0x00000008UL) /**< Offset from WDT Base Address: <tt> 0x0008</tt> */ #define MXC_R_WDT_CLKSEL ((uint32_t)0x00000008UL) /**< Offset from WDT Base Address: <tt> 0x0008</tt> */
#define MXC_R_WDT_CNT ((uint32_t)0x0000000CUL) /**< Offset from WDT Base Address: <tt> 0x000C</tt> */ #define MXC_R_WDT_CNT ((uint32_t)0x0000000CUL) /**< Offset from WDT Base Address: <tt> 0x000C</tt> */
/**@} end of group wdt_registers */ /**@} end of group wdt_registers */
/** /**
@ -108,175 +108,175 @@ typedef struct {
* @brief Watchdog Timer Control Register. * @brief Watchdog Timer Control Register.
* @{ * @{
*/ */
#define MXC_F_WDT_CTRL_INT_LATE_VAL_POS 0 /**< CTRL_INT_LATE_VAL Position */ #define MXC_F_WDT_CTRL_INT_LATE_VAL_POS 0 /**< CTRL_INT_LATE_VAL Position */
#define MXC_F_WDT_CTRL_INT_LATE_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_LATE_VAL_POS)) /**< CTRL_INT_LATE_VAL Mask */ #define MXC_F_WDT_CTRL_INT_LATE_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_LATE_VAL_POS)) /**< CTRL_INT_LATE_VAL Mask */
#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_LATE_VAL_WDT2POW31 Value */ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_LATE_VAL_WDT2POW31 Value */
#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW31 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW31 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW31 Setting */ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW31 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW31 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW31 Setting */
#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_LATE_VAL_WDT2POW30 Value */ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_LATE_VAL_WDT2POW30 Value */
#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW30 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW30 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW30 Setting */ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW30 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW30 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW30 Setting */
#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_LATE_VAL_WDT2POW29 Value */ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_LATE_VAL_WDT2POW29 Value */
#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW29 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW29 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW29 Setting */ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW29 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW29 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW29 Setting */
#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_LATE_VAL_WDT2POW28 Value */ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_LATE_VAL_WDT2POW28 Value */
#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW28 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW28 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW28 Setting */ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW28 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW28 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW28 Setting */
#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_LATE_VAL_WDT2POW27 Value */ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_LATE_VAL_WDT2POW27 Value */
#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW27 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW27 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW27 Setting */ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW27 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW27 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW27 Setting */
#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_LATE_VAL_WDT2POW26 Value */ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_LATE_VAL_WDT2POW26 Value */
#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW26 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW26 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW26 Setting */ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW26 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW26 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW26 Setting */
#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_LATE_VAL_WDT2POW25 Value */ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_LATE_VAL_WDT2POW25 Value */
#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW25 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW25 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW25 Setting */ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW25 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW25 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW25 Setting */
#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_LATE_VAL_WDT2POW24 Value */ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_LATE_VAL_WDT2POW24 Value */
#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW24 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW24 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW24 Setting */ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW24 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW24 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW24 Setting */
#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_LATE_VAL_WDT2POW23 Value */ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_LATE_VAL_WDT2POW23 Value */
#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW23 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW23 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW23 Setting */ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW23 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW23 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW23 Setting */
#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_LATE_VAL_WDT2POW22 Value */ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_LATE_VAL_WDT2POW22 Value */
#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW22 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW22 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW22 Setting */ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW22 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW22 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW22 Setting */
#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_LATE_VAL_WDT2POW21 Value */ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_LATE_VAL_WDT2POW21 Value */
#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW21 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW21 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW21 Setting */ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW21 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW21 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW21 Setting */
#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_LATE_VAL_WDT2POW20 Value */ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_LATE_VAL_WDT2POW20 Value */
#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW20 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW20 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW20 Setting */ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW20 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW20 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW20 Setting */
#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_LATE_VAL_WDT2POW19 Value */ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_LATE_VAL_WDT2POW19 Value */
#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW19 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW19 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW19 Setting */ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW19 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW19 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW19 Setting */
#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_LATE_VAL_WDT2POW18 Value */ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_LATE_VAL_WDT2POW18 Value */
#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW18 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW18 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW18 Setting */ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW18 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW18 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW18 Setting */
#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_LATE_VAL_WDT2POW17 Value */ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_LATE_VAL_WDT2POW17 Value */
#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW17 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW17 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW17 Setting */ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW17 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW17 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW17 Setting */
#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_LATE_VAL_WDT2POW16 Value */ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_LATE_VAL_WDT2POW16 Value */
#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW16 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW16 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW16 Setting */ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW16 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW16 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW16 Setting */
#define MXC_F_WDT_CTRL_RST_LATE_VAL_POS 4 /**< CTRL_RST_LATE_VAL Position */ #define MXC_F_WDT_CTRL_RST_LATE_VAL_POS 4 /**< CTRL_RST_LATE_VAL Position */
#define MXC_F_WDT_CTRL_RST_LATE_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_LATE_VAL_POS)) /**< CTRL_RST_LATE_VAL Mask */ #define MXC_F_WDT_CTRL_RST_LATE_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_LATE_VAL_POS)) /**< CTRL_RST_LATE_VAL Mask */
#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_LATE_VAL_WDT2POW31 Value */ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_LATE_VAL_WDT2POW31 Value */
#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW31 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW31 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW31 Setting */ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW31 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW31 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW31 Setting */
#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_LATE_VAL_WDT2POW30 Value */ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_LATE_VAL_WDT2POW30 Value */
#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW30 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW30 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW30 Setting */ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW30 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW30 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW30 Setting */
#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_LATE_VAL_WDT2POW29 Value */ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_LATE_VAL_WDT2POW29 Value */
#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW29 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW29 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW29 Setting */ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW29 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW29 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW29 Setting */
#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_LATE_VAL_WDT2POW28 Value */ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_LATE_VAL_WDT2POW28 Value */
#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW28 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW28 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW28 Setting */ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW28 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW28 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW28 Setting */
#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_LATE_VAL_WDT2POW27 Value */ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_LATE_VAL_WDT2POW27 Value */
#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW27 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW27 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW27 Setting */ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW27 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW27 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW27 Setting */
#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_LATE_VAL_WDT2POW26 Value */ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_LATE_VAL_WDT2POW26 Value */
#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW26 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW26 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW26 Setting */ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW26 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW26 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW26 Setting */
#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_LATE_VAL_WDT2POW25 Value */ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_LATE_VAL_WDT2POW25 Value */
#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW25 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW25 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW25 Setting */ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW25 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW25 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW25 Setting */
#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_LATE_VAL_WDT2POW24 Value */ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_LATE_VAL_WDT2POW24 Value */
#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW24 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW24 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW24 Setting */ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW24 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW24 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW24 Setting */
#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_LATE_VAL_WDT2POW23 Value */ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_LATE_VAL_WDT2POW23 Value */
#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW23 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW23 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW23 Setting */ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW23 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW23 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW23 Setting */
#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_LATE_VAL_WDT2POW22 Value */ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_LATE_VAL_WDT2POW22 Value */
#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW22 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW22 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW22 Setting */ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW22 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW22 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW22 Setting */
#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_LATE_VAL_WDT2POW21 Value */ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_LATE_VAL_WDT2POW21 Value */
#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW21 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW21 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW21 Setting */ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW21 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW21 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW21 Setting */
#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_LATE_VAL_WDT2POW20 Value */ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_LATE_VAL_WDT2POW20 Value */
#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW20 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW20 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW20 Setting */ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW20 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW20 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW20 Setting */
#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_LATE_VAL_WDT2POW19 Value */ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_LATE_VAL_WDT2POW19 Value */
#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW19 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW19 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW19 Setting */ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW19 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW19 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW19 Setting */
#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_LATE_VAL_WDT2POW18 Value */ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_LATE_VAL_WDT2POW18 Value */
#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW18 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW18 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW18 Setting */ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW18 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW18 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW18 Setting */
#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_LATE_VAL_WDT2POW17 Value */ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_LATE_VAL_WDT2POW17 Value */
#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW17 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW17 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW17 Setting */ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW17 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW17 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW17 Setting */
#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_LATE_VAL_WDT2POW16 Value */ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_LATE_VAL_WDT2POW16 Value */
#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW16 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW16 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW16 Setting */ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW16 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW16 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW16 Setting */
#define MXC_F_WDT_CTRL_EN_POS 8 /**< CTRL_EN Position */ #define MXC_F_WDT_CTRL_EN_POS 8 /**< CTRL_EN Position */
#define MXC_F_WDT_CTRL_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_EN_POS)) /**< CTRL_EN Mask */ #define MXC_F_WDT_CTRL_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_EN_POS)) /**< CTRL_EN Mask */
#define MXC_F_WDT_CTRL_INT_LATE_POS 9 /**< CTRL_INT_LATE Position */ #define MXC_F_WDT_CTRL_INT_LATE_POS 9 /**< CTRL_INT_LATE Position */
#define MXC_F_WDT_CTRL_INT_LATE ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_LATE_POS)) /**< CTRL_INT_LATE Mask */ #define MXC_F_WDT_CTRL_INT_LATE ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_LATE_POS)) /**< CTRL_INT_LATE Mask */
#define MXC_F_WDT_CTRL_WDT_INT_EN_POS 10 /**< CTRL_WDT_INT_EN Position */ #define MXC_F_WDT_CTRL_WDT_INT_EN_POS 10 /**< CTRL_WDT_INT_EN Position */
#define MXC_F_WDT_CTRL_WDT_INT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_INT_EN_POS)) /**< CTRL_WDT_INT_EN Mask */ #define MXC_F_WDT_CTRL_WDT_INT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_INT_EN_POS)) /**< CTRL_WDT_INT_EN Mask */
#define MXC_F_WDT_CTRL_WDT_RST_EN_POS 11 /**< CTRL_WDT_RST_EN Position */ #define MXC_F_WDT_CTRL_WDT_RST_EN_POS 11 /**< CTRL_WDT_RST_EN Position */
#define MXC_F_WDT_CTRL_WDT_RST_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_RST_EN_POS)) /**< CTRL_WDT_RST_EN Mask */ #define MXC_F_WDT_CTRL_WDT_RST_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_RST_EN_POS)) /**< CTRL_WDT_RST_EN Mask */
#define MXC_F_WDT_CTRL_INT_EARLY_POS 12 /**< CTRL_INT_EARLY Position */ #define MXC_F_WDT_CTRL_INT_EARLY_POS 12 /**< CTRL_INT_EARLY Position */
#define MXC_F_WDT_CTRL_INT_EARLY ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EARLY_POS)) /**< CTRL_INT_EARLY Mask */ #define MXC_F_WDT_CTRL_INT_EARLY ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EARLY_POS)) /**< CTRL_INT_EARLY Mask */
#define MXC_F_WDT_CTRL_INT_EARLY_VAL_POS 16 /**< CTRL_INT_EARLY_VAL Position */ #define MXC_F_WDT_CTRL_INT_EARLY_VAL_POS 16 /**< CTRL_INT_EARLY_VAL Position */
#define MXC_F_WDT_CTRL_INT_EARLY_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS)) /**< CTRL_INT_EARLY_VAL Mask */ #define MXC_F_WDT_CTRL_INT_EARLY_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS)) /**< CTRL_INT_EARLY_VAL Mask */
#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_EARLY_VAL_WDT2POW31 Value */ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_EARLY_VAL_WDT2POW31 Value */
#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW31 Setting */ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW31 Setting */
#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_EARLY_VAL_WDT2POW30 Value */ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_EARLY_VAL_WDT2POW30 Value */
#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW30 Setting */ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW30 Setting */
#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_EARLY_VAL_WDT2POW29 Value */ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_EARLY_VAL_WDT2POW29 Value */
#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW29 Setting */ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW29 Setting */
#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_EARLY_VAL_WDT2POW28 Value */ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_EARLY_VAL_WDT2POW28 Value */
#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW28 Setting */ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW28 Setting */
#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_EARLY_VAL_WDT2POW27 Value */ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_EARLY_VAL_WDT2POW27 Value */
#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW27 Setting */ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW27 Setting */
#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_EARLY_VAL_WDT2POW26 Value */ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_EARLY_VAL_WDT2POW26 Value */
#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW26 Setting */ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW26 Setting */
#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_EARLY_VAL_WDT2POW25 Value */ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_EARLY_VAL_WDT2POW25 Value */
#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW25 Setting */ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW25 Setting */
#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_EARLY_VAL_WDT2POW24 Value */ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_EARLY_VAL_WDT2POW24 Value */
#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW24 Setting */ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW24 Setting */
#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_EARLY_VAL_WDT2POW23 Value */ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_EARLY_VAL_WDT2POW23 Value */
#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW23 Setting */ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW23 Setting */
#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_EARLY_VAL_WDT2POW22 Value */ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_EARLY_VAL_WDT2POW22 Value */
#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW22 Setting */ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW22 Setting */
#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_EARLY_VAL_WDT2POW21 Value */ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_EARLY_VAL_WDT2POW21 Value */
#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW21 Setting */ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW21 Setting */
#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_EARLY_VAL_WDT2POW20 Value */ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_EARLY_VAL_WDT2POW20 Value */
#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW20 Setting */ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW20 Setting */
#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_EARLY_VAL_WDT2POW19 Value */ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_EARLY_VAL_WDT2POW19 Value */
#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW19 Setting */ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW19 Setting */
#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_EARLY_VAL_WDT2POW18 Value */ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_EARLY_VAL_WDT2POW18 Value */
#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW18 Setting */ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW18 Setting */
#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_EARLY_VAL_WDT2POW17 Value */ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_EARLY_VAL_WDT2POW17 Value */
#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW17 Setting */ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW17 Setting */
#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_EARLY_VAL_WDT2POW16 Value */ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_EARLY_VAL_WDT2POW16 Value */
#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW16 Setting */ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW16 Setting */
#define MXC_F_WDT_CTRL_RST_EARLY_VAL_POS 20 /**< CTRL_RST_EARLY_VAL Position */ #define MXC_F_WDT_CTRL_RST_EARLY_VAL_POS 20 /**< CTRL_RST_EARLY_VAL Position */
#define MXC_F_WDT_CTRL_RST_EARLY_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS)) /**< CTRL_RST_EARLY_VAL Mask */ #define MXC_F_WDT_CTRL_RST_EARLY_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS)) /**< CTRL_RST_EARLY_VAL Mask */
#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_EARLY_VAL_WDT2POW31 Value */ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_EARLY_VAL_WDT2POW31 Value */
#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW31 Setting */ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW31 Setting */
#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_EARLY_VAL_WDT2POW30 Value */ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_EARLY_VAL_WDT2POW30 Value */
#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW30 Setting */ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW30 Setting */
#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_EARLY_VAL_WDT2POW29 Value */ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_EARLY_VAL_WDT2POW29 Value */
#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW29 Setting */ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW29 Setting */
#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_EARLY_VAL_WDT2POW28 Value */ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_EARLY_VAL_WDT2POW28 Value */
#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW28 Setting */ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW28 Setting */
#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_EARLY_VAL_WDT2POW27 Value */ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_EARLY_VAL_WDT2POW27 Value */
#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW27 Setting */ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW27 Setting */
#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_EARLY_VAL_WDT2POW26 Value */ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_EARLY_VAL_WDT2POW26 Value */
#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW26 Setting */ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW26 Setting */
#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_EARLY_VAL_WDT2POW25 Value */ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_EARLY_VAL_WDT2POW25 Value */
#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW25 Setting */ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW25 Setting */
#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_EARLY_VAL_WDT2POW24 Value */ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_EARLY_VAL_WDT2POW24 Value */
#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW24 Setting */ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW24 Setting */
#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_EARLY_VAL_WDT2POW23 Value */ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_EARLY_VAL_WDT2POW23 Value */
#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW23 Setting */ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW23 Setting */
#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_EARLY_VAL_WDT2POW22 Value */ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_EARLY_VAL_WDT2POW22 Value */
#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW22 Setting */ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW22 Setting */
#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_EARLY_VAL_WDT2POW21 Value */ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_EARLY_VAL_WDT2POW21 Value */
#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW21 Setting */ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW21 Setting */
#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_EARLY_VAL_WDT2POW20 Value */ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_EARLY_VAL_WDT2POW20 Value */
#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW20 Setting */ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW20 Setting */
#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_EARLY_VAL_WDT2POW19 Value */ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_EARLY_VAL_WDT2POW19 Value */
#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW19 Setting */ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW19 Setting */
#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_EARLY_VAL_WDT2POW18 Value */ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_EARLY_VAL_WDT2POW18 Value */
#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW18 Setting */ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW18 Setting */
#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_EARLY_VAL_WDT2POW17 Value */ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_EARLY_VAL_WDT2POW17 Value */
#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW17 Setting */ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW17 Setting */
#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_EARLY_VAL_WDT2POW16 Value */ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_EARLY_VAL_WDT2POW16 Value */
#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW16 Setting */ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW16 Setting */
#define MXC_F_WDT_CTRL_CLKRDY_IE_POS 27 /**< CTRL_CLKRDY_IE Position */ #define MXC_F_WDT_CTRL_CLKRDY_IE_POS 27 /**< CTRL_CLKRDY_IE Position */
#define MXC_F_WDT_CTRL_CLKRDY_IE ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_CLKRDY_IE_POS)) /**< CTRL_CLKRDY_IE Mask */ #define MXC_F_WDT_CTRL_CLKRDY_IE ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_CLKRDY_IE_POS)) /**< CTRL_CLKRDY_IE Mask */
#define MXC_F_WDT_CTRL_CLKRDY_POS 28 /**< CTRL_CLKRDY Position */ #define MXC_F_WDT_CTRL_CLKRDY_POS 28 /**< CTRL_CLKRDY Position */
#define MXC_F_WDT_CTRL_CLKRDY ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_CLKRDY_POS)) /**< CTRL_CLKRDY Mask */ #define MXC_F_WDT_CTRL_CLKRDY ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_CLKRDY_POS)) /**< CTRL_CLKRDY Mask */
#define MXC_F_WDT_CTRL_WIN_EN_POS 29 /**< CTRL_WIN_EN Position */ #define MXC_F_WDT_CTRL_WIN_EN_POS 29 /**< CTRL_WIN_EN Position */
#define MXC_F_WDT_CTRL_WIN_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WIN_EN_POS)) /**< CTRL_WIN_EN Mask */ #define MXC_F_WDT_CTRL_WIN_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WIN_EN_POS)) /**< CTRL_WIN_EN Mask */
#define MXC_F_WDT_CTRL_RST_EARLY_POS 30 /**< CTRL_RST_EARLY Position */ #define MXC_F_WDT_CTRL_RST_EARLY_POS 30 /**< CTRL_RST_EARLY Position */
#define MXC_F_WDT_CTRL_RST_EARLY ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EARLY_POS)) /**< CTRL_RST_EARLY Mask */ #define MXC_F_WDT_CTRL_RST_EARLY ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EARLY_POS)) /**< CTRL_RST_EARLY Mask */
#define MXC_F_WDT_CTRL_RST_LATE_POS 31 /**< CTRL_RST_LATE Position */ #define MXC_F_WDT_CTRL_RST_LATE_POS 31 /**< CTRL_RST_LATE Position */
#define MXC_F_WDT_CTRL_RST_LATE ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_LATE_POS)) /**< CTRL_RST_LATE Mask */ #define MXC_F_WDT_CTRL_RST_LATE ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_LATE_POS)) /**< CTRL_RST_LATE Mask */
/**@} end of group WDT_CTRL_Register */ /**@} end of group WDT_CTRL_Register */
@ -286,12 +286,12 @@ typedef struct {
* @brief Windowed Watchdog Timer Reset Register. * @brief Windowed Watchdog Timer Reset Register.
* @{ * @{
*/ */
#define MXC_F_WDT_RST_RESET_POS 0 /**< RST_RESET Position */ #define MXC_F_WDT_RST_RESET_POS 0 /**< RST_RESET Position */
#define MXC_F_WDT_RST_RESET ((uint32_t)(0xFFUL << MXC_F_WDT_RST_RESET_POS)) /**< RST_RESET Mask */ #define MXC_F_WDT_RST_RESET ((uint32_t)(0xFFUL << MXC_F_WDT_RST_RESET_POS)) /**< RST_RESET Mask */
#define MXC_V_WDT_RST_RESET_SEQ0 ((uint32_t)0xA5UL) /**< RST_RESET_SEQ0 Value */ #define MXC_V_WDT_RST_RESET_SEQ0 ((uint32_t)0xA5UL) /**< RST_RESET_SEQ0 Value */
#define MXC_S_WDT_RST_RESET_SEQ0 (MXC_V_WDT_RST_RESET_SEQ0 << MXC_F_WDT_RST_RESET_POS) /**< RST_RESET_SEQ0 Setting */ #define MXC_S_WDT_RST_RESET_SEQ0 (MXC_V_WDT_RST_RESET_SEQ0 << MXC_F_WDT_RST_RESET_POS) /**< RST_RESET_SEQ0 Setting */
#define MXC_V_WDT_RST_RESET_SEQ1 ((uint32_t)0x5AUL) /**< RST_RESET_SEQ1 Value */ #define MXC_V_WDT_RST_RESET_SEQ1 ((uint32_t)0x5AUL) /**< RST_RESET_SEQ1 Value */
#define MXC_S_WDT_RST_RESET_SEQ1 (MXC_V_WDT_RST_RESET_SEQ1 << MXC_F_WDT_RST_RESET_POS) /**< RST_RESET_SEQ1 Setting */ #define MXC_S_WDT_RST_RESET_SEQ1 (MXC_V_WDT_RST_RESET_SEQ1 << MXC_F_WDT_RST_RESET_POS) /**< RST_RESET_SEQ1 Setting */
/**@} end of group WDT_RST_Register */ /**@} end of group WDT_RST_Register */
@ -301,8 +301,8 @@ typedef struct {
* @brief Windowed Watchdog Timer Clock Select Register. * @brief Windowed Watchdog Timer Clock Select Register.
* @{ * @{
*/ */
#define MXC_F_WDT_CLKSEL_SOURCE_POS 0 /**< CLKSEL_SOURCE Position */ #define MXC_F_WDT_CLKSEL_SOURCE_POS 0 /**< CLKSEL_SOURCE Position */
#define MXC_F_WDT_CLKSEL_SOURCE ((uint32_t)(0x7UL << MXC_F_WDT_CLKSEL_SOURCE_POS)) /**< CLKSEL_SOURCE Mask */ #define MXC_F_WDT_CLKSEL_SOURCE ((uint32_t)(0x7UL << MXC_F_WDT_CLKSEL_SOURCE_POS)) /**< CLKSEL_SOURCE Mask */
/**@} end of group WDT_CLKSEL_Register */ /**@} end of group WDT_CLKSEL_Register */
@ -312,8 +312,8 @@ typedef struct {
* @brief Windowed Watchdog Timer Count Register. * @brief Windowed Watchdog Timer Count Register.
* @{ * @{
*/ */
#define MXC_F_WDT_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ #define MXC_F_WDT_CNT_COUNT_POS 0 /**< CNT_COUNT Position */
#define MXC_F_WDT_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_WDT_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ #define MXC_F_WDT_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_WDT_CNT_COUNT_POS)) /**< CNT_COUNT Mask */
/**@} end of group WDT_CNT_Register */ /**@} end of group WDT_CNT_Register */
@ -321,4 +321,4 @@ typedef struct {
} }
#endif #endif
#endif /* _WDT_REGS_H_ */ #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_WDT_REGS_H_

59
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c
View File

@ -1,5 +1,5 @@
/******************************************************************************* /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,6 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*
******************************************************************************/ ******************************************************************************/
#include <string.h> #include <string.h>
@ -37,9 +36,9 @@
#include <stdlib.h> #include <stdlib.h>
#include "max32670.h" #include "max32670.h"
#include "gcr_regs.h" #include "gcr_regs.h"
#include "pwrseq_regs.h"
#include "mxc_sys.h" #include "mxc_sys.h"
uint32_t SystemCoreClock = HIRC_FREQ; uint32_t SystemCoreClock = HIRC_FREQ;
__weak void SystemCoreClockUpdate(void) __weak void SystemCoreClockUpdate(void)
@ -48,36 +47,35 @@ __weak void SystemCoreClockUpdate(void)
// Get the clock source and frequency // Get the clock source and frequency
clk_src = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL); clk_src = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL);
switch (clk_src) switch (clk_src) {
{ case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK:
case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK: base_freq = EXTCLK_FREQ;
base_freq = EXTCLK_FREQ; break;
break; case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO:
case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO: base_freq = ERFO_FREQ;
base_freq = ERFO_FREQ; break;
break; case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO:
case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO: base_freq = INRO_FREQ;
base_freq = INRO_FREQ; break;
break; case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO:
case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO:
base_freq = IPO_FREQ; base_freq = IPO_FREQ;
break; break;
case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO: case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO:
base_freq = IBRO_FREQ; base_freq = IBRO_FREQ;
break; break;
case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO: case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO:
base_freq = ERTCO_FREQ; base_freq = ERTCO_FREQ;
break; break;
default: default:
// Codes 001 and 111 are reserved. // Codes 001 and 111 are reserved.
// This code should never execute, however, initialize to safe value. // This code should never execute, however, initialize to safe value.
base_freq = HIRC_FREQ; base_freq = HIRC_FREQ;
break; break;
} }
// Get the clock divider // Get the clock divider
if (clk_src == MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO) if (clk_src == MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO) {
{ base_freq = base_freq >> ((MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IPO_DIV) >>
base_freq = base_freq >> ((MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IPO_DIV)>> MXC_F_GCR_CLKCTRL_IPO_DIV_POS); MXC_F_GCR_CLKCTRL_IPO_DIV_POS);
} }
div = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_DIV) >> MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS; div = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_DIV) >> MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS;
@ -109,7 +107,6 @@ __weak int Board_Init(void)
__weak void low_level_init(void) __weak void low_level_init(void)
{ {
/* Do nothing */ /* Do nothing */
return;
} }
/* This function is called just before control is transferred to main(). /* This function is called just before control is transferred to main().

47
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/crc.h
View File

@ -3,8 +3,8 @@
* @brief cyclic redundancy check driver. * @brief cyclic redundancy check driver.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,10 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
#ifndef _CRC_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_CRC_H_
#define _CRC_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_CRC_H_
/***** Includes *****/ /***** Includes *****/
#include "crc_regs.h" #include "crc_regs.h"
@ -58,19 +58,16 @@ extern "C" {
* *
*/ */
typedef struct _mxc_crc_req_t { typedef struct _mxc_crc_req_t {
uint32_t* dataBuffer; ///< Pointer to the data uint32_t *dataBuffer; ///< Pointer to the data
uint32_t dataLen; ///< Length of the data uint32_t dataLen; ///< Length of the data
uint32_t resultCRC; ///< Calculated CRC value uint32_t resultCRC; ///< Calculated CRC value
} mxc_crc_req_t; } mxc_crc_req_t;
/** /**
* @brief CRC data bit order * @brief CRC data bit order
* *
*/ */
typedef enum { typedef enum { CRC_LSB_FIRST, CRC_MSB_FIRST } mxc_crc_bitorder_t;
CRC_LSB_FIRST,
CRC_MSB_FIRST
} mxc_crc_bitorder_t;
/***** Function Prototypes *****/ /***** Function Prototypes *****/
@ -84,14 +81,14 @@ typedef enum {
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_CRC_Init (void); int MXC_CRC_Init(void);
/** /**
* @brief Disable and reset portions of the CRC * @brief Disable and reset portions of the CRC
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_CRC_Shutdown (void); int MXC_CRC_Shutdown(void);
/** /**
* @brief This function should be called from the CRC ISR Handler * @brief This function should be called from the CRC ISR Handler
@ -99,56 +96,56 @@ int MXC_CRC_Shutdown (void);
* @param ch DMA channel * @param ch DMA channel
* @param error error * @param error error
*/ */
void MXC_CRC_Handler (int ch, int error); void MXC_CRC_Handler(int ch, int error);
/** /**
* @brief Set the bit-order of CRC calculation * @brief Set the bit-order of CRC calculation
* *
* @param bitOrder The direction to perform CRC calculation in * @param bitOrder The direction to perform CRC calculation in
*/ */
void MXC_CRC_SetDirection (mxc_crc_bitorder_t bitOrder); void MXC_CRC_SetDirection(mxc_crc_bitorder_t bitOrder);
/** /**
* @brief Set the bit-order of CRC calculation * @brief Set the bit-order of CRC calculation
* *
* @return The direction of calculation, 1 for MSB first, 0 for LSB first * @return The direction of calculation, 1 for MSB first, 0 for LSB first
*/ */
mxc_crc_bitorder_t MXC_CRC_GetDirection (void); mxc_crc_bitorder_t MXC_CRC_GetDirection(void);
/** /**
* @brief Byte Swap CRC Data Input * @brief Byte Swap CRC Data Input
* *
* @param bitOrder The direction to perform CRC calculation in * @param bitOrder The direction to perform CRC calculation in
*/ */
void MXC_CRC_SwapDataIn (mxc_crc_bitorder_t bitOrder); void MXC_CRC_SwapDataIn(mxc_crc_bitorder_t bitOrder);
/** /**
* @brief Byte Swap CRC Data output * @brief Byte Swap CRC Data output
* *
* @param bitOrder The direction to perform CRC calculation in * @param bitOrder The direction to perform CRC calculation in
*/ */
void MXC_CRC_SwapDataOut (mxc_crc_bitorder_t bitOrder); void MXC_CRC_SwapDataOut(mxc_crc_bitorder_t bitOrder);
/** /**
* @brief Set the Polynomial for CRC calculation * @brief Set the Polynomial for CRC calculation
* *
* @param poly The polynomial to use for CRC calculation * @param poly The polynomial to use for CRC calculation
*/ */
void MXC_CRC_SetPoly (uint32_t poly); void MXC_CRC_SetPoly(uint32_t poly);
/** /**
* @brief Get the polynomial for CRC calculation * @brief Get the polynomial for CRC calculation
* *
* @return The polynomial used in calculation * @return The polynomial used in calculation
*/ */
uint32_t MXC_CRC_GetPoly (void); uint32_t MXC_CRC_GetPoly(void);
/** /**
* @brief Get the result of a CRC calculation * @brief Get the result of a CRC calculation
* *
* @return The calculated CRC value * @return The calculated CRC value
*/ */
uint32_t MXC_CRC_GetResult (void); uint32_t MXC_CRC_GetResult(void);
/*******************************/ /*******************************/
/* High Level Functions */ /* High Level Functions */
@ -163,7 +160,7 @@ uint32_t MXC_CRC_GetResult (void);
* *
* @return see \ref MXC_Error_Codes for a list of return codes. * @return see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_CRC_Compute (mxc_crc_req_t* req); int MXC_CRC_Compute(mxc_crc_req_t *req);
/** /**
* @brief Perform a CRC computation using DMA * @brief Perform a CRC computation using DMA
@ -175,11 +172,11 @@ int MXC_CRC_Compute (mxc_crc_req_t* req);
* *
* @return see \ref MXC_Error_Codes for a list of return codes. * @return see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_CRC_ComputeAsync (mxc_crc_req_t* req); int MXC_CRC_ComputeAsync(mxc_crc_req_t *req);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
/**@} end of group crc */ /**@} end of group crc */
#endif /* _CRC_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_CRC_H_

190
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/dma.h
View File

@ -3,8 +3,8 @@
* @brief Direct Memory Access (DMA) driver function prototypes and data types. * @brief Direct Memory Access (DMA) driver function prototypes and data types.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,10 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
#ifndef _DMA_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_DMA_H_
#define _DMA_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_DMA_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdbool.h> #include <stdbool.h>
@ -61,60 +61,69 @@ extern "C" {
* *
*/ */
typedef enum { typedef enum {
MXC_DMA_PRIO_HIGH = MXC_V_DMA_CTRL_PRI_HIGH, ///< High Priority */ MXC_DMA_PRIO_HIGH = MXC_V_DMA_CTRL_PRI_HIGH, ///< High Priority */
MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CTRL_PRI_MEDHIGH, ///< Medium High Priority */ MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CTRL_PRI_MEDHIGH, ///< Medium High Priority */
MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CTRL_PRI_MEDLOW, ///< Medium Low Priority */ MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CTRL_PRI_MEDLOW, ///< Medium Low Priority */
MXC_DMA_PRIO_LOW = MXC_V_DMA_CTRL_PRI_LOW, ///< Low Priority */ MXC_DMA_PRIO_LOW = MXC_V_DMA_CTRL_PRI_LOW, ///< Low Priority */
} mxc_dma_priority_t; } mxc_dma_priority_t;
/** @brief DMA request select */ /** @brief DMA request select */
typedef enum { typedef enum {
MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection MXC_DMA_REQUEST_MEMTOMEM =
MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CTRL_REQUEST_SPI0RX, ///< SPI0 Receive DMA Request Selection MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection
MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CTRL_REQUEST_SPI1RX, ///< SPI1 Receive DMA Request Selection MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CTRL_REQUEST_SPI0RX, ///< SPI0 Receive DMA Request Selection
MXC_DMA_REQUEST_SPI2RX = MXC_S_DMA_CTRL_REQUEST_SPI2RX, ///< SPI2 Receive DMA Request Selection MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CTRL_REQUEST_SPI1RX, ///< SPI1 Receive DMA Request Selection
MXC_DMA_REQUEST_UART0RX = MXC_S_DMA_CTRL_REQUEST_UART0RX, ///< UART0 Receive DMA Request Selection MXC_DMA_REQUEST_SPI2RX = MXC_S_DMA_CTRL_REQUEST_SPI2RX, ///< SPI2 Receive DMA Request Selection
MXC_DMA_REQUEST_UART1RX = MXC_S_DMA_CTRL_REQUEST_UART1RX, ///< UART1 Receive DMA Request Selection MXC_DMA_REQUEST_UART0RX =
MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CTRL_REQUEST_I2C0RX, ///< I2C0 Receive DMA Request Selection MXC_S_DMA_CTRL_REQUEST_UART0RX, ///< UART0 Receive DMA Request Selection
MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CTRL_REQUEST_I2C1RX, ///< I2C1 Receive DMA Request Selection MXC_DMA_REQUEST_UART1RX =
MXC_DMA_REQUEST_I2C2RX = MXC_S_DMA_CTRL_REQUEST_I2C2RX, ///< I2C2 Receive DMA Request Selection MXC_S_DMA_CTRL_REQUEST_UART1RX, ///< UART1 Receive DMA Request Selection
MXC_DMA_REQUEST_UART2RX = MXC_S_DMA_CTRL_REQUEST_UART2RX, ///< UART2 Receive DMA Request Selection MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CTRL_REQUEST_I2C0RX, ///< I2C0 Receive DMA Request Selection
MXC_DMA_REQUEST_AESRX = MXC_S_DMA_CTRL_REQUEST_AESRX, ///< AES Receive DMA Request Selection MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CTRL_REQUEST_I2C1RX, ///< I2C1 Receive DMA Request Selection
MXC_DMA_REQUEST_UART3RX = MXC_S_DMA_CTRL_REQUEST_UART3RX, ///< UART3 Receive DMA Request Selection MXC_DMA_REQUEST_I2C2RX = MXC_S_DMA_CTRL_REQUEST_I2C2RX, ///< I2C2 Receive DMA Request Selection
MXC_DMA_REQUEST_I2SRX = MXC_S_DMA_CTRL_REQUEST_I2SRX, ///< I2S Receive DMA Request Selection MXC_DMA_REQUEST_UART2RX =
MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CTRL_REQUEST_SPI0TX, ///< SPI0 Transmit DMA Request Selection MXC_S_DMA_CTRL_REQUEST_UART2RX, ///< UART2 Receive DMA Request Selection
MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CTRL_REQUEST_SPI1TX, ///< SPI1 Transmit DMA Request Selection MXC_DMA_REQUEST_AESRX = MXC_S_DMA_CTRL_REQUEST_AESRX, ///< AES Receive DMA Request Selection
MXC_DMA_REQUEST_SPI2TX = MXC_S_DMA_CTRL_REQUEST_SPI2TX, ///< SPI2 Transmit DMA Request Selection MXC_DMA_REQUEST_UART3RX =
MXC_DMA_REQUEST_UART0TX = MXC_S_DMA_CTRL_REQUEST_UART0TX, ///< UART0 Transmit DMA Request Selection MXC_S_DMA_CTRL_REQUEST_UART3RX, ///< UART3 Receive DMA Request Selection
MXC_DMA_REQUEST_UART1TX = MXC_S_DMA_CTRL_REQUEST_UART1TX, ///< UART1 Transmit DMA Request Selection MXC_DMA_REQUEST_I2SRX = MXC_S_DMA_CTRL_REQUEST_I2SRX, ///< I2S Receive DMA Request Selection
MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CTRL_REQUEST_I2C0TX, ///< I2C0 Transmit DMA Request Selection MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CTRL_REQUEST_SPI0TX, ///< SPI0 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CTRL_REQUEST_I2C1TX, ///< I2C1 Transmit DMA Request Selection MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CTRL_REQUEST_SPI1TX, ///< SPI1 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2C2TX = MXC_S_DMA_CTRL_REQUEST_I2C2TX, ///< I2C2 Transmit DMA Request Selection MXC_DMA_REQUEST_SPI2TX = MXC_S_DMA_CTRL_REQUEST_SPI2TX, ///< SPI2 Transmit DMA Request Selection
MXC_DMA_REQUEST_CRCTX = MXC_S_DMA_CTRL_REQUEST_CRCTX, ///< CRC Transmit DMA Request Selection MXC_DMA_REQUEST_UART0TX =
MXC_DMA_REQUEST_UART2TX = MXC_S_DMA_CTRL_REQUEST_UART2TX, ///< UART2 Transmit DMA Request Selection MXC_S_DMA_CTRL_REQUEST_UART0TX, ///< UART0 Transmit DMA Request Selection
MXC_DMA_REQUEST_AESTX = MXC_S_DMA_CTRL_REQUEST_AESTX, ///< AES Transmit DMA Request Selection MXC_DMA_REQUEST_UART1TX =
MXC_DMA_REQUEST_UART3TX = MXC_S_DMA_CTRL_REQUEST_UART3TX, ///< UART3 Transmit DMA Request Selection MXC_S_DMA_CTRL_REQUEST_UART1TX, ///< UART1 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2STX = MXC_S_DMA_CTRL_REQUEST_I2STX, ///< I2S Transmit DMA Request Selection MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CTRL_REQUEST_I2C0TX, ///< I2C0 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CTRL_REQUEST_I2C1TX, ///< I2C1 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2C2TX = MXC_S_DMA_CTRL_REQUEST_I2C2TX, ///< I2C2 Transmit DMA Request Selection
MXC_DMA_REQUEST_CRCTX = MXC_S_DMA_CTRL_REQUEST_CRCTX, ///< CRC Transmit DMA Request Selection
MXC_DMA_REQUEST_UART2TX =
MXC_S_DMA_CTRL_REQUEST_UART2TX, ///< UART2 Transmit DMA Request Selection
MXC_DMA_REQUEST_AESTX = MXC_S_DMA_CTRL_REQUEST_AESTX, ///< AES Transmit DMA Request Selection
MXC_DMA_REQUEST_UART3TX =
MXC_S_DMA_CTRL_REQUEST_UART3TX, ///< UART3 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2STX = MXC_S_DMA_CTRL_REQUEST_I2STX, ///< I2S Transmit DMA Request Selection
} mxc_dma_reqsel_t; } mxc_dma_reqsel_t;
/** @brief Enumeration for the DMA prescaler */ /** @brief Enumeration for the DMA prescaler */
typedef enum { typedef enum {
MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CTRL_TO_CLKDIV_DIS, ///< Prescaler disabled MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CTRL_TO_CLKDIV_DIS, ///< Prescaler disabled
MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CTRL_TO_CLKDIV_DIV256, ///< Divide by 256 MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CTRL_TO_CLKDIV_DIV256, ///< Divide by 256
MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K, ///< Divide by 65,536 MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K, ///< Divide by 65,536
MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M, ///< Divide by 16,777,216 MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M, ///< Divide by 16,777,216
} mxc_dma_prescale_t; } mxc_dma_prescale_t;
/** @brief Enumeration for the DMA timeout value */ /** @brief Enumeration for the DMA timeout value */
typedef enum { typedef enum {
MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CTRL_TO_PER_TO4, ///< DMA timeout of 4 clocks MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CTRL_TO_PER_TO4, ///< DMA timeout of 4 clocks
MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CTRL_TO_PER_TO8, ///< DMA timeout of 8 clocks MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CTRL_TO_PER_TO8, ///< DMA timeout of 8 clocks
MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CTRL_TO_PER_TO16, ///< DMA timeout of 16 clocks MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CTRL_TO_PER_TO16, ///< DMA timeout of 16 clocks
MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CTRL_TO_PER_TO32, ///< DMA timeout of 32 clocks MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CTRL_TO_PER_TO32, ///< DMA timeout of 32 clocks
MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CTRL_TO_PER_TO64, ///< DMA timeout of 64 clocks MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CTRL_TO_PER_TO64, ///< DMA timeout of 64 clocks
MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CTRL_TO_PER_TO128, ///< DMA timeout of 128 clocks MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CTRL_TO_PER_TO128, ///< DMA timeout of 128 clocks
MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CTRL_TO_PER_TO256, ///< DMA timeout of 256 clocks MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CTRL_TO_PER_TO256, ///< DMA timeout of 256 clocks
MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CTRL_TO_PER_TO512, ///< DMA timeout of 512 clocks MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CTRL_TO_PER_TO512, ///< DMA timeout of 512 clocks
} mxc_dma_timeout_t; } mxc_dma_timeout_t;
/** @brief DMA transfer data width */ /** @brief DMA transfer data width */
@ -122,9 +131,9 @@ typedef enum {
/* Using the '_V_' define instead of the '_S_' since these same values will be used to /* Using the '_V_' define instead of the '_S_' since these same values will be used to
specify the DSTWD also. The API functions will shift the value the correct amount specify the DSTWD also. The API functions will shift the value the correct amount
prior to writing the cfg register. */ prior to writing the cfg register. */
MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CTRL_SRCWD_BYTE, ///< DMA transfer in bytes MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CTRL_SRCWD_BYTE, ///< DMA transfer in bytes
MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CTRL_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CTRL_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words
MXC_DMA_WIDTH_WORD = MXC_V_DMA_CTRL_SRCWD_WORD, ///< DMA transfer in 32-bit words MXC_DMA_WIDTH_WORD = MXC_V_DMA_CTRL_SRCWD_WORD, ///< DMA transfer in 32-bit words
} mxc_dma_width_t; } mxc_dma_width_t;
/** /**
@ -133,12 +142,12 @@ typedef enum {
* *
*/ */
typedef struct { typedef struct {
int ch; ///< The channel to load the configuration data into int ch; ///< The channel to load the configuration data into
mxc_dma_reqsel_t reqsel;///< The request select line to be used (mem2mem, peripheral) mxc_dma_reqsel_t reqsel; ///< The request select line to be used (mem2mem, peripheral)
mxc_dma_width_t srcwd; ///< The source width (could be dependent on FIFO width) mxc_dma_width_t srcwd; ///< The source width (could be dependent on FIFO width)
mxc_dma_width_t dstwd; ///< The destination width (could be dependent on FIFO width) mxc_dma_width_t dstwd; ///< The destination width (could be dependent on FIFO width)
int srcinc_en; ///< Whether to increment the source address during the transfer int srcinc_en; ///< Whether to increment the source address during the transfer
int dstinc_en; ///< Whether to increment the source address during the transfer int dstinc_en; ///< Whether to increment the source address during the transfer
} mxc_dma_config_t; } mxc_dma_config_t;
/** /**
@ -146,10 +155,10 @@ typedef struct {
* *
*/ */
typedef struct { typedef struct {
int ch; ///< The channel to use for the transfer int ch; ///< The channel to use for the transfer
void* source; ///< Pointer to the source address, if applicable void *source; ///< Pointer to the source address, if applicable
void* dest; ///< Pointer to the destination address, if applicable void *dest; ///< Pointer to the destination address, if applicable
int len; ///< Number of bytes to transfer int len; ///< Number of bytes to transfer
} mxc_dma_srcdst_t; } mxc_dma_srcdst_t;
/** /**
@ -159,12 +168,12 @@ typedef struct {
* *
*/ */
typedef struct { typedef struct {
int ch; ///< The channel to use for the transfer int ch; ///< The channel to use for the transfer
mxc_dma_priority_t prio; ///< The DMA priority for the channel mxc_dma_priority_t prio; ///< The DMA priority for the channel
unsigned int reqwait_en; ///< Delay the timeout timer start until after first transfer unsigned int reqwait_en; ///< Delay the timeout timer start until after first transfer
mxc_dma_timeout_t tosel; ///< Number of prescaled clocks seen by the channel before a timeout mxc_dma_timeout_t tosel; ///< Number of prescaled clocks seen by the channel before a timeout
mxc_dma_prescale_t pssel; ///< Prescaler for the timeout timer mxc_dma_prescale_t pssel; ///< Prescaler for the timeout timer
unsigned int burst_size; ///< Number of bytes moved in a single burst unsigned int burst_size; ///< Number of bytes moved in a single burst
} mxc_dma_adv_config_t; } mxc_dma_adv_config_t;
/** /**
@ -172,7 +181,7 @@ typedef struct {
* *
* @param dest Pointer to the destination of the copy * @param dest Pointer to the destination of the copy
*/ */
typedef void (*mxc_dma_complete_cb_t) (void* dest); typedef void (*mxc_dma_complete_cb_t)(void *dest);
/** /**
* @brief The callback called on completion of a transfer, * @brief The callback called on completion of a transfer,
@ -185,7 +194,7 @@ typedef void (*mxc_dma_complete_cb_t) (void* dest);
* @return Returns the next transfer to be completed, or NULL * @return Returns the next transfer to be completed, or NULL
* if no more transfers will be done * if no more transfers will be done
*/ */
typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t) (mxc_dma_srcdst_t dest); typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest);
/* **** Function Prototypes **** */ /* **** Function Prototypes **** */
/*************************/ /*************************/
@ -196,7 +205,7 @@ typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t) (mxc_dma_srcdst_t dest);
* @details This initialization is required before using the DMA driver functions. * @details This initialization is required before using the DMA driver functions.
* @return #E_NO_ERROR if successful * @return #E_NO_ERROR if successful
*/ */
int MXC_DMA_Init (void); int MXC_DMA_Init(void);
/** /**
* @brief Request DMA channel * @brief Request DMA channel
@ -207,7 +216,7 @@ int MXC_DMA_Init (void);
* @return #E_BAD_STATE DMA is not initialized, call MXC_DMA_Init() first. * @return #E_BAD_STATE DMA is not initialized, call MXC_DMA_Init() first.
* @return #E_BUSY DMA is currently busy (locked), try again later. * @return #E_BUSY DMA is currently busy (locked), try again later.
*/ */
int MXC_DMA_AcquireChannel (void); int MXC_DMA_AcquireChannel(void);
/** /**
* @brief Release DMA channel * @brief Release DMA channel
@ -217,7 +226,7 @@ int MXC_DMA_AcquireChannel (void);
* *
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/ */
int MXC_DMA_ReleaseChannel (int ch); int MXC_DMA_ReleaseChannel(int ch);
/** /**
* @brief Configure the DMA channel * @brief Configure the DMA channel
@ -228,7 +237,7 @@ int MXC_DMA_ReleaseChannel (int ch);
* *
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/ */
int MXC_DMA_ConfigChannel (mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); int MXC_DMA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst);
/** /**
* @brief Configure the DMA channel with more advanced parameters * @brief Configure the DMA channel with more advanced parameters
@ -237,7 +246,7 @@ int MXC_DMA_ConfigChannel (mxc_dma_config_t config, mxc_dma_srcdst_t srcdst);
* *
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/ */
int MXC_DMA_AdvConfigChannel (mxc_dma_adv_config_t advConfig); int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig);
/** /**
* @brief Set channel source, destination, and count for the transfer * @brief Set channel source, destination, and count for the transfer
@ -248,7 +257,7 @@ int MXC_DMA_AdvConfigChannel (mxc_dma_adv_config_t advConfig);
* Guide for more information. * Guide for more information.
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/ */
int MXC_DMA_SetSrcDst (mxc_dma_srcdst_t srcdst); int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst);
/** /**
* @brief Get channel source, destination, and count for transfer * @brief Get channel source, destination, and count for transfer
@ -257,7 +266,7 @@ int MXC_DMA_SetSrcDst (mxc_dma_srcdst_t srcdst);
* *
* @return See \ref MXC_Error_Codes for a list of return values * @return See \ref MXC_Error_Codes for a list of return values
*/ */
int MXC_DMA_GetSrcDst (mxc_dma_srcdst_t* srcdst); int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst);
/** /**
* @brief Set channel reload source, destination, and count for the transfer * @brief Set channel reload source, destination, and count for the transfer
@ -268,7 +277,7 @@ int MXC_DMA_GetSrcDst (mxc_dma_srcdst_t* srcdst);
* Guide for more information. * Guide for more information.
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/ */
int MXC_DMA_SetSrcReload (mxc_dma_srcdst_t srcdstReload); int MXC_DMA_SetSrcReload(mxc_dma_srcdst_t srcdstReload);
/** /**
* @brief Get channel reload source, destination, and count for transfer * @brief Get channel reload source, destination, and count for transfer
@ -277,7 +286,7 @@ int MXC_DMA_SetSrcReload (mxc_dma_srcdst_t srcdstReload);
* *
* @return See \ref MXC_Error_Codes for a list of return values * @return See \ref MXC_Error_Codes for a list of return values
*/ */
int MXC_DMA_GetSrcReload (mxc_dma_srcdst_t* srcdstReload); int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdstReload);
/** /**
* @brief Set channel interrupt callback * @brief Set channel interrupt callback
@ -301,7 +310,7 @@ int MXC_DMA_GetSrcReload (mxc_dma_srcdst_t* srcdstReload);
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR
* otherwise * otherwise
*/ */
int MXC_DMA_SetCallback (int ch, void (*callback) (int, int)); int MXC_DMA_SetCallback(int ch, void (*callback)(int, int));
/** /**
* @brief Set channel interrupt * @brief Set channel interrupt
@ -323,7 +332,7 @@ int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz);
* @param flags The flags to enable * @param flags The flags to enable
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/ */
int MXC_DMA_ChannelEnableInt (int ch, int flags); int MXC_DMA_ChannelEnableInt(int ch, int flags);
/** /**
* @brief Disable channel interrupt * @brief Disable channel interrupt
@ -331,14 +340,14 @@ int MXC_DMA_ChannelEnableInt (int ch, int flags);
* @param flags The flags to disable * @param flags The flags to disable
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/ */
int MXC_DMA_ChannelDisableInt (int ch, int flags); int MXC_DMA_ChannelDisableInt(int ch, int flags);
/** /**
* @brief Read channel interrupt flags * @brief Read channel interrupt flags
* @param ch channel handle * @param ch channel handle
* @return #E_BAD_PARAM if an unused or invalid channel handle, flags otherwise * @return #E_BAD_PARAM if an unused or invalid channel handle, flags otherwise
*/ */
int MXC_DMA_ChannelGetFlags (int ch); int MXC_DMA_ChannelGetFlags(int ch);
/** /**
* @brief Clear channel interrupt flags * @brief Clear channel interrupt flags
@ -346,7 +355,7 @@ int MXC_DMA_ChannelGetFlags (int ch);
* @param flags The flags to clear * @param flags The flags to clear
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/ */
int MXC_DMA_ChannelClearFlags (int ch, int flags); int MXC_DMA_ChannelClearFlags(int ch, int flags);
/** /**
* @brief Enable channel interrupt * @brief Enable channel interrupt
@ -355,14 +364,14 @@ int MXC_DMA_ChannelClearFlags (int ch, int flags);
* @param ch channel handle * @param ch channel handle
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/ */
int MXC_DMA_EnableInt (int ch); int MXC_DMA_EnableInt(int ch);
/** /**
* @brief Disable channel interrupt * @brief Disable channel interrupt
* @param ch channel handle * @param ch channel handle
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/ */
int MXC_DMA_DisableInt (int ch); int MXC_DMA_DisableInt(int ch);
/** /**
* @brief Start transfer * @brief Start transfer
@ -370,14 +379,14 @@ int MXC_DMA_DisableInt (int ch);
* @details Start the DMA channel transfer, assumes that MXC_DMA_SetSrcDstCnt() has been called beforehand. * @details Start the DMA channel transfer, assumes that MXC_DMA_SetSrcDstCnt() has been called beforehand.
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/ */
int MXC_DMA_Start (int ch); int MXC_DMA_Start(int ch);
/** /**
* @brief Stop DMA transfer, irrespective of status (complete or in-progress) * @brief Stop DMA transfer, irrespective of status (complete or in-progress)
* @param ch channel handle * @param ch channel handle
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/ */
int MXC_DMA_Stop (int ch); int MXC_DMA_Stop(int ch);
/** /**
* @brief Get a pointer to the DMA channel registers * @brief Get a pointer to the DMA channel registers
@ -386,7 +395,7 @@ int MXC_DMA_Stop (int ch);
* function can be used on a channel handle returned by MXC_DMA_AcquireChannel(). * function can be used on a channel handle returned by MXC_DMA_AcquireChannel().
* @return NULL if an unused or invalid channel handle, or a valid pointer otherwise * @return NULL if an unused or invalid channel handle, or a valid pointer otherwise
*/ */
mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs (int ch); mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch);
/** /**
* @brief Interrupt handler function * @brief Interrupt handler function
@ -411,7 +420,7 @@ void MXC_DMA_Handler();
* *
* @return see \ref MXC_Error_Codes * @return see \ref MXC_Error_Codes
*/ */
int MXC_DMA_MemCpy (void* dest, void* src, int len, mxc_dma_complete_cb_t callback); int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback);
/** /**
* @brief Performs a memcpy, using DMA, optionally asynchronous * @brief Performs a memcpy, using DMA, optionally asynchronous
@ -424,7 +433,8 @@ int MXC_DMA_MemCpy (void* dest, void* src, int len, mxc_dma_complete_cb_t callba
* *
* @return see \ref MXC_Error_Codes * @return see \ref MXC_Error_Codes
*/ */
int MXC_DMA_DoTransfer (mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback); int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst,
mxc_dma_trans_chain_t callback);
/** /**
* For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver * For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver
*/ */
@ -434,4 +444,4 @@ int MXC_DMA_DoTransfer (mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, m
} }
#endif #endif
#endif /* _DMA_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_DMA_H_

62
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/flc.h
View File

@ -4,8 +4,8 @@
* @details This driver can be used to operate on the embedded flash memory. * @details This driver can be used to operate on the embedded flash memory.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -35,10 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
#ifndef _FLC_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_FLC_H_
#define _FLC_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_FLC_H_
/* **** Includes **** */ /* **** Includes **** */
#include "flc_regs.h" #include "flc_regs.h"
@ -57,10 +57,10 @@ extern "C" {
/***** Definitions *****/ /***** Definitions *****/
/// Bit mask that can be used to find the starting address of a page in flash /// Bit mask that can be used to find the starting address of a page in flash
#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1) #define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1)
/// Calculate the address of a page in flash from the page number /// Calculate the address of a page in flash from the page number
#define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE)) #define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((uint32_t)page * MXC_FLASH_PAGE_SIZE))
/***** Function Prototypes *****/ /***** Function Prototypes *****/
@ -76,14 +76,14 @@ int MXC_FLC_Init();
* with an erase or write operation. * with an erase or write operation.
* @return If non-zero, flash operation is in progress * @return If non-zero, flash operation is in progress
*/ */
int MXC_FLC_Busy (void); int MXC_FLC_Busy(void);
/** /**
* @brief Erases the entire flash array. * @brief Erases the entire flash array.
* @note This function must be executed from RAM. * @note This function must be executed from RAM.
* @return #E_NO_ERROR If function is successful. * @return #E_NO_ERROR If function is successful.
*/ */
int MXC_FLC_MassErase (void); int MXC_FLC_MassErase(void);
/** /**
* @brief Erases the page of flash at the specified address. * @brief Erases the page of flash at the specified address.
@ -91,7 +91,7 @@ int MXC_FLC_MassErase (void);
* @param address Any address within the page to erase. * @param address Any address within the page to erase.
* @return #E_NO_ERROR If function is successful. * @return #E_NO_ERROR If function is successful.
*/ */
int MXC_FLC_PageErase (uint32_t address); int MXC_FLC_PageErase(uint32_t address);
/** /**
* @brief Read Data out of Flash from an address * @brief Read Data out of Flash from an address
@ -101,7 +101,7 @@ int MXC_FLC_PageErase (uint32_t address);
* @param[in] len The length of the buffer * @param[in] len The length of the buffer
* *
*/ */
void MXC_FLC_Read (int address, void* buffer, int len); void MXC_FLC_Read(int address, void *buffer, int len);
/** /**
* @brief Writes data to flash. * @brief Writes data to flash.
@ -112,7 +112,7 @@ void MXC_FLC_Read (int address, void* buffer, int len);
* @return #E_NO_ERROR If function is successful. * @return #E_NO_ERROR If function is successful.
* @note make sure to disable ICC with ICC_Disable(); before Running this function * @note make sure to disable ICC with ICC_Disable(); before Running this function
*/ */
int MXC_FLC_Write (uint32_t address, uint32_t length, uint32_t *buffer); int MXC_FLC_Write(uint32_t address, uint32_t length, uint32_t *buffer);
/** /**
* @brief Writes 32 bits of data to flash. * @brief Writes 32 bits of data to flash.
@ -122,7 +122,7 @@ int MXC_FLC_Write (uint32_t address, uint32_t length, uint32_t *buffer);
* @return #E_NO_ERROR If function is successful. * @return #E_NO_ERROR If function is successful.
* @note make sure to disable ICC with ICC_Disable(); before Running this function * @note make sure to disable ICC with ICC_Disable(); before Running this function
*/ */
int MXC_FLC_Write32 (uint32_t address, uint32_t data); int MXC_FLC_Write32(uint32_t address, uint32_t data);
/** /**
* @brief Writes 128 bits of data to flash. * @brief Writes 128 bits of data to flash.
@ -132,27 +132,27 @@ int MXC_FLC_Write32 (uint32_t address, uint32_t data);
* @return #E_NO_ERROR If function is successful. * @return #E_NO_ERROR If function is successful.
* @note make sure to disable ICC with ICC_Disable(); before Running this function * @note make sure to disable ICC with ICC_Disable(); before Running this function
*/ */
int MXC_FLC_Write128 (uint32_t address, uint32_t *data); int MXC_FLC_Write128(uint32_t address, uint32_t *data);
/** /**
* @brief Enable flash interrupts * @brief Enable flash interrupts
* @param flags Interrupts to enable * @param flags Interrupts to enable
* @return #E_NO_ERROR If function is successful. * @return #E_NO_ERROR If function is successful.
*/ */
int MXC_FLC_EnableInt (uint32_t flags); int MXC_FLC_EnableInt(uint32_t flags);
/** /**
* @brief Disable flash interrupts * @brief Disable flash interrupts
* @param flags Interrupts to disable * @param flags Interrupts to disable
* @return #E_NO_ERROR If function is successful. * @return #E_NO_ERROR If function is successful.
*/ */
int MXC_FLC_DisableInt (uint32_t flags); int MXC_FLC_DisableInt(uint32_t flags);
/** /**
* @brief Retrieve flash interrupt flags * @brief Retrieve flash interrupt flags
* @return Interrupt flags registers * @return Interrupt flags registers
*/ */
int MXC_FLC_GetFlags (void); int MXC_FLC_GetFlags(void);
/** /**
* @brief Clear flash interrupt flags * @brief Clear flash interrupt flags
@ -160,7 +160,7 @@ int MXC_FLC_GetFlags (void);
* @param flags Flag bit(s) to clear * @param flags Flag bit(s) to clear
* @return #E_NO_ERROR If function is successful. * @return #E_NO_ERROR If function is successful.
*/ */
int MXC_FLC_ClearFlags (uint32_t flags); int MXC_FLC_ClearFlags(uint32_t flags);
/** /**
* @brief Unlock info block * @brief Unlock info block
@ -169,7 +169,7 @@ int MXC_FLC_ClearFlags (uint32_t flags);
* *
* @return #E_NO_ERROR If function is successful. * @return #E_NO_ERROR If function is successful.
*/ */
int MXC_FLC_UnlockInfoBlock (uint32_t address); int MXC_FLC_UnlockInfoBlock(uint32_t address);
/** /**
* @brief Lock info block * @brief Lock info block
@ -177,7 +177,27 @@ int MXC_FLC_UnlockInfoBlock (uint32_t address);
* @param[in] address The address in the info block that was written to * @param[in] address The address in the info block that was written to
* @return #E_NO_ERROR If function is successful. * @return #E_NO_ERROR If function is successful.
*/ */
int MXC_FLC_LockInfoBlock (uint32_t address); int MXC_FLC_LockInfoBlock(uint32_t address);
/**
* @brief Blocks write operations to the flash page associated with the 'address' argument
* @note Flash pages cannot be unblocked except for on POR and external resets
*
* @param address Absolute address located anywhere in the flash page to be locked (does not need to be word-aligned)
*
* @return #E_NO_ERROR If function is successful.
*/
int MXC_FLC_BlockPageWrite(uint32_t address);
/**
* @brief Blocks read operations from the flash page associated with the 'address' argument
* @note Flash pages cannot be unblocked except for on POR and external resets
*
* @param address Absolute address located anywhere in the flash page to be locked (does not need to be word-aligned)
*
* @return #E_NO_ERROR If function is successful.
*/
int MXC_FLC_BlockPageRead(uint32_t address);
/**@} end of group flc */ /**@} end of group flc */
@ -185,4 +205,4 @@ int MXC_FLC_LockInfoBlock (uint32_t address);
} }
#endif #endif
#endif /* _FLC_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_FLC_H_

169
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/gpio.h
View File

@ -3,8 +3,8 @@
* @brief General-Purpose Input/Output (GPIO) function prototypes and data types. * @brief General-Purpose Input/Output (GPIO) function prototypes and data types.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
/* Define to prevent redundant inclusion */ /* Define to prevent redundant inclusion */
#ifndef _GPIO_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_GPIO_H_
#define _GPIO_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_GPIO_H_
/* **** Includes **** */ /* **** Includes **** */
#include "gpio_regs.h" #include "gpio_regs.h"
@ -62,48 +62,48 @@ extern "C" {
* @ingroup gpio_port_pin * @ingroup gpio_port_pin
* @{ * @{
*/ */
#define MXC_GPIO_PORT_0 ((uint32_t)(1UL << 0)) ///< Port 0 Define #define MXC_GPIO_PORT_0 ((uint32_t)(1UL << 0)) ///< Port 0 Define
#define MXC_GPIO_PORT_1 ((uint32_t)(1UL << 1)) ///< Port 1 Define #define MXC_GPIO_PORT_1 ((uint32_t)(1UL << 1)) ///< Port 1 Define
#define MXC_GPIO_PORT_2 ((uint32_t)(1UL << 2)) ///< Port 2 Define #define MXC_GPIO_PORT_2 ((uint32_t)(1UL << 2)) ///< Port 2 Define
#define MXC_GPIO_PORT_3 ((uint32_t)(1UL << 3)) ///< Port 3 Define #define MXC_GPIO_PORT_3 ((uint32_t)(1UL << 3)) ///< Port 3 Define
/**@} end of gpio_port group*/ /**@} end of gpio_port group*/
/** /**
* @defgroup gpio_pin Pin Definitions * @defgroup gpio_pin Pin Definitions
* @ingroup gpio_port_pin * @ingroup gpio_port_pin
* @{ * @{
*/ */
#define MXC_GPIO_PIN_0 ((uint32_t)(1UL << 0)) ///< Pin 0 Define #define MXC_GPIO_PIN_0 ((uint32_t)(1UL << 0)) ///< Pin 0 Define
#define MXC_GPIO_PIN_1 ((uint32_t)(1UL << 1)) ///< Pin 1 Define #define MXC_GPIO_PIN_1 ((uint32_t)(1UL << 1)) ///< Pin 1 Define
#define MXC_GPIO_PIN_2 ((uint32_t)(1UL << 2)) ///< Pin 2 Define #define MXC_GPIO_PIN_2 ((uint32_t)(1UL << 2)) ///< Pin 2 Define
#define MXC_GPIO_PIN_3 ((uint32_t)(1UL << 3)) ///< Pin 3 Define #define MXC_GPIO_PIN_3 ((uint32_t)(1UL << 3)) ///< Pin 3 Define
#define MXC_GPIO_PIN_4 ((uint32_t)(1UL << 4)) ///< Pin 4 Define #define MXC_GPIO_PIN_4 ((uint32_t)(1UL << 4)) ///< Pin 4 Define
#define MXC_GPIO_PIN_5 ((uint32_t)(1UL << 5)) ///< Pin 5 Define #define MXC_GPIO_PIN_5 ((uint32_t)(1UL << 5)) ///< Pin 5 Define
#define MXC_GPIO_PIN_6 ((uint32_t)(1UL << 6)) ///< Pin 6 Define #define MXC_GPIO_PIN_6 ((uint32_t)(1UL << 6)) ///< Pin 6 Define
#define MXC_GPIO_PIN_7 ((uint32_t)(1UL << 7)) ///< Pin 7 Define #define MXC_GPIO_PIN_7 ((uint32_t)(1UL << 7)) ///< Pin 7 Define
#define MXC_GPIO_PIN_8 ((uint32_t)(1UL << 8)) ///< Pin 8 Define #define MXC_GPIO_PIN_8 ((uint32_t)(1UL << 8)) ///< Pin 8 Define
#define MXC_GPIO_PIN_9 ((uint32_t)(1UL << 9)) ///< Pin 9 Define #define MXC_GPIO_PIN_9 ((uint32_t)(1UL << 9)) ///< Pin 9 Define
#define MXC_GPIO_PIN_10 ((uint32_t)(1UL << 10)) ///< Pin 10 Define #define MXC_GPIO_PIN_10 ((uint32_t)(1UL << 10)) ///< Pin 10 Define
#define MXC_GPIO_PIN_11 ((uint32_t)(1UL << 11)) ///< Pin 11 Define #define MXC_GPIO_PIN_11 ((uint32_t)(1UL << 11)) ///< Pin 11 Define
#define MXC_GPIO_PIN_12 ((uint32_t)(1UL << 12)) ///< Pin 12 Define #define MXC_GPIO_PIN_12 ((uint32_t)(1UL << 12)) ///< Pin 12 Define
#define MXC_GPIO_PIN_13 ((uint32_t)(1UL << 13)) ///< Pin 13 Define #define MXC_GPIO_PIN_13 ((uint32_t)(1UL << 13)) ///< Pin 13 Define
#define MXC_GPIO_PIN_14 ((uint32_t)(1UL << 14)) ///< Pin 14 Define #define MXC_GPIO_PIN_14 ((uint32_t)(1UL << 14)) ///< Pin 14 Define
#define MXC_GPIO_PIN_15 ((uint32_t)(1UL << 15)) ///< Pin 15 Define #define MXC_GPIO_PIN_15 ((uint32_t)(1UL << 15)) ///< Pin 15 Define
#define MXC_GPIO_PIN_16 ((uint32_t)(1UL << 16)) ///< Pin 16 Define #define MXC_GPIO_PIN_16 ((uint32_t)(1UL << 16)) ///< Pin 16 Define
#define MXC_GPIO_PIN_17 ((uint32_t)(1UL << 17)) ///< Pin 17 Define #define MXC_GPIO_PIN_17 ((uint32_t)(1UL << 17)) ///< Pin 17 Define
#define MXC_GPIO_PIN_18 ((uint32_t)(1UL << 18)) ///< Pin 18 Define #define MXC_GPIO_PIN_18 ((uint32_t)(1UL << 18)) ///< Pin 18 Define
#define MXC_GPIO_PIN_19 ((uint32_t)(1UL << 19)) ///< Pin 19 Define #define MXC_GPIO_PIN_19 ((uint32_t)(1UL << 19)) ///< Pin 19 Define
#define MXC_GPIO_PIN_20 ((uint32_t)(1UL << 20)) ///< Pin 20 Define #define MXC_GPIO_PIN_20 ((uint32_t)(1UL << 20)) ///< Pin 20 Define
#define MXC_GPIO_PIN_21 ((uint32_t)(1UL << 21)) ///< Pin 21 Define #define MXC_GPIO_PIN_21 ((uint32_t)(1UL << 21)) ///< Pin 21 Define
#define MXC_GPIO_PIN_22 ((uint32_t)(1UL << 22)) ///< Pin 22 Define #define MXC_GPIO_PIN_22 ((uint32_t)(1UL << 22)) ///< Pin 22 Define
#define MXC_GPIO_PIN_23 ((uint32_t)(1UL << 23)) ///< Pin 23 Define #define MXC_GPIO_PIN_23 ((uint32_t)(1UL << 23)) ///< Pin 23 Define
#define MXC_GPIO_PIN_24 ((uint32_t)(1UL << 24)) ///< Pin 24 Define #define MXC_GPIO_PIN_24 ((uint32_t)(1UL << 24)) ///< Pin 24 Define
#define MXC_GPIO_PIN_25 ((uint32_t)(1UL << 25)) ///< Pin 25 Define #define MXC_GPIO_PIN_25 ((uint32_t)(1UL << 25)) ///< Pin 25 Define
#define MXC_GPIO_PIN_26 ((uint32_t)(1UL << 26)) ///< Pin 26 Define #define MXC_GPIO_PIN_26 ((uint32_t)(1UL << 26)) ///< Pin 26 Define
#define MXC_GPIO_PIN_27 ((uint32_t)(1UL << 27)) ///< Pin 27 Define #define MXC_GPIO_PIN_27 ((uint32_t)(1UL << 27)) ///< Pin 27 Define
#define MXC_GPIO_PIN_28 ((uint32_t)(1UL << 28)) ///< Pin 28 Define #define MXC_GPIO_PIN_28 ((uint32_t)(1UL << 28)) ///< Pin 28 Define
#define MXC_GPIO_PIN_29 ((uint32_t)(1UL << 29)) ///< Pin 29 Define #define MXC_GPIO_PIN_29 ((uint32_t)(1UL << 29)) ///< Pin 29 Define
#define MXC_GPIO_PIN_30 ((uint32_t)(1UL << 30)) ///< Pin 30 Define #define MXC_GPIO_PIN_30 ((uint32_t)(1UL << 30)) ///< Pin 30 Define
#define MXC_GPIO_PIN_31 ((uint32_t)(1UL << 31)) ///< Pin 31 Define #define MXC_GPIO_PIN_31 ((uint32_t)(1UL << 31)) ///< Pin 31 Define
/**@} end of gpio_pin group */ /**@} end of gpio_pin group */
/**@} end of gpio_port_pin group */ /**@} end of gpio_port_pin group */
@ -115,65 +115,65 @@ extern "C" {
* @param cbdata A void pointer to the data type as registered when * @param cbdata A void pointer to the data type as registered when
* MXC_GPIO_RegisterCallback() was called. * MXC_GPIO_RegisterCallback() was called.
*/ */
typedef void (*mxc_gpio_callback_fn) (void *cbdata); typedef void (*mxc_gpio_callback_fn)(void *cbdata);
/** /**
* @brief Enumeration type for the GPIO Function Type * @brief Enumeration type for the GPIO Function Type
*/ */
typedef enum { typedef enum {
MXC_GPIO_FUNC_IN, ///< GPIO Input MXC_GPIO_FUNC_IN, ///< GPIO Input
MXC_GPIO_FUNC_OUT, ///< GPIO Output MXC_GPIO_FUNC_OUT, ///< GPIO Output
MXC_GPIO_FUNC_ALT1, ///< Alternate Function Selection MXC_GPIO_FUNC_ALT1, ///< Alternate Function Selection
MXC_GPIO_FUNC_ALT2, ///< Alternate Function Selection MXC_GPIO_FUNC_ALT2, ///< Alternate Function Selection
MXC_GPIO_FUNC_ALT3, ///< Alternate Function Selection MXC_GPIO_FUNC_ALT3, ///< Alternate Function Selection
MXC_GPIO_FUNC_ALT4, ///< Alternate Function Selection MXC_GPIO_FUNC_ALT4, ///< Alternate Function Selection
} mxc_gpio_func_t; } mxc_gpio_func_t;
/** /**
* @brief Enumeration type for the voltage level on a given pin. * @brief Enumeration type for the voltage level on a given pin.
*/ */
typedef enum { typedef enum {
MXC_GPIO_VSSEL_VDDIO, ///< Set pin to VIDDIO voltage MXC_GPIO_VSSEL_VDDIO, ///< Set pin to VIDDIO voltage
MXC_GPIO_VSSEL_VDDIOH, ///< Set pin to VIDDIOH voltage MXC_GPIO_VSSEL_VDDIOH, ///< Set pin to VIDDIOH voltage
} mxc_gpio_vssel_t; } mxc_gpio_vssel_t;
/** /**
* @brief Enumeration type for the type of GPIO pad on a given pin. * @brief Enumeration type for the type of GPIO pad on a given pin.
*/ */
typedef enum { typedef enum {
MXC_GPIO_PAD_NONE, ///< No pull-up or pull-down MXC_GPIO_PAD_NONE, ///< No pull-up or pull-down
MXC_GPIO_PAD_PULL_UP, ///< Set pad to weak pull-up MXC_GPIO_PAD_PULL_UP, ///< Set pad to weak pull-up
MXC_GPIO_PAD_PULL_DOWN, ///< Set pad to weak pull-down MXC_GPIO_PAD_PULL_DOWN, ///< Set pad to weak pull-down
} mxc_gpio_pad_t; } mxc_gpio_pad_t;
/** /**
* @brief Structure type for configuring a GPIO port. * @brief Structure type for configuring a GPIO port.
*/ */
typedef struct { typedef struct {
mxc_gpio_regs_t* port; ///< Pointer to GPIO regs mxc_gpio_regs_t *port; ///< Pointer to GPIO regs
uint32_t mask; ///< Pin mask (multiple pins may be set) uint32_t mask; ///< Pin mask (multiple pins may be set)
mxc_gpio_func_t func; ///< Function type mxc_gpio_func_t func; ///< Function type
mxc_gpio_pad_t pad; ///< Pad type mxc_gpio_pad_t pad; ///< Pad type
mxc_gpio_vssel_t vssel; ///< Voltage select mxc_gpio_vssel_t vssel; ///< Voltage select
} mxc_gpio_cfg_t; } mxc_gpio_cfg_t;
/** /**
* @brief Enumeration type for the interrupt modes. * @brief Enumeration type for the interrupt modes.
*/ */
typedef enum { typedef enum {
MXC_GPIO_INT_LEVEL, ///< Interrupt is level sensitive MXC_GPIO_INT_LEVEL, ///< Interrupt is level sensitive
MXC_GPIO_INT_EDGE ///< Interrupt is edge sensitive MXC_GPIO_INT_EDGE ///< Interrupt is edge sensitive
} mxc_gpio_int_mode_t; } mxc_gpio_int_mode_t;
/** /**
* @brief Enumeration type for the interrupt polarity. * @brief Enumeration type for the interrupt polarity.
*/ */
typedef enum { typedef enum {
MXC_GPIO_INT_FALLING, ///< Interrupt triggers on falling edge MXC_GPIO_INT_FALLING, ///< Interrupt triggers on falling edge
MXC_GPIO_INT_HIGH, ///< Interrupt triggers when level is high MXC_GPIO_INT_HIGH, ///< Interrupt triggers when level is high
MXC_GPIO_INT_RISING, ///< Interrupt triggers on rising edge MXC_GPIO_INT_RISING, ///< Interrupt triggers on rising edge
MXC_GPIO_INT_LOW, ///< Interrupt triggers when level is low MXC_GPIO_INT_LOW, ///< Interrupt triggers when level is low
MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge
} mxc_gpio_int_pol_t; } mxc_gpio_int_pol_t;
/* **** Function Prototypes **** */ /* **** Function Prototypes **** */
@ -183,28 +183,28 @@ typedef enum {
* @param portMask Mask for the port to be initialized * @param portMask Mask for the port to be initialized
* @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
*/ */
int MXC_GPIO_Init (uint32_t portMask); int MXC_GPIO_Init(uint32_t portMask);
/** /**
* @brief Shutdown GPIO. * @brief Shutdown GPIO.
* @param portMask Mask for the port to be initialized * @param portMask Mask for the port to be initialized
* @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
*/ */
int MXC_GPIO_Shutdown (uint32_t portMask); int MXC_GPIO_Shutdown(uint32_t portMask);
/** /**
* @brief Reset GPIO. * @brief Reset GPIO.
* @param portMask Mask for the port to be initialized * @param portMask Mask for the port to be initialized
* @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
*/ */
int MXC_GPIO_Reset (uint32_t portMask); int MXC_GPIO_Reset(uint32_t portMask);
/** /**
* @brief Configure GPIO pin(s). * @brief Configure GPIO pin(s).
* @param cfg Pointer to configuration structure describing the pin. * @param cfg Pointer to configuration structure describing the pin.
* @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
*/ */
int MXC_GPIO_Config (const mxc_gpio_cfg_t *cfg); int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg);
/** /**
* @brief Gets the pin(s) input state. * @brief Gets the pin(s) input state.
@ -212,21 +212,21 @@ int MXC_GPIO_Config (const mxc_gpio_cfg_t *cfg);
* @param mask Mask of the pin to read * @param mask Mask of the pin to read
* @return The requested pin state. * @return The requested pin state.
*/ */
uint32_t MXC_GPIO_InGet (mxc_gpio_regs_t* port, uint32_t mask); uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t *port, uint32_t mask);
/** /**
* @brief Sets the pin(s) to a high level output. * @brief Sets the pin(s) to a high level output.
* @param port Pointer to GPIO port. * @param port Pointer to GPIO port.
* @param mask Mask of the pin to set * @param mask Mask of the pin to set
*/ */
void MXC_GPIO_OutSet (mxc_gpio_regs_t* port, uint32_t mask); void MXC_GPIO_OutSet(mxc_gpio_regs_t *port, uint32_t mask);
/** /**
* @brief Clears the pin(s) to a low level output. * @brief Clears the pin(s) to a low level output.
* @param port Pointer to GPIO port. * @param port Pointer to GPIO port.
* @param mask Mask of the pin to clear * @param mask Mask of the pin to clear
*/ */
void MXC_GPIO_OutClr (mxc_gpio_regs_t* port, uint32_t mask); void MXC_GPIO_OutClr(mxc_gpio_regs_t *port, uint32_t mask);
/** /**
* @brief Gets the pin(s) output state. * @brief Gets the pin(s) output state.
@ -235,7 +235,7 @@ void MXC_GPIO_OutClr (mxc_gpio_regs_t* port, uint32_t mask);
* @return The state of the requested pin. * @return The state of the requested pin.
* *
*/ */
uint32_t MXC_GPIO_OutGet (mxc_gpio_regs_t* port, uint32_t mask); uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t *port, uint32_t mask);
/** /**
* @brief Write the pin(s) to a desired output level. * @brief Write the pin(s) to a desired output level.
@ -244,14 +244,14 @@ uint32_t MXC_GPIO_OutGet (mxc_gpio_regs_t* port, uint32_t mask);
* @param val Desired output level of the pin(s). This will be masked * @param val Desired output level of the pin(s). This will be masked
* with the configuration mask. * with the configuration mask.
*/ */
void MXC_GPIO_OutPut (mxc_gpio_regs_t* port, uint32_t mask, uint32_t val); void MXC_GPIO_OutPut(mxc_gpio_regs_t *port, uint32_t mask, uint32_t val);
/** /**
* @brief Toggles the the pin(s) output level. * @brief Toggles the the pin(s) output level.
* @param port Pointer to GPIO port. * @param port Pointer to GPIO port.
* @param mask Mask of the pin to toggle the output * @param mask Mask of the pin to toggle the output
*/ */
void MXC_GPIO_OutToggle (mxc_gpio_regs_t* port, uint32_t mask); void MXC_GPIO_OutToggle(mxc_gpio_regs_t *port, uint32_t mask);
/** /**
* @brief Configure GPIO interrupt(s) * @brief Configure GPIO interrupt(s)
@ -259,7 +259,7 @@ void MXC_GPIO_OutToggle (mxc_gpio_regs_t* port, uint32_t mask);
* @param pol Requested interrupt polarity. * @param pol Requested interrupt polarity.
* @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
*/ */
int MXC_GPIO_IntConfig (const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol); int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol);
/** /**
* @brief Enables the specified GPIO interrupt * @brief Enables the specified GPIO interrupt
@ -267,14 +267,14 @@ int MXC_GPIO_IntConfig (const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol);
* @param mask mask of the pin to enable interrupt * @param mask mask of the pin to enable interrupt
* *
*/ */
void MXC_GPIO_EnableInt (mxc_gpio_regs_t* port, uint32_t mask); void MXC_GPIO_EnableInt(mxc_gpio_regs_t *port, uint32_t mask);
/** /**
* @brief Disables the specified GPIO interrupt. * @brief Disables the specified GPIO interrupt.
* @param port Pointer to GPIO port. * @param port Pointer to GPIO port.
* @param mask mask of the pin to disable interrupt * @param mask mask of the pin to disable interrupt
*/ */
void MXC_GPIO_DisableInt (mxc_gpio_regs_t* port, uint32_t mask); void MXC_GPIO_DisableInt(mxc_gpio_regs_t *port, uint32_t mask);
/** /**
* @brief Gets the interrupt(s) status on a GPIO port * @brief Gets the interrupt(s) status on a GPIO port
@ -283,7 +283,7 @@ void MXC_GPIO_DisableInt (mxc_gpio_regs_t* port, uint32_t mask);
* *
* @return The requested interrupt status. * @return The requested interrupt status.
*/ */
uint32_t MXC_GPIO_GetFlags (mxc_gpio_regs_t* port); uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port);
/** /**
* @brief Gets the interrupt(s) status on a GPIO port * @brief Gets the interrupt(s) status on a GPIO port
@ -291,7 +291,7 @@ uint32_t MXC_GPIO_GetFlags (mxc_gpio_regs_t* port);
* @param port Pointer to GPIO port. * @param port Pointer to GPIO port.
* @param flags The flags to clear * @param flags The flags to clear
*/ */
void MXC_GPIO_ClearFlags (mxc_gpio_regs_t* port, uint32_t flags); void MXC_GPIO_ClearFlags(mxc_gpio_regs_t *port, uint32_t flags);
/** /**
* @brief Registers a callback for the interrupt on a given port and pin. * @brief Registers a callback for the interrupt on a given port and pin.
@ -300,7 +300,8 @@ void MXC_GPIO_ClearFlags (mxc_gpio_regs_t* port, uint32_t flags);
* @param cbdata The parameter to be passed to the callback function, #callback_fn, when an interrupt occurs. * @param cbdata The parameter to be passed to the callback function, #callback_fn, when an interrupt occurs.
* *
*/ */
void MXC_GPIO_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, void *cbdata); void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback,
void *cbdata);
/** /**
* @brief GPIO IRQ Handler. @note If a callback is registered for a given * @brief GPIO IRQ Handler. @note If a callback is registered for a given
@ -309,7 +310,7 @@ void MXC_GPIO_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn
* @param port number of the port that generated the interrupt service routine. * @param port number of the port that generated the interrupt service routine.
* *
*/ */
void MXC_GPIO_Handler (unsigned int port); void MXC_GPIO_Handler(unsigned int port);
/** /**
* @brief Set Voltage select for pins to VDDIO or VDDIOH * @brief Set Voltage select for pins to VDDIO or VDDIOH
@ -320,7 +321,7 @@ void MXC_GPIO_Handler (unsigned int port);
* *
* @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
*/ */
int MXC_GPIO_SetVSSEL (mxc_gpio_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask); int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask);
/**@} end of group gpio */ /**@} end of group gpio */
@ -328,4 +329,4 @@ int MXC_GPIO_SetVSSEL (mxc_gpio_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t m
} }
#endif #endif
#endif /* _GPIO_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_GPIO_H_

143
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/i2s.h
View File

@ -3,8 +3,8 @@
* @brief I2S (Inter-Integrated Sound) driver function prototypes and data types. * @brief I2S (Inter-Integrated Sound) driver function prototypes and data types.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,10 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
#ifndef _I2S_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_I2S_H_
#define _I2S_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_I2S_H_
/* **** Includes **** */ /* **** Includes **** */
#include "mxc_sys.h" #include "mxc_sys.h"
@ -58,27 +58,19 @@ extern "C" {
/** @brief I2S stereo mode select */ /** @brief I2S stereo mode select */
typedef enum { typedef enum {
MXC_I2S_STEREO = 0,
MXC_I2S_MONO_LEFT_CH = 2, MXC_I2S_MONO_LEFT_CH = 2,
MXC_I2S_MONO_RIGHT_CH = 3 MXC_I2S_MONO_RIGHT_CH = 3
} mxc_i2s_stereo_t; } mxc_i2s_stereo_t;
/** @brief I2S polarity configuration */ /** @brief I2S polarity configuration */
typedef enum { typedef enum { MXC_I2S_POL_NORMAL, MXC_I2S_POL_INVERSE } mxc_i2s_polarity_t;
MXC_I2S_POL_NORMAL,
MXC_I2S_POL_INVERSE
} mxc_i2s_polarity_t;
/** @brief I2S transaction bit order */ /** @brief I2S transaction bit order */
typedef enum { typedef enum { MXC_I2S_MSB_FIRST, MXC_I2S_LSB_FIRST } mxc_i2s_bitorder_t;
MXC_I2S_MSB_FIRST,
MXC_I2S_LSB_FIRST
} mxc_i2s_bitorder_t;
/** @brief I2S transaction justify order */ /** @brief I2S transaction justify order */
typedef enum { typedef enum { MXC_I2S_MSB_JUSTIFY, MXC_I2S_LSB_JUSTIFY } mxc_i2s_justify_t;
MXC_I2S_MSB_JUSTIFY,
MXC_I2S_LSB_JUSTIFY
} mxc_i2s_justify_t;
/** @brief I2S transaction word size */ /** @brief I2S transaction word size */
typedef enum { typedef enum {
@ -106,18 +98,18 @@ typedef enum {
/** @brief I2S Configuration Struct */ /** @brief I2S Configuration Struct */
typedef struct { typedef struct {
mxc_i2s_ch_mode_t channelMode; mxc_i2s_ch_mode_t channelMode;
mxc_i2s_stereo_t stereoMode; mxc_i2s_stereo_t stereoMode;
mxc_i2s_wsize_t wordSize; mxc_i2s_wsize_t wordSize;
mxc_i2s_justify_t justify; mxc_i2s_justify_t justify;
mxc_i2s_bitorder_t bitOrder; mxc_i2s_bitorder_t bitOrder;
mxc_i2s_polarity_t wsPolarity; mxc_i2s_polarity_t wsPolarity;
mxc_i2s_samplesize_t sampleSize; mxc_i2s_samplesize_t sampleSize;
uint16_t clkdiv; uint16_t clkdiv;
void *rawData; void *rawData;
void *txData; void *txData;
void *rxData; void *rxData;
uint32_t length; uint32_t length;
} mxc_i2s_req_t; } mxc_i2s_req_t;
/* **** Function Prototypes **** */ /* **** Function Prototypes **** */
@ -182,12 +174,63 @@ int MXC_I2S_SetRXThreshold(uint8_t threshold);
*/ */
int MXC_I2S_SetFrequency(mxc_i2s_ch_mode_t mode, uint16_t clkdiv); int MXC_I2S_SetFrequency(mxc_i2s_ch_mode_t mode, uint16_t clkdiv);
/**
* @brief Sets the clock divider to provide the desired sampling rate.
*
* @param smpl_rate The desired sampling rate.
* @param smpl_sz The size of each sample.
*
* @return If successful, the actual sampling rate. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_SetSampleRate(uint32_t smpl_rate, mxc_i2s_wsize_t smpl_sz);
/**
* @brief Returns the current sampling rate.
*
* @return If successful, sampling rate. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_GetSampleRate(void);
/**
* @brief Calculates the value of the clock divider that should be used in order to get the desired sampling frequency.
*
* @param smpl_rate Desired sampling rate.
* @param smple_sz The size of each I2S word.
*
* @return If successful, the clock divider value. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_CalculateClockDiv(uint32_t smpl_rate, mxc_i2s_wsize_t smpl_sz);
/** /**
* @brief Flush I2S FIFO * @brief Flush I2S FIFO
* *
*/ */
void MXC_I2S_Flush(void); void MXC_I2S_Flush(void);
/**
* @brief Fill I2S FIFO with data to transmit
*
* @param txData Pointer to base address of the data buffer
* @param wordSize Size of the data samples
* @param len Number of samples in the data buffer
* @param smpl_cnt Number of samples already sent from the data buffer
*
* @returns If successful the number of samples successfuly written to the FIFO. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_FillTXFIFO(void *txData, mxc_i2s_wsize_t wordSize, int len, int smpl_cnt);
/**
* @brief Read audio samples from I2S receive buffer
*
* @param rxData Pointer to data buffer that will store the audio samples
* @param wordSize Size of the samples in the FIFO
* @param len Number of samples to read
* @param smpl_cnt Number of samples already received in the data buffer
*
* @returns If successful, the number of samples actually read from the buffer. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_ReadRXFIFO(void *rxData, mxc_i2s_wsize_t wordSize, int len, int smpl_cnt);
/** /**
* @brief Enable Interrupts * @brief Enable Interrupts
* *
@ -216,31 +259,65 @@ int MXC_I2S_GetFlags(void);
*/ */
void MXC_I2S_ClearFlags(uint32_t flags); void MXC_I2S_ClearFlags(uint32_t flags);
/**
* @brief Performs a blocking I2S transaction.
*
* @param Pointer to transaction request structure
*
* @returns If successful, E_NO_ERROR. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_Transaction(mxc_i2s_req_t *i2s_req);
/**
* @brief Sets up an asynchronous I2S transaction.
*
* @param Pointer to transaction request structure
*
* @returns If successful, E_NO_ERROR. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_TransactionAsync(mxc_i2s_req_t *i2s_req);
/** /**
* @brief Configure TX DMA transaction * @brief Configure TX DMA transaction
* *
* @param src_addr source address of data * @param src_addr source address of data
* @param len length od the data to be transmitted * @param len length od the data to be transmitted
*
* @return If successful, the DMA channel number used for the request. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes.
*/ */
void MXC_I2S_TXDMAConfig(void *src_addr, int len); int MXC_I2S_TXDMAConfig(void *src_addr, int len);
/** /**
* @brief Configure RX DMA transaction * @brief Configure RX DMA transaction
* *
* @param dest_addr destination address * @param dest_addr destination address
* @param len length of the data to be received * @param len length of the data to be received
*
* @return If successful, the DMA channel number used for the request. Otherwise, an error code. See \ref MXC_Error_Codes for a list of return codes.
*/ */
void MXC_I2S_RXDMAConfig(void *dest_addr, int len); int MXC_I2S_RXDMAConfig(void *dest_addr, int len);
/**
* @brief Handler for asynchronous I2S transactions.
*/
void MXC_I2S_Handler(void);
/** /**
* @brief Set the callback function pointer for I2S DMA transactions * @brief Set the callback function pointer for I2S DMA transactions
* *
* @param callback Function pointer to the DMA callback function * @param callback Function pointer to the DMA callback function
*/ */
void MXC_I2S_RegisterDMACallback(void(*callback)(int, int)); void MXC_I2S_RegisterDMACallback(void (*callback)(int, int));
/**
* @brief Sets the callback function for asynchronous I2S transactions
*
* @param callback Function pointer to the asynchronous transaction callback
*/
void MXC_I2S_RegisterAsyncCallback(void (*callback)(int));
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* _I2S_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_I2S_H_

26
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/icc.h
View File

@ -3,8 +3,8 @@
* @brief Instruction Controller Cache(ICC) function prototypes and data types. * @brief Instruction Controller Cache(ICC) function prototypes and data types.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
/* Define to prevent redundant inclusion */ /* Define to prevent redundant inclusion */
#ifndef _ICC_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_ICC_H_
#define _ICC_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_ICC_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -58,9 +58,9 @@ extern "C" {
* @brief Enumeration type for the Cache ID Register * @brief Enumeration type for the Cache ID Register
*/ */
typedef enum { typedef enum {
ICC_INFO_RELNUM, ///< Identifies the RTL release version ICC_INFO_RELNUM, ///< Identifies the RTL release version
ICC_INFO_PARTNUM, ///< Specifies the value of C_ID Port Number ICC_INFO_PARTNUM, ///< Specifies the value of C_ID Port Number
ICC_INFO_ID ///< Specifies the value of Cache ID ICC_INFO_ID ///< Specifies the value of Cache ID
} mxc_icc_info_t; } mxc_icc_info_t;
/** /**
@ -68,22 +68,22 @@ typedef enum {
* @param cid Enumeration type for Cache Id Register. * @param cid Enumeration type for Cache Id Register.
* @retval Returns the contents of Cache Id Register. * @retval Returns the contents of Cache Id Register.
*/ */
int MXC_ICC_ID (mxc_icc_info_t cid); int MXC_ICC_ID(mxc_icc_info_t cid);
/** /**
* @brief Enable the instruction cache controller. * @brief Enable the instruction cache controller.
*/ */
void MXC_ICC_Enable (void); void MXC_ICC_Enable(void);
/** /**
* @brief Disable the instruction cache controller. * @brief Disable the instruction cache controller.
*/ */
void MXC_ICC_Disable (void); void MXC_ICC_Disable(void);
/** /**
* @brief Flush the instruction cache controller. * @brief Flush the instruction cache controller.
*/ */
void MXC_ICC_Flush (void); void MXC_ICC_Flush(void);
/**@} end of group icc */ /**@} end of group icc */
@ -91,4 +91,4 @@ void MXC_ICC_Flush (void);
} }
#endif #endif
#endif /* _ICC_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_ICC_H_

196
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/lp.h
View File

@ -3,8 +3,8 @@
* @brief Low Power(LP) function prototypes and data types. * @brief Low Power(LP) function prototypes and data types.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
/* Define to prevent redundant inclusion */ /* Define to prevent redundant inclusion */
#ifndef _LP_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_LP_H_
#define _LP_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_LP_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -62,18 +62,14 @@ extern "C" {
* @brief Enumeration type for voltage selection * @brief Enumeration type for voltage selection
* *
*/ */
typedef enum { typedef enum { MXC_LP_V0_9 = 0, MXC_LP_V1_0, MXC_LP_V1_1 } mxc_lp_ovr_t;
MXC_LP_V0_9 = 0,
MXC_LP_V1_0,
MXC_LP_V1_1
} mxc_lp_ovr_t;
/** /**
* @brief Enumeration type for PM Mode * @brief Enumeration type for PM Mode
* *
*/ */
typedef enum { typedef enum {
MXC_LP_IPO = MXC_F_GCR_PM_IPO_PD, MXC_LP_IPO = MXC_F_GCR_PM_IPO_PD,
MXC_LP_IBRO = MXC_F_GCR_PM_IBRO_PD, MXC_LP_IBRO = MXC_F_GCR_PM_IBRO_PD,
MXC_LP_XRFO = MXC_F_GCR_PM_ERFO_PD MXC_LP_XRFO = MXC_F_GCR_PM_ERFO_PD
} mxc_lp_cfg_ds_pd_t; } mxc_lp_cfg_ds_pd_t;
@ -81,127 +77,127 @@ typedef enum {
/** /**
* @brief Places the device into SLEEP mode. This function returns once an RTC or external interrupt occur. * @brief Places the device into SLEEP mode. This function returns once an RTC or external interrupt occur.
*/ */
void MXC_LP_EnterSleepMode (void); void MXC_LP_EnterSleepMode(void);
/** /**
* @brief Places the device into DEEPSLEEP mode. This function returns once an RTC or external interrupt occur. * @brief Places the device into DEEPSLEEP mode. This function returns once an RTC or external interrupt occur.
*/ */
void MXC_LP_EnterDeepSleepMode (void); void MXC_LP_EnterDeepSleepMode(void);
/** /**
* @brief Places the device into BACKUP mode. CPU state is not maintained in this mode, so this function never returns. * @brief Places the device into BACKUP mode. CPU state is not maintained in this mode, so this function never returns.
* Instead, the device will restart once an RTC or external interrupt occur. * Instead, the device will restart once an RTC or external interrupt occur.
*/ */
void MXC_LP_EnterBackupMode (void); void MXC_LP_EnterBackupMode(void);
/** /**
* @brief Places the device into Storage mode. CPU state is not maintained in this mode, so this function never returns. * @brief Places the device into Storage mode. CPU state is not maintained in this mode, so this function never returns.
* Instead, the device will restart once an RTC or external interrupt occur. * Instead, the device will restart once an RTC or external interrupt occur.
*/ */
void MXC_LP_EnterStorageMode (void); void MXC_LP_EnterStorageMode(void);
/** /**
* @brief Places the device into Shutdown mode. CPU state is not maintained in this mode, so this function never returns. * @brief Places the device into Shutdown mode. CPU state is not maintained in this mode, so this function never returns.
* Instead, the device will restart once an RTC, USB wakeup, or external interrupt occur. * Instead, the device will restart once an RTC, USB wakeup, or external interrupt occur.
*/ */
void MXC_LP_EnterShutDownMode (void); void MXC_LP_EnterShutDownMode(void);
/** /**
* @brief Set ovr bits to set the voltage the micro will run at. * @brief Set ovr bits to set the voltage the micro will run at.
* *
* @param[in] ovr The ovr options are only 0.9V, 1.0V, and 1.1V use enum mxc_lp_ovr_t * @param[in] ovr The ovr options are only 0.9V, 1.0V, and 1.1V use enum mxc_lp_ovr_t
*/ */
void MXC_LP_SetOVR (mxc_lp_ovr_t ovr); void MXC_LP_SetOVR(mxc_lp_ovr_t ovr);
/** /**
* @brief Enable retention regulator * @brief Enable retention regulator
*/ */
void MXC_LP_RetentionRegEnable (void); void MXC_LP_RetentionRegEnable(void);
/** /**
* @brief Disable retention regulator * @brief Disable retention regulator
*/ */
void MXC_LP_RetentionRegDisable (void); void MXC_LP_RetentionRegDisable(void);
/** /**
* @brief Is the retention regulator enabled * @brief Is the retention regulator enabled
* *
* @return 1 = enabled 0 = disabled * @return 1 = enabled 0 = disabled
*/ */
int MXC_LP_RetentionRegIsEnabled (void); int MXC_LP_RetentionRegIsEnabled(void);
/** /**
* @brief Turn bandgap on * @brief Turn bandgap on
*/ */
void MXC_LP_BandgapOn (void); void MXC_LP_BandgapOn(void);
/** /**
* @brief Turn bandgap off * @brief Turn bandgap off
*/ */
void MXC_LP_BandgapOff (void); void MXC_LP_BandgapOff(void);
/** /**
* @brief Is the bandgap on or off * @brief Is the bandgap on or off
* *
* @return 1 = bandgap on , 0 = bandgap off * @return 1 = bandgap on , 0 = bandgap off
*/ */
int MXC_LP_BandgapIsOn (void); int MXC_LP_BandgapIsOn(void);
/** /**
* @brief Enable Power on Reset VDD Core Monitor * @brief Enable Power on Reset VDD Core Monitor
*/ */
void MXC_LP_PORVCOREoreMonitorEnable (void); void MXC_LP_PORVCOREoreMonitorEnable(void);
/** /**
* @brief Disable Power on Reset VDD Core Monitor * @brief Disable Power on Reset VDD Core Monitor
*/ */
void MXC_LP_PORVCOREoreMonitorDisable (void); void MXC_LP_PORVCOREoreMonitorDisable(void);
/** /**
* @brief Is Power on Reset VDD Core Monitor enabled * @brief Is Power on Reset VDD Core Monitor enabled
* *
* @return 1 = enabled , 0 = disabled * @return 1 = enabled , 0 = disabled
*/ */
int MXC_LP_PORVCOREoreMonitorIsEnabled (void); int MXC_LP_PORVCOREoreMonitorIsEnabled(void);
/** /**
* @brief Enable LDO * @brief Enable LDO
*/ */
void MXC_LP_LDOEnable (void); void MXC_LP_LDOEnable(void);
/** /**
* @brief Disable LDO * @brief Disable LDO
*/ */
void MXC_LP_LDODisable (void); void MXC_LP_LDODisable(void);
/** /**
* @brief Is LDO enabled * @brief Is LDO enabled
* *
* @return 1 = enabled , 0 = disabled * @return 1 = enabled , 0 = disabled
*/ */
int MXC_LP_LDOIsEnabled (void); int MXC_LP_LDOIsEnabled(void);
/** /**
* @brief Enable Fast wakeup * @brief Enable Fast wakeup
*/ */
void MXC_LP_FastWakeupEnable (void); void MXC_LP_FastWakeupEnable(void);
/** /**
* @brief Disable Fast wakeup * @brief Disable Fast wakeup
*/ */
void MXC_LP_FastWakeupDisable (void); void MXC_LP_FastWakeupDisable(void);
/** /**
* @brief Is Fast wake up is Enabled * @brief Is Fast wake up is Enabled
* *
* @return 1 = enabled , 0 = disabled * @return 1 = enabled , 0 = disabled
*/ */
int MXC_LP_FastWakeupIsEnabled (void); int MXC_LP_FastWakeupIsEnabled(void);
/** /**
* @brief clear all wake up status * @brief clear all wake up status
*/ */
void MXC_LP_ClearWakeStatus (void); void MXC_LP_ClearWakeStatus(void);
/** /**
* @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode. * @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode.
@ -218,60 +214,70 @@ void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask);
* @param port The port to configure as wakeup sources. * @param port The port to configure as wakeup sources.
* @param mask The pins to configure as wakeup sources. * @param mask The pins to configure as wakeup sources.
*/ */
void MXC_LP_DisableGPIOWakeup (unsigned int port, unsigned int mask); void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask);
/** /**
* @brief Enables the RTC alarm to wake up the device from any low power mode. * @brief Enables the RTC alarm to wake up the device from any low power mode.
*/ */
void MXC_LP_EnableRTCAlarmWakeup (void); void MXC_LP_EnableRTCAlarmWakeup(void);
/** /**
* @brief Disables the RTC alarm from waking up the device. * @brief Disables the RTC alarm from waking up the device.
*/ */
void MXC_LP_DisableRTCAlarmWakeup (void); void MXC_LP_DisableRTCAlarmWakeup(void);
/** /**
* @brief Enables Timer to wakeup from any low power mode. * @brief Enables Timer to wakeup from any low power mode.
* *
* @param tmr Pointer to timer module. * @param tmr Pointer to timer module.
*/ */
void MXC_LP_EnableTimerWakeup(mxc_tmr_regs_t* tmr); void MXC_LP_EnableTimerWakeup(mxc_tmr_regs_t *tmr);
/** /**
* @brief Disables Timer from waking up device. * @brief Disables Timer from waking up device.
* *
* @param tmr Pointer to timer module. * @param tmr Pointer to timer module.
*/ */
void MXC_LP_DisableTimerWakeup(mxc_tmr_regs_t* tmr); void MXC_LP_DisableTimerWakeup(mxc_tmr_regs_t *tmr);
/**
* @brief Enables LPUART0 to wake up the device from any low power mode.
*/
void MXC_LP_EnableUARTWakeup(void);
/**
* @brief Disables LPUART0 from waking up the device.
*/
void MXC_LP_DisableUARTWakeup(void);
/** /**
* @brief Enables the USB to wake up the device from any low power mode. * @brief Enables the USB to wake up the device from any low power mode.
*/ */
void MXC_LP_EnableUSBWakeup (void); void MXC_LP_EnableUSBWakeup(void);
/** /**
* @brief Disables the USB from waking up the device. * @brief Disables the USB from waking up the device.
*/ */
void MXC_LP_DisableUSBWakeup (void); void MXC_LP_DisableUSBWakeup(void);
/** /**
* @brief Enables the HA0 to wake up the device from any low power mode. * @brief Enables the HA0 to wake up the device from any low power mode.
*/ */
void MXC_LP_EnableHA0Wakeup (void); void MXC_LP_EnableHA0Wakeup(void);
/** /**
* @brief Disables the HA)0 from waking up the device. * @brief Disables the HA)0 from waking up the device.
*/ */
void MXC_LP_DisableHA0Wakeup (void); void MXC_LP_DisableHA0Wakeup(void);
/** /**
* @brief Enables the HA1 to wake up the device from any low power mode. * @brief Enables the HA1 to wake up the device from any low power mode.
*/ */
void MXC_LP_EnableHA1Wakeup (void); void MXC_LP_EnableHA1Wakeup(void);
/** /**
* @brief Disables the HA1 from waking up the device. * @brief Disables the HA1 from waking up the device.
*/ */
void MXC_LP_DisableHA1Wakeup (void); void MXC_LP_DisableHA1Wakeup(void);
/** /**
* @brief Configure which clocks are powered down at deep sleep and which are not affected. * @brief Configure which clocks are powered down at deep sleep and which are not affected.
@ -283,254 +289,254 @@ void MXC_LP_DisableHA1Wakeup (void);
* *
* @return #E_NO_ERROR or error based on \ref MXC_Error_Codes * @return #E_NO_ERROR or error based on \ref MXC_Error_Codes
*/ */
int MXC_LP_ConfigDeepSleepClocks (uint32_t mask); int MXC_LP_ConfigDeepSleepClocks(uint32_t mask);
/** /**
* @brief Enable NFC Oscilator Bypass * @brief Enable NFC Oscilator Bypass
*/ */
void MXC_LP_NFCOscBypassEnable (void); void MXC_LP_NFCOscBypassEnable(void);
/** /**
* @brief Disable NFC Oscilator Bypass * @brief Disable NFC Oscilator Bypass
*/ */
void MXC_LP_NFCOscBypassDisable (void); void MXC_LP_NFCOscBypassDisable(void);
/** /**
* @brief Is NFC Oscilator Bypass Enabled * @brief Is NFC Oscilator Bypass Enabled
* *
* @return 1 = enabled, 0 = disabled * @return 1 = enabled, 0 = disabled
*/ */
int MXC_LP_NFCOscBypassIsEnabled (void); int MXC_LP_NFCOscBypassIsEnabled(void);
/** /**
* @brief Enable System Ram 0 in light sleep * @brief Enable System Ram 0 in light sleep
*/ */
void MXC_LP_SysRam0LightSleepEnable (void); void MXC_LP_SysRam0LightSleepEnable(void);
/** /**
* @brief Enable System Ram 1 in light sleep * @brief Enable System Ram 1 in light sleep
*/ */
void MXC_LP_SysRam1LightSleepEnable (void); void MXC_LP_SysRam1LightSleepEnable(void);
/** /**
* @brief Enable System Ram 2 in light sleep * @brief Enable System Ram 2 in light sleep
*/ */
void MXC_LP_SysRam2LightSleepEnable (void); void MXC_LP_SysRam2LightSleepEnable(void);
/** /**
* @brief Enable System Ram 3 in light sleep * @brief Enable System Ram 3 in light sleep
*/ */
void MXC_LP_SysRam3LightSleepEnable (void); void MXC_LP_SysRam3LightSleepEnable(void);
/** /**
* @brief Enable System Ram 4 in light sleep * @brief Enable System Ram 4 in light sleep
*/ */
void MXC_LP_SysRam4LightSleepEnable (void); void MXC_LP_SysRam4LightSleepEnable(void);
/** /**
* @brief Enable System Ram 5 in light sleep * @brief Enable System Ram 5 in light sleep
*/ */
void MXC_LP_SysRam5LightSleepEnable (void); void MXC_LP_SysRam5LightSleepEnable(void);
/** /**
* @brief Enable Icache 0 in light sleep * @brief Enable Icache 0 in light sleep
*/ */
void MXC_LP_ICache0LightSleepEnable (void); void MXC_LP_ICache0LightSleepEnable(void);
/** /**
* @brief Enable Icache XIP in light sleep * @brief Enable Icache XIP in light sleep
*/ */
void MXC_LP_ICacheXIPLightSleepEnable (void); void MXC_LP_ICacheXIPLightSleepEnable(void);
/** /**
* @brief Enable System Cache in light sleep * @brief Enable System Cache in light sleep
*/ */
void MXC_LP_SRCCLightSleepEnable (void); void MXC_LP_SRCCLightSleepEnable(void);
/** /**
* @brief Enable Crypto in light sleep * @brief Enable Crypto in light sleep
*/ */
void MXC_LP_CryptoLightSleepEnable (void); void MXC_LP_CryptoLightSleepEnable(void);
/** /**
* @brief Enable USB in light sleep * @brief Enable USB in light sleep
*/ */
void MXC_LP_USBFIFOLightSleepEnable (void); void MXC_LP_USBFIFOLightSleepEnable(void);
/** /**
* @brief Enable ROM 0 in light sleep * @brief Enable ROM 0 in light sleep
*/ */
void MXC_LP_ROMLightSleepEnable (void); void MXC_LP_ROMLightSleepEnable(void);
/** /**
* @brief Disable System Ram 0 in light sleep * @brief Disable System Ram 0 in light sleep
*/ */
void MXC_LP_SysRam0LightSleepDisable (void); void MXC_LP_SysRam0LightSleepDisable(void);
/** /**
* @brief Disable System Ram 1 in light sleep * @brief Disable System Ram 1 in light sleep
*/ */
void MXC_LP_SysRam1LightSleepDisable (void); void MXC_LP_SysRam1LightSleepDisable(void);
/** /**
* @brief Disable System Ram 2 in light sleep * @brief Disable System Ram 2 in light sleep
*/ */
void MXC_LP_SysRam2LightSleepDisable (void); void MXC_LP_SysRam2LightSleepDisable(void);
/** /**
* @brief Disable System Ram 3 in light sleep * @brief Disable System Ram 3 in light sleep
*/ */
void MXC_LP_SysRam3LightSleepDisable (void); void MXC_LP_SysRam3LightSleepDisable(void);
/** /**
* @brief Disable System Ram 4 in light sleep * @brief Disable System Ram 4 in light sleep
*/ */
void MXC_LP_SysRam4LightSleepDisable (void); void MXC_LP_SysRam4LightSleepDisable(void);
/** /**
* @brief Disable System Ram 5 in light sleep * @brief Disable System Ram 5 in light sleep
*/ */
void MXC_LP_SysRam5LightSleepDisable (void); void MXC_LP_SysRam5LightSleepDisable(void);
/** /**
* @brief Disable Icache 0 in light sleep * @brief Disable Icache 0 in light sleep
*/ */
void MXC_LP_ICache0LightSleepDisable (void); void MXC_LP_ICache0LightSleepDisable(void);
/** /**
* @brief Disable Icache XIP in light sleep * @brief Disable Icache XIP in light sleep
*/ */
void MXC_LP_ICacheXIPLightSleepDisable (void); void MXC_LP_ICacheXIPLightSleepDisable(void);
/** /**
* @brief Disable System Cache in light sleep * @brief Disable System Cache in light sleep
*/ */
void MXC_LP_SRCCLightSleepDisable (void); void MXC_LP_SRCCLightSleepDisable(void);
/** /**
* @brief Disable Crypto in light sleep * @brief Disable Crypto in light sleep
*/ */
void MXC_LP_CryptoLightSleepDisable (void); void MXC_LP_CryptoLightSleepDisable(void);
/** /**
* @brief Disable USB in light sleep * @brief Disable USB in light sleep
*/ */
void MXC_LP_USBFIFOLightSleepDisable (void); void MXC_LP_USBFIFOLightSleepDisable(void);
/** /**
* @brief Disable ROM 0 in light sleep * @brief Disable ROM 0 in light sleep
*/ */
void MXC_LP_ROMLightSleepDisable (void); void MXC_LP_ROMLightSleepDisable(void);
/** /**
* @brief Shutdown System Ram 0 * @brief Shutdown System Ram 0
*/ */
void MXC_LP_SysRam0Shutdown (void); void MXC_LP_SysRam0Shutdown(void);
/** /**
* @brief Wakeup System Ram 0 * @brief Wakeup System Ram 0
*/ */
void MXC_LP_SysRam0PowerUp (void); void MXC_LP_SysRam0PowerUp(void);
/** /**
* @brief Shutdown System Ram 1 * @brief Shutdown System Ram 1
*/ */
void MXC_LP_SysRam1Shutdown (void); void MXC_LP_SysRam1Shutdown(void);
/** /**
* @brief PowerUp System Ram 1 * @brief PowerUp System Ram 1
*/ */
void MXC_LP_SysRam1PowerUp (void); void MXC_LP_SysRam1PowerUp(void);
/** /**
* @brief Shutdown System Ram 2 * @brief Shutdown System Ram 2
*/ */
void MXC_LP_SysRam2Shutdown (void); void MXC_LP_SysRam2Shutdown(void);
/** /**
* @brief PowerUp System Ram 2 * @brief PowerUp System Ram 2
*/ */
void MXC_LP_SysRam2PowerUp (void); void MXC_LP_SysRam2PowerUp(void);
/** /**
* @brief Shutdown System Ram 3 * @brief Shutdown System Ram 3
*/ */
void MXC_LP_SysRam3Shutdown (void); void MXC_LP_SysRam3Shutdown(void);
/** /**
* @brief PowerUp System Ram 3 * @brief PowerUp System Ram 3
*/ */
void MXC_LP_SysRam3PowerUp (void); void MXC_LP_SysRam3PowerUp(void);
/** /**
* @brief Shutdown System Ram 4 * @brief Shutdown System Ram 4
*/ */
void MXC_LP_SysRam4Shutdown (void); void MXC_LP_SysRam4Shutdown(void);
/** /**
* @brief PowerUp System Ram 4 * @brief PowerUp System Ram 4
*/ */
void MXC_LP_SysRam4PowerUp (void); void MXC_LP_SysRam4PowerUp(void);
/** /**
* @brief Shutdown System Ram 5 * @brief Shutdown System Ram 5
*/ */
void MXC_LP_SysRam5Shutdown (void); void MXC_LP_SysRam5Shutdown(void);
/** /**
* @brief PowerUp System Ram 5 * @brief PowerUp System Ram 5
*/ */
void MXC_LP_SysRam5PowerUp (void); void MXC_LP_SysRam5PowerUp(void);
/** /**
* @brief Shutdown Internal Cache * @brief Shutdown Internal Cache
*/ */
void MXC_LP_ICache0Shutdown (void); void MXC_LP_ICache0Shutdown(void);
/** /**
* @brief PowerUp Internal Cache * @brief PowerUp Internal Cache
*/ */
void MXC_LP_ICache0PowerUp (void); void MXC_LP_ICache0PowerUp(void);
/** /**
* @brief Shutdown Internal Cache XIP * @brief Shutdown Internal Cache XIP
*/ */
void MXC_LP_ICacheXIPShutdown (void); void MXC_LP_ICacheXIPShutdown(void);
/** /**
* @brief PowerUp Internal Cache XIP * @brief PowerUp Internal Cache XIP
*/ */
void MXC_LP_ICacheXIPPowerUp (void); void MXC_LP_ICacheXIPPowerUp(void);
/** /**
* @brief Shutdown SRCC * @brief Shutdown SRCC
*/ */
void MXC_LP_SRCCShutdown (void); void MXC_LP_SRCCShutdown(void);
/** /**
* @brief PowerUp SRCC * @brief PowerUp SRCC
*/ */
void MXC_LP_SRCCPowerUp (void); void MXC_LP_SRCCPowerUp(void);
/** /**
* @brief Shutdown USB FIFO * @brief Shutdown USB FIFO
*/ */
void MXC_LP_USBFIFOShutdown (void); void MXC_LP_USBFIFOShutdown(void);
/** /**
* @brief PowerUp USB FIFO * @brief PowerUp USB FIFO
*/ */
void MXC_LP_USBFIFOPowerUp (void); void MXC_LP_USBFIFOPowerUp(void);
/** /**
* @brief Shutdown ROM * @brief Shutdown ROM
*/ */
void MXC_LP_ROMShutdown (void); void MXC_LP_ROMShutdown(void);
/** /**
* @brief PowerUp ROM * @brief PowerUp ROM
*/ */
void MXC_LP_ROMPowerUp (void); void MXC_LP_ROMPowerUp(void);
/**@} end of group pwrseq */ /**@} end of group pwrseq */
@ -538,4 +544,4 @@ void MXC_LP_ROMPowerUp (void);
} }
#endif #endif
#endif /* _LP_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_LP_H_

91
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_aes.h
View File

@ -1,10 +1,10 @@
/** /**
* @file * @file
* @brief Trust Protection Unit driver. * @brief AES driver.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,14 +34,14 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
#ifndef _MXC_AES_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_AES_H_
#define _MXC_AES_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_AES_H_
/***** Includes *****/ /***** Includes *****/
#include "aes_regs.h" #include "aes_regs.h"
#include "aes_key_regs.h" #include "aeskeys_regs.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -56,7 +56,7 @@ extern "C" {
/***** Definitions *****/ /***** Definitions *****/
typedef void (*mxc_aes_complete_t) (void* req, int result); typedef void (*mxc_aes_complete_t)(void *req, int result);
/* ************************************************************************* */ /* ************************************************************************* */
/* Cipher Definitions */ /* Cipher Definitions */
@ -67,9 +67,9 @@ typedef void (*mxc_aes_complete_t) (void* req, int result);
* *
*/ */
typedef enum { typedef enum {
MXC_AES_128BITS = MXC_S_AES_CTRL_KEY_SIZE_AES128, ///< Select AES-128 bit key MXC_AES_128BITS = MXC_S_AES_CTRL_KEY_SIZE_AES128, ///< Select AES-128 bit key
MXC_AES_192BITS = MXC_S_AES_CTRL_KEY_SIZE_AES192, ///< Select AES-192 bit key MXC_AES_192BITS = MXC_S_AES_CTRL_KEY_SIZE_AES192, ///< Select AES-192 bit key
MXC_AES_256BITS = MXC_S_AES_CTRL_KEY_SIZE_AES256, ///< Select AES-256 bit key MXC_AES_256BITS = MXC_S_AES_CTRL_KEY_SIZE_AES256, ///< Select AES-256 bit key
} mxc_aes_keys_t; } mxc_aes_keys_t;
/** /**
@ -77,9 +77,9 @@ typedef enum {
* *
*/ */
typedef enum { typedef enum {
MXC_AES_ENCRYPT_EXT_KEY = 0, ///< Encryption using External key MXC_AES_ENCRYPT_EXT_KEY = 0, ///< Encryption using External key
MXC_AES_DECRYPT_EXT_KEY = 1, ///< Encryption using internal key MXC_AES_DECRYPT_EXT_KEY = 1, ///< Encryption using internal key
MXC_AES_DECRYPT_INT_KEY = 2 ///< Decryption using internal key MXC_AES_DECRYPT_INT_KEY = 2 ///< Decryption using internal key
} mxc_aes_enc_type_t; } mxc_aes_enc_type_t;
/** /**
@ -87,12 +87,12 @@ typedef enum {
* *
*/ */
typedef struct _mxc_aes_cipher_req_t { typedef struct _mxc_aes_cipher_req_t {
uint32_t length; ///< Length of the data uint32_t length; ///< Length of the data
uint32_t *inputData; ///< Pointer to input data uint32_t *inputData; ///< Pointer to input data
uint32_t *resultData; ///< Pointer to encrypted data uint32_t *resultData; ///< Pointer to encrypted data
mxc_aes_keys_t keySize; ///< Size of AES key mxc_aes_keys_t keySize; ///< Size of AES key
mxc_aes_enc_type_t encryption; ///< Encrytion type or \ref mxc_aes_enc_type_t mxc_aes_enc_type_t encryption; ///< Encrytion type or \ref mxc_aes_enc_type_t
mxc_aes_complete_t callback; ///< Callback function mxc_aes_complete_t callback; ///< Callback function
} mxc_aes_req_t; } mxc_aes_req_t;
/***** Function Prototypes *****/ /***** Function Prototypes *****/
@ -106,92 +106,92 @@ typedef struct _mxc_aes_cipher_req_t {
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_AES_Init (void); int MXC_AES_Init(void);
/** /**
* @brief Enable AES Interrupts * @brief Enable AES Interrupts
* *
* @param interrupt interrupt to enable * @param interrupt interrupt to enable
*/ */
void MXC_AES_EnableInt (uint32_t interrupt); void MXC_AES_EnableInt(uint32_t interrupt);
/** /**
* @brief Disable AES Interrupts * @brief Disable AES Interrupts
* *
* @param interrupt interrupt to disable * @param interrupt interrupt to disable
*/ */
void MXC_AES_DisableInt (uint32_t interrupt); void MXC_AES_DisableInt(uint32_t interrupt);
/** /**
* @brief Checks the global AES Busy Status * @brief Checks the global AES Busy Status
* *
* @return E_BUSY if busy and E_NO_ERROR otherwise, see \ref MXC_Error_Codes for a list of return codes. * @return E_BUSY if busy and E_NO_ERROR otherwise, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_AES_IsBusy (void); int MXC_AES_IsBusy(void);
/** /**
* @brief Disable and reset portions of the AES * @brief Disable and reset portions of the AES
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_AES_Shutdown (void); int MXC_AES_Shutdown(void);
/** /**
* @brief This function should be called from the DMA Handler * @brief This function should be called from the DMA Handler
* when using Async functions * when using Async functions
*/ */
void MXC_AES_DMACallback (int ch, int error); void MXC_AES_DMACallback(int ch, int error);
/** /**
* @brief This function should be called before encryption to genrate external key * @brief This function should be called before encryption to genrate external key
*/ */
void MXC_AES_GenerateKey (void); void MXC_AES_GenerateKey(void);
/** /**
* @brief Set Key size for encryption or decryption * @brief Set Key size for encryption or decryption
* *
* @param key Key size, see \ref mxc_aes_keys_t for a list of keys * @param key Key size, see \ref mxc_aes_keys_t for a list of keys
*/ */
void MXC_AES_SetKeySize (mxc_aes_keys_t key); void MXC_AES_SetKeySize(mxc_aes_keys_t key);
/** /**
* @brief Get the currently set key size * @brief Get the currently set key size
* *
* @return mxc_aes_keys_t see \ref mxc_aes_keys_t * @return mxc_aes_keys_t see \ref mxc_aes_keys_t
*/ */
mxc_aes_keys_t MXC_AES_GetKeySize (void); mxc_aes_keys_t MXC_AES_GetKeySize(void);
/** /**
* @brief Flush Input Data FIFO * @brief Flush Input Data FIFO
* *
*/ */
void MXC_AES_FlushInputFIFO (void); void MXC_AES_FlushInputFIFO(void);
/** /**
* @brief Flush Output Data FIFO * @brief Flush Output Data FIFO
* *
*/ */
void MXC_AES_FlushOutputFIFO (void); void MXC_AES_FlushOutputFIFO(void);
/** /**
* @brief Start AES Calculations * @brief Start AES Calculations
* *
*/ */
void MXC_AES_Start (void); void MXC_AES_Start(void);
/** /**
* @brief Get Interrupt flags set * @brief Get Interrupt flags set
* *
* @return return the flags set in intfl register * @return return the flags set in intfl register
*/ */
uint32_t MXC_AES_GetFlags (void); uint32_t MXC_AES_GetFlags(void);
/** /**
* @brief Clear the interrupts * @brief Clear the interrupts
* *
* @param flags flags to be cleared * @param flags flags to be cleared
*/ */
void MXC_AES_ClearFlags (uint32_t flags); void MXC_AES_ClearFlags(uint32_t flags);
/** /**
* @brief * @brief
@ -201,7 +201,7 @@ void MXC_AES_ClearFlags (uint32_t flags);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_AES_Generic (mxc_aes_req_t* req); int MXC_AES_Generic(mxc_aes_req_t *req);
/** /**
* @brief Perform an encryption * @brief Perform an encryption
@ -211,7 +211,7 @@ int MXC_AES_Generic (mxc_aes_req_t* req);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_AES_Encrypt (mxc_aes_req_t* req); int MXC_AES_Encrypt(mxc_aes_req_t *req);
/** /**
* @brief Perform a decryption * @brief Perform a decryption
@ -221,7 +221,7 @@ int MXC_AES_Encrypt (mxc_aes_req_t* req);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_AES_Decrypt (mxc_aes_req_t* req); int MXC_AES_Decrypt(mxc_aes_req_t *req);
/** /**
* @brief Perform AES TX using DMA. Configures DMA request and starts the transmission. * @brief Perform AES TX using DMA. Configures DMA request and starts the transmission.
@ -230,7 +230,7 @@ int MXC_AES_Decrypt (mxc_aes_req_t* req);
* @param len number of words of data * @param len number of words of data
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_AES_TXDMAConfig (void *src_addr, int len); int MXC_AES_TXDMAConfig(void *src_addr, int len);
/** /**
* @brief Perform AES RX using DMA. Configures DMA request and receives data from AES FIFO. * @brief Perform AES RX using DMA. Configures DMA request and receives data from AES FIFO.
@ -239,7 +239,7 @@ int MXC_AES_TXDMAConfig (void *src_addr, int len);
* @param len number of words of data * @param len number of words of data
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_AES_RXDMAConfig (void *dest_addr, int len); int MXC_AES_RXDMAConfig(void *dest_addr, int len);
/** /**
* @brief Perform encryption or decryption using DMA * @brief Perform encryption or decryption using DMA
@ -249,7 +249,7 @@ int MXC_AES_RXDMAConfig (void *dest_addr, int len);
* @param enc 0 for encryption and 1 for decryption * @param enc 0 for encryption and 1 for decryption
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_AES_GenericAsync (mxc_aes_req_t* req, uint8_t enc); int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc);
/** /**
* @brief Perform an encryption using Interrupt * @brief Perform an encryption using Interrupt
@ -259,7 +259,7 @@ int MXC_AES_GenericAsync (mxc_aes_req_t* req, uint8_t enc);
* @param req Structure containing data for the encryption * @param req Structure containing data for the encryption
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_AES_EncryptAsync (mxc_aes_req_t* req); int MXC_AES_EncryptAsync(mxc_aes_req_t *req);
/** /**
* @brief Perform a decryption using Interrupt * @brief Perform a decryption using Interrupt
@ -269,14 +269,14 @@ int MXC_AES_EncryptAsync (mxc_aes_req_t* req);
* @param req Structure containing data for the decryption * @param req Structure containing data for the decryption
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_AES_DecryptAsync (mxc_aes_req_t* req); int MXC_AES_DecryptAsync(mxc_aes_req_t *req);
/** /**
* @brief Set the external key * @brief Set the external key
* @param key Buffer for the key. * @param key Buffer for the key.
* @param len Key size. * @param len Key size.
*/ */
void MXC_AES_SetExtKey(const void* key, mxc_aes_keys_t len); void MXC_AES_SetExtKey(const void *key, mxc_aes_keys_t len);
/** /**
* @brief Set the key that will be loaded into the AES key registers on a POR event. * @brief Set the key that will be loaded into the AES key registers on a POR event.
@ -284,7 +284,7 @@ void MXC_AES_SetExtKey(const void* key, mxc_aes_keys_t len);
* @param len Key size. * @param len Key size.
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_AES_SetPORKey(const void* key, mxc_aes_keys_t len); int MXC_AES_SetPORKey(const void *key, mxc_aes_keys_t len);
/** /**
* @brief Clears the key that will be loaded into the AES key registers on a POR event. * @brief Clears the key that will be loaded into the AES key registers on a POR event.
@ -309,10 +309,9 @@ void MXC_AES_CopyPORKeyToKeyRegisters(mxc_aes_keys_t len);
*/ */
int MXC_AES_HasPORKey(); int MXC_AES_HasPORKey();
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
/**@} end of group aes */ /**@} end of group aes */
#endif /* _MXC_AES_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_AES_H_

24
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_assert.h
View File

@ -3,8 +3,8 @@
* @brief Assertion checks for debugging. * @brief Assertion checks for debugging.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,15 +34,14 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
/* Define to prevent redundant inclusion */ /* Define to prevent redundant inclusion */
#ifndef _MXC_ASSERT_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_ASSERT_H_
#define _MXC_ASSERT_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_ASSERT_H_
/* **** Includes **** */ /* **** Includes **** */
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
@ -65,11 +64,10 @@ extern "C" {
* @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
* defined. * defined.
*/ */
#define MXC_ASSERT(expr) \ #define MXC_ASSERT(expr) \
if (!(expr)) \ if (!(expr)) { \
{ \ mxc_assert(#expr, __FILE__, __LINE__); \
mxc_assert(#expr, __FILE__, __LINE__); \ }
}
/** /**
* Macro that generates an assertion with the message "FAIL". * Macro that generates an assertion with the message "FAIL".
* @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
@ -98,7 +96,7 @@ if (!(expr)) \
* @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
* defined. * defined.
*/ */
void mxc_assert (const char *expr, const char *file, int line); void mxc_assert(const char *expr, const char *file, int line);
/**@} end of group MXC_Assertions*/ /**@} end of group MXC_Assertions*/
@ -106,4 +104,4 @@ void mxc_assert (const char *expr, const char *file, int line);
} }
#endif #endif
#endif /* _MXC_ASSERT_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_ASSERT_H_

40
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_delay.h
View File

@ -3,8 +3,8 @@
* @brief Asynchronous delay routines based on the SysTick Timer. * @brief Asynchronous delay routines based on the SysTick Timer.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,17 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
/* Define to prevent redundant inclusion */ /* Define to prevent redundant inclusion */
#ifndef _DELAY_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_DELAY_H_
#define _DELAY_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_DELAY_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** /**
* @ingroup devicelibs * @ingroup devicelibs
@ -54,21 +60,21 @@
* x = SEC(3) // 3 seconds -> x = 3,000,000 * x = SEC(3) // 3 seconds -> x = 3,000,000
* \endcode * \endcode
*/ */
#define MXC_DELAY_SEC(s) (((unsigned long)s) * 1000000UL) #define MXC_DELAY_SEC(s) (((uint32_t)s) * 1000000UL)
/** /**
* Macro used to specify a microsecond timing parameter in milliseconds. * Macro used to specify a microsecond timing parameter in milliseconds.
* \code * \code
* x = MSEC(3) // 3ms -> x = 3,000 * x = MSEC(3) // 3ms -> x = 3,000
* \endcode * \endcode
*/ */
#define MXC_DELAY_MSEC(ms) (ms * 1000UL) #define MXC_DELAY_MSEC(ms) (ms * 1000UL)
/** /**
* Macro used to specify a microsecond timing parameter. * Macro used to specify a microsecond timing parameter.
* \code * \code
* x = USEC(3) // 3us -> x = 3 * x = USEC(3) // 3us -> x = 3
* \endcode * \endcode
*/ */
#define MXC_DELAY_USEC(us) (us) #define MXC_DELAY_USEC(us) (us)
/** /**
* @brief The callback routine used by MXC_DelayAsync() when the delay is complete * @brief The callback routine used by MXC_DelayAsync() when the delay is complete
@ -76,7 +82,7 @@
* *
* @param result See \ref MXC_Error_Codes for the list of error codes. * @param result See \ref MXC_Error_Codes for the list of error codes.
*/ */
typedef void (*mxc_delay_complete_t) (int result); typedef void (*mxc_delay_complete_t)(int result);
/***** Function Prototypes *****/ /***** Function Prototypes *****/
@ -88,7 +94,7 @@ typedef void (*mxc_delay_complete_t) (int result);
* @param us microseconds to delay * @param us microseconds to delay
* @return #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful. * @return #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful.
*/ */
int MXC_Delay (unsigned long us); int MXC_Delay(uint32_t us);
/** /**
* @brief Starts a non-blocking delay for the specified number of * @brief Starts a non-blocking delay for the specified number of
@ -103,28 +109,32 @@ int MXC_Delay (unsigned long us);
* @return #E_NO_ERROR if no errors, #E_BUSY if currently servicing another * @return #E_NO_ERROR if no errors, #E_BUSY if currently servicing another
* delay request. * delay request.
*/ */
int MXC_DelayAsync (unsigned long us, mxc_delay_complete_t callback); int MXC_DelayAsync(uint32_t us, mxc_delay_complete_t callback);
/** /**
* @brief Returns the status of a non-blocking delay request * @brief Returns the status of a non-blocking delay request
* @pre Start the asynchronous delay by calling MXC_Delay_start(). * @pre Start the asynchronous delay by calling MXC_Delay_start().
* @return #E_BUSY until the requested delay time has expired. * @return #E_BUSY until the requested delay time has expired.
*/ */
int MXC_DelayCheck (void); int MXC_DelayCheck(void);
/** /**
* @brief Stops an asynchronous delay previously started. * @brief Stops an asynchronous delay previously started.
* @pre Start the asynchronous delay by calling MXC_Delay_start(). * @pre Start the asynchronous delay by calling MXC_Delay_start().
*/ */
void MXC_DelayAbort (void); void MXC_DelayAbort(void);
/** /**
* @brief Processes the delay interrupt. * @brief Processes the delay interrupt.
* @details This function must be called from the SysTick IRQ or polled at a * @details This function must be called from the SysTick IRQ or polled at a
* rate greater than the SysTick overflow rate. * rate greater than the SysTick overflow rate.
*/ */
void MXC_DelayHandler (void); void MXC_DelayHandler(void);
/**@} end of group MXC_delay */ /**@} end of group MXC_delay */
#endif /* _DELAY_H_ */ #ifdef __cplusplus
}
#endif
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_DELAY_H_

18
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_device.h
View File

@ -3,8 +3,8 @@
* @brief Device specific header file. * @brief Device specific header file.
*/ */
/******************************************************************************* /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -36,14 +36,14 @@
* *
******************************************************************************/ ******************************************************************************/
#ifndef _MXC_DEVICE_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_DEVICE_H_
#define _MXC_DEVICE_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_DEVICE_H_
#include "max32670.h" #include "max32670.h"
#include "mxc_errors.h" #include "mxc_errors.h"
#include "mxc_pins.h" #include "mxc_pins.h"
#if defined ( __ICCARM__ ) || (__CC_ARM) #if defined(__ICCARM__) || (__CC_ARM)
#include "RTE_Components.h" #include "RTE_Components.h"
#endif #endif
@ -63,14 +63,14 @@
#error TARGET_REV NOT DEFINED #error TARGET_REV NOT DEFINED
#endif #endif
#if(TARGET_REV == 0x4131) #if (TARGET_REV == 0x4131)
// A1 // A1
#define MXC_TMR_REV 0 #define MXC_TMR_REV 0
#define MXC_UART_REV 0 #define MXC_UART_REV 0
#else #else
#error TARGET_REV NOT SUPPORTED #error TARGET_REV NOT SUPPORTED
#endif /* if(TARGET_REV == ...) */ #endif /* if(TARGET_REV == ...) */
#endif /* _MXC_DEVICE_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_DEVICE_H_

52
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_errors.h
View File

@ -3,8 +3,8 @@
* @brief List of common error return codes for Maxim Integrated libraries. * @brief List of common error return codes for Maxim Integrated libraries.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
/* Define to prevent redundant inclusion */ /* Define to prevent redundant inclusion */
#ifndef _MXC_ERRORS_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_ERRORS_H_
#define _MXC_ERRORS_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_ERRORS_H_
/** /**
* @ingroup syscfg * @ingroup syscfg
@ -50,43 +50,45 @@
*/ */
/** No Error */ /** No Error */
#define E_NO_ERROR 0 #define E_NO_ERROR 0
/** No Error, success */ /** No Error, success */
#define E_SUCCESS 0 #define E_SUCCESS 0
/** Pointer is NULL */ /** Pointer is NULL */
#define E_NULL_PTR -1 #define E_NULL_PTR -1
/** No such device */ /** No such device */
#define E_NO_DEVICE -2 #define E_NO_DEVICE -2
/** Parameter not acceptable */ /** Parameter not acceptable */
#define E_BAD_PARAM -3 #define E_BAD_PARAM -3
/** Value not valid or allowed */ /** Value not valid or allowed */
#define E_INVALID -4 #define E_INVALID -4
/** Module not initialized */ /** Module not initialized */
#define E_UNINITIALIZED -5 #define E_UNINITIALIZED -5
/** Busy now, try again later */ /** Busy now, try again later */
#define E_BUSY -6 #define E_BUSY -6
/** Operation not allowed in current state */ /** Operation not allowed in current state */
#define E_BAD_STATE -7 #define E_BAD_STATE -7
/** Generic error */ /** Generic error */
#define E_UNKNOWN -8 #define E_UNKNOWN -8
/** General communications error */ /** General communications error */
#define E_COMM_ERR -9 #define E_COMM_ERR -9
/** Operation timed out */ /** Operation timed out */
#define E_TIME_OUT -10 #define E_TIME_OUT -10
/** Expected response did not occur */ /** Expected response did not occur */
#define E_NO_RESPONSE -11 #define E_NO_RESPONSE -11
/** Operations resulted in unexpected overflow */ /** Operations resulted in unexpected overflow */
#define E_OVERFLOW -12 #define E_OVERFLOW -12
/** Operations resulted in unexpected underflow */ /** Operations resulted in unexpected underflow */
#define E_UNDERFLOW -13 #define E_UNDERFLOW -13
/** Data or resource not available at this time */ /** Data or resource not available at this time */
#define E_NONE_AVAIL -14 #define E_NONE_AVAIL -14
/** Event was shutdown */ /** Event was shutdown */
#define E_SHUTDOWN -15 #define E_SHUTDOWN -15
/** Event was aborted */ /** Event was aborted */
#define E_ABORT -16 #define E_ABORT -16
/** The requested operation is not supported */ /** The requested operation is not supported */
#define E_NOT_SUPPORTED -17 #define E_NOT_SUPPORTED -17
/** The requested operation is failed */
#define E_FAIL -255
/**@} end of MXC_Error_Codes group */ /**@} end of MXC_Error_Codes group */
#endif /* _MXC_ERRORS_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_ERRORS_H_

154
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_i2c.h
View File

@ -3,8 +3,8 @@
* @brief Inter-integrated circuit (I2C) communications interface driver. * @brief Inter-integrated circuit (I2C) communications interface driver.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
/* Define to prevent redundant inclusion */ /* Define to prevent redundant inclusion */
#ifndef _MXC_I2C_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_I2C_H_
#define _MXC_I2C_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_I2C_H_
#include <stdint.h> #include <stdint.h>
#include "mxc_sys.h" #include "mxc_sys.h"
@ -69,7 +69,7 @@ typedef struct _i2c_req_t mxc_i2c_req_t;
* @return 0 if the byte should not be acknowledged (NACK), non-zero to * @return 0 if the byte should not be acknowledged (NACK), non-zero to
* acknowledge the byte. * acknowledge the byte.
*/ */
typedef int (*mxc_i2c_getAck_t) (mxc_i2c_regs_t* i2c, unsigned char byte); typedef int (*mxc_i2c_getAck_t)(mxc_i2c_regs_t *i2c, unsigned char byte);
/** /**
* @brief The callback routine used by the MXC_I2C_MasterTransactionAsync() * @brief The callback routine used by the MXC_I2C_MasterTransactionAsync()
@ -80,7 +80,7 @@ typedef int (*mxc_i2c_getAck_t) (mxc_i2c_regs_t* i2c, unsigned char byte);
* transmitted is not acknowledged, negative if error. * transmitted is not acknowledged, negative if error.
* See \ref MXC_Error_Codes for the list of error codes. * See \ref MXC_Error_Codes for the list of error codes.
*/ */
typedef void (*mxc_i2c_complete_cb_t) (mxc_i2c_req_t* req, int result); typedef void (*mxc_i2c_complete_cb_t)(mxc_i2c_req_t *req, int result);
/** /**
* @brief The callback routine used by the I2C Read/Write FIFO DMA * @brief The callback routine used by the I2C Read/Write FIFO DMA
@ -89,7 +89,7 @@ typedef void (*mxc_i2c_complete_cb_t) (mxc_i2c_req_t* req, int result);
* @param len The length of data actually read/written * @param len The length of data actually read/written
* @param result See \ref MXC_Error_Codes for the list of error codes. * @param result See \ref MXC_Error_Codes for the list of error codes.
*/ */
typedef void (*mxc_i2c_dma_complete_cb_t) (int len, int result); typedef void (*mxc_i2c_dma_complete_cb_t)(int len, int result);
/** /**
* @brief The information required to perform a complete I2C transaction as * @brief The information required to perform a complete I2C transaction as
@ -100,22 +100,22 @@ typedef void (*mxc_i2c_dma_complete_cb_t) (int len, int result);
* MXC_I2C_MasterTransactionAsync() functions. * MXC_I2C_MasterTransactionAsync() functions.
*/ */
struct _i2c_req_t { struct _i2c_req_t {
mxc_i2c_regs_t* i2c; ///< Pointer to I2C registers (selects the mxc_i2c_regs_t *i2c; ///< Pointer to I2C registers (selects the
///< I2C block used.) ///< I2C block used.)
unsigned int addr; ///< The 7-bit or 10-bit address of the slave. unsigned int addr; ///< The 7-bit or 10-bit address of the slave.
unsigned char* tx_buf; ///< The buffer containing the bytes to write. unsigned char *tx_buf; ///< The buffer containing the bytes to write.
unsigned int tx_len; ///< The number of bytes to write. On return unsigned int tx_len; ///< The number of bytes to write. On return
///< from the function, this will be set to ///< from the function, this will be set to
///< the number of bytes actually transmitted. ///< the number of bytes actually transmitted.
unsigned char* rx_buf; ///< The buffer to read the data into. unsigned char *rx_buf; ///< The buffer to read the data into.
unsigned int rx_len; ///< The number of bytes to read. On return unsigned int rx_len; ///< The number of bytes to read. On return
///< from the function, this will be set to ///< from the function, this will be set to
///< the number of bytes actually received. ///< the number of bytes actually received.
int restart; ///< Controls whether the transaction is int restart; ///< Controls whether the transaction is
///< terminated with a stop or repeated start ///< terminated with a stop or repeated start
///< condition. Use 0 for a stop, non-zero ///< condition. Use 0 for a stop, non-zero
///< for repeated start. ///< for repeated start.
mxc_i2c_complete_cb_t callback; ///< The callback used to indicate the mxc_i2c_complete_cb_t callback; ///< The callback used to indicate the
///< transaction is complete or an error has ///< transaction is complete or an error has
///< occurred. This field may be set to NULL ///< occurred. This field may be set to NULL
///< if no indication is necessary. This ///< if no indication is necessary. This
@ -134,18 +134,18 @@ struct _i2c_req_t {
* application to handle these events. * application to handle these events.
*/ */
typedef enum { typedef enum {
MXC_I2C_EVT_MASTER_WR, ///< A slave address match occurred with the master MXC_I2C_EVT_MASTER_WR, ///< A slave address match occurred with the master
///< requesting a write to the slave. ///< requesting a write to the slave.
MXC_I2C_EVT_MASTER_RD, ///< A slave address match occurred with the master MXC_I2C_EVT_MASTER_RD, ///< A slave address match occurred with the master
///< requesting a read from the slave. ///< requesting a read from the slave.
MXC_I2C_EVT_RX_THRESH, ///< The receive FIFO contains more bytes than its MXC_I2C_EVT_RX_THRESH, ///< The receive FIFO contains more bytes than its
///< threshold level. ///< threshold level.
MXC_I2C_EVT_TX_THRESH, ///< The transmit FIFO contains fewer bytes than its MXC_I2C_EVT_TX_THRESH, ///< The transmit FIFO contains fewer bytes than its
///< threshold level. ///< threshold level.
MXC_I2C_EVT_TRANS_COMP, ///< The transaction has ended. MXC_I2C_EVT_TRANS_COMP, ///< The transaction has ended.
MXC_I2C_EVT_UNDERFLOW, ///< The master has attempted a read when the MXC_I2C_EVT_UNDERFLOW, ///< The master has attempted a read when the
///< transmit FIFO was empty. ///< transmit FIFO was empty.
MXC_I2C_EVT_OVERFLOW, ///< The master has written data when the receive MXC_I2C_EVT_OVERFLOW, ///< The master has written data when the receive
///< FIFO was already full. ///< FIFO was already full.
} mxc_i2c_slave_event_t; } mxc_i2c_slave_event_t;
@ -165,8 +165,8 @@ typedef enum {
* non-zero to not acknowledge. The return value is ignored for all * non-zero to not acknowledge. The return value is ignored for all
* other event types. * other event types.
*/ */
typedef int (*mxc_i2c_slave_handler_t) (mxc_i2c_regs_t* i2c, typedef int (*mxc_i2c_slave_handler_t)(mxc_i2c_regs_t *i2c, mxc_i2c_slave_event_t event,
mxc_i2c_slave_event_t event, void* data); void *data);
/***** Function Prototypes *****/ /***** Function Prototypes *****/
@ -188,7 +188,7 @@ typedef int (*mxc_i2c_slave_handler_t) (mxc_i2c_regs_t* i2c,
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_I2C_Init (mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr); int MXC_I2C_Init(mxc_i2c_regs_t *i2c, int masterMode, unsigned int slaveAddr);
/** /**
* @brief Initialize and enable I2C peripheral. * @brief Initialize and enable I2C peripheral.
@ -202,7 +202,7 @@ int MXC_I2C_Init (mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx); int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t *i2c, unsigned int slaveAddr, int idx);
/** /**
* @brief Disable and shutdown I2C peripheral. * @brief Disable and shutdown I2C peripheral.
@ -211,7 +211,7 @@ int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_I2C_Shutdown (mxc_i2c_regs_t* i2c); int MXC_I2C_Shutdown(mxc_i2c_regs_t *i2c);
/** /**
* @brief Reset the I2C peripheral. * @brief Reset the I2C peripheral.
@ -221,7 +221,7 @@ int MXC_I2C_Shutdown (mxc_i2c_regs_t* i2c);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_I2C_Reset (mxc_i2c_regs_t* i2c); int MXC_I2C_Reset(mxc_i2c_regs_t *i2c);
/** /**
* @brief Set the frequency of the I2C interface. * @brief Set the frequency of the I2C interface.
@ -232,7 +232,7 @@ int MXC_I2C_Reset (mxc_i2c_regs_t* i2c);
* @return Negative if error, otherwise actual speed set. See \ref * @return Negative if error, otherwise actual speed set. See \ref
* MXC_Error_Codes for the list of error return codes. * MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_I2C_SetFrequency (mxc_i2c_regs_t* i2c, unsigned int hz); int MXC_I2C_SetFrequency(mxc_i2c_regs_t *i2c, unsigned int hz);
/** /**
* @brief Get the frequency of the I2C interface. * @brief Get the frequency of the I2C interface.
@ -241,7 +241,7 @@ int MXC_I2C_SetFrequency (mxc_i2c_regs_t* i2c, unsigned int hz);
* *
* @return The I2C bus frequency in Hertz * @return The I2C bus frequency in Hertz
*/ */
unsigned int MXC_I2C_GetFrequency (mxc_i2c_regs_t* i2c); unsigned int MXC_I2C_GetFrequency(mxc_i2c_regs_t *i2c);
/** /**
* @brief Checks if the given I2C bus can be placed in sleep more. * @brief Checks if the given I2C bus can be placed in sleep more.
@ -255,7 +255,7 @@ unsigned int MXC_I2C_GetFrequency (mxc_i2c_regs_t* i2c);
* @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref
* MXC_Error_Codes for the list of error return codes. * MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_I2C_ReadyForSleep (mxc_i2c_regs_t* i2c); int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t *i2c);
/** /**
* @brief Enables or disables clock stretching by the slave. * @brief Enables or disables clock stretching by the slave.
@ -268,7 +268,7 @@ int MXC_I2C_ReadyForSleep (mxc_i2c_regs_t* i2c);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_I2C_SetClockStretching (mxc_i2c_regs_t* i2c, int enable); int MXC_I2C_SetClockStretching(mxc_i2c_regs_t *i2c, int enable);
/** /**
* @brief Determines if clock stretching has been enabled. * @brief Determines if clock stretching has been enabled.
@ -277,7 +277,7 @@ int MXC_I2C_SetClockStretching (mxc_i2c_regs_t* i2c, int enable);
* *
* @return Zero if clock stretching is disabled, non-zero otherwise * @return Zero if clock stretching is disabled, non-zero otherwise
*/ */
int MXC_I2C_GetClockStretching (mxc_i2c_regs_t* i2c); int MXC_I2C_GetClockStretching(mxc_i2c_regs_t *i2c);
/* ************************************************************************* */ /* ************************************************************************* */
/* Low-level functions */ /* Low-level functions */
@ -294,7 +294,7 @@ int MXC_I2C_GetClockStretching (mxc_i2c_regs_t* i2c);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_I2C_Start (mxc_i2c_regs_t* i2c); int MXC_I2C_Start(mxc_i2c_regs_t *i2c);
/** /**
* @brief Generate a stop condition on the I2C bus. * @brief Generate a stop condition on the I2C bus.
@ -303,7 +303,7 @@ int MXC_I2C_Start (mxc_i2c_regs_t* i2c);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_I2C_Stop (mxc_i2c_regs_t* i2c); int MXC_I2C_Stop(mxc_i2c_regs_t *i2c);
/** /**
* @brief Write a single byte to the I2C bus. * @brief Write a single byte to the I2C bus.
@ -320,7 +320,7 @@ int MXC_I2C_Stop (mxc_i2c_regs_t* i2c);
* @return 0 if byte is acknowledged, 1 if not acknowledged, negative if * @return 0 if byte is acknowledged, 1 if not acknowledged, negative if
* error. See \ref MXC_Error_Codes for the list of error return codes. * error. See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_I2C_WriteByte (mxc_i2c_regs_t* i2c, unsigned char byte); int MXC_I2C_WriteByte(mxc_i2c_regs_t *i2c, unsigned char byte);
/** /**
* @brief Read a single byte from the I2C bus. * @brief Read a single byte from the I2C bus.
@ -336,7 +336,7 @@ int MXC_I2C_WriteByte (mxc_i2c_regs_t* i2c, unsigned char byte);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_I2C_ReadByte (mxc_i2c_regs_t* i2c, unsigned char* byte, int ack); int MXC_I2C_ReadByte(mxc_i2c_regs_t *i2c, unsigned char *byte, int ack);
/** /**
* @brief Read a single byte from the I2C bus. * @brief Read a single byte from the I2C bus.
@ -360,8 +360,7 @@ int MXC_I2C_ReadByte (mxc_i2c_regs_t* i2c, unsigned char* byte, int ack);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_I2C_ReadByteInteractive (mxc_i2c_regs_t* i2c, unsigned char* byte, int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t *i2c, unsigned char *byte, mxc_i2c_getAck_t getAck);
mxc_i2c_getAck_t getAck);
/** /**
* @brief Write multiple bytes to the I2C bus. * @brief Write multiple bytes to the I2C bus.
@ -380,7 +379,7 @@ int MXC_I2C_ReadByteInteractive (mxc_i2c_regs_t* i2c, unsigned char* byte,
* acknowledged, negative if error. See \ref MXC_Error_Codes for the * acknowledged, negative if error. See \ref MXC_Error_Codes for the
* list of error return codes. * list of error return codes.
*/ */
int MXC_I2C_Write (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len); int MXC_I2C_Write(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len);
/** /**
* @brief Read multiple bytes from the I2C bus. * @brief Read multiple bytes from the I2C bus.
@ -399,8 +398,7 @@ int MXC_I2C_Write (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len)
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_I2C_Read (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len, int MXC_I2C_Read(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack);
int ack);
/** /**
* @brief Unloads bytes from the receive FIFO. * @brief Unloads bytes from the receive FIFO.
@ -411,8 +409,7 @@ int MXC_I2C_Read (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len,
* *
* @return The number of bytes actually read. * @return The number of bytes actually read.
*/ */
int MXC_I2C_ReadRXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len);
unsigned int len);
/** /**
* @brief Unloads bytes from the receive FIFO using DMA for longer reads. * @brief Unloads bytes from the receive FIFO using DMA for longer reads.
@ -426,8 +423,8 @@ int MXC_I2C_ReadRXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes,
* *
* @return See \ref MXC_Error_Codes for a list of return values. * @return See \ref MXC_Error_Codes for a list of return values.
*/ */
int MXC_I2C_ReadRXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes, int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len,
unsigned int len, mxc_i2c_dma_complete_cb_t callback); mxc_i2c_dma_complete_cb_t callback);
/** /**
* @brief Get the number of bytes currently available in the receive FIFO. * @brief Get the number of bytes currently available in the receive FIFO.
@ -436,7 +433,7 @@ int MXC_I2C_ReadRXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes,
* *
* @return The number of bytes available. * @return The number of bytes available.
*/ */
int MXC_I2C_GetRXFIFOAvailable (mxc_i2c_regs_t* i2c); int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t *i2c);
/** /**
* @brief Loads bytes into the transmit FIFO. * @brief Loads bytes into the transmit FIFO.
@ -447,8 +444,7 @@ int MXC_I2C_GetRXFIFOAvailable (mxc_i2c_regs_t* i2c);
* *
* @return The number of bytes actually written. * @return The number of bytes actually written.
*/ */
int MXC_I2C_WriteTXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len);
unsigned int len);
/** /**
* @brief Loads bytes into the transmit FIFO using DMA for longer writes. * @brief Loads bytes into the transmit FIFO using DMA for longer writes.
@ -461,8 +457,8 @@ int MXC_I2C_WriteTXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes,
* *
* @return See \ref MXC_Error_Codes for a list of return values * @return See \ref MXC_Error_Codes for a list of return values
*/ */
int MXC_I2C_WriteTXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes, int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len,
unsigned int len, mxc_i2c_dma_complete_cb_t callback); mxc_i2c_dma_complete_cb_t callback);
/** /**
* @brief Get the amount of free space available in the transmit FIFO. * @brief Get the amount of free space available in the transmit FIFO.
@ -471,21 +467,21 @@ int MXC_I2C_WriteTXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes,
* *
* @return The number of bytes available. * @return The number of bytes available.
*/ */
int MXC_I2C_GetTXFIFOAvailable (mxc_i2c_regs_t* i2c); int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t *i2c);
/** /**
* @brief Removes and discards all bytes currently in the receive FIFO. * @brief Removes and discards all bytes currently in the receive FIFO.
* *
* @param i2c Pointer to I2C registers (selects the I2C block used.) * @param i2c Pointer to I2C registers (selects the I2C block used.)
*/ */
void MXC_I2C_ClearRXFIFO (mxc_i2c_regs_t* i2c); void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t *i2c);
/** /**
* @brief Removes and discards all bytes currently in the transmit FIFO. * @brief Removes and discards all bytes currently in the transmit FIFO.
* *
* @param i2c Pointer to I2C registers (selects the I2C block used.) * @param i2c Pointer to I2C registers (selects the I2C block used.)
*/ */
void MXC_I2C_ClearTXFIFO (mxc_i2c_regs_t* i2c); void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t *i2c);
/** /**
* @brief Get the presently set interrupt flags. * @brief Get the presently set interrupt flags.
@ -496,7 +492,7 @@ void MXC_I2C_ClearTXFIFO (mxc_i2c_regs_t* i2c);
* *
* @return See \ref MXC_Error_Codes for a list of return values * @return See \ref MXC_Error_Codes for a list of return values
*/ */
int MXC_I2C_GetFlags (mxc_i2c_regs_t* i2c, unsigned int *flags0, unsigned int *flags1); int MXC_I2C_GetFlags(mxc_i2c_regs_t *i2c, unsigned int *flags0, unsigned int *flags1);
/** /**
* @brief Clears the Interrupt Flags. * @brief Clears the Interrupt Flags.
@ -505,7 +501,7 @@ int MXC_I2C_GetFlags (mxc_i2c_regs_t* i2c, unsigned int *flags0, unsigned int *f
* @param flags0 Flags to be cleared in interrupt register intfl0. * @param flags0 Flags to be cleared in interrupt register intfl0.
* @param flags1 Flags to be cleared in interrupt register intfl1. * @param flags1 Flags to be cleared in interrupt register intfl1.
*/ */
void MXC_I2C_ClearFlags (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1); void MXC_I2C_ClearFlags(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1);
/** /**
* @brief Enable Interrupts. * @brief Enable Interrupts.
@ -514,7 +510,7 @@ void MXC_I2C_ClearFlags (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int
* @param flags0 Interrupts to be enabled in int->en0 * @param flags0 Interrupts to be enabled in int->en0
* @param flags1 Interrupts to be enabled in int->en1 * @param flags1 Interrupts to be enabled in int->en1
*/ */
void MXC_I2C_EnableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1); void MXC_I2C_EnableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1);
/** /**
* @brief Disable Interrupts. * @brief Disable Interrupts.
@ -523,7 +519,7 @@ void MXC_I2C_EnableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int f
* @param flags0 Interrupts to be disabled in int->en0 * @param flags0 Interrupts to be disabled in int->en0
* @param flags1 Interrupts to be disabled in int->en1 * @param flags1 Interrupts to be disabled in int->en1
*/ */
void MXC_I2C_DisableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1); void MXC_I2C_DisableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1);
/** /**
* @brief Enables the slave preload mode * @brief Enables the slave preload mode
@ -533,28 +529,28 @@ void MXC_I2C_DisableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int
* *
* @param i2c Pointer to I2C registers (selects the I2C block used.) * @param i2c Pointer to I2C registers (selects the I2C block used.)
*/ */
void MXC_I2C_EnablePreload (mxc_i2c_regs_t* i2c); void MXC_I2C_EnablePreload(mxc_i2c_regs_t *i2c);
/** /**
* @brief Disable the slave preload mode * @brief Disable the slave preload mode
* *
* @param i2c Pointer to I2C registers (selects the I2C block used.) * @param i2c Pointer to I2C registers (selects the I2C block used.)
*/ */
void MXC_I2C_DisablePreload (mxc_i2c_regs_t* i2c); void MXC_I2C_DisablePreload(mxc_i2c_regs_t *i2c);
/** /**
* @brief Enables the slave to respond to the general call address * @brief Enables the slave to respond to the general call address
* *
* @param i2c Pointer to I2C registers (selects the I2C block used.) * @param i2c Pointer to I2C registers (selects the I2C block used.)
*/ */
void MXC_I2C_EnableGeneralCall (mxc_i2c_regs_t* i2c); void MXC_I2C_EnableGeneralCall(mxc_i2c_regs_t *i2c);
/** /**
* @brief Prevents the slave from responding to the general call address * @brief Prevents the slave from responding to the general call address
* *
* @param i2c Pointer to I2C registers (selects the I2C block used.) * @param i2c Pointer to I2C registers (selects the I2C block used.)
*/ */
void MXC_I2C_DisableGeneralCall (mxc_i2c_regs_t* i2c); void MXC_I2C_DisableGeneralCall(mxc_i2c_regs_t *i2c);
/** /**
* @brief Set the I2C Timeout * @brief Set the I2C Timeout
@ -568,7 +564,7 @@ void MXC_I2C_DisableGeneralCall (mxc_i2c_regs_t* i2c);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
void MXC_I2C_SetTimeout (mxc_i2c_regs_t* i2c, unsigned int timeout); void MXC_I2C_SetTimeout(mxc_i2c_regs_t *i2c, unsigned int timeout);
/** /**
* @brief Get the current I2C timeout * @brief Get the current I2C timeout
@ -577,7 +573,7 @@ void MXC_I2C_SetTimeout (mxc_i2c_regs_t* i2c, unsigned int timeout);
* *
* @return The current timeout in uS * @return The current timeout in uS
*/ */
unsigned int MXC_I2C_GetTimeout (mxc_i2c_regs_t* i2c); unsigned int MXC_I2C_GetTimeout(mxc_i2c_regs_t *i2c);
/** /**
* @brief Attempts to recover the I2C bus, ensuring the I2C lines are idle. * @brief Attempts to recover the I2C bus, ensuring the I2C lines are idle.
@ -603,7 +599,7 @@ unsigned int MXC_I2C_GetTimeout (mxc_i2c_regs_t* i2c);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_I2C_Recover (mxc_i2c_regs_t* i2c, unsigned int retries); int MXC_I2C_Recover(mxc_i2c_regs_t *i2c, unsigned int retries);
/* ************************************************************************* */ /* ************************************************************************* */
/* Transaction level functions */ /* Transaction level functions */
@ -630,7 +626,7 @@ int MXC_I2C_Recover (mxc_i2c_regs_t* i2c, unsigned int retries);
* acknowledged, negative if error. See \ref MXC_Error_Codes for the * acknowledged, negative if error. See \ref MXC_Error_Codes for the
* list of error return codes. * list of error return codes.
*/ */
int MXC_I2C_MasterTransaction (mxc_i2c_req_t* req); int MXC_I2C_MasterTransaction(mxc_i2c_req_t *req);
/** /**
* @brief Performs a non-blocking I2C Master transaction. * @brief Performs a non-blocking I2C Master transaction.
@ -657,7 +653,7 @@ int MXC_I2C_MasterTransaction (mxc_i2c_req_t* req);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_I2C_MasterTransactionAsync (mxc_i2c_req_t* req); int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t *req);
/** /**
* @brief Performs a non-blocking I2C Master transaction using DMA for reduced time * @brief Performs a non-blocking I2C Master transaction using DMA for reduced time
@ -685,7 +681,7 @@ int MXC_I2C_MasterTransactionAsync (mxc_i2c_req_t* req);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_I2C_MasterTransactionDMA (mxc_i2c_req_t* req); int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t *req);
/** /**
* @brief Performs a blocking I2C Slave transaction. * @brief Performs a blocking I2C Slave transaction.
@ -725,7 +721,7 @@ int MXC_I2C_MasterTransactionDMA (mxc_i2c_req_t* req);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_I2C_SlaveTransaction (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback); int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback);
/** /**
* @brief Performs a non-blocking I2C Slave transaction. * @brief Performs a non-blocking I2C Slave transaction.
@ -768,7 +764,7 @@ int MXC_I2C_SlaveTransaction (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callb
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_I2C_SlaveTransactionAsync (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback); int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback);
/** /**
* @brief Set the receive threshold level. * @brief Set the receive threshold level.
@ -791,7 +787,7 @@ int MXC_I2C_SlaveTransactionAsync (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_I2C_SetRXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes); int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes);
/** /**
* @brief Get the current receive threshold level. * @brief Get the current receive threshold level.
@ -800,7 +796,7 @@ int MXC_I2C_SetRXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes);
* *
* @return The receive threshold value (in bytes). * @return The receive threshold value (in bytes).
*/ */
unsigned int MXC_I2C_GetRXThreshold (mxc_i2c_regs_t* i2c); unsigned int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t *i2c);
/** /**
* @brief Set the transmit threshold level. * @brief Set the transmit threshold level.
@ -824,7 +820,7 @@ unsigned int MXC_I2C_GetRXThreshold (mxc_i2c_regs_t* i2c);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_I2C_SetTXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes); int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes);
/** /**
* @brief Get the current transmit threshold level. * @brief Get the current transmit threshold level.
@ -833,7 +829,7 @@ int MXC_I2C_SetTXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes);
* *
* @return The transmit threshold value (in bytes). * @return The transmit threshold value (in bytes).
*/ */
unsigned int MXC_I2C_GetTXThreshold (mxc_i2c_regs_t* i2c); unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t *i2c);
/** /**
* @brief Abort any asynchronous requests in progress. * @brief Abort any asynchronous requests in progress.
@ -844,7 +840,7 @@ unsigned int MXC_I2C_GetTXThreshold (mxc_i2c_regs_t* i2c);
* *
* @param i2c Pointer to I2C registers (selects the I2C block used.) * @param i2c Pointer to I2C registers (selects the I2C block used.)
*/ */
void MXC_I2C_AbortAsync (mxc_i2c_regs_t* i2c); void MXC_I2C_AbortAsync(mxc_i2c_regs_t *i2c);
/** /**
* @brief The processing function for asynchronous transactions. * @brief The processing function for asynchronous transactions.
@ -855,7 +851,7 @@ void MXC_I2C_AbortAsync (mxc_i2c_regs_t* i2c);
* *
* @param i2c Pointer to I2C registers (selects the I2C block used.) * @param i2c Pointer to I2C registers (selects the I2C block used.)
*/ */
void MXC_I2C_AsyncHandler (mxc_i2c_regs_t* i2c); void MXC_I2C_AsyncHandler(mxc_i2c_regs_t *i2c);
/** /**
* @brief The processing function for DMA transactions. * @brief The processing function for DMA transactions.
@ -866,14 +862,12 @@ void MXC_I2C_AsyncHandler (mxc_i2c_regs_t* i2c);
* @param ch DMA channel * @param ch DMA channel
* @param error Error status * @param error Error status
*/ */
void MXC_I2C_DMACallback (int ch, int error); void MXC_I2C_DMACallback(int ch, int error);
/**@} end of group i2c */ /**@} end of group i2c */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* _MXC_I2C_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_I2C_H_

37
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_lock.h
View File

@ -3,8 +3,8 @@
* @brief Exclusive access lock utility functions. * @brief Exclusive access lock utility functions.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,16 +34,14 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
/* Define to prevent redundant inclusion */ /* Define to prevent redundant inclusion */
#ifndef _MXC_LOCK_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_LOCK_H_
#define _MXC_LOCK_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_LOCK_H_
// To enable disable this module // To enable disable this module
#define USE_LOCK_IN_DRIVERS 0 #define USE_LOCK_IN_DRIVERS 0
#if USE_LOCK_IN_DRIVERS
/* **** Includes **** */ /* **** Includes **** */
#include "mxc_device.h" #include "mxc_device.h"
@ -52,6 +50,8 @@
extern "C" { extern "C" {
#endif #endif
#if USE_LOCK_IN_DRIVERS
/** /**
* @ingroup syscfg * @ingroup syscfg
* @defgroup mxc_lock_utilities Exclusive Access Locks * @defgroup mxc_lock_utilities Exclusive Access Locks
@ -78,27 +78,26 @@ extern "C" {
* *
* @return #E_NO_ERROR if everything successful, #E_BUSY if lock is taken. * @return #E_NO_ERROR if everything successful, #E_BUSY if lock is taken.
*/ */
int MXC_GetLock (uint32_t *lock, uint32_t value); int MXC_GetLock(uint32_t *lock, uint32_t value);
/** /**
* @brief Free the given lock. * @brief Free the given lock.
* @param[in,out] lock Pointer to the variable used for the lock. When the lock * @param[in,out] lock Pointer to the variable used for the lock. When the lock
* is free, the value pointed to by @p lock is set to zero. * is free, the value pointed to by @p lock is set to zero.
*/ */
void MXC_FreeLock (uint32_t *lock); void MXC_FreeLock(uint32_t *lock);
/**@} end of group mxc_lock_utilities */ /**@} end of group mxc_lock_utilities */
#else // USE_LOCK_IN_DRIVERS
#define MXC_GetLock(x, y) E_NO_ERROR
#define MXC_FreeLock(x)
#endif // USE_LOCK_IN_DRIVERS
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_LOCK_H_
#else // USE_LOCK_IN_DRIVERS
#define MXC_GetLock(x, y) E_NO_ERROR
#define MXC_FreeLock(x)
#endif // USE_LOCK_IN_DRIVERS
#endif /* _MXC_LOCK_H_ */

25
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_pins.h
View File

@ -3,8 +3,8 @@
* @brief This file contains constant pin configurations for the peripherals. * @brief This file contains constant pin configurations for the peripherals.
*/ */
/* ***************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,30 +34,25 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
**************************************************************************** */ ******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_PINS_H_
#ifndef _MXC_PINS_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_PINS_H_
#define _MXC_PINS_H_
#include "gpio.h" #include "gpio.h"
typedef enum { typedef enum { MAP_A, MAP_B, MAP_C } sys_map_t;
MAP_A,
MAP_B,
MAP_C
} sys_map_t;
/***** Global Variables *****/ /***** Global Variables *****/
// Predefined GPIO Configurations // Predefined GPIO Configurations
extern const mxc_gpio_cfg_t gpio_cfg_extclk; extern const mxc_gpio_cfg_t gpio_cfg_lpextclk;
extern const mxc_gpio_cfg_t gpio_cfg_hfextclk;
extern const mxc_gpio_cfg_t gpio_cfg_i2c0; extern const mxc_gpio_cfg_t gpio_cfg_i2c0;
extern const mxc_gpio_cfg_t gpio_cfg_i2c1; extern const mxc_gpio_cfg_t gpio_cfg_i2c1;
extern const mxc_gpio_cfg_t gpio_cfg_i2c2; extern const mxc_gpio_cfg_t gpio_cfg_i2c2;
extern const mxc_gpio_cfg_t gpio_cfg_i2c2b; extern const mxc_gpio_cfg_t gpio_cfg_i2c2b;
extern const mxc_gpio_cfg_t gpio_cfg_i2c2c; extern const mxc_gpio_cfg_t gpio_cfg_i2c2c;
extern const mxc_gpio_cfg_t gpio_cfg_uart0a; extern const mxc_gpio_cfg_t gpio_cfg_uart0a;
extern const mxc_gpio_cfg_t gpio_cfg_uart0a_flow; extern const mxc_gpio_cfg_t gpio_cfg_uart0a_flow;
extern const mxc_gpio_cfg_t gpio_cfg_uart0a_flow_disable; extern const mxc_gpio_cfg_t gpio_cfg_uart0a_flow_disable;
@ -80,7 +75,6 @@ extern const mxc_gpio_cfg_t gpio_cfg_uart3;
extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow; extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow;
extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow_disable; extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow_disable;
extern const mxc_gpio_cfg_t gpio_cfg_spi0; extern const mxc_gpio_cfg_t gpio_cfg_spi0;
// NOTE: SPI1 definied here with SS1 only, SS0 is on port0 by itself. // NOTE: SPI1 definied here with SS1 only, SS0 is on port0 by itself.
extern const mxc_gpio_cfg_t gpio_cfg_spi1; extern const mxc_gpio_cfg_t gpio_cfg_spi1;
@ -112,5 +106,4 @@ extern const mxc_gpio_cfg_t gpio_cfg_mon_lc2;
extern const mxc_gpio_cfg_t gpio_cfg_cmd_rs_lc2; extern const mxc_gpio_cfg_t gpio_cfg_cmd_rs_lc2;
extern const mxc_gpio_cfg_t gpio_cfg_chrg_lc2; extern const mxc_gpio_cfg_t gpio_cfg_chrg_lc2;
#endif /* _MXC_PINS_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_PINS_H_

136
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_spi.h
View File

@ -3,8 +3,8 @@
* @brief Serial Peripheral Interface (SPI) communications driver. * @brief Serial Peripheral Interface (SPI) communications driver.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,9 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
#ifndef _SPI_H_
#define _SPI_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_SPI_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_SPI_H_
/***** includes *******/ /***** includes *******/
#include "spi_regs.h" #include "spi_regs.h"
@ -79,10 +80,10 @@ extern "C" {
* *
*/ */
typedef enum { typedef enum {
SPI_WIDTH_3WIRE, ///< 1 Data line, half duplex SPI_WIDTH_3WIRE, ///< 1 Data line, half duplex
SPI_WIDTH_STANDARD, ///< MISO/MOSI, full duplex SPI_WIDTH_STANDARD, ///< MISO/MOSI, full duplex
SPI_WIDTH_DUAL, ///< 2 Data lines, half duplex SPI_WIDTH_DUAL, ///< 2 Data lines, half duplex
SPI_WIDTH_QUAD, ///< 4 Data lines, half duplex SPI_WIDTH_QUAD, ///< 4 Data lines, half duplex
} mxc_spi_width_t; } mxc_spi_width_t;
/** /**
@ -97,10 +98,10 @@ typedef enum {
* *
*/ */
typedef enum { typedef enum {
SPI_MODE_0, ///< clock phase = 0, clock polarity = 0 SPI_MODE_0, ///< clock phase = 0, clock polarity = 0
SPI_MODE_1, ///< clock phase = 0, clock polarity = 1 SPI_MODE_1, ///< clock phase = 0, clock polarity = 1
SPI_MODE_2, ///< clock phase = 1, clock polarity = 0 SPI_MODE_2, ///< clock phase = 1, clock polarity = 0
SPI_MODE_3, ///< clock phase = 1, clock polarity = 1 SPI_MODE_3, ///< clock phase = 1, clock polarity = 1
} mxc_spi_mode_t; } mxc_spi_mode_t;
typedef struct _mxc_spi_req_t mxc_spi_req_t; typedef struct _mxc_spi_req_t mxc_spi_req_t;
@ -111,7 +112,7 @@ typedef struct _mxc_spi_req_t mxc_spi_req_t;
* @param req The details of the transaction. * @param req The details of the transaction.
* @param result See \ref MXC_Error_Codes for the list of error codes. * @param result See \ref MXC_Error_Codes for the list of error codes.
*/ */
typedef void (*spi_complete_cb_t) (void * req, int result); typedef void (*spi_complete_cb_t)(void *req, int result);
/** /**
* @brief The information required to perform a complete SPI transaction * @brief The information required to perform a complete SPI transaction
@ -120,23 +121,23 @@ typedef void (*spi_complete_cb_t) (void * req, int result);
* @note "completeCB" only needs to be initialized for interrupt driven (Async) and DMA transactions. * @note "completeCB" only needs to be initialized for interrupt driven (Async) and DMA transactions.
*/ */
struct _mxc_spi_req_t { struct _mxc_spi_req_t {
mxc_spi_regs_t* spi; ///<Point to SPI registers mxc_spi_regs_t *spi; ///<Point to SPI registers
int ssIdx; ///< Slave select line to use (Master only, ignored in slave mode) int ssIdx; ///< Slave select line to use (Master only, ignored in slave mode)
int ssDeassert; ///< 1 - Deassert SS at end of transaction, 0 - leave SS asserted int ssDeassert; ///< 1 - Deassert SS at end of transaction, 0 - leave SS asserted
uint8_t *txData; ///< Buffer containing transmit data. For character sizes uint8_t *txData; ///< Buffer containing transmit data. For character sizes
///< < 8 bits, pad the MSB of each byte with zeros. For ///< < 8 bits, pad the MSB of each byte with zeros. For
///< character sizes > 8 bits, use two bytes per character ///< character sizes > 8 bits, use two bytes per character
///< and pad the MSB of the upper byte with zeros ///< and pad the MSB of the upper byte with zeros
uint8_t *rxData; ///< Buffer to store received data For character sizes uint8_t *rxData; ///< Buffer to store received data For character sizes
///< < 8 bits, pad the MSB of each byte with zeros. For ///< < 8 bits, pad the MSB of each byte with zeros. For
///< character sizes > 8 bits, use two bytes per character ///< character sizes > 8 bits, use two bytes per character
///< and pad the MSB of the upper byte with zeros ///< and pad the MSB of the upper byte with zeros
uint32_t txLen; ///< Number of bytes to be sent from txData uint32_t txLen; ///< Number of bytes to be sent from txData
uint32_t rxLen; ///< Number of bytes to be stored in rxData uint32_t rxLen; ///< Number of bytes to be stored in rxData
uint32_t txCnt; ///< Number of bytes actually transmitted from txData uint32_t txCnt; ///< Number of bytes actually transmitted from txData
uint32_t rxCnt; ///< Number of bytes stored in rxData uint32_t rxCnt; ///< Number of bytes stored in rxData
spi_complete_cb_t completeCB; ///< Pointer to function called when transaction is complete spi_complete_cb_t completeCB; ///< Pointer to function called when transaction is complete
}; };
/* ************************************************************************* */ /* ************************************************************************* */
@ -172,8 +173,8 @@ struct _mxc_spi_req_t {
* @return If successful, the actual clock frequency is returned. Otherwise, see * @return If successful, the actual clock frequency is returned. Otherwise, see
* \ref MXC_Error_Codes for a list of return codes. * \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_SPI_Init (mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves, int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves,
unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel); unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel);
/** /**
* @brief Disable and shutdown SPI peripheral. * @brief Disable and shutdown SPI peripheral.
@ -182,7 +183,7 @@ int MXC_SPI_Init (mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int num
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_SPI_Shutdown (mxc_spi_regs_t* spi); int MXC_SPI_Shutdown(mxc_spi_regs_t *spi);
/** /**
* @brief Checks if the given SPI bus can be placed in sleep mode. * @brief Checks if the given SPI bus can be placed in sleep mode.
@ -196,7 +197,7 @@ int MXC_SPI_Shutdown (mxc_spi_regs_t* spi);
* @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref
* MXC_Error_Codes for the list of error return codes. * MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_SPI_ReadyForSleep (mxc_spi_regs_t* spi); int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi);
/** /**
* @brief Returns the frequency of the clock used as the bit rate generator for a given SPI instance. * @brief Returns the frequency of the clock used as the bit rate generator for a given SPI instance.
@ -205,7 +206,7 @@ int MXC_SPI_ReadyForSleep (mxc_spi_regs_t* spi);
* *
* @return Frequency of the clock used as the bit rate generator * @return Frequency of the clock used as the bit rate generator
*/ */
int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi); int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi);
/** /**
* @brief Set the frequency of the SPI interface. * @brief Set the frequency of the SPI interface.
@ -218,7 +219,7 @@ int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi);
* @return Negative if error, otherwise actual speed set. See \ref * @return Negative if error, otherwise actual speed set. See \ref
* MXC_Error_Codes for the list of error return codes. * MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_SPI_SetFrequency (mxc_spi_regs_t* spi, unsigned int hz); int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz);
/** /**
* @brief Get the frequency of the SPI interface. * @brief Get the frequency of the SPI interface.
@ -229,7 +230,7 @@ int MXC_SPI_SetFrequency (mxc_spi_regs_t* spi, unsigned int hz);
* *
* @return The SPI bus frequency in Hertz * @return The SPI bus frequency in Hertz
*/ */
unsigned int MXC_SPI_GetFrequency (mxc_spi_regs_t* spi); unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t *spi);
/** /**
* @brief Sets the number of bits per character * @brief Sets the number of bits per character
@ -239,7 +240,7 @@ unsigned int MXC_SPI_GetFrequency (mxc_spi_regs_t* spi);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_SPI_SetDataSize (mxc_spi_regs_t* spi, int dataSize); int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize);
/** /**
* @brief Gets the number of bits per character * @brief Gets the number of bits per character
@ -248,8 +249,7 @@ int MXC_SPI_SetDataSize (mxc_spi_regs_t* spi, int dataSize);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_SPI_GetDataSize (mxc_spi_regs_t* spi); int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi);
/* ************************************************************************* */ /* ************************************************************************* */
/* Low-level functions */ /* Low-level functions */
@ -265,7 +265,7 @@ int MXC_SPI_GetDataSize (mxc_spi_regs_t* spi);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_SPI_SetSlave (mxc_spi_regs_t* spi, int ssIdx); int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx);
/** /**
* @brief Gets the slave select (SS) line used for transmissions * @brief Gets the slave select (SS) line used for transmissions
@ -276,7 +276,7 @@ int MXC_SPI_SetSlave (mxc_spi_regs_t* spi, int ssIdx);
* *
* @return slave slect * @return slave slect
*/ */
int MXC_SPI_GetSlave (mxc_spi_regs_t* spi); int MXC_SPI_GetSlave(mxc_spi_regs_t *spi);
/** /**
* @brief Sets the SPI width used for transmissions * @brief Sets the SPI width used for transmissions
@ -286,7 +286,7 @@ int MXC_SPI_GetSlave (mxc_spi_regs_t* spi);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_SPI_SetWidth (mxc_spi_regs_t* spi, mxc_spi_width_t spiWidth); int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth);
/** /**
* @brief Gets the SPI width used for transmissions * @brief Gets the SPI width used for transmissions
@ -295,7 +295,7 @@ int MXC_SPI_SetWidth (mxc_spi_regs_t* spi, mxc_spi_width_t spiWidth);
* *
* @return Spi Width \ref mxc_spi_width_t * @return Spi Width \ref mxc_spi_width_t
*/ */
mxc_spi_width_t MXC_SPI_GetWidth (mxc_spi_regs_t* spi); mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi);
/** /**
* @brief Sets the spi mode using clock polarity and clock phase * @brief Sets the spi mode using clock polarity and clock phase
@ -305,7 +305,7 @@ mxc_spi_width_t MXC_SPI_GetWidth (mxc_spi_regs_t* spi);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_SPI_SetMode (mxc_spi_regs_t* spi, mxc_spi_mode_t spiMode); int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode);
/** /**
* @brief Gets the spi mode * @brief Gets the spi mode
@ -314,7 +314,7 @@ int MXC_SPI_SetMode (mxc_spi_regs_t* spi, mxc_spi_mode_t spiMode);
* *
* @return mxc_spi_mode_t \ref mxc_spi_mode_t * @return mxc_spi_mode_t \ref mxc_spi_mode_t
*/ */
mxc_spi_mode_t MXC_SPI_GetMode (mxc_spi_regs_t* spi); mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi);
/** /**
* @brief Starts a SPI Transmission * @brief Starts a SPI Transmission
@ -328,7 +328,7 @@ mxc_spi_mode_t MXC_SPI_GetMode (mxc_spi_regs_t* spi);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_SPI_StartTransmission (mxc_spi_regs_t* spi); int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi);
/** /**
* @brief Checks the SPI Peripheral for an ongoing transmission * @brief Checks the SPI Peripheral for an ongoing transmission
@ -339,7 +339,7 @@ int MXC_SPI_StartTransmission (mxc_spi_regs_t* spi);
* *
* @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_SPI_GetActive (mxc_spi_regs_t* spi); int MXC_SPI_GetActive(mxc_spi_regs_t *spi);
/** /**
* @brief Aborts an ongoing SPI Transmission * @brief Aborts an ongoing SPI Transmission
@ -350,7 +350,7 @@ int MXC_SPI_GetActive (mxc_spi_regs_t* spi);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_SPI_AbortTransmission (mxc_spi_regs_t* spi); int MXC_SPI_AbortTransmission(mxc_spi_regs_t *spi);
/** /**
* @brief Unloads bytes from the receive FIFO. * @brief Unloads bytes from the receive FIFO.
@ -361,8 +361,7 @@ int MXC_SPI_AbortTransmission (mxc_spi_regs_t* spi);
* *
* @return The number of bytes actually read. * @return The number of bytes actually read.
*/ */
unsigned int MXC_SPI_ReadRXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes, unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len);
unsigned int len);
/** /**
* @brief Get the number of bytes currently available in the receive FIFO. * @brief Get the number of bytes currently available in the receive FIFO.
@ -371,7 +370,7 @@ unsigned int MXC_SPI_ReadRXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes,
* *
* @return The number of bytes available. * @return The number of bytes available.
*/ */
unsigned int MXC_SPI_GetRXFIFOAvailable (mxc_spi_regs_t* spi); unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t *spi);
/** /**
* @brief Loads bytes into the transmit FIFO. * @brief Loads bytes into the transmit FIFO.
@ -382,8 +381,7 @@ unsigned int MXC_SPI_GetRXFIFOAvailable (mxc_spi_regs_t* spi);
* *
* @return The number of bytes actually written. * @return The number of bytes actually written.
*/ */
unsigned int MXC_SPI_WriteTXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes, unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len);
unsigned int len);
/** /**
* @brief Get the amount of free space available in the transmit FIFO. * @brief Get the amount of free space available in the transmit FIFO.
@ -392,21 +390,21 @@ unsigned int MXC_SPI_WriteTXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes,
* *
* @return The number of bytes available. * @return The number of bytes available.
*/ */
unsigned int MXC_SPI_GetTXFIFOAvailable (mxc_spi_regs_t* spi); unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t *spi);
/** /**
* @brief Removes and discards all bytes currently in the receive FIFO. * @brief Removes and discards all bytes currently in the receive FIFO.
* *
* @param spi Pointer to SPI registers (selects the SPI block used.) * @param spi Pointer to SPI registers (selects the SPI block used.)
*/ */
void MXC_SPI_ClearRXFIFO (mxc_spi_regs_t* spi); void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi);
/** /**
* @brief Removes and discards all bytes currently in the transmit FIFO. * @brief Removes and discards all bytes currently in the transmit FIFO.
* *
* @param spi Pointer to SPI registers (selects the SPI block used.) * @param spi Pointer to SPI registers (selects the SPI block used.)
*/ */
void MXC_SPI_ClearTXFIFO (mxc_spi_regs_t* spi); void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi);
/** /**
* @brief Set the receive threshold level. * @brief Set the receive threshold level.
@ -425,7 +423,7 @@ void MXC_SPI_ClearTXFIFO (mxc_spi_regs_t* spi);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_SPI_SetRXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes); int MXC_SPI_SetRXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes);
/** /**
* @brief Get the current receive threshold level. * @brief Get the current receive threshold level.
@ -434,7 +432,7 @@ int MXC_SPI_SetRXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes);
* *
* @return The receive threshold value (in bytes). * @return The receive threshold value (in bytes).
*/ */
unsigned int MXC_SPI_GetRXThreshold (mxc_spi_regs_t* spi); unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi);
/** /**
* @brief Set the transmit threshold level. * @brief Set the transmit threshold level.
@ -453,7 +451,7 @@ unsigned int MXC_SPI_GetRXThreshold (mxc_spi_regs_t* spi);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_SPI_SetTXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes); int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes);
/** /**
* @brief Get the current transmit threshold level. * @brief Get the current transmit threshold level.
@ -462,7 +460,7 @@ int MXC_SPI_SetTXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes);
* *
* @return The transmit threshold value (in bytes). * @return The transmit threshold value (in bytes).
*/ */
unsigned int MXC_SPI_GetTXThreshold (mxc_spi_regs_t* spi); unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi);
/** /**
* @brief Gets the interrupt flags that are currently set * @brief Gets the interrupt flags that are currently set
@ -474,7 +472,7 @@ unsigned int MXC_SPI_GetTXThreshold (mxc_spi_regs_t* spi);
* *
* @return The interrupt flags * @return The interrupt flags
*/ */
unsigned int MXC_SPI_GetFlags (mxc_spi_regs_t* spi); unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t *spi);
/** /**
* @brief Clears the interrupt flags that are currently set * @brief Clears the interrupt flags that are currently set
@ -484,7 +482,7 @@ unsigned int MXC_SPI_GetFlags (mxc_spi_regs_t* spi);
* *
* @param spi Pointer to SPI registers (selects the SPI block used.) * @param spi Pointer to SPI registers (selects the SPI block used.)
*/ */
void MXC_SPI_ClearFlags (mxc_spi_regs_t* spi); void MXC_SPI_ClearFlags(mxc_spi_regs_t *spi);
/** /**
* @brief Enables specific interrupts * @brief Enables specific interrupts
@ -495,7 +493,7 @@ void MXC_SPI_ClearFlags (mxc_spi_regs_t* spi);
* @param spi Pointer to SPI registers (selects the SPI block used.) * @param spi Pointer to SPI registers (selects the SPI block used.)
* @param mask The interrupts to be enabled * @param mask The interrupts to be enabled
*/ */
void MXC_SPI_EnableInt (mxc_spi_regs_t* spi, unsigned int mask); void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int mask);
/** /**
* @brief Disables specific interrupts * @brief Disables specific interrupts
@ -506,7 +504,7 @@ void MXC_SPI_EnableInt (mxc_spi_regs_t* spi, unsigned int mask);
* @param spi Pointer to SPI registers (selects the SPI block used.) * @param spi Pointer to SPI registers (selects the SPI block used.)
* @param mask The interrupts to be disabled * @param mask The interrupts to be disabled
*/ */
void MXC_SPI_DisableInt (mxc_spi_regs_t* spi, unsigned int mask); void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int mask);
/* ************************************************************************* */ /* ************************************************************************* */
/* Transaction level functions */ /* Transaction level functions */
@ -535,7 +533,7 @@ void MXC_SPI_DisableInt (mxc_spi_regs_t* spi, unsigned int mask);
* *
* @return See \ref MXC_Error_Codes for the list of error return codes. * @return See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_SPI_MasterTransaction (mxc_spi_req_t* req); int MXC_SPI_MasterTransaction(mxc_spi_req_t *req);
/** /**
* @brief Setup an interrupt-driven SPI transaction * @brief Setup an interrupt-driven SPI transaction
@ -547,7 +545,7 @@ int MXC_SPI_MasterTransaction (mxc_spi_req_t* req);
* *
* @return See \ref MXC_Error_Codes for the list of error return codes. * @return See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_SPI_MasterTransactionAsync (mxc_spi_req_t* req); int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req);
/** /**
* @brief Setup a DMA driven SPI transaction * @brief Setup a DMA driven SPI transaction
@ -564,7 +562,7 @@ int MXC_SPI_MasterTransactionAsync (mxc_spi_req_t* req);
* *
* @return See \ref MXC_Error_Codes for the list of error return codes. * @return See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_SPI_MasterTransactionDMA (mxc_spi_req_t* req); int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req);
/** /**
* @brief Performs a blocking SPI transaction. * @brief Performs a blocking SPI transaction.
@ -581,7 +579,7 @@ int MXC_SPI_MasterTransactionDMA (mxc_spi_req_t* req);
* *
* @return See \ref MXC_Error_Codes for the list of error return codes. * @return See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_SPI_SlaveTransaction (mxc_spi_req_t* req); int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req);
/** /**
* @brief Setup an interrupt-driven SPI transaction * @brief Setup an interrupt-driven SPI transaction
@ -593,7 +591,7 @@ int MXC_SPI_SlaveTransaction (mxc_spi_req_t* req);
* *
* @return See \ref MXC_Error_Codes for the list of error return codes. * @return See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_SPI_SlaveTransactionAsync (mxc_spi_req_t* req); int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req);
/** /**
* @brief Setup a DMA driven SPI transaction * @brief Setup a DMA driven SPI transaction
@ -610,7 +608,7 @@ int MXC_SPI_SlaveTransactionAsync (mxc_spi_req_t* req);
* *
* @return See \ref MXC_Error_Codes for the list of error return codes. * @return See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_SPI_SlaveTransactionDMA (mxc_spi_req_t* req); int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req);
/** /**
* @brief Sets the TX data to transmit as a 'dummy' byte * @brief Sets the TX data to transmit as a 'dummy' byte
@ -623,7 +621,7 @@ int MXC_SPI_SlaveTransactionDMA (mxc_spi_req_t* req);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_SPI_SetDefaultTXData (mxc_spi_regs_t* spi, unsigned int defaultTXData); int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData);
/** /**
* @brief Abort any asynchronous requests in progress. * @brief Abort any asynchronous requests in progress.
@ -634,7 +632,7 @@ int MXC_SPI_SetDefaultTXData (mxc_spi_regs_t* spi, unsigned int defaultTXData);
* *
* @param spi Pointer to SPI registers (selects the SPI block used.) * @param spi Pointer to SPI registers (selects the SPI block used.)
*/ */
void MXC_SPI_AbortAsync (mxc_spi_regs_t* spi); void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi);
/** /**
* @brief The processing function for asynchronous transactions. * @brief The processing function for asynchronous transactions.
@ -645,7 +643,7 @@ void MXC_SPI_AbortAsync (mxc_spi_regs_t* spi);
* *
* @param spi Pointer to SPI registers (selects the SPI block used.) * @param spi Pointer to SPI registers (selects the SPI block used.)
*/ */
void MXC_SPI_AsyncHandler (mxc_spi_regs_t* spi); void MXC_SPI_AsyncHandler(mxc_spi_regs_t *spi);
/**@} end of group spi */ /**@} end of group spi */
@ -653,4 +651,4 @@ void MXC_SPI_AsyncHandler (mxc_spi_regs_t* spi);
} }
#endif #endif
#endif /* _PT_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_SPI_H_

263
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_sys.h
View File

@ -3,8 +3,8 @@
* @brief System level header file. * @brief System level header file.
*/ */
/******************************************************************************* /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -36,8 +36,8 @@
* *
******************************************************************************/ ******************************************************************************/
#ifndef _MXC_MXC_SYS_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_SYS_H_
#define _MXC_MXC_SYS_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_SYS_H_
#include "mxc_device.h" #include "mxc_device.h"
#include "gcr_regs.h" #include "gcr_regs.h"
@ -49,85 +49,196 @@ extern "C" {
/** @brief System reset0 and reset1 enumeration. Used in MXC_SYS_PeriphReset0 function */ /** @brief System reset0 and reset1 enumeration. Used in MXC_SYS_PeriphReset0 function */
typedef enum { typedef enum {
MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */ MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */
MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, /**< Reset WDT */ MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, /**< Reset WDT */
MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */ MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */
MXC_SYS_RESET0_GPIO1 = MXC_F_GCR_RST0_GPIO1_POS, /**< Reset GPIO1 */ MXC_SYS_RESET0_GPIO1 = MXC_F_GCR_RST0_GPIO1_POS, /**< Reset GPIO1 */
MXC_SYS_RESET0_TMR0 = MXC_F_GCR_RST0_TMR0_POS, /**< Reset TIMER0 */ MXC_SYS_RESET0_TMR0 = MXC_F_GCR_RST0_TMR0_POS, /**< Reset TIMER0 */
MXC_SYS_RESET0_TMR1 = MXC_F_GCR_RST0_TMR1_POS, /**< Reset TIMER1 */ MXC_SYS_RESET0_TMR1 = MXC_F_GCR_RST0_TMR1_POS, /**< Reset TIMER1 */
MXC_SYS_RESET0_TMR2 = MXC_F_GCR_RST0_TMR2_POS, /**< Reset TIMER2 */ MXC_SYS_RESET0_TMR2 = MXC_F_GCR_RST0_TMR2_POS, /**< Reset TIMER2 */
MXC_SYS_RESET0_TMR3 = MXC_F_GCR_RST0_TMR3_POS, /**< Reset TIMER3 */ MXC_SYS_RESET0_TMR3 = MXC_F_GCR_RST0_TMR3_POS, /**< Reset TIMER3 */
MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, /**< Reset UART0 */ MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, /**< Reset UART0 */
MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, /**< Reset UART1 */ MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, /**< Reset UART1 */
MXC_SYS_RESET0_SPI0 = MXC_F_GCR_RST0_SPI0_POS, /**< Reset SPI0 */ MXC_SYS_RESET0_SPI0 = MXC_F_GCR_RST0_SPI0_POS, /**< Reset SPI0 */
MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */ MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */
MXC_SYS_RESET0_SPI2 = MXC_F_GCR_RST0_SPI2_POS, /**< Reset SPI2 */ MXC_SYS_RESET0_SPI2 = MXC_F_GCR_RST0_SPI2_POS, /**< Reset SPI2 */
MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */ MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */
MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */ MXC_SYS_RESET0_TRNG = MXC_F_GCR_RST0_TRNG_POS, /**< Reset TRNG */
MXC_SYS_RESET0_TRNG = MXC_F_GCR_RST0_TRNG_POS, /**< Reset TRNG */ MXC_SYS_RESET0_UART2 = MXC_F_GCR_RST0_UART2_POS, /**< Reset UART2 */
MXC_SYS_RESET0_UART2 = MXC_F_GCR_RST0_UART2_POS, /**< Reset UART2 */ MXC_SYS_RESET0_SRST = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */
MXC_SYS_RESET0_SRST = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */ MXC_SYS_RESET0_PRST = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */
MXC_SYS_RESET0_PRST = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */ MXC_SYS_RESET0_SYS = MXC_F_GCR_RST0_SYS_POS, /**< System reset */
MXC_SYS_RESET0_SYS = MXC_F_GCR_RST0_SYS_POS, /**< System reset */
/* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */ /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */
MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */ MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */
MXC_SYS_RESET1_WDT1 = (MXC_F_GCR_RST1_WDT1_POS + 32), /**< Reset WDT1 */ MXC_SYS_RESET1_WDT1 = (MXC_F_GCR_RST1_WDT1_POS + 32), /**< Reset WDT1 */
MXC_SYS_RESET1_AES = (MXC_F_GCR_RST1_AES_POS + 32), /**< Reset WDT1 */ MXC_SYS_RESET1_AES = (MXC_F_GCR_RST1_AES_POS + 32), /**< Reset AES */
MXC_SYS_RESET1_CRC = (MXC_F_GCR_RST1_CRC_POS + 32), /**< Reset WDT1 */ MXC_SYS_RESET1_CRC = (MXC_F_GCR_RST1_CRC_POS + 32), /**< Reset CRC */
MXC_SYS_RESET1_I2C2 = (MXC_F_GCR_RST1_I2C2_POS + 32), /**< Reset */ MXC_SYS_RESET1_I2C2 = (MXC_F_GCR_RST1_I2C2_POS + 32), /**< Reset I2C2*/
MXC_SYS_RESET1_I2S = (MXC_F_GCR_RST1_I2S_POS + 32), /**< Reset */ MXC_SYS_RESET1_I2S = (MXC_F_GCR_RST1_I2S_POS + 32), /**< Reset I2S*/
/* LPGCR RESET Below this line we add 64 to separate LPGCR and GCR */ /* LPGCR RESET Below this line we add 64 to separate LPGCR and GCR */
MXC_SYS_RESET_TMR4 = (MXC_F_MCR_RST_LPTMR0_POS + 64), /**< Reset TMR4 */ MXC_SYS_RESET_TMR4 = (MXC_F_MCR_RST_LPTMR0_POS + 64), /**< Reset TMR4 */
MXC_SYS_RESET_TMR5 = (MXC_F_MCR_RST_LPTMR1_POS + 64), /**< Reset TMR5 */ MXC_SYS_RESET_TMR5 = (MXC_F_MCR_RST_LPTMR1_POS + 64), /**< Reset TMR5 */
MXC_SYS_RESET_UART3 = (MXC_F_MCR_RST_LPUART0_POS + 64), /**< Reset UART3 */ MXC_SYS_RESET_UART3 = (MXC_F_MCR_RST_LPUART0_POS + 64), /**< Reset UART3 */
MXC_SYS_RESET_RTC = (MXC_F_MCR_RST_RTC_POS + 64), /**< Reset RTC */
} mxc_sys_reset_t; } mxc_sys_reset_t;
/** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */ /** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */
typedef enum { typedef enum {
MXC_SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */ MXC_SYS_PERIPH_CLOCK_GPIO0 =
MXC_SYS_PERIPH_CLOCK_GPIO1 = MXC_F_GCR_PCLKDIS0_GPIO1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO1 clock */ MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */
MXC_SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PCLKDIS0_DMA_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */ MXC_SYS_PERIPH_CLOCK_GPIO1 =
MXC_SYS_PERIPH_CLOCK_SPI0 = MXC_F_GCR_PCLKDIS0_SPI0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI0 clock */ MXC_F_GCR_PCLKDIS0_GPIO1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO1 clock */
MXC_SYS_PERIPH_CLOCK_SPI1 = MXC_F_GCR_PCLKDIS0_SPI1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */ MXC_SYS_PERIPH_CLOCK_DMA =
MXC_SYS_PERIPH_CLOCK_SPI2 = MXC_F_GCR_PCLKDIS0_SPI2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI2 clock */ MXC_F_GCR_PCLKDIS0_DMA_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */
MXC_SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PCLKDIS0_UART0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */ MXC_SYS_PERIPH_CLOCK_SPI0 =
MXC_SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PCLKDIS0_UART1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */ MXC_F_GCR_PCLKDIS0_SPI0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI0 clock */
MXC_SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PCLKDIS0_I2C0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */ MXC_SYS_PERIPH_CLOCK_SPI1 =
MXC_SYS_PERIPH_CLOCK_TMR0 = MXC_F_GCR_PCLKDIS0_TMR0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T0 clock */ MXC_F_GCR_PCLKDIS0_SPI1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */
MXC_SYS_PERIPH_CLOCK_TMR1 = MXC_F_GCR_PCLKDIS0_TMR1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T1 clock */ MXC_SYS_PERIPH_CLOCK_SPI2 =
MXC_SYS_PERIPH_CLOCK_TMR2 = MXC_F_GCR_PCLKDIS0_TMR2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T2 clock */ MXC_F_GCR_PCLKDIS0_SPI2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI2 clock */
MXC_SYS_PERIPH_CLOCK_TMR3 = MXC_F_GCR_PCLKDIS0_TMR3_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T3 clock */ MXC_SYS_PERIPH_CLOCK_UART0 =
MXC_SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PCLKDIS0_I2C1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */ MXC_F_GCR_PCLKDIS0_UART0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */
MXC_SYS_PERIPH_CLOCK_UART1 =
MXC_F_GCR_PCLKDIS0_UART1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */
MXC_SYS_PERIPH_CLOCK_I2C0 =
MXC_F_GCR_PCLKDIS0_I2C0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */
MXC_SYS_PERIPH_CLOCK_TMR0 =
MXC_F_GCR_PCLKDIS0_TMR0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T0 clock */
MXC_SYS_PERIPH_CLOCK_TMR1 =
MXC_F_GCR_PCLKDIS0_TMR1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T1 clock */
MXC_SYS_PERIPH_CLOCK_TMR2 =
MXC_F_GCR_PCLKDIS0_TMR2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T2 clock */
MXC_SYS_PERIPH_CLOCK_TMR3 =
MXC_F_GCR_PCLKDIS0_TMR3_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T3 clock */
MXC_SYS_PERIPH_CLOCK_I2C1 =
MXC_F_GCR_PCLKDIS0_I2C1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */
/* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */ /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */
MXC_SYS_PERIPH_CLOCK_UART2 = (MXC_F_GCR_PCLKDIS1_UART2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_UART2 clock */ MXC_SYS_PERIPH_CLOCK_UART2 =
MXC_SYS_PERIPH_CLOCK_TRNG = (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_TRNG clock */ (MXC_F_GCR_PCLKDIS1_UART2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_UART2 clock */
MXC_SYS_PERIPH_CLOCK_WDT0 = (MXC_F_GCR_PCLKDIS1_WWDT0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT0 clock */ MXC_SYS_PERIPH_CLOCK_TRNG =
MXC_SYS_PERIPH_CLOCK_WDT1 = (MXC_F_GCR_PCLKDIS1_WWDT1_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT1 clock */ (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_TRNG clock */
MXC_SYS_PERIPH_CLOCK_ICACHE = (MXC_F_GCR_PCLKDIS1_ICC0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_ICACHE clock */ MXC_SYS_PERIPH_CLOCK_WDT0 =
MXC_SYS_PERIPH_CLOCK_CRC = (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CRC clock */ (MXC_F_GCR_PCLKDIS1_WWDT0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT0 clock */
MXC_SYS_PERIPH_CLOCK_AES = (MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_AES clock */ MXC_SYS_PERIPH_CLOCK_WDT1 =
MXC_SYS_PERIPH_CLOCK_I2C2 = (MXC_F_GCR_PCLKDIS1_I2C2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2C2 clock */ (MXC_F_GCR_PCLKDIS1_WWDT1_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT1 clock */
MXC_SYS_PERIPH_CLOCK_I2S = (MXC_F_GCR_PCLKDIS1_I2S_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */ MXC_SYS_PERIPH_CLOCK_ICACHE =
(MXC_F_GCR_PCLKDIS1_ICC0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_ICACHE clock */
MXC_SYS_PERIPH_CLOCK_CRC =
(MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CRC clock */
MXC_SYS_PERIPH_CLOCK_AES =
(MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_AES clock */
MXC_SYS_PERIPH_CLOCK_I2C2 =
(MXC_F_GCR_PCLKDIS1_I2C2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2C2 clock */
MXC_SYS_PERIPH_CLOCK_I2S =
(MXC_F_GCR_PCLKDIS1_I2S_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */
/* LPGCR PCLKDIS Below this line we add 64 to seperate GCR and LPGCR registers */ /* LPGCR PCLKDIS Below this line we add 64 to seperate GCR and LPGCR registers */
MXC_SYS_PERIPH_CLOCK_TMR4 = (MXC_F_MCR_CLKDIS_LPTMR0_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR4 clock */ MXC_SYS_PERIPH_CLOCK_TMR4 =
MXC_SYS_PERIPH_CLOCK_TMR5 = (MXC_F_MCR_CLKDIS_LPTMR1_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR5 clock */ (MXC_F_MCR_CLKDIS_LPTMR0_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR4 clock */
MXC_SYS_PERIPH_CLOCK_UART3 = (MXC_F_MCR_CLKDIS_LPUART0_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_UART3 clock */ MXC_SYS_PERIPH_CLOCK_TMR5 =
(MXC_F_MCR_CLKDIS_LPTMR1_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR5 clock */
MXC_SYS_PERIPH_CLOCK_UART3 =
(MXC_F_MCR_CLKDIS_LPUART0_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_UART3 clock */
} mxc_sys_periph_clock_t; } mxc_sys_periph_clock_t;
/** @brief Enumeration to select System Clock source */ /** @brief Enumeration to select System Clock source */
typedef enum { typedef enum {
MXC_SYS_CLOCK_IPO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO, MXC_SYS_CLOCK_IPO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO,
MXC_SYS_CLOCK_IBRO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO, MXC_SYS_CLOCK_IBRO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO,
MXC_SYS_CLOCK_ERFO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO, MXC_SYS_CLOCK_ERFO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO,
MXC_SYS_CLOCK_INRO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO, MXC_SYS_CLOCK_INRO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO,
MXC_SYS_CLOCK_ERTCO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO, MXC_SYS_CLOCK_ERTCO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO,
MXC_SYS_CLOCK_EXTCLK = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK MXC_SYS_CLOCK_EXTCLK = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK
} mxc_sys_system_clock_t; } mxc_sys_system_clock_t;
#define MXC_SYS_USN_CHECKSUM_LEN 16 #define MXC_SYS_USN_CHECKSUM_LEN 16
/***** Function Prototypes *****/ /***** Function Prototypes *****/
typedef struct {
int ie_status;
int in_critical;
} mxc_crit_state_t;
static mxc_crit_state_t _state = { .ie_status = (int)0xFFFFFFFF, .in_critical = 0 };
static inline void _mxc_crit_get_state()
{
#ifdef __CORTEX_M
/*
On ARM M the 0th bit of the Priority Mask register indicates
whether interrupts are enabled or not.
0 = enabled
1 = disabled
*/
uint32_t primask = __get_PRIMASK();
_state.ie_status = (primask == 0);
#endif
#ifdef __riscv
/*
On RISC-V bit position 3 (Machine Interrupt Enable) of the
mstatus register indicates whether interrupts are enabled.
0 = disabled
1 = enabled
*/
uint32_t mstatus = get_mstatus();
_state.ie_status = ((mstatus & (1 << 3)) != 0);
#endif
}
/**
* @brief Enter a critical section of code that cannot be interrupted.
*/
static inline void MXC_SYS_Crit_Enter(void)
{
_mxc_crit_get_state();
if (_state.ie_status)
__disable_irq();
_state.in_critical = 1;
}
/**
* @brief Exit a critical section of code, re-enabling interrupts if they
* were previously.
*/
static inline void MXC_SYS_Crit_Exit(void)
{
if (_state.ie_status) {
__enable_irq();
}
_state.in_critical = 0;
_mxc_crit_get_state();
/*
^ Reset the state again to prevent edge case
where interrupts get disabled, then Crit_Exit() gets
called, which would inadvertently re-enable interrupts
from old state.
*/
}
/**
* @brief Polls whether code is currently executing from a critical section.
* @returns 1 if code is currently in a critical section (interrupts are disabled).
* 0 if code is not in a critical section.
*/
static inline int MXC_SYS_In_Crit_Section(void)
{
return _state.in_critical;
}
/**
* @brief Macro for wrapping a section of code to make it critical. Note: this macro
* does not support nesting.
*/
// clang-format off
#define MXC_CRITICAL(code) { \
MXC_SYS_Crit_Enter();\
code;\
MXC_SYS_Crit_Exit();\
}
// clang-format on
/** /**
* @brief Reads the device USN. * @brief Reads the device USN.
* @param usn Pointer to store the USN. * @param usn Pointer to store the USN.
@ -141,25 +252,25 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum);
* @param clock Enumeration for desired clock. * @param clock Enumeration for desired clock.
* @returns 0 is the clock is disabled, non 0 if the clock is enabled. * @returns 0 is the clock is disabled, non 0 if the clock is enabled.
*/ */
int MXC_SYS_IsClockEnabled (mxc_sys_periph_clock_t clock); int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock);
/** /**
* @brief Disables the selected peripheral clock. * @brief Disables the selected peripheral clock.
* @param clock Enumeration for desired clock. * @param clock Enumeration for desired clock.
*/ */
void MXC_SYS_ClockDisable (mxc_sys_periph_clock_t clock); void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock);
/** /**
* @brief Enables the selected peripheral clock. * @brief Enables the selected peripheral clock.
* @param clock Enumeration for desired clock. * @param clock Enumeration for desired clock.
*/ */
void MXC_SYS_ClockEnable (mxc_sys_periph_clock_t clock); void MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock);
/** /**
* @brief Enables the 32kHz oscillator * @brief Enables the 32kHz oscillator
* @param mxc_sys_cfg Not used, may be NULL. * @param mxc_sys_cfg Not used, may be NULL.
*/ */
void MXC_SYS_RTCClockEnable (void); void MXC_SYS_RTCClockEnable(void);
/** /**
* @brief Disables the 32kHz oscillator * @brief Disables the 32kHz oscillator
@ -172,14 +283,14 @@ int MXC_SYS_RTCClockDisable();
* @param clock The clock to enable * @param clock The clock to enable
* @return E_NO_ERROR if everything is successful * @return E_NO_ERROR if everything is successful
*/ */
int MXC_SYS_ClockSourceEnable (mxc_sys_system_clock_t clock); int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock);
/** /**
* @brief Disable System Clock Source * @brief Disable System Clock Source
* @param clock The clock to disable * @param clock The clock to disable
* @return E_NO_ERROR if everything is successful * @return E_NO_ERROR if everything is successful
*/ */
int MXC_SYS_ClockSourceDisable (mxc_sys_system_clock_t clock); int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock);
/** /**
* @brief Select the system clock. * @brief Select the system clock.
@ -187,22 +298,22 @@ int MXC_SYS_ClockSourceDisable (mxc_sys_system_clock_t clock);
* @param tmr Optional tmr pointer for timeout. NULL if undesired. * @param tmr Optional tmr pointer for timeout. NULL if undesired.
* @returns E_NO_ERROR if everything is successful. * @returns E_NO_ERROR if everything is successful.
*/ */
int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock); int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock);
/** /**
* @brief Wait for a clock to enable with timeout * @brief Wait for a clock to enable with timeout
* @param ready The clock to wait for * @param ready The clock to wait for
* @return E_NO_ERROR if ready, E_TIME_OUT if timeout * @return E_NO_ERROR if ready, E_TIME_OUT if timeout
*/ */
int MXC_SYS_Clock_Timeout (uint32_t ready); int MXC_SYS_Clock_Timeout(uint32_t ready);
/** /**
* @brief Reset the peripherals and/or CPU in the rstr0 or rstr1 register. * @brief Reset the peripherals and/or CPU in the rstr0 or rstr1 register.
* @param Enumeration for what to reset. Can reset multiple items at once. * @param Enumeration for what to reset. Can reset multiple items at once.
*/ */
void MXC_SYS_Reset_Periph (mxc_sys_reset_t reset); void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* _MXC_MXC_SYS_H_*/ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_SYS_H_

81
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/rtc.h
View File

@ -3,8 +3,8 @@
* @brief Real Time Clock (RTC) functions and prototypes. * @brief Real Time Clock (RTC) functions and prototypes.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,17 +34,19 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
/* Define to prevent redundant inclusion */ /* Define to prevent redundant inclusion */
#ifndef _RTC_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_RTC_H_
#define _RTC_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_RTC_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
#include "mxc_device.h" #include "mxc_device.h"
#include "rtc_regs.h"
#include "mxc_sys.h" #include "mxc_sys.h"
#include "rtc_regs.h"
#include "tmr_regs.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -56,33 +58,36 @@ extern "C" {
* @{ * @{
*/ */
#define MXC_RTC_MAX_SSEC (MXC_F_RTC_SSEC_SSEC + 1)
#define MXC_RTC_TRIM_TMR_IRQ MXC_F_TMR_INTFL_IRQ_A
/* **** Definitions **** */ /* **** Definitions **** */
/** /**
* @brief Bitmasks for each of the RTC's Frequency. * @brief Bitmasks for each of the RTC's Frequency.
*/ */
typedef enum { typedef enum {
MXC_RTC_F_1HZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ1HZ, ///< 1Hz (Compensated) MXC_RTC_F_1HZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ1HZ, ///< 1Hz (Compensated)
MXC_RTC_F_512HZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ512HZ, ///< 512Hz (Compensated) MXC_RTC_F_512HZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ512HZ, ///< 512Hz (Compensated)
MXC_RTC_F_4KHZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ4KHZ, ///< 4Khz MXC_RTC_F_4KHZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ4KHZ, ///< 4Khz
MXC_RTC_F_32KHZ = 32, ///< 32Khz MXC_RTC_F_32KHZ = 32, ///< 32Khz
} mxc_rtc_freq_sel_t; } mxc_rtc_freq_sel_t;
/** /**
* @brief Bitmasks for each of the RTC's interrupt enables. * @brief Bitmasks for each of the RTC's interrupt enables.
*/ */
typedef enum { typedef enum {
MXC_RTC_INT_EN_LONG = MXC_F_RTC_CTRL_TOD_ALARM_IE, ///< Long-interval alarm interrupt enable MXC_RTC_INT_EN_LONG = MXC_F_RTC_CTRL_TOD_ALARM_IE, ///< Long-interval alarm interrupt enable
MXC_RTC_INT_EN_SHORT = MXC_F_RTC_CTRL_SSEC_ALARM_IE, ///< Short-interval alarm interrupt enable MXC_RTC_INT_EN_SHORT = MXC_F_RTC_CTRL_SSEC_ALARM_IE, ///< Short-interval alarm interrupt enable
MXC_RTC_INT_EN_READY = MXC_F_RTC_CTRL_RDY_IE, ///< Timer ready interrupt enable MXC_RTC_INT_EN_READY = MXC_F_RTC_CTRL_RDY_IE, ///< Timer ready interrupt enable
} mxc_rtc_int_en_t; } mxc_rtc_int_en_t;
/** /**
* @brief Bitmasks for each of the RTC's interrupt flags. * @brief Bitmasks for each of the RTC's interrupt flags.
*/ */
typedef enum { typedef enum {
MXC_RTC_INT_FL_LONG = MXC_F_RTC_CTRL_TOD_ALARM, ///< Long-interval alarm interrupt flag MXC_RTC_INT_FL_LONG = MXC_F_RTC_CTRL_TOD_ALARM, ///< Long-interval alarm interrupt flag
MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_SSEC_ALARM, ///< Short-interval alarm interrupt flag MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_SSEC_ALARM, ///< Short-interval alarm interrupt flag
MXC_RTC_INT_FL_READY = MXC_F_RTC_CTRL_RDY, ///< Timer ready interrupt flag MXC_RTC_INT_FL_READY = MXC_F_RTC_CTRL_RDY, ///< Timer ready interrupt flag
} mxc_rtc_int_fl_t; } mxc_rtc_int_fl_t;
/** /**
@ -90,7 +95,7 @@ typedef enum {
* @param ras 20-bit value 0-0xFFFFF * @param ras 20-bit value 0-0xFFFFF
* @retval returns Success or Fail, see \ref MXC_Error_Codes * @retval returns Success or Fail, see \ref MXC_Error_Codes
*/ */
int MXC_RTC_SetTimeofdayAlarm (uint32_t ras); int MXC_RTC_SetTimeofdayAlarm(uint32_t ras);
/** /**
* @brief Set Sub-Second alarm value and enable interrupt, * @brief Set Sub-Second alarm value and enable interrupt,
@ -98,46 +103,46 @@ int MXC_RTC_SetTimeofdayAlarm (uint32_t ras);
* @param rssa 32-bit value 0-0xFFFFFFFF * @param rssa 32-bit value 0-0xFFFFFFFF
* @retval returns Success or Fail, see \ref MXC_Error_Codes * @retval returns Success or Fail, see \ref MXC_Error_Codes
*/ */
int MXC_RTC_SetSubsecondAlarm (uint32_t rssa); int MXC_RTC_SetSubsecondAlarm(uint32_t rssa);
/** /**
* @brief Start the Real Time Clock (Blocking function) * @brief Start the Real Time Clock (Blocking function)
* @retval returns Success or Fail, see \ref MXC_Error_Codes * @retval returns Success or Fail, see \ref MXC_Error_Codes
*/ */
int MXC_RTC_Start (void); int MXC_RTC_Start(void);
/** /**
* @brief Stop the Real Time Clock (Blocking function) * @brief Stop the Real Time Clock (Blocking function)
* @retval returns Success or Fail, see \ref MXC_Error_Codes * @retval returns Success or Fail, see \ref MXC_Error_Codes
*/ */
int MXC_RTC_Stop (void); int MXC_RTC_Stop(void);
/** /**
* @brief Initialize the sec and ssec registers and enable RTC (Blocking function) * @brief Initialize the sec and ssec registers and enable RTC (Blocking function)
* @param sec set the RTC Sec counter (32-bit) * @param sec set the RTC Sec counter (32-bit)
* @param ssec set the RTC Sub-second counter (8-bit) * @param ssec set the RTC Sub-second counter (12-bit)
* @retval returns Success or Fail, see \ref MXC_Error_Codes * @retval returns Success or Fail, see \ref MXC_Error_Codes
*/ */
int MXC_RTC_Init (uint32_t sec, uint8_t ssec); int MXC_RTC_Init(uint32_t sec, uint16_t ssec);
/** /**
* @brief Allow generation of Square Wave on the SQW pin (Blocking function) * @brief Allow generation of Square Wave on the SQW pin (Blocking function)
* @param fq Frequency output selection * @param fq Frequency output selection
* @retval returns Success or Fail, see \ref MXC_Error_Codes * @retval returns Success or Fail, see \ref MXC_Error_Codes
*/ */
int MXC_RTC_SquareWaveStart (mxc_rtc_freq_sel_t fq); int MXC_RTC_SquareWaveStart(mxc_rtc_freq_sel_t fq);
/** /**
* @brief Stop the generation of square wave (Blocking function) * @brief Stop the generation of square wave (Blocking function)
* @retval returns Success or Fail, see \ref MXC_Error_Codes * @retval returns Success or Fail, see \ref MXC_Error_Codes
*/ */
int MXC_RTC_SquareWaveStop (void); int MXC_RTC_SquareWaveStop(void);
/** /**
* @brief Set Trim register value (Blocking function) * @brief Set Trim register value (Blocking function)
* @param trm set the RTC Trim (8-bit, +/- 127) * @param trm set the RTC Trim (8-bit, +/- 127)
* @retval returns Success or Fail, see \ref MXC_Error_Codes * @retval returns Success or Fail, see \ref MXC_Error_Codes
*/ */
int MXC_RTC_Trim (int8_t trm); int MXC_RTC_Trim(int8_t trm);
/** /**
* @brief Enable Interurpts (Blocking function) * @brief Enable Interurpts (Blocking function)
@ -145,7 +150,7 @@ int MXC_RTC_Trim (int8_t trm);
* See #mxc_rtc_int_en_t for available choices. * See #mxc_rtc_int_en_t for available choices.
* @retval returns Success or Fail, see \ref MXC_Error_Codes * @retval returns Success or Fail, see \ref MXC_Error_Codes
*/ */
int MXC_RTC_EnableInt (uint32_t mask); int MXC_RTC_EnableInt(uint32_t mask);
/** /**
* @brief Disable Interurpts (Blocking function) * @brief Disable Interurpts (Blocking function)
@ -153,7 +158,7 @@ int MXC_RTC_EnableInt (uint32_t mask);
* See #mxc_rtc_int_en_t for available choices. * See #mxc_rtc_int_en_t for available choices.
* @retval returns Success or Fail, see \ref MXC_Error_Codes * @retval returns Success or Fail, see \ref MXC_Error_Codes
*/ */
int MXC_RTC_DisableInt (uint32_t mask); int MXC_RTC_DisableInt(uint32_t mask);
/** /**
* @brief Gets interrupt flags. * @brief Gets interrupt flags.
@ -161,7 +166,7 @@ int MXC_RTC_DisableInt (uint32_t mask);
* currently set. See \ref mxc_rtc_int_fl_t for the list * currently set. See \ref mxc_rtc_int_fl_t for the list
* of possible flags. * of possible flags.
*/ */
int MXC_RTC_GetFlags (void); int MXC_RTC_GetFlags(void);
/** /**
* @brief Clear interrupt flags. * @brief Clear interrupt flags.
@ -169,19 +174,19 @@ int MXC_RTC_GetFlags (void);
* See #mxc_rtc_int_fl_t for the list of possible flags. * See #mxc_rtc_int_fl_t for the list of possible flags.
* @retval returns Success or Fail, see \ref MXC_Error_Codes * @retval returns Success or Fail, see \ref MXC_Error_Codes
*/ */
int MXC_RTC_ClearFlags (int flags); int MXC_RTC_ClearFlags(int flags);
/** /**
* @brief Get SubSecond * @brief Get SubSecond
* @retval Returns subsecond value or E_BUSY, see /ref MXC_ERROR_CODES * @retval Returns subsecond value or E_BUSY, see /ref MXC_ERROR_CODES
*/ */
int MXC_RTC_GetSubSecond (void); int MXC_RTC_GetSubSecond(void);
/** /**
* @brief Get Second * @brief Get Second
* @retval returns second value or E_BUSY, see /ref MXC_ERROR_CODES * @retval returns second value or E_BUSY, see /ref MXC_ERROR_CODES
*/ */
int MXC_RTC_GetSecond (void); int MXC_RTC_GetSecond(void);
/** /**
* @brief Get the time using nuclear fusion. Or atomically. Something like that. * @brief Get the time using nuclear fusion. Or atomically. Something like that.
@ -189,7 +194,7 @@ int MXC_RTC_GetSecond (void);
* @param subsec pointer to store subseconds value * @param subsec pointer to store subseconds value
* @retval returns Success or Fail, see \ref MXC_Error_Codes * @retval returns Success or Fail, see \ref MXC_Error_Codes
*/ */
int MXC_RTC_GetTime (uint32_t* sec, uint32_t* subsec); int MXC_RTC_GetTime(uint32_t *sec, uint32_t *subsec);
/** /**
* @brief Get RTC busy flag. * @brief Get RTC busy flag.
@ -197,9 +202,21 @@ int MXC_RTC_GetTime (uint32_t* sec, uint32_t* subsec);
*/ */
int MXC_RTC_GetBusyFlag(void); int MXC_RTC_GetBusyFlag(void);
/**
* @brief Calculate and set the appropriate RTC trim value based on an accurate reference clock
*
* @param tmr Timer available to be used to measure known time periods over which the RTC ticks are counted
*
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*
* @note If RTC running before calling this function and interrupts enabled, accuracy of trimming could be affected
* @note External 32MHz must be installed and calibrated properly for this function to be successful
*/
int MXC_RTC_TrimCrystal(mxc_tmr_regs_t *tmr);
/**@} end of group rtc */ /**@} end of group rtc */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* _RTC_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_RTC_H_

152
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/tmr.h
View File

@ -3,8 +3,8 @@
* @brief Timer (TMR) function prototypes and data types. * @brief Timer (TMR) function prototypes and data types.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,19 +34,20 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
/* Define to prevent redundant inclusion */ /* Define to prevent redundant inclusion */
#ifndef _TMR_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_TMR_H_
#define _TMR_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_TMR_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h>
#include <stdbool.h>
#include "mxc_device.h" #include "mxc_device.h"
#include "tmr_regs.h" #include "tmr_regs.h"
#include "mxc_sys.h" #include "mxc_sys.h"
#include "gcr_regs.h" #include "gcr_regs.h"
#include "mcr_regs.h" #include "mcr_regs.h"
#include "stdbool.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -62,33 +63,33 @@ extern "C" {
* @brief Timer prescaler values * @brief Timer prescaler values
*/ */
typedef enum { typedef enum {
TMR_PRES_1 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1, ///< Divide input clock by 1 TMR_PRES_1 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1, ///< Divide input clock by 1
TMR_PRES_2 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2, ///< Divide input clock by 2 TMR_PRES_2 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2, ///< Divide input clock by 2
TMR_PRES_4 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4, ///< Divide input clock by 4 TMR_PRES_4 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4, ///< Divide input clock by 4
TMR_PRES_8 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8, ///< Divide input clock by 8 TMR_PRES_8 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8, ///< Divide input clock by 8
TMR_PRES_16 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16, ///< Divide input clock by 16 TMR_PRES_16 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16, ///< Divide input clock by 16
TMR_PRES_32 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32, ///< Divide input clock by 32 TMR_PRES_32 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32, ///< Divide input clock by 32
TMR_PRES_64 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64, ///< Divide input clock by 64 TMR_PRES_64 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64, ///< Divide input clock by 64
TMR_PRES_128 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128, ///< Divide input clock by 128 TMR_PRES_128 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128, ///< Divide input clock by 128
TMR_PRES_256 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256, ///< Divide input clock by 256 TMR_PRES_256 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256, ///< Divide input clock by 256
TMR_PRES_512 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512, ///< Divide input clock by 512 TMR_PRES_512 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512, ///< Divide input clock by 512
TMR_PRES_1024 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024, ///< Divide input clock by 1024 TMR_PRES_1024 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024, ///< Divide input clock by 1024
TMR_PRES_2048 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048, ///< Divide input clock by 2048 TMR_PRES_2048 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048, ///< Divide input clock by 2048
TMR_PRES_4096 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 ///< Divide input clock by 4096 TMR_PRES_4096 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 ///< Divide input clock by 4096
} mxc_tmr_pres_t; } mxc_tmr_pres_t;
/** /**
* @brief Timer modes * @brief Timer modes
*/ */
typedef enum { typedef enum {
TMR_MODE_ONESHOT = MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT, ///< Timer Mode ONESHOT TMR_MODE_ONESHOT = MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT, ///< Timer Mode ONESHOT
TMR_MODE_CONTINUOUS = MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS, ///< Timer Mode CONTINUOUS TMR_MODE_CONTINUOUS = MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS, ///< Timer Mode CONTINUOUS
TMR_MODE_COUNTER = MXC_S_TMR_CTRL0_MODE_A_COUNTER, ///< Timer Mode COUNTER TMR_MODE_COUNTER = MXC_S_TMR_CTRL0_MODE_A_COUNTER, ///< Timer Mode COUNTER
TMR_MODE_PWM = MXC_S_TMR_CTRL0_MODE_A_PWM, ///< Timer Mode PWM TMR_MODE_PWM = MXC_S_TMR_CTRL0_MODE_A_PWM, ///< Timer Mode PWM
TMR_MODE_CAPTURE = MXC_S_TMR_CTRL0_MODE_A_CAPTURE, ///< Timer Mode CAPTURE TMR_MODE_CAPTURE = MXC_S_TMR_CTRL0_MODE_A_CAPTURE, ///< Timer Mode CAPTURE
TMR_MODE_COMPARE = MXC_S_TMR_CTRL0_MODE_A_COMPARE, ///< Timer Mode COMPARE TMR_MODE_COMPARE = MXC_S_TMR_CTRL0_MODE_A_COMPARE, ///< Timer Mode COMPARE
TMR_MODE_GATED = MXC_S_TMR_CTRL0_MODE_A_GATED, ///< Timer Mode GATED TMR_MODE_GATED = MXC_S_TMR_CTRL0_MODE_A_GATED, ///< Timer Mode GATED
TMR_MODE_CAPTURE_COMPARE = MXC_S_TMR_CTRL0_MODE_A_CAPCOMP ///< Timer Mode CAPTURECOMPARE TMR_MODE_CAPTURE_COMPARE = MXC_S_TMR_CTRL0_MODE_A_CAPCOMP ///< Timer Mode CAPTURECOMPARE
} mxc_tmr_mode_t; } mxc_tmr_mode_t;
/** /**
@ -96,19 +97,19 @@ typedef enum {
* *
*/ */
typedef enum { typedef enum {
TMR_BIT_MODE_32, ///< Timer Mode 32 bit TMR_BIT_MODE_32, ///< Timer Mode 32 bit
TMR_BIT_MODE_16A, ///< Timer Mode Lower 16 bit TMR_BIT_MODE_16A, ///< Timer Mode Lower 16 bit
TMR_BIT_MODE_16B, ///< Timer Mode Upper 16 bit TMR_BIT_MODE_16B, ///< Timer Mode Upper 16 bit
} mxc_tmr_bit_mode_t; } mxc_tmr_bit_mode_t;
/** /**
* @brief Timer units of time enumeration * @brief Timer units of time enumeration
*/ */
typedef enum { typedef enum {
TMR_UNIT_NANOSEC, ///< Nanosecond Unit Indicator TMR_UNIT_NANOSEC, ///< Nanosecond Unit Indicator
TMR_UNIT_MICROSEC, ///< Microsecond Unit Indicator TMR_UNIT_MICROSEC, ///< Microsecond Unit Indicator
TMR_UNIT_MILLISEC, ///< Millisecond Unit Indicator TMR_UNIT_MILLISEC, ///< Millisecond Unit Indicator
TMR_UNIT_SEC, ///< Second Unit Indicator TMR_UNIT_SEC, ///< Second Unit Indicator
} mxc_tmr_unit_t; } mxc_tmr_unit_t;
/** /**
@ -117,28 +118,28 @@ typedef enum {
* 32K and 80K clocks can only be used for Timers 4 and 5 * 32K and 80K clocks can only be used for Timers 4 and 5
*/ */
typedef enum { typedef enum {
MXC_TMR_APB_CLK, ///< PCLK CLock MXC_TMR_APB_CLK, ///< PCLK CLock
MXC_TMR_EXT_CLK, ///< External Clock MXC_TMR_EXT_CLK, ///< External Clock
MXC_TMR_8M_CLK , ///< 8MHz Clock MXC_TMR_8M_CLK, ///< 8MHz Clock
MXC_TMR_32M_CLK, ///< 32MHz Clock MXC_TMR_32M_CLK, ///< 32MHz Clock
MXC_TMR_32K_CLK, ///< 32KHz Clock MXC_TMR_32K_CLK, ///< 32KHz Clock
MXC_TMR_80K_CLK, ///< 80KHz Clock MXC_TMR_80K_CLK, ///< 80KHz Clock
} mxc_tmr_clock_t; } mxc_tmr_clock_t;
/** /**
* @brief Timer Configuration * @brief Timer Configuration
*/ */
typedef struct { typedef struct {
mxc_tmr_pres_t pres; ///< Desired timer prescaler mxc_tmr_pres_t pres; ///< Desired timer prescaler
mxc_tmr_mode_t mode; ///< Desired timer mode mxc_tmr_mode_t mode; ///< Desired timer mode
mxc_tmr_bit_mode_t bitMode; ///< Desired timer bits mxc_tmr_bit_mode_t bitMode; ///< Desired timer bits
mxc_tmr_clock_t clock; ///< Desired clock source mxc_tmr_clock_t clock; ///< Desired clock source
uint32_t cmp_cnt; ///< Compare register value in timer ticks uint32_t cmp_cnt; ///< Compare register value in timer ticks
unsigned pol; ///< Polarity (0 or 1) unsigned pol; ///< Polarity (0 or 1)
} mxc_tmr_cfg_t; } mxc_tmr_cfg_t;
/* **** Definitions **** */ /* **** Definitions **** */
typedef void (*mxc_tmr_complete_t) (int error); typedef void (*mxc_tmr_complete_t)(int error);
/* **** Function Prototypes **** */ /* **** Function Prototypes **** */
@ -151,25 +152,25 @@ typedef void (*mxc_tmr_complete_t) (int error);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_TMR_Init (mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t* cfg, bool init_pins); int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins);
/** /**
* @brief Shutdown timer module clock. * @brief Shutdown timer module clock.
* @param tmr Pointer to timer module to initialize. * @param tmr Pointer to timer module to initialize.
*/ */
void MXC_TMR_Shutdown (mxc_tmr_regs_t *tmr); void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr);
/** /**
* @brief Start the timer counting. * @brief Start the timer counting.
* @param tmr Pointer to timer module to initialize. * @param tmr Pointer to timer module to initialize.
*/ */
void MXC_TMR_Start (mxc_tmr_regs_t* tmr); void MXC_TMR_Start(mxc_tmr_regs_t *tmr);
/** /**
* @brief Stop the timer. * @brief Stop the timer.
* @param tmr Pointer to timer module to initialize. * @param tmr Pointer to timer module to initialize.
*/ */
void MXC_TMR_Stop (mxc_tmr_regs_t* tmr); void MXC_TMR_Stop(mxc_tmr_regs_t *tmr);
/** /**
* @brief Set the value of the first transition in PWM mode * @brief Set the value of the first transition in PWM mode
@ -178,28 +179,28 @@ void MXC_TMR_Stop (mxc_tmr_regs_t* tmr);
* @note Will block until safe to change the period count. * @note Will block until safe to change the period count.
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_TMR_SetPWM (mxc_tmr_regs_t* tmr, uint32_t pwm); int MXC_TMR_SetPWM(mxc_tmr_regs_t *tmr, uint32_t pwm);
/** /**
* @brief Get the timer compare count. * @brief Get the timer compare count.
* @param tmr Pointer to timer module to initialize. * @param tmr Pointer to timer module to initialize.
* @return Returns the current compare count. * @return Returns the current compare count.
*/ */
uint32_t MXC_TMR_GetCompare (mxc_tmr_regs_t* tmr); uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t *tmr);
/** /**
* @brief Get the timer capture count. * @brief Get the timer capture count.
* @param tmr Pointer to timer module to initialize. * @param tmr Pointer to timer module to initialize.
* @return Returns the most recent capture count. * @return Returns the most recent capture count.
*/ */
uint32_t MXC_TMR_GetCapture (mxc_tmr_regs_t* tmr); uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t *tmr);
/** /**
* @brief Get the timer count. * @brief Get the timer count.
* @param tmr Pointer to timer module to initialize. * @param tmr Pointer to timer module to initialize.
* @return Returns the current count. * @return Returns the current count.
*/ */
uint32_t MXC_TMR_GetCount (mxc_tmr_regs_t* tmr); uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t *tmr);
/** /**
* @brief Calculate count for required frequency. * @brief Calculate count for required frequency.
@ -209,34 +210,35 @@ uint32_t MXC_TMR_GetCount (mxc_tmr_regs_t* tmr);
* @param frequency required frequency. * @param frequency required frequency.
* @return Returns the period count. * @return Returns the period count.
*/ */
uint32_t MXC_TMR_GetPeriod (mxc_tmr_regs_t* tmr, mxc_tmr_clock_t clock, uint32_t prescalar, uint32_t frequency); uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, mxc_tmr_clock_t clock, uint32_t prescalar,
uint32_t frequency);
/** /**
* @brief Clear the timer interrupt. * @brief Clear the timer interrupt.
* @param tmr Pointer to timer module to initialize. * @param tmr Pointer to timer module to initialize.
*/ */
void MXC_TMR_ClearFlags (mxc_tmr_regs_t* tmr); void MXC_TMR_ClearFlags(mxc_tmr_regs_t *tmr);
/** /**
* @brief Get the timer interrupt status. * @brief Get the timer interrupt status.
* @param tmr Pointer to timer module to initialize. * @param tmr Pointer to timer module to initialize.
* @return Returns the interrupt status. 1 if interrupt has occured. * @return Returns the interrupt status. 1 if interrupt has occured.
*/ */
uint32_t MXC_TMR_GetFlags (mxc_tmr_regs_t* tmr); uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t *tmr);
/** /**
* @brief enable interupt * @brief enable interupt
* *
* @param tmr Pointer to timer module to initialize. * @param tmr Pointer to timer module to initialize.
*/ */
void MXC_TMR_EnableInt (mxc_tmr_regs_t* tmr); void MXC_TMR_EnableInt(mxc_tmr_regs_t *tmr);
/** /**
* @brief disable interupt * @brief disable interupt
* *
* @param tmr Pointer to timer module to initialize. * @param tmr Pointer to timer module to initialize.
*/ */
void MXC_TMR_DisableInt (mxc_tmr_regs_t* tmr); void MXC_TMR_DisableInt(mxc_tmr_regs_t *tmr);
/** /**
* @brief Enable wakeup from sleep * @brief Enable wakeup from sleep
@ -244,7 +246,7 @@ void MXC_TMR_DisableInt (mxc_tmr_regs_t* tmr);
* @param tmr Pointer to timer module to initialize. * @param tmr Pointer to timer module to initialize.
* @param cfg System configuration object * @param cfg System configuration object
*/ */
void MXC_TMR_EnableWakeup (mxc_tmr_regs_t* tmr, mxc_tmr_cfg_t* cfg); void MXC_TMR_EnableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg);
/** /**
* @brief Disable wakeup from sleep * @brief Disable wakeup from sleep
@ -252,7 +254,7 @@ void MXC_TMR_EnableWakeup (mxc_tmr_regs_t* tmr, mxc_tmr_cfg_t* cfg);
* @param tmr Pointer to timer module to initialize. * @param tmr Pointer to timer module to initialize.
* @param cfg System configuration object * @param cfg System configuration object
*/ */
void MXC_TMR_DisableWakeup (mxc_tmr_regs_t* tmr, mxc_tmr_cfg_t* cfg); void MXC_TMR_DisableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg);
/** /**
* @brief Set the timer compare count. * @brief Set the timer compare count.
@ -260,14 +262,14 @@ void MXC_TMR_DisableWakeup (mxc_tmr_regs_t* tmr, mxc_tmr_cfg_t* cfg);
* @param cmp_cnt New compare count. * @param cmp_cnt New compare count.
* @note In PWM Mode use this to set the value of the second transition. * @note In PWM Mode use this to set the value of the second transition.
*/ */
void MXC_TMR_SetCompare (mxc_tmr_regs_t *tmr, uint32_t cmp_cnt); void MXC_TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt);
/** /**
* @brief Set the timer count. * @brief Set the timer count.
* @param tmr Pointer to timer module to initialize. * @param tmr Pointer to timer module to initialize.
* @param cnt New count. * @param cnt New count.
*/ */
void MXC_TMR_SetCount (mxc_tmr_regs_t *tmr, uint32_t cnt); void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt);
/** /**
* @brief Dealay for a set periord of time measured in microseconds * @brief Dealay for a set periord of time measured in microseconds
@ -275,7 +277,7 @@ void MXC_TMR_SetCount (mxc_tmr_regs_t *tmr, uint32_t cnt);
* @param tmr The timer * @param tmr The timer
* @param us microseconds to delay for * @param us microseconds to delay for
*/ */
void MXC_TMR_Delay (mxc_tmr_regs_t *tmr, unsigned long us); void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us);
/** /**
* @brief Start a timer that will time out after a certain number of microseconds * @brief Start a timer that will time out after a certain number of microseconds
@ -284,7 +286,7 @@ void MXC_TMR_Delay (mxc_tmr_regs_t *tmr, unsigned long us);
* @param tmr The timer * @param tmr The timer
* @param us microseconds to time out after * @param us microseconds to time out after
*/ */
void MXC_TMR_TO_Start (mxc_tmr_regs_t *tmr, unsigned long us); void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us);
/** /**
* @brief Check on time out timer * @brief Check on time out timer
@ -293,21 +295,21 @@ void MXC_TMR_TO_Start (mxc_tmr_regs_t *tmr, unsigned long us);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_TMR_TO_Check (mxc_tmr_regs_t *tmr); int MXC_TMR_TO_Check(mxc_tmr_regs_t *tmr);
/** /**
* @brief Stop the Timeout timer * @brief Stop the Timeout timer
* *
* @param tmr The timer * @param tmr The timer
*/ */
void MXC_TMR_TO_Stop (mxc_tmr_regs_t *tmr); void MXC_TMR_TO_Stop(mxc_tmr_regs_t *tmr);
/** /**
* @brief Clear timeout timer back to zero * @brief Clear timeout timer back to zero
* *
* @param tmr The timer * @param tmr The timer
*/ */
void MXC_TMR_TO_Clear (mxc_tmr_regs_t *tmr); void MXC_TMR_TO_Clear(mxc_tmr_regs_t *tmr);
/** /**
* @brief Get elapsed time of timeout timer * @brief Get elapsed time of timeout timer
@ -316,7 +318,7 @@ void MXC_TMR_TO_Clear (mxc_tmr_regs_t *tmr);
* *
* @return Time that has elapsed in timeout timer * @return Time that has elapsed in timeout timer
*/ */
unsigned int MXC_TMR_TO_Elapsed (mxc_tmr_regs_t *tmr); unsigned int MXC_TMR_TO_Elapsed(mxc_tmr_regs_t *tmr);
/** /**
* @brief Amount of time remaining until timeour * @brief Amount of time remaining until timeour
@ -325,14 +327,14 @@ unsigned int MXC_TMR_TO_Elapsed (mxc_tmr_regs_t *tmr);
* *
* @return Time that is left until timeout * @return Time that is left until timeout
*/ */
unsigned int MXC_TMR_TO_Remaining (mxc_tmr_regs_t *tmr); unsigned int MXC_TMR_TO_Remaining(mxc_tmr_regs_t *tmr);
/** /**
* @brief Start stopwatch * @brief Start stopwatch
* *
* @param tmr The timer * @param tmr The timer
*/ */
void MXC_TMR_SW_Start (mxc_tmr_regs_t *tmr); void MXC_TMR_SW_Start(mxc_tmr_regs_t *tmr);
/** /**
* @brief Stopwatch stop * @brief Stopwatch stop
@ -341,7 +343,7 @@ void MXC_TMR_SW_Start (mxc_tmr_regs_t *tmr);
* *
* @return the time when the stopwatch is stopped. * @return the time when the stopwatch is stopped.
*/ */
unsigned int MXC_TMR_SW_Stop (mxc_tmr_regs_t *tmr); unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t *tmr);
/** /**
* @brief Get time from timer * @brief Get time from timer
@ -353,7 +355,7 @@ unsigned int MXC_TMR_SW_Stop (mxc_tmr_regs_t *tmr);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_TMR_GetTime (mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units); int MXC_TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units);
/**@} end of group tmr */ /**@} end of group tmr */
@ -361,4 +363,4 @@ int MXC_TMR_GetTime (mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tm
} }
#endif #endif
#endif /* _TMR_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_TMR_H_

40
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/trng.h
View File

@ -3,8 +3,8 @@
* @brief Random number generator driver. * @brief Random number generator driver.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,10 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
#ifndef _TRNG_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_TRNG_H_
#define _TRNG_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_TRNG_H_
/***** Includes *****/ /***** Includes *****/
#include "trng_regs.h" #include "trng_regs.h"
@ -52,9 +52,8 @@ extern "C" {
* @{ * @{
*/ */
/***** Function Prototypes *****/ /***** Function Prototypes *****/
typedef void (*mxc_trng_complete_t) (void* req, int result); typedef void (*mxc_trng_complete_t)(void *req, int result);
/* ************************************************************************* */ /* ************************************************************************* */
/* Global Control/Configuration functions */ /* Global Control/Configuration functions */
@ -65,32 +64,32 @@ typedef void (*mxc_trng_complete_t) (void* req, int result);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_TRNG_Init (void); int MXC_TRNG_Init(void);
/** /**
* @brief Enable TRNG Interrupts * @brief Enable TRNG Interrupts
* *
*/ */
void MXC_TRNG_EnableInt (); void MXC_TRNG_EnableInt();
/** /**
* @brief Disable TRNG Interrupts * @brief Disable TRNG Interrupts
* *
*/ */
void MXC_TRNG_DisableInt (); void MXC_TRNG_DisableInt();
/** /**
* @brief Disable and reset portions of the TRNG * @brief Disable and reset portions of the TRNG
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_TRNG_Shutdown (void); int MXC_TRNG_Shutdown(void);
/** /**
* @brief This function should be called from the TRNG ISR Handler * @brief This function should be called from the TRNG ISR Handler
* when using Async functions * when using Async functions
*/ */
void MXC_TRNG_Handler (void); void MXC_TRNG_Handler(void);
/* ************************************************************************* */ /* ************************************************************************* */
/* True Random Number Generator (TRNG) functions */ /* True Random Number Generator (TRNG) functions */
@ -101,7 +100,7 @@ void MXC_TRNG_Handler (void);
* *
* @return A random 32-bit number * @return A random 32-bit number
*/ */
int MXC_TRNG_RandomInt (void); int MXC_TRNG_RandomInt(void);
/** /**
* @brief Get a random number of length len * @brief Get a random number of length len
@ -111,7 +110,7 @@ int MXC_TRNG_RandomInt (void);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_TRNG_Random (uint8_t* data, uint32_t len); int MXC_TRNG_Random(uint8_t *data, uint32_t len);
/** /**
* @brief Get a random number of length len, do not block while generating data * @brief Get a random number of length len, do not block while generating data
@ -122,16 +121,25 @@ int MXC_TRNG_Random (uint8_t* data, uint32_t len);
* @param callback Function that will be called when all data has been generated * @param callback Function that will be called when all data has been generated
* *
*/ */
void MXC_TRNG_RandomAsync (uint8_t* data, uint32_t len, mxc_trng_complete_t callback); void MXC_TRNG_RandomAsync(uint8_t *data, uint32_t len, mxc_trng_complete_t callback);
/** /**
* @brief Generate an AES key and transfer to the AES block * @brief Generate an AES key and transfer to the AES block
*/ */
void MXC_TRNG_GenerateKey(void); void MXC_TRNG_GenerateKey(void);
/**
* @brief Perform health test of the TRNG entropy source
*
* @return If test fails the function will return E_BAD_STATE (-7), otherwise it will return E_NO_ERROR.
*
* @warning MAX32670 with Rev. A Silicon does not support health tests. (Check MXC_GCR->revision to see which revision your chip is.)
*/
int MXC_TRNG_HealthTest(void);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
/**@} end of group trng */ /**@} end of group trng */
#endif /* _TRNG_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_TRNG_H_

163
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/uart.h
View File

@ -3,8 +3,8 @@
* @brief Serial Peripheral Interface (UART) communications driver. * @brief Serial Peripheral Interface (UART) communications driver.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,16 +34,18 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
/* Define to prevent redundant inclusion */ /* Define to prevent redundant inclusion */
#ifndef _MXC_UART_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_UART_H_
#define _MXC_UART_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_UART_H_
/***** Definitions *****/ /***** Definitions *****/
#include "uart_regs.h" #include "uart_regs.h"
#include "mxc_sys.h" #include "mxc_sys.h"
#define UART_EXTCLK_FREQ EXTCLK_FREQ
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
@ -60,8 +62,8 @@ typedef struct _mxc_uart_req_t mxc_uart_req_t;
* *
*/ */
typedef enum { typedef enum {
MXC_UART_STOP_1, ///< UART Stop 1 clock cycle MXC_UART_STOP_1, ///< UART Stop 1 clock cycle
MXC_UART_STOP_2, ///< UART Stop 2 clock cycle (1.5 clocks for 5 bit characters) MXC_UART_STOP_2, ///< UART Stop 2 clock cycle (1.5 clocks for 5 bit characters)
} mxc_uart_stop_t; } mxc_uart_stop_t;
/** /**
@ -69,11 +71,11 @@ typedef enum {
* *
*/ */
typedef enum { typedef enum {
MXC_UART_PARITY_DISABLE, ///< UART Parity Disabled MXC_UART_PARITY_DISABLE, ///< UART Parity Disabled
MXC_UART_PARITY_EVEN_0, ///< UART Parity Even, 0 based MXC_UART_PARITY_EVEN_0, ///< UART Parity Even, 0 based
MXC_UART_PARITY_EVEN_1, ///< UART Parity Even, 1 based MXC_UART_PARITY_EVEN_1, ///< UART Parity Even, 1 based
MXC_UART_PARITY_ODD_0, ///< UART Parity Odd, 0 based MXC_UART_PARITY_ODD_0, ///< UART Parity Odd, 0 based
MXC_UART_PARITY_ODD_1, ///< UART Parity Odd, 1 based MXC_UART_PARITY_ODD_1, ///< UART Parity Odd, 1 based
} mxc_uart_parity_t; } mxc_uart_parity_t;
/** /**
@ -81,8 +83,8 @@ typedef enum {
* *
*/ */
typedef enum { typedef enum {
MXC_UART_FLOW_DIS, ///< UART Flow Control Disabled MXC_UART_FLOW_DIS, ///< UART Flow Control Disabled
MXC_UART_FLOW_EN, ///< UART Flow Control Enabled MXC_UART_FLOW_EN, ///< UART Flow Control Enabled
} mxc_uart_flow_t; } mxc_uart_flow_t;
/** /**
@ -104,7 +106,7 @@ typedef enum {
* @param req The details of the transaction. * @param req The details of the transaction.
* @param result See \ref MXC_Error_Codes for the list of error codes. * @param result See \ref MXC_Error_Codes for the list of error codes.
*/ */
typedef void (*mxc_uart_complete_cb_t)(mxc_uart_req_t* req, int result); typedef void (*mxc_uart_complete_cb_t)(mxc_uart_req_t *req, int result);
/** /**
* @brief The callback routine used to indicate the transaction has terminated. * @brief The callback routine used to indicate the transaction has terminated.
@ -113,7 +115,7 @@ typedef void (*mxc_uart_complete_cb_t)(mxc_uart_req_t* req, int result);
* @param num The number of characters actually copied * @param num The number of characters actually copied
* @param result See \ref MXC_Error_Codes for the list of error codes. * @param result See \ref MXC_Error_Codes for the list of error codes.
*/ */
typedef void (*mxc_uart_dma_complete_cb_t)(mxc_uart_req_t* req, int num, int result); typedef void (*mxc_uart_dma_complete_cb_t)(mxc_uart_req_t *req, int num, int result);
/** /**
* @brief The information required to perform a complete UART transaction * @brief The information required to perform a complete UART transaction
@ -122,21 +124,21 @@ typedef void (*mxc_uart_dma_complete_cb_t)(mxc_uart_req_t* req, int num, int res
* @note "callback" only needs to be initialized for interrupt driven (Async) and DMA transactions. * @note "callback" only needs to be initialized for interrupt driven (Async) and DMA transactions.
*/ */
struct _mxc_uart_req_t { struct _mxc_uart_req_t {
mxc_uart_regs_t* uart; ///<Point to UART registers mxc_uart_regs_t *uart; ///<Point to UART registers
const uint8_t *txData; ///< Buffer containing transmit data. For character sizes const uint8_t *txData; ///< Buffer containing transmit data. For character sizes
///< < 8 bits, pad the MSB of each byte with zeros. For ///< < 8 bits, pad the MSB of each byte with zeros. For
///< character sizes > 8 bits, use two bytes per character ///< character sizes > 8 bits, use two bytes per character
///< and pad the MSB of the upper byte with zeros ///< and pad the MSB of the upper byte with zeros
uint8_t *rxData; ///< Buffer to store received data For character sizes uint8_t *rxData; ///< Buffer to store received data For character sizes
///< < 8 bits, pad the MSB of each byte with zeros. For ///< < 8 bits, pad the MSB of each byte with zeros. For
///< character sizes > 8 bits, use two bytes per character ///< character sizes > 8 bits, use two bytes per character
///< and pad the MSB of the upper byte with zeros ///< and pad the MSB of the upper byte with zeros
uint32_t txLen; ///< Number of bytes to be sent from txData uint32_t txLen; ///< Number of bytes to be sent from txData
uint32_t rxLen; ///< Number of bytes to be stored in rxData uint32_t rxLen; ///< Number of bytes to be stored in rxData
volatile uint32_t txCnt; ///< Number of bytes actually transmitted from txData volatile uint32_t txCnt; ///< Number of bytes actually transmitted from txData
volatile uint32_t rxCnt; ///< Number of bytes stored in rxData volatile uint32_t rxCnt; ///< Number of bytes stored in rxData
mxc_uart_complete_cb_t callback; ///< Pointer to function called when transaction is complete mxc_uart_complete_cb_t callback; ///< Pointer to function called when transaction is complete
}; };
/***** Function Prototypes *****/ /***** Function Prototypes *****/
@ -164,7 +166,7 @@ struct _mxc_uart_req_t {
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_UART_Init(mxc_uart_regs_t* uart, unsigned int baud, mxc_uart_clock_t clock, sys_map_t map); int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock, sys_map_t map);
/** /**
* @brief Disable and shutdown UART peripheral. * @brief Disable and shutdown UART peripheral.
@ -173,7 +175,7 @@ int MXC_UART_Init(mxc_uart_regs_t* uart, unsigned int baud, mxc_uart_clock_t clo
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_UART_Shutdown(mxc_uart_regs_t* uart); int MXC_UART_Shutdown(mxc_uart_regs_t *uart);
/** /**
* @brief Checks if the given UART bus can be placed in sleep more. * @brief Checks if the given UART bus can be placed in sleep more.
@ -187,7 +189,7 @@ int MXC_UART_Shutdown(mxc_uart_regs_t* uart);
* @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref
* MXC_Error_Codes for the list of error return codes. * MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_UART_ReadyForSleep(mxc_uart_regs_t* uart); int MXC_UART_ReadyForSleep(mxc_uart_regs_t *uart);
/** /**
* @brief Set the frequency of the UART interface. * @brief Set the frequency of the UART interface.
@ -199,7 +201,7 @@ int MXC_UART_ReadyForSleep(mxc_uart_regs_t* uart);
* @return Negative if error, otherwise actual speed set. See \ref * @return Negative if error, otherwise actual speed set. See \ref
* MXC_Error_Codes for the list of error return codes. * MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_UART_SetFrequency(mxc_uart_regs_t* uart, unsigned int baud, mxc_uart_clock_t clock); int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock);
/** /**
* @brief Get the frequency of the UART interface. * @brief Get the frequency of the UART interface.
@ -210,7 +212,7 @@ int MXC_UART_SetFrequency(mxc_uart_regs_t* uart, unsigned int baud, mxc_uart_clo
* *
* @return The UART baud rate * @return The UART baud rate
*/ */
int MXC_UART_GetFrequency(mxc_uart_regs_t* uart); int MXC_UART_GetFrequency(mxc_uart_regs_t *uart);
/** /**
* @brief Sets the number of bits per character * @brief Sets the number of bits per character
@ -220,7 +222,7 @@ int MXC_UART_GetFrequency(mxc_uart_regs_t* uart);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_UART_SetDataSize(mxc_uart_regs_t* uart, int dataSize); int MXC_UART_SetDataSize(mxc_uart_regs_t *uart, int dataSize);
/** /**
* @brief Sets the number of stop bits sent at the end of a character * @brief Sets the number of stop bits sent at the end of a character
@ -230,7 +232,7 @@ int MXC_UART_SetDataSize(mxc_uart_regs_t* uart, int dataSize);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_UART_SetStopBits(mxc_uart_regs_t* uart, mxc_uart_stop_t stopBits); int MXC_UART_SetStopBits(mxc_uart_regs_t *uart, mxc_uart_stop_t stopBits);
/** /**
* @brief Sets the type of parity generation used * @brief Sets the type of parity generation used
@ -240,7 +242,7 @@ int MXC_UART_SetStopBits(mxc_uart_regs_t* uart, mxc_uart_stop_t stopBits);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_UART_SetParity(mxc_uart_regs_t* uart, mxc_uart_parity_t parity); int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity);
/** /**
* @brief Sets the flow control used * @brief Sets the flow control used
@ -251,7 +253,7 @@ int MXC_UART_SetParity(mxc_uart_regs_t* uart, mxc_uart_parity_t parity);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_UART_SetFlowCtrl(mxc_uart_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold, sys_map_t map); int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold, sys_map_t map);
/** /**
* @brief Sets the clock source for the baud rate generator * @brief Sets the clock source for the baud rate generator
@ -262,7 +264,7 @@ int MXC_UART_SetFlowCtrl(mxc_uart_regs_t* uart, mxc_uart_flow_t flowCtrl, int rt
* @return Actual baud rate if successful, otherwise see \ref MXC_Error_Codes * @return Actual baud rate if successful, otherwise see \ref MXC_Error_Codes
* for a list of return codes. * for a list of return codes.
*/ */
int MXC_UART_SetClockSource(mxc_uart_regs_t* uart, mxc_uart_clock_t clock); int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, mxc_uart_clock_t clock);
/* ************************************************************************* */ /* ************************************************************************* */
/* Low-level functions */ /* Low-level functions */
@ -277,7 +279,7 @@ int MXC_UART_SetClockSource(mxc_uart_regs_t* uart, mxc_uart_clock_t clock);
* *
* @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_UART_GetActive(mxc_uart_regs_t* uart); int MXC_UART_GetActive(mxc_uart_regs_t *uart);
/** /**
* @brief Aborts an ongoing UART Transmission * @brief Aborts an ongoing UART Transmission
@ -286,7 +288,7 @@ int MXC_UART_GetActive(mxc_uart_regs_t* uart);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_UART_AbortTransmission(mxc_uart_regs_t* uart); int MXC_UART_AbortTransmission(mxc_uart_regs_t *uart);
/** /**
* @brief Reads the next available character. If no character is available, this function * @brief Reads the next available character. If no character is available, this function
@ -296,7 +298,7 @@ int MXC_UART_AbortTransmission(mxc_uart_regs_t* uart);
* *
* @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t* uart); int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart);
/** /**
* @brief Writes a character on the UART. If the character cannot be written because the * @brief Writes a character on the UART. If the character cannot be written because the
@ -307,7 +309,7 @@ int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t* uart);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_UART_WriteCharacterRaw (mxc_uart_regs_t* uart, uint8_t character); int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character);
/** /**
* @brief Reads the next available character * @brief Reads the next available character
@ -316,7 +318,7 @@ int MXC_UART_WriteCharacterRaw (mxc_uart_regs_t* uart, uint8_t character);
* *
* @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_UART_ReadCharacter(mxc_uart_regs_t* uart); int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart);
/** /**
* @brief Writes a character on the UART * @brief Writes a character on the UART
@ -326,7 +328,7 @@ int MXC_UART_ReadCharacter(mxc_uart_regs_t* uart);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_UART_WriteCharacter(mxc_uart_regs_t* uart, uint8_t character); int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character);
/** /**
* @brief Reads the next available character * @brief Reads the next available character
@ -339,7 +341,7 @@ int MXC_UART_WriteCharacter(mxc_uart_regs_t* uart, uint8_t character);
* *
* @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_UART_Read(mxc_uart_regs_t* uart, uint8_t* buffer, int* len); int MXC_UART_Read(mxc_uart_regs_t *uart, uint8_t *buffer, int *len);
/** /**
* @brief Writes a byte on the UART * @brief Writes a byte on the UART
@ -350,7 +352,7 @@ int MXC_UART_Read(mxc_uart_regs_t* uart, uint8_t* buffer, int* len);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_UART_Write(mxc_uart_regs_t* uart, const uint8_t* byte, int* len); int MXC_UART_Write(mxc_uart_regs_t *uart, const uint8_t *byte, int *len);
/** /**
* @brief Unloads bytes from the receive FIFO. * @brief Unloads bytes from the receive FIFO.
@ -361,8 +363,7 @@ int MXC_UART_Write(mxc_uart_regs_t* uart, const uint8_t* byte, int* len);
* *
* @return The number of bytes actually read. * @return The number of bytes actually read.
*/ */
unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t* uart, unsigned char* bytes, unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len);
unsigned int len);
/** /**
* @brief Unloads bytes from the receive FIFO user DMA for longer reads. * @brief Unloads bytes from the receive FIFO user DMA for longer reads.
@ -374,8 +375,8 @@ unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t* uart, unsigned char* bytes,
* *
* @return See \ref MXC_ERROR_CODES for a list of return values * @return See \ref MXC_ERROR_CODES for a list of return values
*/ */
int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t* uart, unsigned char* bytes, int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len,
unsigned int len, mxc_uart_dma_complete_cb_t callback); mxc_uart_dma_complete_cb_t callback);
/** /**
* @brief Get the number of bytes currently available in the receive FIFO. * @brief Get the number of bytes currently available in the receive FIFO.
@ -384,7 +385,7 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t* uart, unsigned char* bytes,
* *
* @return The number of bytes available. * @return The number of bytes available.
*/ */
unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t* uart); unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart);
/** /**
* @brief Loads bytes into the transmit FIFO. * @brief Loads bytes into the transmit FIFO.
@ -395,8 +396,8 @@ unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t* uart);
* *
* @return The number of bytes actually written. * @return The number of bytes actually written.
*/ */
unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t* uart, const unsigned char* bytes, unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, const unsigned char *bytes,
unsigned int len); unsigned int len);
/** /**
* @brief Loads bytes into the transmit FIFO using DMA for longer writes * @brief Loads bytes into the transmit FIFO using DMA for longer writes
@ -408,8 +409,8 @@ unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t* uart, const unsigned char* by
* *
* @return See \ref MXC_ERROR_CODES for a list of return values * @return See \ref MXC_ERROR_CODES for a list of return values
*/ */
int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t* uart, const unsigned char* bytes, int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, unsigned int len,
unsigned int len, mxc_uart_dma_complete_cb_t callback); mxc_uart_dma_complete_cb_t callback);
/** /**
* @brief Get the amount of free space available in the transmit FIFO. * @brief Get the amount of free space available in the transmit FIFO.
@ -418,7 +419,7 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t* uart, const unsigned char* bytes,
* *
* @return The number of bytes available. * @return The number of bytes available.
*/ */
unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t* uart); unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart);
/** /**
* @brief Removes and discards all bytes currently in the receive FIFO. * @brief Removes and discards all bytes currently in the receive FIFO.
@ -427,7 +428,7 @@ unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t* uart);
* *
* @return See \ref MXC_Error_Codes for the list of error return codes. * @return See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_UART_ClearRXFIFO(mxc_uart_regs_t* uart); int MXC_UART_ClearRXFIFO(mxc_uart_regs_t *uart);
/** /**
* @brief Removes and discards all bytes currently in the transmit FIFO. * @brief Removes and discards all bytes currently in the transmit FIFO.
@ -436,7 +437,7 @@ int MXC_UART_ClearRXFIFO(mxc_uart_regs_t* uart);
* *
* @return See \ref MXC_Error_Codes for the list of error return codes. * @return See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_UART_ClearTXFIFO(mxc_uart_regs_t* uart); int MXC_UART_ClearTXFIFO(mxc_uart_regs_t *uart);
/** /**
* @brief Set the receive threshold level. * @brief Set the receive threshold level.
@ -455,7 +456,7 @@ int MXC_UART_ClearTXFIFO(mxc_uart_regs_t* uart);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_UART_SetRXThreshold(mxc_uart_regs_t* uart, unsigned int numBytes); int MXC_UART_SetRXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes);
/** /**
* @brief Get the current receive threshold level. * @brief Get the current receive threshold level.
@ -464,7 +465,7 @@ int MXC_UART_SetRXThreshold(mxc_uart_regs_t* uart, unsigned int numBytes);
* *
* @return The receive threshold value (in bytes). * @return The receive threshold value (in bytes).
*/ */
unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t* uart); unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t *uart);
/** /**
* @brief Set the transmit threshold level. * @brief Set the transmit threshold level.
@ -483,7 +484,7 @@ unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t* uart);
* *
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/ */
int MXC_UART_SetTXThreshold(mxc_uart_regs_t* uart, unsigned int numBytes); int MXC_UART_SetTXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes);
/** /**
* @brief Get the current transmit threshold level. * @brief Get the current transmit threshold level.
@ -492,7 +493,7 @@ int MXC_UART_SetTXThreshold(mxc_uart_regs_t* uart, unsigned int numBytes);
* *
* @return The transmit threshold value (in bytes). * @return The transmit threshold value (in bytes).
*/ */
unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t* uart); unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart);
/** /**
* @brief Gets the interrupt flags that are currently set * @brief Gets the interrupt flags that are currently set
@ -504,7 +505,7 @@ unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t* uart);
* *
* @return The interrupt flags * @return The interrupt flags
*/ */
unsigned int MXC_UART_GetFlags(mxc_uart_regs_t* uart); unsigned int MXC_UART_GetFlags(mxc_uart_regs_t *uart);
/** /**
* @brief Clears the interrupt flags that are currently set * @brief Clears the interrupt flags that are currently set
@ -517,7 +518,7 @@ unsigned int MXC_UART_GetFlags(mxc_uart_regs_t* uart);
* *
* @return See \ref MXC_Error_Codes for the list of error return codes. * @return See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_UART_ClearFlags(mxc_uart_regs_t* uart, unsigned int flags); int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags);
/** /**
* @brief Enables specific interrupts * @brief Enables specific interrupts
@ -530,7 +531,7 @@ int MXC_UART_ClearFlags(mxc_uart_regs_t* uart, unsigned int flags);
* *
* @return See \ref MXC_Error_Codes for the list of error return codes. * @return See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_UART_EnableInt(mxc_uart_regs_t* uart, unsigned int mask); int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int mask);
/** /**
* @brief Disables specific interrupts * @brief Disables specific interrupts
@ -543,7 +544,7 @@ int MXC_UART_EnableInt(mxc_uart_regs_t* uart, unsigned int mask);
* *
* @return See \ref MXC_Error_Codes for the list of error return codes. * @return See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_UART_DisableInt(mxc_uart_regs_t* uart, unsigned int mask); int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int mask);
/** /**
* @brief Gets the status flags that are currently set * @brief Gets the status flags that are currently set
@ -552,7 +553,7 @@ int MXC_UART_DisableInt(mxc_uart_regs_t* uart, unsigned int mask);
* *
* @return The status flags * @return The status flags
*/ */
unsigned int MXC_UART_GetStatus(mxc_uart_regs_t* uart); unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart);
/* ************************************************************************* */ /* ************************************************************************* */
/* Transaction level functions */ /* Transaction level functions */
@ -569,7 +570,7 @@ unsigned int MXC_UART_GetStatus(mxc_uart_regs_t* uart);
* *
* @return See \ref MXC_Error_Codes for the list of error return codes. * @return See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_UART_Transaction(mxc_uart_req_t* req); int MXC_UART_Transaction(mxc_uart_req_t *req);
/** /**
* @brief Setup an interrupt-driven UART transaction * @brief Setup an interrupt-driven UART transaction
@ -581,7 +582,7 @@ int MXC_UART_Transaction(mxc_uart_req_t* req);
* *
* @return See \ref MXC_Error_Codes for the list of error return codes. * @return See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_UART_TransactionAsync(mxc_uart_req_t* req); int MXC_UART_TransactionAsync(mxc_uart_req_t *req);
/** /**
* @brief Setup a DMA driven UART transaction * @brief Setup a DMA driven UART transaction
@ -596,7 +597,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t* req);
* *
* @return See \ref MXC_Error_Codes for the list of error return codes. * @return See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_UART_TransactionDMA(mxc_uart_req_t* req); int MXC_UART_TransactionDMA(mxc_uart_req_t *req);
/** /**
* @brief The processing function for DMA transactions. * @brief The processing function for DMA transactions.
@ -607,7 +608,7 @@ int MXC_UART_TransactionDMA(mxc_uart_req_t* req);
* @param ch DMA channel * @param ch DMA channel
* @param error Error status * @param error Error status
*/ */
void MXC_UART_DMACallback (int ch, int error); void MXC_UART_DMACallback(int ch, int error);
/** /**
* @brief Async callback * @brief Async callback
@ -617,7 +618,7 @@ void MXC_UART_DMACallback (int ch, int error);
* *
* @return See \ref MXC_Error_Codes for the list of error return codes. * @return See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_UART_AsyncCallback (mxc_uart_regs_t* uart, int retVal); int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal);
/** /**
* @brief stop any async callbacks * @brief stop any async callbacks
@ -626,7 +627,7 @@ int MXC_UART_AsyncCallback (mxc_uart_regs_t* uart, int retVal);
* *
* @return See \ref MXC_Error_Codes for the list of error return codes. * @return See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_UART_AsyncStop (mxc_uart_regs_t* uart); int MXC_UART_AsyncStop(mxc_uart_regs_t *uart);
/** /**
* @brief Abort any asynchronous requests in progress. * @brief Abort any asynchronous requests in progress.
@ -639,7 +640,7 @@ int MXC_UART_AsyncStop (mxc_uart_regs_t* uart);
* *
* @return See \ref MXC_Error_Codes for the list of error return codes. * @return See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_UART_AbortAsync(mxc_uart_regs_t* uart); int MXC_UART_AbortAsync(mxc_uart_regs_t *uart);
/** /**
* @brief The processing function for asynchronous transactions. * @brief The processing function for asynchronous transactions.
@ -652,7 +653,7 @@ int MXC_UART_AbortAsync(mxc_uart_regs_t* uart);
* *
* @return See \ref MXC_Error_Codes for the list of error return codes. * @return See \ref MXC_Error_Codes for the list of error return codes.
*/ */
int MXC_UART_AsyncHandler(mxc_uart_regs_t* uart); int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart);
/** /**
* @brief Provide TXCount for asynchronous transactions.. * @brief Provide TXCount for asynchronous transactions..
@ -661,7 +662,7 @@ int MXC_UART_AsyncHandler(mxc_uart_regs_t* uart);
* *
* @return Returns transmit bytes (in FIFO). * @return Returns transmit bytes (in FIFO).
*/ */
uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t* req); uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req);
/** /**
* @brief Provide RXCount for asynchronous transactions.. * @brief Provide RXCount for asynchronous transactions..
@ -670,7 +671,7 @@ uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t* req);
* *
* @return Returns receive bytes (in FIFO). * @return Returns receive bytes (in FIFO).
*/ */
uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t* req); uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t *req);
/**@} end of group uart */ /**@} end of group uart */
@ -678,4 +679,4 @@ uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t* req);
} }
#endif #endif
#endif /* _MXC_UART_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_UART_H_

56
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/wdt.h
View File

@ -3,8 +3,8 @@
* @brief Watchdog timer (WDT) function prototypes and data types. * @brief Watchdog timer (WDT) function prototypes and data types.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,15 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
/* Define to prevent redundant inclusion */ /* Define to prevent redundant inclusion */
#ifndef _WDT_H_ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_WDT_H_
#define _WDT_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_WDT_H_
#ifdef __CC_ARM
#pragma diag_suppress 66 // enumeration value is out of "int" range
#endif
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -110,11 +106,11 @@ typedef enum {
* @brief Timer Configuration * @brief Timer Configuration
*/ */
typedef struct { typedef struct {
mxc_wdt_mode_t mode; ///< WDT mode mxc_wdt_mode_t mode; ///< WDT mode
mxc_wdt_period_t upperResetPeriod; ///< Reset upper limit mxc_wdt_period_t upperResetPeriod; ///< Reset upper limit
mxc_wdt_period_t lowerResetPeriod; ///< Reset lower limit mxc_wdt_period_t lowerResetPeriod; ///< Reset lower limit
mxc_wdt_period_t upperIntPeriod; ///< Interrupt upper limit mxc_wdt_period_t upperIntPeriod; ///< Interrupt upper limit
mxc_wdt_period_t lowerIntPeriod; ///< Interrupt lower limit mxc_wdt_period_t lowerIntPeriod; ///< Interrupt lower limit
} mxc_wdt_cfg_t; } mxc_wdt_cfg_t;
/* **** Function Prototypes **** */ /* **** Function Prototypes **** */
@ -124,96 +120,96 @@ typedef struct {
* @param cfg watchdog configuration * @param cfg watchdog configuration
* @return See \ref MXC_Error_Codes for the list of error codes. * @return See \ref MXC_Error_Codes for the list of error codes.
*/ */
int MXC_WDT_Init (mxc_wdt_regs_t* wdt, mxc_wdt_cfg_t *cfg); int MXC_WDT_Init(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg);
/** /**
* @brief Shutdown the Watchdog Timer * @brief Shutdown the Watchdog Timer
* @param wdt Pointer to the watchdog registers * @param wdt Pointer to the watchdog registers
* @return See \ref MXC_Error_Codes for the list of error codes. * @return See \ref MXC_Error_Codes for the list of error codes.
*/ */
int MXC_WDT_Shutdown (mxc_wdt_regs_t* wdt); int MXC_WDT_Shutdown(mxc_wdt_regs_t *wdt);
/** /**
* @brief Set the period of the watchdog interrupt. * @brief Set the period of the watchdog interrupt.
* @param wdt Pointer to watchdog registers. * @param wdt Pointer to watchdog registers.
* @param cfg watchdog configuration. * @param cfg watchdog configuration.
*/ */
void MXC_WDT_SetIntPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_cfg_t *cfg); void MXC_WDT_SetIntPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg);
/** /**
* @brief Set the period of the watchdog reset. * @brief Set the period of the watchdog reset.
* @param wdt Pointer to watchdog registers. * @param wdt Pointer to watchdog registers.
* @param cfg watchdog configuration. * @param cfg watchdog configuration.
*/ */
void MXC_WDT_SetResetPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_cfg_t *cfg); void MXC_WDT_SetResetPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg);
/** /**
* @brief Enable the watchdog timer. * @brief Enable the watchdog timer.
* @param wdt Pointer to watchdog registers. * @param wdt Pointer to watchdog registers.
*/ */
void MXC_WDT_Enable (mxc_wdt_regs_t* wdt); void MXC_WDT_Enable(mxc_wdt_regs_t *wdt);
/** /**
* @brief Disable the watchdog timer. * @brief Disable the watchdog timer.
* @param wdt Pointer to watchdog registers. * @param wdt Pointer to watchdog registers.
*/ */
void MXC_WDT_Disable (mxc_wdt_regs_t* wdt); void MXC_WDT_Disable(mxc_wdt_regs_t *wdt);
/** /**
* @brief Enable the watchdog interrupt. * @brief Enable the watchdog interrupt.
* @param wdt Pointer to watchdog registers. * @param wdt Pointer to watchdog registers.
*/ */
void MXC_WDT_EnableInt (mxc_wdt_regs_t* wdt); void MXC_WDT_EnableInt(mxc_wdt_regs_t *wdt);
/** /**
* @brief Disable the watchdog interrupt. * @brief Disable the watchdog interrupt.
* @param wdt Pointer to watchdog registers. * @param wdt Pointer to watchdog registers.
*/ */
void MXC_WDT_DisableInt (mxc_wdt_regs_t* wdt); void MXC_WDT_DisableInt(mxc_wdt_regs_t *wdt);
/** /**
* @brief Enable the watchdog reset. * @brief Enable the watchdog reset.
* @param wdt Pointer to watchdog registers. * @param wdt Pointer to watchdog registers.
*/ */
void MXC_WDT_EnableReset (mxc_wdt_regs_t* wdt); void MXC_WDT_EnableReset(mxc_wdt_regs_t *wdt);
/** /**
* @brief Disable the watchdog reset. * @brief Disable the watchdog reset.
* @param wdt Pointer to watchdog registers. * @param wdt Pointer to watchdog registers.
*/ */
void MXC_WDT_DisableReset (mxc_wdt_regs_t* wdt); void MXC_WDT_DisableReset(mxc_wdt_regs_t *wdt);
/** /**
* @brief Reset the watchdog timer. * @brief Reset the watchdog timer.
* @param wdt Pointer to watchdog registers. * @param wdt Pointer to watchdog registers.
*/ */
void MXC_WDT_ResetTimer (mxc_wdt_regs_t* wdt); void MXC_WDT_ResetTimer(mxc_wdt_regs_t *wdt);
/** /**
* @brief Get the status of the reset flag. * @brief Get the status of the reset flag.
* @param wdt Pointer to watchdog registers. * @param wdt Pointer to watchdog registers.
* @returns 1 if the previous reset was caused by the watchdog, 0 otherwise. * @returns 1 if the previous reset was caused by the watchdog, 0 otherwise.
*/ */
int MXC_WDT_GetResetFlag (mxc_wdt_regs_t* wdt); int MXC_WDT_GetResetFlag(mxc_wdt_regs_t *wdt);
/** /**
* @brief Clears the reset flag. * @brief Clears the reset flag.
* @param wdt Pointer to watchdog registers. * @param wdt Pointer to watchdog registers.
*/ */
void MXC_WDT_ClearResetFlag (mxc_wdt_regs_t* wdt); void MXC_WDT_ClearResetFlag(mxc_wdt_regs_t *wdt);
/** /**
* @brief Get the status of the interrupt flag. * @brief Get the status of the interrupt flag.
* @param wdt Pointer to watchdog registers. * @param wdt Pointer to watchdog registers.
* @returns 1 if the interrupt is pending, 0 otherwise. * @returns 1 if the interrupt is pending, 0 otherwise.
*/ */
int MXC_WDT_GetIntFlag (mxc_wdt_regs_t* wdt); int MXC_WDT_GetIntFlag(mxc_wdt_regs_t *wdt);
/** /**
* @brief Clears the interrupt flag. * @brief Clears the interrupt flag.
* @param wdt Pointer to watchdog registers. * @param wdt Pointer to watchdog registers.
*/ */
void MXC_WDT_ClearIntFlag (mxc_wdt_regs_t* wdt); void MXC_WDT_ClearIntFlag(mxc_wdt_regs_t *wdt);
/**@} end of group wdt */ /**@} end of group wdt */
@ -221,4 +217,4 @@ void MXC_WDT_ClearIntFlag (mxc_wdt_regs_t* wdt);
} }
#endif #endif
#endif /* _WDT_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_WDT_H_

120
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_key_revb_regs.h
View File

@ -1,120 +0,0 @@
/**
* @file aes_key_revb_regs.h
* @brief Registers, Bit Masks and Bit Positions for the AES_KEY_REVB Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _AES_KEY_REVB_REGS_H_
#define _AES_KEY_REVB_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup aes_key_revb
* @defgroup aes_key_revb_registers AES_KEY_REVB_Registers
* @brief Registers, Bit Masks and Bit Positions for the AES_KEY_REVB Peripheral Module.
* @details AES Key Registers.
*/
/**
* @ingroup aes_key_revb_registers
* Structure type to access the AES_KEY_REVB Registers.
*/
typedef struct {
__IO uint32_t aes_key0; /**< <tt>\b 0x00:</tt> AES_KEY_REVB AES_KEY0 Register */
__IO uint32_t aes_key1; /**< <tt>\b 0x04:</tt> AES_KEY_REVB AES_KEY1 Register */
__IO uint32_t aes_key2; /**< <tt>\b 0x08:</tt> AES_KEY_REVB AES_KEY2 Register */
__IO uint32_t aes_key3; /**< <tt>\b 0x0C:</tt> AES_KEY_REVB AES_KEY3 Register */
__IO uint32_t aes_key4; /**< <tt>\b 0x10:</tt> AES_KEY_REVB AES_KEY4 Register */
__IO uint32_t aes_key5; /**< <tt>\b 0x14:</tt> AES_KEY_REVB AES_KEY5 Register */
__IO uint32_t aes_key6; /**< <tt>\b 0x18:</tt> AES_KEY_REVB AES_KEY6 Register */
__IO uint32_t aes_key7; /**< <tt>\b 0x1C:</tt> AES_KEY_REVB AES_KEY7 Register */
} mxc_aes_key_revb_regs_t;
/* Register offsets for module AES_KEY_REVB */
/**
* @ingroup aes_key_revb_registers
* @defgroup AES_KEY_REVB_Register_Offsets Register Offsets
* @brief AES_KEY_REVB Peripheral Register Offsets from the AES_KEY_REVB Base Peripheral Address.
* @{
*/
#define MXC_R_AES_KEY_REVB_AES_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x0000</tt> */
#define MXC_R_AES_KEY_REVB_AES_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x0004</tt> */
#define MXC_R_AES_KEY_REVB_AES_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x0008</tt> */
#define MXC_R_AES_KEY_REVB_AES_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x000C</tt> */
#define MXC_R_AES_KEY_REVB_AES_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x0010</tt> */
#define MXC_R_AES_KEY_REVB_AES_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x0014</tt> */
#define MXC_R_AES_KEY_REVB_AES_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x0018</tt> */
#define MXC_R_AES_KEY_REVB_AES_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x001C</tt> */
/**@} end of group aes_key_revb_registers */
#ifdef __cplusplus
}
#endif
#endif /* _AES_KEY_REVB_REGS_H_ */

138
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_me15.c
View File

@ -3,8 +3,8 @@
* @brief Trust Protection Unit driver. * @brief Trust Protection Unit driver.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,7 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
#include "mxc_device.h" #include "mxc_device.h"
#include "mxc_errors.h" #include "mxc_errors.h"
@ -47,15 +47,14 @@
#define KEY_ADDR 0x10802008 #define KEY_ADDR 0x10802008
#define FMV_ADDR 0x10802000 #define FMV_ADDR 0x10802000
static const uint32_t fmv[2] = {0x2B86D479, 0x2B86D479}; static const uint32_t fmv[2] = { 0x2B86D479, 0x2B86D479 };
static void reverse_key(const void* key, uint8_t* keyr, int len) static void reverse_key(const void *key, uint8_t *keyr, int len)
{ {
int i; int i;
uint8_t tmp; uint8_t tmp;
uint8_t* k = (uint8_t*)key; uint8_t *k = (uint8_t *)key;
for(i = 0; i < len; i++) for (i = 0; i < len; i++) {
{
tmp = k[i]; tmp = k[i];
k[i] = keyr[len - i - 1]; k[i] = keyr[len - i - 1];
keyr[len - i - 1] = tmp; keyr[len - i - 1] = tmp;
@ -75,29 +74,29 @@ int MXC_AES_Init(void)
// Start with a randomly generated key. // Start with a randomly generated key.
MXC_AES_GenerateKey(); MXC_AES_GenerateKey();
MXC_AES_RevB_Init((mxc_aes_revb_regs_t*) MXC_AES); MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES);
return E_NO_ERROR; return E_NO_ERROR;
} }
void MXC_AES_EnableInt (uint32_t interrupt) void MXC_AES_EnableInt(uint32_t interrupt)
{ {
MXC_AES_RevB_EnableInt((mxc_aes_revb_regs_t*) MXC_AES, interrupt); MXC_AES_RevB_EnableInt((mxc_aes_revb_regs_t *)MXC_AES, interrupt);
} }
void MXC_AES_DisableInt (uint32_t interrupt) void MXC_AES_DisableInt(uint32_t interrupt)
{ {
MXC_AES_RevB_DisableInt((mxc_aes_revb_regs_t*) MXC_AES, interrupt); MXC_AES_RevB_DisableInt((mxc_aes_revb_regs_t *)MXC_AES, interrupt);
} }
int MXC_AES_IsBusy(void) int MXC_AES_IsBusy(void)
{ {
return MXC_AES_RevB_IsBusy((mxc_aes_revb_regs_t*) MXC_AES); return MXC_AES_RevB_IsBusy((mxc_aes_revb_regs_t *)MXC_AES);
} }
int MXC_AES_Shutdown (void) int MXC_AES_Shutdown(void)
{ {
int error = MXC_AES_RevB_Shutdown ((mxc_aes_revb_regs_t*) MXC_AES); int error = MXC_AES_RevB_Shutdown((mxc_aes_revb_regs_t *)MXC_AES);
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_AES); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_AES);
@ -117,85 +116,86 @@ void MXC_AES_GenerateKey(void)
void MXC_AES_SetKeySize(mxc_aes_keys_t key) void MXC_AES_SetKeySize(mxc_aes_keys_t key)
{ {
MXC_AES_RevB_SetKeySize((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_keys_t) key); MXC_AES_RevB_SetKeySize((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_keys_t)key);
} }
mxc_aes_keys_t MXC_AES_GetKeySize(void) mxc_aes_keys_t MXC_AES_GetKeySize(void)
{ {
return MXC_AES_RevB_GetKeySize((mxc_aes_revb_regs_t*) MXC_AES); return MXC_AES_RevB_GetKeySize((mxc_aes_revb_regs_t *)MXC_AES);
} }
void MXC_AES_FlushInputFIFO(void) void MXC_AES_FlushInputFIFO(void)
{ {
MXC_AES_RevB_FlushInputFIFO((mxc_aes_revb_regs_t*) MXC_AES); MXC_AES_RevB_FlushInputFIFO((mxc_aes_revb_regs_t *)MXC_AES);
} }
void MXC_AES_FlushOutputFIFO(void) void MXC_AES_FlushOutputFIFO(void)
{ {
MXC_AES_RevB_FlushOutputFIFO((mxc_aes_revb_regs_t*) MXC_AES); MXC_AES_RevB_FlushOutputFIFO((mxc_aes_revb_regs_t *)MXC_AES);
} }
void MXC_AES_Start(void) void MXC_AES_Start(void)
{ {
MXC_AES_RevB_Start((mxc_aes_revb_regs_t*) MXC_AES); MXC_AES_RevB_Start((mxc_aes_revb_regs_t *)MXC_AES);
} }
uint32_t MXC_AES_GetFlags(void) uint32_t MXC_AES_GetFlags(void)
{ {
return MXC_AES_RevB_GetFlags((mxc_aes_revb_regs_t*) MXC_AES); return MXC_AES_RevB_GetFlags((mxc_aes_revb_regs_t *)MXC_AES);
} }
void MXC_AES_ClearFlags(uint32_t flags) void MXC_AES_ClearFlags(uint32_t flags)
{ {
MXC_AES_RevB_ClearFlags((mxc_aes_revb_regs_t*) MXC_AES, flags); MXC_AES_RevB_ClearFlags((mxc_aes_revb_regs_t *)MXC_AES, flags);
} }
int MXC_AES_Generic(mxc_aes_req_t* req) int MXC_AES_Generic(mxc_aes_req_t *req)
{ {
return MXC_AES_RevB_Generic((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req); return MXC_AES_RevB_Generic((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req);
} }
int MXC_AES_Encrypt(mxc_aes_req_t* req) int MXC_AES_Encrypt(mxc_aes_req_t *req)
{ {
return MXC_AES_RevB_Encrypt((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req); return MXC_AES_RevB_Encrypt((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req);
} }
int MXC_AES_Decrypt(mxc_aes_req_t* req) int MXC_AES_Decrypt(mxc_aes_req_t *req)
{ {
return MXC_AES_RevB_Decrypt((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req); return MXC_AES_RevB_Decrypt((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req);
} }
int MXC_AES_TXDMAConfig(void* src_addr, int len) int MXC_AES_TXDMAConfig(void *src_addr, int len)
{ {
return MXC_AES_RevB_TXDMAConfig(src_addr, len); return MXC_AES_RevB_TXDMAConfig(src_addr, len);
} }
int MXC_AES_RXDMAConfig(void* dest_addr, int len) int MXC_AES_RXDMAConfig(void *dest_addr, int len)
{ {
return MXC_AES_RevB_RXDMAConfig(dest_addr, len); return MXC_AES_RevB_RXDMAConfig(dest_addr, len);
} }
int MXC_AES_GenericAsync(mxc_aes_req_t* req, uint8_t enc) int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc)
{ {
return MXC_AES_RevB_GenericAsync((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req, enc); return MXC_AES_RevB_GenericAsync((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req,
enc);
} }
int MXC_AES_EncryptAsync(mxc_aes_req_t* req) int MXC_AES_EncryptAsync(mxc_aes_req_t *req)
{ {
return MXC_AES_RevB_EncryptAsync((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req); return MXC_AES_RevB_EncryptAsync((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req);
} }
int MXC_AES_DecryptAsync(mxc_aes_req_t* req) int MXC_AES_DecryptAsync(mxc_aes_req_t *req)
{ {
return MXC_AES_RevB_DecryptAsync((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req); return MXC_AES_RevB_DecryptAsync((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req);
} }
void MXC_AES_SetExtKey(const void* key, mxc_aes_keys_t len) void MXC_AES_SetExtKey(const void *key, mxc_aes_keys_t len)
{ {
MXC_AES_RevB_SetExtKey((mxc_aes_key_revb_regs_t*) MXC_AESKEY, key, len); MXC_AES_RevB_SetExtKey((mxc_aeskeys_revb_regs_t *)MXC_AESKEYS, key, len);
} }
int MXC_AES_SetPORKey(const void* key, mxc_aes_keys_t len) int MXC_AES_SetPORKey(const void *key, mxc_aes_keys_t len)
{ {
int err = E_BAD_PARAM; int err = E_BAD_PARAM;
uint8_t keyr[32]; uint8_t keyr[32];
@ -204,23 +204,22 @@ int MXC_AES_SetPORKey(const void* key, mxc_aes_keys_t len)
MXC_FLC_UnlockInfoBlock(KEY_ADDR); MXC_FLC_UnlockInfoBlock(KEY_ADDR);
// Write the key // Write the key
switch(len) switch (len) {
{ case MXC_AES_128BITS:
case MXC_AES_128BITS: reverse_key(key, keyr, 16);
reverse_key(key, keyr, 16); err = MXC_FLC_Write(KEY_ADDR, 16, (uint32_t *)keyr);
err = MXC_FLC_Write(KEY_ADDR, 16, (uint32_t*)keyr); break;
break; case MXC_AES_192BITS:
case MXC_AES_192BITS: reverse_key(key, keyr, 24);
reverse_key(key, keyr, 24); err = MXC_FLC_Write(KEY_ADDR, 24, (uint32_t *)keyr);
err = MXC_FLC_Write(KEY_ADDR, 24, (uint32_t*)keyr); break;
break; case MXC_AES_256BITS:
case MXC_AES_256BITS: reverse_key(key, keyr, 32);
reverse_key(key, keyr, 32); err = MXC_FLC_Write(KEY_ADDR, 32, (uint32_t *)keyr);
err = MXC_FLC_Write(KEY_ADDR, 32, (uint32_t*)keyr); break;
break;
} }
if(err == E_NO_ERROR) { if (err == E_NO_ERROR) {
// Write the magic value to activate the key // Write the magic value to activate the key
err = MXC_FLC_Write(FMV_ADDR, sizeof(fmv), (uint32_t *)fmv); err = MXC_FLC_Write(FMV_ADDR, sizeof(fmv), (uint32_t *)fmv);
@ -246,10 +245,10 @@ int MXC_AES_ClearPORKey()
MXC_FLC_UnlockInfoBlock(FMV_ADDR); MXC_FLC_UnlockInfoBlock(FMV_ADDR);
// Copy the current memory contents // Copy the current memory contents
memcpy(page, (uint8_t*)FMV_ADDR + 40, MXC_FLASH_PAGE_SIZE - 40); memcpy(page, (uint8_t *)FMV_ADDR + 40, MXC_FLASH_PAGE_SIZE - 40);
err = MXC_FLC_PageErase(FMV_ADDR); err = MXC_FLC_PageErase(FMV_ADDR);
if(err != E_NO_ERROR) { if (err != E_NO_ERROR) {
// Couldn't erase the memory. Abort. // Couldn't erase the memory. Abort.
// Lock the key region from reads/writes // Lock the key region from reads/writes
MXC_FLC_LockInfoBlock(FMV_ADDR); MXC_FLC_LockInfoBlock(FMV_ADDR);
@ -257,7 +256,7 @@ int MXC_AES_ClearPORKey()
} }
// Write the old contents (minus the fmv and key) back to the part // Write the old contents (minus the fmv and key) back to the part
err = MXC_FLC_Write(FMV_ADDR + 40, MXC_FLASH_PAGE_SIZE - 40, (uint32_t*)page); err = MXC_FLC_Write(FMV_ADDR + 40, MXC_FLASH_PAGE_SIZE - 40, (uint32_t *)page);
// Lock the key region from reads/writes // Lock the key region from reads/writes
MXC_FLC_LockInfoBlock(FMV_ADDR); MXC_FLC_LockInfoBlock(FMV_ADDR);
@ -271,17 +270,16 @@ void MXC_AES_CopyPORKeyToKeyRegisters(mxc_aes_keys_t len)
MXC_FLC_UnlockInfoBlock(KEY_ADDR); MXC_FLC_UnlockInfoBlock(KEY_ADDR);
// Copy the values to the key register // Copy the values to the key register
switch(len) switch (len) {
{ case MXC_AES_128BITS:
case MXC_AES_128BITS: memcpy(MXC_AESKEYS, (uint8_t *)KEY_ADDR, 16);
memcpy(MXC_AESKEY, (uint8_t*)KEY_ADDR, 16); break;
break; case MXC_AES_192BITS:
case MXC_AES_192BITS: memcpy(MXC_AESKEYS, (uint8_t *)KEY_ADDR, 24);
memcpy(MXC_AESKEY, (uint8_t*)KEY_ADDR, 24); break;
break; case MXC_AES_256BITS:
case MXC_AES_256BITS: memcpy(MXC_AESKEYS, (uint8_t *)KEY_ADDR, 32);
memcpy(MXC_AESKEY, (uint8_t*)KEY_ADDR, 32); break;
break;
} }
// Lock the key region from reads/writes // Lock the key region from reads/writes
@ -296,7 +294,7 @@ int MXC_AES_HasPORKey()
MXC_FLC_UnlockInfoBlock(FMV_ADDR); MXC_FLC_UnlockInfoBlock(FMV_ADDR);
// Look for the magic value. // Look for the magic value.
res = memcmp((uint8_t*)FMV_ADDR, (uint8_t*)fmv, 8); res = memcmp((uint8_t *)FMV_ADDR, (uint8_t *)fmv, 8);
// Lock the key region from reads/writes // Lock the key region from reads/writes
MXC_FLC_LockInfoBlock(FMV_ADDR); MXC_FLC_LockInfoBlock(FMV_ADDR);

275
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb.c
View File

@ -1,5 +1,5 @@
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -29,10 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
#ifdef __CC_ARM // Keil
#pragma diag_suppress 188 // enumerated type mixed with another type
#endif
#include <stdlib.h> #include <stdlib.h>
#include <string.h> #include <string.h>
@ -44,7 +41,7 @@
#include "dma.h" #include "dma.h"
#include "aes_regs.h" #include "aes_regs.h"
#include "aes_key_regs.h" #include "aeskeys_regs.h"
#include "aes_revb.h" #include "aes_revb.h"
#include "trng_revb.h" #include "trng_revb.h"
@ -54,203 +51,205 @@ typedef struct {
uint8_t channelRX; uint8_t channelRX;
uint8_t channelTX; uint8_t channelTX;
uint32_t remain; uint32_t remain;
uint32_t* inputText; uint32_t *inputText;
uint32_t* outputText; uint32_t *outputText;
} mxc_aes_revb_dma_req_t; } mxc_aes_revb_dma_req_t;
static mxc_aes_revb_dma_req_t dma_state; static mxc_aes_revb_dma_req_t dma_state;
#define SWAP_BYTES(x) ((((x) >> 24) & 0x000000FF) | (((x) >> 8) & 0x0000FF00) | (((x) << 8) & 0x00FF0000) | (((x) << 24) & 0xFF000000)) #define SWAP_BYTES(x) \
((((x) >> 24) & 0x000000FF) | (((x) >> 8) & 0x0000FF00) | (((x) << 8) & 0x00FF0000) | \
(((x) << 24) & 0xFF000000))
static void memcpy32r(uint32_t * dst, const uint32_t * src, unsigned int len) /* Prevent GCC from optimimzing this function to memcpy */
static void __attribute__((optimize("no-tree-loop-distribute-patterns")))
memcpy32r(uint32_t *dst, const uint32_t *src, unsigned int len)
{ {
uint32_t * dstr = dst + (len/4) - 1; uint32_t *dstr = dst + (len / 4) - 1;
while (len) { while (len) {
*dstr = SWAP_BYTES(*src); *dstr = SWAP_BYTES(*src);
dstr--; dstr--;
src++; src++;
len -= 4; len -= 4;
} }
} }
int MXC_AES_RevB_Init(mxc_aes_revb_regs_t* aes) int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes)
{ {
aes->ctrl = 0x00; aes->ctrl = 0x00;
while (MXC_AES_RevB_IsBusy(aes) != E_NO_ERROR); while (MXC_AES_RevB_IsBusy(aes) != E_NO_ERROR) {}
aes->ctrl |= MXC_F_AES_REVB_CTRL_EN; aes->ctrl |= MXC_F_AES_REVB_CTRL_EN;
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_AES_RevB_Shutdown (mxc_aes_revb_regs_t* aes) int MXC_AES_RevB_Shutdown(mxc_aes_revb_regs_t *aes)
{ {
MXC_AES_RevB_FlushInputFIFO(aes); MXC_AES_RevB_FlushInputFIFO(aes);
MXC_AES_RevB_FlushOutputFIFO(aes); MXC_AES_RevB_FlushOutputFIFO(aes);
while(MXC_AES_RevB_IsBusy(aes) != E_NO_ERROR) ; while (MXC_AES_RevB_IsBusy(aes) != E_NO_ERROR) {}
aes->ctrl = 0x00; aes->ctrl = 0x00;
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_AES_RevB_IsBusy (mxc_aes_revb_regs_t* aes) int MXC_AES_RevB_IsBusy(mxc_aes_revb_regs_t *aes)
{ {
if(aes->status & MXC_F_AES_REVB_STATUS_BUSY) if (aes->status & MXC_F_AES_REVB_STATUS_BUSY) {
{
return E_BUSY; return E_BUSY;
} }
return E_NO_ERROR; return E_NO_ERROR;
} }
void MXC_AES_RevB_SetKeySize(mxc_aes_revb_regs_t* aes, mxc_aes_revb_keys_t key) void MXC_AES_RevB_SetKeySize(mxc_aes_revb_regs_t *aes, mxc_aes_revb_keys_t key)
{ {
while(MXC_AES_IsBusy() != E_NO_ERROR); while (MXC_AES_IsBusy() != E_NO_ERROR) {}
aes->ctrl |= key; aes->ctrl |= key;
} }
mxc_aes_keys_t MXC_AES_RevB_GetKeySize(mxc_aes_revb_regs_t* aes) mxc_aes_keys_t MXC_AES_RevB_GetKeySize(mxc_aes_revb_regs_t *aes)
{ {
return (aes->ctrl & MXC_F_AES_REVB_CTRL_KEY_SIZE); return (aes->ctrl & MXC_F_AES_REVB_CTRL_KEY_SIZE);
} }
void MXC_AES_RevB_FlushInputFIFO(mxc_aes_revb_regs_t* aes) void MXC_AES_RevB_FlushInputFIFO(mxc_aes_revb_regs_t *aes)
{ {
while(MXC_AES_IsBusy() != E_NO_ERROR); while (MXC_AES_IsBusy() != E_NO_ERROR) {}
aes->ctrl |= MXC_F_AES_REVB_CTRL_INPUT_FLUSH; aes->ctrl |= MXC_F_AES_REVB_CTRL_INPUT_FLUSH;
} }
void MXC_AES_RevB_FlushOutputFIFO(mxc_aes_revb_regs_t* aes) void MXC_AES_RevB_FlushOutputFIFO(mxc_aes_revb_regs_t *aes)
{ {
while(MXC_AES_IsBusy() != E_NO_ERROR); while (MXC_AES_IsBusy() != E_NO_ERROR) {}
aes->ctrl |= MXC_F_AES_REVB_CTRL_OUTPUT_FLUSH; aes->ctrl |= MXC_F_AES_REVB_CTRL_OUTPUT_FLUSH;
} }
void MXC_AES_RevB_Start(mxc_aes_revb_regs_t* aes) void MXC_AES_RevB_Start(mxc_aes_revb_regs_t *aes)
{ {
while(MXC_AES_IsBusy() != E_NO_ERROR); while (MXC_AES_IsBusy() != E_NO_ERROR) {}
aes->ctrl |= MXC_F_AES_REVB_CTRL_START; aes->ctrl |= MXC_F_AES_REVB_CTRL_START;
} }
void MXC_AES_RevB_EnableInt (mxc_aes_revb_regs_t* aes, uint32_t interrupt) void MXC_AES_RevB_EnableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt)
{ {
aes->inten |= (interrupt & (MXC_F_AES_REVB_INTEN_DONE | MXC_F_AES_REVB_INTEN_KEY_CHANGE | \ aes->inten |= (interrupt & (MXC_F_AES_REVB_INTEN_DONE | MXC_F_AES_REVB_INTEN_KEY_CHANGE |
MXC_F_AES_REVB_INTEN_KEY_ZERO | MXC_F_AES_REVB_INTEN_OV)); MXC_F_AES_REVB_INTEN_KEY_ZERO | MXC_F_AES_REVB_INTEN_OV));
} }
void MXC_AES_RevB_DisableInt (mxc_aes_revb_regs_t* aes, uint32_t interrupt) void MXC_AES_RevB_DisableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt)
{ {
aes->inten &= ~(interrupt & (MXC_F_AES_REVB_INTEN_DONE | MXC_F_AES_REVB_INTEN_KEY_CHANGE | \ aes->inten &= ~(interrupt & (MXC_F_AES_REVB_INTEN_DONE | MXC_F_AES_REVB_INTEN_KEY_CHANGE |
MXC_F_AES_REVB_INTEN_KEY_ZERO | MXC_F_AES_REVB_INTEN_OV)); MXC_F_AES_REVB_INTEN_KEY_ZERO | MXC_F_AES_REVB_INTEN_OV));
} }
uint32_t MXC_AES_RevB_GetFlags(mxc_aes_revb_regs_t* aes) uint32_t MXC_AES_RevB_GetFlags(mxc_aes_revb_regs_t *aes)
{ {
return aes->intfl; return aes->intfl;
} }
void MXC_AES_RevB_ClearFlags(mxc_aes_revb_regs_t* aes, uint32_t flags) void MXC_AES_RevB_ClearFlags(mxc_aes_revb_regs_t *aes, uint32_t flags)
{ {
aes->intfl = (flags & (MXC_F_AES_REVB_INTFL_DONE | MXC_F_AES_REVB_INTFL_KEY_CHANGE | \ aes->intfl = (flags & (MXC_F_AES_REVB_INTFL_DONE | MXC_F_AES_REVB_INTFL_KEY_CHANGE |
MXC_F_AES_REVB_INTFL_KEY_ZERO | MXC_F_AES_REVB_INTFL_OV)); MXC_F_AES_REVB_INTFL_KEY_ZERO | MXC_F_AES_REVB_INTFL_OV));
} }
int MXC_AES_RevB_Generic(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req) int MXC_AES_RevB_Generic(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req)
{ {
int i; int i;
int remain; int remain;
if(req == NULL) { if (req == NULL) {
return E_NULL_PTR; return E_NULL_PTR;
} }
if(req->inputData == NULL || req->resultData == NULL) { if (req->inputData == NULL || req->resultData == NULL) {
return E_NULL_PTR; return E_NULL_PTR;
} }
if(req->length == 0) { if (req->length == 0) {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
remain = req->length; remain = req->length;
MXC_AES_RevB_FlushInputFIFO(aes); MXC_AES_RevB_FlushInputFIFO(aes);
MXC_AES_RevB_FlushOutputFIFO(aes); MXC_AES_RevB_FlushOutputFIFO(aes);
MXC_AES_RevB_SetKeySize(aes, req->keySize); MXC_AES_RevB_SetKeySize(aes, req->keySize);
while(MXC_AES_IsBusy() != E_NO_ERROR); while (MXC_AES_IsBusy() != E_NO_ERROR) {}
MXC_SETFIELD (aes->ctrl, MXC_F_AES_REVB_CTRL_TYPE, req->encryption << MXC_F_AES_REVB_CTRL_TYPE_POS); MXC_SETFIELD(aes->ctrl, MXC_F_AES_REVB_CTRL_TYPE,
req->encryption << MXC_F_AES_REVB_CTRL_TYPE_POS);
while(remain/4) while (remain / 4) {
{ for (i = 0; i < 4; i++) {
for(i = 0; i < 4; i++) { aes->fifo = SWAP_BYTES(req->inputData[3 - i]);
aes->fifo = SWAP_BYTES(req->inputData[3-i]);
} }
req->inputData += 4; req->inputData += 4;
while(!(aes->intfl & MXC_F_AES_REVB_INTFL_DONE)); while (!(aes->intfl & MXC_F_AES_REVB_INTFL_DONE)) {}
aes->intfl |= MXC_F_AES_REVB_INTFL_DONE; aes->intfl |= MXC_F_AES_REVB_INTFL_DONE;
for(i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
uint32_t tmp = aes->fifo; uint32_t tmp = aes->fifo;
req->resultData[3-i] = SWAP_BYTES(tmp); req->resultData[3 - i] = SWAP_BYTES(tmp);
} }
req->resultData += 4; req->resultData += 4;
remain -= 4; remain -= 4;
} }
if(remain%4) if (remain % 4) {
{ for (i = 0; i < remain; i++) {
for(i = 0; i < remain; i++) { aes->fifo = SWAP_BYTES(req->inputData[remain - 1 - i]);
aes->fifo = SWAP_BYTES(req->inputData[remain-1-i]);
} }
req->inputData += remain; req->inputData += remain;
// Pad last block with 0's // Pad last block with 0's
for(i = remain; i < 4; i++) { for (i = remain; i < 4; i++) {
aes->fifo = 0; aes->fifo = 0;
} }
while(!(aes->intfl & MXC_F_AES_REVB_INTFL_DONE)); while (!(aes->intfl & MXC_F_AES_REVB_INTFL_DONE)) {}
aes->intfl |= MXC_F_AES_REVB_INTFL_DONE; aes->intfl |= MXC_F_AES_REVB_INTFL_DONE;
for(i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
uint32_t tmp = aes->fifo; uint32_t tmp = aes->fifo;
req->resultData[3-i] = SWAP_BYTES(tmp); req->resultData[3 - i] = SWAP_BYTES(tmp);
} }
req->resultData += 4; req->resultData += 4;
} }
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_AES_RevB_Encrypt(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req) int MXC_AES_RevB_Encrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req)
{ {
return MXC_AES_RevB_Generic(aes, req); return MXC_AES_RevB_Generic(aes, req);
} }
int MXC_AES_RevB_Decrypt(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req) int MXC_AES_RevB_Decrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req)
{ {
return MXC_AES_RevB_Generic(aes, req); return MXC_AES_RevB_Generic(aes, req);
} }
int MXC_AES_RevB_TXDMAConfig(void* src_addr, int len) int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len)
{ {
uint8_t channel; uint8_t channel;
mxc_dma_config_t config; mxc_dma_config_t config;
mxc_dma_srcdst_t srcdst; mxc_dma_srcdst_t srcdst;
if (src_addr == NULL) { if (src_addr == NULL) {
return E_NULL_PTR; return E_NULL_PTR;
} }
if (len == 0) { if (len == 0) {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
MXC_DMA_Init(); MXC_DMA_Init();
@ -271,35 +270,33 @@ int MXC_AES_RevB_TXDMAConfig(void* src_addr, int len)
srcdst.ch = channel; srcdst.ch = channel;
srcdst.source = src_addr; srcdst.source = src_addr;
if(dma_state.enc == 1) { if (dma_state.enc == 1) {
srcdst.len = 4; srcdst.len = 4;
} } else if (len > 4) {
else if(len > 4) {
srcdst.len = 4; srcdst.len = 4;
} } else {
else{
srcdst.len = len; srcdst.len = len;
} }
MXC_DMA_ConfigChannel (config, srcdst); MXC_DMA_ConfigChannel(config, srcdst);
MXC_DMA_SetCallback (channel, MXC_AES_RevB_DMACallback); MXC_DMA_SetCallback(channel, MXC_AES_RevB_DMACallback);
MXC_DMA_EnableInt (channel); MXC_DMA_EnableInt(channel);
MXC_DMA_Start (channel); MXC_DMA_Start(channel);
//MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE;
MXC_DMA_SetChannelInterruptEn(channel, 0, 1); MXC_DMA_SetChannelInterruptEn(channel, 0, 1);
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_AES_RevB_RXDMAConfig(void* dest_addr, int len) int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len)
{ {
if (dest_addr == NULL) { if (dest_addr == NULL) {
return E_NULL_PTR; return E_NULL_PTR;
} }
if (len == 0) { if (len == 0) {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
uint8_t channel; uint8_t channel;
@ -324,113 +321,109 @@ int MXC_AES_RevB_RXDMAConfig(void* dest_addr, int len)
srcdst.ch = channel; srcdst.ch = channel;
srcdst.dest = dest_addr; srcdst.dest = dest_addr;
if(dma_state.enc == 0) { if (dma_state.enc == 0) {
srcdst.len = 4; srcdst.len = 4;
} } else if (len > 4) {
else if(len > 4) {
srcdst.len = 4; srcdst.len = 4;
} } else {
else{
srcdst.len = len; srcdst.len = len;
} }
MXC_DMA_ConfigChannel (config, srcdst); MXC_DMA_ConfigChannel(config, srcdst);
MXC_DMA_SetCallback (channel, MXC_AES_RevB_DMACallback); MXC_DMA_SetCallback(channel, MXC_AES_RevB_DMACallback);
MXC_DMA_EnableInt (channel); MXC_DMA_EnableInt(channel);
MXC_DMA_Start (channel); MXC_DMA_Start(channel);
//MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE;
MXC_DMA_SetChannelInterruptEn(channel, 0, 1); MXC_DMA_SetChannelInterruptEn(channel, 0, 1);
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req, uint8_t enc) int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req, uint8_t enc)
{ {
if(req == NULL) { if (req == NULL) {
return E_NULL_PTR; return E_NULL_PTR;
} }
if(req->inputData == NULL || req->resultData == NULL) { if (req->inputData == NULL || req->resultData == NULL) {
return E_NULL_PTR; return E_NULL_PTR;
} }
if(req->length == 0) { if (req->length == 0) {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
MXC_AES_RevB_FlushInputFIFO(aes); MXC_AES_RevB_FlushInputFIFO(aes);
MXC_AES_RevB_FlushOutputFIFO(aes); MXC_AES_RevB_FlushOutputFIFO(aes);
MXC_AES_RevB_SetKeySize(aes, req->keySize); MXC_AES_RevB_SetKeySize(aes, req->keySize);
MXC_AES_IsBusy(); MXC_AES_IsBusy();
MXC_SETFIELD (aes->ctrl, MXC_F_AES_REVB_CTRL_TYPE, req->encryption << MXC_F_AES_REVB_CTRL_TYPE_POS); MXC_SETFIELD(aes->ctrl, MXC_F_AES_REVB_CTRL_TYPE,
req->encryption << MXC_F_AES_REVB_CTRL_TYPE_POS);
dma_state.enc = enc; dma_state.enc = enc;
dma_state.remain = req->length; dma_state.remain = req->length;
dma_state.inputText = req->inputData; dma_state.inputText = req->inputData;
dma_state.outputText = req->resultData; dma_state.outputText = req->resultData;
aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_RX_EN; //Enable AES DMA aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_RX_EN; //Enable AES DMA
aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_TX_EN; //Enable AES DMA aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_TX_EN; //Enable AES DMA
if(MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain) != E_NO_ERROR) { if (MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain) != E_NO_ERROR) {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_AES_RevB_EncryptAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req) int MXC_AES_RevB_EncryptAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req)
{ {
return MXC_AES_RevB_GenericAsync(aes, req, 0); return MXC_AES_RevB_GenericAsync(aes, req, 0);
} }
int MXC_AES_RevB_DecryptAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req) int MXC_AES_RevB_DecryptAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req)
{ {
return MXC_AES_RevB_GenericAsync(aes, req, 1); return MXC_AES_RevB_GenericAsync(aes, req, 1);
} }
void MXC_AES_RevB_DMACallback(int ch, int error) void MXC_AES_RevB_DMACallback(int ch, int error)
{ {
if(error != E_NO_ERROR) { if (error != E_NO_ERROR) {
} else {
} if (dma_state.channelTX == ch) {
else { MXC_DMA_ReleaseChannel(dma_state.channelTX);
if (dma_state.channelTX == ch) { if (dma_state.remain < 4) {
MXC_DMA_ReleaseChannel(dma_state.channelTX); MXC_AES_Start();
if (dma_state.remain < 4) { }
MXC_AES_Start(); MXC_AES_RevB_RXDMAConfig(dma_state.outputText, dma_state.remain);
} else if (dma_state.channelRX == ch) {
if (dma_state.remain > 4) {
dma_state.remain -= 4;
} else if (dma_state.remain > 0) {
dma_state.remain = 0;
}
MXC_DMA_ReleaseChannel(dma_state.channelRX);
if (dma_state.remain > 0) {
MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain);
}
} }
MXC_AES_RevB_RXDMAConfig(dma_state.outputText, dma_state.remain);
}
else if (dma_state.channelRX == ch) {
if (dma_state.remain > 4) {
dma_state.remain -= 4;
} else if (dma_state.remain > 0) {
dma_state.remain = 0;
}
MXC_DMA_ReleaseChannel(dma_state.channelRX);
if (dma_state.remain > 0) {
MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain);
}
}
} }
} }
void MXC_AES_RevB_SetExtKey(mxc_aes_key_revb_regs_t* aeskey, const void* key, mxc_aes_keys_t len) void MXC_AES_RevB_SetExtKey(mxc_aeskeys_revb_regs_t *aeskeys, const void *key, mxc_aes_keys_t len)
{ {
int numBytes; int numBytes;
if(len == MXC_AES_128BITS) { if (len == MXC_AES_128BITS) {
numBytes = 16; numBytes = 16;
} else if (len == MXC_AES_192BITS) { } else if (len == MXC_AES_192BITS) {
numBytes = 24; numBytes = 24;
} else { } else {
numBytes = 32; numBytes = 32;
} }
/* TODO: Figure out if this is the correct byte ordering */ /* TODO: Figure out if this is the correct byte ordering */
memcpy32r((void*)&(aeskey->aes_key0), key, numBytes); memcpy32r((void *)&(aeskeys->key0), key, numBytes);
} }

80
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb.h
View File

@ -1,5 +1,5 @@
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -29,12 +29,15 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_AES_AES_REVB_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_AES_AES_REVB_H_
#include <stdint.h> #include <stdint.h>
#include "mxc_aes.h" #include "mxc_aes.h"
#include "aes_revb_regs.h" #include "aes_revb_regs.h"
#include "aes_key_revb_regs.h" #include "aeskeys_revb_regs.h"
#include "trng_revb_regs.h" #include "trng_revb_regs.h"
/** /**
@ -42,9 +45,9 @@
* *
*/ */
typedef enum { typedef enum {
MXC_AES_REVB_128BITS = MXC_S_AES_REVB_CTRL_KEY_SIZE_AES128, ///< Select AES-128 bit key MXC_AES_REVB_128BITS = MXC_S_AES_REVB_CTRL_KEY_SIZE_AES128, ///< Select AES-128 bit key
MXC_AES_REVB_192BITS = MXC_S_AES_REVB_CTRL_KEY_SIZE_AES192, ///< Select AES-192 bit key MXC_AES_REVB_192BITS = MXC_S_AES_REVB_CTRL_KEY_SIZE_AES192, ///< Select AES-192 bit key
MXC_AES_REVB_256BITS = MXC_S_AES_REVB_CTRL_KEY_SIZE_AES256, ///< Select AES-256 bit key MXC_AES_REVB_256BITS = MXC_S_AES_REVB_CTRL_KEY_SIZE_AES256, ///< Select AES-256 bit key
} mxc_aes_revb_keys_t; } mxc_aes_revb_keys_t;
/** /**
@ -52,9 +55,9 @@ typedef enum {
* *
*/ */
typedef enum { typedef enum {
MXC_AES_REVB_ENCRYPT_EXT_KEY = 0, ///< Encryption using External key MXC_AES_REVB_ENCRYPT_EXT_KEY = 0, ///< Encryption using External key
MXC_AES_REVB_DECRYPT_EXT_KEY = 1, ///< Encryption using internal key MXC_AES_REVB_DECRYPT_EXT_KEY = 1, ///< Encryption using internal key
MXC_AES_REVB_DECRYPT_INT_KEY = 2 ///< Decryption using internal key MXC_AES_REVB_DECRYPT_INT_KEY = 2 ///< Decryption using internal key
} mxc_aes_revb_enc_type_t; } mxc_aes_revb_enc_type_t;
/** /**
@ -62,35 +65,36 @@ typedef enum {
* *
*/ */
typedef struct _mxc_aes_revb_cipher_req_t { typedef struct _mxc_aes_revb_cipher_req_t {
uint32_t length; ///< Length of the data uint32_t length; ///< Length of the data
uint32_t *inputData; ///< Pointer to input data uint32_t *inputData; ///< Pointer to input data
uint32_t *resultData; ///< Pointer to encrypted data uint32_t *resultData; ///< Pointer to encrypted data
mxc_aes_revb_keys_t keySize; ///< Size of AES key mxc_aes_revb_keys_t keySize; ///< Size of AES key
mxc_aes_revb_enc_type_t encryption; ///< Encrytion type or \ref mxc_aes_enc_type_t mxc_aes_revb_enc_type_t encryption; ///< Encrytion type or \ref mxc_aes_enc_type_t
mxc_aes_complete_t callback; ///< Callback function mxc_aes_complete_t callback; ///< Callback function
} mxc_aes_revb_req_t; } mxc_aes_revb_req_t;
int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes);
int MXC_AES_RevB_Init (mxc_aes_revb_regs_t* aes); void MXC_AES_RevB_EnableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt);
void MXC_AES_RevB_EnableInt (mxc_aes_revb_regs_t* aes, uint32_t interrupt); void MXC_AES_RevB_DisableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt);
void MXC_AES_RevB_DisableInt (mxc_aes_revb_regs_t* aes, uint32_t interrupt); int MXC_AES_RevB_IsBusy(mxc_aes_revb_regs_t *aes);
int MXC_AES_RevB_IsBusy (mxc_aes_revb_regs_t* aes); int MXC_AES_RevB_Shutdown(mxc_aes_revb_regs_t *aes);
int MXC_AES_RevB_Shutdown (mxc_aes_revb_regs_t* aes); void MXC_AES_RevB_GenerateKey(mxc_trng_revb_regs_t *trng);
void MXC_AES_RevB_GenerateKey(mxc_trng_revb_regs_t* trng); void MXC_AES_RevB_SetKeySize(mxc_aes_revb_regs_t *aes, mxc_aes_revb_keys_t key);
void MXC_AES_RevB_SetKeySize(mxc_aes_revb_regs_t* aes, mxc_aes_revb_keys_t key); mxc_aes_keys_t MXC_AES_RevB_GetKeySize(mxc_aes_revb_regs_t *aes);
mxc_aes_keys_t MXC_AES_RevB_GetKeySize(mxc_aes_revb_regs_t* aes); void MXC_AES_RevB_FlushInputFIFO(mxc_aes_revb_regs_t *aes);
void MXC_AES_RevB_FlushInputFIFO(mxc_aes_revb_regs_t* aes); void MXC_AES_RevB_FlushOutputFIFO(mxc_aes_revb_regs_t *aes);
void MXC_AES_RevB_FlushOutputFIFO(mxc_aes_revb_regs_t* aes); void MXC_AES_RevB_Start(mxc_aes_revb_regs_t *aes);
void MXC_AES_RevB_Start(mxc_aes_revb_regs_t* aes); uint32_t MXC_AES_RevB_GetFlags(mxc_aes_revb_regs_t *aes);
uint32_t MXC_AES_RevB_GetFlags(mxc_aes_revb_regs_t* aes); void MXC_AES_RevB_ClearFlags(mxc_aes_revb_regs_t *aes, uint32_t flags);
void MXC_AES_RevB_ClearFlags(mxc_aes_revb_regs_t* aes, uint32_t flags); int MXC_AES_RevB_Generic(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req);
int MXC_AES_RevB_Generic(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req); int MXC_AES_RevB_Encrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req);
int MXC_AES_RevB_Encrypt(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req); int MXC_AES_RevB_Decrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req);
int MXC_AES_RevB_Decrypt(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req);
int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len); int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len);
int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len); int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len);
int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req, uint8_t enc); int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req, uint8_t enc);
int MXC_AES_RevB_EncryptAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req); int MXC_AES_RevB_EncryptAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req);
int MXC_AES_RevB_DecryptAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req); int MXC_AES_RevB_DecryptAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req);
void MXC_AES_RevB_DMACallback (int ch, int error); void MXC_AES_RevB_DMACallback(int ch, int error);
void MXC_AES_RevB_SetExtKey(mxc_aes_key_revb_regs_t* aeskey, const void* key, mxc_aes_keys_t len); void MXC_AES_RevB_SetExtKey(mxc_aeskeys_revb_regs_t *aeskey, const void *key, mxc_aes_keys_t len);
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_AES_AES_REVB_H_

10
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb_regs.h
View File

@ -3,8 +3,8 @@
* @brief Registers, Bit Masks and Bit Positions for the AES_REVB Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the AES_REVB Peripheral Module.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _AES_REVB_REGS_H_ #ifndef _AES_REVB_REGS_H_
#define _AES_REVB_REGS_H_ #define _AES_REVB_REGS_H_
@ -67,9 +66,6 @@ extern "C" {
#ifndef __O #ifndef __O
#define __O volatile #define __O volatile
#endif #endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond /// @endcond
/* **** Definitions **** */ /* **** Definitions **** */

117
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aeskeys_revb_regs.h Normal file
View File

@ -0,0 +1,117 @@
/**
* @file aeskeys_revb_regs.h
* @brief Registers, Bit Masks and Bit Positions for the AESKEYS_REVB Peripheral Module.
* @note This file is @generated.
*/
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_AESKEYS_AESKEYS_REVB_REGS_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_AESKEYS_AESKEYS_REVB_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup aeskeys_revb
* @defgroup aeskeys_revb_registers AESKEYS_REVB_Registers
* @brief Registers, Bit Masks and Bit Positions for the AESKEYS_REVB Peripheral Module.
* @details AES Key Registers.
*/
/**
* @ingroup aeskeys_revb_registers
* Structure type to access the AESKEYS_REVB Registers.
*/
typedef struct {
__IO uint32_t key0; /**< <tt>\b 0x00:</tt> AESKEYS_REVB KEY0 Register */
__IO uint32_t key1; /**< <tt>\b 0x04:</tt> AESKEYS_REVB KEY1 Register */
__IO uint32_t key2; /**< <tt>\b 0x08:</tt> AESKEYS_REVB KEY2 Register */
__IO uint32_t key3; /**< <tt>\b 0x0C:</tt> AESKEYS_REVB KEY3 Register */
__IO uint32_t key4; /**< <tt>\b 0x10:</tt> AESKEYS_REVB KEY4 Register */
__IO uint32_t key5; /**< <tt>\b 0x14:</tt> AESKEYS_REVB KEY5 Register */
__IO uint32_t key6; /**< <tt>\b 0x18:</tt> AESKEYS_REVB KEY6 Register */
__IO uint32_t key7; /**< <tt>\b 0x1C:</tt> AESKEYS_REVB KEY7 Register */
} mxc_aeskeys_revb_regs_t;
/* Register offsets for module AESKEYS_REVB */
/**
* @ingroup aeskeys_revb_registers
* @defgroup AESKEYS_REVB_Register_Offsets Register Offsets
* @brief AESKEYS_REVB Peripheral Register Offsets from the AESKEYS_REVB Base Peripheral Address.
* @{
*/
#define MXC_R_AESKEYS_REVB_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AESKEYS_REVB Base Address: <tt> 0x0000</tt> */
#define MXC_R_AESKEYS_REVB_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AESKEYS_REVB Base Address: <tt> 0x0004</tt> */
#define MXC_R_AESKEYS_REVB_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AESKEYS_REVB Base Address: <tt> 0x0008</tt> */
#define MXC_R_AESKEYS_REVB_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AESKEYS_REVB Base Address: <tt> 0x000C</tt> */
#define MXC_R_AESKEYS_REVB_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AESKEYS_REVB Base Address: <tt> 0x0010</tt> */
#define MXC_R_AESKEYS_REVB_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AESKEYS_REVB Base Address: <tt> 0x0014</tt> */
#define MXC_R_AESKEYS_REVB_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AESKEYS_REVB Base Address: <tt> 0x0018</tt> */
#define MXC_R_AESKEYS_REVB_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AESKEYS_REVB Base Address: <tt> 0x001C</tt> */
/**@} end of group aeskeys_revb_registers */
#ifdef __cplusplus
}
#endif
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_AESKEYS_AESKEYS_REVB_REGS_H_

35
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_me15.c
View File

@ -1,5 +1,5 @@
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
#include "mxc_device.h" #include "mxc_device.h"
#include "mxc_errors.h" #include "mxc_errors.h"
@ -39,7 +39,6 @@
#include "crc.h" #include "crc.h"
#include "crc_reva.h" #include "crc_reva.h"
/* ************************************************************************* */ /* ************************************************************************* */
/* Global Control/Configuration functions */ /* Global Control/Configuration functions */
/* ************************************************************************* */ /* ************************************************************************* */
@ -48,66 +47,66 @@ int MXC_CRC_Init(void)
{ {
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC);
MXC_CRC_RevA_Init((mxc_crc_reva_regs_t*) MXC_CRC); MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC);
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_CRC_Shutdown(void) int MXC_CRC_Shutdown(void)
{ {
int error = MXC_CRC_RevA_Shutdown((mxc_crc_reva_regs_t*) MXC_CRC); int error = MXC_CRC_RevA_Shutdown((mxc_crc_reva_regs_t *)MXC_CRC);
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_CRC); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_CRC);
return error; return error;
} }
void MXC_CRC_Handler (int ch, int error) void MXC_CRC_Handler(int ch, int error)
{ {
MXC_CRC_RevA_Handler(ch, error); MXC_CRC_RevA_Handler(ch, error);
} }
void MXC_CRC_SetDirection(mxc_crc_bitorder_t bitOrder) void MXC_CRC_SetDirection(mxc_crc_bitorder_t bitOrder)
{ {
MXC_CRC_RevA_SetDirection((mxc_crc_reva_regs_t*) MXC_CRC, (mxc_crc_reva_bitorder_t) bitOrder); MXC_CRC_RevA_SetDirection((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_bitorder_t)bitOrder);
} }
mxc_crc_bitorder_t MXC_CRC_GetDirection(void) mxc_crc_bitorder_t MXC_CRC_GetDirection(void)
{ {
return MXC_CRC_RevA_GetDirection((mxc_crc_reva_regs_t*) MXC_CRC); return MXC_CRC_RevA_GetDirection((mxc_crc_reva_regs_t *)MXC_CRC);
} }
void MXC_CRC_SwapDataIn(mxc_crc_bitorder_t bitOrder) void MXC_CRC_SwapDataIn(mxc_crc_bitorder_t bitOrder)
{ {
MXC_CRC_RevA_SwapDataIn((mxc_crc_reva_regs_t*) MXC_CRC, (mxc_crc_reva_bitorder_t) bitOrder); MXC_CRC_RevA_SwapDataIn((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_bitorder_t)bitOrder);
} }
void MXC_CRC_SwapDataOut(mxc_crc_bitorder_t bitOrder) void MXC_CRC_SwapDataOut(mxc_crc_bitorder_t bitOrder)
{ {
MXC_CRC_RevA_SwapDataOut((mxc_crc_reva_regs_t*) MXC_CRC, (mxc_crc_reva_bitorder_t) bitOrder); MXC_CRC_RevA_SwapDataOut((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_bitorder_t)bitOrder);
} }
void MXC_CRC_SetPoly(uint32_t poly) void MXC_CRC_SetPoly(uint32_t poly)
{ {
MXC_CRC_RevA_SetPoly((mxc_crc_reva_regs_t*) MXC_CRC, poly); MXC_CRC_RevA_SetPoly((mxc_crc_reva_regs_t *)MXC_CRC, poly);
} }
uint32_t MXC_CRC_GetPoly(void) uint32_t MXC_CRC_GetPoly(void)
{ {
return MXC_CRC_RevA_GetPoly((mxc_crc_reva_regs_t*) MXC_CRC); return MXC_CRC_RevA_GetPoly((mxc_crc_reva_regs_t *)MXC_CRC);
} }
uint32_t MXC_CRC_GetResult(void) uint32_t MXC_CRC_GetResult(void)
{ {
return MXC_CRC_RevA_GetResult((mxc_crc_reva_regs_t*) MXC_CRC); return MXC_CRC_RevA_GetResult((mxc_crc_reva_regs_t *)MXC_CRC);
} }
int MXC_CRC_Compute(mxc_crc_req_t* req) int MXC_CRC_Compute(mxc_crc_req_t *req)
{ {
return MXC_CRC_RevA_Compute((mxc_crc_reva_regs_t*) MXC_CRC, (mxc_crc_reva_req_t*) req); return MXC_CRC_RevA_Compute((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_req_t *)req);
} }
int MXC_CRC_ComputeAsync(mxc_crc_req_t* req) int MXC_CRC_ComputeAsync(mxc_crc_req_t *req)
{ {
return MXC_CRC_RevA_ComputeAsync((mxc_crc_reva_regs_t*) MXC_CRC, (mxc_crc_reva_req_t*) req); return MXC_CRC_RevA_ComputeAsync((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_req_t *)req);
} }

70
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva.c
View File

@ -1,8 +1,8 @@
/* **************************************************************************** /******************************************************************************
* Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files(the "Software"), * copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation * to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense, * the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the * and/or sell copies of the Software, and to permit persons to whom the
@ -29,11 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
#ifdef __CC_ARM
#pragma diag_suppress 188
#endif
#include <stdlib.h> #include <stdlib.h>
#include <string.h> #include <string.h>
@ -48,7 +44,6 @@
#include "crc_regs.h" #include "crc_regs.h"
#include "crc_reva.h" #include "crc_reva.h"
/***** Global Variables *****/ /***** Global Variables *****/
static mxc_crc_reva_req_t *CRCreq; static mxc_crc_reva_req_t *CRCreq;
@ -56,14 +51,14 @@ static mxc_crc_reva_req_t *CRCreq;
/* Global Control/Configuration functions */ /* Global Control/Configuration functions */
/* ************************************************************************* */ /* ************************************************************************* */
int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t* crc) int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc)
{ {
crc->ctrl = 0x00; crc->ctrl = 0x00;
crc->val = 0xFFFFFFFF; crc->val = 0xFFFFFFFF;
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_CRC_RevA_Shutdown(mxc_crc_reva_regs_t* crc) int MXC_CRC_RevA_Shutdown(mxc_crc_reva_regs_t *crc)
{ {
crc->ctrl &= ~MXC_F_CRC_REVA_CTRL_EN; crc->ctrl &= ~MXC_F_CRC_REVA_CTRL_EN;
return E_NO_ERROR; return E_NO_ERROR;
@ -71,7 +66,7 @@ int MXC_CRC_RevA_Shutdown(mxc_crc_reva_regs_t* crc)
int MXC_CRC_RevA_Handler(int ch, int error) int MXC_CRC_RevA_Handler(int ch, int error)
{ {
if(error == E_NO_ERROR) { if (error == E_NO_ERROR) {
CRCreq->resultCRC = MXC_CRC_GetResult(); CRCreq->resultCRC = MXC_CRC_GetResult();
} }
return error; return error;
@ -85,37 +80,39 @@ int MXC_CRC_RevA_Handler(int ch, int error)
/* Low Level Functions */ /* Low Level Functions */
/*******************************/ /*******************************/
void MXC_CRC_RevA_SetDirection(mxc_crc_reva_regs_t* crc, mxc_crc_reva_bitorder_t bitOrder) void MXC_CRC_RevA_SetDirection(mxc_crc_reva_regs_t *crc, mxc_crc_reva_bitorder_t bitOrder)
{ {
MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_MSB, bitOrder << MXC_F_CRC_REVA_CTRL_MSB_POS); MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_MSB, bitOrder << MXC_F_CRC_REVA_CTRL_MSB_POS);
} }
mxc_crc_bitorder_t MXC_CRC_RevA_GetDirection(mxc_crc_reva_regs_t* crc) mxc_crc_bitorder_t MXC_CRC_RevA_GetDirection(mxc_crc_reva_regs_t *crc)
{ {
return !!(crc->ctrl & MXC_F_CRC_REVA_CTRL_MSB); return !!(crc->ctrl & MXC_F_CRC_REVA_CTRL_MSB);
} }
void MXC_CRC_RevA_SwapDataIn(mxc_crc_reva_regs_t* crc, mxc_crc_reva_bitorder_t bitOrder) void MXC_CRC_RevA_SwapDataIn(mxc_crc_reva_regs_t *crc, mxc_crc_reva_bitorder_t bitOrder)
{ {
MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_BYTE_SWAP_IN, bitOrder << MXC_F_CRC_REVA_CTRL_BYTE_SWAP_IN_POS); MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_BYTE_SWAP_IN,
bitOrder << MXC_F_CRC_REVA_CTRL_BYTE_SWAP_IN_POS);
} }
void MXC_CRC_RevA_SwapDataOut(mxc_crc_reva_regs_t* crc, mxc_crc_reva_bitorder_t bitOrder) void MXC_CRC_RevA_SwapDataOut(mxc_crc_reva_regs_t *crc, mxc_crc_reva_bitorder_t bitOrder)
{ {
MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_BYTE_SWAP_OUT, bitOrder << MXC_F_CRC_REVA_CTRL_BYTE_SWAP_OUT_POS); MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_BYTE_SWAP_OUT,
bitOrder << MXC_F_CRC_REVA_CTRL_BYTE_SWAP_OUT_POS);
} }
void MXC_CRC_RevA_SetPoly(mxc_crc_reva_regs_t* crc, uint32_t poly) void MXC_CRC_RevA_SetPoly(mxc_crc_reva_regs_t *crc, uint32_t poly)
{ {
crc->poly = poly; crc->poly = poly;
} }
uint32_t MXC_CRC_RevA_GetPoly(mxc_crc_reva_regs_t* crc) uint32_t MXC_CRC_RevA_GetPoly(mxc_crc_reva_regs_t *crc)
{ {
return crc->poly; return crc->poly;
} }
uint32_t MXC_CRC_RevA_GetResult(mxc_crc_reva_regs_t* crc) uint32_t MXC_CRC_RevA_GetResult(mxc_crc_reva_regs_t *crc)
{ {
return crc->val; return crc->val;
} }
@ -124,20 +121,20 @@ uint32_t MXC_CRC_RevA_GetResult(mxc_crc_reva_regs_t* crc)
/* High Level Functions */ /* High Level Functions */
/*******************************/ /*******************************/
int MXC_CRC_RevA_Compute(mxc_crc_reva_regs_t* crc, mxc_crc_reva_req_t* req) int MXC_CRC_RevA_Compute(mxc_crc_reva_regs_t *crc, mxc_crc_reva_req_t *req)
{ {
int i = 0; int i = 0;
volatile int length; volatile int length;
if(req == NULL) { if (req == NULL) {
return E_NULL_PTR; return E_NULL_PTR;
} }
if(req->dataBuffer == NULL) { if (req->dataBuffer == NULL) {
return E_NULL_PTR; return E_NULL_PTR;
} }
if(req->dataLen == 0) { if (req->dataLen == 0) {
return E_INVALID; return E_INVALID;
} }
@ -145,10 +142,9 @@ int MXC_CRC_RevA_Compute(mxc_crc_reva_regs_t* crc, mxc_crc_reva_req_t* req)
length = req->dataLen; length = req->dataLen;
while(length--) while (length--) {
{
crc->datain32 = req->dataBuffer[i++]; crc->datain32 = req->dataBuffer[i++];
while(crc->ctrl & MXC_F_CRC_REVA_CTRL_BUSY); while (crc->ctrl & MXC_F_CRC_REVA_CTRL_BUSY) {}
} }
// Store the crc value // Store the crc value
@ -157,21 +153,21 @@ int MXC_CRC_RevA_Compute(mxc_crc_reva_regs_t* crc, mxc_crc_reva_req_t* req)
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t* crc, mxc_crc_reva_req_t* req) int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t *crc, mxc_crc_reva_req_t *req)
{ {
uint8_t channel; uint8_t channel;
mxc_dma_config_t config; mxc_dma_config_t config;
mxc_dma_srcdst_t srcdst; mxc_dma_srcdst_t srcdst;
if(req == NULL) { if (req == NULL) {
return E_NULL_PTR; return E_NULL_PTR;
} }
if(req->dataBuffer == NULL) { if (req->dataBuffer == NULL) {
return E_NULL_PTR; return E_NULL_PTR;
} }
if(req->dataLen == 0) { if (req->dataLen == 0) {
return E_INVALID; return E_INVALID;
} }
@ -192,14 +188,14 @@ int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t* crc, mxc_crc_reva_req_t* req)
config.dstinc_en = 0; config.dstinc_en = 0;
srcdst.ch = channel; srcdst.ch = channel;
srcdst.source = (uint8_t*) req->dataBuffer; //transfering bytes srcdst.source = (uint8_t *)req->dataBuffer; //transfering bytes
srcdst.len = req->dataLen * 4; //number of bytes srcdst.len = req->dataLen * 4; //number of bytes
MXC_CRC->ctrl |= MXC_F_CRC_CTRL_DMA_EN; MXC_CRC->ctrl |= MXC_F_CRC_CTRL_DMA_EN;
MXC_CRC->ctrl |= MXC_F_CRC_CTRL_EN; MXC_CRC->ctrl |= MXC_F_CRC_CTRL_EN;
MXC_DMA_ConfigChannel(config,srcdst); MXC_DMA_ConfigChannel(config, srcdst);
MXC_DMA_SetCallback(channel,(void *) MXC_CRC_Handler); MXC_DMA_SetCallback(channel, MXC_CRC_Handler);
MXC_DMA_EnableInt(channel); MXC_DMA_EnableInt(channel);
MXC_DMA_Start(channel); MXC_DMA_Start(channel);
//MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE;

48
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva.h
View File

@ -1,8 +1,8 @@
/* **************************************************************************** /******************************************************************************
* Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files(the "Software"), * copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation * to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense, * the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the * and/or sell copies of the Software, and to permit persons to whom the
@ -29,42 +29,42 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_CRC_CRC_REVA_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_CRC_CRC_REVA_H_
#include "crc.h" #include "crc.h"
#include "crc_reva_regs.h" #include "crc_reva_regs.h"
/***** CRC Definitions *****/ /***** CRC Definitions *****/
/** /**
* @brief Structure used to set up CRC request * @brief Structure used to set up CRC request
* *
*/ */
typedef struct _mxc_crc_reva_req_t { typedef struct _mxc_crc_reva_req_t {
uint32_t* dataBuffer; ///< Pointer to the data uint32_t *dataBuffer; ///< Pointer to the data
uint32_t dataLen; ///< Length of the data uint32_t dataLen; ///< Length of the data
uint32_t resultCRC; ///< Calculated CRC value uint32_t resultCRC; ///< Calculated CRC value
} mxc_crc_reva_req_t; } mxc_crc_reva_req_t;
/** /**
* @brief CRC data bit order * @brief CRC data bit order
* *
*/ */
typedef enum { typedef enum { CRC_REVA_LSB_FIRST, CRC_REVA_MSB_FIRST } mxc_crc_reva_bitorder_t;
CRC_REVA_LSB_FIRST,
CRC_REVA_MSB_FIRST
} mxc_crc_reva_bitorder_t;
int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc);
int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t* crc); int MXC_CRC_RevA_Shutdown(mxc_crc_reva_regs_t *crc);
int MXC_CRC_RevA_Shutdown(mxc_crc_reva_regs_t* crc);
int MXC_CRC_RevA_Handler(int ch, int error); int MXC_CRC_RevA_Handler(int ch, int error);
void MXC_CRC_RevA_SetDirection(mxc_crc_reva_regs_t* crc, mxc_crc_reva_bitorder_t bitOrder); void MXC_CRC_RevA_SetDirection(mxc_crc_reva_regs_t *crc, mxc_crc_reva_bitorder_t bitOrder);
mxc_crc_bitorder_t MXC_CRC_RevA_GetDirection(mxc_crc_reva_regs_t* crc); mxc_crc_bitorder_t MXC_CRC_RevA_GetDirection(mxc_crc_reva_regs_t *crc);
void MXC_CRC_RevA_SwapDataIn(mxc_crc_reva_regs_t* crc, mxc_crc_reva_bitorder_t bitOrder); void MXC_CRC_RevA_SwapDataIn(mxc_crc_reva_regs_t *crc, mxc_crc_reva_bitorder_t bitOrder);
void MXC_CRC_RevA_SwapDataOut(mxc_crc_reva_regs_t* crc, mxc_crc_reva_bitorder_t bitOrder); void MXC_CRC_RevA_SwapDataOut(mxc_crc_reva_regs_t *crc, mxc_crc_reva_bitorder_t bitOrder);
void MXC_CRC_RevA_SetPoly(mxc_crc_reva_regs_t* crc, uint32_t poly); void MXC_CRC_RevA_SetPoly(mxc_crc_reva_regs_t *crc, uint32_t poly);
uint32_t MXC_CRC_RevA_GetPoly(mxc_crc_reva_regs_t* crc); uint32_t MXC_CRC_RevA_GetPoly(mxc_crc_reva_regs_t *crc);
uint32_t MXC_CRC_RevA_GetResult(mxc_crc_reva_regs_t* crc); uint32_t MXC_CRC_RevA_GetResult(mxc_crc_reva_regs_t *crc);
int MXC_CRC_RevA_Compute(mxc_crc_reva_regs_t* crc, mxc_crc_reva_req_t* req); int MXC_CRC_RevA_Compute(mxc_crc_reva_regs_t *crc, mxc_crc_reva_req_t *req);
int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t* crc, mxc_crc_reva_req_t* req); int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t *crc, mxc_crc_reva_req_t *req);
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_CRC_CRC_REVA_H_

7
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva_regs.h
View File

@ -3,8 +3,8 @@
* @brief Registers, Bit Masks and Bit Positions for the CRC_REVA Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the CRC_REVA Peripheral Module.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _CRC_REVA_REGS_H_ #ifndef _CRC_REVA_REGS_H_
#define _CRC_REVA_REGS_H_ #define _CRC_REVA_REGS_H_

39
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_me15.c
View File

@ -1,5 +1,5 @@
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
/****** Includes *******/ /****** Includes *******/
#include <stddef.h> #include <stddef.h>
@ -45,17 +45,17 @@
int MXC_DMA_Init(void) int MXC_DMA_Init(void)
{ {
if(!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA)) { if (!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA)) {
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA);
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA); MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA);
} }
return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t*) MXC_DMA); return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t *)MXC_DMA);
} }
int MXC_DMA_AcquireChannel(void) int MXC_DMA_AcquireChannel(void)
{ {
return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t*) MXC_DMA); return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t *)MXC_DMA);
} }
int MXC_DMA_ReleaseChannel(int ch) int MXC_DMA_ReleaseChannel(int ch)
@ -78,7 +78,7 @@ int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst)
return MXC_DMA_RevA_SetSrcDst(srcdst); return MXC_DMA_RevA_SetSrcDst(srcdst);
} }
int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t* srcdst) int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst)
{ {
return MXC_DMA_RevA_GetSrcDst(srcdst); return MXC_DMA_RevA_GetSrcDst(srcdst);
} }
@ -100,7 +100,7 @@ int MXC_DMA_SetCallback(int ch, void (*callback)(int, int))
int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz) int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz)
{ {
return MXC_DMA_RevA_SetChannelInterruptEn(ch, chdis, ctz); return MXC_DMA_RevA_SetChannelInterruptEn(ch, chdis, ctz);
} }
int MXC_DMA_ChannelEnableInt(int ch, int flags) int MXC_DMA_ChannelEnableInt(int ch, int flags)
@ -125,12 +125,12 @@ int MXC_DMA_ChannelClearFlags(int ch, int flags)
int MXC_DMA_EnableInt(int ch) int MXC_DMA_EnableInt(int ch)
{ {
return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t*) MXC_DMA, ch); return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch);
} }
int MXC_DMA_DisableInt(int ch) int MXC_DMA_DisableInt(int ch)
{ {
return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t*) MXC_DMA, ch); return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch);
} }
int MXC_DMA_Start(int ch) int MXC_DMA_Start(int ch)
@ -143,22 +143,23 @@ int MXC_DMA_Stop(int ch)
return MXC_DMA_RevA_Stop(ch); return MXC_DMA_RevA_Stop(ch);
} }
mxc_dma_ch_regs_t* MXC_DMA_GetCHRegs(int ch) mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch)
{ {
return MXC_DMA_RevA_GetCHRegs(ch); return MXC_DMA_RevA_GetCHRegs(ch);
} }
void MXC_DMA_Handler(void) void MXC_DMA_Handler(void)
{ {
MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t*) MXC_DMA); MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t *)MXC_DMA);
} }
int MXC_DMA_MemCpy(void* dest, void* src, int len, mxc_dma_complete_cb_t callback) int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback)
{ {
return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t*) MXC_DMA, dest, src, len, callback); return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)MXC_DMA, dest, src, len, callback);
} }
int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback) int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst,
mxc_dma_trans_chain_t callback)
{ {
return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t*) MXC_DMA, config, firstSrcDst, callback); return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t *)MXC_DMA, config, firstSrcDst, callback);
} }

313
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva.c
View File

@ -1,8 +1,8 @@
/* **************************************************************************** /******************************************************************************
* Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files(the "Software"), * copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation * to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense, * the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the * and/or sell copies of the Software, and to permit persons to whom the
@ -29,10 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
#ifdef __CC_ARM // Keil
#pragma diag_suppress 68 // integer conversion resulted in a change of sign
#endif
/****** Includes *******/ /****** Includes *******/
#include <stddef.h> #include <stddef.h>
@ -46,28 +43,26 @@
#include "dma_reva_regs.h" #include "dma_reva_regs.h"
/***** Definitions *****/ /***** Definitions *****/
#define CHECK_HANDLE(x)((x >= 0) && (x < MXC_DMA_CHANNELS) && (dma_resource[x].valid)) #define CHECK_HANDLE(x) ((x >= 0) && (x < MXC_DMA_CHANNELS) && (dma_resource[x].valid))
typedef struct { typedef struct {
void* userCallback; // user given callback void *userCallback; // user given callback
void* dest; // memcpy destination void *dest; // memcpy destination
} mxc_dma_highlevel_t; } mxc_dma_highlevel_t;
typedef struct { typedef struct {
unsigned int valid; // Flag to invalidate this resource unsigned int valid; // Flag to invalidate this resource
unsigned int instance; // Hardware instance of this DMA controller unsigned int instance; // Hardware instance of this DMA controller
unsigned int id; // Channel ID, which matches the index into the underlying hardware unsigned int id; // Channel ID, which matches the index into the underlying hardware
mxc_dma_reva_ch_regs_t *regs; // Pointer to the registers for this channel mxc_dma_reva_ch_regs_t *regs; // Pointer to the registers for this channel
void(*cb)(int, int); // Pointer to a callback function type void (*cb)(int, int); // Pointer to a callback function type
} mxc_dma_channel_t; } mxc_dma_channel_t;
/******* Globals *******/ /******* Globals *******/
static unsigned int dma_initialized[MXC_DMA_INSTANCES] = {0}; static unsigned int dma_initialized[MXC_DMA_INSTANCES] = { 0 };
static mxc_dma_channel_t dma_resource[MXC_DMA_CHANNELS]; static mxc_dma_channel_t dma_resource[MXC_DMA_CHANNELS];
static mxc_dma_highlevel_t memcpy_resource[MXC_DMA_CHANNELS]; static mxc_dma_highlevel_t memcpy_resource[MXC_DMA_CHANNELS];
#if USE_LOCK_IN_DRIVERS static uint32_t dma_lock;
static uint32_t dma_lock;
#endif
/****** Functions ******/ /****** Functions ******/
static void memcpy_callback(int ch, int error); static void memcpy_callback(int ch, int error);
@ -78,59 +73,59 @@ int MXC_DMA_RevA_Init(mxc_dma_reva_regs_t *dma)
int i, numCh, offset; int i, numCh, offset;
#if TARGET_NUM == 32665 #if TARGET_NUM == 32665
numCh = MXC_DMA_CH_OFFSET; numCh = MXC_DMA_CH_OFFSET;
offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma); offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma);
#else #else
numCh = MXC_DMA_CHANNELS; numCh = MXC_DMA_CHANNELS;
offset = 0; offset = 0;
#endif #endif
if(dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]) { if (dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma)]) {
return E_BAD_STATE; return E_BAD_STATE;
} }
#ifndef __riscv #ifndef __riscv
/* Initialize mutex */ /* Initialize mutex */
MXC_FreeLock(&dma_lock); MXC_FreeLock(&dma_lock);
if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) {
return E_BUSY; return E_BUSY;
} }
#endif #endif
/* Ensure all channels are disabled at start, clear flags, init handles */ /* Ensure all channels are disabled at start, clear flags, init handles */
dma->inten = 0; dma->inten = 0;
for(i = offset; i < (offset + numCh); i++) { for (i = offset; i < (offset + numCh); i++) {
dma_resource[i].valid = 0; dma_resource[i].valid = 0;
dma_resource[i].instance = 0; dma_resource[i].instance = 0;
dma_resource[i].id = i; dma_resource[i].id = i;
dma_resource[i].regs = (mxc_dma_reva_ch_regs_t*) &(dma->ch[(i % numCh)]); dma_resource[i].regs = (mxc_dma_reva_ch_regs_t *)&(dma->ch[(i % numCh)]);
dma_resource[i].regs->ctrl = 0; dma_resource[i].regs->ctrl = 0;
dma_resource[i].regs->status = dma_resource[i].regs->status; dma_resource[i].regs->status = dma_resource[i].regs->status;
dma_resource[i].cb = NULL; dma_resource[i].cb = NULL;
} }
dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]++; dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma)]++;
#ifndef __riscv #ifndef __riscv
MXC_FreeLock(&dma_lock); MXC_FreeLock(&dma_lock);
#endif #endif
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma) int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t *dma)
{ {
int i, channel, numCh, offset; int i, channel, numCh, offset;
/* Check for initialization */ /* Check for initialization */
if(!dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]) { if (!dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma)]) {
return E_BAD_STATE; return E_BAD_STATE;
} }
#if TARGET_NUM == 32665 #if TARGET_NUM == 32665
numCh = MXC_DMA_CH_OFFSET; numCh = MXC_DMA_CH_OFFSET;
offset = MXC_DMA_CH_OFFSET * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma); offset = MXC_DMA_CH_OFFSET * MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma);
#else #else
numCh = MXC_DMA_CHANNELS; numCh = MXC_DMA_CHANNELS;
offset = 0; offset = 0;
@ -138,15 +133,15 @@ int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma)
#ifndef __riscv #ifndef __riscv
/* If DMA is locked return busy */ /* If DMA is locked return busy */
if(MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) {
return E_BUSY; return E_BUSY;
} }
#endif #endif
/* Default is no channel available */ /* Default is no channel available */
channel = E_NONE_AVAIL; channel = E_NONE_AVAIL;
for(i = offset; i < (offset + numCh); i++) { for (i = offset; i < (offset + numCh); i++) {
if(!dma_resource[i].valid) { if (!dma_resource[i].valid) {
/* Found one */ /* Found one */
channel = i; channel = i;
dma_resource[i].valid = 1; dma_resource[i].valid = 1;
@ -164,8 +159,8 @@ int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma)
int MXC_DMA_RevA_ReleaseChannel(int ch) int MXC_DMA_RevA_ReleaseChannel(int ch)
{ {
if(CHECK_HANDLE(ch)) { if (CHECK_HANDLE(ch)) {
if(MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) {
return E_BUSY; return E_BUSY;
} }
@ -173,8 +168,7 @@ int MXC_DMA_RevA_ReleaseChannel(int ch)
dma_resource[ch].regs->ctrl = 0; dma_resource[ch].regs->ctrl = 0;
dma_resource[ch].regs->status = dma_resource[ch].regs->status; dma_resource[ch].regs->status = dma_resource[ch].regs->status;
MXC_FreeLock(&dma_lock); MXC_FreeLock(&dma_lock);
} } else {
else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
@ -183,116 +177,102 @@ int MXC_DMA_RevA_ReleaseChannel(int ch)
int MXC_DMA_RevA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst) int MXC_DMA_RevA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst)
{ {
if(CHECK_HANDLE(config.ch)) { if (CHECK_HANDLE(config.ch)) {
/* Designed to be safe, not speedy. Should not be called often */ /* Designed to be safe, not speedy. Should not be called often */
dma_resource[config.ch].regs->ctrl = dma_resource[config.ch].regs->ctrl =
((config.srcinc_en ? MXC_F_DMA_REVA_CTRL_SRCINC : 0) | ((config.srcinc_en ? MXC_F_DMA_REVA_CTRL_SRCINC : 0) |
(config.dstinc_en ? MXC_F_DMA_REVA_CTRL_DSTINC : 0) | (config.dstinc_en ? MXC_F_DMA_REVA_CTRL_DSTINC : 0) | config.reqsel |
config.reqsel | (config.srcwd << MXC_F_DMA_REVA_CTRL_SRCWD_POS) |
(config.srcwd << MXC_F_DMA_REVA_CTRL_SRCWD_POS) | (config.dstwd << MXC_F_DMA_REVA_CTRL_DSTWD_POS));
(config.dstwd << MXC_F_DMA_REVA_CTRL_DSTWD_POS)); } else {
}
else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
return MXC_DMA_RevA_SetSrcDst(srcdst); return MXC_DMA_RevA_SetSrcDst(srcdst);
} }
int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig)
{ {
if(CHECK_HANDLE(advConfig.ch) &&(advConfig.burst_size > 0)) { if (CHECK_HANDLE(advConfig.ch) && (advConfig.burst_size > 0)) {
dma_resource[advConfig.ch].regs->ctrl &= ~(0x1F00FC0C); // Clear all fields we set here dma_resource[advConfig.ch].regs->ctrl &= ~(0x1F00FC0C); // Clear all fields we set here
/* Designed to be safe, not speedy. Should not be called often */ /* Designed to be safe, not speedy. Should not be called often */
dma_resource[advConfig.ch].regs->ctrl |= dma_resource[advConfig.ch].regs->ctrl |=
((advConfig.reqwait_en ? MXC_F_DMA_REVA_CTRL_TO_WAIT : 0) | ((advConfig.reqwait_en ? MXC_F_DMA_REVA_CTRL_TO_WAIT : 0) | advConfig.prio |
advConfig.prio | advConfig.tosel | advConfig.pssel | advConfig.tosel | advConfig.pssel |
(((advConfig.burst_size - 1) << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS) & MXC_F_DMA_REVA_CTRL_BURST_SIZE)); (((advConfig.burst_size - 1) << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS) &
} MXC_F_DMA_REVA_CTRL_BURST_SIZE));
else { } else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_DMA_RevA_SetSrcDst(mxc_dma_srcdst_t srcdst) int MXC_DMA_RevA_SetSrcDst(mxc_dma_srcdst_t srcdst)
{ {
if(CHECK_HANDLE(srcdst.ch)) { if (CHECK_HANDLE(srcdst.ch)) {
dma_resource[srcdst.ch].regs->src = (unsigned int) srcdst.source; dma_resource[srcdst.ch].regs->src = (unsigned int)srcdst.source;
dma_resource[srcdst.ch].regs->dst = (unsigned int) srcdst.dest; dma_resource[srcdst.ch].regs->dst = (unsigned int)srcdst.dest;
dma_resource[srcdst.ch].regs->cnt = srcdst.len; dma_resource[srcdst.ch].regs->cnt = srcdst.len;
} } else {
else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t *srcdst)
int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t* srcdst)
{ {
if (CHECK_HANDLE(srcdst->ch)) { if (CHECK_HANDLE(srcdst->ch)) {
srcdst->source = (void*) dma_resource[srcdst->ch].regs->src; srcdst->source = (void *)dma_resource[srcdst->ch].regs->src;
srcdst->dest = (void*) dma_resource[srcdst->ch].regs->dst; srcdst->dest = (void *)dma_resource[srcdst->ch].regs->dst;
srcdst->len = (dma_resource[srcdst->ch].regs->cnt) & ~MXC_F_DMA_REVA_CNTRLD_EN; srcdst->len = (dma_resource[srcdst->ch].regs->cnt) & ~MXC_F_DMA_REVA_CNTRLD_EN;
} } else {
else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst) int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst)
{ {
if(CHECK_HANDLE(srcdst.ch)) { if (CHECK_HANDLE(srcdst.ch)) {
dma_resource[srcdst.ch].regs->srcrld = (unsigned int) srcdst.source; dma_resource[srcdst.ch].regs->srcrld = (unsigned int)srcdst.source;
dma_resource[srcdst.ch].regs->dstrld = (unsigned int) srcdst.dest; dma_resource[srcdst.ch].regs->dstrld = (unsigned int)srcdst.dest;
if(dma_resource[srcdst.ch].regs->ctrl & MXC_F_DMA_REVA_CTRL_EN) { if (dma_resource[srcdst.ch].regs->ctrl & MXC_F_DMA_REVA_CTRL_EN) {
/* If channel is already running, set RLDEN to enable next reload */ /* If channel is already running, set RLDEN to enable next reload */
dma_resource[srcdst.ch].regs->cntrld = MXC_F_DMA_REVA_CNTRLD_EN | srcdst.len; dma_resource[srcdst.ch].regs->cntrld = MXC_F_DMA_REVA_CNTRLD_EN | srcdst.len;
} } else {
else {
/* Otherwise, this is the initial setup, so DMA_Start() will handle setting that bit */ /* Otherwise, this is the initial setup, so DMA_Start() will handle setting that bit */
dma_resource[srcdst.ch].regs->cntrld = srcdst.len; dma_resource[srcdst.ch].regs->cntrld = srcdst.len;
} }
} } else {
else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t *srcdst)
int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t* srcdst)
{ {
if (CHECK_HANDLE(srcdst->ch)) { if (CHECK_HANDLE(srcdst->ch)) {
srcdst->source = (void*) dma_resource[srcdst->ch].regs->srcrld; srcdst->source = (void *)dma_resource[srcdst->ch].regs->srcrld;
srcdst->dest = (void*) dma_resource[srcdst->ch].regs->dstrld; srcdst->dest = (void *)dma_resource[srcdst->ch].regs->dstrld;
srcdst->len = (dma_resource[srcdst->ch].regs->cntrld) & ~MXC_F_DMA_REVA_CNTRLD_EN; srcdst->len = (dma_resource[srcdst->ch].regs->cntrld) & ~MXC_F_DMA_REVA_CNTRLD_EN;
} } else {
else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_DMA_RevA_SetCallback(int ch, void (*callback)(int, int))
int MXC_DMA_RevA_SetCallback(int ch, void(*callback)(int, int))
{ {
if(CHECK_HANDLE(ch)) { if (CHECK_HANDLE(ch)) {
/* Callback for interrupt handler, no checking is done, as NULL is valid for(none) */ /* Callback for interrupt handler, no checking is done, as NULL is valid for(none) */
dma_resource[ch].cb = callback; dma_resource[ch].cb = callback;
} } else {
else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
@ -301,22 +281,20 @@ int MXC_DMA_RevA_SetCallback(int ch, void(*callback)(int, int))
int MXC_DMA_RevA_SetChannelInterruptEn(int ch, bool chdis, bool ctz) int MXC_DMA_RevA_SetChannelInterruptEn(int ch, bool chdis, bool ctz)
{ {
if(CHECK_HANDLE(ch)) { if (CHECK_HANDLE(ch)) {
if(chdis){ if (chdis) {
dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_DIS_IE); dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_DIS_IE);
} }
if(ctz){ if (ctz) {
dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_CTZ_IE); dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_CTZ_IE);
} }
} } else {
else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_DMA_RevA_GetChannelInterruptEn(int ch) int MXC_DMA_RevA_GetChannelInterruptEn(int ch)
{ {
return E_NOT_SUPPORTED; return E_NOT_SUPPORTED;
@ -324,10 +302,10 @@ int MXC_DMA_RevA_GetChannelInterruptEn(int ch)
int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags) int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags)
{ {
if(CHECK_HANDLE(ch)) { if (CHECK_HANDLE(ch)) {
dma_resource[ch].regs->ctrl |= (flags &(MXC_F_DMA_REVA_CTRL_DIS_IE|MXC_F_DMA_REVA_CTRL_CTZ_IE)); dma_resource[ch].regs->ctrl |=
} (flags & (MXC_F_DMA_REVA_CTRL_DIS_IE | MXC_F_DMA_REVA_CTRL_CTZ_IE));
else { } else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
@ -336,10 +314,10 @@ int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags)
int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags) int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags)
{ {
if(CHECK_HANDLE(ch)) { if (CHECK_HANDLE(ch)) {
dma_resource[ch].regs->ctrl &= ~(flags &(MXC_F_DMA_REVA_CTRL_DIS_IE|MXC_F_DMA_REVA_CTRL_CTZ_IE)); dma_resource[ch].regs->ctrl &=
} ~(flags & (MXC_F_DMA_REVA_CTRL_DIS_IE | MXC_F_DMA_REVA_CTRL_CTZ_IE));
else { } else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
@ -348,13 +326,12 @@ int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags)
int MXC_DMA_RevA_EnableInt(mxc_dma_reva_regs_t *dma, int ch) int MXC_DMA_RevA_EnableInt(mxc_dma_reva_regs_t *dma, int ch)
{ {
if(CHECK_HANDLE(ch)) { if (CHECK_HANDLE(ch)) {
#if TARGET_NUM == 32665 #if TARGET_NUM == 32665
ch %= MXC_DMA_CH_OFFSET; ch %= MXC_DMA_CH_OFFSET;
#endif #endif
dma->inten |= (1 << ch); dma->inten |= (1 << ch);
} } else {
else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
@ -363,13 +340,12 @@ int MXC_DMA_RevA_EnableInt(mxc_dma_reva_regs_t *dma, int ch)
int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch) int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch)
{ {
if(CHECK_HANDLE(ch)) { if (CHECK_HANDLE(ch)) {
#if TARGET_NUM == 32665 #if TARGET_NUM == 32665
ch %= MXC_DMA_CH_OFFSET; ch %= MXC_DMA_CH_OFFSET;
#endif #endif
dma->inten &= ~(1 << ch); dma->inten &= ~(1 << ch);
} } else {
else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
@ -378,10 +354,9 @@ int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch)
int MXC_DMA_RevA_ChannelGetFlags(int ch) int MXC_DMA_RevA_ChannelGetFlags(int ch)
{ {
if(CHECK_HANDLE(ch)) { if (CHECK_HANDLE(ch)) {
return dma_resource[ch].regs->status; return dma_resource[ch].regs->status;
} } else {
else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
@ -390,10 +365,9 @@ int MXC_DMA_RevA_ChannelGetFlags(int ch)
int MXC_DMA_RevA_ChannelClearFlags(int ch, int flags) int MXC_DMA_RevA_ChannelClearFlags(int ch, int flags)
{ {
if(CHECK_HANDLE(ch)) { if (CHECK_HANDLE(ch)) {
dma_resource[ch].regs->status |= (flags & 0x5F); // Mask for Interrupt flags dma_resource[ch].regs->status |= (flags & 0x5F); // Mask for Interrupt flags
} } else {
else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
@ -402,17 +376,15 @@ int MXC_DMA_RevA_ChannelClearFlags(int ch, int flags)
int MXC_DMA_RevA_Start(int ch) int MXC_DMA_RevA_Start(int ch)
{ {
if(CHECK_HANDLE(ch)) { if (CHECK_HANDLE(ch)) {
MXC_DMA_ChannelClearFlags(ch, MXC_DMA_RevA_ChannelGetFlags(ch)); MXC_DMA_ChannelClearFlags(ch, MXC_DMA_RevA_ChannelGetFlags(ch));
if(dma_resource[ch].regs->cntrld) { if (dma_resource[ch].regs->cntrld) {
dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_EN | MXC_F_DMA_REVA_CTRL_RLDEN); dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_EN | MXC_F_DMA_REVA_CTRL_RLDEN);
} } else {
else {
dma_resource[ch].regs->ctrl |= MXC_F_DMA_REVA_CTRL_EN; dma_resource[ch].regs->ctrl |= MXC_F_DMA_REVA_CTRL_EN;
} }
} } else {
else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
@ -421,22 +393,20 @@ int MXC_DMA_RevA_Start(int ch)
int MXC_DMA_RevA_Stop(int ch) int MXC_DMA_RevA_Stop(int ch)
{ {
if(CHECK_HANDLE(ch)) { if (CHECK_HANDLE(ch)) {
dma_resource[ch].regs->ctrl &= ~MXC_F_DMA_REVA_CTRL_EN; dma_resource[ch].regs->ctrl &= ~MXC_F_DMA_REVA_CTRL_EN;
} } else {
else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
return E_NO_ERROR; return E_NO_ERROR;
} }
mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch) mxc_dma_ch_regs_t *MXC_DMA_RevA_GetCHRegs(int ch)
{ {
if(CHECK_HANDLE(ch)) { if (CHECK_HANDLE(ch)) {
return(mxc_dma_ch_regs_t*) dma_resource[ch].regs; return (mxc_dma_ch_regs_t *)dma_resource[ch].regs;
} } else {
else {
return NULL; return NULL;
} }
} }
@ -444,17 +414,21 @@ mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch)
void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma) void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma)
{ {
int numCh = MXC_DMA_CHANNELS / MXC_DMA_INSTANCES; int numCh = MXC_DMA_CHANNELS / MXC_DMA_INSTANCES;
int offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma); int offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma);
/* Do callback, if enabled */ /* Do callback, if enabled */
for(int i = offset; i < (offset + numCh); i++) { for (int i = offset; i < (offset + numCh); i++) {
if(CHECK_HANDLE(i)) { if (CHECK_HANDLE(i)) {
if(dma->intfl &(0x1 << (i % numCh))) { if (dma->intfl & (0x1 << (i % numCh))) {
if(dma_resource[i].cb != NULL) { if (dma_resource[i].cb != NULL) {
dma_resource[i].cb(i, E_NO_ERROR); dma_resource[i].cb(i, E_NO_ERROR);
} }
MXC_DMA_ChannelClearFlags(i, MXC_DMA_RevA_ChannelGetFlags(i)); MXC_DMA_ChannelClearFlags(i, MXC_DMA_RevA_ChannelGetFlags(i));
break;
// No need to check rest of the channels if no interrupt flags set.
if (dma->intfl == 0) {
break;
}
} }
} }
} }
@ -463,32 +437,36 @@ void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma)
void memcpy_callback(int ch, int error) void memcpy_callback(int ch, int error)
{ {
mxc_dma_complete_cb_t callback; mxc_dma_complete_cb_t callback;
callback = (mxc_dma_complete_cb_t) memcpy_resource[ch].userCallback; callback = (mxc_dma_complete_cb_t)memcpy_resource[ch].userCallback;
if(error != E_NO_ERROR) { if (error != E_NO_ERROR) {
callback(NULL); callback(NULL);
} }
callback(memcpy_resource[ch].dest); callback(memcpy_resource[ch].dest);
// Release global objects and local resources
callback = NULL; callback = NULL;
memcpy_resource[ch].userCallback = NULL;
memcpy_resource[ch].dest = NULL;
MXC_DMA_ReleaseChannel(ch); MXC_DMA_ReleaseChannel(ch);
} }
int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len, mxc_dma_complete_cb_t callback) int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len,
mxc_dma_complete_cb_t callback)
{ {
int retval; int retval;
mxc_dma_config_t config; mxc_dma_config_t config;
mxc_dma_srcdst_t transfer; mxc_dma_srcdst_t transfer;
int channel; int channel;
#if TARGET_NUM == 32665 #if TARGET_NUM == 32665
channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t*) dma); channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t *)dma);
#else #else
channel = MXC_DMA_AcquireChannel(); channel = MXC_DMA_AcquireChannel();
#endif #endif
if(memcpy_resource[channel].userCallback != NULL) { if (memcpy_resource[channel].userCallback != NULL) {
// We acquired a channel we haven't cleared yet // We acquired a channel we haven't cleared yet
MXC_DMA_ReleaseChannel(channel); MXC_DMA_ReleaseChannel(channel);
return E_UNKNOWN; return E_UNKNOWN;
@ -508,25 +486,25 @@ int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len
retval = MXC_DMA_ConfigChannel(config, transfer); retval = MXC_DMA_ConfigChannel(config, transfer);
if(retval != E_NO_ERROR) { if (retval != E_NO_ERROR) {
return retval; return retval;
} }
retval = MXC_DMA_EnableInt(channel); retval = MXC_DMA_EnableInt(channel);
if(retval != E_NO_ERROR) { if (retval != E_NO_ERROR) {
return retval; return retval;
} }
retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_REVA_CTRL_CTZ_IE); retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_REVA_CTRL_CTZ_IE);
if(retval != E_NO_ERROR) { if (retval != E_NO_ERROR) {
return retval; return retval;
} }
MXC_DMA_SetCallback(channel, memcpy_callback); MXC_DMA_SetCallback(channel, memcpy_callback);
memcpy_resource[channel].userCallback = (void*) callback; memcpy_resource[channel].userCallback = (void *)callback;
memcpy_resource[channel].dest = dest; memcpy_resource[channel].dest = dest;
return MXC_DMA_Start(channel); return MXC_DMA_Start(channel);
@ -539,20 +517,21 @@ void transfer_callback(int ch, int error)
// Call user callback for next transfer // Call user callback for next transfer
// determine whether to load into the transfer slot or reload slot // determine whether to load into the transfer slot or reload slot
// continue on or stop // continue on or stop
while(1); while (1) {}
} }
int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback) int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config,
mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback)
{ {
int retval, channel; int retval, channel;
#if TARGET_NUM == 32665 #if TARGET_NUM == 32665
channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t*) dma); channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t *)dma);
#else #else
channel = MXC_DMA_AcquireChannel(); channel = MXC_DMA_AcquireChannel();
#endif #endif
if(memcpy_resource[channel].userCallback != NULL) { if (memcpy_resource[channel].userCallback != NULL) {
// We acquired a channel we haven't cleared yet // We acquired a channel we haven't cleared yet
MXC_DMA_ReleaseChannel(channel); MXC_DMA_ReleaseChannel(channel);
return E_UNKNOWN; return E_UNKNOWN;
@ -560,25 +539,25 @@ int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, m
retval = MXC_DMA_ConfigChannel(config, firstSrcDst); retval = MXC_DMA_ConfigChannel(config, firstSrcDst);
if(retval != E_NO_ERROR) { if (retval != E_NO_ERROR) {
return retval; return retval;
} }
retval = MXC_DMA_EnableInt(channel); retval = MXC_DMA_EnableInt(channel);
if(retval != E_NO_ERROR) { if (retval != E_NO_ERROR) {
return retval; return retval;
} }
retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_REVA_CTRL_CTZ_IE); retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_REVA_CTRL_CTZ_IE);
if(retval != E_NO_ERROR) { if (retval != E_NO_ERROR) {
return retval; return retval;
} }
MXC_DMA_SetCallback(channel, transfer_callback); MXC_DMA_SetCallback(channel, transfer_callback);
memcpy_resource[channel].userCallback = (void*) callback; memcpy_resource[channel].userCallback = (void *)callback;
return MXC_DMA_Start(channel); return MXC_DMA_Start(channel);
} }

25
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva.h
View File

@ -1,8 +1,8 @@
/* **************************************************************************** /******************************************************************************
* Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files(the "Software"), * copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation * to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense, * the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the * and/or sell copies of the Software, and to permit persons to whom the
@ -29,7 +29,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
*************************************************************************** */ ******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVA_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVA_H_
/****** Includes *******/ /****** Includes *******/
#include "dma_reva_regs.h" #include "dma_reva_regs.h"
@ -41,7 +44,7 @@
/****** Functions ******/ /****** Functions ******/
int MXC_DMA_RevA_Init(mxc_dma_reva_regs_t *dma); int MXC_DMA_RevA_Init(mxc_dma_reva_regs_t *dma);
int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma); int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t *dma);
int MXC_DMA_RevA_ReleaseChannel(int ch); int MXC_DMA_RevA_ReleaseChannel(int ch);
int MXC_DMA_RevA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); int MXC_DMA_RevA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst);
int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig); int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig);
@ -49,7 +52,7 @@ int MXC_DMA_RevA_SetSrcDst(mxc_dma_srcdst_t srcdst);
int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t *srcdst); int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t *srcdst);
int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst); int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst);
int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t *srcdst); int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t *srcdst);
int MXC_DMA_RevA_SetCallback(int ch, void(*callback)(int, int)); int MXC_DMA_RevA_SetCallback(int ch, void (*callback)(int, int));
int MXC_DMA_RevA_SetChannelInterruptEn(int ch, bool chdis, bool ctz); int MXC_DMA_RevA_SetChannelInterruptEn(int ch, bool chdis, bool ctz);
int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags); int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags);
int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags); int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags);
@ -59,7 +62,11 @@ int MXC_DMA_RevA_EnableInt(mxc_dma_reva_regs_t *dma, int ch);
int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch); int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch);
int MXC_DMA_RevA_Start(int ch); int MXC_DMA_RevA_Start(int ch);
int MXC_DMA_RevA_Stop(int ch); int MXC_DMA_RevA_Stop(int ch);
mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch); mxc_dma_ch_regs_t *MXC_DMA_RevA_GetCHRegs(int ch);
void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma); void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma);
int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len, mxc_dma_complete_cb_t callback); int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len,
int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback); mxc_dma_complete_cb_t callback);
int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config,
mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback);
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVA_H_

39
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva_regs.h
View File

@ -3,8 +3,8 @@
* @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _DMA_REVA_REGS_H_ #ifndef _DMA_REVA_REGS_H_
#define _DMA_REVA_REGS_H_ #define _DMA_REVA_REGS_H_
@ -86,14 +85,14 @@ extern "C" {
* Structure type to access the DMA Registers. * Structure type to access the DMA Registers.
*/ */
typedef struct { typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x100:</tt> DMA CTRL Register */ __IO uint32_t ctrl; /**< <tt>\b 0x000:</tt> DMA CTRL Register */
__IO uint32_t status; /**< <tt>\b 0x104:</tt> DMA STATUS Register */ __IO uint32_t status; /**< <tt>\b 0x004:</tt> DMA STATUS Register */
__IO uint32_t src; /**< <tt>\b 0x108:</tt> DMA SRC Register */ __IO uint32_t src; /**< <tt>\b 0x008:</tt> DMA SRC Register */
__IO uint32_t dst; /**< <tt>\b 0x10C:</tt> DMA DST Register */ __IO uint32_t dst; /**< <tt>\b 0x00C:</tt> DMA DST Register */
__IO uint32_t cnt; /**< <tt>\b 0x110:</tt> DMA CNT Register */ __IO uint32_t cnt; /**< <tt>\b 0x010:</tt> DMA CNT Register */
__IO uint32_t srcrld; /**< <tt>\b 0x114:</tt> DMA SRCRLD Register */ __IO uint32_t srcrld; /**< <tt>\b 0x014:</tt> DMA SRCRLD Register */
__IO uint32_t dstrld; /**< <tt>\b 0x118:</tt> DMA DSTRLD Register */ __IO uint32_t dstrld; /**< <tt>\b 0x018:</tt> DMA DSTRLD Register */
__IO uint32_t cntrld; /**< <tt>\b 0x11C:</tt> DMA CNTRLD Register */ __IO uint32_t cntrld; /**< <tt>\b 0x01C:</tt> DMA CNTRLD Register */
} mxc_dma_reva_ch_regs_t; } mxc_dma_reva_ch_regs_t;
typedef struct { typedef struct {
@ -110,14 +109,14 @@ typedef struct {
* @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_DMA_REVA_CTRL ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */ #define MXC_R_DMA_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
#define MXC_R_DMA_REVA_STATUS ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */ #define MXC_R_DMA_REVA_STATUS ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */
#define MXC_R_DMA_REVA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */ #define MXC_R_DMA_REVA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */
#define MXC_R_DMA_REVA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */ #define MXC_R_DMA_REVA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */
#define MXC_R_DMA_REVA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */ #define MXC_R_DMA_REVA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */
#define MXC_R_DMA_REVA_SRCRLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */ #define MXC_R_DMA_REVA_SRCRLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */
#define MXC_R_DMA_REVA_DSTRLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */ #define MXC_R_DMA_REVA_DSTRLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */
#define MXC_R_DMA_REVA_CNTRLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */ #define MXC_R_DMA_REVA_CNTRLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */
#define MXC_R_DMA_REVA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */ #define MXC_R_DMA_REVA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */
#define MXC_R_DMA_REVA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */ #define MXC_R_DMA_REVA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */
#define MXC_R_DMA_REVA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */ #define MXC_R_DMA_REVA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */

42
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_common.c
View File

@ -1,10 +1,10 @@
/** /**
* @file flc.h * @file flc_common.c
* @brief Flash Controler driver. * @brief Common functions for the flash controller drivers.
* @details This driver can be used to operate on the embedded flash memory. * @details This driver can be used to operate on the embedded flash memory.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
/* **** Includes **** */ /* **** Includes **** */
#include <string.h> #include <string.h>
@ -43,21 +42,21 @@
#include "mxc_assert.h" #include "mxc_assert.h"
#include "mxc_sys.h" #include "mxc_sys.h"
#include "flc.h" #include "flc.h"
#include "flc_common.h"
#include "stdlib.h" #include "stdlib.h"
//****************************************************************************** //******************************************************************************
#if IAR_PRAGMAS #if IAR_PRAGMAS
#pragma section=".flashprog" #pragma section = ".flashprog"
#else #else
__attribute__((section(".flashprog"))) __attribute__((section(".flashprog")))
#endif #endif
// Length is number of 32-bit words // Length is number of 32-bit words
int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t* data) int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t *data)
{ {
volatile uint32_t* ptr; volatile uint32_t *ptr;
for (ptr = (uint32_t *)address; ptr < (((uint32_t *)(address)) + length); ptr++, data++) {
for (ptr = (uint32_t*) address; ptr < (((uint32_t*)(address)) + length); ptr++, data++) {
if (*ptr != *data) { if (*ptr != *data) {
return E_BAD_STATE; return E_BAD_STATE;
} }
@ -68,28 +67,27 @@ int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t* data)
//****************************************************************************** //******************************************************************************
#if IAR_PRAGMAS #if IAR_PRAGMAS
#pragma section=".flashprog" #pragma section = ".flashprog"
#else #else
__attribute__((section(".flashprog"))) __attribute__((section(".flashprog")))
#endif #endif
// make sure to disable ICC with ICC_Disable(); before Running this function // make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t* buffer) int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t *buffer)
{ {
int err; int err;
uint32_t bytes_written; uint32_t bytes_written;
uint32_t current_data_32; uint32_t current_data_32;
uint8_t* current_data = (uint8_t*) &current_data_32; uint8_t *current_data = (uint8_t *)&current_data_32;
uint8_t* buffer8 = (uint8_t*)buffer; uint8_t *buffer8 = (uint8_t *)buffer;
// Align the address to a word boundary and read/write if we have to // Align the address to a word boundary and read/write if we have to
if (address & 0x3) { if (address & 0x3) {
// Figure out how many bytes we have to write to round up the address // Figure out how many bytes we have to write to round up the address
bytes_written = 4 - (address & 0x3); bytes_written = 4 - (address & 0x3);
// Save the data currently in the flash // Save the data currently in the flash
memcpy(current_data, (void*)(address & (~0x3)), 4); memcpy(current_data, (void *)(address & (~0x3)), 4);
// Modify current_data to insert the data from buffer // Modify current_data to insert the data from buffer
memcpy(&current_data[4 - bytes_written], buffer8, bytes_written); memcpy(&current_data[4 - bytes_written], buffer8, bytes_written);
@ -128,7 +126,6 @@ int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t* buffer)
length -= 16; length -= 16;
buffer8 += 16; buffer8 += 16;
} }
} }
while (length >= 4) { while (length >= 4) {
@ -144,7 +141,7 @@ int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t* buffer)
if (length > 0) { if (length > 0) {
// Save the data currently in the flash // Save the data currently in the flash
memcpy(current_data, (void*)(address), 4); memcpy(current_data, (void *)(address), 4);
// Modify current_data to insert the data from buffer // Modify current_data to insert the data from buffer
memcpy(current_data, buffer8, length); memcpy(current_data, buffer8, length);
@ -159,12 +156,11 @@ int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t* buffer)
//****************************************************************************** //******************************************************************************
#if IAR_PRAGMAS #if IAR_PRAGMAS
#pragma section=".flashprog" #pragma section = ".flashprog"
#else #else
__attribute__((section(".flashprog"))) __attribute__((section(".flashprog")))
#endif #endif
void MXC_FLC_Com_Read(int address, void* buffer, int len) void MXC_FLC_Com_Read(int address, void *buffer, int len)
{ {
memcpy(buffer, (void*) address, len); memcpy(buffer, (void *)address, len);
} }

28
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_common.h
View File

@ -1,11 +1,11 @@
/** /**
* @file flc.h * @file flc_common.h
* @brief Flash Controller driver. * @brief Common functions for the flash controller driver.
* @details This driver can be used to operate on the embedded flash memory. * @details This driver can be used to operate on the embedded flash memory.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -35,9 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_COMMON_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_COMMON_H_
/* **** Includes **** */ /* **** Includes **** */
#include "mxc_sys.h" #include "mxc_sys.h"
@ -54,19 +55,22 @@ extern "C" {
/***** Definitions *****/ /***** Definitions *****/
/***** Function Prototypes *****/ /***** Function Prototypes *****/
int MXC_FLC_Com_VerifyData (uint32_t address, uint32_t length, uint32_t * data); int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t *data);
int MXC_FLC_Com_Write (uint32_t address, uint32_t length, uint32_t *buffer); int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t *buffer);
void MXC_FLC_Com_Read (int address, void* buffer, int len); void MXC_FLC_Com_Read(int address, void *buffer, int len);
volatile uint32_t *MXC_FLC_GetWELR(uint32_t address, uint32_t page_num);
volatile uint32_t *MXC_FLC_GetRLR(uint32_t address, uint32_t page_num);
/**@} end of group flc */ /**@} end of group flc */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_COMMON_H_

192
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_me15.c
View File

@ -1,10 +1,10 @@
/** /**
* @file flc.h * @file flc_me15.c
* @brief Flash Controler driver. * @brief Flash Controler driver.
* @details This driver can be used to operate on the embedded flash memory. * @details This driver can be used to operate on the embedded flash memory.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
/* **** Includes **** */ /* **** Includes **** */
#include <string.h> #include <string.h>
@ -43,7 +42,7 @@
#include "mxc_assert.h" #include "mxc_assert.h"
#include "mxc_sys.h" #include "mxc_sys.h"
#include "flc.h" #include "flc.h"
#include "flc_revb.h" #include "flc_reva.h"
#include "flc_common.h" #include "flc_common.h"
#include "ecc_regs.h" // For ECCEN registers. #include "ecc_regs.h" // For ECCEN registers.
#include "mcr_regs.h" // For ECCEN registers. #include "mcr_regs.h" // For ECCEN registers.
@ -55,21 +54,17 @@ void MXC_FLC_ME15_Flash_Operation(void)
MXC_GCR->sysctrl |= MXC_F_GCR_SYSCTRL_ICC0_FLUSH; MXC_GCR->sysctrl |= MXC_F_GCR_SYSCTRL_ICC0_FLUSH;
/* Wait for flush to complete */ /* Wait for flush to complete */
while (MXC_GCR->sysctrl & MXC_F_GCR_SYSCTRL_ICC0_FLUSH) { while (MXC_GCR->sysctrl & MXC_F_GCR_SYSCTRL_ICC0_FLUSH) {}
}
} }
//****************************************************************************** //******************************************************************************
int MXC_FLC_ME15_GetByAddress(mxc_flc_regs_t** flc, uint32_t addr) int MXC_FLC_ME15_GetByAddress(mxc_flc_regs_t **flc, uint32_t addr)
{ {
if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) { if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) {
*flc = MXC_FLC0;
}
else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
*flc = MXC_FLC0; *flc = MXC_FLC0;
} } else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
else { *flc = MXC_FLC0;
} else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
@ -77,17 +72,15 @@ int MXC_FLC_ME15_GetByAddress(mxc_flc_regs_t** flc, uint32_t addr)
} }
//****************************************************************************** //******************************************************************************
int MXC_FLC_ME15_GetPhysicalAddress (uint32_t addr, uint32_t *result) int MXC_FLC_ME15_GetPhysicalAddress(uint32_t addr, uint32_t *result)
{ {
if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) { if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) {
*result = addr - MXC_FLASH_MEM_BASE; *result = addr - MXC_FLASH_MEM_BASE;
} } else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
/* For ME15, the info block base was located at the next power of 2 address beyond the main flash. /* For ME15, the info block base was located at the next power of 2 address beyond the main flash.
The ME15 ends at 0x5FFFF, so the info block starts at 0x80000. */ The ME15 ends at 0x5FFFF, so the info block starts at 0x80000. */
*result = (addr & (MXC_INFO_MEM_SIZE - 1)) + 0x80000; *result = (addr & (MXC_INFO_MEM_SIZE - 1)) + 0x80000;
} } else {
else {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
@ -95,32 +88,33 @@ int MXC_FLC_ME15_GetPhysicalAddress (uint32_t addr, uint32_t *result)
} }
//****************************************************************************** //******************************************************************************
int MXC_FLC_Init() int MXC_FLC_Init()
{ {
return E_NO_ERROR; return E_NO_ERROR;
} }
//******************************************************************************
#if IAR_PRAGMAS #if IAR_PRAGMAS
#pragma section=".flashprog" #pragma section = ".flashprog"
#else #else
__attribute__((section(".flashprog"))) __attribute__((section(".flashprog")))
#endif #endif
int MXC_FLC_Busy(void) int MXC_FLC_Busy(void)
{ {
return MXC_FLC_RevB_Busy(); return MXC_FLC_RevA_Busy();
} }
//******************************************************************************
#if IAR_PRAGMAS #if IAR_PRAGMAS
#pragma section=".flashprog" #pragma section = ".flashprog"
#else #else
__attribute__((section(".flashprog"))) __attribute__((section(".flashprog")))
#endif #endif
int MXC_FLC_ME15_PageErase(uint32_t address) int MXC_FLC_PageErase(uint32_t address)
{ {
int err; int err;
uint32_t addr; uint32_t addr;
mxc_flc_regs_t* flc = NULL; mxc_flc_regs_t *flc = NULL;
// Get FLC Instance // Get FLC Instance
if ((err = MXC_FLC_ME15_GetByAddress(&flc, address)) != E_NO_ERROR) { if ((err = MXC_FLC_ME15_GetByAddress(&flc, address)) != E_NO_ERROR) {
@ -131,23 +125,24 @@ int MXC_FLC_ME15_PageErase(uint32_t address)
return err; return err;
} }
err = MXC_FLC_RevB_PageErase ((mxc_flc_revb_regs_t*) flc, addr); err = MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t *)flc, addr);
// Flush the cache // Flush the cache
MXC_FLC_ME15_Flash_Operation(); MXC_FLC_ME15_Flash_Operation();
return err; return err;
} }
//******************************************************************************
#if IAR_PRAGMAS #if IAR_PRAGMAS
#pragma section=".flashprog" #pragma section = ".flashprog"
#else #else
__attribute__((section(".flashprog"))) __attribute__((section(".flashprog")))
#endif #endif
// make sure to disable ICC with ICC_Disable(); before Running this function // make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_ME15_Write128(uint32_t address, uint32_t* data) int MXC_FLC_Write128(uint32_t address, uint32_t *data)
{ {
int err; int err;
mxc_flc_regs_t* flc = NULL; mxc_flc_regs_t *flc = NULL;
uint32_t addr; uint32_t addr;
// Address checked if it is 128-bit aligned // Address checked if it is 128-bit aligned
@ -164,7 +159,7 @@ int MXC_FLC_ME15_Write128(uint32_t address, uint32_t* data)
return err; return err;
} }
if((err= MXC_FLC_RevB_Write128 ((mxc_flc_revb_regs_t*) flc, addr, data)) != E_NO_ERROR) { if ((err = MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t *)flc, addr, data)) != E_NO_ERROR) {
return err; return err;
} }
@ -179,11 +174,11 @@ int MXC_FLC_ME15_Write128(uint32_t address, uint32_t* data)
} }
//****************************************************************************** //******************************************************************************
int MXC_FLC_ME15_Write32(uint32_t address, uint32_t data) int MXC_FLC_Write32(uint32_t address, uint32_t data)
{ {
uint32_t addr, aligned; uint32_t addr, aligned;
int err; int err;
mxc_flc_regs_t* flc = NULL; mxc_flc_regs_t *flc = NULL;
// Address checked if it is byte addressable // Address checked if it is byte addressable
if (address & 0x3) { if (address & 0x3) {
@ -203,22 +198,21 @@ int MXC_FLC_ME15_Write32(uint32_t address, uint32_t data)
} }
if (MXC_ECC->en & MXC_F_ECC_EN_FLASH) { if (MXC_ECC->en & MXC_F_ECC_EN_FLASH) {
return E_BAD_STATE; return E_BAD_STATE;
} }
return MXC_FLC_RevB_Write32 ((mxc_flc_revb_regs_t*) flc, address, data, addr); return MXC_FLC_RevA_Write32Using128((mxc_flc_reva_regs_t *)flc, address, data, addr);
} }
int MXC_FLC_ME15_MassErase(void) //******************************************************************************
int MXC_FLC_MassErase(void)
{ {
int err, i; int err, i;
mxc_flc_regs_t* flc; mxc_flc_regs_t *flc;
for (i=0; i<MXC_FLC_INSTANCES; i++) { for (i = 0; i < MXC_FLC_INSTANCES; i++) {
flc = MXC_FLC_GET_FLC (i); flc = MXC_FLC_GET_FLC(i);
err = MXC_FLC_RevB_MassErase((mxc_flc_revb_regs_t*) flc); err = MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t *)flc);
if (err != E_NO_ERROR) { if (err != E_NO_ERROR) {
return err; return err;
@ -228,87 +222,127 @@ int MXC_FLC_ME15_MassErase(void)
} }
return E_NO_ERROR; return E_NO_ERROR;
} }
int MXC_FLC_ME15_UnlockInfoBlock(uint32_t address)
//******************************************************************************
int MXC_FLC_UnlockInfoBlock(uint32_t address)
{ {
int err; int err;
mxc_flc_regs_t* flc; mxc_flc_regs_t *flc;
if ((err = MXC_FLC_ME15_GetByAddress(&flc, address)) != E_NO_ERROR) { if ((err = MXC_FLC_ME15_GetByAddress(&flc, address)) != E_NO_ERROR) {
return err; return err;
} }
return MXC_FLC_RevB_UnlockInfoBlock ((mxc_flc_revb_regs_t*) flc, address); return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t *)flc, address);
} }
int MXC_FLC_ME15_LockInfoBlock(uint32_t address)
//******************************************************************************
int MXC_FLC_LockInfoBlock(uint32_t address)
{ {
int err; int err;
mxc_flc_regs_t* flc; mxc_flc_regs_t *flc;
if ((err = MXC_FLC_ME15_GetByAddress(&flc, address)) != E_NO_ERROR) { if ((err = MXC_FLC_ME15_GetByAddress(&flc, address)) != E_NO_ERROR) {
return err; return err;
} }
return MXC_FLC_RevB_LockInfoBlock ((mxc_flc_revb_regs_t*) flc, address); return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t *)flc, address);
}
/* ****************************************************************************** */
int MXC_FLC_MassErase(void)
{
return MXC_FLC_ME15_MassErase();
} }
int MXC_FLC_PageErase(uint32_t address) //******************************************************************************
{ int MXC_FLC_Write(uint32_t address, uint32_t length, uint32_t *buffer)
return MXC_FLC_ME15_PageErase(address);
}
int MXC_FLC_Write32(uint32_t address, uint32_t data)
{
return MXC_FLC_ME15_Write32(address, data);
}
int MXC_FLC_Write128(uint32_t address, uint32_t* data)
{
return MXC_FLC_ME15_Write128(address, data);
}
int MXC_FLC_Write(uint32_t address, uint32_t length, uint32_t* buffer)
{ {
return MXC_FLC_Com_Write(address, length, buffer); return MXC_FLC_Com_Write(address, length, buffer);
} }
void MXC_FLC_Read(int address, void* buffer, int len)
//******************************************************************************
void MXC_FLC_Read(int address, void *buffer, int len)
{ {
MXC_FLC_Com_Read(address, buffer, len); MXC_FLC_Com_Read(address, buffer, len);
} }
//******************************************************************************
int MXC_FLC_EnableInt(uint32_t flags) int MXC_FLC_EnableInt(uint32_t flags)
{ {
return MXC_FLC_RevB_EnableInt(flags); return MXC_FLC_RevA_EnableInt(flags);
} }
//******************************************************************************
int MXC_FLC_DisableInt(uint32_t flags) int MXC_FLC_DisableInt(uint32_t flags)
{ {
return MXC_FLC_RevB_DisableInt(flags); return MXC_FLC_RevA_DisableInt(flags);
} }
//******************************************************************************
int MXC_FLC_GetFlags(void) int MXC_FLC_GetFlags(void)
{ {
return MXC_FLC_RevB_GetFlags(); return MXC_FLC_RevA_GetFlags();
} }
//******************************************************************************
int MXC_FLC_ClearFlags(uint32_t flags) int MXC_FLC_ClearFlags(uint32_t flags)
{ {
return MXC_FLC_RevB_ClearFlags(flags); return MXC_FLC_RevA_ClearFlags(flags);
} }
int MXC_FLC_UnlockInfoBlock(uint32_t address) //******************************************************************************
int MXC_FLC_BlockPageWrite(uint32_t address)
{ {
return MXC_FLC_ME15_UnlockInfoBlock(address); if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) {
return E_INVALID;
}
return MXC_FLC_RevA_BlockPageWrite(address, MXC_FLASH_MEM_BASE);
} }
int MXC_FLC_LockInfoBlock(uint32_t address) //******************************************************************************
int MXC_FLC_BlockPageRead(uint32_t address)
{ {
return MXC_FLC_ME15_LockInfoBlock(address); if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) {
return E_INVALID;
}
return MXC_FLC_RevA_BlockPageRead(address, MXC_FLASH_MEM_BASE);
}
//******************************************************************************
volatile uint32_t *MXC_FLC_GetWELR(uint32_t address, uint32_t page_num)
{
uint32_t reg_num;
reg_num = page_num >>
5; // Divide by 32 to get WELR register number containing the page lock bit
if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) {
return NULL;
}
switch (reg_num) {
case 0:
return &(MXC_FLC0->welr0);
case 1:
return &(MXC_FLC0->welr1);
}
return NULL;
}
//******************************************************************************
volatile uint32_t *MXC_FLC_GetRLR(uint32_t address, uint32_t page_num)
{
uint32_t reg_num;
reg_num = page_num >> 5; // Divide by 32 to get RLR register number containing the page lock bit
if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) {
return NULL;
}
switch (reg_num) {
case 0:
return &(MXC_FLC0->rlr0);
case 1:
return &(MXC_FLC0->rlr1);
}
return NULL;
} }

188
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva.c
View File

@ -3,8 +3,8 @@
* @brief Flash Controler driver. * @brief Flash Controler driver.
* @details This driver can be used to operate on the embedded flash memory. * @details This driver can be used to operate on the embedded flash memory.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
/* **** Includes **** */ /* **** Includes **** */
#include <string.h> #include <string.h>
@ -54,31 +53,32 @@
/* **** Globals **** */ /* **** Globals **** */
#ifdef MXC_FLC0 #ifdef MXC_FLC0
static mxc_flc_reva_regs_t *flc_int = (mxc_flc_reva_regs_t*) MXC_FLC0; static mxc_flc_reva_regs_t *flc_int = (mxc_flc_reva_regs_t *)MXC_FLC0;
#else #else
static mxc_flc_reva_regs_t *flc_int = (mxc_flc_reva_regs_t*) MXC_FLC; static mxc_flc_reva_regs_t *flc_int = (mxc_flc_reva_regs_t *)MXC_FLC;
#endif #endif
/* **** Functions **** */ /* **** Functions **** */
//****************************************************************************** //******************************************************************************
#if IAR_PRAGMAS #if IAR_PRAGMAS
#pragma section=".flashprog" #pragma section = ".flashprog"
#else #else
__attribute__((section(".flashprog"))) __attribute__((section(".flashprog")))
#endif #endif
static int MXC_busy_flc(mxc_flc_reva_regs_t* flc) static int MXC_busy_flc(mxc_flc_reva_regs_t *flc)
{ {
return (flc->ctrl & (MXC_F_FLC_REVA_CTRL_WR | MXC_F_FLC_REVA_CTRL_ME | MXC_F_FLC_REVA_CTRL_PGE)); return (flc->ctrl &
(MXC_F_FLC_REVA_CTRL_WR | MXC_F_FLC_REVA_CTRL_ME | MXC_F_FLC_REVA_CTRL_PGE));
} }
//****************************************************************************** //******************************************************************************
#if IAR_PRAGMAS #if IAR_PRAGMAS
#pragma section=".flashprog" #pragma section = ".flashprog"
#else #else
__attribute__((section(".flashprog"))) __attribute__((section(".flashprog")))
#endif #endif
static int MXC_prepare_flc(mxc_flc_reva_regs_t* flc) static int MXC_prepare_flc(mxc_flc_reva_regs_t *flc)
{ {
/* Check if the flash controller is busy */ /* Check if the flash controller is busy */
if (MXC_busy_flc(flc)) { if (MXC_busy_flc(flc)) {
@ -101,7 +101,7 @@ static int MXC_prepare_flc(mxc_flc_reva_regs_t* flc)
//****************************************************************************** //******************************************************************************
#if IAR_PRAGMAS #if IAR_PRAGMAS
#pragma section=".flashprog" #pragma section = ".flashprog"
#else #else
__attribute__((section(".flashprog"))) __attribute__((section(".flashprog")))
#endif #endif
@ -112,8 +112,8 @@ int MXC_FLC_RevA_Busy(void)
mxc_flc_reva_regs_t *flc; mxc_flc_reva_regs_t *flc;
for (i = 0; i < MXC_FLC_INSTANCES; i++) { for (i = 0; i < MXC_FLC_INSTANCES; i++) {
flc = (mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC (i); flc = (mxc_flc_reva_regs_t *)MXC_FLC_GET_FLC(i);
flc_cn = MXC_busy_flc (flc); flc_cn = MXC_busy_flc(flc);
if (flc_cn != 0) { if (flc_cn != 0) {
break; break;
@ -124,11 +124,11 @@ int MXC_FLC_RevA_Busy(void)
} }
//****************************************************************************** //******************************************************************************
#if IAR_PRAGMAS #if IAR_PRAGMAS
#pragma section=".flashprog" #pragma section = ".flashprog"
#else #else
__attribute__((section(".flashprog"))) __attribute__((section(".flashprog")))
#endif #endif
int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc) int MXC_FLC_RevA_MassErase(mxc_flc_reva_regs_t *flc)
{ {
int err; int err;
@ -137,13 +137,14 @@ int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc)
} }
/* Write mass erase code */ /* Write mass erase code */
flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL; flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) |
MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL;
/* Issue mass erase command */ /* Issue mass erase command */
flc->ctrl |= MXC_F_FLC_REVA_CTRL_ME; flc->ctrl |= MXC_F_FLC_REVA_CTRL_ME;
/* Wait until flash operation is complete */ /* Wait until flash operation is complete */
while (MXC_busy_flc(flc)); while (MXC_busy_flc(flc)) {}
/* Lock flash */ /* Lock flash */
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK; flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
@ -159,11 +160,11 @@ int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc)
//****************************************************************************** //******************************************************************************
#if IAR_PRAGMAS #if IAR_PRAGMAS
#pragma section=".flashprog" #pragma section = ".flashprog"
#else #else
__attribute__((section(".flashprog"))) __attribute__((section(".flashprog")))
#endif #endif
int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc, uint32_t addr) int MXC_FLC_RevA_PageErase(mxc_flc_reva_regs_t *flc, uint32_t addr)
{ {
int err; int err;
@ -172,13 +173,14 @@ int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc, uint32_t addr)
} }
/* Write page erase code */ /* Write page erase code */
flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE; flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) |
MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE;
/* Issue page erase command */ /* Issue page erase command */
flc->addr = addr; flc->addr = addr;
flc->ctrl |= MXC_F_FLC_REVA_CTRL_PGE; flc->ctrl |= MXC_F_FLC_REVA_CTRL_PGE;
/* Wait until flash operation is complete */ /* Wait until flash operation is complete */
while (MXC_FLC_Busy()); while (MXC_busy_flc(flc)) {}
/* Lock flash */ /* Lock flash */
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK; flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
@ -192,21 +194,17 @@ int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc, uint32_t addr)
return E_NO_ERROR; return E_NO_ERROR;
} }
//****************************************************************************** //******************************************************************************
#if IAR_PRAGMAS #if IAR_PRAGMAS
#pragma section=".flashprog" #pragma section = ".flashprog"
#else #else
__attribute__((section(".flashprog"))) __attribute__((section(".flashprog")))
#endif #endif
// make sure to disable ICC with ICC_Disable(); before Running this function // make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t* flc, uint32_t logicAddr, uint32_t data, uint32_t physicalAddr) int MXC_FLC_RevA_Write32(mxc_flc_reva_regs_t *flc, uint32_t logicAddr, uint32_t data,
uint32_t physicalAddr)
{ {
int err, i = 0; int err;
uint32_t byte;
volatile uint32_t* ptr;
uint32_t current_data[4] = {0, 0, 0, 0};
// Address checked if it is byte addressable // Address checked if it is byte addressable
if (logicAddr & 0x3) { if (logicAddr & 0x3) {
@ -214,7 +212,63 @@ int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t* flc, uint32_t logicAddr, uint32_t
} }
// Check if the location trying to be written has 1's in to be written to 0's // Check if the location trying to be written has 1's in to be written to 0's
if ((* (uint32_t*) logicAddr & data) != data) { if ((*(uint32_t *)logicAddr & data) != data) {
return E_BAD_STATE;
}
// Align address to 32-bit word
logicAddr = logicAddr & 0xfffffffc;
if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) {
return err;
}
// write 32-bits
flc->ctrl |= MXC_F_FLC_REVA_CTRL_WDTH;
// write the data
flc->addr = logicAddr;
flc->data[0] = data;
flc->ctrl |= MXC_F_FLC_REVA_CTRL_WR;
/* Wait until flash operation is complete */
while ((flc->ctrl & MXC_F_FLC_REVA_CTRL_PEND) != 0) {}
while (MXC_busy_flc(flc)) {}
/* Lock flash */
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
/* Check access violations */
if (flc->intr & MXC_F_FLC_REVA_INTR_AF) {
flc->intr &= ~MXC_F_FLC_REVA_INTR_AF;
return E_BAD_STATE;
}
return E_NO_ERROR;
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section = ".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
// make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_RevA_Write32Using128(mxc_flc_reva_regs_t *flc, uint32_t logicAddr, uint32_t data,
uint32_t physicalAddr)
{
int err, i = 0;
uint32_t byte;
volatile uint32_t *ptr;
uint32_t current_data[4] = { 0, 0, 0, 0 };
// Address checked if it is byte addressable
if (logicAddr & 0x3) {
return E_BAD_PARAM;
}
// Check if the location trying to be written has 1's in to be written to 0's
if ((*(uint32_t *)logicAddr & data) != data) {
return E_BAD_STATE; return E_BAD_STATE;
} }
@ -228,7 +282,7 @@ int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t* flc, uint32_t logicAddr, uint32_t
} }
// Get current data stored in flash // Get current data stored in flash
for (ptr = (uint32_t*) logicAddr; ptr < (uint32_t*)(logicAddr + 16); ptr++, i++) { for (ptr = (uint32_t *)logicAddr; ptr < (uint32_t *)(logicAddr + 16); ptr++, i++) {
current_data[i] = *ptr; current_data[i] = *ptr;
} }
@ -237,14 +291,11 @@ int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t* flc, uint32_t logicAddr, uint32_t
if (byte < 4) { if (byte < 4) {
current_data[0] = data; current_data[0] = data;
} } else if (byte < 8) {
else if (byte < 8) {
current_data[1] = data; current_data[1] = data;
} } else if (byte < 12) {
else if (byte < 12) {
current_data[2] = data; current_data[2] = data;
} } else {
else {
current_data[3] = data; current_data[3] = data;
} }
@ -253,12 +304,12 @@ int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t* flc, uint32_t logicAddr, uint32_t
//****************************************************************************** //******************************************************************************
#if IAR_PRAGMAS #if IAR_PRAGMAS
#pragma section=".flashprog" #pragma section = ".flashprog"
#else #else
__attribute__((section(".flashprog"))) __attribute__((section(".flashprog")))
#endif #endif
// make sure to disable ICC with ICC_Disable(); before Running this function // make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_RevA_Write128 (mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data) int MXC_FLC_RevA_Write128(mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data)
{ {
int err; int err;
@ -283,8 +334,8 @@ int MXC_FLC_RevA_Write128 (mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *da
flc->ctrl |= MXC_F_FLC_REVA_CTRL_WR; flc->ctrl |= MXC_F_FLC_REVA_CTRL_WR;
/* Wait until flash operation is complete */ /* Wait until flash operation is complete */
while ((flc->ctrl & MXC_F_FLC_REVA_CTRL_PEND)!=0){} while ((flc->ctrl & MXC_F_FLC_REVA_CTRL_PEND) != 0) {}
while (MXC_busy_flc (flc)){} while (MXC_busy_flc(flc)) {}
/* Lock flash */ /* Lock flash */
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK; flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
@ -305,7 +356,7 @@ void MXC_FLC_RevA_SetFLCInt(mxc_flc_reva_regs_t *flc)
} }
//****************************************************************************** //******************************************************************************
mxc_flc_reva_regs_t* MXC_FLC_RevA_GetFLCInt(void) mxc_flc_reva_regs_t *MXC_FLC_RevA_GetFLCInt(void)
{ {
return flc_int; return flc_int;
} }
@ -313,7 +364,7 @@ mxc_flc_reva_regs_t* MXC_FLC_RevA_GetFLCInt(void)
//****************************************************************************** //******************************************************************************
int MXC_FLC_RevA_EnableInt(uint32_t mask) int MXC_FLC_RevA_EnableInt(uint32_t mask)
{ {
mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE); mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE);
if (!mask) { if (!mask) {
/* No bits set? Wasn't something we can enable. */ /* No bits set? Wasn't something we can enable. */
@ -329,7 +380,7 @@ int MXC_FLC_RevA_EnableInt(uint32_t mask)
//****************************************************************************** //******************************************************************************
int MXC_FLC_RevA_DisableInt(uint32_t mask) int MXC_FLC_RevA_DisableInt(uint32_t mask)
{ {
mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE); mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE);
if (!mask) { if (!mask) {
/* No bits set? Wasn't something we can disable. */ /* No bits set? Wasn't something we can disable. */
@ -365,9 +416,10 @@ int MXC_FLC_RevA_ClearFlags(uint32_t mask)
} }
//****************************************************************************** //******************************************************************************
int MXC_FLC_RevA_UnlockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address) int MXC_FLC_RevA_UnlockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address)
{ {
if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) { if ((address < MXC_INFO_MEM_BASE) ||
(address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
@ -383,13 +435,51 @@ int MXC_FLC_RevA_UnlockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address)
} }
//****************************************************************************** //******************************************************************************
int MXC_FLC_RevA_LockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address) int MXC_FLC_RevA_LockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address)
{ {
if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) { if ((address < MXC_INFO_MEM_BASE) ||
(address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
return E_BAD_PARAM; return E_BAD_PARAM;
} }
flc->actrl = 0xDEADBEEF; flc->actrl = 0xDEADBEEF;
return E_NO_ERROR; return E_NO_ERROR;
} }
//******************************************************************************
int MXC_FLC_RevA_BlockPageWrite(uint32_t address, uint32_t bank_base)
{
uint32_t page_num;
page_num = address - bank_base; // Get page number in flash bank
page_num /= MXC_FLASH_PAGE_SIZE;
volatile uint32_t *welr = MXC_FLC_GetWELR(
address, page_num); // Get pointer to WELR register containing corresponding page bit
while (page_num > 31) { // Set corresponding bit in WELR register
page_num -= 32;
}
*welr = (1 << page_num);
return E_NO_ERROR;
}
//******************************************************************************
int MXC_FLC_RevA_BlockPageRead(uint32_t address, uint32_t bank_base)
{
uint32_t page_num;
page_num = address - bank_base; // Get page number in flash bank
page_num /= MXC_FLASH_PAGE_SIZE;
volatile uint32_t *rlr = MXC_FLC_GetRLR(
address, page_num); // Get pointer to RLR register containing corresponding page bit
while (page_num > 31) { // Set corresponding bit in WELR register
page_num -= 32;
}
*rlr = (1 << page_num);
return E_NO_ERROR;
}
/**@} end of group flc */ /**@} end of group flc */

53
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva.h
View File

@ -1,10 +1,10 @@
/** /**
* @file flc.h * @file flc_reva.h
* @brief Flash Controler driver. * @brief Flash RevA Controller driver.
* @details This driver can be used to operate on the embedded flash memory. * @details This driver can be used to operate on the embedded flash memory.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_H_
/* **** Includes **** */ /* **** Includes **** */
#include <string.h> #include <string.h>
@ -43,6 +45,7 @@
#include "mxc_assert.h" #include "mxc_assert.h"
#include "mxc_sys.h" #include "mxc_sys.h"
#include "flc.h" #include "flc.h"
#include "flc_common.h"
#include "flc_reva_regs.h" #include "flc_reva_regs.h"
/** /**
@ -56,34 +59,44 @@
/* **** Functions **** */ /* **** Functions **** */
int MXC_FLC_RevA_Busy (void); int MXC_FLC_RevA_Busy(void);
int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc); int MXC_FLC_RevA_MassErase(mxc_flc_reva_regs_t *flc);
int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc,uint32_t addr); int MXC_FLC_RevA_PageErase(mxc_flc_reva_regs_t *flc, uint32_t addr);
int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data, uint32_t physicalAddr); int MXC_FLC_RevA_Write32(mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data,
uint32_t physicalAddr);
int MXC_FLC_RevA_Write128 (mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data); int MXC_FLC_RevA_Write32Using128(mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data,
uint32_t physicalAddr);
void MXC_FLC_RevA_SetFLCInt (mxc_flc_reva_regs_t *flc); int MXC_FLC_RevA_Write128(mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data);
mxc_flc_reva_regs_t* MXC_FLC_RevA_GetFLCInt (void); void MXC_FLC_RevA_SetFLCInt(mxc_flc_reva_regs_t *flc);
int MXC_FLC_RevA_EnableInt (uint32_t mask); mxc_flc_reva_regs_t *MXC_FLC_RevA_GetFLCInt(void);
int MXC_FLC_RevA_DisableInt (uint32_t mask); int MXC_FLC_RevA_EnableInt(uint32_t mask);
int MXC_FLC_RevA_GetFlags (void); int MXC_FLC_RevA_DisableInt(uint32_t mask);
int MXC_FLC_RevA_ClearFlags (uint32_t mask); int MXC_FLC_RevA_GetFlags(void);
int MXC_FLC_RevA_UnlockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address); int MXC_FLC_RevA_ClearFlags(uint32_t mask);
int MXC_FLC_RevA_UnlockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address);
int MXC_FLC_RevA_LockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address);
int MXC_FLC_RevA_BlockPageWrite(uint32_t address, uint32_t bank_base);
int MXC_FLC_RevA_BlockPageRead(uint32_t address, uint32_t bank_base);
int MXC_FLC_RevA_LockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address);
/**@} end of group flc */ /**@} end of group flc */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_H_

123
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva_regs.h
View File

@ -3,8 +3,8 @@
* @brief Registers, Bit Masks and Bit Positions for the FLC_REVA Peripheral Module. * @brief Registers, Bit Masks and Bit Positions for the FLC_REVA Peripheral Module.
*/ */
/* **************************************************************************** /******************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all * property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights. * ownership rights.
* *
* ******************************************************************************/
*************************************************************************** */
#ifndef _FLC_REVA_REGS_H_ #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_
#define _FLC_REVA_REGS_H_ #define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_
/* **** Includes **** */ /* **** Includes **** */
#include <stdint.h> #include <stdint.h>
@ -48,11 +47,11 @@ extern "C" {
#endif #endif
#if defined (__ICCARM__) #if defined (__ICCARM__)
#pragma system_include #pragma system_include
#endif #endif
#if defined (__CC_ARM) #if defined (__CC_ARM)
#pragma anon_unions #pragma anon_unions
#endif #endif
/// @cond /// @cond
/* /*
@ -104,13 +103,13 @@ typedef struct {
* @brief FLC_REVA Peripheral Register Offsets from the FLC_REVA Base Peripheral Address. * @brief FLC_REVA Peripheral Register Offsets from the FLC_REVA Base Peripheral Address.
* @{ * @{
*/ */
#define MXC_R_FLC_REVA_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0000</tt> */ #define MXC_R_FLC_REVA_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0000</tt> */
#define MXC_R_FLC_REVA_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0004</tt> */ #define MXC_R_FLC_REVA_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0004</tt> */
#define MXC_R_FLC_REVA_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0008</tt> */ #define MXC_R_FLC_REVA_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0008</tt> */
#define MXC_R_FLC_REVA_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0024</tt> */ #define MXC_R_FLC_REVA_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0024</tt> */
#define MXC_R_FLC_REVA_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0028</tt> */ #define MXC_R_FLC_REVA_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0028</tt> */
#define MXC_R_FLC_REVA_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0030</tt> */ #define MXC_R_FLC_REVA_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0030</tt> */
#define MXC_R_FLC_REVA_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0040</tt> */ #define MXC_R_FLC_REVA_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0040</tt> */
/**@} end of group flc_reva_registers */ /**@} end of group flc_reva_registers */
/** /**
@ -119,8 +118,8 @@ typedef struct {
* @brief Flash Write Address. * @brief Flash Write Address.
* @{ * @{
*/ */
#define MXC_F_FLC_REVA_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ #define MXC_F_FLC_REVA_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
#define MXC_F_FLC_REVA_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ #define MXC_F_FLC_REVA_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
/**@} end of group FLC_REVA_ADDR_Register */ /**@} end of group FLC_REVA_ADDR_Register */
@ -131,8 +130,8 @@ typedef struct {
* MHz clock for Flash controller. * MHz clock for Flash controller.
* @{ * @{
*/ */
#define MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ #define MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
#define MXC_F_FLC_REVA_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ #define MXC_F_FLC_REVA_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
/**@} end of group FLC_REVA_CLKDIV_Register */ /**@} end of group FLC_REVA_CLKDIV_Register */
@ -142,39 +141,39 @@ typedef struct {
* @brief Flash Control Register. * @brief Flash Control Register.
* @{ * @{
*/ */
#define MXC_F_FLC_REVA_CTRL_WR_POS 0 /**< CTRL_WR Position */ #define MXC_F_FLC_REVA_CTRL_WR_POS 0 /**< CTRL_WR Position */
#define MXC_F_FLC_REVA_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WR_POS)) /**< CTRL_WR Mask */ #define MXC_F_FLC_REVA_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WR_POS)) /**< CTRL_WR Mask */
#define MXC_F_FLC_REVA_CTRL_ME_POS 1 /**< CTRL_ME Position */ #define MXC_F_FLC_REVA_CTRL_ME_POS 1 /**< CTRL_ME Position */
#define MXC_F_FLC_REVA_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_ME_POS)) /**< CTRL_ME Mask */ #define MXC_F_FLC_REVA_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_ME_POS)) /**< CTRL_ME Mask */
#define MXC_F_FLC_REVA_CTRL_PGE_POS 2 /**< CTRL_PGE Position */ #define MXC_F_FLC_REVA_CTRL_PGE_POS 2 /**< CTRL_PGE Position */
#define MXC_F_FLC_REVA_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PGE_POS)) /**< CTRL_PGE Mask */ #define MXC_F_FLC_REVA_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PGE_POS)) /**< CTRL_PGE Mask */
#define MXC_F_FLC_REVA_CTRL_WDTH_POS 4 /**< CTRL_WDTH Position */ #define MXC_F_FLC_REVA_CTRL_WDTH_POS 4 /**< CTRL_WDTH Position */
#define MXC_F_FLC_REVA_CTRL_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WDTH_POS)) /**< CTRL_WDTH Mask */ #define MXC_F_FLC_REVA_CTRL_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WDTH_POS)) /**< CTRL_WDTH Mask */
#define MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ #define MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */
#define MXC_F_FLC_REVA_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ #define MXC_F_FLC_REVA_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */
#define MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ #define MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */
#define MXC_S_FLC_REVA_CTRL_ERASE_CODE_NOP (MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ #define MXC_S_FLC_REVA_CTRL_ERASE_CODE_NOP (MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */
#define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ #define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */
#define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ #define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */
#define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ #define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */
#define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ #define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */
#define MXC_F_FLC_REVA_CTRL_PEND_POS 24 /**< CTRL_PEND Position */ #define MXC_F_FLC_REVA_CTRL_PEND_POS 24 /**< CTRL_PEND Position */
#define MXC_F_FLC_REVA_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PEND_POS)) /**< CTRL_PEND Mask */ #define MXC_F_FLC_REVA_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PEND_POS)) /**< CTRL_PEND Mask */
#define MXC_F_FLC_REVA_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ #define MXC_F_FLC_REVA_CTRL_LVE_POS 25 /**< CTRL_LVE Position */
#define MXC_F_FLC_REVA_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ #define MXC_F_FLC_REVA_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_LVE_POS)) /**< CTRL_LVE Mask */
#define MXC_F_FLC_REVA_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */ #define MXC_F_FLC_REVA_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */
#define MXC_F_FLC_REVA_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_REVA_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */ #define MXC_F_FLC_REVA_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_REVA_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */
#define MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */ #define MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */
#define MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */ #define MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */
#define MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */ #define MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */
#define MXC_S_FLC_REVA_CTRL_UNLOCK_LOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */ #define MXC_S_FLC_REVA_CTRL_UNLOCK_LOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */
/**@} end of group FLC_REVA_CTRL_Register */ /**@} end of group FLC_REVA_CTRL_Register */
@ -184,17 +183,17 @@ typedef struct {
* @brief Flash Interrupt Register. * @brief Flash Interrupt Register.
* @{ * @{
*/ */
#define MXC_F_FLC_REVA_INTR_DONE_POS 0 /**< INTR_DONE Position */ #define MXC_F_FLC_REVA_INTR_DONE_POS 0 /**< INTR_DONE Position */
#define MXC_F_FLC_REVA_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONE_POS)) /**< INTR_DONE Mask */ #define MXC_F_FLC_REVA_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONE_POS)) /**< INTR_DONE Mask */
#define MXC_F_FLC_REVA_INTR_AF_POS 1 /**< INTR_AF Position */ #define MXC_F_FLC_REVA_INTR_AF_POS 1 /**< INTR_AF Position */
#define MXC_F_FLC_REVA_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AF_POS)) /**< INTR_AF Mask */ #define MXC_F_FLC_REVA_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AF_POS)) /**< INTR_AF Mask */
#define MXC_F_FLC_REVA_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ #define MXC_F_FLC_REVA_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */
#define MXC_F_FLC_REVA_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ #define MXC_F_FLC_REVA_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
#define MXC_F_FLC_REVA_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ #define MXC_F_FLC_REVA_INTR_AFIE_POS 9 /**< INTR_AFIE Position */
#define MXC_F_FLC_REVA_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ #define MXC_F_FLC_REVA_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
/**@} end of group FLC_REVA_INTR_Register */ /**@} end of group FLC_REVA_INTR_Register */
@ -204,11 +203,11 @@ typedef struct {
* @brief ECC Data Register. * @brief ECC Data Register.
* @{ * @{
*/ */
#define MXC_F_FLC_REVA_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */ #define MXC_F_FLC_REVA_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */
#define MXC_F_FLC_REVA_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */ #define MXC_F_FLC_REVA_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */
#define MXC_F_FLC_REVA_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */ #define MXC_F_FLC_REVA_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */
#define MXC_F_FLC_REVA_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */ #define MXC_F_FLC_REVA_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */
/**@} end of group FLC_REVA_ECCDATA_Register */ /**@} end of group FLC_REVA_ECCDATA_Register */
@ -218,8 +217,8 @@ typedef struct {
* @brief Flash Write Data. * @brief Flash Write Data.
* @{ * @{
*/ */
#define MXC_F_FLC_REVA_DATA_DATA_POS 0 /**< DATA_DATA Position */ #define MXC_F_FLC_REVA_DATA_DATA_POS 0 /**< DATA_DATA Position */
#define MXC_F_FLC_REVA_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_DATA_DATA_POS)) /**< DATA_DATA Mask */ #define MXC_F_FLC_REVA_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_DATA_DATA_POS)) /**< DATA_DATA Mask */
/**@} end of group FLC_REVA_DATA_Register */ /**@} end of group FLC_REVA_DATA_Register */
@ -234,8 +233,8 @@ typedef struct {
* this register is always zero. * this register is always zero.
* @{ * @{
*/ */
#define MXC_F_FLC_REVA_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ #define MXC_F_FLC_REVA_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */
#define MXC_F_FLC_REVA_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ #define MXC_F_FLC_REVA_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */
/**@} end of group FLC_REVA_ACTRL_Register */ /**@} end of group FLC_REVA_ACTRL_Register */
@ -243,4 +242,4 @@ typedef struct {
} }
#endif #endif
#endif /* _FLC_REVA_REGS_H_ */ #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_

154
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_revb.c
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@ -1,154 +0,0 @@
/**
* @file flc.h
* @brief Flash Controler driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
/* **** Includes **** */
#include <string.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "flc.h"
#include "flc_revb.h"
#include "flc_reva.h"
/**
* @ingroup flc
* @{
*/
/* **** Definitions **** */
/* **** Globals **** */
/* **** Functions **** */
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
int MXC_FLC_RevB_Busy(void)
{
return MXC_FLC_RevA_Busy();
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
int MXC_FLC_RevB_MassErase(mxc_flc_revb_regs_t* flc)
{
return MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t*)flc);
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
int MXC_FLC_RevB_PageErase(mxc_flc_revb_regs_t* flc, uint32_t addr)
{
return MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t*)flc,addr);
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
// make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_RevB_Write32(mxc_flc_revb_regs_t* flc, uint32_t logicAddr, uint32_t data, uint32_t physicalAddr)
{
return MXC_FLC_RevA_Write32((mxc_flc_reva_regs_t*)flc, logicAddr, data, physicalAddr);
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
// make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_RevB_Write128(mxc_flc_revb_regs_t* flc, uint32_t addr, uint32_t* data)
{
return MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t*)flc, addr, data);
}
//******************************************************************************
int MXC_FLC_RevB_EnableInt(uint32_t mask)
{
return MXC_FLC_RevA_EnableInt(mask);
}
//******************************************************************************
int MXC_FLC_RevB_DisableInt(uint32_t mask)
{
return MXC_FLC_RevA_DisableInt(mask);
}
//******************************************************************************
int MXC_FLC_RevB_GetFlags(void)
{
return MXC_FLC_RevA_GetFlags();
}
//******************************************************************************
int MXC_FLC_RevB_ClearFlags(uint32_t mask)
{
return MXC_FLC_RevA_ClearFlags(mask);
}
//******************************************************************************
int MXC_FLC_RevB_UnlockInfoBlock(mxc_flc_revb_regs_t* flc, uint32_t address)
{
return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t*)flc, address);
}
//******************************************************************************
int MXC_FLC_RevB_LockInfoBlock(mxc_flc_revb_regs_t* flc, uint32_t address)
{
return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t*)flc, address);
}
/**@} end of group flc */

85
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_revb.h
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@ -1,85 +0,0 @@
/**
* @file flc.h
* @brief Flash Controler driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
/* **** Includes **** */
#include <string.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "flc_revb_regs.h"
#include "mcr_regs.h" // For ECCEN registers.
/**
* @ingroup flc
* @{
*/
/* **** Definitions **** */
/* **** Globals **** */
/* **** Functions **** */
int MXC_FLC_RevB_Busy (void);
int MXC_FLC_RevB_MassErase (mxc_flc_revb_regs_t *flc);
int MXC_FLC_RevB_PageErase (mxc_flc_revb_regs_t *flc,uint32_t addr);
int MXC_FLC_RevB_Write32 (mxc_flc_revb_regs_t *flc, uint32_t locgialAddr, uint32_t data, uint32_t physicalAddr);
int MXC_FLC_RevB_Write128 (mxc_flc_revb_regs_t *flc, uint32_t addr, uint32_t *data);
int MXC_FLC_RevB_EnableInt (uint32_t mask);
int MXC_FLC_RevB_DisableInt (uint32_t mask);
int MXC_FLC_RevB_GetFlags (void);
int MXC_FLC_RevB_ClearFlags (uint32_t mask);
int MXC_FLC_RevB_UnlockInfoBlock (mxc_flc_revb_regs_t *flc, uint32_t address);
int MXC_FLC_RevB_LockInfoBlock (mxc_flc_revb_regs_t *flc, uint32_t address);
/**@} end of group flc */
#ifdef __cplusplus
}
#endif

301
targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_revb_regs.h
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@ -1,301 +0,0 @@
/**
* @file flc_revb_regs.h
* @brief Registers, Bit Masks and Bit Positions for the FLC_REVB Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
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#ifndef _FLC_REVB_REGS_H_
#define _FLC_REVB_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup flc_revb
* @defgroup flc_revb_registers FLC_REVB_Registers
* @brief Registers, Bit Masks and Bit Positions for the FLC_REVB Peripheral Module.
* @details Flash Memory Control.
*/
/**
* @ingroup flc_revb_registers
* Structure type to access the FLC_REVB Registers.
*/
typedef struct {
__IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC_REVB ADDR Register */
__IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC_REVB CLKDIV Register */
__IO uint32_t ctrl; /**< <tt>\b 0x08:</tt> FLC_REVB CTRL Register */
__R uint32_t rsv_0xc_0x23[6];
__IO uint32_t intr; /**< <tt>\b 0x024:</tt> FLC_REVB INTR Register */
__IO uint32_t eccdata; /**< <tt>\b 0x028:</tt> FLC_REVB ECCDATA Register */
__R uint32_t rsv_0x2c;
__IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC_REVB DATA Register */
__O uint32_t actrl; /**< <tt>\b 0x40:</tt> FLC_REVB ACTRL Register */
__R uint32_t rsv_0x44_0x7f[15];
__IO uint32_t welr0; /**< <tt>\b 0x80:</tt> FLC_REVB WELR0 Register */
__R uint32_t rsv_0x84;
__IO uint32_t welr1; /**< <tt>\b 0x88:</tt> FLC_REVB WELR1 Register */
__R uint32_t rsv_0x8c;
__IO uint32_t rlr0; /**< <tt>\b 0x90:</tt> FLC_REVB RLR0 Register */
__R uint32_t rsv_0x94;
__IO uint32_t rlr1; /**< <tt>\b 0x98:</tt> FLC_REVB RLR1 Register */
} mxc_flc_revb_regs_t;
/* Register offsets for module FLC_REVB */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_Register_Offsets Register Offsets
* @brief FLC_REVB Peripheral Register Offsets from the FLC_REVB Base Peripheral Address.
* @{
*/
#define MXC_R_FLC_REVB_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0000</tt> */
#define MXC_R_FLC_REVB_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0004</tt> */
#define MXC_R_FLC_REVB_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0008</tt> */
#define MXC_R_FLC_REVB_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0024</tt> */
#define MXC_R_FLC_REVB_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0028</tt> */
#define MXC_R_FLC_REVB_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0030</tt> */
#define MXC_R_FLC_REVB_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0040</tt> */
#define MXC_R_FLC_REVB_WELR0 ((uint32_t)0x00000080UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0080</tt> */
#define MXC_R_FLC_REVB_WELR1 ((uint32_t)0x00000088UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0088</tt> */
#define MXC_R_FLC_REVB_RLR0 ((uint32_t)0x00000090UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0090</tt> */
#define MXC_R_FLC_REVB_RLR1 ((uint32_t)0x00000098UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0098</tt> */
/**@} end of group flc_revb_registers */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_ADDR FLC_REVB_ADDR
* @brief Flash Write Address.
* @{
*/
#define MXC_F_FLC_REVB_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
#define MXC_F_FLC_REVB_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
/**@} end of group FLC_REVB_ADDR_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_CLKDIV FLC_REVB_CLKDIV
* @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1
* MHz clock for Flash controller.
* @{
*/
#define MXC_F_FLC_REVB_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
#define MXC_F_FLC_REVB_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_REVB_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
/**@} end of group FLC_REVB_CLKDIV_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_CTRL FLC_REVB_CTRL
* @brief Flash Control Register.
* @{
*/
#define MXC_F_FLC_REVB_CTRL_WR_POS 0 /**< CTRL_WR Position */
#define MXC_F_FLC_REVB_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_WR_POS)) /**< CTRL_WR Mask */
#define MXC_F_FLC_REVB_CTRL_ME_POS 1 /**< CTRL_ME Position */
#define MXC_F_FLC_REVB_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_ME_POS)) /**< CTRL_ME Mask */
#define MXC_F_FLC_REVB_CTRL_PGE_POS 2 /**< CTRL_PGE Position */
#define MXC_F_FLC_REVB_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_PGE_POS)) /**< CTRL_PGE Mask */
#define MXC_F_FLC_REVB_CTRL_WDTH_POS 4 /**< CTRL_WDTH Position */
#define MXC_F_FLC_REVB_CTRL_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_WDTH_POS)) /**< CTRL_WDTH Mask */
#define MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */
#define MXC_F_FLC_REVB_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */
#define MXC_V_FLC_REVB_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */
#define MXC_S_FLC_REVB_CTRL_ERASE_CODE_NOP (MXC_V_FLC_REVB_CTRL_ERASE_CODE_NOP << MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */
#define MXC_V_FLC_REVB_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */
#define MXC_S_FLC_REVB_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_REVB_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */
#define MXC_V_FLC_REVB_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */
#define MXC_S_FLC_REVB_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_REVB_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */
#define MXC_F_FLC_REVB_CTRL_PEND_POS 24 /**< CTRL_PEND Position */
#define MXC_F_FLC_REVB_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_PEND_POS)) /**< CTRL_PEND Mask */
#define MXC_F_FLC_REVB_CTRL_LVE_POS 25 /**< CTRL_LVE Position */
#define MXC_F_FLC_REVB_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_LVE_POS)) /**< CTRL_LVE Mask */
#define MXC_F_FLC_REVB_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */
#define MXC_F_FLC_REVB_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_REVB_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */
#define MXC_V_FLC_REVB_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */
#define MXC_S_FLC_REVB_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_REVB_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_REVB_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */
#define MXC_V_FLC_REVB_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */
#define MXC_S_FLC_REVB_CTRL_UNLOCK_LOCKED (MXC_V_FLC_REVB_CTRL_UNLOCK_LOCKED << MXC_F_FLC_REVB_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */
/**@} end of group FLC_REVB_CTRL_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_INTR FLC_REVB_INTR
* @brief Flash Interrupt Register.
* @{
*/
#define MXC_F_FLC_REVB_INTR_DONE_POS 0 /**< INTR_DONE Position */
#define MXC_F_FLC_REVB_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_REVB_INTR_DONE_POS)) /**< INTR_DONE Mask */
#define MXC_F_FLC_REVB_INTR_AF_POS 1 /**< INTR_AF Position */
#define MXC_F_FLC_REVB_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_REVB_INTR_AF_POS)) /**< INTR_AF Mask */
#define MXC_F_FLC_REVB_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */
#define MXC_F_FLC_REVB_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_REVB_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
#define MXC_F_FLC_REVB_INTR_AFIE_POS 9 /**< INTR_AFIE Position */
#define MXC_F_FLC_REVB_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_REVB_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
/**@} end of group FLC_REVB_INTR_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_ECCDATA FLC_REVB_ECCDATA
* @brief ECC Data Register.
* @{
*/
#define MXC_F_FLC_REVB_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */
#define MXC_F_FLC_REVB_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_REVB_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */
#define MXC_F_FLC_REVB_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */
#define MXC_F_FLC_REVB_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_REVB_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */
/**@} end of group FLC_REVB_ECCDATA_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_DATA FLC_REVB_DATA
* @brief Flash Write Data.
* @{
*/
#define MXC_F_FLC_REVB_DATA_DATA_POS 0 /**< DATA_DATA Position */
#define MXC_F_FLC_REVB_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_DATA_DATA_POS)) /**< DATA_DATA Mask */
/**@} end of group FLC_REVB_DATA_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_ACTRL FLC_REVB_ACTRL
* @brief Access Control Register. Writing the ACTRL register with the following values in
* the order shown, allows read and write access to the system and user Information
* block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = 0xa1e34f20; pflc-actrl
* = 0x9608b2c1. When unlocked, a write of any word will disable access to system
* and user information block. Readback of this register is always zero.
* @{
*/
#define MXC_F_FLC_REVB_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */
#define MXC_F_FLC_REVB_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */
/**@} end of group FLC_REVB_ACTRL_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_WELR0 FLC_REVB_WELR0
* @brief WELR0
* @{
*/
#define MXC_F_FLC_REVB_WELR0_WELR0_POS 0 /**< WELR0_WELR0 Position */
#define MXC_F_FLC_REVB_WELR0_WELR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_WELR0_WELR0_POS)) /**< WELR0_WELR0 Mask */
/**@} end of group FLC_REVB_WELR0_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_WELR1 FLC_REVB_WELR1
* @brief WELR1
* @{
*/
#define MXC_F_FLC_REVB_WELR1_WELR1_POS 0 /**< WELR1_WELR1 Position */
#define MXC_F_FLC_REVB_WELR1_WELR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_WELR1_WELR1_POS)) /**< WELR1_WELR1 Mask */
/**@} end of group FLC_REVB_WELR1_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_RLR0 FLC_REVB_RLR0
* @brief RLR0
* @{
*/
#define MXC_F_FLC_REVB_RLR0_RLR0_POS 0 /**< RLR0_RLR0 Position */
#define MXC_F_FLC_REVB_RLR0_RLR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_RLR0_RLR0_POS)) /**< RLR0_RLR0 Mask */
/**@} end of group FLC_REVB_RLR0_Register */
/**
* @ingroup flc_revb_registers
* @defgroup FLC_REVB_RLR1 FLC_REVB_RLR1
* @brief RLR1
* @{
*/
#define MXC_F_FLC_REVB_RLR1_RLR1_POS 0 /**< RLR1_RLR1 Position */
#define MXC_F_FLC_REVB_RLR1_RLR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_RLR1_RLR1_POS)) /**< RLR1_RLR1 Mask */
/**@} end of group FLC_REVB_RLR1_Register */
#ifdef __cplusplus
}
#endif
#endif /* _FLC_REVB_REGS_H_ */

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