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Update MAX32660 peripheral drivers with final ones that use by SDK

pull/15421/head
Ahmet Polat 2023-04-26 14:37:03 +03:00 committed by Sadik.Ozer
parent d0ca14e4fe
commit 3f4b177128
103 changed files with 7939 additions and 6898 deletions
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62
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h
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@ -1,10 +1,11 @@
/**
* @file dma_regs.h
* @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _DMA_REGS_H_
#define _DMA_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_DMA_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_DMA_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -67,7 +67,9 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
@ -79,29 +81,25 @@ extern "C" {
* @details DMA Controller Fully programmable, chaining capable DMA channels.
*/
/**
* @ingroup dma_registers
* Structure type to access the DMA Channel Registers.
*/
typedef struct {
__IO uint32_t cfg; /**< <tt>\b 0x100:</tt> DMA CFG Register */
__IO uint32_t stat; /**< <tt>\b 0x104:</tt> DMA STAT Register */
__IO uint32_t src; /**< <tt>\b 0x108:</tt> DMA SRC Register */
__IO uint32_t dst; /**< <tt>\b 0x10C:</tt> DMA DST Register */
__IO uint32_t cnt; /**< <tt>\b 0x110:</tt> DMA CNT Register */
__IO uint32_t src_rld; /**< <tt>\b 0x114:</tt> DMA SRC_RLD Register */
__IO uint32_t dst_rld; /**< <tt>\b 0x118:</tt> DMA DST_RLD Register */
__IO uint32_t cnt_rld; /**< <tt>\b 0x11C:</tt> DMA CNT_RLD Register */
} mxc_dma_ch_regs_t;
/**
* @ingroup dma_registers
* Structure type to access the DMA Registers.
*/
typedef struct {
__IO uint32_t cfg; /**< <tt>\b 0x000:</tt> DMA CFG Register */
__IO uint32_t stat; /**< <tt>\b 0x004:</tt> DMA STAT Register */
__IO uint32_t src; /**< <tt>\b 0x008:</tt> DMA SRC Register */
__IO uint32_t dst; /**< <tt>\b 0x00C:</tt> DMA DST Register */
__IO uint32_t cnt; /**< <tt>\b 0x010:</tt> DMA CNT Register */
__IO uint32_t src_rld; /**< <tt>\b 0x014:</tt> DMA SRC_RLD Register */
__IO uint32_t dst_rld; /**< <tt>\b 0x018:</tt> DMA DST_RLD Register */
__IO uint32_t cnt_rld; /**< <tt>\b 0x01C:</tt> DMA CNT_RLD Register */
} mxc_dma_ch_regs_t;
typedef struct {
__IO uint32_t int_en; /**< <tt>\b 0x000:</tt> DMA INT_EN Register */
__I uint32_t int_fl; /**< <tt>\b 0x004:</tt> DMA INT_FL Register */
__I uint32_t rsv_0x8_0xff[62];
__R uint32_t rsv_0x8_0xff[62];
__IO mxc_dma_ch_regs_t ch[4]; /**< <tt>\b 0x100:</tt> DMA CH Register */
} mxc_dma_regs_t;
@ -112,14 +110,14 @@ typedef struct {
* @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address.
* @{
*/
#define MXC_R_DMA_CFG ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
#define MXC_R_DMA_STAT ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */
#define MXC_R_DMA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */
#define MXC_R_DMA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */
#define MXC_R_DMA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */
#define MXC_R_DMA_SRC_RLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */
#define MXC_R_DMA_DST_RLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */
#define MXC_R_DMA_CNT_RLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */
#define MXC_R_DMA_CFG ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */
#define MXC_R_DMA_STAT ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */
#define MXC_R_DMA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: <tt> 0x0008</tt> */
#define MXC_R_DMA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: <tt> 0x000C</tt> */
#define MXC_R_DMA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: <tt> 0x0010</tt> */
#define MXC_R_DMA_SRC_RLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: <tt> 0x0014</tt> */
#define MXC_R_DMA_DST_RLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: <tt> 0x0018</tt> */
#define MXC_R_DMA_CNT_RLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: <tt> 0x001C</tt> */
#define MXC_R_DMA_INT_EN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */
#define MXC_R_DMA_INT_FL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */
#define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
@ -387,4 +385,4 @@ typedef struct {
}
#endif
#endif /* _DMA_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_DMA_REGS_H_

18
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h
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@ -1,10 +1,11 @@
/**
* @file fcr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _FCR_REGS_H_
#define _FCR_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FCR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FCR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -67,7 +67,9 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
@ -121,4 +123,4 @@ typedef struct {
}
#endif
#endif /* _FCR_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FCR_REGS_H_

22
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h
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@ -1,10 +1,11 @@
/**
* @file flc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _FLC_REGS_H_
#define _FLC_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FLC_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FLC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -67,7 +67,9 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
@ -87,9 +89,9 @@ typedef struct {
__IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC ADDR Register */
__IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC CLKDIV Register */
__IO uint32_t ctrl; /**< <tt>\b 0x08:</tt> FLC CTRL Register */
__I uint32_t rsv_0xc_0x23[6];
__R uint32_t rsv_0xc_0x23[6];
__IO uint32_t intr; /**< <tt>\b 0x024:</tt> FLC INTR Register */
__I uint32_t rsv_0x28_0x2f[2];
__R uint32_t rsv_0x28_0x2f[2];
__IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC DATA Register */
__O uint32_t actrl; /**< <tt>\b 0x40:</tt> FLC ACTRL Register */
} mxc_flc_regs_t;
@ -225,4 +227,4 @@ typedef struct {
}
#endif
#endif /* _FLC_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FLC_REGS_H_

22
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h
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@ -1,10 +1,11 @@
/**
* @file gcr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _GCR_REGS_H_
#define _GCR_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GCR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GCR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -67,7 +67,9 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
@ -88,11 +90,11 @@ typedef struct {
__IO uint32_t rst0; /**< <tt>\b 0x04:</tt> GCR RST0 Register */
__IO uint32_t clk_ctrl; /**< <tt>\b 0x08:</tt> GCR CLK_CTRL Register */
__IO uint32_t pm; /**< <tt>\b 0x0C:</tt> GCR PM Register */
__I uint32_t rsv_0x10_0x23[5];
__R uint32_t rsv_0x10_0x23[5];
__IO uint32_t pclk_dis0; /**< <tt>\b 0x24:</tt> GCR PCLK_DIS0 Register */
__IO uint32_t mem_ctrl; /**< <tt>\b 0x28:</tt> GCR MEM_CTRL Register */
__IO uint32_t mem_zctrl; /**< <tt>\b 0x2C:</tt> GCR MEM_ZCTRL Register */
__I uint32_t rsv_0x30_0x3f[4];
__R uint32_t rsv_0x30_0x3f[4];
__IO uint32_t sys_stat; /**< <tt>\b 0x40:</tt> GCR SYS_STAT Register */
__IO uint32_t rst1; /**< <tt>\b 0x44:</tt> GCR RST1 Register */
__IO uint32_t pclk_dis1; /**< <tt>\b 0x48:</tt> GCR PCLK_DIS1 Register */
@ -433,4 +435,4 @@ typedef struct {
}
#endif
#endif /* _GCR_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GCR_REGS_H_

58
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h
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@ -1,10 +1,11 @@
/**
* @file gpio_regs.h
* @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _GPIO_REGS_H_
#define _GPIO_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GPIO_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GPIO_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -67,7 +67,9 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
@ -100,13 +102,13 @@ typedef struct {
__IO uint32_t int_en; /**< <tt>\b 0x34:</tt> GPIO INT_EN Register */
__IO uint32_t int_en_set; /**< <tt>\b 0x38:</tt> GPIO INT_EN_SET Register */
__IO uint32_t int_en_clr; /**< <tt>\b 0x3C:</tt> GPIO INT_EN_CLR Register */
__IO uint32_t int_stat; /**< <tt>\b 0x40:</tt> GPIO INT_STAT Register */
__I uint32_t rsv_0x44;
__I uint32_t int_stat; /**< <tt>\b 0x40:</tt> GPIO INT_STAT Register */
__R uint32_t rsv_0x44;
__IO uint32_t int_clr; /**< <tt>\b 0x48:</tt> GPIO INT_CLR Register */
__IO uint32_t wake_en; /**< <tt>\b 0x4C:</tt> GPIO WAKE_EN Register */
__IO uint32_t wake_en_set; /**< <tt>\b 0x50:</tt> GPIO WAKE_EN_SET Register */
__IO uint32_t wake_en_clr; /**< <tt>\b 0x54:</tt> GPIO WAKE_EN_CLR Register */
__I uint32_t rsv_0x58;
__R uint32_t rsv_0x58;
__IO uint32_t int_dual_edge; /**< <tt>\b 0x5C:</tt> GPIO INT_DUAL_EDGE Register */
__IO uint32_t pad_cfg1; /**< <tt>\b 0x60:</tt> GPIO PAD_CFG1 Register */
__IO uint32_t pad_cfg2; /**< <tt>\b 0x64:</tt> GPIO PAD_CFG2 Register */
@ -116,13 +118,13 @@ typedef struct {
__IO uint32_t en2; /**< <tt>\b 0x74:</tt> GPIO EN2 Register */
__IO uint32_t en2_set; /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */
__IO uint32_t en2_clr; /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */
__I uint32_t rsv_0x80_0xa7[10];
__R uint32_t rsv_0x80_0xa7[10];
__IO uint32_t is; /**< <tt>\b 0xA8:</tt> GPIO IS Register */
__IO uint32_t sr; /**< <tt>\b 0xAC:</tt> GPIO SR Register */
__IO uint32_t ds0; /**< <tt>\b 0xB0:</tt> GPIO DS0 Register */
__IO uint32_t ds1; /**< <tt>\b 0xB4:</tt> GPIO DS1 Register */
__IO uint32_t ps; /**< <tt>\b 0xB8:</tt> GPIO PS Register */
__I uint32_t rsv_0xbc;
__R uint32_t rsv_0xbc;
__IO uint32_t vssel; /**< <tt>\b 0xC0:</tt> GPIO VSSEL Register */
} mxc_gpio_regs_t;
@ -174,7 +176,7 @@ typedef struct {
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN0 GPIO_EN0
* @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one
* @brief GPIO Function Enable 0 Register. Each bit controls the GPIO_EN setting for one
* GPIO pin on the associated port.
* @{
*/
@ -190,7 +192,7 @@ typedef struct {
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN0_SET GPIO_EN0_SET
* @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this
* @brief GPIO Set Function Enable 0 Register. Writing a 1 to one or more bits in this
* register sets the bits in the same positions in GPIO_EN to 1, without affecting
* other bits in that register.
* @{
@ -618,6 +620,32 @@ typedef struct {
/**@} end of group GPIO_EN2_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_IS GPIO_IS
* @brief GPIO Input Hysteresis Enable.
* @{
*/
#define MXC_F_GPIO_IS_ALL_POS 0 /**< IS_ALL Position */
#define MXC_F_GPIO_IS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IS_ALL_POS)) /**< IS_ALL Mask */
/**@} end of group GPIO_IS_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_SR GPIO_SR
* @brief GPIO Slew Rate Enable Register.
* @{
*/
#define MXC_F_GPIO_SR_ALL_POS 0 /**< SR_ALL Position */
#define MXC_F_GPIO_SR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_SR_ALL_POS)) /**< SR_ALL Mask */
#define MXC_V_GPIO_SR_ALL_FAST ((uint32_t)0x0UL) /**< SR_ALL_FAST Value */
#define MXC_S_GPIO_SR_ALL_FAST (MXC_V_GPIO_SR_ALL_FAST << MXC_F_GPIO_SR_ALL_POS) /**< SR_ALL_FAST Setting */
#define MXC_V_GPIO_SR_ALL_SLOW ((uint32_t)0x1UL) /**< SR_ALL_SLOW Value */
#define MXC_S_GPIO_SR_ALL_SLOW (MXC_V_GPIO_SR_ALL_SLOW << MXC_F_GPIO_SR_ALL_POS) /**< SR_ALL_SLOW Setting */
/**@} end of group GPIO_SR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_DS0 GPIO_DS0
@ -674,4 +702,4 @@ typedef struct {
}
#endif
#endif /* _GPIO_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GPIO_REGS_H_

30
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h
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@ -1,10 +1,11 @@
/**
* @file i2c_regs.h
* @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _I2C_REGS_H_
#define _I2C_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_I2C_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_I2C_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -67,7 +67,9 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
@ -296,6 +298,9 @@ typedef struct {
#define MXC_F_I2C_INTFL0_TXLOI_POS 15 /**< INTFL0_TXLOI Position */
#define MXC_F_I2C_INTFL0_TXLOI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TXLOI_POS)) /**< INTFL0_TXLOI Mask */
#define MXC_F_I2C_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */
#define MXC_F_I2C_INTFL0_MAMI ((uint32_t)(0xFUL << MXC_F_I2C_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */
/**@} end of group I2C_INTFL0_Register */
/**
@ -352,6 +357,9 @@ typedef struct {
#define MXC_F_I2C_INTEN0_TXLOIE_POS 15 /**< INTEN0_TXLOIE Position */
#define MXC_F_I2C_INTEN0_TXLOIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXLOIE_POS)) /**< INTEN0_TXLOIE Mask */
#define MXC_F_I2C_INTEN0_MAMIE_POS 16 /**< INTEN0_MAMIE Position */
#define MXC_F_I2C_INTEN0_MAMIE ((uint32_t)(0xFUL << MXC_F_I2C_INTEN0_MAMIE_POS)) /**< INTEN0_MAMIE Mask */
/**@} end of group I2C_INTEN0_Register */
/**
@ -560,6 +568,12 @@ typedef struct {
#define MXC_F_I2C_SLADDR_SLA_POS 0 /**< SLADDR_SLA Position */
#define MXC_F_I2C_SLADDR_SLA ((uint32_t)(0x3FFUL << MXC_F_I2C_SLADDR_SLA_POS)) /**< SLADDR_SLA Mask */
#define MXC_F_I2C_SLADDR_SLADIS_POS 10 /**< SLADDR_SLADIS Position */
#define MXC_F_I2C_SLADDR_SLADIS ((uint32_t)(0x1UL << MXC_F_I2C_SLADDR_SLADIS_POS)) /**< SLADDR_SLADIS Mask */
#define MXC_F_I2C_SLADDR_SLAIDX_POS 11 /**< SLADDR_SLAIDX Position */
#define MXC_F_I2C_SLADDR_SLAIDX ((uint32_t)(0xFUL << MXC_F_I2C_SLADDR_SLAIDX_POS)) /**< SLADDR_SLAIDX Mask */
#define MXC_F_I2C_SLADDR_EA_POS 15 /**< SLADDR_EA Position */
#define MXC_F_I2C_SLADDR_EA ((uint32_t)(0x1UL << MXC_F_I2C_SLADDR_EA_POS)) /**< SLADDR_EA Mask */
@ -583,4 +597,4 @@ typedef struct {
}
#endif
#endif /* _I2C_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_I2C_REGS_H_

22
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file icc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _ICC_REGS_H_
#define _ICC_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_ICC_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_ICC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -67,7 +67,9 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
@ -86,9 +88,9 @@ extern "C" {
typedef struct {
__I uint32_t cache_id; /**< <tt>\b 0x0000:</tt> ICC CACHE_ID Register */
__I uint32_t mem_size; /**< <tt>\b 0x0004:</tt> ICC MEM_SIZE Register */
__I uint32_t rsv_0x8_0xff[62];
__R uint32_t rsv_0x8_0xff[62];
__IO uint32_t cache_ctrl; /**< <tt>\b 0x0100:</tt> ICC CACHE_CTRL Register */
__I uint32_t rsv_0x104_0x6ff[383];
__R uint32_t rsv_0x104_0x6ff[383];
__IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> ICC INVALIDATE Register */
} mxc_icc_regs_t;
@ -154,4 +156,4 @@ typedef struct {
}
#endif
#endif /* _ICC_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_ICC_REGS_H_

74
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/max32660.h
View File

@ -3,8 +3,8 @@
* @brief Device-specific perhiperal header file
*/
/*******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
******************************************************************************/
#ifndef _MAX32660_REGS_H_
#define _MAX32660_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_MAX32660_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_MAX32660_H_
#ifndef TARGET_NUM
#define TARGET_NUM 32660
@ -147,7 +146,6 @@ typedef enum {
#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
@ -162,7 +160,6 @@ typedef enum {
#include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
#include "system_max32660.h" /*!< System Header */
/* ================================================================================ */
/* ================== Device Specific Memory Section ================== */
/* ================================================================================ */
@ -208,7 +205,6 @@ typedef enum {
#define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL)
#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
/******************************************************************************/
/* GPIO */
#define MXC_CFG_GPIO_INSTANCES (1)
@ -225,6 +221,10 @@ typedef enum {
/******************************************************************************/
/* Timer */
#define SEC(s) (((uint32_t)s) * 1000000UL)
#define MSEC(ms) (ms * 1000UL)
#define USEC(us) (us)
#define MXC_CFG_TMR_INSTANCES (3)
#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
@ -234,25 +234,18 @@ typedef enum {
#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
#define MXC_TMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? TMR0_IRQn : \
(i) == 1 ? TMR1_IRQn : \
(i) == 2 ? TMR2_IRQn : 0)
#define MXC_TMR_GET_IRQ(i) \
(IRQn_Type)((i) == 0 ? TMR0_IRQn : (i) == 1 ? TMR1_IRQn : (i) == 2 ? TMR2_IRQn : 0)
#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
(i) == 1 ? MXC_BASE_TMR1 : \
(i) == 2 ? MXC_BASE_TMR2 : 0)
#define MXC_TMR_GET_BASE(i) \
((i) == 0 ? MXC_BASE_TMR0 : (i) == 1 ? MXC_BASE_TMR1 : (i) == 2 ? MXC_BASE_TMR2 : 0)
#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
(i) == 1 ? MXC_TMR1 : \
(i) == 2 ? MXC_TMR2 : 0)
#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : (i) == 1 ? MXC_TMR1 : (i) == 2 ? MXC_TMR2 : 0)
#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
(p) == MXC_TMR1 ? 1 : \
(p) == MXC_TMR2 ? 2 : -1)
#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : (p) == MXC_TMR1 ? 1 : (p) == MXC_TMR2 ? 2 : -1)
/******************************************************************************/
/* SPIMSS */
#define MXC_SPIMSS_INSTANCES (1)
#define MXC_SPIMSS_FIFO_DEPTH (8)
@ -272,17 +265,13 @@ typedef enum {
#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL)
#define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1)
#define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : \
(i) == 1 ? I2C1_IRQn : 0)
#define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : 0)
#define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : \
(i) == 1 ? MXC_BASE_I2C1 : 0)
#define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : 0)
#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : \
(i) == 1 ? MXC_I2C1 : 0)
#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : 0)
#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : \
(p) == MXC_I2C1 ? 1 : -1)
#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : -1)
/******************************************************************************/
/* DMA */
@ -300,6 +289,7 @@ typedef enum {
#define MXC_BASE_FLC ((uint32_t)0x40029000UL)
#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
#define MXC_FLC0 MXC_FLC
#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC : 0)
@ -310,7 +300,6 @@ typedef enum {
/******************************************************************************/
/* UART / Serial Port Interface */
#define MXC_UART_INSTANCES (2)
#define MXC_UART_FIFO_DEPTH (8)
@ -319,22 +308,16 @@ typedef enum {
#define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
(i) == 1 ? UART1_IRQn : 0)
#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : (i) == 1 ? UART1_IRQn : 0)
#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
(i) == 1 ? MXC_BASE_UART1 : 0)
#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : (i) == 1 ? MXC_BASE_UART1 : 0)
#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
(i) == 1 ? MXC_UART1 : 0)
#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : 0)
#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
(p) == MXC_UART1 ? 1 : -1)
#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : -1)
/******************************************************************************/
/* SPI */
#include "spi_regs.h"
#define MXC_SPI_INSTANCES (1)
#define MXC_SPI_SS_INSTANCES (1)
#define MXC_SPI_FIFO_DEPTH (32)
@ -350,7 +333,6 @@ typedef enum {
/******************************************************************************/
/* Bit Shifting */
#define MXC_F_BIT_0 (1 << 0)
#define MXC_F_BIT_1 (1 << 1)
#define MXC_F_BIT_2 (1 << 2)
@ -386,15 +368,15 @@ typedef enum {
/******************************************************************************/
/* Bit Banding */
#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \
(((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
#define BITBAND(reg, bit) \
((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \
((bit) << 2))
#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
#define MXC_SETFIELD(reg, mask, value) (reg = (reg & ~mask) | (value & mask))
#define MXC_SETFIELD(reg, mask, value) ((reg) = ((reg) & ~(mask)) | ((value) & (mask)))
/******************************************************************************/
/* SCB CPACR */
@ -405,4 +387,4 @@ typedef enum {
#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */
#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */
#endif /* _MAX32660_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_MAX32660_H_

20
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file pwrseq_regs.h
* @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _PWRSEQ_REGS_H_
#define _PWRSEQ_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_PWRSEQ_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_PWRSEQ_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -67,7 +67,9 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
@ -87,7 +89,7 @@ typedef struct {
__IO uint32_t lp_ctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LP_CTRL Register */
__IO uint32_t lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL Register */
__IO uint32_t lpwk_en; /**< <tt>\b 0x08:</tt> PWRSEQ LPWK_EN Register */
__I uint32_t rsv_0xc_0x3f[13];
__R uint32_t rsv_0xc_0x3f[13];
__IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
} mxc_pwrseq_regs_t;
@ -204,4 +206,4 @@ typedef struct {
}
#endif
#endif /* _PWRSEQ_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_PWRSEQ_REGS_H_

14
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/rtc_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file rtc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _RTC_REGS_H_
#define _RTC_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_RTC_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_RTC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -250,4 +250,4 @@ typedef struct {
}
#endif
#endif /* _RTC_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_RTC_REGS_H_

14
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/sir_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file sir_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _SIR_REGS_H_
#define _SIR_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SIR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SIR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -132,4 +132,4 @@ typedef struct {
}
#endif
#endif /* _SIR_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SIR_REGS_H_

20
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file spi_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _SPI_REGS_H_
#define _SPI_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPI_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPI_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -67,7 +67,9 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
@ -90,7 +92,7 @@ typedef struct {
__IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPI CTRL2 Register */
__IO uint32_t ss_time; /**< <tt>\b 0x10:</tt> SPI SS_TIME Register */
__IO uint32_t clk_cfg; /**< <tt>\b 0x14:</tt> SPI CLK_CFG Register */
__I uint32_t rsv_0x18;
__R uint32_t rsv_0x18;
__IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPI DMA Register */
__IO uint32_t int_fl; /**< <tt>\b 0x20:</tt> SPI INT_FL Register */
__IO uint32_t int_en; /**< <tt>\b 0x24:</tt> SPI INT_EN Register */
@ -439,4 +441,4 @@ typedef struct {
}
#endif
#endif /* _SPI_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPI_REGS_H_

22
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file spimss_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _SPIMSS_REGS_H_
#define _SPIMSS_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPIMSS_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPIMSS_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -67,7 +67,9 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
@ -85,11 +87,11 @@ extern "C" {
*/
typedef struct {
__IO uint16_t data; /**< <tt>\b 0x00:</tt> SPIMSS DATA Register */
__I uint16_t rsv_0x2;
__R uint16_t rsv_0x2;
__IO uint32_t ctrl; /**< <tt>\b 0x04:</tt> SPIMSS CTRL Register */
__IO uint32_t int_fl; /**< <tt>\b 0x08:</tt> SPIMSS INT_FL Register */
__IO uint32_t mode; /**< <tt>\b 0x0C:</tt> SPIMSS MODE Register */
__I uint32_t rsv_0x10;
__R uint32_t rsv_0x10;
__IO uint32_t brg; /**< <tt>\b 0x14:</tt> SPIMSS BRG Register */
__IO uint32_t dma; /**< <tt>\b 0x18:</tt> SPIMSS DMA Register */
__IO uint32_t i2s_ctrl; /**< <tt>\b 0x1C:</tt> SPIMSS I2S_CTRL Register */
@ -343,4 +345,4 @@ typedef struct {
}
#endif
#endif /* _SPIMSS_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPIMSS_REGS_H_

14
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/system_max32660.h
View File

@ -3,9 +3,8 @@
* @brief System-specific header file
*/
/*******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -35,11 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
******************************************************************************/
#ifndef _SYSTEM_MAX32660_H_
#define _SYSTEM_MAX32660_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SYSTEM_MAX32660_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SYSTEM_MAX32660_H_
#ifdef __cplusplus
extern "C" {
@ -55,6 +53,8 @@ extern "C" {
#define HFX_FREQ 32768
#endif
/* NOTE: This is the nominal value for NANORING. The actual value may vary from chip to chip.
Update if use of this oscillator requires precise timing.*/
#ifndef NANORING_FREQ
#define NANORING_FREQ 8000
#endif
@ -88,4 +88,4 @@ void SystemCoreClockUpdate(void);
}
#endif
#endif /* _SYSTEM_MAX32660_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SYSTEM_MAX32660_H_

34
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file tmr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _TMR_REGS_H_
#define _TMR_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_TMR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_TMR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -67,7 +67,9 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
@ -173,10 +175,6 @@ typedef struct {
#define MXC_S_TMR_CN_TMODE_GATED (MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */
#define MXC_V_TMR_CN_TMODE_CAPCOMP ((uint32_t)0x7UL) /**< CN_TMODE_CAPCOMP Value */
#define MXC_S_TMR_CN_TMODE_CAPCOMP (MXC_V_TMR_CN_TMODE_CAPCOMP << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPCOMP Setting */
#define MXC_V_TMR_CN_TMODE_DUAL_EDGE ((uint32_t)0x8UL) /**< CN_TMODE_DUAL_EDGE Value */
#define MXC_S_TMR_CN_TMODE_DUAL_EDGE (MXC_V_TMR_CN_TMODE_DUAL_EDGE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_DUAL_EDGE Setting */
#define MXC_V_TMR_CN_TMODE_IGATED ((uint32_t)0xCUL) /**< CN_TMODE_IGATED Value */
#define MXC_S_TMR_CN_TMODE_IGATED (MXC_V_TMR_CN_TMODE_IGATED << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_IGATED Setting */
#define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */
#define MXC_F_TMR_CN_PRES ((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */
@ -196,17 +194,17 @@ typedef struct {
#define MXC_S_TMR_CN_PRES_DIV_BY_64 (MXC_V_TMR_CN_PRES_DIV_BY_64 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_64 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_128 ((uint32_t)0x7UL) /**< CN_PRES_DIV_BY_128 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_128 (MXC_V_TMR_CN_PRES_DIV_BY_128 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_128 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_256 ((uint32_t)0x8UL) /**< CN_PRES_DIV_BY_256 Value */
#define MXC_V_TMR_CN_PRES_DIV_BY_256 ((uint32_t)0x0UL) /**< CN_PRES_DIV_BY_256 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_256 (MXC_V_TMR_CN_PRES_DIV_BY_256 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_256 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_512 ((uint32_t)0x9UL) /**< CN_PRES_DIV_BY_512 Value */
#define MXC_V_TMR_CN_PRES_DIV_BY_512 ((uint32_t)0x1UL) /**< CN_PRES_DIV_BY_512 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_512 (MXC_V_TMR_CN_PRES_DIV_BY_512 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_512 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_1024 ((uint32_t)0xAUL) /**< CN_PRES_DIV_BY_1024 Value */
#define MXC_V_TMR_CN_PRES_DIV_BY_1024 ((uint32_t)0x2UL) /**< CN_PRES_DIV_BY_1024 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_1024 (MXC_V_TMR_CN_PRES_DIV_BY_1024 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_1024 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_2048 ((uint32_t)0xBUL) /**< CN_PRES_DIV_BY_2048 Value */
#define MXC_V_TMR_CN_PRES_DIV_BY_2048 ((uint32_t)0x3UL) /**< CN_PRES_DIV_BY_2048 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_2048 (MXC_V_TMR_CN_PRES_DIV_BY_2048 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_2048 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_4096 ((uint32_t)0xCUL) /**< CN_PRES_DIV_BY_4096 Value */
#define MXC_V_TMR_CN_PRES_DIV_BY_4096 ((uint32_t)0x4UL) /**< CN_PRES_DIV_BY_4096 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_4096 (MXC_V_TMR_CN_PRES_DIV_BY_4096 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_4096 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_8192 ((uint32_t)0xDUL) /**< CN_PRES_DIV_BY_8192 Value */
#define MXC_V_TMR_CN_PRES_DIV_BY_8192 ((uint32_t)0x5UL) /**< CN_PRES_DIV_BY_8192 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_8192 (MXC_V_TMR_CN_PRES_DIV_BY_8192 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_8192 Setting */
#define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */
@ -236,4 +234,4 @@ typedef struct {
}
#endif
#endif /* _TMR_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_TMR_REGS_H_

18
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file uart_regs.h
* @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _UART_REGS_H_
#define _UART_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_UART_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_UART_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -67,7 +67,9 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
@ -399,4 +401,4 @@ typedef struct {
}
#endif
#endif /* _UART_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_UART_REGS_H_

18
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h
View File

@ -1,10 +1,11 @@
/**
* @file wdt_regs.h
* @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module.
* @note This file is @generated.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _WDT_REGS_H_
#define _WDT_REGS_H_
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_WDT_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_WDT_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -67,7 +67,9 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
@ -211,4 +213,4 @@ typedef struct {
}
#endif
#endif /* _WDT_REGS_H_ */
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_WDT_REGS_H_

63
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c
View File

@ -3,8 +3,8 @@
* @brief System-level initialization implementation file
*/
/*******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,9 +34,6 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
******************************************************************************/
#include <string.h>
@ -48,8 +45,8 @@
#include "tmr_regs.h"
#include "wdt_regs.h"
#include "mxc_sys.h"
#include "icc.h"
extern void (*const __isr_vector[])(void);
uint32_t SystemCoreClock = HIRC96_FREQ;
__weak void SystemCoreClockUpdate(void)
@ -79,7 +76,7 @@ __weak void SystemCoreClockUpdate(void)
}
// Get the clock divider
div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL) >> MXC_F_GCR_CLK_CTRL_PSC_POS;
div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_PSC) >> MXC_F_GCR_CLK_CTRL_PSC_POS;
SystemCoreClock = base_freq >> div;
}
@ -94,20 +91,15 @@ __weak void SystemCoreClockUpdate(void)
*/
__weak int PreInit(void)
{
/* Switch system clock to HIRC, 96 MHz*/
MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC);
/* Enable cache here to reduce boot time */
MXC_ICC_Enable();
/* Do nothing */
return 0;
}
/* Override this function for early platform initialization
*/
__weak void low_level_init(void)
/* This function can be implemented by the application to initialize the board */
__weak int Board_Init(void)
{
/* Do nothing */
return 0;
}
/* This function is called just before control is transferred to main().
@ -118,16 +110,23 @@ __weak void low_level_init(void)
*/
__weak void SystemInit(void)
{
MXC_WDT0->ctrl &= ~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */
/* Configure the interrupt controller to use the application vector table in */
/* the application space */
/* IAR & Keil must set vector table after all memory initialization. */
SCB->VTOR = (uint32_t)__isr_vector;
MXC_WDT0->ctrl &=
~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */
#if (__FPU_PRESENT == 1)
/* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
/* Grant full access, per "Table B3-24 CPACR bit assignments". */
/* DDI0403D "ARMv7-M Architecture Reference Manual" */
SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
__DSB();
__ISB();
#endif
/* Switch system clock to HIRC */
MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC);
/* Disable clocks to peripherals by default to reduce power */
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_DMA);
@ -141,6 +140,26 @@ __weak void SystemInit(void)
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2);
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1);
/* Early platform initialization */
low_level_init();
Board_Init();
}
#if defined(__CC_ARM)
/* Global variable initialization does not occur until post scatterload in Keil tools.*/
/* External function called after our post scatterload function implementation. */
extern void $Super$$__main_after_scatterload(void);
/**
* @brief Initialization function for SystemCoreClock and Board_Init.
* @details $Sub$$__main_after_scatterload is called during system startup in the Keil
* toolset. Global variable and static variable space must be set up by the compiler
* prior to using these memory spaces. Setting up the SystemCoreClock and Board_Init
* require global memory for variable storage and are called from this function in
* the Keil tool chain.
*/
void $Sub$$__main_after_scatterload(void)
{
SystemInit();
$Super$$__main_after_scatterload();
}
#endif /* __CC_ARM */

25
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/dma.h
View File

@ -3,8 +3,8 @@
* @brief Direct Memory Access (DMA) driver function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,10 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef _DMA_H_
#define _DMA_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_DMA_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_DMA_H_
/* **** Includes **** */
#include <stdbool.h>
@ -57,7 +57,6 @@ extern "C" {
/* **** Definitions **** */
/**
* @brief Enumeration for the DMA Channel's priority level.
*
@ -71,7 +70,8 @@ typedef enum {
/** @brief DMA request select */
typedef enum {
MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CFG_REQSEL_MEMTOMEM, ///< Memory to Memory DMA Request Selection
MXC_DMA_REQUEST_MEMTOMEM =
MXC_S_DMA_CFG_REQSEL_MEMTOMEM, ///< Memory to Memory DMA Request Selection
MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CFG_REQSEL_SPI0RX, ///< SPI0 Receive DMA Request Selection
MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CFG_REQSEL_SPI1RX, ///< SPI1 Receive DMA Request Selection
MXC_DMA_REQUEST_UART0RX = MXC_S_DMA_CFG_REQSEL_UART0RX, ///< UART0 Receive DMA Request Selection
@ -80,8 +80,10 @@ typedef enum {
MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CFG_REQSEL_I2C1RX, ///< I2C1 Receive DMA Request Selection
MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CFG_REQSEL_SPI0TX, ///< SPI0 Transmit DMA Request Selection
MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CFG_REQSEL_SPI1TX, ///< SPI1 Transmit DMA Request Selection
MXC_DMA_REQUEST_UART0TX = MXC_S_DMA_CFG_REQSEL_UART0TX, ///< UART0 Transmit DMA Request Selection
MXC_DMA_REQUEST_UART1TX = MXC_S_DMA_CFG_REQSEL_UART1TX, ///< UART1 Transmit DMA Request Selection
MXC_DMA_REQUEST_UART0TX =
MXC_S_DMA_CFG_REQSEL_UART0TX, ///< UART0 Transmit DMA Request Selection
MXC_DMA_REQUEST_UART1TX =
MXC_S_DMA_CFG_REQSEL_UART1TX, ///< UART1 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CFG_REQSEL_I2C0TX, ///< I2C0 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CFG_REQSEL_I2C1TX, ///< I2C1 Transmit DMA Request Selection
} mxc_dma_reqsel_t;
@ -413,7 +415,8 @@ int MXC_DMA_MemCpy (void* dest, void* src, int len, mxc_dma_complete_cb_t callba
*
* @return see \ref MXC_Error_Codes
*/
int MXC_DMA_DoTransfer (mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback);
int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst,
mxc_dma_trans_chain_t callback);
/**
* For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver
*/
@ -423,4 +426,4 @@ int MXC_DMA_DoTransfer (mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, m
}
#endif
#endif /* _DMA_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_DMA_H_

14
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/flc.h
View File

@ -4,8 +4,8 @@
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -35,10 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef _FLC_H_
#define _FLC_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_FLC_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_FLC_H_
/* **** Includes **** */
#include "flc_regs.h"
@ -61,7 +61,7 @@ extern "C" {
#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1)
/// Calculate the address of a page in flash from the page number
#define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE))
#define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((uint32_t)page * MXC_FLASH_PAGE_SIZE))
/***** Function Prototypes *****/
@ -186,4 +186,4 @@ int MXC_FLC_LockInfoBlock (uint32_t address);
}
#endif
#endif /* _FLC_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_FLC_H_

40
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/gpio.h
View File

@ -3,8 +3,8 @@
* @brief General-Purpose Input/Output (GPIO) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _GPIO_H_
#define _GPIO_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_GPIO_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_GPIO_H_
/* **** Includes **** */
#include "gpio_regs.h"
@ -279,7 +279,8 @@ void MXC_GPIO_ClearFlags (mxc_gpio_regs_t* port, uint32_t flags);
* @param cbdata The parameter to be passed to the callback function, #callback_fn, when an interrupt occurs.
*
*/
void MXC_GPIO_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, void *cbdata);
void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback,
void *cbdata);
/**
* @brief GPIO IRQ Handler. @note If a callback is registered for a given
@ -301,10 +302,35 @@ void MXC_GPIO_Handler (unsigned int port);
*/
int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask);
/**
* @brief Enables GPIO pins to be used as a wakeup source.
*
* @param port The GPIO port
* @param mask Pins in the GPIO port that will be enabled as a wakeup source.
*/
void MXC_GPIO_SetWakeEn(mxc_gpio_regs_t *port, uint32_t mask);
/**
* @brief Disables GPIO pins from being used as a wakeup source.
*
* @param port The GPIO port
* @param mask Pins in the GPIO port that will be disabled as a wakeup source.
*/
void MXC_GPIO_ClearWakeEn(mxc_gpio_regs_t *port, uint32_t mask);
/**
* @brief Returns the pins currently enabled as wakeup sources.
*
* @param port The GPIO port to check.
*
* @returns The value of the wake enable register.
*/
uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port);
/**@} end of group gpio */
#ifdef __cplusplus
}
#endif
#endif /* _GPIO_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_GPIO_H_

14
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/i2s.h
View File

@ -3,8 +3,8 @@
* @brief I2S (Inter-Integrated Sound) driver function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,10 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef _I2S_H_
#define _I2S_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_I2S_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_I2S_H_
/* **** Includes **** */
#include "mxc_sys.h"
@ -77,7 +77,6 @@ typedef enum {
AUDIO_IN = 2,
} mxc_i2s_direction_t;
/** @brief I2S Configuration Struct */
typedef struct {
mxc_i2s_sys_map_t map;
@ -183,9 +182,8 @@ int MXC_I2S_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count);
int MXC_I2S_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count);
/**@} end of group i2s */
#ifdef __cplusplus
}
#endif
#endif /* _I2S_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_I2S_H_

12
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/icc.h
View File

@ -3,8 +3,8 @@
* @brief Instruction Controller Cache(ICC) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _ICC_H_
#define _ICC_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_ICC_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_ICC_H_
/* **** Includes **** */
#include <stdint.h>
@ -91,4 +91,4 @@ void MXC_ICC_Flush (void);
}
#endif
#endif /* _ICC_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_ICC_H_

30
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h
View File

@ -3,9 +3,8 @@
* @brief Low power function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -35,16 +34,14 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-09-26 08:48:30 -0500 (Wed, 26 Sep 2018) $
* $Revision: 38105 $
*
*************************************************************************** */
******************************************************************************/
// Define to prevent redundant inclusion
#ifndef _LP_H_
#define _LP_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_LP_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_LP_H_
/***** Includes *****/
#include "gpio.h"
#include "pwrseq_regs.h"
#ifdef __cplusplus
@ -163,18 +160,18 @@ void MXC_LP_DisableSysRAM0LightSleep(void);
* @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode.
* Call this function multiple times to enable pins on multiple ports. This function does not configure
* the GPIO pins nor does it setup their interrupt functionality.
* @param port The port to configure as wakeup sources.
* @param mask The pins to configure as wakeup sources.
* @param wu_pins The port and pins to configure as wakeup sources. Only the gpio and mask fields of the
* structure are used. The func and pad fields are ignored.
*/
void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask);
void MXC_LP_EnableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins);
/**
* @brief Disables the selected GPIO port and its selected pins as a wake up source.
* Call this function multiple times to disable pins on multiple ports.
* @param port The port to configure as wakeup sources.
* @param mask The pins to configure as wakeup sources.
* @param wu_pins The port and pins to disable as wakeup sources. Only the gpio and mask fields of the
* structure are used. The func and pad fields are ignored.
*/
void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask);
void MXC_LP_DisableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins);
/**
* @brief Enables the RTC alarm to wake up the device from any low power mode.
@ -327,7 +324,6 @@ void MXC_LP_EnableVCoreSVM(void);
*/
void MXC_LP_DisableVCoreSVM(void);
/**
* @brief Enables VDDIO Power-On-Reset Monitor
*/
@ -343,4 +339,4 @@ void MXC_LP_DisableVDDIOPorMonitor(void);
}
#endif
#endif /* _LP_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_LP_H_

38
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/msr.h
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,8 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
********************************************************************************
*/
******************************************************************************/
/**
* \file
@ -42,8 +41,12 @@
* prototypes.
*/
#ifndef _MSR_H_
#define _MSR_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MSR_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MSR_H_
#ifdef __cplusplus
extern "C" {
#endif
/***** Definitions *****/
@ -79,16 +82,16 @@
/// Structure to contain result of a track decode
typedef struct {
uint8_t error_code; /**< Error code value */
uint8_t parity_errs; /**< Number of characters with parity errors */
uint8_t lrc; /**< LRC check value. A value of '0' indicates a
successful LRC check. Any other value should be
considered a failure. */
uint8_t direction; /**< Swipe direction determined from decode */
uint8_t len; /**< Number or decoded characters. This does not include
the sentinels or the LRC. */
uint8_t error_code; ///< Error code value
uint8_t parity_errs; ///< Number of characters with parity errors
uint8_t lrc; ///< LRC check value. A value of '0' indicates a
/// successful LRC check. Any other value should be
/// considered a failure.
uint8_t direction; ///< Swipe direction determined from decode
uint8_t len; ///< Number or decoded characters. This does not include
/// the sentinels or the LRC.
uint16_t speed;
uint8_t data[MSR_MAX_DEC_LEN]; /**< The decoded data */
uint8_t data[MSR_MAX_DEC_LEN]; ///< The decoded data
} msr_decoded_track_t;
/// MSR sample fields
@ -169,5 +172,8 @@ void msr_set_complete_callback (void (*func) (void));
*/
unsigned int mcr_get_track_samples(unsigned int track, msr_samples_t *samples);
#endif /* _MSR_H_ */
#ifdef __cplusplus
}
#endif
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MSR_H_

16
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_assert.h
View File

@ -3,8 +3,8 @@
* @brief Assertion checks for debugging.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,15 +34,14 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _MXC_ASSERT_H_
#define _MXC_ASSERT_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_ASSERT_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_ASSERT_H_
/* **** Includes **** */
#ifdef __cplusplus
extern "C" {
#endif
@ -66,8 +65,7 @@ extern "C" {
* defined.
*/
#define MXC_ASSERT(expr) \
if (!(expr)) \
{ \
if (!(expr)) { \
mxc_assert(#expr, __FILE__, __LINE__); \
}
/**
@ -106,4 +104,4 @@ void mxc_assert (const char *expr, const char *file, int line);
}
#endif
#endif /* _MXC_ASSERT_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_ASSERT_H_

28
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_delay.h
View File

@ -3,8 +3,8 @@
* @brief Asynchronous delay routines based on the SysTick Timer.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,17 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _DELAY_H_
#define _DELAY_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_DELAY_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_DELAY_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @ingroup devicelibs
@ -54,7 +60,7 @@
* x = SEC(3) // 3 seconds -> x = 3,000,000
* \endcode
*/
#define MXC_DELAY_SEC(s) (((unsigned long)s) * 1000000UL)
#define MXC_DELAY_SEC(s) (((uint32_t)s) * 1000000UL)
/**
* Macro used to specify a microsecond timing parameter in milliseconds.
* \code
@ -88,7 +94,7 @@ typedef void (*mxc_delay_complete_t) (int result);
* @param us microseconds to delay
* @return #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful.
*/
int MXC_Delay (unsigned long us);
int MXC_Delay(uint32_t us);
/**
* @brief Starts a non-blocking delay for the specified number of
@ -103,7 +109,7 @@ int MXC_Delay (unsigned long us);
* @return #E_NO_ERROR if no errors, #E_BUSY if currently servicing another
* delay request.
*/
int MXC_DelayAsync (unsigned long us, mxc_delay_complete_t callback);
int MXC_DelayAsync(uint32_t us, mxc_delay_complete_t callback);
/**
* @brief Returns the status of a non-blocking delay request
@ -127,4 +133,8 @@ void MXC_DelayHandler (void);
/**@} end of group MXC_delay */
#endif /* _DELAY_H_ */
#ifdef __cplusplus
}
#endif
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_DELAY_H_

14
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,6 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
******************************************************************************/
/**
@ -37,13 +36,12 @@
* @brief contains device and revision specific definitions
*/
#ifndef _MXC_DEVICE_H_
#define _MXC_DEVICE_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_DEVICE_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_DEVICE_H_
#include "max32660.h"
#include "mxc_errors.h"
#ifndef TARGET
#error TARGET NOT DEFINED
#endif
@ -51,9 +49,7 @@
// Create a string definition for the TARGET
#define STRING_ARG(arg) #arg
#define STRING_NAME(name) STRING_ARG(name)
#if MBED_VERSION && MBED_VERSION < 51200
#define TARGET_NAME STRING_NAME(TARGET)
#endif
// Define which revisions of the IP we are using
#ifndef TARGET_REV
@ -71,4 +67,4 @@
#endif // if(TARGET_REV == ...)
#endif /* _MXC_DEVICE_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_DEVICE_H_

14
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_errors.h
View File

@ -3,8 +3,8 @@
* @brief List of common error return codes for Maxim Integrated libraries.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _MXC_ERRORS_H_
#define _MXC_ERRORS_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_ERRORS_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_ERRORS_H_
/**
* @ingroup syscfg
@ -87,6 +87,8 @@
#define E_ABORT -16
/** The requested operation is not supported */
#define E_NOT_SUPPORTED -17
/** The requested operation is failed */
#define E_FAIL -255
/**@} end of MXC_Error_Codes group */
#endif /* _MXC_ERRORS_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_ERRORS_H_

48
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_i2c.h
View File

@ -3,8 +3,8 @@
* @brief Inter-integrated circuit (I2C) communications interface driver.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _MXC_I2C_H_
#define _MXC_I2C_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_I2C_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_I2C_H_
#include <stdint.h>
#include "mxc_sys.h"
@ -165,8 +165,8 @@ typedef enum {
* non-zero to not acknowledge. The return value is ignored for all
* other event types.
*/
typedef int (*mxc_i2c_slave_handler_t) (mxc_i2c_regs_t* i2c,
mxc_i2c_slave_event_t event, void* data);
typedef int (*mxc_i2c_slave_handler_t)(mxc_i2c_regs_t *i2c, mxc_i2c_slave_event_t event,
void *data);
/***** Function Prototypes *****/
@ -350,8 +350,7 @@ int MXC_I2C_ReadByte (mxc_i2c_regs_t* i2c, unsigned char* byte, int ack);
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_ReadByteInteractive (mxc_i2c_regs_t* i2c, unsigned char* byte,
mxc_i2c_getAck_t getAck);
int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t *i2c, unsigned char *byte, mxc_i2c_getAck_t getAck);
/**
* @brief Write multiple bytes to the I2C bus.
@ -389,8 +388,7 @@ int MXC_I2C_Write (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len)
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_Read (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len,
int ack);
int MXC_I2C_Read(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack);
/**
* @brief Unloads bytes from the receive FIFO.
@ -401,8 +399,7 @@ int MXC_I2C_Read (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len,
*
* @return The number of bytes actually read.
*/
int MXC_I2C_ReadRXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes,
unsigned int len);
int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len);
/**
* @brief Unloads bytes from the receive FIFO using DMA for longer reads.
@ -416,8 +413,8 @@ int MXC_I2C_ReadRXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes,
*
* @return See \ref MXC_Error_Codes for a list of return values.
*/
int MXC_I2C_ReadRXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes,
unsigned int len, mxc_i2c_dma_complete_cb_t callback);
int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len,
mxc_i2c_dma_complete_cb_t callback);
/**
* @brief Get the number of bytes currently available in the receive FIFO.
@ -437,8 +434,7 @@ int MXC_I2C_GetRXFIFOAvailable (mxc_i2c_regs_t* i2c);
*
* @return The number of bytes actually written.
*/
int MXC_I2C_WriteTXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes,
unsigned int len);
int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len);
/**
* @brief Loads bytes into the transmit FIFO using DMA for longer writes.
@ -451,8 +447,8 @@ int MXC_I2C_WriteTXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes,
*
* @return See \ref MXC_Error_Codes for a list of return values
*/
int MXC_I2C_WriteTXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes,
unsigned int len, mxc_i2c_dma_complete_cb_t callback);
int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len,
mxc_i2c_dma_complete_cb_t callback);
/**
* @brief Get the amount of free space available in the transmit FIFO.
@ -825,6 +821,16 @@ int MXC_I2C_SetTXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes);
*/
unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t *i2c);
/**
* @brief Stop any asynchronous requests in progress.
*
* Stop any asynchronous requests in progress. Any callbacks associated with
* the active transaction will be NOT executed.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*/
void MXC_I2C_AsyncStop(mxc_i2c_regs_t *i2c);
/**
* @brief Abort any asynchronous requests in progress.
*
@ -858,12 +864,10 @@ void MXC_I2C_AsyncHandler (mxc_i2c_regs_t* i2c);
*/
void MXC_I2C_DMACallback(int ch, int error);
/**@} end of group i2c */
#ifdef __cplusplus
}
#endif
#endif /* _MXC_I2C_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_I2C_H_

25
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_lock.h
View File

@ -3,8 +3,8 @@
* @brief Exclusive access lock utility functions.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,16 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _MXC_LOCK_H_
#define _MXC_LOCK_H_
// To enable disable this module
#define USE_LOCK_IN_DRIVERS 0
#if USE_LOCK_IN_DRIVERS
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_LOCK_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_LOCK_H_
/* **** Includes **** */
#include "mxc_device.h"
@ -93,12 +88,4 @@ void MXC_FreeLock (uint32_t *lock);
}
#endif
#else // USE_LOCK_IN_DRIVERS
#define MXC_GetLock(x, y) E_NO_ERROR
#define MXC_FreeLock(x)
#endif // USE_LOCK_IN_DRIVERS
#endif /* _MXC_LOCK_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_LOCK_H_

24
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_pins.h
View File

@ -4,7 +4,7 @@
*/
/******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,21 +34,16 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
#ifndef _MXC_PINS_H_
#define _MXC_PINS_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_PINS_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_PINS_H_
#include "gpio.h"
/***** Global Variables *****/
typedef enum {
MAP_A,
MAP_B,
MAP_C
} sys_map_t;
typedef enum { MAP_A, MAP_B, MAP_C } sys_map_t;
// Predefined GPIO Configurations
extern const mxc_gpio_cfg_t gpio_cfg_swda;
@ -57,7 +52,6 @@ extern const mxc_gpio_cfg_t gpio_cfg_swdb;
extern const mxc_gpio_cfg_t gpio_cfg_i2c0;
extern const mxc_gpio_cfg_t gpio_cfg_i2c1;
extern const mxc_gpio_cfg_t gpio_cfg_uart0;
extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow;
extern const mxc_gpio_cfg_t gpio_cfg_uart1a;
@ -65,13 +59,9 @@ extern const mxc_gpio_cfg_t gpio_cfg_uart1b;
extern const mxc_gpio_cfg_t gpio_cfg_uart1c;
extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow;
extern const mxc_gpio_cfg_t gpio_cfg_spi0;
extern const mxc_gpio_cfg_t gpio_cfg_spi0_ss;
extern const mxc_gpio_cfg_t gpio_cfg_spi1a;
extern const mxc_gpio_cfg_t gpio_cfg_spi1a_ss;
extern const mxc_gpio_cfg_t gpio_cfg_spi1b;
extern const mxc_gpio_cfg_t gpio_cfg_spi1b_ss;
// Timers are only defined once, depending on package, each timer could be mapped to other pins
extern const mxc_gpio_cfg_t gpio_cfg_tmr0;
@ -80,6 +70,4 @@ extern const mxc_gpio_cfg_t gpio_cfg_32kcal;
extern const mxc_gpio_cfg_t gpio_cfg_i2s0a;
extern const mxc_gpio_cfg_t gpio_cfg_i2s0b;
#endif /* _MXC_PINS_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_PINS_H_

39
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_spi.h
View File

@ -3,8 +3,8 @@
* @brief Serial Peripheral Interface (SPI) communications driver.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,9 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#ifndef _SPI_H_
#define _SPI_H_
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPI_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPI_H_
/***** includes *******/
#include "spi_regs.h"
@ -46,6 +47,9 @@
#include "mxc_pins.h"
#include "mxc_lock.h"
#ifdef __cplusplus
extern "C" {
#endif
/***** Definitions *****/
@ -165,15 +169,12 @@ struct _mxc_spi_req_t {
* @param hz The requested clock frequency. The actual clock frequency
* will be returned by the function if successful. Used in
* master mode only.
* @param drv_ssel Hardware block able to drive SS pin, or it can be leaved as it is
* To upper layer firmware drive it.
* 1:Driver will drive SS pin, 0:Driver will NOT drive it
*
* @return If successful, the actual clock frequency is returned. Otherwise, see
* \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves,
unsigned ssPolarity, unsigned int hz, unsigned drv_ssel);
unsigned ssPolarity, unsigned int hz);
/**
* @brief Disable and shutdown SPI peripheral.
@ -198,6 +199,15 @@ int MXC_SPI_Shutdown (mxc_spi_regs_t* spi);
*/
int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi);
/**
* @brief Returns the frequency of the clock used as the bit rate generator for a given SPI instance.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*
* @return Frequency of the clock used as the bit rate generator
*/
int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi);
/**
* @brief Set the frequency of the SPI interface.
*
@ -211,8 +221,6 @@ int MXC_SPI_ReadyForSleep (mxc_spi_regs_t* spi);
*/
int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz);
int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi);
/**
* @brief Get the frequency of the SPI interface.
*
@ -243,7 +251,6 @@ int MXC_SPI_SetDataSize (mxc_spi_regs_t* spi, int dataSize);
*/
int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi);
/* ************************************************************************* */
/* Low-level functions */
/* ************************************************************************* */
@ -354,8 +361,7 @@ int MXC_SPI_AbortTransmission (mxc_spi_regs_t* spi);
*
* @return The number of bytes actually read.
*/
unsigned int MXC_SPI_ReadRXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes,
unsigned int len);
unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len);
/**
* @brief Get the number of bytes currently available in the receive FIFO.
@ -375,8 +381,7 @@ unsigned int MXC_SPI_GetRXFIFOAvailable (mxc_spi_regs_t* spi);
*
* @return The number of bytes actually written.
*/
unsigned int MXC_SPI_WriteTXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes,
unsigned int len);
unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len);
/**
* @brief Get the amount of free space available in the transmit FIFO.
@ -645,4 +650,4 @@ void MXC_SPI_AsyncHandler (mxc_spi_regs_t* spi);
}
#endif
#endif /* _PT_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPI_H_

169
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_sys.h
View File

@ -3,8 +3,8 @@
* @brief System level header file.
*/
/*******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -36,8 +36,8 @@
*
******************************************************************************/
#ifndef _MXC_MXC_SYS_H_
#define _MXC_MXC_SYS_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_SYS_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_SYS_H_
#include "mxc_device.h"
#include "gcr_regs.h"
@ -46,6 +46,13 @@
extern "C" {
#endif
/**
* @defgroup mxc_sys System Configuration (MXC_SYS)
* @ingroup syscfg
* @details API for system configuration including clock source selection and entering critical sections of code.
* @{
*/
/** @brief System reset0 and reset1 enumeration. Used in MXC_SYS_PeriphReset0 function */
typedef enum {
MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */
@ -69,20 +76,33 @@ typedef enum {
/** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */
typedef enum {
MXC_SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PCLK_DIS0_GPIO0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */
MXC_SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PCLK_DIS0_DMAD_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */
MXC_SYS_PERIPH_CLOCK_SPI0 = MXC_F_GCR_PCLK_DIS0_SPI0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI0 clock */
MXC_SYS_PERIPH_CLOCK_SPI1 = MXC_F_GCR_PCLK_DIS0_SPI1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */
MXC_SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PCLK_DIS0_UART0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */
MXC_SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PCLK_DIS0_UART1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */
MXC_SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PCLK_DIS0_I2C0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */
MXC_SYS_PERIPH_CLOCK_TMR0 = MXC_F_GCR_PCLK_DIS0_TIMER0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T0 clock */
MXC_SYS_PERIPH_CLOCK_TMR1 = MXC_F_GCR_PCLK_DIS0_TIMER1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T1 clock */
MXC_SYS_PERIPH_CLOCK_TMR2 = MXC_F_GCR_PCLK_DIS0_TIMER2D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T2 clock */
MXC_SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PCLK_DIS0_I2C1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */
MXC_SYS_PERIPH_CLOCK_GPIO0 =
MXC_F_GCR_PCLK_DIS0_GPIO0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */
MXC_SYS_PERIPH_CLOCK_DMA =
MXC_F_GCR_PCLK_DIS0_DMAD_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */
MXC_SYS_PERIPH_CLOCK_SPI0 =
MXC_F_GCR_PCLK_DIS0_SPI0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI0 clock */
MXC_SYS_PERIPH_CLOCK_SPI1 =
MXC_F_GCR_PCLK_DIS0_SPI1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */
MXC_SYS_PERIPH_CLOCK_UART0 =
MXC_F_GCR_PCLK_DIS0_UART0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */
MXC_SYS_PERIPH_CLOCK_UART1 =
MXC_F_GCR_PCLK_DIS0_UART1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */
MXC_SYS_PERIPH_CLOCK_I2C0 =
MXC_F_GCR_PCLK_DIS0_I2C0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */
MXC_SYS_PERIPH_CLOCK_TMR0 =
MXC_F_GCR_PCLK_DIS0_TIMER0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T0 clock */
MXC_SYS_PERIPH_CLOCK_TMR1 =
MXC_F_GCR_PCLK_DIS0_TIMER1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T1 clock */
MXC_SYS_PERIPH_CLOCK_TMR2 =
MXC_F_GCR_PCLK_DIS0_TIMER2D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T2 clock */
MXC_SYS_PERIPH_CLOCK_I2C1 =
MXC_F_GCR_PCLK_DIS0_I2C1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */
/* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */
MXC_SYS_PERIPH_CLOCK_FLCD = (MXC_F_GCR_PCLK_DIS1_FLCD_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT1 clock */
MXC_SYS_PERIPH_CLOCK_ICACHE = (MXC_F_GCR_PCLK_DIS1_ICCD_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */
MXC_SYS_PERIPH_CLOCK_FLCD =
(MXC_F_GCR_PCLK_DIS1_FLCD_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT1 clock */
MXC_SYS_PERIPH_CLOCK_ICACHE =
(MXC_F_GCR_PCLK_DIS1_ICCD_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */
} mxc_sys_periph_clock_t;
/** @brief Enumeration to select System Clock source */
@ -93,8 +113,120 @@ typedef enum {
MXC_SYS_CLOCK_HIRC = MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC, /**< High Frequency Internal Oscillator */
} mxc_sys_system_clock_t;
#define MXC_SYS_USN_LEN 8
/***** Function Prototypes *****/
typedef struct {
int ie_status;
int in_critical;
} mxc_crit_state_t;
static mxc_crit_state_t _state = { .ie_status = 0xFFFFFFFF, .in_critical = 0 };
static inline void _mxc_crit_get_state()
{
#ifndef __riscv
/*
On ARM M the 0th bit of the Priority Mask register indicates
whether interrupts are enabled or not.
0 = enabled
1 = disabled
*/
uint32_t primask = __get_PRIMASK();
_state.ie_status = (primask == 0);
#else
/*
On RISC-V bit position 3 (Machine Interrupt Enable) of the
mstatus register indicates whether interrupts are enabled.
0 = disabled
1 = enabled
*/
uint32_t mstatus = get_mstatus();
_state.ie_status = ((mstatus & (1 << 3)) != 0);
#endif
}
/**
* @brief Enter a critical section of code that cannot be interrupted. Call @ref MXC_SYS_Crit_Exit to exit the critical section.
* @details Ex:
* @code
* MXC_SYS_Crit_Enter();
* printf("Hello critical section!\n");
* MXC_SYS_Crit_Exit();
* @endcode
* The @ref MXC_CRITICAL macro is also provided as a convencience macro for wrapping a code section in this way.
* @returns None
*/
static inline void MXC_SYS_Crit_Enter(void)
{
_mxc_crit_get_state();
if (_state.ie_status)
__disable_irq();
_state.in_critical = 1;
}
/**
* @brief Exit a critical section of code from @ref MXC_SYS_Crit_Enter
* @returns None
*/
static inline void MXC_SYS_Crit_Exit(void)
{
if (_state.ie_status) {
__enable_irq();
}
_state.in_critical = 0;
_mxc_crit_get_state();
/*
^ Reset the state again to prevent edge case
where interrupts get disabled, then Crit_Exit() gets
called, which would inadvertently re-enable interrupts
from old state.
*/
}
/**
* @brief Polls whether code is currently executing from a critical section.
* @returns 1 if code is currently in a critical section (interrupts are disabled).
* 0 if code is not in a critical section.
*/
static inline int MXC_SYS_In_Crit_Section(void)
{
return _state.in_critical;
}
// clang-format off
/**
* @brief Macro for wrapping a section of code to make it critical (interrupts disabled). Note: this macro
* does not support nesting.
* @details
* Ex:
* \code
* MXC_CRITICAL(
* printf("Hello critical section!\n");
* )
* \endcode
* This macro places a call to @ref MXC_SYS_Crit_Enter before the code, and a call to @ref MXC_SYS_Crit_Exit after.
* @param code The code section to wrap.
*/
#define MXC_CRITICAL(code) {\
MXC_SYS_Crit_Enter();\
code;\
MXC_SYS_Crit_Exit();\
}
// clang-format on
/**
* @brief Reads the device USN.
* @param usn Pointer to store the USN.
* @param len Length of the USN buffer
* @param part Which USN part you want (0, 1, 2)
* @returns E_NO_ERROR if everything is successful.
*/
int MXC_SYS_GetUSN(uint8_t *usn, int len, int part);
/**
* @brief Determines if the selected peripheral clock is enabled.
* @param clock Enumeration for desired clock.
@ -143,7 +275,6 @@ int MXC_SYS_ClockSourceDisable (mxc_sys_system_clock_t clock);
/**
* @brief Select the system clock.
* @param clock Enumeration for desired clock.
* @param tmr Optional tmr pointer for timeout. NULL if undesired.
* @returns E_NO_ERROR if everything is successful.
*/
int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock);
@ -164,4 +295,4 @@ void MXC_SYS_Reset_Periph (mxc_sys_reset_t reset);
}
#endif
#endif /* _MXC_MXC_SYS_H_*/
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_SYS_H_

41
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/rtc.h
View File

@ -3,8 +3,8 @@
* @brief Real Time Clock (RTC) functions and prototypes.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _RTC_H_
#define _RTC_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_RTC_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_RTC_H_
/* **** Includes **** */
#include <stdint.h>
@ -56,6 +56,9 @@ extern "C" {
* @{
*/
#define MXC_RTC_MAX_SSEC (0xFFF + 1) // 0xFFF = max ssec counter value
#define MXC_RTC_TRIM_TMR_IRQ MXC_F_TMR_INTR_IRQ
/* **** Definitions **** */
/**
* @brief Bitmasks for each of the RTC's Frequency.
@ -101,18 +104,18 @@ int MXC_RTC_SetTimeofdayAlarm (uint32_t ras);
int MXC_RTC_SetSubsecondAlarm(uint32_t rssa);
/**
* @brief Start the Real Time Clock
* @brief Start the Real Time Clock (Blocking function)
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_Start(void);
/**
* @brief Stop the Real Time Clock
* @brief Stop the Real Time Clock (Blocking function)
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_Stop(void);
/**
* @brief Initialize the sec and ssec registers and enable RTC
* @brief Initialize the sec and ssec registers and enable RTC (Blocking function)
* @param sec set the RTC Sec counter (32-bit)
* @param ssec set the RTC Sub-second counter (8-bit)
* @retval returns Success or Fail, see \ref MXC_Error_Codes
@ -120,27 +123,27 @@ int MXC_RTC_Stop (void);
int MXC_RTC_Init(uint32_t sec, uint8_t ssec);
/**
* @brief Allow generation of Square Wave on the SQW pin
* @brief Allow generation of Square Wave on the SQW pin (Blocking function)
* @param fq Frequency output selection
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_SquareWaveStart(mxc_rtc_freq_sel_t fq);
/**
* @brief Stop the generation of square wave
* @brief Stop the generation of square wave (Blocking function)
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_SquareWaveStop(void);
/**
* @brief Set Trim register value
* @brief Set Trim register value (Blocking function)
* @param trm set the RTC Trim (8-bit, +/- 127)
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_Trim(int8_t trm);
/**
* @brief Enable Interurpts
* @brief Enable Interurpts (Blocking function)
* @param mask The bitwise OR of interrupts to enable.
* See #mxc_rtc_int_en_t for available choices.
* @retval returns Success or Fail, see \ref MXC_Error_Codes
@ -148,7 +151,7 @@ int MXC_RTC_Trim (int8_t trm);
int MXC_RTC_EnableInt(uint32_t mask);
/**
* @brief Disable Interurpts
* @brief Disable Interurpts (Blocking function)
* @param mask The mask of interrupts to disable.
* See #mxc_rtc_int_en_t for available choices.
* @retval returns Success or Fail, see \ref MXC_Error_Codes
@ -172,13 +175,13 @@ int MXC_RTC_GetFlags (void);
int MXC_RTC_ClearFlags(int flags);
/**
* @brief Get SubSecond
* @brief Get SubSecond or E_BUSY, see /ref MXC_ERROR_CODES
* @retval Returns subsecond value
*/
int MXC_RTC_GetSubSecond(void);
/**
* @brief Get Second
* @brief Get Second or E_BUSY, see /ref MXC_ERROR_CODES
* @retval returns second value
*/
int MXC_RTC_GetSecond(void);
@ -191,9 +194,15 @@ int MXC_RTC_GetSecond (void);
*/
int MXC_RTC_GetTime(uint32_t *sec, uint32_t *subsec);
/**
* @brief Get RTC busy flag.
* @retval returns Success or E_BUSY, see /ref MXC_ERROR_CODES
*/
int MXC_RTC_GetBusyFlag(void);
/**@} end of group rtc */
#ifdef __cplusplus
}
#endif
#endif /* _RTC_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_RTC_H_

31
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/spimss.h
View File

@ -3,8 +3,8 @@
* @brief Serial Peripheral Interface (SPIMSS) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,12 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _SPIMSS_H_
#define _SPIMSS_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPIMSS_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPIMSS_H_
/* **** Includes **** */
#include "mxc_device.h"
@ -60,7 +59,6 @@ extern "C" {
/* **** Definitions **** */
/**
* @brief Enumeration type for setting the number data lines to use for communication.
*/
@ -115,12 +113,10 @@ struct mxc_spimss_req {
* @param mode SPI mode for clock phase and polarity.
* @param freq Desired clock frequency.
* @param sys_cfg System configuration object
* @param drv_ssel 1 SSEL will be drive by driver
* 0 SSEL will NOT be drive by driver
*
* @return \c #E_NO_ERROR if successful, appropriate error otherwise
*/
int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg, unsigned drv_ssel);
int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg);
/**
* @brief Shutdown SPI module.
@ -179,19 +175,6 @@ int MXC_SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req);
*/
int MXC_SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req);
/**
* @brief Sets the TX data to transmit as a 'dummy' byte
*
* In single wire master mode, this data is transmitted on MOSI when performing
* an RX (MISO) only transaction. This defaults to 0.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
* @param defaultTXData Data to shift out in RX-only transactions
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPIMSS_SetDefaultTXData (mxc_spimss_req_t* spi, unsigned int defaultTXData);
/**
* @brief Aborts an Asynchronous request
*
@ -207,4 +190,4 @@ int MXC_SPIMSS_AbortAsync(mxc_spimss_req_t *req);
}
#endif
#endif /* _SPIMSS_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPIMSS_H_

48
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/tmr.h
View File

@ -3,8 +3,8 @@
* @brief Timer (TMR) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _TMR_H_
#define _TMR_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_TMR_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_TMR_H_
/* **** Includes **** */
#include "mxc_device.h"
@ -69,12 +69,16 @@ typedef enum {
TMR_PRES_32 = MXC_S_TMR_CN_PRES_DIV_BY_32, ///< Divide input clock by 32
TMR_PRES_64 = MXC_S_TMR_CN_PRES_DIV_BY_64, ///< Divide input clock by 64
TMR_PRES_128 = MXC_S_TMR_CN_PRES_DIV_BY_128, ///< Divide input clock by 128
TMR_PRES_256 = MXC_S_TMR_CN_PRES_DIV_BY_256, ///< Divide input clock by 256
TMR_PRES_512 = MXC_S_TMR_CN_PRES_DIV_BY_512, ///< Divide input clock by 512
TMR_PRES_1024 = MXC_S_TMR_CN_PRES_DIV_BY_1024, ///< Divide input clock by 1024
TMR_PRES_2048 = MXC_S_TMR_CN_PRES_DIV_BY_2048, ///< Divide input clock by 2048
TMR_PRES_4096 = MXC_S_TMR_CN_PRES_DIV_BY_4096, ///< Divide input clock by 4096
TMR_PRES_8192 = MXC_S_TMR_CN_PRES_DIV_BY_8192 ///< Divide input clock by 8192
TMR_PRES_256 = MXC_S_TMR_CN_PRES_DIV_BY_256 | MXC_F_TMR_CN_PRES3, ///< Divide input clock by 256
TMR_PRES_512 = MXC_S_TMR_CN_PRES_DIV_BY_512 | MXC_F_TMR_CN_PRES3, ///< Divide input clock by 512
TMR_PRES_1024 = MXC_S_TMR_CN_PRES_DIV_BY_1024 |
MXC_F_TMR_CN_PRES3, ///< Divide input clock by 1024
TMR_PRES_2048 = MXC_S_TMR_CN_PRES_DIV_BY_2048 |
MXC_F_TMR_CN_PRES3, ///< Divide input clock by 2048
TMR_PRES_4096 = MXC_S_TMR_CN_PRES_DIV_BY_4096 |
MXC_F_TMR_CN_PRES3, ///< Divide input clock by 4096
TMR_PRES_8192 = MXC_S_TMR_CN_PRES_DIV_BY_8192 |
MXC_F_TMR_CN_PRES3 ///< Divide input clock by 8192
} mxc_tmr_pres_t;
/**
@ -111,25 +115,12 @@ typedef enum {
TMR_UNIT_SEC, ///< Second Unit Indicator
} mxc_tmr_unit_t;
/**
* @brief Clock settings
* @note 8M and 32M clocks can be used for Timers 0,1,2 and 3
* 32K and 80K clocks can only be used for Timers 4 and 5
*/
typedef enum {
MXC_TMR_HFIO_CLK, ///< HFIO Clock
MXC_TMR_NANORING_CLK, ///< 8KHz Nanoring Clock
MXC_TMR_EXT_CLK, ///< External Clock
} mxc_tmr_clock_t;
/**
* @brief Timer Configuration
*/
typedef struct {
mxc_tmr_pres_t pres; ///< Desired timer prescaler
mxc_tmr_mode_t mode; ///< Desired timer mode
mxc_tmr_bit_mode_t bitMode; ///< Desired timer bits
mxc_tmr_clock_t clock; ///< Desired clock source
uint32_t cmp_cnt; ///< Compare register value in timer ticks
unsigned pol; ///< Polarity (0 or 1)
} mxc_tmr_cfg_t;
@ -199,12 +190,11 @@ uint32_t MXC_TMR_GetCount (mxc_tmr_regs_t* tmr);
/**
* @brief Calculate count for required frequency.
* @param tmr Timer
* @param clock Clock source.
* @param prescalar prescalar
* @param frequency required frequency.
* @return Returns the period count.
*/
uint32_t MXC_TMR_GetPeriod (mxc_tmr_regs_t* tmr, mxc_tmr_clock_t clock, uint32_t prescalar, uint32_t frequency);
uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, uint32_t prescalar, uint32_t frequency);
/**
* @brief Clear the timer interrupt.
@ -254,7 +244,7 @@ void MXC_TMR_SetCount (mxc_tmr_regs_t *tmr, uint32_t cnt);
* @param tmr The timer
* @param us microseconds to delay for
*/
void MXC_TMR_Delay (mxc_tmr_regs_t *tmr, unsigned long us);
void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us);
/**
* @brief Start a timer that will time out after a certain number of microseconds
@ -263,7 +253,7 @@ void MXC_TMR_Delay (mxc_tmr_regs_t *tmr, unsigned long us);
* @param tmr The timer
* @param us microseconds to time out after
*/
void MXC_TMR_TO_Start (mxc_tmr_regs_t *tmr, unsigned long us);
void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us);
/**
* @brief Check on time out timer
@ -340,4 +330,4 @@ int MXC_TMR_GetTime (mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tm
}
#endif
#endif /* _TMR_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_TMR_H_

55
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/uart.h
View File

@ -3,8 +3,8 @@
* @brief (UART) communications driver.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _MXC_UART_H_
#define _MXC_UART_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_UART_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_UART_H_
/***** Definitions *****/
#include "uart_regs.h"
@ -95,7 +95,6 @@ typedef enum {
MXC_UART_FLOW_EN_HIGH, ///< UART Flow Control Enabled, Active High
} mxc_uart_flow_t;
/**
* @brief The callback routine used to indicate the transaction has terminated.
*
@ -130,8 +129,8 @@ struct _mxc_uart_req_t {
///< and pad the MSB of the upper byte with zeros
uint32_t txLen; ///< Number of bytes to be sent from txData
uint32_t rxLen; ///< Number of bytes to be stored in rxData
uint32_t txCnt; ///< Number of bytes actually transmitted from txData
uint32_t rxCnt; ///< Number of bytes stored in rxData
volatile uint32_t txCnt; ///< Number of bytes actually transmitted from txData
volatile uint32_t rxCnt; ///< Number of bytes stored in rxData
mxc_uart_complete_cb_t callback; ///< Pointer to function called when transaction is complete
};
@ -386,8 +385,7 @@ int MXC_UART_Write (mxc_uart_regs_t* uart, uint8_t* byte, int* len);
*
* @return The number of bytes actually read.
*/
unsigned int MXC_UART_ReadRXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len);
unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len);
/**
* @brief Unloads bytes from the receive FIFO user DMA for longer reads.
@ -399,8 +397,8 @@ unsigned int MXC_UART_ReadRXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes,
*
* @return See \ref MXC_Error_Codes for a list of return values
*/
int MXC_UART_ReadRXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len, mxc_uart_dma_complete_cb_t callback);
int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len,
mxc_uart_dma_complete_cb_t callback);
/**
* @brief Get the number of bytes currently available in the receive FIFO.
@ -420,8 +418,7 @@ unsigned int MXC_UART_GetRXFIFOAvailable (mxc_uart_regs_t* uart);
*
* @return The number of bytes actually written.
*/
unsigned int MXC_UART_WriteTXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len);
unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len);
/**
* @brief Loads bytes into the transmit FIFO using DMA for longer writes
@ -433,8 +430,8 @@ unsigned int MXC_UART_WriteTXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes,
*
* @return See \ref MXC_Error_Codes for a list of return values
*/
int MXC_UART_WriteTXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len, mxc_uart_dma_complete_cb_t callback);
int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len,
mxc_uart_dma_complete_cb_t callback);
/**
* @brief Get the amount of free space available in the transmit FIFO.
@ -645,6 +642,8 @@ void MXC_UART_DMACallback (int ch, int error);
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal);
int MXC_UART_TxAsyncCallback(mxc_uart_regs_t *uart, int retVal);
int MXC_UART_RxAsyncCallback(mxc_uart_regs_t *uart, int retVal);
/**
* @brief stop any async callbacks
@ -654,6 +653,8 @@ int MXC_UART_AsyncCallback (mxc_uart_regs_t* uart, int retVal);
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_AsyncStop(mxc_uart_regs_t *uart);
int MXC_UART_TxAsyncStop(mxc_uart_regs_t *uart);
int MXC_UART_RxAsyncStop(mxc_uart_regs_t *uart);
/**
* @brief Abort any asynchronous requests in progress.
@ -667,6 +668,8 @@ int MXC_UART_AsyncStop (mxc_uart_regs_t* uart);
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_AbortAsync(mxc_uart_regs_t *uart);
int MXC_UART_TxAbortAsync(mxc_uart_regs_t *uart);
int MXC_UART_RxAbortAsync(mxc_uart_regs_t *uart);
/**
* @brief The processing function for asynchronous transactions.
@ -681,10 +684,28 @@ int MXC_UART_AbortAsync (mxc_uart_regs_t* uart);
*/
int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart);
/**
* @brief Provide TXCount for asynchronous transactions..
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return Returns transmit bytes (in FIFO).
*/
uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req);
/**
* @brief Provide RXCount for asynchronous transactions..
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return Returns receive bytes (in FIFO).
*/
uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t *req);
/**@} end of group uart */
#ifdef __cplusplus
}
#endif
#endif /* _MXC_UART_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_UART_H_

12
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/wdt.h
View File

@ -3,8 +3,8 @@
* @brief Watchdog timer (WDT) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/* Define to prevent redundant inclusion */
#ifndef _WDT_H_
#define _WDT_H_
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_WDT_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_WDT_H_
/* **** Includes **** */
#include <stdint.h>
@ -182,4 +182,4 @@ void MXC_WDT_ClearIntFlag (mxc_wdt_regs_t* wdt);
}
#endif
#endif /* _WDT_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_WDT_H_

10
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_me11.c
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
/****** Includes *******/
#include <stddef.h>
@ -164,8 +164,8 @@ int MXC_DMA_MemCpy(void* dest, void* src, int len, mxc_dma_complete_cb_t callbac
return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)MXC_DMA, dest, src, len, callback);
}
int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback)
int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst,
mxc_dma_trans_chain_t callback)
{
return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t *)MXC_DMA, config, firstSrcDst, callback);
}

110
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva.c
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,10 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#ifdef __CC_ARM // Keil
#pragma diag_suppress 68 // integer conversion resulted in a change of sign
#endif
******************************************************************************/
/****** Includes *******/
#include <stddef.h>
@ -65,10 +62,7 @@ typedef struct {
static unsigned int dma_initialized[MXC_DMA_INSTANCES] = { 0 };
static mxc_dma_channel_t dma_resource[MXC_DMA_CHANNELS];
static mxc_dma_highlevel_t memcpy_resource[MXC_DMA_CHANNELS];
#if USE_LOCK_IN_DRIVERS
static uint32_t dma_lock;
#endif
/****** Functions ******/
static void memcpy_callback(int ch, int error);
@ -174,8 +168,7 @@ int MXC_DMA_RevA_ReleaseChannel(int ch)
dma_resource[ch].regs->ctrl = 0;
dma_resource[ch].regs->status = dma_resource[ch].regs->status;
MXC_FreeLock(&dma_lock);
}
else {
} else {
return E_BAD_PARAM;
}
@ -188,67 +181,59 @@ int MXC_DMA_RevA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst)
/* Designed to be safe, not speedy. Should not be called often */
dma_resource[config.ch].regs->ctrl =
((config.srcinc_en ? MXC_F_DMA_REVA_CTRL_SRCINC : 0) |
(config.dstinc_en ? MXC_F_DMA_REVA_CTRL_DSTINC : 0) |
config.reqsel |
(config.dstinc_en ? MXC_F_DMA_REVA_CTRL_DSTINC : 0) | config.reqsel |
(config.srcwd << MXC_F_DMA_REVA_CTRL_SRCWD_POS) |
(config.dstwd << MXC_F_DMA_REVA_CTRL_DSTWD_POS));
}
else {
} else {
return E_BAD_PARAM;
}
return MXC_DMA_RevA_SetSrcDst(srcdst);
}
int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig)
{
if (CHECK_HANDLE(advConfig.ch) && (advConfig.burst_size > 0)) {
dma_resource[advConfig.ch].regs->ctrl &= ~(0x1F00FC0C); // Clear all fields we set here
/* Designed to be safe, not speedy. Should not be called often */
dma_resource[advConfig.ch].regs->ctrl |=
((advConfig.reqwait_en ? MXC_F_DMA_REVA_CTRL_TO_WAIT : 0) |
advConfig.prio | advConfig.tosel | advConfig.pssel |
(((advConfig.burst_size - 1) << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS) & MXC_F_DMA_REVA_CTRL_BURST_SIZE));
}
else {
((advConfig.reqwait_en ? MXC_F_DMA_REVA_CTRL_TO_WAIT : 0) | advConfig.prio |
advConfig.tosel | advConfig.pssel |
(((advConfig.burst_size - 1) << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS) &
MXC_F_DMA_REVA_CTRL_BURST_SIZE));
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_SetSrcDst(mxc_dma_srcdst_t srcdst)
{
if (CHECK_HANDLE(srcdst.ch)) {
dma_resource[srcdst.ch].regs->src = (unsigned int)srcdst.source;
dma_resource[srcdst.ch].regs->dst = (unsigned int)srcdst.dest;
dma_resource[srcdst.ch].regs->cnt = srcdst.len;
}
else {
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t *srcdst)
{
if (CHECK_HANDLE(srcdst->ch)) {
srcdst->source = (void *)dma_resource[srcdst->ch].regs->src;
srcdst->dest = (void *)dma_resource[srcdst->ch].regs->dst;
srcdst->len = (dma_resource[srcdst->ch].regs->cnt) & ~MXC_F_DMA_REVA_CNTRLD_EN;
}
else {
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst)
{
if (CHECK_HANDLE(srcdst.ch)) {
@ -258,42 +243,36 @@ int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst)
if (dma_resource[srcdst.ch].regs->ctrl & MXC_F_DMA_REVA_CTRL_EN) {
/* If channel is already running, set RLDEN to enable next reload */
dma_resource[srcdst.ch].regs->cntrld = MXC_F_DMA_REVA_CNTRLD_EN | srcdst.len;
}
else {
} else {
/* Otherwise, this is the initial setup, so DMA_Start() will handle setting that bit */
dma_resource[srcdst.ch].regs->cntrld = srcdst.len;
}
}
else {
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t *srcdst)
{
if (CHECK_HANDLE(srcdst->ch)) {
srcdst->source = (void *)dma_resource[srcdst->ch].regs->srcrld;
srcdst->dest = (void *)dma_resource[srcdst->ch].regs->dstrld;
srcdst->len = (dma_resource[srcdst->ch].regs->cntrld) & ~MXC_F_DMA_REVA_CNTRLD_EN;
}
else {
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_SetCallback(int ch, void (*callback)(int, int))
{
if (CHECK_HANDLE(ch)) {
/* Callback for interrupt handler, no checking is done, as NULL is valid for(none) */
dma_resource[ch].cb = callback;
}
else {
} else {
return E_BAD_PARAM;
}
@ -309,15 +288,13 @@ int MXC_DMA_RevA_SetChannelInterruptEn(int ch, bool chdis, bool ctz)
if (ctz) {
dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_CTZ_IE);
}
}
else {
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_GetChannelInterruptEn(int ch)
{
return E_NOT_SUPPORTED;
@ -326,9 +303,9 @@ int MXC_DMA_RevA_GetChannelInterruptEn(int ch)
int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags)
{
if (CHECK_HANDLE(ch)) {
dma_resource[ch].regs->ctrl |= (flags &(MXC_F_DMA_REVA_CTRL_DIS_IE|MXC_F_DMA_REVA_CTRL_CTZ_IE));
}
else {
dma_resource[ch].regs->ctrl |=
(flags & (MXC_F_DMA_REVA_CTRL_DIS_IE | MXC_F_DMA_REVA_CTRL_CTZ_IE));
} else {
return E_BAD_PARAM;
}
@ -338,9 +315,9 @@ int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags)
int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags)
{
if (CHECK_HANDLE(ch)) {
dma_resource[ch].regs->ctrl &= ~(flags &(MXC_F_DMA_REVA_CTRL_DIS_IE|MXC_F_DMA_REVA_CTRL_CTZ_IE));
}
else {
dma_resource[ch].regs->ctrl &=
~(flags & (MXC_F_DMA_REVA_CTRL_DIS_IE | MXC_F_DMA_REVA_CTRL_CTZ_IE));
} else {
return E_BAD_PARAM;
}
@ -354,8 +331,7 @@ int MXC_DMA_RevA_EnableInt(mxc_dma_reva_regs_t *dma, int ch)
ch %= MXC_DMA_CH_OFFSET;
#endif
dma->inten |= (1 << ch);
}
else {
} else {
return E_BAD_PARAM;
}
@ -369,8 +345,7 @@ int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch)
ch %= MXC_DMA_CH_OFFSET;
#endif
dma->inten &= ~(1 << ch);
}
else {
} else {
return E_BAD_PARAM;
}
@ -381,8 +356,7 @@ int MXC_DMA_RevA_ChannelGetFlags(int ch)
{
if (CHECK_HANDLE(ch)) {
return dma_resource[ch].regs->status;
}
else {
} else {
return E_BAD_PARAM;
}
@ -393,8 +367,7 @@ int MXC_DMA_RevA_ChannelClearFlags(int ch, int flags)
{
if (CHECK_HANDLE(ch)) {
dma_resource[ch].regs->status |= (flags & 0x5F); // Mask for Interrupt flags
}
else {
} else {
return E_BAD_PARAM;
}
@ -408,12 +381,10 @@ int MXC_DMA_RevA_Start(int ch)
if (dma_resource[ch].regs->cntrld) {
dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_EN | MXC_F_DMA_REVA_CTRL_RLDEN);
}
else {
} else {
dma_resource[ch].regs->ctrl |= MXC_F_DMA_REVA_CTRL_EN;
}
}
else {
} else {
return E_BAD_PARAM;
}
@ -424,8 +395,7 @@ int MXC_DMA_RevA_Stop(int ch)
{
if (CHECK_HANDLE(ch)) {
dma_resource[ch].regs->ctrl &= ~MXC_F_DMA_REVA_CTRL_EN;
}
else {
} else {
return E_BAD_PARAM;
}
@ -436,8 +406,7 @@ mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch)
{
if (CHECK_HANDLE(ch)) {
return (mxc_dma_ch_regs_t *)dma_resource[ch].regs;
}
else {
} else {
return NULL;
}
}
@ -455,11 +424,15 @@ void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma)
}
MXC_DMA_ChannelClearFlags(i, MXC_DMA_RevA_ChannelGetFlags(i));
// No need to check rest of the channels if no interrupt flags set.
if (dma->intfl == 0) {
break;
}
}
}
}
}
void memcpy_callback(int ch, int error)
{
@ -472,11 +445,15 @@ void memcpy_callback(int ch, int error)
callback(memcpy_resource[ch].dest);
// Release global objects and local resources
callback = NULL;
memcpy_resource[ch].userCallback = NULL;
memcpy_resource[ch].dest = NULL;
MXC_DMA_ReleaseChannel(ch);
}
int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len, mxc_dma_complete_cb_t callback)
int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len,
mxc_dma_complete_cb_t callback)
{
int retval;
mxc_dma_config_t config;
@ -540,10 +517,11 @@ void transfer_callback(int ch, int error)
// Call user callback for next transfer
// determine whether to load into the transfer slot or reload slot
// continue on or stop
while(1);
while (1) {}
}
int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback)
int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config,
mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback)
{
int retval, channel;

17
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva.h
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVA_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVA_H_
/****** Includes *******/
#include "dma_reva_regs.h"
@ -61,5 +64,9 @@ int MXC_DMA_RevA_Start(int ch);
int MXC_DMA_RevA_Stop(int ch);
mxc_dma_ch_regs_t *MXC_DMA_RevA_GetCHRegs(int ch);
void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma);
int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len, mxc_dma_complete_cb_t callback);
int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback);
int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len,
mxc_dma_complete_cb_t callback);
int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config,
mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback);
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVA_H_

39
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva_regs.h
View File

@ -3,8 +3,8 @@
* @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _DMA_REVA_REGS_H_
#define _DMA_REVA_REGS_H_
@ -86,14 +85,14 @@ extern "C" {
* Structure type to access the DMA Registers.
*/
typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x100:</tt> DMA CTRL Register */
__IO uint32_t status; /**< <tt>\b 0x104:</tt> DMA STATUS Register */
__IO uint32_t src; /**< <tt>\b 0x108:</tt> DMA SRC Register */
__IO uint32_t dst; /**< <tt>\b 0x10C:</tt> DMA DST Register */
__IO uint32_t cnt; /**< <tt>\b 0x110:</tt> DMA CNT Register */
__IO uint32_t srcrld; /**< <tt>\b 0x114:</tt> DMA SRCRLD Register */
__IO uint32_t dstrld; /**< <tt>\b 0x118:</tt> DMA DSTRLD Register */
__IO uint32_t cntrld; /**< <tt>\b 0x11C:</tt> DMA CNTRLD Register */
__IO uint32_t ctrl; /**< <tt>\b 0x000:</tt> DMA CTRL Register */
__IO uint32_t status; /**< <tt>\b 0x004:</tt> DMA STATUS Register */
__IO uint32_t src; /**< <tt>\b 0x008:</tt> DMA SRC Register */
__IO uint32_t dst; /**< <tt>\b 0x00C:</tt> DMA DST Register */
__IO uint32_t cnt; /**< <tt>\b 0x010:</tt> DMA CNT Register */
__IO uint32_t srcrld; /**< <tt>\b 0x014:</tt> DMA SRCRLD Register */
__IO uint32_t dstrld; /**< <tt>\b 0x018:</tt> DMA DSTRLD Register */
__IO uint32_t cntrld; /**< <tt>\b 0x01C:</tt> DMA CNTRLD Register */
} mxc_dma_reva_ch_regs_t;
typedef struct {
@ -110,14 +109,14 @@ typedef struct {
* @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address.
* @{
*/
#define MXC_R_DMA_REVA_CTRL ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
#define MXC_R_DMA_REVA_STATUS ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */
#define MXC_R_DMA_REVA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */
#define MXC_R_DMA_REVA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */
#define MXC_R_DMA_REVA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */
#define MXC_R_DMA_REVA_SRCRLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */
#define MXC_R_DMA_REVA_DSTRLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */
#define MXC_R_DMA_REVA_CNTRLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */
#define MXC_R_DMA_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
#define MXC_R_DMA_REVA_STATUS ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */
#define MXC_R_DMA_REVA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */
#define MXC_R_DMA_REVA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */
#define MXC_R_DMA_REVA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */
#define MXC_R_DMA_REVA_SRCRLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */
#define MXC_R_DMA_REVA_DSTRLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */
#define MXC_R_DMA_REVA_CNTRLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */
#define MXC_R_DMA_REVA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */
#define MXC_R_DMA_REVA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */
#define MXC_R_DMA_REVA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */

16
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_common.c
View File

@ -1,10 +1,10 @@
/**
* @file flc.h
* @brief Flash Controler driver.
* @file flc_common.c
* @brief Common functions for the flash controller drivers.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include <string.h>
@ -43,6 +42,7 @@
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "flc.h"
#include "flc_common.h"
#include "stdlib.h"
//******************************************************************************
@ -56,7 +56,6 @@ int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t* data)
{
volatile uint32_t *ptr;
for (ptr = (uint32_t *)address; ptr < (((uint32_t *)(address)) + length); ptr++, data++) {
if (*ptr != *data) {
return E_BAD_STATE;
@ -84,7 +83,6 @@ int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t* buffer)
// Align the address to a word boundary and read/write if we have to
if (address & 0x3) {
// Figure out how many bytes we have to write to round up the address
bytes_written = 4 - (address & 0x3);
@ -128,7 +126,6 @@ int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t* buffer)
length -= 16;
buffer8 += 16;
}
}
while (length >= 4) {
@ -167,4 +164,3 @@ void MXC_FLC_Com_Read(int address, void* buffer, int len)
{
memcpy(buffer, (void *)address, len);
}

22
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_common.h
View File

@ -1,11 +1,11 @@
/**
* @file flc.h
* @brief Flash Controller driver.
* @file flc_common.h
* @brief Common functions for the flash controller driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -35,9 +35,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_COMMON_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_COMMON_H_
/* **** Includes **** */
#include "mxc_sys.h"
@ -54,8 +55,6 @@ extern "C" {
/***** Definitions *****/
/***** Function Prototypes *****/
int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t *data);
@ -64,9 +63,14 @@ int MXC_FLC_Com_Write (uint32_t address, uint32_t length, uint32_t *buffer);
void MXC_FLC_Com_Read(int address, void *buffer, int len);
/**@} end of group flc */
volatile uint32_t *MXC_FLC_GetWELR(uint32_t address, uint32_t page_num);
volatile uint32_t *MXC_FLC_GetRLR(uint32_t address, uint32_t page_num);
/**@} end of group flc */
#ifdef __cplusplus
}
#endif
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_COMMON_H_

135
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_me11.c
View File

@ -1,10 +1,10 @@
/**
* @file flc.h
* @file flc_me11.c
* @brief Flash Controler driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include <string.h>
@ -49,26 +48,43 @@
//******************************************************************************
void MXC_FLC_ME11_Flash_Operation(void)
{
/*
This function should be called after modifying the contents of flash memory.
It flushes the instruction caches and line fill buffer.
It should be called _afterwards_ because after flash is modified the cache
may contain instructions that may no longer be valid. _Before_ the
flash modifications the ICC may contain relevant cached instructions related to
the incoming flash instructions (especially relevant in the case of external memory),
and these instructions will be valid up until the point that the modifications are made.
The line fill buffer is a FLC-related buffer that also may no longer be valid.
It's flushed by reading 2 pages of flash.
*/
/* Flush all instruction caches */
MXC_GCR->scon |= MXC_F_GCR_SCON_ICC0_FLUSH;
/* Wait for flush to complete */
while(MXC_GCR->scon & MXC_F_GCR_SCON_ICC0_FLUSH) {
}
while (MXC_GCR->scon & MXC_F_GCR_SCON_ICC0_FLUSH) {}
// Clear the line fill buffer by reading 2 pages from flash
volatile uint32_t *line_addr;
volatile uint32_t __unused line; // __unused attribute removes warning
line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE);
line = *line_addr;
line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE + MXC_FLASH_PAGE_SIZE);
line = *line_addr;
}
//******************************************************************************
int MXC_FLC_ME11_GetByAddress(mxc_flc_regs_t **flc, uint32_t addr)
{
// flash base start from 0x00000000
if ( addr < MXC_FLASH_MEM_SIZE ) {
if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) {
*flc = MXC_FLC;
}
else if((addr >= MXC_INFO_MEM_BASE) && (addr <(MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
} else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
*flc = MXC_FLC;
}
else {
} else {
return E_BAD_PARAM;
}
@ -78,14 +94,11 @@ int MXC_FLC_ME11_GetByAddress(mxc_flc_regs_t **flc, uint32_t addr)
//******************************************************************************
int MXC_FLC_ME11_GetPhysicalAddress(uint32_t addr, uint32_t *result)
{
// flash base start from 0x00000000
if ( addr < MXC_FLASH_MEM_SIZE ) {
if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) {
*result = addr & (MXC_FLASH_MEM_SIZE - 1);
}
else if((addr >= MXC_INFO_MEM_BASE) && (addr <(MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
} else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
*result = (addr & (MXC_INFO_MEM_SIZE - 1)) + MXC_FLASH_MEM_SIZE;
}
else {
} else {
return E_BAD_PARAM;
}
@ -93,12 +106,12 @@ int MXC_FLC_ME11_GetPhysicalAddress(uint32_t addr, uint32_t *result)
}
//******************************************************************************
int MXC_FLC_Init()
{
return E_NO_ERROR;
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section = ".flashprog"
#else
@ -109,12 +122,13 @@ int MXC_FLC_Busy(void)
return MXC_FLC_RevA_Busy();
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section = ".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
int MXC_FLC_ME11_PageErase(uint32_t address)
int MXC_FLC_PageErase(uint32_t address)
{
int err;
uint32_t addr;
@ -136,13 +150,14 @@ int MXC_FLC_ME11_PageErase(uint32_t address)
return err;
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section = ".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
// make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_ME11_Write128(uint32_t address, uint32_t *data)
int MXC_FLC_Write128(uint32_t address, uint32_t *data)
{
int err;
mxc_flc_regs_t *flc = NULL;
@ -177,7 +192,7 @@ int MXC_FLC_ME11_Write128(uint32_t address, uint32_t *data)
}
//******************************************************************************
int MXC_FLC_ME11_Write32(uint32_t address, uint32_t data)
int MXC_FLC_Write32(uint32_t address, uint32_t data)
{
uint32_t addr, aligned;
int err;
@ -200,11 +215,16 @@ int MXC_FLC_ME11_Write32(uint32_t address, uint32_t data)
return err;
}
return MXC_FLC_RevA_Write32((mxc_flc_reva_regs_t*) flc, address, data, addr);
err = MXC_FLC_RevA_Write32((mxc_flc_reva_regs_t *)flc, address, data, addr);
// Flush the cache
MXC_FLC_ME11_Flash_Operation();
return err;
}
int MXC_FLC_ME11_MassErase(void)
//******************************************************************************
int MXC_FLC_MassErase(void)
{
int err;
mxc_flc_regs_t *flc;
@ -219,10 +239,10 @@ int MXC_FLC_ME11_MassErase(void)
MXC_FLC_ME11_Flash_Operation();
return E_NO_ERROR;
}
int MXC_FLC_ME11_UnlockInfoBlock(uint32_t address)
//******************************************************************************
int MXC_FLC_UnlockInfoBlock(uint32_t address)
{
int err;
mxc_flc_regs_t *flc;
@ -233,7 +253,9 @@ int MXC_FLC_ME11_UnlockInfoBlock(uint32_t address)
return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t *)flc, address);
}
int MXC_FLC_ME11_LockInfoBlock(uint32_t address)
//******************************************************************************
int MXC_FLC_LockInfoBlock(uint32_t address)
{
int err;
mxc_flc_regs_t *flc;
@ -244,62 +266,67 @@ int MXC_FLC_ME11_LockInfoBlock(uint32_t address)
return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t *)flc, address);
}
/* ****************************************************************************** */
int MXC_FLC_MassErase(void)
{
return MXC_FLC_ME11_MassErase();
}
int MXC_FLC_PageErase(uint32_t address)
{
return MXC_FLC_ME11_PageErase(address);
}
int MXC_FLC_Write32(uint32_t address, uint32_t data)
{
return MXC_FLC_ME11_Write32(address, data);
}
int MXC_FLC_Write128(uint32_t address, uint32_t *data)
{
return MXC_FLC_ME11_Write128(address, data);
}
//******************************************************************************
int MXC_FLC_Write(uint32_t address, uint32_t length, uint32_t *buffer)
{
return MXC_FLC_Com_Write(address, length, buffer);
}
//******************************************************************************
void MXC_FLC_Read(int address, void *buffer, int len)
{
MXC_FLC_Com_Read(address, buffer, len);
}
//******************************************************************************
int MXC_FLC_EnableInt(uint32_t flags)
{
return MXC_FLC_RevA_EnableInt(flags);
}
//******************************************************************************
int MXC_FLC_DisableInt(uint32_t flags)
{
return MXC_FLC_RevA_DisableInt(flags);
}
//******************************************************************************
int MXC_FLC_GetFlags(void)
{
return MXC_FLC_RevA_GetFlags();
}
//******************************************************************************
int MXC_FLC_ClearFlags(uint32_t flags)
{
return MXC_FLC_RevA_ClearFlags(flags);
}
int MXC_FLC_UnlockInfoBlock(uint32_t address)
//******************************************************************************
int MXC_FLC_BlockPageWrite(uint32_t address)
{
return MXC_FLC_ME11_UnlockInfoBlock(address);
/* MAX32660 does not support flash page read and write locks */
return E_NOT_SUPPORTED;
}
int MXC_FLC_LockInfoBlock(uint32_t address)
//******************************************************************************
int MXC_FLC_BlockPageRead(uint32_t address)
{
return MXC_FLC_ME11_LockInfoBlock(address);
/* MAX32660 does not support flash page read and write locks */
return E_NOT_SUPPORTED;
}
//******************************************************************************
volatile uint32_t *MXC_FLC_GetWELR(uint32_t address, uint32_t page_num)
{
/* MAX32660 does not support flash page read and write locks */
return NULL;
}
//******************************************************************************
volatile uint32_t *MXC_FLC_GetRLR(uint32_t address, uint32_t page_num)
{
/* MAX32660 does not support flash page read and write locks */
return NULL;
}

151
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva.c
View File

@ -3,8 +3,8 @@
* @brief Flash Controler driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include <string.h>
@ -53,6 +52,11 @@
/* **** Definitions **** */
/* **** Globals **** */
#ifdef MXC_FLC0
static mxc_flc_reva_regs_t *flc_int = (mxc_flc_reva_regs_t *)MXC_FLC0;
#else
static mxc_flc_reva_regs_t *flc_int = (mxc_flc_reva_regs_t *)MXC_FLC;
#endif
/* **** Functions **** */
@ -64,7 +68,8 @@ __attribute__((section(".flashprog")))
#endif
static int MXC_busy_flc(mxc_flc_reva_regs_t *flc)
{
return (flc->ctrl & (MXC_F_FLC_REVA_CTRL_WR | MXC_F_FLC_REVA_CTRL_ME | MXC_F_FLC_REVA_CTRL_PGE));
return (flc->ctrl &
(MXC_F_FLC_REVA_CTRL_WR | MXC_F_FLC_REVA_CTRL_ME | MXC_F_FLC_REVA_CTRL_PGE));
}
//******************************************************************************
@ -132,13 +137,14 @@ int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc)
}
/* Write mass erase code */
flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL;
flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) |
MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL;
/* Issue mass erase command */
flc->ctrl |= MXC_F_FLC_REVA_CTRL_ME;
/* Wait until flash operation is complete */
while (MXC_busy_flc(flc));
while (MXC_busy_flc(flc)) {}
/* Lock flash */
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
@ -167,13 +173,14 @@ int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc, uint32_t addr)
}
/* Write page erase code */
flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE;
flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) |
MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE;
/* Issue page erase command */
flc->addr = addr;
flc->ctrl |= MXC_F_FLC_REVA_CTRL_PGE;
/* Wait until flash operation is complete */
while (MXC_FLC_Busy());
while (MXC_busy_flc(flc)) {}
/* Lock flash */
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
@ -187,7 +194,58 @@ int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc, uint32_t addr)
return E_NO_ERROR;
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section = ".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
// make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_RevA_Write32(mxc_flc_reva_regs_t *flc, uint32_t logicAddr, uint32_t data,
uint32_t physicalAddr)
{
int err;
// Address checked if it is byte addressable
if (logicAddr & 0x3) {
return E_BAD_PARAM;
}
// Check if the location trying to be written has 1's in to be written to 0's
if ((*(uint32_t *)logicAddr & data) != data) {
return E_BAD_STATE;
}
// Align address to 32-bit word
logicAddr = logicAddr & 0xfffffffc;
if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) {
return err;
}
// write 32-bits
flc->ctrl |= MXC_F_FLC_REVA_CTRL_WDTH;
// write the data
flc->addr = logicAddr;
flc->data[0] = data;
flc->ctrl |= MXC_F_FLC_REVA_CTRL_WR;
/* Wait until flash operation is complete */
while ((flc->ctrl & MXC_F_FLC_REVA_CTRL_PEND) != 0) {}
while (MXC_busy_flc(flc)) {}
/* Lock flash */
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
/* Check access violations */
if (flc->intr & MXC_F_FLC_REVA_INTR_AF) {
flc->intr &= ~MXC_F_FLC_REVA_INTR_AF;
return E_BAD_STATE;
}
return E_NO_ERROR;
}
//******************************************************************************
#if IAR_PRAGMAS
@ -196,7 +254,8 @@ int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc, uint32_t addr)
__attribute__((section(".flashprog")))
#endif
// make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t* flc, uint32_t logicAddr, uint32_t data, uint32_t physicalAddr)
int MXC_FLC_RevA_Write32Using128(mxc_flc_reva_regs_t *flc, uint32_t logicAddr, uint32_t data,
uint32_t physicalAddr)
{
int err, i = 0;
uint32_t byte;
@ -232,14 +291,11 @@ int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t* flc, uint32_t logicAddr, uint32_t
if (byte < 4) {
current_data[0] = data;
}
else if (byte < 8) {
} else if (byte < 8) {
current_data[1] = data;
}
else if (byte < 12) {
} else if (byte < 12) {
current_data[2] = data;
}
else {
} else {
current_data[3] = data;
}
@ -293,6 +349,18 @@ int MXC_FLC_RevA_Write128 (mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *da
return E_NO_ERROR;
}
//******************************************************************************
void MXC_FLC_RevA_SetFLCInt(mxc_flc_reva_regs_t *flc)
{
flc_int = flc;
}
//******************************************************************************
mxc_flc_reva_regs_t *MXC_FLC_RevA_GetFLCInt(void)
{
return flc_int;
}
//******************************************************************************
int MXC_FLC_RevA_EnableInt(uint32_t mask)
{
@ -304,7 +372,7 @@ int MXC_FLC_RevA_EnableInt(uint32_t mask)
}
/* Apply enables and write back, preserving the flags */
((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr |= mask;
flc_int->intr |= mask;
return E_NO_ERROR;
}
@ -320,7 +388,7 @@ int MXC_FLC_RevA_DisableInt(uint32_t mask)
}
/* Apply disables and write back, preserving the flags */
((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr &= ~mask;
flc_int->intr &= ~mask;
return E_NO_ERROR;
}
@ -328,7 +396,7 @@ int MXC_FLC_RevA_DisableInt(uint32_t mask)
//******************************************************************************
int MXC_FLC_RevA_GetFlags(void)
{
return (((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr & (MXC_F_FLC_REVA_INTR_DONE | MXC_F_FLC_REVA_INTR_AF));
return (flc_int->intr & (MXC_F_FLC_REVA_INTR_DONE | MXC_F_FLC_REVA_INTR_AF));
}
//******************************************************************************
@ -342,7 +410,7 @@ int MXC_FLC_RevA_ClearFlags(uint32_t mask)
}
/* Both flags are write zero clear */
((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr ^= mask;
flc_int->intr ^= mask;
return E_NO_ERROR;
}
@ -350,7 +418,8 @@ int MXC_FLC_RevA_ClearFlags(uint32_t mask)
//******************************************************************************
int MXC_FLC_RevA_UnlockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address)
{
if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
if ((address < MXC_INFO_MEM_BASE) ||
(address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
return E_BAD_PARAM;
}
@ -368,11 +437,49 @@ int MXC_FLC_RevA_UnlockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address)
//******************************************************************************
int MXC_FLC_RevA_LockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address)
{
if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
if ((address < MXC_INFO_MEM_BASE) ||
(address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
return E_BAD_PARAM;
}
flc->actrl = 0xDEADBEEF;
return E_NO_ERROR;
}
//******************************************************************************
int MXC_FLC_RevA_BlockPageWrite(uint32_t address, uint32_t bank_base)
{
uint32_t page_num;
page_num = address - bank_base; // Get page number in flash bank
page_num /= MXC_FLASH_PAGE_SIZE;
volatile uint32_t *welr = MXC_FLC_GetWELR(
address, page_num); // Get pointer to WELR register containing corresponding page bit
while (page_num > 31) { // Set corresponding bit in WELR register
page_num -= 32;
}
*welr = (1 << page_num);
return E_NO_ERROR;
}
//******************************************************************************
int MXC_FLC_RevA_BlockPageRead(uint32_t address, uint32_t bank_base)
{
uint32_t page_num;
page_num = address - bank_base; // Get page number in flash bank
page_num /= MXC_FLASH_PAGE_SIZE;
volatile uint32_t *rlr = MXC_FLC_GetRLR(
address, page_num); // Get pointer to RLR register containing corresponding page bit
while (page_num > 31) { // Set corresponding bit in WELR register
page_num -= 32;
}
*rlr = (1 << page_num);
return E_NO_ERROR;
}
/**@} end of group flc */

33
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva.h
View File

@ -1,10 +1,10 @@
/**
* @file flc.h
* @brief Flash Controler driver.
* @file flc_reva.h
* @brief Flash RevA Controller driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_H_
/* **** Includes **** */
#include <string.h>
@ -43,6 +45,7 @@
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "flc.h"
#include "flc_common.h"
#include "flc_reva_regs.h"
/**
@ -62,10 +65,18 @@ int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc);
int MXC_FLC_RevA_PageErase(mxc_flc_reva_regs_t *flc, uint32_t addr);
int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data, uint32_t physicalAddr);
int MXC_FLC_RevA_Write32(mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data,
uint32_t physicalAddr);
int MXC_FLC_RevA_Write32Using128(mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data,
uint32_t physicalAddr);
int MXC_FLC_RevA_Write128(mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data);
void MXC_FLC_RevA_SetFLCInt(mxc_flc_reva_regs_t *flc);
mxc_flc_reva_regs_t *MXC_FLC_RevA_GetFLCInt(void);
int MXC_FLC_RevA_EnableInt(uint32_t mask);
int MXC_FLC_RevA_DisableInt(uint32_t mask);
@ -77,9 +88,15 @@ int MXC_FLC_RevA_ClearFlags (uint32_t mask);
int MXC_FLC_RevA_UnlockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address);
int MXC_FLC_RevA_LockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address);
/**@} end of group flc */
int MXC_FLC_RevA_BlockPageWrite(uint32_t address, uint32_t bank_base);
int MXC_FLC_RevA_BlockPageRead(uint32_t address, uint32_t bank_base);
/**@} end of group flc */
#ifdef __cplusplus
}
#endif
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_H_

13
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva_regs.h
View File

@ -3,8 +3,8 @@
* @brief Registers, Bit Masks and Bit Positions for the FLC_REVA Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _FLC_REVA_REGS_H_
#define _FLC_REVA_REGS_H_
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -243,4 +242,4 @@ typedef struct {
}
#endif
#endif /* _FLC_REVA_REGS_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_

10
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c
View File

@ -1,5 +1,5 @@
/******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,13 +29,14 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include <stddef.h>
#include "gpio_common.h"
#include "mxc_device.h"
#include "mxc_assert.h"
#include "gpio.h"
#include <stddef.h>
/* **** Globals **** */
static void (*callback[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT])(void *);
@ -61,7 +62,8 @@ int MXC_GPIO_Common_Init(uint32_t portmask)
return E_NO_ERROR;
}
void MXC_GPIO_Common_RegisterCallback(const mxc_gpio_cfg_t* cfg, mxc_gpio_callback_fn func, void* cbdata)
void MXC_GPIO_Common_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn func,
void *cbdata)
{
uint32_t mask;
unsigned int pin;

14
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,10 +29,14 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_COMMON_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_COMMON_H_
/* **** Includes **** */
#include "gpio_regs.h"
#include "gpio.h"
#ifdef __cplusplus
extern "C" {
@ -41,7 +45,8 @@ extern "C" {
/* **** Function Prototypes **** */
int MXC_GPIO_Common_Init(uint32_t portmask);
void MXC_GPIO_Common_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, void *cbdata);
void MXC_GPIO_Common_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback,
void *cbdata);
void MXC_GPIO_Common_Handler(unsigned int port);
/**@} end of group gpio */
@ -50,3 +55,4 @@ void MXC_GPIO_Common_Handler (unsigned int port);
}
#endif
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_COMMON_H_

29
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_me11.c
View File

@ -1,5 +1,5 @@
/******************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,29 +29,27 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include <stddef.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_errors.h"
#include "gpio.h"
#include "gpio_reva.h"
#include "gpio_common.h"
#include <stddef.h>
#include "mxc_sys.h"
/* **** Functions **** */
int MXC_GPIO_Init(uint32_t portmask)
{
int retval = MXC_GPIO_Common_Init(portmask);
if (portmask & MXC_GPIO_PORT_0) {
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0);
}
return MXC_GPIO_Common_Init(portmask) + retval;
return MXC_GPIO_Common_Init(portmask);
}
int MXC_GPIO_Shutdown(uint32_t portmask)
@ -135,9 +133,7 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg)
}
// Configure the vssel
MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask);
return E_NO_ERROR;
return MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask);
}
uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t *port, uint32_t mask)
@ -209,3 +205,18 @@ int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t ma
{
return MXC_GPIO_RevA_SetVSSEL((mxc_gpio_reva_regs_t *)port, vssel, mask);
}
void MXC_GPIO_SetWakeEn(mxc_gpio_regs_t *port, uint32_t mask)
{
MXC_GPIO_RevA_SetWakeEn((mxc_gpio_reva_regs_t *)port, mask);
}
void MXC_GPIO_ClearWakeEn(mxc_gpio_regs_t *port, uint32_t mask)
{
MXC_GPIO_RevA_ClearWakeEn((mxc_gpio_reva_regs_t *)port, mask);
}
uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port)
{
return MXC_GPIO_RevA_GetWakeEn((mxc_gpio_reva_regs_t *)port);
}

62
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c
View File

@ -1,5 +1,5 @@
/******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,16 +29,16 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include <stddef.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_errors.h"
#include "gpio.h"
#include "gpio_reva.h"
#include "gpio_common.h"
#include <stddef.h>
/* **** Functions **** */
uint32_t MXC_GPIO_RevA_InGet(mxc_gpio_reva_regs_t *port, uint32_t mask)
@ -77,7 +77,7 @@ int MXC_GPIO_RevA_IntConfig(const mxc_gpio_cfg_t* cfg, mxc_gpio_int_pol_t pol)
switch (pol) {
case MXC_GPIO_INT_HIGH:
gpio->intpol &= ~cfg->mask;
gpio->intpol |= cfg->mask;
gpio->dualedge &= ~cfg->mask;
gpio->intmode &= ~cfg->mask;
break;
@ -89,7 +89,7 @@ int MXC_GPIO_RevA_IntConfig(const mxc_gpio_cfg_t* cfg, mxc_gpio_int_pol_t pol)
break;
case MXC_GPIO_INT_LOW: /* MXC_GPIO_INT_LOW */
gpio->intpol |= cfg->mask;
gpio->intpol &= ~cfg->mask;
gpio->dualedge &= ~cfg->mask;
gpio->intmode &= ~cfg->mask;
break;
@ -153,12 +153,19 @@ int MXC_GPIO_RevA_SetVSSEL (mxc_gpio_reva_regs_t* port, mxc_gpio_vssel_t vssel,
int MXC_GPIO_RevA_SetAF(mxc_gpio_reva_regs_t *port, mxc_gpio_func_t func, uint32_t mask)
{
//This is required for new devices going forward.
port->inen |= mask;
//Switch to I/O mode first
port->en0_set = mask;
switch (func) {
case MXC_GPIO_FUNC_IN:
port->outen_clr = mask;
port->en0_set = mask;
port->en1_clr = mask;
port->en2_clr = mask;
port->en3_clr = mask;
break;
case MXC_GPIO_FUNC_OUT:
@ -166,32 +173,46 @@ int MXC_GPIO_RevA_SetAF (mxc_gpio_reva_regs_t* port, mxc_gpio_func_t func, uint3
port->en0_set = mask;
port->en1_clr = mask;
port->en2_clr = mask;
port->en3_clr = mask;
break;
case MXC_GPIO_FUNC_ALT1:
port->en0_clr = mask;
port->en1_clr = mask;
port->en3_clr = mask;
port->en2_clr = mask;
port->en1_clr = mask;
port->en0_clr = mask;
break;
case MXC_GPIO_FUNC_ALT2:
port->en0_clr = mask;
port->en1_set = mask;
port->en3_clr = mask;
port->en2_clr = mask;
port->en1_set = mask;
port->en0_clr = mask;
break;
#if TARGET_NUM != 32650
case MXC_GPIO_FUNC_ALT3:
port->en0_clr = mask;
port->en1_clr = mask;
port->en3_clr = mask;
port->en2_set = mask;
port->en1_clr = mask;
port->en0_clr = mask;
break;
case MXC_GPIO_FUNC_ALT4:
port->en0_clr = mask;
port->en1_set = mask;
port->en3_clr = mask;
port->en2_set = mask;
port->en1_set = mask;
port->en0_clr = mask;
break;
#if TARGET_NUM == 32662
case MXC_GPIO_FUNC_ALT5:
port->en3_set = mask;
port->en2_clr = mask;
port->en1_clr = mask;
port->en0_clr = mask;
break;
#endif
#endif
default:
return E_BAD_PARAM;
@ -199,3 +220,18 @@ int MXC_GPIO_RevA_SetAF (mxc_gpio_reva_regs_t* port, mxc_gpio_func_t func, uint3
return E_NO_ERROR;
}
void MXC_GPIO_RevA_SetWakeEn(mxc_gpio_reva_regs_t *port, uint32_t mask)
{
port->wken_set = mask;
}
void MXC_GPIO_RevA_ClearWakeEn(mxc_gpio_reva_regs_t *port, uint32_t mask)
{
port->wken_clr = mask;
}
uint32_t MXC_GPIO_RevA_GetWakeEn(mxc_gpio_reva_regs_t *port)
{
return port->wken;
}

18
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.h
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_H_
/* **** Includes **** */
#include "gpio_reva_regs.h"
@ -38,8 +41,6 @@
extern "C" {
#endif
/**
* @brief Enumeration type for the pullup strength on a given pin.
*/
@ -61,13 +62,16 @@ void MXC_GPIO_RevA_EnableInt (mxc_gpio_reva_regs_t* port, uint32_t mask);
void MXC_GPIO_RevA_DisableInt(mxc_gpio_reva_regs_t *port, uint32_t mask);
void MXC_GPIO_RevA_ClearFlags(mxc_gpio_reva_regs_t *port, uint32_t flags);
uint32_t MXC_GPIO_RevA_GetFlags(mxc_gpio_reva_regs_t *port);
#if TARGET_NUM != 32650
int MXC_GPIO_RevA_SetVSSEL(mxc_gpio_reva_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask);
#endif
int MXC_GPIO_RevA_SetAF(mxc_gpio_reva_regs_t *port, mxc_gpio_func_t func, uint32_t mask);
void MXC_GPIO_RevA_SetWakeEn(mxc_gpio_reva_regs_t *port, uint32_t mask);
void MXC_GPIO_RevA_ClearWakeEn(mxc_gpio_reva_regs_t *port, uint32_t mask);
uint32_t MXC_GPIO_RevA_GetWakeEn(mxc_gpio_reva_regs_t *port);
/**@} end of group gpio */
#ifdef __cplusplus
}
#endif
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_H_

450
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_regs.h
View File

@ -1,10 +1,10 @@
/**
* @file gpio_regs.h
* @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
* @file gpio_reva_regs.h
* @brief Registers, Bit Masks and Bit Positions for the GPIO_REVA Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _GPIO_REVA_REGS_H_
#define _GPIO_REVA_REGS_H_
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_REGS_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -75,123 +74,129 @@ extern "C" {
/* **** Definitions **** */
/**
* @ingroup gpio
* @defgroup gpio_registers GPIO_Registers
* @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
* @ingroup gpio_reva
* @defgroup gpio_reva_registers GPIO_REVA_Registers
* @brief Registers, Bit Masks and Bit Positions for the GPIO_REVA Peripheral Module.
* @details Individual I/O for each GPIO
*/
/**
* @ingroup gpio_registers
* Structure type to access the GPIO Registers.
* @ingroup gpio_reva_registers
* Structure type to access the GPIO_REVA Registers.
*/
typedef struct {
__IO uint32_t en0; /**< <tt>\b 0x00:</tt> GPIO EN0 Register */
__IO uint32_t en0_set; /**< <tt>\b 0x04:</tt> GPIO EN0_SET Register */
__IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */
__IO uint32_t outen; /**< <tt>\b 0x0C:</tt> GPIO OUTEN Register */
__IO uint32_t outen_set; /**< <tt>\b 0x10:</tt> GPIO OUTEN_SET Register */
__IO uint32_t outen_clr; /**< <tt>\b 0x14:</tt> GPIO OUTEN_CLR Register */
__IO uint32_t out; /**< <tt>\b 0x18:</tt> GPIO OUT Register */
__O uint32_t out_set; /**< <tt>\b 0x1C:</tt> GPIO OUT_SET Register */
__O uint32_t out_clr; /**< <tt>\b 0x20:</tt> GPIO OUT_CLR Register */
__I uint32_t in; /**< <tt>\b 0x24:</tt> GPIO IN Register */
__IO uint32_t intmode; /**< <tt>\b 0x28:</tt> GPIO INTMODE Register */
__IO uint32_t intpol; /**< <tt>\b 0x2C:</tt> GPIO INTPOL Register */
__IO uint32_t inen; /**< <tt>\b 0x30:</tt> GPIO INEN Register */
__IO uint32_t inten; /**< <tt>\b 0x34:</tt> GPIO INTEN Register */
__IO uint32_t inten_set; /**< <tt>\b 0x38:</tt> GPIO INTEN_SET Register */
__IO uint32_t inten_clr; /**< <tt>\b 0x3C:</tt> GPIO INTEN_CLR Register */
__I uint32_t intfl; /**< <tt>\b 0x40:</tt> GPIO INTFL Register */
__IO uint32_t en0; /**< <tt>\b 0x00:</tt> GPIO_REVA EN0 Register */
__IO uint32_t en0_set; /**< <tt>\b 0x04:</tt> GPIO_REVA EN0_SET Register */
__IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO_REVA EN0_CLR Register */
__IO uint32_t outen; /**< <tt>\b 0x0C:</tt> GPIO_REVA OUTEN Register */
__IO uint32_t outen_set; /**< <tt>\b 0x10:</tt> GPIO_REVA OUTEN_SET Register */
__IO uint32_t outen_clr; /**< <tt>\b 0x14:</tt> GPIO_REVA OUTEN_CLR Register */
__IO uint32_t out; /**< <tt>\b 0x18:</tt> GPIO_REVA OUT Register */
__O uint32_t out_set; /**< <tt>\b 0x1C:</tt> GPIO_REVA OUT_SET Register */
__O uint32_t out_clr; /**< <tt>\b 0x20:</tt> GPIO_REVA OUT_CLR Register */
__I uint32_t in; /**< <tt>\b 0x24:</tt> GPIO_REVA IN Register */
__IO uint32_t intmode; /**< <tt>\b 0x28:</tt> GPIO_REVA INTMODE Register */
__IO uint32_t intpol; /**< <tt>\b 0x2C:</tt> GPIO_REVA INTPOL Register */
__IO uint32_t inen; /**< <tt>\b 0x30:</tt> GPIO_REVA INEN Register */
__IO uint32_t inten; /**< <tt>\b 0x34:</tt> GPIO_REVA INTEN Register */
__IO uint32_t inten_set; /**< <tt>\b 0x38:</tt> GPIO_REVA INTEN_SET Register */
__IO uint32_t inten_clr; /**< <tt>\b 0x3C:</tt> GPIO_REVA INTEN_CLR Register */
__I uint32_t intfl; /**< <tt>\b 0x40:</tt> GPIO_REVA INTFL Register */
__R uint32_t rsv_0x44;
__IO uint32_t intfl_clr; /**< <tt>\b 0x48:</tt> GPIO INTFL_CLR Register */
__IO uint32_t wken; /**< <tt>\b 0x4C:</tt> GPIO WKEN Register */
__IO uint32_t wken_set; /**< <tt>\b 0x50:</tt> GPIO WKEN_SET Register */
__IO uint32_t wken_clr; /**< <tt>\b 0x54:</tt> GPIO WKEN_CLR Register */
__IO uint32_t intfl_clr; /**< <tt>\b 0x48:</tt> GPIO_REVA INTFL_CLR Register */
__IO uint32_t wken; /**< <tt>\b 0x4C:</tt> GPIO_REVA WKEN Register */
__IO uint32_t wken_set; /**< <tt>\b 0x50:</tt> GPIO_REVA WKEN_SET Register */
__IO uint32_t wken_clr; /**< <tt>\b 0x54:</tt> GPIO_REVA WKEN_CLR Register */
__R uint32_t rsv_0x58;
__IO uint32_t dualedge; /**< <tt>\b 0x5C:</tt> GPIO DUALEDGE Register */
__IO uint32_t padctrl0; /**< <tt>\b 0x60:</tt> GPIO PADCTRL0 Register */
__IO uint32_t padctrl1; /**< <tt>\b 0x64:</tt> GPIO PADCTRL1 Register */
__IO uint32_t en1; /**< <tt>\b 0x68:</tt> GPIO EN1 Register */
__IO uint32_t en1_set; /**< <tt>\b 0x6C:</tt> GPIO EN1_SET Register */
__IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */
__IO uint32_t en2; /**< <tt>\b 0x74:</tt> GPIO EN2 Register */
__IO uint32_t en2_set; /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */
__IO uint32_t en2_clr; /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */
__R uint32_t rsv_0x80_0xa7[10];
__IO uint32_t hysen; /**< <tt>\b 0xA8:</tt> GPIO HYSEN Register */
__IO uint32_t srsel; /**< <tt>\b 0xAC:</tt> GPIO SRSEL Register */
__IO uint32_t ds0; /**< <tt>\b 0xB0:</tt> GPIO DS0 Register */
__IO uint32_t ds1; /**< <tt>\b 0xB4:</tt> GPIO DS1 Register */
__IO uint32_t ps; /**< <tt>\b 0xB8:</tt> GPIO PS Register */
__IO uint32_t dualedge; /**< <tt>\b 0x5C:</tt> GPIO_REVA DUALEDGE Register */
__IO uint32_t padctrl0; /**< <tt>\b 0x60:</tt> GPIO_REVA PADCTRL0 Register */
__IO uint32_t padctrl1; /**< <tt>\b 0x64:</tt> GPIO_REVA PADCTRL1 Register */
__IO uint32_t en1; /**< <tt>\b 0x68:</tt> GPIO_REVA EN1 Register */
__IO uint32_t en1_set; /**< <tt>\b 0x6C:</tt> GPIO_REVA EN1_SET Register */
__IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO_REVA EN1_CLR Register */
__IO uint32_t en2; /**< <tt>\b 0x74:</tt> GPIO_REVA EN2 Register */
__IO uint32_t en2_set; /**< <tt>\b 0x78:</tt> GPIO_REVA EN2_SET Register */
__IO uint32_t en2_clr; /**< <tt>\b 0x7C:</tt> GPIO_REVA EN2_CLR Register */
__IO uint32_t en3; /**< <tt>\b 0x80:</tt> GPIO_REVA EN3 Register */
__IO uint32_t en3_set; /**< <tt>\b 0x84:</tt> GPIO_REVA EN3_SET Register */
__IO uint32_t en3_clr; /**< <tt>\b 0x88:</tt> GPIO_REVA EN3_CLR Register */
__R uint32_t rsv_0x8c_0xa7[7];
__IO uint32_t hysen; /**< <tt>\b 0xA8:</tt> GPIO_REVA HYSEN Register */
__IO uint32_t srsel; /**< <tt>\b 0xAC:</tt> GPIO_REVA SRSEL Register */
__IO uint32_t ds0; /**< <tt>\b 0xB0:</tt> GPIO_REVA DS0 Register */
__IO uint32_t ds1; /**< <tt>\b 0xB4:</tt> GPIO_REVA DS1 Register */
__IO uint32_t ps; /**< <tt>\b 0xB8:</tt> GPIO_REVA PS Register */
__R uint32_t rsv_0xbc;
__IO uint32_t vssel; /**< <tt>\b 0xC0:</tt> GPIO VSSEL Register */
__IO uint32_t vssel; /**< <tt>\b 0xC0:</tt> GPIO_REVA VSSEL Register */
} mxc_gpio_reva_regs_t;
/* Register offsets for module GPIO */
/* Register offsets for module GPIO_REVA */
/**
* @ingroup gpio_registers
* @defgroup GPIO_Register_Offsets Register Offsets
* @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address.
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_Register_Offsets Register Offsets
* @brief GPIO_REVA Peripheral Register Offsets from the GPIO_REVA Base Peripheral Address.
* @{
*/
#define MXC_R_GPIO_REVA_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> 0x0000</tt> */
#define MXC_R_GPIO_REVA_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> 0x0004</tt> */
#define MXC_R_GPIO_REVA_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> 0x0008</tt> */
#define MXC_R_GPIO_REVA_OUTEN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> 0x000C</tt> */
#define MXC_R_GPIO_REVA_OUTEN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> 0x0010</tt> */
#define MXC_R_GPIO_REVA_OUTEN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> 0x0014</tt> */
#define MXC_R_GPIO_REVA_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> 0x0018</tt> */
#define MXC_R_GPIO_REVA_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> 0x001C</tt> */
#define MXC_R_GPIO_REVA_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> 0x0020</tt> */
#define MXC_R_GPIO_REVA_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */
#define MXC_R_GPIO_REVA_INTMODE ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */
#define MXC_R_GPIO_REVA_INTPOL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */
#define MXC_R_GPIO_REVA_INEN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt> 0x0030</tt> */
#define MXC_R_GPIO_REVA_INTEN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */
#define MXC_R_GPIO_REVA_INTEN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */
#define MXC_R_GPIO_REVA_INTEN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */
#define MXC_R_GPIO_REVA_INTFL ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> 0x0040</tt> */
#define MXC_R_GPIO_REVA_INTFL_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> 0x0048</tt> */
#define MXC_R_GPIO_REVA_WKEN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> 0x004C</tt> */
#define MXC_R_GPIO_REVA_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */
#define MXC_R_GPIO_REVA_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */
#define MXC_R_GPIO_REVA_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */
#define MXC_R_GPIO_REVA_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */
#define MXC_R_GPIO_REVA_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */
#define MXC_R_GPIO_REVA_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */
#define MXC_R_GPIO_REVA_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */
#define MXC_R_GPIO_REVA_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */
#define MXC_R_GPIO_REVA_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> 0x0074</tt> */
#define MXC_R_GPIO_REVA_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> 0x0078</tt> */
#define MXC_R_GPIO_REVA_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> 0x007C</tt> */
#define MXC_R_GPIO_REVA_HYSEN ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> 0x00A8</tt> */
#define MXC_R_GPIO_REVA_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> 0x00AC</tt> */
#define MXC_R_GPIO_REVA_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> 0x00B0</tt> */
#define MXC_R_GPIO_REVA_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> 0x00B4</tt> */
#define MXC_R_GPIO_REVA_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> 0x00B8</tt> */
#define MXC_R_GPIO_REVA_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> 0x00C0</tt> */
/**@} end of group gpio_registers */
#define MXC_R_GPIO_REVA_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0000</tt> */
#define MXC_R_GPIO_REVA_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0004</tt> */
#define MXC_R_GPIO_REVA_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0008</tt> */
#define MXC_R_GPIO_REVA_OUTEN ((uint32_t)0x0000000CUL) /**< Offset from GPIO_REVA Base Address: <tt> 0x000C</tt> */
#define MXC_R_GPIO_REVA_OUTEN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0010</tt> */
#define MXC_R_GPIO_REVA_OUTEN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0014</tt> */
#define MXC_R_GPIO_REVA_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0018</tt> */
#define MXC_R_GPIO_REVA_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO_REVA Base Address: <tt> 0x001C</tt> */
#define MXC_R_GPIO_REVA_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0020</tt> */
#define MXC_R_GPIO_REVA_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0024</tt> */
#define MXC_R_GPIO_REVA_INTMODE ((uint32_t)0x00000028UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0028</tt> */
#define MXC_R_GPIO_REVA_INTPOL ((uint32_t)0x0000002CUL) /**< Offset from GPIO_REVA Base Address: <tt> 0x002C</tt> */
#define MXC_R_GPIO_REVA_INEN ((uint32_t)0x00000030UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0030</tt> */
#define MXC_R_GPIO_REVA_INTEN ((uint32_t)0x00000034UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0034</tt> */
#define MXC_R_GPIO_REVA_INTEN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0038</tt> */
#define MXC_R_GPIO_REVA_INTEN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO_REVA Base Address: <tt> 0x003C</tt> */
#define MXC_R_GPIO_REVA_INTFL ((uint32_t)0x00000040UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0040</tt> */
#define MXC_R_GPIO_REVA_INTFL_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0048</tt> */
#define MXC_R_GPIO_REVA_WKEN ((uint32_t)0x0000004CUL) /**< Offset from GPIO_REVA Base Address: <tt> 0x004C</tt> */
#define MXC_R_GPIO_REVA_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0050</tt> */
#define MXC_R_GPIO_REVA_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0054</tt> */
#define MXC_R_GPIO_REVA_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO_REVA Base Address: <tt> 0x005C</tt> */
#define MXC_R_GPIO_REVA_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0060</tt> */
#define MXC_R_GPIO_REVA_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0064</tt> */
#define MXC_R_GPIO_REVA_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0068</tt> */
#define MXC_R_GPIO_REVA_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO_REVA Base Address: <tt> 0x006C</tt> */
#define MXC_R_GPIO_REVA_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0070</tt> */
#define MXC_R_GPIO_REVA_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0074</tt> */
#define MXC_R_GPIO_REVA_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0078</tt> */
#define MXC_R_GPIO_REVA_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO_REVA Base Address: <tt> 0x007C</tt> */
#define MXC_R_GPIO_REVA_EN3 ((uint32_t)0x00000080UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0080</tt> */
#define MXC_R_GPIO_REVA_EN3_SET ((uint32_t)0x00000084UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0084</tt> */
#define MXC_R_GPIO_REVA_EN3_CLR ((uint32_t)0x00000088UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0088</tt> */
#define MXC_R_GPIO_REVA_HYSEN ((uint32_t)0x000000A8UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x00A8</tt> */
#define MXC_R_GPIO_REVA_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO_REVA Base Address: <tt> 0x00AC</tt> */
#define MXC_R_GPIO_REVA_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x00B0</tt> */
#define MXC_R_GPIO_REVA_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x00B4</tt> */
#define MXC_R_GPIO_REVA_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x00B8</tt> */
#define MXC_R_GPIO_REVA_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x00C0</tt> */
/**@} end of group gpio_reva_registers */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN0 GPIO_EN0
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_EN0 GPIO_REVA_EN0
* @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one
* GPIO pin on the associated port.
* @{
*/
#define MXC_F_GPIO_REVA_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_REVA_EN Position */
#define MXC_F_GPIO_REVA_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */
#define MXC_F_GPIO_REVA_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */
#define MXC_V_GPIO_REVA_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */
#define MXC_S_GPIO_REVA_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_REVA_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */
#define MXC_V_GPIO_REVA_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */
#define MXC_S_GPIO_REVA_EN0_GPIO_EN_GPIO (MXC_V_GPIO_REVA_EN0_GPIO_EN_GPIO << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */
/**@} end of group GPIO_EN0_Register */
/**@} end of group GPIO_REVA_EN0_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN0_SET GPIO_EN0_SET
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_EN0_SET GPIO_REVA_EN0_SET
* @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this
* register sets the bits in the same positions in GPIO_EN to 1, without affecting
* other bits in that register.
@ -200,11 +205,11 @@ typedef struct {
#define MXC_F_GPIO_REVA_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */
#define MXC_F_GPIO_REVA_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */
/**@} end of group GPIO_EN0_SET_Register */
/**@} end of group GPIO_REVA_EN0_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN0_CLR GPIO_EN0_CLR
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_EN0_CLR GPIO_REVA_EN0_CLR
* @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this
* register clears the bits in the same positions in GPIO_EN to 0, without
* affecting other bits in that register.
@ -213,11 +218,11 @@ typedef struct {
#define MXC_F_GPIO_REVA_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */
#define MXC_F_GPIO_REVA_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */
/**@} end of group GPIO_EN0_CLR_Register */
/**@} end of group GPIO_REVA_EN0_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUTEN GPIO_OUTEN
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_OUTEN GPIO_REVA_OUTEN
* @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one
* GPIO pin in the associated port.
* @{
@ -229,11 +234,11 @@ typedef struct {
#define MXC_V_GPIO_REVA_OUTEN_EN_EN ((uint32_t)0x1UL) /**< OUTEN_EN_EN Value */
#define MXC_S_GPIO_REVA_OUTEN_EN_EN (MXC_V_GPIO_REVA_OUTEN_EN_EN << MXC_F_GPIO_REVA_OUTEN_EN_POS) /**< OUTEN_EN_EN Setting */
/**@} end of group GPIO_OUTEN_Register */
/**@} end of group GPIO_REVA_OUTEN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUTEN_SET GPIO_OUTEN_SET
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_OUTEN_SET GPIO_REVA_OUTEN_SET
* @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits
* in this register sets the bits in the same positions in GPIO_OUT_EN to 1,
* without affecting other bits in that register.
@ -242,11 +247,11 @@ typedef struct {
#define MXC_F_GPIO_REVA_OUTEN_SET_ALL_POS 0 /**< OUTEN_SET_ALL Position */
#define MXC_F_GPIO_REVA_OUTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */
/**@} end of group GPIO_OUTEN_SET_Register */
/**@} end of group GPIO_REVA_OUTEN_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUTEN_CLR GPIO_OUTEN_CLR
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_OUTEN_CLR GPIO_REVA_OUTEN_CLR
* @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more
* bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0,
* without affecting other bits in that register.
@ -255,11 +260,11 @@ typedef struct {
#define MXC_F_GPIO_REVA_OUTEN_CLR_ALL_POS 0 /**< OUTEN_CLR_ALL Position */
#define MXC_F_GPIO_REVA_OUTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */
/**@} end of group GPIO_OUTEN_CLR_Register */
/**@} end of group GPIO_REVA_OUTEN_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT GPIO_OUT
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_OUT GPIO_REVA_OUT
* @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the
* associated port. This register can be written either directly, or by using the
* GPIO_OUT_SET and GPIO_OUT_CLR registers.
@ -272,11 +277,11 @@ typedef struct {
#define MXC_V_GPIO_REVA_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */
#define MXC_S_GPIO_REVA_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_REVA_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */
/**@} end of group GPIO_OUT_Register */
/**@} end of group GPIO_REVA_OUT_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_SET GPIO_OUT_SET
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_OUT_SET GPIO_REVA_OUT_SET
* @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits
* in the same positions in GPIO_OUT to 1, without affecting other bits in that
* register.
@ -289,11 +294,11 @@ typedef struct {
#define MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */
#define MXC_S_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */
/**@} end of group GPIO_OUT_SET_Register */
/**@} end of group GPIO_REVA_OUT_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_CLR GPIO_OUT_CLR
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_OUT_CLR GPIO_REVA_OUT_CLR
* @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the
* bits in the same positions in GPIO_OUT to 0, without affecting other bits in
* that register.
@ -302,11 +307,11 @@ typedef struct {
#define MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */
#define MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */
/**@} end of group GPIO_OUT_CLR_Register */
/**@} end of group GPIO_REVA_OUT_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_IN GPIO_IN
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_IN GPIO_REVA_IN
* @brief GPIO Input Register. Read-only register to read from the logic states of the
* GPIO pins on this port.
* @{
@ -314,11 +319,11 @@ typedef struct {
#define MXC_F_GPIO_REVA_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */
#define MXC_F_GPIO_REVA_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */
/**@} end of group GPIO_IN_Register */
/**@} end of group GPIO_REVA_IN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INTMODE GPIO_INTMODE
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_INTMODE GPIO_REVA_INTMODE
* @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt
* mode setting for the associated GPIO pin on this port.
* @{
@ -330,11 +335,11 @@ typedef struct {
#define MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE ((uint32_t)0x1UL) /**< INTMODE_GPIO_INTMODE_EDGE Value */
#define MXC_S_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE (MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_EDGE Setting */
/**@} end of group GPIO_INTMODE_Register */
/**@} end of group GPIO_REVA_INTMODE_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INTPOL GPIO_INTPOL
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_INTPOL GPIO_REVA_INTPOL
* @brief GPIO Interrupt Polarity Register. Each bit in this register controls the
* interrupt polarity setting for one GPIO pin in the associated port.
* @{
@ -346,27 +351,27 @@ typedef struct {
#define MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING ((uint32_t)0x1UL) /**< INTPOL_GPIO_INTPOL_RISING Value */
#define MXC_S_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING (MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_RISING Setting */
/**@} end of group GPIO_INTPOL_Register */
/**@} end of group GPIO_REVA_INTPOL_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INTEN GPIO_INTEN
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_INTEN GPIO_REVA_INTEN
* @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO
* interrupt enable for the associated pin on the GPIO port.
* @{
*/
#define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS 0 /**< INTEN_GPIO_REVA_INTEN Position */
#define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS 0 /**< INTEN_GPIO_INTEN Position */
#define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS)) /**< INTEN_GPIO_INTEN Mask */
#define MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_DIS ((uint32_t)0x0UL) /**< INTEN_GPIO_INTEN_DIS Value */
#define MXC_S_GPIO_REVA_INTEN_GPIO_INTEN_DIS (MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_DIS << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_DIS Setting */
#define MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_EN ((uint32_t)0x1UL) /**< INTEN_GPIO_INTEN_EN Value */
#define MXC_S_GPIO_REVA_INTEN_GPIO_INTEN_EN (MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_EN << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_EN Setting */
/**@} end of group GPIO_INTEN_Register */
/**@} end of group GPIO_REVA_INTEN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INTEN_SET GPIO_INTEN_SET
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_INTEN_SET GPIO_REVA_INTEN_SET
* @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets
* the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits
* in that register.
@ -379,11 +384,11 @@ typedef struct {
#define MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET ((uint32_t)0x1UL) /**< INTEN_SET_GPIO_INTEN_SET_SET Value */
#define MXC_S_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET (MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_SET Setting */
/**@} end of group GPIO_INTEN_SET_Register */
/**@} end of group GPIO_REVA_INTEN_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INTEN_CLR GPIO_INTEN_CLR
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_INTEN_CLR GPIO_REVA_INTEN_CLR
* @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register
* clears the bits in the same positions in GPIO_INT_EN to 0, without affecting
* other bits in that register.
@ -396,11 +401,11 @@ typedef struct {
#define MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Value */
#define MXC_S_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR (MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Setting */
/**@} end of group GPIO_INTEN_CLR_Register */
/**@} end of group GPIO_REVA_INTEN_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INTFL GPIO_INTFL
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_INTFL GPIO_REVA_INTFL
* @brief GPIO Interrupt Status Register. Each bit in this register contains the pending
* interrupt status for the associated GPIO pin in this port.
* @{
@ -412,11 +417,11 @@ typedef struct {
#define MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_PENDING ((uint32_t)0x1UL) /**< INTFL_GPIO_INTFL_PENDING Value */
#define MXC_S_GPIO_REVA_INTFL_GPIO_INTFL_PENDING (MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_PENDING << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_PENDING Setting */
/**@} end of group GPIO_INTFL_Register */
/**@} end of group GPIO_REVA_INTFL_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INTFL_CLR GPIO_INTFL_CLR
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_INTFL_CLR GPIO_REVA_INTFL_CLR
* @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the
* bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits
* in that register.
@ -425,27 +430,27 @@ typedef struct {
#define MXC_F_GPIO_REVA_INTFL_CLR_ALL_POS 0 /**< INTFL_CLR_ALL Position */
#define MXC_F_GPIO_REVA_INTFL_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */
/**@} end of group GPIO_INTFL_CLR_Register */
/**@} end of group GPIO_REVA_INTFL_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_WKEN GPIO_WKEN
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_WKEN GPIO_REVA_WKEN
* @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup
* enable for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS 0 /**< WKEN_GPIO_WKEN Position */
#define MXC_F_GPIO_REVA_WKEN_GPIO_WKEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS)) /**< WKEN_GPIO_WKEN Mask */
#define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_DIS ((uint32_t)0x0UL) /**< WKEN_GPIO_REVA_WKEN_DIS Value */
#define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_DIS (MXC_V_GPIO_WKEN_REVA_GPIO_WKEN_DIS << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_DIS Setting */
#define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_DIS ((uint32_t)0x0UL) /**< WKEN_GPIO_WKEN_DIS Value */
#define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_DIS (MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_DIS << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_DIS Setting */
#define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_EN ((uint32_t)0x1UL) /**< WKEN_GPIO_WKEN_EN Value */
#define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_EN (MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_EN << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_EN Setting */
/**@} end of group GPIO_WKEN_Register */
/**@} end of group GPIO_REVA_WKEN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_WKEN_SET GPIO_WKEN_SET
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_WKEN_SET GPIO_REVA_WKEN_SET
* @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the
* bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in
* that register.
@ -454,11 +459,11 @@ typedef struct {
#define MXC_F_GPIO_REVA_WKEN_SET_ALL_POS 0 /**< WKEN_SET_ALL Position */
#define MXC_F_GPIO_REVA_WKEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */
/**@} end of group GPIO_WKEN_SET_Register */
/**@} end of group GPIO_REVA_WKEN_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_WKEN_CLR GPIO_WKEN_CLR
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_WKEN_CLR GPIO_REVA_WKEN_CLR
* @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears
* the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other
* bits in that register.
@ -467,11 +472,11 @@ typedef struct {
#define MXC_F_GPIO_REVA_WKEN_CLR_ALL_POS 0 /**< WKEN_CLR_ALL Position */
#define MXC_F_GPIO_REVA_WKEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */
/**@} end of group GPIO_WKEN_CLR_Register */
/**@} end of group GPIO_REVA_WKEN_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_DUALEDGE GPIO_DUALEDGE
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_DUALEDGE GPIO_REVA_DUALEDGE
* @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual
* edge mode for the associated GPIO pin in this port.
* @{
@ -483,11 +488,11 @@ typedef struct {
#define MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN ((uint32_t)0x1UL) /**< DUALEDGE_GPIO_DUALEDGE_EN Value */
#define MXC_S_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN (MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_EN Setting */
/**@} end of group GPIO_DUALEDGE_Register */
/**@} end of group GPIO_REVA_DUALEDGE_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_PADCTRL0 GPIO_PADCTRL0
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_PADCTRL0 GPIO_REVA_PADCTRL0
* @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for
* the associated GPIO pin in this port.
* @{
@ -501,11 +506,11 @@ typedef struct {
#define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD ((uint32_t)0x2UL) /**< PADCTRL0_GPIO_PADCTRL0_PD Value */
#define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PD Setting */
/**@} end of group GPIO_PADCTRL0_Register */
/**@} end of group GPIO_REVA_PADCTRL0_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_PADCTRL1 GPIO_PADCTRL1
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_PADCTRL1 GPIO_REVA_PADCTRL1
* @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for
* the associated GPIO pin in this port.
* @{
@ -519,11 +524,11 @@ typedef struct {
#define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD ((uint32_t)0x2UL) /**< PADCTRL1_GPIO_PADCTRL1_PD Value */
#define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PD Setting */
/**@} end of group GPIO_PADCTRL1_Register */
/**@} end of group GPIO_REVA_PADCTRL1_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN1 GPIO_EN1
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_EN1 GPIO_REVA_EN1
* @brief GPIO Alternate Function Enable Register. Each bit in this register selects
* between primary/secondary functions for the associated GPIO pin in this port.
* @{
@ -535,11 +540,11 @@ typedef struct {
#define MXC_V_GPIO_REVA_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */
#define MXC_S_GPIO_REVA_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_REVA_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */
/**@} end of group GPIO_EN1_Register */
/**@} end of group GPIO_REVA_EN1_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN1_SET GPIO_EN1_SET
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_EN1_SET GPIO_REVA_EN1_SET
* @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register
* sets the bits in the same positions in GPIO_EN1 to 1, without affecting other
* bits in that register.
@ -548,11 +553,11 @@ typedef struct {
#define MXC_F_GPIO_REVA_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */
#define MXC_F_GPIO_REVA_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */
/**@} end of group GPIO_EN1_SET_Register */
/**@} end of group GPIO_REVA_EN1_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN1_CLR GPIO_EN1_CLR
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_EN1_CLR GPIO_REVA_EN1_CLR
* @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register
* clears the bits in the same positions in GPIO_EN1 to 0, without affecting other
* bits in that register.
@ -561,11 +566,11 @@ typedef struct {
#define MXC_F_GPIO_REVA_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */
#define MXC_F_GPIO_REVA_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */
/**@} end of group GPIO_EN1_CLR_Register */
/**@} end of group GPIO_REVA_EN1_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN2 GPIO_EN2
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_EN2 GPIO_REVA_EN2
* @brief GPIO Alternate Function Enable Register. Each bit in this register selects
* between primary/secondary functions for the associated GPIO pin in this port.
* @{
@ -577,11 +582,11 @@ typedef struct {
#define MXC_V_GPIO_REVA_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */
#define MXC_S_GPIO_REVA_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_REVA_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */
/**@} end of group GPIO_EN2_Register */
/**@} end of group GPIO_REVA_EN2_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN2_SET GPIO_EN2_SET
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_EN2_SET GPIO_REVA_EN2_SET
* @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register
* sets the bits in the same positions in GPIO_EN2 to 1, without affecting other
* bits in that register.
@ -590,11 +595,11 @@ typedef struct {
#define MXC_F_GPIO_REVA_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */
#define MXC_F_GPIO_REVA_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */
/**@} end of group GPIO_EN2_SET_Register */
/**@} end of group GPIO_REVA_EN2_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN2_CLR GPIO_EN2_CLR
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_EN2_CLR GPIO_REVA_EN2_CLR
* @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this
* register clears the bits in the same positions in GPIO_EN2 to 0, without
* affecting other bits in that register.
@ -603,22 +608,64 @@ typedef struct {
#define MXC_F_GPIO_REVA_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */
#define MXC_F_GPIO_REVA_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */
/**@} end of group GPIO_EN2_CLR_Register */
/**@} end of group GPIO_REVA_EN2_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_HYSEN GPIO_HYSEN
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_EN3 GPIO_REVA_EN3
* @brief GPIO Alternate Function Enable Register. Each bit in this register selects
* between primary/secondary functions for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_REVA_EN3_GPIO_EN3_POS 0 /**< EN3_GPIO_EN3 Position */
#define MXC_F_GPIO_REVA_EN3_GPIO_EN3 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN3_GPIO_EN3_POS)) /**< EN3_GPIO_EN3 Mask */
#define MXC_V_GPIO_REVA_EN3_GPIO_EN3_PRIMARY ((uint32_t)0x0UL) /**< EN3_GPIO_EN3_PRIMARY Value */
#define MXC_S_GPIO_REVA_EN3_GPIO_EN3_PRIMARY (MXC_V_GPIO_REVA_EN3_GPIO_EN3_PRIMARY << MXC_F_GPIO_REVA_EN3_GPIO_EN3_POS) /**< EN3_GPIO_EN3_PRIMARY Setting */
#define MXC_V_GPIO_REVA_EN3_GPIO_EN3_SECONDARY ((uint32_t)0x1UL) /**< EN3_GPIO_EN3_SECONDARY Value */
#define MXC_S_GPIO_REVA_EN3_GPIO_EN3_SECONDARY (MXC_V_GPIO_REVA_EN3_GPIO_EN3_SECONDARY << MXC_F_GPIO_REVA_EN3_GPIO_EN3_POS) /**< EN3_GPIO_EN3_SECONDARY Setting */
/**@} end of group GPIO_REVA_EN3_Register */
/**
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_EN3_SET GPIO_REVA_EN3_SET
* @brief GPIO Alternate Function 3 Set. Writing a 1 to one or more bits in this register
* sets the bits in the same positions in GPIO_EN3 to 1, without affecting other
* bits in that register.
* @{
*/
#define MXC_F_GPIO_REVA_EN3_SET_ALL_POS 0 /**< EN3_SET_ALL Position */
#define MXC_F_GPIO_REVA_EN3_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN3_SET_ALL_POS)) /**< EN3_SET_ALL Mask */
/**@} end of group GPIO_REVA_EN3_SET_Register */
/**
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_EN3_CLR GPIO_REVA_EN3_CLR
* @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this
* register clears the bits in the same positions in GPIO_EN3 to 0, without
* affecting other bits in that register.
* @{
*/
#define MXC_F_GPIO_REVA_EN3_CLR_ALL_POS 0 /**< EN3_CLR_ALL Position */
#define MXC_F_GPIO_REVA_EN3_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN3_CLR_ALL_POS)) /**< EN3_CLR_ALL Mask */
/**@} end of group GPIO_REVA_EN3_CLR_Register */
/**
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_HYSEN GPIO_REVA_HYSEN
* @brief GPIO Input Hysteresis Enable.
* @{
*/
#define MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN_POS 0 /**< HYSEN_GPIO_HYSEN Position */
#define MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN_POS)) /**< HYSEN_GPIO_HYSEN Mask */
/**@} end of group GPIO_HYSEN_Register */
/**@} end of group GPIO_REVA_HYSEN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_SRSEL GPIO_SRSEL
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_SRSEL GPIO_REVA_SRSEL
* @brief GPIO Slew Rate Enable Register.
* @{
*/
@ -629,11 +676,11 @@ typedef struct {
#define MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW ((uint32_t)0x1UL) /**< SRSEL_GPIO_SRSEL_SLOW Value */
#define MXC_S_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW (MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_SLOW Setting */
/**@} end of group GPIO_SRSEL_Register */
/**@} end of group GPIO_REVA_SRSEL_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_DS0 GPIO_DS0
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_DS0 GPIO_REVA_DS0
* @brief GPIO Drive Strength Register. Each bit in this register selects the drive
* strength for the associated GPIO pin in this port. Refer to the Datasheet for
* sink/source current of GPIO pins in each mode.
@ -646,11 +693,11 @@ typedef struct {
#define MXC_V_GPIO_REVA_DS0_GPIO_DS0_HD ((uint32_t)0x1UL) /**< DS0_GPIO_DS0_HD Value */
#define MXC_S_GPIO_REVA_DS0_GPIO_DS0_HD (MXC_V_GPIO_REVA_DS0_GPIO_DS0_HD << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_HD Setting */
/**@} end of group GPIO_DS0_Register */
/**@} end of group GPIO_REVA_DS0_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_DS1 GPIO_DS1
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_DS1 GPIO_REVA_DS1
* @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive
* strength for the associated GPIO pin in this port. Refer to the Datasheet for
* sink/source current of GPIO pins in each mode.
@ -659,32 +706,33 @@ typedef struct {
#define MXC_F_GPIO_REVA_DS1_GPIO_DS1_POS 0 /**< DS1_GPIO_DS1 Position */
#define MXC_F_GPIO_REVA_DS1_GPIO_DS1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DS1_GPIO_DS1_POS)) /**< DS1_GPIO_DS1 Mask */
/**@} end of group GPIO_DS1_Register */
/**@} end of group GPIO_REVA_DS1_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_PS GPIO_PS
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_PS GPIO_REVA_PS
* @brief GPIO Pull Select Mode.
* @{
*/
#define MXC_F_GPIO_REVA_PS_ALL_POS 0 /**< PS_ALL Position */
#define MXC_F_GPIO_REVA_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PS_ALL_POS)) /**< PS_ALL Mask */
/**@} end of group GPIO_PS_Register */
/**@} end of group GPIO_REVA_PS_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_VSSEL GPIO_VSSEL
* @ingroup gpio_reva_registers
* @defgroup GPIO_REVA_VSSEL GPIO_REVA_VSSEL
* @brief GPIO Voltage Select.
* @{
*/
#define MXC_F_GPIO_REVA_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */
#define MXC_F_GPIO_REVA_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */
/**@} end of group GPIO_VSSEL_Register */
/**@} end of group GPIO_REVA_VSSEL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _GPIO_REVA_REGS_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_REGS_H_

18
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#include <stdio.h>
#include <stddef.h>
@ -42,7 +42,7 @@
#include "mxc_delay.h"
#include "i2c_regs.h"
#include "dma_regs.h"
#include "mxc_i2c.h"
#include "i2c.h"
#include "i2c_reva.h"
/* **** Definitions **** */
@ -382,6 +382,16 @@ unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t *i2c)
return MXC_I2C_RevA_GetTXThreshold((mxc_i2c_reva_regs_t *)i2c);
}
void MXC_I2C_AsyncStop(mxc_i2c_regs_t *i2c)
{
MXC_I2C_RevA_AsyncStop((mxc_i2c_reva_regs_t *)i2c);
}
void MXC_I2C_AbortAsync(mxc_i2c_regs_t *i2c)
{
MXC_I2C_RevA_AbortAsync((mxc_i2c_reva_regs_t *)i2c);
}
void MXC_I2C_AsyncHandler(mxc_i2c_regs_t *i2c)
{
MXC_I2C_RevA_AsyncHandler((mxc_i2c_reva_regs_t *)i2c, interruptCheck);

99
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#include <stdio.h>
#include <stddef.h>
@ -40,7 +40,7 @@
#include "mxc_sys.h"
#include "mxc_delay.h"
#include "i2c_regs.h"
#include "mxc_i2c.h"
#include "i2c.h"
#include "i2c_reva.h"
#include "dma.h"
@ -66,9 +66,8 @@ void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c);
void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c);
void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum);
int MXC_I2C_RevA_DMAHandler(mxc_i2c_reva_req_t *req);
unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
mxc_i2c_reva_slave_handler_t callback,
unsigned int interruptEnables, int *retVal);
void MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback,
uint32_t *int_en, int *retVal);
/* ************************************************************************* */
/* Control/Configuration functions */
@ -145,8 +144,8 @@ int MXC_I2C_RevA_SetFrequency(mxc_i2c_reva_regs_t *i2c, unsigned int hz)
return E_NULL_PTR;
}
if (hz > MXC_I2C_REVA_FASTPLUS_SPEED) {
// We're going to enable high speed
if (hz > MXC_I2C_REVA_FASTPLUS_SPEED && hz <= MXC_I2C_REVA_HIGH_SPEED) {
// Enable high speed mode
int hsLowClks, hsHiClks;
// Calculate the period of SCL and set up 33% duty cycle
@ -164,7 +163,17 @@ int MXC_I2C_RevA_SetFrequency(mxc_i2c_reva_regs_t *i2c, unsigned int hz)
return E_BAD_PARAM;
}
hsLowClks = (hsLowClks << MXC_F_I2C_REVA_HSCLK_LO_POS) & MXC_F_I2C_REVA_HSCLK_LO;
hsHiClks = (hsHiClks << MXC_F_I2C_REVA_HSCLK_HI_POS) & MXC_F_I2C_REVA_HSCLK_HI;
i2c->hsclk = (hsLowClks | hsHiClks);
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_HS_EN;
hz = MXC_I2C_REVA_FAST_SPEED; // High speed preambles will be sent at 400kHz
} else if (hz > MXC_I2C_REVA_HIGH_SPEED) {
return E_BAD_PARAM;
}
// Calculate the period of SCL, 50% duty cycle
@ -1017,9 +1026,12 @@ void MXC_I2C_RevA_DMACallback(int ch, int error)
int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback,
uint32_t interruptCheck)
{
unsigned int interruptEnables = interruptCheck;
int retVal = E_NO_ERROR;
uint32_t int_en[2];
int_en[0] = interruptCheck;
int_en[1] = 0;
if (MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c) < 0) {
return E_BAD_PARAM;
}
@ -1050,8 +1062,8 @@ int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_h
// I2C_EVT_UNDERFLOW
// I2C_EVT_OVERFLOW
while (interruptEnables > 0) {
interruptEnables = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, interruptEnables, &retVal);
while (int_en[0] > 0 || int_en[1] > 0) {
MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, int_en, &retVal);
}
return retVal;
@ -1270,9 +1282,8 @@ void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum)
}
}
unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
mxc_i2c_reva_slave_handler_t callback,
unsigned int interruptEnables, int *retVal)
void MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback,
uint32_t *int_en, int *retVal)
{
uint32_t tFlags = i2c->intfl0;
*retVal = E_NO_ERROR;
@ -1294,8 +1305,7 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
// I2C_EVT_TRANS_COMP
// I2C_EVT_UNDERFLOW
// I2C_EVT_OVERFLOW
if (!(interruptEnables &
(MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH |
if (!(int_en[0] & (MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH |
MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) {
// The STOPERR/STARTERR interrupt that's enabled here could fire before we are addressed
// (fires anytime a stop/start is detected out of sequence).
@ -1310,11 +1320,12 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts
MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c);
MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c);
interruptEnables = 0;
int_en[0] = 0;
int_en[1] = 0;
AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL;
}
if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV)) {
if (int_en[0] & MXC_F_I2C_REVA_INTFL0_RX_THD || int_en[1] & MXC_F_I2C_REVA_INTFL1_RX_OV) {
if (tFlags & MXC_F_I2C_REVA_INTFL0_RX_THD) {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_RX_THRESH, NULL);
@ -1332,8 +1343,8 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
}
}
if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN |
MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT)) {
if (int_en[0] & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT) ||
int_en[1] & MXC_F_I2C_REVA_INTFL1_TX_UN) {
if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_THD) {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_TX_THRESH, NULL);
@ -1358,7 +1369,8 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
}
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT;
interruptEnables = 0;
int_en[0] = 0;
int_en[1] = 0;
AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL;
}
}
@ -1371,7 +1383,8 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
}
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_STOP;
interruptEnables = 0;
int_en[0] = 0;
int_en[1] = 0;
AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL;
}
}
@ -1383,8 +1396,10 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV |
MXC_I2C_REVA_ERROR;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT;
int_en[0] = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE | MXC_I2C_REVA_ERROR;
int_en[1] = MXC_F_I2C_REVA_INTFL1_RX_OV;
}
if (tFlags & MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH) {
@ -1394,8 +1409,9 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN |
MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR;
int_en[0] = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT |
MXC_I2C_REVA_ERROR;
int_en[1] = MXC_F_I2C_REVA_INTFL1_TX_UN;
}
if (tFlags & MXC_F_I2C_REVA_INTFL0_ADDR_MATCH) {
@ -1404,19 +1420,23 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL);
}
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN |
MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT;
int_en[0] = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT |
MXC_I2C_REVA_ERROR;
int_en[1] = MXC_F_I2C_REVA_INTFL1_TX_UN;
} else {
if (callback != NULL) {
callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL);
}
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV |
int_en[0] = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE |
MXC_I2C_REVA_ERROR;
int_en[1] = MXC_F_I2C_REVA_INTFL1_RX_OV;
}
} else if (tFlags & MXC_I2C_REVA_ERROR) {
*retVal = E_COMM_ERR;
@ -1429,17 +1449,17 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
MXC_I2C_REVA_INTFL1_MASK); // clear all i2c interrupts
MXC_I2C_RevA_ClearTXFIFO(i2c);
MXC_I2C_RevA_ClearRXFIFO(i2c);
interruptEnables = 0;
int_en[0] = 0;
int_en[1] = 0;
AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL;
}
return interruptEnables;
}
void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck)
{
int i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c);
int slaveRetVal;
uint32_t int_en[2];
if (i2cNum < 0) {
return;
@ -1449,6 +1469,13 @@ void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck
MXC_I2C_RevA_MasterAsyncHandler(i2cNum);
} else {
mxc_i2c_reva_slave_handler_t callback = (mxc_i2c_reva_slave_handler_t)AsyncRequests[i2cNum];
i2c->inten0 = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, i2c->inten0, &slaveRetVal);
int_en[0] = i2c->inten0;
int_en[1] = i2c->inten1;
MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, int_en, &slaveRetVal);
i2c->inten0 = int_en[0];
i2c->inten1 = int_en[1];
}
}

13
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_
@ -51,7 +51,7 @@
#define MXC_I2C_REVA_STD_MODE 100000
#define MXC_I2C_REVA_FAST_SPEED 400000
#define MXC_I2C_REVA_FASTPLUS_SPEED 1000000
#define MXC_I2C_REVA_HS_MODE 3400000
#define MXC_I2C_REVA_HIGH_SPEED 3400000
#define MXC_I2C_REVA_INTFL0_MASK 0x00FFFFFF
#define MXC_I2C_REVA_INTFL1_MASK 0x00000007
@ -163,9 +163,8 @@ void MXC_I2C_RevA_AsyncCallback(mxc_i2c_reva_regs_t *i2c, int retVal);
void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c);
void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c);
void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum);
unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
mxc_i2c_reva_slave_handler_t callback,
unsigned int interruptEnables, int *retVal);
void MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback,
uint32_t *int_en, int *retVal);
void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck);
void MXC_I2C_RevA_DMACallback(int ch, int error);

7
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h
View File

@ -3,8 +3,8 @@
* @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_

5
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_common.c
View File

@ -1,5 +1,5 @@
/******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include "mxc_device.h"
@ -38,6 +38,7 @@
#include "mxc_sys.h"
#include "icc.h"
#include "icc_reva.h"
#include "icc_common.h"
void MXC_ICC_Com_Flush(void)
{

11
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_common.h
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_COMMON_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_COMMON_H_
/* **** Includes **** */
#include "mxc_sys.h"
@ -48,3 +51,5 @@ void MXC_ICC_Com_Flush(void);
#ifdef __cplusplus
}
#endif
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_COMMON_H_

4
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_me11.c
View File

@ -1,5 +1,5 @@
/******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include "mxc_device.h"

9
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva.c
View File

@ -1,5 +1,5 @@
/******************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include <stddef.h>
@ -38,6 +38,7 @@
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "icc.h"
#include "icc_reva.h"
#include "icc_reva_regs.h"
/* **** Definitions **** */
@ -77,11 +78,11 @@ void MXC_ICC_RevA_Enable(mxc_icc_reva_regs_t *icc)
icc->ctrl &= ~MXC_F_ICC_REVA_CTRL_EN;
icc->invalidate = 1;
while(!(MXC_ICC_Ready(icc)));
while (!(MXC_ICC_Ready(icc))) {}
// Enable Cache
icc->ctrl |= MXC_F_ICC_REVA_CTRL_EN;
while(!(MXC_ICC_Ready(icc)));
while (!(MXC_ICC_Ready(icc))) {}
}
void MXC_ICC_RevA_Disable(mxc_icc_reva_regs_t *icc)

11
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva.h
View File

@ -1,8 +1,8 @@
/******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software");,
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
@ -29,7 +29,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_H_
/* **** Includes **** */
#include "mxc_device.h"
@ -48,3 +51,5 @@
int MXC_ICC_RevA_ID(mxc_icc_reva_regs_t *icc, mxc_icc_info_t cid);
void MXC_ICC_RevA_Enable(mxc_icc_reva_regs_t *icc);
void MXC_ICC_RevA_Disable(mxc_icc_reva_regs_t *icc);
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_H_

14
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva_regs.h
View File

@ -3,8 +3,8 @@
* @brief Registers, Bit Masks and Bit Positions for the ICC_REVA Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,11 +34,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _ICC_REVA_REGS_H_
#define _ICC_REVA_REGS_H_
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_REGS_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_REGS_H_
/* **** Includes **** */
#include <stdint.h>
@ -156,4 +155,5 @@ typedef struct {
}
#endif
#endif /* _ICC_REVA_REGS_H_ */
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_REGS_H_

127
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/LP/lp_me11.c
View File

@ -3,8 +3,8 @@
* @brief Low power functions
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,14 +34,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
/***** Includes *****/
#include "lp.h"
#include "pwrseq_regs.h"
#include "mxc_errors.h"
#include "gcr_regs.h"
#include "mxc_device.h"
#include "mxc_errors.h"
@ -56,7 +53,7 @@ void MXC_LP_ClearWakeStatus(void)
MXC_PWRSEQ->lp_wakefl = 0xFFFFFFFF;
/* These flags are slow to clear, so block until they do */
while(MXC_PWRSEQ->lp_wakefl & (MXC_PWRSEQ->lpwk_en));
while (MXC_PWRSEQ->lp_wakefl & (MXC_PWRSEQ->lpwk_en)) {}
}
void MXC_LP_EnableSRAM3(void)
@ -159,24 +156,23 @@ void MXC_LP_DisableRTCAlarmWakeup(void)
MXC_GCR->pm &= ~MXC_F_GCR_PM_RTCWK_EN;
}
void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask)
void MXC_LP_EnableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins)
{
MXC_GCR->pm |= MXC_F_GCR_PM_GPIOWK_EN;
//switch(port)
//switch(wu_pins->port)
//{
/*case 0:*/ MXC_PWRSEQ->lpwk_en |= mask; //break;
/*case 0:*/ MXC_PWRSEQ->lpwk_en |= wu_pins->mask; //break;
//}
}
void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask)
void MXC_LP_DisableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins)
{
//switch(port)
//switch(wu_pins->port)
//{
/* case 0:*/ MXC_PWRSEQ->lpwk_en &= ~mask; //break;
/* case 0:*/ MXC_PWRSEQ->lpwk_en &= ~wu_pins->mask; //break;
//}
if(MXC_PWRSEQ->lpwk_en == 0)
{
if (MXC_PWRSEQ->lpwk_en == 0) {
MXC_GCR->pm &= ~MXC_F_GCR_PM_GPIOWK_EN;
}
}
@ -205,14 +201,14 @@ void MXC_LP_EnterBackupMode(void)
{
MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE;
MXC_GCR->pm |= MXC_S_GCR_PM_MODE_BACKUP;
while(1);
while (1) {}
}
void MXC_LP_EnterShutdownMode(void)
{
MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE;
MXC_GCR->pm |= MXC_S_GCR_PM_MODE_SHUTDOWN;
while(1);
while (1) {}
}
int MXC_LP_SetOperatingVoltage(mxc_lp_ovr_t ovr)
@ -235,7 +231,8 @@ int MXC_LP_SetOperatingVoltage(mxc_lp_ovr_t ovr)
}
// Set flash wait state for any clock so its not to low after clock changes.
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x5UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) |
(0x5UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
// Set the OVR bits
MXC_PWRSEQ->lp_ctrl &= ~(MXC_F_PWRSEQ_LP_CTRL_OVR);
@ -266,130 +263,160 @@ int MXC_LP_SetOperatingVoltage(mxc_lp_ovr_t ovr)
// Set Flash Wait States
if (ovr == MXC_LP_OVR_0_9) {
if (div == 0) {
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) |
(0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
} else {
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) |
(0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
}
} else if (ovr == MXC_LP_OVR_1_0) {
if (div == 0) {
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) |
(0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
} else {
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) |
(0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
}
} else {
if (div == 0) {
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x4UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) |
(0x4UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
} else if (div == 1) {
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) |
(0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
} else {
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) |
(0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
}
}
// Caller must perform peripheral reset
return E_NO_ERROR;
}
void MXC_LP_EnableSRamRet0(void){
void MXC_LP_EnableSRamRet0(void)
{
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0;
}
void MXC_LP_DisableSRamRet0(void){
void MXC_LP_DisableSRamRet0(void)
{
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0;
}
void MXC_LP_EnableSRamRet1(void){
void MXC_LP_EnableSRamRet1(void)
{
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1;
}
void MXC_LP_DisableSRamRet1(void){
void MXC_LP_DisableSRamRet1(void)
{
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1;
}
void MXC_LP_EnableSRamRet2(void){
void MXC_LP_EnableSRamRet2(void)
{
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2;
}
void MXC_LP_DisableSRamRet2(void){
void MXC_LP_DisableSRamRet2(void)
{
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2;
}
void MXC_LP_EnableSRamRet3(void){
void MXC_LP_EnableSRamRet3(void)
{
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3;
}
void MXC_LP_DisableSRamRet3(void){
void MXC_LP_DisableSRamRet3(void)
{
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3;
}
void MXC_LP_EnableBlockDetect(void){
void MXC_LP_EnableBlockDetect(void)
{
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS;
}
void MXC_LP_DisableBlockDetect(void){
void MXC_LP_DisableBlockDetect(void)
{
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS;
}
void MXC_LP_EnableRamRetReg(void){
void MXC_LP_EnableRamRetReg(void)
{
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RETREG_EN;
}
void MXC_LP_DisableRamRetReg(void){
void MXC_LP_DisableRamRetReg(void)
{
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RETREG_EN;
}
void MXC_LP_EnableFastWk(void){
void MXC_LP_EnableFastWk(void)
{
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN;
}
void MXC_LP_DisableFastWk(void){
void MXC_LP_DisableFastWk(void)
{
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN;
}
void MXC_LP_EnableBandGap(void){
void MXC_LP_EnableBandGap(void)
{
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_BG_OFF;
}
void MXC_LP_DisableBandGap(void){
void MXC_LP_DisableBandGap(void)
{
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_BG_OFF;
}
void MXC_LP_EnableVCorePORSignal(void){
void MXC_LP_EnableVCorePORSignal(void)
{
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS;
}
void MXC_LP_DisableVCorePORSignal(void){
void MXC_LP_DisableVCorePORSignal(void)
{
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS;
}
void MXC_LP_EnableLDO(void){
void MXC_LP_EnableLDO(void)
{
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_LDO_DIS;
}
void MXC_LP_DisableLDO(void){
void MXC_LP_DisableLDO(void)
{
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_LDO_DIS;
}
void MXC_LP_EnableVCoreSVM(void){
void MXC_LP_EnableVCoreSVM(void)
{
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS;
}
void MXC_LP_DisableVCoreSVM(void){
void MXC_LP_DisableVCoreSVM(void)
{
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS;
}
void MXC_LP_EnableVDDIOPorMonitoF(void){
void MXC_LP_EnableVDDIOPorMonitoF(void)
{
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS;
}
void MXC_LP_DisableVDDIOPorMonitor(void){
void MXC_LP_DisableVDDIOPorMonitor(void)
{
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS;
}

50
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_me11.c
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
#include "mxc_device.h"
#include "rtc_regs.h"
@ -78,7 +78,7 @@ int MXC_RTC_Init (uint32_t sec, uint8_t ssec)
// Enable clock
MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN;
return MXC_RTC_RevA_Init ((mxc_rtc_reva_regs_t*) MXC_RTC, sec, ssec);
return MXC_RTC_RevA_Init((mxc_rtc_reva_regs_t *)MXC_RTC, sec, (ssec & MXC_F_RTC_SSEC_RTSS));
}
int MXC_RTC_SquareWave(mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft)
@ -88,6 +88,20 @@ int MXC_RTC_SquareWave (mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft)
return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t *)MXC_RTC, sqe, ft);
}
int MXC_RTC_SquareWaveStart(mxc_rtc_freq_sel_t fq)
{
MXC_GPIO_Config(&gpio_cfg_32kcal);
return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t *)MXC_RTC, MXC_RTC_REVA_SQUARE_WAVE_ENABLED,
fq);
}
int MXC_RTC_SquareWaveStop(void)
{
return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t *)MXC_RTC,
MXC_RTC_REVA_SQUARE_WAVE_DISABLED, 0);
}
int MXC_RTC_Trim(int8_t trm)
{
return MXC_RTC_RevA_Trim((mxc_rtc_reva_regs_t *)MXC_RTC, trm);
@ -95,25 +109,43 @@ int MXC_RTC_Trim (int8_t trm)
int MXC_RTC_GetFlags(void)
{
return MXC_RTC_RevA_GetFlags();
return MXC_RTC_RevA_GetFlags((mxc_rtc_reva_regs_t *)MXC_RTC);
}
int MXC_RTC_ClearFlags(int flags)
{
return MXC_RTC_RevA_ClearFlags (flags);
return MXC_RTC_RevA_ClearFlags((mxc_rtc_reva_regs_t *)MXC_RTC, flags);
}
int MXC_RTC_GetSubSecond(void)
{
return MXC_RTC_RevA_GetSubSecond();
MXC_RTC->ctrl &= ~MXC_F_RTC_CTRL_RDY; // Ensure valid data is in SSEC register
while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {}
return MXC_RTC_RevA_GetSubSecond((mxc_rtc_reva_regs_t *)MXC_RTC);
}
int MXC_RTC_GetSecond(void)
{
return MXC_RTC_RevA_GetSecond();
MXC_RTC->ctrl &= ~MXC_F_RTC_CTRL_RDY; // Ensure valid data is in SEC register
while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {}
return MXC_RTC_RevA_GetSecond((mxc_rtc_reva_regs_t *)MXC_RTC);
}
int MXC_RTC_GetTime(uint32_t *sec, uint32_t *subsec)
{
return MXC_RTC_RevA_GetTime (sec, subsec);
return MXC_RTC_RevA_GetTime((mxc_rtc_reva_regs_t *)MXC_RTC, sec, subsec);
}
int MXC_RTC_GetBusyFlag(void)
{
return MXC_RTC_RevA_GetBusyFlag((mxc_rtc_reva_regs_t *)MXC_RTC);
}
int MXC_RTC_TrimCrystal(mxc_tmr_regs_t *tmr)
{
/* MAX32660 does not have a clock source which can
be used as the reference clock for the trim function */
return E_NOT_SUPPORTED;
}

283
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva.c
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,33 +29,34 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
#include <stdbool.h>
#include <stddef.h>
#include "mxc_device.h"
#include "rtc.h"
#include "mxc_sys.h"
#include "mxc_delay.h"
#include "gpio_regs.h"
#include "mxc_delay.h"
#include "mxc_device.h"
#include "mxc_errors.h"
#include "mxc_sys.h"
#include "rtc.h"
#include "rtc_reva.h"
#include "tmr.h"
#if TARGET_NUM == 32650
#include "pwrseq_regs.h"
#endif
int MXC_RTC_CheckBusy(void)
void MXC_RTC_Wait_BusyToClear(void)
{
// Time-out transfer if it takes > BUSY_TIMEOUT microseconds
MXC_DelayAsync(MXC_DELAY_USEC(MXC_BUSY_TIMEOUT), NULL);
while (MXC_RTC_REVA_IS_BUSY) {}
}
while (MXC_RTC_REVA_IS_BUSY) {
if (MXC_DelayCheck() != E_BUSY) {
int MXC_RTC_RevA_GetBusyFlag(mxc_rtc_reva_regs_t *rtc)
{
if (MXC_RTC_REVA_IS_BUSY) {
return E_BUSY;
}
}
MXC_DelayAbort();
return E_SUCCESS;
}
@ -68,12 +69,16 @@ int MXC_RTC_RevA_EnableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask)
return E_BAD_PARAM;
}
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
rtc->ctrl |= mask;
/* If TOD and SSEC interrupt enable, check busy after CTRL register write*/
mask &= ~MXC_RTC_INT_EN_READY;
if (mask) {
MXC_RTC_Wait_BusyToClear();
}
return E_SUCCESS;
}
@ -86,19 +91,23 @@ int MXC_RTC_RevA_DisableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask)
return E_BAD_PARAM;
}
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
rtc->ctrl &= ~mask;
/* If TOD and SSEC interrupt enable, check busy after CTRL register write*/
mask &= ~MXC_RTC_INT_EN_READY;
if (mask) {
MXC_RTC_Wait_BusyToClear();
}
return E_SUCCESS;
}
int MXC_RTC_RevA_SetTimeofdayAlarm(mxc_rtc_reva_regs_t *rtc, uint32_t ras)
{
// ras can only be written if BUSY = 0 & (RTCE = 0 or ADE = 0);
if (MXC_RTC_CheckBusy()) {
if (MXC_RTC_RevA_GetBusyFlag(rtc)) {
return E_BUSY;
}
@ -110,7 +119,7 @@ int MXC_RTC_RevA_SetTimeofdayAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t ras)
int MXC_RTC_RevA_SetSubsecondAlarm(mxc_rtc_reva_regs_t *rtc, uint32_t rssa)
{
// ras can only be written if BUSY = 0 & (RTCE = 0 or ASE = 0);
if (MXC_RTC_CheckBusy()) {
if (MXC_RTC_RevA_GetBusyFlag(rtc)) {
return E_BUSY;
}
@ -121,22 +130,18 @@ int MXC_RTC_RevA_SetSubsecondAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t rssa)
int MXC_RTC_RevA_Start(mxc_rtc_reva_regs_t *rtc)
{
if (MXC_RTC_CheckBusy()) {
if (MXC_RTC_RevA_GetBusyFlag(rtc)) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
// Can only write if WE=1 and BUSY=0
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 1
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing...
@ -145,128 +150,99 @@ int MXC_RTC_RevA_Start (mxc_rtc_reva_regs_t *rtc)
int MXC_RTC_RevA_Stop(mxc_rtc_reva_regs_t *rtc)
{
if (MXC_RTC_CheckBusy()) {
if (MXC_RTC_RevA_GetBusyFlag(rtc)) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
// Can only write if WE=1 and BUSY=0
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 0
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing...
return E_SUCCESS;
}
int MXC_RTC_RevA_Init (mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint8_t ssec)
int MXC_RTC_RevA_Init(mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint32_t ssec)
{
if (MXC_RTC_CheckBusy()) {
if (MXC_RTC_RevA_GetBusyFlag(rtc)) {
return E_BUSY;
}
rtc->ctrl = MXC_F_RTC_REVA_CTRL_WR_EN; // Allow Writes
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
rtc->ctrl = MXC_RTC_REVA_CTRL_RESET_DEFAULT; // Start with a Clean Register
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Set Write Enable, allow writing to reg.
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
rtc->ssec = ssec;
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
rtc->sec = sec;
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing...
return E_SUCCESS;
}
int MXC_RTC_RevA_SquareWave (mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft)
int MXC_RTC_RevA_SquareWave(mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe,
mxc_rtc_freq_sel_t ft)
{
if (MXC_RTC_CheckBusy()) {
if (MXC_RTC_RevA_GetBusyFlag(rtc)) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
if (sqe == MXC_RTC_REVA_SQUARE_WAVE_ENABLED) {
if (ft == MXC_RTC_F_32KHZ) { // if 32KHz output is selected...
rtc->oscctrl |= MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Enable 32KHz wave
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_SQW_EN; // Enable output on the pin
}
else { // if 1Hz, 512Hz, 4KHz output is selected
} else { // if 1Hz, 512Hz, 4KHz output is selected
rtc->oscctrl &=
~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled
rtc->oscctrl &= ~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_SQW_SEL;
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
rtc->ctrl |= (MXC_F_RTC_REVA_CTRL_SQW_EN | ft); // Enable Sq. wave,
}
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // Enable Real Time Clock
}
else { // Turn off the square wave output on the pin
} else { // Turn off the square wave output on the pin
rtc->oscctrl &=
~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled
rtc->oscctrl &= ~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_SQW_EN; // No sq. wave output
}
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Disable Writing to register
@ -275,67 +251,66 @@ int MXC_RTC_RevA_SquareWave (mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t
int MXC_RTC_RevA_Trim(mxc_rtc_reva_regs_t *rtc, int8_t trim)
{
if (MXC_RTC_CheckBusy()) {
if (MXC_RTC_RevA_GetBusyFlag(rtc)) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN;
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
MXC_SETFIELD(rtc->trim, MXC_F_RTC_REVA_TRIM_TRIM, trim << MXC_F_RTC_REVA_TRIM_TRIM_POS);
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC_Wait_BusyToClear();
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Disable Writing to register
return E_SUCCESS;
}
int MXC_RTC_RevA_GetFlags(void)
int MXC_RTC_RevA_GetFlags(mxc_rtc_reva_regs_t *rtc)
{
return MXC_RTC->ctrl & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY);
return rtc->ctrl & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY);
}
int MXC_RTC_RevA_ClearFlags(int flags)
int MXC_RTC_RevA_ClearFlags(mxc_rtc_reva_regs_t *rtc, int flags)
{
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC->ctrl &= ~(flags & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY));
rtc->ctrl &= ~(flags & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY));
return E_SUCCESS;
}
int MXC_RTC_RevA_GetSubSecond(void)
int MXC_RTC_RevA_GetSubSecond(mxc_rtc_reva_regs_t *rtc)
{
if (MXC_RTC_RevA_GetBusyFlag(rtc)) {
return E_BUSY;
}
#if TARGET_NUM == 32650
int ssec;
if (ChipRevision > 0xA1) {
ssec = ((MXC_PWRSEQ->ctrl >> 12)& 0xF00) | (MXC_RTC->ssec & 0xFF);
ssec = ((MXC_PWRSEQ->ctrl >> 12) & 0xF00) | (rtc->ssec & 0xFF);
} else {
ssec = MXC_RTC->ssec;
ssec = rtc->ssec;
}
return ssec;
#else
return MXC_RTC->ssec;
return rtc->ssec;
#endif
}
int MXC_RTC_RevA_GetSecond(void)
int MXC_RTC_RevA_GetSecond(mxc_rtc_reva_regs_t *rtc)
{
return MXC_RTC->sec;
if (MXC_RTC_RevA_GetBusyFlag(rtc)) {
return E_BUSY;
}
int MXC_RTC_RevA_GetTime(uint32_t* sec, uint32_t* subsec)
return rtc->sec;
}
int MXC_RTC_RevA_GetTime(mxc_rtc_reva_regs_t *rtc, uint32_t *sec, uint32_t *subsec)
{
uint32_t temp_sec;
uint32_t temp_sec = 0;
if (sec == NULL || subsec == NULL) {
return E_NULL_PTR;
@ -343,32 +318,106 @@ int MXC_RTC_RevA_GetTime(uint32_t* sec, uint32_t* subsec)
do {
// Check if an update is about to happen.
if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) {
if (!(rtc->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) {
return E_BUSY;
}
// Read the seconds count.
temp_sec = MXC_RTC_RevA_GetSecond();
temp_sec = MXC_RTC_RevA_GetSecond(rtc);
if (temp_sec == E_BUSY) {
return E_BUSY;
}
// Check if an update is about to happen.
if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) {
if (!(rtc->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) {
return E_BUSY;
}
// Read the sub-seconds count.
*subsec = MXC_RTC_RevA_GetSubSecond();
*subsec = MXC_RTC_RevA_GetSubSecond(rtc);
// Check if an update is about to happen.
if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) {
if (!(rtc->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) {
return E_BUSY;
}
// Read the seconds count.
*sec = MXC_RTC_RevA_GetSecond();
*sec = MXC_RTC_RevA_GetSecond(rtc);
// Repeat until a steady state is reached.
}
while (temp_sec != *sec);
} while (temp_sec != *sec);
return E_NO_ERROR;
}
int MXC_RTC_RevA_TrimCrystal(mxc_rtc_reva_regs_t *rtc, mxc_tmr_regs_t *tmr)
{
int err, ppm = 0;
uint32_t sec = 0, ssec = 0, ctrl = 0;
uint32_t sec_sample[MXC_RTC_REVA_TRIM_PERIODS + 1] = { 0 };
uint32_t ssec_sample[MXC_RTC_REVA_TRIM_PERIODS + 1] = { 0 };
bool rtc_en = true;
if (!(rtc->ctrl & MXC_F_RTC_REVA_CTRL_EN)) { // If RTC not enable, initialize it
rtc_en = false;
while ((sec = MXC_RTC_RevA_GetSecond(rtc)) < 0) {}
// Save state
while ((ssec = MXC_RTC_RevA_GetSubSecond(rtc)) < 0) {}
while (rtc->ctrl & MXC_F_RTC_CTRL_BUSY) {}
ctrl = rtc->ctrl;
if ((err = MXC_RTC_Init(0, 0)) != E_NO_ERROR) {
return err;
}
MXC_RTC_Start();
}
MXC_TMR_ClearFlags(tmr);
MXC_TMR_Start(tmr); // Sample the RTC ticks in MXC_RTC_REVA_TRIM_PERIODS number of periods
while ((sec_sample[0] = MXC_RTC_RevA_GetSecond(rtc)) < 0) {}
while ((ssec_sample[0] = MXC_RTC_RevA_GetSubSecond(rtc)) < 0) {}
for (int i = 1; i < (MXC_RTC_REVA_TRIM_PERIODS + 1); i++) {
while (!(MXC_TMR_GetFlags(tmr) & MXC_RTC_TRIM_TMR_IRQ)) {}
// Wait for time trim period to elapse
while ((sec_sample[i] = MXC_RTC_RevA_GetSecond(rtc)) < 0) {}
// Take time sample
while ((ssec_sample[i] = MXC_RTC_RevA_GetSubSecond(rtc)) < 0) {}
MXC_TMR_ClearFlags(tmr);
}
MXC_TMR_Stop(tmr); // Shutdown timer
MXC_TMR_Shutdown(tmr);
if (!rtc_en) { // If RTC wasn't enabled entering the function, restore state
MXC_RTC_Stop();
while (rtc->ctrl & MXC_F_RTC_REVA_CTRL_BUSY) {}
MXC_SETFIELD(rtc->ssec, MXC_F_RTC_REVA_SSEC_SSEC, (ssec << MXC_F_RTC_REVA_SSEC_SSEC_POS));
while (rtc->ctrl & MXC_F_RTC_REVA_CTRL_BUSY) {}
MXC_SETFIELD(rtc->sec, MXC_F_RTC_REVA_SEC_SEC, (sec << MXC_F_RTC_REVA_SEC_SEC_POS));
while (rtc->ctrl & MXC_F_RTC_REVA_CTRL_BUSY) {}
rtc->ctrl = ctrl;
}
for (int i = 0; i < MXC_RTC_REVA_TRIM_PERIODS;
i++) { // Get total error in RTC ticks over MXC_RTC_REVA_TRIM_PERIODS number of sample periods
if (sec_sample[i] < sec_sample[i + 1]) {
ppm += MXC_RTC_REVA_TICKS_PER_PERIOD -
((MXC_RTC_MAX_SSEC - ssec_sample[i]) + ssec_sample[i + 1]);
} else {
ppm += MXC_RTC_REVA_TICKS_PER_PERIOD - (ssec_sample[i + 1] - ssec_sample[i]);
}
}
ppm /= MXC_RTC_REVA_TRIM_PERIODS;
ppm = PPM(ppm); // Convert total error to PPM and set trim
if (ppm < -128 || ppm > 127) {
return E_OVERFLOW;
}
return MXC_RTC_RevA_Trim(rtc, (int8_t)ppm); // Set Trim
}

45
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva.h
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,15 +29,19 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_RTC_RTC_REVA_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_RTC_RTC_REVA_H_
#include "gpio.h"
#include "mxc_delay.h"
#include "mxc_device.h"
#include "mxc_errors.h"
#include "mxc_sys.h"
#include "rtc_reva_regs.h"
#include "rtc.h"
#include "mxc_sys.h"
#include "mxc_delay.h"
#include "gpio.h"
#include "mxc_errors.h"
#include "tmr.h"
typedef enum {
MXC_RTC_REVA_SQUARE_WAVE_DISABLED, ///< Sq. wave output disabled
@ -45,22 +49,31 @@ typedef enum {
} mxc_rtc_reva_sqwave_en_t;
#define MXC_RTC_REVA_CTRL_RESET_DEFAULT (0x0000UL)
#define MXC_RTC_REVA_IS_BUSY (MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_BUSY)
#define MXC_RTC_REVA_IS_ENABLED (MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RTCE)
#define MXC_RTC_REVA_IS_BUSY (MXC_F_RTC_REVA_CTRL_BUSY & MXC_RTC->ctrl)
#define MXC_RTC_REVA_IS_ENABLED (MXC_F_RTC_REVA_CTRL_RTCE & MXC_RTC->ctrl)
#define MXC_RTC_REVA_TRIM_PERIODS 5
#define MXC_RTC_REVA_TICKS_PER_PERIOD (MXC_RTC_MAX_SSEC / MXC_RTC_REVA_TRIM_PERIODS)
#define PPM(ppm) ((ppm * 1000000) / 4096)
#define MXC_BUSY_TIMEOUT 1000 // Timeout counts for the Busy bit
int MXC_RTC_RevA_Init (mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint8_t ssec);
int MXC_RTC_RevA_Init(mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint32_t ssec);
int MXC_RTC_RevA_EnableInt(mxc_rtc_reva_regs_t *rtc, uint32_t mask);
int MXC_RTC_RevA_DisableInt(mxc_rtc_reva_regs_t *rtc, uint32_t mask);
int MXC_RTC_RevA_SetTimeofdayAlarm(mxc_rtc_reva_regs_t *rtc, uint32_t ras);
int MXC_RTC_RevA_SetSubsecondAlarm(mxc_rtc_reva_regs_t *rtc, uint32_t rssa);
int MXC_RTC_RevA_Start(mxc_rtc_reva_regs_t *rtc);
int MXC_RTC_RevA_Stop(mxc_rtc_reva_regs_t *rtc);
int MXC_RTC_RevA_SquareWave (mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft);
int MXC_RTC_RevA_SquareWave(mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe,
mxc_rtc_freq_sel_t ft);
int MXC_RTC_RevA_Trim(mxc_rtc_reva_regs_t *rtc, int8_t trm);
int MXC_RTC_RevA_GetFlags (void);
int MXC_RTC_RevA_ClearFlags (int flags);
int MXC_RTC_RevA_GetSubSecond (void);
int MXC_RTC_RevA_GetSecond (void);
int MXC_RTC_RevA_GetTime (uint32_t* sec, uint32_t* subsec);
int MXC_RTC_RevA_GetFlags(mxc_rtc_reva_regs_t *rtc);
int MXC_RTC_RevA_ClearFlags(mxc_rtc_reva_regs_t *rtc, int flags);
int MXC_RTC_RevA_GetSubSecond(mxc_rtc_reva_regs_t *rtc);
int MXC_RTC_RevA_GetSecond(mxc_rtc_reva_regs_t *rtc);
int MXC_RTC_RevA_GetTime(mxc_rtc_reva_regs_t *rtc, uint32_t *sec, uint32_t *subsec);
int MXC_RTC_RevA_GetBusyFlag(mxc_rtc_reva_regs_t *rtc);
int MXC_RTC_RevA_TrimCrystal(mxc_rtc_reva_regs_t *rtc, mxc_tmr_regs_t *tmr);
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_RTC_RTC_REVA_H_

7
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva_regs.h
View File

@ -3,8 +3,8 @@
* @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _RTC_REVA_REGS_H_
#define _RTC_REVA_REGS_H_

50
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_me11.c
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#include <stdio.h>
#include <stddef.h>
@ -44,8 +44,12 @@
/* **** Functions **** */
int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves,
unsigned ssPolarity, unsigned int hz, unsigned drv_ssel)
unsigned ssPolarity, unsigned int hz)
{
int spi_num;
spi_num = MXC_SPI_GET_IDX(spi);
MXC_ASSERT(spi_num >= 0);
if (numSlaves > MXC_SPI_SS_INSTANCES) {
return E_BAD_PARAM;
@ -59,26 +63,30 @@ int MXC_SPI_Init(mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numS
// Configure GPIO for spi
if (spi == MXC_SPI0) {
MXC_GCR->rst0 |= MXC_F_GCR_RST0_SPI0;
while(MXC_GCR->rst0 & MXC_F_GCR_RST0_SPI0);
while (MXC_GCR->rst0 & MXC_F_GCR_RST0_SPI0) {}
MXC_GCR->pclk_dis0 &= ~(MXC_F_GCR_PCLK_DIS0_SPI0D);
MXC_GPIO_Config(&gpio_cfg_spi0);
}
else {
} else {
return E_NO_DEVICE;
}
return MXC_SPI_RevA_Init((mxc_spi_reva_regs_t*) spi, masterMode, quadModeUsed, numSlaves, ssPolarity, hz, drv_ssel);
return MXC_SPI_RevA_Init((mxc_spi_reva_regs_t *)spi, masterMode, quadModeUsed, numSlaves,
ssPolarity, hz);
}
int MXC_SPI_Shutdown(mxc_spi_regs_t *spi)
{
if(spi != MXC_SPI0) {
return E_NO_DEVICE;
}
int spi_num;
spi_num = MXC_SPI_GET_IDX(spi);
MXC_ASSERT(spi_num >= 0);
MXC_SPI_RevA_Shutdown((mxc_spi_reva_regs_t *)spi);
//
if (spi == MXC_SPI0) {
MXC_GCR->pclk_dis0 |= (MXC_F_GCR_PCLK_DIS0_SPI0D);
} else {
return E_INVALID;
}
return E_NO_ERROR;
}
@ -92,8 +100,7 @@ int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi)
{
if (spi == MXC_SPI0) {
return PeripheralClock;
}
else {
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
@ -131,7 +138,7 @@ int MXC_SPI_GetSlave(mxc_spi_regs_t* spi)
int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth)
{
return MXC_SPI_RevA_SetWidth((mxc_spi_reva_regs_t*) spi, (mxc_spi_reva_width_t)spiWidth);
return MXC_SPI_RevA_SetWidth((mxc_spi_reva_regs_t *)spi, spiWidth);
}
mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi)
@ -141,12 +148,12 @@ mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t* spi)
int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode)
{
return MXC_SPI_RevA_SetMode ((mxc_spi_reva_regs_t*) spi, (mxc_spi_reva_mode_t)spiMode);
return MXC_SPI_RevA_SetMode((mxc_spi_reva_regs_t *)spi, spiMode);
}
mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi)
{
return (mxc_spi_mode_t) MXC_SPI_RevA_GetMode((mxc_spi_reva_regs_t*) spi);
return MXC_SPI_RevA_GetMode((mxc_spi_reva_regs_t *)spi);
}
int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi)
@ -164,8 +171,7 @@ int MXC_SPI_AbortTransmission(mxc_spi_regs_t* spi)
return MXC_SPI_RevA_AbortTransmission((mxc_spi_reva_regs_t *)spi);
}
unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t* spi, unsigned char* bytes,
unsigned int len)
unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len)
{
return MXC_SPI_RevA_ReadRXFIFO((mxc_spi_reva_regs_t *)spi, bytes, len);
}
@ -175,8 +181,7 @@ unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t* spi)
return MXC_SPI_RevA_GetRXFIFOAvailable((mxc_spi_reva_regs_t *)spi);
}
unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t* spi, unsigned char* bytes,
unsigned int len)
unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len)
{
return MXC_SPI_RevA_WriteTXFIFO((mxc_spi_reva_regs_t *)spi, bytes, len);
}
@ -286,7 +291,8 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t* req)
}
}
return MXC_SPI_RevA_MasterTransactionDMA((mxc_spi_reva_req_t*) req, reqselTx, reqselRx, MXC_DMA);
return MXC_SPI_RevA_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx,
MXC_DMA);
}
int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req)

531
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c
View File

File diff suppressed because it is too large Load Diff

31
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.h
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_SPI_SPI_REVA_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_SPI_SPI_REVA_H_
#include <stdio.h>
#include <stddef.h>
@ -41,9 +44,13 @@
#include "mxc_delay.h"
#include "spi_regs.h"
#include "spi_reva_regs.h"
#include "mxc_spi.h"
#include "spi.h"
#include "dma.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SPI_REVA_WIDTH_3WIRE,
SPI_REVA_WIDTH_STANDARD,
@ -74,13 +81,15 @@ struct _mxc_spi_reva_req_t {
};
int MXC_SPI_RevA_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves,
unsigned ssPolarity, unsigned int hz, unsigned drv_ssel);
unsigned ssPolarity, unsigned int hz);
int MXC_SPI_RevA_Shutdown(mxc_spi_reva_regs_t *spi);
int MXC_SPI_RevA_ReadyForSleep(mxc_spi_reva_regs_t *spi);
int MXC_SPI_RevA_SetFrequency(mxc_spi_reva_regs_t *spi, unsigned int hz);
unsigned int MXC_SPI_RevA_GetFrequency(mxc_spi_reva_regs_t *spi);
int MXC_SPI_RevA_SetDataSize(mxc_spi_reva_regs_t *spi, int dataSize);
int MXC_SPI_RevA_GetDataSize(mxc_spi_reva_regs_t *spi);
int MXC_SPI_RevA_SetMTMode(mxc_spi_reva_regs_t *spi, int mtMode);
int MXC_SPI_RevA_GetMTMode(mxc_spi_reva_regs_t *spi);
int MXC_SPI_RevA_SetSlave(mxc_spi_reva_regs_t *spi, int ssIdx);
int MXC_SPI_RevA_GetSlave(mxc_spi_reva_regs_t *spi);
int MXC_SPI_RevA_SetWidth(mxc_spi_reva_regs_t *spi, mxc_spi_reva_width_t spiWidth);
@ -108,11 +117,19 @@ void MXC_SPI_RevA_EnableInt (mxc_spi_reva_regs_t* spi, unsigned int mask);
void MXC_SPI_RevA_DisableInt(mxc_spi_reva_regs_t *spi, unsigned int mask);
int MXC_SPI_RevA_MasterTransaction(mxc_spi_reva_req_t *req);
int MXC_SPI_RevA_MasterTransactionAsync(mxc_spi_reva_req_t *req);
int MXC_SPI_RevA_MasterTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma);
int MXC_SPI_RevA_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int reqselRx,
mxc_dma_regs_t *dma);
int MXC_SPI_RevA_SlaveTransaction(mxc_spi_reva_req_t *req);
int MXC_SPI_RevA_SlaveTransactionAsync(mxc_spi_reva_req_t *req);
int MXC_SPI_RevA_SlaveTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma);
int MXC_SPI_RevA_SlaveTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int reqselRx,
mxc_dma_regs_t *dma);
void MXC_SPI_RevA_DMACallback(int ch, int error);
int MXC_SPI_RevA_SetDefaultTXData(mxc_spi_reva_regs_t *spi, unsigned int defaultTXData);
void MXC_SPI_RevA_AbortAsync(mxc_spi_reva_regs_t *spi);
void MXC_SPI_RevA_AsyncHandler(mxc_spi_reva_regs_t *spi);
#ifdef __cplusplus
}
#endif
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_SPI_SPI_REVA_H_

7
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva_regs.h
View File

@ -3,8 +3,8 @@
* @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _SPI_REVA_REGS_H_
#define _SPI_REVA_REGS_H_

13
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_me11.c
View File

@ -3,8 +3,8 @@
* @brief Inter-Integrated Sound (I2S) driver implementation.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#include <stddef.h>
#include <stdint.h>
@ -59,11 +58,9 @@ int MXC_I2S_Init(const mxc_i2s_config_t *config, void(*dma_ctz_cb)(int, int))
{
if (config->map == I2S_MAP_A) {
MXC_GPIO_Config(&gpio_cfg_spi1a); // SPIMSS: I2S and SPI share pins
}
else if(config->map == I2S_MAP_B) {
} else if (config->map == I2S_MAP_B) {
MXC_GPIO_Config(&gpio_cfg_spi1b);
}
else {
} else {
return E_BAD_PARAM;
}

190
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_reva.c
View File

@ -3,8 +3,8 @@
* @brief Inter-Integrated Sound(I2S) driver implementation.
*/
/* ****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#include <stddef.h>
#include <stdint.h>
@ -53,9 +52,11 @@
#define I2S_CHANNELS 2
#define I2S_WIDTH 16
static int dma_channel = -1;
static int tx_dma_channel = -1;
static int rx_dma_channel = -1;
int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *config, void(*dma_ctz_cb)(int, int))
int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *config,
void (*dma_ctz_cb)(int, int))
{
unsigned int baud;
uint16_t clkdiv;
@ -67,8 +68,12 @@ int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *co
/* Setup SPI_MSS as master, mode 0, 16 bit transfers as I2S Requires */
spimss->ctrl = MXC_F_SPIMSS_REVA_CTRL_MMEN;
spimss->mode = MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS16 | MXC_F_SPIMSS_REVA_MODE_SS_IO;
spimss->dma = MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES8;
spimss->mode = MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS16 | MXC_F_SPIMSS_REVA_MODE_SS_IO;
spimss->dma = (1 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) | /* TX DMA request FIFO level */
MXC_F_SPIMSS_DMA_TX_FIFO_CLR | /* Clear TX FIFO */
(1 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) | /* RX DMA request FIFO level */
MXC_F_SPIMSS_DMA_RX_FIFO_CLR; /* Clear RX FIFO */
/* Setup I2S register from i2s_cfg_t */
spimss->i2s_ctrl = config->justify << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS |
@ -109,36 +114,40 @@ int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *co
return err;
}
dma_channel = err;
tx_dma_channel = err;
dma_config.ch = dma_channel;
dma_config.ch = tx_dma_channel;
dma_config.srcwd = MXC_DMA_WIDTH_HALFWORD;
dma_config.dstwd = MXC_DMA_WIDTH_WORD;
dma_config.srcwd = MXC_DMA_WIDTH_WORD;
dma_config.dstwd = MXC_DMA_WIDTH_HALFWORD;
#if TARGET_NUM == 32650
dma_config.reqsel = MXC_DMA_REQUEST_SPIMSSTX;
#endif
#if TARGET_NUM == 32660
dma_config.reqsel = MXC_DMA_REQUEST_SPI1TX;
#endif
dma_config.srcinc_en = 1;
dma_config.dstinc_en = 0;
srcdst.ch = dma_channel;
srcdst.ch = tx_dma_channel;
srcdst.source = config->src_addr;
srcdst.dest = NULL;
srcdst.len = config->length;
MXC_DMA_ConfigChannel(dma_config, srcdst);
MXC_DMA_SetChannelInterruptEn(dma_channel, 0, 1);
MXC_DMA_SetChannelInterruptEn(tx_dma_channel, 0, 1);
MXC_DMA->ch[dma_channel].cfg &= ~MXC_F_DMA_CFG_BRST;
MXC_DMA->ch[dma_channel].cfg |= (0x1f << MXC_F_DMA_CFG_BRST_POS);
MXC_DMA->ch[tx_dma_channel].cfg &= ~MXC_F_DMA_CFG_BRST;
MXC_DMA->ch[tx_dma_channel].cfg |= (3 << MXC_F_DMA_CFG_BRST_POS);
if (ctz_en) {
MXC_DMA_SetCallback(dma_channel, dma_ctz_cb);
MXC_DMA_EnableInt(dma_channel);
MXC_DMA_SetCallback(tx_dma_channel, dma_ctz_cb);
MXC_DMA_EnableInt(tx_dma_channel);
}
}
if (config->audio_direction / 2) {
spimss->dma = MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN | MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR;
spimss->dma |= MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN | MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR;
if ((err = MXC_DMA_Init()) != E_NO_ERROR) {
if (err != E_BAD_STATE) { //DMA already initialized
return err;
@ -149,32 +158,36 @@ int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *co
return err;
}
dma_channel = err;
rx_dma_channel = err;
dma_config.ch = dma_channel;
dma_config.ch = rx_dma_channel;
dma_config.srcwd = MXC_DMA_WIDTH_WORD;
dma_config.dstwd = MXC_DMA_WIDTH_HALFWORD;
dma_config.srcwd = MXC_DMA_WIDTH_HALFWORD;
dma_config.dstwd = MXC_DMA_WIDTH_WORD;
#if TARGET_NUM == 32650
dma_config.reqsel = MXC_DMA_REQUEST_SPIMSSRX;
#endif
#if TARGET_NUM == 32660
dma_config.reqsel = MXC_DMA_REQUEST_SPI1RX;
#endif
dma_config.srcinc_en = 0;
dma_config.dstinc_en = 1;
srcdst.ch = dma_channel;
srcdst.ch = rx_dma_channel;
srcdst.source = NULL;
srcdst.dest = config->dst_addr;
srcdst.len = config->length;
MXC_DMA_ConfigChannel(dma_config, srcdst);
MXC_DMA_SetChannelInterruptEn(dma_channel, 0, 1);
MXC_DMA_SetChannelInterruptEn(rx_dma_channel, 0, 1);
MXC_DMA->ch[dma_channel].cfg &= ~MXC_F_DMA_CFG_BRST;
MXC_DMA->ch[dma_channel].cfg |= (0x1f << MXC_F_DMA_CFG_BRST_POS);
MXC_DMA->ch[rx_dma_channel].cfg &= ~MXC_F_DMA_CFG_BRST;
MXC_DMA->ch[rx_dma_channel].cfg |= (3 << MXC_F_DMA_CFG_BRST_POS);
if (ctz_en) {
MXC_DMA_SetCallback(dma_channel, dma_ctz_cb);
MXC_DMA_EnableInt(dma_channel);
MXC_DMA_SetCallback(rx_dma_channel, dma_ctz_cb);
MXC_DMA_EnableInt(rx_dma_channel);
}
}
@ -191,12 +204,28 @@ int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *co
int MXC_I2S_RevA_Shutdown(mxc_spimss_reva_regs_t *spimss)
{
int retTx = E_NO_ERROR;
int retRx = E_NO_ERROR;
spimss->ctrl = 0;
spimss->i2s_ctrl = 0;
spimss->brg = 0;
spimss->mode = 0;
spimss->dma = 0;
return MXC_DMA_ReleaseChannel(dma_channel);
if (tx_dma_channel != -1) {
retTx = MXC_DMA_ReleaseChannel(tx_dma_channel);
}
if (rx_dma_channel != -1) {
retRx = MXC_DMA_ReleaseChannel(rx_dma_channel);
}
if (retTx != E_NO_ERROR) {
return retTx;
} else {
return retRx;
}
}
int MXC_I2S_RevA_Mute(mxc_spimss_reva_regs_t *spimss)
@ -225,40 +254,125 @@ int MXC_I2S_RevA_Unpause(mxc_spimss_reva_regs_t *spimss)
int MXC_I2S_RevA_Stop(mxc_spimss_reva_regs_t *spimss)
{
int retTx = E_NO_ERROR;
int retRx = E_NO_ERROR;
spimss->ctrl &= ~MXC_F_SPIMSS_REVA_CTRL_ENABLE;
spimss->i2s_ctrl &= ~MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN;
return MXC_DMA_Stop(dma_channel);
if (tx_dma_channel != -1) {
retTx = MXC_DMA_Stop(tx_dma_channel);
}
if (rx_dma_channel != -1) {
retRx = MXC_DMA_Stop(rx_dma_channel);
}
if (retTx != E_NO_ERROR) {
return retTx;
} else {
return retRx;
}
}
int MXC_I2S_RevA_Start(mxc_spimss_reva_regs_t *spimss)
{
int retTx = E_NO_ERROR;
int retRx = E_NO_ERROR;
spimss->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE;
spimss->i2s_ctrl |= MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN;
return MXC_DMA_Start(dma_channel);
if (tx_dma_channel != -1) {
retTx = MXC_DMA_Start(tx_dma_channel);
}
if (rx_dma_channel != -1) {
retRx = MXC_DMA_Start(rx_dma_channel);
}
if (retTx != E_NO_ERROR) {
return retTx;
} else {
return retRx;
}
}
int MXC_I2S_RevA_DMA_ClearFlags(void)
{
int flags = MXC_DMA_ChannelGetFlags(dma_channel);
return MXC_DMA_ChannelClearFlags(dma_channel, flags);
int retTx = E_NO_ERROR;
int retRx = E_NO_ERROR;
int flags;
if (tx_dma_channel != -1) {
flags = MXC_DMA_ChannelGetFlags(tx_dma_channel);
retTx = MXC_DMA_ChannelClearFlags(tx_dma_channel, flags);
}
if (rx_dma_channel != -1) {
flags = MXC_DMA_ChannelGetFlags(rx_dma_channel);
retRx = MXC_DMA_ChannelClearFlags(rx_dma_channel, flags);
}
if (retTx != E_NO_ERROR) {
return retTx;
} else {
return retRx;
}
}
int MXC_I2S_RevA_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count)
{
int retTx = E_NO_ERROR;
int retRx = E_NO_ERROR;
mxc_dma_srcdst_t srcdst;
srcdst.ch = dma_channel;
if (tx_dma_channel != -1) {
srcdst.ch = tx_dma_channel;
srcdst.source = src_addr;
srcdst.dest = dst_addr;
srcdst.len = count;
return MXC_DMA_SetSrcDst(srcdst);
retTx = MXC_DMA_SetSrcDst(srcdst);
}
if (rx_dma_channel != -1) {
srcdst.ch = rx_dma_channel;
srcdst.source = src_addr;
srcdst.dest = dst_addr;
srcdst.len = count;
retRx = MXC_DMA_SetSrcDst(srcdst);
}
if (retTx != E_NO_ERROR) {
return retTx;
} else {
return retRx;
}
}
int MXC_I2S_RevA_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count)
{
int retTx = E_NO_ERROR;
int retRx = E_NO_ERROR;
mxc_dma_srcdst_t srcdst;
srcdst.ch = dma_channel;
if (tx_dma_channel != -1) {
srcdst.ch = tx_dma_channel;
srcdst.source = src_addr;
srcdst.dest = dst_addr;
srcdst.len = count;
return MXC_DMA_SetSrcReload(srcdst);
retTx = MXC_DMA_SetSrcReload(srcdst);
}
if (rx_dma_channel != -1) {
srcdst.ch = rx_dma_channel;
srcdst.source = src_addr;
srcdst.dest = dst_addr;
srcdst.len = count;
retRx = MXC_DMA_SetSrcReload(srcdst);
}
if (retTx != E_NO_ERROR) {
return retTx;
} else {
return retRx;
}
}

16
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_reva.h
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_I2S_REVA_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_I2S_REVA_H_
#include <stdio.h>
#include <stddef.h>
@ -37,9 +40,8 @@
#include "i2s.h"
#include "spimss_reva_regs.h"
int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *req, void (*dma_ctz_cb)(int, int));
int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *req,
void (*dma_ctz_cb)(int, int));
int MXC_I2S_RevA_Shutdown(mxc_spimss_reva_regs_t *spimss);
int MXC_I2S_RevA_Mute(mxc_spimss_reva_regs_t *spimss);
int MXC_I2S_RevA_Unmute(mxc_spimss_reva_regs_t *spimss);
@ -50,3 +52,5 @@ int MXC_I2S_RevA_Start(mxc_spimss_reva_regs_t *spimss);
int MXC_I2S_RevA_DMA_ClearFlags(void);
int MXC_I2S_RevA_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count);
int MXC_I2S_RevA_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count);
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_I2S_REVA_H_

40
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_me11.c
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#include <stdio.h>
#include <stddef.h>
@ -45,8 +45,14 @@
/* **** Functions **** */
/* ************************************************************************** */
int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg, unsigned drv_ssel)
int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg)
{
int spi_num;
spi_num = MXC_SPIMSS_GET_IDX(spi);
MXC_ASSERT(spi_num >= 0);
if (mode > 3) {
return E_BAD_PARAM;
}
@ -59,7 +65,7 @@ int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const
// Configure GPIO for spimss
if (spi == MXC_SPIMSS) {
MXC_GCR->rst0 |= MXC_F_GCR_RST0_SPI1;
while (MXC_GCR->rst0 & MXC_F_GCR_RST0_SPI1);
while (MXC_GCR->rst0 & MXC_F_GCR_RST0_SPI1) {}
MXC_GCR->pclk_dis0 &= ~(MXC_F_GCR_PCLK_DIS0_SPI1D);
if (sys_cfg == MAP_A) {
MXC_GPIO_Config(&gpio_cfg_spi1a); // SPI1A chosen
@ -72,19 +78,20 @@ int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const
return E_NO_DEVICE;
}
return MXC_SPIMSS_RevA_Init((mxc_spimss_reva_regs_t*) spi, mode, freq, drv_ssel);
return MXC_SPIMSS_RevA_Init((mxc_spimss_reva_regs_t *)spi, mode, freq);
}
/* ************************************************************************* */
int MXC_SPIMSS_Shutdown(mxc_spimss_regs_t *spi)
{
if(spi != MXC_SPIMSS) {
return E_NO_DEVICE;
}
int spi_num;
spi_num = MXC_SPIMSS_GET_IDX(spi);
MXC_ASSERT(spi_num >= 0);
MXC_SPIMSS_RevA_Shutdown((mxc_spimss_reva_regs_t *)spi);
//
MXC_GCR->pclk_dis0 |= (MXC_F_GCR_PCLK_DIS0_SPI1D);
if (spi == MXC_SPIMSS) {
MXC_GCR->pclk_dis0 |= (MXC_F_GCR_PCLK_DIS0_SPI1D);
}
return E_NO_ERROR;
}
/* ************************************************************************** */
@ -99,7 +106,6 @@ int MXC_SPIMSS_MasterTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req)
return MXC_SPIMSS_RevA_MasterTrans((mxc_spimss_reva_regs_t *)spi, (spimss_reva_req_t *)req);
}
/* ************************************************************************** */
int MXC_SPIMSS_SlaveTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req)
{
@ -109,7 +115,8 @@ int MXC_SPIMSS_SlaveTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req)
/* ************************************************************************** */
int MXC_SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req)
{
return MXC_SPIMSS_RevA_MasterTransAsync((mxc_spimss_reva_regs_t*) spi, (spimss_reva_req_t*) req);
return MXC_SPIMSS_RevA_MasterTransAsync((mxc_spimss_reva_regs_t *)spi,
(spimss_reva_req_t *)req);
}
/* ************************************************************************** */
@ -117,13 +124,6 @@ int MXC_SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req)
{
return MXC_SPIMSS_RevA_SlaveTransAsync((mxc_spimss_reva_regs_t *)spi, (spimss_reva_req_t *)req);
}
/* ************************************************************************* */
int MXC_SPIMSS_SetDefaultTXData(mxc_spimss_req_t* spi, unsigned int defaultTXData)
{
return MXC_SPIMSS_RevA_SetDefaultTXData((spimss_reva_req_t*) spi, defaultTXData);
}
/* ************************************************************************* */
int MXC_SPIMSS_AbortAsync(mxc_spimss_req_t *req)
{

204
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.c
View File

@ -5,7 +5,7 @@
*/
/******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -35,8 +35,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
**************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include <string.h>
@ -55,26 +54,24 @@
/* **** Definitions **** */
/* **** Globals **** */
typedef struct {
spimss_reva_req_t *req;
unsigned defaultTXData;
unsigned drv_ssel;
} spimss_reva_req_state_t;
static spimss_reva_req_state_t states[MXC_SPIMSS_INSTANCES];
/* **** Functions **** */
static int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req, int master);
static uint32_t MXC_SPIMSS_RevA_MasterTransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
static int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req,
int master);
static uint32_t MXC_SPIMSS_RevA_MasterTransHandler(mxc_spimss_reva_regs_t *spi,
spimss_reva_req_t *req);
static uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
static uint32_t MXC_SPIMSS_RevA_SlaveTransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
static uint32_t MXC_SPIMSS_RevA_SlaveTransHandler(mxc_spimss_reva_regs_t *spi,
spimss_reva_req_t *req);
/* ************************************************************************** */
int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq, unsigned drv_ssel)
int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq)
{
int spi_num;
unsigned int spimss_clk;
@ -82,8 +79,6 @@ int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned fr
spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t *)spi);
states[spi_num].req = NULL;
states[spi_num].defaultTXData = 0;
states[spi_num].drv_ssel = drv_ssel;
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Keep the SPI Disabled (This is the SPI Start)
// Set the bit rate
@ -94,9 +89,11 @@ int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned fr
pol = mode >> 1; // Get the polarity out of the mode input value
pha = mode & 1; // Get the phase out of the mode input value
spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_REVA_CTRL_CLKPOL)) | (pol << MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS); // polarity
spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_REVA_CTRL_CLKPOL)) |
(pol << MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS); // polarity
spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_REVA_CTRL_PHASE)) | (pha << MXC_F_SPIMSS_REVA_CTRL_PHASE_POS); // phase
spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_REVA_CTRL_PHASE)) |
(pha << MXC_F_SPIMSS_REVA_CTRL_PHASE_POS); // phase
spi->int_fl &= ~(MXC_F_SPIMSS_REVA_INT_FL_IRQ);
@ -119,7 +116,6 @@ int MXC_SPIMSS_RevA_Shutdown(mxc_spimss_reva_regs_t *spi)
// Call all of the pending callbacks for this SPI
spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t *)spi);
if (states[spi_num].req != NULL) {
// Save the request
temp_req = states[spi_num].req;
@ -168,38 +164,29 @@ int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *r
if (master) { // Enable master mode
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_MMEN; // SPI configured as master.
if (states[spi_num].drv_ssel) {
spi->mode |= MXC_F_SPIMSS_REVA_MODE_SS_IO; // SSEL pin is an output.
}
spi->mode |= MXC_F_SPIMSS_REVA_CTRL_MMEN; // SSEL pin is an output.
} else { // Enable slave mode
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_MMEN); // SPI configured as slave.
spi->mode &= ~(MXC_F_SPIMSS_REVA_MODE_SS_IO); // SSEL pin is an input.
spi->mode &= ~(MXC_F_SPIMSS_REVA_CTRL_MMEN); // SSEL pin is an input.
}
// Setup the character size
if (req->bits < 16) {
MXC_SETFIELD(spi->mode, MXC_F_SPIMSS_REVA_MODE_NUMBITS , req->bits << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS);
MXC_SETFIELD(spi->mode, MXC_F_SPIMSS_REVA_MODE_NUMBITS,
req->bits << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS);
} else {
MXC_SETFIELD(spi->mode, MXC_F_SPIMSS_REVA_MODE_NUMBITS , 0 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS);
MXC_SETFIELD(spi->mode, MXC_F_SPIMSS_REVA_MODE_NUMBITS,
0 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS);
}
if (req->tx_data == NULL) {
// Must have something to send, so we'll use the rx_data buffer initialized to 0.
memset(req->rx_data, states[spi_num].defaultTXData, (req->bits > 8 ? req->len << 1 : req->len));
req->tx_data = req->rx_data;
}
// Clear the TX and RX FIFO
spi->dma |= (MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR | MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR);
if (states[spi_num].drv_ssel) {
// Setup the slave select
spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV; // Assert a high on Slave Select,
// to get the line ready for active low later
}
// Clear the TX and RX FIFO
spi->dma |= (MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR | MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR);
return E_NO_ERROR;
}
@ -229,7 +216,6 @@ void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi) // From the IRQ
if (int_enable == 1) {
spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE);
}
}
@ -237,7 +223,6 @@ void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi) // From the IRQ
int MXC_SPIMSS_RevA_MasterTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req)
{
int error;
int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 1)) != E_NO_ERROR) {
return error;
@ -245,24 +230,19 @@ int MXC_SPIMSS_RevA_MasterTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *
req->callback = NULL;
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI
if (states[spi_num].drv_ssel) {
spi->mode &= ~(MXC_F_SPIMSS_REVA_MODE_SSV); // This will assert the Slave Select.
}
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI
while (MXC_SPIMSS_RevA_MasterTransHandler(spi,req)!=0) {
;
}
while (MXC_SPIMSS_RevA_MasterTransHandler(spi, req) != 0) {}
if (states[spi_num].drv_ssel) {
spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV;
}
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted...
spi->ctrl &=
~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted...
// stop the transmission...
return E_NO_ERROR;
}
/* ************************************************************************** */
int MXC_SPIMSS_RevA_SlaveTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req)
{
@ -277,7 +257,8 @@ int MXC_SPIMSS_RevA_SlaveTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *r
while ((spi->int_fl & MXC_F_SPIMSS_REVA_INT_FL_TXST) == MXC_F_SPIMSS_REVA_INT_FL_TXST) {}
}
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted...
spi->ctrl &=
~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted...
// stop the transmission...
return E_NO_ERROR;
}
@ -287,7 +268,9 @@ int MXC_SPIMSS_RevA_MasterTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_re
{
int error;
uint8_t int_enable;
int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
// Clear state for next transaction
MXC_SPIMSS_AbortAsync((mxc_spimss_req_t *)req);
if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 1)) != E_NO_ERROR) {
return error;
@ -295,10 +278,9 @@ int MXC_SPIMSS_RevA_MasterTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_re
int_enable = MXC_SPIMSS_RevA_MasterTransHandler(spi, req);
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI
if (states[spi_num].drv_ssel) {
spi->mode ^= MXC_F_SPIMSS_REVA_MODE_SSV; // This will assert the Slave Select.
}
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI
if (int_enable == 1) {
spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR);
@ -356,18 +338,67 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r
uint32_t length = req->len;
spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t *)spi);
if (spi_num < 0) {
MXC_ASSERT(0);
// Read the RX FIFO
if (req->rx_data != NULL) {
// Wait for there to be data in the RX FIFO
rx_avail = ((spi->dma & MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) >>
MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS);
if ((length - req->rx_num) < rx_avail) {
rx_avail = (length - req->rx_num);
}
// Read from the FIFO
while (rx_avail) {
// Don't read less than 2 bytes if we are using greater than 8 bit characters
if (req->bits > 8) {
((uint16_t *)req->rx_data)[req->rx_num++] = spi->data;
rx_avail -= 1;
} else {
((uint8_t *)req->rx_data)[req->rx_num++] = spi->data;
rx_avail -= 1;
}
rx_avail = ((spi->dma & MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) >>
MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS);
if ((length - req->rx_num) < rx_avail) {
rx_avail = (length - req->rx_num);
}
}
remain = length - req->rx_num;
if (remain) {
if (remain > MXC_SPIMSS_FIFO_DEPTH) {
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) |
((2) << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS));
} else {
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) |
((remain - 1) << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS));
}
int_en = 1;
}
// Break out if we've received all the bytes and we're not transmitting
if ((req->tx_data == NULL) && (req->rx_num == length)) {
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR);
int_en = 0;
MXC_FreeLock((uint32_t *)&states[spi_num].req);
// Callback if not NULL
if (req->callback != NULL) {
req->callback(req, E_NO_ERROR);
}
}
}
// Note:- spi->dma shows the FIFO TX count and FIFO RX count in
// Words, while the calculation below is in bytes.
if (req->tx_data != NULL) {
if (req->tx_num < length) {
// Calculate how many bytes we can write to the FIFO (tx_avail holds that value)
tx_avail = MXC_SPIMSS_FIFO_DEPTH - (((spi->dma & MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) >> MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS)); // in bytes
tx_avail =
MXC_SPIMSS_FIFO_DEPTH - (((spi->dma & MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) >>
MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS)); // in bytes
if ((length - req->tx_num) < tx_avail) {
tx_avail = (length - req->tx_num); // This is for the last spin
@ -385,7 +416,6 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r
spi->data = ((uint8_t *)req->tx_data)[req->tx_num++];
tx_avail -= 1;
}
}
}
@ -394,10 +424,13 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r
// If there are values remaining to be transmitted, this portion will get
// executed and int_en set, to indicate that this must spin and come back again...
if (remain) {
if (remain > MXC_SPIMSS_FIFO_DEPTH) { // more tx rounds will happen... Transfer the maximum,
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) | ((MXC_SPIMSS_FIFO_DEPTH) << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS));
if (remain >
MXC_SPIMSS_FIFO_DEPTH) { // more tx rounds will happen... Transfer the maximum,
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) |
((MXC_SPIMSS_FIFO_DEPTH) << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS));
} else { // only one more tx round will be done... Transfer whatever remains,
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) | ((remain) << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS));
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) |
((remain) << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS));
}
int_en = 1; // This will act as a trigger for the next round...
}
@ -414,45 +447,6 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r
}
}
// Read the RX FIFO
// Wait for there to be data in the RX FIFO
uint16_t rx_data;
rx_avail = ((spi->dma & MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) >> MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS);
if ((length - req->rx_num) < rx_avail) {
rx_avail = (length - req->rx_num);
}
// Read from the FIFO
while (rx_avail) {
rx_data = spi->data;
rx_avail -= 1;
if (req->rx_data != NULL) {
if (req->bits>8) {
((uint16_t*)req->rx_data)[req->rx_num] = rx_data;
} else {
((uint8_t*)req->rx_data)[req->rx_num] = rx_data;
}
}
req->rx_num++; // assume read one byte
rx_avail = ((spi->dma & MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) >> MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS);
if ((length - req->rx_num) < rx_avail) {
rx_avail = (length - req->rx_num);
}
}
remain = length - req->rx_num;
if (remain) {
if (remain > MXC_SPIMSS_FIFO_DEPTH) {
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) | ((2) << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS));
} else {
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) | ((remain-1) << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS));
}
int_en = 1;
}
// Break out once we've transmitted and received all of the data
if ((req->rx_num == length) && (req->tx_num == length)) {
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR);
@ -467,15 +461,6 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r
return int_en;
}
/* ************************************************************************* */
int MXC_SPIMSS_RevA_SetDefaultTXData (spimss_reva_req_t* spi, unsigned int defaultTXData)
{
int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
MXC_ASSERT (spi_num >= 0);
states[spi_num].defaultTXData = defaultTXData;
return E_NO_ERROR;
}
/* ************************************************************************* */
int MXC_SPIMSS_RevA_AbortAsync(spimss_reva_req_t *req)
{
@ -490,7 +475,6 @@ int MXC_SPIMSS_RevA_AbortAsync(spimss_reva_req_t *req)
// Find the request, set to NULL
for (spi_num = 0; spi_num < MXC_SPIMSS_INSTANCES; spi_num++) {
if (req == states[spi_num].req) {
spi = (mxc_spimss_reva_regs_t *)MXC_SPIMSS_GET_SPI(spi_num);
// Disable interrupts, clear the flags

15
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.h
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_SPIMSS_REVA_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_SPIMSS_REVA_H_
#include <stdio.h>
#include <stddef.h>
@ -92,13 +95,13 @@ struct spimss_reva_req {
spimss_reva_callback_fn callback; /**< Callback function if desired, NULL otherwise */
};
int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq, unsigned drv_ssel);
int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq);
int MXC_SPIMSS_RevA_Shutdown(mxc_spimss_reva_regs_t *spi);
void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi);
int MXC_SPIMSS_RevA_MasterTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
int MXC_SPIMSS_RevA_SlaveTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
int MXC_SPIMSS_RevA_MasterTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
int MXC_SPIMSS_RevA_SlaveTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
int MXC_SPIMSS_RevA_SetDefaultTXData (spimss_reva_req_t* spi, unsigned int defaultTXData);
int MXC_SPIMSS_RevA_AbortAsync(spimss_reva_req_t *req);
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_SPIMSS_REVA_H_

7
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva_regs.h
View File

@ -3,8 +3,8 @@
* @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _SPIMSS_REVA_REGS_H_
#define _SPIMSS_REVA_REGS_H_

5
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_assert.c
View File

@ -1,5 +1,5 @@
/******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,8 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include "mxc_device.h"

32
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_delay.c
View File

@ -1,5 +1,5 @@
/******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,8 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include <stdint.h>
@ -41,7 +40,7 @@
#ifdef __riscv
int MXC_Delay(unsigned long us)
int MXC_Delay(uint32_t us)
{
// Check if there is nothing to do
if (us == 0) {
@ -62,7 +61,7 @@ int MXC_Delay(unsigned long us)
return E_NO_ERROR;
}
int MXC_DelayAsync(unsigned long us, mxc_delay_complete_t callback)
int MXC_DelayAsync(uint32_t us, mxc_delay_complete_t callback)
{
return E_NOT_SUPPORTED;
}
@ -72,9 +71,7 @@ int MXC_DelayCheck(void)
return E_NOT_SUPPORTED;
}
void MXC_DelayAbort(void)
{
}
void MXC_DelayAbort(void) {}
#else
@ -84,7 +81,7 @@ static uint32_t endtick;
static uint32_t ctrl_save;
static mxc_delay_complete_t cbFunc;
static void MXC_DelayInit(unsigned long us);
static void MXC_DelayInit(uint32_t us);
extern void SysTick_Handler(void);
/* ************************************************************************** */
@ -101,8 +98,7 @@ void MXC_DelayHandler(void)
// Decrement overflow flag if delay is still ongoing
if (overflows > 0) {
overflows--;
}
else {
} else {
MXC_DelayAbort();
if (cbFunc != NULL) {
@ -114,7 +110,7 @@ void MXC_DelayHandler(void)
}
/* ************************************************************************** */
static void MXC_DelayInit(unsigned long us)
static void MXC_DelayInit(uint32_t us)
{
uint32_t starttick, reload, ticks, lastticks;
@ -131,8 +127,7 @@ static void MXC_DelayInit(unsigned long us)
SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk;
starttick = SysTick_VAL_CURRENT_Msk;
reload = SysTick_LOAD_RELOAD_Msk + 1;
}
else {
} else {
reload = SysTick->LOAD + 1; // get the current reload value
}
@ -149,14 +144,13 @@ static void MXC_DelayInit(unsigned long us)
if (lastticks >= starttick) {
overflows++;
endtick = reload - (lastticks - starttick);
}
else {
} else {
endtick = starttick - lastticks;
}
}
/* ************************************************************************** */
int MXC_DelayAsync(unsigned long us, mxc_delay_complete_t callback)
int MXC_DelayAsync(uint32_t us, mxc_delay_complete_t callback)
{
cbFunc = callback;
@ -222,7 +216,7 @@ void MXC_DelayAbort(void)
}
/* ************************************************************************** */
int MXC_Delay(unsigned long us)
int MXC_Delay(uint32_t us)
{
// Check if timeout currently ongoing
if (overflows > 0) {
@ -248,7 +242,7 @@ int MXC_Delay(unsigned long us)
}
// Wait for the counter value
while (SysTick->VAL > endtick);
while (SysTick->VAL > endtick) {}
MXC_DelayAbort();
return E_NO_ERROR;

18
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,28 +29,24 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include "mxc_device.h"
#include "mxc_lock.h"
#if USE_LOCK_IN_DRIVERS
#ifndef __riscv
/* ************************************************************************** */
int MXC_GetLock(uint32_t *lock, uint32_t value)
{
do {
// Return if the lock is taken by a different thread
if (__LDREXW((volatile unsigned long*) lock) != 0) {
if (__LDREXW((volatile uint32_t *)lock) != 0) {
return E_BUSY;
}
// Attempt to take the lock
}
while (__STREXW(value, (volatile unsigned long*) lock) != 0);
} while (__STREXW(value, (volatile uint32_t *)lock) != 0);
// Do not start any other memory access until memory barrier is complete
__DMB();
@ -79,5 +75,3 @@ void MXC_FreeLock(uint32_t* lock)
#warning "Unimplemented for RISCV"
}
#endif
#endif // USE_LOCK_IN_DRIVERS

76
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/pins_me11.c
View File

@ -4,7 +4,7 @@
*/
/******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
**************************************************************************** */
******************************************************************************/
#include "gpio.h"
#include "mxc_device.h"
@ -43,34 +42,55 @@
/***** Definitions *****/
/***** Global Variables *****/
const mxc_gpio_cfg_t gpio_cfg_swda = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_swdb = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_swda = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1),
MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_swdb = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9),
MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_i2c0 = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, MXC_GPIO_VSSEL_VDDIO};
const mxc_gpio_cfg_t gpio_cfg_i2c1 = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, MXC_GPIO_VSSEL_VDDIO};
const mxc_gpio_cfg_t gpio_cfg_i2c0 = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9),
MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP,
MXC_GPIO_VSSEL_VDDIO };
const mxc_gpio_cfg_t gpio_cfg_i2c1 = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3),
MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP,
MXC_GPIO_VSSEL_VDDIO };
const mxc_gpio_cfg_t gpio_cfg_uart0 = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5),
MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_uart0_flow = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7),
MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_uart1a = { MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11),
MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_uart1b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1),
MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_uart1c = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7),
MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_uart1_flow = { MXC_GPIO0, (MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13),
MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_uart0 = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_uart0_flow = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_uart1a = { MXC_GPIO0, (MXC_GPIO_PIN_10|MXC_GPIO_PIN_11), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_uart1b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_uart1c = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_uart1_flow = { MXC_GPIO0, (MXC_GPIO_PIN_12|MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
//SPI0
const mxc_gpio_cfg_t gpio_cfg_spi0 = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_spi0_ss = { MXC_GPIO0, MXC_GPIO_PIN_7, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
// SPI1A
const mxc_gpio_cfg_t gpio_cfg_spi1a = { MXC_GPIO0, (MXC_GPIO_PIN_10| MXC_GPIO_PIN_11| MXC_GPIO_PIN_12), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_spi1a_ss = { MXC_GPIO0, MXC_GPIO_PIN_13, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
//SPI1B
const mxc_gpio_cfg_t gpio_cfg_spi1b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_spi1b_ss = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_spi0 = {
MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7),
MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE
};
const mxc_gpio_cfg_t gpio_cfg_spi1a = {
MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11 | MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13),
MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE
};
const mxc_gpio_cfg_t gpio_cfg_spi1b = {
MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3),
MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE
};
// Timers are only defined once, depending on package, each timer could be mapped to other pins
const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO};
const mxc_gpio_cfg_t gpio_cfg_32kcal = { MXC_GPIO0, MXC_GPIO_PIN_2, MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO};
const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT3,
MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO };
const mxc_gpio_cfg_t gpio_cfg_32kcal = { MXC_GPIO0, MXC_GPIO_PIN_2, MXC_GPIO_FUNC_ALT3,
MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO };
const mxc_gpio_cfg_t gpio_cfg_i2s0a = { MXC_GPIO0, (MXC_GPIO_PIN_10| MXC_GPIO_PIN_11| MXC_GPIO_PIN_12|MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_i2s0b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_i2s0a = {
MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11 | MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13),
MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE
};
const mxc_gpio_cfg_t gpio_cfg_i2s0b = {
MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3),
MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE
};

109
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/sys_me11.c
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,8 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
/**
* @file mxc_sys.c
@ -45,6 +44,7 @@
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "mxc_delay.h"
#include "flc.h"
#include "gcr_regs.h"
#include "fcr_regs.h"
@ -60,6 +60,59 @@
/* **** Functions **** */
/* ************************************************************************** */
int MXC_SYS_GetUSN(uint8_t *usn, int len, int part)
{
if (len != MXC_SYS_USN_LEN) {
return E_BAD_PARAM;
}
uint32_t infoblock[6];
MXC_FLC_UnlockInfoBlock(0x0000);
infoblock[0] = *(uint32_t *)MXC_INFO_MEM_BASE;
infoblock[1] = *(uint32_t *)(MXC_INFO_MEM_BASE + 4);
infoblock[2] = *(uint32_t *)(MXC_INFO_MEM_BASE + 8);
infoblock[3] = *(uint32_t *)(MXC_INFO_MEM_BASE + 12);
infoblock[4] = *(uint32_t *)(MXC_INFO_MEM_BASE + 16);
infoblock[5] = *(uint32_t *)(MXC_INFO_MEM_BASE + 20);
MXC_FLC_LockInfoBlock(0x0000);
if (part == 0) {
usn[0] = (infoblock[0] & 0x000000FF);
usn[1] = (infoblock[0] & 0x0000FF00) >> 8;
usn[2] = (infoblock[0] & 0x00FF0000) >> 16;
usn[3] = (infoblock[0] & 0x3F000000) >> 24;
usn[3] |= (infoblock[1] & 0x00000003) << 30;
usn[4] = (infoblock[1] & 0x000003FC) >> 2;
usn[5] = (infoblock[1] & 0x0003FC00) >> 10;
usn[6] = (infoblock[1] & 0x03FC0000) >> 18;
usn[7] = (infoblock[1] & 0x3C000000) >> 26;
} else if (part == 1) {
usn[0] = (infoblock[2] & 0x000000FF);
usn[1] = (infoblock[2] & 0x0000FF00) >> 8;
usn[2] = (infoblock[2] & 0x00FF0000) >> 16;
usn[3] = (infoblock[2] & 0xFF000000) >> 24;
usn[4] = (infoblock[3] & 0x000000FF);
usn[5] = (infoblock[3] & 0x0000FF00) >> 8;
usn[6] = (infoblock[3] & 0x00FF0000) >> 16;
usn[7] = (infoblock[3] & 0xFF000000) >> 24;
} else if (part == 2) {
usn[0] = (infoblock[4] & 0x000000FF);
usn[1] = (infoblock[4] & 0x0000FF00) >> 8;
usn[2] = (infoblock[4] & 0x00FF0000) >> 16;
usn[3] = (infoblock[4] & 0xFF000000) >> 24;
usn[4] = (infoblock[5] & 0x000000FF);
usn[5] = (infoblock[5] & 0x0000FF00) >> 8;
usn[6] = (infoblock[5] & 0x00FF0000) >> 16;
usn[7] = (infoblock[5] & 0xFF000000) >> 24;
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
/* ************************************************************************** */
int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock)
{
@ -67,8 +120,7 @@ int MXC_SYS_IsClockEnabled (mxc_sys_periph_clock_t clock)
if (clock > 31) {
clock -= 32;
return !(MXC_GCR->pclk_dis1 & (0x1 << clock));
}
else {
} else {
return !(MXC_GCR->pclk_dis0 & (0x1 << clock));
}
}
@ -80,8 +132,7 @@ void MXC_SYS_ClockDisable (mxc_sys_periph_clock_t clock)
if (clock > 31) {
clock -= 32;
MXC_GCR->pclk_dis1 |= (0x1 << clock);
}
else {
} else {
MXC_GCR->pclk_dis0 |= (0x1 << clock);
}
}
@ -93,8 +144,7 @@ void MXC_SYS_ClockEnable (mxc_sys_periph_clock_t clock)
if (clock > 31) {
clock -= 32;
MXC_GCR->pclk_dis1 &= ~(0x1 << clock);
}
else {
} else {
MXC_GCR->pclk_dis0 &= ~(0x1 << clock);
}
}
@ -111,8 +161,7 @@ int MXC_SYS_RTCClockDisable (void)
if ((MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL) != MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN) {
MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_X32K_EN;
return E_NO_ERROR;
}
else {
} else {
return E_BAD_STATE;
}
}
@ -132,9 +181,8 @@ int MXC_SYS_ClockSourceEnable (mxc_sys_system_clock_t clock)
break;
case MXC_SYS_CLOCK_NANORING:
// MXC_GCR->clk_ctrl |= MXC_F_GCR_CLKCTRL_EXTCLK_EN;
// return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_EXTCLK_RDY);
return E_NOT_SUPPORTED;
// 80khz nanoring is always enabled
return E_NO_ERROR;
break;
default:
@ -165,7 +213,7 @@ int MXC_SYS_ClockSourceDisable (mxc_sys_system_clock_t clock)
break;
case MXC_SYS_CLOCK_NANORING:
// MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLKCTRL_EXTCLK_EN;
// 80khz nanoring is always enabled
return E_BAD_PARAM;
default:
@ -186,8 +234,7 @@ int MXC_SYS_Clock_Timeout (uint32_t ready)
MXC_DelayAbort();
return E_NO_ERROR;
}
}
while (MXC_DelayCheck() == E_BUSY);
} while (MXC_DelayCheck() == E_BUSY);
return E_TIME_OUT;
}
@ -205,7 +252,6 @@ int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock)
// Enable HIRC clock
if (!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_HIRC_EN)) {
MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC_EN;
// Check if HIRC clock is ready
@ -237,19 +283,12 @@ int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock)
break;
case MXC_SYS_CLOCK_NANORING:
// Enable HIRC clock
// if(!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLKCTRL_EXTCLK_EN)) {
// MXC_GCR->clk_ctrl |=MXC_F_GCR_CLKCTRL_EXTCLK_EN;
if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_LIRC8K_RDY) != E_NO_ERROR) {
return E_TIME_OUT;
}
// // Check if HIRC clock is ready
// if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_EXTCLK_RDY) != E_NO_ERROR) {
// return E_TIME_OUT;
// }
// }
// Set HIRC clock as System Clock
// MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK);
MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING);
MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL,
MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING);
break;
@ -259,7 +298,6 @@ int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock)
// Wait for system clock to be ready
if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_CLKRDY) != E_NO_ERROR) {
// Restore the old system clock if timeout
MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, current_clock);
@ -272,7 +310,6 @@ int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock)
return E_NO_ERROR;
}
/* ************************************************************************** */
void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset)
{
@ -280,10 +317,10 @@ void MXC_SYS_Reset_Periph (mxc_sys_reset_t reset)
if (reset > 31) {
reset -= 32;
MXC_GCR->rst1 = (0x1 << reset);
}
else {
while (MXC_GCR->rst1 & (0x1 << reset)) {}
} else {
MXC_GCR->rst0 = (0x1 << reset);
while (MXC_GCR->rst0 & (0x1 << reset)) {}
}
}
/**@} end of mxc_sys */

6
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_common.c
View File

@ -1,5 +1,5 @@
/******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include <stddef.h>
@ -39,7 +39,7 @@
/* **** Functions **** */
void MXC_TMR_Common_Delay(mxc_tmr_regs_t* tmr, unsigned long us)
void MXC_TMR_Common_Delay(mxc_tmr_regs_t *tmr, uint32_t us)
{
// Return immediately if delay is 0
if (!us) {

13
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_common.h
View File

@ -1,5 +1,5 @@
/******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_COMMON_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_COMMON_H_
/* **** Includes **** */
#include <stddef.h>
@ -37,8 +40,8 @@
#include "tmr.h"
/* **** Functions **** */
void MXC_TMR_Common_Delay (mxc_tmr_regs_t *tmr, unsigned long us);
void MXC_TMR_Common_TO_Start (mxc_tmr_regs_t *tmr, unsigned long us);
void MXC_TMR_Common_Delay(mxc_tmr_regs_t *tmr, uint32_t us);
void MXC_TMR_Common_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us);
int MXC_TMR_Common_TO_Check(mxc_tmr_regs_t *tmr);
void MXC_TMR_Common_TO_Stop(mxc_tmr_regs_t *tmr);
void MXC_TMR_Common_TO_Clear(mxc_tmr_regs_t *tmr);
@ -46,3 +49,5 @@ unsigned int MXC_TMR_Common_TO_Elapsed (mxc_tmr_regs_t *tmr);
unsigned int MXC_TMR_Common_TO_Remaining(mxc_tmr_regs_t *tmr);
void MXC_TMR_Common_SW_Start(mxc_tmr_regs_t *tmr);
unsigned int MXC_TMR_Common_SW_Stop(mxc_tmr_regs_t *tmr);
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_COMMON_H_

57
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_me11.c
View File

@ -1,5 +1,5 @@
/******************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
#include "tmr.h"
#include "tmr_reva.h"
@ -41,43 +41,26 @@ int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t* cfg)
MXC_ASSERT(tmr_id >= 0);
switch(cfg->clock){
case MXC_TMR_EXT_CLK:
MXC_GPIO_Config(&gpio_cfg_32kcal);
break;
case MXC_TMR_HFIO_CLK:
MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_HIRC);
break;
case MXC_TMR_NANORING_CLK:
MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_NANORING);
break;
default:
return E_BAD_PARAM;
break;
}
//enable peripheral clock and configure gpio pins
switch (tmr_id) {
case 0:
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TIMER0);
while(MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER0);
while (MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER0) {}
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR0);
MXC_GPIO_Config(&gpio_cfg_tmr0);
break;
case 1:
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TIMER1);
while(MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER1);
while (MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER1) {}
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR1);
break;
case 2:
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TIMER2);
while(MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER2);
while (MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER2) {}
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR2);
break;
}
MXC_TMR_RevA_Init((mxc_tmr_reva_regs_t *)tmr, cfg);
return E_NO_ERROR;
}
@ -131,28 +114,14 @@ uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t* tmr)
return MXC_TMR_RevA_GetCapture((mxc_tmr_reva_regs_t *)tmr);
}
uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t* tmr, mxc_tmr_clock_t clock, uint32_t prescalar, uint32_t frequency)
uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, uint32_t prescalar, uint32_t frequency)
{
uint32_t retVal, clkFreq;
switch(clock) {
case MXC_TMR_HFIO_CLK:
clkFreq = PeripheralClock;
break;
case MXC_TMR_NANORING_CLK:
clkFreq = 80000;
break;
case MXC_TMR_EXT_CLK:
clkFreq = HFX_FREQ;
break;
default:
clkFreq = PeripheralClock;
break;
}
uint32_t retVal;
if (frequency == 0) {
return 0;
}
else {
retVal = clkFreq / (prescalar * frequency);
} else {
retVal = PeripheralClock / (prescalar * frequency);
return retVal;
}
return retVal;
@ -183,12 +152,12 @@ void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt)
MXC_TMR_RevA_SetCount((mxc_tmr_reva_regs_t *)tmr, cnt);
}
void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, unsigned long us)
void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us)
{
MXC_TMR_Common_Delay(tmr, us);
}
void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, unsigned long us)
void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us)
{
MXC_TMR_RevA_TO_Start((mxc_tmr_reva_regs_t *)tmr, us);
}

69
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva.c
View File

@ -1,5 +1,5 @@
/******************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,10 +29,11 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include <stddef.h>
#include <string.h>
#include "mxc_assert.h"
#include "tmr.h"
#include "tmr_reva.h"
@ -82,6 +83,7 @@ void MXC_TMR_RevA_Init(mxc_tmr_reva_regs_t *tmr, mxc_tmr_cfg_t* cfg)
case TMR_PRES_256:
tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3);
tmr->cn &= ~(MXC_S_TMR_REVA_CN_PRES_DIV1);
break;
case TMR_PRES_512:
@ -101,12 +103,11 @@ void MXC_TMR_RevA_Init(mxc_tmr_reva_regs_t *tmr, mxc_tmr_cfg_t* cfg)
case TMR_PRES_4096:
tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3);
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV128);
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV32);
break;
default:
tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3);
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV128);
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV1);
break;
}
@ -120,9 +121,7 @@ void MXC_TMR_RevA_Init(mxc_tmr_reva_regs_t *tmr, mxc_tmr_cfg_t* cfg)
void MXC_TMR_RevA_Shutdown(mxc_tmr_reva_regs_t *tmr)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
MXC_ASSERT(tmr_id >= 0);
// Disable timer and clear settings
tmr->cn = 0;
@ -131,9 +130,7 @@ void MXC_TMR_RevA_Shutdown(mxc_tmr_reva_regs_t *tmr)
void MXC_TMR_RevA_Start(mxc_tmr_reva_regs_t *tmr)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
MXC_ASSERT(tmr_id >= 0);
tmr->cn |= MXC_F_TMR_REVA_CN_TEN;
}
@ -141,9 +138,7 @@ void MXC_TMR_RevA_Start(mxc_tmr_reva_regs_t* tmr)
void MXC_TMR_RevA_Stop(mxc_tmr_reva_regs_t *tmr)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
MXC_ASSERT(tmr_id >= 0);
tmr->cn &= ~MXC_F_TMR_REVA_CN_TEN;
}
@ -151,9 +146,7 @@ void MXC_TMR_RevA_Stop(mxc_tmr_reva_regs_t* tmr)
int MXC_TMR_RevA_SetPWM(mxc_tmr_reva_regs_t *tmr, uint32_t pwm)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
MXC_ASSERT(tmr_id >= 0);
if (pwm > (tmr->cmp)) {
return E_BAD_PARAM;
@ -167,9 +160,7 @@ int MXC_TMR_RevA_SetPWM(mxc_tmr_reva_regs_t* tmr, uint32_t pwm)
uint32_t MXC_TMR_RevA_GetCompare(mxc_tmr_reva_regs_t *tmr)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
MXC_ASSERT(tmr_id >= 0);
return tmr->cmp;
}
@ -177,9 +168,7 @@ uint32_t MXC_TMR_RevA_GetCompare(mxc_tmr_reva_regs_t* tmr)
uint32_t MXC_TMR_RevA_GetCapture(mxc_tmr_reva_regs_t *tmr)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
MXC_ASSERT(tmr_id >= 0);
return tmr->pwm; //check this
}
@ -187,9 +176,7 @@ uint32_t MXC_TMR_RevA_GetCapture(mxc_tmr_reva_regs_t* tmr)
uint32_t MXC_TMR_RevA_GetCount(mxc_tmr_reva_regs_t *tmr)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
MXC_ASSERT(tmr_id >= 0);
return tmr->cnt;
}
@ -197,9 +184,7 @@ uint32_t MXC_TMR_RevA_GetCount(mxc_tmr_reva_regs_t* tmr)
void MXC_TMR_RevA_ClearFlags(mxc_tmr_reva_regs_t *tmr)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
MXC_ASSERT(tmr_id >= 0);
tmr->intr = MXC_F_TMR_REVA_INTR_IRQ;
}
@ -207,9 +192,7 @@ void MXC_TMR_RevA_ClearFlags(mxc_tmr_reva_regs_t* tmr)
uint32_t MXC_TMR_RevA_GetFlags(mxc_tmr_reva_regs_t *tmr)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
MXC_ASSERT(tmr_id >= 0);
return tmr->intr;
}
@ -217,9 +200,7 @@ uint32_t MXC_TMR_RevA_GetFlags(mxc_tmr_reva_regs_t* tmr)
void MXC_TMR_RevA_SetCompare(mxc_tmr_reva_regs_t *tmr, uint32_t cmp_cnt)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
MXC_ASSERT(tmr_id >= 0);
tmr->cmp = cmp_cnt;
}
@ -227,17 +208,16 @@ void MXC_TMR_RevA_SetCompare(mxc_tmr_reva_regs_t *tmr, uint32_t cmp_cnt)
void MXC_TMR_RevA_SetCount(mxc_tmr_reva_regs_t *tmr, uint32_t cnt)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
MXC_ASSERT(tmr_id >= 0);
tmr->cnt = cnt;
}
void MXC_TMR_RevA_TO_Start(mxc_tmr_reva_regs_t *tmr, unsigned long us)
void MXC_TMR_RevA_TO_Start(mxc_tmr_reva_regs_t *tmr, uint32_t us)
{
uint64_t ticks;
int clk_shift = 0;
mxc_tmr_cfg_t cfg;
ticks = (uint64_t)us * (uint64_t)PeripheralClock / (uint64_t)1000000;
@ -247,7 +227,8 @@ void MXC_TMR_RevA_TO_Start(mxc_tmr_reva_regs_t *tmr, unsigned long us)
}
mxc_tmr_pres_t prescale = (mxc_tmr_pres_t)clk_shift << MXC_F_TMR_REVA_CN_PRES_POS;
mxc_tmr_cfg_t cfg = {0, 0, 0, 0}; // = (mxc_tmr_cfg_t) {.pres=0, .mode=0, .cmp_cnt=0, .pol=0};
memset(&cfg, 0, sizeof(mxc_tmr_cfg_t));
// Initialize the timer in one-shot mode
cfg.pres = prescale;
@ -261,12 +242,14 @@ void MXC_TMR_RevA_TO_Start(mxc_tmr_reva_regs_t *tmr, unsigned long us)
MXC_TMR_Start((mxc_tmr_regs_t *)tmr);
}
int MXC_TMR_RevA_GetTime(mxc_tmr_reva_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units)
int MXC_TMR_RevA_GetTime(mxc_tmr_reva_regs_t *tmr, uint32_t ticks, uint32_t *time,
mxc_tmr_unit_t *units)
{
uint64_t temp_time = 0;
uint32_t timerClock = PeripheralClock;
uint32_t prescale = ((tmr->cn & MXC_F_TMR_REVA_CN_PRES) >> MXC_F_TMR_REVA_CN_PRES_POS)
|(((tmr->cn & MXC_F_TMR_REVA_CN_PRES3) >> (MXC_F_TMR_REVA_CN_PRES3_POS)) <<3);
uint32_t prescale =
((tmr->cn & MXC_F_TMR_REVA_CN_PRES) >> MXC_F_TMR_REVA_CN_PRES_POS) |
(((tmr->cn & MXC_F_TMR_REVA_CN_PRES3) >> (MXC_F_TMR_REVA_CN_PRES3_POS)) << 3);
temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / (timerClock / 1000000);

13
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva.h
View File

@ -1,5 +1,5 @@
/******************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_REVA_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_REVA_H_
/* **** Includes **** */
#include <stddef.h>
@ -53,6 +56,8 @@ void MXC_TMR_RevA_ClearFlags(mxc_tmr_reva_regs_t* tmr);
uint32_t MXC_TMR_RevA_GetFlags(mxc_tmr_reva_regs_t *tmr);
void MXC_TMR_RevA_SetCompare(mxc_tmr_reva_regs_t *tmr, uint32_t cmp_cnt);
void MXC_TMR_RevA_SetCount(mxc_tmr_reva_regs_t *tmr, uint32_t cnt);
void MXC_TMR_RevA_TO_Start(mxc_tmr_reva_regs_t *tmr, unsigned long us);
int MXC_TMR_RevA_GetTime(mxc_tmr_reva_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units);
void MXC_TMR_RevA_TO_Start(mxc_tmr_reva_regs_t *tmr, uint32_t us);
int MXC_TMR_RevA_GetTime(mxc_tmr_reva_regs_t *tmr, uint32_t ticks, uint32_t *time,
mxc_tmr_unit_t *units);
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_REVA_H_

7
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva_regs.h
View File

@ -3,8 +3,8 @@
* @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _TMR_REVA_REGS_H_
#define _TMR_REVA_REGS_H_

10
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_common.c
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#include "uart_common.h"
#include "uart.h"
@ -37,7 +37,7 @@
int MXC_UART_Common_ReadCharacter(mxc_uart_regs_t *uart)
{
// Wait until FIFO has a character ready.
while (MXC_UART_GetRXFIFOAvailable(uart) < 1);
while (MXC_UART_GetRXFIFOAvailable(uart) < 1) {}
// Read the character using the non-blocking function.
return MXC_UART_ReadCharacterRaw(uart);
@ -46,7 +46,7 @@ int MXC_UART_Common_ReadCharacter(mxc_uart_regs_t* uart)
int MXC_UART_Common_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character)
{
// Wait until FIFO has space for the character.
while (MXC_UART_GetTXFIFOAvailable(uart) < 1);
while (MXC_UART_GetTXFIFOAvailable(uart) < 1) {}
// Write the character using the non-blocking function.
return MXC_UART_WriteCharacterRaw(uart, character);

10
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_common.h
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,10 +29,14 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_COMMON_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_COMMON_H_
#include "uart_regs.h"
int MXC_UART_Common_ReadCharacter(mxc_uart_regs_t *uart);
int MXC_UART_Common_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character);
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_COMMON_H_

69
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_me11.c
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#include "uart.h"
#include "mxc_device.h"
@ -41,7 +41,7 @@
void MXC_UART_DMACallback(int ch, int error)
{
return MXC_UART_RevA_DMACallback (ch, error);
MXC_UART_RevA_DMACallback(ch, error);
}
int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal)
@ -49,11 +49,31 @@ int MXC_UART_AsyncCallback (mxc_uart_regs_t* uart, int retVal)
return MXC_UART_RevA_AsyncCallback((mxc_uart_reva_regs_t *)uart, retVal);
}
int MXC_UART_TxAsyncCallback(mxc_uart_regs_t *uart, int retVal)
{
return MXC_UART_RevA_TxAsyncCallback((mxc_uart_reva_regs_t *)uart, retVal);
}
int MXC_UART_RxAsyncCallback(mxc_uart_regs_t *uart, int retVal)
{
return MXC_UART_RevA_RxAsyncCallback((mxc_uart_reva_regs_t *)uart, retVal);
}
int MXC_UART_AsyncStop(mxc_uart_regs_t *uart)
{
return MXC_UART_RevA_AsyncStop((mxc_uart_reva_regs_t *)uart);
}
int MXC_UART_TxAsyncStop(mxc_uart_regs_t *uart)
{
return MXC_UART_RevA_TxAsyncStop((mxc_uart_reva_regs_t *)uart);
}
int MXC_UART_RxAsyncStop(mxc_uart_regs_t *uart)
{
return MXC_UART_RevA_RxAsyncStop((mxc_uart_reva_regs_t *)uart);
}
int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, sys_map_t map)
{
int retval;
@ -214,15 +234,13 @@ int MXC_UART_Write (mxc_uart_regs_t* uart, uint8_t* byte, int* len)
return MXC_UART_RevA_Write((mxc_uart_reva_regs_t *)uart, byte, len);
}
unsigned int MXC_UART_ReadRXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len)
unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len)
{
return MXC_UART_RevA_ReadRXFIFO((mxc_uart_reva_regs_t *)uart, bytes, len);
}
int MXC_UART_ReadRXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len, mxc_uart_dma_complete_cb_t callback)
int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len,
mxc_uart_dma_complete_cb_t callback)
{
mxc_dma_config_t config;
@ -243,7 +261,8 @@ int MXC_UART_ReadRXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes,
break;
}
return MXC_UART_RevA_ReadRXFIFODMA ((mxc_uart_reva_regs_t*) uart, MXC_DMA, bytes, len, callback, config);
return MXC_UART_RevA_ReadRXFIFODMA((mxc_uart_reva_regs_t *)uart, MXC_DMA, bytes, len, callback,
config);
}
unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart)
@ -251,14 +270,13 @@ unsigned int MXC_UART_GetRXFIFOAvailable (mxc_uart_regs_t* uart)
return MXC_UART_RevA_GetRXFIFOAvailable((mxc_uart_reva_regs_t *)uart);
}
unsigned int MXC_UART_WriteTXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len)
unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len)
{
return MXC_UART_RevA_WriteTXFIFO((mxc_uart_reva_regs_t *)uart, bytes, len);
}
int MXC_UART_WriteTXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len, mxc_uart_dma_complete_cb_t callback)
int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len,
mxc_uart_dma_complete_cb_t callback)
{
mxc_dma_config_t config;
@ -279,7 +297,8 @@ int MXC_UART_WriteTXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes,
break;
}
return MXC_UART_RevA_WriteTXFIFODMA ((mxc_uart_reva_regs_t*) uart, MXC_DMA, bytes, len, callback, config);
return MXC_UART_RevA_WriteTXFIFODMA((mxc_uart_reva_regs_t *)uart, MXC_DMA, bytes, len, callback,
config);
}
unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart)
@ -367,7 +386,27 @@ int MXC_UART_AbortAsync (mxc_uart_regs_t* uart)
return MXC_UART_RevA_AbortAsync((mxc_uart_reva_regs_t *)uart);
}
int MXC_UART_TxAbortAsync(mxc_uart_regs_t *uart)
{
return MXC_UART_RevA_TxAbortAsync((mxc_uart_reva_regs_t *)uart);
}
int MXC_UART_RxAbortAsync(mxc_uart_regs_t *uart)
{
return MXC_UART_RevA_RxAbortAsync((mxc_uart_reva_regs_t *)uart);
}
int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart)
{
return MXC_UART_RevA_AsyncHandler((mxc_uart_reva_regs_t *)uart);
}
uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req)
{
return req->txCnt;
}
uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t *req)
{
return req->rxCnt;
}

402
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.c
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#include <stdio.h>
#include "mxc_device.h"
@ -39,16 +39,17 @@
#include "dma.h"
/* **** Definitions **** */
#define MXC_UART_REVA_ERRINT_EN (MXC_F_UART_REVA_INT_EN_RX_FRAME_ERROR | \
MXC_F_UART_REVA_INT_EN_RX_PARITY_ERROR | \
#define MXC_UART_REVA_ERRINT_EN \
(MXC_F_UART_REVA_INT_EN_RX_FRAME_ERROR | MXC_F_UART_REVA_INT_EN_RX_PARITY_ERROR | \
MXC_F_UART_REVA_INT_EN_RX_OVERRUN)
#define MXC_UART_REVA_ERRINT_FL (MXC_F_UART_REVA_INT_FL_RX_FRAME_ERROR | \
MXC_F_UART_REVA_INT_FL_RX_PARITY_ERROR | \
#define MXC_UART_REVA_ERRINT_FL \
(MXC_F_UART_REVA_INT_FL_RX_FRAME_ERROR | MXC_F_UART_REVA_INT_FL_RX_PARITY_ERROR | \
MXC_F_UART_REVA_INT_FL_RX_OVERRUN)
/* **** Variable Declaration **** */
static void* AsyncRequests[MXC_UART_INSTANCES];
static void *TxAsyncRequests[MXC_UART_INSTANCES];
static void *RxAsyncRequests[MXC_UART_INSTANCES];
// Structure to save DMA state
typedef struct {
@ -84,7 +85,8 @@ int MXC_UART_RevA_Init (mxc_uart_reva_regs_t* uart, unsigned int baud)
return err;
}
if ((err = (MXC_UART_SetParity ((mxc_uart_regs_t*) uart, MXC_UART_PARITY_DISABLE))) != E_NO_ERROR) {
if ((err = (MXC_UART_SetParity((mxc_uart_regs_t *)uart, MXC_UART_PARITY_DISABLE))) !=
E_NO_ERROR) {
return err;
}
@ -105,10 +107,12 @@ int MXC_UART_RevA_ReadyForSleep (mxc_uart_reva_regs_t* uart)
return E_BAD_PARAM;
}
if (AsyncRequests[MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart)] != NULL) {
if (TxAsyncRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)uart)] != NULL) {
return E_BUSY;
}
/* We can sleep if waiting for RX Async */
return MXC_UART_GetActive((mxc_uart_regs_t *)uart);
}
@ -129,21 +133,24 @@ int MXC_UART_RevA_SetFrequency (mxc_uart_reva_regs_t* uart, unsigned int baud)
#else
return E_BAD_PARAM;
#endif
}
else {
} else {
periphClock = PeripheralClock;
}
uartDiv = (float)periphClock / baud;
// Find the largest value of prescale that keeps div > 1
for (prescale = 8; prescale < 128; prescale = prescale << 1) {
for (prescale = 8; prescale <= 128; prescale = prescale << 1) {
if (uartDiv / (float)prescale < 1) {
prescale = prescale >> 1;
break;
}
}
if (prescale > 128) {
prescale = 128;
}
if (prescale < 8) {
return E_BAD_PARAM;
}
@ -154,8 +161,7 @@ int MXC_UART_RevA_SetFrequency (mxc_uart_reva_regs_t* uart, unsigned int baud)
// Work around for Jira Bug: ME10-650
if (decimalDiv > 3) {
decimalDiv -= 3;
}
else {
} else {
decimalDiv += 3;
}
@ -189,7 +195,8 @@ int MXC_UART_RevA_SetFrequency (mxc_uart_reva_regs_t* uart, unsigned int baud)
decimalDiv <<= MXC_F_UART_REVA_BAUD1_DBAUD_POS;
MXC_SETFIELD(uart->baud0, MXC_F_UART_REVA_BAUD0_FACTOR, prescale);
MXC_SETFIELD (uart->baud0, MXC_F_UART_REVA_BAUD0_IBAUD, (((int) uartDiv) << MXC_F_UART_REVA_BAUD0_IBAUD_POS));
MXC_SETFIELD(uart->baud0, MXC_F_UART_REVA_BAUD0_IBAUD,
(((int)uartDiv) << MXC_F_UART_REVA_BAUD0_IBAUD_POS));
MXC_SETFIELD(uart->baud1, MXC_F_UART_REVA_BAUD1_DBAUD, decimalDiv);
return MXC_UART_GetFrequency((mxc_uart_regs_t *)uart);
@ -207,8 +214,7 @@ int MXC_UART_RevA_GetFrequency (mxc_uart_reva_regs_t* uart)
#else
return E_BAD_PARAM;
#endif
}
else {
} else {
periphClock = PeripheralClock;
}
@ -220,12 +226,11 @@ int MXC_UART_RevA_GetFrequency (mxc_uart_reva_regs_t* uart)
// subtracted 3 in this range
if (decimalDiv > 3 && decimalDiv <= 6) {
decimalDiv -= 3;
}
else {
} else {
decimalDiv += 3;
}
uartDiv += decimalDiv / (float)128;
uartDiv += decimalDiv / 128.0;
uartDiv *= (1 << (7 - (uart->baud0 & MXC_F_UART_REVA_BAUD0_FACTOR)));
return (int)((float)periphClock / uartDiv);
@ -256,11 +261,13 @@ int MXC_UART_RevA_SetStopBits (mxc_uart_reva_regs_t* uart, mxc_uart_stop_t stopB
switch (stopBits) {
case MXC_UART_STOP_1:
MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_STOPBITS, 0 << MXC_F_UART_REVA_CTRL_STOPBITS_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_STOPBITS,
0 << MXC_F_UART_REVA_CTRL_STOPBITS_POS);
break;
case MXC_UART_STOP_2:
MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_STOPBITS, 1 << MXC_F_UART_REVA_CTRL_STOPBITS_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_STOPBITS,
1 << MXC_F_UART_REVA_CTRL_STOPBITS_POS);
break;
default:
@ -279,57 +286,66 @@ int MXC_UART_RevA_SetParity (mxc_uart_reva_regs_t* uart, mxc_uart_parity_t parit
switch (parity) {
case MXC_UART_PARITY_DISABLE:
MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 0 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS );
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN,
0 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS);
break;
case MXC_UART_PARITY_EVEN:
case MXC_UART_PARITY_EVEN_0:
MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN,
1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_EVEN);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 0 << MXC_F_UART_REVA_CTRL_PARMD_POS);
break;
case MXC_UART_PARITY_EVEN_1:
MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN,
1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_EVEN);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 1 << MXC_F_UART_REVA_CTRL_PARMD_POS);
break;
case MXC_UART_PARITY_ODD:
case MXC_UART_PARITY_ODD_0:
MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN,
1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_ODD);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 0 << MXC_F_UART_REVA_CTRL_PARMD_POS);
break;
case MXC_UART_PARITY_ODD_1:
MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN,
1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_ODD);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 1 << MXC_F_UART_REVA_CTRL_PARMD_POS);
break;
case MXC_UART_PARITY_MARK:
case MXC_UART_PARITY_MARK_0:
MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN,
1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_MARK);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 0 << MXC_F_UART_REVA_CTRL_PARMD_POS);
break;
case MXC_UART_PARITY_MARK_1:
MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN,
1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_MARK);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 1 << MXC_F_UART_REVA_CTRL_PARMD_POS);
break;
case MXC_UART_PARITY_SPACE:
case MXC_UART_PARITY_SPACE_0:
MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN,
1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_SPACE);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 0 << MXC_F_UART_REVA_CTRL_PARMD_POS);
break;
case MXC_UART_PARITY_SPACE_1:
MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN,
1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_SPACE);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 1 << MXC_F_UART_REVA_CTRL_PARMD_POS);
break;
@ -342,7 +358,8 @@ int MXC_UART_RevA_SetParity (mxc_uart_reva_regs_t* uart, mxc_uart_parity_t parit
return E_NO_ERROR;
}
int MXC_UART_RevA_SetFlowCtrl (mxc_uart_reva_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold)
int MXC_UART_RevA_SetFlowCtrl(mxc_uart_reva_regs_t *uart, mxc_uart_flow_t flowCtrl,
int rtsThreshold)
{
if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) {
return E_BAD_PARAM;
@ -350,17 +367,22 @@ int MXC_UART_RevA_SetFlowCtrl (mxc_uart_reva_regs_t* uart, mxc_uart_flow_t flowC
switch (flowCtrl) {
case MXC_UART_FLOW_DIS:
MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_CTRL, 0 << MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_CTRL,
0 << MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS);
break;
case MXC_UART_FLOW_EN_LOW:
MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_CTRL, 1 << MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS);
MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_POL, 0 << MXC_F_UART_REVA_CTRL_FLOW_POL_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_CTRL,
1 << MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_POL,
0 << MXC_F_UART_REVA_CTRL_FLOW_POL_POS);
break;
case MXC_UART_FLOW_EN_HIGH:
MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_CTRL, 1 << MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS);
MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_POL, 1 << MXC_F_UART_REVA_CTRL_FLOW_POL_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_CTRL,
1 << MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS);
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_POL,
1 << MXC_F_UART_REVA_CTRL_FLOW_POL_POS);
break;
default:
@ -372,7 +394,7 @@ int MXC_UART_RevA_SetFlowCtrl (mxc_uart_reva_regs_t* uart, mxc_uart_flow_t flowC
return E_BAD_PARAM;
}
rtsThreshold <<= MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH_POS;
rtsThreshold <<= MXC_F_UART_REVA_THRESH_CTRL_RTS_FIFO_THRESH_POS;
MXC_SETFIELD(uart->thresh_ctrl, MXC_F_UART_REVA_THRESH_CTRL_RTS_FIFO_THRESH, rtsThreshold);
return E_NO_ERROR;
@ -393,8 +415,7 @@ int MXC_UART_RevA_SetClockSource (mxc_uart_reva_regs_t* uart, int usePCLK)
if (usePCLK) {
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_CLKSEL, 0 << MXC_F_UART_REVA_CTRL_CLKSEL_POS);
}
else {
} else {
MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_CLKSEL, 1 << MXC_F_UART_REVA_CTRL_CLKSEL_POS);
}
@ -484,8 +505,7 @@ int MXC_UART_RevA_Read (mxc_uart_reva_regs_t* uart, uint8_t* buffer, int* len)
if (retVal < 0) {
*len = read;
return retVal;
}
else {
} else {
buffer[read] = retVal;
}
}
@ -512,7 +532,8 @@ int MXC_UART_RevA_Write (mxc_uart_reva_regs_t* uart, uint8_t* byte, int* len)
return E_NO_ERROR;
}
unsigned int MXC_UART_RevA_ReadRXFIFO (mxc_uart_reva_regs_t* uart, unsigned char* bytes, unsigned int len)
unsigned int MXC_UART_RevA_ReadRXFIFO(mxc_uart_reva_regs_t *uart, unsigned char *bytes,
unsigned int len)
{
unsigned int read = 0;
@ -527,7 +548,8 @@ unsigned int MXC_UART_RevA_ReadRXFIFO (mxc_uart_reva_regs_t* uart, unsigned char
return read;
}
int MXC_UART_RevA_ReadRXFIFODMA (mxc_uart_reva_regs_t* uart, mxc_dma_regs_t* dma, unsigned char* bytes, unsigned int len,
int MXC_UART_RevA_ReadRXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma,
unsigned char *bytes, unsigned int len,
mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config)
{
uint8_t channel;
@ -561,7 +583,6 @@ int MXC_UART_RevA_ReadRXFIFODMA (mxc_uart_reva_regs_t* uart, mxc_dma_regs_t* dma
srcdst.dest = bytes;
srcdst.len = len;
states[uart_num].channelRx = channel;
MXC_DMA_ConfigChannel(config, srcdst);
MXC_DMA_SetCallback(channel, MXC_UART_DMACallback);
@ -576,10 +597,12 @@ int MXC_UART_RevA_ReadRXFIFODMA (mxc_uart_reva_regs_t* uart, mxc_dma_regs_t* dma
unsigned int MXC_UART_RevA_GetRXFIFOAvailable(mxc_uart_reva_regs_t *uart)
{
return (uart->status & MXC_F_UART_REVA_STATUS_RX_FIFO_CNT) >> MXC_F_UART_REVA_STATUS_RX_FIFO_CNT_POS;
return (uart->status & MXC_F_UART_REVA_STATUS_RX_FIFO_CNT) >>
MXC_F_UART_REVA_STATUS_RX_FIFO_CNT_POS;
}
unsigned int MXC_UART_RevA_WriteTXFIFO (mxc_uart_reva_regs_t* uart, unsigned char* bytes, unsigned int len)
unsigned int MXC_UART_RevA_WriteTXFIFO(mxc_uart_reva_regs_t *uart, unsigned char *bytes,
unsigned int len)
{
unsigned int written = 0;
@ -594,8 +617,10 @@ unsigned int MXC_UART_RevA_WriteTXFIFO (mxc_uart_reva_regs_t* uart, unsigned cha
return written;
}
unsigned int MXC_UART_RevA_WriteTXFIFODMA (mxc_uart_reva_regs_t* uart, mxc_dma_regs_t* dma, unsigned char* bytes, unsigned int len,
mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config)
unsigned int MXC_UART_RevA_WriteTXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma,
unsigned char *bytes, unsigned int len,
mxc_uart_dma_complete_cb_t callback,
mxc_dma_config_t config)
{
uint8_t channel;
mxc_dma_srcdst_t srcdst;
@ -628,7 +653,6 @@ unsigned int MXC_UART_RevA_WriteTXFIFODMA (mxc_uart_reva_regs_t* uart, mxc_dma_r
srcdst.source = bytes;
srcdst.len = len;
states[uart_num].channelTx = channel;
MXC_DMA_ConfigChannel(config, srcdst);
MXC_DMA_SetCallback(channel, MXC_UART_DMACallback);
@ -644,7 +668,8 @@ unsigned int MXC_UART_RevA_WriteTXFIFODMA (mxc_uart_reva_regs_t* uart, mxc_dma_r
unsigned int MXC_UART_RevA_GetTXFIFOAvailable(mxc_uart_reva_regs_t *uart)
{
int txCnt = (uart->status & MXC_F_UART_REVA_STATUS_TX_FIFO_CNT) >> MXC_F_UART_REVA_STATUS_TX_FIFO_CNT_POS;
int txCnt = (uart->status & MXC_F_UART_REVA_STATUS_TX_FIFO_CNT) >>
MXC_F_UART_REVA_STATUS_TX_FIFO_CNT_POS;
return MXC_UART_FIFO_DEPTH - txCnt;
}
@ -656,7 +681,7 @@ int MXC_UART_RevA_ClearRXFIFO (mxc_uart_reva_regs_t* uart)
uart->ctrl |= MXC_F_UART_REVA_CTRL_RX_FLUSH;
while (uart->ctrl & MXC_F_UART_REVA_CTRL_RX_FLUSH);
while (uart->ctrl & MXC_F_UART_REVA_CTRL_RX_FLUSH) {}
return E_NO_ERROR;
}
@ -669,7 +694,7 @@ int MXC_UART_RevA_ClearTXFIFO (mxc_uart_reva_regs_t* uart)
uart->ctrl |= MXC_F_UART_REVA_CTRL_TX_FLUSH;
while (uart->ctrl & MXC_F_UART_REVA_CTRL_TX_FLUSH);
while (uart->ctrl & MXC_F_UART_REVA_CTRL_TX_FLUSH) {}
return E_NO_ERROR;
}
@ -692,7 +717,8 @@ int MXC_UART_RevA_SetRXThreshold (mxc_uart_reva_regs_t* uart, unsigned int numBy
unsigned int MXC_UART_RevA_GetRXThreshold(mxc_uart_reva_regs_t *uart)
{
return (uart->thresh_ctrl & MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH) >> MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH_POS;
return (uart->thresh_ctrl & MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH) >>
MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH_POS;
}
int MXC_UART_RevA_SetTXThreshold(mxc_uart_reva_regs_t *uart, unsigned int numBytes)
@ -713,7 +739,8 @@ int MXC_UART_RevA_SetTXThreshold (mxc_uart_reva_regs_t* uart, unsigned int numBy
unsigned int MXC_UART_RevA_GetTXThreshold(mxc_uart_reva_regs_t *uart)
{
return (uart->thresh_ctrl & MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH) >> MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH_POS;
return (uart->thresh_ctrl & MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH) >>
MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH_POS;
}
unsigned int MXC_UART_RevA_GetFlags(mxc_uart_reva_regs_t *uart)
@ -761,15 +788,15 @@ unsigned int MXC_UART_RevA_GetStatus (mxc_uart_reva_regs_t* uart)
int MXC_UART_RevA_Busy(mxc_uart_reva_regs_t *uart)
{
int uart_num = MXC_UART_GET_IDX((mxc_uart_regs_t*) uart); // Holds the current index of tx_states
int uart_num =
MXC_UART_GET_IDX((mxc_uart_regs_t *)uart); // Holds the current index of tx_states
MXC_ASSERT(uart_num >= 0);
if ((uart->status & MXC_F_UART_REVA_STATUS_TX_BUSY) || (uart->status & MXC_F_UART_REVA_STATUS_RX_BUSY)) {
if ((uart->status & MXC_F_UART_REVA_STATUS_TX_BUSY) ||
(uart->status & MXC_F_UART_REVA_STATUS_RX_BUSY)) {
return E_BUSY;
}
// Check to see if there are any ongoing transactions and the UART has room in its FIFO
if ((states[uart_num].req == NULL) &&
!(uart->status & MXC_F_UART_REVA_STATUS_TX_FULL)) {
if ((states[uart_num].req == NULL) && !(uart->status & MXC_F_UART_REVA_STATUS_TX_FULL)) {
return E_NO_ERROR;
}
@ -806,30 +833,39 @@ int MXC_UART_RevA_Transaction (mxc_uart_reva_req_t* req)
numToWrite = MXC_UART_GetTXFIFOAvailable((mxc_uart_regs_t *)(req->uart));
numToWrite = numToWrite > (req->txLen - req->txCnt) ? req->txLen - req->txCnt : numToWrite;
req->txCnt += MXC_UART_WriteTXFIFO ((mxc_uart_regs_t*)(req->uart), &req->txData[req->txCnt], numToWrite);
req->txCnt += MXC_UART_WriteTXFIFO((mxc_uart_regs_t *)(req->uart), &req->txData[req->txCnt],
numToWrite);
while (req->txCnt < req->txLen) {
while ( !(MXC_UART_GetFlags ((mxc_uart_regs_t*)(req->uart)) & MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH));
while (!(MXC_UART_GetFlags((mxc_uart_regs_t *)(req->uart)) &
MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH)) {}
numToWrite = MXC_UART_GetTXFIFOAvailable((mxc_uart_regs_t *)(req->uart));
numToWrite = numToWrite > (req->txLen-req->txCnt) ? req->txLen-req->txCnt : numToWrite;
req->txCnt += MXC_UART_WriteTXFIFO ((mxc_uart_regs_t*)(req->uart), &req->txData[req->txCnt], numToWrite);
MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH);
numToWrite = numToWrite > (req->txLen - req->txCnt) ? req->txLen - req->txCnt :
numToWrite;
req->txCnt += MXC_UART_WriteTXFIFO((mxc_uart_regs_t *)(req->uart),
&req->txData[req->txCnt], numToWrite);
MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart),
MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH);
}
}
if (req->rxLen) {
numToRead = MXC_UART_GetRXFIFOAvailable((mxc_uart_regs_t *)(req->uart));
numToRead = numToRead > (req->rxLen - req->rxCnt) ? req->rxLen - req->rxCnt : numToRead;
req->rxCnt += MXC_UART_ReadRXFIFO ((mxc_uart_regs_t*)(req->uart), &req->rxData[req->rxCnt], numToRead);
req->rxCnt += MXC_UART_ReadRXFIFO((mxc_uart_regs_t *)(req->uart), &req->rxData[req->rxCnt],
numToRead);
while (req->rxCnt < req->rxLen) {
while ( !(MXC_UART_GetFlags ((mxc_uart_regs_t*)(req->uart)) & MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH));
while (!(MXC_UART_GetFlags((mxc_uart_regs_t *)(req->uart)) &
MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH)) {}
numToRead = MXC_UART_GetRXFIFOAvailable((mxc_uart_regs_t *)(req->uart));
numToRead = numToRead > (req->rxLen - req->rxCnt) ? req->rxLen - req->rxCnt : numToRead;
req->rxCnt += MXC_UART_ReadRXFIFO ((mxc_uart_regs_t*)(req->uart), &req->rxData[req->rxCnt], numToRead);
MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH);
req->rxCnt += MXC_UART_ReadRXFIFO((mxc_uart_regs_t *)(req->uart),
&req->rxData[req->rxCnt], numToRead);
MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart),
MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH);
}
}
@ -844,44 +880,41 @@ int MXC_UART_RevA_TransactionAsync (mxc_uart_reva_req_t* req)
return E_BAD_PARAM;
}
MXC_UART_DisableInt ((mxc_uart_regs_t*)(req->uart), 0xFFFFFFFF);
MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), 0xFFFFFFFF);
MXC_UART_ClearRXFIFO ((mxc_uart_regs_t*)(req->uart));
MXC_UART_ClearTXFIFO ((mxc_uart_regs_t*)(req->uart));
req->txCnt = 0;
req->rxCnt = 0;
if (req->txLen) {
if (req->txData == NULL) {
return E_BAD_PARAM;
}
req->txCnt = 0;
MXC_UART_EnableInt((mxc_uart_regs_t *)(req->uart), MXC_F_UART_REVA_INT_EN_TX_FIFO_THRESH);
numToWrite = MXC_UART_GetTXFIFOAvailable((mxc_uart_regs_t *)(req->uart));
numToWrite = numToWrite > (req->txLen - req->txCnt) ? req->txLen - req->txCnt : numToWrite;
req->txCnt += MXC_UART_WriteTXFIFO ((mxc_uart_regs_t*)(req->uart), &req->txData[req->txCnt], numToWrite);
req->txCnt += MXC_UART_WriteTXFIFO((mxc_uart_regs_t *)(req->uart), &req->txData[req->txCnt],
numToWrite);
TxAsyncRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart))] = (void *)req;
}
if (req->rxLen) {
// All error interrupts are related to RX
MXC_UART_EnableInt ((mxc_uart_regs_t*)(req->uart), MXC_UART_REVA_ERRINT_EN);
if (req->rxData == NULL) {
MXC_UART_DisableInt((mxc_uart_regs_t *)(req->uart), 0xFFFFFFFF);
MXC_UART_ClearTXFIFO ((mxc_uart_regs_t*)(req->uart));
return E_BAD_PARAM;
}
req->rxCnt = 0;
// All error interrupts are related to RX
MXC_UART_EnableInt((mxc_uart_regs_t *)(req->uart), MXC_UART_REVA_ERRINT_EN);
MXC_UART_EnableInt((mxc_uart_regs_t *)(req->uart), MXC_F_UART_REVA_INT_EN_RX_FIFO_THRESH);
numToRead = MXC_UART_GetRXFIFOAvailable((mxc_uart_regs_t *)(req->uart));
numToRead = numToRead > (req->rxLen - req->rxCnt) ? req->rxLen - req->rxCnt : numToRead;
req->rxCnt += MXC_UART_ReadRXFIFO ((mxc_uart_regs_t*)(req->uart), &req->rxData[req->rxCnt], numToRead);
req->rxCnt += MXC_UART_ReadRXFIFO((mxc_uart_regs_t *)(req->uart), &req->rxData[req->rxCnt],
numToRead);
MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart), MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH);
RxAsyncRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart))] = (void *)req;
}
AsyncRequests[MXC_UART_GET_IDX ((mxc_uart_regs_t*)(req->uart))] = (void *) req;
return E_NO_ERROR;
}
@ -911,8 +944,10 @@ int MXC_UART_RevA_TransactionDMA (mxc_uart_reva_req_t* req, mxc_dma_regs_t* dma)
MXC_UART_ClearRXFIFO((mxc_uart_regs_t *)(req->uart));
MXC_UART_ClearTXFIFO((mxc_uart_regs_t *)(req->uart));
(req->uart)->dma |= (1 << MXC_F_UART_REVA_DMA_RXDMA_LEVEL_POS); // Set RX DMA threshold to 1 byte
(req->uart)->dma |= (2 << MXC_F_UART_REVA_DMA_TXDMA_LEVEL_POS); // Set TX DMA threshold to 2 bytes
(req->uart)->dma |=
(1 << MXC_F_UART_REVA_DMA_RXDMA_LEVEL_POS); // Set RX DMA threshold to 1 byte
(req->uart)->dma |=
(2 << MXC_F_UART_REVA_DMA_TXDMA_LEVEL_POS); // Set TX DMA threshold to 2 bytes
#if TARGET_NUM == 32665
MXC_DMA_Init(dma);
@ -923,11 +958,13 @@ int MXC_UART_RevA_TransactionDMA (mxc_uart_reva_req_t* req, mxc_dma_regs_t* dma)
//tx
if ((req->txData != NULL) && (req->txLen)) {
#if TARGET_NUM == 32665
if (MXC_UART_WriteTXFIFODMA ((mxc_uart_regs_t*)(req->uart), dma, req->txData, req->txLen, NULL) != E_NO_ERROR) {
if (MXC_UART_WriteTXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->txData, req->txLen,
NULL) != E_NO_ERROR) {
return E_BAD_PARAM;
}
#else
if (MXC_UART_WriteTXFIFODMA ((mxc_uart_regs_t*)(req->uart), req->txData, req->txLen, NULL) != E_NO_ERROR) {
if (MXC_UART_WriteTXFIFODMA((mxc_uart_regs_t *)(req->uart), req->txData, req->txLen,
NULL) != E_NO_ERROR) {
return E_BAD_PARAM;
}
#endif
@ -935,11 +972,13 @@ int MXC_UART_RevA_TransactionDMA (mxc_uart_reva_req_t* req, mxc_dma_regs_t* dma)
if ((req->rxData != NULL) && (req->rxLen)) {
#if TARGET_NUM == 32665
if (MXC_UART_ReadRXFIFODMA ((mxc_uart_regs_t*)(req->uart), dma, req->rxData, req->rxLen, NULL) != E_NO_ERROR) {
if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->rxData, req->rxLen,
NULL) != E_NO_ERROR) {
return E_BAD_PARAM;
}
#else
if (MXC_UART_ReadRXFIFODMA ((mxc_uart_regs_t*)(req->uart), req->rxData, req->rxLen, NULL) != E_NO_ERROR) {
if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), req->rxData, req->rxLen, NULL) !=
E_NO_ERROR) {
return E_BAD_PARAM;
}
#endif
@ -961,9 +1000,7 @@ void MXC_UART_RevA_DMACallback (int ch, int error)
temp_req->callback((mxc_uart_req_t *)temp_req, E_NO_ERROR);
}
break;
}
else if (states[i].channelRx == ch) {
} else if (states[i].channelRx == ch) {
//save the request
temp_req = states[i].req;
// Callback if not NULL
@ -975,13 +1012,14 @@ void MXC_UART_RevA_DMACallback (int ch, int error)
}
}
int MXC_UART_RevA_AsyncCallback (mxc_uart_reva_regs_t* uart, int retVal)
int MXC_UART_RevA_RxAsyncCallback(mxc_uart_reva_regs_t *uart, int retVal)
{
if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) {
return E_BAD_PARAM;
}
mxc_uart_reva_req_t* req = (mxc_uart_reva_req_t*) AsyncRequests[MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart)];
mxc_uart_reva_req_t *req =
(mxc_uart_reva_req_t *)RxAsyncRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)uart)];
if (req->callback != NULL) {
req->callback((mxc_uart_req_t *)req, retVal);
@ -990,26 +1028,157 @@ int MXC_UART_RevA_AsyncCallback (mxc_uart_reva_regs_t* uart, int retVal)
return E_NO_ERROR;
}
int MXC_UART_RevA_AsyncStop (mxc_uart_reva_regs_t* uart)
int MXC_UART_RevA_TxAsyncCallback(mxc_uart_reva_regs_t *uart, int retVal)
{
if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) {
return E_BAD_PARAM;
}
MXC_UART_DisableInt ((mxc_uart_regs_t*) uart, 0xFFFFFFFF);
AsyncRequests[MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart)] = NULL;
mxc_uart_reva_req_t *req =
(mxc_uart_reva_req_t *)TxAsyncRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)uart)];
if (req->callback != NULL) {
req->callback((mxc_uart_req_t *)req, retVal);
}
return E_NO_ERROR;
}
int MXC_UART_RevA_AbortAsync (mxc_uart_reva_regs_t* uart)
int MXC_UART_RevA_AsyncCallback(mxc_uart_reva_regs_t *uart, int retVal)
{
int retvalTx, retvalRx;
bool reqMatch;
// If the requests are identical, only call one callback
if (TxAsyncRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)uart)] ==
RxAsyncRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)uart)]) {
reqMatch = TRUE;
} else {
reqMatch = FALSE;
}
retvalTx = MXC_UART_RevA_TxAsyncCallback(uart, retVal);
if (!reqMatch) {
retvalRx = MXC_UART_RevA_RxAsyncCallback(uart, retVal);
} else {
retvalRx = E_NO_ERROR;
}
if (retvalTx != E_NO_ERROR) {
return retvalTx;
}
if (retvalRx != E_NO_ERROR) {
return retvalRx;
}
return E_NO_ERROR;
}
int MXC_UART_RevA_TxAsyncStop(mxc_uart_reva_regs_t *uart)
{
if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) {
return E_BAD_PARAM;
}
MXC_UART_AsyncCallback ((mxc_uart_regs_t*) uart, E_ABORT);
MXC_UART_AsyncStop ((mxc_uart_regs_t*) uart);
MXC_UART_DisableInt((mxc_uart_regs_t *)uart, MXC_F_UART_REVA_INT_EN_TX_FIFO_THRESH);
TxAsyncRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)uart)] = NULL;
return E_NO_ERROR;
}
int MXC_UART_RevA_RxAsyncStop(mxc_uart_reva_regs_t *uart)
{
if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) {
return E_BAD_PARAM;
}
MXC_UART_DisableInt((mxc_uart_regs_t *)uart,
(MXC_UART_REVA_ERRINT_EN | MXC_F_UART_REVA_INT_EN_RX_FIFO_THRESH));
RxAsyncRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)uart)] = NULL;
return E_NO_ERROR;
}
int MXC_UART_RevA_AsyncStop(mxc_uart_reva_regs_t *uart)
{
int uartNum;
if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) {
return E_BAD_PARAM;
}
uartNum = MXC_UART_GET_IDX((mxc_uart_regs_t *)uart);
mxc_uart_reva_req_t *req = (mxc_uart_reva_req_t *)TxAsyncRequests[uartNum];
if (req != NULL) {
MXC_UART_TxAsyncStop((mxc_uart_regs_t *)uart);
}
req = (mxc_uart_reva_req_t *)RxAsyncRequests[uartNum];
if (req != NULL) {
MXC_UART_RxAsyncStop((mxc_uart_regs_t *)uart);
}
return E_NO_ERROR;
}
int MXC_UART_RevA_TxAbortAsync(mxc_uart_reva_regs_t *uart)
{
int uartNum;
if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) {
return E_BAD_PARAM;
}
uartNum = MXC_UART_GET_IDX((mxc_uart_regs_t *)uart);
mxc_uart_reva_req_t *req = (mxc_uart_reva_req_t *)TxAsyncRequests[uartNum];
if (req != NULL) {
MXC_UART_TxAsyncCallback((mxc_uart_regs_t *)uart, E_ABORT);
MXC_UART_TxAsyncStop((mxc_uart_regs_t *)uart);
}
return E_NO_ERROR;
}
int MXC_UART_RevA_RxAbortAsync(mxc_uart_reva_regs_t *uart)
{
int uartNum;
if (MXC_UART_GET_IDX((mxc_uart_regs_t *)uart) < 0) {
return E_BAD_PARAM;
}
uartNum = MXC_UART_GET_IDX((mxc_uart_regs_t *)uart);
mxc_uart_reva_req_t *req = (mxc_uart_reva_req_t *)RxAsyncRequests[uartNum];
if (req != NULL) {
MXC_UART_RxAsyncCallback((mxc_uart_regs_t *)uart, E_ABORT);
MXC_UART_RxAsyncStop((mxc_uart_regs_t *)uart);
}
return E_NO_ERROR;
}
int MXC_UART_RevA_AbortAsync(mxc_uart_reva_regs_t *uart)
{
int retvalTx, retvalRx;
retvalTx = MXC_UART_RevA_TxAbortAsync(uart);
retvalRx = MXC_UART_RevA_RxAbortAsync(uart);
if (retvalTx != E_NO_ERROR) {
return retvalTx;
}
if (retvalRx != E_NO_ERROR) {
return retvalRx;
}
return E_NO_ERROR;
}
@ -1024,8 +1193,6 @@ int MXC_UART_RevA_AsyncHandler (mxc_uart_reva_regs_t* uart)
return E_BAD_PARAM;
}
req = (mxc_uart_reva_req_t*) AsyncRequests[uartNum];
flags = MXC_UART_GetFlags((mxc_uart_regs_t *)uart);
if (flags & MXC_UART_REVA_ERRINT_FL & uart->int_en) {
@ -1034,17 +1201,28 @@ int MXC_UART_RevA_AsyncHandler (mxc_uart_reva_regs_t* uart)
return E_INVALID;
}
if ( (flags & MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH) && (req->txLen)) {
req = (mxc_uart_reva_req_t *)TxAsyncRequests[uartNum];
if ((flags & MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH) && (req != NULL) && (req->txLen)) {
numToWrite = MXC_UART_GetTXFIFOAvailable((mxc_uart_regs_t *)(req->uart));
numToWrite = numToWrite > (req->txLen - req->txCnt) ? req->txLen - req->txCnt : numToWrite;
req->txCnt += MXC_UART_WriteTXFIFO ((mxc_uart_regs_t*)(req->uart), &req->txData[req->txCnt], numToWrite);
req->txCnt += MXC_UART_WriteTXFIFO((mxc_uart_regs_t *)(req->uart), &req->txData[req->txCnt],
numToWrite);
MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart), MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH);
}
if ( (flags & MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH) && (req->rxLen)) {
if (req->txCnt == req->txLen) {
MXC_UART_TxAsyncCallback((mxc_uart_regs_t *)uart, E_NO_ERROR);
MXC_UART_TxAsyncStop((mxc_uart_regs_t *)uart);
}
req = (mxc_uart_reva_req_t *)RxAsyncRequests[uartNum];
if ((flags & MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH) && (req != NULL) && (req->rxLen)) {
numToRead = MXC_UART_GetRXFIFOAvailable((mxc_uart_regs_t *)(req->uart));
numToRead = numToRead > (req->rxLen - req->rxCnt) ? req->rxLen - req->rxCnt : numToRead;
req->rxCnt += MXC_UART_ReadRXFIFO ((mxc_uart_regs_t*)(req->uart), &req->rxData[req->rxCnt], numToRead);
req->rxCnt += MXC_UART_ReadRXFIFO((mxc_uart_regs_t *)(req->uart), &req->rxData[req->rxCnt],
numToRead);
if ((req->rxLen - req->rxCnt) < MXC_UART_GetRXThreshold((mxc_uart_regs_t *)(req->uart))) {
MXC_UART_SetRXThreshold((mxc_uart_regs_t *)(req->uart), req->rxLen - req->rxCnt);
@ -1053,9 +1231,9 @@ int MXC_UART_RevA_AsyncHandler (mxc_uart_reva_regs_t* uart)
MXC_UART_ClearFlags((mxc_uart_regs_t *)(req->uart), MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH);
}
if ( (req->rxCnt == req->rxLen) && (req->txCnt == req->txLen)) {
MXC_UART_AsyncCallback ((mxc_uart_regs_t*) uart, E_NO_ERROR);
MXC_UART_AsyncStop ((mxc_uart_regs_t*) uart);
if (req->rxCnt == req->rxLen) {
MXC_UART_RxAsyncCallback((mxc_uart_regs_t *)uart, E_NO_ERROR);
MXC_UART_RxAsyncStop((mxc_uart_regs_t *)uart);
}
return E_NO_ERROR;

31
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.h
View File

@ -1,5 +1,5 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,10 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
******************************************************************************/
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_REVA_H_
#define LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_REVA_H_
#include "mxc_device.h"
#include "mxc_assert.h"
@ -58,7 +61,8 @@ int MXC_UART_RevA_GetFrequency (mxc_uart_reva_regs_t* uart);
int MXC_UART_RevA_SetDataSize(mxc_uart_reva_regs_t *uart, int dataSize);
int MXC_UART_RevA_SetStopBits(mxc_uart_reva_regs_t *uart, mxc_uart_stop_t stopBits);
int MXC_UART_RevA_SetParity(mxc_uart_reva_regs_t *uart, mxc_uart_parity_t parity);
int MXC_UART_RevA_SetFlowCtrl (mxc_uart_reva_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold);
int MXC_UART_RevA_SetFlowCtrl(mxc_uart_reva_regs_t *uart, mxc_uart_flow_t flowCtrl,
int rtsThreshold);
int MXC_UART_RevA_SetClockSource(mxc_uart_reva_regs_t *uart, int usePCLK);
int MXC_UART_RevA_SetNullModem(mxc_uart_reva_regs_t *uart, int nullModem);
int MXC_UART_RevA_SendBreak(mxc_uart_reva_regs_t *uart);
@ -70,13 +74,16 @@ int MXC_UART_RevA_Read (mxc_uart_reva_regs_t* uart, uint8_t* buffer, int* len);
int MXC_UART_RevA_Write(mxc_uart_reva_regs_t *uart, uint8_t *byte, int *len);
unsigned int MXC_UART_RevA_ReadRXFIFO(mxc_uart_reva_regs_t *uart, unsigned char *bytes,
unsigned int len);
int MXC_UART_RevA_ReadRXFIFODMA (mxc_uart_reva_regs_t* uart, mxc_dma_regs_t* dma, unsigned char* bytes,
unsigned int len, mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config);
int MXC_UART_RevA_ReadRXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma,
unsigned char *bytes, unsigned int len,
mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config);
unsigned int MXC_UART_RevA_GetRXFIFOAvailable(mxc_uart_reva_regs_t *uart);
unsigned int MXC_UART_RevA_WriteTXFIFO(mxc_uart_reva_regs_t *uart, unsigned char *bytes,
unsigned int len);
unsigned int MXC_UART_RevA_WriteTXFIFODMA (mxc_uart_reva_regs_t* uart, mxc_dma_regs_t* dma, unsigned char* bytes,
unsigned int len, mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config);
unsigned int MXC_UART_RevA_WriteTXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma,
unsigned char *bytes, unsigned int len,
mxc_uart_dma_complete_cb_t callback,
mxc_dma_config_t config);
unsigned int MXC_UART_RevA_GetTXFIFOAvailable(mxc_uart_reva_regs_t *uart);
int MXC_UART_RevA_ClearRXFIFO(mxc_uart_reva_regs_t *uart);
int MXC_UART_RevA_ClearTXFIFO(mxc_uart_reva_regs_t *uart);
@ -93,8 +100,16 @@ int MXC_UART_RevA_Busy(mxc_uart_reva_regs_t* uart);
int MXC_UART_RevA_Transaction(mxc_uart_reva_req_t *req);
int MXC_UART_RevA_TransactionAsync(mxc_uart_reva_req_t *req);
int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma);
int MXC_UART_RevA_TxAbortAsync(mxc_uart_reva_regs_t *uart);
int MXC_UART_RevA_RxAbortAsync(mxc_uart_reva_regs_t *uart);
int MXC_UART_RevA_AbortAsync(mxc_uart_reva_regs_t *uart);
int MXC_UART_RevA_AsyncHandler(mxc_uart_reva_regs_t *uart);
int MXC_UART_RevA_TxAsyncStop(mxc_uart_reva_regs_t *uart);
int MXC_UART_RevA_RxAsyncStop(mxc_uart_reva_regs_t *uart);
int MXC_UART_RevA_AsyncStop(mxc_uart_reva_regs_t *uart);
int MXC_UART_RevA_AsyncCallback(mxc_uart_reva_regs_t *uart, int retVal);
int MXC_UART_RevA_TxAsyncCallback(mxc_uart_reva_regs_t *uart, int retVal);
int MXC_UART_RevA_RxAsyncCallback(mxc_uart_reva_regs_t *uart, int retVal);
void MXC_UART_RevA_DMACallback(int ch, int error);
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_REVA_H_

7
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva_regs.h
View File

@ -3,8 +3,8 @@
* @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
/******************************************************************************
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -34,8 +34,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
******************************************************************************/
#ifndef _UART_REVA_REGS_H_
#define _UART_REVA_REGS_H_

4
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_common.c
View File

@ -1,5 +1,5 @@
/******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include "mxc_device.h"

10
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_me11.c
View File

@ -1,5 +1,5 @@
/******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -29,7 +29,7 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
******************************************************************************/
/* **** Includes **** */
#include "mxc_device.h"
@ -46,8 +46,7 @@ int MXC_WDT_Init (mxc_wdt_regs_t* wdt)
{
if (wdt == MXC_WDT0) {
return E_NO_ERROR;
}
else {
} else {
return E_BAD_PARAM;
}
@ -58,8 +57,7 @@ int MXC_WDT_Shutdown (mxc_wdt_regs_t* wdt)
{
if (wdt == MXC_WDT0) {
return E_NO_ERROR;
}
else {
} else {
return E_BAD_PARAM;
}

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