mirror of https://github.com/ARMmbed/mbed-os.git
Update MAX32660 peripheral drivers with final ones that use by SDK
Ahmet Polat
Sadik.Ozer
parent
d0ca14e4fe
commit
3f4b177128
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@ -1,10 +1,11 @@
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/**
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* @file dma_regs.h
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* @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
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* @note This file is @generated.
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*/
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/* ****************************************************************************
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* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
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/******************************************************************************
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* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@ -34,11 +35,10 @@
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*
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*
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*************************************************************************** */
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******************************************************************************/
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#ifndef _DMA_REGS_H_
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#define _DMA_REGS_H_
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#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_DMA_REGS_H_
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#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_DMA_REGS_H_
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/* **** Includes **** */
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#include <stdint.h>
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@ -46,11 +46,11 @@
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined (__ICCARM__)
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#pragma system_include
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#endif
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#if defined (__CC_ARM)
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#pragma anon_unions
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#endif
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@ -67,7 +67,9 @@ extern "C" {
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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@ -76,32 +78,28 @@ extern "C" {
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* @ingroup dma
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* @defgroup dma_registers DMA_Registers
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* @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
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* @details DMA Controller Fully programmable, chaining capable DMA channels.
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* @details DMA Controller Fully programmable, chaining capable DMA channels.
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*/
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/**
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* @ingroup dma_registers
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* Structure type to access the DMA Channel Registers.
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*/
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typedef struct {
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__IO uint32_t cfg; /**< <tt>\b 0x100:</tt> DMA CFG Register */
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__IO uint32_t stat; /**< <tt>\b 0x104:</tt> DMA STAT Register */
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__IO uint32_t src; /**< <tt>\b 0x108:</tt> DMA SRC Register */
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__IO uint32_t dst; /**< <tt>\b 0x10C:</tt> DMA DST Register */
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__IO uint32_t cnt; /**< <tt>\b 0x110:</tt> DMA CNT Register */
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__IO uint32_t src_rld; /**< <tt>\b 0x114:</tt> DMA SRC_RLD Register */
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__IO uint32_t dst_rld; /**< <tt>\b 0x118:</tt> DMA DST_RLD Register */
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__IO uint32_t cnt_rld; /**< <tt>\b 0x11C:</tt> DMA CNT_RLD Register */
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} mxc_dma_ch_regs_t;
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/**
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* @ingroup dma_registers
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* Structure type to access the DMA Registers.
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*/
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typedef struct {
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__IO uint32_t cfg; /**< <tt>\b 0x000:</tt> DMA CFG Register */
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__IO uint32_t stat; /**< <tt>\b 0x004:</tt> DMA STAT Register */
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__IO uint32_t src; /**< <tt>\b 0x008:</tt> DMA SRC Register */
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__IO uint32_t dst; /**< <tt>\b 0x00C:</tt> DMA DST Register */
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__IO uint32_t cnt; /**< <tt>\b 0x010:</tt> DMA CNT Register */
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__IO uint32_t src_rld; /**< <tt>\b 0x014:</tt> DMA SRC_RLD Register */
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__IO uint32_t dst_rld; /**< <tt>\b 0x018:</tt> DMA DST_RLD Register */
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__IO uint32_t cnt_rld; /**< <tt>\b 0x01C:</tt> DMA CNT_RLD Register */
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} mxc_dma_ch_regs_t;
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typedef struct {
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__IO uint32_t int_en; /**< <tt>\b 0x000:</tt> DMA INT_EN Register */
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__I uint32_t int_fl; /**< <tt>\b 0x004:</tt> DMA INT_FL Register */
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__I uint32_t rsv_0x8_0xff[62];
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__R uint32_t rsv_0x8_0xff[62];
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__IO mxc_dma_ch_regs_t ch[4]; /**< <tt>\b 0x100:</tt> DMA CH Register */
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} mxc_dma_regs_t;
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@ -109,20 +107,20 @@ typedef struct {
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/**
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* @ingroup dma_registers
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* @defgroup DMA_Register_Offsets Register Offsets
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* @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address.
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* @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address.
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* @{
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*/
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#define MXC_R_DMA_CFG ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
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#define MXC_R_DMA_STAT ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */
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#define MXC_R_DMA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */
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#define MXC_R_DMA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */
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#define MXC_R_DMA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */
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#define MXC_R_DMA_SRC_RLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */
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#define MXC_R_DMA_DST_RLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */
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#define MXC_R_DMA_CNT_RLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */
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#define MXC_R_DMA_INT_EN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */
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#define MXC_R_DMA_INT_FL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */
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#define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
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#define MXC_R_DMA_CFG ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */
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#define MXC_R_DMA_STAT ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */
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#define MXC_R_DMA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: <tt> 0x0008</tt> */
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#define MXC_R_DMA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: <tt> 0x000C</tt> */
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#define MXC_R_DMA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: <tt> 0x0010</tt> */
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#define MXC_R_DMA_SRC_RLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: <tt> 0x0014</tt> */
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#define MXC_R_DMA_DST_RLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: <tt> 0x0018</tt> */
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#define MXC_R_DMA_CNT_RLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: <tt> 0x001C</tt> */
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#define MXC_R_DMA_INT_EN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */
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#define MXC_R_DMA_INT_FL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */
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#define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
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/**@} end of group dma_registers */
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/**
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@ -131,12 +129,12 @@ typedef struct {
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* @brief DMA Control Register.
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* @{
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*/
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#define MXC_F_DMA_INT_EN_CHIEN_POS 0 /**< INT_EN_CHIEN Position */
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#define MXC_F_DMA_INT_EN_CHIEN ((uint32_t)(0xFUL << MXC_F_DMA_INT_EN_CHIEN_POS)) /**< INT_EN_CHIEN Mask */
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#define MXC_V_DMA_INT_EN_CHIEN_DIS ((uint32_t)0x0UL) /**< INT_EN_CHIEN_DIS Value */
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#define MXC_S_DMA_INT_EN_CHIEN_DIS (MXC_V_DMA_INT_EN_CHIEN_DIS << MXC_F_DMA_INT_EN_CHIEN_POS) /**< INT_EN_CHIEN_DIS Setting */
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#define MXC_V_DMA_INT_EN_CHIEN_EN ((uint32_t)0x1UL) /**< INT_EN_CHIEN_EN Value */
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#define MXC_S_DMA_INT_EN_CHIEN_EN (MXC_V_DMA_INT_EN_CHIEN_EN << MXC_F_DMA_INT_EN_CHIEN_POS) /**< INT_EN_CHIEN_EN Setting */
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#define MXC_F_DMA_INT_EN_CHIEN_POS 0 /**< INT_EN_CHIEN Position */
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#define MXC_F_DMA_INT_EN_CHIEN ((uint32_t)(0xFUL << MXC_F_DMA_INT_EN_CHIEN_POS)) /**< INT_EN_CHIEN Mask */
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#define MXC_V_DMA_INT_EN_CHIEN_DIS ((uint32_t)0x0UL) /**< INT_EN_CHIEN_DIS Value */
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#define MXC_S_DMA_INT_EN_CHIEN_DIS (MXC_V_DMA_INT_EN_CHIEN_DIS << MXC_F_DMA_INT_EN_CHIEN_POS) /**< INT_EN_CHIEN_DIS Setting */
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#define MXC_V_DMA_INT_EN_CHIEN_EN ((uint32_t)0x1UL) /**< INT_EN_CHIEN_EN Value */
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#define MXC_S_DMA_INT_EN_CHIEN_EN (MXC_V_DMA_INT_EN_CHIEN_EN << MXC_F_DMA_INT_EN_CHIEN_POS) /**< INT_EN_CHIEN_EN Setting */
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/**@} end of group DMA_INT_EN_Register */
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* @brief DMA Interrupt Register.
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* @{
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*/
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#define MXC_F_DMA_INT_FL_IPEND_POS 0 /**< INT_FL_IPEND Position */
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#define MXC_F_DMA_INT_FL_IPEND ((uint32_t)(0xFUL << MXC_F_DMA_INT_FL_IPEND_POS)) /**< INT_FL_IPEND Mask */
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#define MXC_V_DMA_INT_FL_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INT_FL_IPEND_INACTIVE Value */
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#define MXC_S_DMA_INT_FL_IPEND_INACTIVE (MXC_V_DMA_INT_FL_IPEND_INACTIVE << MXC_F_DMA_INT_FL_IPEND_POS) /**< INT_FL_IPEND_INACTIVE Setting */
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#define MXC_V_DMA_INT_FL_IPEND_PENDING ((uint32_t)0x1UL) /**< INT_FL_IPEND_PENDING Value */
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#define MXC_S_DMA_INT_FL_IPEND_PENDING (MXC_V_DMA_INT_FL_IPEND_PENDING << MXC_F_DMA_INT_FL_IPEND_POS) /**< INT_FL_IPEND_PENDING Setting */
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#define MXC_F_DMA_INT_FL_IPEND_POS 0 /**< INT_FL_IPEND Position */
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#define MXC_F_DMA_INT_FL_IPEND ((uint32_t)(0xFUL << MXC_F_DMA_INT_FL_IPEND_POS)) /**< INT_FL_IPEND Mask */
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#define MXC_V_DMA_INT_FL_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INT_FL_IPEND_INACTIVE Value */
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#define MXC_S_DMA_INT_FL_IPEND_INACTIVE (MXC_V_DMA_INT_FL_IPEND_INACTIVE << MXC_F_DMA_INT_FL_IPEND_POS) /**< INT_FL_IPEND_INACTIVE Setting */
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#define MXC_V_DMA_INT_FL_IPEND_PENDING ((uint32_t)0x1UL) /**< INT_FL_IPEND_PENDING Value */
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#define MXC_S_DMA_INT_FL_IPEND_PENDING (MXC_V_DMA_INT_FL_IPEND_PENDING << MXC_F_DMA_INT_FL_IPEND_POS) /**< INT_FL_IPEND_PENDING Setting */
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/**@} end of group DMA_INT_FL_Register */
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* @brief DMA Channel Configuration Register.
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* @{
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*/
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#define MXC_F_DMA_CFG_CHEN_POS 0 /**< CFG_CHEN Position */
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#define MXC_F_DMA_CFG_CHEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHEN_POS)) /**< CFG_CHEN Mask */
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#define MXC_F_DMA_CFG_CHEN_POS 0 /**< CFG_CHEN Position */
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#define MXC_F_DMA_CFG_CHEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHEN_POS)) /**< CFG_CHEN Mask */
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#define MXC_F_DMA_CFG_RLDEN_POS 1 /**< CFG_RLDEN Position */
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#define MXC_F_DMA_CFG_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_RLDEN_POS)) /**< CFG_RLDEN Mask */
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#define MXC_F_DMA_CFG_RLDEN_POS 1 /**< CFG_RLDEN Position */
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#define MXC_F_DMA_CFG_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_RLDEN_POS)) /**< CFG_RLDEN Mask */
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#define MXC_F_DMA_CFG_PRI_POS 2 /**< CFG_PRI Position */
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#define MXC_F_DMA_CFG_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PRI_POS)) /**< CFG_PRI Mask */
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#define MXC_V_DMA_CFG_PRI_HIGH ((uint32_t)0x0UL) /**< CFG_PRI_HIGH Value */
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#define MXC_S_DMA_CFG_PRI_HIGH (MXC_V_DMA_CFG_PRI_HIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_HIGH Setting */
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#define MXC_V_DMA_CFG_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CFG_PRI_MEDHIGH Value */
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#define MXC_S_DMA_CFG_PRI_MEDHIGH (MXC_V_DMA_CFG_PRI_MEDHIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDHIGH Setting */
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#define MXC_V_DMA_CFG_PRI_MEDLOW ((uint32_t)0x2UL) /**< CFG_PRI_MEDLOW Value */
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#define MXC_S_DMA_CFG_PRI_MEDLOW (MXC_V_DMA_CFG_PRI_MEDLOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDLOW Setting */
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#define MXC_V_DMA_CFG_PRI_LOW ((uint32_t)0x3UL) /**< CFG_PRI_LOW Value */
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#define MXC_S_DMA_CFG_PRI_LOW (MXC_V_DMA_CFG_PRI_LOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_LOW Setting */
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#define MXC_F_DMA_CFG_PRI_POS 2 /**< CFG_PRI Position */
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#define MXC_F_DMA_CFG_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PRI_POS)) /**< CFG_PRI Mask */
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#define MXC_V_DMA_CFG_PRI_HIGH ((uint32_t)0x0UL) /**< CFG_PRI_HIGH Value */
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#define MXC_S_DMA_CFG_PRI_HIGH (MXC_V_DMA_CFG_PRI_HIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_HIGH Setting */
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#define MXC_V_DMA_CFG_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CFG_PRI_MEDHIGH Value */
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#define MXC_S_DMA_CFG_PRI_MEDHIGH (MXC_V_DMA_CFG_PRI_MEDHIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDHIGH Setting */
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#define MXC_V_DMA_CFG_PRI_MEDLOW ((uint32_t)0x2UL) /**< CFG_PRI_MEDLOW Value */
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#define MXC_S_DMA_CFG_PRI_MEDLOW (MXC_V_DMA_CFG_PRI_MEDLOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDLOW Setting */
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#define MXC_V_DMA_CFG_PRI_LOW ((uint32_t)0x3UL) /**< CFG_PRI_LOW Value */
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#define MXC_S_DMA_CFG_PRI_LOW (MXC_V_DMA_CFG_PRI_LOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_LOW Setting */
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#define MXC_F_DMA_CFG_REQSEL_POS 4 /**< CFG_REQSEL Position */
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#define MXC_F_DMA_CFG_REQSEL ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS)) /**< CFG_REQSEL Mask */
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#define MXC_V_DMA_CFG_REQSEL_MEMTOMEM ((uint32_t)0x0UL) /**< CFG_REQSEL_MEMTOMEM Value */
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#define MXC_S_DMA_CFG_REQSEL_MEMTOMEM (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_MEMTOMEM Setting */
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#define MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0x1UL) /**< CFG_REQSEL_SPI0RX Value */
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#define MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0RX Setting */
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#define MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x2UL) /**< CFG_REQSEL_SPI1RX Value */
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#define MXC_S_DMA_CFG_REQSEL_SPI1RX (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1RX Setting */
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#define MXC_V_DMA_CFG_REQSEL_UART0RX ((uint32_t)0x4UL) /**< CFG_REQSEL_UART0RX Value */
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#define MXC_S_DMA_CFG_REQSEL_UART0RX (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0RX Setting */
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#define MXC_V_DMA_CFG_REQSEL_UART1RX ((uint32_t)0x5UL) /**< CFG_REQSEL_UART1RX Value */
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#define MXC_S_DMA_CFG_REQSEL_UART1RX (MXC_V_DMA_CFG_REQSEL_UART1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1RX Setting */
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#define MXC_V_DMA_CFG_REQSEL_I2C0RX ((uint32_t)0x7UL) /**< CFG_REQSEL_I2C0RX Value */
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#define MXC_S_DMA_CFG_REQSEL_I2C0RX (MXC_V_DMA_CFG_REQSEL_I2C0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0RX Setting */
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#define MXC_V_DMA_CFG_REQSEL_I2C1RX ((uint32_t)0x8UL) /**< CFG_REQSEL_I2C1RX Value */
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#define MXC_S_DMA_CFG_REQSEL_I2C1RX (MXC_V_DMA_CFG_REQSEL_I2C1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1RX Setting */
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#define MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x21UL) /**< CFG_REQSEL_SPI0TX Value */
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#define MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0TX Setting */
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#define MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x22UL) /**< CFG_REQSEL_SPI1TX Value */
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#define MXC_S_DMA_CFG_REQSEL_SPI1TX (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1TX Setting */
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#define MXC_V_DMA_CFG_REQSEL_UART0TX ((uint32_t)0x24UL) /**< CFG_REQSEL_UART0TX Value */
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#define MXC_S_DMA_CFG_REQSEL_UART0TX (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0TX Setting */
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#define MXC_V_DMA_CFG_REQSEL_UART1TX ((uint32_t)0x25UL) /**< CFG_REQSEL_UART1TX Value */
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#define MXC_S_DMA_CFG_REQSEL_UART1TX (MXC_V_DMA_CFG_REQSEL_UART1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1TX Setting */
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#define MXC_V_DMA_CFG_REQSEL_I2C0TX ((uint32_t)0x27UL) /**< CFG_REQSEL_I2C0TX Value */
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#define MXC_S_DMA_CFG_REQSEL_I2C0TX (MXC_V_DMA_CFG_REQSEL_I2C0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0TX Setting */
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#define MXC_V_DMA_CFG_REQSEL_I2C1TX ((uint32_t)0x28UL) /**< CFG_REQSEL_I2C1TX Value */
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#define MXC_S_DMA_CFG_REQSEL_I2C1TX (MXC_V_DMA_CFG_REQSEL_I2C1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1TX Setting */
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#define MXC_F_DMA_CFG_REQSEL_POS 4 /**< CFG_REQSEL Position */
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#define MXC_F_DMA_CFG_REQSEL ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS)) /**< CFG_REQSEL Mask */
|
||||
#define MXC_V_DMA_CFG_REQSEL_MEMTOMEM ((uint32_t)0x0UL) /**< CFG_REQSEL_MEMTOMEM Value */
|
||||
#define MXC_S_DMA_CFG_REQSEL_MEMTOMEM (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_MEMTOMEM Setting */
|
||||
#define MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0x1UL) /**< CFG_REQSEL_SPI0RX Value */
|
||||
#define MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0RX Setting */
|
||||
#define MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x2UL) /**< CFG_REQSEL_SPI1RX Value */
|
||||
#define MXC_S_DMA_CFG_REQSEL_SPI1RX (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1RX Setting */
|
||||
#define MXC_V_DMA_CFG_REQSEL_UART0RX ((uint32_t)0x4UL) /**< CFG_REQSEL_UART0RX Value */
|
||||
#define MXC_S_DMA_CFG_REQSEL_UART0RX (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0RX Setting */
|
||||
#define MXC_V_DMA_CFG_REQSEL_UART1RX ((uint32_t)0x5UL) /**< CFG_REQSEL_UART1RX Value */
|
||||
#define MXC_S_DMA_CFG_REQSEL_UART1RX (MXC_V_DMA_CFG_REQSEL_UART1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1RX Setting */
|
||||
#define MXC_V_DMA_CFG_REQSEL_I2C0RX ((uint32_t)0x7UL) /**< CFG_REQSEL_I2C0RX Value */
|
||||
#define MXC_S_DMA_CFG_REQSEL_I2C0RX (MXC_V_DMA_CFG_REQSEL_I2C0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0RX Setting */
|
||||
#define MXC_V_DMA_CFG_REQSEL_I2C1RX ((uint32_t)0x8UL) /**< CFG_REQSEL_I2C1RX Value */
|
||||
#define MXC_S_DMA_CFG_REQSEL_I2C1RX (MXC_V_DMA_CFG_REQSEL_I2C1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1RX Setting */
|
||||
#define MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x21UL) /**< CFG_REQSEL_SPI0TX Value */
|
||||
#define MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0TX Setting */
|
||||
#define MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x22UL) /**< CFG_REQSEL_SPI1TX Value */
|
||||
#define MXC_S_DMA_CFG_REQSEL_SPI1TX (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1TX Setting */
|
||||
#define MXC_V_DMA_CFG_REQSEL_UART0TX ((uint32_t)0x24UL) /**< CFG_REQSEL_UART0TX Value */
|
||||
#define MXC_S_DMA_CFG_REQSEL_UART0TX (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0TX Setting */
|
||||
#define MXC_V_DMA_CFG_REQSEL_UART1TX ((uint32_t)0x25UL) /**< CFG_REQSEL_UART1TX Value */
|
||||
#define MXC_S_DMA_CFG_REQSEL_UART1TX (MXC_V_DMA_CFG_REQSEL_UART1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1TX Setting */
|
||||
#define MXC_V_DMA_CFG_REQSEL_I2C0TX ((uint32_t)0x27UL) /**< CFG_REQSEL_I2C0TX Value */
|
||||
#define MXC_S_DMA_CFG_REQSEL_I2C0TX (MXC_V_DMA_CFG_REQSEL_I2C0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0TX Setting */
|
||||
#define MXC_V_DMA_CFG_REQSEL_I2C1TX ((uint32_t)0x28UL) /**< CFG_REQSEL_I2C1TX Value */
|
||||
#define MXC_S_DMA_CFG_REQSEL_I2C1TX (MXC_V_DMA_CFG_REQSEL_I2C1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1TX Setting */
|
||||
|
||||
#define MXC_F_DMA_CFG_REQWAIT_POS 10 /**< CFG_REQWAIT Position */
|
||||
#define MXC_F_DMA_CFG_REQWAIT ((uint32_t)(0x1UL << MXC_F_DMA_CFG_REQWAIT_POS)) /**< CFG_REQWAIT Mask */
|
||||
#define MXC_F_DMA_CFG_REQWAIT_POS 10 /**< CFG_REQWAIT Position */
|
||||
#define MXC_F_DMA_CFG_REQWAIT ((uint32_t)(0x1UL << MXC_F_DMA_CFG_REQWAIT_POS)) /**< CFG_REQWAIT Mask */
|
||||
|
||||
#define MXC_F_DMA_CFG_TOSEL_POS 11 /**< CFG_TOSEL Position */
|
||||
#define MXC_F_DMA_CFG_TOSEL ((uint32_t)(0x7UL << MXC_F_DMA_CFG_TOSEL_POS)) /**< CFG_TOSEL Mask */
|
||||
#define MXC_V_DMA_CFG_TOSEL_TO4 ((uint32_t)0x0UL) /**< CFG_TOSEL_TO4 Value */
|
||||
#define MXC_S_DMA_CFG_TOSEL_TO4 (MXC_V_DMA_CFG_TOSEL_TO4 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO4 Setting */
|
||||
#define MXC_V_DMA_CFG_TOSEL_TO8 ((uint32_t)0x1UL) /**< CFG_TOSEL_TO8 Value */
|
||||
#define MXC_S_DMA_CFG_TOSEL_TO8 (MXC_V_DMA_CFG_TOSEL_TO8 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO8 Setting */
|
||||
#define MXC_V_DMA_CFG_TOSEL_TO16 ((uint32_t)0x2UL) /**< CFG_TOSEL_TO16 Value */
|
||||
#define MXC_S_DMA_CFG_TOSEL_TO16 (MXC_V_DMA_CFG_TOSEL_TO16 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO16 Setting */
|
||||
#define MXC_V_DMA_CFG_TOSEL_TO32 ((uint32_t)0x3UL) /**< CFG_TOSEL_TO32 Value */
|
||||
#define MXC_S_DMA_CFG_TOSEL_TO32 (MXC_V_DMA_CFG_TOSEL_TO32 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO32 Setting */
|
||||
#define MXC_V_DMA_CFG_TOSEL_TO64 ((uint32_t)0x4UL) /**< CFG_TOSEL_TO64 Value */
|
||||
#define MXC_S_DMA_CFG_TOSEL_TO64 (MXC_V_DMA_CFG_TOSEL_TO64 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO64 Setting */
|
||||
#define MXC_V_DMA_CFG_TOSEL_TO128 ((uint32_t)0x5UL) /**< CFG_TOSEL_TO128 Value */
|
||||
#define MXC_S_DMA_CFG_TOSEL_TO128 (MXC_V_DMA_CFG_TOSEL_TO128 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO128 Setting */
|
||||
#define MXC_V_DMA_CFG_TOSEL_TO256 ((uint32_t)0x6UL) /**< CFG_TOSEL_TO256 Value */
|
||||
#define MXC_S_DMA_CFG_TOSEL_TO256 (MXC_V_DMA_CFG_TOSEL_TO256 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO256 Setting */
|
||||
#define MXC_V_DMA_CFG_TOSEL_TO512 ((uint32_t)0x7UL) /**< CFG_TOSEL_TO512 Value */
|
||||
#define MXC_S_DMA_CFG_TOSEL_TO512 (MXC_V_DMA_CFG_TOSEL_TO512 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO512 Setting */
|
||||
#define MXC_F_DMA_CFG_TOSEL_POS 11 /**< CFG_TOSEL Position */
|
||||
#define MXC_F_DMA_CFG_TOSEL ((uint32_t)(0x7UL << MXC_F_DMA_CFG_TOSEL_POS)) /**< CFG_TOSEL Mask */
|
||||
#define MXC_V_DMA_CFG_TOSEL_TO4 ((uint32_t)0x0UL) /**< CFG_TOSEL_TO4 Value */
|
||||
#define MXC_S_DMA_CFG_TOSEL_TO4 (MXC_V_DMA_CFG_TOSEL_TO4 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO4 Setting */
|
||||
#define MXC_V_DMA_CFG_TOSEL_TO8 ((uint32_t)0x1UL) /**< CFG_TOSEL_TO8 Value */
|
||||
#define MXC_S_DMA_CFG_TOSEL_TO8 (MXC_V_DMA_CFG_TOSEL_TO8 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO8 Setting */
|
||||
#define MXC_V_DMA_CFG_TOSEL_TO16 ((uint32_t)0x2UL) /**< CFG_TOSEL_TO16 Value */
|
||||
#define MXC_S_DMA_CFG_TOSEL_TO16 (MXC_V_DMA_CFG_TOSEL_TO16 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO16 Setting */
|
||||
#define MXC_V_DMA_CFG_TOSEL_TO32 ((uint32_t)0x3UL) /**< CFG_TOSEL_TO32 Value */
|
||||
#define MXC_S_DMA_CFG_TOSEL_TO32 (MXC_V_DMA_CFG_TOSEL_TO32 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO32 Setting */
|
||||
#define MXC_V_DMA_CFG_TOSEL_TO64 ((uint32_t)0x4UL) /**< CFG_TOSEL_TO64 Value */
|
||||
#define MXC_S_DMA_CFG_TOSEL_TO64 (MXC_V_DMA_CFG_TOSEL_TO64 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO64 Setting */
|
||||
#define MXC_V_DMA_CFG_TOSEL_TO128 ((uint32_t)0x5UL) /**< CFG_TOSEL_TO128 Value */
|
||||
#define MXC_S_DMA_CFG_TOSEL_TO128 (MXC_V_DMA_CFG_TOSEL_TO128 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO128 Setting */
|
||||
#define MXC_V_DMA_CFG_TOSEL_TO256 ((uint32_t)0x6UL) /**< CFG_TOSEL_TO256 Value */
|
||||
#define MXC_S_DMA_CFG_TOSEL_TO256 (MXC_V_DMA_CFG_TOSEL_TO256 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO256 Setting */
|
||||
#define MXC_V_DMA_CFG_TOSEL_TO512 ((uint32_t)0x7UL) /**< CFG_TOSEL_TO512 Value */
|
||||
#define MXC_S_DMA_CFG_TOSEL_TO512 (MXC_V_DMA_CFG_TOSEL_TO512 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO512 Setting */
|
||||
|
||||
#define MXC_F_DMA_CFG_PSSEL_POS 14 /**< CFG_PSSEL Position */
|
||||
#define MXC_F_DMA_CFG_PSSEL ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PSSEL_POS)) /**< CFG_PSSEL Mask */
|
||||
#define MXC_V_DMA_CFG_PSSEL_DIS ((uint32_t)0x0UL) /**< CFG_PSSEL_DIS Value */
|
||||
#define MXC_S_DMA_CFG_PSSEL_DIS (MXC_V_DMA_CFG_PSSEL_DIS << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIS Setting */
|
||||
#define MXC_V_DMA_CFG_PSSEL_DIV256 ((uint32_t)0x1UL) /**< CFG_PSSEL_DIV256 Value */
|
||||
#define MXC_S_DMA_CFG_PSSEL_DIV256 (MXC_V_DMA_CFG_PSSEL_DIV256 << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV256 Setting */
|
||||
#define MXC_V_DMA_CFG_PSSEL_DIV64K ((uint32_t)0x2UL) /**< CFG_PSSEL_DIV64K Value */
|
||||
#define MXC_S_DMA_CFG_PSSEL_DIV64K (MXC_V_DMA_CFG_PSSEL_DIV64K << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV64K Setting */
|
||||
#define MXC_V_DMA_CFG_PSSEL_DIV16M ((uint32_t)0x3UL) /**< CFG_PSSEL_DIV16M Value */
|
||||
#define MXC_S_DMA_CFG_PSSEL_DIV16M (MXC_V_DMA_CFG_PSSEL_DIV16M << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV16M Setting */
|
||||
#define MXC_F_DMA_CFG_PSSEL_POS 14 /**< CFG_PSSEL Position */
|
||||
#define MXC_F_DMA_CFG_PSSEL ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PSSEL_POS)) /**< CFG_PSSEL Mask */
|
||||
#define MXC_V_DMA_CFG_PSSEL_DIS ((uint32_t)0x0UL) /**< CFG_PSSEL_DIS Value */
|
||||
#define MXC_S_DMA_CFG_PSSEL_DIS (MXC_V_DMA_CFG_PSSEL_DIS << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIS Setting */
|
||||
#define MXC_V_DMA_CFG_PSSEL_DIV256 ((uint32_t)0x1UL) /**< CFG_PSSEL_DIV256 Value */
|
||||
#define MXC_S_DMA_CFG_PSSEL_DIV256 (MXC_V_DMA_CFG_PSSEL_DIV256 << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV256 Setting */
|
||||
#define MXC_V_DMA_CFG_PSSEL_DIV64K ((uint32_t)0x2UL) /**< CFG_PSSEL_DIV64K Value */
|
||||
#define MXC_S_DMA_CFG_PSSEL_DIV64K (MXC_V_DMA_CFG_PSSEL_DIV64K << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV64K Setting */
|
||||
#define MXC_V_DMA_CFG_PSSEL_DIV16M ((uint32_t)0x3UL) /**< CFG_PSSEL_DIV16M Value */
|
||||
#define MXC_S_DMA_CFG_PSSEL_DIV16M (MXC_V_DMA_CFG_PSSEL_DIV16M << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV16M Setting */
|
||||
|
||||
#define MXC_F_DMA_CFG_SRCWD_POS 16 /**< CFG_SRCWD Position */
|
||||
#define MXC_F_DMA_CFG_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_SRCWD_POS)) /**< CFG_SRCWD Mask */
|
||||
#define MXC_V_DMA_CFG_SRCWD_BYTE ((uint32_t)0x0UL) /**< CFG_SRCWD_BYTE Value */
|
||||
#define MXC_S_DMA_CFG_SRCWD_BYTE (MXC_V_DMA_CFG_SRCWD_BYTE << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_BYTE Setting */
|
||||
#define MXC_V_DMA_CFG_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_SRCWD_HALFWORD Value */
|
||||
#define MXC_S_DMA_CFG_SRCWD_HALFWORD (MXC_V_DMA_CFG_SRCWD_HALFWORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_HALFWORD Setting */
|
||||
#define MXC_V_DMA_CFG_SRCWD_WORD ((uint32_t)0x2UL) /**< CFG_SRCWD_WORD Value */
|
||||
#define MXC_S_DMA_CFG_SRCWD_WORD (MXC_V_DMA_CFG_SRCWD_WORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_WORD Setting */
|
||||
#define MXC_F_DMA_CFG_SRCWD_POS 16 /**< CFG_SRCWD Position */
|
||||
#define MXC_F_DMA_CFG_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_SRCWD_POS)) /**< CFG_SRCWD Mask */
|
||||
#define MXC_V_DMA_CFG_SRCWD_BYTE ((uint32_t)0x0UL) /**< CFG_SRCWD_BYTE Value */
|
||||
#define MXC_S_DMA_CFG_SRCWD_BYTE (MXC_V_DMA_CFG_SRCWD_BYTE << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_BYTE Setting */
|
||||
#define MXC_V_DMA_CFG_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_SRCWD_HALFWORD Value */
|
||||
#define MXC_S_DMA_CFG_SRCWD_HALFWORD (MXC_V_DMA_CFG_SRCWD_HALFWORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_HALFWORD Setting */
|
||||
#define MXC_V_DMA_CFG_SRCWD_WORD ((uint32_t)0x2UL) /**< CFG_SRCWD_WORD Value */
|
||||
#define MXC_S_DMA_CFG_SRCWD_WORD (MXC_V_DMA_CFG_SRCWD_WORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_WORD Setting */
|
||||
|
||||
#define MXC_F_DMA_CFG_SRCINC_POS 18 /**< CFG_SRCINC Position */
|
||||
#define MXC_F_DMA_CFG_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_SRCINC_POS)) /**< CFG_SRCINC Mask */
|
||||
#define MXC_F_DMA_CFG_SRCINC_POS 18 /**< CFG_SRCINC Position */
|
||||
#define MXC_F_DMA_CFG_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_SRCINC_POS)) /**< CFG_SRCINC Mask */
|
||||
|
||||
#define MXC_F_DMA_CFG_DSTWD_POS 20 /**< CFG_DSTWD Position */
|
||||
#define MXC_F_DMA_CFG_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_DSTWD_POS)) /**< CFG_DSTWD Mask */
|
||||
#define MXC_V_DMA_CFG_DSTWD_BYTE ((uint32_t)0x0UL) /**< CFG_DSTWD_BYTE Value */
|
||||
#define MXC_S_DMA_CFG_DSTWD_BYTE (MXC_V_DMA_CFG_DSTWD_BYTE << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_BYTE Setting */
|
||||
#define MXC_V_DMA_CFG_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_DSTWD_HALFWORD Value */
|
||||
#define MXC_S_DMA_CFG_DSTWD_HALFWORD (MXC_V_DMA_CFG_DSTWD_HALFWORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_HALFWORD Setting */
|
||||
#define MXC_V_DMA_CFG_DSTWD_WORD ((uint32_t)0x2UL) /**< CFG_DSTWD_WORD Value */
|
||||
#define MXC_S_DMA_CFG_DSTWD_WORD (MXC_V_DMA_CFG_DSTWD_WORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_WORD Setting */
|
||||
#define MXC_F_DMA_CFG_DSTWD_POS 20 /**< CFG_DSTWD Position */
|
||||
#define MXC_F_DMA_CFG_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_DSTWD_POS)) /**< CFG_DSTWD Mask */
|
||||
#define MXC_V_DMA_CFG_DSTWD_BYTE ((uint32_t)0x0UL) /**< CFG_DSTWD_BYTE Value */
|
||||
#define MXC_S_DMA_CFG_DSTWD_BYTE (MXC_V_DMA_CFG_DSTWD_BYTE << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_BYTE Setting */
|
||||
#define MXC_V_DMA_CFG_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_DSTWD_HALFWORD Value */
|
||||
#define MXC_S_DMA_CFG_DSTWD_HALFWORD (MXC_V_DMA_CFG_DSTWD_HALFWORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_HALFWORD Setting */
|
||||
#define MXC_V_DMA_CFG_DSTWD_WORD ((uint32_t)0x2UL) /**< CFG_DSTWD_WORD Value */
|
||||
#define MXC_S_DMA_CFG_DSTWD_WORD (MXC_V_DMA_CFG_DSTWD_WORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_WORD Setting */
|
||||
|
||||
#define MXC_F_DMA_CFG_DSTINC_POS 22 /**< CFG_DSTINC Position */
|
||||
#define MXC_F_DMA_CFG_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_DSTINC_POS)) /**< CFG_DSTINC Mask */
|
||||
#define MXC_F_DMA_CFG_DSTINC_POS 22 /**< CFG_DSTINC Position */
|
||||
#define MXC_F_DMA_CFG_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_DSTINC_POS)) /**< CFG_DSTINC Mask */
|
||||
|
||||
#define MXC_F_DMA_CFG_BRST_POS 24 /**< CFG_BRST Position */
|
||||
#define MXC_F_DMA_CFG_BRST ((uint32_t)(0x1FUL << MXC_F_DMA_CFG_BRST_POS)) /**< CFG_BRST Mask */
|
||||
#define MXC_F_DMA_CFG_BRST_POS 24 /**< CFG_BRST Position */
|
||||
#define MXC_F_DMA_CFG_BRST ((uint32_t)(0x1FUL << MXC_F_DMA_CFG_BRST_POS)) /**< CFG_BRST Mask */
|
||||
|
||||
#define MXC_F_DMA_CFG_CHDIEN_POS 30 /**< CFG_CHDIEN Position */
|
||||
#define MXC_F_DMA_CFG_CHDIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHDIEN_POS)) /**< CFG_CHDIEN Mask */
|
||||
#define MXC_F_DMA_CFG_CHDIEN_POS 30 /**< CFG_CHDIEN Position */
|
||||
#define MXC_F_DMA_CFG_CHDIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHDIEN_POS)) /**< CFG_CHDIEN Mask */
|
||||
|
||||
#define MXC_F_DMA_CFG_CTZIEN_POS 31 /**< CFG_CTZIEN Position */
|
||||
#define MXC_F_DMA_CFG_CTZIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CTZIEN_POS)) /**< CFG_CTZIEN Mask */
|
||||
#define MXC_F_DMA_CFG_CTZIEN_POS 31 /**< CFG_CTZIEN Position */
|
||||
#define MXC_F_DMA_CFG_CTZIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CTZIEN_POS)) /**< CFG_CTZIEN Mask */
|
||||
|
||||
/**@} end of group DMA_CFG_Register */
|
||||
|
||||
|
|
@ -281,23 +279,23 @@ typedef struct {
|
|||
* @brief DMA Channel Status Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_DMA_STAT_CH_ST_POS 0 /**< STAT_CH_ST Position */
|
||||
#define MXC_F_DMA_STAT_CH_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_CH_ST_POS)) /**< STAT_CH_ST Mask */
|
||||
#define MXC_F_DMA_STAT_CH_ST_POS 0 /**< STAT_CH_ST Position */
|
||||
#define MXC_F_DMA_STAT_CH_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_CH_ST_POS)) /**< STAT_CH_ST Mask */
|
||||
|
||||
#define MXC_F_DMA_STAT_IPEND_POS 1 /**< STAT_IPEND Position */
|
||||
#define MXC_F_DMA_STAT_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_STAT_IPEND_POS)) /**< STAT_IPEND Mask */
|
||||
#define MXC_F_DMA_STAT_IPEND_POS 1 /**< STAT_IPEND Position */
|
||||
#define MXC_F_DMA_STAT_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_STAT_IPEND_POS)) /**< STAT_IPEND Mask */
|
||||
|
||||
#define MXC_F_DMA_STAT_CTZ_ST_POS 2 /**< STAT_CTZ_ST Position */
|
||||
#define MXC_F_DMA_STAT_CTZ_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_CTZ_ST_POS)) /**< STAT_CTZ_ST Mask */
|
||||
#define MXC_F_DMA_STAT_CTZ_ST_POS 2 /**< STAT_CTZ_ST Position */
|
||||
#define MXC_F_DMA_STAT_CTZ_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_CTZ_ST_POS)) /**< STAT_CTZ_ST Mask */
|
||||
|
||||
#define MXC_F_DMA_STAT_RLD_ST_POS 3 /**< STAT_RLD_ST Position */
|
||||
#define MXC_F_DMA_STAT_RLD_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_RLD_ST_POS)) /**< STAT_RLD_ST Mask */
|
||||
#define MXC_F_DMA_STAT_RLD_ST_POS 3 /**< STAT_RLD_ST Position */
|
||||
#define MXC_F_DMA_STAT_RLD_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_RLD_ST_POS)) /**< STAT_RLD_ST Mask */
|
||||
|
||||
#define MXC_F_DMA_STAT_BUS_ERR_POS 4 /**< STAT_BUS_ERR Position */
|
||||
#define MXC_F_DMA_STAT_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_STAT_BUS_ERR_POS)) /**< STAT_BUS_ERR Mask */
|
||||
#define MXC_F_DMA_STAT_BUS_ERR_POS 4 /**< STAT_BUS_ERR Position */
|
||||
#define MXC_F_DMA_STAT_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_STAT_BUS_ERR_POS)) /**< STAT_BUS_ERR Mask */
|
||||
|
||||
#define MXC_F_DMA_STAT_TO_ST_POS 6 /**< STAT_TO_ST Position */
|
||||
#define MXC_F_DMA_STAT_TO_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_TO_ST_POS)) /**< STAT_TO_ST Mask */
|
||||
#define MXC_F_DMA_STAT_TO_ST_POS 6 /**< STAT_TO_ST Position */
|
||||
#define MXC_F_DMA_STAT_TO_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_TO_ST_POS)) /**< STAT_TO_ST Mask */
|
||||
|
||||
/**@} end of group DMA_STAT_Register */
|
||||
|
||||
|
|
@ -311,8 +309,8 @@ typedef struct {
|
|||
* register is reloaded with the contents of DMA_SRC_RLD.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_DMA_SRC_SRC_POS 0 /**< SRC_SRC Position */
|
||||
#define MXC_F_DMA_SRC_SRC ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_SRC_POS)) /**< SRC_SRC Mask */
|
||||
#define MXC_F_DMA_SRC_SRC_POS 0 /**< SRC_SRC Position */
|
||||
#define MXC_F_DMA_SRC_SRC ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_SRC_POS)) /**< SRC_SRC Mask */
|
||||
|
||||
/**@} end of group DMA_SRC_Register */
|
||||
|
||||
|
|
@ -326,8 +324,8 @@ typedef struct {
|
|||
* while RLDEN=1, the register is reloaded with DMA_DST_RLD.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_DMA_DST_DST_POS 0 /**< DST_DST Position */
|
||||
#define MXC_F_DMA_DST_DST ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_DST_POS)) /**< DST_DST Mask */
|
||||
#define MXC_F_DMA_DST_DST_POS 0 /**< DST_DST Position */
|
||||
#define MXC_F_DMA_DST_DST ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_DST_POS)) /**< DST_DST Mask */
|
||||
|
||||
/**@} end of group DMA_DST_Register */
|
||||
|
||||
|
|
@ -340,8 +338,8 @@ typedef struct {
|
|||
* reaches 0, a count-to-zero condition is triggered.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */
|
||||
#define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */
|
||||
#define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */
|
||||
#define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */
|
||||
|
||||
/**@} end of group DMA_CNT_Register */
|
||||
|
||||
|
|
@ -352,8 +350,8 @@ typedef struct {
|
|||
* upon a count-to-zero condition.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_DMA_SRC_RLD_SRC_RLD_POS 0 /**< SRC_RLD_SRC_RLD Position */
|
||||
#define MXC_F_DMA_SRC_RLD_SRC_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRC_RLD_SRC_RLD_POS)) /**< SRC_RLD_SRC_RLD Mask */
|
||||
#define MXC_F_DMA_SRC_RLD_SRC_RLD_POS 0 /**< SRC_RLD_SRC_RLD Position */
|
||||
#define MXC_F_DMA_SRC_RLD_SRC_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRC_RLD_SRC_RLD_POS)) /**< SRC_RLD_SRC_RLD Mask */
|
||||
|
||||
/**@} end of group DMA_SRC_RLD_Register */
|
||||
|
||||
|
|
@ -364,8 +362,8 @@ typedef struct {
|
|||
* DMA0_DST upon a count-to-zero condition.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_DMA_DST_RLD_DST_RLD_POS 0 /**< DST_RLD_DST_RLD Position */
|
||||
#define MXC_F_DMA_DST_RLD_DST_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DST_RLD_DST_RLD_POS)) /**< DST_RLD_DST_RLD Mask */
|
||||
#define MXC_F_DMA_DST_RLD_DST_RLD_POS 0 /**< DST_RLD_DST_RLD Position */
|
||||
#define MXC_F_DMA_DST_RLD_DST_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DST_RLD_DST_RLD_POS)) /**< DST_RLD_DST_RLD Mask */
|
||||
|
||||
/**@} end of group DMA_DST_RLD_Register */
|
||||
|
||||
|
|
@ -375,11 +373,11 @@ typedef struct {
|
|||
* @brief DMA Channel Count Reload Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_DMA_CNT_RLD_CNT_RLD_POS 0 /**< CNT_RLD_CNT_RLD Position */
|
||||
#define MXC_F_DMA_CNT_RLD_CNT_RLD ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_RLD_CNT_RLD_POS)) /**< CNT_RLD_CNT_RLD Mask */
|
||||
#define MXC_F_DMA_CNT_RLD_CNT_RLD_POS 0 /**< CNT_RLD_CNT_RLD Position */
|
||||
#define MXC_F_DMA_CNT_RLD_CNT_RLD ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_RLD_CNT_RLD_POS)) /**< CNT_RLD_CNT_RLD Mask */
|
||||
|
||||
#define MXC_F_DMA_CNT_RLD_RLDEN_POS 31 /**< CNT_RLD_RLDEN Position */
|
||||
#define MXC_F_DMA_CNT_RLD_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CNT_RLD_RLDEN_POS)) /**< CNT_RLD_RLDEN Mask */
|
||||
#define MXC_F_DMA_CNT_RLD_RLDEN_POS 31 /**< CNT_RLD_RLDEN Position */
|
||||
#define MXC_F_DMA_CNT_RLD_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CNT_RLD_RLDEN_POS)) /**< CNT_RLD_RLDEN Mask */
|
||||
|
||||
/**@} end of group DMA_CNT_RLD_Register */
|
||||
|
||||
|
|
@ -387,4 +385,4 @@ typedef struct {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DMA_REGS_H_ */
|
||||
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_DMA_REGS_H_
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
/**
|
||||
* @file fcr_regs.h
|
||||
* @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module.
|
||||
* @note This file is @generated.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +35,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _FCR_REGS_H_
|
||||
#define _FCR_REGS_H_
|
||||
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FCR_REGS_H_
|
||||
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FCR_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -46,11 +46,11 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__ICCARM__)
|
||||
#pragma system_include
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__CC_ARM)
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
|
@ -67,7 +67,9 @@ extern "C" {
|
|||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
|
||||
#ifndef __R
|
||||
#define __R volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
|
@ -76,7 +78,7 @@ extern "C" {
|
|||
* @ingroup fcr
|
||||
* @defgroup fcr_registers FCR_Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module.
|
||||
* @details Function Control.
|
||||
* @details Function Control.
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
@ -91,10 +93,10 @@ typedef struct {
|
|||
/**
|
||||
* @ingroup fcr_registers
|
||||
* @defgroup FCR_Register_Offsets Register Offsets
|
||||
* @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address.
|
||||
* @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_FCR_REG0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_FCR_REG0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: <tt> 0x0000</tt> */
|
||||
/**@} end of group fcr_registers */
|
||||
|
||||
/**
|
||||
|
|
@ -103,17 +105,17 @@ typedef struct {
|
|||
* @brief Register 0.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS 20 /**< REG0_I2C0_SDA_FILTER_EN Position */
|
||||
#define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS)) /**< REG0_I2C0_SDA_FILTER_EN Mask */
|
||||
#define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS 20 /**< REG0_I2C0_SDA_FILTER_EN Position */
|
||||
#define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS)) /**< REG0_I2C0_SDA_FILTER_EN Mask */
|
||||
|
||||
#define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS 21 /**< REG0_I2C0_SCL_FILTER_EN Position */
|
||||
#define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS)) /**< REG0_I2C0_SCL_FILTER_EN Mask */
|
||||
#define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS 21 /**< REG0_I2C0_SCL_FILTER_EN Position */
|
||||
#define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS)) /**< REG0_I2C0_SCL_FILTER_EN Mask */
|
||||
|
||||
#define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS 22 /**< REG0_I2C1_SDA_FILTER_EN Position */
|
||||
#define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS)) /**< REG0_I2C1_SDA_FILTER_EN Mask */
|
||||
#define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS 22 /**< REG0_I2C1_SDA_FILTER_EN Position */
|
||||
#define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS)) /**< REG0_I2C1_SDA_FILTER_EN Mask */
|
||||
|
||||
#define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS 23 /**< REG0_I2C1_SCL_FILTER_EN Position */
|
||||
#define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS)) /**< REG0_I2C1_SCL_FILTER_EN Mask */
|
||||
#define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS 23 /**< REG0_I2C1_SCL_FILTER_EN Position */
|
||||
#define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS)) /**< REG0_I2C1_SCL_FILTER_EN Mask */
|
||||
|
||||
/**@} end of group FCR_REG0_Register */
|
||||
|
||||
|
|
@ -121,4 +123,4 @@ typedef struct {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FCR_REGS_H_ */
|
||||
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FCR_REGS_H_
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
/**
|
||||
* @file flc_regs.h
|
||||
* @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
|
||||
* @note This file is @generated.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +35,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _FLC_REGS_H_
|
||||
#define _FLC_REGS_H_
|
||||
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FLC_REGS_H_
|
||||
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FLC_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -46,11 +46,11 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__ICCARM__)
|
||||
#pragma system_include
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__CC_ARM)
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
|
@ -67,7 +67,9 @@ extern "C" {
|
|||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
|
||||
#ifndef __R
|
||||
#define __R volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
|
@ -76,7 +78,7 @@ extern "C" {
|
|||
* @ingroup flc
|
||||
* @defgroup flc_registers FLC_Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
|
||||
* @details Flash Memory Control.
|
||||
* @details Flash Memory Control.
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
@ -87,9 +89,9 @@ typedef struct {
|
|||
__IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC ADDR Register */
|
||||
__IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC CLKDIV Register */
|
||||
__IO uint32_t ctrl; /**< <tt>\b 0x08:</tt> FLC CTRL Register */
|
||||
__I uint32_t rsv_0xc_0x23[6];
|
||||
__R uint32_t rsv_0xc_0x23[6];
|
||||
__IO uint32_t intr; /**< <tt>\b 0x024:</tt> FLC INTR Register */
|
||||
__I uint32_t rsv_0x28_0x2f[2];
|
||||
__R uint32_t rsv_0x28_0x2f[2];
|
||||
__IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC DATA Register */
|
||||
__O uint32_t actrl; /**< <tt>\b 0x40:</tt> FLC ACTRL Register */
|
||||
} mxc_flc_regs_t;
|
||||
|
|
@ -98,15 +100,15 @@ typedef struct {
|
|||
/**
|
||||
* @ingroup flc_registers
|
||||
* @defgroup FLC_Register_Offsets Register Offsets
|
||||
* @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address.
|
||||
* @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */
|
||||
#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */
|
||||
#define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0040</tt> */
|
||||
#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */
|
||||
#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */
|
||||
#define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0040</tt> */
|
||||
/**@} end of group flc_registers */
|
||||
|
||||
/**
|
||||
|
|
@ -115,8 +117,8 @@ typedef struct {
|
|||
* @brief Flash Write Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
|
||||
#define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
|
||||
#define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
|
||||
#define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
|
||||
|
||||
/**@} end of group FLC_ADDR_Register */
|
||||
|
||||
|
|
@ -127,8 +129,8 @@ typedef struct {
|
|||
* MHz clock for Flash controller.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
|
||||
#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
|
||||
#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
|
||||
#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
|
||||
|
||||
/**@} end of group FLC_CLKDIV_Register */
|
||||
|
||||
|
|
@ -138,39 +140,39 @@ typedef struct {
|
|||
* @brief Flash Control Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_CTRL_WRITE_POS 0 /**< CTRL_WRITE Position */
|
||||
#define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WRITE_POS)) /**< CTRL_WRITE Mask */
|
||||
#define MXC_F_FLC_CTRL_WRITE_POS 0 /**< CTRL_WRITE Position */
|
||||
#define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WRITE_POS)) /**< CTRL_WRITE Mask */
|
||||
|
||||
#define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 /**< CTRL_MASS_ERASE Position */
|
||||
#define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) /**< CTRL_MASS_ERASE Mask */
|
||||
#define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 /**< CTRL_MASS_ERASE Position */
|
||||
#define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) /**< CTRL_MASS_ERASE Mask */
|
||||
|
||||
#define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 /**< CTRL_PAGE_ERASE Position */
|
||||
#define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) /**< CTRL_PAGE_ERASE Mask */
|
||||
#define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 /**< CTRL_PAGE_ERASE Position */
|
||||
#define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) /**< CTRL_PAGE_ERASE Mask */
|
||||
|
||||
#define MXC_F_FLC_CTRL_WIDTH_POS 4 /**< CTRL_WIDTH Position */
|
||||
#define MXC_F_FLC_CTRL_WIDTH ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WIDTH_POS)) /**< CTRL_WIDTH Mask */
|
||||
#define MXC_F_FLC_CTRL_WIDTH_POS 4 /**< CTRL_WIDTH Position */
|
||||
#define MXC_F_FLC_CTRL_WIDTH ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WIDTH_POS)) /**< CTRL_WIDTH Mask */
|
||||
|
||||
#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */
|
||||
#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */
|
||||
#define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */
|
||||
#define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */
|
||||
#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */
|
||||
#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */
|
||||
#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */
|
||||
#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */
|
||||
#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */
|
||||
#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */
|
||||
#define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */
|
||||
#define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */
|
||||
#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */
|
||||
#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */
|
||||
#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */
|
||||
#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */
|
||||
|
||||
#define MXC_F_FLC_CTRL_BUSY_POS 24 /**< CTRL_BUSY Position */
|
||||
#define MXC_F_FLC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */
|
||||
#define MXC_F_FLC_CTRL_BUSY_POS 24 /**< CTRL_BUSY Position */
|
||||
#define MXC_F_FLC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */
|
||||
|
||||
#define MXC_F_FLC_CTRL_LVE_POS 25 /**< CTRL_LVE Position */
|
||||
#define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */
|
||||
#define MXC_F_FLC_CTRL_LVE_POS 25 /**< CTRL_LVE Position */
|
||||
#define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */
|
||||
|
||||
#define MXC_F_FLC_CTRL_UNLOCK_CODE_POS 28 /**< CTRL_UNLOCK_CODE Position */
|
||||
#define MXC_F_FLC_CTRL_UNLOCK_CODE ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_CODE_POS)) /**< CTRL_UNLOCK_CODE Mask */
|
||||
#define MXC_V_FLC_CTRL_UNLOCK_CODE_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_CODE_UNLOCKED Value */
|
||||
#define MXC_S_FLC_CTRL_UNLOCK_CODE_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_CODE_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_CODE_POS) /**< CTRL_UNLOCK_CODE_UNLOCKED Setting */
|
||||
#define MXC_V_FLC_CTRL_UNLOCK_CODE_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_CODE_LOCKED Value */
|
||||
#define MXC_S_FLC_CTRL_UNLOCK_CODE_LOCKED (MXC_V_FLC_CTRL_UNLOCK_CODE_LOCKED << MXC_F_FLC_CTRL_UNLOCK_CODE_POS) /**< CTRL_UNLOCK_CODE_LOCKED Setting */
|
||||
#define MXC_F_FLC_CTRL_UNLOCK_CODE_POS 28 /**< CTRL_UNLOCK_CODE Position */
|
||||
#define MXC_F_FLC_CTRL_UNLOCK_CODE ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_CODE_POS)) /**< CTRL_UNLOCK_CODE Mask */
|
||||
#define MXC_V_FLC_CTRL_UNLOCK_CODE_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_CODE_UNLOCKED Value */
|
||||
#define MXC_S_FLC_CTRL_UNLOCK_CODE_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_CODE_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_CODE_POS) /**< CTRL_UNLOCK_CODE_UNLOCKED Setting */
|
||||
#define MXC_V_FLC_CTRL_UNLOCK_CODE_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_CODE_LOCKED Value */
|
||||
#define MXC_S_FLC_CTRL_UNLOCK_CODE_LOCKED (MXC_V_FLC_CTRL_UNLOCK_CODE_LOCKED << MXC_F_FLC_CTRL_UNLOCK_CODE_POS) /**< CTRL_UNLOCK_CODE_LOCKED Setting */
|
||||
|
||||
/**@} end of group FLC_CTRL_Register */
|
||||
|
||||
|
|
@ -180,17 +182,17 @@ typedef struct {
|
|||
* @brief Flash Interrupt Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */
|
||||
#define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */
|
||||
#define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */
|
||||
#define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */
|
||||
|
||||
#define MXC_F_FLC_INTR_ACCESS_FAIL_POS 1 /**< INTR_ACCESS_FAIL Position */
|
||||
#define MXC_F_FLC_INTR_ACCESS_FAIL ((uint32_t)(0x1UL << MXC_F_FLC_INTR_ACCESS_FAIL_POS)) /**< INTR_ACCESS_FAIL Mask */
|
||||
#define MXC_F_FLC_INTR_ACCESS_FAIL_POS 1 /**< INTR_ACCESS_FAIL Position */
|
||||
#define MXC_F_FLC_INTR_ACCESS_FAIL ((uint32_t)(0x1UL << MXC_F_FLC_INTR_ACCESS_FAIL_POS)) /**< INTR_ACCESS_FAIL Mask */
|
||||
|
||||
#define MXC_F_FLC_INTR_DONE_IE_POS 8 /**< INTR_DONE_IE Position */
|
||||
#define MXC_F_FLC_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_IE_POS)) /**< INTR_DONE_IE Mask */
|
||||
#define MXC_F_FLC_INTR_DONE_IE_POS 8 /**< INTR_DONE_IE Position */
|
||||
#define MXC_F_FLC_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_IE_POS)) /**< INTR_DONE_IE Mask */
|
||||
|
||||
#define MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS 9 /**< INTR_ACCESS_FAIL_IE Position */
|
||||
#define MXC_F_FLC_INTR_ACCESS_FAIL_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS)) /**< INTR_ACCESS_FAIL_IE Mask */
|
||||
#define MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS 9 /**< INTR_ACCESS_FAIL_IE Position */
|
||||
#define MXC_F_FLC_INTR_ACCESS_FAIL_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS)) /**< INTR_ACCESS_FAIL_IE Mask */
|
||||
|
||||
/**@} end of group FLC_INTR_Register */
|
||||
|
||||
|
|
@ -200,8 +202,8 @@ typedef struct {
|
|||
* @brief Flash Write Data.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */
|
||||
#define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */
|
||||
#define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */
|
||||
#define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */
|
||||
|
||||
/**@} end of group FLC_DATA_Register */
|
||||
|
||||
|
|
@ -216,8 +218,8 @@ typedef struct {
|
|||
* this register is always zero.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */
|
||||
#define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */
|
||||
#define MXC_F_FLC_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */
|
||||
#define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */
|
||||
|
||||
/**@} end of group FLC_ACTRL_Register */
|
||||
|
||||
|
|
@ -225,4 +227,4 @@ typedef struct {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FLC_REGS_H_ */
|
||||
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FLC_REGS_H_
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
/**
|
||||
* @file gcr_regs.h
|
||||
* @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
|
||||
* @note This file is @generated.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +35,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _GCR_REGS_H_
|
||||
#define _GCR_REGS_H_
|
||||
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GCR_REGS_H_
|
||||
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GCR_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -46,11 +46,11 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__ICCARM__)
|
||||
#pragma system_include
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__CC_ARM)
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
|
@ -67,7 +67,9 @@ extern "C" {
|
|||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
|
||||
#ifndef __R
|
||||
#define __R volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
|
@ -76,7 +78,7 @@ extern "C" {
|
|||
* @ingroup gcr
|
||||
* @defgroup gcr_registers GCR_Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
|
||||
* @details Global Control Registers.
|
||||
* @details Global Control Registers.
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
@ -88,11 +90,11 @@ typedef struct {
|
|||
__IO uint32_t rst0; /**< <tt>\b 0x04:</tt> GCR RST0 Register */
|
||||
__IO uint32_t clk_ctrl; /**< <tt>\b 0x08:</tt> GCR CLK_CTRL Register */
|
||||
__IO uint32_t pm; /**< <tt>\b 0x0C:</tt> GCR PM Register */
|
||||
__I uint32_t rsv_0x10_0x23[5];
|
||||
__R uint32_t rsv_0x10_0x23[5];
|
||||
__IO uint32_t pclk_dis0; /**< <tt>\b 0x24:</tt> GCR PCLK_DIS0 Register */
|
||||
__IO uint32_t mem_ctrl; /**< <tt>\b 0x28:</tt> GCR MEM_CTRL Register */
|
||||
__IO uint32_t mem_zctrl; /**< <tt>\b 0x2C:</tt> GCR MEM_ZCTRL Register */
|
||||
__I uint32_t rsv_0x30_0x3f[4];
|
||||
__R uint32_t rsv_0x30_0x3f[4];
|
||||
__IO uint32_t sys_stat; /**< <tt>\b 0x40:</tt> GCR SYS_STAT Register */
|
||||
__IO uint32_t rst1; /**< <tt>\b 0x44:</tt> GCR RST1 Register */
|
||||
__IO uint32_t pclk_dis1; /**< <tt>\b 0x48:</tt> GCR PCLK_DIS1 Register */
|
||||
|
|
@ -105,22 +107,22 @@ typedef struct {
|
|||
/**
|
||||
* @ingroup gcr_registers
|
||||
* @defgroup GCR_Register_Offsets Register Offsets
|
||||
* @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address.
|
||||
* @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_GCR_SCON ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_GCR_CLK_CTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */
|
||||
#define MXC_R_GCR_PCLK_DIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */
|
||||
#define MXC_R_GCR_MEM_CTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */
|
||||
#define MXC_R_GCR_MEM_ZCTRL ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */
|
||||
#define MXC_R_GCR_SYS_STAT ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */
|
||||
#define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */
|
||||
#define MXC_R_GCR_PCLK_DIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */
|
||||
#define MXC_R_GCR_EVTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */
|
||||
#define MXC_R_GCR_REV ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */
|
||||
#define MXC_R_GCR_SYS_IE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */
|
||||
#define MXC_R_GCR_SCON ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_GCR_CLK_CTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */
|
||||
#define MXC_R_GCR_PCLK_DIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */
|
||||
#define MXC_R_GCR_MEM_CTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */
|
||||
#define MXC_R_GCR_MEM_ZCTRL ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */
|
||||
#define MXC_R_GCR_SYS_STAT ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */
|
||||
#define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */
|
||||
#define MXC_R_GCR_PCLK_DIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */
|
||||
#define MXC_R_GCR_EVTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */
|
||||
#define MXC_R_GCR_REV ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */
|
||||
#define MXC_R_GCR_SYS_IE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */
|
||||
/**@} end of group gcr_registers */
|
||||
|
||||
/**
|
||||
|
|
@ -129,17 +131,17 @@ typedef struct {
|
|||
* @brief System Control.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS 4 /**< SCON_FLASH_PAGE_FLIP Position */
|
||||
#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**< SCON_FLASH_PAGE_FLIP Mask */
|
||||
#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS 4 /**< SCON_FLASH_PAGE_FLIP Position */
|
||||
#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**< SCON_FLASH_PAGE_FLIP Mask */
|
||||
|
||||
#define MXC_F_GCR_SCON_FPU_DIS_POS 5 /**< SCON_FPU_DIS Position */
|
||||
#define MXC_F_GCR_SCON_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS Mask */
|
||||
#define MXC_F_GCR_SCON_FPU_DIS_POS 5 /**< SCON_FPU_DIS Position */
|
||||
#define MXC_F_GCR_SCON_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS Mask */
|
||||
|
||||
#define MXC_F_GCR_SCON_ICC0_FLUSH_POS 6 /**< SCON_ICC0_FLUSH Position */
|
||||
#define MXC_F_GCR_SCON_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_ICC0_FLUSH_POS)) /**< SCON_ICC0_FLUSH Mask */
|
||||
#define MXC_F_GCR_SCON_ICC0_FLUSH_POS 6 /**< SCON_ICC0_FLUSH Position */
|
||||
#define MXC_F_GCR_SCON_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_ICC0_FLUSH_POS)) /**< SCON_ICC0_FLUSH Mask */
|
||||
|
||||
#define MXC_F_GCR_SCON_SWD_DIS_POS 14 /**< SCON_SWD_DIS Position */
|
||||
#define MXC_F_GCR_SCON_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS Mask */
|
||||
#define MXC_F_GCR_SCON_SWD_DIS_POS 14 /**< SCON_SWD_DIS Position */
|
||||
#define MXC_F_GCR_SCON_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS Mask */
|
||||
|
||||
/**@} end of group GCR_SCON_Register */
|
||||
|
||||
|
|
@ -149,50 +151,50 @@ typedef struct {
|
|||
* @brief Reset.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */
|
||||
#define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */
|
||||
#define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */
|
||||
#define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */
|
||||
|
||||
#define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */
|
||||
#define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */
|
||||
#define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */
|
||||
#define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */
|
||||
|
||||
#define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */
|
||||
#define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */
|
||||
#define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */
|
||||
#define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */
|
||||
|
||||
#define MXC_F_GCR_RST0_TIMER0_POS 5 /**< RST0_TIMER0 Position */
|
||||
#define MXC_F_GCR_RST0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER0_POS)) /**< RST0_TIMER0 Mask */
|
||||
#define MXC_F_GCR_RST0_TIMER0_POS 5 /**< RST0_TIMER0 Position */
|
||||
#define MXC_F_GCR_RST0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER0_POS)) /**< RST0_TIMER0 Mask */
|
||||
|
||||
#define MXC_F_GCR_RST0_TIMER1_POS 6 /**< RST0_TIMER1 Position */
|
||||
#define MXC_F_GCR_RST0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER1_POS)) /**< RST0_TIMER1 Mask */
|
||||
#define MXC_F_GCR_RST0_TIMER1_POS 6 /**< RST0_TIMER1 Position */
|
||||
#define MXC_F_GCR_RST0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER1_POS)) /**< RST0_TIMER1 Mask */
|
||||
|
||||
#define MXC_F_GCR_RST0_TIMER2_POS 7 /**< RST0_TIMER2 Position */
|
||||
#define MXC_F_GCR_RST0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER2_POS)) /**< RST0_TIMER2 Mask */
|
||||
#define MXC_F_GCR_RST0_TIMER2_POS 7 /**< RST0_TIMER2 Position */
|
||||
#define MXC_F_GCR_RST0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER2_POS)) /**< RST0_TIMER2 Mask */
|
||||
|
||||
#define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */
|
||||
#define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */
|
||||
#define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */
|
||||
#define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */
|
||||
|
||||
#define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */
|
||||
#define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */
|
||||
#define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */
|
||||
#define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */
|
||||
|
||||
#define MXC_F_GCR_RST0_SPI0_POS 13 /**< RST0_SPI0 Position */
|
||||
#define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */
|
||||
#define MXC_F_GCR_RST0_SPI0_POS 13 /**< RST0_SPI0 Position */
|
||||
#define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */
|
||||
|
||||
#define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */
|
||||
#define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */
|
||||
#define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */
|
||||
#define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */
|
||||
|
||||
#define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */
|
||||
#define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */
|
||||
#define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */
|
||||
#define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */
|
||||
|
||||
#define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */
|
||||
#define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */
|
||||
#define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */
|
||||
#define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */
|
||||
|
||||
#define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */
|
||||
#define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */
|
||||
#define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */
|
||||
#define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */
|
||||
|
||||
#define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */
|
||||
#define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */
|
||||
#define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */
|
||||
#define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */
|
||||
|
||||
#define MXC_F_GCR_RST0_SYSTEM_POS 31 /**< RST0_SYSTEM Position */
|
||||
#define MXC_F_GCR_RST0_SYSTEM ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYSTEM_POS)) /**< RST0_SYSTEM Mask */
|
||||
#define MXC_F_GCR_RST0_SYSTEM_POS 31 /**< RST0_SYSTEM Position */
|
||||
#define MXC_F_GCR_RST0_SYSTEM ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYSTEM_POS)) /**< RST0_SYSTEM Mask */
|
||||
|
||||
/**@} end of group GCR_RST0_Register */
|
||||
|
||||
|
|
@ -202,51 +204,51 @@ typedef struct {
|
|||
* @brief Clock Control.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GCR_CLK_CTRL_PSC_POS 6 /**< CLK_CTRL_PSC Position */
|
||||
#define MXC_F_GCR_CLK_CTRL_PSC ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_PSC_POS)) /**< CLK_CTRL_PSC Mask */
|
||||
#define MXC_V_GCR_CLK_CTRL_PSC_DIV1 ((uint32_t)0x0UL) /**< CLK_CTRL_PSC_DIV1 Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_PSC_DIV1 (MXC_V_GCR_CLK_CTRL_PSC_DIV1 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV1 Setting */
|
||||
#define MXC_V_GCR_CLK_CTRL_PSC_DIV2 ((uint32_t)0x1UL) /**< CLK_CTRL_PSC_DIV2 Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_PSC_DIV2 (MXC_V_GCR_CLK_CTRL_PSC_DIV2 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV2 Setting */
|
||||
#define MXC_V_GCR_CLK_CTRL_PSC_DIV4 ((uint32_t)0x2UL) /**< CLK_CTRL_PSC_DIV4 Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_PSC_DIV4 (MXC_V_GCR_CLK_CTRL_PSC_DIV4 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV4 Setting */
|
||||
#define MXC_V_GCR_CLK_CTRL_PSC_DIV8 ((uint32_t)0x3UL) /**< CLK_CTRL_PSC_DIV8 Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_PSC_DIV8 (MXC_V_GCR_CLK_CTRL_PSC_DIV8 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV8 Setting */
|
||||
#define MXC_V_GCR_CLK_CTRL_PSC_DIV16 ((uint32_t)0x4UL) /**< CLK_CTRL_PSC_DIV16 Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_PSC_DIV16 (MXC_V_GCR_CLK_CTRL_PSC_DIV16 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV16 Setting */
|
||||
#define MXC_V_GCR_CLK_CTRL_PSC_DIV32 ((uint32_t)0x5UL) /**< CLK_CTRL_PSC_DIV32 Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_PSC_DIV32 (MXC_V_GCR_CLK_CTRL_PSC_DIV32 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV32 Setting */
|
||||
#define MXC_V_GCR_CLK_CTRL_PSC_DIV64 ((uint32_t)0x6UL) /**< CLK_CTRL_PSC_DIV64 Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_PSC_DIV64 (MXC_V_GCR_CLK_CTRL_PSC_DIV64 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV64 Setting */
|
||||
#define MXC_V_GCR_CLK_CTRL_PSC_DIV128 ((uint32_t)0x7UL) /**< CLK_CTRL_PSC_DIV128 Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_PSC_DIV128 (MXC_V_GCR_CLK_CTRL_PSC_DIV128 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV128 Setting */
|
||||
#define MXC_F_GCR_CLK_CTRL_PSC_POS 6 /**< CLK_CTRL_PSC Position */
|
||||
#define MXC_F_GCR_CLK_CTRL_PSC ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_PSC_POS)) /**< CLK_CTRL_PSC Mask */
|
||||
#define MXC_V_GCR_CLK_CTRL_PSC_DIV1 ((uint32_t)0x0UL) /**< CLK_CTRL_PSC_DIV1 Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_PSC_DIV1 (MXC_V_GCR_CLK_CTRL_PSC_DIV1 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV1 Setting */
|
||||
#define MXC_V_GCR_CLK_CTRL_PSC_DIV2 ((uint32_t)0x1UL) /**< CLK_CTRL_PSC_DIV2 Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_PSC_DIV2 (MXC_V_GCR_CLK_CTRL_PSC_DIV2 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV2 Setting */
|
||||
#define MXC_V_GCR_CLK_CTRL_PSC_DIV4 ((uint32_t)0x2UL) /**< CLK_CTRL_PSC_DIV4 Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_PSC_DIV4 (MXC_V_GCR_CLK_CTRL_PSC_DIV4 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV4 Setting */
|
||||
#define MXC_V_GCR_CLK_CTRL_PSC_DIV8 ((uint32_t)0x3UL) /**< CLK_CTRL_PSC_DIV8 Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_PSC_DIV8 (MXC_V_GCR_CLK_CTRL_PSC_DIV8 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV8 Setting */
|
||||
#define MXC_V_GCR_CLK_CTRL_PSC_DIV16 ((uint32_t)0x4UL) /**< CLK_CTRL_PSC_DIV16 Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_PSC_DIV16 (MXC_V_GCR_CLK_CTRL_PSC_DIV16 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV16 Setting */
|
||||
#define MXC_V_GCR_CLK_CTRL_PSC_DIV32 ((uint32_t)0x5UL) /**< CLK_CTRL_PSC_DIV32 Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_PSC_DIV32 (MXC_V_GCR_CLK_CTRL_PSC_DIV32 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV32 Setting */
|
||||
#define MXC_V_GCR_CLK_CTRL_PSC_DIV64 ((uint32_t)0x6UL) /**< CLK_CTRL_PSC_DIV64 Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_PSC_DIV64 (MXC_V_GCR_CLK_CTRL_PSC_DIV64 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV64 Setting */
|
||||
#define MXC_V_GCR_CLK_CTRL_PSC_DIV128 ((uint32_t)0x7UL) /**< CLK_CTRL_PSC_DIV128 Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_PSC_DIV128 (MXC_V_GCR_CLK_CTRL_PSC_DIV128 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV128 Setting */
|
||||
|
||||
#define MXC_F_GCR_CLK_CTRL_CLKSEL_POS 9 /**< CLK_CTRL_CLKSEL Position */
|
||||
#define MXC_F_GCR_CLK_CTRL_CLKSEL ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_CLKSEL_POS)) /**< CLK_CTRL_CLKSEL Mask */
|
||||
#define MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC ((uint32_t)0x0UL) /**< CLK_CTRL_CLKSEL_HIRC Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_CLKSEL_HIRC (MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) /**< CLK_CTRL_CLKSEL_HIRC Setting */
|
||||
#define MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING ((uint32_t)0x3UL) /**< CLK_CTRL_CLKSEL_NANORING Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING (MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) /**< CLK_CTRL_CLKSEL_NANORING Setting */
|
||||
#define MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN ((uint32_t)0x6UL) /**< CLK_CTRL_CLKSEL_HFXIN Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN (MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) /**< CLK_CTRL_CLKSEL_HFXIN Setting */
|
||||
#define MXC_F_GCR_CLK_CTRL_CLKSEL_POS 9 /**< CLK_CTRL_CLKSEL Position */
|
||||
#define MXC_F_GCR_CLK_CTRL_CLKSEL ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_CLKSEL_POS)) /**< CLK_CTRL_CLKSEL Mask */
|
||||
#define MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC ((uint32_t)0x0UL) /**< CLK_CTRL_CLKSEL_HIRC Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_CLKSEL_HIRC (MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) /**< CLK_CTRL_CLKSEL_HIRC Setting */
|
||||
#define MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING ((uint32_t)0x3UL) /**< CLK_CTRL_CLKSEL_NANORING Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING (MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) /**< CLK_CTRL_CLKSEL_NANORING Setting */
|
||||
#define MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN ((uint32_t)0x6UL) /**< CLK_CTRL_CLKSEL_HFXIN Value */
|
||||
#define MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN (MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) /**< CLK_CTRL_CLKSEL_HFXIN Setting */
|
||||
|
||||
#define MXC_F_GCR_CLK_CTRL_CLKRDY_POS 13 /**< CLK_CTRL_CLKRDY Position */
|
||||
#define MXC_F_GCR_CLK_CTRL_CLKRDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_CLKRDY_POS)) /**< CLK_CTRL_CLKRDY Mask */
|
||||
#define MXC_F_GCR_CLK_CTRL_CLKRDY_POS 13 /**< CLK_CTRL_CLKRDY Position */
|
||||
#define MXC_F_GCR_CLK_CTRL_CLKRDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_CLKRDY_POS)) /**< CLK_CTRL_CLKRDY Mask */
|
||||
|
||||
#define MXC_F_GCR_CLK_CTRL_X32K_EN_POS 17 /**< CLK_CTRL_X32K_EN Position */
|
||||
#define MXC_F_GCR_CLK_CTRL_X32K_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_EN_POS)) /**< CLK_CTRL_X32K_EN Mask */
|
||||
#define MXC_F_GCR_CLK_CTRL_X32K_EN_POS 17 /**< CLK_CTRL_X32K_EN Position */
|
||||
#define MXC_F_GCR_CLK_CTRL_X32K_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_EN_POS)) /**< CLK_CTRL_X32K_EN Mask */
|
||||
|
||||
#define MXC_F_GCR_CLK_CTRL_HIRC_EN_POS 18 /**< CLK_CTRL_HIRC_EN Position */
|
||||
#define MXC_F_GCR_CLK_CTRL_HIRC_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC_EN_POS)) /**< CLK_CTRL_HIRC_EN Mask */
|
||||
#define MXC_F_GCR_CLK_CTRL_HIRC_EN_POS 18 /**< CLK_CTRL_HIRC_EN Position */
|
||||
#define MXC_F_GCR_CLK_CTRL_HIRC_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC_EN_POS)) /**< CLK_CTRL_HIRC_EN Mask */
|
||||
|
||||
#define MXC_F_GCR_CLK_CTRL_X32K_RDY_POS 25 /**< CLK_CTRL_X32K_RDY Position */
|
||||
#define MXC_F_GCR_CLK_CTRL_X32K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_RDY_POS)) /**< CLK_CTRL_X32K_RDY Mask */
|
||||
#define MXC_F_GCR_CLK_CTRL_X32K_RDY_POS 25 /**< CLK_CTRL_X32K_RDY Position */
|
||||
#define MXC_F_GCR_CLK_CTRL_X32K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_RDY_POS)) /**< CLK_CTRL_X32K_RDY Mask */
|
||||
|
||||
#define MXC_F_GCR_CLK_CTRL_HIRC_RDY_POS 26 /**< CLK_CTRL_HIRC_RDY Position */
|
||||
#define MXC_F_GCR_CLK_CTRL_HIRC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC_RDY_POS)) /**< CLK_CTRL_HIRC_RDY Mask */
|
||||
#define MXC_F_GCR_CLK_CTRL_HIRC_RDY_POS 26 /**< CLK_CTRL_HIRC_RDY Position */
|
||||
#define MXC_F_GCR_CLK_CTRL_HIRC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC_RDY_POS)) /**< CLK_CTRL_HIRC_RDY Mask */
|
||||
|
||||
#define MXC_F_GCR_CLK_CTRL_LIRC8K_RDY_POS 29 /**< CLK_CTRL_LIRC8K_RDY Position */
|
||||
#define MXC_F_GCR_CLK_CTRL_LIRC8K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_LIRC8K_RDY_POS)) /**< CLK_CTRL_LIRC8K_RDY Mask */
|
||||
#define MXC_F_GCR_CLK_CTRL_LIRC8K_RDY_POS 29 /**< CLK_CTRL_LIRC8K_RDY Position */
|
||||
#define MXC_F_GCR_CLK_CTRL_LIRC8K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_LIRC8K_RDY_POS)) /**< CLK_CTRL_LIRC8K_RDY Mask */
|
||||
|
||||
/**@} end of group GCR_CLK_CTRL_Register */
|
||||
|
||||
|
|
@ -256,23 +258,23 @@ typedef struct {
|
|||
* @brief Power Management.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */
|
||||
#define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */
|
||||
#define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */
|
||||
#define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */
|
||||
#define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */
|
||||
#define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */
|
||||
#define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */
|
||||
#define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */
|
||||
#define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */
|
||||
#define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */
|
||||
#define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */
|
||||
#define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */
|
||||
#define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */
|
||||
#define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */
|
||||
#define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */
|
||||
#define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */
|
||||
|
||||
#define MXC_F_GCR_PM_GPIOWK_EN_POS 4 /**< PM_GPIOWK_EN Position */
|
||||
#define MXC_F_GCR_PM_GPIOWK_EN ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWK_EN_POS)) /**< PM_GPIOWK_EN Mask */
|
||||
#define MXC_F_GCR_PM_GPIOWK_EN_POS 4 /**< PM_GPIOWK_EN Position */
|
||||
#define MXC_F_GCR_PM_GPIOWK_EN ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWK_EN_POS)) /**< PM_GPIOWK_EN Mask */
|
||||
|
||||
#define MXC_F_GCR_PM_RTCWK_EN_POS 5 /**< PM_RTCWK_EN Position */
|
||||
#define MXC_F_GCR_PM_RTCWK_EN ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWK_EN_POS)) /**< PM_RTCWK_EN Mask */
|
||||
#define MXC_F_GCR_PM_RTCWK_EN_POS 5 /**< PM_RTCWK_EN Position */
|
||||
#define MXC_F_GCR_PM_RTCWK_EN ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWK_EN_POS)) /**< PM_RTCWK_EN Mask */
|
||||
|
||||
#define MXC_F_GCR_PM_HFIOPD_POS 15 /**< PM_HFIOPD Position */
|
||||
#define MXC_F_GCR_PM_HFIOPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HFIOPD_POS)) /**< PM_HFIOPD Mask */
|
||||
#define MXC_F_GCR_PM_HFIOPD_POS 15 /**< PM_HFIOPD Position */
|
||||
#define MXC_F_GCR_PM_HFIOPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HFIOPD_POS)) /**< PM_HFIOPD Mask */
|
||||
|
||||
/**@} end of group GCR_PM_Register */
|
||||
|
||||
|
|
@ -282,38 +284,38 @@ typedef struct {
|
|||
* @brief Peripheral Clock Disable.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GCR_PCLK_DIS0_GPIO0D_POS 0 /**< PCLK_DIS0_GPIO0D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_GPIO0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_GPIO0D_POS)) /**< PCLK_DIS0_GPIO0D Mask */
|
||||
#define MXC_F_GCR_PCLK_DIS0_GPIO0D_POS 0 /**< PCLK_DIS0_GPIO0D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_GPIO0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_GPIO0D_POS)) /**< PCLK_DIS0_GPIO0D Mask */
|
||||
|
||||
#define MXC_F_GCR_PCLK_DIS0_DMAD_POS 5 /**< PCLK_DIS0_DMAD Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_DMAD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_DMAD_POS)) /**< PCLK_DIS0_DMAD Mask */
|
||||
#define MXC_F_GCR_PCLK_DIS0_DMAD_POS 5 /**< PCLK_DIS0_DMAD Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_DMAD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_DMAD_POS)) /**< PCLK_DIS0_DMAD Mask */
|
||||
|
||||
#define MXC_F_GCR_PCLK_DIS0_SPI0D_POS 6 /**< PCLK_DIS0_SPI0D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_SPI0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI0D_POS)) /**< PCLK_DIS0_SPI0D Mask */
|
||||
#define MXC_F_GCR_PCLK_DIS0_SPI0D_POS 6 /**< PCLK_DIS0_SPI0D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_SPI0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI0D_POS)) /**< PCLK_DIS0_SPI0D Mask */
|
||||
|
||||
#define MXC_F_GCR_PCLK_DIS0_SPI1D_POS 7 /**< PCLK_DIS0_SPI1D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_SPI1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI1D_POS)) /**< PCLK_DIS0_SPI1D Mask */
|
||||
#define MXC_F_GCR_PCLK_DIS0_SPI1D_POS 7 /**< PCLK_DIS0_SPI1D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_SPI1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI1D_POS)) /**< PCLK_DIS0_SPI1D Mask */
|
||||
|
||||
#define MXC_F_GCR_PCLK_DIS0_UART0D_POS 9 /**< PCLK_DIS0_UART0D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_UART0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART0D_POS)) /**< PCLK_DIS0_UART0D Mask */
|
||||
#define MXC_F_GCR_PCLK_DIS0_UART0D_POS 9 /**< PCLK_DIS0_UART0D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_UART0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART0D_POS)) /**< PCLK_DIS0_UART0D Mask */
|
||||
|
||||
#define MXC_F_GCR_PCLK_DIS0_UART1D_POS 10 /**< PCLK_DIS0_UART1D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_UART1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART1D_POS)) /**< PCLK_DIS0_UART1D Mask */
|
||||
#define MXC_F_GCR_PCLK_DIS0_UART1D_POS 10 /**< PCLK_DIS0_UART1D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_UART1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART1D_POS)) /**< PCLK_DIS0_UART1D Mask */
|
||||
|
||||
#define MXC_F_GCR_PCLK_DIS0_I2C0D_POS 13 /**< PCLK_DIS0_I2C0D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_I2C0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C0D_POS)) /**< PCLK_DIS0_I2C0D Mask */
|
||||
#define MXC_F_GCR_PCLK_DIS0_I2C0D_POS 13 /**< PCLK_DIS0_I2C0D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_I2C0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C0D_POS)) /**< PCLK_DIS0_I2C0D Mask */
|
||||
|
||||
#define MXC_F_GCR_PCLK_DIS0_TIMER0D_POS 15 /**< PCLK_DIS0_TIMER0D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_TIMER0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER0D_POS)) /**< PCLK_DIS0_TIMER0D Mask */
|
||||
#define MXC_F_GCR_PCLK_DIS0_TIMER0D_POS 15 /**< PCLK_DIS0_TIMER0D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_TIMER0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER0D_POS)) /**< PCLK_DIS0_TIMER0D Mask */
|
||||
|
||||
#define MXC_F_GCR_PCLK_DIS0_TIMER1D_POS 16 /**< PCLK_DIS0_TIMER1D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_TIMER1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER1D_POS)) /**< PCLK_DIS0_TIMER1D Mask */
|
||||
#define MXC_F_GCR_PCLK_DIS0_TIMER1D_POS 16 /**< PCLK_DIS0_TIMER1D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_TIMER1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER1D_POS)) /**< PCLK_DIS0_TIMER1D Mask */
|
||||
|
||||
#define MXC_F_GCR_PCLK_DIS0_TIMER2D_POS 17 /**< PCLK_DIS0_TIMER2D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_TIMER2D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER2D_POS)) /**< PCLK_DIS0_TIMER2D Mask */
|
||||
#define MXC_F_GCR_PCLK_DIS0_TIMER2D_POS 17 /**< PCLK_DIS0_TIMER2D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_TIMER2D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER2D_POS)) /**< PCLK_DIS0_TIMER2D Mask */
|
||||
|
||||
#define MXC_F_GCR_PCLK_DIS0_I2C1D_POS 28 /**< PCLK_DIS0_I2C1D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_I2C1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C1D_POS)) /**< PCLK_DIS0_I2C1D Mask */
|
||||
#define MXC_F_GCR_PCLK_DIS0_I2C1D_POS 28 /**< PCLK_DIS0_I2C1D Position */
|
||||
#define MXC_F_GCR_PCLK_DIS0_I2C1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C1D_POS)) /**< PCLK_DIS0_I2C1D Mask */
|
||||
|
||||
/**@} end of group GCR_PCLK_DIS0_Register */
|
||||
|
||||
|
|
@ -323,23 +325,23 @@ typedef struct {
|
|||
* @brief Memory Clock Control Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GCR_MEM_CTRL_FWS_POS 0 /**< MEM_CTRL_FWS Position */
|
||||
#define MXC_F_GCR_MEM_CTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEM_CTRL_FWS_POS)) /**< MEM_CTRL_FWS Mask */
|
||||
#define MXC_F_GCR_MEM_CTRL_FWS_POS 0 /**< MEM_CTRL_FWS Position */
|
||||
#define MXC_F_GCR_MEM_CTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEM_CTRL_FWS_POS)) /**< MEM_CTRL_FWS Mask */
|
||||
|
||||
#define MXC_F_GCR_MEM_CTRL_RAM0_LS_POS 8 /**< MEM_CTRL_RAM0_LS Position */
|
||||
#define MXC_F_GCR_MEM_CTRL_RAM0_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM0_LS_POS)) /**< MEM_CTRL_RAM0_LS Mask */
|
||||
#define MXC_F_GCR_MEM_CTRL_RAM0_LS_POS 8 /**< MEM_CTRL_RAM0_LS Position */
|
||||
#define MXC_F_GCR_MEM_CTRL_RAM0_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM0_LS_POS)) /**< MEM_CTRL_RAM0_LS Mask */
|
||||
|
||||
#define MXC_F_GCR_MEM_CTRL_RAM1_LS_POS 9 /**< MEM_CTRL_RAM1_LS Position */
|
||||
#define MXC_F_GCR_MEM_CTRL_RAM1_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM1_LS_POS)) /**< MEM_CTRL_RAM1_LS Mask */
|
||||
#define MXC_F_GCR_MEM_CTRL_RAM1_LS_POS 9 /**< MEM_CTRL_RAM1_LS Position */
|
||||
#define MXC_F_GCR_MEM_CTRL_RAM1_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM1_LS_POS)) /**< MEM_CTRL_RAM1_LS Mask */
|
||||
|
||||
#define MXC_F_GCR_MEM_CTRL_RAM2_LS_POS 10 /**< MEM_CTRL_RAM2_LS Position */
|
||||
#define MXC_F_GCR_MEM_CTRL_RAM2_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM2_LS_POS)) /**< MEM_CTRL_RAM2_LS Mask */
|
||||
#define MXC_F_GCR_MEM_CTRL_RAM2_LS_POS 10 /**< MEM_CTRL_RAM2_LS Position */
|
||||
#define MXC_F_GCR_MEM_CTRL_RAM2_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM2_LS_POS)) /**< MEM_CTRL_RAM2_LS Mask */
|
||||
|
||||
#define MXC_F_GCR_MEM_CTRL_RAM3_LS_POS 11 /**< MEM_CTRL_RAM3_LS Position */
|
||||
#define MXC_F_GCR_MEM_CTRL_RAM3_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM3_LS_POS)) /**< MEM_CTRL_RAM3_LS Mask */
|
||||
#define MXC_F_GCR_MEM_CTRL_RAM3_LS_POS 11 /**< MEM_CTRL_RAM3_LS Position */
|
||||
#define MXC_F_GCR_MEM_CTRL_RAM3_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM3_LS_POS)) /**< MEM_CTRL_RAM3_LS Mask */
|
||||
|
||||
#define MXC_F_GCR_MEM_CTRL_ICACHE_RET_POS 12 /**< MEM_CTRL_ICACHE_RET Position */
|
||||
#define MXC_F_GCR_MEM_CTRL_ICACHE_RET ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_ICACHE_RET_POS)) /**< MEM_CTRL_ICACHE_RET Mask */
|
||||
#define MXC_F_GCR_MEM_CTRL_ICACHE_RET_POS 12 /**< MEM_CTRL_ICACHE_RET Position */
|
||||
#define MXC_F_GCR_MEM_CTRL_ICACHE_RET ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_ICACHE_RET_POS)) /**< MEM_CTRL_ICACHE_RET Mask */
|
||||
|
||||
/**@} end of group GCR_MEM_CTRL_Register */
|
||||
|
||||
|
|
@ -349,11 +351,11 @@ typedef struct {
|
|||
* @brief Memory Zeroize Control.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO_POS 0 /**< MEM_ZCTRL_SRAM_ZERO Position */
|
||||
#define MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO_POS)) /**< MEM_ZCTRL_SRAM_ZERO Mask */
|
||||
#define MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO_POS 0 /**< MEM_ZCTRL_SRAM_ZERO Position */
|
||||
#define MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO_POS)) /**< MEM_ZCTRL_SRAM_ZERO Mask */
|
||||
|
||||
#define MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO_POS 1 /**< MEM_ZCTRL_ICACHE_ZERO Position */
|
||||
#define MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO_POS)) /**< MEM_ZCTRL_ICACHE_ZERO Mask */
|
||||
#define MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO_POS 1 /**< MEM_ZCTRL_ICACHE_ZERO Position */
|
||||
#define MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO_POS)) /**< MEM_ZCTRL_ICACHE_ZERO Mask */
|
||||
|
||||
/**@} end of group GCR_MEM_ZCTRL_Register */
|
||||
|
||||
|
|
@ -363,8 +365,8 @@ typedef struct {
|
|||
* @brief System Status Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GCR_SYS_STAT_ICECLOCK_POS 0 /**< SYS_STAT_ICECLOCK Position */
|
||||
#define MXC_F_GCR_SYS_STAT_ICECLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_ICECLOCK_POS)) /**< SYS_STAT_ICECLOCK Mask */
|
||||
#define MXC_F_GCR_SYS_STAT_ICECLOCK_POS 0 /**< SYS_STAT_ICECLOCK Position */
|
||||
#define MXC_F_GCR_SYS_STAT_ICECLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_ICECLOCK_POS)) /**< SYS_STAT_ICECLOCK Mask */
|
||||
|
||||
/**@} end of group GCR_SYS_STAT_Register */
|
||||
|
||||
|
|
@ -374,8 +376,8 @@ typedef struct {
|
|||
* @brief Reset 1.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */
|
||||
#define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */
|
||||
#define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */
|
||||
#define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */
|
||||
|
||||
/**@} end of group GCR_RST1_Register */
|
||||
|
||||
|
|
@ -385,11 +387,11 @@ typedef struct {
|
|||
* @brief Peripheral Clock Disable.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GCR_PCLK_DIS1_FLCD_POS 3 /**< PCLK_DIS1_FLCD Position */
|
||||
#define MXC_F_GCR_PCLK_DIS1_FLCD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_FLCD_POS)) /**< PCLK_DIS1_FLCD Mask */
|
||||
#define MXC_F_GCR_PCLK_DIS1_FLCD_POS 3 /**< PCLK_DIS1_FLCD Position */
|
||||
#define MXC_F_GCR_PCLK_DIS1_FLCD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_FLCD_POS)) /**< PCLK_DIS1_FLCD Mask */
|
||||
|
||||
#define MXC_F_GCR_PCLK_DIS1_ICCD_POS 11 /**< PCLK_DIS1_ICCD Position */
|
||||
#define MXC_F_GCR_PCLK_DIS1_ICCD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_ICCD_POS)) /**< PCLK_DIS1_ICCD Mask */
|
||||
#define MXC_F_GCR_PCLK_DIS1_ICCD_POS 11 /**< PCLK_DIS1_ICCD Position */
|
||||
#define MXC_F_GCR_PCLK_DIS1_ICCD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_ICCD_POS)) /**< PCLK_DIS1_ICCD Mask */
|
||||
|
||||
/**@} end of group GCR_PCLK_DIS1_Register */
|
||||
|
||||
|
|
@ -399,11 +401,11 @@ typedef struct {
|
|||
* @brief Event Enable Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GCR_EVTEN_DMAEVENT_POS 0 /**< EVTEN_DMAEVENT Position */
|
||||
#define MXC_F_GCR_EVTEN_DMAEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**< EVTEN_DMAEVENT Mask */
|
||||
#define MXC_F_GCR_EVTEN_DMAEVENT_POS 0 /**< EVTEN_DMAEVENT Position */
|
||||
#define MXC_F_GCR_EVTEN_DMAEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**< EVTEN_DMAEVENT Mask */
|
||||
|
||||
#define MXC_F_GCR_EVTEN_RX_EVT_POS 1 /**< EVTEN_RX_EVT Position */
|
||||
#define MXC_F_GCR_EVTEN_RX_EVT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_RX_EVT_POS)) /**< EVTEN_RX_EVT Mask */
|
||||
#define MXC_F_GCR_EVTEN_RX_EVT_POS 1 /**< EVTEN_RX_EVT Position */
|
||||
#define MXC_F_GCR_EVTEN_RX_EVT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_RX_EVT_POS)) /**< EVTEN_RX_EVT Mask */
|
||||
|
||||
/**@} end of group GCR_EVTEN_Register */
|
||||
|
||||
|
|
@ -413,8 +415,8 @@ typedef struct {
|
|||
* @brief Revision Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GCR_REV_REVISION_POS 0 /**< REV_REVISION Position */
|
||||
#define MXC_F_GCR_REV_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REV_REVISION_POS)) /**< REV_REVISION Mask */
|
||||
#define MXC_F_GCR_REV_REVISION_POS 0 /**< REV_REVISION Position */
|
||||
#define MXC_F_GCR_REV_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REV_REVISION_POS)) /**< REV_REVISION Mask */
|
||||
|
||||
/**@} end of group GCR_REV_Register */
|
||||
|
||||
|
|
@ -424,8 +426,8 @@ typedef struct {
|
|||
* @brief System Status Interrupt Enable
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GCR_SYS_IE_ICEULIE_POS 0 /**< SYS_IE_ICEULIE Position */
|
||||
#define MXC_F_GCR_SYS_IE_ICEULIE ((uint32_t)(0x1UL << MXC_F_GCR_SYS_IE_ICEULIE_POS)) /**< SYS_IE_ICEULIE Mask */
|
||||
#define MXC_F_GCR_SYS_IE_ICEULIE_POS 0 /**< SYS_IE_ICEULIE Position */
|
||||
#define MXC_F_GCR_SYS_IE_ICEULIE ((uint32_t)(0x1UL << MXC_F_GCR_SYS_IE_ICEULIE_POS)) /**< SYS_IE_ICEULIE Mask */
|
||||
|
||||
/**@} end of group GCR_SYS_IE_Register */
|
||||
|
||||
|
|
@ -433,4 +435,4 @@ typedef struct {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _GCR_REGS_H_ */
|
||||
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GCR_REGS_H_
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
/**
|
||||
* @file gpio_regs.h
|
||||
* @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
|
||||
* @note This file is @generated.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +35,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _GPIO_REGS_H_
|
||||
#define _GPIO_REGS_H_
|
||||
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GPIO_REGS_H_
|
||||
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GPIO_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -46,11 +46,11 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__ICCARM__)
|
||||
#pragma system_include
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__CC_ARM)
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
|
@ -67,7 +67,9 @@ extern "C" {
|
|||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
|
||||
#ifndef __R
|
||||
#define __R volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
|
@ -76,7 +78,7 @@ extern "C" {
|
|||
* @ingroup gpio
|
||||
* @defgroup gpio_registers GPIO_Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
|
||||
* @details Individual I/O for each GPIO
|
||||
* @details Individual I/O for each GPIO
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
@ -100,13 +102,13 @@ typedef struct {
|
|||
__IO uint32_t int_en; /**< <tt>\b 0x34:</tt> GPIO INT_EN Register */
|
||||
__IO uint32_t int_en_set; /**< <tt>\b 0x38:</tt> GPIO INT_EN_SET Register */
|
||||
__IO uint32_t int_en_clr; /**< <tt>\b 0x3C:</tt> GPIO INT_EN_CLR Register */
|
||||
__IO uint32_t int_stat; /**< <tt>\b 0x40:</tt> GPIO INT_STAT Register */
|
||||
__I uint32_t rsv_0x44;
|
||||
__I uint32_t int_stat; /**< <tt>\b 0x40:</tt> GPIO INT_STAT Register */
|
||||
__R uint32_t rsv_0x44;
|
||||
__IO uint32_t int_clr; /**< <tt>\b 0x48:</tt> GPIO INT_CLR Register */
|
||||
__IO uint32_t wake_en; /**< <tt>\b 0x4C:</tt> GPIO WAKE_EN Register */
|
||||
__IO uint32_t wake_en_set; /**< <tt>\b 0x50:</tt> GPIO WAKE_EN_SET Register */
|
||||
__IO uint32_t wake_en_clr; /**< <tt>\b 0x54:</tt> GPIO WAKE_EN_CLR Register */
|
||||
__I uint32_t rsv_0x58;
|
||||
__R uint32_t rsv_0x58;
|
||||
__IO uint32_t int_dual_edge; /**< <tt>\b 0x5C:</tt> GPIO INT_DUAL_EDGE Register */
|
||||
__IO uint32_t pad_cfg1; /**< <tt>\b 0x60:</tt> GPIO PAD_CFG1 Register */
|
||||
__IO uint32_t pad_cfg2; /**< <tt>\b 0x64:</tt> GPIO PAD_CFG2 Register */
|
||||
|
|
@ -116,13 +118,13 @@ typedef struct {
|
|||
__IO uint32_t en2; /**< <tt>\b 0x74:</tt> GPIO EN2 Register */
|
||||
__IO uint32_t en2_set; /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */
|
||||
__IO uint32_t en2_clr; /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */
|
||||
__I uint32_t rsv_0x80_0xa7[10];
|
||||
__R uint32_t rsv_0x80_0xa7[10];
|
||||
__IO uint32_t is; /**< <tt>\b 0xA8:</tt> GPIO IS Register */
|
||||
__IO uint32_t sr; /**< <tt>\b 0xAC:</tt> GPIO SR Register */
|
||||
__IO uint32_t ds0; /**< <tt>\b 0xB0:</tt> GPIO DS0 Register */
|
||||
__IO uint32_t ds1; /**< <tt>\b 0xB4:</tt> GPIO DS1 Register */
|
||||
__IO uint32_t ps; /**< <tt>\b 0xB8:</tt> GPIO PS Register */
|
||||
__I uint32_t rsv_0xbc;
|
||||
__R uint32_t rsv_0xbc;
|
||||
__IO uint32_t vssel; /**< <tt>\b 0xC0:</tt> GPIO VSSEL Register */
|
||||
} mxc_gpio_regs_t;
|
||||
|
||||
|
|
@ -130,73 +132,73 @@ typedef struct {
|
|||
/**
|
||||
* @ingroup gpio_registers
|
||||
* @defgroup GPIO_Register_Offsets Register Offsets
|
||||
* @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address.
|
||||
* @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_GPIO_OUT_EN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> 0x000C</tt> */
|
||||
#define MXC_R_GPIO_OUT_EN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> 0x0010</tt> */
|
||||
#define MXC_R_GPIO_OUT_EN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> 0x0014</tt> */
|
||||
#define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> 0x0018</tt> */
|
||||
#define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> 0x001C</tt> */
|
||||
#define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> 0x0020</tt> */
|
||||
#define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */
|
||||
#define MXC_R_GPIO_INT_MOD ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */
|
||||
#define MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */
|
||||
#define MXC_R_GPIO_IN_EN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt> 0x0030</tt> */
|
||||
#define MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */
|
||||
#define MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */
|
||||
#define MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */
|
||||
#define MXC_R_GPIO_INT_STAT ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> 0x0040</tt> */
|
||||
#define MXC_R_GPIO_INT_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> 0x0048</tt> */
|
||||
#define MXC_R_GPIO_WAKE_EN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> 0x004C</tt> */
|
||||
#define MXC_R_GPIO_WAKE_EN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */
|
||||
#define MXC_R_GPIO_WAKE_EN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */
|
||||
#define MXC_R_GPIO_INT_DUAL_EDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */
|
||||
#define MXC_R_GPIO_PAD_CFG1 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */
|
||||
#define MXC_R_GPIO_PAD_CFG2 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */
|
||||
#define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */
|
||||
#define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */
|
||||
#define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */
|
||||
#define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> 0x0074</tt> */
|
||||
#define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> 0x0078</tt> */
|
||||
#define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> 0x007C</tt> */
|
||||
#define MXC_R_GPIO_IS ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> 0x00A8</tt> */
|
||||
#define MXC_R_GPIO_SR ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> 0x00AC</tt> */
|
||||
#define MXC_R_GPIO_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> 0x00B0</tt> */
|
||||
#define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> 0x00B4</tt> */
|
||||
#define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> 0x00B8</tt> */
|
||||
#define MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> 0x00C0</tt> */
|
||||
#define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_GPIO_OUT_EN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> 0x000C</tt> */
|
||||
#define MXC_R_GPIO_OUT_EN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> 0x0010</tt> */
|
||||
#define MXC_R_GPIO_OUT_EN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> 0x0014</tt> */
|
||||
#define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> 0x0018</tt> */
|
||||
#define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> 0x001C</tt> */
|
||||
#define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> 0x0020</tt> */
|
||||
#define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */
|
||||
#define MXC_R_GPIO_INT_MOD ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */
|
||||
#define MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */
|
||||
#define MXC_R_GPIO_IN_EN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt> 0x0030</tt> */
|
||||
#define MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */
|
||||
#define MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */
|
||||
#define MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */
|
||||
#define MXC_R_GPIO_INT_STAT ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> 0x0040</tt> */
|
||||
#define MXC_R_GPIO_INT_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> 0x0048</tt> */
|
||||
#define MXC_R_GPIO_WAKE_EN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> 0x004C</tt> */
|
||||
#define MXC_R_GPIO_WAKE_EN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */
|
||||
#define MXC_R_GPIO_WAKE_EN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */
|
||||
#define MXC_R_GPIO_INT_DUAL_EDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */
|
||||
#define MXC_R_GPIO_PAD_CFG1 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */
|
||||
#define MXC_R_GPIO_PAD_CFG2 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */
|
||||
#define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */
|
||||
#define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */
|
||||
#define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */
|
||||
#define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> 0x0074</tt> */
|
||||
#define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> 0x0078</tt> */
|
||||
#define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> 0x007C</tt> */
|
||||
#define MXC_R_GPIO_IS ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> 0x00A8</tt> */
|
||||
#define MXC_R_GPIO_SR ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> 0x00AC</tt> */
|
||||
#define MXC_R_GPIO_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> 0x00B0</tt> */
|
||||
#define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> 0x00B4</tt> */
|
||||
#define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> 0x00B8</tt> */
|
||||
#define MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> 0x00C0</tt> */
|
||||
/**@} end of group gpio_registers */
|
||||
|
||||
/**
|
||||
* @ingroup gpio_registers
|
||||
* @defgroup GPIO_EN0 GPIO_EN0
|
||||
* @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one
|
||||
* @brief GPIO Function Enable 0 Register. Each bit controls the GPIO_EN setting for one
|
||||
* GPIO pin on the associated port.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */
|
||||
#define MXC_F_GPIO_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */
|
||||
#define MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */
|
||||
#define MXC_S_GPIO_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */
|
||||
#define MXC_V_GPIO_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */
|
||||
#define MXC_S_GPIO_EN0_GPIO_EN_GPIO (MXC_V_GPIO_EN0_GPIO_EN_GPIO << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */
|
||||
#define MXC_F_GPIO_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */
|
||||
#define MXC_F_GPIO_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */
|
||||
#define MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */
|
||||
#define MXC_S_GPIO_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */
|
||||
#define MXC_V_GPIO_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */
|
||||
#define MXC_S_GPIO_EN0_GPIO_EN_GPIO (MXC_V_GPIO_EN0_GPIO_EN_GPIO << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */
|
||||
|
||||
/**@} end of group GPIO_EN0_Register */
|
||||
|
||||
/**
|
||||
* @ingroup gpio_registers
|
||||
* @defgroup GPIO_EN0_SET GPIO_EN0_SET
|
||||
* @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this
|
||||
* @brief GPIO Set Function Enable 0 Register. Writing a 1 to one or more bits in this
|
||||
* register sets the bits in the same positions in GPIO_EN to 1, without affecting
|
||||
* other bits in that register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */
|
||||
#define MXC_F_GPIO_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */
|
||||
#define MXC_F_GPIO_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */
|
||||
#define MXC_F_GPIO_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */
|
||||
|
||||
/**@} end of group GPIO_EN0_SET_Register */
|
||||
|
||||
|
|
@ -208,8 +210,8 @@ typedef struct {
|
|||
* affecting other bits in that register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */
|
||||
#define MXC_F_GPIO_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */
|
||||
#define MXC_F_GPIO_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */
|
||||
#define MXC_F_GPIO_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */
|
||||
|
||||
/**@} end of group GPIO_EN0_CLR_Register */
|
||||
|
||||
|
|
@ -220,12 +222,12 @@ typedef struct {
|
|||
* GPIO pin in the associated port.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS 0 /**< OUT_EN_GPIO_OUT_EN Position */
|
||||
#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN Mask */
|
||||
#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS ((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */
|
||||
#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS Setting */
|
||||
#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN ((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */
|
||||
#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN Setting */
|
||||
#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS 0 /**< OUT_EN_GPIO_OUT_EN Position */
|
||||
#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN Mask */
|
||||
#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS ((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */
|
||||
#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS Setting */
|
||||
#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN ((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */
|
||||
#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN Setting */
|
||||
|
||||
/**@} end of group GPIO_OUT_EN_Register */
|
||||
|
||||
|
|
@ -237,8 +239,8 @@ typedef struct {
|
|||
* without affecting other bits in that register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */
|
||||
#define MXC_F_GPIO_OUT_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */
|
||||
#define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */
|
||||
#define MXC_F_GPIO_OUT_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */
|
||||
|
||||
/**@} end of group GPIO_OUT_EN_SET_Register */
|
||||
|
||||
|
|
@ -250,8 +252,8 @@ typedef struct {
|
|||
* without affecting other bits in that register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */
|
||||
#define MXC_F_GPIO_OUT_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */
|
||||
#define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */
|
||||
#define MXC_F_GPIO_OUT_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */
|
||||
|
||||
/**@} end of group GPIO_OUT_EN_CLR_Register */
|
||||
|
||||
|
|
@ -263,12 +265,12 @@ typedef struct {
|
|||
* GPIO_OUT_SET and GPIO_OUT_CLR registers.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */
|
||||
#define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */
|
||||
#define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */
|
||||
#define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */
|
||||
#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */
|
||||
#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */
|
||||
#define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */
|
||||
#define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */
|
||||
#define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */
|
||||
#define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */
|
||||
#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */
|
||||
#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */
|
||||
|
||||
/**@} end of group GPIO_OUT_Register */
|
||||
|
||||
|
|
@ -280,12 +282,12 @@ typedef struct {
|
|||
* register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */
|
||||
#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */
|
||||
#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */
|
||||
#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */
|
||||
#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */
|
||||
#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */
|
||||
#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */
|
||||
#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */
|
||||
#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */
|
||||
#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */
|
||||
#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */
|
||||
#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */
|
||||
|
||||
/**@} end of group GPIO_OUT_SET_Register */
|
||||
|
||||
|
|
@ -297,8 +299,8 @@ typedef struct {
|
|||
* that register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */
|
||||
#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */
|
||||
#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */
|
||||
#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */
|
||||
|
||||
/**@} end of group GPIO_OUT_CLR_Register */
|
||||
|
||||
|
|
@ -309,8 +311,8 @@ typedef struct {
|
|||
* GPIO pins on this port.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */
|
||||
#define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */
|
||||
#define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */
|
||||
#define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */
|
||||
|
||||
/**@} end of group GPIO_IN_Register */
|
||||
|
||||
|
|
@ -321,12 +323,12 @@ typedef struct {
|
|||
* mode setting for the associated GPIO pin on this port.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS 0 /**< INT_MOD_GPIO_INT_MOD Position */
|
||||
#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< INT_MOD_GPIO_INT_MOD Mask */
|
||||
#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL ((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */
|
||||
#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_LEVEL Setting */
|
||||
#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE ((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */
|
||||
#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_EDGE Setting */
|
||||
#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS 0 /**< INT_MOD_GPIO_INT_MOD Position */
|
||||
#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< INT_MOD_GPIO_INT_MOD Mask */
|
||||
#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL ((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */
|
||||
#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_LEVEL Setting */
|
||||
#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE ((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */
|
||||
#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_EDGE Setting */
|
||||
|
||||
/**@} end of group GPIO_INT_MOD_Register */
|
||||
|
||||
|
|
@ -337,12 +339,12 @@ typedef struct {
|
|||
* interrupt polarity setting for one GPIO pin in the associated port.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS 0 /**< INT_POL_GPIO_INT_POL Position */
|
||||
#define MXC_F_GPIO_INT_POL_GPIO_INT_POL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< INT_POL_GPIO_INT_POL Mask */
|
||||
#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING ((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */
|
||||
#define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_FALLING Setting */
|
||||
#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING ((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */
|
||||
#define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_RISING Setting */
|
||||
#define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS 0 /**< INT_POL_GPIO_INT_POL Position */
|
||||
#define MXC_F_GPIO_INT_POL_GPIO_INT_POL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< INT_POL_GPIO_INT_POL Mask */
|
||||
#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING ((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */
|
||||
#define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_FALLING Setting */
|
||||
#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING ((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */
|
||||
#define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_RISING Setting */
|
||||
|
||||
/**@} end of group GPIO_INT_POL_Register */
|
||||
|
||||
|
|
@ -352,12 +354,12 @@ typedef struct {
|
|||
* @brief GPIO Port Input Enable.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS 0 /**< IN_EN_GPIO_IN_EN Position */
|
||||
#define MXC_F_GPIO_IN_EN_GPIO_IN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS)) /**< IN_EN_GPIO_IN_EN Mask */
|
||||
#define MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS ((uint32_t)0x0UL) /**< IN_EN_GPIO_IN_EN_DIS Value */
|
||||
#define MXC_S_GPIO_IN_EN_GPIO_IN_EN_DIS (MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) /**< IN_EN_GPIO_IN_EN_DIS Setting */
|
||||
#define MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN ((uint32_t)0x1UL) /**< IN_EN_GPIO_IN_EN_EN Value */
|
||||
#define MXC_S_GPIO_IN_EN_GPIO_IN_EN_EN (MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) /**< IN_EN_GPIO_IN_EN_EN Setting */
|
||||
#define MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS 0 /**< IN_EN_GPIO_IN_EN Position */
|
||||
#define MXC_F_GPIO_IN_EN_GPIO_IN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS)) /**< IN_EN_GPIO_IN_EN Mask */
|
||||
#define MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS ((uint32_t)0x0UL) /**< IN_EN_GPIO_IN_EN_DIS Value */
|
||||
#define MXC_S_GPIO_IN_EN_GPIO_IN_EN_DIS (MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) /**< IN_EN_GPIO_IN_EN_DIS Setting */
|
||||
#define MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN ((uint32_t)0x1UL) /**< IN_EN_GPIO_IN_EN_EN Value */
|
||||
#define MXC_S_GPIO_IN_EN_GPIO_IN_EN_EN (MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) /**< IN_EN_GPIO_IN_EN_EN Setting */
|
||||
|
||||
/**@} end of group GPIO_IN_EN_Register */
|
||||
|
||||
|
|
@ -368,12 +370,12 @@ typedef struct {
|
|||
* interrupt enable for the associated pin on the GPIO port.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS 0 /**< INT_EN_GPIO_INT_EN Position */
|
||||
#define MXC_F_GPIO_INT_EN_GPIO_INT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN Mask */
|
||||
#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS ((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */
|
||||
#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS Setting */
|
||||
#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN ((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */
|
||||
#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN Setting */
|
||||
#define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS 0 /**< INT_EN_GPIO_INT_EN Position */
|
||||
#define MXC_F_GPIO_INT_EN_GPIO_INT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN Mask */
|
||||
#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS ((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */
|
||||
#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS Setting */
|
||||
#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN ((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */
|
||||
#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN Setting */
|
||||
|
||||
/**@} end of group GPIO_INT_EN_Register */
|
||||
|
||||
|
|
@ -385,12 +387,12 @@ typedef struct {
|
|||
* in that register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS 0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */
|
||||
#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< INT_EN_SET_GPIO_INT_EN_SET Mask */
|
||||
#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO ((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */
|
||||
#define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Setting */
|
||||
#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET ((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */
|
||||
#define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Setting */
|
||||
#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS 0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */
|
||||
#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< INT_EN_SET_GPIO_INT_EN_SET Mask */
|
||||
#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO ((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */
|
||||
#define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Setting */
|
||||
#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET ((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */
|
||||
#define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Setting */
|
||||
|
||||
/**@} end of group GPIO_INT_EN_SET_Register */
|
||||
|
||||
|
|
@ -402,12 +404,12 @@ typedef struct {
|
|||
* other bits in that register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS 0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */
|
||||
#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< INT_EN_CLR_GPIO_INT_EN_CLR Mask */
|
||||
#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO ((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */
|
||||
#define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Setting */
|
||||
#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR ((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */
|
||||
#define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Setting */
|
||||
#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS 0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */
|
||||
#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< INT_EN_CLR_GPIO_INT_EN_CLR Mask */
|
||||
#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO ((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */
|
||||
#define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Setting */
|
||||
#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR ((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */
|
||||
#define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Setting */
|
||||
|
||||
/**@} end of group GPIO_INT_EN_CLR_Register */
|
||||
|
||||
|
|
@ -418,12 +420,12 @@ typedef struct {
|
|||
* interrupt status for the associated GPIO pin in this port.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS 0 /**< INT_STAT_GPIO_INT_STAT Position */
|
||||
#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< INT_STAT_GPIO_INT_STAT Mask */
|
||||
#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO ((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */
|
||||
#define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_NO Setting */
|
||||
#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING ((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */
|
||||
#define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_PENDING Setting */
|
||||
#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS 0 /**< INT_STAT_GPIO_INT_STAT Position */
|
||||
#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< INT_STAT_GPIO_INT_STAT Mask */
|
||||
#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO ((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */
|
||||
#define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_NO Setting */
|
||||
#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING ((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */
|
||||
#define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_PENDING Setting */
|
||||
|
||||
/**@} end of group GPIO_INT_STAT_Register */
|
||||
|
||||
|
|
@ -435,8 +437,8 @@ typedef struct {
|
|||
* in that register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */
|
||||
#define MXC_F_GPIO_INT_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */
|
||||
#define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */
|
||||
#define MXC_F_GPIO_INT_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */
|
||||
|
||||
/**@} end of group GPIO_INT_CLR_Register */
|
||||
|
||||
|
|
@ -447,12 +449,12 @@ typedef struct {
|
|||
* enable for the associated GPIO pin in this port.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS 0 /**< WAKE_EN_GPIO_WAKE_EN Position */
|
||||
#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< WAKE_EN_GPIO_WAKE_EN Mask */
|
||||
#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS ((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */
|
||||
#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS Setting */
|
||||
#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN ((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */
|
||||
#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN Setting */
|
||||
#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS 0 /**< WAKE_EN_GPIO_WAKE_EN Position */
|
||||
#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< WAKE_EN_GPIO_WAKE_EN Mask */
|
||||
#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS ((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */
|
||||
#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS Setting */
|
||||
#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN ((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */
|
||||
#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN Setting */
|
||||
|
||||
/**@} end of group GPIO_WAKE_EN_Register */
|
||||
|
||||
|
|
@ -464,8 +466,8 @@ typedef struct {
|
|||
* that register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */
|
||||
#define MXC_F_GPIO_WAKE_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL Mask */
|
||||
#define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */
|
||||
#define MXC_F_GPIO_WAKE_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL Mask */
|
||||
|
||||
/**@} end of group GPIO_WAKE_EN_SET_Register */
|
||||
|
||||
|
|
@ -477,8 +479,8 @@ typedef struct {
|
|||
* bits in that register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */
|
||||
#define MXC_F_GPIO_WAKE_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL Mask */
|
||||
#define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */
|
||||
#define MXC_F_GPIO_WAKE_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL Mask */
|
||||
|
||||
/**@} end of group GPIO_WAKE_EN_CLR_Register */
|
||||
|
||||
|
|
@ -489,12 +491,12 @@ typedef struct {
|
|||
* edge mode for the associated GPIO pin in this port.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS 0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */
|
||||
#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Mask */
|
||||
#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO ((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */
|
||||
#define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Setting */
|
||||
#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN ((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */
|
||||
#define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Setting */
|
||||
#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS 0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */
|
||||
#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Mask */
|
||||
#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO ((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */
|
||||
#define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Setting */
|
||||
#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN ((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */
|
||||
#define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Setting */
|
||||
|
||||
/**@} end of group GPIO_INT_DUAL_EDGE_Register */
|
||||
|
||||
|
|
@ -505,14 +507,14 @@ typedef struct {
|
|||
* the associated GPIO pin in this port.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS 0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */
|
||||
#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< PAD_CFG1_GPIO_PAD_CFG1 Mask */
|
||||
#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */
|
||||
#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Setting */
|
||||
#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU ((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */
|
||||
#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Setting */
|
||||
#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD ((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */
|
||||
#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Setting */
|
||||
#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS 0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */
|
||||
#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< PAD_CFG1_GPIO_PAD_CFG1 Mask */
|
||||
#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */
|
||||
#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Setting */
|
||||
#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU ((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */
|
||||
#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Setting */
|
||||
#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD ((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */
|
||||
#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Setting */
|
||||
|
||||
/**@} end of group GPIO_PAD_CFG1_Register */
|
||||
|
||||
|
|
@ -523,14 +525,14 @@ typedef struct {
|
|||
* the associated GPIO pin in this port.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS 0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */
|
||||
#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< PAD_CFG2_GPIO_PAD_CFG2 Mask */
|
||||
#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */
|
||||
#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Setting */
|
||||
#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU ((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */
|
||||
#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Setting */
|
||||
#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD ((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */
|
||||
#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Setting */
|
||||
#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS 0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */
|
||||
#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< PAD_CFG2_GPIO_PAD_CFG2 Mask */
|
||||
#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */
|
||||
#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Setting */
|
||||
#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU ((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */
|
||||
#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Setting */
|
||||
#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD ((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */
|
||||
#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Setting */
|
||||
|
||||
/**@} end of group GPIO_PAD_CFG2_Register */
|
||||
|
||||
|
|
@ -541,12 +543,12 @@ typedef struct {
|
|||
* between primary/secondary functions for the associated GPIO pin in this port.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */
|
||||
#define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */
|
||||
#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */
|
||||
#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */
|
||||
#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */
|
||||
#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */
|
||||
#define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */
|
||||
#define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */
|
||||
#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */
|
||||
#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */
|
||||
#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */
|
||||
#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */
|
||||
|
||||
/**@} end of group GPIO_EN1_Register */
|
||||
|
||||
|
|
@ -558,8 +560,8 @@ typedef struct {
|
|||
* bits in that register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */
|
||||
#define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */
|
||||
#define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */
|
||||
#define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */
|
||||
|
||||
/**@} end of group GPIO_EN1_SET_Register */
|
||||
|
||||
|
|
@ -571,8 +573,8 @@ typedef struct {
|
|||
* bits in that register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */
|
||||
#define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */
|
||||
#define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */
|
||||
#define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */
|
||||
|
||||
/**@} end of group GPIO_EN1_CLR_Register */
|
||||
|
||||
|
|
@ -583,12 +585,12 @@ typedef struct {
|
|||
* between primary/secondary functions for the associated GPIO pin in this port.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */
|
||||
#define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */
|
||||
#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */
|
||||
#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */
|
||||
#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */
|
||||
#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */
|
||||
#define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */
|
||||
#define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */
|
||||
#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */
|
||||
#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */
|
||||
#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */
|
||||
#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */
|
||||
|
||||
/**@} end of group GPIO_EN2_Register */
|
||||
|
||||
|
|
@ -600,8 +602,8 @@ typedef struct {
|
|||
* bits in that register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */
|
||||
#define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */
|
||||
#define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */
|
||||
#define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */
|
||||
|
||||
/**@} end of group GPIO_EN2_SET_Register */
|
||||
|
||||
|
|
@ -613,11 +615,37 @@ typedef struct {
|
|||
* affecting other bits in that register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */
|
||||
#define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */
|
||||
#define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */
|
||||
#define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */
|
||||
|
||||
/**@} end of group GPIO_EN2_CLR_Register */
|
||||
|
||||
/**
|
||||
* @ingroup gpio_registers
|
||||
* @defgroup GPIO_IS GPIO_IS
|
||||
* @brief GPIO Input Hysteresis Enable.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_IS_ALL_POS 0 /**< IS_ALL Position */
|
||||
#define MXC_F_GPIO_IS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IS_ALL_POS)) /**< IS_ALL Mask */
|
||||
|
||||
/**@} end of group GPIO_IS_Register */
|
||||
|
||||
/**
|
||||
* @ingroup gpio_registers
|
||||
* @defgroup GPIO_SR GPIO_SR
|
||||
* @brief GPIO Slew Rate Enable Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_SR_ALL_POS 0 /**< SR_ALL Position */
|
||||
#define MXC_F_GPIO_SR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_SR_ALL_POS)) /**< SR_ALL Mask */
|
||||
#define MXC_V_GPIO_SR_ALL_FAST ((uint32_t)0x0UL) /**< SR_ALL_FAST Value */
|
||||
#define MXC_S_GPIO_SR_ALL_FAST (MXC_V_GPIO_SR_ALL_FAST << MXC_F_GPIO_SR_ALL_POS) /**< SR_ALL_FAST Setting */
|
||||
#define MXC_V_GPIO_SR_ALL_SLOW ((uint32_t)0x1UL) /**< SR_ALL_SLOW Value */
|
||||
#define MXC_S_GPIO_SR_ALL_SLOW (MXC_V_GPIO_SR_ALL_SLOW << MXC_F_GPIO_SR_ALL_POS) /**< SR_ALL_SLOW Setting */
|
||||
|
||||
/**@} end of group GPIO_SR_Register */
|
||||
|
||||
/**
|
||||
* @ingroup gpio_registers
|
||||
* @defgroup GPIO_DS0 GPIO_DS0
|
||||
|
|
@ -626,12 +654,12 @@ typedef struct {
|
|||
* sink/source current of GPIO pins in each mode.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_DS0_ALL_POS 0 /**< DS0_ALL Position */
|
||||
#define MXC_F_GPIO_DS0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_ALL_POS)) /**< DS0_ALL Mask */
|
||||
#define MXC_V_GPIO_DS0_ALL_LD ((uint32_t)0x0UL) /**< DS0_ALL_LD Value */
|
||||
#define MXC_S_GPIO_DS0_ALL_LD (MXC_V_GPIO_DS0_ALL_LD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_LD Setting */
|
||||
#define MXC_V_GPIO_DS0_ALL_HD ((uint32_t)0x1UL) /**< DS0_ALL_HD Value */
|
||||
#define MXC_S_GPIO_DS0_ALL_HD (MXC_V_GPIO_DS0_ALL_HD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_HD Setting */
|
||||
#define MXC_F_GPIO_DS0_ALL_POS 0 /**< DS0_ALL Position */
|
||||
#define MXC_F_GPIO_DS0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_ALL_POS)) /**< DS0_ALL Mask */
|
||||
#define MXC_V_GPIO_DS0_ALL_LD ((uint32_t)0x0UL) /**< DS0_ALL_LD Value */
|
||||
#define MXC_S_GPIO_DS0_ALL_LD (MXC_V_GPIO_DS0_ALL_LD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_LD Setting */
|
||||
#define MXC_V_GPIO_DS0_ALL_HD ((uint32_t)0x1UL) /**< DS0_ALL_HD Value */
|
||||
#define MXC_S_GPIO_DS0_ALL_HD (MXC_V_GPIO_DS0_ALL_HD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_HD Setting */
|
||||
|
||||
/**@} end of group GPIO_DS0_Register */
|
||||
|
||||
|
|
@ -643,8 +671,8 @@ typedef struct {
|
|||
* sink/source current of GPIO pins in each mode.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */
|
||||
#define MXC_F_GPIO_DS1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */
|
||||
#define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */
|
||||
#define MXC_F_GPIO_DS1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */
|
||||
|
||||
/**@} end of group GPIO_DS1_Register */
|
||||
|
||||
|
|
@ -654,8 +682,8 @@ typedef struct {
|
|||
* @brief GPIO Pull Select Mode.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */
|
||||
#define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */
|
||||
#define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */
|
||||
#define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */
|
||||
|
||||
/**@} end of group GPIO_PS_Register */
|
||||
|
||||
|
|
@ -665,8 +693,8 @@ typedef struct {
|
|||
* @brief GPIO Voltage Select.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */
|
||||
#define MXC_F_GPIO_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */
|
||||
#define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */
|
||||
#define MXC_F_GPIO_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */
|
||||
|
||||
/**@} end of group GPIO_VSSEL_Register */
|
||||
|
||||
|
|
@ -674,4 +702,4 @@ typedef struct {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _GPIO_REGS_H_ */
|
||||
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GPIO_REGS_H_
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
/**
|
||||
* @file i2c_regs.h
|
||||
* @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
|
||||
* @note This file is @generated.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +35,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _I2C_REGS_H_
|
||||
#define _I2C_REGS_H_
|
||||
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_I2C_REGS_H_
|
||||
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_I2C_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -46,11 +46,11 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__ICCARM__)
|
||||
#pragma system_include
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__CC_ARM)
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
|
@ -67,7 +67,9 @@ extern "C" {
|
|||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
|
||||
#ifndef __R
|
||||
#define __R volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
|
@ -76,7 +78,7 @@ extern "C" {
|
|||
* @ingroup i2c
|
||||
* @defgroup i2c_registers I2C_Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
|
||||
* @details Inter-Integrated Circuit.
|
||||
* @details Inter-Integrated Circuit.
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
@ -109,28 +111,28 @@ typedef struct {
|
|||
/**
|
||||
* @ingroup i2c_registers
|
||||
* @defgroup I2C_Register_Offsets Register Offsets
|
||||
* @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address.
|
||||
* @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_I2C_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_I2C_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> 0x000C</tt> */
|
||||
#define MXC_R_I2C_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> 0x0010</tt> */
|
||||
#define MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> 0x0014</tt> */
|
||||
#define MXC_R_I2C_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> 0x0018</tt> */
|
||||
#define MXC_R_I2C_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> 0x001C</tt> */
|
||||
#define MXC_R_I2C_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> 0x0020</tt> */
|
||||
#define MXC_R_I2C_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> 0x0024</tt> */
|
||||
#define MXC_R_I2C_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> 0x0028</tt> */
|
||||
#define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> 0x002C</tt> */
|
||||
#define MXC_R_I2C_MSTR_MODE ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> 0x0030</tt> */
|
||||
#define MXC_R_I2C_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> 0x0034</tt> */
|
||||
#define MXC_R_I2C_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> 0x0038</tt> */
|
||||
#define MXC_R_I2C_HS_CLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt> 0x003C</tt> */
|
||||
#define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> 0x0040</tt> */
|
||||
#define MXC_R_I2C_SLADDR ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: <tt> 0x0044</tt> */
|
||||
#define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> 0x0048</tt> */
|
||||
#define MXC_R_I2C_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_I2C_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> 0x000C</tt> */
|
||||
#define MXC_R_I2C_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> 0x0010</tt> */
|
||||
#define MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> 0x0014</tt> */
|
||||
#define MXC_R_I2C_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> 0x0018</tt> */
|
||||
#define MXC_R_I2C_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> 0x001C</tt> */
|
||||
#define MXC_R_I2C_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> 0x0020</tt> */
|
||||
#define MXC_R_I2C_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> 0x0024</tt> */
|
||||
#define MXC_R_I2C_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> 0x0028</tt> */
|
||||
#define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> 0x002C</tt> */
|
||||
#define MXC_R_I2C_MSTR_MODE ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> 0x0030</tt> */
|
||||
#define MXC_R_I2C_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> 0x0034</tt> */
|
||||
#define MXC_R_I2C_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> 0x0038</tt> */
|
||||
#define MXC_R_I2C_HS_CLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt> 0x003C</tt> */
|
||||
#define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> 0x0040</tt> */
|
||||
#define MXC_R_I2C_SLADDR ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: <tt> 0x0044</tt> */
|
||||
#define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> 0x0048</tt> */
|
||||
/**@} end of group i2c_registers */
|
||||
|
||||
/**
|
||||
|
|
@ -139,47 +141,47 @@ typedef struct {
|
|||
* @brief Control Register0.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_CTRL0_I2CEN_POS 0 /**< CTRL0_I2CEN Position */
|
||||
#define MXC_F_I2C_CTRL0_I2CEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_I2CEN_POS)) /**< CTRL0_I2CEN Mask */
|
||||
#define MXC_F_I2C_CTRL0_I2CEN_POS 0 /**< CTRL0_I2CEN Position */
|
||||
#define MXC_F_I2C_CTRL0_I2CEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_I2CEN_POS)) /**< CTRL0_I2CEN Mask */
|
||||
|
||||
#define MXC_F_I2C_CTRL0_MST_POS 1 /**< CTRL0_MST Position */
|
||||
#define MXC_F_I2C_CTRL0_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_MST_POS)) /**< CTRL0_MST Mask */
|
||||
#define MXC_F_I2C_CTRL0_MST_POS 1 /**< CTRL0_MST Position */
|
||||
#define MXC_F_I2C_CTRL0_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_MST_POS)) /**< CTRL0_MST Mask */
|
||||
|
||||
#define MXC_F_I2C_CTRL0_GCEN_POS 2 /**< CTRL0_GCEN Position */
|
||||
#define MXC_F_I2C_CTRL0_GCEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_GCEN_POS)) /**< CTRL0_GCEN Mask */
|
||||
#define MXC_F_I2C_CTRL0_GCEN_POS 2 /**< CTRL0_GCEN Position */
|
||||
#define MXC_F_I2C_CTRL0_GCEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_GCEN_POS)) /**< CTRL0_GCEN Mask */
|
||||
|
||||
#define MXC_F_I2C_CTRL0_IRXM_POS 3 /**< CTRL0_IRXM Position */
|
||||
#define MXC_F_I2C_CTRL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_IRXM_POS)) /**< CTRL0_IRXM Mask */
|
||||
#define MXC_F_I2C_CTRL0_IRXM_POS 3 /**< CTRL0_IRXM Position */
|
||||
#define MXC_F_I2C_CTRL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_IRXM_POS)) /**< CTRL0_IRXM Mask */
|
||||
|
||||
#define MXC_F_I2C_CTRL0_ACK_POS 4 /**< CTRL0_ACK Position */
|
||||
#define MXC_F_I2C_CTRL0_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_ACK_POS)) /**< CTRL0_ACK Mask */
|
||||
#define MXC_F_I2C_CTRL0_ACK_POS 4 /**< CTRL0_ACK Position */
|
||||
#define MXC_F_I2C_CTRL0_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_ACK_POS)) /**< CTRL0_ACK Mask */
|
||||
|
||||
#define MXC_F_I2C_CTRL0_SCLO_POS 6 /**< CTRL0_SCLO Position */
|
||||
#define MXC_F_I2C_CTRL0_SCLO ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCLO_POS)) /**< CTRL0_SCLO Mask */
|
||||
#define MXC_F_I2C_CTRL0_SCLO_POS 6 /**< CTRL0_SCLO Position */
|
||||
#define MXC_F_I2C_CTRL0_SCLO ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCLO_POS)) /**< CTRL0_SCLO Mask */
|
||||
|
||||
#define MXC_F_I2C_CTRL0_SDAO_POS 7 /**< CTRL0_SDAO Position */
|
||||
#define MXC_F_I2C_CTRL0_SDAO ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDAO_POS)) /**< CTRL0_SDAO Mask */
|
||||
#define MXC_F_I2C_CTRL0_SDAO_POS 7 /**< CTRL0_SDAO Position */
|
||||
#define MXC_F_I2C_CTRL0_SDAO ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDAO_POS)) /**< CTRL0_SDAO Mask */
|
||||
|
||||
#define MXC_F_I2C_CTRL0_SCL_POS 8 /**< CTRL0_SCL Position */
|
||||
#define MXC_F_I2C_CTRL0_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_POS)) /**< CTRL0_SCL Mask */
|
||||
#define MXC_F_I2C_CTRL0_SCL_POS 8 /**< CTRL0_SCL Position */
|
||||
#define MXC_F_I2C_CTRL0_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_POS)) /**< CTRL0_SCL Mask */
|
||||
|
||||
#define MXC_F_I2C_CTRL0_SDA_POS 9 /**< CTRL0_SDA Position */
|
||||
#define MXC_F_I2C_CTRL0_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDA_POS)) /**< CTRL0_SDA Mask */
|
||||
#define MXC_F_I2C_CTRL0_SDA_POS 9 /**< CTRL0_SDA Position */
|
||||
#define MXC_F_I2C_CTRL0_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDA_POS)) /**< CTRL0_SDA Mask */
|
||||
|
||||
#define MXC_F_I2C_CTRL0_SWOE_POS 10 /**< CTRL0_SWOE Position */
|
||||
#define MXC_F_I2C_CTRL0_SWOE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SWOE_POS)) /**< CTRL0_SWOE Mask */
|
||||
#define MXC_F_I2C_CTRL0_SWOE_POS 10 /**< CTRL0_SWOE Position */
|
||||
#define MXC_F_I2C_CTRL0_SWOE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SWOE_POS)) /**< CTRL0_SWOE Mask */
|
||||
|
||||
#define MXC_F_I2C_CTRL0_READ_POS 11 /**< CTRL0_READ Position */
|
||||
#define MXC_F_I2C_CTRL0_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_READ_POS)) /**< CTRL0_READ Mask */
|
||||
#define MXC_F_I2C_CTRL0_READ_POS 11 /**< CTRL0_READ Position */
|
||||
#define MXC_F_I2C_CTRL0_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_READ_POS)) /**< CTRL0_READ Mask */
|
||||
|
||||
#define MXC_F_I2C_CTRL0_SCL_STRD_POS 12 /**< CTRL0_SCL_STRD Position */
|
||||
#define MXC_F_I2C_CTRL0_SCL_STRD ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_STRD_POS)) /**< CTRL0_SCL_STRD Mask */
|
||||
#define MXC_F_I2C_CTRL0_SCL_STRD_POS 12 /**< CTRL0_SCL_STRD Position */
|
||||
#define MXC_F_I2C_CTRL0_SCL_STRD ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_STRD_POS)) /**< CTRL0_SCL_STRD Mask */
|
||||
|
||||
#define MXC_F_I2C_CTRL0_SCL_PPM_POS 13 /**< CTRL0_SCL_PPM Position */
|
||||
#define MXC_F_I2C_CTRL0_SCL_PPM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_PPM_POS)) /**< CTRL0_SCL_PPM Mask */
|
||||
#define MXC_F_I2C_CTRL0_SCL_PPM_POS 13 /**< CTRL0_SCL_PPM Position */
|
||||
#define MXC_F_I2C_CTRL0_SCL_PPM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_PPM_POS)) /**< CTRL0_SCL_PPM Mask */
|
||||
|
||||
#define MXC_F_I2C_CTRL0_HSMODE_POS 15 /**< CTRL0_HSMODE Position */
|
||||
#define MXC_F_I2C_CTRL0_HSMODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_HSMODE_POS)) /**< CTRL0_HSMODE Mask */
|
||||
#define MXC_F_I2C_CTRL0_HSMODE_POS 15 /**< CTRL0_HSMODE Position */
|
||||
#define MXC_F_I2C_CTRL0_HSMODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_HSMODE_POS)) /**< CTRL0_HSMODE Mask */
|
||||
|
||||
/**@} end of group I2C_CTRL0_Register */
|
||||
|
||||
|
|
@ -189,56 +191,56 @@ typedef struct {
|
|||
* @brief Status Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */
|
||||
#define MXC_F_I2C_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */
|
||||
#define MXC_F_I2C_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */
|
||||
#define MXC_F_I2C_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */
|
||||
|
||||
#define MXC_F_I2C_STATUS_RXE_POS 1 /**< STATUS_RXE Position */
|
||||
#define MXC_F_I2C_STATUS_RXE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RXE_POS)) /**< STATUS_RXE Mask */
|
||||
#define MXC_F_I2C_STATUS_RXE_POS 1 /**< STATUS_RXE Position */
|
||||
#define MXC_F_I2C_STATUS_RXE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RXE_POS)) /**< STATUS_RXE Mask */
|
||||
|
||||
#define MXC_F_I2C_STATUS_RXF_POS 2 /**< STATUS_RXF Position */
|
||||
#define MXC_F_I2C_STATUS_RXF ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RXF_POS)) /**< STATUS_RXF Mask */
|
||||
#define MXC_F_I2C_STATUS_RXF_POS 2 /**< STATUS_RXF Position */
|
||||
#define MXC_F_I2C_STATUS_RXF ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RXF_POS)) /**< STATUS_RXF Mask */
|
||||
|
||||
#define MXC_F_I2C_STATUS_TXE_POS 3 /**< STATUS_TXE Position */
|
||||
#define MXC_F_I2C_STATUS_TXE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TXE_POS)) /**< STATUS_TXE Mask */
|
||||
#define MXC_F_I2C_STATUS_TXE_POS 3 /**< STATUS_TXE Position */
|
||||
#define MXC_F_I2C_STATUS_TXE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TXE_POS)) /**< STATUS_TXE Mask */
|
||||
|
||||
#define MXC_F_I2C_STATUS_TXF_POS 4 /**< STATUS_TXF Position */
|
||||
#define MXC_F_I2C_STATUS_TXF ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TXF_POS)) /**< STATUS_TXF Mask */
|
||||
#define MXC_F_I2C_STATUS_TXF_POS 4 /**< STATUS_TXF Position */
|
||||
#define MXC_F_I2C_STATUS_TXF ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TXF_POS)) /**< STATUS_TXF Mask */
|
||||
|
||||
#define MXC_F_I2C_STATUS_CKMD_POS 5 /**< STATUS_CKMD Position */
|
||||
#define MXC_F_I2C_STATUS_CKMD ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CKMD_POS)) /**< STATUS_CKMD Mask */
|
||||
#define MXC_F_I2C_STATUS_CKMD_POS 5 /**< STATUS_CKMD Position */
|
||||
#define MXC_F_I2C_STATUS_CKMD ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CKMD_POS)) /**< STATUS_CKMD Mask */
|
||||
|
||||
#define MXC_F_I2C_STATUS_STAT_POS 8 /**< STATUS_STAT Position */
|
||||
#define MXC_F_I2C_STATUS_STAT ((uint32_t)(0xFUL << MXC_F_I2C_STATUS_STAT_POS)) /**< STATUS_STAT Mask */
|
||||
#define MXC_V_I2C_STATUS_STAT_IDLE ((uint32_t)0x0UL) /**< STATUS_STAT_IDLE Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_IDLE (MXC_V_I2C_STATUS_STAT_IDLE << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_IDLE Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_MTX_ADDR ((uint32_t)0x1UL) /**< STATUS_STAT_MTX_ADDR Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_MTX_ADDR (MXC_V_I2C_STATUS_STAT_MTX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MTX_ADDR Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_MRX_ADDR_ACK ((uint32_t)0x2UL) /**< STATUS_STAT_MRX_ADDR_ACK Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_MRX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_MRX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MRX_ADDR_ACK Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_MTX_EX_ADDR ((uint32_t)0x3UL) /**< STATUS_STAT_MTX_EX_ADDR Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_MTX_EX_ADDR (MXC_V_I2C_STATUS_STAT_MTX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MTX_EX_ADDR Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_MRX_EX_ADDR ((uint32_t)0x4UL) /**< STATUS_STAT_MRX_EX_ADDR Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_MRX_EX_ADDR (MXC_V_I2C_STATUS_STAT_MRX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MRX_EX_ADDR Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_SRX_ADDR ((uint32_t)0x5UL) /**< STATUS_STAT_SRX_ADDR Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_SRX_ADDR (MXC_V_I2C_STATUS_STAT_SRX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_SRX_ADDR Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_STX_ADDR_ACK ((uint32_t)0x6UL) /**< STATUS_STAT_STX_ADDR_ACK Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_STX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_STX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_STX_ADDR_ACK Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_SRX_EX_ADDR ((uint32_t)0x7UL) /**< STATUS_STAT_SRX_EX_ADDR Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_SRX_EX_ADDR (MXC_V_I2C_STATUS_STAT_SRX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_SRX_EX_ADDR Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_STX_EX_ADDR_ACK ((uint32_t)0x8UL) /**< STATUS_STAT_STX_EX_ADDR_ACK Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_STX_EX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_STX_EX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_STX_EX_ADDR_ACK Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_TX ((uint32_t)0x9UL) /**< STATUS_STAT_TX Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_TX (MXC_V_I2C_STATUS_STAT_TX << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_TX Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_RX_ACK ((uint32_t)0xAUL) /**< STATUS_STAT_RX_ACK Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_RX_ACK (MXC_V_I2C_STATUS_STAT_RX_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_RX_ACK Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_RX ((uint32_t)0xBUL) /**< STATUS_STAT_RX Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_RX (MXC_V_I2C_STATUS_STAT_RX << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_RX Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_TX_ACK ((uint32_t)0xCUL) /**< STATUS_STAT_TX_ACK Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_TX_ACK (MXC_V_I2C_STATUS_STAT_TX_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_TX_ACK Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_NACK ((uint32_t)0xDUL) /**< STATUS_STAT_NACK Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_NACK (MXC_V_I2C_STATUS_STAT_NACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_NACK Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_BY_ST ((uint32_t)0xFUL) /**< STATUS_STAT_BY_ST Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_BY_ST (MXC_V_I2C_STATUS_STAT_BY_ST << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_BY_ST Setting */
|
||||
#define MXC_F_I2C_STATUS_STAT_POS 8 /**< STATUS_STAT Position */
|
||||
#define MXC_F_I2C_STATUS_STAT ((uint32_t)(0xFUL << MXC_F_I2C_STATUS_STAT_POS)) /**< STATUS_STAT Mask */
|
||||
#define MXC_V_I2C_STATUS_STAT_IDLE ((uint32_t)0x0UL) /**< STATUS_STAT_IDLE Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_IDLE (MXC_V_I2C_STATUS_STAT_IDLE << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_IDLE Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_MTX_ADDR ((uint32_t)0x1UL) /**< STATUS_STAT_MTX_ADDR Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_MTX_ADDR (MXC_V_I2C_STATUS_STAT_MTX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MTX_ADDR Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_MRX_ADDR_ACK ((uint32_t)0x2UL) /**< STATUS_STAT_MRX_ADDR_ACK Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_MRX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_MRX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MRX_ADDR_ACK Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_MTX_EX_ADDR ((uint32_t)0x3UL) /**< STATUS_STAT_MTX_EX_ADDR Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_MTX_EX_ADDR (MXC_V_I2C_STATUS_STAT_MTX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MTX_EX_ADDR Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_MRX_EX_ADDR ((uint32_t)0x4UL) /**< STATUS_STAT_MRX_EX_ADDR Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_MRX_EX_ADDR (MXC_V_I2C_STATUS_STAT_MRX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MRX_EX_ADDR Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_SRX_ADDR ((uint32_t)0x5UL) /**< STATUS_STAT_SRX_ADDR Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_SRX_ADDR (MXC_V_I2C_STATUS_STAT_SRX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_SRX_ADDR Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_STX_ADDR_ACK ((uint32_t)0x6UL) /**< STATUS_STAT_STX_ADDR_ACK Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_STX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_STX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_STX_ADDR_ACK Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_SRX_EX_ADDR ((uint32_t)0x7UL) /**< STATUS_STAT_SRX_EX_ADDR Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_SRX_EX_ADDR (MXC_V_I2C_STATUS_STAT_SRX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_SRX_EX_ADDR Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_STX_EX_ADDR_ACK ((uint32_t)0x8UL) /**< STATUS_STAT_STX_EX_ADDR_ACK Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_STX_EX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_STX_EX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_STX_EX_ADDR_ACK Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_TX ((uint32_t)0x9UL) /**< STATUS_STAT_TX Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_TX (MXC_V_I2C_STATUS_STAT_TX << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_TX Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_RX_ACK ((uint32_t)0xAUL) /**< STATUS_STAT_RX_ACK Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_RX_ACK (MXC_V_I2C_STATUS_STAT_RX_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_RX_ACK Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_RX ((uint32_t)0xBUL) /**< STATUS_STAT_RX Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_RX (MXC_V_I2C_STATUS_STAT_RX << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_RX Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_TX_ACK ((uint32_t)0xCUL) /**< STATUS_STAT_TX_ACK Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_TX_ACK (MXC_V_I2C_STATUS_STAT_TX_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_TX_ACK Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_NACK ((uint32_t)0xDUL) /**< STATUS_STAT_NACK Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_NACK (MXC_V_I2C_STATUS_STAT_NACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_NACK Setting */
|
||||
#define MXC_V_I2C_STATUS_STAT_BY_ST ((uint32_t)0xFUL) /**< STATUS_STAT_BY_ST Value */
|
||||
#define MXC_S_I2C_STATUS_STAT_BY_ST (MXC_V_I2C_STATUS_STAT_BY_ST << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_BY_ST Setting */
|
||||
|
||||
/**@} end of group I2C_STATUS_Register */
|
||||
|
||||
|
|
@ -248,53 +250,56 @@ typedef struct {
|
|||
* @brief Interrupt Status Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_INTFL0_DONEI_POS 0 /**< INTFL0_DONEI Position */
|
||||
#define MXC_F_I2C_INTFL0_DONEI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONEI_POS)) /**< INTFL0_DONEI Mask */
|
||||
#define MXC_F_I2C_INTFL0_DONEI_POS 0 /**< INTFL0_DONEI Position */
|
||||
#define MXC_F_I2C_INTFL0_DONEI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONEI_POS)) /**< INTFL0_DONEI Mask */
|
||||
|
||||
#define MXC_F_I2C_INTFL0_IRXMI_POS 1 /**< INTFL0_IRXMI Position */
|
||||
#define MXC_F_I2C_INTFL0_IRXMI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXMI_POS)) /**< INTFL0_IRXMI Mask */
|
||||
#define MXC_F_I2C_INTFL0_IRXMI_POS 1 /**< INTFL0_IRXMI Position */
|
||||
#define MXC_F_I2C_INTFL0_IRXMI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXMI_POS)) /**< INTFL0_IRXMI Mask */
|
||||
|
||||
#define MXC_F_I2C_INTFL0_GCI_POS 2 /**< INTFL0_GCI Position */
|
||||
#define MXC_F_I2C_INTFL0_GCI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GCI_POS)) /**< INTFL0_GCI Mask */
|
||||
#define MXC_F_I2C_INTFL0_GCI_POS 2 /**< INTFL0_GCI Position */
|
||||
#define MXC_F_I2C_INTFL0_GCI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GCI_POS)) /**< INTFL0_GCI Mask */
|
||||
|
||||
#define MXC_F_I2C_INTFL0_AMI_POS 3 /**< INTFL0_AMI Position */
|
||||
#define MXC_F_I2C_INTFL0_AMI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_AMI_POS)) /**< INTFL0_AMI Mask */
|
||||
#define MXC_F_I2C_INTFL0_AMI_POS 3 /**< INTFL0_AMI Position */
|
||||
#define MXC_F_I2C_INTFL0_AMI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_AMI_POS)) /**< INTFL0_AMI Mask */
|
||||
|
||||
#define MXC_F_I2C_INTFL0_RXTHI_POS 4 /**< INTFL0_RXTHI Position */
|
||||
#define MXC_F_I2C_INTFL0_RXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RXTHI_POS)) /**< INTFL0_RXTHI Mask */
|
||||
#define MXC_F_I2C_INTFL0_RXTHI_POS 4 /**< INTFL0_RXTHI Position */
|
||||
#define MXC_F_I2C_INTFL0_RXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RXTHI_POS)) /**< INTFL0_RXTHI Mask */
|
||||
|
||||
#define MXC_F_I2C_INTFL0_TXTHI_POS 5 /**< INTFL0_TXTHI Position */
|
||||
#define MXC_F_I2C_INTFL0_TXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TXTHI_POS)) /**< INTFL0_TXTHI Mask */
|
||||
#define MXC_F_I2C_INTFL0_TXTHI_POS 5 /**< INTFL0_TXTHI Position */
|
||||
#define MXC_F_I2C_INTFL0_TXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TXTHI_POS)) /**< INTFL0_TXTHI Mask */
|
||||
|
||||
#define MXC_F_I2C_INTFL0_STOPI_POS 6 /**< INTFL0_STOPI Position */
|
||||
#define MXC_F_I2C_INTFL0_STOPI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOPI_POS)) /**< INTFL0_STOPI Mask */
|
||||
#define MXC_F_I2C_INTFL0_STOPI_POS 6 /**< INTFL0_STOPI Position */
|
||||
#define MXC_F_I2C_INTFL0_STOPI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOPI_POS)) /**< INTFL0_STOPI Mask */
|
||||
|
||||
#define MXC_F_I2C_INTFL0_ADRACKI_POS 7 /**< INTFL0_ADRACKI Position */
|
||||
#define MXC_F_I2C_INTFL0_ADRACKI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADRACKI_POS)) /**< INTFL0_ADRACKI Mask */
|
||||
#define MXC_F_I2C_INTFL0_ADRACKI_POS 7 /**< INTFL0_ADRACKI Position */
|
||||
#define MXC_F_I2C_INTFL0_ADRACKI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADRACKI_POS)) /**< INTFL0_ADRACKI Mask */
|
||||
|
||||
#define MXC_F_I2C_INTFL0_ARBERI_POS 8 /**< INTFL0_ARBERI Position */
|
||||
#define MXC_F_I2C_INTFL0_ARBERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARBERI_POS)) /**< INTFL0_ARBERI Mask */
|
||||
#define MXC_F_I2C_INTFL0_ARBERI_POS 8 /**< INTFL0_ARBERI Position */
|
||||
#define MXC_F_I2C_INTFL0_ARBERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARBERI_POS)) /**< INTFL0_ARBERI Mask */
|
||||
|
||||
#define MXC_F_I2C_INTFL0_TOERI_POS 9 /**< INTFL0_TOERI Position */
|
||||
#define MXC_F_I2C_INTFL0_TOERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TOERI_POS)) /**< INTFL0_TOERI Mask */
|
||||
#define MXC_F_I2C_INTFL0_TOERI_POS 9 /**< INTFL0_TOERI Position */
|
||||
#define MXC_F_I2C_INTFL0_TOERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TOERI_POS)) /**< INTFL0_TOERI Mask */
|
||||
|
||||
#define MXC_F_I2C_INTFL0_ADRERI_POS 10 /**< INTFL0_ADRERI Position */
|
||||
#define MXC_F_I2C_INTFL0_ADRERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADRERI_POS)) /**< INTFL0_ADRERI Mask */
|
||||
#define MXC_F_I2C_INTFL0_ADRERI_POS 10 /**< INTFL0_ADRERI Position */
|
||||
#define MXC_F_I2C_INTFL0_ADRERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADRERI_POS)) /**< INTFL0_ADRERI Mask */
|
||||
|
||||
#define MXC_F_I2C_INTFL0_DATERI_POS 11 /**< INTFL0_DATERI Position */
|
||||
#define MXC_F_I2C_INTFL0_DATERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATERI_POS)) /**< INTFL0_DATERI Mask */
|
||||
#define MXC_F_I2C_INTFL0_DATERI_POS 11 /**< INTFL0_DATERI Position */
|
||||
#define MXC_F_I2C_INTFL0_DATERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATERI_POS)) /**< INTFL0_DATERI Mask */
|
||||
|
||||
#define MXC_F_I2C_INTFL0_DNRERI_POS 12 /**< INTFL0_DNRERI Position */
|
||||
#define MXC_F_I2C_INTFL0_DNRERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNRERI_POS)) /**< INTFL0_DNRERI Mask */
|
||||
#define MXC_F_I2C_INTFL0_DNRERI_POS 12 /**< INTFL0_DNRERI Position */
|
||||
#define MXC_F_I2C_INTFL0_DNRERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNRERI_POS)) /**< INTFL0_DNRERI Mask */
|
||||
|
||||
#define MXC_F_I2C_INTFL0_STRTERI_POS 13 /**< INTFL0_STRTERI Position */
|
||||
#define MXC_F_I2C_INTFL0_STRTERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STRTERI_POS)) /**< INTFL0_STRTERI Mask */
|
||||
#define MXC_F_I2C_INTFL0_STRTERI_POS 13 /**< INTFL0_STRTERI Position */
|
||||
#define MXC_F_I2C_INTFL0_STRTERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STRTERI_POS)) /**< INTFL0_STRTERI Mask */
|
||||
|
||||
#define MXC_F_I2C_INTFL0_STOPERI_POS 14 /**< INTFL0_STOPERI Position */
|
||||
#define MXC_F_I2C_INTFL0_STOPERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOPERI_POS)) /**< INTFL0_STOPERI Mask */
|
||||
#define MXC_F_I2C_INTFL0_STOPERI_POS 14 /**< INTFL0_STOPERI Position */
|
||||
#define MXC_F_I2C_INTFL0_STOPERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOPERI_POS)) /**< INTFL0_STOPERI Mask */
|
||||
|
||||
#define MXC_F_I2C_INTFL0_TXLOI_POS 15 /**< INTFL0_TXLOI Position */
|
||||
#define MXC_F_I2C_INTFL0_TXLOI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TXLOI_POS)) /**< INTFL0_TXLOI Mask */
|
||||
#define MXC_F_I2C_INTFL0_TXLOI_POS 15 /**< INTFL0_TXLOI Position */
|
||||
#define MXC_F_I2C_INTFL0_TXLOI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TXLOI_POS)) /**< INTFL0_TXLOI Mask */
|
||||
|
||||
#define MXC_F_I2C_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */
|
||||
#define MXC_F_I2C_INTFL0_MAMI ((uint32_t)(0xFUL << MXC_F_I2C_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */
|
||||
|
||||
/**@} end of group I2C_INTFL0_Register */
|
||||
|
||||
|
|
@ -304,53 +309,56 @@ typedef struct {
|
|||
* @brief Interrupt Enable Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_INTEN0_DONEIE_POS 0 /**< INTEN0_DONEIE Position */
|
||||
#define MXC_F_I2C_INTEN0_DONEIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONEIE_POS)) /**< INTEN0_DONEIE Mask */
|
||||
#define MXC_F_I2C_INTEN0_DONEIE_POS 0 /**< INTEN0_DONEIE Position */
|
||||
#define MXC_F_I2C_INTEN0_DONEIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONEIE_POS)) /**< INTEN0_DONEIE Mask */
|
||||
|
||||
#define MXC_F_I2C_INTEN0_IRXMIE_POS 1 /**< INTEN0_IRXMIE Position */
|
||||
#define MXC_F_I2C_INTEN0_IRXMIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXMIE_POS)) /**< INTEN0_IRXMIE Mask */
|
||||
#define MXC_F_I2C_INTEN0_IRXMIE_POS 1 /**< INTEN0_IRXMIE Position */
|
||||
#define MXC_F_I2C_INTEN0_IRXMIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXMIE_POS)) /**< INTEN0_IRXMIE Mask */
|
||||
|
||||
#define MXC_F_I2C_INTEN0_GCIE_POS 2 /**< INTEN0_GCIE Position */
|
||||
#define MXC_F_I2C_INTEN0_GCIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GCIE_POS)) /**< INTEN0_GCIE Mask */
|
||||
#define MXC_F_I2C_INTEN0_GCIE_POS 2 /**< INTEN0_GCIE Position */
|
||||
#define MXC_F_I2C_INTEN0_GCIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GCIE_POS)) /**< INTEN0_GCIE Mask */
|
||||
|
||||
#define MXC_F_I2C_INTEN0_AMIE_POS 3 /**< INTEN0_AMIE Position */
|
||||
#define MXC_F_I2C_INTEN0_AMIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_AMIE_POS)) /**< INTEN0_AMIE Mask */
|
||||
#define MXC_F_I2C_INTEN0_AMIE_POS 3 /**< INTEN0_AMIE Position */
|
||||
#define MXC_F_I2C_INTEN0_AMIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_AMIE_POS)) /**< INTEN0_AMIE Mask */
|
||||
|
||||
#define MXC_F_I2C_INTEN0_RXTHIE_POS 4 /**< INTEN0_RXTHIE Position */
|
||||
#define MXC_F_I2C_INTEN0_RXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RXTHIE_POS)) /**< INTEN0_RXTHIE Mask */
|
||||
#define MXC_F_I2C_INTEN0_RXTHIE_POS 4 /**< INTEN0_RXTHIE Position */
|
||||
#define MXC_F_I2C_INTEN0_RXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RXTHIE_POS)) /**< INTEN0_RXTHIE Mask */
|
||||
|
||||
#define MXC_F_I2C_INTEN0_TXTHIE_POS 5 /**< INTEN0_TXTHIE Position */
|
||||
#define MXC_F_I2C_INTEN0_TXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXTHIE_POS)) /**< INTEN0_TXTHIE Mask */
|
||||
#define MXC_F_I2C_INTEN0_TXTHIE_POS 5 /**< INTEN0_TXTHIE Position */
|
||||
#define MXC_F_I2C_INTEN0_TXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXTHIE_POS)) /**< INTEN0_TXTHIE Mask */
|
||||
|
||||
#define MXC_F_I2C_INTEN0_STOPIE_POS 6 /**< INTEN0_STOPIE Position */
|
||||
#define MXC_F_I2C_INTEN0_STOPIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOPIE_POS)) /**< INTEN0_STOPIE Mask */
|
||||
#define MXC_F_I2C_INTEN0_STOPIE_POS 6 /**< INTEN0_STOPIE Position */
|
||||
#define MXC_F_I2C_INTEN0_STOPIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOPIE_POS)) /**< INTEN0_STOPIE Mask */
|
||||
|
||||
#define MXC_F_I2C_INTEN0_ADRACKIE_POS 7 /**< INTEN0_ADRACKIE Position */
|
||||
#define MXC_F_I2C_INTEN0_ADRACKIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADRACKIE_POS)) /**< INTEN0_ADRACKIE Mask */
|
||||
#define MXC_F_I2C_INTEN0_ADRACKIE_POS 7 /**< INTEN0_ADRACKIE Position */
|
||||
#define MXC_F_I2C_INTEN0_ADRACKIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADRACKIE_POS)) /**< INTEN0_ADRACKIE Mask */
|
||||
|
||||
#define MXC_F_I2C_INTEN0_ARBERIE_POS 8 /**< INTEN0_ARBERIE Position */
|
||||
#define MXC_F_I2C_INTEN0_ARBERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARBERIE_POS)) /**< INTEN0_ARBERIE Mask */
|
||||
#define MXC_F_I2C_INTEN0_ARBERIE_POS 8 /**< INTEN0_ARBERIE Position */
|
||||
#define MXC_F_I2C_INTEN0_ARBERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARBERIE_POS)) /**< INTEN0_ARBERIE Mask */
|
||||
|
||||
#define MXC_F_I2C_INTEN0_TOERIE_POS 9 /**< INTEN0_TOERIE Position */
|
||||
#define MXC_F_I2C_INTEN0_TOERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TOERIE_POS)) /**< INTEN0_TOERIE Mask */
|
||||
#define MXC_F_I2C_INTEN0_TOERIE_POS 9 /**< INTEN0_TOERIE Position */
|
||||
#define MXC_F_I2C_INTEN0_TOERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TOERIE_POS)) /**< INTEN0_TOERIE Mask */
|
||||
|
||||
#define MXC_F_I2C_INTEN0_ADRERIE_POS 10 /**< INTEN0_ADRERIE Position */
|
||||
#define MXC_F_I2C_INTEN0_ADRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADRERIE_POS)) /**< INTEN0_ADRERIE Mask */
|
||||
#define MXC_F_I2C_INTEN0_ADRERIE_POS 10 /**< INTEN0_ADRERIE Position */
|
||||
#define MXC_F_I2C_INTEN0_ADRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADRERIE_POS)) /**< INTEN0_ADRERIE Mask */
|
||||
|
||||
#define MXC_F_I2C_INTEN0_DATERIE_POS 11 /**< INTEN0_DATERIE Position */
|
||||
#define MXC_F_I2C_INTEN0_DATERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATERIE_POS)) /**< INTEN0_DATERIE Mask */
|
||||
#define MXC_F_I2C_INTEN0_DATERIE_POS 11 /**< INTEN0_DATERIE Position */
|
||||
#define MXC_F_I2C_INTEN0_DATERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATERIE_POS)) /**< INTEN0_DATERIE Mask */
|
||||
|
||||
#define MXC_F_I2C_INTEN0_DNRERIE_POS 12 /**< INTEN0_DNRERIE Position */
|
||||
#define MXC_F_I2C_INTEN0_DNRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNRERIE_POS)) /**< INTEN0_DNRERIE Mask */
|
||||
#define MXC_F_I2C_INTEN0_DNRERIE_POS 12 /**< INTEN0_DNRERIE Position */
|
||||
#define MXC_F_I2C_INTEN0_DNRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNRERIE_POS)) /**< INTEN0_DNRERIE Mask */
|
||||
|
||||
#define MXC_F_I2C_INTEN0_STRTERIE_POS 13 /**< INTEN0_STRTERIE Position */
|
||||
#define MXC_F_I2C_INTEN0_STRTERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STRTERIE_POS)) /**< INTEN0_STRTERIE Mask */
|
||||
#define MXC_F_I2C_INTEN0_STRTERIE_POS 13 /**< INTEN0_STRTERIE Position */
|
||||
#define MXC_F_I2C_INTEN0_STRTERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STRTERIE_POS)) /**< INTEN0_STRTERIE Mask */
|
||||
|
||||
#define MXC_F_I2C_INTEN0_STOPERIE_POS 14 /**< INTEN0_STOPERIE Position */
|
||||
#define MXC_F_I2C_INTEN0_STOPERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOPERIE_POS)) /**< INTEN0_STOPERIE Mask */
|
||||
#define MXC_F_I2C_INTEN0_STOPERIE_POS 14 /**< INTEN0_STOPERIE Position */
|
||||
#define MXC_F_I2C_INTEN0_STOPERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOPERIE_POS)) /**< INTEN0_STOPERIE Mask */
|
||||
|
||||
#define MXC_F_I2C_INTEN0_TXLOIE_POS 15 /**< INTEN0_TXLOIE Position */
|
||||
#define MXC_F_I2C_INTEN0_TXLOIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXLOIE_POS)) /**< INTEN0_TXLOIE Mask */
|
||||
#define MXC_F_I2C_INTEN0_TXLOIE_POS 15 /**< INTEN0_TXLOIE Position */
|
||||
#define MXC_F_I2C_INTEN0_TXLOIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXLOIE_POS)) /**< INTEN0_TXLOIE Mask */
|
||||
|
||||
#define MXC_F_I2C_INTEN0_MAMIE_POS 16 /**< INTEN0_MAMIE Position */
|
||||
#define MXC_F_I2C_INTEN0_MAMIE ((uint32_t)(0xFUL << MXC_F_I2C_INTEN0_MAMIE_POS)) /**< INTEN0_MAMIE Mask */
|
||||
|
||||
/**@} end of group I2C_INTEN0_Register */
|
||||
|
||||
|
|
@ -360,11 +368,11 @@ typedef struct {
|
|||
* @brief Interrupt Status Register 1.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_INTFL1_RXOFI_POS 0 /**< INTFL1_RXOFI Position */
|
||||
#define MXC_F_I2C_INTFL1_RXOFI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RXOFI_POS)) /**< INTFL1_RXOFI Mask */
|
||||
#define MXC_F_I2C_INTFL1_RXOFI_POS 0 /**< INTFL1_RXOFI Position */
|
||||
#define MXC_F_I2C_INTFL1_RXOFI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RXOFI_POS)) /**< INTFL1_RXOFI Mask */
|
||||
|
||||
#define MXC_F_I2C_INTFL1_TXUFI_POS 1 /**< INTFL1_TXUFI Position */
|
||||
#define MXC_F_I2C_INTFL1_TXUFI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TXUFI_POS)) /**< INTFL1_TXUFI Mask */
|
||||
#define MXC_F_I2C_INTFL1_TXUFI_POS 1 /**< INTFL1_TXUFI Position */
|
||||
#define MXC_F_I2C_INTFL1_TXUFI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TXUFI_POS)) /**< INTFL1_TXUFI Mask */
|
||||
|
||||
/**@} end of group I2C_INTFL1_Register */
|
||||
|
||||
|
|
@ -374,11 +382,11 @@ typedef struct {
|
|||
* @brief Interrupt Staus Register 1.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_INTEN1_RXOFIE_POS 0 /**< INTEN1_RXOFIE Position */
|
||||
#define MXC_F_I2C_INTEN1_RXOFIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RXOFIE_POS)) /**< INTEN1_RXOFIE Mask */
|
||||
#define MXC_F_I2C_INTEN1_RXOFIE_POS 0 /**< INTEN1_RXOFIE Position */
|
||||
#define MXC_F_I2C_INTEN1_RXOFIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RXOFIE_POS)) /**< INTEN1_RXOFIE Mask */
|
||||
|
||||
#define MXC_F_I2C_INTEN1_TXUFIE_POS 1 /**< INTEN1_TXUFIE Position */
|
||||
#define MXC_F_I2C_INTEN1_TXUFIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TXUFIE_POS)) /**< INTEN1_TXUFIE Mask */
|
||||
#define MXC_F_I2C_INTEN1_TXUFIE_POS 1 /**< INTEN1_TXUFIE Position */
|
||||
#define MXC_F_I2C_INTEN1_TXUFIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TXUFIE_POS)) /**< INTEN1_TXUFIE Mask */
|
||||
|
||||
/**@} end of group I2C_INTEN1_Register */
|
||||
|
||||
|
|
@ -388,11 +396,11 @@ typedef struct {
|
|||
* @brief FIFO Configuration Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_FIFOLEN_RXLEN_POS 0 /**< FIFOLEN_RXLEN Position */
|
||||
#define MXC_F_I2C_FIFOLEN_RXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RXLEN_POS)) /**< FIFOLEN_RXLEN Mask */
|
||||
#define MXC_F_I2C_FIFOLEN_RXLEN_POS 0 /**< FIFOLEN_RXLEN Position */
|
||||
#define MXC_F_I2C_FIFOLEN_RXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RXLEN_POS)) /**< FIFOLEN_RXLEN Mask */
|
||||
|
||||
#define MXC_F_I2C_FIFOLEN_TXLEN_POS 8 /**< FIFOLEN_TXLEN Position */
|
||||
#define MXC_F_I2C_FIFOLEN_TXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TXLEN_POS)) /**< FIFOLEN_TXLEN Mask */
|
||||
#define MXC_F_I2C_FIFOLEN_TXLEN_POS 8 /**< FIFOLEN_TXLEN Position */
|
||||
#define MXC_F_I2C_FIFOLEN_TXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TXLEN_POS)) /**< FIFOLEN_TXLEN Mask */
|
||||
|
||||
/**@} end of group I2C_FIFOLEN_Register */
|
||||
|
||||
|
|
@ -402,14 +410,14 @@ typedef struct {
|
|||
* @brief Receive Control Register 0.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */
|
||||
#define MXC_F_I2C_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */
|
||||
#define MXC_F_I2C_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */
|
||||
#define MXC_F_I2C_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */
|
||||
|
||||
#define MXC_F_I2C_RXCTRL0_RXFSH_POS 7 /**< RXCTRL0_RXFSH Position */
|
||||
#define MXC_F_I2C_RXCTRL0_RXFSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_RXFSH_POS)) /**< RXCTRL0_RXFSH Mask */
|
||||
#define MXC_F_I2C_RXCTRL0_RXFSH_POS 7 /**< RXCTRL0_RXFSH Position */
|
||||
#define MXC_F_I2C_RXCTRL0_RXFSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_RXFSH_POS)) /**< RXCTRL0_RXFSH Mask */
|
||||
|
||||
#define MXC_F_I2C_RXCTRL0_RXTH_POS 8 /**< RXCTRL0_RXTH Position */
|
||||
#define MXC_F_I2C_RXCTRL0_RXTH ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_RXTH_POS)) /**< RXCTRL0_RXTH Mask */
|
||||
#define MXC_F_I2C_RXCTRL0_RXTH_POS 8 /**< RXCTRL0_RXTH Position */
|
||||
#define MXC_F_I2C_RXCTRL0_RXTH ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_RXTH_POS)) /**< RXCTRL0_RXTH Mask */
|
||||
|
||||
/**@} end of group I2C_RXCTRL0_Register */
|
||||
|
||||
|
|
@ -419,11 +427,11 @@ typedef struct {
|
|||
* @brief Receive Control Register 1.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_RXCTRL1_RXCNT_POS 0 /**< RXCTRL1_RXCNT Position */
|
||||
#define MXC_F_I2C_RXCTRL1_RXCNT ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_RXCNT_POS)) /**< RXCTRL1_RXCNT Mask */
|
||||
#define MXC_F_I2C_RXCTRL1_RXCNT_POS 0 /**< RXCTRL1_RXCNT Position */
|
||||
#define MXC_F_I2C_RXCTRL1_RXCNT ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_RXCNT_POS)) /**< RXCTRL1_RXCNT Mask */
|
||||
|
||||
#define MXC_F_I2C_RXCTRL1_RXFIFO_POS 8 /**< RXCTRL1_RXFIFO Position */
|
||||
#define MXC_F_I2C_RXCTRL1_RXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_RXFIFO_POS)) /**< RXCTRL1_RXFIFO Mask */
|
||||
#define MXC_F_I2C_RXCTRL1_RXFIFO_POS 8 /**< RXCTRL1_RXFIFO Position */
|
||||
#define MXC_F_I2C_RXCTRL1_RXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_RXFIFO_POS)) /**< RXCTRL1_RXFIFO Mask */
|
||||
|
||||
/**@} end of group I2C_RXCTRL1_Register */
|
||||
|
||||
|
|
@ -433,17 +441,17 @@ typedef struct {
|
|||
* @brief Transmit Control Register 0.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_TXCTRL0_TXPRELD_POS 0 /**< TXCTRL0_TXPRELD Position */
|
||||
#define MXC_F_I2C_TXCTRL0_TXPRELD ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TXPRELD_POS)) /**< TXCTRL0_TXPRELD Mask */
|
||||
#define MXC_F_I2C_TXCTRL0_TXPRELD_POS 0 /**< TXCTRL0_TXPRELD Position */
|
||||
#define MXC_F_I2C_TXCTRL0_TXPRELD ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TXPRELD_POS)) /**< TXCTRL0_TXPRELD Mask */
|
||||
|
||||
#define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */
|
||||
#define MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */
|
||||
#define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */
|
||||
#define MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */
|
||||
|
||||
#define MXC_F_I2C_TXCTRL0_TXFSH_POS 7 /**< TXCTRL0_TXFSH Position */
|
||||
#define MXC_F_I2C_TXCTRL0_TXFSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TXFSH_POS)) /**< TXCTRL0_TXFSH Mask */
|
||||
#define MXC_F_I2C_TXCTRL0_TXFSH_POS 7 /**< TXCTRL0_TXFSH Position */
|
||||
#define MXC_F_I2C_TXCTRL0_TXFSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TXFSH_POS)) /**< TXCTRL0_TXFSH Mask */
|
||||
|
||||
#define MXC_F_I2C_TXCTRL0_TXTH_POS 8 /**< TXCTRL0_TXTH Position */
|
||||
#define MXC_F_I2C_TXCTRL0_TXTH ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_TXTH_POS)) /**< TXCTRL0_TXTH Mask */
|
||||
#define MXC_F_I2C_TXCTRL0_TXTH_POS 8 /**< TXCTRL0_TXTH Position */
|
||||
#define MXC_F_I2C_TXCTRL0_TXTH ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_TXTH_POS)) /**< TXCTRL0_TXTH Mask */
|
||||
|
||||
/**@} end of group I2C_TXCTRL0_Register */
|
||||
|
||||
|
|
@ -453,23 +461,23 @@ typedef struct {
|
|||
* @brief Transmit Control Register 1.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_TXCTRL1_TXRDY_POS 0 /**< TXCTRL1_TXRDY Position */
|
||||
#define MXC_F_I2C_TXCTRL1_TXRDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_TXRDY_POS)) /**< TXCTRL1_TXRDY Mask */
|
||||
#define MXC_F_I2C_TXCTRL1_TXRDY_POS 0 /**< TXCTRL1_TXRDY Position */
|
||||
#define MXC_F_I2C_TXCTRL1_TXRDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_TXRDY_POS)) /**< TXCTRL1_TXRDY Mask */
|
||||
|
||||
#define MXC_F_I2C_TXCTRL1_TXLAST_POS 1 /**< TXCTRL1_TXLAST Position */
|
||||
#define MXC_F_I2C_TXCTRL1_TXLAST ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_TXLAST_POS)) /**< TXCTRL1_TXLAST Mask */
|
||||
#define MXC_F_I2C_TXCTRL1_TXLAST_POS 1 /**< TXCTRL1_TXLAST Position */
|
||||
#define MXC_F_I2C_TXCTRL1_TXLAST ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_TXLAST_POS)) /**< TXCTRL1_TXLAST Mask */
|
||||
|
||||
#define MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS_POS 2 /**< TXCTRL1_FLSH_GCADDR_DIS Position */
|
||||
#define MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS_POS)) /**< TXCTRL1_FLSH_GCADDR_DIS Mask */
|
||||
#define MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS_POS 2 /**< TXCTRL1_FLSH_GCADDR_DIS Position */
|
||||
#define MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS_POS)) /**< TXCTRL1_FLSH_GCADDR_DIS Mask */
|
||||
|
||||
#define MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS_POS 4 /**< TXCTRL1_FLSH_SLADDR_DIS Position */
|
||||
#define MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS_POS)) /**< TXCTRL1_FLSH_SLADDR_DIS Mask */
|
||||
#define MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS_POS 4 /**< TXCTRL1_FLSH_SLADDR_DIS Position */
|
||||
#define MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS_POS)) /**< TXCTRL1_FLSH_SLADDR_DIS Mask */
|
||||
|
||||
#define MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS_POS 5 /**< TXCTRL1_FLSH_NACK_DIS Position */
|
||||
#define MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS_POS)) /**< TXCTRL1_FLSH_NACK_DIS Mask */
|
||||
#define MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS_POS 5 /**< TXCTRL1_FLSH_NACK_DIS Position */
|
||||
#define MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS_POS)) /**< TXCTRL1_FLSH_NACK_DIS Mask */
|
||||
|
||||
#define MXC_F_I2C_TXCTRL1_TXFIFO_POS 8 /**< TXCTRL1_TXFIFO Position */
|
||||
#define MXC_F_I2C_TXCTRL1_TXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_TXFIFO_POS)) /**< TXCTRL1_TXFIFO Mask */
|
||||
#define MXC_F_I2C_TXCTRL1_TXFIFO_POS 8 /**< TXCTRL1_TXFIFO Position */
|
||||
#define MXC_F_I2C_TXCTRL1_TXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_TXFIFO_POS)) /**< TXCTRL1_TXFIFO Mask */
|
||||
|
||||
/**@} end of group I2C_TXCTRL1_Register */
|
||||
|
||||
|
|
@ -479,8 +487,8 @@ typedef struct {
|
|||
* @brief Data Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */
|
||||
#define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
|
||||
#define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */
|
||||
#define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
|
||||
|
||||
/**@} end of group I2C_FIFO_Register */
|
||||
|
||||
|
|
@ -490,17 +498,17 @@ typedef struct {
|
|||
* @brief Master Control Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_MSTR_MODE_START_POS 0 /**< MSTR_MODE_START Position */
|
||||
#define MXC_F_I2C_MSTR_MODE_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_START_POS)) /**< MSTR_MODE_START Mask */
|
||||
#define MXC_F_I2C_MSTR_MODE_START_POS 0 /**< MSTR_MODE_START Position */
|
||||
#define MXC_F_I2C_MSTR_MODE_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_START_POS)) /**< MSTR_MODE_START Mask */
|
||||
|
||||
#define MXC_F_I2C_MSTR_MODE_RESTART_POS 1 /**< MSTR_MODE_RESTART Position */
|
||||
#define MXC_F_I2C_MSTR_MODE_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_RESTART_POS)) /**< MSTR_MODE_RESTART Mask */
|
||||
#define MXC_F_I2C_MSTR_MODE_RESTART_POS 1 /**< MSTR_MODE_RESTART Position */
|
||||
#define MXC_F_I2C_MSTR_MODE_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_RESTART_POS)) /**< MSTR_MODE_RESTART Mask */
|
||||
|
||||
#define MXC_F_I2C_MSTR_MODE_STOP_POS 2 /**< MSTR_MODE_STOP Position */
|
||||
#define MXC_F_I2C_MSTR_MODE_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_STOP_POS)) /**< MSTR_MODE_STOP Mask */
|
||||
#define MXC_F_I2C_MSTR_MODE_STOP_POS 2 /**< MSTR_MODE_STOP Position */
|
||||
#define MXC_F_I2C_MSTR_MODE_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_STOP_POS)) /**< MSTR_MODE_STOP Mask */
|
||||
|
||||
#define MXC_F_I2C_MSTR_MODE_SEA_POS 7 /**< MSTR_MODE_SEA Position */
|
||||
#define MXC_F_I2C_MSTR_MODE_SEA ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_SEA_POS)) /**< MSTR_MODE_SEA Mask */
|
||||
#define MXC_F_I2C_MSTR_MODE_SEA_POS 7 /**< MSTR_MODE_SEA Position */
|
||||
#define MXC_F_I2C_MSTR_MODE_SEA ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_SEA_POS)) /**< MSTR_MODE_SEA Mask */
|
||||
|
||||
/**@} end of group I2C_MSTR_MODE_Register */
|
||||
|
||||
|
|
@ -510,8 +518,8 @@ typedef struct {
|
|||
* @brief Clock Low Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_CLKLO_SCL_LO_POS 0 /**< CLKLO_SCL_LO Position */
|
||||
#define MXC_F_I2C_CLKLO_SCL_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_SCL_LO_POS)) /**< CLKLO_SCL_LO Mask */
|
||||
#define MXC_F_I2C_CLKLO_SCL_LO_POS 0 /**< CLKLO_SCL_LO Position */
|
||||
#define MXC_F_I2C_CLKLO_SCL_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_SCL_LO_POS)) /**< CLKLO_SCL_LO Mask */
|
||||
|
||||
/**@} end of group I2C_CLKLO_Register */
|
||||
|
||||
|
|
@ -521,8 +529,8 @@ typedef struct {
|
|||
* @brief Clock high Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_CLKHI_SCL_HI_POS 0 /**< CLKHI_SCL_HI Position */
|
||||
#define MXC_F_I2C_CLKHI_SCL_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_SCL_HI_POS)) /**< CLKHI_SCL_HI Mask */
|
||||
#define MXC_F_I2C_CLKHI_SCL_HI_POS 0 /**< CLKHI_SCL_HI Position */
|
||||
#define MXC_F_I2C_CLKHI_SCL_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_SCL_HI_POS)) /**< CLKHI_SCL_HI Mask */
|
||||
|
||||
/**@} end of group I2C_CLKHI_Register */
|
||||
|
||||
|
|
@ -532,11 +540,11 @@ typedef struct {
|
|||
* @brief HS-Mode Clock Control Register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 /**< HS_CLK_HS_CLK_LO Position */
|
||||
#define MXC_F_I2C_HS_CLK_HS_CLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) /**< HS_CLK_HS_CLK_LO Mask */
|
||||
#define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 /**< HS_CLK_HS_CLK_LO Position */
|
||||
#define MXC_F_I2C_HS_CLK_HS_CLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) /**< HS_CLK_HS_CLK_LO Mask */
|
||||
|
||||
#define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 /**< HS_CLK_HS_CLK_HI Position */
|
||||
#define MXC_F_I2C_HS_CLK_HS_CLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) /**< HS_CLK_HS_CLK_HI Mask */
|
||||
#define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 /**< HS_CLK_HS_CLK_HI Position */
|
||||
#define MXC_F_I2C_HS_CLK_HS_CLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) /**< HS_CLK_HS_CLK_HI Mask */
|
||||
|
||||
/**@} end of group I2C_HS_CLK_Register */
|
||||
|
||||
|
|
@ -546,8 +554,8 @@ typedef struct {
|
|||
* @brief Timeout Register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */
|
||||
#define MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */
|
||||
#define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */
|
||||
#define MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */
|
||||
|
||||
/**@} end of group I2C_TIMEOUT_Register */
|
||||
|
||||
|
|
@ -557,11 +565,17 @@ typedef struct {
|
|||
* @brief Slave Address Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_SLADDR_SLA_POS 0 /**< SLADDR_SLA Position */
|
||||
#define MXC_F_I2C_SLADDR_SLA ((uint32_t)(0x3FFUL << MXC_F_I2C_SLADDR_SLA_POS)) /**< SLADDR_SLA Mask */
|
||||
#define MXC_F_I2C_SLADDR_SLA_POS 0 /**< SLADDR_SLA Position */
|
||||
#define MXC_F_I2C_SLADDR_SLA ((uint32_t)(0x3FFUL << MXC_F_I2C_SLADDR_SLA_POS)) /**< SLADDR_SLA Mask */
|
||||
|
||||
#define MXC_F_I2C_SLADDR_EA_POS 15 /**< SLADDR_EA Position */
|
||||
#define MXC_F_I2C_SLADDR_EA ((uint32_t)(0x1UL << MXC_F_I2C_SLADDR_EA_POS)) /**< SLADDR_EA Mask */
|
||||
#define MXC_F_I2C_SLADDR_SLADIS_POS 10 /**< SLADDR_SLADIS Position */
|
||||
#define MXC_F_I2C_SLADDR_SLADIS ((uint32_t)(0x1UL << MXC_F_I2C_SLADDR_SLADIS_POS)) /**< SLADDR_SLADIS Mask */
|
||||
|
||||
#define MXC_F_I2C_SLADDR_SLAIDX_POS 11 /**< SLADDR_SLAIDX Position */
|
||||
#define MXC_F_I2C_SLADDR_SLAIDX ((uint32_t)(0xFUL << MXC_F_I2C_SLADDR_SLAIDX_POS)) /**< SLADDR_SLAIDX Mask */
|
||||
|
||||
#define MXC_F_I2C_SLADDR_EA_POS 15 /**< SLADDR_EA Position */
|
||||
#define MXC_F_I2C_SLADDR_EA ((uint32_t)(0x1UL << MXC_F_I2C_SLADDR_EA_POS)) /**< SLADDR_EA Mask */
|
||||
|
||||
/**@} end of group I2C_SLADDR_Register */
|
||||
|
||||
|
|
@ -571,11 +585,11 @@ typedef struct {
|
|||
* @brief DMA Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2C_DMA_TXEN_POS 0 /**< DMA_TXEN Position */
|
||||
#define MXC_F_I2C_DMA_TXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TXEN_POS)) /**< DMA_TXEN Mask */
|
||||
#define MXC_F_I2C_DMA_TXEN_POS 0 /**< DMA_TXEN Position */
|
||||
#define MXC_F_I2C_DMA_TXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TXEN_POS)) /**< DMA_TXEN Mask */
|
||||
|
||||
#define MXC_F_I2C_DMA_RXEN_POS 1 /**< DMA_RXEN Position */
|
||||
#define MXC_F_I2C_DMA_RXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RXEN_POS)) /**< DMA_RXEN Mask */
|
||||
#define MXC_F_I2C_DMA_RXEN_POS 1 /**< DMA_RXEN Position */
|
||||
#define MXC_F_I2C_DMA_RXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RXEN_POS)) /**< DMA_RXEN Mask */
|
||||
|
||||
/**@} end of group I2C_DMA_Register */
|
||||
|
||||
|
|
@ -583,4 +597,4 @@ typedef struct {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _I2C_REGS_H_ */
|
||||
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_I2C_REGS_H_
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
/**
|
||||
* @file icc_regs.h
|
||||
* @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module.
|
||||
* @note This file is @generated.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +35,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _ICC_REGS_H_
|
||||
#define _ICC_REGS_H_
|
||||
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_ICC_REGS_H_
|
||||
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_ICC_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -46,11 +46,11 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__ICCARM__)
|
||||
#pragma system_include
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__CC_ARM)
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
|
@ -67,7 +67,9 @@ extern "C" {
|
|||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
|
||||
#ifndef __R
|
||||
#define __R volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
|
@ -76,7 +78,7 @@ extern "C" {
|
|||
* @ingroup icc
|
||||
* @defgroup icc_registers ICC_Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module.
|
||||
* @details Instruction Cache Controller Registers
|
||||
* @details Instruction Cache Controller Registers
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
@ -86,9 +88,9 @@ extern "C" {
|
|||
typedef struct {
|
||||
__I uint32_t cache_id; /**< <tt>\b 0x0000:</tt> ICC CACHE_ID Register */
|
||||
__I uint32_t mem_size; /**< <tt>\b 0x0004:</tt> ICC MEM_SIZE Register */
|
||||
__I uint32_t rsv_0x8_0xff[62];
|
||||
__R uint32_t rsv_0x8_0xff[62];
|
||||
__IO uint32_t cache_ctrl; /**< <tt>\b 0x0100:</tt> ICC CACHE_CTRL Register */
|
||||
__I uint32_t rsv_0x104_0x6ff[383];
|
||||
__R uint32_t rsv_0x104_0x6ff[383];
|
||||
__IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> ICC INVALIDATE Register */
|
||||
} mxc_icc_regs_t;
|
||||
|
||||
|
|
@ -96,13 +98,13 @@ typedef struct {
|
|||
/**
|
||||
* @ingroup icc_registers
|
||||
* @defgroup ICC_Register_Offsets Register Offsets
|
||||
* @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address.
|
||||
* @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_ICC_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_ICC_MEM_SIZE ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_ICC_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt> 0x0100</tt> */
|
||||
#define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt> 0x0700</tt> */
|
||||
#define MXC_R_ICC_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_ICC_MEM_SIZE ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_ICC_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt> 0x0100</tt> */
|
||||
#define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt> 0x0700</tt> */
|
||||
/**@} end of group icc_registers */
|
||||
|
||||
/**
|
||||
|
|
@ -111,14 +113,14 @@ typedef struct {
|
|||
* @brief Cache ID Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ICC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */
|
||||
#define MXC_F_ICC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */
|
||||
#define MXC_F_ICC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */
|
||||
#define MXC_F_ICC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */
|
||||
|
||||
#define MXC_F_ICC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */
|
||||
#define MXC_F_ICC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */
|
||||
#define MXC_F_ICC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */
|
||||
#define MXC_F_ICC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */
|
||||
|
||||
#define MXC_F_ICC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */
|
||||
#define MXC_F_ICC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */
|
||||
#define MXC_F_ICC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */
|
||||
#define MXC_F_ICC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */
|
||||
|
||||
/**@} end of group ICC_CACHE_ID_Register */
|
||||
|
||||
|
|
@ -128,11 +130,11 @@ typedef struct {
|
|||
* @brief Memory Configuration Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ICC_MEM_SIZE_CCHSZ_POS 0 /**< MEM_SIZE_CCHSZ Position */
|
||||
#define MXC_F_ICC_MEM_SIZE_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEM_SIZE_CCHSZ_POS)) /**< MEM_SIZE_CCHSZ Mask */
|
||||
#define MXC_F_ICC_MEM_SIZE_CCHSZ_POS 0 /**< MEM_SIZE_CCHSZ Position */
|
||||
#define MXC_F_ICC_MEM_SIZE_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEM_SIZE_CCHSZ_POS)) /**< MEM_SIZE_CCHSZ Mask */
|
||||
|
||||
#define MXC_F_ICC_MEM_SIZE_MEMSZ_POS 16 /**< MEM_SIZE_MEMSZ Position */
|
||||
#define MXC_F_ICC_MEM_SIZE_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEM_SIZE_MEMSZ_POS)) /**< MEM_SIZE_MEMSZ Mask */
|
||||
#define MXC_F_ICC_MEM_SIZE_MEMSZ_POS 16 /**< MEM_SIZE_MEMSZ Position */
|
||||
#define MXC_F_ICC_MEM_SIZE_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEM_SIZE_MEMSZ_POS)) /**< MEM_SIZE_MEMSZ Mask */
|
||||
|
||||
/**@} end of group ICC_MEM_SIZE_Register */
|
||||
|
||||
|
|
@ -142,11 +144,11 @@ typedef struct {
|
|||
* @brief Cache Control and Status Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ICC_CACHE_CTRL_ENABLE_POS 0 /**< CACHE_CTRL_ENABLE Position */
|
||||
#define MXC_F_ICC_CACHE_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_ENABLE_POS)) /**< CACHE_CTRL_ENABLE Mask */
|
||||
#define MXC_F_ICC_CACHE_CTRL_ENABLE_POS 0 /**< CACHE_CTRL_ENABLE Position */
|
||||
#define MXC_F_ICC_CACHE_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_ENABLE_POS)) /**< CACHE_CTRL_ENABLE Mask */
|
||||
|
||||
#define MXC_F_ICC_CACHE_CTRL_READY_POS 16 /**< CACHE_CTRL_READY Position */
|
||||
#define MXC_F_ICC_CACHE_CTRL_READY ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_READY_POS)) /**< CACHE_CTRL_READY Mask */
|
||||
#define MXC_F_ICC_CACHE_CTRL_READY_POS 16 /**< CACHE_CTRL_READY Position */
|
||||
#define MXC_F_ICC_CACHE_CTRL_READY ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_READY_POS)) /**< CACHE_CTRL_READY Mask */
|
||||
|
||||
/**@} end of group ICC_CACHE_CTRL_Register */
|
||||
|
||||
|
|
@ -154,4 +156,4 @@ typedef struct {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ICC_REGS_H_ */
|
||||
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_ICC_REGS_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Device-specific perhiperal header file
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,36 +34,35 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _MAX32660_REGS_H_
|
||||
#define _MAX32660_REGS_H_
|
||||
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_MAX32660_H_
|
||||
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_MAX32660_H_
|
||||
|
||||
#ifndef TARGET_NUM
|
||||
#define TARGET_NUM 32660
|
||||
#define TARGET_NUM 32660
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE (0)
|
||||
#ifndef FALSE
|
||||
#define FALSE (0)
|
||||
#endif
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE (1)
|
||||
#ifndef TRUE
|
||||
#define TRUE (1)
|
||||
#endif
|
||||
|
||||
#if !defined (__GNUC__)
|
||||
#if !defined(__GNUC__)
|
||||
#define CMSIS_VECTAB_VIRTUAL
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h"
|
||||
#endif /* !__GNUC__ */
|
||||
|
||||
/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
|
||||
#if defined ( __GNUC__ ) /* GCC */
|
||||
#if defined(__GNUC__) /* GCC */
|
||||
#define __weak __attribute__((weak))
|
||||
|
||||
#elif defined ( __CC_ARM) /* Keil */
|
||||
#elif defined(__CC_ARM) /* Keil */
|
||||
|
||||
#define inline __inline
|
||||
#pragma anon_unions
|
||||
|
|
@ -71,15 +70,15 @@
|
|||
#endif
|
||||
|
||||
typedef enum {
|
||||
NonMaskableInt_IRQn = -14,
|
||||
HardFault_IRQn = -13,
|
||||
MemoryManagement_IRQn = -12,
|
||||
BusFault_IRQn = -11,
|
||||
UsageFault_IRQn = -10,
|
||||
SVCall_IRQn = -5,
|
||||
DebugMonitor_IRQn = -4,
|
||||
PendSV_IRQn = -2,
|
||||
SysTick_IRQn = -1,
|
||||
NonMaskableInt_IRQn = -14,
|
||||
HardFault_IRQn = -13,
|
||||
MemoryManagement_IRQn = -12,
|
||||
BusFault_IRQn = -11,
|
||||
UsageFault_IRQn = -10,
|
||||
SVCall_IRQn = -5,
|
||||
DebugMonitor_IRQn = -4,
|
||||
PendSV_IRQn = -2,
|
||||
SysTick_IRQn = -1,
|
||||
|
||||
/* Device-specific interrupt sources (external to ARM core) */
|
||||
/* table entry number */
|
||||
|
|
@ -87,93 +86,91 @@ typedef enum {
|
|||
/* |||| table offset address */
|
||||
/* vvvv vvvvvv */
|
||||
|
||||
PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */
|
||||
WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */
|
||||
RSV00_IRQn, /* 0x12 0x0048 18: RSV00 */
|
||||
RTC_IRQn, /* 0x13 0x004C 19: RTC */
|
||||
RSV1_IRQn, /* 0x14 0x0050 20: RSV1 */
|
||||
TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */
|
||||
TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */
|
||||
TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */
|
||||
RSV02_IRQn, /* 0x18 0x0060 24: RSV02 */
|
||||
RSV03_IRQn, /* 0x19 0x0064 25: RSV03 */
|
||||
RSV04_IRQn, /* 0x1A 0x0068 26: RSV04 */
|
||||
RSV05_IRQn, /* 0x1B 0x006C 27: RSV05 */
|
||||
RSV06_IRQn, /* 0x1C 0x0070 28: RSV06 */
|
||||
I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */
|
||||
UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */
|
||||
UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */
|
||||
SPI0_IRQn, /* 0x20 0x0080 32: SPI17Y */
|
||||
SPIMSS_IRQn, /* 0x21 0x0084 33: SPIMSS */
|
||||
RSV07_IRQn, /* 0x22 0x0088 34: RSV07 */
|
||||
RSV08_IRQn, /* 0x23 0x008C 35: RSV08 */
|
||||
RSV09_IRQn, /* 0x24 0x0090 36: RSV09 */
|
||||
RSV10_IRQn, /* 0x25 0x0094 37: RSV10 */
|
||||
RSV11_IRQn, /* 0x26 0x0098 38: RSV11 */
|
||||
FLC_IRQn, /* 0x27 0x009C 39: FLC */
|
||||
GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */
|
||||
RSV12_IRQn, /* 0x29 0x00A4 41: RSV12 */
|
||||
RSV13_IRQn, /* 0x2A 0x00A8 42: RSV13 */
|
||||
RSV14_IRQn, /* 0x2B 0x00AC 43: RSV14 */
|
||||
DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */
|
||||
DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */
|
||||
DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */
|
||||
DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */
|
||||
RSV15_IRQn, /* 0x30 0x00C0 48: RSV15 */
|
||||
RSV16_IRQn, /* 0x31 0x00C4 49: RSV16 */
|
||||
RSV17_IRQn, /* 0x32 0x00C8 50: RSV17 */
|
||||
RSV18_IRQn, /* 0x33 0x00CC 51: RSV18 */
|
||||
I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */
|
||||
RSV19_IRQn, /* 0x35 0x00D4 53: RSV19 */
|
||||
RSV20_IRQn, /* 0x36 0x00D8 54: RSV20 */
|
||||
RSV21_IRQn, /* 0x37 0x00DC 55: RSV21 */
|
||||
RSV22_IRQn, /* 0x38 0x00E0 56: RSV22 */
|
||||
RSV23_IRQn, /* 0x39 0x00E4 57: RSV23 */
|
||||
RSV24_IRQn, /* 0x3A 0x00E8 58: RSV24 */
|
||||
RSV25_IRQn, /* 0x3B 0x00EC 59: RSV25 */
|
||||
RSV26_IRQn, /* 0x3C 0x00F0 60: RSV26 */
|
||||
RSV27_IRQn, /* 0x3D 0x00F4 61: RSV27 */
|
||||
RSV28_IRQn, /* 0x3E 0x00F8 62: RSV28 */
|
||||
RSV29_IRQn, /* 0x3F 0x00FC 63: RSV29 */
|
||||
RSV30_IRQn, /* 0x40 0x0100 64: RSV30 */
|
||||
RSV31_IRQn, /* 0x41 0x0104 65: RSV31 */
|
||||
RSV32_IRQn, /* 0x42 0x0108 66: RSV32 */
|
||||
RSV33_IRQn, /* 0x43 0x010C 67: RSV33 */
|
||||
RSV34_IRQn, /* 0x44 0x0110 68: RSV34 */
|
||||
RSV35_IRQn, /* 0x45 0x0114 69: RSV35 */
|
||||
GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */
|
||||
PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */
|
||||
WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */
|
||||
RSV00_IRQn, /* 0x12 0x0048 18: RSV00 */
|
||||
RTC_IRQn, /* 0x13 0x004C 19: RTC */
|
||||
RSV1_IRQn, /* 0x14 0x0050 20: RSV1 */
|
||||
TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */
|
||||
TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */
|
||||
TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */
|
||||
RSV02_IRQn, /* 0x18 0x0060 24: RSV02 */
|
||||
RSV03_IRQn, /* 0x19 0x0064 25: RSV03 */
|
||||
RSV04_IRQn, /* 0x1A 0x0068 26: RSV04 */
|
||||
RSV05_IRQn, /* 0x1B 0x006C 27: RSV05 */
|
||||
RSV06_IRQn, /* 0x1C 0x0070 28: RSV06 */
|
||||
I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */
|
||||
UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */
|
||||
UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */
|
||||
SPI0_IRQn, /* 0x20 0x0080 32: SPI17Y */
|
||||
SPIMSS_IRQn, /* 0x21 0x0084 33: SPIMSS */
|
||||
RSV07_IRQn, /* 0x22 0x0088 34: RSV07 */
|
||||
RSV08_IRQn, /* 0x23 0x008C 35: RSV08 */
|
||||
RSV09_IRQn, /* 0x24 0x0090 36: RSV09 */
|
||||
RSV10_IRQn, /* 0x25 0x0094 37: RSV10 */
|
||||
RSV11_IRQn, /* 0x26 0x0098 38: RSV11 */
|
||||
FLC_IRQn, /* 0x27 0x009C 39: FLC */
|
||||
GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */
|
||||
RSV12_IRQn, /* 0x29 0x00A4 41: RSV12 */
|
||||
RSV13_IRQn, /* 0x2A 0x00A8 42: RSV13 */
|
||||
RSV14_IRQn, /* 0x2B 0x00AC 43: RSV14 */
|
||||
DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */
|
||||
DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */
|
||||
DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */
|
||||
DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */
|
||||
RSV15_IRQn, /* 0x30 0x00C0 48: RSV15 */
|
||||
RSV16_IRQn, /* 0x31 0x00C4 49: RSV16 */
|
||||
RSV17_IRQn, /* 0x32 0x00C8 50: RSV17 */
|
||||
RSV18_IRQn, /* 0x33 0x00CC 51: RSV18 */
|
||||
I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */
|
||||
RSV19_IRQn, /* 0x35 0x00D4 53: RSV19 */
|
||||
RSV20_IRQn, /* 0x36 0x00D8 54: RSV20 */
|
||||
RSV21_IRQn, /* 0x37 0x00DC 55: RSV21 */
|
||||
RSV22_IRQn, /* 0x38 0x00E0 56: RSV22 */
|
||||
RSV23_IRQn, /* 0x39 0x00E4 57: RSV23 */
|
||||
RSV24_IRQn, /* 0x3A 0x00E8 58: RSV24 */
|
||||
RSV25_IRQn, /* 0x3B 0x00EC 59: RSV25 */
|
||||
RSV26_IRQn, /* 0x3C 0x00F0 60: RSV26 */
|
||||
RSV27_IRQn, /* 0x3D 0x00F4 61: RSV27 */
|
||||
RSV28_IRQn, /* 0x3E 0x00F8 62: RSV28 */
|
||||
RSV29_IRQn, /* 0x3F 0x00FC 63: RSV29 */
|
||||
RSV30_IRQn, /* 0x40 0x0100 64: RSV30 */
|
||||
RSV31_IRQn, /* 0x41 0x0104 65: RSV31 */
|
||||
RSV32_IRQn, /* 0x42 0x0108 66: RSV32 */
|
||||
RSV33_IRQn, /* 0x43 0x010C 67: RSV33 */
|
||||
RSV34_IRQn, /* 0x44 0x0110 68: RSV34 */
|
||||
RSV35_IRQn, /* 0x45 0x0114 69: RSV35 */
|
||||
GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */
|
||||
MXC_IRQ_EXT_COUNT,
|
||||
} IRQn_Type;
|
||||
|
||||
#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Processor and Core Peripheral Section ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
|
||||
#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present or not */
|
||||
|
||||
#include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
|
||||
#include "system_max32660.h" /*!< System Header */
|
||||
#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present or not */
|
||||
|
||||
#include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
|
||||
#include "system_max32660.h" /*!< System Header */
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================== Device Specific Memory Section ================== */
|
||||
/* ================================================================================ */
|
||||
|
||||
#define MXC_FLASH_MEM_BASE 0x00000000UL
|
||||
#define MXC_FLASH_PAGE_SIZE 0x00002000UL
|
||||
#define MXC_FLASH_MEM_SIZE 0x00040000UL
|
||||
#define MXC_INFO_MEM_BASE 0x00040000UL
|
||||
#define MXC_INFO_MEM_SIZE 0x00001000UL
|
||||
#define MXC_SRAM_MEM_BASE 0x20000000UL
|
||||
#define MXC_SRAM_MEM_SIZE 0x00018000UL
|
||||
#define MXC_FLASH_MEM_BASE 0x00000000UL
|
||||
#define MXC_FLASH_PAGE_SIZE 0x00002000UL
|
||||
#define MXC_FLASH_MEM_SIZE 0x00040000UL
|
||||
#define MXC_INFO_MEM_BASE 0x00040000UL
|
||||
#define MXC_INFO_MEM_SIZE 0x00001000UL
|
||||
#define MXC_SRAM_MEM_BASE 0x20000000UL
|
||||
#define MXC_SRAM_MEM_SIZE 0x00018000UL
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Device Specific Peripheral Section ================ */
|
||||
|
|
@ -185,224 +182,209 @@ typedef enum {
|
|||
|
||||
/******************************************************************************/
|
||||
/* Global control */
|
||||
#define MXC_BASE_GCR ((uint32_t)0x40000000UL)
|
||||
#define MXC_GCR ((mxc_gcr_regs_t*)MXC_BASE_GCR)
|
||||
#define MXC_BASE_GCR ((uint32_t)0x40000000UL)
|
||||
#define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR)
|
||||
|
||||
/******************************************************************************/
|
||||
/* Non-battery backed SI Registers */
|
||||
#define MXC_BASE_SIR ((uint32_t)0x40000400UL)
|
||||
#define MXC_SIR ((mxc_sir_regs_t*)MXC_BASE_SIR)
|
||||
#define MXC_BASE_SIR ((uint32_t)0x40000400UL)
|
||||
#define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR)
|
||||
|
||||
/******************************************************************************/
|
||||
/* Watchdog */
|
||||
#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
|
||||
#define MXC_WDT0 ((mxc_wdt_regs_t*)MXC_BASE_WDT0)
|
||||
#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
|
||||
#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
|
||||
|
||||
/******************************************************************************/
|
||||
/* Real Time Clock */
|
||||
#define MXC_BASE_RTC ((uint32_t)0x40006000UL)
|
||||
#define MXC_RTC ((mxc_rtc_regs_t*)MXC_BASE_RTC)
|
||||
#define MXC_BASE_RTC ((uint32_t)0x40006000UL)
|
||||
#define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC)
|
||||
|
||||
/******************************************************************************/
|
||||
/* Power Sequencer */
|
||||
#define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL)
|
||||
#define MXC_PWRSEQ ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ)
|
||||
|
||||
#define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL)
|
||||
#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
|
||||
|
||||
/******************************************************************************/
|
||||
/* GPIO */
|
||||
#define MXC_CFG_GPIO_INSTANCES (1)
|
||||
#define MXC_CFG_GPIO_PINS_PORT (14)
|
||||
#define MXC_CFG_GPIO_INSTANCES (1)
|
||||
#define MXC_CFG_GPIO_PINS_PORT (14)
|
||||
|
||||
#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
|
||||
#define MXC_GPIO0 ((mxc_gpio_regs_t*)MXC_BASE_GPIO0)
|
||||
#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
|
||||
#define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0)
|
||||
|
||||
#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 :-1)
|
||||
#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : -1)
|
||||
|
||||
#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : 0)
|
||||
#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : 0)
|
||||
|
||||
#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : 0)
|
||||
#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : 0)
|
||||
|
||||
/******************************************************************************/
|
||||
/* Timer */
|
||||
#define MXC_CFG_TMR_INSTANCES (3)
|
||||
#define SEC(s) (((uint32_t)s) * 1000000UL)
|
||||
#define MSEC(ms) (ms * 1000UL)
|
||||
#define USEC(us) (us)
|
||||
|
||||
#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
|
||||
#define MXC_TMR0 ((mxc_tmr_regs_t*)MXC_BASE_TMR0)
|
||||
#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
|
||||
#define MXC_TMR1 ((mxc_tmr_regs_t*)MXC_BASE_TMR1)
|
||||
#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
|
||||
#define MXC_TMR2 ((mxc_tmr_regs_t*)MXC_BASE_TMR2)
|
||||
#define MXC_CFG_TMR_INSTANCES (3)
|
||||
|
||||
#define MXC_TMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? TMR0_IRQn : \
|
||||
(i) == 1 ? TMR1_IRQn : \
|
||||
(i) == 2 ? TMR2_IRQn : 0)
|
||||
#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
|
||||
#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0)
|
||||
#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
|
||||
#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1)
|
||||
#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
|
||||
#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
|
||||
|
||||
#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
|
||||
(i) == 1 ? MXC_BASE_TMR1 : \
|
||||
(i) == 2 ? MXC_BASE_TMR2 : 0)
|
||||
#define MXC_TMR_GET_IRQ(i) \
|
||||
(IRQn_Type)((i) == 0 ? TMR0_IRQn : (i) == 1 ? TMR1_IRQn : (i) == 2 ? TMR2_IRQn : 0)
|
||||
|
||||
#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
|
||||
(i) == 1 ? MXC_TMR1 : \
|
||||
(i) == 2 ? MXC_TMR2 : 0)
|
||||
#define MXC_TMR_GET_BASE(i) \
|
||||
((i) == 0 ? MXC_BASE_TMR0 : (i) == 1 ? MXC_BASE_TMR1 : (i) == 2 ? MXC_BASE_TMR2 : 0)
|
||||
|
||||
#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
|
||||
(p) == MXC_TMR1 ? 1 : \
|
||||
(p) == MXC_TMR2 ? 2 : -1)
|
||||
#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : (i) == 1 ? MXC_TMR1 : (i) == 2 ? MXC_TMR2 : 0)
|
||||
|
||||
#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : (p) == MXC_TMR1 ? 1 : (p) == MXC_TMR2 ? 2 : -1)
|
||||
|
||||
/******************************************************************************/
|
||||
/* SPIMSS */
|
||||
#define MXC_SPIMSS_INSTANCES (1)
|
||||
#define MXC_SPIMSS_FIFO_DEPTH (8)
|
||||
|
||||
#define MXC_SPIMSS_INSTANCES (1)
|
||||
#define MXC_SPIMSS_FIFO_DEPTH (8)
|
||||
#define MXC_BASE_SPIMSS ((uint32_t)0x40019000UL)
|
||||
#define MXC_SPIMSS ((mxc_spimss_regs_t *)MXC_BASE_SPIMSS)
|
||||
|
||||
#define MXC_BASE_SPIMSS ((uint32_t)0x40019000UL)
|
||||
#define MXC_SPIMSS ((mxc_spimss_regs_t*)MXC_BASE_SPIMSS)
|
||||
|
||||
#define MXC_SPIMSS_GET_IDX(p) ((p) == MXC_SPIMSS ? 0 : -1)
|
||||
#define MXC_SPIMSS_GET_SPI(i) ((i) == 0 ? MXC_SPIMSS : 0)
|
||||
#define MXC_SPIMSS_GET_IDX(p) ((p) == MXC_SPIMSS ? 0 : -1)
|
||||
#define MXC_SPIMSS_GET_SPI(i) ((i) == 0 ? MXC_SPIMSS : 0)
|
||||
|
||||
/******************************************************************************/
|
||||
/* I2C */
|
||||
#define MXC_I2C_INSTANCES (2)
|
||||
#define MXC_I2C_FIFO_DEPTH (8)
|
||||
#define MXC_I2C_INSTANCES (2)
|
||||
#define MXC_I2C_FIFO_DEPTH (8)
|
||||
|
||||
#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL)
|
||||
#define MXC_I2C0 ((mxc_i2c_regs_t*)MXC_BASE_I2C0)
|
||||
#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL)
|
||||
#define MXC_I2C1 ((mxc_i2c_regs_t*)MXC_BASE_I2C1)
|
||||
#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL)
|
||||
#define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0)
|
||||
#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL)
|
||||
#define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1)
|
||||
|
||||
#define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : \
|
||||
(i) == 1 ? I2C1_IRQn : 0)
|
||||
#define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : 0)
|
||||
|
||||
#define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : \
|
||||
(i) == 1 ? MXC_BASE_I2C1 : 0)
|
||||
#define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : 0)
|
||||
|
||||
#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : \
|
||||
(i) == 1 ? MXC_I2C1 : 0)
|
||||
#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : 0)
|
||||
|
||||
#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : \
|
||||
(p) == MXC_I2C1 ? 1 : -1)
|
||||
#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : -1)
|
||||
|
||||
/******************************************************************************/
|
||||
/* DMA */
|
||||
#define MXC_DMA_CHANNELS (4)
|
||||
#define MXC_DMA_INSTANCES (1)
|
||||
#define MXC_DMA_CHANNELS (4)
|
||||
#define MXC_DMA_INSTANCES (1)
|
||||
|
||||
#define MXC_BASE_DMA ((uint32_t)0x40028000UL)
|
||||
#define MXC_DMA ((mxc_dma_regs_t*)MXC_BASE_DMA)
|
||||
#define MXC_BASE_DMA ((uint32_t)0x40028000UL)
|
||||
#define MXC_DMA ((mxc_dma_regs_t *)MXC_BASE_DMA)
|
||||
|
||||
#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1)
|
||||
#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1)
|
||||
|
||||
/******************************************************************************/
|
||||
/* FLC */
|
||||
#define MXC_FLC_INSTANCES (1)
|
||||
#define MXC_FLC_INSTANCES (1)
|
||||
|
||||
#define MXC_BASE_FLC ((uint32_t)0x40029000UL)
|
||||
#define MXC_FLC ((mxc_flc_regs_t*)MXC_BASE_FLC)
|
||||
#define MXC_BASE_FLC ((uint32_t)0x40029000UL)
|
||||
#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
|
||||
#define MXC_FLC0 MXC_FLC
|
||||
|
||||
#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC : 0)
|
||||
#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC : 0)
|
||||
|
||||
/******************************************************************************/
|
||||
/* Instruction Cache */
|
||||
#define MXC_BASE_ICC ((uint32_t)0x4002A000UL)
|
||||
#define MXC_ICC ((mxc_icc_regs_t*)MXC_BASE_ICC)
|
||||
#define MXC_BASE_ICC ((uint32_t)0x4002A000UL)
|
||||
#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
|
||||
|
||||
/******************************************************************************/
|
||||
/* UART / Serial Port Interface */
|
||||
#define MXC_UART_INSTANCES (2)
|
||||
#define MXC_UART_FIFO_DEPTH (8)
|
||||
|
||||
#define MXC_UART_INSTANCES (2)
|
||||
#define MXC_UART_FIFO_DEPTH (8)
|
||||
#define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
|
||||
#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
|
||||
#define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
|
||||
#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
|
||||
|
||||
#define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
|
||||
#define MXC_UART0 ((mxc_uart_regs_t*)MXC_BASE_UART0)
|
||||
#define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
|
||||
#define MXC_UART1 ((mxc_uart_regs_t*)MXC_BASE_UART1)
|
||||
#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : (i) == 1 ? UART1_IRQn : 0)
|
||||
|
||||
#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
|
||||
(i) == 1 ? UART1_IRQn : 0)
|
||||
#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : (i) == 1 ? MXC_BASE_UART1 : 0)
|
||||
|
||||
#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
|
||||
(i) == 1 ? MXC_BASE_UART1 : 0)
|
||||
#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : 0)
|
||||
|
||||
#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
|
||||
(i) == 1 ? MXC_UART1 : 0)
|
||||
|
||||
#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
|
||||
(p) == MXC_UART1 ? 1 : -1)
|
||||
#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : -1)
|
||||
|
||||
/******************************************************************************/
|
||||
/* SPI */
|
||||
#include "spi_regs.h"
|
||||
#define MXC_SPI_INSTANCES (1)
|
||||
#define MXC_SPI_SS_INSTANCES (1)
|
||||
#define MXC_SPI_FIFO_DEPTH (32)
|
||||
|
||||
#define MXC_SPI_INSTANCES (1)
|
||||
#define MXC_SPI_SS_INSTANCES (1)
|
||||
#define MXC_SPI_FIFO_DEPTH (32)
|
||||
#define MXC_BASE_SPI ((uint32_t)0x40046000UL)
|
||||
#define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI)
|
||||
|
||||
#define MXC_BASE_SPI ((uint32_t)0x40046000UL)
|
||||
#define MXC_SPI0 ((mxc_spi_regs_t*)MXC_BASE_SPI)
|
||||
#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : -1)
|
||||
|
||||
#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : -1)
|
||||
#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI : 0)
|
||||
|
||||
#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI : 0)
|
||||
|
||||
#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : 0)
|
||||
#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : 0)
|
||||
|
||||
/******************************************************************************/
|
||||
/* Bit Shifting */
|
||||
|
||||
#define MXC_F_BIT_0 (1 << 0)
|
||||
#define MXC_F_BIT_1 (1 << 1)
|
||||
#define MXC_F_BIT_2 (1 << 2)
|
||||
#define MXC_F_BIT_3 (1 << 3)
|
||||
#define MXC_F_BIT_4 (1 << 4)
|
||||
#define MXC_F_BIT_5 (1 << 5)
|
||||
#define MXC_F_BIT_6 (1 << 6)
|
||||
#define MXC_F_BIT_7 (1 << 7)
|
||||
#define MXC_F_BIT_8 (1 << 8)
|
||||
#define MXC_F_BIT_9 (1 << 9)
|
||||
#define MXC_F_BIT_10 (1 << 10)
|
||||
#define MXC_F_BIT_11 (1 << 11)
|
||||
#define MXC_F_BIT_12 (1 << 12)
|
||||
#define MXC_F_BIT_13 (1 << 13)
|
||||
#define MXC_F_BIT_14 (1 << 14)
|
||||
#define MXC_F_BIT_15 (1 << 15)
|
||||
#define MXC_F_BIT_16 (1 << 16)
|
||||
#define MXC_F_BIT_17 (1 << 17)
|
||||
#define MXC_F_BIT_18 (1 << 18)
|
||||
#define MXC_F_BIT_19 (1 << 19)
|
||||
#define MXC_F_BIT_20 (1 << 20)
|
||||
#define MXC_F_BIT_21 (1 << 21)
|
||||
#define MXC_F_BIT_22 (1 << 22)
|
||||
#define MXC_F_BIT_23 (1 << 23)
|
||||
#define MXC_F_BIT_24 (1 << 24)
|
||||
#define MXC_F_BIT_25 (1 << 25)
|
||||
#define MXC_F_BIT_26 (1 << 26)
|
||||
#define MXC_F_BIT_27 (1 << 27)
|
||||
#define MXC_F_BIT_28 (1 << 28)
|
||||
#define MXC_F_BIT_29 (1 << 29)
|
||||
#define MXC_F_BIT_30 (1 << 30)
|
||||
#define MXC_F_BIT_31 (1 << 31)
|
||||
#define MXC_F_BIT_0 (1 << 0)
|
||||
#define MXC_F_BIT_1 (1 << 1)
|
||||
#define MXC_F_BIT_2 (1 << 2)
|
||||
#define MXC_F_BIT_3 (1 << 3)
|
||||
#define MXC_F_BIT_4 (1 << 4)
|
||||
#define MXC_F_BIT_5 (1 << 5)
|
||||
#define MXC_F_BIT_6 (1 << 6)
|
||||
#define MXC_F_BIT_7 (1 << 7)
|
||||
#define MXC_F_BIT_8 (1 << 8)
|
||||
#define MXC_F_BIT_9 (1 << 9)
|
||||
#define MXC_F_BIT_10 (1 << 10)
|
||||
#define MXC_F_BIT_11 (1 << 11)
|
||||
#define MXC_F_BIT_12 (1 << 12)
|
||||
#define MXC_F_BIT_13 (1 << 13)
|
||||
#define MXC_F_BIT_14 (1 << 14)
|
||||
#define MXC_F_BIT_15 (1 << 15)
|
||||
#define MXC_F_BIT_16 (1 << 16)
|
||||
#define MXC_F_BIT_17 (1 << 17)
|
||||
#define MXC_F_BIT_18 (1 << 18)
|
||||
#define MXC_F_BIT_19 (1 << 19)
|
||||
#define MXC_F_BIT_20 (1 << 20)
|
||||
#define MXC_F_BIT_21 (1 << 21)
|
||||
#define MXC_F_BIT_22 (1 << 22)
|
||||
#define MXC_F_BIT_23 (1 << 23)
|
||||
#define MXC_F_BIT_24 (1 << 24)
|
||||
#define MXC_F_BIT_25 (1 << 25)
|
||||
#define MXC_F_BIT_26 (1 << 26)
|
||||
#define MXC_F_BIT_27 (1 << 27)
|
||||
#define MXC_F_BIT_28 (1 << 28)
|
||||
#define MXC_F_BIT_29 (1 << 29)
|
||||
#define MXC_F_BIT_30 (1 << 30)
|
||||
#define MXC_F_BIT_31 (1 << 31)
|
||||
|
||||
/******************************************************************************/
|
||||
/* Bit Banding */
|
||||
#define BITBAND(reg, bit) \
|
||||
((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \
|
||||
((bit) << 2))
|
||||
|
||||
#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \
|
||||
(((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
|
||||
#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
|
||||
#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
|
||||
#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
|
||||
|
||||
#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
|
||||
#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
|
||||
#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
|
||||
|
||||
#define MXC_SETFIELD(reg, mask, value) (reg = (reg & ~mask) | (value & mask))
|
||||
#define MXC_SETFIELD(reg, mask, value) ((reg) = ((reg) & ~(mask)) | ((value) & (mask)))
|
||||
|
||||
/******************************************************************************/
|
||||
/* SCB CPACR */
|
||||
|
||||
/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
|
||||
#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */
|
||||
#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */
|
||||
#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */
|
||||
#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */
|
||||
#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */
|
||||
#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */
|
||||
#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */
|
||||
#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */
|
||||
|
||||
#endif /* _MAX32660_REGS_H_ */
|
||||
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_MAX32660_H_
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
/**
|
||||
* @file pwrseq_regs.h
|
||||
* @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module.
|
||||
* @note This file is @generated.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +35,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _PWRSEQ_REGS_H_
|
||||
#define _PWRSEQ_REGS_H_
|
||||
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_PWRSEQ_REGS_H_
|
||||
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_PWRSEQ_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -46,11 +46,11 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__ICCARM__)
|
||||
#pragma system_include
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__CC_ARM)
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
|
@ -67,7 +67,9 @@ extern "C" {
|
|||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
|
||||
#ifndef __R
|
||||
#define __R volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
|
@ -76,7 +78,7 @@ extern "C" {
|
|||
* @ingroup pwrseq
|
||||
* @defgroup pwrseq_registers PWRSEQ_Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module.
|
||||
* @details Power Sequencer / Low Power Control Register.
|
||||
* @details Power Sequencer / Low Power Control Register.
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
@ -87,7 +89,7 @@ typedef struct {
|
|||
__IO uint32_t lp_ctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LP_CTRL Register */
|
||||
__IO uint32_t lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL Register */
|
||||
__IO uint32_t lpwk_en; /**< <tt>\b 0x08:</tt> PWRSEQ LPWK_EN Register */
|
||||
__I uint32_t rsv_0xc_0x3f[13];
|
||||
__R uint32_t rsv_0xc_0x3f[13];
|
||||
__IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
|
||||
} mxc_pwrseq_regs_t;
|
||||
|
||||
|
|
@ -95,13 +97,13 @@ typedef struct {
|
|||
/**
|
||||
* @ingroup pwrseq_registers
|
||||
* @defgroup PWRSEQ_Register_Offsets Register Offsets
|
||||
* @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address.
|
||||
* @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_PWRSEQ_LP_CTRL ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_PWRSEQ_LP_WAKEFL ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_PWRSEQ_LPWK_EN ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */
|
||||
#define MXC_R_PWRSEQ_LP_CTRL ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_PWRSEQ_LP_WAKEFL ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_PWRSEQ_LPWK_EN ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */
|
||||
/**@} end of group pwrseq_registers */
|
||||
|
||||
/**
|
||||
|
|
@ -110,50 +112,50 @@ typedef struct {
|
|||
* @brief Low Power Control Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS 0 /**< LP_CTRL_RAMRET_SEL0 Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< LP_CTRL_RAMRET_SEL0 Mask */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS 0 /**< LP_CTRL_RAMRET_SEL0 Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< LP_CTRL_RAMRET_SEL0 Mask */
|
||||
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS 1 /**< LP_CTRL_RAMRET_SEL1 Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< LP_CTRL_RAMRET_SEL1 Mask */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS 1 /**< LP_CTRL_RAMRET_SEL1 Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< LP_CTRL_RAMRET_SEL1 Mask */
|
||||
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS 2 /**< LP_CTRL_RAMRET_SEL2 Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< LP_CTRL_RAMRET_SEL2 Mask */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS 2 /**< LP_CTRL_RAMRET_SEL2 Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< LP_CTRL_RAMRET_SEL2 Mask */
|
||||
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS 3 /**< LP_CTRL_RAMRET_SEL3 Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< LP_CTRL_RAMRET_SEL3 Mask */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS 3 /**< LP_CTRL_RAMRET_SEL3 Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< LP_CTRL_RAMRET_SEL3 Mask */
|
||||
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */
|
||||
#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V ((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */
|
||||
#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */
|
||||
#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V ((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */
|
||||
#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */
|
||||
#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V ((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */
|
||||
#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */
|
||||
#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V ((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */
|
||||
#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */
|
||||
#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V ((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */
|
||||
#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */
|
||||
#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V ((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */
|
||||
#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */
|
||||
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS 6 /**< LP_CTRL_VCORE_DET_BYPASS Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< LP_CTRL_VCORE_DET_BYPASS Mask */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS 6 /**< LP_CTRL_VCORE_DET_BYPASS Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< LP_CTRL_VCORE_DET_BYPASS Mask */
|
||||
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS 8 /**< LP_CTRL_RETREG_EN Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN Mask */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS 8 /**< LP_CTRL_RETREG_EN Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN Mask */
|
||||
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS 10 /**< LP_CTRL_FAST_WK_EN Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< LP_CTRL_FAST_WK_EN Mask */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS 10 /**< LP_CTRL_FAST_WK_EN Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< LP_CTRL_FAST_WK_EN Mask */
|
||||
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF Mask */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF Mask */
|
||||
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS 12 /**< LP_CTRL_VCORE_POR_DIS Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< LP_CTRL_VCORE_POR_DIS Mask */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS 12 /**< LP_CTRL_VCORE_POR_DIS Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< LP_CTRL_VCORE_POR_DIS Mask */
|
||||
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS 16 /**< LP_CTRL_LDO_DIS Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS Mask */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS 16 /**< LP_CTRL_LDO_DIS Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS Mask */
|
||||
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS 20 /**< LP_CTRL_VCORE_SVM_DIS Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< LP_CTRL_VCORE_SVM_DIS Mask */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS 20 /**< LP_CTRL_VCORE_SVM_DIS Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< LP_CTRL_VCORE_SVM_DIS Mask */
|
||||
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS 25 /**< LP_CTRL_VDDIO_POR_DIS Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< LP_CTRL_VDDIO_POR_DIS Mask */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS 25 /**< LP_CTRL_VDDIO_POR_DIS Position */
|
||||
#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< LP_CTRL_VDDIO_POR_DIS Mask */
|
||||
|
||||
/**@} end of group PWRSEQ_LP_CTRL_Register */
|
||||
|
||||
|
|
@ -163,8 +165,8 @@ typedef struct {
|
|||
* @brief Low Power Mode Wakeup Flags for GPIO0
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */
|
||||
#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST Mask */
|
||||
#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */
|
||||
#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST Mask */
|
||||
|
||||
/**@} end of group PWRSEQ_LP_WAKEFL_Register */
|
||||
|
||||
|
|
@ -175,8 +177,8 @@ typedef struct {
|
|||
* functionality for GPIO0.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */
|
||||
#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN Mask */
|
||||
#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */
|
||||
#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN Mask */
|
||||
|
||||
/**@} end of group PWRSEQ_LPWK_EN_Register */
|
||||
|
||||
|
|
@ -186,17 +188,17 @@ typedef struct {
|
|||
* @brief Low Power Memory Shutdown Control.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS 0 /**< LPMEMSD_SRAM0_OFF Position */
|
||||
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF Mask */
|
||||
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS 0 /**< LPMEMSD_SRAM0_OFF Position */
|
||||
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF Mask */
|
||||
|
||||
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS 1 /**< LPMEMSD_SRAM1_OFF Position */
|
||||
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF Mask */
|
||||
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS 1 /**< LPMEMSD_SRAM1_OFF Position */
|
||||
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF Mask */
|
||||
|
||||
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS 2 /**< LPMEMSD_SRAM2_OFF Position */
|
||||
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF Mask */
|
||||
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS 2 /**< LPMEMSD_SRAM2_OFF Position */
|
||||
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF Mask */
|
||||
|
||||
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS 3 /**< LPMEMSD_SRAM3_OFF Position */
|
||||
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF Mask */
|
||||
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS 3 /**< LPMEMSD_SRAM3_OFF Position */
|
||||
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF Mask */
|
||||
|
||||
/**@} end of group PWRSEQ_LPMEMSD_Register */
|
||||
|
||||
|
|
@ -204,4 +206,4 @@ typedef struct {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _PWRSEQ_REGS_H_ */
|
||||
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_PWRSEQ_REGS_H_
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
/**
|
||||
* @file rtc_regs.h
|
||||
* @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
|
||||
* @note This file is @generated.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +35,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _RTC_REGS_H_
|
||||
#define _RTC_REGS_H_
|
||||
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_RTC_REGS_H_
|
||||
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_RTC_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -46,11 +46,11 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__ICCARM__)
|
||||
#pragma system_include
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__CC_ARM)
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
|
@ -78,7 +78,7 @@ extern "C" {
|
|||
* @ingroup rtc
|
||||
* @defgroup rtc_registers RTC_Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
|
||||
* @details Real Time Clock and Alarm.
|
||||
* @details Real Time Clock and Alarm.
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
@ -99,16 +99,16 @@ typedef struct {
|
|||
/**
|
||||
* @ingroup rtc_registers
|
||||
* @defgroup RTC_Register_Offsets Register Offsets
|
||||
* @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address.
|
||||
* @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_RTC_RAS ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_RTC_RSSA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: <tt> 0x000C</tt> */
|
||||
#define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: <tt> 0x0010</tt> */
|
||||
#define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: <tt> 0x0014</tt> */
|
||||
#define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: <tt> 0x0018</tt> */
|
||||
#define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_RTC_RAS ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_RTC_RSSA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: <tt> 0x000C</tt> */
|
||||
#define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: <tt> 0x0010</tt> */
|
||||
#define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: <tt> 0x0014</tt> */
|
||||
#define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: <tt> 0x0018</tt> */
|
||||
/**@} end of group rtc_registers */
|
||||
|
||||
/**
|
||||
|
|
@ -118,8 +118,8 @@ typedef struct {
|
|||
* when this register rolls over from 0xFF to 0x00.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_RTC_SSEC_RTSS_POS 0 /**< SSEC_RTSS Position */
|
||||
#define MXC_F_RTC_SSEC_RTSS ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_RTSS_POS)) /**< SSEC_RTSS Mask */
|
||||
#define MXC_F_RTC_SSEC_RTSS_POS 0 /**< SSEC_RTSS Position */
|
||||
#define MXC_F_RTC_SSEC_RTSS ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_RTSS_POS)) /**< SSEC_RTSS Mask */
|
||||
|
||||
/**@} end of group RTC_SSEC_Register */
|
||||
|
||||
|
|
@ -129,8 +129,8 @@ typedef struct {
|
|||
* @brief Time-of-day Alarm.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_RTC_RAS_RAS_POS 0 /**< RAS_RAS Position */
|
||||
#define MXC_F_RTC_RAS_RAS ((uint32_t)(0xFFFFFUL << MXC_F_RTC_RAS_RAS_POS)) /**< RAS_RAS Mask */
|
||||
#define MXC_F_RTC_RAS_RAS_POS 0 /**< RAS_RAS Position */
|
||||
#define MXC_F_RTC_RAS_RAS ((uint32_t)(0xFFFFFUL << MXC_F_RTC_RAS_RAS_POS)) /**< RAS_RAS Mask */
|
||||
|
||||
/**@} end of group RTC_RAS_Register */
|
||||
|
||||
|
|
@ -141,8 +141,8 @@ typedef struct {
|
|||
* second alarm.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_RTC_RSSA_RSSA_POS 0 /**< RSSA_RSSA Position */
|
||||
#define MXC_F_RTC_RSSA_RSSA ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_RSSA_RSSA_POS)) /**< RSSA_RSSA Mask */
|
||||
#define MXC_F_RTC_RSSA_RSSA_POS 0 /**< RSSA_RSSA Position */
|
||||
#define MXC_F_RTC_RSSA_RSSA ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_RSSA_RSSA_POS)) /**< RSSA_RSSA Mask */
|
||||
|
||||
/**@} end of group RTC_RSSA_Register */
|
||||
|
||||
|
|
@ -152,57 +152,57 @@ typedef struct {
|
|||
* @brief RTC Control Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_RTC_CTRL_RTCE_POS 0 /**< CTRL_RTCE Position */
|
||||
#define MXC_F_RTC_CTRL_RTCE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RTCE_POS)) /**< CTRL_RTCE Mask */
|
||||
#define MXC_F_RTC_CTRL_RTCE_POS 0 /**< CTRL_RTCE Position */
|
||||
#define MXC_F_RTC_CTRL_RTCE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RTCE_POS)) /**< CTRL_RTCE Mask */
|
||||
|
||||
#define MXC_F_RTC_CTRL_ADE_POS 1 /**< CTRL_ADE Position */
|
||||
#define MXC_F_RTC_CTRL_ADE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ADE_POS)) /**< CTRL_ADE Mask */
|
||||
#define MXC_F_RTC_CTRL_ADE_POS 1 /**< CTRL_ADE Position */
|
||||
#define MXC_F_RTC_CTRL_ADE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ADE_POS)) /**< CTRL_ADE Mask */
|
||||
|
||||
#define MXC_F_RTC_CTRL_ASE_POS 2 /**< CTRL_ASE Position */
|
||||
#define MXC_F_RTC_CTRL_ASE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ASE_POS)) /**< CTRL_ASE Mask */
|
||||
#define MXC_F_RTC_CTRL_ASE_POS 2 /**< CTRL_ASE Position */
|
||||
#define MXC_F_RTC_CTRL_ASE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ASE_POS)) /**< CTRL_ASE Mask */
|
||||
|
||||
#define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */
|
||||
#define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */
|
||||
#define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */
|
||||
#define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */
|
||||
|
||||
#define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */
|
||||
#define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
|
||||
#define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */
|
||||
#define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
|
||||
|
||||
#define MXC_F_RTC_CTRL_RDYE_POS 5 /**< CTRL_RDYE Position */
|
||||
#define MXC_F_RTC_CTRL_RDYE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDYE_POS)) /**< CTRL_RDYE Mask */
|
||||
#define MXC_F_RTC_CTRL_RDYE_POS 5 /**< CTRL_RDYE Position */
|
||||
#define MXC_F_RTC_CTRL_RDYE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDYE_POS)) /**< CTRL_RDYE Mask */
|
||||
|
||||
#define MXC_F_RTC_CTRL_ALDF_POS 6 /**< CTRL_ALDF Position */
|
||||
#define MXC_F_RTC_CTRL_ALDF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALDF_POS)) /**< CTRL_ALDF Mask */
|
||||
#define MXC_F_RTC_CTRL_ALDF_POS 6 /**< CTRL_ALDF Position */
|
||||
#define MXC_F_RTC_CTRL_ALDF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALDF_POS)) /**< CTRL_ALDF Mask */
|
||||
|
||||
#define MXC_F_RTC_CTRL_ALSF_POS 7 /**< CTRL_ALSF Position */
|
||||
#define MXC_F_RTC_CTRL_ALSF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALSF_POS)) /**< CTRL_ALSF Mask */
|
||||
#define MXC_F_RTC_CTRL_ALSF_POS 7 /**< CTRL_ALSF Position */
|
||||
#define MXC_F_RTC_CTRL_ALSF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALSF_POS)) /**< CTRL_ALSF Mask */
|
||||
|
||||
#define MXC_F_RTC_CTRL_SQE_POS 8 /**< CTRL_SQE Position */
|
||||
#define MXC_F_RTC_CTRL_SQE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQE_POS)) /**< CTRL_SQE Mask */
|
||||
#define MXC_F_RTC_CTRL_SQE_POS 8 /**< CTRL_SQE Position */
|
||||
#define MXC_F_RTC_CTRL_SQE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQE_POS)) /**< CTRL_SQE Mask */
|
||||
|
||||
#define MXC_F_RTC_CTRL_FT_POS 9 /**< CTRL_FT Position */
|
||||
#define MXC_F_RTC_CTRL_FT ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_FT_POS)) /**< CTRL_FT Mask */
|
||||
#define MXC_V_RTC_CTRL_FT_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_FT_FREQ1HZ Value */
|
||||
#define MXC_S_RTC_CTRL_FT_FREQ1HZ (MXC_V_RTC_CTRL_FT_FREQ1HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ1HZ Setting */
|
||||
#define MXC_V_RTC_CTRL_FT_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_FT_FREQ512HZ Value */
|
||||
#define MXC_S_RTC_CTRL_FT_FREQ512HZ (MXC_V_RTC_CTRL_FT_FREQ512HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ512HZ Setting */
|
||||
#define MXC_V_RTC_CTRL_FT_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_FT_FREQ4KHZ Value */
|
||||
#define MXC_S_RTC_CTRL_FT_FREQ4KHZ (MXC_V_RTC_CTRL_FT_FREQ4KHZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ4KHZ Setting */
|
||||
#define MXC_V_RTC_CTRL_FT_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_FT_CLKDIV8 Value */
|
||||
#define MXC_S_RTC_CTRL_FT_CLKDIV8 (MXC_V_RTC_CTRL_FT_CLKDIV8 << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_CLKDIV8 Setting */
|
||||
#define MXC_F_RTC_CTRL_FT_POS 9 /**< CTRL_FT Position */
|
||||
#define MXC_F_RTC_CTRL_FT ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_FT_POS)) /**< CTRL_FT Mask */
|
||||
#define MXC_V_RTC_CTRL_FT_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_FT_FREQ1HZ Value */
|
||||
#define MXC_S_RTC_CTRL_FT_FREQ1HZ (MXC_V_RTC_CTRL_FT_FREQ1HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ1HZ Setting */
|
||||
#define MXC_V_RTC_CTRL_FT_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_FT_FREQ512HZ Value */
|
||||
#define MXC_S_RTC_CTRL_FT_FREQ512HZ (MXC_V_RTC_CTRL_FT_FREQ512HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ512HZ Setting */
|
||||
#define MXC_V_RTC_CTRL_FT_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_FT_FREQ4KHZ Value */
|
||||
#define MXC_S_RTC_CTRL_FT_FREQ4KHZ (MXC_V_RTC_CTRL_FT_FREQ4KHZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ4KHZ Setting */
|
||||
#define MXC_V_RTC_CTRL_FT_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_FT_CLKDIV8 Value */
|
||||
#define MXC_S_RTC_CTRL_FT_CLKDIV8 (MXC_V_RTC_CTRL_FT_CLKDIV8 << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_CLKDIV8 Setting */
|
||||
|
||||
#define MXC_F_RTC_CTRL_X32KMD_POS 11 /**< CTRL_X32KMD Position */
|
||||
#define MXC_F_RTC_CTRL_X32KMD ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_X32KMD_POS)) /**< CTRL_X32KMD Mask */
|
||||
#define MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE ((uint32_t)0x0UL) /**< CTRL_X32KMD_NOISEIMMUNEMODE Value */
|
||||
#define MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE (MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_NOISEIMMUNEMODE Setting */
|
||||
#define MXC_V_RTC_CTRL_X32KMD_QUIETMODE ((uint32_t)0x1UL) /**< CTRL_X32KMD_QUIETMODE Value */
|
||||
#define MXC_S_RTC_CTRL_X32KMD_QUIETMODE (MXC_V_RTC_CTRL_X32KMD_QUIETMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETMODE Setting */
|
||||
#define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP ((uint32_t)0x2UL) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Value */
|
||||
#define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Setting */
|
||||
#define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP ((uint32_t)0x3UL) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Value */
|
||||
#define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Setting */
|
||||
#define MXC_F_RTC_CTRL_X32KMD_POS 11 /**< CTRL_X32KMD Position */
|
||||
#define MXC_F_RTC_CTRL_X32KMD ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_X32KMD_POS)) /**< CTRL_X32KMD Mask */
|
||||
#define MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE ((uint32_t)0x0UL) /**< CTRL_X32KMD_NOISEIMMUNEMODE Value */
|
||||
#define MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE (MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_NOISEIMMUNEMODE Setting */
|
||||
#define MXC_V_RTC_CTRL_X32KMD_QUIETMODE ((uint32_t)0x1UL) /**< CTRL_X32KMD_QUIETMODE Value */
|
||||
#define MXC_S_RTC_CTRL_X32KMD_QUIETMODE (MXC_V_RTC_CTRL_X32KMD_QUIETMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETMODE Setting */
|
||||
#define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP ((uint32_t)0x2UL) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Value */
|
||||
#define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Setting */
|
||||
#define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP ((uint32_t)0x3UL) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Value */
|
||||
#define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Setting */
|
||||
|
||||
#define MXC_F_RTC_CTRL_WE_POS 15 /**< CTRL_WE Position */
|
||||
#define MXC_F_RTC_CTRL_WE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WE_POS)) /**< CTRL_WE Mask */
|
||||
#define MXC_F_RTC_CTRL_WE_POS 15 /**< CTRL_WE Position */
|
||||
#define MXC_F_RTC_CTRL_WE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WE_POS)) /**< CTRL_WE Mask */
|
||||
|
||||
/**@} end of group RTC_CTRL_Register */
|
||||
|
||||
|
|
@ -212,11 +212,11 @@ typedef struct {
|
|||
* @brief RTC Trim Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */
|
||||
#define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */
|
||||
#define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */
|
||||
#define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */
|
||||
|
||||
#define MXC_F_RTC_TRIM_VBATTMR_POS 8 /**< TRIM_VBATTMR Position */
|
||||
#define MXC_F_RTC_TRIM_VBATTMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VBATTMR_POS)) /**< TRIM_VBATTMR Mask */
|
||||
#define MXC_F_RTC_TRIM_VBATTMR_POS 8 /**< TRIM_VBATTMR Position */
|
||||
#define MXC_F_RTC_TRIM_VBATTMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VBATTMR_POS)) /**< TRIM_VBATTMR Mask */
|
||||
|
||||
/**@} end of group RTC_TRIM_Register */
|
||||
|
||||
|
|
@ -226,23 +226,23 @@ typedef struct {
|
|||
* @brief RTC Oscillator Control Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_RTC_OSCCTRL_FLITER_EN_POS 0 /**< OSCCTRL_FLITER_EN Position */
|
||||
#define MXC_F_RTC_OSCCTRL_FLITER_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_FLITER_EN_POS)) /**< OSCCTRL_FLITER_EN Mask */
|
||||
#define MXC_F_RTC_OSCCTRL_FLITER_EN_POS 0 /**< OSCCTRL_FLITER_EN Position */
|
||||
#define MXC_F_RTC_OSCCTRL_FLITER_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_FLITER_EN_POS)) /**< OSCCTRL_FLITER_EN Mask */
|
||||
|
||||
#define MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS 1 /**< OSCCTRL_IBIAS_SEL Position */
|
||||
#define MXC_F_RTC_OSCCTRL_IBIAS_SEL ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS)) /**< OSCCTRL_IBIAS_SEL Mask */
|
||||
#define MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS 1 /**< OSCCTRL_IBIAS_SEL Position */
|
||||
#define MXC_F_RTC_OSCCTRL_IBIAS_SEL ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS)) /**< OSCCTRL_IBIAS_SEL Mask */
|
||||
|
||||
#define MXC_F_RTC_OSCCTRL_HYST_EN_POS 2 /**< OSCCTRL_HYST_EN Position */
|
||||
#define MXC_F_RTC_OSCCTRL_HYST_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_HYST_EN_POS)) /**< OSCCTRL_HYST_EN Mask */
|
||||
#define MXC_F_RTC_OSCCTRL_HYST_EN_POS 2 /**< OSCCTRL_HYST_EN Position */
|
||||
#define MXC_F_RTC_OSCCTRL_HYST_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_HYST_EN_POS)) /**< OSCCTRL_HYST_EN Mask */
|
||||
|
||||
#define MXC_F_RTC_OSCCTRL_IBIAS_EN_POS 3 /**< OSCCTRL_IBIAS_EN Position */
|
||||
#define MXC_F_RTC_OSCCTRL_IBIAS_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_EN_POS)) /**< OSCCTRL_IBIAS_EN Mask */
|
||||
#define MXC_F_RTC_OSCCTRL_IBIAS_EN_POS 3 /**< OSCCTRL_IBIAS_EN Position */
|
||||
#define MXC_F_RTC_OSCCTRL_IBIAS_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_EN_POS)) /**< OSCCTRL_IBIAS_EN Mask */
|
||||
|
||||
#define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */
|
||||
#define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */
|
||||
#define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */
|
||||
#define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */
|
||||
|
||||
#define MXC_F_RTC_OSCCTRL_OUT32K_POS 5 /**< OSCCTRL_OUT32K Position */
|
||||
#define MXC_F_RTC_OSCCTRL_OUT32K ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_OUT32K_POS)) /**< OSCCTRL_OUT32K Mask */
|
||||
#define MXC_F_RTC_OSCCTRL_OUT32K_POS 5 /**< OSCCTRL_OUT32K Position */
|
||||
#define MXC_F_RTC_OSCCTRL_OUT32K ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_OUT32K_POS)) /**< OSCCTRL_OUT32K Mask */
|
||||
|
||||
/**@} end of group RTC_OSCCTRL_Register */
|
||||
|
||||
|
|
@ -250,4 +250,4 @@ typedef struct {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _RTC_REGS_H_ */
|
||||
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_RTC_REGS_H_
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
/**
|
||||
* @file sir_regs.h
|
||||
* @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module.
|
||||
* @note This file is @generated.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +35,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _SIR_REGS_H_
|
||||
#define _SIR_REGS_H_
|
||||
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SIR_REGS_H_
|
||||
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SIR_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -46,11 +46,11 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__ICCARM__)
|
||||
#pragma system_include
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__CC_ARM)
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
|
@ -78,7 +78,7 @@ extern "C" {
|
|||
* @ingroup sir
|
||||
* @defgroup sir_registers SIR_Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module.
|
||||
* @details System Initialization Registers.
|
||||
* @details System Initialization Registers.
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
@ -94,11 +94,11 @@ typedef struct {
|
|||
/**
|
||||
* @ingroup sir_registers
|
||||
* @defgroup SIR_Register_Offsets Register Offsets
|
||||
* @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address.
|
||||
* @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_SIR_STATUS ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_SIR_ADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_SIR_STATUS ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_SIR_ADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: <tt> 0x0004</tt> */
|
||||
/**@} end of group sir_registers */
|
||||
|
||||
/**
|
||||
|
|
@ -107,11 +107,11 @@ typedef struct {
|
|||
* @brief System Initialization Status Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SIR_STATUS_CFG_VALID_POS 0 /**< STATUS_CFG_VALID Position */
|
||||
#define MXC_F_SIR_STATUS_CFG_VALID ((uint32_t)(0x1UL << MXC_F_SIR_STATUS_CFG_VALID_POS)) /**< STATUS_CFG_VALID Mask */
|
||||
#define MXC_F_SIR_STATUS_CFG_VALID_POS 0 /**< STATUS_CFG_VALID Position */
|
||||
#define MXC_F_SIR_STATUS_CFG_VALID ((uint32_t)(0x1UL << MXC_F_SIR_STATUS_CFG_VALID_POS)) /**< STATUS_CFG_VALID Mask */
|
||||
|
||||
#define MXC_F_SIR_STATUS_CFG_ERR_POS 1 /**< STATUS_CFG_ERR Position */
|
||||
#define MXC_F_SIR_STATUS_CFG_ERR ((uint32_t)(0x1UL << MXC_F_SIR_STATUS_CFG_ERR_POS)) /**< STATUS_CFG_ERR Mask */
|
||||
#define MXC_F_SIR_STATUS_CFG_ERR_POS 1 /**< STATUS_CFG_ERR Position */
|
||||
#define MXC_F_SIR_STATUS_CFG_ERR ((uint32_t)(0x1UL << MXC_F_SIR_STATUS_CFG_ERR_POS)) /**< STATUS_CFG_ERR Mask */
|
||||
|
||||
/**@} end of group SIR_STATUS_Register */
|
||||
|
||||
|
|
@ -123,8 +123,8 @@ typedef struct {
|
|||
* 1).
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SIR_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
|
||||
#define MXC_F_SIR_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
|
||||
#define MXC_F_SIR_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
|
||||
#define MXC_F_SIR_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
|
||||
|
||||
/**@} end of group SIR_ADDR_Register */
|
||||
|
||||
|
|
@ -132,4 +132,4 @@ typedef struct {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SIR_REGS_H_ */
|
||||
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SIR_REGS_H_
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
/**
|
||||
* @file spi_regs.h
|
||||
* @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module.
|
||||
* @note This file is @generated.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +35,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _SPI_REGS_H_
|
||||
#define _SPI_REGS_H_
|
||||
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPI_REGS_H_
|
||||
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPI_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -46,11 +46,11 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__ICCARM__)
|
||||
#pragma system_include
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__CC_ARM)
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
|
@ -67,7 +67,9 @@ extern "C" {
|
|||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
|
||||
#ifndef __R
|
||||
#define __R volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
|
@ -76,7 +78,7 @@ extern "C" {
|
|||
* @ingroup spi
|
||||
* @defgroup spi_registers SPI_Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module.
|
||||
* @details SPI peripheral.
|
||||
* @details SPI peripheral.
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
@ -90,7 +92,7 @@ typedef struct {
|
|||
__IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPI CTRL2 Register */
|
||||
__IO uint32_t ss_time; /**< <tt>\b 0x10:</tt> SPI SS_TIME Register */
|
||||
__IO uint32_t clk_cfg; /**< <tt>\b 0x14:</tt> SPI CLK_CFG Register */
|
||||
__I uint32_t rsv_0x18;
|
||||
__R uint32_t rsv_0x18;
|
||||
__IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPI DMA Register */
|
||||
__IO uint32_t int_fl; /**< <tt>\b 0x20:</tt> SPI INT_FL Register */
|
||||
__IO uint32_t int_en; /**< <tt>\b 0x24:</tt> SPI INT_EN Register */
|
||||
|
|
@ -103,21 +105,21 @@ typedef struct {
|
|||
/**
|
||||
* @ingroup spi_registers
|
||||
* @defgroup SPI_Register_Offsets Register Offsets
|
||||
* @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address.
|
||||
* @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_SPI_DATA ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: <tt> 0x000C</tt> */
|
||||
#define MXC_R_SPI_SS_TIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: <tt> 0x0010</tt> */
|
||||
#define MXC_R_SPI_CLK_CFG ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: <tt> 0x0014</tt> */
|
||||
#define MXC_R_SPI_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: <tt> 0x001C</tt> */
|
||||
#define MXC_R_SPI_INT_FL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: <tt> 0x0020</tt> */
|
||||
#define MXC_R_SPI_INT_EN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: <tt> 0x0024</tt> */
|
||||
#define MXC_R_SPI_WAKE_FL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: <tt> 0x0028</tt> */
|
||||
#define MXC_R_SPI_WAKE_EN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: <tt> 0x002C</tt> */
|
||||
#define MXC_R_SPI_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: <tt> 0x0030</tt> */
|
||||
#define MXC_R_SPI_DATA ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: <tt> 0x000C</tt> */
|
||||
#define MXC_R_SPI_SS_TIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: <tt> 0x0010</tt> */
|
||||
#define MXC_R_SPI_CLK_CFG ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: <tt> 0x0014</tt> */
|
||||
#define MXC_R_SPI_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: <tt> 0x001C</tt> */
|
||||
#define MXC_R_SPI_INT_FL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: <tt> 0x0020</tt> */
|
||||
#define MXC_R_SPI_INT_EN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: <tt> 0x0024</tt> */
|
||||
#define MXC_R_SPI_WAKE_FL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: <tt> 0x0028</tt> */
|
||||
#define MXC_R_SPI_WAKE_EN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: <tt> 0x002C</tt> */
|
||||
#define MXC_R_SPI_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: <tt> 0x0030</tt> */
|
||||
/**@} end of group spi_registers */
|
||||
|
||||
/**
|
||||
|
|
@ -134,31 +136,31 @@ typedef struct {
|
|||
* @brief Register for controlling SPI peripheral.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPI_CTRL0_SPI_EN_POS 0 /**< CTRL0_SPI_EN Position */
|
||||
#define MXC_F_SPI_CTRL0_SPI_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SPI_EN_POS)) /**< CTRL0_SPI_EN Mask */
|
||||
#define MXC_F_SPI_CTRL0_SPI_EN_POS 0 /**< CTRL0_SPI_EN Position */
|
||||
#define MXC_F_SPI_CTRL0_SPI_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SPI_EN_POS)) /**< CTRL0_SPI_EN Mask */
|
||||
|
||||
#define MXC_F_SPI_CTRL0_MM_EN_POS 1 /**< CTRL0_MM_EN Position */
|
||||
#define MXC_F_SPI_CTRL0_MM_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MM_EN_POS)) /**< CTRL0_MM_EN Mask */
|
||||
#define MXC_F_SPI_CTRL0_MM_EN_POS 1 /**< CTRL0_MM_EN Position */
|
||||
#define MXC_F_SPI_CTRL0_MM_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MM_EN_POS)) /**< CTRL0_MM_EN Mask */
|
||||
|
||||
#define MXC_F_SPI_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */
|
||||
#define MXC_F_SPI_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */
|
||||
#define MXC_F_SPI_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */
|
||||
#define MXC_F_SPI_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */
|
||||
|
||||
#define MXC_F_SPI_CTRL0_START_POS 5 /**< CTRL0_START Position */
|
||||
#define MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) /**< CTRL0_START Mask */
|
||||
#define MXC_F_SPI_CTRL0_START_POS 5 /**< CTRL0_START Position */
|
||||
#define MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) /**< CTRL0_START Mask */
|
||||
|
||||
#define MXC_F_SPI_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */
|
||||
#define MXC_F_SPI_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */
|
||||
#define MXC_F_SPI_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */
|
||||
#define MXC_F_SPI_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */
|
||||
|
||||
#define MXC_F_SPI_CTRL0_SS_SEL_POS 16 /**< CTRL0_SS_SEL Position */
|
||||
#define MXC_F_SPI_CTRL0_SS_SEL ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_SEL_POS)) /**< CTRL0_SS_SEL Mask */
|
||||
#define MXC_V_SPI_CTRL0_SS_SEL_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_SEL_SS0 Value */
|
||||
#define MXC_S_SPI_CTRL0_SS_SEL_SS0 (MXC_V_SPI_CTRL0_SS_SEL_SS0 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS0 Setting */
|
||||
#define MXC_V_SPI_CTRL0_SS_SEL_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_SEL_SS1 Value */
|
||||
#define MXC_S_SPI_CTRL0_SS_SEL_SS1 (MXC_V_SPI_CTRL0_SS_SEL_SS1 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS1 Setting */
|
||||
#define MXC_V_SPI_CTRL0_SS_SEL_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_SEL_SS2 Value */
|
||||
#define MXC_S_SPI_CTRL0_SS_SEL_SS2 (MXC_V_SPI_CTRL0_SS_SEL_SS2 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS2 Setting */
|
||||
#define MXC_V_SPI_CTRL0_SS_SEL_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_SEL_SS3 Value */
|
||||
#define MXC_S_SPI_CTRL0_SS_SEL_SS3 (MXC_V_SPI_CTRL0_SS_SEL_SS3 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS3 Setting */
|
||||
#define MXC_F_SPI_CTRL0_SS_SEL_POS 16 /**< CTRL0_SS_SEL Position */
|
||||
#define MXC_F_SPI_CTRL0_SS_SEL ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_SEL_POS)) /**< CTRL0_SS_SEL Mask */
|
||||
#define MXC_V_SPI_CTRL0_SS_SEL_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_SEL_SS0 Value */
|
||||
#define MXC_S_SPI_CTRL0_SS_SEL_SS0 (MXC_V_SPI_CTRL0_SS_SEL_SS0 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS0 Setting */
|
||||
#define MXC_V_SPI_CTRL0_SS_SEL_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_SEL_SS1 Value */
|
||||
#define MXC_S_SPI_CTRL0_SS_SEL_SS1 (MXC_V_SPI_CTRL0_SS_SEL_SS1 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS1 Setting */
|
||||
#define MXC_V_SPI_CTRL0_SS_SEL_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_SEL_SS2 Value */
|
||||
#define MXC_S_SPI_CTRL0_SS_SEL_SS2 (MXC_V_SPI_CTRL0_SS_SEL_SS2 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS2 Setting */
|
||||
#define MXC_V_SPI_CTRL0_SS_SEL_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_SEL_SS3 Value */
|
||||
#define MXC_S_SPI_CTRL0_SS_SEL_SS3 (MXC_V_SPI_CTRL0_SS_SEL_SS3 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS3 Setting */
|
||||
|
||||
/**@} end of group SPI_CTRL0_Register */
|
||||
|
||||
|
|
@ -168,11 +170,11 @@ typedef struct {
|
|||
* @brief Register for controlling SPI peripheral.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */
|
||||
#define MXC_F_SPI_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */
|
||||
#define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */
|
||||
#define MXC_F_SPI_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */
|
||||
|
||||
#define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */
|
||||
#define MXC_F_SPI_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */
|
||||
#define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */
|
||||
#define MXC_F_SPI_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */
|
||||
|
||||
/**@} end of group SPI_CTRL1_Register */
|
||||
|
||||
|
|
@ -182,31 +184,31 @@ typedef struct {
|
|||
* @brief Register for controlling SPI peripheral.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPI_CTRL2_CLK_PHA_POS 0 /**< CTRL2_CLK_PHA Position */
|
||||
#define MXC_F_SPI_CTRL2_CLK_PHA ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_PHA_POS)) /**< CTRL2_CLK_PHA Mask */
|
||||
#define MXC_F_SPI_CTRL2_CLK_PHA_POS 0 /**< CTRL2_CLK_PHA Position */
|
||||
#define MXC_F_SPI_CTRL2_CLK_PHA ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_PHA_POS)) /**< CTRL2_CLK_PHA Mask */
|
||||
|
||||
#define MXC_F_SPI_CTRL2_CLK_POL_POS 1 /**< CTRL2_CLK_POL Position */
|
||||
#define MXC_F_SPI_CTRL2_CLK_POL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_POL_POS)) /**< CTRL2_CLK_POL Mask */
|
||||
#define MXC_F_SPI_CTRL2_CLK_POL_POS 1 /**< CTRL2_CLK_POL Position */
|
||||
#define MXC_F_SPI_CTRL2_CLK_POL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_POL_POS)) /**< CTRL2_CLK_POL Mask */
|
||||
|
||||
#define MXC_F_SPI_CTRL2_NUM_BITS_POS 8 /**< CTRL2_NUM_BITS Position */
|
||||
#define MXC_F_SPI_CTRL2_NUM_BITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUM_BITS_POS)) /**< CTRL2_NUM_BITS Mask */
|
||||
#define MXC_V_SPI_CTRL2_NUM_BITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUM_BITS_0 Value */
|
||||
#define MXC_S_SPI_CTRL2_NUM_BITS_0 (MXC_V_SPI_CTRL2_NUM_BITS_0 << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_0 Setting */
|
||||
#define MXC_F_SPI_CTRL2_NUM_BITS_POS 8 /**< CTRL2_NUM_BITS Position */
|
||||
#define MXC_F_SPI_CTRL2_NUM_BITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUM_BITS_POS)) /**< CTRL2_NUM_BITS Mask */
|
||||
#define MXC_V_SPI_CTRL2_NUM_BITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUM_BITS_0 Value */
|
||||
#define MXC_S_SPI_CTRL2_NUM_BITS_0 (MXC_V_SPI_CTRL2_NUM_BITS_0 << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_0 Setting */
|
||||
|
||||
#define MXC_F_SPI_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */
|
||||
#define MXC_F_SPI_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */
|
||||
#define MXC_V_SPI_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */
|
||||
#define MXC_S_SPI_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */
|
||||
#define MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */
|
||||
#define MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */
|
||||
#define MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */
|
||||
#define MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */
|
||||
#define MXC_F_SPI_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */
|
||||
#define MXC_F_SPI_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */
|
||||
#define MXC_V_SPI_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */
|
||||
#define MXC_S_SPI_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */
|
||||
#define MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */
|
||||
#define MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */
|
||||
#define MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */
|
||||
#define MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */
|
||||
|
||||
#define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */
|
||||
#define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */
|
||||
#define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */
|
||||
#define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */
|
||||
|
||||
#define MXC_F_SPI_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */
|
||||
#define MXC_F_SPI_CTRL2_SS_POL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */
|
||||
#define MXC_F_SPI_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */
|
||||
#define MXC_F_SPI_CTRL2_SS_POL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */
|
||||
|
||||
/**@} end of group SPI_CTRL2_Register */
|
||||
|
||||
|
|
@ -216,20 +218,20 @@ typedef struct {
|
|||
* @brief Register for controlling SPI peripheral/Slave Select Timing.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPI_SS_TIME_SSACT1_POS 0 /**< SS_TIME_SSACT1 Position */
|
||||
#define MXC_F_SPI_SS_TIME_SSACT1 ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSACT1_POS)) /**< SS_TIME_SSACT1 Mask */
|
||||
#define MXC_V_SPI_SS_TIME_SSACT1_256 ((uint32_t)0x0UL) /**< SS_TIME_SSACT1_256 Value */
|
||||
#define MXC_S_SPI_SS_TIME_SSACT1_256 (MXC_V_SPI_SS_TIME_SSACT1_256 << MXC_F_SPI_SS_TIME_SSACT1_POS) /**< SS_TIME_SSACT1_256 Setting */
|
||||
#define MXC_F_SPI_SS_TIME_SSACT1_POS 0 /**< SS_TIME_SSACT1 Position */
|
||||
#define MXC_F_SPI_SS_TIME_SSACT1 ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSACT1_POS)) /**< SS_TIME_SSACT1 Mask */
|
||||
#define MXC_V_SPI_SS_TIME_SSACT1_256 ((uint32_t)0x0UL) /**< SS_TIME_SSACT1_256 Value */
|
||||
#define MXC_S_SPI_SS_TIME_SSACT1_256 (MXC_V_SPI_SS_TIME_SSACT1_256 << MXC_F_SPI_SS_TIME_SSACT1_POS) /**< SS_TIME_SSACT1_256 Setting */
|
||||
|
||||
#define MXC_F_SPI_SS_TIME_SSACT2_POS 8 /**< SS_TIME_SSACT2 Position */
|
||||
#define MXC_F_SPI_SS_TIME_SSACT2 ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSACT2_POS)) /**< SS_TIME_SSACT2 Mask */
|
||||
#define MXC_V_SPI_SS_TIME_SSACT2_256 ((uint32_t)0x0UL) /**< SS_TIME_SSACT2_256 Value */
|
||||
#define MXC_S_SPI_SS_TIME_SSACT2_256 (MXC_V_SPI_SS_TIME_SSACT2_256 << MXC_F_SPI_SS_TIME_SSACT2_POS) /**< SS_TIME_SSACT2_256 Setting */
|
||||
#define MXC_F_SPI_SS_TIME_SSACT2_POS 8 /**< SS_TIME_SSACT2 Position */
|
||||
#define MXC_F_SPI_SS_TIME_SSACT2 ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSACT2_POS)) /**< SS_TIME_SSACT2 Mask */
|
||||
#define MXC_V_SPI_SS_TIME_SSACT2_256 ((uint32_t)0x0UL) /**< SS_TIME_SSACT2_256 Value */
|
||||
#define MXC_S_SPI_SS_TIME_SSACT2_256 (MXC_V_SPI_SS_TIME_SSACT2_256 << MXC_F_SPI_SS_TIME_SSACT2_POS) /**< SS_TIME_SSACT2_256 Setting */
|
||||
|
||||
#define MXC_F_SPI_SS_TIME_SSINACT_POS 16 /**< SS_TIME_SSINACT Position */
|
||||
#define MXC_F_SPI_SS_TIME_SSINACT ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSINACT_POS)) /**< SS_TIME_SSINACT Mask */
|
||||
#define MXC_V_SPI_SS_TIME_SSINACT_256 ((uint32_t)0x0UL) /**< SS_TIME_SSINACT_256 Value */
|
||||
#define MXC_S_SPI_SS_TIME_SSINACT_256 (MXC_V_SPI_SS_TIME_SSINACT_256 << MXC_F_SPI_SS_TIME_SSINACT_POS) /**< SS_TIME_SSINACT_256 Setting */
|
||||
#define MXC_F_SPI_SS_TIME_SSINACT_POS 16 /**< SS_TIME_SSINACT Position */
|
||||
#define MXC_F_SPI_SS_TIME_SSINACT ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSINACT_POS)) /**< SS_TIME_SSINACT Mask */
|
||||
#define MXC_V_SPI_SS_TIME_SSINACT_256 ((uint32_t)0x0UL) /**< SS_TIME_SSINACT_256 Value */
|
||||
#define MXC_S_SPI_SS_TIME_SSINACT_256 (MXC_V_SPI_SS_TIME_SSINACT_256 << MXC_F_SPI_SS_TIME_SSINACT_POS) /**< SS_TIME_SSINACT_256 Setting */
|
||||
|
||||
/**@} end of group SPI_SS_TIME_Register */
|
||||
|
||||
|
|
@ -239,18 +241,18 @@ typedef struct {
|
|||
* @brief Register for controlling SPI clock rate.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPI_CLK_CFG_LO_POS 0 /**< CLK_CFG_LO Position */
|
||||
#define MXC_F_SPI_CLK_CFG_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_LO_POS)) /**< CLK_CFG_LO Mask */
|
||||
#define MXC_V_SPI_CLK_CFG_LO_DIS ((uint32_t)0x0UL) /**< CLK_CFG_LO_DIS Value */
|
||||
#define MXC_S_SPI_CLK_CFG_LO_DIS (MXC_V_SPI_CLK_CFG_LO_DIS << MXC_F_SPI_CLK_CFG_LO_POS) /**< CLK_CFG_LO_DIS Setting */
|
||||
#define MXC_F_SPI_CLK_CFG_LO_POS 0 /**< CLK_CFG_LO Position */
|
||||
#define MXC_F_SPI_CLK_CFG_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_LO_POS)) /**< CLK_CFG_LO Mask */
|
||||
#define MXC_V_SPI_CLK_CFG_LO_DIS ((uint32_t)0x0UL) /**< CLK_CFG_LO_DIS Value */
|
||||
#define MXC_S_SPI_CLK_CFG_LO_DIS (MXC_V_SPI_CLK_CFG_LO_DIS << MXC_F_SPI_CLK_CFG_LO_POS) /**< CLK_CFG_LO_DIS Setting */
|
||||
|
||||
#define MXC_F_SPI_CLK_CFG_HI_POS 8 /**< CLK_CFG_HI Position */
|
||||
#define MXC_F_SPI_CLK_CFG_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_HI_POS)) /**< CLK_CFG_HI Mask */
|
||||
#define MXC_V_SPI_CLK_CFG_HI_DIS ((uint32_t)0x0UL) /**< CLK_CFG_HI_DIS Value */
|
||||
#define MXC_S_SPI_CLK_CFG_HI_DIS (MXC_V_SPI_CLK_CFG_HI_DIS << MXC_F_SPI_CLK_CFG_HI_POS) /**< CLK_CFG_HI_DIS Setting */
|
||||
#define MXC_F_SPI_CLK_CFG_HI_POS 8 /**< CLK_CFG_HI Position */
|
||||
#define MXC_F_SPI_CLK_CFG_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_HI_POS)) /**< CLK_CFG_HI Mask */
|
||||
#define MXC_V_SPI_CLK_CFG_HI_DIS ((uint32_t)0x0UL) /**< CLK_CFG_HI_DIS Value */
|
||||
#define MXC_S_SPI_CLK_CFG_HI_DIS (MXC_V_SPI_CLK_CFG_HI_DIS << MXC_F_SPI_CLK_CFG_HI_POS) /**< CLK_CFG_HI_DIS Setting */
|
||||
|
||||
#define MXC_F_SPI_CLK_CFG_SCALE_POS 16 /**< CLK_CFG_SCALE Position */
|
||||
#define MXC_F_SPI_CLK_CFG_SCALE ((uint32_t)(0xFUL << MXC_F_SPI_CLK_CFG_SCALE_POS)) /**< CLK_CFG_SCALE Mask */
|
||||
#define MXC_F_SPI_CLK_CFG_SCALE_POS 16 /**< CLK_CFG_SCALE Position */
|
||||
#define MXC_F_SPI_CLK_CFG_SCALE ((uint32_t)(0xFUL << MXC_F_SPI_CLK_CFG_SCALE_POS)) /**< CLK_CFG_SCALE Mask */
|
||||
|
||||
/**@} end of group SPI_CLK_CFG_Register */
|
||||
|
||||
|
|
@ -260,35 +262,35 @@ typedef struct {
|
|||
* @brief Register for controlling DMA.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */
|
||||
#define MXC_F_SPI_DMA_TX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */
|
||||
#define MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */
|
||||
#define MXC_F_SPI_DMA_TX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */
|
||||
|
||||
#define MXC_F_SPI_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */
|
||||
#define MXC_F_SPI_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */
|
||||
#define MXC_F_SPI_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */
|
||||
#define MXC_F_SPI_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */
|
||||
|
||||
#define MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */
|
||||
#define MXC_F_SPI_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */
|
||||
#define MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */
|
||||
#define MXC_F_SPI_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */
|
||||
|
||||
#define MXC_F_SPI_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */
|
||||
#define MXC_F_SPI_DMA_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */
|
||||
#define MXC_F_SPI_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */
|
||||
#define MXC_F_SPI_DMA_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */
|
||||
|
||||
#define MXC_F_SPI_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */
|
||||
#define MXC_F_SPI_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */
|
||||
#define MXC_F_SPI_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */
|
||||
#define MXC_F_SPI_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */
|
||||
|
||||
#define MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */
|
||||
#define MXC_F_SPI_DMA_RX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */
|
||||
#define MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */
|
||||
#define MXC_F_SPI_DMA_RX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */
|
||||
|
||||
#define MXC_F_SPI_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */
|
||||
#define MXC_F_SPI_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */
|
||||
#define MXC_F_SPI_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */
|
||||
#define MXC_F_SPI_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */
|
||||
|
||||
#define MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS 23 /**< DMA_RX_FIFO_CLEAR Position */
|
||||
#define MXC_F_SPI_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */
|
||||
#define MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS 23 /**< DMA_RX_FIFO_CLEAR Position */
|
||||
#define MXC_F_SPI_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */
|
||||
|
||||
#define MXC_F_SPI_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */
|
||||
#define MXC_F_SPI_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */
|
||||
#define MXC_F_SPI_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */
|
||||
#define MXC_F_SPI_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */
|
||||
|
||||
#define MXC_F_SPI_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */
|
||||
#define MXC_F_SPI_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */
|
||||
#define MXC_F_SPI_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */
|
||||
#define MXC_F_SPI_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */
|
||||
|
||||
/**@} end of group SPI_DMA_Register */
|
||||
|
||||
|
|
@ -299,41 +301,41 @@ typedef struct {
|
|||
* clear.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPI_INT_FL_TX_LEVEL_POS 0 /**< INT_FL_TX_LEVEL Position */
|
||||
#define MXC_F_SPI_INT_FL_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_LEVEL_POS)) /**< INT_FL_TX_LEVEL Mask */
|
||||
#define MXC_F_SPI_INT_FL_TX_LEVEL_POS 0 /**< INT_FL_TX_LEVEL Position */
|
||||
#define MXC_F_SPI_INT_FL_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_LEVEL_POS)) /**< INT_FL_TX_LEVEL Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_FL_TX_EMPTY_POS 1 /**< INT_FL_TX_EMPTY Position */
|
||||
#define MXC_F_SPI_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_EMPTY_POS)) /**< INT_FL_TX_EMPTY Mask */
|
||||
#define MXC_F_SPI_INT_FL_TX_EMPTY_POS 1 /**< INT_FL_TX_EMPTY Position */
|
||||
#define MXC_F_SPI_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_EMPTY_POS)) /**< INT_FL_TX_EMPTY Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_FL_RX_LEVEL_POS 2 /**< INT_FL_RX_LEVEL Position */
|
||||
#define MXC_F_SPI_INT_FL_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_LEVEL_POS)) /**< INT_FL_RX_LEVEL Mask */
|
||||
#define MXC_F_SPI_INT_FL_RX_LEVEL_POS 2 /**< INT_FL_RX_LEVEL Position */
|
||||
#define MXC_F_SPI_INT_FL_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_LEVEL_POS)) /**< INT_FL_RX_LEVEL Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_FL_RX_FULL_POS 3 /**< INT_FL_RX_FULL Position */
|
||||
#define MXC_F_SPI_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_FULL_POS)) /**< INT_FL_RX_FULL Mask */
|
||||
#define MXC_F_SPI_INT_FL_RX_FULL_POS 3 /**< INT_FL_RX_FULL Position */
|
||||
#define MXC_F_SPI_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_FULL_POS)) /**< INT_FL_RX_FULL Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_FL_SSA_POS 4 /**< INT_FL_SSA Position */
|
||||
#define MXC_F_SPI_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSA_POS)) /**< INT_FL_SSA Mask */
|
||||
#define MXC_F_SPI_INT_FL_SSA_POS 4 /**< INT_FL_SSA Position */
|
||||
#define MXC_F_SPI_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSA_POS)) /**< INT_FL_SSA Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_FL_SSD_POS 5 /**< INT_FL_SSD Position */
|
||||
#define MXC_F_SPI_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSD_POS)) /**< INT_FL_SSD Mask */
|
||||
#define MXC_F_SPI_INT_FL_SSD_POS 5 /**< INT_FL_SSD Position */
|
||||
#define MXC_F_SPI_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSD_POS)) /**< INT_FL_SSD Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_FL_ABORT_POS 9 /**< INT_FL_ABORT Position */
|
||||
#define MXC_F_SPI_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_ABORT_POS)) /**< INT_FL_ABORT Mask */
|
||||
#define MXC_F_SPI_INT_FL_ABORT_POS 9 /**< INT_FL_ABORT Position */
|
||||
#define MXC_F_SPI_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_ABORT_POS)) /**< INT_FL_ABORT Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_FL_M_DONE_POS 11 /**< INT_FL_M_DONE Position */
|
||||
#define MXC_F_SPI_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_M_DONE_POS)) /**< INT_FL_M_DONE Mask */
|
||||
#define MXC_F_SPI_INT_FL_M_DONE_POS 11 /**< INT_FL_M_DONE Position */
|
||||
#define MXC_F_SPI_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_M_DONE_POS)) /**< INT_FL_M_DONE Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_FL_TX_OVR_POS 12 /**< INT_FL_TX_OVR Position */
|
||||
#define MXC_F_SPI_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_OVR_POS)) /**< INT_FL_TX_OVR Mask */
|
||||
#define MXC_F_SPI_INT_FL_TX_OVR_POS 12 /**< INT_FL_TX_OVR Position */
|
||||
#define MXC_F_SPI_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_OVR_POS)) /**< INT_FL_TX_OVR Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_FL_TX_UND_POS 13 /**< INT_FL_TX_UND Position */
|
||||
#define MXC_F_SPI_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_UND_POS)) /**< INT_FL_TX_UND Mask */
|
||||
#define MXC_F_SPI_INT_FL_TX_UND_POS 13 /**< INT_FL_TX_UND Position */
|
||||
#define MXC_F_SPI_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_UND_POS)) /**< INT_FL_TX_UND Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_FL_RX_OVR_POS 14 /**< INT_FL_RX_OVR Position */
|
||||
#define MXC_F_SPI_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */
|
||||
#define MXC_F_SPI_INT_FL_RX_OVR_POS 14 /**< INT_FL_RX_OVR Position */
|
||||
#define MXC_F_SPI_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_FL_RX_UND_POS 15 /**< INT_FL_RX_UND Position */
|
||||
#define MXC_F_SPI_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_UND_POS)) /**< INT_FL_RX_UND Mask */
|
||||
#define MXC_F_SPI_INT_FL_RX_UND_POS 15 /**< INT_FL_RX_UND Position */
|
||||
#define MXC_F_SPI_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_UND_POS)) /**< INT_FL_RX_UND Mask */
|
||||
|
||||
/**@} end of group SPI_INT_FL_Register */
|
||||
|
||||
|
|
@ -343,44 +345,44 @@ typedef struct {
|
|||
* @brief Register for enabling interrupts.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPI_INT_EN_TX_LEVEL_POS 0 /**< INT_EN_TX_LEVEL Position */
|
||||
#define MXC_F_SPI_INT_EN_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_LEVEL_POS)) /**< INT_EN_TX_LEVEL Mask */
|
||||
#define MXC_F_SPI_INT_EN_TX_LEVEL_POS 0 /**< INT_EN_TX_LEVEL Position */
|
||||
#define MXC_F_SPI_INT_EN_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_LEVEL_POS)) /**< INT_EN_TX_LEVEL Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_EN_TX_EMPTY_POS 1 /**< INT_EN_TX_EMPTY Position */
|
||||
#define MXC_F_SPI_INT_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_EMPTY_POS)) /**< INT_EN_TX_EMPTY Mask */
|
||||
#define MXC_F_SPI_INT_EN_TX_EMPTY_POS 1 /**< INT_EN_TX_EMPTY Position */
|
||||
#define MXC_F_SPI_INT_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_EMPTY_POS)) /**< INT_EN_TX_EMPTY Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_EN_RX_LEVEL_POS 2 /**< INT_EN_RX_LEVEL Position */
|
||||
#define MXC_F_SPI_INT_EN_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_LEVEL_POS)) /**< INT_EN_RX_LEVEL Mask */
|
||||
#define MXC_F_SPI_INT_EN_RX_LEVEL_POS 2 /**< INT_EN_RX_LEVEL Position */
|
||||
#define MXC_F_SPI_INT_EN_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_LEVEL_POS)) /**< INT_EN_RX_LEVEL Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_EN_RX_FULL_POS 3 /**< INT_EN_RX_FULL Position */
|
||||
#define MXC_F_SPI_INT_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_FULL_POS)) /**< INT_EN_RX_FULL Mask */
|
||||
#define MXC_F_SPI_INT_EN_RX_FULL_POS 3 /**< INT_EN_RX_FULL Position */
|
||||
#define MXC_F_SPI_INT_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_FULL_POS)) /**< INT_EN_RX_FULL Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_EN_SSA_POS 4 /**< INT_EN_SSA Position */
|
||||
#define MXC_F_SPI_INT_EN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSA_POS)) /**< INT_EN_SSA Mask */
|
||||
#define MXC_F_SPI_INT_EN_SSA_POS 4 /**< INT_EN_SSA Position */
|
||||
#define MXC_F_SPI_INT_EN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSA_POS)) /**< INT_EN_SSA Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_EN_SSD_POS 5 /**< INT_EN_SSD Position */
|
||||
#define MXC_F_SPI_INT_EN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSD_POS)) /**< INT_EN_SSD Mask */
|
||||
#define MXC_F_SPI_INT_EN_SSD_POS 5 /**< INT_EN_SSD Position */
|
||||
#define MXC_F_SPI_INT_EN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSD_POS)) /**< INT_EN_SSD Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_EN_FAULT_POS 8 /**< INT_EN_FAULT Position */
|
||||
#define MXC_F_SPI_INT_EN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_FAULT_POS)) /**< INT_EN_FAULT Mask */
|
||||
#define MXC_F_SPI_INT_EN_FAULT_POS 8 /**< INT_EN_FAULT Position */
|
||||
#define MXC_F_SPI_INT_EN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_FAULT_POS)) /**< INT_EN_FAULT Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_EN_ABORT_POS 9 /**< INT_EN_ABORT Position */
|
||||
#define MXC_F_SPI_INT_EN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_ABORT_POS)) /**< INT_EN_ABORT Mask */
|
||||
#define MXC_F_SPI_INT_EN_ABORT_POS 9 /**< INT_EN_ABORT Position */
|
||||
#define MXC_F_SPI_INT_EN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_ABORT_POS)) /**< INT_EN_ABORT Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_EN_M_DONE_POS 11 /**< INT_EN_M_DONE Position */
|
||||
#define MXC_F_SPI_INT_EN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_M_DONE_POS)) /**< INT_EN_M_DONE Mask */
|
||||
#define MXC_F_SPI_INT_EN_M_DONE_POS 11 /**< INT_EN_M_DONE Position */
|
||||
#define MXC_F_SPI_INT_EN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_M_DONE_POS)) /**< INT_EN_M_DONE Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_EN_TX_OVR_POS 12 /**< INT_EN_TX_OVR Position */
|
||||
#define MXC_F_SPI_INT_EN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_OVR_POS)) /**< INT_EN_TX_OVR Mask */
|
||||
#define MXC_F_SPI_INT_EN_TX_OVR_POS 12 /**< INT_EN_TX_OVR Position */
|
||||
#define MXC_F_SPI_INT_EN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_OVR_POS)) /**< INT_EN_TX_OVR Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_EN_TX_UND_POS 13 /**< INT_EN_TX_UND Position */
|
||||
#define MXC_F_SPI_INT_EN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_UND_POS)) /**< INT_EN_TX_UND Mask */
|
||||
#define MXC_F_SPI_INT_EN_TX_UND_POS 13 /**< INT_EN_TX_UND Position */
|
||||
#define MXC_F_SPI_INT_EN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_UND_POS)) /**< INT_EN_TX_UND Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_EN_RX_OVR_POS 14 /**< INT_EN_RX_OVR Position */
|
||||
#define MXC_F_SPI_INT_EN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_OVR_POS)) /**< INT_EN_RX_OVR Mask */
|
||||
#define MXC_F_SPI_INT_EN_RX_OVR_POS 14 /**< INT_EN_RX_OVR Position */
|
||||
#define MXC_F_SPI_INT_EN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_OVR_POS)) /**< INT_EN_RX_OVR Mask */
|
||||
|
||||
#define MXC_F_SPI_INT_EN_RX_UND_POS 15 /**< INT_EN_RX_UND Position */
|
||||
#define MXC_F_SPI_INT_EN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_UND_POS)) /**< INT_EN_RX_UND Mask */
|
||||
#define MXC_F_SPI_INT_EN_RX_UND_POS 15 /**< INT_EN_RX_UND Position */
|
||||
#define MXC_F_SPI_INT_EN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_UND_POS)) /**< INT_EN_RX_UND Mask */
|
||||
|
||||
/**@} end of group SPI_INT_EN_Register */
|
||||
|
||||
|
|
@ -390,17 +392,17 @@ typedef struct {
|
|||
* @brief Register for wake up flags. All bits in this register are write 1 to clear.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPI_WAKE_FL_TX_LEVEL_POS 0 /**< WAKE_FL_TX_LEVEL Position */
|
||||
#define MXC_F_SPI_WAKE_FL_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_LEVEL_POS)) /**< WAKE_FL_TX_LEVEL Mask */
|
||||
#define MXC_F_SPI_WAKE_FL_TX_LEVEL_POS 0 /**< WAKE_FL_TX_LEVEL Position */
|
||||
#define MXC_F_SPI_WAKE_FL_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_LEVEL_POS)) /**< WAKE_FL_TX_LEVEL Mask */
|
||||
|
||||
#define MXC_F_SPI_WAKE_FL_TX_EMPTY_POS 1 /**< WAKE_FL_TX_EMPTY Position */
|
||||
#define MXC_F_SPI_WAKE_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_EMPTY_POS)) /**< WAKE_FL_TX_EMPTY Mask */
|
||||
#define MXC_F_SPI_WAKE_FL_TX_EMPTY_POS 1 /**< WAKE_FL_TX_EMPTY Position */
|
||||
#define MXC_F_SPI_WAKE_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_EMPTY_POS)) /**< WAKE_FL_TX_EMPTY Mask */
|
||||
|
||||
#define MXC_F_SPI_WAKE_FL_RX_LEVEL_POS 2 /**< WAKE_FL_RX_LEVEL Position */
|
||||
#define MXC_F_SPI_WAKE_FL_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_LEVEL_POS)) /**< WAKE_FL_RX_LEVEL Mask */
|
||||
#define MXC_F_SPI_WAKE_FL_RX_LEVEL_POS 2 /**< WAKE_FL_RX_LEVEL Position */
|
||||
#define MXC_F_SPI_WAKE_FL_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_LEVEL_POS)) /**< WAKE_FL_RX_LEVEL Mask */
|
||||
|
||||
#define MXC_F_SPI_WAKE_FL_RX_FULL_POS 3 /**< WAKE_FL_RX_FULL Position */
|
||||
#define MXC_F_SPI_WAKE_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_FULL_POS)) /**< WAKE_FL_RX_FULL Mask */
|
||||
#define MXC_F_SPI_WAKE_FL_RX_FULL_POS 3 /**< WAKE_FL_RX_FULL Position */
|
||||
#define MXC_F_SPI_WAKE_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_FULL_POS)) /**< WAKE_FL_RX_FULL Mask */
|
||||
|
||||
/**@} end of group SPI_WAKE_FL_Register */
|
||||
|
||||
|
|
@ -410,17 +412,17 @@ typedef struct {
|
|||
* @brief Register for wake up enable.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPI_WAKE_EN_TX_LEVEL_POS 0 /**< WAKE_EN_TX_LEVEL Position */
|
||||
#define MXC_F_SPI_WAKE_EN_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_LEVEL_POS)) /**< WAKE_EN_TX_LEVEL Mask */
|
||||
#define MXC_F_SPI_WAKE_EN_TX_LEVEL_POS 0 /**< WAKE_EN_TX_LEVEL Position */
|
||||
#define MXC_F_SPI_WAKE_EN_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_LEVEL_POS)) /**< WAKE_EN_TX_LEVEL Mask */
|
||||
|
||||
#define MXC_F_SPI_WAKE_EN_TX_EMPTY_POS 1 /**< WAKE_EN_TX_EMPTY Position */
|
||||
#define MXC_F_SPI_WAKE_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_EMPTY_POS)) /**< WAKE_EN_TX_EMPTY Mask */
|
||||
#define MXC_F_SPI_WAKE_EN_TX_EMPTY_POS 1 /**< WAKE_EN_TX_EMPTY Position */
|
||||
#define MXC_F_SPI_WAKE_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_EMPTY_POS)) /**< WAKE_EN_TX_EMPTY Mask */
|
||||
|
||||
#define MXC_F_SPI_WAKE_EN_RX_LEVEL_POS 2 /**< WAKE_EN_RX_LEVEL Position */
|
||||
#define MXC_F_SPI_WAKE_EN_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_LEVEL_POS)) /**< WAKE_EN_RX_LEVEL Mask */
|
||||
#define MXC_F_SPI_WAKE_EN_RX_LEVEL_POS 2 /**< WAKE_EN_RX_LEVEL Position */
|
||||
#define MXC_F_SPI_WAKE_EN_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_LEVEL_POS)) /**< WAKE_EN_RX_LEVEL Mask */
|
||||
|
||||
#define MXC_F_SPI_WAKE_EN_RX_FULL_POS 3 /**< WAKE_EN_RX_FULL Position */
|
||||
#define MXC_F_SPI_WAKE_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_FULL_POS)) /**< WAKE_EN_RX_FULL Mask */
|
||||
#define MXC_F_SPI_WAKE_EN_RX_FULL_POS 3 /**< WAKE_EN_RX_FULL Position */
|
||||
#define MXC_F_SPI_WAKE_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_FULL_POS)) /**< WAKE_EN_RX_FULL Mask */
|
||||
|
||||
/**@} end of group SPI_WAKE_EN_Register */
|
||||
|
||||
|
|
@ -430,8 +432,8 @@ typedef struct {
|
|||
* @brief SPI Status register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPI_STAT_BUSY_POS 0 /**< STAT_BUSY Position */
|
||||
#define MXC_F_SPI_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) /**< STAT_BUSY Mask */
|
||||
#define MXC_F_SPI_STAT_BUSY_POS 0 /**< STAT_BUSY Position */
|
||||
#define MXC_F_SPI_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) /**< STAT_BUSY Mask */
|
||||
|
||||
/**@} end of group SPI_STAT_Register */
|
||||
|
||||
|
|
@ -439,4 +441,4 @@ typedef struct {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SPI_REGS_H_ */
|
||||
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPI_REGS_H_
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
/**
|
||||
* @file spimss_regs.h
|
||||
* @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module.
|
||||
* @note This file is @generated.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +35,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _SPIMSS_REGS_H_
|
||||
#define _SPIMSS_REGS_H_
|
||||
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPIMSS_REGS_H_
|
||||
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPIMSS_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -46,11 +46,11 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__ICCARM__)
|
||||
#pragma system_include
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__CC_ARM)
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
|
@ -67,7 +67,9 @@ extern "C" {
|
|||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
|
||||
#ifndef __R
|
||||
#define __R volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
|
@ -76,7 +78,7 @@ extern "C" {
|
|||
* @ingroup spimss
|
||||
* @defgroup spimss_registers SPIMSS_Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module.
|
||||
* @details Serial Peripheral Interface.
|
||||
* @details Serial Peripheral Interface.
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
@ -85,11 +87,11 @@ extern "C" {
|
|||
*/
|
||||
typedef struct {
|
||||
__IO uint16_t data; /**< <tt>\b 0x00:</tt> SPIMSS DATA Register */
|
||||
__I uint16_t rsv_0x2;
|
||||
__R uint16_t rsv_0x2;
|
||||
__IO uint32_t ctrl; /**< <tt>\b 0x04:</tt> SPIMSS CTRL Register */
|
||||
__IO uint32_t int_fl; /**< <tt>\b 0x08:</tt> SPIMSS INT_FL Register */
|
||||
__IO uint32_t mode; /**< <tt>\b 0x0C:</tt> SPIMSS MODE Register */
|
||||
__I uint32_t rsv_0x10;
|
||||
__R uint32_t rsv_0x10;
|
||||
__IO uint32_t brg; /**< <tt>\b 0x14:</tt> SPIMSS BRG Register */
|
||||
__IO uint32_t dma; /**< <tt>\b 0x18:</tt> SPIMSS DMA Register */
|
||||
__IO uint32_t i2s_ctrl; /**< <tt>\b 0x1C:</tt> SPIMSS I2S_CTRL Register */
|
||||
|
|
@ -99,16 +101,16 @@ typedef struct {
|
|||
/**
|
||||
* @ingroup spimss_registers
|
||||
* @defgroup SPIMSS_Register_Offsets Register Offsets
|
||||
* @brief SPIMSS Peripheral Register Offsets from the SPIMSS Base Peripheral Address.
|
||||
* @brief SPIMSS Peripheral Register Offsets from the SPIMSS Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_SPIMSS_DATA ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_SPIMSS_CTRL ((uint32_t)0x00000004UL) /**< Offset from SPIMSS Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_SPIMSS_INT_FL ((uint32_t)0x00000008UL) /**< Offset from SPIMSS Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_SPIMSS_MODE ((uint32_t)0x0000000CUL) /**< Offset from SPIMSS Base Address: <tt> 0x000C</tt> */
|
||||
#define MXC_R_SPIMSS_BRG ((uint32_t)0x00000014UL) /**< Offset from SPIMSS Base Address: <tt> 0x0014</tt> */
|
||||
#define MXC_R_SPIMSS_DMA ((uint32_t)0x00000018UL) /**< Offset from SPIMSS Base Address: <tt> 0x0018</tt> */
|
||||
#define MXC_R_SPIMSS_I2S_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIMSS Base Address: <tt> 0x001C</tt> */
|
||||
#define MXC_R_SPIMSS_DATA ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_SPIMSS_CTRL ((uint32_t)0x00000004UL) /**< Offset from SPIMSS Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_SPIMSS_INT_FL ((uint32_t)0x00000008UL) /**< Offset from SPIMSS Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_SPIMSS_MODE ((uint32_t)0x0000000CUL) /**< Offset from SPIMSS Base Address: <tt> 0x000C</tt> */
|
||||
#define MXC_R_SPIMSS_BRG ((uint32_t)0x00000014UL) /**< Offset from SPIMSS Base Address: <tt> 0x0014</tt> */
|
||||
#define MXC_R_SPIMSS_DMA ((uint32_t)0x00000018UL) /**< Offset from SPIMSS Base Address: <tt> 0x0018</tt> */
|
||||
#define MXC_R_SPIMSS_I2S_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIMSS Base Address: <tt> 0x001C</tt> */
|
||||
/**@} end of group spimss_registers */
|
||||
|
||||
/**
|
||||
|
|
@ -117,8 +119,8 @@ typedef struct {
|
|||
* @brief SPI 16-bit Data Access
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIMSS_DATA_DATA_POS 0 /**< DATA_DATA Position */
|
||||
#define MXC_F_SPIMSS_DATA_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIMSS_DATA_DATA_POS)) /**< DATA_DATA Mask */
|
||||
#define MXC_F_SPIMSS_DATA_DATA_POS 0 /**< DATA_DATA Position */
|
||||
#define MXC_F_SPIMSS_DATA_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIMSS_DATA_DATA_POS)) /**< DATA_DATA Mask */
|
||||
|
||||
/**@} end of group SPIMSS_DATA_Register */
|
||||
|
||||
|
|
@ -128,29 +130,29 @@ typedef struct {
|
|||
* @brief SPI Control Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIMSS_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */
|
||||
#define MXC_F_SPIMSS_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */
|
||||
#define MXC_F_SPIMSS_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */
|
||||
#define MXC_F_SPIMSS_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_CTRL_MMEN_POS 1 /**< CTRL_MMEN Position */
|
||||
#define MXC_F_SPIMSS_CTRL_MMEN ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_MMEN_POS)) /**< CTRL_MMEN Mask */
|
||||
#define MXC_F_SPIMSS_CTRL_MMEN_POS 1 /**< CTRL_MMEN Position */
|
||||
#define MXC_F_SPIMSS_CTRL_MMEN ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_MMEN_POS)) /**< CTRL_MMEN Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_CTRL_WOR_POS 2 /**< CTRL_WOR Position */
|
||||
#define MXC_F_SPIMSS_CTRL_WOR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_WOR_POS)) /**< CTRL_WOR Mask */
|
||||
#define MXC_F_SPIMSS_CTRL_WOR_POS 2 /**< CTRL_WOR Position */
|
||||
#define MXC_F_SPIMSS_CTRL_WOR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_WOR_POS)) /**< CTRL_WOR Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_CTRL_CLKPOL_POS 3 /**< CTRL_CLKPOL Position */
|
||||
#define MXC_F_SPIMSS_CTRL_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_CLKPOL_POS)) /**< CTRL_CLKPOL Mask */
|
||||
#define MXC_F_SPIMSS_CTRL_CLKPOL_POS 3 /**< CTRL_CLKPOL Position */
|
||||
#define MXC_F_SPIMSS_CTRL_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_CLKPOL_POS)) /**< CTRL_CLKPOL Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_CTRL_PHASE_POS 4 /**< CTRL_PHASE Position */
|
||||
#define MXC_F_SPIMSS_CTRL_PHASE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_PHASE_POS)) /**< CTRL_PHASE Mask */
|
||||
#define MXC_F_SPIMSS_CTRL_PHASE_POS 4 /**< CTRL_PHASE Position */
|
||||
#define MXC_F_SPIMSS_CTRL_PHASE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_PHASE_POS)) /**< CTRL_PHASE Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_CTRL_BIRQ_POS 5 /**< CTRL_BIRQ Position */
|
||||
#define MXC_F_SPIMSS_CTRL_BIRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_BIRQ_POS)) /**< CTRL_BIRQ Mask */
|
||||
#define MXC_F_SPIMSS_CTRL_BIRQ_POS 5 /**< CTRL_BIRQ Position */
|
||||
#define MXC_F_SPIMSS_CTRL_BIRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_BIRQ_POS)) /**< CTRL_BIRQ Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_CTRL_STR_POS 6 /**< CTRL_STR Position */
|
||||
#define MXC_F_SPIMSS_CTRL_STR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_STR_POS)) /**< CTRL_STR Mask */
|
||||
#define MXC_F_SPIMSS_CTRL_STR_POS 6 /**< CTRL_STR Position */
|
||||
#define MXC_F_SPIMSS_CTRL_STR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_STR_POS)) /**< CTRL_STR Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_CTRL_IRQE_POS 7 /**< CTRL_IRQE Position */
|
||||
#define MXC_F_SPIMSS_CTRL_IRQE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_IRQE_POS)) /**< CTRL_IRQE Mask */
|
||||
#define MXC_F_SPIMSS_CTRL_IRQE_POS 7 /**< CTRL_IRQE Position */
|
||||
#define MXC_F_SPIMSS_CTRL_IRQE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_IRQE_POS)) /**< CTRL_IRQE Mask */
|
||||
|
||||
/**@} end of group SPIMSS_CTRL_Register */
|
||||
|
||||
|
|
@ -160,29 +162,29 @@ typedef struct {
|
|||
* @brief SPI Interrupt Flag Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIMSS_INT_FL_SLAS_POS 0 /**< INT_FL_SLAS Position */
|
||||
#define MXC_F_SPIMSS_INT_FL_SLAS ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_SLAS_POS)) /**< INT_FL_SLAS Mask */
|
||||
#define MXC_F_SPIMSS_INT_FL_SLAS_POS 0 /**< INT_FL_SLAS Position */
|
||||
#define MXC_F_SPIMSS_INT_FL_SLAS ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_SLAS_POS)) /**< INT_FL_SLAS Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_INT_FL_TXST_POS 1 /**< INT_FL_TXST Position */
|
||||
#define MXC_F_SPIMSS_INT_FL_TXST ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TXST_POS)) /**< INT_FL_TXST Mask */
|
||||
#define MXC_F_SPIMSS_INT_FL_TXST_POS 1 /**< INT_FL_TXST Position */
|
||||
#define MXC_F_SPIMSS_INT_FL_TXST ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TXST_POS)) /**< INT_FL_TXST Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_INT_FL_TUND_POS 2 /**< INT_FL_TUND Position */
|
||||
#define MXC_F_SPIMSS_INT_FL_TUND ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TUND_POS)) /**< INT_FL_TUND Mask */
|
||||
#define MXC_F_SPIMSS_INT_FL_TUND_POS 2 /**< INT_FL_TUND Position */
|
||||
#define MXC_F_SPIMSS_INT_FL_TUND ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TUND_POS)) /**< INT_FL_TUND Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_INT_FL_ROVR_POS 3 /**< INT_FL_ROVR Position */
|
||||
#define MXC_F_SPIMSS_INT_FL_ROVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_ROVR_POS)) /**< INT_FL_ROVR Mask */
|
||||
#define MXC_F_SPIMSS_INT_FL_ROVR_POS 3 /**< INT_FL_ROVR Position */
|
||||
#define MXC_F_SPIMSS_INT_FL_ROVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_ROVR_POS)) /**< INT_FL_ROVR Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_INT_FL_ABT_POS 4 /**< INT_FL_ABT Position */
|
||||
#define MXC_F_SPIMSS_INT_FL_ABT ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_ABT_POS)) /**< INT_FL_ABT Mask */
|
||||
#define MXC_F_SPIMSS_INT_FL_ABT_POS 4 /**< INT_FL_ABT Position */
|
||||
#define MXC_F_SPIMSS_INT_FL_ABT ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_ABT_POS)) /**< INT_FL_ABT Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_INT_FL_COL_POS 5 /**< INT_FL_COL Position */
|
||||
#define MXC_F_SPIMSS_INT_FL_COL ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_COL_POS)) /**< INT_FL_COL Mask */
|
||||
#define MXC_F_SPIMSS_INT_FL_COL_POS 5 /**< INT_FL_COL Position */
|
||||
#define MXC_F_SPIMSS_INT_FL_COL ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_COL_POS)) /**< INT_FL_COL Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_INT_FL_TOVR_POS 6 /**< INT_FL_TOVR Position */
|
||||
#define MXC_F_SPIMSS_INT_FL_TOVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TOVR_POS)) /**< INT_FL_TOVR Mask */
|
||||
#define MXC_F_SPIMSS_INT_FL_TOVR_POS 6 /**< INT_FL_TOVR Position */
|
||||
#define MXC_F_SPIMSS_INT_FL_TOVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TOVR_POS)) /**< INT_FL_TOVR Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_INT_FL_IRQ_POS 7 /**< INT_FL_IRQ Position */
|
||||
#define MXC_F_SPIMSS_INT_FL_IRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_IRQ_POS)) /**< INT_FL_IRQ Mask */
|
||||
#define MXC_F_SPIMSS_INT_FL_IRQ_POS 7 /**< INT_FL_IRQ Position */
|
||||
#define MXC_F_SPIMSS_INT_FL_IRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_IRQ_POS)) /**< INT_FL_IRQ Mask */
|
||||
|
||||
/**@} end of group SPIMSS_INT_FL_Register */
|
||||
|
||||
|
|
@ -192,49 +194,49 @@ typedef struct {
|
|||
* @brief SPI Mode Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIMSS_MODE_SSV_POS 0 /**< MODE_SSV Position */
|
||||
#define MXC_F_SPIMSS_MODE_SSV ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_SSV_POS)) /**< MODE_SSV Mask */
|
||||
#define MXC_F_SPIMSS_MODE_SSV_POS 0 /**< MODE_SSV Position */
|
||||
#define MXC_F_SPIMSS_MODE_SSV ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_SSV_POS)) /**< MODE_SSV Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_MODE_SS_IO_POS 1 /**< MODE_SS_IO Position */
|
||||
#define MXC_F_SPIMSS_MODE_SS_IO ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_SS_IO_POS)) /**< MODE_SS_IO Mask */
|
||||
#define MXC_F_SPIMSS_MODE_SS_IO_POS 1 /**< MODE_SS_IO Position */
|
||||
#define MXC_F_SPIMSS_MODE_SS_IO ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_SS_IO_POS)) /**< MODE_SS_IO Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_MODE_NUMBITS_POS 2 /**< MODE_NUMBITS Position */
|
||||
#define MXC_F_SPIMSS_MODE_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIMSS_MODE_NUMBITS_POS)) /**< MODE_NUMBITS Mask */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS16 ((uint32_t)0x0UL) /**< MODE_NUMBITS_BITS16 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS16 (MXC_V_SPIMSS_MODE_NUMBITS_BITS16 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS16 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS1 ((uint32_t)0x1UL) /**< MODE_NUMBITS_BITS1 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS1 (MXC_V_SPIMSS_MODE_NUMBITS_BITS1 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS1 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS2 ((uint32_t)0x2UL) /**< MODE_NUMBITS_BITS2 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS2 (MXC_V_SPIMSS_MODE_NUMBITS_BITS2 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS2 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS3 ((uint32_t)0x3UL) /**< MODE_NUMBITS_BITS3 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS3 (MXC_V_SPIMSS_MODE_NUMBITS_BITS3 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS3 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS4 ((uint32_t)0x4UL) /**< MODE_NUMBITS_BITS4 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS4 (MXC_V_SPIMSS_MODE_NUMBITS_BITS4 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS4 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS5 ((uint32_t)0x5UL) /**< MODE_NUMBITS_BITS5 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS5 (MXC_V_SPIMSS_MODE_NUMBITS_BITS5 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS5 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS6 ((uint32_t)0x6UL) /**< MODE_NUMBITS_BITS6 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS6 (MXC_V_SPIMSS_MODE_NUMBITS_BITS6 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS6 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS7 ((uint32_t)0x7UL) /**< MODE_NUMBITS_BITS7 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS7 (MXC_V_SPIMSS_MODE_NUMBITS_BITS7 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS7 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS8 ((uint32_t)0x8UL) /**< MODE_NUMBITS_BITS8 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS8 (MXC_V_SPIMSS_MODE_NUMBITS_BITS8 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS8 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS9 ((uint32_t)0x9UL) /**< MODE_NUMBITS_BITS9 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS9 (MXC_V_SPIMSS_MODE_NUMBITS_BITS9 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS9 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS10 ((uint32_t)0xAUL) /**< MODE_NUMBITS_BITS10 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS10 (MXC_V_SPIMSS_MODE_NUMBITS_BITS10 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS10 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS11 ((uint32_t)0xBUL) /**< MODE_NUMBITS_BITS11 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS11 (MXC_V_SPIMSS_MODE_NUMBITS_BITS11 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS11 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS12 ((uint32_t)0xCUL) /**< MODE_NUMBITS_BITS12 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS12 (MXC_V_SPIMSS_MODE_NUMBITS_BITS12 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS12 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS13 ((uint32_t)0xDUL) /**< MODE_NUMBITS_BITS13 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS13 (MXC_V_SPIMSS_MODE_NUMBITS_BITS13 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS13 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS14 ((uint32_t)0xEUL) /**< MODE_NUMBITS_BITS14 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS14 (MXC_V_SPIMSS_MODE_NUMBITS_BITS14 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS14 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS15 ((uint32_t)0xFUL) /**< MODE_NUMBITS_BITS15 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS15 (MXC_V_SPIMSS_MODE_NUMBITS_BITS15 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS15 Setting */
|
||||
#define MXC_F_SPIMSS_MODE_NUMBITS_POS 2 /**< MODE_NUMBITS Position */
|
||||
#define MXC_F_SPIMSS_MODE_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIMSS_MODE_NUMBITS_POS)) /**< MODE_NUMBITS Mask */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS16 ((uint32_t)0x0UL) /**< MODE_NUMBITS_BITS16 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS16 (MXC_V_SPIMSS_MODE_NUMBITS_BITS16 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS16 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS1 ((uint32_t)0x1UL) /**< MODE_NUMBITS_BITS1 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS1 (MXC_V_SPIMSS_MODE_NUMBITS_BITS1 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS1 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS2 ((uint32_t)0x2UL) /**< MODE_NUMBITS_BITS2 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS2 (MXC_V_SPIMSS_MODE_NUMBITS_BITS2 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS2 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS3 ((uint32_t)0x3UL) /**< MODE_NUMBITS_BITS3 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS3 (MXC_V_SPIMSS_MODE_NUMBITS_BITS3 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS3 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS4 ((uint32_t)0x4UL) /**< MODE_NUMBITS_BITS4 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS4 (MXC_V_SPIMSS_MODE_NUMBITS_BITS4 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS4 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS5 ((uint32_t)0x5UL) /**< MODE_NUMBITS_BITS5 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS5 (MXC_V_SPIMSS_MODE_NUMBITS_BITS5 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS5 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS6 ((uint32_t)0x6UL) /**< MODE_NUMBITS_BITS6 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS6 (MXC_V_SPIMSS_MODE_NUMBITS_BITS6 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS6 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS7 ((uint32_t)0x7UL) /**< MODE_NUMBITS_BITS7 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS7 (MXC_V_SPIMSS_MODE_NUMBITS_BITS7 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS7 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS8 ((uint32_t)0x8UL) /**< MODE_NUMBITS_BITS8 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS8 (MXC_V_SPIMSS_MODE_NUMBITS_BITS8 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS8 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS9 ((uint32_t)0x9UL) /**< MODE_NUMBITS_BITS9 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS9 (MXC_V_SPIMSS_MODE_NUMBITS_BITS9 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS9 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS10 ((uint32_t)0xAUL) /**< MODE_NUMBITS_BITS10 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS10 (MXC_V_SPIMSS_MODE_NUMBITS_BITS10 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS10 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS11 ((uint32_t)0xBUL) /**< MODE_NUMBITS_BITS11 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS11 (MXC_V_SPIMSS_MODE_NUMBITS_BITS11 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS11 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS12 ((uint32_t)0xCUL) /**< MODE_NUMBITS_BITS12 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS12 (MXC_V_SPIMSS_MODE_NUMBITS_BITS12 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS12 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS13 ((uint32_t)0xDUL) /**< MODE_NUMBITS_BITS13 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS13 (MXC_V_SPIMSS_MODE_NUMBITS_BITS13 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS13 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS14 ((uint32_t)0xEUL) /**< MODE_NUMBITS_BITS14 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS14 (MXC_V_SPIMSS_MODE_NUMBITS_BITS14 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS14 Setting */
|
||||
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS15 ((uint32_t)0xFUL) /**< MODE_NUMBITS_BITS15 Value */
|
||||
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS15 (MXC_V_SPIMSS_MODE_NUMBITS_BITS15 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS15 Setting */
|
||||
|
||||
#define MXC_F_SPIMSS_MODE_TX_LJ_POS 7 /**< MODE_TX_LJ Position */
|
||||
#define MXC_F_SPIMSS_MODE_TX_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_TX_LJ_POS)) /**< MODE_TX_LJ Mask */
|
||||
#define MXC_F_SPIMSS_MODE_TX_LJ_POS 7 /**< MODE_TX_LJ Position */
|
||||
#define MXC_F_SPIMSS_MODE_TX_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_TX_LJ_POS)) /**< MODE_TX_LJ Mask */
|
||||
|
||||
/**@} end of group SPIMSS_MODE_Register */
|
||||
|
||||
|
|
@ -247,8 +249,8 @@ typedef struct {
|
|||
* 4).
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIMSS_BRG_DIV_POS 0 /**< BRG_DIV Position */
|
||||
#define MXC_F_SPIMSS_BRG_DIV ((uint32_t)(0xFFFFUL << MXC_F_SPIMSS_BRG_DIV_POS)) /**< BRG_DIV Mask */
|
||||
#define MXC_F_SPIMSS_BRG_DIV_POS 0 /**< BRG_DIV Position */
|
||||
#define MXC_F_SPIMSS_BRG_DIV ((uint32_t)(0xFFFFUL << MXC_F_SPIMSS_BRG_DIV_POS)) /**< BRG_DIV Mask */
|
||||
|
||||
/**@} end of group SPIMSS_BRG_Register */
|
||||
|
||||
|
|
@ -258,61 +260,61 @@ typedef struct {
|
|||
* @brief SPI DMA Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS 0 /**< DMA_TX_FIFO_LVL Position */
|
||||
#define MXC_F_SPIMSS_DMA_TX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)) /**< DMA_TX_FIFO_LVL Mask */
|
||||
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_TX_FIFO_LVL_ENTRY1 Value */
|
||||
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRY1 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_TX_FIFO_LVL_ENTRIES2 Value */
|
||||
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES2 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_TX_FIFO_LVL_ENTRIES3 Value */
|
||||
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES3 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_TX_FIFO_LVL_ENTRIES4 Value */
|
||||
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES4 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_TX_FIFO_LVL_ENTRIES5 Value */
|
||||
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES5 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_TX_FIFO_LVL_ENTRIES6 Value */
|
||||
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES6 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_TX_FIFO_LVL_ENTRIES7 Value */
|
||||
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES7 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_TX_FIFO_LVL_ENTRIES8 Value */
|
||||
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES8 Setting */
|
||||
#define MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS 0 /**< DMA_TX_FIFO_LVL Position */
|
||||
#define MXC_F_SPIMSS_DMA_TX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)) /**< DMA_TX_FIFO_LVL Mask */
|
||||
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_TX_FIFO_LVL_ENTRY1 Value */
|
||||
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRY1 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_TX_FIFO_LVL_ENTRIES2 Value */
|
||||
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES2 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_TX_FIFO_LVL_ENTRIES3 Value */
|
||||
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES3 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_TX_FIFO_LVL_ENTRIES4 Value */
|
||||
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES4 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_TX_FIFO_LVL_ENTRIES5 Value */
|
||||
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES5 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_TX_FIFO_LVL_ENTRIES6 Value */
|
||||
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES6 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_TX_FIFO_LVL_ENTRIES7 Value */
|
||||
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES7 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_TX_FIFO_LVL_ENTRIES8 Value */
|
||||
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES8 Setting */
|
||||
|
||||
#define MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS 4 /**< DMA_TX_FIFO_CLR Position */
|
||||
#define MXC_F_SPIMSS_DMA_TX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS)) /**< DMA_TX_FIFO_CLR Mask */
|
||||
#define MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS 4 /**< DMA_TX_FIFO_CLR Position */
|
||||
#define MXC_F_SPIMSS_DMA_TX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS)) /**< DMA_TX_FIFO_CLR Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */
|
||||
#define MXC_F_SPIMSS_DMA_TX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */
|
||||
#define MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */
|
||||
#define MXC_F_SPIMSS_DMA_TX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */
|
||||
#define MXC_F_SPIMSS_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */
|
||||
#define MXC_F_SPIMSS_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */
|
||||
#define MXC_F_SPIMSS_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS 16 /**< DMA_RX_FIFO_LVL Position */
|
||||
#define MXC_F_SPIMSS_DMA_RX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)) /**< DMA_RX_FIFO_LVL Mask */
|
||||
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_RX_FIFO_LVL_ENTRY1 Value */
|
||||
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRY1 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_RX_FIFO_LVL_ENTRIES2 Value */
|
||||
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES2 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_RX_FIFO_LVL_ENTRIES3 Value */
|
||||
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES3 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_RX_FIFO_LVL_ENTRIES4 Value */
|
||||
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES4 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_RX_FIFO_LVL_ENTRIES5 Value */
|
||||
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES5 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_RX_FIFO_LVL_ENTRIES6 Value */
|
||||
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES6 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_RX_FIFO_LVL_ENTRIES7 Value */
|
||||
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES7 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_RX_FIFO_LVL_ENTRIES8 Value */
|
||||
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES8 Setting */
|
||||
#define MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS 16 /**< DMA_RX_FIFO_LVL Position */
|
||||
#define MXC_F_SPIMSS_DMA_RX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)) /**< DMA_RX_FIFO_LVL Mask */
|
||||
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_RX_FIFO_LVL_ENTRY1 Value */
|
||||
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRY1 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_RX_FIFO_LVL_ENTRIES2 Value */
|
||||
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES2 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_RX_FIFO_LVL_ENTRIES3 Value */
|
||||
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES3 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_RX_FIFO_LVL_ENTRIES4 Value */
|
||||
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES4 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_RX_FIFO_LVL_ENTRIES5 Value */
|
||||
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES5 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_RX_FIFO_LVL_ENTRIES6 Value */
|
||||
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES6 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_RX_FIFO_LVL_ENTRIES7 Value */
|
||||
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES7 Setting */
|
||||
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_RX_FIFO_LVL_ENTRIES8 Value */
|
||||
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES8 Setting */
|
||||
|
||||
#define MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS 20 /**< DMA_RX_FIFO_CLR Position */
|
||||
#define MXC_F_SPIMSS_DMA_RX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS)) /**< DMA_RX_FIFO_CLR Mask */
|
||||
#define MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS 20 /**< DMA_RX_FIFO_CLR Position */
|
||||
#define MXC_F_SPIMSS_DMA_RX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS)) /**< DMA_RX_FIFO_CLR Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */
|
||||
#define MXC_F_SPIMSS_DMA_RX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */
|
||||
#define MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */
|
||||
#define MXC_F_SPIMSS_DMA_RX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */
|
||||
#define MXC_F_SPIMSS_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */
|
||||
#define MXC_F_SPIMSS_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */
|
||||
#define MXC_F_SPIMSS_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */
|
||||
|
||||
/**@} end of group SPIMSS_DMA_Register */
|
||||
|
||||
|
|
@ -322,20 +324,20 @@ typedef struct {
|
|||
* @brief I2S Control Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS 0 /**< I2S_CTRL_I2S_EN Position */
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS)) /**< I2S_CTRL_I2S_EN Mask */
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS 0 /**< I2S_CTRL_I2S_EN Position */
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS)) /**< I2S_CTRL_I2S_EN Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS 1 /**< I2S_CTRL_I2S_MUTE Position */
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS)) /**< I2S_CTRL_I2S_MUTE Mask */
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS 1 /**< I2S_CTRL_I2S_MUTE Position */
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS)) /**< I2S_CTRL_I2S_MUTE Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS 2 /**< I2S_CTRL_I2S_PAUSE Position */
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS)) /**< I2S_CTRL_I2S_PAUSE Mask */
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS 2 /**< I2S_CTRL_I2S_PAUSE Position */
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS)) /**< I2S_CTRL_I2S_PAUSE Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS 3 /**< I2S_CTRL_I2S_MONO Position */
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS)) /**< I2S_CTRL_I2S_MONO Mask */
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS 3 /**< I2S_CTRL_I2S_MONO Position */
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS)) /**< I2S_CTRL_I2S_MONO Mask */
|
||||
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS 4 /**< I2S_CTRL_I2S_LJ Position */
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS)) /**< I2S_CTRL_I2S_LJ Mask */
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS 4 /**< I2S_CTRL_I2S_LJ Position */
|
||||
#define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS)) /**< I2S_CTRL_I2S_LJ Mask */
|
||||
|
||||
/**@} end of group SPIMSS_I2S_CTRL_Register */
|
||||
|
||||
|
|
@ -343,4 +345,4 @@ typedef struct {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SPIMSS_REGS_H_ */
|
||||
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPIMSS_REGS_H_
|
||||
|
|
|
|||
|
|
@ -3,9 +3,8 @@
|
|||
* @brief System-specific header file
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -35,11 +34,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _SYSTEM_MAX32660_H_
|
||||
#define _SYSTEM_MAX32660_H_
|
||||
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SYSTEM_MAX32660_H_
|
||||
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SYSTEM_MAX32660_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
|
@ -52,20 +50,22 @@ extern "C" {
|
|||
*----------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef HFX_FREQ
|
||||
#define HFX_FREQ 32768
|
||||
#define HFX_FREQ 32768
|
||||
#endif
|
||||
|
||||
/* NOTE: This is the nominal value for NANORING. The actual value may vary from chip to chip.
|
||||
Update if use of this oscillator requires precise timing.*/
|
||||
#ifndef NANORING_FREQ
|
||||
#define NANORING_FREQ 8000
|
||||
#define NANORING_FREQ 8000
|
||||
#endif
|
||||
|
||||
#ifndef HIRC96_FREQ
|
||||
#define HIRC96_FREQ 96000000
|
||||
#define HIRC96_FREQ 96000000
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
#ifndef PeripheralClock
|
||||
#define PeripheralClock (SystemCoreClock /2) /*!< Peripheral Clock Frequency */
|
||||
#define PeripheralClock (SystemCoreClock / 2) /*!< Peripheral Clock Frequency */
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -88,4 +88,4 @@ void SystemCoreClockUpdate(void);
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SYSTEM_MAX32660_H_ */
|
||||
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SYSTEM_MAX32660_H_
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
/**
|
||||
* @file tmr_regs.h
|
||||
* @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
|
||||
* @note This file is @generated.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +35,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _TMR_REGS_H_
|
||||
#define _TMR_REGS_H_
|
||||
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_TMR_REGS_H_
|
||||
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_TMR_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -46,11 +46,11 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__ICCARM__)
|
||||
#pragma system_include
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__CC_ARM)
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
|
@ -67,7 +67,9 @@ extern "C" {
|
|||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
|
||||
#ifndef __R
|
||||
#define __R volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
|
@ -76,7 +78,7 @@ extern "C" {
|
|||
* @ingroup tmr
|
||||
* @defgroup tmr_registers TMR_Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
|
||||
* @details Low-Power Configurable Timer
|
||||
* @details Low-Power Configurable Timer
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
@ -95,14 +97,14 @@ typedef struct {
|
|||
/**
|
||||
* @ingroup tmr_registers
|
||||
* @defgroup TMR_Register_Offsets Register Offsets
|
||||
* @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address.
|
||||
* @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_TMR_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_TMR_INTR ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> 0x000C</tt> */
|
||||
#define MXC_R_TMR_CN ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> 0x0010</tt> */
|
||||
#define MXC_R_TMR_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_TMR_INTR ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> 0x000C</tt> */
|
||||
#define MXC_R_TMR_CN ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> 0x0010</tt> */
|
||||
/**@} end of group tmr_registers */
|
||||
|
||||
/**
|
||||
|
|
@ -111,8 +113,8 @@ typedef struct {
|
|||
* @brief Timer Counter Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_TMR_CNT_COUNT_POS 0 /**< CNT_COUNT Position */
|
||||
#define MXC_F_TMR_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CNT_COUNT_POS)) /**< CNT_COUNT Mask */
|
||||
#define MXC_F_TMR_CNT_COUNT_POS 0 /**< CNT_COUNT Position */
|
||||
#define MXC_F_TMR_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CNT_COUNT_POS)) /**< CNT_COUNT Mask */
|
||||
|
||||
/**@} end of group TMR_CNT_Register */
|
||||
|
||||
|
|
@ -122,8 +124,8 @@ typedef struct {
|
|||
* @brief Timer Compare Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_TMR_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */
|
||||
#define MXC_F_TMR_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */
|
||||
#define MXC_F_TMR_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */
|
||||
#define MXC_F_TMR_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */
|
||||
|
||||
/**@} end of group TMR_CMP_Register */
|
||||
|
||||
|
|
@ -133,8 +135,8 @@ typedef struct {
|
|||
* @brief Timer PWM Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_TMR_PWM_PWM_POS 0 /**< PWM_PWM Position */
|
||||
#define MXC_F_TMR_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_PWM_PWM_POS)) /**< PWM_PWM Mask */
|
||||
#define MXC_F_TMR_PWM_PWM_POS 0 /**< PWM_PWM Position */
|
||||
#define MXC_F_TMR_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_PWM_PWM_POS)) /**< PWM_PWM Mask */
|
||||
|
||||
/**@} end of group TMR_PWM_Register */
|
||||
|
||||
|
|
@ -144,8 +146,8 @@ typedef struct {
|
|||
* @brief Timer Interrupt Status Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_TMR_INTR_IRQ_POS 0 /**< INTR_IRQ Position */
|
||||
#define MXC_F_TMR_INTR_IRQ ((uint32_t)(0x1UL << MXC_F_TMR_INTR_IRQ_POS)) /**< INTR_IRQ Mask */
|
||||
#define MXC_F_TMR_INTR_IRQ_POS 0 /**< INTR_IRQ Position */
|
||||
#define MXC_F_TMR_INTR_IRQ ((uint32_t)(0x1UL << MXC_F_TMR_INTR_IRQ_POS)) /**< INTR_IRQ Mask */
|
||||
|
||||
/**@} end of group TMR_INTR_Register */
|
||||
|
||||
|
|
@ -155,80 +157,76 @@ typedef struct {
|
|||
* @brief Timer Control Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */
|
||||
#define MXC_F_TMR_CN_TMODE ((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */
|
||||
#define MXC_V_TMR_CN_TMODE_ONE_SHOT ((uint32_t)0x0UL) /**< CN_TMODE_ONE_SHOT Value */
|
||||
#define MXC_S_TMR_CN_TMODE_ONE_SHOT (MXC_V_TMR_CN_TMODE_ONE_SHOT << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONE_SHOT Setting */
|
||||
#define MXC_V_TMR_CN_TMODE_CONTINUOUS ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */
|
||||
#define MXC_S_TMR_CN_TMODE_CONTINUOUS (MXC_V_TMR_CN_TMODE_CONTINUOUS << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */
|
||||
#define MXC_V_TMR_CN_TMODE_COUNTER ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */
|
||||
#define MXC_S_TMR_CN_TMODE_COUNTER (MXC_V_TMR_CN_TMODE_COUNTER << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */
|
||||
#define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */
|
||||
#define MXC_S_TMR_CN_TMODE_PWM (MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */
|
||||
#define MXC_V_TMR_CN_TMODE_CAPTURE ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */
|
||||
#define MXC_S_TMR_CN_TMODE_CAPTURE (MXC_V_TMR_CN_TMODE_CAPTURE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */
|
||||
#define MXC_V_TMR_CN_TMODE_COMPARE ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */
|
||||
#define MXC_S_TMR_CN_TMODE_COMPARE (MXC_V_TMR_CN_TMODE_COMPARE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */
|
||||
#define MXC_V_TMR_CN_TMODE_GATED ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value */
|
||||
#define MXC_S_TMR_CN_TMODE_GATED (MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */
|
||||
#define MXC_V_TMR_CN_TMODE_CAPCOMP ((uint32_t)0x7UL) /**< CN_TMODE_CAPCOMP Value */
|
||||
#define MXC_S_TMR_CN_TMODE_CAPCOMP (MXC_V_TMR_CN_TMODE_CAPCOMP << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPCOMP Setting */
|
||||
#define MXC_V_TMR_CN_TMODE_DUAL_EDGE ((uint32_t)0x8UL) /**< CN_TMODE_DUAL_EDGE Value */
|
||||
#define MXC_S_TMR_CN_TMODE_DUAL_EDGE (MXC_V_TMR_CN_TMODE_DUAL_EDGE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_DUAL_EDGE Setting */
|
||||
#define MXC_V_TMR_CN_TMODE_IGATED ((uint32_t)0xCUL) /**< CN_TMODE_IGATED Value */
|
||||
#define MXC_S_TMR_CN_TMODE_IGATED (MXC_V_TMR_CN_TMODE_IGATED << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_IGATED Setting */
|
||||
#define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */
|
||||
#define MXC_F_TMR_CN_TMODE ((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */
|
||||
#define MXC_V_TMR_CN_TMODE_ONE_SHOT ((uint32_t)0x0UL) /**< CN_TMODE_ONE_SHOT Value */
|
||||
#define MXC_S_TMR_CN_TMODE_ONE_SHOT (MXC_V_TMR_CN_TMODE_ONE_SHOT << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONE_SHOT Setting */
|
||||
#define MXC_V_TMR_CN_TMODE_CONTINUOUS ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */
|
||||
#define MXC_S_TMR_CN_TMODE_CONTINUOUS (MXC_V_TMR_CN_TMODE_CONTINUOUS << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */
|
||||
#define MXC_V_TMR_CN_TMODE_COUNTER ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */
|
||||
#define MXC_S_TMR_CN_TMODE_COUNTER (MXC_V_TMR_CN_TMODE_COUNTER << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */
|
||||
#define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */
|
||||
#define MXC_S_TMR_CN_TMODE_PWM (MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */
|
||||
#define MXC_V_TMR_CN_TMODE_CAPTURE ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */
|
||||
#define MXC_S_TMR_CN_TMODE_CAPTURE (MXC_V_TMR_CN_TMODE_CAPTURE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */
|
||||
#define MXC_V_TMR_CN_TMODE_COMPARE ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */
|
||||
#define MXC_S_TMR_CN_TMODE_COMPARE (MXC_V_TMR_CN_TMODE_COMPARE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */
|
||||
#define MXC_V_TMR_CN_TMODE_GATED ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value */
|
||||
#define MXC_S_TMR_CN_TMODE_GATED (MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */
|
||||
#define MXC_V_TMR_CN_TMODE_CAPCOMP ((uint32_t)0x7UL) /**< CN_TMODE_CAPCOMP Value */
|
||||
#define MXC_S_TMR_CN_TMODE_CAPCOMP (MXC_V_TMR_CN_TMODE_CAPCOMP << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPCOMP Setting */
|
||||
|
||||
#define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */
|
||||
#define MXC_F_TMR_CN_PRES ((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_1 ((uint32_t)0x0UL) /**< CN_PRES_DIV_BY_1 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_1 (MXC_V_TMR_CN_PRES_DIV_BY_1 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_1 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_2 ((uint32_t)0x1UL) /**< CN_PRES_DIV_BY_2 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_2 (MXC_V_TMR_CN_PRES_DIV_BY_2 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_2 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_4 ((uint32_t)0x2UL) /**< CN_PRES_DIV_BY_4 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_4 (MXC_V_TMR_CN_PRES_DIV_BY_4 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_4 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_8 ((uint32_t)0x3UL) /**< CN_PRES_DIV_BY_8 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_8 (MXC_V_TMR_CN_PRES_DIV_BY_8 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_8 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_16 ((uint32_t)0x4UL) /**< CN_PRES_DIV_BY_16 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_16 (MXC_V_TMR_CN_PRES_DIV_BY_16 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_16 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_32 ((uint32_t)0x5UL) /**< CN_PRES_DIV_BY_32 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_32 (MXC_V_TMR_CN_PRES_DIV_BY_32 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_32 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_64 ((uint32_t)0x6UL) /**< CN_PRES_DIV_BY_64 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_64 (MXC_V_TMR_CN_PRES_DIV_BY_64 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_64 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_128 ((uint32_t)0x7UL) /**< CN_PRES_DIV_BY_128 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_128 (MXC_V_TMR_CN_PRES_DIV_BY_128 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_128 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_256 ((uint32_t)0x8UL) /**< CN_PRES_DIV_BY_256 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_256 (MXC_V_TMR_CN_PRES_DIV_BY_256 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_256 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_512 ((uint32_t)0x9UL) /**< CN_PRES_DIV_BY_512 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_512 (MXC_V_TMR_CN_PRES_DIV_BY_512 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_512 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_1024 ((uint32_t)0xAUL) /**< CN_PRES_DIV_BY_1024 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_1024 (MXC_V_TMR_CN_PRES_DIV_BY_1024 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_1024 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_2048 ((uint32_t)0xBUL) /**< CN_PRES_DIV_BY_2048 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_2048 (MXC_V_TMR_CN_PRES_DIV_BY_2048 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_2048 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_4096 ((uint32_t)0xCUL) /**< CN_PRES_DIV_BY_4096 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_4096 (MXC_V_TMR_CN_PRES_DIV_BY_4096 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_4096 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_8192 ((uint32_t)0xDUL) /**< CN_PRES_DIV_BY_8192 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_8192 (MXC_V_TMR_CN_PRES_DIV_BY_8192 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_8192 Setting */
|
||||
#define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */
|
||||
#define MXC_F_TMR_CN_PRES ((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_1 ((uint32_t)0x0UL) /**< CN_PRES_DIV_BY_1 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_1 (MXC_V_TMR_CN_PRES_DIV_BY_1 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_1 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_2 ((uint32_t)0x1UL) /**< CN_PRES_DIV_BY_2 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_2 (MXC_V_TMR_CN_PRES_DIV_BY_2 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_2 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_4 ((uint32_t)0x2UL) /**< CN_PRES_DIV_BY_4 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_4 (MXC_V_TMR_CN_PRES_DIV_BY_4 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_4 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_8 ((uint32_t)0x3UL) /**< CN_PRES_DIV_BY_8 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_8 (MXC_V_TMR_CN_PRES_DIV_BY_8 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_8 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_16 ((uint32_t)0x4UL) /**< CN_PRES_DIV_BY_16 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_16 (MXC_V_TMR_CN_PRES_DIV_BY_16 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_16 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_32 ((uint32_t)0x5UL) /**< CN_PRES_DIV_BY_32 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_32 (MXC_V_TMR_CN_PRES_DIV_BY_32 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_32 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_64 ((uint32_t)0x6UL) /**< CN_PRES_DIV_BY_64 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_64 (MXC_V_TMR_CN_PRES_DIV_BY_64 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_64 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_128 ((uint32_t)0x7UL) /**< CN_PRES_DIV_BY_128 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_128 (MXC_V_TMR_CN_PRES_DIV_BY_128 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_128 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_256 ((uint32_t)0x0UL) /**< CN_PRES_DIV_BY_256 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_256 (MXC_V_TMR_CN_PRES_DIV_BY_256 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_256 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_512 ((uint32_t)0x1UL) /**< CN_PRES_DIV_BY_512 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_512 (MXC_V_TMR_CN_PRES_DIV_BY_512 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_512 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_1024 ((uint32_t)0x2UL) /**< CN_PRES_DIV_BY_1024 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_1024 (MXC_V_TMR_CN_PRES_DIV_BY_1024 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_1024 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_2048 ((uint32_t)0x3UL) /**< CN_PRES_DIV_BY_2048 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_2048 (MXC_V_TMR_CN_PRES_DIV_BY_2048 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_2048 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_4096 ((uint32_t)0x4UL) /**< CN_PRES_DIV_BY_4096 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_4096 (MXC_V_TMR_CN_PRES_DIV_BY_4096 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_4096 Setting */
|
||||
#define MXC_V_TMR_CN_PRES_DIV_BY_8192 ((uint32_t)0x5UL) /**< CN_PRES_DIV_BY_8192 Value */
|
||||
#define MXC_S_TMR_CN_PRES_DIV_BY_8192 (MXC_V_TMR_CN_PRES_DIV_BY_8192 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_8192 Setting */
|
||||
|
||||
#define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */
|
||||
#define MXC_F_TMR_CN_TPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */
|
||||
#define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */
|
||||
#define MXC_F_TMR_CN_TPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */
|
||||
|
||||
#define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */
|
||||
#define MXC_F_TMR_CN_TEN ((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */
|
||||
#define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */
|
||||
#define MXC_F_TMR_CN_TEN ((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */
|
||||
|
||||
#define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */
|
||||
#define MXC_F_TMR_CN_PRES3 ((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */
|
||||
#define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */
|
||||
#define MXC_F_TMR_CN_PRES3 ((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */
|
||||
|
||||
#define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */
|
||||
#define MXC_F_TMR_CN_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask */
|
||||
#define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */
|
||||
#define MXC_F_TMR_CN_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask */
|
||||
|
||||
#define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */
|
||||
#define MXC_F_TMR_CN_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask */
|
||||
#define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */
|
||||
#define MXC_F_TMR_CN_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask */
|
||||
|
||||
#define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */
|
||||
#define MXC_F_TMR_CN_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask */
|
||||
#define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */
|
||||
#define MXC_F_TMR_CN_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask */
|
||||
|
||||
#define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */
|
||||
#define MXC_F_TMR_CN_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask */
|
||||
#define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */
|
||||
#define MXC_F_TMR_CN_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask */
|
||||
|
||||
/**@} end of group TMR_CN_Register */
|
||||
|
||||
|
|
@ -236,4 +234,4 @@ typedef struct {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TMR_REGS_H_ */
|
||||
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_TMR_REGS_H_
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
/**
|
||||
* @file uart_regs.h
|
||||
* @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
|
||||
* @note This file is @generated.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +35,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _UART_REGS_H_
|
||||
#define _UART_REGS_H_
|
||||
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_UART_REGS_H_
|
||||
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_UART_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -46,11 +46,11 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__ICCARM__)
|
||||
#pragma system_include
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__CC_ARM)
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
|
@ -67,7 +67,9 @@ extern "C" {
|
|||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
|
||||
#ifndef __R
|
||||
#define __R volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
|
@ -76,7 +78,7 @@ extern "C" {
|
|||
* @ingroup uart
|
||||
* @defgroup uart_registers UART_Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
|
||||
* @details UART
|
||||
* @details UART
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
@ -100,19 +102,19 @@ typedef struct {
|
|||
/**
|
||||
* @ingroup uart_registers
|
||||
* @defgroup UART_Register_Offsets Register Offsets
|
||||
* @brief UART Peripheral Register Offsets from the UART Base Peripheral Address.
|
||||
* @brief UART Peripheral Register Offsets from the UART Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_UART_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_UART_CTRL1 ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_UART_STAT ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_UART_INT_EN ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt> 0x000C</tt> */
|
||||
#define MXC_R_UART_INT_FL ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> 0x0010</tt> */
|
||||
#define MXC_R_UART_BAUD0 ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> 0x0014</tt> */
|
||||
#define MXC_R_UART_BAUD1 ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt> 0x0018</tt> */
|
||||
#define MXC_R_UART_FIFO ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt> 0x001C</tt> */
|
||||
#define MXC_R_UART_DMA ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> 0x0020</tt> */
|
||||
#define MXC_R_UART_TXFIFO ((uint32_t)0x00000024UL) /**< Offset from UART Base Address: <tt> 0x0024</tt> */
|
||||
#define MXC_R_UART_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_UART_CTRL1 ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_UART_STAT ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_UART_INT_EN ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt> 0x000C</tt> */
|
||||
#define MXC_R_UART_INT_FL ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> 0x0010</tt> */
|
||||
#define MXC_R_UART_BAUD0 ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> 0x0014</tt> */
|
||||
#define MXC_R_UART_BAUD1 ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt> 0x0018</tt> */
|
||||
#define MXC_R_UART_FIFO ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt> 0x001C</tt> */
|
||||
#define MXC_R_UART_DMA ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> 0x0020</tt> */
|
||||
#define MXC_R_UART_TXFIFO ((uint32_t)0x00000024UL) /**< Offset from UART Base Address: <tt> 0x0024</tt> */
|
||||
/**@} end of group uart_registers */
|
||||
|
||||
/**
|
||||
|
|
@ -121,66 +123,66 @@ typedef struct {
|
|||
* @brief Control Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_UART_CTRL0_ENABLE_POS 0 /**< CTRL0_ENABLE Position */
|
||||
#define MXC_F_UART_CTRL0_ENABLE ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_ENABLE_POS)) /**< CTRL0_ENABLE Mask */
|
||||
#define MXC_F_UART_CTRL0_ENABLE_POS 0 /**< CTRL0_ENABLE Position */
|
||||
#define MXC_F_UART_CTRL0_ENABLE ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_ENABLE_POS)) /**< CTRL0_ENABLE Mask */
|
||||
|
||||
#define MXC_F_UART_CTRL0_PARITY_EN_POS 1 /**< CTRL0_PARITY_EN Position */
|
||||
#define MXC_F_UART_CTRL0_PARITY_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_PARITY_EN_POS)) /**< CTRL0_PARITY_EN Mask */
|
||||
#define MXC_F_UART_CTRL0_PARITY_EN_POS 1 /**< CTRL0_PARITY_EN Position */
|
||||
#define MXC_F_UART_CTRL0_PARITY_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_PARITY_EN_POS)) /**< CTRL0_PARITY_EN Mask */
|
||||
|
||||
#define MXC_F_UART_CTRL0_PARITY_MODE_POS 2 /**< CTRL0_PARITY_MODE Position */
|
||||
#define MXC_F_UART_CTRL0_PARITY_MODE ((uint32_t)(0x3UL << MXC_F_UART_CTRL0_PARITY_MODE_POS)) /**< CTRL0_PARITY_MODE Mask */
|
||||
#define MXC_V_UART_CTRL0_PARITY_MODE_EVEN ((uint32_t)0x0UL) /**< CTRL0_PARITY_MODE_EVEN Value */
|
||||
#define MXC_S_UART_CTRL0_PARITY_MODE_EVEN (MXC_V_UART_CTRL0_PARITY_MODE_EVEN << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_EVEN Setting */
|
||||
#define MXC_V_UART_CTRL0_PARITY_MODE_ODD ((uint32_t)0x1UL) /**< CTRL0_PARITY_MODE_ODD Value */
|
||||
#define MXC_S_UART_CTRL0_PARITY_MODE_ODD (MXC_V_UART_CTRL0_PARITY_MODE_ODD << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_ODD Setting */
|
||||
#define MXC_V_UART_CTRL0_PARITY_MODE_MARK ((uint32_t)0x2UL) /**< CTRL0_PARITY_MODE_MARK Value */
|
||||
#define MXC_S_UART_CTRL0_PARITY_MODE_MARK (MXC_V_UART_CTRL0_PARITY_MODE_MARK << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_MARK Setting */
|
||||
#define MXC_V_UART_CTRL0_PARITY_MODE_SPACE ((uint32_t)0x3UL) /**< CTRL0_PARITY_MODE_SPACE Value */
|
||||
#define MXC_S_UART_CTRL0_PARITY_MODE_SPACE (MXC_V_UART_CTRL0_PARITY_MODE_SPACE << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_SPACE Setting */
|
||||
#define MXC_F_UART_CTRL0_PARITY_MODE_POS 2 /**< CTRL0_PARITY_MODE Position */
|
||||
#define MXC_F_UART_CTRL0_PARITY_MODE ((uint32_t)(0x3UL << MXC_F_UART_CTRL0_PARITY_MODE_POS)) /**< CTRL0_PARITY_MODE Mask */
|
||||
#define MXC_V_UART_CTRL0_PARITY_MODE_EVEN ((uint32_t)0x0UL) /**< CTRL0_PARITY_MODE_EVEN Value */
|
||||
#define MXC_S_UART_CTRL0_PARITY_MODE_EVEN (MXC_V_UART_CTRL0_PARITY_MODE_EVEN << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_EVEN Setting */
|
||||
#define MXC_V_UART_CTRL0_PARITY_MODE_ODD ((uint32_t)0x1UL) /**< CTRL0_PARITY_MODE_ODD Value */
|
||||
#define MXC_S_UART_CTRL0_PARITY_MODE_ODD (MXC_V_UART_CTRL0_PARITY_MODE_ODD << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_ODD Setting */
|
||||
#define MXC_V_UART_CTRL0_PARITY_MODE_MARK ((uint32_t)0x2UL) /**< CTRL0_PARITY_MODE_MARK Value */
|
||||
#define MXC_S_UART_CTRL0_PARITY_MODE_MARK (MXC_V_UART_CTRL0_PARITY_MODE_MARK << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_MARK Setting */
|
||||
#define MXC_V_UART_CTRL0_PARITY_MODE_SPACE ((uint32_t)0x3UL) /**< CTRL0_PARITY_MODE_SPACE Value */
|
||||
#define MXC_S_UART_CTRL0_PARITY_MODE_SPACE (MXC_V_UART_CTRL0_PARITY_MODE_SPACE << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_SPACE Setting */
|
||||
|
||||
#define MXC_F_UART_CTRL0_PARITY_LVL_POS 4 /**< CTRL0_PARITY_LVL Position */
|
||||
#define MXC_F_UART_CTRL0_PARITY_LVL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_PARITY_LVL_POS)) /**< CTRL0_PARITY_LVL Mask */
|
||||
#define MXC_F_UART_CTRL0_PARITY_LVL_POS 4 /**< CTRL0_PARITY_LVL Position */
|
||||
#define MXC_F_UART_CTRL0_PARITY_LVL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_PARITY_LVL_POS)) /**< CTRL0_PARITY_LVL Mask */
|
||||
|
||||
#define MXC_F_UART_CTRL0_TXFLUSH_POS 5 /**< CTRL0_TXFLUSH Position */
|
||||
#define MXC_F_UART_CTRL0_TXFLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_TXFLUSH_POS)) /**< CTRL0_TXFLUSH Mask */
|
||||
#define MXC_F_UART_CTRL0_TXFLUSH_POS 5 /**< CTRL0_TXFLUSH Position */
|
||||
#define MXC_F_UART_CTRL0_TXFLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_TXFLUSH_POS)) /**< CTRL0_TXFLUSH Mask */
|
||||
|
||||
#define MXC_F_UART_CTRL0_RXFLUSH_POS 6 /**< CTRL0_RXFLUSH Position */
|
||||
#define MXC_F_UART_CTRL0_RXFLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_RXFLUSH_POS)) /**< CTRL0_RXFLUSH Mask */
|
||||
#define MXC_F_UART_CTRL0_RXFLUSH_POS 6 /**< CTRL0_RXFLUSH Position */
|
||||
#define MXC_F_UART_CTRL0_RXFLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_RXFLUSH_POS)) /**< CTRL0_RXFLUSH Mask */
|
||||
|
||||
#define MXC_F_UART_CTRL0_BITACC_POS 7 /**< CTRL0_BITACC Position */
|
||||
#define MXC_F_UART_CTRL0_BITACC ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_BITACC_POS)) /**< CTRL0_BITACC Mask */
|
||||
#define MXC_F_UART_CTRL0_BITACC_POS 7 /**< CTRL0_BITACC Position */
|
||||
#define MXC_F_UART_CTRL0_BITACC ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_BITACC_POS)) /**< CTRL0_BITACC Mask */
|
||||
|
||||
#define MXC_F_UART_CTRL0_SIZE_POS 8 /**< CTRL0_SIZE Position */
|
||||
#define MXC_F_UART_CTRL0_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL0_SIZE_POS)) /**< CTRL0_SIZE Mask */
|
||||
#define MXC_V_UART_CTRL0_SIZE_5 ((uint32_t)0x0UL) /**< CTRL0_SIZE_5 Value */
|
||||
#define MXC_S_UART_CTRL0_SIZE_5 (MXC_V_UART_CTRL0_SIZE_5 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_5 Setting */
|
||||
#define MXC_V_UART_CTRL0_SIZE_6 ((uint32_t)0x1UL) /**< CTRL0_SIZE_6 Value */
|
||||
#define MXC_S_UART_CTRL0_SIZE_6 (MXC_V_UART_CTRL0_SIZE_6 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_6 Setting */
|
||||
#define MXC_V_UART_CTRL0_SIZE_7 ((uint32_t)0x2UL) /**< CTRL0_SIZE_7 Value */
|
||||
#define MXC_S_UART_CTRL0_SIZE_7 (MXC_V_UART_CTRL0_SIZE_7 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_7 Setting */
|
||||
#define MXC_V_UART_CTRL0_SIZE_8 ((uint32_t)0x3UL) /**< CTRL0_SIZE_8 Value */
|
||||
#define MXC_S_UART_CTRL0_SIZE_8 (MXC_V_UART_CTRL0_SIZE_8 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_8 Setting */
|
||||
#define MXC_F_UART_CTRL0_SIZE_POS 8 /**< CTRL0_SIZE Position */
|
||||
#define MXC_F_UART_CTRL0_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL0_SIZE_POS)) /**< CTRL0_SIZE Mask */
|
||||
#define MXC_V_UART_CTRL0_SIZE_5 ((uint32_t)0x0UL) /**< CTRL0_SIZE_5 Value */
|
||||
#define MXC_S_UART_CTRL0_SIZE_5 (MXC_V_UART_CTRL0_SIZE_5 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_5 Setting */
|
||||
#define MXC_V_UART_CTRL0_SIZE_6 ((uint32_t)0x1UL) /**< CTRL0_SIZE_6 Value */
|
||||
#define MXC_S_UART_CTRL0_SIZE_6 (MXC_V_UART_CTRL0_SIZE_6 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_6 Setting */
|
||||
#define MXC_V_UART_CTRL0_SIZE_7 ((uint32_t)0x2UL) /**< CTRL0_SIZE_7 Value */
|
||||
#define MXC_S_UART_CTRL0_SIZE_7 (MXC_V_UART_CTRL0_SIZE_7 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_7 Setting */
|
||||
#define MXC_V_UART_CTRL0_SIZE_8 ((uint32_t)0x3UL) /**< CTRL0_SIZE_8 Value */
|
||||
#define MXC_S_UART_CTRL0_SIZE_8 (MXC_V_UART_CTRL0_SIZE_8 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_8 Setting */
|
||||
|
||||
#define MXC_F_UART_CTRL0_STOP_POS 10 /**< CTRL0_STOP Position */
|
||||
#define MXC_F_UART_CTRL0_STOP ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_STOP_POS)) /**< CTRL0_STOP Mask */
|
||||
#define MXC_F_UART_CTRL0_STOP_POS 10 /**< CTRL0_STOP Position */
|
||||
#define MXC_F_UART_CTRL0_STOP ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_STOP_POS)) /**< CTRL0_STOP Mask */
|
||||
|
||||
#define MXC_F_UART_CTRL0_FLOW_POS 11 /**< CTRL0_FLOW Position */
|
||||
#define MXC_F_UART_CTRL0_FLOW ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_FLOW_POS)) /**< CTRL0_FLOW Mask */
|
||||
#define MXC_F_UART_CTRL0_FLOW_POS 11 /**< CTRL0_FLOW Position */
|
||||
#define MXC_F_UART_CTRL0_FLOW ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_FLOW_POS)) /**< CTRL0_FLOW Mask */
|
||||
|
||||
#define MXC_F_UART_CTRL0_FLOWPOL_POS 12 /**< CTRL0_FLOWPOL Position */
|
||||
#define MXC_F_UART_CTRL0_FLOWPOL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_FLOWPOL_POS)) /**< CTRL0_FLOWPOL Mask */
|
||||
#define MXC_F_UART_CTRL0_FLOWPOL_POS 12 /**< CTRL0_FLOWPOL Position */
|
||||
#define MXC_F_UART_CTRL0_FLOWPOL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_FLOWPOL_POS)) /**< CTRL0_FLOWPOL Mask */
|
||||
|
||||
#define MXC_F_UART_CTRL0_NULLMOD_POS 13 /**< CTRL0_NULLMOD Position */
|
||||
#define MXC_F_UART_CTRL0_NULLMOD ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_NULLMOD_POS)) /**< CTRL0_NULLMOD Mask */
|
||||
#define MXC_F_UART_CTRL0_NULLMOD_POS 13 /**< CTRL0_NULLMOD Position */
|
||||
#define MXC_F_UART_CTRL0_NULLMOD ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_NULLMOD_POS)) /**< CTRL0_NULLMOD Mask */
|
||||
|
||||
#define MXC_F_UART_CTRL0_BREAK_POS 14 /**< CTRL0_BREAK Position */
|
||||
#define MXC_F_UART_CTRL0_BREAK ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_BREAK_POS)) /**< CTRL0_BREAK Mask */
|
||||
#define MXC_F_UART_CTRL0_BREAK_POS 14 /**< CTRL0_BREAK Position */
|
||||
#define MXC_F_UART_CTRL0_BREAK ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_BREAK_POS)) /**< CTRL0_BREAK Mask */
|
||||
|
||||
#define MXC_F_UART_CTRL0_CLK_SEL_POS 15 /**< CTRL0_CLK_SEL Position */
|
||||
#define MXC_F_UART_CTRL0_CLK_SEL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_CLK_SEL_POS)) /**< CTRL0_CLK_SEL Mask */
|
||||
#define MXC_F_UART_CTRL0_CLK_SEL_POS 15 /**< CTRL0_CLK_SEL Position */
|
||||
#define MXC_F_UART_CTRL0_CLK_SEL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_CLK_SEL_POS)) /**< CTRL0_CLK_SEL Mask */
|
||||
|
||||
#define MXC_F_UART_CTRL0_TO_CNT_POS 16 /**< CTRL0_TO_CNT Position */
|
||||
#define MXC_F_UART_CTRL0_TO_CNT ((uint32_t)(0xFFUL << MXC_F_UART_CTRL0_TO_CNT_POS)) /**< CTRL0_TO_CNT Mask */
|
||||
#define MXC_F_UART_CTRL0_TO_CNT_POS 16 /**< CTRL0_TO_CNT Position */
|
||||
#define MXC_F_UART_CTRL0_TO_CNT ((uint32_t)(0xFFUL << MXC_F_UART_CTRL0_TO_CNT_POS)) /**< CTRL0_TO_CNT Mask */
|
||||
|
||||
/**@} end of group UART_CTRL0_Register */
|
||||
|
||||
|
|
@ -190,14 +192,14 @@ typedef struct {
|
|||
* @brief Threshold Control register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_UART_CTRL1_RX_FIFO_LVL_POS 0 /**< CTRL1_RX_FIFO_LVL Position */
|
||||
#define MXC_F_UART_CTRL1_RX_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_RX_FIFO_LVL_POS)) /**< CTRL1_RX_FIFO_LVL Mask */
|
||||
#define MXC_F_UART_CTRL1_RX_FIFO_LVL_POS 0 /**< CTRL1_RX_FIFO_LVL Position */
|
||||
#define MXC_F_UART_CTRL1_RX_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_RX_FIFO_LVL_POS)) /**< CTRL1_RX_FIFO_LVL Mask */
|
||||
|
||||
#define MXC_F_UART_CTRL1_TX_FIFO_LVL_POS 8 /**< CTRL1_TX_FIFO_LVL Position */
|
||||
#define MXC_F_UART_CTRL1_TX_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_TX_FIFO_LVL_POS)) /**< CTRL1_TX_FIFO_LVL Mask */
|
||||
#define MXC_F_UART_CTRL1_TX_FIFO_LVL_POS 8 /**< CTRL1_TX_FIFO_LVL Position */
|
||||
#define MXC_F_UART_CTRL1_TX_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_TX_FIFO_LVL_POS)) /**< CTRL1_TX_FIFO_LVL Mask */
|
||||
|
||||
#define MXC_F_UART_CTRL1_RTS_FIFO_LVL_POS 16 /**< CTRL1_RTS_FIFO_LVL Position */
|
||||
#define MXC_F_UART_CTRL1_RTS_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_RTS_FIFO_LVL_POS)) /**< CTRL1_RTS_FIFO_LVL Mask */
|
||||
#define MXC_F_UART_CTRL1_RTS_FIFO_LVL_POS 16 /**< CTRL1_RTS_FIFO_LVL Position */
|
||||
#define MXC_F_UART_CTRL1_RTS_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_RTS_FIFO_LVL_POS)) /**< CTRL1_RTS_FIFO_LVL Mask */
|
||||
|
||||
/**@} end of group UART_CTRL1_Register */
|
||||
|
||||
|
|
@ -207,38 +209,38 @@ typedef struct {
|
|||
* @brief Status Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_UART_STAT_TX_BUSY_POS 0 /**< STAT_TX_BUSY Position */
|
||||
#define MXC_F_UART_STAT_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_BUSY_POS)) /**< STAT_TX_BUSY Mask */
|
||||
#define MXC_F_UART_STAT_TX_BUSY_POS 0 /**< STAT_TX_BUSY Position */
|
||||
#define MXC_F_UART_STAT_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_BUSY_POS)) /**< STAT_TX_BUSY Mask */
|
||||
|
||||
#define MXC_F_UART_STAT_RX_BUSY_POS 1 /**< STAT_RX_BUSY Position */
|
||||
#define MXC_F_UART_STAT_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_BUSY_POS)) /**< STAT_RX_BUSY Mask */
|
||||
#define MXC_F_UART_STAT_RX_BUSY_POS 1 /**< STAT_RX_BUSY Position */
|
||||
#define MXC_F_UART_STAT_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_BUSY_POS)) /**< STAT_RX_BUSY Mask */
|
||||
|
||||
#define MXC_F_UART_STAT_PARITY_POS 2 /**< STAT_PARITY Position */
|
||||
#define MXC_F_UART_STAT_PARITY ((uint32_t)(0x1UL << MXC_F_UART_STAT_PARITY_POS)) /**< STAT_PARITY Mask */
|
||||
#define MXC_F_UART_STAT_PARITY_POS 2 /**< STAT_PARITY Position */
|
||||
#define MXC_F_UART_STAT_PARITY ((uint32_t)(0x1UL << MXC_F_UART_STAT_PARITY_POS)) /**< STAT_PARITY Mask */
|
||||
|
||||
#define MXC_F_UART_STAT_BREAK_POS 3 /**< STAT_BREAK Position */
|
||||
#define MXC_F_UART_STAT_BREAK ((uint32_t)(0x1UL << MXC_F_UART_STAT_BREAK_POS)) /**< STAT_BREAK Mask */
|
||||
#define MXC_F_UART_STAT_BREAK_POS 3 /**< STAT_BREAK Position */
|
||||
#define MXC_F_UART_STAT_BREAK ((uint32_t)(0x1UL << MXC_F_UART_STAT_BREAK_POS)) /**< STAT_BREAK Mask */
|
||||
|
||||
#define MXC_F_UART_STAT_RX_EMPTY_POS 4 /**< STAT_RX_EMPTY Position */
|
||||
#define MXC_F_UART_STAT_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_EMPTY_POS)) /**< STAT_RX_EMPTY Mask */
|
||||
#define MXC_F_UART_STAT_RX_EMPTY_POS 4 /**< STAT_RX_EMPTY Position */
|
||||
#define MXC_F_UART_STAT_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_EMPTY_POS)) /**< STAT_RX_EMPTY Mask */
|
||||
|
||||
#define MXC_F_UART_STAT_RX_FULL_POS 5 /**< STAT_RX_FULL Position */
|
||||
#define MXC_F_UART_STAT_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_FULL_POS)) /**< STAT_RX_FULL Mask */
|
||||
#define MXC_F_UART_STAT_RX_FULL_POS 5 /**< STAT_RX_FULL Position */
|
||||
#define MXC_F_UART_STAT_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_FULL_POS)) /**< STAT_RX_FULL Mask */
|
||||
|
||||
#define MXC_F_UART_STAT_TX_EMPTY_POS 6 /**< STAT_TX_EMPTY Position */
|
||||
#define MXC_F_UART_STAT_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_EMPTY_POS)) /**< STAT_TX_EMPTY Mask */
|
||||
#define MXC_F_UART_STAT_TX_EMPTY_POS 6 /**< STAT_TX_EMPTY Position */
|
||||
#define MXC_F_UART_STAT_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_EMPTY_POS)) /**< STAT_TX_EMPTY Mask */
|
||||
|
||||
#define MXC_F_UART_STAT_TX_FULL_POS 7 /**< STAT_TX_FULL Position */
|
||||
#define MXC_F_UART_STAT_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_FULL_POS)) /**< STAT_TX_FULL Mask */
|
||||
#define MXC_F_UART_STAT_TX_FULL_POS 7 /**< STAT_TX_FULL Position */
|
||||
#define MXC_F_UART_STAT_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_FULL_POS)) /**< STAT_TX_FULL Mask */
|
||||
|
||||
#define MXC_F_UART_STAT_RX_NUM_POS 8 /**< STAT_RX_NUM Position */
|
||||
#define MXC_F_UART_STAT_RX_NUM ((uint32_t)(0x3FUL << MXC_F_UART_STAT_RX_NUM_POS)) /**< STAT_RX_NUM Mask */
|
||||
#define MXC_F_UART_STAT_RX_NUM_POS 8 /**< STAT_RX_NUM Position */
|
||||
#define MXC_F_UART_STAT_RX_NUM ((uint32_t)(0x3FUL << MXC_F_UART_STAT_RX_NUM_POS)) /**< STAT_RX_NUM Mask */
|
||||
|
||||
#define MXC_F_UART_STAT_TX_NUM_POS 16 /**< STAT_TX_NUM Position */
|
||||
#define MXC_F_UART_STAT_TX_NUM ((uint32_t)(0x3FUL << MXC_F_UART_STAT_TX_NUM_POS)) /**< STAT_TX_NUM Mask */
|
||||
#define MXC_F_UART_STAT_TX_NUM_POS 16 /**< STAT_TX_NUM Position */
|
||||
#define MXC_F_UART_STAT_TX_NUM ((uint32_t)(0x3FUL << MXC_F_UART_STAT_TX_NUM_POS)) /**< STAT_TX_NUM Mask */
|
||||
|
||||
#define MXC_F_UART_STAT_RX_TO_POS 24 /**< STAT_RX_TO Position */
|
||||
#define MXC_F_UART_STAT_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_TO_POS)) /**< STAT_RX_TO Mask */
|
||||
#define MXC_F_UART_STAT_RX_TO_POS 24 /**< STAT_RX_TO Position */
|
||||
#define MXC_F_UART_STAT_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_TO_POS)) /**< STAT_RX_TO Mask */
|
||||
|
||||
/**@} end of group UART_STAT_Register */
|
||||
|
||||
|
|
@ -248,35 +250,35 @@ typedef struct {
|
|||
* @brief Interrupt Enable Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS 0 /**< INT_EN_RX_FRAME_ERROR Position */
|
||||
#define MXC_F_UART_INT_EN_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**< INT_EN_RX_FRAME_ERROR Mask */
|
||||
#define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS 0 /**< INT_EN_RX_FRAME_ERROR Position */
|
||||
#define MXC_F_UART_INT_EN_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**< INT_EN_RX_FRAME_ERROR Mask */
|
||||
|
||||
#define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS 1 /**< INT_EN_RX_PARITY_ERROR Position */
|
||||
#define MXC_F_UART_INT_EN_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**< INT_EN_RX_PARITY_ERROR Mask */
|
||||
#define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS 1 /**< INT_EN_RX_PARITY_ERROR Position */
|
||||
#define MXC_F_UART_INT_EN_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**< INT_EN_RX_PARITY_ERROR Mask */
|
||||
|
||||
#define MXC_F_UART_INT_EN_CTS_POS 2 /**< INT_EN_CTS Position */
|
||||
#define MXC_F_UART_INT_EN_CTS ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_POS)) /**< INT_EN_CTS Mask */
|
||||
#define MXC_F_UART_INT_EN_CTS_POS 2 /**< INT_EN_CTS Position */
|
||||
#define MXC_F_UART_INT_EN_CTS ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_POS)) /**< INT_EN_CTS Mask */
|
||||
|
||||
#define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */
|
||||
#define MXC_F_UART_INT_EN_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN Mask */
|
||||
#define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */
|
||||
#define MXC_F_UART_INT_EN_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN Mask */
|
||||
|
||||
#define MXC_F_UART_INT_EN_RX_FIFO_LVL_POS 4 /**< INT_EN_RX_FIFO_LVL Position */
|
||||
#define MXC_F_UART_INT_EN_RX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FIFO_LVL_POS)) /**< INT_EN_RX_FIFO_LVL Mask */
|
||||
#define MXC_F_UART_INT_EN_RX_FIFO_LVL_POS 4 /**< INT_EN_RX_FIFO_LVL Position */
|
||||
#define MXC_F_UART_INT_EN_RX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FIFO_LVL_POS)) /**< INT_EN_RX_FIFO_LVL Mask */
|
||||
|
||||
#define MXC_F_UART_INT_EN_TX_FIFO_AE_POS 5 /**< INT_EN_TX_FIFO_AE Position */
|
||||
#define MXC_F_UART_INT_EN_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_AE_POS)) /**< INT_EN_TX_FIFO_AE Mask */
|
||||
#define MXC_F_UART_INT_EN_TX_FIFO_AE_POS 5 /**< INT_EN_TX_FIFO_AE Position */
|
||||
#define MXC_F_UART_INT_EN_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_AE_POS)) /**< INT_EN_TX_FIFO_AE Mask */
|
||||
|
||||
#define MXC_F_UART_INT_EN_TX_FIFO_LVL_POS 6 /**< INT_EN_TX_FIFO_LVL Position */
|
||||
#define MXC_F_UART_INT_EN_TX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_LVL_POS)) /**< INT_EN_TX_FIFO_LVL Mask */
|
||||
#define MXC_F_UART_INT_EN_TX_FIFO_LVL_POS 6 /**< INT_EN_TX_FIFO_LVL Position */
|
||||
#define MXC_F_UART_INT_EN_TX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_LVL_POS)) /**< INT_EN_TX_FIFO_LVL Mask */
|
||||
|
||||
#define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */
|
||||
#define MXC_F_UART_INT_EN_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */
|
||||
#define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */
|
||||
#define MXC_F_UART_INT_EN_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */
|
||||
|
||||
#define MXC_F_UART_INT_EN_RX_TO_POS 8 /**< INT_EN_RX_TO Position */
|
||||
#define MXC_F_UART_INT_EN_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_TO_POS)) /**< INT_EN_RX_TO Mask */
|
||||
#define MXC_F_UART_INT_EN_RX_TO_POS 8 /**< INT_EN_RX_TO Position */
|
||||
#define MXC_F_UART_INT_EN_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_TO_POS)) /**< INT_EN_RX_TO Mask */
|
||||
|
||||
#define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */
|
||||
#define MXC_F_UART_INT_EN_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK Mask */
|
||||
#define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */
|
||||
#define MXC_F_UART_INT_EN_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK Mask */
|
||||
|
||||
/**@} end of group UART_INT_EN_Register */
|
||||
|
||||
|
|
@ -286,35 +288,35 @@ typedef struct {
|
|||
* @brief Interrupt Status Flags.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_UART_INT_FL_FRAME_POS 0 /**< INT_FL_FRAME Position */
|
||||
#define MXC_F_UART_INT_FL_FRAME ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_FRAME_POS)) /**< INT_FL_FRAME Mask */
|
||||
#define MXC_F_UART_INT_FL_FRAME_POS 0 /**< INT_FL_FRAME Position */
|
||||
#define MXC_F_UART_INT_FL_FRAME ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_FRAME_POS)) /**< INT_FL_FRAME Mask */
|
||||
|
||||
#define MXC_F_UART_INT_FL_PARITY_POS 1 /**< INT_FL_PARITY Position */
|
||||
#define MXC_F_UART_INT_FL_PARITY ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_PARITY_POS)) /**< INT_FL_PARITY Mask */
|
||||
#define MXC_F_UART_INT_FL_PARITY_POS 1 /**< INT_FL_PARITY Position */
|
||||
#define MXC_F_UART_INT_FL_PARITY ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_PARITY_POS)) /**< INT_FL_PARITY Mask */
|
||||
|
||||
#define MXC_F_UART_INT_FL_CTS_POS 2 /**< INT_FL_CTS Position */
|
||||
#define MXC_F_UART_INT_FL_CTS ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_POS)) /**< INT_FL_CTS Mask */
|
||||
#define MXC_F_UART_INT_FL_CTS_POS 2 /**< INT_FL_CTS Position */
|
||||
#define MXC_F_UART_INT_FL_CTS ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_POS)) /**< INT_FL_CTS Mask */
|
||||
|
||||
#define MXC_F_UART_INT_FL_RX_OVR_POS 3 /**< INT_FL_RX_OVR Position */
|
||||
#define MXC_F_UART_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */
|
||||
#define MXC_F_UART_INT_FL_RX_OVR_POS 3 /**< INT_FL_RX_OVR Position */
|
||||
#define MXC_F_UART_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */
|
||||
|
||||
#define MXC_F_UART_INT_FL_RX_FIFO_LVL_POS 4 /**< INT_FL_RX_FIFO_LVL Position */
|
||||
#define MXC_F_UART_INT_FL_RX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FIFO_LVL_POS)) /**< INT_FL_RX_FIFO_LVL Mask */
|
||||
#define MXC_F_UART_INT_FL_RX_FIFO_LVL_POS 4 /**< INT_FL_RX_FIFO_LVL Position */
|
||||
#define MXC_F_UART_INT_FL_RX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FIFO_LVL_POS)) /**< INT_FL_RX_FIFO_LVL Mask */
|
||||
|
||||
#define MXC_F_UART_INT_FL_TX_FIFO_AE_POS 5 /**< INT_FL_TX_FIFO_AE Position */
|
||||
#define MXC_F_UART_INT_FL_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_AE_POS)) /**< INT_FL_TX_FIFO_AE Mask */
|
||||
#define MXC_F_UART_INT_FL_TX_FIFO_AE_POS 5 /**< INT_FL_TX_FIFO_AE Position */
|
||||
#define MXC_F_UART_INT_FL_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_AE_POS)) /**< INT_FL_TX_FIFO_AE Mask */
|
||||
|
||||
#define MXC_F_UART_INT_FL_TX_FIFO_LVL_POS 6 /**< INT_FL_TX_FIFO_LVL Position */
|
||||
#define MXC_F_UART_INT_FL_TX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_LVL_POS)) /**< INT_FL_TX_FIFO_LVL Mask */
|
||||
#define MXC_F_UART_INT_FL_TX_FIFO_LVL_POS 6 /**< INT_FL_TX_FIFO_LVL Position */
|
||||
#define MXC_F_UART_INT_FL_TX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_LVL_POS)) /**< INT_FL_TX_FIFO_LVL Mask */
|
||||
|
||||
#define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */
|
||||
#define MXC_F_UART_INT_FL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */
|
||||
#define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */
|
||||
#define MXC_F_UART_INT_FL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */
|
||||
|
||||
#define MXC_F_UART_INT_FL_RX_TO_POS 8 /**< INT_FL_RX_TO Position */
|
||||
#define MXC_F_UART_INT_FL_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_TO_POS)) /**< INT_FL_RX_TO Mask */
|
||||
#define MXC_F_UART_INT_FL_RX_TO_POS 8 /**< INT_FL_RX_TO Position */
|
||||
#define MXC_F_UART_INT_FL_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_TO_POS)) /**< INT_FL_RX_TO Mask */
|
||||
|
||||
#define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */
|
||||
#define MXC_F_UART_INT_FL_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK Mask */
|
||||
#define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */
|
||||
#define MXC_F_UART_INT_FL_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK Mask */
|
||||
|
||||
/**@} end of group UART_INT_FL_Register */
|
||||
|
||||
|
|
@ -324,21 +326,21 @@ typedef struct {
|
|||
* @brief Baud rate register. Integer portion.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */
|
||||
#define MXC_F_UART_BAUD0_IBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */
|
||||
#define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */
|
||||
#define MXC_F_UART_BAUD0_IBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */
|
||||
|
||||
#define MXC_F_UART_BAUD0_CLKDIV_POS 16 /**< BAUD0_CLKDIV Position */
|
||||
#define MXC_F_UART_BAUD0_CLKDIV ((uint32_t)(0x7UL << MXC_F_UART_BAUD0_CLKDIV_POS)) /**< BAUD0_CLKDIV Mask */
|
||||
#define MXC_V_UART_BAUD0_CLKDIV_128 ((uint32_t)0x0UL) /**< BAUD0_CLKDIV_128 Value */
|
||||
#define MXC_S_UART_BAUD0_CLKDIV_128 (MXC_V_UART_BAUD0_CLKDIV_128 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_128 Setting */
|
||||
#define MXC_V_UART_BAUD0_CLKDIV_64 ((uint32_t)0x1UL) /**< BAUD0_CLKDIV_64 Value */
|
||||
#define MXC_S_UART_BAUD0_CLKDIV_64 (MXC_V_UART_BAUD0_CLKDIV_64 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_64 Setting */
|
||||
#define MXC_V_UART_BAUD0_CLKDIV_32 ((uint32_t)0x2UL) /**< BAUD0_CLKDIV_32 Value */
|
||||
#define MXC_S_UART_BAUD0_CLKDIV_32 (MXC_V_UART_BAUD0_CLKDIV_32 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_32 Setting */
|
||||
#define MXC_V_UART_BAUD0_CLKDIV_16 ((uint32_t)0x3UL) /**< BAUD0_CLKDIV_16 Value */
|
||||
#define MXC_S_UART_BAUD0_CLKDIV_16 (MXC_V_UART_BAUD0_CLKDIV_16 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_16 Setting */
|
||||
#define MXC_V_UART_BAUD0_CLKDIV_8 ((uint32_t)0x4UL) /**< BAUD0_CLKDIV_8 Value */
|
||||
#define MXC_S_UART_BAUD0_CLKDIV_8 (MXC_V_UART_BAUD0_CLKDIV_8 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_8 Setting */
|
||||
#define MXC_F_UART_BAUD0_CLKDIV_POS 16 /**< BAUD0_CLKDIV Position */
|
||||
#define MXC_F_UART_BAUD0_CLKDIV ((uint32_t)(0x7UL << MXC_F_UART_BAUD0_CLKDIV_POS)) /**< BAUD0_CLKDIV Mask */
|
||||
#define MXC_V_UART_BAUD0_CLKDIV_128 ((uint32_t)0x0UL) /**< BAUD0_CLKDIV_128 Value */
|
||||
#define MXC_S_UART_BAUD0_CLKDIV_128 (MXC_V_UART_BAUD0_CLKDIV_128 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_128 Setting */
|
||||
#define MXC_V_UART_BAUD0_CLKDIV_64 ((uint32_t)0x1UL) /**< BAUD0_CLKDIV_64 Value */
|
||||
#define MXC_S_UART_BAUD0_CLKDIV_64 (MXC_V_UART_BAUD0_CLKDIV_64 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_64 Setting */
|
||||
#define MXC_V_UART_BAUD0_CLKDIV_32 ((uint32_t)0x2UL) /**< BAUD0_CLKDIV_32 Value */
|
||||
#define MXC_S_UART_BAUD0_CLKDIV_32 (MXC_V_UART_BAUD0_CLKDIV_32 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_32 Setting */
|
||||
#define MXC_V_UART_BAUD0_CLKDIV_16 ((uint32_t)0x3UL) /**< BAUD0_CLKDIV_16 Value */
|
||||
#define MXC_S_UART_BAUD0_CLKDIV_16 (MXC_V_UART_BAUD0_CLKDIV_16 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_16 Setting */
|
||||
#define MXC_V_UART_BAUD0_CLKDIV_8 ((uint32_t)0x4UL) /**< BAUD0_CLKDIV_8 Value */
|
||||
#define MXC_S_UART_BAUD0_CLKDIV_8 (MXC_V_UART_BAUD0_CLKDIV_8 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_8 Setting */
|
||||
|
||||
/**@} end of group UART_BAUD0_Register */
|
||||
|
||||
|
|
@ -348,8 +350,8 @@ typedef struct {
|
|||
* @brief Baud rate register. Decimal Setting.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */
|
||||
#define MXC_F_UART_BAUD1_DBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */
|
||||
#define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */
|
||||
#define MXC_F_UART_BAUD1_DBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */
|
||||
|
||||
/**@} end of group UART_BAUD1_Register */
|
||||
|
||||
|
|
@ -359,8 +361,8 @@ typedef struct {
|
|||
* @brief FIFO Data buffer.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */
|
||||
#define MXC_F_UART_FIFO_FIFO ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask */
|
||||
#define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */
|
||||
#define MXC_F_UART_FIFO_FIFO ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask */
|
||||
|
||||
/**@} end of group UART_FIFO_Register */
|
||||
|
||||
|
|
@ -370,17 +372,17 @@ typedef struct {
|
|||
* @brief DMA Configuration.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_UART_DMA_TXDMA_EN_POS 0 /**< DMA_TXDMA_EN Position */
|
||||
#define MXC_F_UART_DMA_TXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TXDMA_EN_POS)) /**< DMA_TXDMA_EN Mask */
|
||||
#define MXC_F_UART_DMA_TXDMA_EN_POS 0 /**< DMA_TXDMA_EN Position */
|
||||
#define MXC_F_UART_DMA_TXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TXDMA_EN_POS)) /**< DMA_TXDMA_EN Mask */
|
||||
|
||||
#define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */
|
||||
#define MXC_F_UART_DMA_RXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */
|
||||
#define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */
|
||||
#define MXC_F_UART_DMA_RXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */
|
||||
|
||||
#define MXC_F_UART_DMA_TXDMA_LVL_POS 8 /**< DMA_TXDMA_LVL Position */
|
||||
#define MXC_F_UART_DMA_TXDMA_LVL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_TXDMA_LVL_POS)) /**< DMA_TXDMA_LVL Mask */
|
||||
#define MXC_F_UART_DMA_TXDMA_LVL_POS 8 /**< DMA_TXDMA_LVL Position */
|
||||
#define MXC_F_UART_DMA_TXDMA_LVL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_TXDMA_LVL_POS)) /**< DMA_TXDMA_LVL Mask */
|
||||
|
||||
#define MXC_F_UART_DMA_RXDMA_LVL_POS 16 /**< DMA_RXDMA_LVL Position */
|
||||
#define MXC_F_UART_DMA_RXDMA_LVL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_RXDMA_LVL_POS)) /**< DMA_RXDMA_LVL Mask */
|
||||
#define MXC_F_UART_DMA_RXDMA_LVL_POS 16 /**< DMA_RXDMA_LVL Position */
|
||||
#define MXC_F_UART_DMA_RXDMA_LVL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_RXDMA_LVL_POS)) /**< DMA_RXDMA_LVL Mask */
|
||||
|
||||
/**@} end of group UART_DMA_Register */
|
||||
|
||||
|
|
@ -390,8 +392,8 @@ typedef struct {
|
|||
* @brief Transmit FIFO Status register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_UART_TXFIFO_DATA_POS 0 /**< TXFIFO_DATA Position */
|
||||
#define MXC_F_UART_TXFIFO_DATA ((uint32_t)(0x7FUL << MXC_F_UART_TXFIFO_DATA_POS)) /**< TXFIFO_DATA Mask */
|
||||
#define MXC_F_UART_TXFIFO_DATA_POS 0 /**< TXFIFO_DATA Position */
|
||||
#define MXC_F_UART_TXFIFO_DATA ((uint32_t)(0x7FUL << MXC_F_UART_TXFIFO_DATA_POS)) /**< TXFIFO_DATA Mask */
|
||||
|
||||
/**@} end of group UART_TXFIFO_Register */
|
||||
|
||||
|
|
@ -399,4 +401,4 @@ typedef struct {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _UART_REGS_H_ */
|
||||
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_UART_REGS_H_
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
/**
|
||||
* @file wdt_regs.h
|
||||
* @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module.
|
||||
* @note This file is @generated.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +35,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _WDT_REGS_H_
|
||||
#define _WDT_REGS_H_
|
||||
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_WDT_REGS_H_
|
||||
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_WDT_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -46,11 +46,11 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__ICCARM__)
|
||||
#pragma system_include
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__CC_ARM)
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
|
@ -67,7 +67,9 @@ extern "C" {
|
|||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
|
||||
#ifndef __R
|
||||
#define __R volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
|
@ -76,7 +78,7 @@ extern "C" {
|
|||
* @ingroup wdt
|
||||
* @defgroup wdt_registers WDT_Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module.
|
||||
* @details Watchdog Timer 0
|
||||
* @details Watchdog Timer 0
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
@ -92,11 +94,11 @@ typedef struct {
|
|||
/**
|
||||
* @ingroup wdt_registers
|
||||
* @defgroup WDT_Register_Offsets Register Offsets
|
||||
* @brief WDT Peripheral Register Offsets from the WDT Base Peripheral Address.
|
||||
* @brief WDT Peripheral Register Offsets from the WDT Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_WDT_CTRL ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_WDT_RST ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_WDT_CTRL ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_WDT_RST ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: <tt> 0x0004</tt> */
|
||||
/**@} end of group wdt_registers */
|
||||
|
||||
/**
|
||||
|
|
@ -105,90 +107,90 @@ typedef struct {
|
|||
* @brief Watchdog Timer Control Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< CTRL_INT_PERIOD Position */
|
||||
#define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD Mask */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16 Setting */
|
||||
#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< CTRL_INT_PERIOD Position */
|
||||
#define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD Mask */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17 Setting */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16 Setting */
|
||||
|
||||
#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< CTRL_RST_PERIOD Position */
|
||||
#define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD Mask */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16 Setting */
|
||||
#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< CTRL_RST_PERIOD Position */
|
||||
#define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD Mask */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17 Setting */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16 Setting */
|
||||
|
||||
#define MXC_F_WDT_CTRL_WDT_EN_POS 8 /**< CTRL_WDT_EN Position */
|
||||
#define MXC_F_WDT_CTRL_WDT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */
|
||||
#define MXC_F_WDT_CTRL_WDT_EN_POS 8 /**< CTRL_WDT_EN Position */
|
||||
#define MXC_F_WDT_CTRL_WDT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */
|
||||
|
||||
#define MXC_F_WDT_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */
|
||||
#define MXC_F_WDT_CTRL_INT_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */
|
||||
#define MXC_F_WDT_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */
|
||||
#define MXC_F_WDT_CTRL_INT_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */
|
||||
|
||||
#define MXC_F_WDT_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */
|
||||
#define MXC_F_WDT_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */
|
||||
#define MXC_F_WDT_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */
|
||||
#define MXC_F_WDT_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */
|
||||
|
||||
#define MXC_F_WDT_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */
|
||||
#define MXC_F_WDT_CTRL_RST_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */
|
||||
#define MXC_F_WDT_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */
|
||||
#define MXC_F_WDT_CTRL_RST_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */
|
||||
|
||||
#define MXC_F_WDT_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */
|
||||
#define MXC_F_WDT_CTRL_RST_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */
|
||||
#define MXC_F_WDT_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */
|
||||
#define MXC_F_WDT_CTRL_RST_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */
|
||||
|
||||
/**@} end of group WDT_CTRL_Register */
|
||||
|
||||
|
|
@ -198,12 +200,12 @@ typedef struct {
|
|||
* @brief Watchdog Timer Reset Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_WDT_RST_WDT_RST_POS 0 /**< RST_WDT_RST Position */
|
||||
#define MXC_F_WDT_RST_WDT_RST ((uint32_t)(0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */
|
||||
#define MXC_V_WDT_RST_WDT_RST_SEQ0 ((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */
|
||||
#define MXC_S_WDT_RST_WDT_RST_SEQ0 (MXC_V_WDT_RST_WDT_RST_SEQ0 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */
|
||||
#define MXC_V_WDT_RST_WDT_RST_SEQ1 ((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */
|
||||
#define MXC_S_WDT_RST_WDT_RST_SEQ1 (MXC_V_WDT_RST_WDT_RST_SEQ1 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */
|
||||
#define MXC_F_WDT_RST_WDT_RST_POS 0 /**< RST_WDT_RST Position */
|
||||
#define MXC_F_WDT_RST_WDT_RST ((uint32_t)(0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */
|
||||
#define MXC_V_WDT_RST_WDT_RST_SEQ0 ((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */
|
||||
#define MXC_S_WDT_RST_WDT_RST_SEQ0 (MXC_V_WDT_RST_WDT_RST_SEQ0 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */
|
||||
#define MXC_V_WDT_RST_WDT_RST_SEQ1 ((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */
|
||||
#define MXC_S_WDT_RST_WDT_RST_SEQ1 (MXC_V_WDT_RST_WDT_RST_SEQ1 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */
|
||||
|
||||
/**@} end of group WDT_RST_Register */
|
||||
|
||||
|
|
@ -211,4 +213,4 @@ typedef struct {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _WDT_REGS_H_ */
|
||||
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_WDT_REGS_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief System-level initialization implementation file
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,9 +34,6 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
|
||||
* $Revision: 40072 $
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <string.h>
|
||||
|
|
@ -48,38 +45,38 @@
|
|||
#include "tmr_regs.h"
|
||||
#include "wdt_regs.h"
|
||||
#include "mxc_sys.h"
|
||||
#include "icc.h"
|
||||
|
||||
extern void (*const __isr_vector[])(void);
|
||||
uint32_t SystemCoreClock = HIRC96_FREQ;
|
||||
|
||||
__weak void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t base_freq, div, clk_src,ovr;
|
||||
uint32_t base_freq, div, clk_src, ovr;
|
||||
|
||||
// Get the clock source and frequency
|
||||
clk_src = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL);
|
||||
|
||||
|
||||
if (clk_src == MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN) {
|
||||
base_freq = HFX_FREQ;
|
||||
} else {
|
||||
if (clk_src == MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING) {
|
||||
base_freq = NANORING_FREQ;
|
||||
} else {
|
||||
ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR);
|
||||
if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) {
|
||||
base_freq = HIRC96_FREQ/4;
|
||||
} else {
|
||||
if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) {
|
||||
base_freq = HIRC96_FREQ/2;
|
||||
} else {
|
||||
base_freq = HIRC96_FREQ;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (clk_src == MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING) {
|
||||
base_freq = NANORING_FREQ;
|
||||
} else {
|
||||
ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR);
|
||||
if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) {
|
||||
base_freq = HIRC96_FREQ / 4;
|
||||
} else {
|
||||
if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) {
|
||||
base_freq = HIRC96_FREQ / 2;
|
||||
} else {
|
||||
base_freq = HIRC96_FREQ;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Get the clock divider
|
||||
div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL) >> MXC_F_GCR_CLK_CTRL_PSC_POS;
|
||||
div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_PSC) >> MXC_F_GCR_CLK_CTRL_PSC_POS;
|
||||
|
||||
SystemCoreClock = base_freq >> div;
|
||||
}
|
||||
|
|
@ -94,20 +91,15 @@ __weak void SystemCoreClockUpdate(void)
|
|||
*/
|
||||
__weak int PreInit(void)
|
||||
{
|
||||
/* Switch system clock to HIRC, 96 MHz*/
|
||||
MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC);
|
||||
|
||||
/* Enable cache here to reduce boot time */
|
||||
MXC_ICC_Enable();
|
||||
|
||||
/* Do nothing */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Override this function for early platform initialization
|
||||
*/
|
||||
__weak void low_level_init(void)
|
||||
/* This function can be implemented by the application to initialize the board */
|
||||
__weak int Board_Init(void)
|
||||
{
|
||||
|
||||
/* Do nothing */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* This function is called just before control is transferred to main().
|
||||
|
|
@ -118,16 +110,23 @@ __weak void low_level_init(void)
|
|||
*/
|
||||
__weak void SystemInit(void)
|
||||
{
|
||||
MXC_WDT0->ctrl &= ~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */
|
||||
/* Configure the interrupt controller to use the application vector table in */
|
||||
/* the application space */
|
||||
/* IAR & Keil must set vector table after all memory initialization. */
|
||||
SCB->VTOR = (uint32_t)__isr_vector;
|
||||
|
||||
MXC_WDT0->ctrl &=
|
||||
~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */
|
||||
|
||||
#if (__FPU_PRESENT == 1)
|
||||
/* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
|
||||
/* Grant full access, per "Table B3-24 CPACR bit assignments". */
|
||||
/* DDI0403D "ARMv7-M Architecture Reference Manual" */
|
||||
SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
/* Switch system clock to HIRC */
|
||||
MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC);
|
||||
|
||||
/* Disable clocks to peripherals by default to reduce power */
|
||||
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_DMA);
|
||||
|
|
@ -140,7 +139,27 @@ __weak void SystemInit(void)
|
|||
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR1);
|
||||
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2);
|
||||
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1);
|
||||
|
||||
/* Early platform initialization */
|
||||
low_level_init();
|
||||
|
||||
Board_Init();
|
||||
}
|
||||
|
||||
#if defined(__CC_ARM)
|
||||
/* Global variable initialization does not occur until post scatterload in Keil tools.*/
|
||||
|
||||
/* External function called after our post scatterload function implementation. */
|
||||
extern void $Super$$__main_after_scatterload(void);
|
||||
|
||||
/**
|
||||
* @brief Initialization function for SystemCoreClock and Board_Init.
|
||||
* @details $Sub$$__main_after_scatterload is called during system startup in the Keil
|
||||
* toolset. Global variable and static variable space must be set up by the compiler
|
||||
* prior to using these memory spaces. Setting up the SystemCoreClock and Board_Init
|
||||
* require global memory for variable storage and are called from this function in
|
||||
* the Keil tool chain.
|
||||
*/
|
||||
void $Sub$$__main_after_scatterload(void)
|
||||
{
|
||||
SystemInit();
|
||||
$Super$$__main_after_scatterload();
|
||||
}
|
||||
#endif /* __CC_ARM */
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Direct Memory Access (DMA) driver function prototypes and data types.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -33,11 +33,11 @@
|
|||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _DMA_H_
|
||||
#define _DMA_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_DMA_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_DMA_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdbool.h>
|
||||
|
|
@ -57,53 +57,55 @@ extern "C" {
|
|||
|
||||
/* **** Definitions **** */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enumeration for the DMA Channel's priority level.
|
||||
*
|
||||
*/
|
||||
typedef enum {
|
||||
MXC_DMA_PRIO_HIGH = MXC_V_DMA_CFG_PRI_HIGH, ///< High Priority */
|
||||
MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CFG_PRI_MEDHIGH, ///< Medium High Priority */
|
||||
MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CFG_PRI_MEDLOW, ///< Medium Low Priority */
|
||||
MXC_DMA_PRIO_LOW = MXC_V_DMA_CFG_PRI_LOW, ///< Low Priority */
|
||||
MXC_DMA_PRIO_HIGH = MXC_V_DMA_CFG_PRI_HIGH, ///< High Priority */
|
||||
MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CFG_PRI_MEDHIGH, ///< Medium High Priority */
|
||||
MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CFG_PRI_MEDLOW, ///< Medium Low Priority */
|
||||
MXC_DMA_PRIO_LOW = MXC_V_DMA_CFG_PRI_LOW, ///< Low Priority */
|
||||
} mxc_dma_priority_t;
|
||||
|
||||
/** @brief DMA request select */
|
||||
typedef enum {
|
||||
MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CFG_REQSEL_MEMTOMEM, ///< Memory to Memory DMA Request Selection
|
||||
MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CFG_REQSEL_SPI0RX, ///< SPI0 Receive DMA Request Selection
|
||||
MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CFG_REQSEL_SPI1RX, ///< SPI1 Receive DMA Request Selection
|
||||
MXC_DMA_REQUEST_UART0RX = MXC_S_DMA_CFG_REQSEL_UART0RX, ///< UART0 Receive DMA Request Selection
|
||||
MXC_DMA_REQUEST_UART1RX = MXC_S_DMA_CFG_REQSEL_UART1RX, ///< UART1 Receive DMA Request Selection
|
||||
MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CFG_REQSEL_I2C0RX, ///< I2C0 Receive DMA Request Selection
|
||||
MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CFG_REQSEL_I2C1RX, ///< I2C1 Receive DMA Request Selection
|
||||
MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CFG_REQSEL_SPI0TX, ///< SPI0 Transmit DMA Request Selection
|
||||
MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CFG_REQSEL_SPI1TX, ///< SPI1 Transmit DMA Request Selection
|
||||
MXC_DMA_REQUEST_UART0TX = MXC_S_DMA_CFG_REQSEL_UART0TX, ///< UART0 Transmit DMA Request Selection
|
||||
MXC_DMA_REQUEST_UART1TX = MXC_S_DMA_CFG_REQSEL_UART1TX, ///< UART1 Transmit DMA Request Selection
|
||||
MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CFG_REQSEL_I2C0TX, ///< I2C0 Transmit DMA Request Selection
|
||||
MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CFG_REQSEL_I2C1TX, ///< I2C1 Transmit DMA Request Selection
|
||||
MXC_DMA_REQUEST_MEMTOMEM =
|
||||
MXC_S_DMA_CFG_REQSEL_MEMTOMEM, ///< Memory to Memory DMA Request Selection
|
||||
MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CFG_REQSEL_SPI0RX, ///< SPI0 Receive DMA Request Selection
|
||||
MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CFG_REQSEL_SPI1RX, ///< SPI1 Receive DMA Request Selection
|
||||
MXC_DMA_REQUEST_UART0RX = MXC_S_DMA_CFG_REQSEL_UART0RX, ///< UART0 Receive DMA Request Selection
|
||||
MXC_DMA_REQUEST_UART1RX = MXC_S_DMA_CFG_REQSEL_UART1RX, ///< UART1 Receive DMA Request Selection
|
||||
MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CFG_REQSEL_I2C0RX, ///< I2C0 Receive DMA Request Selection
|
||||
MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CFG_REQSEL_I2C1RX, ///< I2C1 Receive DMA Request Selection
|
||||
MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CFG_REQSEL_SPI0TX, ///< SPI0 Transmit DMA Request Selection
|
||||
MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CFG_REQSEL_SPI1TX, ///< SPI1 Transmit DMA Request Selection
|
||||
MXC_DMA_REQUEST_UART0TX =
|
||||
MXC_S_DMA_CFG_REQSEL_UART0TX, ///< UART0 Transmit DMA Request Selection
|
||||
MXC_DMA_REQUEST_UART1TX =
|
||||
MXC_S_DMA_CFG_REQSEL_UART1TX, ///< UART1 Transmit DMA Request Selection
|
||||
MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CFG_REQSEL_I2C0TX, ///< I2C0 Transmit DMA Request Selection
|
||||
MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CFG_REQSEL_I2C1TX, ///< I2C1 Transmit DMA Request Selection
|
||||
} mxc_dma_reqsel_t;
|
||||
|
||||
/** @brief Enumeration for the DMA prescaler */
|
||||
typedef enum {
|
||||
MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CFG_PSSEL_DIS, ///< Prescaler disabled
|
||||
MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CFG_PSSEL_DIV256, ///< Divide by 256
|
||||
MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CFG_PSSEL_DIV64K, ///< Divide by 65,536
|
||||
MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CFG_PSSEL_DIV16M, ///< Divide by 16,777,216
|
||||
MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CFG_PSSEL_DIS, ///< Prescaler disabled
|
||||
MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CFG_PSSEL_DIV256, ///< Divide by 256
|
||||
MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CFG_PSSEL_DIV64K, ///< Divide by 65,536
|
||||
MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CFG_PSSEL_DIV16M, ///< Divide by 16,777,216
|
||||
} mxc_dma_prescale_t;
|
||||
|
||||
/** @brief Enumeration for the DMA timeout value */
|
||||
typedef enum {
|
||||
MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CFG_TOSEL_TO4, ///< DMA timeout of 4 clocks
|
||||
MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CFG_TOSEL_TO8, ///< DMA timeout of 8 clocks
|
||||
MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CFG_TOSEL_TO16, ///< DMA timeout of 16 clocks
|
||||
MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CFG_TOSEL_TO32, ///< DMA timeout of 32 clocks
|
||||
MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CFG_TOSEL_TO64, ///< DMA timeout of 64 clocks
|
||||
MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CFG_TOSEL_TO128, ///< DMA timeout of 128 clocks
|
||||
MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CFG_TOSEL_TO256, ///< DMA timeout of 256 clocks
|
||||
MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CFG_TOSEL_TO512, ///< DMA timeout of 512 clocks
|
||||
MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CFG_TOSEL_TO4, ///< DMA timeout of 4 clocks
|
||||
MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CFG_TOSEL_TO8, ///< DMA timeout of 8 clocks
|
||||
MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CFG_TOSEL_TO16, ///< DMA timeout of 16 clocks
|
||||
MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CFG_TOSEL_TO32, ///< DMA timeout of 32 clocks
|
||||
MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CFG_TOSEL_TO64, ///< DMA timeout of 64 clocks
|
||||
MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CFG_TOSEL_TO128, ///< DMA timeout of 128 clocks
|
||||
MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CFG_TOSEL_TO256, ///< DMA timeout of 256 clocks
|
||||
MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CFG_TOSEL_TO512, ///< DMA timeout of 512 clocks
|
||||
} mxc_dma_timeout_t;
|
||||
|
||||
/** @brief DMA transfer data width */
|
||||
|
|
@ -111,9 +113,9 @@ typedef enum {
|
|||
/* Using the '_V_' define instead of the '_S_' since these same values will be used to
|
||||
specify the DSTWD also. The API functions will shift the value the correct amount
|
||||
prior to writing the cfg register. */
|
||||
MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CFG_SRCWD_BYTE, ///< DMA transfer in bytes
|
||||
MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CFG_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words
|
||||
MXC_DMA_WIDTH_WORD = MXC_V_DMA_CFG_SRCWD_WORD, ///< DMA transfer in 32-bit words
|
||||
MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CFG_SRCWD_BYTE, ///< DMA transfer in bytes
|
||||
MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CFG_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words
|
||||
MXC_DMA_WIDTH_WORD = MXC_V_DMA_CFG_SRCWD_WORD, ///< DMA transfer in 32-bit words
|
||||
} mxc_dma_width_t;
|
||||
|
||||
/**
|
||||
|
|
@ -122,12 +124,12 @@ typedef enum {
|
|||
*
|
||||
*/
|
||||
typedef struct {
|
||||
int ch; ///< The channel to load the configuration data into
|
||||
mxc_dma_reqsel_t reqsel;///< The request select line to be used (mem2mem, peripheral)
|
||||
mxc_dma_width_t srcwd; ///< The source width (could be dependent on FIFO width)
|
||||
mxc_dma_width_t dstwd; ///< The destination width (could be dependent on FIFO width)
|
||||
int srcinc_en; ///< Whether to increment the source address during the transfer
|
||||
int dstinc_en; ///< Whether to increment the source address during the transfer
|
||||
int ch; ///< The channel to load the configuration data into
|
||||
mxc_dma_reqsel_t reqsel; ///< The request select line to be used (mem2mem, peripheral)
|
||||
mxc_dma_width_t srcwd; ///< The source width (could be dependent on FIFO width)
|
||||
mxc_dma_width_t dstwd; ///< The destination width (could be dependent on FIFO width)
|
||||
int srcinc_en; ///< Whether to increment the source address during the transfer
|
||||
int dstinc_en; ///< Whether to increment the source address during the transfer
|
||||
} mxc_dma_config_t;
|
||||
|
||||
/**
|
||||
|
|
@ -135,10 +137,10 @@ typedef struct {
|
|||
*
|
||||
*/
|
||||
typedef struct {
|
||||
int ch; ///< The channel to use for the transfer
|
||||
void* source; ///< Pointer to the source address, if applicable
|
||||
void* dest; ///< Pointer to the destination address, if applicable
|
||||
int len; ///< Number of bytes to transfer
|
||||
int ch; ///< The channel to use for the transfer
|
||||
void *source; ///< Pointer to the source address, if applicable
|
||||
void *dest; ///< Pointer to the destination address, if applicable
|
||||
int len; ///< Number of bytes to transfer
|
||||
} mxc_dma_srcdst_t;
|
||||
|
||||
/**
|
||||
|
|
@ -148,12 +150,12 @@ typedef struct {
|
|||
*
|
||||
*/
|
||||
typedef struct {
|
||||
int ch; ///< The channel to use for the transfer
|
||||
mxc_dma_priority_t prio; ///< The DMA priority for the channel
|
||||
unsigned int reqwait_en; ///< Delay the timeout timer start until after first transfer
|
||||
mxc_dma_timeout_t tosel; ///< Number of prescaled clocks seen by the channel before a timeout
|
||||
mxc_dma_prescale_t pssel; ///< Prescaler for the timeout timer
|
||||
unsigned int burst_size; ///< Number of bytes moved in a single burst
|
||||
int ch; ///< The channel to use for the transfer
|
||||
mxc_dma_priority_t prio; ///< The DMA priority for the channel
|
||||
unsigned int reqwait_en; ///< Delay the timeout timer start until after first transfer
|
||||
mxc_dma_timeout_t tosel; ///< Number of prescaled clocks seen by the channel before a timeout
|
||||
mxc_dma_prescale_t pssel; ///< Prescaler for the timeout timer
|
||||
unsigned int burst_size; ///< Number of bytes moved in a single burst
|
||||
} mxc_dma_adv_config_t;
|
||||
|
||||
/**
|
||||
|
|
@ -161,7 +163,7 @@ typedef struct {
|
|||
*
|
||||
* @param dest Pointer to the destination of the copy
|
||||
*/
|
||||
typedef void (*mxc_dma_complete_cb_t) (void* dest);
|
||||
typedef void (*mxc_dma_complete_cb_t)(void *dest);
|
||||
|
||||
/**
|
||||
* @brief The callback called on completion of a transfer,
|
||||
|
|
@ -174,7 +176,7 @@ typedef void (*mxc_dma_complete_cb_t) (void* dest);
|
|||
* @return Returns the next transfer to be completed, or NULL
|
||||
* if no more transfers will be done
|
||||
*/
|
||||
typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t) (mxc_dma_srcdst_t dest);
|
||||
typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest);
|
||||
|
||||
/* **** Function Prototypes **** */
|
||||
/*************************/
|
||||
|
|
@ -185,7 +187,7 @@ typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t) (mxc_dma_srcdst_t dest);
|
|||
* @details This initialization is required before using the DMA driver functions.
|
||||
* @return #E_NO_ERROR if successful
|
||||
*/
|
||||
int MXC_DMA_Init (void);
|
||||
int MXC_DMA_Init(void);
|
||||
|
||||
/**
|
||||
* @brief Request DMA channel
|
||||
|
|
@ -196,7 +198,7 @@ int MXC_DMA_Init (void);
|
|||
* @return #E_BAD_STATE DMA is not initialized, call MXC_DMA_Init() first.
|
||||
* @return #E_BUSY DMA is currently busy (locked), try again later.
|
||||
*/
|
||||
int MXC_DMA_AcquireChannel (void);
|
||||
int MXC_DMA_AcquireChannel(void);
|
||||
|
||||
/**
|
||||
* @brief Release DMA channel
|
||||
|
|
@ -206,7 +208,7 @@ int MXC_DMA_AcquireChannel (void);
|
|||
*
|
||||
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
|
||||
*/
|
||||
int MXC_DMA_ReleaseChannel (int ch);
|
||||
int MXC_DMA_ReleaseChannel(int ch);
|
||||
|
||||
/**
|
||||
* @brief Configure the DMA channel
|
||||
|
|
@ -217,7 +219,7 @@ int MXC_DMA_ReleaseChannel (int ch);
|
|||
*
|
||||
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
|
||||
*/
|
||||
int MXC_DMA_ConfigChannel (mxc_dma_config_t config, mxc_dma_srcdst_t srcdst);
|
||||
int MXC_DMA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst);
|
||||
|
||||
/**
|
||||
* @brief Configure the DMA channel with more advanced parameters
|
||||
|
|
@ -226,7 +228,7 @@ int MXC_DMA_ConfigChannel (mxc_dma_config_t config, mxc_dma_srcdst_t srcdst);
|
|||
*
|
||||
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
|
||||
*/
|
||||
int MXC_DMA_AdvConfigChannel (mxc_dma_adv_config_t advConfig);
|
||||
int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig);
|
||||
|
||||
/**
|
||||
* @brief Set channel source, destination, and count for the transfer
|
||||
|
|
@ -237,7 +239,7 @@ int MXC_DMA_AdvConfigChannel (mxc_dma_adv_config_t advConfig);
|
|||
* Guide for more information.
|
||||
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
|
||||
*/
|
||||
int MXC_DMA_SetSrcDst (mxc_dma_srcdst_t srcdst);
|
||||
int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst);
|
||||
|
||||
/**
|
||||
* @brief Get channel source, destination, and count for transfer
|
||||
|
|
@ -246,7 +248,7 @@ int MXC_DMA_SetSrcDst (mxc_dma_srcdst_t srcdst);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for a list of return values
|
||||
*/
|
||||
int MXC_DMA_GetSrcDst (mxc_dma_srcdst_t *srcdst);
|
||||
int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst);
|
||||
|
||||
/**
|
||||
* @brief Set channel reload source, destination, and count for the transfer
|
||||
|
|
@ -257,7 +259,7 @@ int MXC_DMA_GetSrcDst (mxc_dma_srcdst_t *srcdst);
|
|||
* Guide for more information.
|
||||
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
|
||||
*/
|
||||
int MXC_DMA_SetSrcReload (mxc_dma_srcdst_t srcdstReload);
|
||||
int MXC_DMA_SetSrcReload(mxc_dma_srcdst_t srcdstReload);
|
||||
|
||||
/**
|
||||
* @brief Get channel reload source, destination, and count for transfer
|
||||
|
|
@ -266,7 +268,7 @@ int MXC_DMA_SetSrcReload (mxc_dma_srcdst_t srcdstReload);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for a list of return values
|
||||
*/
|
||||
int MXC_DMA_GetSrcReload (mxc_dma_srcdst_t *srcdstReload);
|
||||
int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdstReload);
|
||||
|
||||
/**
|
||||
* @brief Set channel interrupt callback
|
||||
|
|
@ -290,7 +292,7 @@ int MXC_DMA_GetSrcReload (mxc_dma_srcdst_t *srcdstReload);
|
|||
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR
|
||||
* otherwise
|
||||
*/
|
||||
int MXC_DMA_SetCallback (int ch, void (*callback) (int, int));
|
||||
int MXC_DMA_SetCallback(int ch, void (*callback)(int, int));
|
||||
|
||||
/**
|
||||
* @brief Set channel interrupt
|
||||
|
|
@ -302,7 +304,7 @@ int MXC_DMA_SetCallback (int ch, void (*callback) (int, int));
|
|||
* @param ctz Enable channel count to zero interrupt.
|
||||
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
|
||||
*/
|
||||
int MXC_DMA_SetChannelInterruptEn (int ch, bool chdis, bool ctz);
|
||||
int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz);
|
||||
|
||||
/**
|
||||
* @brief Enable channel interrupt
|
||||
|
|
@ -312,7 +314,7 @@ int MXC_DMA_SetChannelInterruptEn (int ch, bool chdis, bool ctz);
|
|||
* @param flags The flags to enable
|
||||
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
|
||||
*/
|
||||
int MXC_DMA_ChannelEnableInt (int ch, int flags);
|
||||
int MXC_DMA_ChannelEnableInt(int ch, int flags);
|
||||
|
||||
/**
|
||||
* @brief Disable channel interrupt
|
||||
|
|
@ -320,14 +322,14 @@ int MXC_DMA_ChannelEnableInt (int ch, int flags);
|
|||
* @param flags The flags to disable
|
||||
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
|
||||
*/
|
||||
int MXC_DMA_ChannelDisableInt (int ch, int flags);
|
||||
int MXC_DMA_ChannelDisableInt(int ch, int flags);
|
||||
|
||||
/**
|
||||
* @brief Read channel interrupt flags
|
||||
* @param ch channel handle
|
||||
* @return #E_BAD_PARAM if an unused or invalid channel handle, flags otherwise
|
||||
*/
|
||||
int MXC_DMA_ChannelGetFlags (int ch);
|
||||
int MXC_DMA_ChannelGetFlags(int ch);
|
||||
|
||||
/**
|
||||
* @brief Clear channel interrupt flags
|
||||
|
|
@ -335,7 +337,7 @@ int MXC_DMA_ChannelGetFlags (int ch);
|
|||
* @param flags The flags to clear
|
||||
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
|
||||
*/
|
||||
int MXC_DMA_ChannelClearFlags (int ch, int flags);
|
||||
int MXC_DMA_ChannelClearFlags(int ch, int flags);
|
||||
|
||||
/**
|
||||
* @brief Enable channel interrupt
|
||||
|
|
@ -344,14 +346,14 @@ int MXC_DMA_ChannelClearFlags (int ch, int flags);
|
|||
* @param ch channel handle
|
||||
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
|
||||
*/
|
||||
int MXC_DMA_EnableInt (int ch);
|
||||
int MXC_DMA_EnableInt(int ch);
|
||||
|
||||
/**
|
||||
* @brief Disable channel interrupt
|
||||
* @param ch channel handle
|
||||
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
|
||||
*/
|
||||
int MXC_DMA_DisableInt (int ch);
|
||||
int MXC_DMA_DisableInt(int ch);
|
||||
|
||||
/**
|
||||
* @brief Start transfer
|
||||
|
|
@ -359,14 +361,14 @@ int MXC_DMA_DisableInt (int ch);
|
|||
* @details Start the DMA channel transfer, assumes that MXC_DMA_SetSrcDstCnt() has been called beforehand.
|
||||
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
|
||||
*/
|
||||
int MXC_DMA_Start (int ch);
|
||||
int MXC_DMA_Start(int ch);
|
||||
|
||||
/**
|
||||
* @brief Stop DMA transfer, irrespective of status (complete or in-progress)
|
||||
* @param ch channel handle
|
||||
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
|
||||
*/
|
||||
int MXC_DMA_Stop (int ch);
|
||||
int MXC_DMA_Stop(int ch);
|
||||
|
||||
/**
|
||||
* @brief Get a pointer to the DMA channel registers
|
||||
|
|
@ -375,7 +377,7 @@ int MXC_DMA_Stop (int ch);
|
|||
* function can be used on a channel handle returned by MXC_DMA_AcquireChannel().
|
||||
* @return NULL if an unused or invalid channel handle, or a valid pointer otherwise
|
||||
*/
|
||||
mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs (int ch);
|
||||
mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch);
|
||||
|
||||
/**
|
||||
* @brief Interrupt handler function
|
||||
|
|
@ -400,7 +402,7 @@ void MXC_DMA_Handler();
|
|||
*
|
||||
* @return see \ref MXC_Error_Codes
|
||||
*/
|
||||
int MXC_DMA_MemCpy (void* dest, void* src, int len, mxc_dma_complete_cb_t callback);
|
||||
int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback);
|
||||
|
||||
/**
|
||||
* @brief Performs a memcpy, using DMA, optionally asynchronous
|
||||
|
|
@ -413,7 +415,8 @@ int MXC_DMA_MemCpy (void* dest, void* src, int len, mxc_dma_complete_cb_t callba
|
|||
*
|
||||
* @return see \ref MXC_Error_Codes
|
||||
*/
|
||||
int MXC_DMA_DoTransfer (mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback);
|
||||
int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst,
|
||||
mxc_dma_trans_chain_t callback);
|
||||
/**
|
||||
* For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver
|
||||
*/
|
||||
|
|
@ -423,4 +426,4 @@ int MXC_DMA_DoTransfer (mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, m
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DMA_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_DMA_H_
|
||||
|
|
|
|||
|
|
@ -4,8 +4,8 @@
|
|||
* @details This driver can be used to operate on the embedded flash memory.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -35,10 +35,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _FLC_H_
|
||||
#define _FLC_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_FLC_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_FLC_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "flc_regs.h"
|
||||
|
|
@ -58,10 +58,10 @@ extern "C" {
|
|||
/***** Definitions *****/
|
||||
|
||||
/// Bit mask that can be used to find the starting address of a page in flash
|
||||
#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1)
|
||||
#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1)
|
||||
|
||||
/// Calculate the address of a page in flash from the page number
|
||||
#define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE))
|
||||
#define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((uint32_t)page * MXC_FLASH_PAGE_SIZE))
|
||||
|
||||
/***** Function Prototypes *****/
|
||||
|
||||
|
|
@ -77,14 +77,14 @@ int MXC_FLC_Init();
|
|||
* with an erase or write operation.
|
||||
* @return If non-zero, flash operation is in progress
|
||||
*/
|
||||
int MXC_FLC_Busy (void);
|
||||
int MXC_FLC_Busy(void);
|
||||
|
||||
/**
|
||||
* @brief Erases the entire flash array.
|
||||
* @note This function must be executed from RAM.
|
||||
* @return #E_NO_ERROR If function is successful.
|
||||
*/
|
||||
int MXC_FLC_MassErase (void);
|
||||
int MXC_FLC_MassErase(void);
|
||||
|
||||
/**
|
||||
* @brief Erases the page of flash at the specified address.
|
||||
|
|
@ -92,7 +92,7 @@ int MXC_FLC_MassErase (void);
|
|||
* @param address Any address within the page to erase.
|
||||
* @return #E_NO_ERROR If function is successful.
|
||||
*/
|
||||
int MXC_FLC_PageErase (uint32_t address);
|
||||
int MXC_FLC_PageErase(uint32_t address);
|
||||
|
||||
/**
|
||||
* @brief Read Data out of Flash from an address
|
||||
|
|
@ -102,7 +102,7 @@ int MXC_FLC_PageErase (uint32_t address);
|
|||
* @param[in] len The length of the buffer
|
||||
*
|
||||
*/
|
||||
void MXC_FLC_Read (int address, void* buffer, int len);
|
||||
void MXC_FLC_Read(int address, void *buffer, int len);
|
||||
|
||||
/**
|
||||
* @brief Writes data to flash.
|
||||
|
|
@ -113,7 +113,7 @@ void MXC_FLC_Read (int address, void* buffer, int len);
|
|||
* @return #E_NO_ERROR If function is successful.
|
||||
* @note make sure to disable ICC with ICC_Disable(); before Running this function
|
||||
*/
|
||||
int MXC_FLC_Write (uint32_t address, uint32_t length, uint32_t *buffer);
|
||||
int MXC_FLC_Write(uint32_t address, uint32_t length, uint32_t *buffer);
|
||||
|
||||
/**
|
||||
* @brief Writes 32 bits of data to flash.
|
||||
|
|
@ -123,7 +123,7 @@ int MXC_FLC_Write (uint32_t address, uint32_t length, uint32_t *buffer);
|
|||
* @return #E_NO_ERROR If function is successful.
|
||||
* @note make sure to disable ICC with ICC_Disable(); before Running this function
|
||||
*/
|
||||
int MXC_FLC_Write32 (uint32_t address, uint32_t data);
|
||||
int MXC_FLC_Write32(uint32_t address, uint32_t data);
|
||||
|
||||
/**
|
||||
* @brief Writes 128 bits of data to flash.
|
||||
|
|
@ -133,27 +133,27 @@ int MXC_FLC_Write32 (uint32_t address, uint32_t data);
|
|||
* @return #E_NO_ERROR If function is successful.
|
||||
* @note make sure to disable ICC with ICC_Disable(); before Running this function
|
||||
*/
|
||||
int MXC_FLC_Write128 (uint32_t address, uint32_t *data);
|
||||
int MXC_FLC_Write128(uint32_t address, uint32_t *data);
|
||||
|
||||
/**
|
||||
* @brief Enable flash interrupts
|
||||
* @param flags Interrupts to enable
|
||||
* @return #E_NO_ERROR If function is successful.
|
||||
*/
|
||||
int MXC_FLC_EnableInt (uint32_t flags);
|
||||
int MXC_FLC_EnableInt(uint32_t flags);
|
||||
|
||||
/**
|
||||
* @brief Disable flash interrupts
|
||||
* @param flags Interrupts to disable
|
||||
* @return #E_NO_ERROR If function is successful.
|
||||
*/
|
||||
int MXC_FLC_DisableInt (uint32_t flags);
|
||||
int MXC_FLC_DisableInt(uint32_t flags);
|
||||
|
||||
/**
|
||||
* @brief Retrieve flash interrupt flags
|
||||
* @return Interrupt flags registers
|
||||
*/
|
||||
int MXC_FLC_GetFlags (void);
|
||||
int MXC_FLC_GetFlags(void);
|
||||
|
||||
/**
|
||||
* @brief Clear flash interrupt flags
|
||||
|
|
@ -161,7 +161,7 @@ int MXC_FLC_GetFlags (void);
|
|||
* @param flags Flag bit(s) to clear
|
||||
* @return #E_NO_ERROR If function is successful.
|
||||
*/
|
||||
int MXC_FLC_ClearFlags (uint32_t flags);
|
||||
int MXC_FLC_ClearFlags(uint32_t flags);
|
||||
|
||||
/**
|
||||
* @brief Unlock info block
|
||||
|
|
@ -170,7 +170,7 @@ int MXC_FLC_ClearFlags (uint32_t flags);
|
|||
*
|
||||
* @return #E_NO_ERROR If function is successful.
|
||||
*/
|
||||
int MXC_FLC_UnlockInfoBlock (uint32_t address);
|
||||
int MXC_FLC_UnlockInfoBlock(uint32_t address);
|
||||
|
||||
/**
|
||||
* @brief Lock info block
|
||||
|
|
@ -178,7 +178,7 @@ int MXC_FLC_UnlockInfoBlock (uint32_t address);
|
|||
* @param[in] address The address in the info block that was written to
|
||||
* @return #E_NO_ERROR If function is successful.
|
||||
*/
|
||||
int MXC_FLC_LockInfoBlock (uint32_t address);
|
||||
int MXC_FLC_LockInfoBlock(uint32_t address);
|
||||
|
||||
/**@} end of group flc */
|
||||
|
||||
|
|
@ -186,4 +186,4 @@ int MXC_FLC_LockInfoBlock (uint32_t address);
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FLC_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_FLC_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief General-Purpose Input/Output (GPIO) function prototypes and data types.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +34,11 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _GPIO_H_
|
||||
#define _GPIO_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_GPIO_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_GPIO_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "gpio_regs.h"
|
||||
|
|
@ -62,27 +62,27 @@ extern "C" {
|
|||
* @ingroup gpio_port_pin
|
||||
* @{
|
||||
*/
|
||||
#define MXC_GPIO_PORT_0 ((uint32_t)(1UL << 0)) ///< Port 0 Define
|
||||
#define MXC_GPIO_PORT_0 ((uint32_t)(1UL << 0)) ///< Port 0 Define
|
||||
/**@} end of gpio_port group*/
|
||||
/**
|
||||
* @defgroup gpio_pin Pin Definitions
|
||||
* @ingroup gpio_port_pin
|
||||
* @{
|
||||
*/
|
||||
#define MXC_GPIO_PIN_0 ((uint32_t)(1UL << 0)) ///< Pin 0 Define
|
||||
#define MXC_GPIO_PIN_1 ((uint32_t)(1UL << 1)) ///< Pin 1 Define
|
||||
#define MXC_GPIO_PIN_2 ((uint32_t)(1UL << 2)) ///< Pin 2 Define
|
||||
#define MXC_GPIO_PIN_3 ((uint32_t)(1UL << 3)) ///< Pin 3 Define
|
||||
#define MXC_GPIO_PIN_4 ((uint32_t)(1UL << 4)) ///< Pin 4 Define
|
||||
#define MXC_GPIO_PIN_5 ((uint32_t)(1UL << 5)) ///< Pin 5 Define
|
||||
#define MXC_GPIO_PIN_6 ((uint32_t)(1UL << 6)) ///< Pin 6 Define
|
||||
#define MXC_GPIO_PIN_7 ((uint32_t)(1UL << 7)) ///< Pin 7 Define
|
||||
#define MXC_GPIO_PIN_8 ((uint32_t)(1UL << 8)) ///< Pin 8 Define
|
||||
#define MXC_GPIO_PIN_9 ((uint32_t)(1UL << 9)) ///< Pin 9 Define
|
||||
#define MXC_GPIO_PIN_10 ((uint32_t)(1UL << 10)) ///< Pin 10 Define
|
||||
#define MXC_GPIO_PIN_11 ((uint32_t)(1UL << 11)) ///< Pin 11 Define
|
||||
#define MXC_GPIO_PIN_12 ((uint32_t)(1UL << 12)) ///< Pin 12 Define
|
||||
#define MXC_GPIO_PIN_13 ((uint32_t)(1UL << 13)) ///< Pin 13 Define
|
||||
#define MXC_GPIO_PIN_0 ((uint32_t)(1UL << 0)) ///< Pin 0 Define
|
||||
#define MXC_GPIO_PIN_1 ((uint32_t)(1UL << 1)) ///< Pin 1 Define
|
||||
#define MXC_GPIO_PIN_2 ((uint32_t)(1UL << 2)) ///< Pin 2 Define
|
||||
#define MXC_GPIO_PIN_3 ((uint32_t)(1UL << 3)) ///< Pin 3 Define
|
||||
#define MXC_GPIO_PIN_4 ((uint32_t)(1UL << 4)) ///< Pin 4 Define
|
||||
#define MXC_GPIO_PIN_5 ((uint32_t)(1UL << 5)) ///< Pin 5 Define
|
||||
#define MXC_GPIO_PIN_6 ((uint32_t)(1UL << 6)) ///< Pin 6 Define
|
||||
#define MXC_GPIO_PIN_7 ((uint32_t)(1UL << 7)) ///< Pin 7 Define
|
||||
#define MXC_GPIO_PIN_8 ((uint32_t)(1UL << 8)) ///< Pin 8 Define
|
||||
#define MXC_GPIO_PIN_9 ((uint32_t)(1UL << 9)) ///< Pin 9 Define
|
||||
#define MXC_GPIO_PIN_10 ((uint32_t)(1UL << 10)) ///< Pin 10 Define
|
||||
#define MXC_GPIO_PIN_11 ((uint32_t)(1UL << 11)) ///< Pin 11 Define
|
||||
#define MXC_GPIO_PIN_12 ((uint32_t)(1UL << 12)) ///< Pin 12 Define
|
||||
#define MXC_GPIO_PIN_13 ((uint32_t)(1UL << 13)) ///< Pin 13 Define
|
||||
/**@} end of gpio_pin group */
|
||||
/**@} end of gpio_port_pin group */
|
||||
|
||||
|
|
@ -94,65 +94,65 @@ extern "C" {
|
|||
* @param cbdata A void pointer to the data type as registered when
|
||||
* MXC_GPIO_RegisterCallback() was called.
|
||||
*/
|
||||
typedef void (*mxc_gpio_callback_fn) (void *cbdata);
|
||||
typedef void (*mxc_gpio_callback_fn)(void *cbdata);
|
||||
|
||||
/**
|
||||
* @brief Enumeration type for the GPIO Function Type
|
||||
*/
|
||||
typedef enum {
|
||||
MXC_GPIO_FUNC_IN, ///< GPIO Input
|
||||
MXC_GPIO_FUNC_OUT, ///< GPIO Output
|
||||
MXC_GPIO_FUNC_ALT1, ///< Alternate Function Selection
|
||||
MXC_GPIO_FUNC_ALT2, ///< Alternate Function Selection
|
||||
MXC_GPIO_FUNC_ALT3, ///< Alternate Function Selection
|
||||
MXC_GPIO_FUNC_ALT4, ///< Alternate Function Selection
|
||||
MXC_GPIO_FUNC_IN, ///< GPIO Input
|
||||
MXC_GPIO_FUNC_OUT, ///< GPIO Output
|
||||
MXC_GPIO_FUNC_ALT1, ///< Alternate Function Selection
|
||||
MXC_GPIO_FUNC_ALT2, ///< Alternate Function Selection
|
||||
MXC_GPIO_FUNC_ALT3, ///< Alternate Function Selection
|
||||
MXC_GPIO_FUNC_ALT4, ///< Alternate Function Selection
|
||||
} mxc_gpio_func_t;
|
||||
|
||||
/**
|
||||
* @brief Enumeration type for the voltage level on a given pin.
|
||||
*/
|
||||
typedef enum {
|
||||
MXC_GPIO_VSSEL_VDDIO, ///< Set pin to VIDDIO voltage
|
||||
MXC_GPIO_VSSEL_VDDIOH, ///< Set pin to VIDDIOH voltage
|
||||
MXC_GPIO_VSSEL_VDDIO, ///< Set pin to VIDDIO voltage
|
||||
MXC_GPIO_VSSEL_VDDIOH, ///< Set pin to VIDDIOH voltage
|
||||
} mxc_gpio_vssel_t;
|
||||
|
||||
/**
|
||||
* @brief Enumeration type for the type of GPIO pad on a given pin.
|
||||
*/
|
||||
typedef enum {
|
||||
MXC_GPIO_PAD_NONE, ///< No pull-up or pull-down
|
||||
MXC_GPIO_PAD_PULL_UP, ///< Set pad to weak pull-up
|
||||
MXC_GPIO_PAD_PULL_DOWN, ///< Set pad to weak pull-down
|
||||
MXC_GPIO_PAD_NONE, ///< No pull-up or pull-down
|
||||
MXC_GPIO_PAD_PULL_UP, ///< Set pad to weak pull-up
|
||||
MXC_GPIO_PAD_PULL_DOWN, ///< Set pad to weak pull-down
|
||||
} mxc_gpio_pad_t;
|
||||
|
||||
/**
|
||||
* @brief Structure type for configuring a GPIO port.
|
||||
*/
|
||||
typedef struct {
|
||||
mxc_gpio_regs_t* port; ///< Pointer to GPIO regs
|
||||
uint32_t mask; ///< Pin mask (multiple pins may be set)
|
||||
mxc_gpio_func_t func; ///< Function type
|
||||
mxc_gpio_pad_t pad; ///< Pad type
|
||||
mxc_gpio_vssel_t vssel; ///< Voltage select
|
||||
mxc_gpio_regs_t *port; ///< Pointer to GPIO regs
|
||||
uint32_t mask; ///< Pin mask (multiple pins may be set)
|
||||
mxc_gpio_func_t func; ///< Function type
|
||||
mxc_gpio_pad_t pad; ///< Pad type
|
||||
mxc_gpio_vssel_t vssel; ///< Voltage select
|
||||
} mxc_gpio_cfg_t;
|
||||
|
||||
/**
|
||||
* @brief Enumeration type for the interrupt modes.
|
||||
*/
|
||||
typedef enum {
|
||||
MXC_GPIO_INT_LEVEL, ///< Interrupt is level sensitive
|
||||
MXC_GPIO_INT_EDGE ///< Interrupt is edge sensitive
|
||||
MXC_GPIO_INT_LEVEL, ///< Interrupt is level sensitive
|
||||
MXC_GPIO_INT_EDGE ///< Interrupt is edge sensitive
|
||||
} mxc_gpio_int_mode_t;
|
||||
|
||||
/**
|
||||
* @brief Enumeration type for the interrupt polarity.
|
||||
*/
|
||||
typedef enum {
|
||||
MXC_GPIO_INT_FALLING, ///< Interrupt triggers on falling edge
|
||||
MXC_GPIO_INT_HIGH, ///< Interrupt triggers when level is high
|
||||
MXC_GPIO_INT_RISING, ///< Interrupt triggers on rising edge
|
||||
MXC_GPIO_INT_LOW, ///< Interrupt triggers when level is low
|
||||
MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge
|
||||
MXC_GPIO_INT_FALLING, ///< Interrupt triggers on falling edge
|
||||
MXC_GPIO_INT_HIGH, ///< Interrupt triggers when level is high
|
||||
MXC_GPIO_INT_RISING, ///< Interrupt triggers on rising edge
|
||||
MXC_GPIO_INT_LOW, ///< Interrupt triggers when level is low
|
||||
MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge
|
||||
} mxc_gpio_int_pol_t;
|
||||
|
||||
/* **** Function Prototypes **** */
|
||||
|
|
@ -162,28 +162,28 @@ typedef enum {
|
|||
* @param portMask Mask for the port to be initialized
|
||||
* @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
|
||||
*/
|
||||
int MXC_GPIO_Init (uint32_t portMask);
|
||||
int MXC_GPIO_Init(uint32_t portMask);
|
||||
|
||||
/**
|
||||
* @brief Shutdown GPIO.
|
||||
* @param portMask Mask for the port to be initialized
|
||||
* @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
|
||||
*/
|
||||
int MXC_GPIO_Shutdown (uint32_t portMask);
|
||||
int MXC_GPIO_Shutdown(uint32_t portMask);
|
||||
|
||||
/**
|
||||
* @brief Reset GPIO.
|
||||
* @param portMask Mask for the port to be initialized
|
||||
* @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
|
||||
*/
|
||||
int MXC_GPIO_Reset (uint32_t portMask);
|
||||
int MXC_GPIO_Reset(uint32_t portMask);
|
||||
|
||||
/**
|
||||
* @brief Configure GPIO pin(s).
|
||||
* @param cfg Pointer to configuration structure describing the pin.
|
||||
* @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
|
||||
*/
|
||||
int MXC_GPIO_Config (const mxc_gpio_cfg_t *cfg);
|
||||
int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg);
|
||||
|
||||
/**
|
||||
* @brief Gets the pin(s) input state.
|
||||
|
|
@ -191,21 +191,21 @@ int MXC_GPIO_Config (const mxc_gpio_cfg_t *cfg);
|
|||
* @param mask Mask of the pin(s) to read
|
||||
* @return The requested pin state.
|
||||
*/
|
||||
uint32_t MXC_GPIO_InGet (mxc_gpio_regs_t* port, uint32_t mask);
|
||||
uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t *port, uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Sets the pin(s) to a high level output.
|
||||
* @param port Pointer to the GPIO port registers
|
||||
* @param mask Mask of the pin(s) to set
|
||||
*/
|
||||
void MXC_GPIO_OutSet (mxc_gpio_regs_t* port, uint32_t mask);
|
||||
void MXC_GPIO_OutSet(mxc_gpio_regs_t *port, uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Clears the pin(s) to a low level output.
|
||||
* @param port Pointer to the GPIO port registers
|
||||
* @param mask Mask of the pin(s) to clear
|
||||
*/
|
||||
void MXC_GPIO_OutClr (mxc_gpio_regs_t* port, uint32_t mask);
|
||||
void MXC_GPIO_OutClr(mxc_gpio_regs_t *port, uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Gets the pin(s) output state.
|
||||
|
|
@ -214,7 +214,7 @@ void MXC_GPIO_OutClr (mxc_gpio_regs_t* port, uint32_t mask);
|
|||
* @return The state of the requested pin.
|
||||
*
|
||||
*/
|
||||
uint32_t MXC_GPIO_OutGet (mxc_gpio_regs_t* port, uint32_t mask);
|
||||
uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t *port, uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Write the pin(s) to a desired output level.
|
||||
|
|
@ -223,14 +223,14 @@ uint32_t MXC_GPIO_OutGet (mxc_gpio_regs_t* port, uint32_t mask);
|
|||
* @param val Desired output level of the pin(s). This will be masked
|
||||
* with the configuration mask.
|
||||
*/
|
||||
void MXC_GPIO_OutPut (mxc_gpio_regs_t* port, uint32_t mask, uint32_t val);
|
||||
void MXC_GPIO_OutPut(mxc_gpio_regs_t *port, uint32_t mask, uint32_t val);
|
||||
|
||||
/**
|
||||
* @brief Toggles the the pin(s) output level.
|
||||
* @param port Pointer to the GPIO port registers
|
||||
* @param mask Mask of the pin(s) to toggle
|
||||
*/
|
||||
void MXC_GPIO_OutToggle (mxc_gpio_regs_t* port, uint32_t mask);
|
||||
void MXC_GPIO_OutToggle(mxc_gpio_regs_t *port, uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Configure GPIO interrupt(s)
|
||||
|
|
@ -238,7 +238,7 @@ void MXC_GPIO_OutToggle (mxc_gpio_regs_t* port, uint32_t mask);
|
|||
* @param pol Requested interrupt polarity.
|
||||
* @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
|
||||
*/
|
||||
int MXC_GPIO_IntConfig (const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol);
|
||||
int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol);
|
||||
|
||||
/**
|
||||
* @brief Enables the specified GPIO interrupt
|
||||
|
|
@ -246,14 +246,14 @@ int MXC_GPIO_IntConfig (const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol);
|
|||
* @param mask Mask of the pin(s) to enable interrupts for
|
||||
*
|
||||
*/
|
||||
void MXC_GPIO_EnableInt (mxc_gpio_regs_t* port, uint32_t mask);
|
||||
void MXC_GPIO_EnableInt(mxc_gpio_regs_t *port, uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Disables the specified GPIO interrupt.
|
||||
* @param port Pointer to the GPIO port registers
|
||||
* @param mask Mask of the pin(s) to disable interrupts for
|
||||
*/
|
||||
void MXC_GPIO_DisableInt (mxc_gpio_regs_t* port, uint32_t mask);
|
||||
void MXC_GPIO_DisableInt(mxc_gpio_regs_t *port, uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Gets the interrupt(s) status on a GPIO port
|
||||
|
|
@ -262,7 +262,7 @@ void MXC_GPIO_DisableInt (mxc_gpio_regs_t* port, uint32_t mask);
|
|||
*
|
||||
* @return The requested interrupt status.
|
||||
*/
|
||||
uint32_t MXC_GPIO_GetFlags (mxc_gpio_regs_t* port);
|
||||
uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port);
|
||||
|
||||
/**
|
||||
* @brief Gets the interrupt(s) status on a GPIO port
|
||||
|
|
@ -270,7 +270,7 @@ uint32_t MXC_GPIO_GetFlags (mxc_gpio_regs_t* port);
|
|||
* @param port Pointer to the port requested
|
||||
* @param flags The flags to clear
|
||||
*/
|
||||
void MXC_GPIO_ClearFlags (mxc_gpio_regs_t* port, uint32_t flags);
|
||||
void MXC_GPIO_ClearFlags(mxc_gpio_regs_t *port, uint32_t flags);
|
||||
|
||||
/**
|
||||
* @brief Registers a callback for the interrupt on a given port and pin.
|
||||
|
|
@ -279,7 +279,8 @@ void MXC_GPIO_ClearFlags (mxc_gpio_regs_t* port, uint32_t flags);
|
|||
* @param cbdata The parameter to be passed to the callback function, #callback_fn, when an interrupt occurs.
|
||||
*
|
||||
*/
|
||||
void MXC_GPIO_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, void *cbdata);
|
||||
void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback,
|
||||
void *cbdata);
|
||||
|
||||
/**
|
||||
* @brief GPIO IRQ Handler. @note If a callback is registered for a given
|
||||
|
|
@ -288,7 +289,7 @@ void MXC_GPIO_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn
|
|||
* @param port Number of the port that generated the interrupt service routine.
|
||||
*
|
||||
*/
|
||||
void MXC_GPIO_Handler (unsigned int port);
|
||||
void MXC_GPIO_Handler(unsigned int port);
|
||||
|
||||
/**
|
||||
* @brief Set Voltage select for pins to VDDIO or VDDIOH
|
||||
|
|
@ -299,7 +300,32 @@ void MXC_GPIO_Handler (unsigned int port);
|
|||
*
|
||||
* @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
|
||||
*/
|
||||
int MXC_GPIO_SetVSSEL (mxc_gpio_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask);
|
||||
int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Enables GPIO pins to be used as a wakeup source.
|
||||
*
|
||||
* @param port The GPIO port
|
||||
* @param mask Pins in the GPIO port that will be enabled as a wakeup source.
|
||||
*/
|
||||
void MXC_GPIO_SetWakeEn(mxc_gpio_regs_t *port, uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Disables GPIO pins from being used as a wakeup source.
|
||||
*
|
||||
* @param port The GPIO port
|
||||
* @param mask Pins in the GPIO port that will be disabled as a wakeup source.
|
||||
*/
|
||||
void MXC_GPIO_ClearWakeEn(mxc_gpio_regs_t *port, uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Returns the pins currently enabled as wakeup sources.
|
||||
*
|
||||
* @param port The GPIO port to check.
|
||||
*
|
||||
* @returns The value of the wake enable register.
|
||||
*/
|
||||
uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port);
|
||||
|
||||
/**@} end of group gpio */
|
||||
|
||||
|
|
@ -307,4 +333,4 @@ int MXC_GPIO_SetVSSEL (mxc_gpio_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t m
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _GPIO_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_GPIO_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief I2S (Inter-Integrated Sound) driver function prototypes and data types.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,10 +34,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _I2S_H_
|
||||
#define _I2S_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_I2S_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_I2S_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_sys.h"
|
||||
|
|
@ -62,7 +62,7 @@ typedef enum {
|
|||
} mxc_i2s_sys_map_t;
|
||||
|
||||
typedef enum {
|
||||
LEFT_JUSTIFIED= 0,
|
||||
LEFT_JUSTIFIED = 0,
|
||||
RIGHT_JUSTIFIED = 1,
|
||||
} mxc_i2s_justify_t;
|
||||
|
||||
|
|
@ -77,21 +77,20 @@ typedef enum {
|
|||
AUDIO_IN = 2,
|
||||
} mxc_i2s_direction_t;
|
||||
|
||||
|
||||
/** @brief I2S Configuration Struct */
|
||||
typedef struct {
|
||||
mxc_i2s_sys_map_t map;
|
||||
mxc_i2s_justify_t justify;
|
||||
mxc_i2s_audio_mode_t audio_mode;
|
||||
mxc_i2s_direction_t audio_direction;
|
||||
uint16_t sample_rate;
|
||||
unsigned int start_immediately;
|
||||
unsigned int dma_reload_en;
|
||||
void *src_addr;
|
||||
void *dst_addr;
|
||||
uint32_t length;
|
||||
mxc_i2s_sys_map_t map;
|
||||
mxc_i2s_justify_t justify;
|
||||
mxc_i2s_audio_mode_t audio_mode;
|
||||
mxc_i2s_direction_t audio_direction;
|
||||
uint16_t sample_rate;
|
||||
unsigned int start_immediately;
|
||||
unsigned int dma_reload_en;
|
||||
void *src_addr;
|
||||
void *dst_addr;
|
||||
uint32_t length;
|
||||
} mxc_i2s_config_t;
|
||||
|
||||
|
||||
/* **** Function Prototypes **** */
|
||||
|
||||
/**
|
||||
|
|
@ -101,62 +100,62 @@ typedef struct {
|
|||
* @param dma_ctz_cb Function pointer to Count-to-Zero callback function.
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_I2S_Init(const mxc_i2s_config_t *config, void(*dma_ctz_cb)(int, int));
|
||||
int MXC_I2S_Init(const mxc_i2s_config_t *config, void (*dma_ctz_cb)(int, int));
|
||||
|
||||
/**
|
||||
* @brief Release I2S
|
||||
* @details De-configures the I2S protocol and stops DMA request
|
||||
* @return \c #E_BAD_PARAM if DMA cannot be stopped, #E_NO_ERROR otherwise
|
||||
*/
|
||||
*/
|
||||
int MXC_I2S_Shutdown(void);
|
||||
|
||||
/**
|
||||
* @brief Mute I2S Output
|
||||
* @details Sets I2S data to zero, continues sending clock and accessing DMA
|
||||
* @return \c #E_NO_ERROR
|
||||
*/
|
||||
*/
|
||||
int MXC_I2S_Mute(void);
|
||||
|
||||
/**
|
||||
* @brief Unmute I2S Output
|
||||
* @details Restores I2S data
|
||||
* @return \c #E_NO_ERROR
|
||||
*/
|
||||
*/
|
||||
int MXC_I2S_Unmute(void);
|
||||
|
||||
/**
|
||||
* @brief Pause I2S Output
|
||||
* @details Similar to mute, but stops FIFO and DMA access, clocks continue
|
||||
* @return \c #E_NO_ERROR
|
||||
*/
|
||||
*/
|
||||
int MXC_I2S_Pause(void);
|
||||
|
||||
/**
|
||||
* @brief Unpause I2S Output
|
||||
* @details Similar to mute, but restarts FIFO and DMA access
|
||||
* @return \c #E_NO_ERROR
|
||||
*/
|
||||
*/
|
||||
int MXC_I2S_Unpause(void);
|
||||
|
||||
/**
|
||||
* @brief Stops I2S Output
|
||||
* @details Similar to pause, but also halts clock
|
||||
* @return \c #E_NO_ERROR
|
||||
*/
|
||||
*/
|
||||
int MXC_I2S_Stop(void);
|
||||
|
||||
/**
|
||||
* @brief Starts I2S Output
|
||||
* @details Starts I2S Output, automatically called by configure if requested
|
||||
* @return \c #E_NO_ERROR
|
||||
*/
|
||||
*/
|
||||
int MXC_I2S_Start(void);
|
||||
|
||||
/**
|
||||
* @brief Clears DMA Interrupt Flags
|
||||
* @details Clears the DMA Interrupt flags, should be called at the end of a dma_ctz_cb
|
||||
* @return \c #E_NO_ERROR
|
||||
*/
|
||||
*/
|
||||
int MXC_I2S_DMA_ClearFlags(void);
|
||||
|
||||
/**
|
||||
|
|
@ -167,7 +166,7 @@ int MXC_I2S_DMA_ClearFlags(void);
|
|||
* @details Sets the address to read/write data in memory and the length of
|
||||
* the transfer. The unused addr parameter is ignored.
|
||||
* @return \c #E_NO_ERROR
|
||||
*/
|
||||
*/
|
||||
int MXC_I2S_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count);
|
||||
|
||||
/**
|
||||
|
|
@ -179,13 +178,12 @@ int MXC_I2S_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count);
|
|||
* (a CTZ event occurs) the src, dst, and count registers will be
|
||||
* set to these. The DMA reload flag clears after a reload occurs.
|
||||
* @return \c #E_NO_ERROR
|
||||
*/
|
||||
*/
|
||||
int MXC_I2S_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count);
|
||||
/**@} end of group i2s */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _I2S_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_I2S_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Instruction Controller Cache(ICC) function prototypes and data types.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +34,11 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _ICC_H_
|
||||
#define _ICC_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_ICC_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_ICC_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -58,9 +58,9 @@ extern "C" {
|
|||
* @brief Enumeration type for the Cache ID Register
|
||||
*/
|
||||
typedef enum {
|
||||
ICC_INFO_RELNUM, ///< Identifies the RTL release version
|
||||
ICC_INFO_PARTNUM, ///< Specifies the value of C_ID Port Number
|
||||
ICC_INFO_ID ///< Specifies the value of Cache ID
|
||||
ICC_INFO_RELNUM, ///< Identifies the RTL release version
|
||||
ICC_INFO_PARTNUM, ///< Specifies the value of C_ID Port Number
|
||||
ICC_INFO_ID ///< Specifies the value of Cache ID
|
||||
} mxc_icc_info_t;
|
||||
|
||||
/**
|
||||
|
|
@ -68,22 +68,22 @@ typedef enum {
|
|||
* @param cid Enumeration type for Cache Id Register.
|
||||
* @retval Returns the contents of Cache Id Register.
|
||||
*/
|
||||
int MXC_ICC_ID (mxc_icc_info_t cid);
|
||||
int MXC_ICC_ID(mxc_icc_info_t cid);
|
||||
|
||||
/**
|
||||
* @brief Enable the instruction cache controller.
|
||||
*/
|
||||
void MXC_ICC_Enable (void);
|
||||
void MXC_ICC_Enable(void);
|
||||
|
||||
/**
|
||||
* @brief Disable the instruction cache controller.
|
||||
*/
|
||||
void MXC_ICC_Disable (void);
|
||||
void MXC_ICC_Disable(void);
|
||||
|
||||
/**
|
||||
* @brief Flush the instruction cache controller.
|
||||
*/
|
||||
void MXC_ICC_Flush (void);
|
||||
void MXC_ICC_Flush(void);
|
||||
|
||||
/**@} end of group icc */
|
||||
|
||||
|
|
@ -91,4 +91,4 @@ void MXC_ICC_Flush (void);
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ICC_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_ICC_H_
|
||||
|
|
|
|||
|
|
@ -3,9 +3,8 @@
|
|||
* @brief Low power function prototypes and data types.
|
||||
*/
|
||||
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -35,16 +34,14 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2018-09-26 08:48:30 -0500 (Wed, 26 Sep 2018) $
|
||||
* $Revision: 38105 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
// Define to prevent redundant inclusion
|
||||
#ifndef _LP_H_
|
||||
#define _LP_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_LP_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_LP_H_
|
||||
|
||||
/***** Includes *****/
|
||||
#include "gpio.h"
|
||||
#include "pwrseq_regs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
|
@ -59,9 +56,9 @@ extern "C" {
|
|||
|
||||
/** @brief System reset0 enumeration. Used in SYS_PeriphReset0 function */
|
||||
typedef enum {
|
||||
MXC_LP_OVR_0_9 = MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V, /**< Reset DMA */
|
||||
MXC_LP_OVR_1_0 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V, /**< Reset DMA */
|
||||
MXC_LP_OVR_1_1 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V, /**< Reset DMA */
|
||||
MXC_LP_OVR_0_9 = MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V, /**< Reset DMA */
|
||||
MXC_LP_OVR_1_0 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V, /**< Reset DMA */
|
||||
MXC_LP_OVR_1_1 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V, /**< Reset DMA */
|
||||
} mxc_lp_ovr_t;
|
||||
|
||||
/**
|
||||
|
|
@ -163,18 +160,18 @@ void MXC_LP_DisableSysRAM0LightSleep(void);
|
|||
* @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode.
|
||||
* Call this function multiple times to enable pins on multiple ports. This function does not configure
|
||||
* the GPIO pins nor does it setup their interrupt functionality.
|
||||
* @param port The port to configure as wakeup sources.
|
||||
* @param mask The pins to configure as wakeup sources.
|
||||
* @param wu_pins The port and pins to configure as wakeup sources. Only the gpio and mask fields of the
|
||||
* structure are used. The func and pad fields are ignored.
|
||||
*/
|
||||
void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask);
|
||||
void MXC_LP_EnableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins);
|
||||
|
||||
/**
|
||||
* @brief Disables the selected GPIO port and its selected pins as a wake up source.
|
||||
* Call this function multiple times to disable pins on multiple ports.
|
||||
* @param port The port to configure as wakeup sources.
|
||||
* @param mask The pins to configure as wakeup sources.
|
||||
* @param wu_pins The port and pins to disable as wakeup sources. Only the gpio and mask fields of the
|
||||
* structure are used. The func and pad fields are ignored.
|
||||
*/
|
||||
void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask);
|
||||
void MXC_LP_DisableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins);
|
||||
|
||||
/**
|
||||
* @brief Enables the RTC alarm to wake up the device from any low power mode.
|
||||
|
|
@ -327,7 +324,6 @@ void MXC_LP_EnableVCoreSVM(void);
|
|||
*/
|
||||
void MXC_LP_DisableVCoreSVM(void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enables VDDIO Power-On-Reset Monitor
|
||||
*/
|
||||
|
|
@ -343,4 +339,4 @@ void MXC_LP_DisableVDDIOPorMonitor(void);
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _LP_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_LP_H_
|
||||
|
|
|
|||
|
|
@ -1,36 +1,35 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
********************************************************************************
|
||||
*/
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* \file
|
||||
|
|
@ -42,60 +41,64 @@
|
|||
* prototypes.
|
||||
*/
|
||||
|
||||
#ifndef _MSR_H_
|
||||
#define _MSR_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MSR_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MSR_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***** Definitions *****/
|
||||
|
||||
/// Number of tracks on a card
|
||||
#ifndef MSR_NUM_TRACKS
|
||||
#define MSR_NUM_TRACKS 3
|
||||
#define MSR_NUM_TRACKS 3
|
||||
#endif
|
||||
|
||||
#define MSR_MAX_SAMPLES 1536
|
||||
#define MSR_MAX_SAMPLES 1536
|
||||
|
||||
// Assuming nominal bit density of 210 bpi and 3.375 inch length
|
||||
#define MSR_MAX_RAW_LEN_BITS (709)
|
||||
#define MSR_MAX_RAW_LEN_BYTES ((MSR_MAX_RAW_LEN_BITS + 7) / 8)
|
||||
#define MSR_MAX_RAW_LEN_BITS (709)
|
||||
#define MSR_MAX_RAW_LEN_BYTES ((MSR_MAX_RAW_LEN_BITS + 7) / 8)
|
||||
#define MSR_MAX_RAW_LEN_HALFWORDS ((MSR_MAX_RAW_LEN_BITS + 15) / 16)
|
||||
|
||||
/// Maximum size in bytes of decoded track characters (5-bit min to 8-bit max)
|
||||
#define MSR_MAX_DEC_LEN (MSR_MAX_RAW_LEN_BITS / 5)
|
||||
#define MSR_MAX_DEC_LEN (MSR_MAX_RAW_LEN_BITS / 5)
|
||||
|
||||
/// Swipe direction: the card was swiped in the forward direction
|
||||
#define MSR_FORWARD 0
|
||||
#define MSR_FORWARD 0
|
||||
/// Swipe direction: the card was swiped in the reverse direction
|
||||
#define MSR_REVERSE 1
|
||||
#define MSR_REVERSE 1
|
||||
|
||||
/// Error codes
|
||||
#define MSR_ERR_OK 0x00
|
||||
#define MSR_ERR_BAD_LEN 0x01
|
||||
#define MSR_ERR_START_SEN 0x02
|
||||
#define MSR_ERR_END_SEN 0x04
|
||||
#define MSR_ERR_OUTLIER 0x08
|
||||
#define MSR_ERR_PARAM 0x10
|
||||
#define MSR_ERR_LRC 0x40
|
||||
#define MSR_ERR_PARITY 0x80
|
||||
#define MSR_ERR_OK 0x00
|
||||
#define MSR_ERR_BAD_LEN 0x01
|
||||
#define MSR_ERR_START_SEN 0x02
|
||||
#define MSR_ERR_END_SEN 0x04
|
||||
#define MSR_ERR_OUTLIER 0x08
|
||||
#define MSR_ERR_PARAM 0x10
|
||||
#define MSR_ERR_LRC 0x40
|
||||
#define MSR_ERR_PARITY 0x80
|
||||
|
||||
/// Structure to contain result of a track decode
|
||||
typedef struct {
|
||||
uint8_t error_code; /**< Error code value */
|
||||
uint8_t parity_errs; /**< Number of characters with parity errors */
|
||||
uint8_t lrc; /**< LRC check value. A value of '0' indicates a
|
||||
successful LRC check. Any other value should be
|
||||
considered a failure. */
|
||||
uint8_t direction; /**< Swipe direction determined from decode */
|
||||
uint8_t len; /**< Number or decoded characters. This does not include
|
||||
the sentinels or the LRC. */
|
||||
uint8_t error_code; ///< Error code value
|
||||
uint8_t parity_errs; ///< Number of characters with parity errors
|
||||
uint8_t lrc; ///< LRC check value. A value of '0' indicates a
|
||||
/// successful LRC check. Any other value should be
|
||||
/// considered a failure.
|
||||
uint8_t direction; ///< Swipe direction determined from decode
|
||||
uint8_t len; ///< Number or decoded characters. This does not include
|
||||
/// the sentinels or the LRC.
|
||||
uint16_t speed;
|
||||
uint8_t data[MSR_MAX_DEC_LEN]; /**< The decoded data */
|
||||
uint8_t data[MSR_MAX_DEC_LEN]; ///< The decoded data
|
||||
} msr_decoded_track_t;
|
||||
|
||||
/// MSR sample fields
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t time : 9;
|
||||
uint16_t amp : 7;
|
||||
uint16_t amp : 7;
|
||||
};
|
||||
uint16_t value;
|
||||
} msr_sample_t;
|
||||
|
|
@ -112,25 +115,25 @@ typedef struct {
|
|||
* \brief Initializes magnetic card reader hardware
|
||||
* \returns #E_NO_ERROR if everything is successful
|
||||
*/
|
||||
int msr_init (void);
|
||||
int msr_init(void);
|
||||
|
||||
/**
|
||||
* \brief Initializes specified track
|
||||
* \param track track number (1 to 3)
|
||||
*/
|
||||
void msr_init_track (unsigned int track);
|
||||
void msr_init_track(unsigned int track);
|
||||
|
||||
/**
|
||||
* \brief Enables magnetic card reader
|
||||
* \pre The reader should be initialized by calling msr_init() and then
|
||||
* waiting at least 100 us before calling this function.
|
||||
*/
|
||||
void msr_enable (void);
|
||||
void msr_enable(void);
|
||||
|
||||
/**
|
||||
* \brief Disables magnetic card reader
|
||||
*/
|
||||
void msr_disable (void);
|
||||
void msr_disable(void);
|
||||
|
||||
/**
|
||||
* \brief Task used to execute driver functionality.
|
||||
|
|
@ -139,7 +142,7 @@ void msr_disable (void);
|
|||
* when MSR interrupt servicing is disabled.
|
||||
* \returns 1 if all tracking reading is complete, 0 otherwise
|
||||
*/
|
||||
int msr_task (void);
|
||||
int msr_task(void);
|
||||
|
||||
/**
|
||||
* \brief Decodes the specified track of data
|
||||
|
|
@ -148,7 +151,7 @@ int msr_task (void);
|
|||
* \returns number of characters decoded
|
||||
* \note This function has significant stack usage.
|
||||
*/
|
||||
unsigned int msr_track_decode (unsigned int track, msr_decoded_track_t * decoded_track);
|
||||
unsigned int msr_track_decode(unsigned int track, msr_decoded_track_t *decoded_track);
|
||||
|
||||
/**
|
||||
* \brief Registers an application callback function
|
||||
|
|
@ -158,7 +161,7 @@ unsigned int msr_track_decode (unsigned int track, msr_decoded_track_t * decoded
|
|||
* function function with a NULL parameter.
|
||||
* \param func application callback function
|
||||
*/
|
||||
void msr_set_complete_callback (void (*func) (void));
|
||||
void msr_set_complete_callback(void (*func)(void));
|
||||
|
||||
/**
|
||||
* \brief Retrieves the raw (undecoded) sample data for the specified track
|
||||
|
|
@ -167,7 +170,10 @@ void msr_set_complete_callback (void (*func) (void));
|
|||
* \param samples pointer to where the sample data will be copied
|
||||
* \returns number of samples retrieved
|
||||
*/
|
||||
unsigned int mcr_get_track_samples (unsigned int track, msr_samples_t * samples);
|
||||
unsigned int mcr_get_track_samples(unsigned int track, msr_samples_t *samples);
|
||||
|
||||
#endif /* _MSR_H_ */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MSR_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Assertion checks for debugging.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,15 +34,14 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_ASSERT_H_
|
||||
#define _MXC_ASSERT_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_ASSERT_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_ASSERT_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
|
@ -65,11 +64,10 @@ extern "C" {
|
|||
* @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
|
||||
* defined.
|
||||
*/
|
||||
#define MXC_ASSERT(expr) \
|
||||
if (!(expr)) \
|
||||
{ \
|
||||
mxc_assert(#expr, __FILE__, __LINE__); \
|
||||
}
|
||||
#define MXC_ASSERT(expr) \
|
||||
if (!(expr)) { \
|
||||
mxc_assert(#expr, __FILE__, __LINE__); \
|
||||
}
|
||||
/**
|
||||
* Macro that generates an assertion with the message "FAIL".
|
||||
* @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
|
||||
|
|
@ -98,7 +96,7 @@ if (!(expr)) \
|
|||
* @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
|
||||
* defined.
|
||||
*/
|
||||
void mxc_assert (const char *expr, const char *file, int line);
|
||||
void mxc_assert(const char *expr, const char *file, int line);
|
||||
|
||||
/**@} end of group MXC_Assertions*/
|
||||
|
||||
|
|
@ -106,4 +104,4 @@ void mxc_assert (const char *expr, const char *file, int line);
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_ASSERT_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_ASSERT_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Asynchronous delay routines based on the SysTick Timer.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +34,17 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _DELAY_H_
|
||||
#define _DELAY_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_DELAY_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_DELAY_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @ingroup devicelibs
|
||||
|
|
@ -54,21 +60,21 @@
|
|||
* x = SEC(3) // 3 seconds -> x = 3,000,000
|
||||
* \endcode
|
||||
*/
|
||||
#define MXC_DELAY_SEC(s) (((unsigned long)s) * 1000000UL)
|
||||
#define MXC_DELAY_SEC(s) (((uint32_t)s) * 1000000UL)
|
||||
/**
|
||||
* Macro used to specify a microsecond timing parameter in milliseconds.
|
||||
* \code
|
||||
* x = MSEC(3) // 3ms -> x = 3,000
|
||||
* \endcode
|
||||
*/
|
||||
#define MXC_DELAY_MSEC(ms) (ms * 1000UL)
|
||||
#define MXC_DELAY_MSEC(ms) (ms * 1000UL)
|
||||
/**
|
||||
* Macro used to specify a microsecond timing parameter.
|
||||
* \code
|
||||
* x = USEC(3) // 3us -> x = 3
|
||||
* \endcode
|
||||
*/
|
||||
#define MXC_DELAY_USEC(us) (us)
|
||||
#define MXC_DELAY_USEC(us) (us)
|
||||
|
||||
/**
|
||||
* @brief The callback routine used by MXC_DelayAsync() when the delay is complete
|
||||
|
|
@ -76,7 +82,7 @@
|
|||
*
|
||||
* @param result See \ref MXC_Error_Codes for the list of error codes.
|
||||
*/
|
||||
typedef void (*mxc_delay_complete_t) (int result);
|
||||
typedef void (*mxc_delay_complete_t)(int result);
|
||||
|
||||
/***** Function Prototypes *****/
|
||||
|
||||
|
|
@ -88,7 +94,7 @@ typedef void (*mxc_delay_complete_t) (int result);
|
|||
* @param us microseconds to delay
|
||||
* @return #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful.
|
||||
*/
|
||||
int MXC_Delay (unsigned long us);
|
||||
int MXC_Delay(uint32_t us);
|
||||
|
||||
/**
|
||||
* @brief Starts a non-blocking delay for the specified number of
|
||||
|
|
@ -103,28 +109,32 @@ int MXC_Delay (unsigned long us);
|
|||
* @return #E_NO_ERROR if no errors, #E_BUSY if currently servicing another
|
||||
* delay request.
|
||||
*/
|
||||
int MXC_DelayAsync (unsigned long us, mxc_delay_complete_t callback);
|
||||
int MXC_DelayAsync(uint32_t us, mxc_delay_complete_t callback);
|
||||
|
||||
/**
|
||||
* @brief Returns the status of a non-blocking delay request
|
||||
* @pre Start the asynchronous delay by calling MXC_Delay_start().
|
||||
* @return #E_BUSY until the requested delay time has expired.
|
||||
*/
|
||||
int MXC_DelayCheck (void);
|
||||
int MXC_DelayCheck(void);
|
||||
|
||||
/**
|
||||
* @brief Stops an asynchronous delay previously started.
|
||||
* @pre Start the asynchronous delay by calling MXC_Delay_start().
|
||||
*/
|
||||
void MXC_DelayAbort (void);
|
||||
void MXC_DelayAbort(void);
|
||||
|
||||
/**
|
||||
* @brief Processes the delay interrupt.
|
||||
* @details This function must be called from the SysTick IRQ or polled at a
|
||||
* rate greater than the SysTick overflow rate.
|
||||
*/
|
||||
void MXC_DelayHandler (void);
|
||||
void MXC_DelayHandler(void);
|
||||
|
||||
/**@} end of group MXC_delay */
|
||||
|
||||
#endif /* _DELAY_H_ */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_DELAY_H_
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,46 +29,42 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @file mxc_device.h
|
||||
* @brief contains device and revision specific definitions
|
||||
*/
|
||||
|
||||
#ifndef _MXC_DEVICE_H_
|
||||
#define _MXC_DEVICE_H_
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_DEVICE_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_DEVICE_H_
|
||||
|
||||
#include "max32660.h"
|
||||
#include "mxc_errors.h"
|
||||
|
||||
|
||||
#ifndef TARGET
|
||||
#error TARGET NOT DEFINED
|
||||
#error TARGET NOT DEFINED
|
||||
#endif
|
||||
|
||||
// Create a string definition for the TARGET
|
||||
#define STRING_ARG(arg) #arg
|
||||
#define STRING_NAME(name) STRING_ARG(name)
|
||||
#if MBED_VERSION && MBED_VERSION < 51200
|
||||
#define TARGET_NAME STRING_NAME(TARGET)
|
||||
#endif
|
||||
|
||||
// Define which revisions of the IP we are using
|
||||
#ifndef TARGET_REV
|
||||
#error TARGET_REV NOT DEFINED
|
||||
#error TARGET_REV NOT DEFINED
|
||||
#endif
|
||||
|
||||
#if(TARGET_REV == 0x4131)
|
||||
// A1
|
||||
#define MXC_PBM_REV 0
|
||||
#define MXC_TMR_REV 0
|
||||
#define MXC_UART_REV 1
|
||||
#if (TARGET_REV == 0x4131)
|
||||
// A1
|
||||
#define MXC_PBM_REV 0
|
||||
#define MXC_TMR_REV 0
|
||||
#define MXC_UART_REV 1
|
||||
#else
|
||||
|
||||
#error TARGET_REV NOT SUPPORTED
|
||||
|
||||
#endif // if(TARGET_REV == ...)
|
||||
#endif // if(TARGET_REV == ...)
|
||||
|
||||
#endif /* _MXC_DEVICE_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_DEVICE_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief List of common error return codes for Maxim Integrated libraries.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +34,11 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_ERRORS_H_
|
||||
#define _MXC_ERRORS_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_ERRORS_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_ERRORS_H_
|
||||
|
||||
/**
|
||||
* @ingroup syscfg
|
||||
|
|
@ -50,43 +50,45 @@
|
|||
*/
|
||||
|
||||
/** No Error */
|
||||
#define E_NO_ERROR 0
|
||||
#define E_NO_ERROR 0
|
||||
/** No Error, success */
|
||||
#define E_SUCCESS 0
|
||||
#define E_SUCCESS 0
|
||||
/** Pointer is NULL */
|
||||
#define E_NULL_PTR -1
|
||||
#define E_NULL_PTR -1
|
||||
/** No such device */
|
||||
#define E_NO_DEVICE -2
|
||||
#define E_NO_DEVICE -2
|
||||
/** Parameter not acceptable */
|
||||
#define E_BAD_PARAM -3
|
||||
#define E_BAD_PARAM -3
|
||||
/** Value not valid or allowed */
|
||||
#define E_INVALID -4
|
||||
#define E_INVALID -4
|
||||
/** Module not initialized */
|
||||
#define E_UNINITIALIZED -5
|
||||
#define E_UNINITIALIZED -5
|
||||
/** Busy now, try again later */
|
||||
#define E_BUSY -6
|
||||
#define E_BUSY -6
|
||||
/** Operation not allowed in current state */
|
||||
#define E_BAD_STATE -7
|
||||
#define E_BAD_STATE -7
|
||||
/** Generic error */
|
||||
#define E_UNKNOWN -8
|
||||
#define E_UNKNOWN -8
|
||||
/** General communications error */
|
||||
#define E_COMM_ERR -9
|
||||
#define E_COMM_ERR -9
|
||||
/** Operation timed out */
|
||||
#define E_TIME_OUT -10
|
||||
#define E_TIME_OUT -10
|
||||
/** Expected response did not occur */
|
||||
#define E_NO_RESPONSE -11
|
||||
#define E_NO_RESPONSE -11
|
||||
/** Operations resulted in unexpected overflow */
|
||||
#define E_OVERFLOW -12
|
||||
#define E_OVERFLOW -12
|
||||
/** Operations resulted in unexpected underflow */
|
||||
#define E_UNDERFLOW -13
|
||||
#define E_UNDERFLOW -13
|
||||
/** Data or resource not available at this time */
|
||||
#define E_NONE_AVAIL -14
|
||||
#define E_NONE_AVAIL -14
|
||||
/** Event was shutdown */
|
||||
#define E_SHUTDOWN -15
|
||||
#define E_SHUTDOWN -15
|
||||
/** Event was aborted */
|
||||
#define E_ABORT -16
|
||||
#define E_ABORT -16
|
||||
/** The requested operation is not supported */
|
||||
#define E_NOT_SUPPORTED -17
|
||||
#define E_NOT_SUPPORTED -17
|
||||
/** The requested operation is failed */
|
||||
#define E_FAIL -255
|
||||
/**@} end of MXC_Error_Codes group */
|
||||
|
||||
#endif /* _MXC_ERRORS_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_ERRORS_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Inter-integrated circuit (I2C) communications interface driver.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +34,11 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_I2C_H_
|
||||
#define _MXC_I2C_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_I2C_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_I2C_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include "mxc_sys.h"
|
||||
|
|
@ -69,7 +69,7 @@ typedef struct _i2c_req_t mxc_i2c_req_t;
|
|||
* @return 0 if the byte should not be acknowledged (NACK), non-zero to
|
||||
* acknowledge the byte.
|
||||
*/
|
||||
typedef int (*mxc_i2c_getAck_t) (mxc_i2c_regs_t* i2c, unsigned char byte);
|
||||
typedef int (*mxc_i2c_getAck_t)(mxc_i2c_regs_t *i2c, unsigned char byte);
|
||||
|
||||
/**
|
||||
* @brief The callback routine used by the MXC_I2C_MasterTransactionAsync()
|
||||
|
|
@ -80,7 +80,7 @@ typedef int (*mxc_i2c_getAck_t) (mxc_i2c_regs_t* i2c, unsigned char byte);
|
|||
* transmitted is not acknowledged, negative if error.
|
||||
* See \ref MXC_Error_Codes for the list of error codes.
|
||||
*/
|
||||
typedef void (*mxc_i2c_complete_cb_t) (mxc_i2c_req_t* req, int result);
|
||||
typedef void (*mxc_i2c_complete_cb_t)(mxc_i2c_req_t *req, int result);
|
||||
|
||||
/**
|
||||
* @brief The callback routine used by the I2C Read/Write FIFO DMA
|
||||
|
|
@ -89,7 +89,7 @@ typedef void (*mxc_i2c_complete_cb_t) (mxc_i2c_req_t* req, int result);
|
|||
* @param len The length of data actually read/written
|
||||
* @param result See \ref MXC_Error_Codes for the list of error codes.
|
||||
*/
|
||||
typedef void (*mxc_i2c_dma_complete_cb_t) (int len, int result);
|
||||
typedef void (*mxc_i2c_dma_complete_cb_t)(int len, int result);
|
||||
|
||||
/**
|
||||
* @brief The information required to perform a complete I2C transaction as
|
||||
|
|
@ -100,22 +100,22 @@ typedef void (*mxc_i2c_dma_complete_cb_t) (int len, int result);
|
|||
* MXC_I2C_MasterTransactionAsync() functions.
|
||||
*/
|
||||
struct _i2c_req_t {
|
||||
mxc_i2c_regs_t* i2c; ///< Pointer to I2C registers (selects the
|
||||
mxc_i2c_regs_t *i2c; ///< Pointer to I2C registers (selects the
|
||||
///< I2C block used.)
|
||||
unsigned int addr; ///< The 7-bit or 10-bit address of the slave.
|
||||
unsigned char* tx_buf; ///< The buffer containing the bytes to write.
|
||||
unsigned int tx_len; ///< The number of bytes to write. On return
|
||||
unsigned int addr; ///< The 7-bit or 10-bit address of the slave.
|
||||
unsigned char *tx_buf; ///< The buffer containing the bytes to write.
|
||||
unsigned int tx_len; ///< The number of bytes to write. On return
|
||||
///< from the function, this will be set to
|
||||
///< the number of bytes actually transmitted.
|
||||
unsigned char* rx_buf; ///< The buffer to read the data into.
|
||||
unsigned int rx_len; ///< The number of bytes to read. On return
|
||||
unsigned char *rx_buf; ///< The buffer to read the data into.
|
||||
unsigned int rx_len; ///< The number of bytes to read. On return
|
||||
///< from the function, this will be set to
|
||||
///< the number of bytes actually received.
|
||||
int restart; ///< Controls whether the transaction is
|
||||
int restart; ///< Controls whether the transaction is
|
||||
///< terminated with a stop or repeated start
|
||||
///< condition. Use 0 for a stop, non-zero
|
||||
///< for repeated start.
|
||||
mxc_i2c_complete_cb_t callback; ///< The callback used to indicate the
|
||||
mxc_i2c_complete_cb_t callback; ///< The callback used to indicate the
|
||||
///< transaction is complete or an error has
|
||||
///< occurred. This field may be set to NULL
|
||||
///< if no indication is necessary. This
|
||||
|
|
@ -134,18 +134,18 @@ struct _i2c_req_t {
|
|||
* application to handle these events.
|
||||
*/
|
||||
typedef enum {
|
||||
MXC_I2C_EVT_MASTER_WR, ///< A slave address match occurred with the master
|
||||
MXC_I2C_EVT_MASTER_WR, ///< A slave address match occurred with the master
|
||||
///< requesting a write to the slave.
|
||||
MXC_I2C_EVT_MASTER_RD, ///< A slave address match occurred with the master
|
||||
MXC_I2C_EVT_MASTER_RD, ///< A slave address match occurred with the master
|
||||
///< requesting a read from the slave.
|
||||
MXC_I2C_EVT_RX_THRESH, ///< The receive FIFO contains more bytes than its
|
||||
MXC_I2C_EVT_RX_THRESH, ///< The receive FIFO contains more bytes than its
|
||||
///< threshold level.
|
||||
MXC_I2C_EVT_TX_THRESH, ///< The transmit FIFO contains fewer bytes than its
|
||||
MXC_I2C_EVT_TX_THRESH, ///< The transmit FIFO contains fewer bytes than its
|
||||
///< threshold level.
|
||||
MXC_I2C_EVT_TRANS_COMP, ///< The transaction has ended.
|
||||
MXC_I2C_EVT_UNDERFLOW, ///< The master has attempted a read when the
|
||||
MXC_I2C_EVT_UNDERFLOW, ///< The master has attempted a read when the
|
||||
///< transmit FIFO was empty.
|
||||
MXC_I2C_EVT_OVERFLOW, ///< The master has written data when the receive
|
||||
MXC_I2C_EVT_OVERFLOW, ///< The master has written data when the receive
|
||||
///< FIFO was already full.
|
||||
} mxc_i2c_slave_event_t;
|
||||
|
||||
|
|
@ -165,9 +165,9 @@ typedef enum {
|
|||
* non-zero to not acknowledge. The return value is ignored for all
|
||||
* other event types.
|
||||
*/
|
||||
typedef int (*mxc_i2c_slave_handler_t) (mxc_i2c_regs_t* i2c,
|
||||
mxc_i2c_slave_event_t event, void* data);
|
||||
|
||||
typedef int (*mxc_i2c_slave_handler_t)(mxc_i2c_regs_t *i2c, mxc_i2c_slave_event_t event,
|
||||
void *data);
|
||||
|
||||
/***** Function Prototypes *****/
|
||||
|
||||
/* ************************************************************************* */
|
||||
|
|
@ -188,7 +188,7 @@ typedef int (*mxc_i2c_slave_handler_t) (mxc_i2c_regs_t* i2c,
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_I2C_Init (mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr);
|
||||
int MXC_I2C_Init(mxc_i2c_regs_t *i2c, int masterMode, unsigned int slaveAddr);
|
||||
|
||||
/**
|
||||
* @brief Set slave address for I2C instances acting as slaves on the bus.
|
||||
|
|
@ -202,7 +202,7 @@ int MXC_I2C_Init (mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx);
|
||||
int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t *i2c, unsigned int slaveAddr, int idx);
|
||||
|
||||
/**
|
||||
* @brief Disable and shutdown I2C peripheral.
|
||||
|
|
@ -211,7 +211,7 @@ int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_I2C_Shutdown (mxc_i2c_regs_t* i2c);
|
||||
int MXC_I2C_Shutdown(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief Set the frequency of the I2C interface.
|
||||
|
|
@ -222,7 +222,7 @@ int MXC_I2C_Shutdown (mxc_i2c_regs_t* i2c);
|
|||
* @return Negative if error, otherwise actual speed set. See \ref
|
||||
* MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_I2C_SetFrequency (mxc_i2c_regs_t* i2c, unsigned int hz);
|
||||
int MXC_I2C_SetFrequency(mxc_i2c_regs_t *i2c, unsigned int hz);
|
||||
|
||||
/**
|
||||
* @brief Get the frequency of the I2C interface.
|
||||
|
|
@ -231,7 +231,7 @@ int MXC_I2C_SetFrequency (mxc_i2c_regs_t* i2c, unsigned int hz);
|
|||
*
|
||||
* @return The I2C bus frequency in Hertz
|
||||
*/
|
||||
unsigned int MXC_I2C_GetFrequency (mxc_i2c_regs_t* i2c);
|
||||
unsigned int MXC_I2C_GetFrequency(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief Checks if the given I2C bus can be placed in sleep more.
|
||||
|
|
@ -245,7 +245,7 @@ unsigned int MXC_I2C_GetFrequency (mxc_i2c_regs_t* i2c);
|
|||
* @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref
|
||||
* MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_I2C_ReadyForSleep (mxc_i2c_regs_t* i2c);
|
||||
int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief Enables or disables clock stretching by the slave.
|
||||
|
|
@ -258,7 +258,7 @@ int MXC_I2C_ReadyForSleep (mxc_i2c_regs_t* i2c);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_I2C_SetClockStretching (mxc_i2c_regs_t* i2c, int enable);
|
||||
int MXC_I2C_SetClockStretching(mxc_i2c_regs_t *i2c, int enable);
|
||||
|
||||
/**
|
||||
* @brief Determines if clock stretching has been enabled.
|
||||
|
|
@ -267,7 +267,7 @@ int MXC_I2C_SetClockStretching (mxc_i2c_regs_t* i2c, int enable);
|
|||
*
|
||||
* @return Zero if clock stretching is disabled, non-zero otherwise
|
||||
*/
|
||||
int MXC_I2C_GetClockStretching (mxc_i2c_regs_t* i2c);
|
||||
int MXC_I2C_GetClockStretching(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/* ************************************************************************* */
|
||||
/* Low-level functions */
|
||||
|
|
@ -284,7 +284,7 @@ int MXC_I2C_GetClockStretching (mxc_i2c_regs_t* i2c);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_I2C_Start (mxc_i2c_regs_t* i2c);
|
||||
int MXC_I2C_Start(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief Generate a stop condition on the I2C bus.
|
||||
|
|
@ -293,7 +293,7 @@ int MXC_I2C_Start (mxc_i2c_regs_t* i2c);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_I2C_Stop (mxc_i2c_regs_t* i2c);
|
||||
int MXC_I2C_Stop(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief Write a single byte to the I2C bus.
|
||||
|
|
@ -310,7 +310,7 @@ int MXC_I2C_Stop (mxc_i2c_regs_t* i2c);
|
|||
* @return 0 if byte is acknowledged, 1 if not acknowledged, negative if
|
||||
* error. See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_I2C_WriteByte (mxc_i2c_regs_t* i2c, unsigned char byte);
|
||||
int MXC_I2C_WriteByte(mxc_i2c_regs_t *i2c, unsigned char byte);
|
||||
|
||||
/**
|
||||
* @brief Read a single byte from the I2C bus.
|
||||
|
|
@ -326,7 +326,7 @@ int MXC_I2C_WriteByte (mxc_i2c_regs_t* i2c, unsigned char byte);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_I2C_ReadByte (mxc_i2c_regs_t* i2c, unsigned char* byte, int ack);
|
||||
int MXC_I2C_ReadByte(mxc_i2c_regs_t *i2c, unsigned char *byte, int ack);
|
||||
|
||||
/**
|
||||
* @brief Read a single byte from the I2C bus.
|
||||
|
|
@ -350,9 +350,8 @@ int MXC_I2C_ReadByte (mxc_i2c_regs_t* i2c, unsigned char* byte, int ack);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_I2C_ReadByteInteractive (mxc_i2c_regs_t* i2c, unsigned char* byte,
|
||||
mxc_i2c_getAck_t getAck);
|
||||
|
||||
int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t *i2c, unsigned char *byte, mxc_i2c_getAck_t getAck);
|
||||
|
||||
/**
|
||||
* @brief Write multiple bytes to the I2C bus.
|
||||
*
|
||||
|
|
@ -370,7 +369,7 @@ int MXC_I2C_ReadByteInteractive (mxc_i2c_regs_t* i2c, unsigned char* byte,
|
|||
* acknowledged, negative if error. See \ref MXC_Error_Codes for the
|
||||
* list of error return codes.
|
||||
*/
|
||||
int MXC_I2C_Write (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len);
|
||||
int MXC_I2C_Write(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len);
|
||||
|
||||
/**
|
||||
* @brief Read multiple bytes from the I2C bus.
|
||||
|
|
@ -389,9 +388,8 @@ int MXC_I2C_Write (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len)
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_I2C_Read (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len,
|
||||
int ack);
|
||||
|
||||
int MXC_I2C_Read(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack);
|
||||
|
||||
/**
|
||||
* @brief Unloads bytes from the receive FIFO.
|
||||
*
|
||||
|
|
@ -401,9 +399,8 @@ int MXC_I2C_Read (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len,
|
|||
*
|
||||
* @return The number of bytes actually read.
|
||||
*/
|
||||
int MXC_I2C_ReadRXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes,
|
||||
unsigned int len);
|
||||
|
||||
int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len);
|
||||
|
||||
/**
|
||||
* @brief Unloads bytes from the receive FIFO using DMA for longer reads.
|
||||
*
|
||||
|
|
@ -416,9 +413,9 @@ int MXC_I2C_ReadRXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes,
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for a list of return values.
|
||||
*/
|
||||
int MXC_I2C_ReadRXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes,
|
||||
unsigned int len, mxc_i2c_dma_complete_cb_t callback);
|
||||
|
||||
int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len,
|
||||
mxc_i2c_dma_complete_cb_t callback);
|
||||
|
||||
/**
|
||||
* @brief Get the number of bytes currently available in the receive FIFO.
|
||||
*
|
||||
|
|
@ -426,7 +423,7 @@ int MXC_I2C_ReadRXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes,
|
|||
*
|
||||
* @return The number of bytes available.
|
||||
*/
|
||||
int MXC_I2C_GetRXFIFOAvailable (mxc_i2c_regs_t* i2c);
|
||||
int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief Loads bytes into the transmit FIFO.
|
||||
|
|
@ -437,9 +434,8 @@ int MXC_I2C_GetRXFIFOAvailable (mxc_i2c_regs_t* i2c);
|
|||
*
|
||||
* @return The number of bytes actually written.
|
||||
*/
|
||||
int MXC_I2C_WriteTXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes,
|
||||
unsigned int len);
|
||||
|
||||
int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len);
|
||||
|
||||
/**
|
||||
* @brief Loads bytes into the transmit FIFO using DMA for longer writes.
|
||||
*
|
||||
|
|
@ -451,9 +447,9 @@ int MXC_I2C_WriteTXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes,
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for a list of return values
|
||||
*/
|
||||
int MXC_I2C_WriteTXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes,
|
||||
unsigned int len, mxc_i2c_dma_complete_cb_t callback);
|
||||
|
||||
int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len,
|
||||
mxc_i2c_dma_complete_cb_t callback);
|
||||
|
||||
/**
|
||||
* @brief Get the amount of free space available in the transmit FIFO.
|
||||
*
|
||||
|
|
@ -461,21 +457,21 @@ int MXC_I2C_WriteTXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes,
|
|||
*
|
||||
* @return The number of bytes available.
|
||||
*/
|
||||
int MXC_I2C_GetTXFIFOAvailable (mxc_i2c_regs_t* i2c);
|
||||
int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief Removes and discards all bytes currently in the receive FIFO.
|
||||
*
|
||||
* @param i2c Pointer to I2C registers (selects the I2C block used.)
|
||||
*/
|
||||
void MXC_I2C_ClearRXFIFO (mxc_i2c_regs_t* i2c);
|
||||
void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief Removes and discards all bytes currently in the transmit FIFO.
|
||||
*
|
||||
* @param i2c Pointer to I2C registers (selects the I2C block used.)
|
||||
*/
|
||||
void MXC_I2C_ClearTXFIFO (mxc_i2c_regs_t* i2c);
|
||||
void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief Get the presently set interrupt flags.
|
||||
|
|
@ -486,7 +482,7 @@ void MXC_I2C_ClearTXFIFO (mxc_i2c_regs_t* i2c);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for a list of return values
|
||||
*/
|
||||
int MXC_I2C_GetFlags (mxc_i2c_regs_t* i2c, unsigned int *flags0, unsigned int *flags1);
|
||||
int MXC_I2C_GetFlags(mxc_i2c_regs_t *i2c, unsigned int *flags0, unsigned int *flags1);
|
||||
|
||||
/**
|
||||
* @brief Clears the Interrupt Flags.
|
||||
|
|
@ -495,7 +491,7 @@ int MXC_I2C_GetFlags (mxc_i2c_regs_t* i2c, unsigned int *flags0, unsigned int *f
|
|||
* @param flags0 Flags to clear in the intfl0 interrupt register.
|
||||
* @param flags1 Flags to clear in the intfl1 interrupt register.
|
||||
*/
|
||||
void MXC_I2C_ClearFlags (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1);
|
||||
void MXC_I2C_ClearFlags(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1);
|
||||
|
||||
/**
|
||||
* @brief Enable Interrupts.
|
||||
|
|
@ -504,7 +500,7 @@ void MXC_I2C_ClearFlags (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int
|
|||
* @param flags0 Interrupts to be enabled in int->en0
|
||||
* @param flags1 Interrupts to be enabled in int->en1
|
||||
*/
|
||||
void MXC_I2C_EnableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1);
|
||||
void MXC_I2C_EnableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1);
|
||||
|
||||
/**
|
||||
* @brief Disable Interrupts.
|
||||
|
|
@ -513,7 +509,7 @@ void MXC_I2C_EnableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int f
|
|||
* @param flags0 Interrupts to be disabled in int->en0
|
||||
* @param flags1 Interrupts to be disabled in int->en1
|
||||
*/
|
||||
void MXC_I2C_DisableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1);
|
||||
void MXC_I2C_DisableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1);
|
||||
|
||||
/**
|
||||
* @brief Enables the slave preload mode
|
||||
|
|
@ -523,28 +519,28 @@ void MXC_I2C_DisableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int
|
|||
*
|
||||
* @param i2c Pointer to I2C registers (selects the I2C block used.)
|
||||
*/
|
||||
void MXC_I2C_EnablePreload (mxc_i2c_regs_t* i2c);
|
||||
void MXC_I2C_EnablePreload(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief Disable the slave preload mode
|
||||
*
|
||||
* @param i2c Pointer to I2C registers (selects the I2C block used.)
|
||||
*/
|
||||
void MXC_I2C_DisablePreload (mxc_i2c_regs_t* i2c);
|
||||
void MXC_I2C_DisablePreload(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief Enables the slave to respond to the general call address
|
||||
*
|
||||
* @param i2c Pointer to I2C registers (selects the I2C block used.)
|
||||
*/
|
||||
void MXC_I2C_EnableGeneralCall (mxc_i2c_regs_t* i2c);
|
||||
void MXC_I2C_EnableGeneralCall(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief Prevents the slave from responding to the general call address
|
||||
*
|
||||
* @param i2c Pointer to I2C registers (selects the I2C block used.)
|
||||
*/
|
||||
void MXC_I2C_DisableGeneralCall (mxc_i2c_regs_t* i2c);
|
||||
void MXC_I2C_DisableGeneralCall(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief Set the I2C Timeout
|
||||
|
|
@ -558,7 +554,7 @@ void MXC_I2C_DisableGeneralCall (mxc_i2c_regs_t* i2c);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
void MXC_I2C_SetTimeout (mxc_i2c_regs_t* i2c, unsigned int timeout);
|
||||
void MXC_I2C_SetTimeout(mxc_i2c_regs_t *i2c, unsigned int timeout);
|
||||
|
||||
/**
|
||||
* @brief Get the current I2C timeout
|
||||
|
|
@ -567,7 +563,7 @@ void MXC_I2C_SetTimeout (mxc_i2c_regs_t* i2c, unsigned int timeout);
|
|||
*
|
||||
* @return The current timeout in uS
|
||||
*/
|
||||
unsigned int MXC_I2C_GetTimeout (mxc_i2c_regs_t* i2c);
|
||||
unsigned int MXC_I2C_GetTimeout(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief Attempts to recover the I2C bus, ensuring the I2C lines are idle.
|
||||
|
|
@ -593,7 +589,7 @@ unsigned int MXC_I2C_GetTimeout (mxc_i2c_regs_t* i2c);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_I2C_Recover (mxc_i2c_regs_t* i2c, unsigned int retries);
|
||||
int MXC_I2C_Recover(mxc_i2c_regs_t *i2c, unsigned int retries);
|
||||
|
||||
/* ************************************************************************* */
|
||||
/* Transaction level functions */
|
||||
|
|
@ -620,7 +616,7 @@ int MXC_I2C_Recover (mxc_i2c_regs_t* i2c, unsigned int retries);
|
|||
* acknowledged, negative if error. See \ref MXC_Error_Codes for the
|
||||
* list of error return codes.
|
||||
*/
|
||||
int MXC_I2C_MasterTransaction (mxc_i2c_req_t* req);
|
||||
int MXC_I2C_MasterTransaction(mxc_i2c_req_t *req);
|
||||
|
||||
/**
|
||||
* @brief Performs a non-blocking I2C Master transaction.
|
||||
|
|
@ -647,7 +643,7 @@ int MXC_I2C_MasterTransaction (mxc_i2c_req_t* req);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_I2C_MasterTransactionAsync (mxc_i2c_req_t* req);
|
||||
int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t *req);
|
||||
|
||||
/**
|
||||
* @brief Performs a non-blocking I2C Master transaction using DMA for reduced time
|
||||
|
|
@ -675,7 +671,7 @@ int MXC_I2C_MasterTransactionAsync (mxc_i2c_req_t* req);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_I2C_MasterTransactionDMA (mxc_i2c_req_t* req);
|
||||
int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t *req);
|
||||
|
||||
/**
|
||||
* @brief Performs a blocking I2C Slave transaction.
|
||||
|
|
@ -715,7 +711,7 @@ int MXC_I2C_MasterTransactionDMA (mxc_i2c_req_t* req);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_I2C_SlaveTransaction (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback);
|
||||
int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback);
|
||||
|
||||
/**
|
||||
* @brief Performs a non-blocking I2C Slave transaction.
|
||||
|
|
@ -758,7 +754,7 @@ int MXC_I2C_SlaveTransaction (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callb
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_I2C_SlaveTransactionAsync (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback);
|
||||
int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback);
|
||||
|
||||
/**
|
||||
* @brief Set the receive threshold level.
|
||||
|
|
@ -781,7 +777,7 @@ int MXC_I2C_SlaveTransactionAsync (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_I2C_SetRXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes);
|
||||
int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes);
|
||||
|
||||
/**
|
||||
* @brief Get the current receive threshold level.
|
||||
|
|
@ -790,7 +786,7 @@ int MXC_I2C_SetRXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes);
|
|||
*
|
||||
* @return The receive threshold value (in bytes).
|
||||
*/
|
||||
unsigned int MXC_I2C_GetRXThreshold (mxc_i2c_regs_t* i2c);
|
||||
unsigned int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief Set the transmit threshold level.
|
||||
|
|
@ -814,7 +810,7 @@ unsigned int MXC_I2C_GetRXThreshold (mxc_i2c_regs_t* i2c);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_I2C_SetTXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes);
|
||||
int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes);
|
||||
|
||||
/**
|
||||
* @brief Get the current transmit threshold level.
|
||||
|
|
@ -823,7 +819,17 @@ int MXC_I2C_SetTXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes);
|
|||
*
|
||||
* @return The transmit threshold value (in bytes).
|
||||
*/
|
||||
unsigned int MXC_I2C_GetTXThreshold (mxc_i2c_regs_t* i2c);
|
||||
unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief Stop any asynchronous requests in progress.
|
||||
*
|
||||
* Stop any asynchronous requests in progress. Any callbacks associated with
|
||||
* the active transaction will be NOT executed.
|
||||
*
|
||||
* @param i2c Pointer to I2C registers (selects the I2C block used.)
|
||||
*/
|
||||
void MXC_I2C_AsyncStop(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief Abort any asynchronous requests in progress.
|
||||
|
|
@ -834,7 +840,7 @@ unsigned int MXC_I2C_GetTXThreshold (mxc_i2c_regs_t* i2c);
|
|||
*
|
||||
* @param i2c Pointer to I2C registers (selects the I2C block used.)
|
||||
*/
|
||||
void MXC_I2C_AbortAsync (mxc_i2c_regs_t* i2c);
|
||||
void MXC_I2C_AbortAsync(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief The processing function for asynchronous transactions.
|
||||
|
|
@ -845,7 +851,7 @@ void MXC_I2C_AbortAsync (mxc_i2c_regs_t* i2c);
|
|||
*
|
||||
* @param i2c Pointer to I2C registers (selects the I2C block used.)
|
||||
*/
|
||||
void MXC_I2C_AsyncHandler (mxc_i2c_regs_t* i2c);
|
||||
void MXC_I2C_AsyncHandler(mxc_i2c_regs_t *i2c);
|
||||
|
||||
/**
|
||||
* @brief The processing function for DMA transactions.
|
||||
|
|
@ -856,14 +862,12 @@ void MXC_I2C_AsyncHandler (mxc_i2c_regs_t* i2c);
|
|||
* @param ch DMA channel
|
||||
* @param error Error status
|
||||
*/
|
||||
void MXC_I2C_DMACallback (int ch, int error);
|
||||
|
||||
void MXC_I2C_DMACallback(int ch, int error);
|
||||
|
||||
/**@} end of group i2c */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_I2C_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_I2C_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Exclusive access lock utility functions.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,16 +34,11 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_LOCK_H_
|
||||
#define _MXC_LOCK_H_
|
||||
|
||||
// To enable disable this module
|
||||
#define USE_LOCK_IN_DRIVERS 0
|
||||
|
||||
#if USE_LOCK_IN_DRIVERS
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_LOCK_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_LOCK_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_device.h"
|
||||
|
|
@ -78,14 +73,14 @@ extern "C" {
|
|||
*
|
||||
* @return #E_NO_ERROR if everything successful, #E_BUSY if lock is taken.
|
||||
*/
|
||||
int MXC_GetLock (uint32_t *lock, uint32_t value);
|
||||
int MXC_GetLock(uint32_t *lock, uint32_t value);
|
||||
|
||||
/**
|
||||
* @brief Free the given lock.
|
||||
* @param[in,out] lock Pointer to the variable used for the lock. When the lock
|
||||
* is free, the value pointed to by @p lock is set to zero.
|
||||
*/
|
||||
void MXC_FreeLock (uint32_t *lock);
|
||||
void MXC_FreeLock(uint32_t *lock);
|
||||
|
||||
/**@} end of group mxc_lock_utilities */
|
||||
|
||||
|
|
@ -93,12 +88,4 @@ void MXC_FreeLock (uint32_t *lock);
|
|||
}
|
||||
#endif
|
||||
|
||||
|
||||
#else // USE_LOCK_IN_DRIVERS
|
||||
|
||||
#define MXC_GetLock(x, y) E_NO_ERROR
|
||||
#define MXC_FreeLock(x)
|
||||
|
||||
#endif // USE_LOCK_IN_DRIVERS
|
||||
|
||||
#endif /* _MXC_LOCK_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_LOCK_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief This file contains constant pin configurations for the peripherals.
|
||||
*/
|
||||
|
||||
/* *****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,21 +34,16 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef _MXC_PINS_H_
|
||||
#define _MXC_PINS_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_PINS_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_PINS_H_
|
||||
|
||||
#include "gpio.h"
|
||||
|
||||
/***** Global Variables *****/
|
||||
|
||||
typedef enum {
|
||||
MAP_A,
|
||||
MAP_B,
|
||||
MAP_C
|
||||
} sys_map_t;
|
||||
typedef enum { MAP_A, MAP_B, MAP_C } sys_map_t;
|
||||
|
||||
// Predefined GPIO Configurations
|
||||
extern const mxc_gpio_cfg_t gpio_cfg_swda;
|
||||
|
|
@ -57,7 +52,6 @@ extern const mxc_gpio_cfg_t gpio_cfg_swdb;
|
|||
extern const mxc_gpio_cfg_t gpio_cfg_i2c0;
|
||||
extern const mxc_gpio_cfg_t gpio_cfg_i2c1;
|
||||
|
||||
|
||||
extern const mxc_gpio_cfg_t gpio_cfg_uart0;
|
||||
extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow;
|
||||
extern const mxc_gpio_cfg_t gpio_cfg_uart1a;
|
||||
|
|
@ -65,13 +59,9 @@ extern const mxc_gpio_cfg_t gpio_cfg_uart1b;
|
|||
extern const mxc_gpio_cfg_t gpio_cfg_uart1c;
|
||||
extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow;
|
||||
|
||||
|
||||
extern const mxc_gpio_cfg_t gpio_cfg_spi0;
|
||||
extern const mxc_gpio_cfg_t gpio_cfg_spi0_ss;
|
||||
extern const mxc_gpio_cfg_t gpio_cfg_spi1a;
|
||||
extern const mxc_gpio_cfg_t gpio_cfg_spi1a_ss;
|
||||
extern const mxc_gpio_cfg_t gpio_cfg_spi1b;
|
||||
extern const mxc_gpio_cfg_t gpio_cfg_spi1b_ss;
|
||||
|
||||
// Timers are only defined once, depending on package, each timer could be mapped to other pins
|
||||
extern const mxc_gpio_cfg_t gpio_cfg_tmr0;
|
||||
|
|
@ -80,6 +70,4 @@ extern const mxc_gpio_cfg_t gpio_cfg_32kcal;
|
|||
extern const mxc_gpio_cfg_t gpio_cfg_i2s0a;
|
||||
extern const mxc_gpio_cfg_t gpio_cfg_i2s0b;
|
||||
|
||||
|
||||
#endif /* _MXC_PINS_H_ */
|
||||
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_PINS_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Serial Peripheral Interface (SPI) communications driver.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,9 +34,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
#ifndef _SPI_H_
|
||||
#define _SPI_H_
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPI_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPI_H_
|
||||
|
||||
/***** includes *******/
|
||||
#include "spi_regs.h"
|
||||
|
|
@ -46,6 +47,9 @@
|
|||
#include "mxc_pins.h"
|
||||
#include "mxc_lock.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***** Definitions *****/
|
||||
|
||||
|
|
@ -76,10 +80,10 @@
|
|||
*
|
||||
*/
|
||||
typedef enum {
|
||||
SPI_WIDTH_3WIRE, ///< 1 Data line, half duplex
|
||||
SPI_WIDTH_STANDARD, ///< MISO/MOSI, full duplex
|
||||
SPI_WIDTH_DUAL, ///< 2 Data lines, half duplex
|
||||
SPI_WIDTH_QUAD, ///< 4 Data lines, half duplex
|
||||
SPI_WIDTH_3WIRE, ///< 1 Data line, half duplex
|
||||
SPI_WIDTH_STANDARD, ///< MISO/MOSI, full duplex
|
||||
SPI_WIDTH_DUAL, ///< 2 Data lines, half duplex
|
||||
SPI_WIDTH_QUAD, ///< 4 Data lines, half duplex
|
||||
} mxc_spi_width_t;
|
||||
|
||||
/**
|
||||
|
|
@ -94,10 +98,10 @@ typedef enum {
|
|||
*
|
||||
*/
|
||||
typedef enum {
|
||||
SPI_MODE_0, ///< clock phase = 0, clock polarity = 0
|
||||
SPI_MODE_1, ///< clock phase = 0, clock polarity = 1
|
||||
SPI_MODE_2, ///< clock phase = 1, clock polarity = 0
|
||||
SPI_MODE_3, ///< clock phase = 1, clock polarity = 1
|
||||
SPI_MODE_0, ///< clock phase = 0, clock polarity = 0
|
||||
SPI_MODE_1, ///< clock phase = 0, clock polarity = 1
|
||||
SPI_MODE_2, ///< clock phase = 1, clock polarity = 0
|
||||
SPI_MODE_3, ///< clock phase = 1, clock polarity = 1
|
||||
} mxc_spi_mode_t;
|
||||
|
||||
typedef struct _mxc_spi_req_t mxc_spi_req_t;
|
||||
|
|
@ -108,7 +112,7 @@ typedef struct _mxc_spi_req_t mxc_spi_req_t;
|
|||
* @param req The details of the transaction.
|
||||
* @param result See \ref MXC_Error_Codes for the list of error codes.
|
||||
*/
|
||||
typedef void (*spi_complete_cb_t) (void * req, int result);
|
||||
typedef void (*spi_complete_cb_t)(void *req, int result);
|
||||
|
||||
/**
|
||||
* @brief The information required to perform a complete SPI transaction
|
||||
|
|
@ -117,23 +121,23 @@ typedef void (*spi_complete_cb_t) (void * req, int result);
|
|||
* @param "completeCB" only needs to be initialized for interrupt driven (Async) and DMA transactions.
|
||||
*/
|
||||
struct _mxc_spi_req_t {
|
||||
mxc_spi_regs_t* spi; ///<Point to SPI registers
|
||||
int ssIdx; ///< Slave select line to use (Master only, ignored in slave mode)
|
||||
int ssDeassert; ///< 1 - Deassert SS at end of transaction, 0 - leave SS asserted
|
||||
uint8_t *txData; ///< Buffer containing transmit data. For character sizes
|
||||
mxc_spi_regs_t *spi; ///<Point to SPI registers
|
||||
int ssIdx; ///< Slave select line to use (Master only, ignored in slave mode)
|
||||
int ssDeassert; ///< 1 - Deassert SS at end of transaction, 0 - leave SS asserted
|
||||
uint8_t *txData; ///< Buffer containing transmit data. For character sizes
|
||||
///< < 8 bits, pad the MSB of each byte with zeros. For
|
||||
///< character sizes > 8 bits, use two bytes per character
|
||||
///< and pad the MSB of the upper byte with zeros
|
||||
uint8_t *rxData; ///< Buffer to store received data For character sizes
|
||||
uint8_t *rxData; ///< Buffer to store received data For character sizes
|
||||
///< < 8 bits, pad the MSB of each byte with zeros. For
|
||||
///< character sizes > 8 bits, use two bytes per character
|
||||
///< and pad the MSB of the upper byte with zeros
|
||||
uint32_t txLen; ///< Number of bytes to be sent from txData
|
||||
uint32_t rxLen; ///< Number of bytes to be stored in rxData
|
||||
uint32_t txCnt; ///< Number of bytes actually transmitted from txData
|
||||
uint32_t rxCnt; ///< Number of bytes stored in rxData
|
||||
uint32_t txLen; ///< Number of bytes to be sent from txData
|
||||
uint32_t rxLen; ///< Number of bytes to be stored in rxData
|
||||
uint32_t txCnt; ///< Number of bytes actually transmitted from txData
|
||||
uint32_t rxCnt; ///< Number of bytes stored in rxData
|
||||
|
||||
spi_complete_cb_t completeCB; ///< Pointer to function called when transaction is complete
|
||||
spi_complete_cb_t completeCB; ///< Pointer to function called when transaction is complete
|
||||
};
|
||||
|
||||
/* ************************************************************************* */
|
||||
|
|
@ -165,15 +169,12 @@ struct _mxc_spi_req_t {
|
|||
* @param hz The requested clock frequency. The actual clock frequency
|
||||
* will be returned by the function if successful. Used in
|
||||
* master mode only.
|
||||
* @param drv_ssel Hardware block able to drive SS pin, or it can be leaved as it is
|
||||
* To upper layer firmware drive it.
|
||||
* 1:Driver will drive SS pin, 0:Driver will NOT drive it
|
||||
*
|
||||
* @return If successful, the actual clock frequency is returned. Otherwise, see
|
||||
* \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_SPI_Init (mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves,
|
||||
unsigned ssPolarity, unsigned int hz, unsigned drv_ssel);
|
||||
int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves,
|
||||
unsigned ssPolarity, unsigned int hz);
|
||||
|
||||
/**
|
||||
* @brief Disable and shutdown SPI peripheral.
|
||||
|
|
@ -182,7 +183,7 @@ int MXC_SPI_Init (mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int num
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_SPI_Shutdown (mxc_spi_regs_t* spi);
|
||||
int MXC_SPI_Shutdown(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Checks if the given SPI bus can be placed in sleep mode.
|
||||
|
|
@ -196,7 +197,16 @@ int MXC_SPI_Shutdown (mxc_spi_regs_t* spi);
|
|||
* @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref
|
||||
* MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_SPI_ReadyForSleep (mxc_spi_regs_t* spi);
|
||||
int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Returns the frequency of the clock used as the bit rate generator for a given SPI instance.
|
||||
*
|
||||
* @param spi Pointer to SPI registers (selects the SPI block used.)
|
||||
*
|
||||
* @return Frequency of the clock used as the bit rate generator
|
||||
*/
|
||||
int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Set the frequency of the SPI interface.
|
||||
|
|
@ -209,9 +219,7 @@ int MXC_SPI_ReadyForSleep (mxc_spi_regs_t* spi);
|
|||
* @return Negative if error, otherwise actual speed set. See \ref
|
||||
* MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_SPI_SetFrequency (mxc_spi_regs_t* spi, unsigned int hz);
|
||||
|
||||
int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi);
|
||||
int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz);
|
||||
|
||||
/**
|
||||
* @brief Get the frequency of the SPI interface.
|
||||
|
|
@ -222,7 +230,7 @@ int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi);
|
|||
*
|
||||
* @return The SPI bus frequency in Hertz
|
||||
*/
|
||||
unsigned int MXC_SPI_GetFrequency (mxc_spi_regs_t* spi);
|
||||
unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Sets the number of bits per character
|
||||
|
|
@ -232,7 +240,7 @@ unsigned int MXC_SPI_GetFrequency (mxc_spi_regs_t* spi);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_SPI_SetDataSize (mxc_spi_regs_t* spi, int dataSize);
|
||||
int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize);
|
||||
|
||||
/**
|
||||
* @brief Gets the number of bits per character
|
||||
|
|
@ -241,8 +249,7 @@ int MXC_SPI_SetDataSize (mxc_spi_regs_t* spi, int dataSize);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_SPI_GetDataSize (mxc_spi_regs_t* spi);
|
||||
|
||||
int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi);
|
||||
|
||||
/* ************************************************************************* */
|
||||
/* Low-level functions */
|
||||
|
|
@ -258,7 +265,7 @@ int MXC_SPI_GetDataSize (mxc_spi_regs_t* spi);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_SPI_SetSlave (mxc_spi_regs_t* spi, int ssIdx);
|
||||
int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx);
|
||||
|
||||
/**
|
||||
* @brief Gets the slave select (SS) line used for transmissions
|
||||
|
|
@ -269,7 +276,7 @@ int MXC_SPI_SetSlave (mxc_spi_regs_t* spi, int ssIdx);
|
|||
*
|
||||
* @return slave slect
|
||||
*/
|
||||
int MXC_SPI_GetSlave (mxc_spi_regs_t* spi);
|
||||
int MXC_SPI_GetSlave(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Sets the SPI width used for transmissions
|
||||
|
|
@ -279,7 +286,7 @@ int MXC_SPI_GetSlave (mxc_spi_regs_t* spi);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_SPI_SetWidth (mxc_spi_regs_t* spi, mxc_spi_width_t spiWidth);
|
||||
int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth);
|
||||
|
||||
/**
|
||||
* @brief Gets the SPI width used for transmissions
|
||||
|
|
@ -288,7 +295,7 @@ int MXC_SPI_SetWidth (mxc_spi_regs_t* spi, mxc_spi_width_t spiWidth);
|
|||
*
|
||||
* @return Spi Width \ref mxc_spi_width_t
|
||||
*/
|
||||
mxc_spi_width_t MXC_SPI_GetWidth (mxc_spi_regs_t* spi);
|
||||
mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Sets the spi mode using clock polarity and clock phase
|
||||
|
|
@ -298,7 +305,7 @@ mxc_spi_width_t MXC_SPI_GetWidth (mxc_spi_regs_t* spi);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_SPI_SetMode (mxc_spi_regs_t* spi, mxc_spi_mode_t spiMode);
|
||||
int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode);
|
||||
|
||||
/**
|
||||
* @brief Gets the spi mode
|
||||
|
|
@ -307,7 +314,7 @@ int MXC_SPI_SetMode (mxc_spi_regs_t* spi, mxc_spi_mode_t spiMode);
|
|||
*
|
||||
* @return mxc_spi_mode_t \ref mxc_spi_mode_t
|
||||
*/
|
||||
mxc_spi_mode_t MXC_SPI_GetMode (mxc_spi_regs_t* spi);
|
||||
mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Starts a SPI Transmission
|
||||
|
|
@ -321,7 +328,7 @@ mxc_spi_mode_t MXC_SPI_GetMode (mxc_spi_regs_t* spi);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_SPI_StartTransmission (mxc_spi_regs_t* spi);
|
||||
int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Checks the SPI Peripheral for an ongoing transmission
|
||||
|
|
@ -332,7 +339,7 @@ int MXC_SPI_StartTransmission (mxc_spi_regs_t* spi);
|
|||
*
|
||||
* @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_SPI_GetActive (mxc_spi_regs_t* spi);
|
||||
int MXC_SPI_GetActive(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Aborts an ongoing SPI Transmission
|
||||
|
|
@ -343,7 +350,7 @@ int MXC_SPI_GetActive (mxc_spi_regs_t* spi);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_SPI_AbortTransmission (mxc_spi_regs_t* spi);
|
||||
int MXC_SPI_AbortTransmission(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Unloads bytes from the receive FIFO.
|
||||
|
|
@ -354,8 +361,7 @@ int MXC_SPI_AbortTransmission (mxc_spi_regs_t* spi);
|
|||
*
|
||||
* @return The number of bytes actually read.
|
||||
*/
|
||||
unsigned int MXC_SPI_ReadRXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes,
|
||||
unsigned int len);
|
||||
unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len);
|
||||
|
||||
/**
|
||||
* @brief Get the number of bytes currently available in the receive FIFO.
|
||||
|
|
@ -364,7 +370,7 @@ unsigned int MXC_SPI_ReadRXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes,
|
|||
*
|
||||
* @return The number of bytes available.
|
||||
*/
|
||||
unsigned int MXC_SPI_GetRXFIFOAvailable (mxc_spi_regs_t* spi);
|
||||
unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Loads bytes into the transmit FIFO.
|
||||
|
|
@ -375,8 +381,7 @@ unsigned int MXC_SPI_GetRXFIFOAvailable (mxc_spi_regs_t* spi);
|
|||
*
|
||||
* @return The number of bytes actually written.
|
||||
*/
|
||||
unsigned int MXC_SPI_WriteTXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes,
|
||||
unsigned int len);
|
||||
unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len);
|
||||
|
||||
/**
|
||||
* @brief Get the amount of free space available in the transmit FIFO.
|
||||
|
|
@ -385,21 +390,21 @@ unsigned int MXC_SPI_WriteTXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes,
|
|||
*
|
||||
* @return The number of bytes available.
|
||||
*/
|
||||
unsigned int MXC_SPI_GetTXFIFOAvailable (mxc_spi_regs_t* spi);
|
||||
unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Removes and discards all bytes currently in the receive FIFO.
|
||||
*
|
||||
* @param spi Pointer to SPI registers (selects the SPI block used.)
|
||||
*/
|
||||
void MXC_SPI_ClearRXFIFO (mxc_spi_regs_t* spi);
|
||||
void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Removes and discards all bytes currently in the transmit FIFO.
|
||||
*
|
||||
* @param spi Pointer to SPI registers (selects the SPI block used.)
|
||||
*/
|
||||
void MXC_SPI_ClearTXFIFO (mxc_spi_regs_t* spi);
|
||||
void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Set the receive threshold level.
|
||||
|
|
@ -418,7 +423,7 @@ void MXC_SPI_ClearTXFIFO (mxc_spi_regs_t* spi);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_SPI_SetRXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes);
|
||||
int MXC_SPI_SetRXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes);
|
||||
|
||||
/**
|
||||
* @brief Get the current receive threshold level.
|
||||
|
|
@ -427,7 +432,7 @@ int MXC_SPI_SetRXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes);
|
|||
*
|
||||
* @return The receive threshold value (in bytes).
|
||||
*/
|
||||
unsigned int MXC_SPI_GetRXThreshold (mxc_spi_regs_t* spi);
|
||||
unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Set the transmit threshold level.
|
||||
|
|
@ -446,7 +451,7 @@ unsigned int MXC_SPI_GetRXThreshold (mxc_spi_regs_t* spi);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_SPI_SetTXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes);
|
||||
int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes);
|
||||
|
||||
/**
|
||||
* @brief Get the current transmit threshold level.
|
||||
|
|
@ -455,7 +460,7 @@ int MXC_SPI_SetTXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes);
|
|||
*
|
||||
* @return The transmit threshold value (in bytes).
|
||||
*/
|
||||
unsigned int MXC_SPI_GetTXThreshold (mxc_spi_regs_t* spi);
|
||||
unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Gets the interrupt flags that are currently set
|
||||
|
|
@ -467,7 +472,7 @@ unsigned int MXC_SPI_GetTXThreshold (mxc_spi_regs_t* spi);
|
|||
*
|
||||
* @return The interrupt flags
|
||||
*/
|
||||
unsigned int MXC_SPI_GetFlags (mxc_spi_regs_t* spi);
|
||||
unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Clears the interrupt flags that are currently set
|
||||
|
|
@ -477,7 +482,7 @@ unsigned int MXC_SPI_GetFlags (mxc_spi_regs_t* spi);
|
|||
*
|
||||
* @param spi Pointer to SPI registers (selects the SPI block used.)
|
||||
*/
|
||||
void MXC_SPI_ClearFlags (mxc_spi_regs_t* spi);
|
||||
void MXC_SPI_ClearFlags(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief Enables specific interrupts
|
||||
|
|
@ -488,7 +493,7 @@ void MXC_SPI_ClearFlags (mxc_spi_regs_t* spi);
|
|||
* @param spi Pointer to SPI registers (selects the SPI block used.)
|
||||
* @param mask The interrupts to be enabled
|
||||
*/
|
||||
void MXC_SPI_EnableInt (mxc_spi_regs_t* spi, unsigned int mask);
|
||||
void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int mask);
|
||||
|
||||
/**
|
||||
* @brief Disables specific interrupts
|
||||
|
|
@ -499,7 +504,7 @@ void MXC_SPI_EnableInt (mxc_spi_regs_t* spi, unsigned int mask);
|
|||
* @param spi Pointer to SPI registers (selects the SPI block used.)
|
||||
* @param mask The interrupts to be disabled
|
||||
*/
|
||||
void MXC_SPI_DisableInt (mxc_spi_regs_t* spi, unsigned int mask);
|
||||
void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int mask);
|
||||
|
||||
/* ************************************************************************* */
|
||||
/* Transaction level functions */
|
||||
|
|
@ -528,7 +533,7 @@ void MXC_SPI_DisableInt (mxc_spi_regs_t* spi, unsigned int mask);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_SPI_MasterTransaction (mxc_spi_req_t* req);
|
||||
int MXC_SPI_MasterTransaction(mxc_spi_req_t *req);
|
||||
|
||||
/**
|
||||
* @brief Setup an interrupt-driven SPI transaction
|
||||
|
|
@ -540,7 +545,7 @@ int MXC_SPI_MasterTransaction (mxc_spi_req_t* req);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_SPI_MasterTransactionAsync (mxc_spi_req_t* req);
|
||||
int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req);
|
||||
|
||||
/**
|
||||
* @brief Setup a DMA driven SPI transaction
|
||||
|
|
@ -557,7 +562,7 @@ int MXC_SPI_MasterTransactionAsync (mxc_spi_req_t* req);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_SPI_MasterTransactionDMA (mxc_spi_req_t* req);
|
||||
int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req);
|
||||
|
||||
/**
|
||||
* @brief Performs a blocking SPI transaction.
|
||||
|
|
@ -574,7 +579,7 @@ int MXC_SPI_MasterTransactionDMA (mxc_spi_req_t* req);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_SPI_SlaveTransaction (mxc_spi_req_t* req);
|
||||
int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req);
|
||||
|
||||
/**
|
||||
* @brief Setup an interrupt-driven SPI transaction
|
||||
|
|
@ -586,7 +591,7 @@ int MXC_SPI_SlaveTransaction (mxc_spi_req_t* req);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_SPI_SlaveTransactionAsync (mxc_spi_req_t* req);
|
||||
int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req);
|
||||
|
||||
/**
|
||||
* @brief Setup a DMA driven SPI transaction
|
||||
|
|
@ -603,7 +608,7 @@ int MXC_SPI_SlaveTransactionAsync (mxc_spi_req_t* req);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_SPI_SlaveTransactionDMA (mxc_spi_req_t* req);
|
||||
int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req);
|
||||
|
||||
/**
|
||||
* @brief Sets the TX data to transmit as a 'dummy' byte
|
||||
|
|
@ -616,7 +621,7 @@ int MXC_SPI_SlaveTransactionDMA (mxc_spi_req_t* req);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_SPI_SetDefaultTXData (mxc_spi_regs_t* spi, unsigned int defaultTXData);
|
||||
int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData);
|
||||
|
||||
/**
|
||||
* @brief Abort any asynchronous requests in progress.
|
||||
|
|
@ -627,7 +632,7 @@ int MXC_SPI_SetDefaultTXData (mxc_spi_regs_t* spi, unsigned int defaultTXData);
|
|||
*
|
||||
* @param spi Pointer to SPI registers (selects the SPI block used.)
|
||||
*/
|
||||
void MXC_SPI_AbortAsync (mxc_spi_regs_t* spi);
|
||||
void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi);
|
||||
|
||||
/**
|
||||
* @brief The processing function for asynchronous transactions.
|
||||
|
|
@ -638,11 +643,11 @@ void MXC_SPI_AbortAsync (mxc_spi_regs_t* spi);
|
|||
*
|
||||
* @param spi Pointer to SPI registers (selects the SPI block used.)
|
||||
*/
|
||||
void MXC_SPI_AsyncHandler (mxc_spi_regs_t* spi);
|
||||
void MXC_SPI_AsyncHandler(mxc_spi_regs_t *spi);
|
||||
/**@} end of group spi */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _PT_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPI_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief System level header file.
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -36,8 +36,8 @@
|
|||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _MXC_MXC_SYS_H_
|
||||
#define _MXC_MXC_SYS_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_SYS_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_SYS_H_
|
||||
|
||||
#include "mxc_device.h"
|
||||
#include "gcr_regs.h"
|
||||
|
|
@ -46,79 +46,211 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup mxc_sys System Configuration (MXC_SYS)
|
||||
* @ingroup syscfg
|
||||
* @details API for system configuration including clock source selection and entering critical sections of code.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief System reset0 and reset1 enumeration. Used in MXC_SYS_PeriphReset0 function */
|
||||
typedef enum {
|
||||
MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */
|
||||
MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, /**< Reset WDT */
|
||||
MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */
|
||||
MXC_SYS_RESET0_TIMER0 = MXC_F_GCR_RST0_TIMER0_POS, /**< Reset TIMER0 */
|
||||
MXC_SYS_RESET0_TIMER1 = MXC_F_GCR_RST0_TIMER1_POS, /**< Reset TIMER1 */
|
||||
MXC_SYS_RESET0_TIMER2 = MXC_F_GCR_RST0_TIMER2_POS, /**< Reset TIMER2 */
|
||||
MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, /**< Reset UART0 */
|
||||
MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, /**< Reset UART1 */
|
||||
MXC_SYS_RESET0_SPI0 = MXC_F_GCR_RST0_SPI0_POS, /**< Reset SPI0 */
|
||||
MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */
|
||||
MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */
|
||||
MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */
|
||||
MXC_SYS_RESET0_SRST = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */
|
||||
MXC_SYS_RESET0_PRST = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */
|
||||
MXC_SYS_RESET0_SYSTEM = MXC_F_GCR_RST0_SYSTEM_POS, /**< System reset */
|
||||
MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */
|
||||
MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, /**< Reset WDT */
|
||||
MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */
|
||||
MXC_SYS_RESET0_TIMER0 = MXC_F_GCR_RST0_TIMER0_POS, /**< Reset TIMER0 */
|
||||
MXC_SYS_RESET0_TIMER1 = MXC_F_GCR_RST0_TIMER1_POS, /**< Reset TIMER1 */
|
||||
MXC_SYS_RESET0_TIMER2 = MXC_F_GCR_RST0_TIMER2_POS, /**< Reset TIMER2 */
|
||||
MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, /**< Reset UART0 */
|
||||
MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, /**< Reset UART1 */
|
||||
MXC_SYS_RESET0_SPI0 = MXC_F_GCR_RST0_SPI0_POS, /**< Reset SPI0 */
|
||||
MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */
|
||||
MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */
|
||||
MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */
|
||||
MXC_SYS_RESET0_SRST = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */
|
||||
MXC_SYS_RESET0_PRST = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */
|
||||
MXC_SYS_RESET0_SYSTEM = MXC_F_GCR_RST0_SYSTEM_POS, /**< System reset */
|
||||
/* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */
|
||||
MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */
|
||||
MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */
|
||||
} mxc_sys_reset_t;
|
||||
|
||||
/** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */
|
||||
typedef enum {
|
||||
MXC_SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PCLK_DIS0_GPIO0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PCLK_DIS0_DMAD_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */
|
||||
MXC_SYS_PERIPH_CLOCK_SPI0 = MXC_F_GCR_PCLK_DIS0_SPI0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI0 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_SPI1 = MXC_F_GCR_PCLK_DIS0_SPI1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PCLK_DIS0_UART0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PCLK_DIS0_UART1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PCLK_DIS0_I2C0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_TMR0 = MXC_F_GCR_PCLK_DIS0_TIMER0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T0 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_TMR1 = MXC_F_GCR_PCLK_DIS0_TIMER1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T1 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_TMR2 = MXC_F_GCR_PCLK_DIS0_TIMER2D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T2 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PCLK_DIS0_I2C1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_GPIO0 =
|
||||
MXC_F_GCR_PCLK_DIS0_GPIO0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_DMA =
|
||||
MXC_F_GCR_PCLK_DIS0_DMAD_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */
|
||||
MXC_SYS_PERIPH_CLOCK_SPI0 =
|
||||
MXC_F_GCR_PCLK_DIS0_SPI0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI0 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_SPI1 =
|
||||
MXC_F_GCR_PCLK_DIS0_SPI1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_UART0 =
|
||||
MXC_F_GCR_PCLK_DIS0_UART0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_UART1 =
|
||||
MXC_F_GCR_PCLK_DIS0_UART1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_I2C0 =
|
||||
MXC_F_GCR_PCLK_DIS0_I2C0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_TMR0 =
|
||||
MXC_F_GCR_PCLK_DIS0_TIMER0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T0 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_TMR1 =
|
||||
MXC_F_GCR_PCLK_DIS0_TIMER1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T1 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_TMR2 =
|
||||
MXC_F_GCR_PCLK_DIS0_TIMER2D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T2 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_I2C1 =
|
||||
MXC_F_GCR_PCLK_DIS0_I2C1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */
|
||||
/* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */
|
||||
MXC_SYS_PERIPH_CLOCK_FLCD = (MXC_F_GCR_PCLK_DIS1_FLCD_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT1 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_ICACHE = (MXC_F_GCR_PCLK_DIS1_ICCD_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */
|
||||
MXC_SYS_PERIPH_CLOCK_FLCD =
|
||||
(MXC_F_GCR_PCLK_DIS1_FLCD_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT1 clock */
|
||||
MXC_SYS_PERIPH_CLOCK_ICACHE =
|
||||
(MXC_F_GCR_PCLK_DIS1_ICCD_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */
|
||||
} mxc_sys_periph_clock_t;
|
||||
|
||||
/** @brief Enumeration to select System Clock source */
|
||||
typedef enum {
|
||||
MXC_SYS_CLOCK_NANORING = MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING, /**< 8KHz nanoring on MAX32660 */
|
||||
MXC_SYS_CLOCK_HFXIN = MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN, /**< 32KHz on MAX32660 */
|
||||
MXC_SYS_CLOCK_HFXIN_DIGITAL = 0x9, /**< External Clock Input*/
|
||||
MXC_SYS_CLOCK_HIRC = MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC, /**< High Frequency Internal Oscillator */
|
||||
MXC_SYS_CLOCK_NANORING = MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING, /**< 8KHz nanoring on MAX32660 */
|
||||
MXC_SYS_CLOCK_HFXIN = MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN, /**< 32KHz on MAX32660 */
|
||||
MXC_SYS_CLOCK_HFXIN_DIGITAL = 0x9, /**< External Clock Input*/
|
||||
MXC_SYS_CLOCK_HIRC = MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC, /**< High Frequency Internal Oscillator */
|
||||
} mxc_sys_system_clock_t;
|
||||
|
||||
#define MXC_SYS_USN_LEN 8
|
||||
|
||||
/***** Function Prototypes *****/
|
||||
|
||||
typedef struct {
|
||||
int ie_status;
|
||||
int in_critical;
|
||||
} mxc_crit_state_t;
|
||||
|
||||
static mxc_crit_state_t _state = { .ie_status = 0xFFFFFFFF, .in_critical = 0 };
|
||||
|
||||
static inline void _mxc_crit_get_state()
|
||||
{
|
||||
#ifndef __riscv
|
||||
/*
|
||||
On ARM M the 0th bit of the Priority Mask register indicates
|
||||
whether interrupts are enabled or not.
|
||||
|
||||
0 = enabled
|
||||
1 = disabled
|
||||
*/
|
||||
uint32_t primask = __get_PRIMASK();
|
||||
_state.ie_status = (primask == 0);
|
||||
#else
|
||||
/*
|
||||
On RISC-V bit position 3 (Machine Interrupt Enable) of the
|
||||
mstatus register indicates whether interrupts are enabled.
|
||||
|
||||
0 = disabled
|
||||
1 = enabled
|
||||
*/
|
||||
uint32_t mstatus = get_mstatus();
|
||||
_state.ie_status = ((mstatus & (1 << 3)) != 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enter a critical section of code that cannot be interrupted. Call @ref MXC_SYS_Crit_Exit to exit the critical section.
|
||||
* @details Ex:
|
||||
* @code
|
||||
* MXC_SYS_Crit_Enter();
|
||||
* printf("Hello critical section!\n");
|
||||
* MXC_SYS_Crit_Exit();
|
||||
* @endcode
|
||||
* The @ref MXC_CRITICAL macro is also provided as a convencience macro for wrapping a code section in this way.
|
||||
* @returns None
|
||||
*/
|
||||
static inline void MXC_SYS_Crit_Enter(void)
|
||||
{
|
||||
_mxc_crit_get_state();
|
||||
if (_state.ie_status)
|
||||
__disable_irq();
|
||||
_state.in_critical = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Exit a critical section of code from @ref MXC_SYS_Crit_Enter
|
||||
* @returns None
|
||||
*/
|
||||
static inline void MXC_SYS_Crit_Exit(void)
|
||||
{
|
||||
if (_state.ie_status) {
|
||||
__enable_irq();
|
||||
}
|
||||
_state.in_critical = 0;
|
||||
_mxc_crit_get_state();
|
||||
/*
|
||||
^ Reset the state again to prevent edge case
|
||||
where interrupts get disabled, then Crit_Exit() gets
|
||||
called, which would inadvertently re-enable interrupts
|
||||
from old state.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Polls whether code is currently executing from a critical section.
|
||||
* @returns 1 if code is currently in a critical section (interrupts are disabled).
|
||||
* 0 if code is not in a critical section.
|
||||
*/
|
||||
static inline int MXC_SYS_In_Crit_Section(void)
|
||||
{
|
||||
return _state.in_critical;
|
||||
}
|
||||
|
||||
// clang-format off
|
||||
/**
|
||||
* @brief Macro for wrapping a section of code to make it critical (interrupts disabled). Note: this macro
|
||||
* does not support nesting.
|
||||
* @details
|
||||
* Ex:
|
||||
* \code
|
||||
* MXC_CRITICAL(
|
||||
* printf("Hello critical section!\n");
|
||||
* )
|
||||
* \endcode
|
||||
* This macro places a call to @ref MXC_SYS_Crit_Enter before the code, and a call to @ref MXC_SYS_Crit_Exit after.
|
||||
* @param code The code section to wrap.
|
||||
*/
|
||||
#define MXC_CRITICAL(code) {\
|
||||
MXC_SYS_Crit_Enter();\
|
||||
code;\
|
||||
MXC_SYS_Crit_Exit();\
|
||||
}
|
||||
// clang-format on
|
||||
|
||||
/**
|
||||
* @brief Reads the device USN.
|
||||
* @param usn Pointer to store the USN.
|
||||
* @param len Length of the USN buffer
|
||||
* @param part Which USN part you want (0, 1, 2)
|
||||
* @returns E_NO_ERROR if everything is successful.
|
||||
*/
|
||||
int MXC_SYS_GetUSN(uint8_t *usn, int len, int part);
|
||||
|
||||
/**
|
||||
* @brief Determines if the selected peripheral clock is enabled.
|
||||
* @param clock Enumeration for desired clock.
|
||||
* @returns 0 is the clock is disabled, non 0 if the clock is enabled.
|
||||
*/
|
||||
int MXC_SYS_IsClockEnabled (mxc_sys_periph_clock_t clock);
|
||||
int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock);
|
||||
|
||||
/**
|
||||
* @brief Disables the selected peripheral clock.
|
||||
* @param clock Enumeration for desired clock.
|
||||
*/
|
||||
void MXC_SYS_ClockDisable (mxc_sys_periph_clock_t clock);
|
||||
void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock);
|
||||
|
||||
/**
|
||||
* @brief Enables the selected peripheral clock.
|
||||
* @param clock Enumeration for desired clock.
|
||||
*/
|
||||
void MXC_SYS_ClockEnable (mxc_sys_periph_clock_t clock);
|
||||
void MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock);
|
||||
|
||||
/**
|
||||
* @brief Enables the 32kHz oscillator
|
||||
* @param mxc_sys_cfg Not used, may be NULL.
|
||||
*/
|
||||
void MXC_SYS_RTCClockEnable (void);
|
||||
void MXC_SYS_RTCClockEnable(void);
|
||||
|
||||
/**
|
||||
* @brief Disables the 32kHz oscillator
|
||||
|
|
@ -131,37 +263,36 @@ int MXC_SYS_RTCClockDisable();
|
|||
* @param clock The clock to enable
|
||||
* @return E_NO_ERROR if everything is successful
|
||||
*/
|
||||
int MXC_SYS_ClockSourceEnable (mxc_sys_system_clock_t clock);
|
||||
int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock);
|
||||
|
||||
/**
|
||||
* @brief Disable System Clock Source
|
||||
* @param clock The clock to disable
|
||||
* @return E_NO_ERROR if everything is successful
|
||||
*/
|
||||
int MXC_SYS_ClockSourceDisable (mxc_sys_system_clock_t clock);
|
||||
int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock);
|
||||
|
||||
/**
|
||||
* @brief Select the system clock.
|
||||
* @param clock Enumeration for desired clock.
|
||||
* @param tmr Optional tmr pointer for timeout. NULL if undesired.
|
||||
* @returns E_NO_ERROR if everything is successful.
|
||||
*/
|
||||
int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock);
|
||||
int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock);
|
||||
|
||||
/**
|
||||
* @brief Wait for a clock to enable with timeout
|
||||
* @param ready The clock to wait for
|
||||
* @return E_NO_ERROR if ready, E_TIME_OUT if timeout
|
||||
*/
|
||||
int MXC_SYS_Clock_Timeout (uint32_t ready);
|
||||
int MXC_SYS_Clock_Timeout(uint32_t ready);
|
||||
/**
|
||||
* @brief Reset the peripherals and/or CPU in the rstr0 or rstr1 register.
|
||||
* @param Enumeration for what to reset. Can reset multiple items at once.
|
||||
*/
|
||||
void MXC_SYS_Reset_Periph (mxc_sys_reset_t reset);
|
||||
void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_MXC_SYS_H_*/
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_SYS_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Real Time Clock (RTC) functions and prototypes.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +34,11 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _RTC_H_
|
||||
#define _RTC_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_RTC_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_RTC_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -56,33 +56,36 @@ extern "C" {
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define MXC_RTC_MAX_SSEC (0xFFF + 1) // 0xFFF = max ssec counter value
|
||||
#define MXC_RTC_TRIM_TMR_IRQ MXC_F_TMR_INTR_IRQ
|
||||
|
||||
/* **** Definitions **** */
|
||||
/**
|
||||
* @brief Bitmasks for each of the RTC's Frequency.
|
||||
*/
|
||||
typedef enum {
|
||||
MXC_RTC_F_1HZ = MXC_S_RTC_CTRL_FT_FREQ1HZ, ///< 1Hz (Compensated)
|
||||
MXC_RTC_F_1HZ = MXC_S_RTC_CTRL_FT_FREQ1HZ, ///< 1Hz (Compensated)
|
||||
MXC_RTC_F_512HZ = MXC_S_RTC_CTRL_FT_FREQ512HZ, ///< 512Hz (Compensated)
|
||||
MXC_RTC_F_4KHZ = MXC_S_RTC_CTRL_FT_FREQ4KHZ, ///< 4Khz
|
||||
MXC_RTC_F_32KHZ = 32, ///< 32Khz
|
||||
MXC_RTC_F_4KHZ = MXC_S_RTC_CTRL_FT_FREQ4KHZ, ///< 4Khz
|
||||
MXC_RTC_F_32KHZ = 32, ///< 32Khz
|
||||
} mxc_rtc_freq_sel_t;
|
||||
|
||||
/**
|
||||
* @brief Bitmasks for each of the RTC's interrupt enables.
|
||||
*/
|
||||
typedef enum {
|
||||
MXC_RTC_INT_EN_LONG = MXC_F_RTC_CTRL_ADE, ///< Long-interval alarm interrupt enable
|
||||
MXC_RTC_INT_EN_SHORT = MXC_F_RTC_CTRL_ASE, ///< Short-interval alarm interrupt enable
|
||||
MXC_RTC_INT_EN_READY = MXC_F_RTC_CTRL_RDYE, ///< Timer ready interrupt enable
|
||||
MXC_RTC_INT_EN_LONG = MXC_F_RTC_CTRL_ADE, ///< Long-interval alarm interrupt enable
|
||||
MXC_RTC_INT_EN_SHORT = MXC_F_RTC_CTRL_ASE, ///< Short-interval alarm interrupt enable
|
||||
MXC_RTC_INT_EN_READY = MXC_F_RTC_CTRL_RDYE, ///< Timer ready interrupt enable
|
||||
} mxc_rtc_int_en_t;
|
||||
|
||||
/**
|
||||
* @brief Bitmasks for each of the RTC's interrupt flags.
|
||||
*/
|
||||
typedef enum {
|
||||
MXC_RTC_INT_FL_LONG = MXC_F_RTC_CTRL_ALDF, ///< Long-interval alarm interrupt flag
|
||||
MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_ALSF, ///< Short-interval alarm interrupt flag
|
||||
MXC_RTC_INT_FL_READY = MXC_F_RTC_CTRL_RDY, ///< Timer ready interrupt flag
|
||||
MXC_RTC_INT_FL_LONG = MXC_F_RTC_CTRL_ALDF, ///< Long-interval alarm interrupt flag
|
||||
MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_ALSF, ///< Short-interval alarm interrupt flag
|
||||
MXC_RTC_INT_FL_READY = MXC_F_RTC_CTRL_RDY, ///< Timer ready interrupt flag
|
||||
} mxc_rtc_int_fl_t;
|
||||
|
||||
/**
|
||||
|
|
@ -90,7 +93,7 @@ typedef enum {
|
|||
* @param ras 20-bit value 0-0xFFFFF
|
||||
* @retval returns Success or Fail, see \ref MXC_Error_Codes
|
||||
*/
|
||||
int MXC_RTC_SetTimeofdayAlarm (uint32_t ras);
|
||||
int MXC_RTC_SetTimeofdayAlarm(uint32_t ras);
|
||||
|
||||
/**
|
||||
* @brief Set Sub-Second alarm value and enable interrupt,
|
||||
|
|
@ -98,62 +101,62 @@ int MXC_RTC_SetTimeofdayAlarm (uint32_t ras);
|
|||
* @param rssa 32-bit value 0-0xFFFFFFFF
|
||||
* @retval returns Success or Fail, see \ref MXC_Error_Codes
|
||||
*/
|
||||
int MXC_RTC_SetSubsecondAlarm (uint32_t rssa);
|
||||
int MXC_RTC_SetSubsecondAlarm(uint32_t rssa);
|
||||
|
||||
/**
|
||||
* @brief Start the Real Time Clock
|
||||
* @brief Start the Real Time Clock (Blocking function)
|
||||
* @retval returns Success or Fail, see \ref MXC_Error_Codes
|
||||
*/
|
||||
int MXC_RTC_Start (void);
|
||||
int MXC_RTC_Start(void);
|
||||
/**
|
||||
* @brief Stop the Real Time Clock
|
||||
* @brief Stop the Real Time Clock (Blocking function)
|
||||
* @retval returns Success or Fail, see \ref MXC_Error_Codes
|
||||
*/
|
||||
int MXC_RTC_Stop (void);
|
||||
int MXC_RTC_Stop(void);
|
||||
|
||||
/**
|
||||
* @brief Initialize the sec and ssec registers and enable RTC
|
||||
* @brief Initialize the sec and ssec registers and enable RTC (Blocking function)
|
||||
* @param sec set the RTC Sec counter (32-bit)
|
||||
* @param ssec set the RTC Sub-second counter (8-bit)
|
||||
* @retval returns Success or Fail, see \ref MXC_Error_Codes
|
||||
*/
|
||||
int MXC_RTC_Init (uint32_t sec, uint8_t ssec);
|
||||
int MXC_RTC_Init(uint32_t sec, uint8_t ssec);
|
||||
|
||||
/**
|
||||
* @brief Allow generation of Square Wave on the SQW pin
|
||||
* @brief Allow generation of Square Wave on the SQW pin (Blocking function)
|
||||
* @param fq Frequency output selection
|
||||
* @retval returns Success or Fail, see \ref MXC_Error_Codes
|
||||
*/
|
||||
int MXC_RTC_SquareWaveStart (mxc_rtc_freq_sel_t fq);
|
||||
|
||||
/**
|
||||
* @brief Stop the generation of square wave
|
||||
* @retval returns Success or Fail, see \ref MXC_Error_Codes
|
||||
*/
|
||||
int MXC_RTC_SquareWaveStop (void);
|
||||
int MXC_RTC_SquareWaveStart(mxc_rtc_freq_sel_t fq);
|
||||
|
||||
/**
|
||||
* @brief Set Trim register value
|
||||
* @brief Stop the generation of square wave (Blocking function)
|
||||
* @retval returns Success or Fail, see \ref MXC_Error_Codes
|
||||
*/
|
||||
int MXC_RTC_SquareWaveStop(void);
|
||||
|
||||
/**
|
||||
* @brief Set Trim register value (Blocking function)
|
||||
* @param trm set the RTC Trim (8-bit, +/- 127)
|
||||
* @retval returns Success or Fail, see \ref MXC_Error_Codes
|
||||
*/
|
||||
int MXC_RTC_Trim (int8_t trm);
|
||||
int MXC_RTC_Trim(int8_t trm);
|
||||
|
||||
/**
|
||||
* @brief Enable Interurpts
|
||||
* @brief Enable Interurpts (Blocking function)
|
||||
* @param mask The bitwise OR of interrupts to enable.
|
||||
* See #mxc_rtc_int_en_t for available choices.
|
||||
* @retval returns Success or Fail, see \ref MXC_Error_Codes
|
||||
*/
|
||||
int MXC_RTC_EnableInt (uint32_t mask);
|
||||
int MXC_RTC_EnableInt(uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Disable Interurpts
|
||||
* @brief Disable Interurpts (Blocking function)
|
||||
* @param mask The mask of interrupts to disable.
|
||||
* See #mxc_rtc_int_en_t for available choices.
|
||||
* @retval returns Success or Fail, see \ref MXC_Error_Codes
|
||||
*/
|
||||
int MXC_RTC_DisableInt (uint32_t mask);
|
||||
int MXC_RTC_DisableInt(uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Gets interrupt flags.
|
||||
|
|
@ -161,7 +164,7 @@ int MXC_RTC_DisableInt (uint32_t mask);
|
|||
* currently set. See \ref mxc_rtc_int_fl_t for the list
|
||||
* of possible flags.
|
||||
*/
|
||||
int MXC_RTC_GetFlags (void);
|
||||
int MXC_RTC_GetFlags(void);
|
||||
|
||||
/**
|
||||
* @brief Clear interrupt flags.
|
||||
|
|
@ -169,19 +172,19 @@ int MXC_RTC_GetFlags (void);
|
|||
* See #mxc_rtc_int_fl_t for the list of possible flags.
|
||||
* @retval returns Success or Fail, see \ref MXC_Error_Codes
|
||||
*/
|
||||
int MXC_RTC_ClearFlags (int flags);
|
||||
int MXC_RTC_ClearFlags(int flags);
|
||||
|
||||
/**
|
||||
* @brief Get SubSecond
|
||||
* @brief Get SubSecond or E_BUSY, see /ref MXC_ERROR_CODES
|
||||
* @retval Returns subsecond value
|
||||
*/
|
||||
int MXC_RTC_GetSubSecond (void);
|
||||
int MXC_RTC_GetSubSecond(void);
|
||||
|
||||
/**
|
||||
* @brief Get Second
|
||||
* @brief Get Second or E_BUSY, see /ref MXC_ERROR_CODES
|
||||
* @retval returns second value
|
||||
*/
|
||||
int MXC_RTC_GetSecond (void);
|
||||
int MXC_RTC_GetSecond(void);
|
||||
|
||||
/**
|
||||
* @brief Get the time using nuclear fusion. Or atomically. Something like that.
|
||||
|
|
@ -189,11 +192,17 @@ int MXC_RTC_GetSecond (void);
|
|||
* @param subsec pointer to store subseconds value
|
||||
* @retval returns Success or Fail, see \ref MXC_Error_Codes
|
||||
*/
|
||||
int MXC_RTC_GetTime (uint32_t* sec, uint32_t* subsec);
|
||||
int MXC_RTC_GetTime(uint32_t *sec, uint32_t *subsec);
|
||||
|
||||
/**
|
||||
* @brief Get RTC busy flag.
|
||||
* @retval returns Success or E_BUSY, see /ref MXC_ERROR_CODES
|
||||
*/
|
||||
int MXC_RTC_GetBusyFlag(void);
|
||||
|
||||
/**@} end of group rtc */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _RTC_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_RTC_H_
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**
|
||||
* @file spimss.h
|
||||
* @brief Serial Peripheral Interface (SPIMSS) function prototypes and data types.
|
||||
*/
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,12 +34,11 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
******************************************************************************/
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _SPIMSS_H_
|
||||
#define _SPIMSS_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPIMSS_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPIMSS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_device.h"
|
||||
|
|
@ -60,14 +59,13 @@ extern "C" {
|
|||
|
||||
/* **** Definitions **** */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enumeration type for setting the number data lines to use for communication.
|
||||
*/
|
||||
typedef enum { // ONLY FOR COMPATIBILITY FOR CONSOLIDATION WITH SPY17, NOT USED OR NEEDED
|
||||
DUMMY_1, /**< NOT USED */
|
||||
DUMMY_2, /**< NOT USED */
|
||||
DUMMY_3, /**< NOT USED */
|
||||
typedef enum { // ONLY FOR COMPATIBILITY FOR CONSOLIDATION WITH SPY17, NOT USED OR NEEDED
|
||||
DUMMY_1, /**< NOT USED */
|
||||
DUMMY_2, /**< NOT USED */
|
||||
DUMMY_3, /**< NOT USED */
|
||||
} mxc_spimss_width_t;
|
||||
|
||||
/**
|
||||
|
|
@ -87,7 +85,7 @@ typedef struct mxc_spimss_req mxc_spimss_req_t;
|
|||
* | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. |
|
||||
* @note Callback will execute in interrupt context
|
||||
*/
|
||||
typedef void (*mxc_spimss_callback_fn)(mxc_spimss_req_t * req, int error_code);
|
||||
typedef void (*mxc_spimss_callback_fn)(mxc_spimss_req_t *req, int error_code);
|
||||
|
||||
/**
|
||||
* @brief Structure definition for an SPI Master Transaction request.
|
||||
|
|
@ -95,16 +93,16 @@ typedef void (*mxc_spimss_callback_fn)(mxc_spimss_req_t * req, int error_code);
|
|||
* structure must remain allocated until the callback is completed.
|
||||
*/
|
||||
struct mxc_spimss_req {
|
||||
uint8_t ssel; /**< Not Used*/
|
||||
uint8_t deass; /**< Not Used*/
|
||||
const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */
|
||||
void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/
|
||||
mxc_spimss_width_t width; /**< Not Used */
|
||||
unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */
|
||||
unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */
|
||||
unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */
|
||||
unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */
|
||||
mxc_spimss_callback_fn callback; /**< Callback function if desired, NULL otherwise */
|
||||
uint8_t ssel; /**< Not Used*/
|
||||
uint8_t deass; /**< Not Used*/
|
||||
const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */
|
||||
void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/
|
||||
mxc_spimss_width_t width; /**< Not Used */
|
||||
unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */
|
||||
unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */
|
||||
unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */
|
||||
unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */
|
||||
mxc_spimss_callback_fn callback; /**< Callback function if desired, NULL otherwise */
|
||||
};
|
||||
|
||||
/* **** Function Prototypes **** */
|
||||
|
|
@ -115,12 +113,10 @@ struct mxc_spimss_req {
|
|||
* @param mode SPI mode for clock phase and polarity.
|
||||
* @param freq Desired clock frequency.
|
||||
* @param sys_cfg System configuration object
|
||||
* @param drv_ssel 1 SSEL will be drive by driver
|
||||
* 0 SSEL will NOT be drive by driver
|
||||
*
|
||||
* @return \c #E_NO_ERROR if successful, appropriate error otherwise
|
||||
*/
|
||||
int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg, unsigned drv_ssel);
|
||||
int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg);
|
||||
|
||||
/**
|
||||
* @brief Shutdown SPI module.
|
||||
|
|
@ -179,19 +175,6 @@ int MXC_SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req);
|
|||
*/
|
||||
int MXC_SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req);
|
||||
|
||||
/**
|
||||
* @brief Sets the TX data to transmit as a 'dummy' byte
|
||||
*
|
||||
* In single wire master mode, this data is transmitted on MOSI when performing
|
||||
* an RX (MISO) only transaction. This defaults to 0.
|
||||
*
|
||||
* @param spi Pointer to SPI registers (selects the SPI block used.)
|
||||
* @param defaultTXData Data to shift out in RX-only transactions
|
||||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_SPIMSS_SetDefaultTXData (mxc_spimss_req_t* spi, unsigned int defaultTXData);
|
||||
|
||||
/**
|
||||
* @brief Aborts an Asynchronous request
|
||||
*
|
||||
|
|
@ -207,4 +190,4 @@ int MXC_SPIMSS_AbortAsync(mxc_spimss_req_t *req);
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SPIMSS_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_SPIMSS_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Timer (TMR) function prototypes and data types.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +34,11 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _TMR_H_
|
||||
#define _TMR_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_TMR_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_TMR_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_device.h"
|
||||
|
|
@ -61,34 +61,38 @@ extern "C" {
|
|||
* @brief Timer prescaler values
|
||||
*/
|
||||
typedef enum {
|
||||
TMR_PRES_1 = MXC_S_TMR_CN_PRES_DIV_BY_1, ///< Divide input clock by 1
|
||||
TMR_PRES_2 = MXC_S_TMR_CN_PRES_DIV_BY_2, ///< Divide input clock by 2
|
||||
TMR_PRES_4 = MXC_S_TMR_CN_PRES_DIV_BY_4, ///< Divide input clock by 4
|
||||
TMR_PRES_8 = MXC_S_TMR_CN_PRES_DIV_BY_8, ///< Divide input clock by 8
|
||||
TMR_PRES_16 = MXC_S_TMR_CN_PRES_DIV_BY_16, ///< Divide input clock by 16
|
||||
TMR_PRES_32 = MXC_S_TMR_CN_PRES_DIV_BY_32, ///< Divide input clock by 32
|
||||
TMR_PRES_64 = MXC_S_TMR_CN_PRES_DIV_BY_64, ///< Divide input clock by 64
|
||||
TMR_PRES_128 = MXC_S_TMR_CN_PRES_DIV_BY_128, ///< Divide input clock by 128
|
||||
TMR_PRES_256 = MXC_S_TMR_CN_PRES_DIV_BY_256, ///< Divide input clock by 256
|
||||
TMR_PRES_512 = MXC_S_TMR_CN_PRES_DIV_BY_512, ///< Divide input clock by 512
|
||||
TMR_PRES_1024 = MXC_S_TMR_CN_PRES_DIV_BY_1024, ///< Divide input clock by 1024
|
||||
TMR_PRES_2048 = MXC_S_TMR_CN_PRES_DIV_BY_2048, ///< Divide input clock by 2048
|
||||
TMR_PRES_4096 = MXC_S_TMR_CN_PRES_DIV_BY_4096, ///< Divide input clock by 4096
|
||||
TMR_PRES_8192 = MXC_S_TMR_CN_PRES_DIV_BY_8192 ///< Divide input clock by 8192
|
||||
TMR_PRES_1 = MXC_S_TMR_CN_PRES_DIV_BY_1, ///< Divide input clock by 1
|
||||
TMR_PRES_2 = MXC_S_TMR_CN_PRES_DIV_BY_2, ///< Divide input clock by 2
|
||||
TMR_PRES_4 = MXC_S_TMR_CN_PRES_DIV_BY_4, ///< Divide input clock by 4
|
||||
TMR_PRES_8 = MXC_S_TMR_CN_PRES_DIV_BY_8, ///< Divide input clock by 8
|
||||
TMR_PRES_16 = MXC_S_TMR_CN_PRES_DIV_BY_16, ///< Divide input clock by 16
|
||||
TMR_PRES_32 = MXC_S_TMR_CN_PRES_DIV_BY_32, ///< Divide input clock by 32
|
||||
TMR_PRES_64 = MXC_S_TMR_CN_PRES_DIV_BY_64, ///< Divide input clock by 64
|
||||
TMR_PRES_128 = MXC_S_TMR_CN_PRES_DIV_BY_128, ///< Divide input clock by 128
|
||||
TMR_PRES_256 = MXC_S_TMR_CN_PRES_DIV_BY_256 | MXC_F_TMR_CN_PRES3, ///< Divide input clock by 256
|
||||
TMR_PRES_512 = MXC_S_TMR_CN_PRES_DIV_BY_512 | MXC_F_TMR_CN_PRES3, ///< Divide input clock by 512
|
||||
TMR_PRES_1024 = MXC_S_TMR_CN_PRES_DIV_BY_1024 |
|
||||
MXC_F_TMR_CN_PRES3, ///< Divide input clock by 1024
|
||||
TMR_PRES_2048 = MXC_S_TMR_CN_PRES_DIV_BY_2048 |
|
||||
MXC_F_TMR_CN_PRES3, ///< Divide input clock by 2048
|
||||
TMR_PRES_4096 = MXC_S_TMR_CN_PRES_DIV_BY_4096 |
|
||||
MXC_F_TMR_CN_PRES3, ///< Divide input clock by 4096
|
||||
TMR_PRES_8192 = MXC_S_TMR_CN_PRES_DIV_BY_8192 |
|
||||
MXC_F_TMR_CN_PRES3 ///< Divide input clock by 8192
|
||||
} mxc_tmr_pres_t;
|
||||
|
||||
/**
|
||||
* @brief Timer modes
|
||||
*/
|
||||
typedef enum {
|
||||
TMR_MODE_ONESHOT = MXC_S_TMR_CN_TMODE_ONE_SHOT, ///< Timer Mode ONESHOT
|
||||
TMR_MODE_CONTINUOUS = MXC_V_TMR_CN_TMODE_CONTINUOUS, ///< Timer Mode CONTINUOUS
|
||||
TMR_MODE_COUNTER = MXC_V_TMR_CN_TMODE_COUNTER, ///< Timer Mode COUNTER
|
||||
TMR_MODE_PWM = MXC_V_TMR_CN_TMODE_PWM, ///< Timer Mode PWM
|
||||
TMR_MODE_CAPTURE = MXC_V_TMR_CN_TMODE_CAPTURE, ///< Timer Mode CAPTURE
|
||||
TMR_MODE_COMPARE = MXC_V_TMR_CN_TMODE_COMPARE, ///< Timer Mode COMPARE
|
||||
TMR_MODE_GATED = MXC_V_TMR_CN_TMODE_GATED, ///< Timer Mode GATED
|
||||
TMR_MODE_CAPTURE_COMPARE = MXC_S_TMR_CN_TMODE_CAPCOMP ///< Timer Mode CAPTURECOMPARE
|
||||
TMR_MODE_ONESHOT = MXC_S_TMR_CN_TMODE_ONE_SHOT, ///< Timer Mode ONESHOT
|
||||
TMR_MODE_CONTINUOUS = MXC_V_TMR_CN_TMODE_CONTINUOUS, ///< Timer Mode CONTINUOUS
|
||||
TMR_MODE_COUNTER = MXC_V_TMR_CN_TMODE_COUNTER, ///< Timer Mode COUNTER
|
||||
TMR_MODE_PWM = MXC_V_TMR_CN_TMODE_PWM, ///< Timer Mode PWM
|
||||
TMR_MODE_CAPTURE = MXC_V_TMR_CN_TMODE_CAPTURE, ///< Timer Mode CAPTURE
|
||||
TMR_MODE_COMPARE = MXC_V_TMR_CN_TMODE_COMPARE, ///< Timer Mode COMPARE
|
||||
TMR_MODE_GATED = MXC_V_TMR_CN_TMODE_GATED, ///< Timer Mode GATED
|
||||
TMR_MODE_CAPTURE_COMPARE = MXC_S_TMR_CN_TMODE_CAPCOMP ///< Timer Mode CAPTURECOMPARE
|
||||
} mxc_tmr_mode_t;
|
||||
|
||||
/**
|
||||
|
|
@ -96,46 +100,33 @@ typedef enum {
|
|||
*
|
||||
*/
|
||||
typedef enum {
|
||||
TMR_BIT_MODE_32, ///< Timer Mode 32 bit
|
||||
TMR_BIT_MODE_16A, ///< Timer Mode Lower 16 bit
|
||||
TMR_BIT_MODE_16B, ///< Timer Mode Upper 16 bit
|
||||
TMR_BIT_MODE_32, ///< Timer Mode 32 bit
|
||||
TMR_BIT_MODE_16A, ///< Timer Mode Lower 16 bit
|
||||
TMR_BIT_MODE_16B, ///< Timer Mode Upper 16 bit
|
||||
} mxc_tmr_bit_mode_t;
|
||||
|
||||
/**
|
||||
* @brief Timer units of time enumeration
|
||||
*/
|
||||
typedef enum {
|
||||
TMR_UNIT_NANOSEC, ///< Nanosecond Unit Indicator
|
||||
TMR_UNIT_MICROSEC, ///< Microsecond Unit Indicator
|
||||
TMR_UNIT_MILLISEC, ///< Millisecond Unit Indicator
|
||||
TMR_UNIT_SEC, ///< Second Unit Indicator
|
||||
TMR_UNIT_NANOSEC, ///< Nanosecond Unit Indicator
|
||||
TMR_UNIT_MICROSEC, ///< Microsecond Unit Indicator
|
||||
TMR_UNIT_MILLISEC, ///< Millisecond Unit Indicator
|
||||
TMR_UNIT_SEC, ///< Second Unit Indicator
|
||||
} mxc_tmr_unit_t;
|
||||
|
||||
/**
|
||||
* @brief Clock settings
|
||||
* @note 8M and 32M clocks can be used for Timers 0,1,2 and 3
|
||||
* 32K and 80K clocks can only be used for Timers 4 and 5
|
||||
*/
|
||||
typedef enum {
|
||||
MXC_TMR_HFIO_CLK, ///< HFIO Clock
|
||||
MXC_TMR_NANORING_CLK, ///< 8KHz Nanoring Clock
|
||||
MXC_TMR_EXT_CLK, ///< External Clock
|
||||
} mxc_tmr_clock_t;
|
||||
|
||||
/**
|
||||
* @brief Timer Configuration
|
||||
*/
|
||||
typedef struct {
|
||||
mxc_tmr_pres_t pres; ///< Desired timer prescaler
|
||||
mxc_tmr_mode_t mode; ///< Desired timer mode
|
||||
mxc_tmr_bit_mode_t bitMode; ///< Desired timer bits
|
||||
mxc_tmr_clock_t clock; ///< Desired clock source
|
||||
uint32_t cmp_cnt; ///< Compare register value in timer ticks
|
||||
unsigned pol; ///< Polarity (0 or 1)
|
||||
mxc_tmr_pres_t pres; ///< Desired timer prescaler
|
||||
mxc_tmr_mode_t mode; ///< Desired timer mode
|
||||
uint32_t cmp_cnt; ///< Compare register value in timer ticks
|
||||
unsigned pol; ///< Polarity (0 or 1)
|
||||
} mxc_tmr_cfg_t;
|
||||
|
||||
/* **** Definitions **** */
|
||||
typedef void (*mxc_tmr_complete_t) (int error);
|
||||
typedef void (*mxc_tmr_complete_t)(int error);
|
||||
|
||||
/* **** Function Prototypes **** */
|
||||
|
||||
|
|
@ -146,25 +137,25 @@ typedef void (*mxc_tmr_complete_t) (int error);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_TMR_Init (mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t* cfg);
|
||||
int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg);
|
||||
|
||||
/**
|
||||
* @brief Shutdown timer module clock.
|
||||
* @param tmr Pointer to timer module to initialize.
|
||||
*/
|
||||
void MXC_TMR_Shutdown (mxc_tmr_regs_t *tmr);
|
||||
void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr);
|
||||
|
||||
/**
|
||||
* @brief Start the timer counting.
|
||||
* @param tmr Pointer to timer module to initialize.
|
||||
*/
|
||||
void MXC_TMR_Start (mxc_tmr_regs_t* tmr);
|
||||
void MXC_TMR_Start(mxc_tmr_regs_t *tmr);
|
||||
|
||||
/**
|
||||
* @brief Stop the timer.
|
||||
* @param tmr Pointer to timer module to initialize.
|
||||
*/
|
||||
void MXC_TMR_Stop (mxc_tmr_regs_t* tmr);
|
||||
void MXC_TMR_Stop(mxc_tmr_regs_t *tmr);
|
||||
|
||||
/**
|
||||
* @brief Set the value of the first transition in PWM mode
|
||||
|
|
@ -173,65 +164,64 @@ void MXC_TMR_Stop (mxc_tmr_regs_t* tmr);
|
|||
* @note Will block until safe to change the period count.
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_TMR_SetPWM (mxc_tmr_regs_t* tmr, uint32_t pwm);
|
||||
int MXC_TMR_SetPWM(mxc_tmr_regs_t *tmr, uint32_t pwm);
|
||||
|
||||
/**
|
||||
* @brief Get the timer compare count.
|
||||
* @param tmr Pointer to timer module to initialize.
|
||||
* @return Returns the current compare count.
|
||||
*/
|
||||
uint32_t MXC_TMR_GetCompare (mxc_tmr_regs_t* tmr);
|
||||
uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t *tmr);
|
||||
|
||||
/**
|
||||
* @brief Get the timer capture count.
|
||||
* @param tmr Pointer to timer module to initialize.
|
||||
* @return Returns the most recent capture count.
|
||||
*/
|
||||
uint32_t MXC_TMR_GetCapture (mxc_tmr_regs_t* tmr);
|
||||
uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t *tmr);
|
||||
|
||||
/**
|
||||
* @brief Get the timer count.
|
||||
* @param tmr Pointer to timer module to initialize.
|
||||
* @return Returns the current count.
|
||||
*/
|
||||
uint32_t MXC_TMR_GetCount (mxc_tmr_regs_t* tmr);
|
||||
uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t *tmr);
|
||||
|
||||
/**
|
||||
* @brief Calculate count for required frequency.
|
||||
* @param tmr Timer
|
||||
* @param clock Clock source.
|
||||
* @param prescalar prescalar
|
||||
* @param frequency required frequency.
|
||||
* @return Returns the period count.
|
||||
*/
|
||||
uint32_t MXC_TMR_GetPeriod (mxc_tmr_regs_t* tmr, mxc_tmr_clock_t clock, uint32_t prescalar, uint32_t frequency);
|
||||
uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, uint32_t prescalar, uint32_t frequency);
|
||||
|
||||
/**
|
||||
* @brief Clear the timer interrupt.
|
||||
* @param tmr Pointer to timer module to initialize.
|
||||
*/
|
||||
void MXC_TMR_ClearFlags (mxc_tmr_regs_t* tmr);
|
||||
void MXC_TMR_ClearFlags(mxc_tmr_regs_t *tmr);
|
||||
|
||||
/**
|
||||
* @brief Get the timer interrupt status.
|
||||
* @param tmr Pointer to timer module to initialize.
|
||||
* @return Returns the interrupt status. 1 if interrupt has occured.
|
||||
*/
|
||||
uint32_t MXC_TMR_GetFlags (mxc_tmr_regs_t* tmr);
|
||||
uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t *tmr);
|
||||
|
||||
/**
|
||||
* @brief enable interupt
|
||||
*
|
||||
* @param tmr The timer
|
||||
*/
|
||||
void MXC_TMR_EnableInt (mxc_tmr_regs_t* tmr);
|
||||
void MXC_TMR_EnableInt(mxc_tmr_regs_t *tmr);
|
||||
|
||||
/**
|
||||
* @brief disable interupt
|
||||
*
|
||||
* @param tmr The timer
|
||||
*/
|
||||
void MXC_TMR_DisableInt (mxc_tmr_regs_t* tmr);
|
||||
void MXC_TMR_DisableInt(mxc_tmr_regs_t *tmr);
|
||||
|
||||
/**
|
||||
* @brief Set the timer compare count.
|
||||
|
|
@ -239,14 +229,14 @@ void MXC_TMR_DisableInt (mxc_tmr_regs_t* tmr);
|
|||
* @param cmp_cnt New compare count.
|
||||
* @note In PWM Mode use this to set the value of the second transition.
|
||||
*/
|
||||
void MXC_TMR_SetCompare (mxc_tmr_regs_t *tmr, uint32_t cmp_cnt);
|
||||
void MXC_TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt);
|
||||
|
||||
/**
|
||||
* @brief Set the timer count.
|
||||
* @param tmr Pointer to timer module to initialize.
|
||||
* @param cnt New count.
|
||||
*/
|
||||
void MXC_TMR_SetCount (mxc_tmr_regs_t *tmr, uint32_t cnt);
|
||||
void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt);
|
||||
|
||||
/**
|
||||
* @brief Dealay for a set periord of time measured in microseconds
|
||||
|
|
@ -254,7 +244,7 @@ void MXC_TMR_SetCount (mxc_tmr_regs_t *tmr, uint32_t cnt);
|
|||
* @param tmr The timer
|
||||
* @param us microseconds to delay for
|
||||
*/
|
||||
void MXC_TMR_Delay (mxc_tmr_regs_t *tmr, unsigned long us);
|
||||
void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us);
|
||||
|
||||
/**
|
||||
* @brief Start a timer that will time out after a certain number of microseconds
|
||||
|
|
@ -263,7 +253,7 @@ void MXC_TMR_Delay (mxc_tmr_regs_t *tmr, unsigned long us);
|
|||
* @param tmr The timer
|
||||
* @param us microseconds to time out after
|
||||
*/
|
||||
void MXC_TMR_TO_Start (mxc_tmr_regs_t *tmr, unsigned long us);
|
||||
void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us);
|
||||
|
||||
/**
|
||||
* @brief Check on time out timer
|
||||
|
|
@ -272,21 +262,21 @@ void MXC_TMR_TO_Start (mxc_tmr_regs_t *tmr, unsigned long us);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_TMR_TO_Check (mxc_tmr_regs_t *tmr);
|
||||
int MXC_TMR_TO_Check(mxc_tmr_regs_t *tmr);
|
||||
|
||||
/**
|
||||
* @brief Stop the Timeout timer
|
||||
*
|
||||
* @param tmr The timer
|
||||
*/
|
||||
void MXC_TMR_TO_Stop (mxc_tmr_regs_t *tmr);
|
||||
void MXC_TMR_TO_Stop(mxc_tmr_regs_t *tmr);
|
||||
|
||||
/**
|
||||
* @brief Clear timeout timer back to zero
|
||||
*
|
||||
* @param tmr The timer
|
||||
*/
|
||||
void MXC_TMR_TO_Clear (mxc_tmr_regs_t *tmr);
|
||||
void MXC_TMR_TO_Clear(mxc_tmr_regs_t *tmr);
|
||||
|
||||
/**
|
||||
* @brief Get elapsed time of timeout timer
|
||||
|
|
@ -295,7 +285,7 @@ void MXC_TMR_TO_Clear (mxc_tmr_regs_t *tmr);
|
|||
*
|
||||
* @return Time that has elapsed in timeout timer
|
||||
*/
|
||||
unsigned int MXC_TMR_TO_Elapsed (mxc_tmr_regs_t *tmr);
|
||||
unsigned int MXC_TMR_TO_Elapsed(mxc_tmr_regs_t *tmr);
|
||||
|
||||
/**
|
||||
* @brief Amount of time remaining until timeour
|
||||
|
|
@ -304,14 +294,14 @@ unsigned int MXC_TMR_TO_Elapsed (mxc_tmr_regs_t *tmr);
|
|||
*
|
||||
* @return Time that is left until timeout
|
||||
*/
|
||||
unsigned int MXC_TMR_TO_Remaining (mxc_tmr_regs_t *tmr);
|
||||
unsigned int MXC_TMR_TO_Remaining(mxc_tmr_regs_t *tmr);
|
||||
|
||||
/**
|
||||
* @brief Start stopwatch
|
||||
*
|
||||
* @param tmr The timer
|
||||
*/
|
||||
void MXC_TMR_SW_Start (mxc_tmr_regs_t *tmr);
|
||||
void MXC_TMR_SW_Start(mxc_tmr_regs_t *tmr);
|
||||
|
||||
/**
|
||||
* @brief Stopwatch stop
|
||||
|
|
@ -320,7 +310,7 @@ void MXC_TMR_SW_Start (mxc_tmr_regs_t *tmr);
|
|||
*
|
||||
* @return the time when the stopwatch is stopped.
|
||||
*/
|
||||
unsigned int MXC_TMR_SW_Stop (mxc_tmr_regs_t *tmr);
|
||||
unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t *tmr);
|
||||
|
||||
/**
|
||||
* @brief Get time from timer
|
||||
|
|
@ -332,7 +322,7 @@ unsigned int MXC_TMR_SW_Stop (mxc_tmr_regs_t *tmr);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_TMR_GetTime (mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units);
|
||||
int MXC_TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units);
|
||||
|
||||
/**@} end of group tmr */
|
||||
|
||||
|
|
@ -340,4 +330,4 @@ int MXC_TMR_GetTime (mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tm
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TMR_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_TMR_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief (UART) communications driver.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +34,11 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_UART_H_
|
||||
#define _MXC_UART_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_UART_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_UART_H_
|
||||
|
||||
/***** Definitions *****/
|
||||
#include "uart_regs.h"
|
||||
|
|
@ -61,8 +61,8 @@ typedef struct _mxc_uart_req_t mxc_uart_req_t;
|
|||
*
|
||||
*/
|
||||
typedef enum {
|
||||
MXC_UART_STOP_1, ///< UART Stop 1 clock cycle
|
||||
MXC_UART_STOP_2, ///< UART Stop 2 clock cycle (1.5 clocks for 5 bit characters)
|
||||
MXC_UART_STOP_1, ///< UART Stop 1 clock cycle
|
||||
MXC_UART_STOP_2, ///< UART Stop 2 clock cycle (1.5 clocks for 5 bit characters)
|
||||
} mxc_uart_stop_t;
|
||||
|
||||
/**
|
||||
|
|
@ -70,19 +70,19 @@ typedef enum {
|
|||
*
|
||||
*/
|
||||
typedef enum {
|
||||
MXC_UART_PARITY_DISABLE, ///< UART Parity Disabled
|
||||
MXC_UART_PARITY_EVEN, ///< UART Parity Even
|
||||
MXC_UART_PARITY_ODD, ///< UART Parity Odd
|
||||
MXC_UART_PARITY_MARK, ///< UART Parity Mark
|
||||
MXC_UART_PARITY_SPACE, ///< UART Parity Space
|
||||
MXC_UART_PARITY_EVEN_0, ///< UART Parity Even, 0 based
|
||||
MXC_UART_PARITY_EVEN_1, ///< UART Parity Even, 1 based
|
||||
MXC_UART_PARITY_ODD_0, ///< UART Parity Odd, 0 based
|
||||
MXC_UART_PARITY_ODD_1, ///< UART Parity Odd, 1 based
|
||||
MXC_UART_PARITY_MARK_0, ///< UART Parity Mark, 0 based
|
||||
MXC_UART_PARITY_MARK_1, ///< UART Parity Mark, 1 based
|
||||
MXC_UART_PARITY_SPACE_0, ///< UART Parity Space, 0 based
|
||||
MXC_UART_PARITY_SPACE_1, ///< UART Parity Space, 1 based
|
||||
MXC_UART_PARITY_DISABLE, ///< UART Parity Disabled
|
||||
MXC_UART_PARITY_EVEN, ///< UART Parity Even
|
||||
MXC_UART_PARITY_ODD, ///< UART Parity Odd
|
||||
MXC_UART_PARITY_MARK, ///< UART Parity Mark
|
||||
MXC_UART_PARITY_SPACE, ///< UART Parity Space
|
||||
MXC_UART_PARITY_EVEN_0, ///< UART Parity Even, 0 based
|
||||
MXC_UART_PARITY_EVEN_1, ///< UART Parity Even, 1 based
|
||||
MXC_UART_PARITY_ODD_0, ///< UART Parity Odd, 0 based
|
||||
MXC_UART_PARITY_ODD_1, ///< UART Parity Odd, 1 based
|
||||
MXC_UART_PARITY_MARK_0, ///< UART Parity Mark, 0 based
|
||||
MXC_UART_PARITY_MARK_1, ///< UART Parity Mark, 1 based
|
||||
MXC_UART_PARITY_SPACE_0, ///< UART Parity Space, 0 based
|
||||
MXC_UART_PARITY_SPACE_1, ///< UART Parity Space, 1 based
|
||||
} mxc_uart_parity_t;
|
||||
|
||||
/**
|
||||
|
|
@ -90,19 +90,18 @@ typedef enum {
|
|||
*
|
||||
*/
|
||||
typedef enum {
|
||||
MXC_UART_FLOW_DIS, ///< UART Flow Control Disabled
|
||||
MXC_UART_FLOW_EN_LOW, ///< UART Flow Control Enabled, Active Low
|
||||
MXC_UART_FLOW_EN_HIGH, ///< UART Flow Control Enabled, Active High
|
||||
MXC_UART_FLOW_DIS, ///< UART Flow Control Disabled
|
||||
MXC_UART_FLOW_EN_LOW, ///< UART Flow Control Enabled, Active Low
|
||||
MXC_UART_FLOW_EN_HIGH, ///< UART Flow Control Enabled, Active High
|
||||
} mxc_uart_flow_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief The callback routine used to indicate the transaction has terminated.
|
||||
*
|
||||
* @param req The details of the transaction.
|
||||
* @param result See \ref MXC_Error_Codes for the list of error codes.
|
||||
*/
|
||||
typedef void (*mxc_uart_complete_cb_t) (mxc_uart_req_t* req, int result);
|
||||
typedef void (*mxc_uart_complete_cb_t)(mxc_uart_req_t *req, int result);
|
||||
|
||||
/**
|
||||
* @brief The callback routine used to indicate the transaction has terminated.
|
||||
|
|
@ -111,7 +110,7 @@ typedef void (*mxc_uart_complete_cb_t) (mxc_uart_req_t* req, int result);
|
|||
* @param num The number of characters actually copied
|
||||
* @param result See \ref MXC_Error_Codes for the list of error codes.
|
||||
*/
|
||||
typedef void (*mxc_uart_dma_complete_cb_t) (mxc_uart_req_t* req, int num, int result);
|
||||
typedef void (*mxc_uart_dma_complete_cb_t)(mxc_uart_req_t *req, int num, int result);
|
||||
|
||||
/**
|
||||
* @brief The information required to perform a complete UART transaction
|
||||
|
|
@ -119,21 +118,21 @@ typedef void (*mxc_uart_dma_complete_cb_t) (mxc_uart_req_t* req, int num, int re
|
|||
* @note This structure is used by blocking, async, and DMA based transactions.
|
||||
*/
|
||||
struct _mxc_uart_req_t {
|
||||
mxc_uart_regs_t* uart; ///<Point to UART registers
|
||||
uint8_t *txData; ///< Buffer containing transmit data. For character sizes
|
||||
mxc_uart_regs_t *uart; ///<Point to UART registers
|
||||
uint8_t *txData; ///< Buffer containing transmit data. For character sizes
|
||||
///< < 8 bits, pad the MSB of each byte with zeros. For
|
||||
///< character sizes > 8 bits, use two bytes per character
|
||||
///< and pad the MSB of the upper byte with zeros
|
||||
uint8_t *rxData; ///< Buffer to store received data For character sizes
|
||||
uint8_t *rxData; ///< Buffer to store received data For character sizes
|
||||
///< < 8 bits, pad the MSB of each byte with zeros. For
|
||||
///< character sizes > 8 bits, use two bytes per character
|
||||
///< and pad the MSB of the upper byte with zeros
|
||||
uint32_t txLen; ///< Number of bytes to be sent from txData
|
||||
uint32_t rxLen; ///< Number of bytes to be stored in rxData
|
||||
uint32_t txCnt; ///< Number of bytes actually transmitted from txData
|
||||
uint32_t rxCnt; ///< Number of bytes stored in rxData
|
||||
uint32_t txLen; ///< Number of bytes to be sent from txData
|
||||
uint32_t rxLen; ///< Number of bytes to be stored in rxData
|
||||
volatile uint32_t txCnt; ///< Number of bytes actually transmitted from txData
|
||||
volatile uint32_t rxCnt; ///< Number of bytes stored in rxData
|
||||
|
||||
mxc_uart_complete_cb_t callback; ///< Pointer to function called when transaction is complete
|
||||
mxc_uart_complete_cb_t callback; ///< Pointer to function called when transaction is complete
|
||||
};
|
||||
|
||||
/***** Function Prototypes *****/
|
||||
|
|
@ -163,7 +162,7 @@ struct _mxc_uart_req_t {
|
|||
* @return If successful, the actual clock frequency is returned. Otherwise, see
|
||||
* \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_Init (mxc_uart_regs_t* uart, unsigned int baud, sys_map_t map);
|
||||
int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, sys_map_t map);
|
||||
|
||||
/**
|
||||
* @brief Disable and shutdown UART peripheral.
|
||||
|
|
@ -172,7 +171,7 @@ int MXC_UART_Init (mxc_uart_regs_t* uart, unsigned int baud, sys_map_t map);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_Shutdown (mxc_uart_regs_t* uart);
|
||||
int MXC_UART_Shutdown(mxc_uart_regs_t *uart);
|
||||
|
||||
/**
|
||||
* @brief Checks if the given UART bus can be placed in sleep more.
|
||||
|
|
@ -186,7 +185,7 @@ int MXC_UART_Shutdown (mxc_uart_regs_t* uart);
|
|||
* @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref
|
||||
* MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_UART_ReadyForSleep (mxc_uart_regs_t* uart);
|
||||
int MXC_UART_ReadyForSleep(mxc_uart_regs_t *uart);
|
||||
|
||||
/**
|
||||
* @brief Set the frequency of the UART interface.
|
||||
|
|
@ -199,7 +198,7 @@ int MXC_UART_ReadyForSleep (mxc_uart_regs_t* uart);
|
|||
* @return Negative if error, otherwise actual speed set. See \ref
|
||||
* MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_UART_SetFrequency (mxc_uart_regs_t* uart, unsigned int baud);
|
||||
int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud);
|
||||
|
||||
/**
|
||||
* @brief Get the frequency of the UART interface.
|
||||
|
|
@ -210,7 +209,7 @@ int MXC_UART_SetFrequency (mxc_uart_regs_t* uart, unsigned int baud);
|
|||
*
|
||||
* @return The UART baud rate
|
||||
*/
|
||||
int MXC_UART_GetFrequency (mxc_uart_regs_t* uart);
|
||||
int MXC_UART_GetFrequency(mxc_uart_regs_t *uart);
|
||||
|
||||
/**
|
||||
* @brief Sets the number of bits per character
|
||||
|
|
@ -220,7 +219,7 @@ int MXC_UART_GetFrequency (mxc_uart_regs_t* uart);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_SetDataSize (mxc_uart_regs_t* uart, int dataSize);
|
||||
int MXC_UART_SetDataSize(mxc_uart_regs_t *uart, int dataSize);
|
||||
|
||||
/**
|
||||
* @brief Sets the number of stop bits sent at the end of a character
|
||||
|
|
@ -230,7 +229,7 @@ int MXC_UART_SetDataSize (mxc_uart_regs_t* uart, int dataSize);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_SetStopBits (mxc_uart_regs_t* uart, mxc_uart_stop_t stopBits);
|
||||
int MXC_UART_SetStopBits(mxc_uart_regs_t *uart, mxc_uart_stop_t stopBits);
|
||||
|
||||
/**
|
||||
* @brief Sets the type of parity generation used
|
||||
|
|
@ -240,7 +239,7 @@ int MXC_UART_SetStopBits (mxc_uart_regs_t* uart, mxc_uart_stop_t stopBits);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_SetParity (mxc_uart_regs_t* uart, mxc_uart_parity_t parity);
|
||||
int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity);
|
||||
|
||||
/**
|
||||
* @brief Sets the flow control used
|
||||
|
|
@ -251,7 +250,7 @@ int MXC_UART_SetParity (mxc_uart_regs_t* uart, mxc_uart_parity_t parity);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_SetFlowCtrl (mxc_uart_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold);
|
||||
int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold);
|
||||
|
||||
/**
|
||||
* @brief Sets the clock source for the baud rate generator
|
||||
|
|
@ -265,7 +264,7 @@ int MXC_UART_SetFlowCtrl (mxc_uart_regs_t* uart, mxc_uart_flow_t flowCtrl, int r
|
|||
* @return Actual baud rate if successful, otherwise see \ref MXC_Error_Codes
|
||||
* for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_SetClockSource (mxc_uart_regs_t* uart, int usePCLK);
|
||||
int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, int usePCLK);
|
||||
|
||||
/**
|
||||
* @brief Enables or Disables the built-in null modem
|
||||
|
|
@ -276,7 +275,7 @@ int MXC_UART_SetClockSource (mxc_uart_regs_t* uart, int usePCLK);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_SetNullModem (mxc_uart_regs_t* uart, int nullModem);
|
||||
int MXC_UART_SetNullModem(mxc_uart_regs_t *uart, int nullModem);
|
||||
|
||||
/* ************************************************************************* */
|
||||
/* Low-level functions */
|
||||
|
|
@ -289,7 +288,7 @@ int MXC_UART_SetNullModem (mxc_uart_regs_t* uart, int nullModem);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_SendBreak (mxc_uart_regs_t* uart);
|
||||
int MXC_UART_SendBreak(mxc_uart_regs_t *uart);
|
||||
|
||||
/**
|
||||
* @brief Checks the UART Peripheral for an ongoing transmission
|
||||
|
|
@ -300,7 +299,7 @@ int MXC_UART_SendBreak (mxc_uart_regs_t* uart);
|
|||
*
|
||||
* @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_GetActive (mxc_uart_regs_t* uart);
|
||||
int MXC_UART_GetActive(mxc_uart_regs_t *uart);
|
||||
|
||||
/**
|
||||
* @brief Aborts an ongoing UART Transmission
|
||||
|
|
@ -309,7 +308,7 @@ int MXC_UART_GetActive (mxc_uart_regs_t* uart);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_AbortTransmission (mxc_uart_regs_t* uart);
|
||||
int MXC_UART_AbortTransmission(mxc_uart_regs_t *uart);
|
||||
|
||||
/**
|
||||
* @brief Reads the next available character. This function will block until a character
|
||||
|
|
@ -319,7 +318,7 @@ int MXC_UART_AbortTransmission (mxc_uart_regs_t* uart);
|
|||
*
|
||||
* @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_ReadCharacter (mxc_uart_regs_t* uart);
|
||||
int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart);
|
||||
|
||||
/**
|
||||
* @brief Writes a character on the UART. This function will block until the character
|
||||
|
|
@ -330,7 +329,7 @@ int MXC_UART_ReadCharacter (mxc_uart_regs_t* uart);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_WriteCharacter (mxc_uart_regs_t* uart, uint8_t character);
|
||||
int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character);
|
||||
|
||||
/**
|
||||
* @brief Reads the next available character. If no character is available, this function
|
||||
|
|
@ -340,7 +339,7 @@ int MXC_UART_WriteCharacter (mxc_uart_regs_t* uart, uint8_t character);
|
|||
*
|
||||
* @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_ReadCharacterRaw (mxc_uart_regs_t* uart);
|
||||
int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart);
|
||||
|
||||
/**
|
||||
* @brief Writes a character on the UART. If the character cannot be written because the
|
||||
|
|
@ -351,7 +350,7 @@ int MXC_UART_ReadCharacterRaw (mxc_uart_regs_t* uart);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_WriteCharacterRaw (mxc_uart_regs_t* uart, uint8_t character);
|
||||
int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character);
|
||||
|
||||
/**
|
||||
* @brief Reads the next available character
|
||||
|
|
@ -364,7 +363,7 @@ int MXC_UART_WriteCharacterRaw (mxc_uart_regs_t* uart, uint8_t character);
|
|||
*
|
||||
* @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_Read (mxc_uart_regs_t* uart, uint8_t* buffer, int* len);
|
||||
int MXC_UART_Read(mxc_uart_regs_t *uart, uint8_t *buffer, int *len);
|
||||
|
||||
/**
|
||||
* @brief Writes a byte on the UART
|
||||
|
|
@ -375,7 +374,7 @@ int MXC_UART_Read (mxc_uart_regs_t* uart, uint8_t* buffer, int* len);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_Write (mxc_uart_regs_t* uart, uint8_t* byte, int* len);
|
||||
int MXC_UART_Write(mxc_uart_regs_t *uart, uint8_t *byte, int *len);
|
||||
|
||||
/**
|
||||
* @brief Unloads bytes from the receive FIFO.
|
||||
|
|
@ -386,9 +385,8 @@ int MXC_UART_Write (mxc_uart_regs_t* uart, uint8_t* byte, int* len);
|
|||
*
|
||||
* @return The number of bytes actually read.
|
||||
*/
|
||||
unsigned int MXC_UART_ReadRXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes,
|
||||
unsigned int len);
|
||||
|
||||
unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len);
|
||||
|
||||
/**
|
||||
* @brief Unloads bytes from the receive FIFO user DMA for longer reads.
|
||||
*
|
||||
|
|
@ -399,9 +397,9 @@ unsigned int MXC_UART_ReadRXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes,
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for a list of return values
|
||||
*/
|
||||
int MXC_UART_ReadRXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes,
|
||||
unsigned int len, mxc_uart_dma_complete_cb_t callback);
|
||||
|
||||
int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len,
|
||||
mxc_uart_dma_complete_cb_t callback);
|
||||
|
||||
/**
|
||||
* @brief Get the number of bytes currently available in the receive FIFO.
|
||||
*
|
||||
|
|
@ -409,7 +407,7 @@ int MXC_UART_ReadRXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes,
|
|||
*
|
||||
* @return The number of bytes available.
|
||||
*/
|
||||
unsigned int MXC_UART_GetRXFIFOAvailable (mxc_uart_regs_t* uart);
|
||||
unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart);
|
||||
|
||||
/**
|
||||
* @brief Loads bytes into the transmit FIFO.
|
||||
|
|
@ -420,9 +418,8 @@ unsigned int MXC_UART_GetRXFIFOAvailable (mxc_uart_regs_t* uart);
|
|||
*
|
||||
* @return The number of bytes actually written.
|
||||
*/
|
||||
unsigned int MXC_UART_WriteTXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes,
|
||||
unsigned int len);
|
||||
|
||||
unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len);
|
||||
|
||||
/**
|
||||
* @brief Loads bytes into the transmit FIFO using DMA for longer writes
|
||||
*
|
||||
|
|
@ -433,9 +430,9 @@ unsigned int MXC_UART_WriteTXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes,
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for a list of return values
|
||||
*/
|
||||
int MXC_UART_WriteTXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes,
|
||||
unsigned int len, mxc_uart_dma_complete_cb_t callback);
|
||||
|
||||
int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len,
|
||||
mxc_uart_dma_complete_cb_t callback);
|
||||
|
||||
/**
|
||||
* @brief Get the amount of free space available in the transmit FIFO.
|
||||
*
|
||||
|
|
@ -443,7 +440,7 @@ int MXC_UART_WriteTXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes,
|
|||
*
|
||||
* @return The number of bytes available.
|
||||
*/
|
||||
unsigned int MXC_UART_GetTXFIFOAvailable (mxc_uart_regs_t* uart);
|
||||
unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart);
|
||||
|
||||
/**
|
||||
* @brief Removes and discards all bytes currently in the receive FIFO.
|
||||
|
|
@ -452,7 +449,7 @@ unsigned int MXC_UART_GetTXFIFOAvailable (mxc_uart_regs_t* uart);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_UART_ClearRXFIFO (mxc_uart_regs_t* uart);
|
||||
int MXC_UART_ClearRXFIFO(mxc_uart_regs_t *uart);
|
||||
|
||||
/**
|
||||
* @brief Removes and discards all bytes currently in the transmit FIFO.
|
||||
|
|
@ -461,7 +458,7 @@ int MXC_UART_ClearRXFIFO (mxc_uart_regs_t* uart);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_UART_ClearTXFIFO (mxc_uart_regs_t* uart);
|
||||
int MXC_UART_ClearTXFIFO(mxc_uart_regs_t *uart);
|
||||
|
||||
/**
|
||||
* @brief Set the receive threshold level.
|
||||
|
|
@ -480,7 +477,7 @@ int MXC_UART_ClearTXFIFO (mxc_uart_regs_t* uart);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_SetRXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes);
|
||||
int MXC_UART_SetRXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes);
|
||||
|
||||
/**
|
||||
* @brief Get the current receive threshold level.
|
||||
|
|
@ -489,7 +486,7 @@ int MXC_UART_SetRXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes);
|
|||
*
|
||||
* @return The receive threshold value (in bytes).
|
||||
*/
|
||||
unsigned int MXC_UART_GetRXThreshold (mxc_uart_regs_t* uart);
|
||||
unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t *uart);
|
||||
|
||||
/**
|
||||
* @brief Set the transmit threshold level.
|
||||
|
|
@ -508,7 +505,7 @@ unsigned int MXC_UART_GetRXThreshold (mxc_uart_regs_t* uart);
|
|||
*
|
||||
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
|
||||
*/
|
||||
int MXC_UART_SetTXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes);
|
||||
int MXC_UART_SetTXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes);
|
||||
|
||||
/**
|
||||
* @brief Get the current transmit threshold level.
|
||||
|
|
@ -517,7 +514,7 @@ int MXC_UART_SetTXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes);
|
|||
*
|
||||
* @return The transmit threshold value (in bytes).
|
||||
*/
|
||||
unsigned int MXC_UART_GetTXThreshold (mxc_uart_regs_t* uart);
|
||||
unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart);
|
||||
|
||||
/**
|
||||
* @brief Gets the interrupt flags that are currently set
|
||||
|
|
@ -529,7 +526,7 @@ unsigned int MXC_UART_GetTXThreshold (mxc_uart_regs_t* uart);
|
|||
*
|
||||
* @return The interrupt flags
|
||||
*/
|
||||
unsigned int MXC_UART_GetFlags (mxc_uart_regs_t* uart);
|
||||
unsigned int MXC_UART_GetFlags(mxc_uart_regs_t *uart);
|
||||
|
||||
/**
|
||||
* @brief Clears the interrupt flags that are currently set
|
||||
|
|
@ -542,7 +539,7 @@ unsigned int MXC_UART_GetFlags (mxc_uart_regs_t* uart);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_UART_ClearFlags (mxc_uart_regs_t* uart, unsigned int flags);
|
||||
int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags);
|
||||
|
||||
/**
|
||||
* @brief Enables specific interrupts
|
||||
|
|
@ -555,7 +552,7 @@ int MXC_UART_ClearFlags (mxc_uart_regs_t* uart, unsigned int flags);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_UART_EnableInt (mxc_uart_regs_t* uart, unsigned int mask);
|
||||
int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int mask);
|
||||
|
||||
/**
|
||||
* @brief Disables specific interrupts
|
||||
|
|
@ -568,7 +565,7 @@ int MXC_UART_EnableInt (mxc_uart_regs_t* uart, unsigned int mask);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_UART_DisableInt (mxc_uart_regs_t* uart, unsigned int mask);
|
||||
int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int mask);
|
||||
|
||||
/**
|
||||
* @brief Gets the status flags that are currently set
|
||||
|
|
@ -577,9 +574,9 @@ int MXC_UART_DisableInt (mxc_uart_regs_t* uart, unsigned int mask);
|
|||
*
|
||||
* @return The status flags
|
||||
*/
|
||||
unsigned int MXC_UART_GetStatus (mxc_uart_regs_t* uart);
|
||||
unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart);
|
||||
|
||||
int MXC_UART_Busy(mxc_uart_regs_t* uart);
|
||||
int MXC_UART_Busy(mxc_uart_regs_t *uart);
|
||||
|
||||
/* ************************************************************************* */
|
||||
/* Transaction level functions */
|
||||
|
|
@ -596,7 +593,7 @@ int MXC_UART_Busy(mxc_uart_regs_t* uart);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_UART_Transaction (mxc_uart_req_t* req);
|
||||
int MXC_UART_Transaction(mxc_uart_req_t *req);
|
||||
|
||||
/**
|
||||
* @brief Setup an interrupt-driven UART transaction
|
||||
|
|
@ -608,7 +605,7 @@ int MXC_UART_Transaction (mxc_uart_req_t* req);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_UART_TransactionAsync (mxc_uart_req_t* req);
|
||||
int MXC_UART_TransactionAsync(mxc_uart_req_t *req);
|
||||
|
||||
/**
|
||||
* @brief Setup a DMA driven UART transaction
|
||||
|
|
@ -623,7 +620,7 @@ int MXC_UART_TransactionAsync (mxc_uart_req_t* req);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_UART_TransactionDMA (mxc_uart_req_t* req);
|
||||
int MXC_UART_TransactionDMA(mxc_uart_req_t *req);
|
||||
|
||||
/**
|
||||
* @brief The processing function for DMA transactions.
|
||||
|
|
@ -634,7 +631,7 @@ int MXC_UART_TransactionDMA (mxc_uart_req_t* req);
|
|||
* @param ch DMA channel
|
||||
* @param error Error status
|
||||
*/
|
||||
void MXC_UART_DMACallback (int ch, int error);
|
||||
void MXC_UART_DMACallback(int ch, int error);
|
||||
|
||||
/**
|
||||
* @brief Async callback
|
||||
|
|
@ -644,7 +641,9 @@ void MXC_UART_DMACallback (int ch, int error);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_UART_AsyncCallback (mxc_uart_regs_t* uart, int retVal);
|
||||
int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal);
|
||||
int MXC_UART_TxAsyncCallback(mxc_uart_regs_t *uart, int retVal);
|
||||
int MXC_UART_RxAsyncCallback(mxc_uart_regs_t *uart, int retVal);
|
||||
|
||||
/**
|
||||
* @brief stop any async callbacks
|
||||
|
|
@ -653,7 +652,9 @@ int MXC_UART_AsyncCallback (mxc_uart_regs_t* uart, int retVal);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_UART_AsyncStop (mxc_uart_regs_t* uart);
|
||||
int MXC_UART_AsyncStop(mxc_uart_regs_t *uart);
|
||||
int MXC_UART_TxAsyncStop(mxc_uart_regs_t *uart);
|
||||
int MXC_UART_RxAsyncStop(mxc_uart_regs_t *uart);
|
||||
|
||||
/**
|
||||
* @brief Abort any asynchronous requests in progress.
|
||||
|
|
@ -666,7 +667,9 @@ int MXC_UART_AsyncStop (mxc_uart_regs_t* uart);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_UART_AbortAsync (mxc_uart_regs_t* uart);
|
||||
int MXC_UART_AbortAsync(mxc_uart_regs_t *uart);
|
||||
int MXC_UART_TxAbortAsync(mxc_uart_regs_t *uart);
|
||||
int MXC_UART_RxAbortAsync(mxc_uart_regs_t *uart);
|
||||
|
||||
/**
|
||||
* @brief The processing function for asynchronous transactions.
|
||||
|
|
@ -679,7 +682,25 @@ int MXC_UART_AbortAsync (mxc_uart_regs_t* uart);
|
|||
*
|
||||
* @return See \ref MXC_Error_Codes for the list of error return codes.
|
||||
*/
|
||||
int MXC_UART_AsyncHandler (mxc_uart_regs_t* uart);
|
||||
int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart);
|
||||
|
||||
/**
|
||||
* @brief Provide TXCount for asynchronous transactions..
|
||||
*
|
||||
* @param uart Pointer to UART registers (selects the UART block used.)
|
||||
*
|
||||
* @return Returns transmit bytes (in FIFO).
|
||||
*/
|
||||
uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req);
|
||||
|
||||
/**
|
||||
* @brief Provide RXCount for asynchronous transactions..
|
||||
*
|
||||
* @param uart Pointer to UART registers (selects the UART block used.)
|
||||
*
|
||||
* @return Returns receive bytes (in FIFO).
|
||||
*/
|
||||
uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t *req);
|
||||
|
||||
/**@} end of group uart */
|
||||
|
||||
|
|
@ -687,4 +708,4 @@ int MXC_UART_AsyncHandler (mxc_uart_regs_t* uart);
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_UART_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_UART_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Watchdog timer (WDT) function prototypes and data types.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +34,11 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _WDT_H_
|
||||
#define _WDT_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_WDT_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_WDT_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -60,22 +60,22 @@ extern "C" {
|
|||
/** @brief Watchdog period enumeration.
|
||||
Used to configure the period of the watchdog interrupt */
|
||||
typedef enum {
|
||||
MXC_WDT_PERIOD_2_31 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31, ///< Period 2^31
|
||||
MXC_WDT_PERIOD_2_30 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30, ///< Period 2^30
|
||||
MXC_WDT_PERIOD_2_29 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29, ///< Period 2^29
|
||||
MXC_WDT_PERIOD_2_28 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28, ///< Period 2^28
|
||||
MXC_WDT_PERIOD_2_27 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27, ///< Period 2^27
|
||||
MXC_WDT_PERIOD_2_26 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26, ///< Period 2^26
|
||||
MXC_WDT_PERIOD_2_25 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25, ///< Period 2^25
|
||||
MXC_WDT_PERIOD_2_24 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24, ///< Period 2^24
|
||||
MXC_WDT_PERIOD_2_23 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23, ///< Period 2^23
|
||||
MXC_WDT_PERIOD_2_22 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22, ///< Period 2^22
|
||||
MXC_WDT_PERIOD_2_21 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21, ///< Period 2^21
|
||||
MXC_WDT_PERIOD_2_20 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20, ///< Period 2^20
|
||||
MXC_WDT_PERIOD_2_19 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19, ///< Period 2^19
|
||||
MXC_WDT_PERIOD_2_18 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18, ///< Period 2^18
|
||||
MXC_WDT_PERIOD_2_17 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17, ///< Period 2^17
|
||||
MXC_WDT_PERIOD_2_16 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16, ///< Period 2^16
|
||||
MXC_WDT_PERIOD_2_31 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31, ///< Period 2^31
|
||||
MXC_WDT_PERIOD_2_30 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30, ///< Period 2^30
|
||||
MXC_WDT_PERIOD_2_29 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29, ///< Period 2^29
|
||||
MXC_WDT_PERIOD_2_28 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28, ///< Period 2^28
|
||||
MXC_WDT_PERIOD_2_27 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27, ///< Period 2^27
|
||||
MXC_WDT_PERIOD_2_26 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26, ///< Period 2^26
|
||||
MXC_WDT_PERIOD_2_25 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25, ///< Period 2^25
|
||||
MXC_WDT_PERIOD_2_24 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24, ///< Period 2^24
|
||||
MXC_WDT_PERIOD_2_23 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23, ///< Period 2^23
|
||||
MXC_WDT_PERIOD_2_22 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22, ///< Period 2^22
|
||||
MXC_WDT_PERIOD_2_21 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21, ///< Period 2^21
|
||||
MXC_WDT_PERIOD_2_20 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20, ///< Period 2^20
|
||||
MXC_WDT_PERIOD_2_19 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19, ///< Period 2^19
|
||||
MXC_WDT_PERIOD_2_18 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18, ///< Period 2^18
|
||||
MXC_WDT_PERIOD_2_17 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17, ///< Period 2^17
|
||||
MXC_WDT_PERIOD_2_16 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16, ///< Period 2^16
|
||||
} mxc_wdt_period_t;
|
||||
|
||||
/* **** Function Prototypes **** */
|
||||
|
|
@ -85,96 +85,96 @@ typedef enum {
|
|||
* @param wdt Pointer to the watchdog registers
|
||||
* @return See \ref MXC_Error_Codes for the list of error codes.
|
||||
*/
|
||||
int MXC_WDT_Init (mxc_wdt_regs_t* wdt);
|
||||
int MXC_WDT_Init(mxc_wdt_regs_t *wdt);
|
||||
|
||||
/**
|
||||
* @brief Shutdown the Watchdog Timer
|
||||
* @param wdt Pointer to the watchdog registers
|
||||
* @return See \ref MXC_Error_Codes for the list of error codes.
|
||||
*/
|
||||
int MXC_WDT_Shutdown (mxc_wdt_regs_t* wdt);
|
||||
int MXC_WDT_Shutdown(mxc_wdt_regs_t *wdt);
|
||||
|
||||
/**
|
||||
* @brief Set the period of the watchdog interrupt.
|
||||
* @param wdt Pointer to watchdog registers.
|
||||
* @param period Enumeration of the desired watchdog period.
|
||||
*/
|
||||
void MXC_WDT_SetIntPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_period_t period);
|
||||
void MXC_WDT_SetIntPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_period_t period);
|
||||
|
||||
/**
|
||||
* @brief Set the period of the watchdog reset.
|
||||
* @param wdt Pointer to watchdog registers.
|
||||
* @param period Enumeration of the desired watchdog period.
|
||||
*/
|
||||
void MXC_WDT_SetResetPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_period_t period);
|
||||
void MXC_WDT_SetResetPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_period_t period);
|
||||
|
||||
/**
|
||||
* @brief Enable the watchdog timer.
|
||||
* @param wdt Pointer to watchdog registers.
|
||||
*/
|
||||
void MXC_WDT_Enable (mxc_wdt_regs_t* wdt);
|
||||
void MXC_WDT_Enable(mxc_wdt_regs_t *wdt);
|
||||
|
||||
/**
|
||||
* @brief Disable the watchdog timer.
|
||||
* @param wdt Pointer to watchdog registers.
|
||||
*/
|
||||
void MXC_WDT_Disable (mxc_wdt_regs_t* wdt);
|
||||
void MXC_WDT_Disable(mxc_wdt_regs_t *wdt);
|
||||
|
||||
/**
|
||||
* @brief Enable the watchdog interrupt.
|
||||
* @param wdt Pointer to watchdog registers.
|
||||
*/
|
||||
void MXC_WDT_EnableInt (mxc_wdt_regs_t* wdt);
|
||||
void MXC_WDT_EnableInt(mxc_wdt_regs_t *wdt);
|
||||
|
||||
/**
|
||||
* @brief Enable the watchdog reset.
|
||||
* @param wdt Pointer to watchdog registers.
|
||||
*/
|
||||
void MXC_WDT_EnableReset (mxc_wdt_regs_t* wdt);
|
||||
void MXC_WDT_EnableReset(mxc_wdt_regs_t *wdt);
|
||||
|
||||
/**
|
||||
* @brief Enable the watchdog interrupt.
|
||||
* @param wdt Pointer to watchdog registers.
|
||||
*/
|
||||
void MXC_WDT_DisableInt (mxc_wdt_regs_t* wdt);
|
||||
void MXC_WDT_DisableInt(mxc_wdt_regs_t *wdt);
|
||||
|
||||
/**
|
||||
* @brief Enable the watchdog reset.
|
||||
* @param wdt Pointer to watchdog registers.
|
||||
*/
|
||||
void MXC_WDT_DisableReset (mxc_wdt_regs_t* wdt);
|
||||
void MXC_WDT_DisableReset(mxc_wdt_regs_t *wdt);
|
||||
|
||||
/**
|
||||
* @brief Reset the watchdog timer.
|
||||
* @param wdt Pointer to watchdog registers.
|
||||
*/
|
||||
void MXC_WDT_ResetTimer (mxc_wdt_regs_t* wdt);
|
||||
void MXC_WDT_ResetTimer(mxc_wdt_regs_t *wdt);
|
||||
|
||||
/**
|
||||
* @brief Get the status of the reset flag.
|
||||
* @param wdt Pointer to watchdog registers.
|
||||
* @returns 1 if the previous reset was caused by the watchdog, 0 otherwise.
|
||||
*/
|
||||
int MXC_WDT_GetResetFlag (mxc_wdt_regs_t* wdt);
|
||||
int MXC_WDT_GetResetFlag(mxc_wdt_regs_t *wdt);
|
||||
|
||||
/**
|
||||
* @brief Clears the reset flag.
|
||||
* @param wdt Pointer to watchdog registers.
|
||||
*/
|
||||
void MXC_WDT_ClearResetFlag (mxc_wdt_regs_t* wdt);
|
||||
void MXC_WDT_ClearResetFlag(mxc_wdt_regs_t *wdt);
|
||||
|
||||
/**
|
||||
* @brief Get the status of the interrupt flag.
|
||||
* @param wdt Pointer to watchdog registers.
|
||||
* @returns 1 if the interrupt is pending, 0 otherwise.
|
||||
*/
|
||||
int MXC_WDT_GetIntFlag (mxc_wdt_regs_t* wdt);
|
||||
int MXC_WDT_GetIntFlag(mxc_wdt_regs_t *wdt);
|
||||
|
||||
/**
|
||||
* @brief Clears the interrupt flag.
|
||||
* @param wdt Pointer to watchdog registers.
|
||||
*/
|
||||
void MXC_WDT_ClearIntFlag (mxc_wdt_regs_t* wdt);
|
||||
void MXC_WDT_ClearIntFlag(mxc_wdt_regs_t *wdt);
|
||||
|
||||
/**@} end of group wdt */
|
||||
|
||||
|
|
@ -182,4 +182,4 @@ void MXC_WDT_ClearIntFlag (mxc_wdt_regs_t* wdt);
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _WDT_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_WDT_H_
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files(the "Software"),
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/****** Includes *******/
|
||||
#include <stddef.h>
|
||||
|
|
@ -51,17 +51,17 @@
|
|||
|
||||
int MXC_DMA_Init(void)
|
||||
{
|
||||
if(!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA)) {
|
||||
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA);
|
||||
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA);
|
||||
}
|
||||
|
||||
return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t*) MXC_DMA);
|
||||
if (!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA)) {
|
||||
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA);
|
||||
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA);
|
||||
}
|
||||
|
||||
return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t *)MXC_DMA);
|
||||
}
|
||||
|
||||
int MXC_DMA_AcquireChannel(void)
|
||||
{
|
||||
return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t*) MXC_DMA);
|
||||
return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t *)MXC_DMA);
|
||||
}
|
||||
|
||||
int MXC_DMA_ReleaseChannel(int ch)
|
||||
|
|
@ -80,7 +80,7 @@ int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig)
|
|||
}
|
||||
|
||||
int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst)
|
||||
{
|
||||
{
|
||||
return MXC_DMA_RevA_SetSrcDst(srcdst);
|
||||
}
|
||||
|
||||
|
|
@ -99,14 +99,14 @@ int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdst)
|
|||
return MXC_DMA_RevA_GetSrcReload(srcdst);
|
||||
}
|
||||
|
||||
int MXC_DMA_SetCallback(int ch, void(*callback)(int, int))
|
||||
int MXC_DMA_SetCallback(int ch, void (*callback)(int, int))
|
||||
{
|
||||
return MXC_DMA_RevA_SetCallback(ch, callback);
|
||||
}
|
||||
|
||||
int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz)
|
||||
{
|
||||
return MXC_DMA_RevA_SetChannelInterruptEn(ch, chdis, ctz);
|
||||
return MXC_DMA_RevA_SetChannelInterruptEn(ch, chdis, ctz);
|
||||
}
|
||||
|
||||
int MXC_DMA_ChannelEnableInt(int ch, int flags)
|
||||
|
|
@ -131,12 +131,12 @@ int MXC_DMA_ChannelClearFlags(int ch, int flags)
|
|||
|
||||
int MXC_DMA_EnableInt(int ch)
|
||||
{
|
||||
return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t*) MXC_DMA, ch);
|
||||
return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch);
|
||||
}
|
||||
|
||||
int MXC_DMA_DisableInt(int ch)
|
||||
{
|
||||
return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t*) MXC_DMA, ch);
|
||||
return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch);
|
||||
}
|
||||
|
||||
int MXC_DMA_Start(int ch)
|
||||
|
|
@ -149,23 +149,23 @@ int MXC_DMA_Stop(int ch)
|
|||
return MXC_DMA_RevA_Stop(ch);
|
||||
}
|
||||
|
||||
mxc_dma_ch_regs_t* MXC_DMA_GetCHRegs(int ch)
|
||||
mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch)
|
||||
{
|
||||
return MXC_DMA_RevA_GetCHRegs(ch);
|
||||
}
|
||||
|
||||
void MXC_DMA_Handler(void)
|
||||
{
|
||||
MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t*) MXC_DMA);
|
||||
MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t *)MXC_DMA);
|
||||
}
|
||||
|
||||
int MXC_DMA_MemCpy(void* dest, void* src, int len, mxc_dma_complete_cb_t callback)
|
||||
int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback)
|
||||
{
|
||||
return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t*) MXC_DMA, dest, src, len, callback);
|
||||
return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)MXC_DMA, dest, src, len, callback);
|
||||
}
|
||||
|
||||
int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback)
|
||||
int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst,
|
||||
mxc_dma_trans_chain_t callback)
|
||||
{
|
||||
return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t*) MXC_DMA, config, firstSrcDst, callback);
|
||||
return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t *)MXC_DMA, config, firstSrcDst, callback);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files(the "Software"),
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
|
|
@ -29,10 +29,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
#ifdef __CC_ARM // Keil
|
||||
#pragma diag_suppress 68 // integer conversion resulted in a change of sign
|
||||
#endif
|
||||
******************************************************************************/
|
||||
|
||||
/****** Includes *******/
|
||||
#include <stddef.h>
|
||||
|
|
@ -46,29 +43,26 @@
|
|||
#include "dma_reva_regs.h"
|
||||
|
||||
/***** Definitions *****/
|
||||
#define CHECK_HANDLE(x)((x >= 0) && (x < MXC_DMA_CHANNELS) && (dma_resource[x].valid))
|
||||
#define CHECK_HANDLE(x) ((x >= 0) && (x < MXC_DMA_CHANNELS) && (dma_resource[x].valid))
|
||||
|
||||
typedef struct {
|
||||
void* userCallback; // user given callback
|
||||
void* dest; // memcpy destination
|
||||
void *userCallback; // user given callback
|
||||
void *dest; // memcpy destination
|
||||
} mxc_dma_highlevel_t;
|
||||
|
||||
typedef struct {
|
||||
unsigned int valid; // Flag to invalidate this resource
|
||||
unsigned int instance; // Hardware instance of this DMA controller
|
||||
unsigned int id; // Channel ID, which matches the index into the underlying hardware
|
||||
mxc_dma_reva_ch_regs_t *regs; // Pointer to the registers for this channel
|
||||
void(*cb)(int, int); // Pointer to a callback function type
|
||||
unsigned int valid; // Flag to invalidate this resource
|
||||
unsigned int instance; // Hardware instance of this DMA controller
|
||||
unsigned int id; // Channel ID, which matches the index into the underlying hardware
|
||||
mxc_dma_reva_ch_regs_t *regs; // Pointer to the registers for this channel
|
||||
void (*cb)(int, int); // Pointer to a callback function type
|
||||
} mxc_dma_channel_t;
|
||||
|
||||
/******* Globals *******/
|
||||
static unsigned int dma_initialized[MXC_DMA_INSTANCES] = {0};
|
||||
static unsigned int dma_initialized[MXC_DMA_INSTANCES] = { 0 };
|
||||
static mxc_dma_channel_t dma_resource[MXC_DMA_CHANNELS];
|
||||
static mxc_dma_highlevel_t memcpy_resource[MXC_DMA_CHANNELS];
|
||||
|
||||
#if USE_LOCK_IN_DRIVERS
|
||||
static uint32_t dma_lock;
|
||||
#endif
|
||||
static uint32_t dma_lock;
|
||||
|
||||
/****** Functions ******/
|
||||
static void memcpy_callback(int ch, int error);
|
||||
|
|
@ -79,59 +73,59 @@ int MXC_DMA_RevA_Init(mxc_dma_reva_regs_t *dma)
|
|||
int i, numCh, offset;
|
||||
#if TARGET_NUM == 32665
|
||||
numCh = MXC_DMA_CH_OFFSET;
|
||||
offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma);
|
||||
offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma);
|
||||
#else
|
||||
numCh = MXC_DMA_CHANNELS;
|
||||
offset = 0;
|
||||
#endif
|
||||
|
||||
if(dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]) {
|
||||
|
||||
if (dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma)]) {
|
||||
return E_BAD_STATE;
|
||||
}
|
||||
|
||||
|
||||
#ifndef __riscv
|
||||
/* Initialize mutex */
|
||||
MXC_FreeLock(&dma_lock);
|
||||
|
||||
if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) {
|
||||
return E_BUSY;
|
||||
}
|
||||
/* Initialize mutex */
|
||||
MXC_FreeLock(&dma_lock);
|
||||
|
||||
if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) {
|
||||
return E_BUSY;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* Ensure all channels are disabled at start, clear flags, init handles */
|
||||
dma->inten = 0;
|
||||
|
||||
for(i = offset; i < (offset + numCh); i++) {
|
||||
|
||||
for (i = offset; i < (offset + numCh); i++) {
|
||||
dma_resource[i].valid = 0;
|
||||
dma_resource[i].instance = 0;
|
||||
dma_resource[i].id = i;
|
||||
dma_resource[i].regs = (mxc_dma_reva_ch_regs_t*) &(dma->ch[(i % numCh)]);
|
||||
dma_resource[i].regs = (mxc_dma_reva_ch_regs_t *)&(dma->ch[(i % numCh)]);
|
||||
dma_resource[i].regs->ctrl = 0;
|
||||
dma_resource[i].regs->status = dma_resource[i].regs->status;
|
||||
|
||||
|
||||
dma_resource[i].cb = NULL;
|
||||
}
|
||||
|
||||
dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]++;
|
||||
|
||||
dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma)]++;
|
||||
#ifndef __riscv
|
||||
MXC_FreeLock(&dma_lock);
|
||||
MXC_FreeLock(&dma_lock);
|
||||
#endif
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma)
|
||||
int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t *dma)
|
||||
{
|
||||
int i, channel, numCh, offset;
|
||||
|
||||
|
||||
/* Check for initialization */
|
||||
if(!dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]) {
|
||||
if (!dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma)]) {
|
||||
return E_BAD_STATE;
|
||||
}
|
||||
|
||||
|
||||
#if TARGET_NUM == 32665
|
||||
numCh = MXC_DMA_CH_OFFSET;
|
||||
offset = MXC_DMA_CH_OFFSET * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma);
|
||||
offset = MXC_DMA_CH_OFFSET * MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma);
|
||||
#else
|
||||
numCh = MXC_DMA_CHANNELS;
|
||||
offset = 0;
|
||||
|
|
@ -139,15 +133,15 @@ int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma)
|
|||
|
||||
#ifndef __riscv
|
||||
/* If DMA is locked return busy */
|
||||
if(MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) {
|
||||
if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) {
|
||||
return E_BUSY;
|
||||
}
|
||||
#endif
|
||||
/* Default is no channel available */
|
||||
channel = E_NONE_AVAIL;
|
||||
|
||||
for(i = offset; i < (offset + numCh); i++) {
|
||||
if(!dma_resource[i].valid) {
|
||||
|
||||
for (i = offset; i < (offset + numCh); i++) {
|
||||
if (!dma_resource[i].valid) {
|
||||
/* Found one */
|
||||
channel = i;
|
||||
dma_resource[i].valid = 1;
|
||||
|
|
@ -165,159 +159,142 @@ int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma)
|
|||
|
||||
int MXC_DMA_RevA_ReleaseChannel(int ch)
|
||||
{
|
||||
if(CHECK_HANDLE(ch)) {
|
||||
if(MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) {
|
||||
if (CHECK_HANDLE(ch)) {
|
||||
if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
||||
dma_resource[ch].valid = 0;
|
||||
dma_resource[ch].regs->ctrl = 0;
|
||||
dma_resource[ch].regs->status = dma_resource[ch].regs->status;
|
||||
MXC_FreeLock(&dma_lock);
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_DMA_RevA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst)
|
||||
{
|
||||
if(CHECK_HANDLE(config.ch)) {
|
||||
if (CHECK_HANDLE(config.ch)) {
|
||||
/* Designed to be safe, not speedy. Should not be called often */
|
||||
dma_resource[config.ch].regs->ctrl =
|
||||
((config.srcinc_en ? MXC_F_DMA_REVA_CTRL_SRCINC : 0) |
|
||||
(config.dstinc_en ? MXC_F_DMA_REVA_CTRL_DSTINC : 0) |
|
||||
config.reqsel |
|
||||
(config.srcwd << MXC_F_DMA_REVA_CTRL_SRCWD_POS) |
|
||||
(config.dstwd << MXC_F_DMA_REVA_CTRL_DSTWD_POS));
|
||||
}
|
||||
else {
|
||||
((config.srcinc_en ? MXC_F_DMA_REVA_CTRL_SRCINC : 0) |
|
||||
(config.dstinc_en ? MXC_F_DMA_REVA_CTRL_DSTINC : 0) | config.reqsel |
|
||||
(config.srcwd << MXC_F_DMA_REVA_CTRL_SRCWD_POS) |
|
||||
(config.dstwd << MXC_F_DMA_REVA_CTRL_DSTWD_POS));
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return MXC_DMA_RevA_SetSrcDst(srcdst);
|
||||
}
|
||||
|
||||
|
||||
int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig)
|
||||
{
|
||||
if(CHECK_HANDLE(advConfig.ch) &&(advConfig.burst_size > 0)) {
|
||||
if (CHECK_HANDLE(advConfig.ch) && (advConfig.burst_size > 0)) {
|
||||
dma_resource[advConfig.ch].regs->ctrl &= ~(0x1F00FC0C); // Clear all fields we set here
|
||||
/* Designed to be safe, not speedy. Should not be called often */
|
||||
dma_resource[advConfig.ch].regs->ctrl |=
|
||||
((advConfig.reqwait_en ? MXC_F_DMA_REVA_CTRL_TO_WAIT : 0) |
|
||||
advConfig.prio | advConfig.tosel | advConfig.pssel |
|
||||
(((advConfig.burst_size - 1) << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS) & MXC_F_DMA_REVA_CTRL_BURST_SIZE));
|
||||
}
|
||||
else {
|
||||
((advConfig.reqwait_en ? MXC_F_DMA_REVA_CTRL_TO_WAIT : 0) | advConfig.prio |
|
||||
advConfig.tosel | advConfig.pssel |
|
||||
(((advConfig.burst_size - 1) << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS) &
|
||||
MXC_F_DMA_REVA_CTRL_BURST_SIZE));
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
||||
int MXC_DMA_RevA_SetSrcDst(mxc_dma_srcdst_t srcdst)
|
||||
{
|
||||
if(CHECK_HANDLE(srcdst.ch)) {
|
||||
dma_resource[srcdst.ch].regs->src = (unsigned int) srcdst.source;
|
||||
dma_resource[srcdst.ch].regs->dst = (unsigned int) srcdst.dest;
|
||||
if (CHECK_HANDLE(srcdst.ch)) {
|
||||
dma_resource[srcdst.ch].regs->src = (unsigned int)srcdst.source;
|
||||
dma_resource[srcdst.ch].regs->dst = (unsigned int)srcdst.dest;
|
||||
dma_resource[srcdst.ch].regs->cnt = srcdst.len;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
||||
int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t* srcdst)
|
||||
int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t *srcdst)
|
||||
{
|
||||
if (CHECK_HANDLE(srcdst->ch)) {
|
||||
srcdst->source = (void*) dma_resource[srcdst->ch].regs->src;
|
||||
srcdst->dest = (void*) dma_resource[srcdst->ch].regs->dst;
|
||||
srcdst->source = (void *)dma_resource[srcdst->ch].regs->src;
|
||||
srcdst->dest = (void *)dma_resource[srcdst->ch].regs->dst;
|
||||
srcdst->len = (dma_resource[srcdst->ch].regs->cnt) & ~MXC_F_DMA_REVA_CNTRLD_EN;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
||||
int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst)
|
||||
{
|
||||
if(CHECK_HANDLE(srcdst.ch)) {
|
||||
dma_resource[srcdst.ch].regs->srcrld = (unsigned int) srcdst.source;
|
||||
dma_resource[srcdst.ch].regs->dstrld = (unsigned int) srcdst.dest;
|
||||
|
||||
if(dma_resource[srcdst.ch].regs->ctrl & MXC_F_DMA_REVA_CTRL_EN) {
|
||||
if (CHECK_HANDLE(srcdst.ch)) {
|
||||
dma_resource[srcdst.ch].regs->srcrld = (unsigned int)srcdst.source;
|
||||
dma_resource[srcdst.ch].regs->dstrld = (unsigned int)srcdst.dest;
|
||||
|
||||
if (dma_resource[srcdst.ch].regs->ctrl & MXC_F_DMA_REVA_CTRL_EN) {
|
||||
/* If channel is already running, set RLDEN to enable next reload */
|
||||
dma_resource[srcdst.ch].regs->cntrld = MXC_F_DMA_REVA_CNTRLD_EN | srcdst.len;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
/* Otherwise, this is the initial setup, so DMA_Start() will handle setting that bit */
|
||||
dma_resource[srcdst.ch].regs->cntrld = srcdst.len;
|
||||
}
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
||||
int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t* srcdst)
|
||||
int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t *srcdst)
|
||||
{
|
||||
if (CHECK_HANDLE(srcdst->ch)) {
|
||||
srcdst->source = (void*) dma_resource[srcdst->ch].regs->srcrld;
|
||||
srcdst->dest = (void*) dma_resource[srcdst->ch].regs->dstrld;
|
||||
srcdst->source = (void *)dma_resource[srcdst->ch].regs->srcrld;
|
||||
srcdst->dest = (void *)dma_resource[srcdst->ch].regs->dstrld;
|
||||
srcdst->len = (dma_resource[srcdst->ch].regs->cntrld) & ~MXC_F_DMA_REVA_CNTRLD_EN;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
||||
int MXC_DMA_RevA_SetCallback(int ch, void(*callback)(int, int))
|
||||
int MXC_DMA_RevA_SetCallback(int ch, void (*callback)(int, int))
|
||||
{
|
||||
if(CHECK_HANDLE(ch)) {
|
||||
if (CHECK_HANDLE(ch)) {
|
||||
/* Callback for interrupt handler, no checking is done, as NULL is valid for(none) */
|
||||
dma_resource[ch].cb = callback;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_DMA_RevA_SetChannelInterruptEn(int ch, bool chdis, bool ctz)
|
||||
{
|
||||
if(CHECK_HANDLE(ch)) {
|
||||
if(chdis){
|
||||
dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_DIS_IE);
|
||||
}
|
||||
if(ctz){
|
||||
dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_CTZ_IE);
|
||||
}
|
||||
}
|
||||
else {
|
||||
if (CHECK_HANDLE(ch)) {
|
||||
if (chdis) {
|
||||
dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_DIS_IE);
|
||||
}
|
||||
if (ctz) {
|
||||
dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_CTZ_IE);
|
||||
}
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
||||
int MXC_DMA_RevA_GetChannelInterruptEn(int ch)
|
||||
{
|
||||
return E_NOT_SUPPORTED;
|
||||
|
|
@ -325,119 +302,111 @@ int MXC_DMA_RevA_GetChannelInterruptEn(int ch)
|
|||
|
||||
int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags)
|
||||
{
|
||||
if(CHECK_HANDLE(ch)) {
|
||||
dma_resource[ch].regs->ctrl |= (flags &(MXC_F_DMA_REVA_CTRL_DIS_IE|MXC_F_DMA_REVA_CTRL_CTZ_IE));
|
||||
}
|
||||
else {
|
||||
if (CHECK_HANDLE(ch)) {
|
||||
dma_resource[ch].regs->ctrl |=
|
||||
(flags & (MXC_F_DMA_REVA_CTRL_DIS_IE | MXC_F_DMA_REVA_CTRL_CTZ_IE));
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags)
|
||||
{
|
||||
if(CHECK_HANDLE(ch)) {
|
||||
dma_resource[ch].regs->ctrl &= ~(flags &(MXC_F_DMA_REVA_CTRL_DIS_IE|MXC_F_DMA_REVA_CTRL_CTZ_IE));
|
||||
}
|
||||
else {
|
||||
if (CHECK_HANDLE(ch)) {
|
||||
dma_resource[ch].regs->ctrl &=
|
||||
~(flags & (MXC_F_DMA_REVA_CTRL_DIS_IE | MXC_F_DMA_REVA_CTRL_CTZ_IE));
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_DMA_RevA_EnableInt(mxc_dma_reva_regs_t *dma, int ch)
|
||||
{
|
||||
if(CHECK_HANDLE(ch)) {
|
||||
#if TARGET_NUM == 32665
|
||||
if (CHECK_HANDLE(ch)) {
|
||||
#if TARGET_NUM == 32665
|
||||
ch %= MXC_DMA_CH_OFFSET;
|
||||
#endif
|
||||
dma->inten |= (1 << ch);
|
||||
}
|
||||
else {
|
||||
#endif
|
||||
dma->inten |= (1 << ch);
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch)
|
||||
{
|
||||
if(CHECK_HANDLE(ch)) {
|
||||
#if TARGET_NUM == 32665
|
||||
if (CHECK_HANDLE(ch)) {
|
||||
#if TARGET_NUM == 32665
|
||||
ch %= MXC_DMA_CH_OFFSET;
|
||||
#endif
|
||||
dma->inten &= ~(1 << ch);
|
||||
}
|
||||
else {
|
||||
#endif
|
||||
dma->inten &= ~(1 << ch);
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_DMA_RevA_ChannelGetFlags(int ch)
|
||||
{
|
||||
if(CHECK_HANDLE(ch)) {
|
||||
if (CHECK_HANDLE(ch)) {
|
||||
return dma_resource[ch].regs->status;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_DMA_RevA_ChannelClearFlags(int ch, int flags)
|
||||
{
|
||||
if(CHECK_HANDLE(ch)) {
|
||||
dma_resource[ch].regs->status |= (flags & 0x5F); // Mask for Interrupt flags
|
||||
}
|
||||
else {
|
||||
if (CHECK_HANDLE(ch)) {
|
||||
dma_resource[ch].regs->status |= (flags & 0x5F); // Mask for Interrupt flags
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_DMA_RevA_Start(int ch)
|
||||
{
|
||||
if(CHECK_HANDLE(ch)) {
|
||||
if (CHECK_HANDLE(ch)) {
|
||||
MXC_DMA_ChannelClearFlags(ch, MXC_DMA_RevA_ChannelGetFlags(ch));
|
||||
|
||||
if(dma_resource[ch].regs->cntrld) {
|
||||
|
||||
if (dma_resource[ch].regs->cntrld) {
|
||||
dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_EN | MXC_F_DMA_REVA_CTRL_RLDEN);
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
dma_resource[ch].regs->ctrl |= MXC_F_DMA_REVA_CTRL_EN;
|
||||
}
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_DMA_RevA_Stop(int ch)
|
||||
{
|
||||
if(CHECK_HANDLE(ch)) {
|
||||
if (CHECK_HANDLE(ch)) {
|
||||
dma_resource[ch].regs->ctrl &= ~MXC_F_DMA_REVA_CTRL_EN;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch)
|
||||
mxc_dma_ch_regs_t *MXC_DMA_RevA_GetCHRegs(int ch)
|
||||
{
|
||||
if(CHECK_HANDLE(ch)) {
|
||||
return(mxc_dma_ch_regs_t*) dma_resource[ch].regs;
|
||||
}
|
||||
else {
|
||||
if (CHECK_HANDLE(ch)) {
|
||||
return (mxc_dma_ch_regs_t *)dma_resource[ch].regs;
|
||||
} else {
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
|
@ -445,17 +414,21 @@ mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch)
|
|||
void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma)
|
||||
{
|
||||
int numCh = MXC_DMA_CHANNELS / MXC_DMA_INSTANCES;
|
||||
int offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma);
|
||||
int offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t *)dma);
|
||||
/* Do callback, if enabled */
|
||||
for(int i = offset; i < (offset + numCh); i++) {
|
||||
if(CHECK_HANDLE(i)) {
|
||||
if(dma->intfl &(0x1 << (i % numCh))) {
|
||||
if(dma_resource[i].cb != NULL) {
|
||||
for (int i = offset; i < (offset + numCh); i++) {
|
||||
if (CHECK_HANDLE(i)) {
|
||||
if (dma->intfl & (0x1 << (i % numCh))) {
|
||||
if (dma_resource[i].cb != NULL) {
|
||||
dma_resource[i].cb(i, E_NO_ERROR);
|
||||
}
|
||||
|
||||
|
||||
MXC_DMA_ChannelClearFlags(i, MXC_DMA_RevA_ChannelGetFlags(i));
|
||||
break;
|
||||
|
||||
// No need to check rest of the channels if no interrupt flags set.
|
||||
if (dma->intfl == 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -464,72 +437,76 @@ void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma)
|
|||
void memcpy_callback(int ch, int error)
|
||||
{
|
||||
mxc_dma_complete_cb_t callback;
|
||||
callback = (mxc_dma_complete_cb_t) memcpy_resource[ch].userCallback;
|
||||
|
||||
if(error != E_NO_ERROR) {
|
||||
callback = (mxc_dma_complete_cb_t)memcpy_resource[ch].userCallback;
|
||||
|
||||
if (error != E_NO_ERROR) {
|
||||
callback(NULL);
|
||||
}
|
||||
|
||||
|
||||
callback(memcpy_resource[ch].dest);
|
||||
|
||||
|
||||
// Release global objects and local resources
|
||||
callback = NULL;
|
||||
memcpy_resource[ch].userCallback = NULL;
|
||||
memcpy_resource[ch].dest = NULL;
|
||||
MXC_DMA_ReleaseChannel(ch);
|
||||
}
|
||||
|
||||
int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len, mxc_dma_complete_cb_t callback)
|
||||
int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len,
|
||||
mxc_dma_complete_cb_t callback)
|
||||
{
|
||||
int retval;
|
||||
mxc_dma_config_t config;
|
||||
mxc_dma_srcdst_t transfer;
|
||||
int channel;
|
||||
|
||||
#if TARGET_NUM == 32665
|
||||
channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t*) dma);
|
||||
#else
|
||||
#if TARGET_NUM == 32665
|
||||
channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t *)dma);
|
||||
#else
|
||||
channel = MXC_DMA_AcquireChannel();
|
||||
#endif
|
||||
|
||||
if(memcpy_resource[channel].userCallback != NULL) {
|
||||
#endif
|
||||
|
||||
if (memcpy_resource[channel].userCallback != NULL) {
|
||||
// We acquired a channel we haven't cleared yet
|
||||
MXC_DMA_ReleaseChannel(channel);
|
||||
return E_UNKNOWN;
|
||||
}
|
||||
|
||||
|
||||
transfer.ch = channel;
|
||||
transfer.source = src;
|
||||
transfer.dest = dest;
|
||||
transfer.len = len;
|
||||
|
||||
|
||||
config.ch = channel;
|
||||
config.reqsel = MXC_DMA_REQUEST_MEMTOMEM;
|
||||
config.srcwd = MXC_DMA_WIDTH_WORD;
|
||||
config.dstwd = MXC_DMA_WIDTH_WORD;
|
||||
config.srcinc_en = 1;
|
||||
config.dstinc_en = 1;
|
||||
|
||||
|
||||
retval = MXC_DMA_ConfigChannel(config, transfer);
|
||||
|
||||
if(retval != E_NO_ERROR) {
|
||||
|
||||
if (retval != E_NO_ERROR) {
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
retval = MXC_DMA_EnableInt(channel);
|
||||
|
||||
if(retval != E_NO_ERROR) {
|
||||
|
||||
if (retval != E_NO_ERROR) {
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_REVA_CTRL_CTZ_IE);
|
||||
|
||||
if(retval != E_NO_ERROR) {
|
||||
|
||||
if (retval != E_NO_ERROR) {
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
MXC_DMA_SetCallback(channel, memcpy_callback);
|
||||
|
||||
memcpy_resource[channel].userCallback = (void*) callback;
|
||||
|
||||
memcpy_resource[channel].userCallback = (void *)callback;
|
||||
memcpy_resource[channel].dest = dest;
|
||||
|
||||
|
||||
return MXC_DMA_Start(channel);
|
||||
}
|
||||
|
||||
|
|
@ -540,46 +517,47 @@ void transfer_callback(int ch, int error)
|
|||
// Call user callback for next transfer
|
||||
// determine whether to load into the transfer slot or reload slot
|
||||
// continue on or stop
|
||||
while(1);
|
||||
while (1) {}
|
||||
}
|
||||
|
||||
int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback)
|
||||
int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config,
|
||||
mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback)
|
||||
{
|
||||
int retval, channel;
|
||||
|
||||
#if TARGET_NUM == 32665
|
||||
channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t*) dma);
|
||||
#else
|
||||
#if TARGET_NUM == 32665
|
||||
channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t *)dma);
|
||||
#else
|
||||
channel = MXC_DMA_AcquireChannel();
|
||||
#endif
|
||||
|
||||
if(memcpy_resource[channel].userCallback != NULL) {
|
||||
#endif
|
||||
|
||||
if (memcpy_resource[channel].userCallback != NULL) {
|
||||
// We acquired a channel we haven't cleared yet
|
||||
MXC_DMA_ReleaseChannel(channel);
|
||||
return E_UNKNOWN;
|
||||
}
|
||||
|
||||
|
||||
retval = MXC_DMA_ConfigChannel(config, firstSrcDst);
|
||||
|
||||
if(retval != E_NO_ERROR) {
|
||||
|
||||
if (retval != E_NO_ERROR) {
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
retval = MXC_DMA_EnableInt(channel);
|
||||
|
||||
if(retval != E_NO_ERROR) {
|
||||
|
||||
if (retval != E_NO_ERROR) {
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_REVA_CTRL_CTZ_IE);
|
||||
|
||||
if(retval != E_NO_ERROR) {
|
||||
|
||||
if (retval != E_NO_ERROR) {
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
MXC_DMA_SetCallback(channel, transfer_callback);
|
||||
|
||||
memcpy_resource[channel].userCallback = (void*) callback;
|
||||
|
||||
|
||||
memcpy_resource[channel].userCallback = (void *)callback;
|
||||
|
||||
return MXC_DMA_Start(channel);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files(the "Software"),
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
|
|
@ -29,7 +29,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVA_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVA_H_
|
||||
|
||||
/****** Includes *******/
|
||||
#include "dma_reva_regs.h"
|
||||
|
|
@ -41,7 +44,7 @@
|
|||
|
||||
/****** Functions ******/
|
||||
int MXC_DMA_RevA_Init(mxc_dma_reva_regs_t *dma);
|
||||
int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma);
|
||||
int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t *dma);
|
||||
int MXC_DMA_RevA_ReleaseChannel(int ch);
|
||||
int MXC_DMA_RevA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst);
|
||||
int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig);
|
||||
|
|
@ -49,7 +52,7 @@ int MXC_DMA_RevA_SetSrcDst(mxc_dma_srcdst_t srcdst);
|
|||
int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t *srcdst);
|
||||
int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst);
|
||||
int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t *srcdst);
|
||||
int MXC_DMA_RevA_SetCallback(int ch, void(*callback)(int, int));
|
||||
int MXC_DMA_RevA_SetCallback(int ch, void (*callback)(int, int));
|
||||
int MXC_DMA_RevA_SetChannelInterruptEn(int ch, bool chdis, bool ctz);
|
||||
int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags);
|
||||
int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags);
|
||||
|
|
@ -59,7 +62,11 @@ int MXC_DMA_RevA_EnableInt(mxc_dma_reva_regs_t *dma, int ch);
|
|||
int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch);
|
||||
int MXC_DMA_RevA_Start(int ch);
|
||||
int MXC_DMA_RevA_Stop(int ch);
|
||||
mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch);
|
||||
mxc_dma_ch_regs_t *MXC_DMA_RevA_GetCHRegs(int ch);
|
||||
void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma);
|
||||
int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len, mxc_dma_complete_cb_t callback);
|
||||
int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback);
|
||||
int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len,
|
||||
mxc_dma_complete_cb_t callback);
|
||||
int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config,
|
||||
mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback);
|
||||
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVA_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,8 +34,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _DMA_REVA_REGS_H_
|
||||
#define _DMA_REVA_REGS_H_
|
||||
|
|
@ -86,14 +85,14 @@ extern "C" {
|
|||
* Structure type to access the DMA Registers.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t ctrl; /**< <tt>\b 0x100:</tt> DMA CTRL Register */
|
||||
__IO uint32_t status; /**< <tt>\b 0x104:</tt> DMA STATUS Register */
|
||||
__IO uint32_t src; /**< <tt>\b 0x108:</tt> DMA SRC Register */
|
||||
__IO uint32_t dst; /**< <tt>\b 0x10C:</tt> DMA DST Register */
|
||||
__IO uint32_t cnt; /**< <tt>\b 0x110:</tt> DMA CNT Register */
|
||||
__IO uint32_t srcrld; /**< <tt>\b 0x114:</tt> DMA SRCRLD Register */
|
||||
__IO uint32_t dstrld; /**< <tt>\b 0x118:</tt> DMA DSTRLD Register */
|
||||
__IO uint32_t cntrld; /**< <tt>\b 0x11C:</tt> DMA CNTRLD Register */
|
||||
__IO uint32_t ctrl; /**< <tt>\b 0x000:</tt> DMA CTRL Register */
|
||||
__IO uint32_t status; /**< <tt>\b 0x004:</tt> DMA STATUS Register */
|
||||
__IO uint32_t src; /**< <tt>\b 0x008:</tt> DMA SRC Register */
|
||||
__IO uint32_t dst; /**< <tt>\b 0x00C:</tt> DMA DST Register */
|
||||
__IO uint32_t cnt; /**< <tt>\b 0x010:</tt> DMA CNT Register */
|
||||
__IO uint32_t srcrld; /**< <tt>\b 0x014:</tt> DMA SRCRLD Register */
|
||||
__IO uint32_t dstrld; /**< <tt>\b 0x018:</tt> DMA DSTRLD Register */
|
||||
__IO uint32_t cntrld; /**< <tt>\b 0x01C:</tt> DMA CNTRLD Register */
|
||||
} mxc_dma_reva_ch_regs_t;
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -110,14 +109,14 @@ typedef struct {
|
|||
* @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_DMA_REVA_CTRL ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
|
||||
#define MXC_R_DMA_REVA_STATUS ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */
|
||||
#define MXC_R_DMA_REVA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */
|
||||
#define MXC_R_DMA_REVA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */
|
||||
#define MXC_R_DMA_REVA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */
|
||||
#define MXC_R_DMA_REVA_SRCRLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */
|
||||
#define MXC_R_DMA_REVA_DSTRLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */
|
||||
#define MXC_R_DMA_REVA_CNTRLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */
|
||||
#define MXC_R_DMA_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
|
||||
#define MXC_R_DMA_REVA_STATUS ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */
|
||||
#define MXC_R_DMA_REVA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */
|
||||
#define MXC_R_DMA_REVA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */
|
||||
#define MXC_R_DMA_REVA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */
|
||||
#define MXC_R_DMA_REVA_SRCRLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */
|
||||
#define MXC_R_DMA_REVA_DSTRLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */
|
||||
#define MXC_R_DMA_REVA_CNTRLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */
|
||||
#define MXC_R_DMA_REVA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_DMA_REVA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_DMA_REVA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**
|
||||
* @file flc.h
|
||||
* @brief Flash Controler driver.
|
||||
* @file flc_common.c
|
||||
* @brief Common functions for the flash controller drivers.
|
||||
* @details This driver can be used to operate on the embedded flash memory.
|
||||
*/
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,8 +34,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <string.h>
|
||||
|
|
@ -43,79 +42,78 @@
|
|||
#include "mxc_assert.h"
|
||||
#include "mxc_sys.h"
|
||||
#include "flc.h"
|
||||
#include "flc_common.h"
|
||||
#include "stdlib.h"
|
||||
|
||||
//******************************************************************************
|
||||
#if IAR_PRAGMAS
|
||||
#pragma section=".flashprog"
|
||||
#pragma section = ".flashprog"
|
||||
#else
|
||||
__attribute__((section(".flashprog")))
|
||||
#endif
|
||||
// Length is number of 32-bit words
|
||||
int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t* data)
|
||||
int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t *data)
|
||||
{
|
||||
volatile uint32_t* ptr;
|
||||
|
||||
|
||||
for (ptr = (uint32_t*) address; ptr < (((uint32_t*)(address)) + length); ptr++, data++) {
|
||||
volatile uint32_t *ptr;
|
||||
|
||||
for (ptr = (uint32_t *)address; ptr < (((uint32_t *)(address)) + length); ptr++, data++) {
|
||||
if (*ptr != *data) {
|
||||
return E_BAD_STATE;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
#if IAR_PRAGMAS
|
||||
#pragma section=".flashprog"
|
||||
#pragma section = ".flashprog"
|
||||
#else
|
||||
__attribute__((section(".flashprog")))
|
||||
#endif
|
||||
// make sure to disable ICC with ICC_Disable(); before Running this function
|
||||
int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t* buffer)
|
||||
int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t *buffer)
|
||||
{
|
||||
int err;
|
||||
uint32_t bytes_written;
|
||||
|
||||
uint32_t current_data_32;
|
||||
uint8_t* current_data = (uint8_t*) ¤t_data_32;
|
||||
uint8_t* buffer8 = (uint8_t*)buffer;
|
||||
uint8_t *current_data = (uint8_t *)¤t_data_32;
|
||||
uint8_t *buffer8 = (uint8_t *)buffer;
|
||||
|
||||
// Align the address to a word boundary and read/write if we have to
|
||||
if (address & 0x3) {
|
||||
|
||||
// Figure out how many bytes we have to write to round up the address
|
||||
bytes_written = 4 - (address & 0x3);
|
||||
|
||||
|
||||
// Save the data currently in the flash
|
||||
memcpy(current_data, (void*)(address & (~0x3)), 4);
|
||||
|
||||
memcpy(current_data, (void *)(address & (~0x3)), 4);
|
||||
|
||||
// Modify current_data to insert the data from buffer
|
||||
memcpy(¤t_data[4 - bytes_written], buffer8, bytes_written);
|
||||
|
||||
|
||||
// Write the modified data
|
||||
if ((err = MXC_FLC_Write32(address - (address % 4), current_data_32)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
address += bytes_written;
|
||||
length -= bytes_written;
|
||||
buffer8 += bytes_written;
|
||||
}
|
||||
|
||||
|
||||
// Align the address to a 4-word (128bit) boundary
|
||||
while ((length >= 4) && ((address & 0xF) != 0)) {
|
||||
memcpy(current_data, buffer8, 4);
|
||||
if ((err = MXC_FLC_Write32(address, current_data_32)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
address += 4;
|
||||
length -= 4;
|
||||
buffer8 += 4;
|
||||
}
|
||||
|
||||
|
||||
if (length >= 16) {
|
||||
uint32_t buff128[4];
|
||||
while (length >= 16) {
|
||||
|
|
@ -123,48 +121,46 @@ int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t* buffer)
|
|||
if ((err = MXC_FLC_Write128(address, buff128)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
address += 16;
|
||||
length -= 16;
|
||||
buffer8 += 16;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
while (length >= 4) {
|
||||
memcpy(current_data, buffer8, 4);
|
||||
if ((err = MXC_FLC_Write32(address, current_data_32)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
address += 4;
|
||||
length -= 4;
|
||||
buffer8 += 4;
|
||||
}
|
||||
|
||||
|
||||
if (length > 0) {
|
||||
// Save the data currently in the flash
|
||||
memcpy(current_data, (void*)(address), 4);
|
||||
|
||||
memcpy(current_data, (void *)(address), 4);
|
||||
|
||||
// Modify current_data to insert the data from buffer
|
||||
memcpy(current_data, buffer8, length);
|
||||
|
||||
|
||||
if ((err = MXC_FLC_Write32(address, current_data_32)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
#if IAR_PRAGMAS
|
||||
#pragma section=".flashprog"
|
||||
#pragma section = ".flashprog"
|
||||
#else
|
||||
__attribute__((section(".flashprog")))
|
||||
#endif
|
||||
void MXC_FLC_Com_Read(int address, void* buffer, int len)
|
||||
void MXC_FLC_Com_Read(int address, void *buffer, int len)
|
||||
{
|
||||
memcpy(buffer, (void*) address, len);
|
||||
memcpy(buffer, (void *)address, len);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
/**
|
||||
* @file flc.h
|
||||
* @brief Flash Controller driver.
|
||||
* @file flc_common.h
|
||||
* @brief Common functions for the flash controller driver.
|
||||
* @details This driver can be used to operate on the embedded flash memory.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -35,9 +35,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_COMMON_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_COMMON_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_sys.h"
|
||||
|
|
@ -54,19 +55,22 @@ extern "C" {
|
|||
|
||||
/***** Definitions *****/
|
||||
|
||||
|
||||
|
||||
/***** Function Prototypes *****/
|
||||
|
||||
int MXC_FLC_Com_VerifyData (uint32_t address, uint32_t length, uint32_t * data);
|
||||
int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t *data);
|
||||
|
||||
int MXC_FLC_Com_Write (uint32_t address, uint32_t length, uint32_t *buffer);
|
||||
int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t *buffer);
|
||||
|
||||
void MXC_FLC_Com_Read (int address, void* buffer, int len);
|
||||
void MXC_FLC_Com_Read(int address, void *buffer, int len);
|
||||
|
||||
volatile uint32_t *MXC_FLC_GetWELR(uint32_t address, uint32_t page_num);
|
||||
|
||||
volatile uint32_t *MXC_FLC_GetRLR(uint32_t address, uint32_t page_num);
|
||||
|
||||
/**@} end of group flc */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_COMMON_H_
|
||||
|
|
|
|||
|
|
@ -1,15 +1,15 @@
|
|||
/**
|
||||
* @file flc.h
|
||||
* @file flc_me11.c
|
||||
* @brief Flash Controler driver.
|
||||
* @details This driver can be used to operate on the embedded flash memory.
|
||||
*/
|
||||
/* ****************************************************************************
|
||||
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files(the "Software"),
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
|
|
@ -20,7 +20,7 @@
|
|||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
|
|
@ -29,13 +29,12 @@
|
|||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <string.h>
|
||||
|
|
@ -49,58 +48,72 @@
|
|||
//******************************************************************************
|
||||
void MXC_FLC_ME11_Flash_Operation(void)
|
||||
{
|
||||
/*
|
||||
This function should be called after modifying the contents of flash memory.
|
||||
It flushes the instruction caches and line fill buffer.
|
||||
|
||||
It should be called _afterwards_ because after flash is modified the cache
|
||||
may contain instructions that may no longer be valid. _Before_ the
|
||||
flash modifications the ICC may contain relevant cached instructions related to
|
||||
the incoming flash instructions (especially relevant in the case of external memory),
|
||||
and these instructions will be valid up until the point that the modifications are made.
|
||||
|
||||
The line fill buffer is a FLC-related buffer that also may no longer be valid.
|
||||
It's flushed by reading 2 pages of flash.
|
||||
*/
|
||||
|
||||
/* Flush all instruction caches */
|
||||
MXC_GCR->scon |= MXC_F_GCR_SCON_ICC0_FLUSH;
|
||||
|
||||
|
||||
/* Wait for flush to complete */
|
||||
while(MXC_GCR->scon & MXC_F_GCR_SCON_ICC0_FLUSH) {
|
||||
}
|
||||
while (MXC_GCR->scon & MXC_F_GCR_SCON_ICC0_FLUSH) {}
|
||||
|
||||
// Clear the line fill buffer by reading 2 pages from flash
|
||||
volatile uint32_t *line_addr;
|
||||
volatile uint32_t __unused line; // __unused attribute removes warning
|
||||
line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE);
|
||||
line = *line_addr;
|
||||
line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE + MXC_FLASH_PAGE_SIZE);
|
||||
line = *line_addr;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int MXC_FLC_ME11_GetByAddress(mxc_flc_regs_t **flc, uint32_t addr)
|
||||
{
|
||||
|
||||
// flash base start from 0x00000000
|
||||
if ( addr < MXC_FLASH_MEM_SIZE ) {
|
||||
if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) {
|
||||
*flc = MXC_FLC;
|
||||
}
|
||||
else if((addr >= MXC_INFO_MEM_BASE) && (addr <(MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
|
||||
} else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
|
||||
*flc = MXC_FLC;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int MXC_FLC_ME11_GetPhysicalAddress(uint32_t addr, uint32_t *result)
|
||||
{
|
||||
// flash base start from 0x00000000
|
||||
if ( addr < MXC_FLASH_MEM_SIZE ) {
|
||||
*result = addr & (MXC_FLASH_MEM_SIZE-1);
|
||||
}
|
||||
else if((addr >= MXC_INFO_MEM_BASE) && (addr <(MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
|
||||
*result = (addr & (MXC_INFO_MEM_SIZE-1)) + MXC_FLASH_MEM_SIZE;
|
||||
}
|
||||
else {
|
||||
if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) {
|
||||
*result = addr & (MXC_FLASH_MEM_SIZE - 1);
|
||||
} else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
|
||||
*result = (addr & (MXC_INFO_MEM_SIZE - 1)) + MXC_FLASH_MEM_SIZE;
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
|
||||
int MXC_FLC_Init()
|
||||
{
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
#if IAR_PRAGMAS
|
||||
#pragma section=".flashprog"
|
||||
#pragma section = ".flashprog"
|
||||
#else
|
||||
__attribute__((section(".flashprog")))
|
||||
#endif
|
||||
|
|
@ -109,197 +122,211 @@ int MXC_FLC_Busy(void)
|
|||
return MXC_FLC_RevA_Busy();
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
#if IAR_PRAGMAS
|
||||
#pragma section=".flashprog"
|
||||
#pragma section = ".flashprog"
|
||||
#else
|
||||
__attribute__((section(".flashprog")))
|
||||
#endif
|
||||
int MXC_FLC_ME11_PageErase(uint32_t address)
|
||||
int MXC_FLC_PageErase(uint32_t address)
|
||||
{
|
||||
int err;
|
||||
uint32_t addr;
|
||||
mxc_flc_regs_t *flc = NULL;
|
||||
|
||||
|
||||
// Get FLC Instance
|
||||
if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) {
|
||||
if ((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
if((err = MXC_FLC_ME11_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) {
|
||||
|
||||
if ((err = MXC_FLC_ME11_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
err = MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t*) flc, addr);
|
||||
|
||||
err = MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t *)flc, addr);
|
||||
// Flush the cache
|
||||
MXC_FLC_ME11_Flash_Operation();
|
||||
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
#if IAR_PRAGMAS
|
||||
#pragma section=".flashprog"
|
||||
#pragma section = ".flashprog"
|
||||
#else
|
||||
__attribute__((section(".flashprog")))
|
||||
#endif
|
||||
// make sure to disable ICC with ICC_Disable(); before Running this function
|
||||
int MXC_FLC_ME11_Write128(uint32_t address, uint32_t *data)
|
||||
int MXC_FLC_Write128(uint32_t address, uint32_t *data)
|
||||
{
|
||||
int err;
|
||||
mxc_flc_regs_t *flc = NULL;
|
||||
uint32_t addr;
|
||||
|
||||
|
||||
// Address checked if it is 128-bit aligned
|
||||
if(address & 0xF) {
|
||||
if (address & 0xF) {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
// Get FLC Instance
|
||||
if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) {
|
||||
if ((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
if((err = MXC_FLC_ME11_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) {
|
||||
|
||||
if ((err = MXC_FLC_ME11_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
if((err = MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t*) flc, addr, data)) != E_NO_ERROR) {
|
||||
|
||||
if ((err = MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t *)flc, addr, data)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
// Flush the cache
|
||||
MXC_FLC_ME11_Flash_Operation();
|
||||
|
||||
if((err= MXC_FLC_Com_VerifyData(address, 4, data)) !=E_NO_ERROR) {
|
||||
|
||||
if ((err = MXC_FLC_Com_VerifyData(address, 4, data)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int MXC_FLC_ME11_Write32(uint32_t address, uint32_t data)
|
||||
int MXC_FLC_Write32(uint32_t address, uint32_t data)
|
||||
{
|
||||
uint32_t addr, aligned;
|
||||
int err;
|
||||
mxc_flc_regs_t *flc = NULL;
|
||||
|
||||
|
||||
// Address checked if it is byte addressable
|
||||
if(address & 0x3) {
|
||||
if (address & 0x3) {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
// Align address to 128-bit word
|
||||
aligned = address & 0xfffffff0;
|
||||
|
||||
|
||||
// Get FLC Instance
|
||||
if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) {
|
||||
if ((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
if((err = MXC_FLC_ME11_GetPhysicalAddress(aligned, &addr)) < E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
return MXC_FLC_RevA_Write32((mxc_flc_reva_regs_t*) flc, address, data, addr);
|
||||
|
||||
}
|
||||
|
||||
int MXC_FLC_ME11_MassErase(void)
|
||||
{
|
||||
int err;
|
||||
mxc_flc_regs_t *flc;
|
||||
|
||||
flc = MXC_FLC;
|
||||
err = MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t*) flc);
|
||||
|
||||
if(err != E_NO_ERROR) {
|
||||
if ((err = MXC_FLC_ME11_GetPhysicalAddress(aligned, &addr)) < E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
err = MXC_FLC_RevA_Write32((mxc_flc_reva_regs_t *)flc, address, data, addr);
|
||||
|
||||
// Flush the cache
|
||||
MXC_FLC_ME11_Flash_Operation();
|
||||
|
||||
return E_NO_ERROR;
|
||||
|
||||
|
||||
|
||||
return err;
|
||||
}
|
||||
int MXC_FLC_ME11_UnlockInfoBlock(uint32_t address)
|
||||
{
|
||||
int err;
|
||||
mxc_flc_regs_t *flc;
|
||||
|
||||
if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t*) flc, address);
|
||||
}
|
||||
int MXC_FLC_ME11_LockInfoBlock(uint32_t address)
|
||||
{
|
||||
int err;
|
||||
mxc_flc_regs_t *flc;
|
||||
|
||||
if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t*) flc, address);
|
||||
}
|
||||
/* ****************************************************************************** */
|
||||
|
||||
//******************************************************************************
|
||||
int MXC_FLC_MassErase(void)
|
||||
{
|
||||
return MXC_FLC_ME11_MassErase();
|
||||
int err;
|
||||
mxc_flc_regs_t *flc;
|
||||
|
||||
flc = MXC_FLC;
|
||||
err = MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t *)flc);
|
||||
|
||||
if (err != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
MXC_FLC_ME11_Flash_Operation();
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_FLC_PageErase(uint32_t address)
|
||||
//******************************************************************************
|
||||
int MXC_FLC_UnlockInfoBlock(uint32_t address)
|
||||
{
|
||||
return MXC_FLC_ME11_PageErase(address);
|
||||
int err;
|
||||
mxc_flc_regs_t *flc;
|
||||
|
||||
if ((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t *)flc, address);
|
||||
}
|
||||
|
||||
int MXC_FLC_Write32(uint32_t address, uint32_t data)
|
||||
//******************************************************************************
|
||||
int MXC_FLC_LockInfoBlock(uint32_t address)
|
||||
{
|
||||
return MXC_FLC_ME11_Write32(address, data);
|
||||
}
|
||||
|
||||
int MXC_FLC_Write128(uint32_t address, uint32_t *data)
|
||||
{
|
||||
return MXC_FLC_ME11_Write128(address, data);
|
||||
int err;
|
||||
mxc_flc_regs_t *flc;
|
||||
|
||||
if ((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t *)flc, address);
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int MXC_FLC_Write(uint32_t address, uint32_t length, uint32_t *buffer)
|
||||
{
|
||||
return MXC_FLC_Com_Write(address, length, buffer);
|
||||
}
|
||||
void MXC_FLC_Read(int address, void* buffer, int len)
|
||||
|
||||
//******************************************************************************
|
||||
void MXC_FLC_Read(int address, void *buffer, int len)
|
||||
{
|
||||
MXC_FLC_Com_Read(address, buffer, len);
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int MXC_FLC_EnableInt(uint32_t flags)
|
||||
{
|
||||
return MXC_FLC_RevA_EnableInt(flags);
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int MXC_FLC_DisableInt(uint32_t flags)
|
||||
{
|
||||
return MXC_FLC_RevA_DisableInt(flags);
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int MXC_FLC_GetFlags(void)
|
||||
{
|
||||
return MXC_FLC_RevA_GetFlags();
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int MXC_FLC_ClearFlags(uint32_t flags)
|
||||
{
|
||||
return MXC_FLC_RevA_ClearFlags(flags);
|
||||
}
|
||||
|
||||
int MXC_FLC_UnlockInfoBlock(uint32_t address)
|
||||
//******************************************************************************
|
||||
int MXC_FLC_BlockPageWrite(uint32_t address)
|
||||
{
|
||||
return MXC_FLC_ME11_UnlockInfoBlock(address);
|
||||
/* MAX32660 does not support flash page read and write locks */
|
||||
return E_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
int MXC_FLC_LockInfoBlock(uint32_t address)
|
||||
//******************************************************************************
|
||||
int MXC_FLC_BlockPageRead(uint32_t address)
|
||||
{
|
||||
return MXC_FLC_ME11_LockInfoBlock(address);
|
||||
/* MAX32660 does not support flash page read and write locks */
|
||||
return E_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
volatile uint32_t *MXC_FLC_GetWELR(uint32_t address, uint32_t page_num)
|
||||
{
|
||||
/* MAX32660 does not support flash page read and write locks */
|
||||
return NULL;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
volatile uint32_t *MXC_FLC_GetRLR(uint32_t address, uint32_t page_num)
|
||||
{
|
||||
/* MAX32660 does not support flash page read and write locks */
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Flash Controler driver.
|
||||
* @details This driver can be used to operate on the embedded flash memory.
|
||||
*/
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,8 +34,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <string.h>
|
||||
|
|
@ -53,50 +52,56 @@
|
|||
/* **** Definitions **** */
|
||||
|
||||
/* **** Globals **** */
|
||||
#ifdef MXC_FLC0
|
||||
static mxc_flc_reva_regs_t *flc_int = (mxc_flc_reva_regs_t *)MXC_FLC0;
|
||||
#else
|
||||
static mxc_flc_reva_regs_t *flc_int = (mxc_flc_reva_regs_t *)MXC_FLC;
|
||||
#endif
|
||||
|
||||
/* **** Functions **** */
|
||||
|
||||
//******************************************************************************
|
||||
#if IAR_PRAGMAS
|
||||
#pragma section=".flashprog"
|
||||
#pragma section = ".flashprog"
|
||||
#else
|
||||
__attribute__((section(".flashprog")))
|
||||
#endif
|
||||
static int MXC_busy_flc(mxc_flc_reva_regs_t* flc)
|
||||
static int MXC_busy_flc(mxc_flc_reva_regs_t *flc)
|
||||
{
|
||||
return (flc->ctrl & (MXC_F_FLC_REVA_CTRL_WR | MXC_F_FLC_REVA_CTRL_ME | MXC_F_FLC_REVA_CTRL_PGE));
|
||||
return (flc->ctrl &
|
||||
(MXC_F_FLC_REVA_CTRL_WR | MXC_F_FLC_REVA_CTRL_ME | MXC_F_FLC_REVA_CTRL_PGE));
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
#if IAR_PRAGMAS
|
||||
#pragma section=".flashprog"
|
||||
#pragma section = ".flashprog"
|
||||
#else
|
||||
__attribute__((section(".flashprog")))
|
||||
#endif
|
||||
static int MXC_prepare_flc(mxc_flc_reva_regs_t* flc)
|
||||
static int MXC_prepare_flc(mxc_flc_reva_regs_t *flc)
|
||||
{
|
||||
/* Check if the flash controller is busy */
|
||||
if (MXC_busy_flc(flc)) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
||||
// Set flash clock divider to generate a 1MHz clock from the APB clock
|
||||
flc->clkdiv = SystemCoreClock / 1000000;
|
||||
|
||||
|
||||
/* Clear stale errors */
|
||||
if (flc->intr & MXC_F_FLC_REVA_INTR_AF) {
|
||||
flc->intr &= ~MXC_F_FLC_REVA_INTR_AF;
|
||||
}
|
||||
|
||||
|
||||
/* Unlock flash */
|
||||
flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_UNLOCK) | MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED;
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
#if IAR_PRAGMAS
|
||||
#pragma section=".flashprog"
|
||||
#pragma section = ".flashprog"
|
||||
#else
|
||||
__attribute__((section(".flashprog")))
|
||||
#endif
|
||||
|
|
@ -105,60 +110,61 @@ int MXC_FLC_RevA_Busy(void)
|
|||
uint32_t flc_cn = 0;
|
||||
int i;
|
||||
mxc_flc_reva_regs_t *flc;
|
||||
|
||||
|
||||
for (i = 0; i < MXC_FLC_INSTANCES; i++) {
|
||||
flc = (mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC (i);
|
||||
flc_cn = MXC_busy_flc (flc);
|
||||
|
||||
flc = (mxc_flc_reva_regs_t *)MXC_FLC_GET_FLC(i);
|
||||
flc_cn = MXC_busy_flc(flc);
|
||||
|
||||
if (flc_cn != 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
return flc_cn;
|
||||
}
|
||||
//******************************************************************************
|
||||
#if IAR_PRAGMAS
|
||||
#pragma section=".flashprog"
|
||||
#pragma section = ".flashprog"
|
||||
#else
|
||||
__attribute__((section(".flashprog")))
|
||||
#endif
|
||||
int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc)
|
||||
int MXC_FLC_RevA_MassErase(mxc_flc_reva_regs_t *flc)
|
||||
{
|
||||
int err;
|
||||
|
||||
|
||||
if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
/* Write mass erase code */
|
||||
flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL;
|
||||
|
||||
flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) |
|
||||
MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL;
|
||||
|
||||
/* Issue mass erase command */
|
||||
flc->ctrl |= MXC_F_FLC_REVA_CTRL_ME;
|
||||
|
||||
|
||||
/* Wait until flash operation is complete */
|
||||
while (MXC_busy_flc(flc));
|
||||
|
||||
while (MXC_busy_flc(flc)) {}
|
||||
|
||||
/* Lock flash */
|
||||
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
|
||||
|
||||
|
||||
/* Check access violations */
|
||||
if (flc->intr & MXC_F_FLC_REVA_INTR_AF) {
|
||||
flc->intr &= ~MXC_F_FLC_REVA_INTR_AF;
|
||||
return E_BAD_STATE;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
#if IAR_PRAGMAS
|
||||
#pragma section=".flashprog"
|
||||
#pragma section = ".flashprog"
|
||||
#else
|
||||
__attribute__((section(".flashprog")))
|
||||
#endif
|
||||
int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc, uint32_t addr)
|
||||
int MXC_FLC_RevA_PageErase(mxc_flc_reva_regs_t *flc, uint32_t addr)
|
||||
{
|
||||
int err;
|
||||
|
||||
|
|
@ -167,108 +173,158 @@ int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc, uint32_t addr)
|
|||
}
|
||||
|
||||
/* Write page erase code */
|
||||
flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE;
|
||||
flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) |
|
||||
MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE;
|
||||
/* Issue page erase command */
|
||||
flc->addr = addr;
|
||||
flc->ctrl |= MXC_F_FLC_REVA_CTRL_PGE;
|
||||
|
||||
|
||||
/* Wait until flash operation is complete */
|
||||
while (MXC_FLC_Busy());
|
||||
|
||||
while (MXC_busy_flc(flc)) {}
|
||||
|
||||
/* Lock flash */
|
||||
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
|
||||
|
||||
|
||||
/* Check access violations */
|
||||
if (flc->intr & MXC_F_FLC_REVA_INTR_AF) {
|
||||
flc->intr &= ~MXC_F_FLC_REVA_INTR_AF;
|
||||
return E_BAD_STATE;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
||||
|
||||
//******************************************************************************
|
||||
#if IAR_PRAGMAS
|
||||
#pragma section=".flashprog"
|
||||
#pragma section = ".flashprog"
|
||||
#else
|
||||
__attribute__((section(".flashprog")))
|
||||
#endif
|
||||
// make sure to disable ICC with ICC_Disable(); before Running this function
|
||||
int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t* flc, uint32_t logicAddr, uint32_t data, uint32_t physicalAddr)
|
||||
int MXC_FLC_RevA_Write32(mxc_flc_reva_regs_t *flc, uint32_t logicAddr, uint32_t data,
|
||||
uint32_t physicalAddr)
|
||||
{
|
||||
int err, i = 0;
|
||||
uint32_t byte;
|
||||
volatile uint32_t* ptr;
|
||||
uint32_t current_data[4] = {0, 0, 0, 0};
|
||||
|
||||
int err;
|
||||
|
||||
// Address checked if it is byte addressable
|
||||
if (logicAddr & 0x3) {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
// Check if the location trying to be written has 1's in to be written to 0's
|
||||
if ((* (uint32_t*) logicAddr & data) != data) {
|
||||
if ((*(uint32_t *)logicAddr & data) != data) {
|
||||
return E_BAD_STATE;
|
||||
}
|
||||
|
||||
|
||||
// Align address to 32-bit word
|
||||
logicAddr = logicAddr & 0xfffffffc;
|
||||
|
||||
if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
// write 32-bits
|
||||
flc->ctrl |= MXC_F_FLC_REVA_CTRL_WDTH;
|
||||
|
||||
// write the data
|
||||
flc->addr = logicAddr;
|
||||
flc->data[0] = data;
|
||||
flc->ctrl |= MXC_F_FLC_REVA_CTRL_WR;
|
||||
|
||||
/* Wait until flash operation is complete */
|
||||
while ((flc->ctrl & MXC_F_FLC_REVA_CTRL_PEND) != 0) {}
|
||||
while (MXC_busy_flc(flc)) {}
|
||||
|
||||
/* Lock flash */
|
||||
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
|
||||
|
||||
/* Check access violations */
|
||||
if (flc->intr & MXC_F_FLC_REVA_INTR_AF) {
|
||||
flc->intr &= ~MXC_F_FLC_REVA_INTR_AF;
|
||||
return E_BAD_STATE;
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
#if IAR_PRAGMAS
|
||||
#pragma section = ".flashprog"
|
||||
#else
|
||||
__attribute__((section(".flashprog")))
|
||||
#endif
|
||||
// make sure to disable ICC with ICC_Disable(); before Running this function
|
||||
int MXC_FLC_RevA_Write32Using128(mxc_flc_reva_regs_t *flc, uint32_t logicAddr, uint32_t data,
|
||||
uint32_t physicalAddr)
|
||||
{
|
||||
int err, i = 0;
|
||||
uint32_t byte;
|
||||
volatile uint32_t *ptr;
|
||||
uint32_t current_data[4] = { 0, 0, 0, 0 };
|
||||
|
||||
// Address checked if it is byte addressable
|
||||
if (logicAddr & 0x3) {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
// Check if the location trying to be written has 1's in to be written to 0's
|
||||
if ((*(uint32_t *)logicAddr & data) != data) {
|
||||
return E_BAD_STATE;
|
||||
}
|
||||
|
||||
// Get byte idx within 128-bit word
|
||||
byte = (logicAddr & 0xf);
|
||||
// Align address to 128-bit word
|
||||
logicAddr = logicAddr & 0xfffffff0;
|
||||
|
||||
|
||||
if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
// Get current data stored in flash
|
||||
for (ptr = (uint32_t*) logicAddr; ptr < (uint32_t*)(logicAddr + 16); ptr++, i++) {
|
||||
for (ptr = (uint32_t *)logicAddr; ptr < (uint32_t *)(logicAddr + 16); ptr++, i++) {
|
||||
current_data[i] = *ptr;
|
||||
}
|
||||
|
||||
|
||||
// write the data
|
||||
flc->addr = physicalAddr;
|
||||
|
||||
|
||||
if (byte < 4) {
|
||||
current_data[0] = data;
|
||||
}
|
||||
else if (byte < 8) {
|
||||
} else if (byte < 8) {
|
||||
current_data[1] = data;
|
||||
}
|
||||
else if (byte < 12) {
|
||||
} else if (byte < 12) {
|
||||
current_data[2] = data;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
current_data[3] = data;
|
||||
}
|
||||
|
||||
|
||||
return MXC_FLC_Write128(logicAddr, current_data);
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
#if IAR_PRAGMAS
|
||||
#pragma section=".flashprog"
|
||||
#pragma section = ".flashprog"
|
||||
#else
|
||||
__attribute__((section(".flashprog")))
|
||||
#endif
|
||||
// make sure to disable ICC with ICC_Disable(); before Running this function
|
||||
int MXC_FLC_RevA_Write128 (mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data)
|
||||
int MXC_FLC_RevA_Write128(mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data)
|
||||
{
|
||||
int err;
|
||||
|
||||
|
||||
// Address checked if it is 128-bit aligned
|
||||
if (addr & 0xF) {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
// write 128-bits
|
||||
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_WDTH;
|
||||
|
||||
|
||||
// write the data
|
||||
flc->addr = addr;
|
||||
flc->data[0] = data[0];
|
||||
|
|
@ -278,101 +334,152 @@ int MXC_FLC_RevA_Write128 (mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *da
|
|||
flc->ctrl |= MXC_F_FLC_REVA_CTRL_WR;
|
||||
|
||||
/* Wait until flash operation is complete */
|
||||
while ((flc->ctrl & MXC_F_FLC_REVA_CTRL_PEND)!=0){}
|
||||
while (MXC_busy_flc (flc)){}
|
||||
|
||||
while ((flc->ctrl & MXC_F_FLC_REVA_CTRL_PEND) != 0) {}
|
||||
while (MXC_busy_flc(flc)) {}
|
||||
|
||||
/* Lock flash */
|
||||
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
|
||||
|
||||
|
||||
/* Check access violations */
|
||||
if (flc->intr & MXC_F_FLC_REVA_INTR_AF) {
|
||||
flc->intr &= ~MXC_F_FLC_REVA_INTR_AF;
|
||||
return E_BAD_STATE;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
void MXC_FLC_RevA_SetFLCInt(mxc_flc_reva_regs_t *flc)
|
||||
{
|
||||
flc_int = flc;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
mxc_flc_reva_regs_t *MXC_FLC_RevA_GetFLCInt(void)
|
||||
{
|
||||
return flc_int;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int MXC_FLC_RevA_EnableInt(uint32_t mask)
|
||||
{
|
||||
mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE);
|
||||
|
||||
mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE);
|
||||
|
||||
if (!mask) {
|
||||
/* No bits set? Wasn't something we can enable. */
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
/* Apply enables and write back, preserving the flags */
|
||||
((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr |= mask;
|
||||
|
||||
flc_int->intr |= mask;
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int MXC_FLC_RevA_DisableInt(uint32_t mask)
|
||||
{
|
||||
mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE);
|
||||
|
||||
mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE);
|
||||
|
||||
if (!mask) {
|
||||
/* No bits set? Wasn't something we can disable. */
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
/* Apply disables and write back, preserving the flags */
|
||||
((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr &= ~mask;
|
||||
|
||||
flc_int->intr &= ~mask;
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int MXC_FLC_RevA_GetFlags(void)
|
||||
{
|
||||
return (((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr & (MXC_F_FLC_REVA_INTR_DONE | MXC_F_FLC_REVA_INTR_AF));
|
||||
return (flc_int->intr & (MXC_F_FLC_REVA_INTR_DONE | MXC_F_FLC_REVA_INTR_AF));
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int MXC_FLC_RevA_ClearFlags(uint32_t mask)
|
||||
{
|
||||
mask &= (MXC_F_FLC_REVA_INTR_DONE | MXC_F_FLC_REVA_INTR_AF);
|
||||
|
||||
|
||||
if (!mask) {
|
||||
/* No bits set? Wasn't something we can clear. */
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
/* Both flags are write zero clear */
|
||||
((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr ^= mask;
|
||||
|
||||
flc_int->intr ^= mask;
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int MXC_FLC_RevA_UnlockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address)
|
||||
int MXC_FLC_RevA_UnlockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address)
|
||||
{
|
||||
if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
|
||||
if ((address < MXC_INFO_MEM_BASE) ||
|
||||
(address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
/* Make sure the info block is locked */
|
||||
flc->actrl = 0x1234;
|
||||
|
||||
|
||||
/* Write the unlock sequence */
|
||||
flc->actrl = 0x3a7f5ca3;
|
||||
flc->actrl = 0xa1e34f20;
|
||||
flc->actrl = 0x9608b2c1;
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int MXC_FLC_RevA_LockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address)
|
||||
int MXC_FLC_RevA_LockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address)
|
||||
{
|
||||
if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
|
||||
if ((address < MXC_INFO_MEM_BASE) ||
|
||||
(address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
flc->actrl = 0xDEADBEEF;
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int MXC_FLC_RevA_BlockPageWrite(uint32_t address, uint32_t bank_base)
|
||||
{
|
||||
uint32_t page_num;
|
||||
page_num = address - bank_base; // Get page number in flash bank
|
||||
page_num /= MXC_FLASH_PAGE_SIZE;
|
||||
|
||||
volatile uint32_t *welr = MXC_FLC_GetWELR(
|
||||
address, page_num); // Get pointer to WELR register containing corresponding page bit
|
||||
|
||||
while (page_num > 31) { // Set corresponding bit in WELR register
|
||||
page_num -= 32;
|
||||
}
|
||||
*welr = (1 << page_num);
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int MXC_FLC_RevA_BlockPageRead(uint32_t address, uint32_t bank_base)
|
||||
{
|
||||
uint32_t page_num;
|
||||
page_num = address - bank_base; // Get page number in flash bank
|
||||
page_num /= MXC_FLASH_PAGE_SIZE;
|
||||
|
||||
volatile uint32_t *rlr = MXC_FLC_GetRLR(
|
||||
address, page_num); // Get pointer to RLR register containing corresponding page bit
|
||||
|
||||
while (page_num > 31) { // Set corresponding bit in WELR register
|
||||
page_num -= 32;
|
||||
}
|
||||
*rlr = (1 << page_num);
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/**@} end of group flc */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**
|
||||
* @file flc.h
|
||||
* @brief Flash Controler driver.
|
||||
* @file flc_reva.h
|
||||
* @brief Flash RevA Controller driver.
|
||||
* @details This driver can be used to operate on the embedded flash memory.
|
||||
*/
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,8 +34,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <string.h>
|
||||
|
|
@ -43,6 +45,7 @@
|
|||
#include "mxc_assert.h"
|
||||
#include "mxc_sys.h"
|
||||
#include "flc.h"
|
||||
#include "flc_common.h"
|
||||
#include "flc_reva_regs.h"
|
||||
|
||||
/**
|
||||
|
|
@ -56,30 +59,44 @@
|
|||
|
||||
/* **** Functions **** */
|
||||
|
||||
int MXC_FLC_RevA_Busy (void);
|
||||
int MXC_FLC_RevA_Busy(void);
|
||||
|
||||
int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc);
|
||||
int MXC_FLC_RevA_MassErase(mxc_flc_reva_regs_t *flc);
|
||||
|
||||
int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc,uint32_t addr);
|
||||
int MXC_FLC_RevA_PageErase(mxc_flc_reva_regs_t *flc, uint32_t addr);
|
||||
|
||||
int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data, uint32_t physicalAddr);
|
||||
int MXC_FLC_RevA_Write32(mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data,
|
||||
uint32_t physicalAddr);
|
||||
|
||||
int MXC_FLC_RevA_Write128 (mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data);
|
||||
int MXC_FLC_RevA_Write32Using128(mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data,
|
||||
uint32_t physicalAddr);
|
||||
|
||||
int MXC_FLC_RevA_EnableInt (uint32_t mask);
|
||||
int MXC_FLC_RevA_Write128(mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data);
|
||||
|
||||
int MXC_FLC_RevA_DisableInt (uint32_t mask);
|
||||
void MXC_FLC_RevA_SetFLCInt(mxc_flc_reva_regs_t *flc);
|
||||
|
||||
int MXC_FLC_RevA_GetFlags (void);
|
||||
mxc_flc_reva_regs_t *MXC_FLC_RevA_GetFLCInt(void);
|
||||
|
||||
int MXC_FLC_RevA_ClearFlags (uint32_t mask);
|
||||
int MXC_FLC_RevA_EnableInt(uint32_t mask);
|
||||
|
||||
int MXC_FLC_RevA_UnlockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address);
|
||||
int MXC_FLC_RevA_DisableInt(uint32_t mask);
|
||||
|
||||
int MXC_FLC_RevA_GetFlags(void);
|
||||
|
||||
int MXC_FLC_RevA_ClearFlags(uint32_t mask);
|
||||
|
||||
int MXC_FLC_RevA_UnlockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address);
|
||||
|
||||
int MXC_FLC_RevA_LockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address);
|
||||
|
||||
int MXC_FLC_RevA_BlockPageWrite(uint32_t address, uint32_t bank_base);
|
||||
|
||||
int MXC_FLC_RevA_BlockPageRead(uint32_t address, uint32_t bank_base);
|
||||
|
||||
int MXC_FLC_RevA_LockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address);
|
||||
/**@} end of group flc */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Registers, Bit Masks and Bit Positions for the FLC_REVA Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +34,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _FLC_REVA_REGS_H_
|
||||
#define _FLC_REVA_REGS_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -46,13 +45,13 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__ICCARM__)
|
||||
#pragma system_include
|
||||
#pragma system_include
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__CC_ARM)
|
||||
#pragma anon_unions
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
/// @cond
|
||||
/*
|
||||
|
|
@ -104,13 +103,13 @@ typedef struct {
|
|||
* @brief FLC_REVA Peripheral Register Offsets from the FLC_REVA Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_FLC_REVA_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_FLC_REVA_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_FLC_REVA_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_FLC_REVA_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0024</tt> */
|
||||
#define MXC_R_FLC_REVA_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0028</tt> */
|
||||
#define MXC_R_FLC_REVA_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0030</tt> */
|
||||
#define MXC_R_FLC_REVA_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0040</tt> */
|
||||
#define MXC_R_FLC_REVA_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_FLC_REVA_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_FLC_REVA_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0008</tt> */
|
||||
#define MXC_R_FLC_REVA_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0024</tt> */
|
||||
#define MXC_R_FLC_REVA_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0028</tt> */
|
||||
#define MXC_R_FLC_REVA_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0030</tt> */
|
||||
#define MXC_R_FLC_REVA_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0040</tt> */
|
||||
/**@} end of group flc_reva_registers */
|
||||
|
||||
/**
|
||||
|
|
@ -119,8 +118,8 @@ typedef struct {
|
|||
* @brief Flash Write Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_REVA_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
|
||||
#define MXC_F_FLC_REVA_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
|
||||
#define MXC_F_FLC_REVA_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
|
||||
#define MXC_F_FLC_REVA_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
|
||||
|
||||
/**@} end of group FLC_REVA_ADDR_Register */
|
||||
|
||||
|
|
@ -131,8 +130,8 @@ typedef struct {
|
|||
* MHz clock for Flash controller.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
|
||||
#define MXC_F_FLC_REVA_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
|
||||
#define MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
|
||||
#define MXC_F_FLC_REVA_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
|
||||
|
||||
/**@} end of group FLC_REVA_CLKDIV_Register */
|
||||
|
||||
|
|
@ -142,39 +141,39 @@ typedef struct {
|
|||
* @brief Flash Control Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_REVA_CTRL_WR_POS 0 /**< CTRL_WR Position */
|
||||
#define MXC_F_FLC_REVA_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WR_POS)) /**< CTRL_WR Mask */
|
||||
#define MXC_F_FLC_REVA_CTRL_WR_POS 0 /**< CTRL_WR Position */
|
||||
#define MXC_F_FLC_REVA_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WR_POS)) /**< CTRL_WR Mask */
|
||||
|
||||
#define MXC_F_FLC_REVA_CTRL_ME_POS 1 /**< CTRL_ME Position */
|
||||
#define MXC_F_FLC_REVA_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_ME_POS)) /**< CTRL_ME Mask */
|
||||
#define MXC_F_FLC_REVA_CTRL_ME_POS 1 /**< CTRL_ME Position */
|
||||
#define MXC_F_FLC_REVA_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_ME_POS)) /**< CTRL_ME Mask */
|
||||
|
||||
#define MXC_F_FLC_REVA_CTRL_PGE_POS 2 /**< CTRL_PGE Position */
|
||||
#define MXC_F_FLC_REVA_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PGE_POS)) /**< CTRL_PGE Mask */
|
||||
#define MXC_F_FLC_REVA_CTRL_PGE_POS 2 /**< CTRL_PGE Position */
|
||||
#define MXC_F_FLC_REVA_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PGE_POS)) /**< CTRL_PGE Mask */
|
||||
|
||||
#define MXC_F_FLC_REVA_CTRL_WDTH_POS 4 /**< CTRL_WDTH Position */
|
||||
#define MXC_F_FLC_REVA_CTRL_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WDTH_POS)) /**< CTRL_WDTH Mask */
|
||||
#define MXC_F_FLC_REVA_CTRL_WDTH_POS 4 /**< CTRL_WDTH Position */
|
||||
#define MXC_F_FLC_REVA_CTRL_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WDTH_POS)) /**< CTRL_WDTH Mask */
|
||||
|
||||
#define MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */
|
||||
#define MXC_F_FLC_REVA_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */
|
||||
#define MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */
|
||||
#define MXC_S_FLC_REVA_CTRL_ERASE_CODE_NOP (MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */
|
||||
#define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */
|
||||
#define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */
|
||||
#define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */
|
||||
#define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */
|
||||
#define MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */
|
||||
#define MXC_F_FLC_REVA_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */
|
||||
#define MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */
|
||||
#define MXC_S_FLC_REVA_CTRL_ERASE_CODE_NOP (MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */
|
||||
#define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */
|
||||
#define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */
|
||||
#define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */
|
||||
#define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */
|
||||
|
||||
#define MXC_F_FLC_REVA_CTRL_PEND_POS 24 /**< CTRL_PEND Position */
|
||||
#define MXC_F_FLC_REVA_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PEND_POS)) /**< CTRL_PEND Mask */
|
||||
#define MXC_F_FLC_REVA_CTRL_PEND_POS 24 /**< CTRL_PEND Position */
|
||||
#define MXC_F_FLC_REVA_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PEND_POS)) /**< CTRL_PEND Mask */
|
||||
|
||||
#define MXC_F_FLC_REVA_CTRL_LVE_POS 25 /**< CTRL_LVE Position */
|
||||
#define MXC_F_FLC_REVA_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_LVE_POS)) /**< CTRL_LVE Mask */
|
||||
#define MXC_F_FLC_REVA_CTRL_LVE_POS 25 /**< CTRL_LVE Position */
|
||||
#define MXC_F_FLC_REVA_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_LVE_POS)) /**< CTRL_LVE Mask */
|
||||
|
||||
#define MXC_F_FLC_REVA_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */
|
||||
#define MXC_F_FLC_REVA_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_REVA_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */
|
||||
#define MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */
|
||||
#define MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */
|
||||
#define MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */
|
||||
#define MXC_S_FLC_REVA_CTRL_UNLOCK_LOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */
|
||||
#define MXC_F_FLC_REVA_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */
|
||||
#define MXC_F_FLC_REVA_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_REVA_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */
|
||||
#define MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */
|
||||
#define MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */
|
||||
#define MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */
|
||||
#define MXC_S_FLC_REVA_CTRL_UNLOCK_LOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */
|
||||
|
||||
/**@} end of group FLC_REVA_CTRL_Register */
|
||||
|
||||
|
|
@ -184,17 +183,17 @@ typedef struct {
|
|||
* @brief Flash Interrupt Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_REVA_INTR_DONE_POS 0 /**< INTR_DONE Position */
|
||||
#define MXC_F_FLC_REVA_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONE_POS)) /**< INTR_DONE Mask */
|
||||
#define MXC_F_FLC_REVA_INTR_DONE_POS 0 /**< INTR_DONE Position */
|
||||
#define MXC_F_FLC_REVA_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONE_POS)) /**< INTR_DONE Mask */
|
||||
|
||||
#define MXC_F_FLC_REVA_INTR_AF_POS 1 /**< INTR_AF Position */
|
||||
#define MXC_F_FLC_REVA_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AF_POS)) /**< INTR_AF Mask */
|
||||
#define MXC_F_FLC_REVA_INTR_AF_POS 1 /**< INTR_AF Position */
|
||||
#define MXC_F_FLC_REVA_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AF_POS)) /**< INTR_AF Mask */
|
||||
|
||||
#define MXC_F_FLC_REVA_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */
|
||||
#define MXC_F_FLC_REVA_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
|
||||
#define MXC_F_FLC_REVA_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */
|
||||
#define MXC_F_FLC_REVA_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
|
||||
|
||||
#define MXC_F_FLC_REVA_INTR_AFIE_POS 9 /**< INTR_AFIE Position */
|
||||
#define MXC_F_FLC_REVA_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
|
||||
#define MXC_F_FLC_REVA_INTR_AFIE_POS 9 /**< INTR_AFIE Position */
|
||||
#define MXC_F_FLC_REVA_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
|
||||
|
||||
/**@} end of group FLC_REVA_INTR_Register */
|
||||
|
||||
|
|
@ -204,11 +203,11 @@ typedef struct {
|
|||
* @brief ECC Data Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_REVA_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */
|
||||
#define MXC_F_FLC_REVA_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */
|
||||
#define MXC_F_FLC_REVA_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */
|
||||
#define MXC_F_FLC_REVA_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */
|
||||
|
||||
#define MXC_F_FLC_REVA_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */
|
||||
#define MXC_F_FLC_REVA_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */
|
||||
#define MXC_F_FLC_REVA_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */
|
||||
#define MXC_F_FLC_REVA_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */
|
||||
|
||||
/**@} end of group FLC_REVA_ECCDATA_Register */
|
||||
|
||||
|
|
@ -218,8 +217,8 @@ typedef struct {
|
|||
* @brief Flash Write Data.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_REVA_DATA_DATA_POS 0 /**< DATA_DATA Position */
|
||||
#define MXC_F_FLC_REVA_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_DATA_DATA_POS)) /**< DATA_DATA Mask */
|
||||
#define MXC_F_FLC_REVA_DATA_DATA_POS 0 /**< DATA_DATA Position */
|
||||
#define MXC_F_FLC_REVA_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_DATA_DATA_POS)) /**< DATA_DATA Mask */
|
||||
|
||||
/**@} end of group FLC_REVA_DATA_Register */
|
||||
|
||||
|
|
@ -234,8 +233,8 @@ typedef struct {
|
|||
* this register is always zero.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_REVA_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */
|
||||
#define MXC_F_FLC_REVA_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */
|
||||
#define MXC_F_FLC_REVA_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */
|
||||
#define MXC_F_FLC_REVA_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */
|
||||
|
||||
/**@} end of group FLC_REVA_ACTRL_Register */
|
||||
|
||||
|
|
@ -243,4 +242,4 @@ typedef struct {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FLC_REVA_REGS_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_FLC_FLC_REVA_REGS_H_
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* *****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,17 +29,18 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stddef.h>
|
||||
#include "gpio_common.h"
|
||||
#include "mxc_device.h"
|
||||
#include "mxc_assert.h"
|
||||
#include "gpio.h"
|
||||
#include <stddef.h>
|
||||
|
||||
/* **** Globals **** */
|
||||
static void (*callback[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT])(void*);
|
||||
static void* cbparam[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT];
|
||||
static void (*callback[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT])(void *);
|
||||
static void *cbparam[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT];
|
||||
static uint8_t initialized = 0;
|
||||
|
||||
/* **** Functions **** */
|
||||
|
|
@ -47,34 +48,35 @@ int MXC_GPIO_Common_Init(uint32_t portmask)
|
|||
{
|
||||
if (!initialized) {
|
||||
int i, j;
|
||||
|
||||
|
||||
for (i = 0; i < MXC_CFG_GPIO_INSTANCES; i++) {
|
||||
// Initialize call back arrays
|
||||
for (j = 0; j < MXC_CFG_GPIO_PINS_PORT; j++) {
|
||||
callback[i][j] = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
initialized = 1;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
void MXC_GPIO_Common_RegisterCallback(const mxc_gpio_cfg_t* cfg, mxc_gpio_callback_fn func, void* cbdata)
|
||||
void MXC_GPIO_Common_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn func,
|
||||
void *cbdata)
|
||||
{
|
||||
uint32_t mask;
|
||||
unsigned int pin;
|
||||
|
||||
|
||||
mask = cfg->mask;
|
||||
pin = 0;
|
||||
|
||||
|
||||
while (mask) {
|
||||
if (mask & 1) {
|
||||
callback[MXC_GPIO_GET_IDX(cfg->port)][pin] = func;
|
||||
cbparam[MXC_GPIO_GET_IDX(cfg->port)][pin] = cbdata;
|
||||
}
|
||||
|
||||
|
||||
pin++;
|
||||
mask >>= 1;
|
||||
}
|
||||
|
|
@ -84,23 +86,23 @@ void MXC_GPIO_Common_Handler(unsigned int port)
|
|||
{
|
||||
uint32_t stat;
|
||||
unsigned int pin;
|
||||
|
||||
|
||||
MXC_ASSERT(port < MXC_CFG_GPIO_INSTANCES);
|
||||
|
||||
mxc_gpio_regs_t* gpio = MXC_GPIO_GET_GPIO(port);
|
||||
|
||||
|
||||
mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port);
|
||||
|
||||
stat = MXC_GPIO_GetFlags(gpio);
|
||||
MXC_GPIO_ClearFlags(gpio, stat);
|
||||
|
||||
|
||||
pin = 0;
|
||||
|
||||
|
||||
while (stat) {
|
||||
if (stat & 1) {
|
||||
if (callback[port][pin]) {
|
||||
callback[port][pin](cbparam[port][pin]);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
pin++;
|
||||
stat >>= 1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,10 +29,14 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_COMMON_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_COMMON_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "gpio_regs.h"
|
||||
#include "gpio.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
|
@ -40,9 +44,10 @@ extern "C" {
|
|||
|
||||
/* **** Function Prototypes **** */
|
||||
|
||||
int MXC_GPIO_Common_Init (uint32_t portmask);
|
||||
void MXC_GPIO_Common_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, void *cbdata);
|
||||
void MXC_GPIO_Common_Handler (unsigned int port);
|
||||
int MXC_GPIO_Common_Init(uint32_t portmask);
|
||||
void MXC_GPIO_Common_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback,
|
||||
void *cbdata);
|
||||
void MXC_GPIO_Common_Handler(unsigned int port);
|
||||
|
||||
/**@} end of group gpio */
|
||||
|
||||
|
|
@ -50,3 +55,4 @@ void MXC_GPIO_Common_Handler (unsigned int port);
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_COMMON_H_
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
/* *****************************************************************************
|
||||
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files(the "Software"),
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
|
|
@ -29,43 +29,41 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stddef.h>
|
||||
#include "mxc_device.h"
|
||||
#include "mxc_assert.h"
|
||||
#include "mxc_errors.h"
|
||||
#include "gpio.h"
|
||||
#include "gpio_reva.h"
|
||||
#include "gpio_common.h"
|
||||
#include <stddef.h>
|
||||
#include "mxc_sys.h"
|
||||
|
||||
/* **** Functions **** */
|
||||
|
||||
int MXC_GPIO_Init(uint32_t portmask)
|
||||
{
|
||||
int retval = MXC_GPIO_Common_Init(portmask);
|
||||
|
||||
if(portmask & MXC_GPIO_PORT_0) {
|
||||
if (portmask & MXC_GPIO_PORT_0) {
|
||||
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0);
|
||||
}
|
||||
|
||||
return MXC_GPIO_Common_Init(portmask) + retval;
|
||||
|
||||
return MXC_GPIO_Common_Init(portmask);
|
||||
}
|
||||
|
||||
int MXC_GPIO_Shutdown(uint32_t portmask)
|
||||
{
|
||||
if(portmask & MXC_GPIO_PORT_0) {
|
||||
if (portmask & MXC_GPIO_PORT_0) {
|
||||
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO0);
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_GPIO_Reset(uint32_t portmask)
|
||||
{
|
||||
if(portmask & MXC_GPIO_PORT_0) {
|
||||
if (portmask & MXC_GPIO_PORT_0) {
|
||||
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_GPIO0);
|
||||
}
|
||||
|
||||
|
|
@ -75,99 +73,97 @@ int MXC_GPIO_Reset(uint32_t portmask)
|
|||
int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg)
|
||||
{
|
||||
mxc_gpio_regs_t *gpio = cfg->port;
|
||||
|
||||
|
||||
// Set the GPIO type
|
||||
switch(cfg->func) {
|
||||
switch (cfg->func) {
|
||||
case MXC_GPIO_FUNC_IN:
|
||||
gpio->out_en_clr = cfg->mask;
|
||||
gpio->en0_set = cfg->mask;
|
||||
gpio->en1_clr = cfg->mask;
|
||||
gpio->en2_clr = cfg->mask;
|
||||
gpio->out_en_clr = cfg->mask;
|
||||
gpio->en0_set = cfg->mask;
|
||||
gpio->en1_clr = cfg->mask;
|
||||
gpio->en2_clr = cfg->mask;
|
||||
break;
|
||||
|
||||
|
||||
case MXC_GPIO_FUNC_OUT:
|
||||
gpio->out_en_set = cfg->mask;
|
||||
gpio->en0_set = cfg->mask;
|
||||
gpio->en1_clr = cfg->mask;
|
||||
gpio->en2_clr = cfg->mask;
|
||||
gpio->out_en_set = cfg->mask;
|
||||
gpio->en0_set = cfg->mask;
|
||||
gpio->en1_clr = cfg->mask;
|
||||
gpio->en2_clr = cfg->mask;
|
||||
break;
|
||||
|
||||
|
||||
case MXC_GPIO_FUNC_ALT1:
|
||||
gpio->en0_clr = cfg->mask;
|
||||
gpio->en1_clr = cfg->mask;
|
||||
gpio->en2_clr = cfg->mask;
|
||||
gpio->en0_clr = cfg->mask;
|
||||
gpio->en1_clr = cfg->mask;
|
||||
gpio->en2_clr = cfg->mask;
|
||||
break;
|
||||
|
||||
|
||||
case MXC_GPIO_FUNC_ALT2:
|
||||
gpio->en0_clr = cfg->mask;
|
||||
gpio->en1_set = cfg->mask;
|
||||
gpio->en2_clr = cfg->mask;
|
||||
gpio->en0_clr = cfg->mask;
|
||||
gpio->en1_set = cfg->mask;
|
||||
gpio->en2_clr = cfg->mask;
|
||||
break;
|
||||
|
||||
|
||||
case MXC_GPIO_FUNC_ALT3:
|
||||
gpio->en0_set = cfg->mask;
|
||||
gpio->en1_set = cfg->mask;
|
||||
gpio->en0_set = cfg->mask;
|
||||
gpio->en1_set = cfg->mask;
|
||||
// gpio->en2_set |= cfg->mask;
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
// Configure the pad
|
||||
switch(cfg->pad) {
|
||||
switch (cfg->pad) {
|
||||
case MXC_GPIO_PAD_NONE:
|
||||
gpio->pad_cfg1 &= ~cfg->mask;
|
||||
break;
|
||||
|
||||
|
||||
case MXC_GPIO_PAD_PULL_UP:
|
||||
gpio->pad_cfg1 |= cfg->mask;
|
||||
gpio->pad_cfg1 |= cfg->mask;
|
||||
gpio->ps |= cfg->mask;
|
||||
break;
|
||||
|
||||
|
||||
case MXC_GPIO_PAD_PULL_DOWN:
|
||||
gpio->pad_cfg1 |= cfg->mask;
|
||||
gpio->pad_cfg1 |= cfg->mask;
|
||||
gpio->ps &= ~cfg->mask;
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
// Configure the vssel
|
||||
MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask);
|
||||
|
||||
return E_NO_ERROR;
|
||||
return MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask);
|
||||
}
|
||||
|
||||
uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t *port, uint32_t mask)
|
||||
{
|
||||
return MXC_GPIO_RevA_InGet((mxc_gpio_reva_regs_t*) port, mask);
|
||||
return MXC_GPIO_RevA_InGet((mxc_gpio_reva_regs_t *)port, mask);
|
||||
}
|
||||
|
||||
void MXC_GPIO_OutSet(mxc_gpio_regs_t *port, uint32_t mask)
|
||||
{
|
||||
MXC_GPIO_RevA_OutSet((mxc_gpio_reva_regs_t*) port, mask);
|
||||
MXC_GPIO_RevA_OutSet((mxc_gpio_reva_regs_t *)port, mask);
|
||||
}
|
||||
|
||||
void MXC_GPIO_OutClr(mxc_gpio_regs_t *port, uint32_t mask)
|
||||
{
|
||||
MXC_GPIO_RevA_OutClr((mxc_gpio_reva_regs_t*) port, mask);
|
||||
MXC_GPIO_RevA_OutClr((mxc_gpio_reva_regs_t *)port, mask);
|
||||
}
|
||||
|
||||
uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t *port, uint32_t mask)
|
||||
{
|
||||
return MXC_GPIO_RevA_OutGet((mxc_gpio_reva_regs_t*) port, mask);
|
||||
return MXC_GPIO_RevA_OutGet((mxc_gpio_reva_regs_t *)port, mask);
|
||||
}
|
||||
|
||||
void MXC_GPIO_OutPut(mxc_gpio_regs_t *port, uint32_t mask, uint32_t val)
|
||||
{
|
||||
MXC_GPIO_RevA_OutPut((mxc_gpio_reva_regs_t*) port, mask, val);
|
||||
MXC_GPIO_RevA_OutPut((mxc_gpio_reva_regs_t *)port, mask, val);
|
||||
}
|
||||
|
||||
void MXC_GPIO_OutToggle(mxc_gpio_regs_t *port, uint32_t mask)
|
||||
{
|
||||
MXC_GPIO_RevA_OutToggle((mxc_gpio_reva_regs_t*) port, mask);
|
||||
MXC_GPIO_RevA_OutToggle((mxc_gpio_reva_regs_t *)port, mask);
|
||||
}
|
||||
|
||||
int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol)
|
||||
|
|
@ -177,12 +173,12 @@ int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol)
|
|||
|
||||
void MXC_GPIO_EnableInt(mxc_gpio_regs_t *port, uint32_t mask)
|
||||
{
|
||||
MXC_GPIO_RevA_EnableInt((mxc_gpio_reva_regs_t*) port, mask);
|
||||
MXC_GPIO_RevA_EnableInt((mxc_gpio_reva_regs_t *)port, mask);
|
||||
}
|
||||
|
||||
void MXC_GPIO_DisableInt(mxc_gpio_regs_t *port, uint32_t mask)
|
||||
{
|
||||
MXC_GPIO_RevA_DisableInt((mxc_gpio_reva_regs_t*) port, mask);
|
||||
MXC_GPIO_RevA_DisableInt((mxc_gpio_reva_regs_t *)port, mask);
|
||||
}
|
||||
|
||||
void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn func, void *cbdata)
|
||||
|
|
@ -197,15 +193,30 @@ void MXC_GPIO_Handler(unsigned int port)
|
|||
|
||||
void MXC_GPIO_ClearFlags(mxc_gpio_regs_t *port, uint32_t flags)
|
||||
{
|
||||
MXC_GPIO_RevA_ClearFlags((mxc_gpio_reva_regs_t*) port, flags);
|
||||
MXC_GPIO_RevA_ClearFlags((mxc_gpio_reva_regs_t *)port, flags);
|
||||
}
|
||||
|
||||
uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port)
|
||||
{
|
||||
return MXC_GPIO_RevA_GetFlags((mxc_gpio_reva_regs_t*) port);
|
||||
return MXC_GPIO_RevA_GetFlags((mxc_gpio_reva_regs_t *)port);
|
||||
}
|
||||
|
||||
int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask)
|
||||
{
|
||||
return MXC_GPIO_RevA_SetVSSEL((mxc_gpio_reva_regs_t*) port, vssel, mask);
|
||||
return MXC_GPIO_RevA_SetVSSEL((mxc_gpio_reva_regs_t *)port, vssel, mask);
|
||||
}
|
||||
|
||||
void MXC_GPIO_SetWakeEn(mxc_gpio_regs_t *port, uint32_t mask)
|
||||
{
|
||||
MXC_GPIO_RevA_SetWakeEn((mxc_gpio_reva_regs_t *)port, mask);
|
||||
}
|
||||
|
||||
void MXC_GPIO_ClearWakeEn(mxc_gpio_regs_t *port, uint32_t mask)
|
||||
{
|
||||
MXC_GPIO_RevA_ClearWakeEn((mxc_gpio_reva_regs_t *)port, mask);
|
||||
}
|
||||
|
||||
uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port)
|
||||
{
|
||||
return MXC_GPIO_RevA_GetWakeEn((mxc_gpio_reva_regs_t *)port);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* *****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,173 +29,209 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stddef.h>
|
||||
#include "mxc_device.h"
|
||||
#include "mxc_assert.h"
|
||||
#include "mxc_errors.h"
|
||||
#include "gpio.h"
|
||||
#include "gpio_reva.h"
|
||||
#include "gpio_common.h"
|
||||
#include <stddef.h>
|
||||
|
||||
/* **** Functions **** */
|
||||
uint32_t MXC_GPIO_RevA_InGet (mxc_gpio_reva_regs_t* port, uint32_t mask)
|
||||
uint32_t MXC_GPIO_RevA_InGet(mxc_gpio_reva_regs_t *port, uint32_t mask)
|
||||
{
|
||||
return (port->in & mask);
|
||||
}
|
||||
|
||||
void MXC_GPIO_RevA_OutSet (mxc_gpio_reva_regs_t* port, uint32_t mask)
|
||||
void MXC_GPIO_RevA_OutSet(mxc_gpio_reva_regs_t *port, uint32_t mask)
|
||||
{
|
||||
port->out_set = mask;
|
||||
}
|
||||
|
||||
void MXC_GPIO_RevA_OutClr (mxc_gpio_reva_regs_t* port, uint32_t mask)
|
||||
void MXC_GPIO_RevA_OutClr(mxc_gpio_reva_regs_t *port, uint32_t mask)
|
||||
{
|
||||
port->out_clr = mask;
|
||||
}
|
||||
|
||||
uint32_t MXC_GPIO_RevA_OutGet (mxc_gpio_reva_regs_t* port, uint32_t mask)
|
||||
uint32_t MXC_GPIO_RevA_OutGet(mxc_gpio_reva_regs_t *port, uint32_t mask)
|
||||
{
|
||||
return (port->out & mask);
|
||||
}
|
||||
|
||||
void MXC_GPIO_RevA_OutPut (mxc_gpio_reva_regs_t* port, uint32_t mask, uint32_t val)
|
||||
void MXC_GPIO_RevA_OutPut(mxc_gpio_reva_regs_t *port, uint32_t mask, uint32_t val)
|
||||
{
|
||||
port->out = (port->out & ~mask) | (val & mask);
|
||||
}
|
||||
|
||||
void MXC_GPIO_RevA_OutToggle (mxc_gpio_reva_regs_t* port, uint32_t mask)
|
||||
void MXC_GPIO_RevA_OutToggle(mxc_gpio_reva_regs_t *port, uint32_t mask)
|
||||
{
|
||||
port->out ^= mask;
|
||||
}
|
||||
|
||||
int MXC_GPIO_RevA_IntConfig(const mxc_gpio_cfg_t* cfg, mxc_gpio_int_pol_t pol)
|
||||
int MXC_GPIO_RevA_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol)
|
||||
{
|
||||
mxc_gpio_reva_regs_t *gpio = (mxc_gpio_reva_regs_t*) cfg->port;
|
||||
|
||||
mxc_gpio_reva_regs_t *gpio = (mxc_gpio_reva_regs_t *)cfg->port;
|
||||
|
||||
switch (pol) {
|
||||
case MXC_GPIO_INT_HIGH:
|
||||
gpio->intpol &= ~cfg->mask;
|
||||
gpio->intpol |= cfg->mask;
|
||||
gpio->dualedge &= ~cfg->mask;
|
||||
gpio->intmode &= ~cfg->mask;
|
||||
gpio->intmode &= ~cfg->mask;
|
||||
break;
|
||||
|
||||
case MXC_GPIO_INT_FALLING: /* MXC_GPIO_INT_HIGH */
|
||||
gpio->intpol &= ~cfg->mask;
|
||||
gpio->dualedge &= ~cfg->mask;
|
||||
gpio->intmode |= cfg->mask;
|
||||
break;
|
||||
|
||||
case MXC_GPIO_INT_LOW: /* MXC_GPIO_INT_LOW */
|
||||
gpio->intpol |= cfg->mask;
|
||||
gpio->dualedge &= ~cfg->mask;
|
||||
gpio->intmode &= ~cfg->mask;
|
||||
break;
|
||||
|
||||
case MXC_GPIO_INT_RISING: /* MXC_GPIO_INT_LOW */
|
||||
gpio->intpol |= cfg->mask;
|
||||
|
||||
case MXC_GPIO_INT_FALLING: /* MXC_GPIO_INT_HIGH */
|
||||
gpio->intpol &= ~cfg->mask;
|
||||
gpio->dualedge &= ~cfg->mask;
|
||||
gpio->intmode |= cfg->mask;
|
||||
gpio->intmode |= cfg->mask;
|
||||
break;
|
||||
|
||||
|
||||
case MXC_GPIO_INT_LOW: /* MXC_GPIO_INT_LOW */
|
||||
gpio->intpol &= ~cfg->mask;
|
||||
gpio->dualedge &= ~cfg->mask;
|
||||
gpio->intmode &= ~cfg->mask;
|
||||
break;
|
||||
|
||||
case MXC_GPIO_INT_RISING: /* MXC_GPIO_INT_LOW */
|
||||
gpio->intpol |= cfg->mask;
|
||||
gpio->dualedge &= ~cfg->mask;
|
||||
gpio->intmode |= cfg->mask;
|
||||
break;
|
||||
|
||||
case MXC_GPIO_INT_BOTH:
|
||||
gpio->dualedge |= cfg->mask;
|
||||
gpio->intmode |= cfg->mask;
|
||||
gpio->dualedge |= cfg->mask;
|
||||
gpio->intmode |= cfg->mask;
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
void MXC_GPIO_RevA_EnableInt (mxc_gpio_reva_regs_t* port, uint32_t mask)
|
||||
void MXC_GPIO_RevA_EnableInt(mxc_gpio_reva_regs_t *port, uint32_t mask)
|
||||
{
|
||||
port->inten_set = mask;
|
||||
}
|
||||
|
||||
void MXC_GPIO_RevA_DisableInt (mxc_gpio_reva_regs_t* port, uint32_t mask)
|
||||
void MXC_GPIO_RevA_DisableInt(mxc_gpio_reva_regs_t *port, uint32_t mask)
|
||||
{
|
||||
port->inten_clr = mask;
|
||||
}
|
||||
|
||||
void MXC_GPIO_RevA_ClearFlags (mxc_gpio_reva_regs_t* port, uint32_t flags)
|
||||
void MXC_GPIO_RevA_ClearFlags(mxc_gpio_reva_regs_t *port, uint32_t flags)
|
||||
{
|
||||
port->intfl_clr = flags;
|
||||
port->intfl_clr = flags;
|
||||
}
|
||||
|
||||
uint32_t MXC_GPIO_RevA_GetFlags (mxc_gpio_reva_regs_t* port)
|
||||
uint32_t MXC_GPIO_RevA_GetFlags(mxc_gpio_reva_regs_t *port)
|
||||
{
|
||||
return port->intfl;
|
||||
}
|
||||
|
||||
int MXC_GPIO_RevA_SetVSSEL (mxc_gpio_reva_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask)
|
||||
int MXC_GPIO_RevA_SetVSSEL(mxc_gpio_reva_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask)
|
||||
{
|
||||
// Configure the vssel
|
||||
switch (vssel) {
|
||||
case MXC_GPIO_VSSEL_VDDIO:
|
||||
port->vssel &= ~mask;
|
||||
break;
|
||||
|
||||
|
||||
case MXC_GPIO_VSSEL_VDDIOH:
|
||||
port->vssel |= mask;
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_GPIO_RevA_SetAF (mxc_gpio_reva_regs_t* port, mxc_gpio_func_t func, uint32_t mask)
|
||||
int MXC_GPIO_RevA_SetAF(mxc_gpio_reva_regs_t *port, mxc_gpio_func_t func, uint32_t mask)
|
||||
{
|
||||
//This is required for new devices going forward.
|
||||
port->inen |= mask;
|
||||
|
||||
//Switch to I/O mode first
|
||||
port->en0_set = mask;
|
||||
|
||||
switch (func) {
|
||||
case MXC_GPIO_FUNC_IN:
|
||||
port->outen_clr = mask;
|
||||
port->en0_set = mask;
|
||||
port->en1_clr = mask;
|
||||
port->en2_clr = mask;
|
||||
break;
|
||||
|
||||
case MXC_GPIO_FUNC_OUT:
|
||||
port->outen_set = mask;
|
||||
port->en0_set = mask;
|
||||
port->en1_clr = mask;
|
||||
port->en2_clr = mask;
|
||||
break;
|
||||
|
||||
case MXC_GPIO_FUNC_ALT1:
|
||||
port->en0_clr = mask;
|
||||
port->en1_clr = mask;
|
||||
port->en2_clr = mask;
|
||||
break;
|
||||
|
||||
case MXC_GPIO_FUNC_ALT2:
|
||||
port->en0_clr = mask;
|
||||
port->en1_set = mask;
|
||||
port->en2_clr = mask;
|
||||
port->outen_clr = mask;
|
||||
port->en0_set = mask;
|
||||
port->en1_clr = mask;
|
||||
port->en2_clr = mask;
|
||||
port->en3_clr = mask;
|
||||
break;
|
||||
|
||||
#if TARGET_NUM != 32650
|
||||
case MXC_GPIO_FUNC_OUT:
|
||||
port->outen_set = mask;
|
||||
port->en0_set = mask;
|
||||
port->en1_clr = mask;
|
||||
port->en2_clr = mask;
|
||||
port->en3_clr = mask;
|
||||
break;
|
||||
|
||||
case MXC_GPIO_FUNC_ALT1:
|
||||
port->en3_clr = mask;
|
||||
port->en2_clr = mask;
|
||||
port->en1_clr = mask;
|
||||
port->en0_clr = mask;
|
||||
break;
|
||||
|
||||
case MXC_GPIO_FUNC_ALT2:
|
||||
port->en3_clr = mask;
|
||||
port->en2_clr = mask;
|
||||
port->en1_set = mask;
|
||||
port->en0_clr = mask;
|
||||
break;
|
||||
|
||||
#if TARGET_NUM != 32650
|
||||
case MXC_GPIO_FUNC_ALT3:
|
||||
port->en0_clr = mask;
|
||||
port->en1_clr = mask;
|
||||
port->en2_set = mask;
|
||||
port->en3_clr = mask;
|
||||
port->en2_set = mask;
|
||||
port->en1_clr = mask;
|
||||
port->en0_clr = mask;
|
||||
break;
|
||||
|
||||
|
||||
case MXC_GPIO_FUNC_ALT4:
|
||||
port->en0_clr = mask;
|
||||
port->en1_set = mask;
|
||||
port->en2_set = mask;
|
||||
port->en3_clr = mask;
|
||||
port->en2_set = mask;
|
||||
port->en1_set = mask;
|
||||
port->en0_clr = mask;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if TARGET_NUM == 32662
|
||||
case MXC_GPIO_FUNC_ALT5:
|
||||
port->en3_set = mask;
|
||||
port->en2_clr = mask;
|
||||
port->en1_clr = mask;
|
||||
port->en0_clr = mask;
|
||||
break;
|
||||
#endif
|
||||
#endif
|
||||
default:
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
void MXC_GPIO_RevA_SetWakeEn(mxc_gpio_reva_regs_t *port, uint32_t mask)
|
||||
{
|
||||
port->wken_set = mask;
|
||||
}
|
||||
|
||||
void MXC_GPIO_RevA_ClearWakeEn(mxc_gpio_reva_regs_t *port, uint32_t mask)
|
||||
{
|
||||
port->wken_clr = mask;
|
||||
}
|
||||
|
||||
uint32_t MXC_GPIO_RevA_GetWakeEn(mxc_gpio_reva_regs_t *port)
|
||||
{
|
||||
return port->wken;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,7 +29,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "gpio_reva_regs.h"
|
||||
|
|
@ -38,36 +41,37 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enumeration type for the pullup strength on a given pin.
|
||||
*/
|
||||
typedef enum {
|
||||
MXC_GPIO_PS_NONE, /**< No pull-up or pull-down strength required*/
|
||||
MXC_GPIO_PS_PULL_SELECT, /**< Selct pull-up or pull-down strength*/
|
||||
MXC_GPIO_PS_NONE, /**< No pull-up or pull-down strength required*/
|
||||
MXC_GPIO_PS_PULL_SELECT, /**< Selct pull-up or pull-down strength*/
|
||||
} mxc_gpio_ps_t;
|
||||
|
||||
/* **** Function Prototypes **** */
|
||||
|
||||
uint32_t MXC_GPIO_RevA_InGet (mxc_gpio_reva_regs_t* port, uint32_t mask);
|
||||
void MXC_GPIO_RevA_OutSet (mxc_gpio_reva_regs_t* port, uint32_t mask);
|
||||
void MXC_GPIO_RevA_OutClr (mxc_gpio_reva_regs_t* port, uint32_t mask);
|
||||
uint32_t MXC_GPIO_RevA_OutGet (mxc_gpio_reva_regs_t* port, uint32_t mask);
|
||||
void MXC_GPIO_RevA_OutPut (mxc_gpio_reva_regs_t* port, uint32_t mask, uint32_t val);
|
||||
void MXC_GPIO_RevA_OutToggle (mxc_gpio_reva_regs_t* port, uint32_t mask);
|
||||
int MXC_GPIO_RevA_IntConfig (const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol);
|
||||
void MXC_GPIO_RevA_EnableInt (mxc_gpio_reva_regs_t* port, uint32_t mask);
|
||||
void MXC_GPIO_RevA_DisableInt (mxc_gpio_reva_regs_t* port, uint32_t mask);
|
||||
void MXC_GPIO_RevA_ClearFlags (mxc_gpio_reva_regs_t* port, uint32_t flags);
|
||||
uint32_t MXC_GPIO_RevA_GetFlags (mxc_gpio_reva_regs_t* port);
|
||||
#if TARGET_NUM != 32650
|
||||
int MXC_GPIO_RevA_SetVSSEL (mxc_gpio_reva_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask);
|
||||
#endif
|
||||
int MXC_GPIO_RevA_SetAF (mxc_gpio_reva_regs_t* port, mxc_gpio_func_t func, uint32_t mask);
|
||||
uint32_t MXC_GPIO_RevA_InGet(mxc_gpio_reva_regs_t *port, uint32_t mask);
|
||||
void MXC_GPIO_RevA_OutSet(mxc_gpio_reva_regs_t *port, uint32_t mask);
|
||||
void MXC_GPIO_RevA_OutClr(mxc_gpio_reva_regs_t *port, uint32_t mask);
|
||||
uint32_t MXC_GPIO_RevA_OutGet(mxc_gpio_reva_regs_t *port, uint32_t mask);
|
||||
void MXC_GPIO_RevA_OutPut(mxc_gpio_reva_regs_t *port, uint32_t mask, uint32_t val);
|
||||
void MXC_GPIO_RevA_OutToggle(mxc_gpio_reva_regs_t *port, uint32_t mask);
|
||||
int MXC_GPIO_RevA_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol);
|
||||
void MXC_GPIO_RevA_EnableInt(mxc_gpio_reva_regs_t *port, uint32_t mask);
|
||||
void MXC_GPIO_RevA_DisableInt(mxc_gpio_reva_regs_t *port, uint32_t mask);
|
||||
void MXC_GPIO_RevA_ClearFlags(mxc_gpio_reva_regs_t *port, uint32_t flags);
|
||||
uint32_t MXC_GPIO_RevA_GetFlags(mxc_gpio_reva_regs_t *port);
|
||||
int MXC_GPIO_RevA_SetVSSEL(mxc_gpio_reva_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask);
|
||||
int MXC_GPIO_RevA_SetAF(mxc_gpio_reva_regs_t *port, mxc_gpio_func_t func, uint32_t mask);
|
||||
void MXC_GPIO_RevA_SetWakeEn(mxc_gpio_reva_regs_t *port, uint32_t mask);
|
||||
void MXC_GPIO_RevA_ClearWakeEn(mxc_gpio_reva_regs_t *port, uint32_t mask);
|
||||
uint32_t MXC_GPIO_RevA_GetWakeEn(mxc_gpio_reva_regs_t *port);
|
||||
|
||||
/**@} end of group gpio */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_H_
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,10 +1,10 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files(the "Software"),
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
|
|
@ -15,7 +15,7 @@
|
|||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
|
|
@ -24,12 +24,12 @@
|
|||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stddef.h>
|
||||
|
|
@ -42,7 +42,7 @@
|
|||
#include "mxc_delay.h"
|
||||
#include "i2c_regs.h"
|
||||
#include "dma_regs.h"
|
||||
#include "mxc_i2c.h"
|
||||
#include "i2c.h"
|
||||
#include "i2c_reva.h"
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
|
@ -382,6 +382,16 @@ unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t *i2c)
|
|||
return MXC_I2C_RevA_GetTXThreshold((mxc_i2c_reva_regs_t *)i2c);
|
||||
}
|
||||
|
||||
void MXC_I2C_AsyncStop(mxc_i2c_regs_t *i2c)
|
||||
{
|
||||
MXC_I2C_RevA_AsyncStop((mxc_i2c_reva_regs_t *)i2c);
|
||||
}
|
||||
|
||||
void MXC_I2C_AbortAsync(mxc_i2c_regs_t *i2c)
|
||||
{
|
||||
MXC_I2C_RevA_AbortAsync((mxc_i2c_reva_regs_t *)i2c);
|
||||
}
|
||||
|
||||
void MXC_I2C_AsyncHandler(mxc_i2c_regs_t *i2c)
|
||||
{
|
||||
MXC_I2C_RevA_AsyncHandler((mxc_i2c_reva_regs_t *)i2c, interruptCheck);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stddef.h>
|
||||
|
|
@ -40,7 +40,7 @@
|
|||
#include "mxc_sys.h"
|
||||
#include "mxc_delay.h"
|
||||
#include "i2c_regs.h"
|
||||
#include "mxc_i2c.h"
|
||||
#include "i2c.h"
|
||||
#include "i2c_reva.h"
|
||||
#include "dma.h"
|
||||
|
||||
|
|
@ -66,9 +66,8 @@ void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c);
|
|||
void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c);
|
||||
void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum);
|
||||
int MXC_I2C_RevA_DMAHandler(mxc_i2c_reva_req_t *req);
|
||||
unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
|
||||
mxc_i2c_reva_slave_handler_t callback,
|
||||
unsigned int interruptEnables, int *retVal);
|
||||
void MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback,
|
||||
uint32_t *int_en, int *retVal);
|
||||
|
||||
/* ************************************************************************* */
|
||||
/* Control/Configuration functions */
|
||||
|
|
@ -145,8 +144,8 @@ int MXC_I2C_RevA_SetFrequency(mxc_i2c_reva_regs_t *i2c, unsigned int hz)
|
|||
return E_NULL_PTR;
|
||||
}
|
||||
|
||||
if (hz > MXC_I2C_REVA_FASTPLUS_SPEED) {
|
||||
// We're going to enable high speed
|
||||
if (hz > MXC_I2C_REVA_FASTPLUS_SPEED && hz <= MXC_I2C_REVA_HIGH_SPEED) {
|
||||
// Enable high speed mode
|
||||
int hsLowClks, hsHiClks;
|
||||
|
||||
// Calculate the period of SCL and set up 33% duty cycle
|
||||
|
|
@ -164,7 +163,17 @@ int MXC_I2C_RevA_SetFrequency(mxc_i2c_reva_regs_t *i2c, unsigned int hz)
|
|||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
hsLowClks = (hsLowClks << MXC_F_I2C_REVA_HSCLK_LO_POS) & MXC_F_I2C_REVA_HSCLK_LO;
|
||||
hsHiClks = (hsHiClks << MXC_F_I2C_REVA_HSCLK_HI_POS) & MXC_F_I2C_REVA_HSCLK_HI;
|
||||
|
||||
i2c->hsclk = (hsLowClks | hsHiClks);
|
||||
|
||||
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_HS_EN;
|
||||
|
||||
hz = MXC_I2C_REVA_FAST_SPEED; // High speed preambles will be sent at 400kHz
|
||||
|
||||
} else if (hz > MXC_I2C_REVA_HIGH_SPEED) {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
// Calculate the period of SCL, 50% duty cycle
|
||||
|
|
@ -805,7 +814,7 @@ int MXC_I2C_RevA_MasterTransaction(mxc_i2c_reva_req_t *req)
|
|||
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART;
|
||||
} else {
|
||||
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP;
|
||||
|
||||
|
||||
while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_STOP)) {}
|
||||
// Wait for Transaction to finish
|
||||
}
|
||||
|
|
@ -1017,9 +1026,12 @@ void MXC_I2C_RevA_DMACallback(int ch, int error)
|
|||
int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback,
|
||||
uint32_t interruptCheck)
|
||||
{
|
||||
unsigned int interruptEnables = interruptCheck;
|
||||
int retVal = E_NO_ERROR;
|
||||
|
||||
uint32_t int_en[2];
|
||||
int_en[0] = interruptCheck;
|
||||
int_en[1] = 0;
|
||||
|
||||
if (MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c) < 0) {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
|
@ -1050,8 +1062,8 @@ int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_h
|
|||
// I2C_EVT_UNDERFLOW
|
||||
// I2C_EVT_OVERFLOW
|
||||
|
||||
while (interruptEnables > 0) {
|
||||
interruptEnables = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, interruptEnables, &retVal);
|
||||
while (int_en[0] > 0 || int_en[1] > 0) {
|
||||
MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, int_en, &retVal);
|
||||
}
|
||||
|
||||
return retVal;
|
||||
|
|
@ -1270,9 +1282,8 @@ void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum)
|
|||
}
|
||||
}
|
||||
|
||||
unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
|
||||
mxc_i2c_reva_slave_handler_t callback,
|
||||
unsigned int interruptEnables, int *retVal)
|
||||
void MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback,
|
||||
uint32_t *int_en, int *retVal)
|
||||
{
|
||||
uint32_t tFlags = i2c->intfl0;
|
||||
*retVal = E_NO_ERROR;
|
||||
|
|
@ -1294,9 +1305,8 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
|
|||
// I2C_EVT_TRANS_COMP
|
||||
// I2C_EVT_UNDERFLOW
|
||||
// I2C_EVT_OVERFLOW
|
||||
if (!(interruptEnables &
|
||||
(MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH |
|
||||
MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) {
|
||||
if (!(int_en[0] & (MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH |
|
||||
MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) {
|
||||
// The STOPERR/STARTERR interrupt that's enabled here could fire before we are addressed
|
||||
// (fires anytime a stop/start is detected out of sequence).
|
||||
if (tFlags & MXC_I2C_REVA_ERROR) {
|
||||
|
|
@ -1310,11 +1320,12 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
|
|||
MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts
|
||||
MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c);
|
||||
MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c);
|
||||
interruptEnables = 0;
|
||||
int_en[0] = 0;
|
||||
int_en[1] = 0;
|
||||
AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL;
|
||||
}
|
||||
|
||||
if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV)) {
|
||||
if (int_en[0] & MXC_F_I2C_REVA_INTFL0_RX_THD || int_en[1] & MXC_F_I2C_REVA_INTFL1_RX_OV) {
|
||||
if (tFlags & MXC_F_I2C_REVA_INTFL0_RX_THD) {
|
||||
if (callback != NULL) {
|
||||
callback(i2c, MXC_I2C_REVA_EVT_RX_THRESH, NULL);
|
||||
|
|
@ -1332,8 +1343,8 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
|
|||
}
|
||||
}
|
||||
|
||||
if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN |
|
||||
MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT)) {
|
||||
if (int_en[0] & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT) ||
|
||||
int_en[1] & MXC_F_I2C_REVA_INTFL1_TX_UN) {
|
||||
if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_THD) {
|
||||
if (callback != NULL) {
|
||||
callback(i2c, MXC_I2C_REVA_EVT_TX_THRESH, NULL);
|
||||
|
|
@ -1358,7 +1369,8 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
|
|||
}
|
||||
|
||||
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT;
|
||||
interruptEnables = 0;
|
||||
int_en[0] = 0;
|
||||
int_en[1] = 0;
|
||||
AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL;
|
||||
}
|
||||
}
|
||||
|
|
@ -1371,7 +1383,8 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
|
|||
}
|
||||
|
||||
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_STOP;
|
||||
interruptEnables = 0;
|
||||
int_en[0] = 0;
|
||||
int_en[1] = 0;
|
||||
AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL;
|
||||
}
|
||||
}
|
||||
|
|
@ -1383,8 +1396,10 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
|
|||
|
||||
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH;
|
||||
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
|
||||
interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV |
|
||||
MXC_I2C_REVA_ERROR;
|
||||
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT;
|
||||
|
||||
int_en[0] = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE | MXC_I2C_REVA_ERROR;
|
||||
int_en[1] = MXC_F_I2C_REVA_INTFL1_RX_OV;
|
||||
}
|
||||
|
||||
if (tFlags & MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH) {
|
||||
|
|
@ -1394,8 +1409,9 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
|
|||
|
||||
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH;
|
||||
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
|
||||
interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN |
|
||||
MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR;
|
||||
int_en[0] = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT |
|
||||
MXC_I2C_REVA_ERROR;
|
||||
int_en[1] = MXC_F_I2C_REVA_INTFL1_TX_UN;
|
||||
}
|
||||
|
||||
if (tFlags & MXC_F_I2C_REVA_INTFL0_ADDR_MATCH) {
|
||||
|
|
@ -1404,19 +1420,23 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
|
|||
callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL);
|
||||
}
|
||||
|
||||
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH;
|
||||
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
|
||||
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
|
||||
interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN |
|
||||
MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR;
|
||||
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT;
|
||||
|
||||
int_en[0] = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT |
|
||||
MXC_I2C_REVA_ERROR;
|
||||
int_en[1] = MXC_F_I2C_REVA_INTFL1_TX_UN;
|
||||
} else {
|
||||
if (callback != NULL) {
|
||||
callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL);
|
||||
}
|
||||
|
||||
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH;
|
||||
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
|
||||
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH;
|
||||
interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV |
|
||||
MXC_I2C_REVA_ERROR;
|
||||
int_en[0] = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE |
|
||||
MXC_I2C_REVA_ERROR;
|
||||
int_en[1] = MXC_F_I2C_REVA_INTFL1_RX_OV;
|
||||
}
|
||||
} else if (tFlags & MXC_I2C_REVA_ERROR) {
|
||||
*retVal = E_COMM_ERR;
|
||||
|
|
@ -1429,17 +1449,17 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
|
|||
MXC_I2C_REVA_INTFL1_MASK); // clear all i2c interrupts
|
||||
MXC_I2C_RevA_ClearTXFIFO(i2c);
|
||||
MXC_I2C_RevA_ClearRXFIFO(i2c);
|
||||
interruptEnables = 0;
|
||||
int_en[0] = 0;
|
||||
int_en[1] = 0;
|
||||
AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL;
|
||||
}
|
||||
|
||||
return interruptEnables;
|
||||
}
|
||||
|
||||
void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck)
|
||||
{
|
||||
int i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c);
|
||||
int slaveRetVal;
|
||||
uint32_t int_en[2];
|
||||
|
||||
if (i2cNum < 0) {
|
||||
return;
|
||||
|
|
@ -1449,6 +1469,13 @@ void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck
|
|||
MXC_I2C_RevA_MasterAsyncHandler(i2cNum);
|
||||
} else {
|
||||
mxc_i2c_reva_slave_handler_t callback = (mxc_i2c_reva_slave_handler_t)AsyncRequests[i2cNum];
|
||||
i2c->inten0 = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, i2c->inten0, &slaveRetVal);
|
||||
|
||||
int_en[0] = i2c->inten0;
|
||||
int_en[1] = i2c->inten1;
|
||||
|
||||
MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, int_en, &slaveRetVal);
|
||||
|
||||
i2c->inten0 = int_en[0];
|
||||
i2c->inten1 = int_en[1];
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_
|
||||
|
|
@ -51,7 +51,7 @@
|
|||
#define MXC_I2C_REVA_STD_MODE 100000
|
||||
#define MXC_I2C_REVA_FAST_SPEED 400000
|
||||
#define MXC_I2C_REVA_FASTPLUS_SPEED 1000000
|
||||
#define MXC_I2C_REVA_HS_MODE 3400000
|
||||
#define MXC_I2C_REVA_HIGH_SPEED 3400000
|
||||
|
||||
#define MXC_I2C_REVA_INTFL0_MASK 0x00FFFFFF
|
||||
#define MXC_I2C_REVA_INTFL1_MASK 0x00000007
|
||||
|
|
@ -163,9 +163,8 @@ void MXC_I2C_RevA_AsyncCallback(mxc_i2c_reva_regs_t *i2c, int retVal);
|
|||
void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c);
|
||||
void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c);
|
||||
void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum);
|
||||
unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c,
|
||||
mxc_i2c_reva_slave_handler_t callback,
|
||||
unsigned int interruptEnables, int *retVal);
|
||||
void MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback,
|
||||
uint32_t *int_en, int *retVal);
|
||||
void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck);
|
||||
void MXC_I2C_RevA_DMACallback(int ch, int error);
|
||||
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,8 +34,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* *****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_device.h"
|
||||
|
|
@ -38,6 +38,7 @@
|
|||
#include "mxc_sys.h"
|
||||
#include "icc.h"
|
||||
#include "icc_reva.h"
|
||||
#include "icc_common.h"
|
||||
|
||||
void MXC_ICC_Com_Flush(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,7 +29,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_COMMON_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_COMMON_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_sys.h"
|
||||
|
|
@ -48,3 +51,5 @@ void MXC_ICC_Com_Flush(void);
|
|||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_COMMON_H_
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* *****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_device.h"
|
||||
|
|
@ -42,22 +42,22 @@
|
|||
|
||||
/* **** Functions **** */
|
||||
|
||||
int MXC_ICC_ID (mxc_icc_info_t cid)
|
||||
int MXC_ICC_ID(mxc_icc_info_t cid)
|
||||
{
|
||||
return MXC_ICC_RevA_ID ((mxc_icc_reva_regs_t*) MXC_ICC, cid);
|
||||
return MXC_ICC_RevA_ID((mxc_icc_reva_regs_t *)MXC_ICC, cid);
|
||||
}
|
||||
|
||||
void MXC_ICC_Enable (void)
|
||||
void MXC_ICC_Enable(void)
|
||||
{
|
||||
MXC_ICC_RevA_Enable ((mxc_icc_reva_regs_t*) MXC_ICC);
|
||||
MXC_ICC_RevA_Enable((mxc_icc_reva_regs_t *)MXC_ICC);
|
||||
}
|
||||
|
||||
void MXC_ICC_Disable (void)
|
||||
void MXC_ICC_Disable(void)
|
||||
{
|
||||
MXC_ICC_RevA_Disable ((mxc_icc_reva_regs_t*) MXC_ICC);
|
||||
MXC_ICC_RevA_Disable((mxc_icc_reva_regs_t *)MXC_ICC);
|
||||
}
|
||||
|
||||
void MXC_ICC_Flush (void)
|
||||
void MXC_ICC_Flush(void)
|
||||
{
|
||||
MXC_ICC_Com_Flush();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
/* *****************************************************************************
|
||||
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files(the "Software"),
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stddef.h>
|
||||
|
|
@ -38,6 +38,7 @@
|
|||
#include "mxc_assert.h"
|
||||
#include "mxc_sys.h"
|
||||
#include "icc.h"
|
||||
#include "icc_reva.h"
|
||||
#include "icc_reva_regs.h"
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
|
@ -45,27 +46,27 @@
|
|||
/* **** Globals **** */
|
||||
|
||||
/* **** Functions **** */
|
||||
static int MXC_ICC_Ready(mxc_icc_reva_regs_t* icc)
|
||||
static int MXC_ICC_Ready(mxc_icc_reva_regs_t *icc)
|
||||
{
|
||||
return (icc->ctrl & MXC_F_ICC_REVA_CTRL_RDY);
|
||||
}
|
||||
|
||||
int MXC_ICC_RevA_ID(mxc_icc_reva_regs_t* icc, mxc_icc_info_t cid)
|
||||
int MXC_ICC_RevA_ID(mxc_icc_reva_regs_t *icc, mxc_icc_info_t cid)
|
||||
{
|
||||
if(icc == NULL) {
|
||||
if (icc == NULL) {
|
||||
return E_NULL_PTR;
|
||||
}
|
||||
|
||||
switch(cid) {
|
||||
switch (cid) {
|
||||
case ICC_INFO_RELNUM:
|
||||
return ((icc->info & MXC_F_ICC_REVA_INFO_RELNUM) >> MXC_F_ICC_REVA_INFO_RELNUM_POS);
|
||||
|
||||
|
||||
case ICC_INFO_PARTNUM:
|
||||
return ((icc->info & MXC_F_ICC_REVA_INFO_PARTNUM) >> MXC_F_ICC_REVA_INFO_PARTNUM_POS);
|
||||
|
||||
|
||||
case ICC_INFO_ID:
|
||||
return ((icc->info & MXC_F_ICC_REVA_INFO_ID) >> MXC_F_ICC_REVA_INFO_ID_POS);
|
||||
|
||||
|
||||
default:
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
|
@ -76,15 +77,15 @@ void MXC_ICC_RevA_Enable(mxc_icc_reva_regs_t *icc)
|
|||
// Invalidate cache and wait until ready
|
||||
icc->ctrl &= ~MXC_F_ICC_REVA_CTRL_EN;
|
||||
icc->invalidate = 1;
|
||||
|
||||
while(!(MXC_ICC_Ready(icc)));
|
||||
|
||||
|
||||
while (!(MXC_ICC_Ready(icc))) {}
|
||||
|
||||
// Enable Cache
|
||||
icc->ctrl |= MXC_F_ICC_REVA_CTRL_EN;
|
||||
while(!(MXC_ICC_Ready(icc)));
|
||||
while (!(MXC_ICC_Ready(icc))) {}
|
||||
}
|
||||
|
||||
void MXC_ICC_RevA_Disable(mxc_icc_reva_regs_t* icc)
|
||||
void MXC_ICC_RevA_Disable(mxc_icc_reva_regs_t *icc)
|
||||
{
|
||||
// Disable Cache
|
||||
icc->ctrl &= ~MXC_F_ICC_REVA_CTRL_EN;
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
/* *****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software");,
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
|
|
@ -29,7 +29,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_device.h"
|
||||
|
|
@ -45,6 +48,8 @@
|
|||
|
||||
/* **** Functions **** */
|
||||
|
||||
int MXC_ICC_RevA_ID (mxc_icc_reva_regs_t* icc, mxc_icc_info_t cid);
|
||||
void MXC_ICC_RevA_Enable (mxc_icc_reva_regs_t* icc);
|
||||
void MXC_ICC_RevA_Disable (mxc_icc_reva_regs_t* icc);
|
||||
int MXC_ICC_RevA_ID(mxc_icc_reva_regs_t *icc, mxc_icc_info_t cid);
|
||||
void MXC_ICC_RevA_Enable(mxc_icc_reva_regs_t *icc);
|
||||
void MXC_ICC_RevA_Disable(mxc_icc_reva_regs_t *icc);
|
||||
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Registers, Bit Masks and Bit Positions for the ICC_REVA Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,11 +34,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _ICC_REVA_REGS_H_
|
||||
#define _ICC_REVA_REGS_H_
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_REGS_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -46,11 +45,11 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__ICCARM__)
|
||||
#pragma system_include
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__CC_ARM)
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
|
@ -101,10 +100,10 @@ typedef struct {
|
|||
* @brief ICC_REVA Peripheral Register Offsets from the ICC_REVA Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_ICC_REVA_INFO ((uint32_t)0x00000000UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_ICC_REVA_SZ ((uint32_t)0x00000004UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_ICC_REVA_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0100</tt> */
|
||||
#define MXC_R_ICC_REVA_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0700</tt> */
|
||||
#define MXC_R_ICC_REVA_INFO ((uint32_t)0x00000000UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0000</tt> */
|
||||
#define MXC_R_ICC_REVA_SZ ((uint32_t)0x00000004UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0004</tt> */
|
||||
#define MXC_R_ICC_REVA_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0100</tt> */
|
||||
#define MXC_R_ICC_REVA_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0700</tt> */
|
||||
/**@} end of group icc_reva_registers */
|
||||
|
||||
/**
|
||||
|
|
@ -113,14 +112,14 @@ typedef struct {
|
|||
* @brief Cache ID Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ICC_REVA_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */
|
||||
#define MXC_F_ICC_REVA_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */
|
||||
#define MXC_F_ICC_REVA_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */
|
||||
#define MXC_F_ICC_REVA_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */
|
||||
|
||||
#define MXC_F_ICC_REVA_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */
|
||||
#define MXC_F_ICC_REVA_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_REVA_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */
|
||||
#define MXC_F_ICC_REVA_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */
|
||||
#define MXC_F_ICC_REVA_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_REVA_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */
|
||||
|
||||
#define MXC_F_ICC_REVA_INFO_ID_POS 10 /**< INFO_ID Position */
|
||||
#define MXC_F_ICC_REVA_INFO_ID ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_ID_POS)) /**< INFO_ID Mask */
|
||||
#define MXC_F_ICC_REVA_INFO_ID_POS 10 /**< INFO_ID Position */
|
||||
#define MXC_F_ICC_REVA_INFO_ID ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_ID_POS)) /**< INFO_ID Mask */
|
||||
|
||||
/**@} end of group ICC_REVA_INFO_Register */
|
||||
|
||||
|
|
@ -130,11 +129,11 @@ typedef struct {
|
|||
* @brief Memory Configuration Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ICC_REVA_SZ_CCH_POS 0 /**< SZ_CCH Position */
|
||||
#define MXC_F_ICC_REVA_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_CCH_POS)) /**< SZ_CCH Mask */
|
||||
#define MXC_F_ICC_REVA_SZ_CCH_POS 0 /**< SZ_CCH Position */
|
||||
#define MXC_F_ICC_REVA_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_CCH_POS)) /**< SZ_CCH Mask */
|
||||
|
||||
#define MXC_F_ICC_REVA_SZ_MEM_POS 16 /**< SZ_MEM Position */
|
||||
#define MXC_F_ICC_REVA_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_MEM_POS)) /**< SZ_MEM Mask */
|
||||
#define MXC_F_ICC_REVA_SZ_MEM_POS 16 /**< SZ_MEM Position */
|
||||
#define MXC_F_ICC_REVA_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_MEM_POS)) /**< SZ_MEM Mask */
|
||||
|
||||
/**@} end of group ICC_REVA_SZ_Register */
|
||||
|
||||
|
|
@ -144,11 +143,11 @@ typedef struct {
|
|||
* @brief Cache Control and Status Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ICC_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */
|
||||
#define MXC_F_ICC_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */
|
||||
#define MXC_F_ICC_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */
|
||||
#define MXC_F_ICC_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */
|
||||
|
||||
#define MXC_F_ICC_REVA_CTRL_RDY_POS 16 /**< CTRL_RDY Position */
|
||||
#define MXC_F_ICC_REVA_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
|
||||
#define MXC_F_ICC_REVA_CTRL_RDY_POS 16 /**< CTRL_RDY Position */
|
||||
#define MXC_F_ICC_REVA_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
|
||||
|
||||
/**@} end of group ICC_REVA_CTRL_Register */
|
||||
|
||||
|
|
@ -156,4 +155,5 @@ typedef struct {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ICC_REVA_REGS_H_ */
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_ICC_ICC_REVA_REGS_H_
|
||||
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Low power functions
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,14 +34,11 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
******************************************************************************/
|
||||
|
||||
/***** Includes *****/
|
||||
#include "lp.h"
|
||||
#include "pwrseq_regs.h"
|
||||
#include "mxc_errors.h"
|
||||
#include "gcr_regs.h"
|
||||
#include "mxc_device.h"
|
||||
#include "mxc_errors.h"
|
||||
|
|
@ -56,7 +53,7 @@ void MXC_LP_ClearWakeStatus(void)
|
|||
MXC_PWRSEQ->lp_wakefl = 0xFFFFFFFF;
|
||||
|
||||
/* These flags are slow to clear, so block until they do */
|
||||
while(MXC_PWRSEQ->lp_wakefl & (MXC_PWRSEQ->lpwk_en));
|
||||
while (MXC_PWRSEQ->lp_wakefl & (MXC_PWRSEQ->lpwk_en)) {}
|
||||
}
|
||||
|
||||
void MXC_LP_EnableSRAM3(void)
|
||||
|
|
@ -153,66 +150,65 @@ void MXC_LP_EnableRTCAlarmWakeup(void)
|
|||
{
|
||||
MXC_GCR->pm |= MXC_F_GCR_PM_RTCWK_EN;
|
||||
}
|
||||
|
||||
|
||||
void MXC_LP_DisableRTCAlarmWakeup(void)
|
||||
{
|
||||
MXC_GCR->pm &= ~MXC_F_GCR_PM_RTCWK_EN;
|
||||
}
|
||||
|
||||
void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask)
|
||||
void MXC_LP_EnableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins)
|
||||
{
|
||||
MXC_GCR->pm |= MXC_F_GCR_PM_GPIOWK_EN;
|
||||
//switch(port)
|
||||
//switch(wu_pins->port)
|
||||
//{
|
||||
/*case 0:*/ MXC_PWRSEQ->lpwk_en |= mask; //break;
|
||||
/*case 0:*/ MXC_PWRSEQ->lpwk_en |= wu_pins->mask; //break;
|
||||
//}
|
||||
}
|
||||
|
||||
void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask)
|
||||
void MXC_LP_DisableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins)
|
||||
{
|
||||
//switch(port)
|
||||
//switch(wu_pins->port)
|
||||
//{
|
||||
/* case 0:*/ MXC_PWRSEQ->lpwk_en &= ~mask; //break;
|
||||
/* case 0:*/ MXC_PWRSEQ->lpwk_en &= ~wu_pins->mask; //break;
|
||||
//}
|
||||
|
||||
if(MXC_PWRSEQ->lpwk_en == 0)
|
||||
{
|
||||
|
||||
if (MXC_PWRSEQ->lpwk_en == 0) {
|
||||
MXC_GCR->pm &= ~MXC_F_GCR_PM_GPIOWK_EN;
|
||||
}
|
||||
}
|
||||
|
||||
void MXC_LP_EnterSleepMode(void)
|
||||
{
|
||||
// Clear SLEEPDEEP bit
|
||||
{
|
||||
// Clear SLEEPDEEP bit
|
||||
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
// Go into Sleep mode and wait for an interrupt to wake the processor
|
||||
// Go into Sleep mode and wait for an interrupt to wake the processor
|
||||
__WFI();
|
||||
}
|
||||
|
||||
void MXC_LP_EnterDeepSleepMode(void)
|
||||
{
|
||||
// Set SLEEPDEEP bit
|
||||
{
|
||||
// Set SLEEPDEEP bit
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
// Auto-powerdown 96 MHz oscillator when in deep sleep
|
||||
// Auto-powerdown 96 MHz oscillator when in deep sleep
|
||||
MXC_GCR->pm |= MXC_F_GCR_PM_HFIOPD;
|
||||
// Go into Deepsleep mode and wait for an interrupt to wake the processor
|
||||
// Go into Deepsleep mode and wait for an interrupt to wake the processor
|
||||
__WFI();
|
||||
}
|
||||
|
||||
void MXC_LP_EnterBackupMode(void)
|
||||
{
|
||||
{
|
||||
MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE;
|
||||
MXC_GCR->pm |= MXC_S_GCR_PM_MODE_BACKUP;
|
||||
while(1);
|
||||
while (1) {}
|
||||
}
|
||||
|
||||
void MXC_LP_EnterShutdownMode(void)
|
||||
{
|
||||
MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE;
|
||||
MXC_GCR->pm |= MXC_S_GCR_PM_MODE_SHUTDOWN;
|
||||
while(1);
|
||||
while (1) {}
|
||||
}
|
||||
|
||||
int MXC_LP_SetOperatingVoltage(mxc_lp_ovr_t ovr)
|
||||
|
|
@ -221,28 +217,29 @@ int MXC_LP_SetOperatingVoltage(mxc_lp_ovr_t ovr)
|
|||
int error;
|
||||
|
||||
// Ensure part is operating from internal LDO for core power
|
||||
if(MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_LDO_DIS) {
|
||||
if (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_LDO_DIS) {
|
||||
return E_BAD_STATE;
|
||||
}
|
||||
|
||||
// Select the 8KHz nanoring (no guarantee 32KHz is attached) as system clock source
|
||||
current_clock = MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL;
|
||||
if(current_clock == MXC_SYS_CLOCK_HIRC) {
|
||||
if (current_clock == MXC_SYS_CLOCK_HIRC) {
|
||||
error = MXC_SYS_Clock_Select(MXC_SYS_CLOCK_NANORING);
|
||||
if(error != E_NO_ERROR) {
|
||||
if (error != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
}
|
||||
|
||||
// Set flash wait state for any clock so its not to low after clock changes.
|
||||
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x5UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
|
||||
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) |
|
||||
(0x5UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
|
||||
|
||||
// Set the OVR bits
|
||||
MXC_PWRSEQ->lp_ctrl &= ~(MXC_F_PWRSEQ_LP_CTRL_OVR);
|
||||
MXC_PWRSEQ->lp_ctrl |= ovr;
|
||||
|
||||
// Set LVE bit
|
||||
if(ovr == MXC_LP_OVR_0_9) {
|
||||
if (ovr == MXC_LP_OVR_0_9) {
|
||||
MXC_FLC->ctrl |= MXC_F_FLC_CTRL_LVE;
|
||||
|
||||
} else {
|
||||
|
|
@ -250,11 +247,11 @@ int MXC_LP_SetOperatingVoltage(mxc_lp_ovr_t ovr)
|
|||
}
|
||||
|
||||
// Revert the clock to original state if it was HIRC
|
||||
if(current_clock == MXC_SYS_CLOCK_HIRC) {
|
||||
error = MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC);
|
||||
if(error != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
if (current_clock == MXC_SYS_CLOCK_HIRC) {
|
||||
error = MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC);
|
||||
if (error != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
}
|
||||
|
||||
// Update SystemCoreClock variable
|
||||
|
|
@ -264,132 +261,162 @@ int MXC_LP_SetOperatingVoltage(mxc_lp_ovr_t ovr)
|
|||
div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_PSC) >> MXC_F_GCR_CLK_CTRL_PSC_POS;
|
||||
|
||||
// Set Flash Wait States
|
||||
if(ovr == MXC_LP_OVR_0_9) {
|
||||
if(div == 0) {
|
||||
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
|
||||
if (ovr == MXC_LP_OVR_0_9) {
|
||||
if (div == 0) {
|
||||
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) |
|
||||
(0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
|
||||
|
||||
} else {
|
||||
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
|
||||
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) |
|
||||
(0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
|
||||
}
|
||||
|
||||
} else if(ovr == MXC_LP_OVR_1_0) {
|
||||
if(div == 0) {
|
||||
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
|
||||
} else if (ovr == MXC_LP_OVR_1_0) {
|
||||
if (div == 0) {
|
||||
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) |
|
||||
(0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
|
||||
|
||||
} else {
|
||||
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
|
||||
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) |
|
||||
(0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
|
||||
}
|
||||
|
||||
} else {
|
||||
if(div == 0) {
|
||||
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x4UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
|
||||
|
||||
} else if(div == 1) {
|
||||
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
|
||||
if (div == 0) {
|
||||
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) |
|
||||
(0x4UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
|
||||
|
||||
} else if (div == 1) {
|
||||
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) |
|
||||
(0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
|
||||
|
||||
} else {
|
||||
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
|
||||
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) |
|
||||
(0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
|
||||
}
|
||||
}
|
||||
|
||||
// Caller must perform peripheral reset
|
||||
|
||||
return E_NO_ERROR;
|
||||
|
||||
}
|
||||
|
||||
void MXC_LP_EnableSRamRet0(void){
|
||||
void MXC_LP_EnableSRamRet0(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0;
|
||||
}
|
||||
|
||||
void MXC_LP_DisableSRamRet0(void){
|
||||
|
||||
void MXC_LP_DisableSRamRet0(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0;
|
||||
}
|
||||
|
||||
void MXC_LP_EnableSRamRet1(void){
|
||||
void MXC_LP_EnableSRamRet1(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1;
|
||||
}
|
||||
|
||||
void MXC_LP_DisableSRamRet1(void){
|
||||
|
||||
void MXC_LP_DisableSRamRet1(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1;
|
||||
}
|
||||
|
||||
void MXC_LP_EnableSRamRet2(void){
|
||||
void MXC_LP_EnableSRamRet2(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2;
|
||||
}
|
||||
|
||||
void MXC_LP_DisableSRamRet2(void){
|
||||
|
||||
void MXC_LP_DisableSRamRet2(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2;
|
||||
}
|
||||
|
||||
void MXC_LP_EnableSRamRet3(void){
|
||||
void MXC_LP_EnableSRamRet3(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3;
|
||||
}
|
||||
|
||||
void MXC_LP_DisableSRamRet3(void){
|
||||
|
||||
void MXC_LP_DisableSRamRet3(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3;
|
||||
}
|
||||
|
||||
void MXC_LP_EnableBlockDetect(void){
|
||||
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS;
|
||||
void MXC_LP_EnableBlockDetect(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS;
|
||||
}
|
||||
|
||||
void MXC_LP_DisableBlockDetect(void){
|
||||
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS;
|
||||
void MXC_LP_DisableBlockDetect(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS;
|
||||
}
|
||||
|
||||
void MXC_LP_EnableRamRetReg(void){
|
||||
void MXC_LP_EnableRamRetReg(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RETREG_EN;
|
||||
}
|
||||
|
||||
void MXC_LP_DisableRamRetReg(void){
|
||||
void MXC_LP_DisableRamRetReg(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RETREG_EN;
|
||||
}
|
||||
|
||||
void MXC_LP_EnableFastWk(void){
|
||||
void MXC_LP_EnableFastWk(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN;
|
||||
}
|
||||
|
||||
void MXC_LP_DisableFastWk(void){
|
||||
void MXC_LP_DisableFastWk(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN;
|
||||
}
|
||||
|
||||
void MXC_LP_EnableBandGap(void){
|
||||
void MXC_LP_EnableBandGap(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_BG_OFF;
|
||||
}
|
||||
|
||||
void MXC_LP_DisableBandGap(void){
|
||||
void MXC_LP_DisableBandGap(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_BG_OFF;
|
||||
}
|
||||
|
||||
void MXC_LP_EnableVCorePORSignal(void){
|
||||
void MXC_LP_EnableVCorePORSignal(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS;
|
||||
}
|
||||
|
||||
void MXC_LP_DisableVCorePORSignal(void){
|
||||
void MXC_LP_DisableVCorePORSignal(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS;
|
||||
}
|
||||
|
||||
void MXC_LP_EnableLDO(void){
|
||||
void MXC_LP_EnableLDO(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_LDO_DIS;
|
||||
}
|
||||
|
||||
void MXC_LP_DisableLDO(void){
|
||||
void MXC_LP_DisableLDO(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_LDO_DIS;
|
||||
}
|
||||
|
||||
void MXC_LP_EnableVCoreSVM(void){
|
||||
void MXC_LP_EnableVCoreSVM(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS;
|
||||
}
|
||||
|
||||
void MXC_LP_DisableVCoreSVM(void){
|
||||
void MXC_LP_DisableVCoreSVM(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS;
|
||||
}
|
||||
|
||||
void MXC_LP_EnableVDDIOPorMonitoF(void){
|
||||
void MXC_LP_EnableVDDIOPorMonitoF(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS;
|
||||
}
|
||||
|
||||
void MXC_LP_DisableVDDIOPorMonitor(void){
|
||||
void MXC_LP_DisableVDDIOPorMonitor(void)
|
||||
{
|
||||
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#include "mxc_device.h"
|
||||
#include "rtc_regs.h"
|
||||
|
|
@ -43,77 +43,109 @@
|
|||
|
||||
/* ***** Functions ***** */
|
||||
|
||||
int MXC_RTC_EnableInt (uint32_t mask)
|
||||
int MXC_RTC_EnableInt(uint32_t mask)
|
||||
{
|
||||
return MXC_RTC_RevA_EnableInt ((mxc_rtc_reva_regs_t*) MXC_RTC, mask);
|
||||
return MXC_RTC_RevA_EnableInt((mxc_rtc_reva_regs_t *)MXC_RTC, mask);
|
||||
}
|
||||
|
||||
int MXC_RTC_DisableInt (uint32_t mask)
|
||||
int MXC_RTC_DisableInt(uint32_t mask)
|
||||
{
|
||||
return MXC_RTC_RevA_DisableInt ((mxc_rtc_reva_regs_t*) MXC_RTC, mask);
|
||||
return MXC_RTC_RevA_DisableInt((mxc_rtc_reva_regs_t *)MXC_RTC, mask);
|
||||
}
|
||||
|
||||
int MXC_RTC_SetTimeofdayAlarm (uint32_t ras)
|
||||
int MXC_RTC_SetTimeofdayAlarm(uint32_t ras)
|
||||
{
|
||||
return MXC_RTC_RevA_SetTimeofdayAlarm ((mxc_rtc_reva_regs_t*) MXC_RTC, ras);
|
||||
return MXC_RTC_RevA_SetTimeofdayAlarm((mxc_rtc_reva_regs_t *)MXC_RTC, ras);
|
||||
}
|
||||
|
||||
int MXC_RTC_SetSubsecondAlarm (uint32_t rssa)
|
||||
int MXC_RTC_SetSubsecondAlarm(uint32_t rssa)
|
||||
{
|
||||
return MXC_RTC_RevA_SetSubsecondAlarm ((mxc_rtc_reva_regs_t*) MXC_RTC, rssa);
|
||||
return MXC_RTC_RevA_SetSubsecondAlarm((mxc_rtc_reva_regs_t *)MXC_RTC, rssa);
|
||||
}
|
||||
|
||||
int MXC_RTC_Start (void)
|
||||
int MXC_RTC_Start(void)
|
||||
{
|
||||
return MXC_RTC_RevA_Start ((mxc_rtc_reva_regs_t*) MXC_RTC);
|
||||
return MXC_RTC_RevA_Start((mxc_rtc_reva_regs_t *)MXC_RTC);
|
||||
}
|
||||
|
||||
int MXC_RTC_Stop (void)
|
||||
int MXC_RTC_Stop(void)
|
||||
{
|
||||
return MXC_RTC_RevA_Stop ((mxc_rtc_reva_regs_t*) MXC_RTC);
|
||||
return MXC_RTC_RevA_Stop((mxc_rtc_reva_regs_t *)MXC_RTC);
|
||||
}
|
||||
|
||||
int MXC_RTC_Init (uint32_t sec, uint8_t ssec)
|
||||
int MXC_RTC_Init(uint32_t sec, uint8_t ssec)
|
||||
{
|
||||
// Enable clock
|
||||
MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN;
|
||||
|
||||
return MXC_RTC_RevA_Init ((mxc_rtc_reva_regs_t*) MXC_RTC, sec, ssec);
|
||||
|
||||
return MXC_RTC_RevA_Init((mxc_rtc_reva_regs_t *)MXC_RTC, sec, (ssec & MXC_F_RTC_SSEC_RTSS));
|
||||
}
|
||||
|
||||
int MXC_RTC_SquareWave (mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft)
|
||||
int MXC_RTC_SquareWave(mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft)
|
||||
{
|
||||
MXC_GPIO_Config (&gpio_cfg_32kcal);
|
||||
|
||||
return MXC_RTC_RevA_SquareWave ((mxc_rtc_reva_regs_t*) MXC_RTC, sqe, ft);
|
||||
MXC_GPIO_Config(&gpio_cfg_32kcal);
|
||||
|
||||
return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t *)MXC_RTC, sqe, ft);
|
||||
}
|
||||
|
||||
int MXC_RTC_Trim (int8_t trm)
|
||||
int MXC_RTC_SquareWaveStart(mxc_rtc_freq_sel_t fq)
|
||||
{
|
||||
return MXC_RTC_RevA_Trim ((mxc_rtc_reva_regs_t*) MXC_RTC, trm);
|
||||
MXC_GPIO_Config(&gpio_cfg_32kcal);
|
||||
|
||||
return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t *)MXC_RTC, MXC_RTC_REVA_SQUARE_WAVE_ENABLED,
|
||||
fq);
|
||||
}
|
||||
|
||||
int MXC_RTC_GetFlags (void)
|
||||
int MXC_RTC_SquareWaveStop(void)
|
||||
{
|
||||
return MXC_RTC_RevA_GetFlags();
|
||||
return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t *)MXC_RTC,
|
||||
MXC_RTC_REVA_SQUARE_WAVE_DISABLED, 0);
|
||||
}
|
||||
|
||||
int MXC_RTC_ClearFlags (int flags)
|
||||
int MXC_RTC_Trim(int8_t trm)
|
||||
{
|
||||
return MXC_RTC_RevA_ClearFlags (flags);
|
||||
return MXC_RTC_RevA_Trim((mxc_rtc_reva_regs_t *)MXC_RTC, trm);
|
||||
}
|
||||
|
||||
int MXC_RTC_GetSubSecond (void)
|
||||
int MXC_RTC_GetFlags(void)
|
||||
{
|
||||
return MXC_RTC_RevA_GetSubSecond();
|
||||
return MXC_RTC_RevA_GetFlags((mxc_rtc_reva_regs_t *)MXC_RTC);
|
||||
}
|
||||
|
||||
int MXC_RTC_GetSecond (void)
|
||||
int MXC_RTC_ClearFlags(int flags)
|
||||
{
|
||||
return MXC_RTC_RevA_GetSecond();
|
||||
return MXC_RTC_RevA_ClearFlags((mxc_rtc_reva_regs_t *)MXC_RTC, flags);
|
||||
}
|
||||
|
||||
int MXC_RTC_GetTime (uint32_t* sec, uint32_t* subsec)
|
||||
int MXC_RTC_GetSubSecond(void)
|
||||
{
|
||||
return MXC_RTC_RevA_GetTime (sec, subsec);
|
||||
MXC_RTC->ctrl &= ~MXC_F_RTC_CTRL_RDY; // Ensure valid data is in SSEC register
|
||||
while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {}
|
||||
|
||||
return MXC_RTC_RevA_GetSubSecond((mxc_rtc_reva_regs_t *)MXC_RTC);
|
||||
}
|
||||
|
||||
int MXC_RTC_GetSecond(void)
|
||||
{
|
||||
MXC_RTC->ctrl &= ~MXC_F_RTC_CTRL_RDY; // Ensure valid data is in SEC register
|
||||
while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {}
|
||||
|
||||
return MXC_RTC_RevA_GetSecond((mxc_rtc_reva_regs_t *)MXC_RTC);
|
||||
}
|
||||
|
||||
int MXC_RTC_GetTime(uint32_t *sec, uint32_t *subsec)
|
||||
{
|
||||
return MXC_RTC_RevA_GetTime((mxc_rtc_reva_regs_t *)MXC_RTC, sec, subsec);
|
||||
}
|
||||
|
||||
int MXC_RTC_GetBusyFlag(void)
|
||||
{
|
||||
return MXC_RTC_RevA_GetBusyFlag((mxc_rtc_reva_regs_t *)MXC_RTC);
|
||||
}
|
||||
|
||||
int MXC_RTC_TrimCrystal(mxc_tmr_regs_t *tmr)
|
||||
{
|
||||
/* MAX32660 does not have a clock source which can
|
||||
be used as the reference clock for the trim function */
|
||||
return E_NOT_SUPPORTED;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,346 +29,395 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include "mxc_device.h"
|
||||
#include "rtc.h"
|
||||
#include "mxc_sys.h"
|
||||
#include "mxc_delay.h"
|
||||
|
||||
#include "gpio_regs.h"
|
||||
#include "mxc_delay.h"
|
||||
#include "mxc_device.h"
|
||||
#include "mxc_errors.h"
|
||||
#include "mxc_sys.h"
|
||||
#include "rtc.h"
|
||||
#include "rtc_reva.h"
|
||||
#include "tmr.h"
|
||||
|
||||
#if TARGET_NUM == 32650
|
||||
#include "pwrseq_regs.h"
|
||||
#include "pwrseq_regs.h"
|
||||
#endif
|
||||
|
||||
int MXC_RTC_CheckBusy(void)
|
||||
void MXC_RTC_Wait_BusyToClear(void)
|
||||
{
|
||||
// Time-out transfer if it takes > BUSY_TIMEOUT microseconds
|
||||
MXC_DelayAsync(MXC_DELAY_USEC(MXC_BUSY_TIMEOUT), NULL);
|
||||
while (MXC_RTC_REVA_IS_BUSY) {}
|
||||
}
|
||||
|
||||
while (MXC_RTC_REVA_IS_BUSY) {
|
||||
if (MXC_DelayCheck() != E_BUSY) {
|
||||
return E_BUSY;
|
||||
}
|
||||
int MXC_RTC_RevA_GetBusyFlag(mxc_rtc_reva_regs_t *rtc)
|
||||
{
|
||||
if (MXC_RTC_REVA_IS_BUSY) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
MXC_DelayAbort();
|
||||
return E_SUCCESS;
|
||||
}
|
||||
|
||||
int MXC_RTC_RevA_EnableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask)
|
||||
int MXC_RTC_RevA_EnableInt(mxc_rtc_reva_regs_t *rtc, uint32_t mask)
|
||||
{
|
||||
mask &= (MXC_RTC_INT_EN_LONG | MXC_RTC_INT_EN_SHORT | MXC_RTC_INT_EN_READY);
|
||||
|
||||
mask &= (MXC_RTC_INT_EN_LONG | MXC_RTC_INT_EN_SHORT | MXC_RTC_INT_EN_READY);
|
||||
|
||||
if (!mask) {
|
||||
/* No bits set? Wasn't something we can enable. */
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
rtc->ctrl |= mask;
|
||||
|
||||
|
||||
/* If TOD and SSEC interrupt enable, check busy after CTRL register write*/
|
||||
mask &= ~MXC_RTC_INT_EN_READY;
|
||||
|
||||
if (mask) {
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
}
|
||||
return E_SUCCESS;
|
||||
}
|
||||
|
||||
int MXC_RTC_RevA_DisableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask)
|
||||
int MXC_RTC_RevA_DisableInt(mxc_rtc_reva_regs_t *rtc, uint32_t mask)
|
||||
{
|
||||
mask &= (MXC_RTC_INT_EN_LONG | MXC_RTC_INT_EN_SHORT | MXC_RTC_INT_EN_READY);
|
||||
|
||||
mask &= (MXC_RTC_INT_EN_LONG | MXC_RTC_INT_EN_SHORT | MXC_RTC_INT_EN_READY);
|
||||
|
||||
if (!mask) {
|
||||
/* No bits set? Wasn't something we can enable. */
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
rtc->ctrl &= ~mask;
|
||||
|
||||
|
||||
/* If TOD and SSEC interrupt enable, check busy after CTRL register write*/
|
||||
mask &= ~MXC_RTC_INT_EN_READY;
|
||||
|
||||
if (mask) {
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
}
|
||||
return E_SUCCESS;
|
||||
}
|
||||
|
||||
int MXC_RTC_RevA_SetTimeofdayAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t ras)
|
||||
int MXC_RTC_RevA_SetTimeofdayAlarm(mxc_rtc_reva_regs_t *rtc, uint32_t ras)
|
||||
{
|
||||
// ras can only be written if BUSY = 0 & (RTCE = 0 or ADE = 0);
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
if (MXC_RTC_RevA_GetBusyFlag(rtc)) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
||||
rtc->toda = (ras << MXC_F_RTC_REVA_TODA_TOD_ALARM_POS) & MXC_F_RTC_REVA_TODA_TOD_ALARM;
|
||||
|
||||
|
||||
return E_SUCCESS;
|
||||
}
|
||||
|
||||
int MXC_RTC_RevA_SetSubsecondAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t rssa)
|
||||
int MXC_RTC_RevA_SetSubsecondAlarm(mxc_rtc_reva_regs_t *rtc, uint32_t rssa)
|
||||
{
|
||||
// ras can only be written if BUSY = 0 & (RTCE = 0 or ASE = 0);
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
if (MXC_RTC_RevA_GetBusyFlag(rtc)) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
||||
rtc->sseca = (rssa << MXC_F_RTC_REVA_SSECA_SSEC_ALARM_POS) & MXC_F_RTC_REVA_SSECA_SSEC_ALARM;
|
||||
|
||||
|
||||
return E_SUCCESS;
|
||||
}
|
||||
|
||||
int MXC_RTC_RevA_Start (mxc_rtc_reva_regs_t *rtc)
|
||||
int MXC_RTC_RevA_Start(mxc_rtc_reva_regs_t *rtc)
|
||||
{
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
if (MXC_RTC_RevA_GetBusyFlag(rtc)) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
||||
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
// Can only write if WE=1 and BUSY=0
|
||||
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 1
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing...
|
||||
|
||||
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 1
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing...
|
||||
|
||||
return E_SUCCESS;
|
||||
}
|
||||
|
||||
int MXC_RTC_RevA_Stop (mxc_rtc_reva_regs_t *rtc)
|
||||
int MXC_RTC_RevA_Stop(mxc_rtc_reva_regs_t *rtc)
|
||||
{
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
if (MXC_RTC_RevA_GetBusyFlag(rtc)) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
||||
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
// Can only write if WE=1 and BUSY=0
|
||||
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 0
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing...
|
||||
|
||||
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 0
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing...
|
||||
|
||||
return E_SUCCESS;
|
||||
}
|
||||
|
||||
int MXC_RTC_RevA_Init (mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint8_t ssec)
|
||||
int MXC_RTC_RevA_Init(mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint32_t ssec)
|
||||
{
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
if (MXC_RTC_RevA_GetBusyFlag(rtc)) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
rtc->ctrl = MXC_F_RTC_REVA_CTRL_WR_EN; // Allow Writes
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
rtc->ctrl = MXC_RTC_REVA_CTRL_RESET_DEFAULT; // Start with a Clean Register
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Set Write Enable, allow writing to reg.
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
||||
rtc->ctrl = MXC_F_RTC_REVA_CTRL_WR_EN; // Allow Writes
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
rtc->ctrl = MXC_RTC_REVA_CTRL_RESET_DEFAULT; // Start with a Clean Register
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Set Write Enable, allow writing to reg.
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
rtc->ssec = ssec;
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
rtc->sec = sec;
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing...
|
||||
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing...
|
||||
|
||||
return E_SUCCESS;
|
||||
}
|
||||
|
||||
int MXC_RTC_RevA_SquareWave (mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft)
|
||||
int MXC_RTC_RevA_SquareWave(mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe,
|
||||
mxc_rtc_freq_sel_t ft)
|
||||
{
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
if (MXC_RTC_RevA_GetBusyFlag(rtc)) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
||||
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
if (sqe == MXC_RTC_REVA_SQUARE_WAVE_ENABLED) {
|
||||
if (ft == MXC_RTC_F_32KHZ) { // if 32KHz output is selected...
|
||||
rtc->oscctrl |= MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Enable 32KHz wave
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_SQW_EN; // Enable output on the pin
|
||||
if (ft == MXC_RTC_F_32KHZ) { // if 32KHz output is selected...
|
||||
rtc->oscctrl |= MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Enable 32KHz wave
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_SQW_EN; // Enable output on the pin
|
||||
} else { // if 1Hz, 512Hz, 4KHz output is selected
|
||||
rtc->oscctrl &=
|
||||
~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_SQW_SEL;
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
rtc->ctrl |= (MXC_F_RTC_REVA_CTRL_SQW_EN | ft); // Enable Sq. wave,
|
||||
}
|
||||
else { // if 1Hz, 512Hz, 4KHz output is selected
|
||||
|
||||
rtc->oscctrl &= ~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
rtc->ctrl &= ~ MXC_F_RTC_REVA_CTRL_SQW_SEL;
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
rtc->ctrl |= (MXC_F_RTC_REVA_CTRL_SQW_EN | ft); // Enable Sq. wave,
|
||||
}
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // Enable Real Time Clock
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // Enable Real Time Clock
|
||||
} else { // Turn off the square wave output on the pin
|
||||
rtc->oscctrl &=
|
||||
~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_SQW_EN; // No sq. wave output
|
||||
}
|
||||
else { // Turn off the square wave output on the pin
|
||||
|
||||
rtc->oscctrl &= ~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_SQW_EN; // No sq. wave output
|
||||
}
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Disable Writing to register
|
||||
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Disable Writing to register
|
||||
|
||||
return E_SUCCESS;
|
||||
}
|
||||
|
||||
int MXC_RTC_RevA_Trim (mxc_rtc_reva_regs_t *rtc, int8_t trim)
|
||||
int MXC_RTC_RevA_Trim(mxc_rtc_reva_regs_t *rtc, int8_t trim)
|
||||
{
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
if (MXC_RTC_RevA_GetBusyFlag(rtc)) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
||||
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN;
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
MXC_SETFIELD (rtc->trim, MXC_F_RTC_REVA_TRIM_TRIM, trim << MXC_F_RTC_REVA_TRIM_TRIM_POS);
|
||||
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Disable Writing to register
|
||||
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
MXC_SETFIELD(rtc->trim, MXC_F_RTC_REVA_TRIM_TRIM, trim << MXC_F_RTC_REVA_TRIM_TRIM_POS);
|
||||
|
||||
MXC_RTC_Wait_BusyToClear();
|
||||
|
||||
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Disable Writing to register
|
||||
|
||||
return E_SUCCESS;
|
||||
}
|
||||
|
||||
int MXC_RTC_RevA_GetFlags(void)
|
||||
int MXC_RTC_RevA_GetFlags(mxc_rtc_reva_regs_t *rtc)
|
||||
{
|
||||
return MXC_RTC->ctrl & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY);
|
||||
return rtc->ctrl & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY);
|
||||
}
|
||||
|
||||
int MXC_RTC_RevA_ClearFlags(int flags)
|
||||
int MXC_RTC_RevA_ClearFlags(mxc_rtc_reva_regs_t *rtc, int flags)
|
||||
{
|
||||
if (MXC_RTC_CheckBusy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
MXC_RTC->ctrl &= ~(flags & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY));
|
||||
|
||||
rtc->ctrl &= ~(flags & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY));
|
||||
|
||||
return E_SUCCESS;
|
||||
}
|
||||
|
||||
int MXC_RTC_RevA_GetSubSecond(void)
|
||||
int MXC_RTC_RevA_GetSubSecond(mxc_rtc_reva_regs_t *rtc)
|
||||
{
|
||||
if (MXC_RTC_RevA_GetBusyFlag(rtc)) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
#if TARGET_NUM == 32650
|
||||
int ssec;
|
||||
if(ChipRevision > 0xA1){
|
||||
ssec = ((MXC_PWRSEQ->ctrl >> 12)& 0xF00) | (MXC_RTC->ssec & 0xFF);
|
||||
}else{
|
||||
ssec = MXC_RTC->ssec;
|
||||
if (ChipRevision > 0xA1) {
|
||||
ssec = ((MXC_PWRSEQ->ctrl >> 12) & 0xF00) | (rtc->ssec & 0xFF);
|
||||
} else {
|
||||
ssec = rtc->ssec;
|
||||
}
|
||||
return ssec;
|
||||
return ssec;
|
||||
#else
|
||||
return MXC_RTC->ssec;
|
||||
return rtc->ssec;
|
||||
#endif
|
||||
}
|
||||
|
||||
int MXC_RTC_RevA_GetSecond(void)
|
||||
int MXC_RTC_RevA_GetSecond(mxc_rtc_reva_regs_t *rtc)
|
||||
{
|
||||
return MXC_RTC->sec;
|
||||
if (MXC_RTC_RevA_GetBusyFlag(rtc)) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
return rtc->sec;
|
||||
}
|
||||
|
||||
int MXC_RTC_RevA_GetTime(uint32_t* sec, uint32_t* subsec)
|
||||
int MXC_RTC_RevA_GetTime(mxc_rtc_reva_regs_t *rtc, uint32_t *sec, uint32_t *subsec)
|
||||
{
|
||||
uint32_t temp_sec;
|
||||
|
||||
uint32_t temp_sec = 0;
|
||||
|
||||
if (sec == NULL || subsec == NULL) {
|
||||
return E_NULL_PTR;
|
||||
}
|
||||
|
||||
|
||||
do {
|
||||
// Check if an update is about to happen.
|
||||
if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) {
|
||||
if (!(rtc->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
||||
// Read the seconds count.
|
||||
temp_sec = MXC_RTC_RevA_GetSecond();
|
||||
|
||||
// Check if an update is about to happen.
|
||||
if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) {
|
||||
temp_sec = MXC_RTC_RevA_GetSecond(rtc);
|
||||
|
||||
if (temp_sec == E_BUSY) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
||||
// Check if an update is about to happen.
|
||||
if (!(rtc->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
// Read the sub-seconds count.
|
||||
*subsec = MXC_RTC_RevA_GetSubSecond();
|
||||
|
||||
*subsec = MXC_RTC_RevA_GetSubSecond(rtc);
|
||||
|
||||
// Check if an update is about to happen.
|
||||
if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) {
|
||||
if (!(rtc->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
||||
// Read the seconds count.
|
||||
*sec = MXC_RTC_RevA_GetSecond();
|
||||
|
||||
*sec = MXC_RTC_RevA_GetSecond(rtc);
|
||||
|
||||
// Repeat until a steady state is reached.
|
||||
}
|
||||
while (temp_sec != *sec);
|
||||
|
||||
} while (temp_sec != *sec);
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_RTC_RevA_TrimCrystal(mxc_rtc_reva_regs_t *rtc, mxc_tmr_regs_t *tmr)
|
||||
{
|
||||
int err, ppm = 0;
|
||||
uint32_t sec = 0, ssec = 0, ctrl = 0;
|
||||
uint32_t sec_sample[MXC_RTC_REVA_TRIM_PERIODS + 1] = { 0 };
|
||||
uint32_t ssec_sample[MXC_RTC_REVA_TRIM_PERIODS + 1] = { 0 };
|
||||
bool rtc_en = true;
|
||||
|
||||
if (!(rtc->ctrl & MXC_F_RTC_REVA_CTRL_EN)) { // If RTC not enable, initialize it
|
||||
rtc_en = false;
|
||||
while ((sec = MXC_RTC_RevA_GetSecond(rtc)) < 0) {}
|
||||
// Save state
|
||||
while ((ssec = MXC_RTC_RevA_GetSubSecond(rtc)) < 0) {}
|
||||
while (rtc->ctrl & MXC_F_RTC_CTRL_BUSY) {}
|
||||
ctrl = rtc->ctrl;
|
||||
|
||||
if ((err = MXC_RTC_Init(0, 0)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
MXC_RTC_Start();
|
||||
}
|
||||
|
||||
MXC_TMR_ClearFlags(tmr);
|
||||
MXC_TMR_Start(tmr); // Sample the RTC ticks in MXC_RTC_REVA_TRIM_PERIODS number of periods
|
||||
while ((sec_sample[0] = MXC_RTC_RevA_GetSecond(rtc)) < 0) {}
|
||||
while ((ssec_sample[0] = MXC_RTC_RevA_GetSubSecond(rtc)) < 0) {}
|
||||
|
||||
for (int i = 1; i < (MXC_RTC_REVA_TRIM_PERIODS + 1); i++) {
|
||||
while (!(MXC_TMR_GetFlags(tmr) & MXC_RTC_TRIM_TMR_IRQ)) {}
|
||||
// Wait for time trim period to elapse
|
||||
|
||||
while ((sec_sample[i] = MXC_RTC_RevA_GetSecond(rtc)) < 0) {}
|
||||
// Take time sample
|
||||
while ((ssec_sample[i] = MXC_RTC_RevA_GetSubSecond(rtc)) < 0) {}
|
||||
|
||||
MXC_TMR_ClearFlags(tmr);
|
||||
}
|
||||
|
||||
MXC_TMR_Stop(tmr); // Shutdown timer
|
||||
MXC_TMR_Shutdown(tmr);
|
||||
|
||||
if (!rtc_en) { // If RTC wasn't enabled entering the function, restore state
|
||||
MXC_RTC_Stop();
|
||||
|
||||
while (rtc->ctrl & MXC_F_RTC_REVA_CTRL_BUSY) {}
|
||||
MXC_SETFIELD(rtc->ssec, MXC_F_RTC_REVA_SSEC_SSEC, (ssec << MXC_F_RTC_REVA_SSEC_SSEC_POS));
|
||||
while (rtc->ctrl & MXC_F_RTC_REVA_CTRL_BUSY) {}
|
||||
MXC_SETFIELD(rtc->sec, MXC_F_RTC_REVA_SEC_SEC, (sec << MXC_F_RTC_REVA_SEC_SEC_POS));
|
||||
while (rtc->ctrl & MXC_F_RTC_REVA_CTRL_BUSY) {}
|
||||
rtc->ctrl = ctrl;
|
||||
}
|
||||
|
||||
for (int i = 0; i < MXC_RTC_REVA_TRIM_PERIODS;
|
||||
i++) { // Get total error in RTC ticks over MXC_RTC_REVA_TRIM_PERIODS number of sample periods
|
||||
if (sec_sample[i] < sec_sample[i + 1]) {
|
||||
ppm += MXC_RTC_REVA_TICKS_PER_PERIOD -
|
||||
((MXC_RTC_MAX_SSEC - ssec_sample[i]) + ssec_sample[i + 1]);
|
||||
} else {
|
||||
ppm += MXC_RTC_REVA_TICKS_PER_PERIOD - (ssec_sample[i + 1] - ssec_sample[i]);
|
||||
}
|
||||
}
|
||||
|
||||
ppm /= MXC_RTC_REVA_TRIM_PERIODS;
|
||||
ppm = PPM(ppm); // Convert total error to PPM and set trim
|
||||
if (ppm < -128 || ppm > 127) {
|
||||
return E_OVERFLOW;
|
||||
}
|
||||
|
||||
return MXC_RTC_RevA_Trim(rtc, (int8_t)ppm); // Set Trim
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,38 +29,51 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_RTC_RTC_REVA_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_RTC_RTC_REVA_H_
|
||||
|
||||
#include "gpio.h"
|
||||
#include "mxc_delay.h"
|
||||
#include "mxc_device.h"
|
||||
#include "mxc_errors.h"
|
||||
#include "mxc_sys.h"
|
||||
#include "rtc_reva_regs.h"
|
||||
#include "rtc.h"
|
||||
#include "mxc_sys.h"
|
||||
#include "mxc_delay.h"
|
||||
#include "gpio.h"
|
||||
#include "mxc_errors.h"
|
||||
#include "tmr.h"
|
||||
|
||||
typedef enum {
|
||||
MXC_RTC_REVA_SQUARE_WAVE_DISABLED, ///< Sq. wave output disabled
|
||||
MXC_RTC_REVA_SQUARE_WAVE_ENABLED, ///< Sq. wave output enabled
|
||||
MXC_RTC_REVA_SQUARE_WAVE_ENABLED, ///< Sq. wave output enabled
|
||||
} mxc_rtc_reva_sqwave_en_t;
|
||||
|
||||
#define MXC_RTC_REVA_CTRL_RESET_DEFAULT (0x0000UL)
|
||||
#define MXC_RTC_REVA_IS_BUSY (MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_BUSY)
|
||||
#define MXC_RTC_REVA_IS_ENABLED (MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RTCE)
|
||||
#define MXC_RTC_REVA_IS_BUSY (MXC_F_RTC_REVA_CTRL_BUSY & MXC_RTC->ctrl)
|
||||
#define MXC_RTC_REVA_IS_ENABLED (MXC_F_RTC_REVA_CTRL_RTCE & MXC_RTC->ctrl)
|
||||
|
||||
#define MXC_BUSY_TIMEOUT 1000 // Timeout counts for the Busy bit
|
||||
#define MXC_RTC_REVA_TRIM_PERIODS 5
|
||||
#define MXC_RTC_REVA_TICKS_PER_PERIOD (MXC_RTC_MAX_SSEC / MXC_RTC_REVA_TRIM_PERIODS)
|
||||
#define PPM(ppm) ((ppm * 1000000) / 4096)
|
||||
|
||||
int MXC_RTC_RevA_Init (mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint8_t ssec);
|
||||
int MXC_RTC_RevA_EnableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask);
|
||||
int MXC_RTC_RevA_DisableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask);
|
||||
int MXC_RTC_RevA_SetTimeofdayAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t ras);
|
||||
int MXC_RTC_RevA_SetSubsecondAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t rssa);
|
||||
int MXC_RTC_RevA_Start (mxc_rtc_reva_regs_t *rtc);
|
||||
int MXC_RTC_RevA_Stop (mxc_rtc_reva_regs_t *rtc);
|
||||
int MXC_RTC_RevA_SquareWave (mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft);
|
||||
int MXC_RTC_RevA_Trim (mxc_rtc_reva_regs_t *rtc, int8_t trm);
|
||||
int MXC_RTC_RevA_GetFlags (void);
|
||||
int MXC_RTC_RevA_ClearFlags (int flags);
|
||||
int MXC_RTC_RevA_GetSubSecond (void);
|
||||
int MXC_RTC_RevA_GetSecond (void);
|
||||
int MXC_RTC_RevA_GetTime (uint32_t* sec, uint32_t* subsec);
|
||||
#define MXC_BUSY_TIMEOUT 1000 // Timeout counts for the Busy bit
|
||||
|
||||
int MXC_RTC_RevA_Init(mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint32_t ssec);
|
||||
int MXC_RTC_RevA_EnableInt(mxc_rtc_reva_regs_t *rtc, uint32_t mask);
|
||||
int MXC_RTC_RevA_DisableInt(mxc_rtc_reva_regs_t *rtc, uint32_t mask);
|
||||
int MXC_RTC_RevA_SetTimeofdayAlarm(mxc_rtc_reva_regs_t *rtc, uint32_t ras);
|
||||
int MXC_RTC_RevA_SetSubsecondAlarm(mxc_rtc_reva_regs_t *rtc, uint32_t rssa);
|
||||
int MXC_RTC_RevA_Start(mxc_rtc_reva_regs_t *rtc);
|
||||
int MXC_RTC_RevA_Stop(mxc_rtc_reva_regs_t *rtc);
|
||||
int MXC_RTC_RevA_SquareWave(mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe,
|
||||
mxc_rtc_freq_sel_t ft);
|
||||
int MXC_RTC_RevA_Trim(mxc_rtc_reva_regs_t *rtc, int8_t trm);
|
||||
int MXC_RTC_RevA_GetFlags(mxc_rtc_reva_regs_t *rtc);
|
||||
int MXC_RTC_RevA_ClearFlags(mxc_rtc_reva_regs_t *rtc, int flags);
|
||||
int MXC_RTC_RevA_GetSubSecond(mxc_rtc_reva_regs_t *rtc);
|
||||
int MXC_RTC_RevA_GetSecond(mxc_rtc_reva_regs_t *rtc);
|
||||
int MXC_RTC_RevA_GetTime(mxc_rtc_reva_regs_t *rtc, uint32_t *sec, uint32_t *subsec);
|
||||
int MXC_RTC_RevA_GetBusyFlag(mxc_rtc_reva_regs_t *rtc);
|
||||
int MXC_RTC_RevA_TrimCrystal(mxc_rtc_reva_regs_t *rtc, mxc_tmr_regs_t *tmr);
|
||||
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_RTC_RTC_REVA_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,8 +34,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _RTC_REVA_REGS_H_
|
||||
#define _RTC_REVA_REGS_H_
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files(the "Software"),
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
|
|
@ -15,7 +15,7 @@
|
|||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
|
|
@ -24,12 +24,12 @@
|
|||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stddef.h>
|
||||
|
|
@ -43,210 +43,215 @@
|
|||
#include "dma.h"
|
||||
|
||||
/* **** Functions **** */
|
||||
int MXC_SPI_Init(mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves,
|
||||
unsigned ssPolarity, unsigned int hz, unsigned drv_ssel)
|
||||
int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves,
|
||||
unsigned ssPolarity, unsigned int hz)
|
||||
{
|
||||
|
||||
if(numSlaves > MXC_SPI_SS_INSTANCES) {
|
||||
int spi_num;
|
||||
|
||||
spi_num = MXC_SPI_GET_IDX(spi);
|
||||
MXC_ASSERT(spi_num >= 0);
|
||||
|
||||
if (numSlaves > MXC_SPI_SS_INSTANCES) {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
// Check if frequency is too high
|
||||
if(hz > PeripheralClock) {
|
||||
if (hz > PeripheralClock) {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
// Configure GPIO for spi
|
||||
if(spi == MXC_SPI0) {
|
||||
if (spi == MXC_SPI0) {
|
||||
MXC_GCR->rst0 |= MXC_F_GCR_RST0_SPI0;
|
||||
while(MXC_GCR->rst0 & MXC_F_GCR_RST0_SPI0);
|
||||
while (MXC_GCR->rst0 & MXC_F_GCR_RST0_SPI0) {}
|
||||
MXC_GCR->pclk_dis0 &= ~(MXC_F_GCR_PCLK_DIS0_SPI0D);
|
||||
MXC_GPIO_Config(&gpio_cfg_spi0);
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
return E_NO_DEVICE;
|
||||
}
|
||||
|
||||
return MXC_SPI_RevA_Init((mxc_spi_reva_regs_t*) spi, masterMode, quadModeUsed, numSlaves, ssPolarity, hz, drv_ssel);
|
||||
|
||||
return MXC_SPI_RevA_Init((mxc_spi_reva_regs_t *)spi, masterMode, quadModeUsed, numSlaves,
|
||||
ssPolarity, hz);
|
||||
}
|
||||
|
||||
int MXC_SPI_Shutdown(mxc_spi_regs_t* spi)
|
||||
{
|
||||
if(spi != MXC_SPI0) {
|
||||
return E_NO_DEVICE;
|
||||
}
|
||||
int MXC_SPI_Shutdown(mxc_spi_regs_t *spi)
|
||||
{
|
||||
int spi_num;
|
||||
spi_num = MXC_SPI_GET_IDX(spi);
|
||||
MXC_ASSERT(spi_num >= 0);
|
||||
|
||||
MXC_SPI_RevA_Shutdown((mxc_spi_reva_regs_t*) spi);
|
||||
//
|
||||
MXC_GCR->pclk_dis0 |= (MXC_F_GCR_PCLK_DIS0_SPI0D);
|
||||
MXC_SPI_RevA_Shutdown((mxc_spi_reva_regs_t *)spi);
|
||||
|
||||
if (spi == MXC_SPI0) {
|
||||
MXC_GCR->pclk_dis0 |= (MXC_F_GCR_PCLK_DIS0_SPI0D);
|
||||
} else {
|
||||
return E_INVALID;
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_SPI_ReadyForSleep(mxc_spi_regs_t* spi)
|
||||
int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi)
|
||||
{
|
||||
return MXC_SPI_RevA_ReadyForSleep((mxc_spi_reva_regs_t*) spi);
|
||||
return MXC_SPI_RevA_ReadyForSleep((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi)
|
||||
int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi)
|
||||
{
|
||||
if(spi == MXC_SPI0) {
|
||||
if (spi == MXC_SPI0) {
|
||||
return PeripheralClock;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_SPI_SetFrequency(mxc_spi_regs_t* spi, unsigned int hz)
|
||||
int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz)
|
||||
{
|
||||
return MXC_SPI_RevA_SetFrequency((mxc_spi_reva_regs_t*) spi, hz);
|
||||
return MXC_SPI_RevA_SetFrequency((mxc_spi_reva_regs_t *)spi, hz);
|
||||
}
|
||||
|
||||
unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t* spi)
|
||||
unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t *spi)
|
||||
{
|
||||
return MXC_SPI_RevA_GetFrequency((mxc_spi_reva_regs_t*) spi);
|
||||
return MXC_SPI_RevA_GetFrequency((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
int MXC_SPI_SetDataSize(mxc_spi_regs_t* spi, int dataSize)
|
||||
int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize)
|
||||
{
|
||||
return MXC_SPI_RevA_SetDataSize((mxc_spi_reva_regs_t*) spi, dataSize);
|
||||
return MXC_SPI_RevA_SetDataSize((mxc_spi_reva_regs_t *)spi, dataSize);
|
||||
}
|
||||
|
||||
int MXC_SPI_GetDataSize(mxc_spi_regs_t* spi)
|
||||
int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi)
|
||||
{
|
||||
return MXC_SPI_RevA_GetDataSize((mxc_spi_reva_regs_t*) spi);
|
||||
return MXC_SPI_RevA_GetDataSize((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
int MXC_SPI_SetSlave(mxc_spi_regs_t* spi, int ssIdx)
|
||||
int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx)
|
||||
{
|
||||
return MXC_SPI_RevA_SetSlave((mxc_spi_reva_regs_t*) spi, ssIdx);
|
||||
return MXC_SPI_RevA_SetSlave((mxc_spi_reva_regs_t *)spi, ssIdx);
|
||||
}
|
||||
|
||||
int MXC_SPI_GetSlave(mxc_spi_regs_t* spi)
|
||||
int MXC_SPI_GetSlave(mxc_spi_regs_t *spi)
|
||||
{
|
||||
return MXC_SPI_RevA_GetSlave((mxc_spi_reva_regs_t*) spi);
|
||||
return MXC_SPI_RevA_GetSlave((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
int MXC_SPI_SetWidth(mxc_spi_regs_t* spi, mxc_spi_width_t spiWidth)
|
||||
int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth)
|
||||
{
|
||||
return MXC_SPI_RevA_SetWidth((mxc_spi_reva_regs_t*) spi, (mxc_spi_reva_width_t)spiWidth);
|
||||
return MXC_SPI_RevA_SetWidth((mxc_spi_reva_regs_t *)spi, spiWidth);
|
||||
}
|
||||
|
||||
mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t* spi)
|
||||
mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi)
|
||||
{
|
||||
return(mxc_spi_width_t) MXC_SPI_RevA_GetWidth((mxc_spi_reva_regs_t*) spi);
|
||||
return (mxc_spi_width_t)MXC_SPI_RevA_GetWidth((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
int MXC_SPI_SetMode (mxc_spi_regs_t* spi, mxc_spi_mode_t spiMode)
|
||||
int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode)
|
||||
{
|
||||
return MXC_SPI_RevA_SetMode ((mxc_spi_reva_regs_t*) spi, (mxc_spi_reva_mode_t)spiMode);
|
||||
return MXC_SPI_RevA_SetMode((mxc_spi_reva_regs_t *)spi, spiMode);
|
||||
}
|
||||
|
||||
mxc_spi_mode_t MXC_SPI_GetMode (mxc_spi_regs_t* spi)
|
||||
mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi)
|
||||
{
|
||||
return (mxc_spi_mode_t) MXC_SPI_RevA_GetMode((mxc_spi_reva_regs_t*) spi);
|
||||
return MXC_SPI_RevA_GetMode((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
int MXC_SPI_StartTransmission(mxc_spi_regs_t* spi)
|
||||
int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi)
|
||||
{
|
||||
return MXC_SPI_RevA_StartTransmission((mxc_spi_reva_regs_t*) spi);
|
||||
return MXC_SPI_RevA_StartTransmission((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
int MXC_SPI_GetActive(mxc_spi_regs_t* spi)
|
||||
int MXC_SPI_GetActive(mxc_spi_regs_t *spi)
|
||||
{
|
||||
return MXC_SPI_RevA_GetActive((mxc_spi_reva_regs_t*) spi);
|
||||
return MXC_SPI_RevA_GetActive((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
int MXC_SPI_AbortTransmission(mxc_spi_regs_t* spi)
|
||||
int MXC_SPI_AbortTransmission(mxc_spi_regs_t *spi)
|
||||
{
|
||||
return MXC_SPI_RevA_AbortTransmission((mxc_spi_reva_regs_t*) spi);
|
||||
return MXC_SPI_RevA_AbortTransmission((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t* spi, unsigned char* bytes,
|
||||
unsigned int len)
|
||||
unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len)
|
||||
{
|
||||
return MXC_SPI_RevA_ReadRXFIFO((mxc_spi_reva_regs_t*) spi, bytes, len);
|
||||
return MXC_SPI_RevA_ReadRXFIFO((mxc_spi_reva_regs_t *)spi, bytes, len);
|
||||
}
|
||||
|
||||
unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t* spi)
|
||||
unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t *spi)
|
||||
{
|
||||
return MXC_SPI_RevA_GetRXFIFOAvailable((mxc_spi_reva_regs_t*) spi);
|
||||
return MXC_SPI_RevA_GetRXFIFOAvailable((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t* spi, unsigned char* bytes,
|
||||
unsigned int len)
|
||||
unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len)
|
||||
{
|
||||
return MXC_SPI_RevA_WriteTXFIFO((mxc_spi_reva_regs_t*) spi, bytes, len);
|
||||
return MXC_SPI_RevA_WriteTXFIFO((mxc_spi_reva_regs_t *)spi, bytes, len);
|
||||
}
|
||||
|
||||
unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t* spi)
|
||||
unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t *spi)
|
||||
{
|
||||
return MXC_SPI_RevA_GetTXFIFOAvailable((mxc_spi_reva_regs_t*) spi);
|
||||
return MXC_SPI_RevA_GetTXFIFOAvailable((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t* spi)
|
||||
void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi)
|
||||
{
|
||||
MXC_SPI_RevA_ClearRXFIFO((mxc_spi_reva_regs_t*) spi);
|
||||
MXC_SPI_RevA_ClearRXFIFO((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t* spi)
|
||||
void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi)
|
||||
{
|
||||
MXC_SPI_RevA_ClearTXFIFO((mxc_spi_reva_regs_t*) spi);
|
||||
MXC_SPI_RevA_ClearTXFIFO((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
int MXC_SPI_SetRXThreshold(mxc_spi_regs_t* spi, unsigned int numBytes)
|
||||
int MXC_SPI_SetRXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes)
|
||||
{
|
||||
return MXC_SPI_RevA_SetRXThreshold((mxc_spi_reva_regs_t*) spi, numBytes);
|
||||
return MXC_SPI_RevA_SetRXThreshold((mxc_spi_reva_regs_t *)spi, numBytes);
|
||||
}
|
||||
|
||||
unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t* spi)
|
||||
unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi)
|
||||
{
|
||||
return MXC_SPI_RevA_GetRXThreshold((mxc_spi_reva_regs_t*) spi);
|
||||
return MXC_SPI_RevA_GetRXThreshold((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
int MXC_SPI_SetTXThreshold(mxc_spi_regs_t* spi, unsigned int numBytes)
|
||||
int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes)
|
||||
{
|
||||
return MXC_SPI_RevA_SetTXThreshold((mxc_spi_reva_regs_t*) spi, numBytes);
|
||||
return MXC_SPI_RevA_SetTXThreshold((mxc_spi_reva_regs_t *)spi, numBytes);
|
||||
}
|
||||
|
||||
unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t* spi)
|
||||
unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi)
|
||||
{
|
||||
return MXC_SPI_RevA_GetTXThreshold((mxc_spi_reva_regs_t*) spi);
|
||||
return MXC_SPI_RevA_GetTXThreshold((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t* spi)
|
||||
unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t *spi)
|
||||
{
|
||||
return MXC_SPI_RevA_GetFlags((mxc_spi_reva_regs_t*) spi);
|
||||
return MXC_SPI_RevA_GetFlags((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
void MXC_SPI_ClearFlags(mxc_spi_regs_t* spi)
|
||||
void MXC_SPI_ClearFlags(mxc_spi_regs_t *spi)
|
||||
{
|
||||
MXC_SPI_RevA_ClearFlags((mxc_spi_reva_regs_t*) spi);
|
||||
MXC_SPI_RevA_ClearFlags((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
void MXC_SPI_EnableInt(mxc_spi_regs_t* spi, unsigned int mask)
|
||||
void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int mask)
|
||||
{
|
||||
MXC_SPI_RevA_EnableInt((mxc_spi_reva_regs_t*) spi, mask);
|
||||
MXC_SPI_RevA_EnableInt((mxc_spi_reva_regs_t *)spi, mask);
|
||||
}
|
||||
|
||||
void MXC_SPI_DisableInt(mxc_spi_regs_t* spi, unsigned int mask)
|
||||
void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int mask)
|
||||
{
|
||||
MXC_SPI_RevA_DisableInt((mxc_spi_reva_regs_t*) spi, mask);
|
||||
MXC_SPI_RevA_DisableInt((mxc_spi_reva_regs_t *)spi, mask);
|
||||
}
|
||||
|
||||
int MXC_SPI_MasterTransaction(mxc_spi_req_t* req)
|
||||
int MXC_SPI_MasterTransaction(mxc_spi_req_t *req)
|
||||
{
|
||||
return MXC_SPI_RevA_MasterTransaction((mxc_spi_reva_req_t*) req);
|
||||
return MXC_SPI_RevA_MasterTransaction((mxc_spi_reva_req_t *)req);
|
||||
}
|
||||
|
||||
int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t* req)
|
||||
int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req)
|
||||
{
|
||||
return MXC_SPI_RevA_MasterTransactionAsync((mxc_spi_reva_req_t*) req);
|
||||
return MXC_SPI_RevA_MasterTransactionAsync((mxc_spi_reva_req_t *)req);
|
||||
}
|
||||
|
||||
int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t* req)
|
||||
int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req)
|
||||
{
|
||||
int reqselTx = -1;
|
||||
int reqselRx = -1;
|
||||
|
|
@ -255,9 +260,9 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t* req)
|
|||
|
||||
spi_num = MXC_SPI_GET_IDX(req->spi);
|
||||
MXC_ASSERT(spi_num >= 0);
|
||||
|
||||
if(req->txData != NULL) {
|
||||
switch(spi_num) {
|
||||
|
||||
if (req->txData != NULL) {
|
||||
switch (spi_num) {
|
||||
case 0:
|
||||
reqselTx = MXC_DMA_REQUEST_SPI0TX;
|
||||
break;
|
||||
|
|
@ -267,12 +272,12 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t* req)
|
|||
break;
|
||||
|
||||
default:
|
||||
return E_BAD_PARAM;
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
}
|
||||
|
||||
if(req->rxData != NULL) {
|
||||
switch(spi_num) {
|
||||
if (req->rxData != NULL) {
|
||||
switch (spi_num) {
|
||||
case 0:
|
||||
reqselRx = MXC_DMA_REQUEST_SPI0RX;
|
||||
break;
|
||||
|
|
@ -286,20 +291,21 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t* req)
|
|||
}
|
||||
}
|
||||
|
||||
return MXC_SPI_RevA_MasterTransactionDMA((mxc_spi_reva_req_t*) req, reqselTx, reqselRx, MXC_DMA);
|
||||
return MXC_SPI_RevA_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx,
|
||||
MXC_DMA);
|
||||
}
|
||||
|
||||
int MXC_SPI_SlaveTransaction(mxc_spi_req_t* req)
|
||||
int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req)
|
||||
{
|
||||
return MXC_SPI_RevA_SlaveTransaction((mxc_spi_reva_req_t*) req);
|
||||
return MXC_SPI_RevA_SlaveTransaction((mxc_spi_reva_req_t *)req);
|
||||
}
|
||||
|
||||
int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t* req)
|
||||
int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req)
|
||||
{
|
||||
return MXC_SPI_RevA_SlaveTransactionAsync((mxc_spi_reva_req_t*) req);
|
||||
return MXC_SPI_RevA_SlaveTransactionAsync((mxc_spi_reva_req_t *)req);
|
||||
}
|
||||
|
||||
int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t* req)
|
||||
int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req)
|
||||
{
|
||||
int reqselTx = -1;
|
||||
int reqselRx = -1;
|
||||
|
|
@ -308,9 +314,9 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t* req)
|
|||
|
||||
spi_num = MXC_SPI_GET_IDX(req->spi);
|
||||
MXC_ASSERT(spi_num >= 0);
|
||||
|
||||
if(req->txData != NULL) {
|
||||
switch(spi_num) {
|
||||
|
||||
if (req->txData != NULL) {
|
||||
switch (spi_num) {
|
||||
case 0:
|
||||
reqselTx = MXC_DMA_REQUEST_SPI0TX;
|
||||
break;
|
||||
|
|
@ -324,8 +330,8 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t* req)
|
|||
}
|
||||
}
|
||||
|
||||
if(req->rxData != NULL) {
|
||||
switch(spi_num) {
|
||||
if (req->rxData != NULL) {
|
||||
switch (spi_num) {
|
||||
case 0:
|
||||
reqselRx = MXC_DMA_REQUEST_SPI0RX;
|
||||
break;
|
||||
|
|
@ -333,26 +339,26 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t* req)
|
|||
case 1:
|
||||
reqselRx = MXC_DMA_REQUEST_SPI1RX;
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
}
|
||||
|
||||
return MXC_SPI_RevA_SlaveTransactionDMA((mxc_spi_reva_req_t*) req, reqselTx, reqselRx, MXC_DMA);
|
||||
return MXC_SPI_RevA_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, MXC_DMA);
|
||||
}
|
||||
|
||||
int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t* spi, unsigned int defaultTXData)
|
||||
int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData)
|
||||
{
|
||||
return MXC_SPI_RevA_SetDefaultTXData((mxc_spi_reva_regs_t*) spi, defaultTXData);
|
||||
return MXC_SPI_RevA_SetDefaultTXData((mxc_spi_reva_regs_t *)spi, defaultTXData);
|
||||
}
|
||||
|
||||
void MXC_SPI_AbortAsync(mxc_spi_regs_t* spi)
|
||||
void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi)
|
||||
{
|
||||
MXC_SPI_RevA_AbortAsync((mxc_spi_reva_regs_t*) spi);
|
||||
MXC_SPI_RevA_AbortAsync((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
void MXC_SPI_AsyncHandler(mxc_spi_regs_t* spi)
|
||||
void MXC_SPI_AsyncHandler(mxc_spi_regs_t *spi)
|
||||
{
|
||||
MXC_SPI_RevA_AsyncHandler((mxc_spi_reva_regs_t*) spi);
|
||||
MXC_SPI_RevA_AsyncHandler((mxc_spi_reva_regs_t *)spi);
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,5 +1,5 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,7 +29,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_SPI_SPI_REVA_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_SPI_SPI_REVA_H_
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stddef.h>
|
||||
|
|
@ -41,9 +44,13 @@
|
|||
#include "mxc_delay.h"
|
||||
#include "spi_regs.h"
|
||||
#include "spi_reva_regs.h"
|
||||
#include "mxc_spi.h"
|
||||
#include "spi.h"
|
||||
#include "dma.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
SPI_REVA_WIDTH_3WIRE,
|
||||
SPI_REVA_WIDTH_STANDARD,
|
||||
|
|
@ -52,7 +59,7 @@ typedef enum {
|
|||
} mxc_spi_reva_width_t;
|
||||
|
||||
typedef enum {
|
||||
SPI_REVA_MODE_0,
|
||||
SPI_REVA_MODE_0,
|
||||
SPI_REVA_MODE_1,
|
||||
SPI_REVA_MODE_2,
|
||||
SPI_REVA_MODE_3,
|
||||
|
|
@ -61,58 +68,68 @@ typedef enum {
|
|||
typedef struct _mxc_spi_reva_req_t mxc_spi_reva_req_t;
|
||||
|
||||
struct _mxc_spi_reva_req_t {
|
||||
mxc_spi_reva_regs_t* spi;
|
||||
int ssIdx;
|
||||
int ssDeassert;
|
||||
uint8_t *txData;
|
||||
uint8_t *rxData;
|
||||
uint32_t txLen;
|
||||
uint32_t rxLen;
|
||||
uint32_t txCnt;
|
||||
uint32_t rxCnt;
|
||||
spi_complete_cb_t completeCB;
|
||||
mxc_spi_reva_regs_t *spi;
|
||||
int ssIdx;
|
||||
int ssDeassert;
|
||||
uint8_t *txData;
|
||||
uint8_t *rxData;
|
||||
uint32_t txLen;
|
||||
uint32_t rxLen;
|
||||
uint32_t txCnt;
|
||||
uint32_t rxCnt;
|
||||
spi_complete_cb_t completeCB;
|
||||
};
|
||||
|
||||
int MXC_SPI_RevA_Init (mxc_spi_reva_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves,
|
||||
unsigned ssPolarity, unsigned int hz, unsigned drv_ssel);
|
||||
int MXC_SPI_RevA_Shutdown (mxc_spi_reva_regs_t* spi);
|
||||
int MXC_SPI_RevA_ReadyForSleep (mxc_spi_reva_regs_t* spi);
|
||||
int MXC_SPI_RevA_SetFrequency (mxc_spi_reva_regs_t* spi, unsigned int hz);
|
||||
unsigned int MXC_SPI_RevA_GetFrequency (mxc_spi_reva_regs_t* spi);
|
||||
int MXC_SPI_RevA_SetDataSize (mxc_spi_reva_regs_t* spi, int dataSize);
|
||||
int MXC_SPI_RevA_GetDataSize (mxc_spi_reva_regs_t* spi);
|
||||
int MXC_SPI_RevA_SetSlave (mxc_spi_reva_regs_t* spi, int ssIdx);
|
||||
int MXC_SPI_RevA_GetSlave (mxc_spi_reva_regs_t* spi);
|
||||
int MXC_SPI_RevA_SetWidth (mxc_spi_reva_regs_t* spi, mxc_spi_reva_width_t spiWidth);
|
||||
mxc_spi_reva_width_t MXC_SPI_RevA_GetWidth (mxc_spi_reva_regs_t* spi);
|
||||
int MXC_SPI_RevA_SetMode (mxc_spi_reva_regs_t* spi, mxc_spi_reva_mode_t spiMode);
|
||||
mxc_spi_reva_mode_t MXC_SPI_RevA_GetMode (mxc_spi_reva_regs_t* spi);
|
||||
int MXC_SPI_RevA_StartTransmission (mxc_spi_reva_regs_t* spi);
|
||||
int MXC_SPI_RevA_GetActive (mxc_spi_reva_regs_t* spi);
|
||||
int MXC_SPI_RevA_AbortTransmission (mxc_spi_reva_regs_t* spi);
|
||||
unsigned int MXC_SPI_RevA_ReadRXFIFO (mxc_spi_reva_regs_t* spi, unsigned char* bytes,
|
||||
int MXC_SPI_RevA_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves,
|
||||
unsigned ssPolarity, unsigned int hz);
|
||||
int MXC_SPI_RevA_Shutdown(mxc_spi_reva_regs_t *spi);
|
||||
int MXC_SPI_RevA_ReadyForSleep(mxc_spi_reva_regs_t *spi);
|
||||
int MXC_SPI_RevA_SetFrequency(mxc_spi_reva_regs_t *spi, unsigned int hz);
|
||||
unsigned int MXC_SPI_RevA_GetFrequency(mxc_spi_reva_regs_t *spi);
|
||||
int MXC_SPI_RevA_SetDataSize(mxc_spi_reva_regs_t *spi, int dataSize);
|
||||
int MXC_SPI_RevA_GetDataSize(mxc_spi_reva_regs_t *spi);
|
||||
int MXC_SPI_RevA_SetMTMode(mxc_spi_reva_regs_t *spi, int mtMode);
|
||||
int MXC_SPI_RevA_GetMTMode(mxc_spi_reva_regs_t *spi);
|
||||
int MXC_SPI_RevA_SetSlave(mxc_spi_reva_regs_t *spi, int ssIdx);
|
||||
int MXC_SPI_RevA_GetSlave(mxc_spi_reva_regs_t *spi);
|
||||
int MXC_SPI_RevA_SetWidth(mxc_spi_reva_regs_t *spi, mxc_spi_reva_width_t spiWidth);
|
||||
mxc_spi_reva_width_t MXC_SPI_RevA_GetWidth(mxc_spi_reva_regs_t *spi);
|
||||
int MXC_SPI_RevA_SetMode(mxc_spi_reva_regs_t *spi, mxc_spi_reva_mode_t spiMode);
|
||||
mxc_spi_reva_mode_t MXC_SPI_RevA_GetMode(mxc_spi_reva_regs_t *spi);
|
||||
int MXC_SPI_RevA_StartTransmission(mxc_spi_reva_regs_t *spi);
|
||||
int MXC_SPI_RevA_GetActive(mxc_spi_reva_regs_t *spi);
|
||||
int MXC_SPI_RevA_AbortTransmission(mxc_spi_reva_regs_t *spi);
|
||||
unsigned int MXC_SPI_RevA_ReadRXFIFO(mxc_spi_reva_regs_t *spi, unsigned char *bytes,
|
||||
unsigned int len);
|
||||
unsigned int MXC_SPI_RevA_WriteTXFIFO(mxc_spi_reva_regs_t *spi, unsigned char *bytes,
|
||||
unsigned int len);
|
||||
unsigned int MXC_SPI_RevA_WriteTXFIFO (mxc_spi_reva_regs_t* spi, unsigned char* bytes,
|
||||
unsigned int len);
|
||||
unsigned int MXC_SPI_RevA_GetTXFIFOAvailable (mxc_spi_reva_regs_t* spi);
|
||||
unsigned int MXC_SPI_RevA_GetRXFIFOAvailable (mxc_spi_reva_regs_t* spi);
|
||||
void MXC_SPI_RevA_ClearRXFIFO (mxc_spi_reva_regs_t* spi);
|
||||
void MXC_SPI_RevA_ClearTXFIFO (mxc_spi_reva_regs_t* spi);
|
||||
int MXC_SPI_RevA_SetRXThreshold (mxc_spi_reva_regs_t* spi, unsigned int numBytes);
|
||||
unsigned int MXC_SPI_RevA_GetRXThreshold (mxc_spi_reva_regs_t* spi);
|
||||
int MXC_SPI_RevA_SetTXThreshold (mxc_spi_reva_regs_t* spi, unsigned int numBytes);
|
||||
unsigned int MXC_SPI_RevA_GetTXThreshold (mxc_spi_reva_regs_t* spi);
|
||||
unsigned int MXC_SPI_RevA_GetFlags (mxc_spi_reva_regs_t* spi);
|
||||
void MXC_SPI_RevA_ClearFlags (mxc_spi_reva_regs_t* spi);
|
||||
void MXC_SPI_RevA_EnableInt (mxc_spi_reva_regs_t* spi, unsigned int mask);
|
||||
void MXC_SPI_RevA_DisableInt (mxc_spi_reva_regs_t* spi, unsigned int mask);
|
||||
int MXC_SPI_RevA_MasterTransaction (mxc_spi_reva_req_t* req);
|
||||
int MXC_SPI_RevA_MasterTransactionAsync (mxc_spi_reva_req_t* req);
|
||||
int MXC_SPI_RevA_MasterTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma);
|
||||
int MXC_SPI_RevA_SlaveTransaction (mxc_spi_reva_req_t* req);
|
||||
int MXC_SPI_RevA_SlaveTransactionAsync (mxc_spi_reva_req_t* req);
|
||||
int MXC_SPI_RevA_SlaveTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma);
|
||||
void MXC_SPI_RevA_DMACallback (int ch, int error);
|
||||
int MXC_SPI_RevA_SetDefaultTXData (mxc_spi_reva_regs_t* spi, unsigned int defaultTXData);
|
||||
void MXC_SPI_RevA_AbortAsync (mxc_spi_reva_regs_t* spi);
|
||||
void MXC_SPI_RevA_AsyncHandler (mxc_spi_reva_regs_t* spi);
|
||||
unsigned int MXC_SPI_RevA_GetTXFIFOAvailable(mxc_spi_reva_regs_t *spi);
|
||||
unsigned int MXC_SPI_RevA_GetRXFIFOAvailable(mxc_spi_reva_regs_t *spi);
|
||||
void MXC_SPI_RevA_ClearRXFIFO(mxc_spi_reva_regs_t *spi);
|
||||
void MXC_SPI_RevA_ClearTXFIFO(mxc_spi_reva_regs_t *spi);
|
||||
int MXC_SPI_RevA_SetRXThreshold(mxc_spi_reva_regs_t *spi, unsigned int numBytes);
|
||||
unsigned int MXC_SPI_RevA_GetRXThreshold(mxc_spi_reva_regs_t *spi);
|
||||
int MXC_SPI_RevA_SetTXThreshold(mxc_spi_reva_regs_t *spi, unsigned int numBytes);
|
||||
unsigned int MXC_SPI_RevA_GetTXThreshold(mxc_spi_reva_regs_t *spi);
|
||||
unsigned int MXC_SPI_RevA_GetFlags(mxc_spi_reva_regs_t *spi);
|
||||
void MXC_SPI_RevA_ClearFlags(mxc_spi_reva_regs_t *spi);
|
||||
void MXC_SPI_RevA_EnableInt(mxc_spi_reva_regs_t *spi, unsigned int mask);
|
||||
void MXC_SPI_RevA_DisableInt(mxc_spi_reva_regs_t *spi, unsigned int mask);
|
||||
int MXC_SPI_RevA_MasterTransaction(mxc_spi_reva_req_t *req);
|
||||
int MXC_SPI_RevA_MasterTransactionAsync(mxc_spi_reva_req_t *req);
|
||||
int MXC_SPI_RevA_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int reqselRx,
|
||||
mxc_dma_regs_t *dma);
|
||||
int MXC_SPI_RevA_SlaveTransaction(mxc_spi_reva_req_t *req);
|
||||
int MXC_SPI_RevA_SlaveTransactionAsync(mxc_spi_reva_req_t *req);
|
||||
int MXC_SPI_RevA_SlaveTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int reqselRx,
|
||||
mxc_dma_regs_t *dma);
|
||||
void MXC_SPI_RevA_DMACallback(int ch, int error);
|
||||
int MXC_SPI_RevA_SetDefaultTXData(mxc_spi_reva_regs_t *spi, unsigned int defaultTXData);
|
||||
void MXC_SPI_RevA_AbortAsync(mxc_spi_reva_regs_t *spi);
|
||||
void MXC_SPI_RevA_AsyncHandler(mxc_spi_reva_regs_t *spi);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_SPI_SPI_REVA_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,8 +34,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _SPI_REVA_REGS_H_
|
||||
#define _SPI_REVA_REGS_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Inter-Integrated Sound (I2S) driver implementation.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,8 +34,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
|
@ -51,61 +50,59 @@
|
|||
#include "spimss_regs.h"
|
||||
|
||||
#define I2S_CHANNELS 2
|
||||
#define I2S_WIDTH 16
|
||||
#define I2S_WIDTH 16
|
||||
|
||||
int dma_channel = -1;
|
||||
|
||||
int MXC_I2S_Init(const mxc_i2s_config_t *config, void(*dma_ctz_cb)(int, int))
|
||||
int MXC_I2S_Init(const mxc_i2s_config_t *config, void (*dma_ctz_cb)(int, int))
|
||||
{
|
||||
if(config->map == I2S_MAP_A) {
|
||||
MXC_GPIO_Config(&gpio_cfg_spi1a); // SPIMSS: I2S and SPI share pins
|
||||
}
|
||||
else if(config->map == I2S_MAP_B) {
|
||||
if (config->map == I2S_MAP_A) {
|
||||
MXC_GPIO_Config(&gpio_cfg_spi1a); // SPIMSS: I2S and SPI share pins
|
||||
} else if (config->map == I2S_MAP_B) {
|
||||
MXC_GPIO_Config(&gpio_cfg_spi1b);
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI1); // SPI1 clock used for SPIMSS
|
||||
|
||||
return MXC_I2S_RevA_Init((mxc_spimss_reva_regs_t*) MXC_SPIMSS, config, dma_ctz_cb);
|
||||
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI1); // SPI1 clock used for SPIMSS
|
||||
|
||||
return MXC_I2S_RevA_Init((mxc_spimss_reva_regs_t *)MXC_SPIMSS, config, dma_ctz_cb);
|
||||
}
|
||||
|
||||
int MXC_I2S_Shutdown(void)
|
||||
{
|
||||
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI1); // SPI1 used for SPIMSS
|
||||
return MXC_I2S_RevA_Shutdown((mxc_spimss_reva_regs_t*) MXC_SPIMSS);
|
||||
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI1); // SPI1 used for SPIMSS
|
||||
return MXC_I2S_RevA_Shutdown((mxc_spimss_reva_regs_t *)MXC_SPIMSS);
|
||||
}
|
||||
|
||||
int MXC_I2S_Mute(void)
|
||||
{
|
||||
return MXC_I2S_RevA_Mute((mxc_spimss_reva_regs_t*) MXC_SPIMSS);
|
||||
return MXC_I2S_RevA_Mute((mxc_spimss_reva_regs_t *)MXC_SPIMSS);
|
||||
}
|
||||
|
||||
int MXC_I2S_Unmute(void)
|
||||
{
|
||||
return MXC_I2S_RevA_Unmute((mxc_spimss_reva_regs_t*) MXC_SPIMSS);
|
||||
return MXC_I2S_RevA_Unmute((mxc_spimss_reva_regs_t *)MXC_SPIMSS);
|
||||
}
|
||||
|
||||
int MXC_I2S_Pause(void)
|
||||
{
|
||||
return MXC_I2S_RevA_Pause((mxc_spimss_reva_regs_t*) MXC_SPIMSS);
|
||||
return MXC_I2S_RevA_Pause((mxc_spimss_reva_regs_t *)MXC_SPIMSS);
|
||||
}
|
||||
|
||||
int MXC_I2S_Unpause(void)
|
||||
{
|
||||
return MXC_I2S_RevA_Unpause((mxc_spimss_reva_regs_t*) MXC_SPIMSS);
|
||||
return MXC_I2S_RevA_Unpause((mxc_spimss_reva_regs_t *)MXC_SPIMSS);
|
||||
}
|
||||
|
||||
int MXC_I2S_Stop(void)
|
||||
{
|
||||
return MXC_I2S_RevA_Stop((mxc_spimss_reva_regs_t*) MXC_SPIMSS);
|
||||
return MXC_I2S_RevA_Stop((mxc_spimss_reva_regs_t *)MXC_SPIMSS);
|
||||
}
|
||||
|
||||
int MXC_I2S_Start(void)
|
||||
{
|
||||
return MXC_I2S_RevA_Start((mxc_spimss_reva_regs_t*) MXC_SPIMSS);
|
||||
return MXC_I2S_RevA_Start((mxc_spimss_reva_regs_t *)MXC_SPIMSS);
|
||||
}
|
||||
|
||||
int MXC_I2S_DMA_ClearFlags(void)
|
||||
|
|
|
|||
|
|
@ -3,11 +3,11 @@
|
|||
* @brief Inter-Integrated Sound(I2S) driver implementation.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files(the "Software"),
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
|
|
@ -34,8 +34,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
|
@ -51,11 +50,13 @@
|
|||
#include "spimss_reva.h"
|
||||
|
||||
#define I2S_CHANNELS 2
|
||||
#define I2S_WIDTH 16
|
||||
#define I2S_WIDTH 16
|
||||
|
||||
static int dma_channel = -1;
|
||||
static int tx_dma_channel = -1;
|
||||
static int rx_dma_channel = -1;
|
||||
|
||||
int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *config, void(*dma_ctz_cb)(int, int))
|
||||
int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *config,
|
||||
void (*dma_ctz_cb)(int, int))
|
||||
{
|
||||
unsigned int baud;
|
||||
uint16_t clkdiv;
|
||||
|
|
@ -67,123 +68,135 @@ int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *co
|
|||
|
||||
/* Setup SPI_MSS as master, mode 0, 16 bit transfers as I2S Requires */
|
||||
spimss->ctrl = MXC_F_SPIMSS_REVA_CTRL_MMEN;
|
||||
spimss->mode = MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS16 | MXC_F_SPIMSS_REVA_MODE_SS_IO;
|
||||
spimss->dma = MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES8;
|
||||
spimss->mode = MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS16 | MXC_F_SPIMSS_REVA_MODE_SS_IO;
|
||||
|
||||
spimss->dma = (1 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) | /* TX DMA request FIFO level */
|
||||
MXC_F_SPIMSS_DMA_TX_FIFO_CLR | /* Clear TX FIFO */
|
||||
(1 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) | /* RX DMA request FIFO level */
|
||||
MXC_F_SPIMSS_DMA_RX_FIFO_CLR; /* Clear RX FIFO */
|
||||
|
||||
/* Setup I2S register from i2s_cfg_t */
|
||||
spimss->i2s_ctrl = config->justify << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS |
|
||||
config->audio_mode << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS;
|
||||
spimss->i2s_ctrl = config->justify << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS |
|
||||
config->audio_mode << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS;
|
||||
|
||||
/* Determine divisor for baud rate generator */
|
||||
baud = config->sample_rate * I2S_CHANNELS * I2S_WIDTH;
|
||||
|
||||
if((PeripheralClock / 4) < baud) {
|
||||
if ((PeripheralClock / 4) < baud) {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
clkdiv = PeripheralClock / (2 * baud); // Peripheral clock in system_max*****.h
|
||||
clkdiv = PeripheralClock / (2 * baud); // Peripheral clock in system_max*****.h
|
||||
|
||||
if(clkdiv < 2) {
|
||||
if (clkdiv < 2) {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
spimss->brg = clkdiv;
|
||||
|
||||
/* Prepare SPIMSS DMA register for DMA setup */
|
||||
if(dma_ctz_cb == NULL) {
|
||||
if (dma_ctz_cb == NULL) {
|
||||
ctz_en = 0;
|
||||
} else {
|
||||
ctz_en = 1;
|
||||
}
|
||||
|
||||
/* Initialize DMA */
|
||||
if(config->audio_direction % 2) {
|
||||
if (config->audio_direction % 2) {
|
||||
spimss->dma |= MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN | MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR;
|
||||
if((err = MXC_DMA_Init()) != E_NO_ERROR) {
|
||||
if(err != E_BAD_STATE) {
|
||||
if ((err = MXC_DMA_Init()) != E_NO_ERROR) {
|
||||
if (err != E_BAD_STATE) {
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
if((err = MXC_DMA_AcquireChannel()) < 0) {
|
||||
if ((err = MXC_DMA_AcquireChannel()) < 0) {
|
||||
return err;
|
||||
}
|
||||
|
||||
dma_channel = err;
|
||||
tx_dma_channel = err;
|
||||
|
||||
dma_config.ch = dma_channel;
|
||||
dma_config.ch = tx_dma_channel;
|
||||
|
||||
dma_config.srcwd = MXC_DMA_WIDTH_HALFWORD;
|
||||
dma_config.dstwd = MXC_DMA_WIDTH_WORD;
|
||||
#if TARGET_NUM == 32650
|
||||
dma_config.srcwd = MXC_DMA_WIDTH_WORD;
|
||||
dma_config.dstwd = MXC_DMA_WIDTH_HALFWORD;
|
||||
#if TARGET_NUM == 32650
|
||||
dma_config.reqsel = MXC_DMA_REQUEST_SPIMSSTX;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#if TARGET_NUM == 32660
|
||||
dma_config.reqsel = MXC_DMA_REQUEST_SPI1TX;
|
||||
#endif
|
||||
|
||||
dma_config.srcinc_en = 1;
|
||||
dma_config.dstinc_en = 0;
|
||||
|
||||
srcdst.ch = dma_channel;
|
||||
srcdst.ch = tx_dma_channel;
|
||||
srcdst.source = config->src_addr;
|
||||
srcdst.dest = NULL;
|
||||
srcdst.len = config->length;
|
||||
|
||||
MXC_DMA_ConfigChannel(dma_config, srcdst);
|
||||
MXC_DMA_SetChannelInterruptEn(dma_channel, 0, 1);
|
||||
MXC_DMA_SetChannelInterruptEn(tx_dma_channel, 0, 1);
|
||||
|
||||
MXC_DMA->ch[dma_channel].cfg &= ~MXC_F_DMA_CFG_BRST;
|
||||
MXC_DMA->ch[dma_channel].cfg |= (0x1f << MXC_F_DMA_CFG_BRST_POS);
|
||||
MXC_DMA->ch[tx_dma_channel].cfg &= ~MXC_F_DMA_CFG_BRST;
|
||||
MXC_DMA->ch[tx_dma_channel].cfg |= (3 << MXC_F_DMA_CFG_BRST_POS);
|
||||
|
||||
if(ctz_en) {
|
||||
MXC_DMA_SetCallback(dma_channel, dma_ctz_cb);
|
||||
MXC_DMA_EnableInt(dma_channel);
|
||||
if (ctz_en) {
|
||||
MXC_DMA_SetCallback(tx_dma_channel, dma_ctz_cb);
|
||||
MXC_DMA_EnableInt(tx_dma_channel);
|
||||
}
|
||||
}
|
||||
if(config->audio_direction / 2) {
|
||||
spimss->dma = MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN | MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR;
|
||||
if((err = MXC_DMA_Init()) != E_NO_ERROR) {
|
||||
if(err != E_BAD_STATE) { //DMA already initialized
|
||||
if (config->audio_direction / 2) {
|
||||
spimss->dma |= MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN | MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR;
|
||||
if ((err = MXC_DMA_Init()) != E_NO_ERROR) {
|
||||
if (err != E_BAD_STATE) { //DMA already initialized
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
if((err = MXC_DMA_AcquireChannel()) < 0) {
|
||||
if ((err = MXC_DMA_AcquireChannel()) < 0) {
|
||||
return err;
|
||||
}
|
||||
|
||||
dma_channel = err;
|
||||
rx_dma_channel = err;
|
||||
|
||||
dma_config.ch = dma_channel;
|
||||
|
||||
dma_config.srcwd = MXC_DMA_WIDTH_WORD;
|
||||
dma_config.dstwd = MXC_DMA_WIDTH_HALFWORD;
|
||||
#if TARGET_NUM == 32650
|
||||
dma_config.ch = rx_dma_channel;
|
||||
|
||||
dma_config.srcwd = MXC_DMA_WIDTH_HALFWORD;
|
||||
dma_config.dstwd = MXC_DMA_WIDTH_WORD;
|
||||
#if TARGET_NUM == 32650
|
||||
dma_config.reqsel = MXC_DMA_REQUEST_SPIMSSRX;
|
||||
#endif
|
||||
#endif
|
||||
#if TARGET_NUM == 32660
|
||||
dma_config.reqsel = MXC_DMA_REQUEST_SPI1RX;
|
||||
#endif
|
||||
|
||||
dma_config.srcinc_en = 0;
|
||||
dma_config.dstinc_en = 1;
|
||||
|
||||
srcdst.ch = dma_channel;
|
||||
srcdst.ch = rx_dma_channel;
|
||||
srcdst.source = NULL;
|
||||
srcdst.dest = config->dst_addr;
|
||||
srcdst.len = config->length;
|
||||
|
||||
MXC_DMA_ConfigChannel(dma_config, srcdst);
|
||||
MXC_DMA_SetChannelInterruptEn(dma_channel, 0, 1);
|
||||
MXC_DMA_SetChannelInterruptEn(rx_dma_channel, 0, 1);
|
||||
|
||||
MXC_DMA->ch[dma_channel].cfg &= ~MXC_F_DMA_CFG_BRST;
|
||||
MXC_DMA->ch[dma_channel].cfg |= (0x1f << MXC_F_DMA_CFG_BRST_POS);
|
||||
MXC_DMA->ch[rx_dma_channel].cfg &= ~MXC_F_DMA_CFG_BRST;
|
||||
MXC_DMA->ch[rx_dma_channel].cfg |= (3 << MXC_F_DMA_CFG_BRST_POS);
|
||||
|
||||
if(ctz_en) {
|
||||
MXC_DMA_SetCallback(dma_channel, dma_ctz_cb);
|
||||
MXC_DMA_EnableInt(dma_channel);
|
||||
if (ctz_en) {
|
||||
MXC_DMA_SetCallback(rx_dma_channel, dma_ctz_cb);
|
||||
MXC_DMA_EnableInt(rx_dma_channel);
|
||||
}
|
||||
}
|
||||
|
||||
MXC_I2S_DMA_SetAddrCnt(config->src_addr, config->dst_addr, config->length);
|
||||
if(config->dma_reload_en) {
|
||||
if (config->dma_reload_en) {
|
||||
MXC_I2S_DMA_SetReload(config->src_addr, config->dst_addr, config->length);
|
||||
}
|
||||
|
||||
if(config->start_immediately) {
|
||||
if (config->start_immediately) {
|
||||
return MXC_I2S_Start();
|
||||
}
|
||||
return E_NO_ERROR;
|
||||
|
|
@ -191,12 +204,28 @@ int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *co
|
|||
|
||||
int MXC_I2S_RevA_Shutdown(mxc_spimss_reva_regs_t *spimss)
|
||||
{
|
||||
int retTx = E_NO_ERROR;
|
||||
int retRx = E_NO_ERROR;
|
||||
|
||||
spimss->ctrl = 0;
|
||||
spimss->i2s_ctrl = 0;
|
||||
spimss->brg = 0;
|
||||
spimss->mode = 0;
|
||||
spimss->dma = 0;
|
||||
return MXC_DMA_ReleaseChannel(dma_channel);
|
||||
|
||||
if (tx_dma_channel != -1) {
|
||||
retTx = MXC_DMA_ReleaseChannel(tx_dma_channel);
|
||||
}
|
||||
|
||||
if (rx_dma_channel != -1) {
|
||||
retRx = MXC_DMA_ReleaseChannel(rx_dma_channel);
|
||||
}
|
||||
|
||||
if (retTx != E_NO_ERROR) {
|
||||
return retTx;
|
||||
} else {
|
||||
return retRx;
|
||||
}
|
||||
}
|
||||
|
||||
int MXC_I2S_RevA_Mute(mxc_spimss_reva_regs_t *spimss)
|
||||
|
|
@ -225,40 +254,125 @@ int MXC_I2S_RevA_Unpause(mxc_spimss_reva_regs_t *spimss)
|
|||
|
||||
int MXC_I2S_RevA_Stop(mxc_spimss_reva_regs_t *spimss)
|
||||
{
|
||||
int retTx = E_NO_ERROR;
|
||||
int retRx = E_NO_ERROR;
|
||||
|
||||
spimss->ctrl &= ~MXC_F_SPIMSS_REVA_CTRL_ENABLE;
|
||||
spimss->i2s_ctrl &= ~MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN;
|
||||
return MXC_DMA_Stop(dma_channel);
|
||||
|
||||
if (tx_dma_channel != -1) {
|
||||
retTx = MXC_DMA_Stop(tx_dma_channel);
|
||||
}
|
||||
if (rx_dma_channel != -1) {
|
||||
retRx = MXC_DMA_Stop(rx_dma_channel);
|
||||
}
|
||||
|
||||
if (retTx != E_NO_ERROR) {
|
||||
return retTx;
|
||||
} else {
|
||||
return retRx;
|
||||
}
|
||||
}
|
||||
|
||||
int MXC_I2S_RevA_Start(mxc_spimss_reva_regs_t *spimss)
|
||||
{
|
||||
int retTx = E_NO_ERROR;
|
||||
int retRx = E_NO_ERROR;
|
||||
|
||||
spimss->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE;
|
||||
spimss->i2s_ctrl |= MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN;
|
||||
return MXC_DMA_Start(dma_channel);
|
||||
|
||||
if (tx_dma_channel != -1) {
|
||||
retTx = MXC_DMA_Start(tx_dma_channel);
|
||||
}
|
||||
if (rx_dma_channel != -1) {
|
||||
retRx = MXC_DMA_Start(rx_dma_channel);
|
||||
}
|
||||
|
||||
if (retTx != E_NO_ERROR) {
|
||||
return retTx;
|
||||
} else {
|
||||
return retRx;
|
||||
}
|
||||
}
|
||||
|
||||
int MXC_I2S_RevA_DMA_ClearFlags(void)
|
||||
{
|
||||
int flags = MXC_DMA_ChannelGetFlags(dma_channel);
|
||||
return MXC_DMA_ChannelClearFlags(dma_channel, flags);
|
||||
int retTx = E_NO_ERROR;
|
||||
int retRx = E_NO_ERROR;
|
||||
|
||||
int flags;
|
||||
|
||||
if (tx_dma_channel != -1) {
|
||||
flags = MXC_DMA_ChannelGetFlags(tx_dma_channel);
|
||||
retTx = MXC_DMA_ChannelClearFlags(tx_dma_channel, flags);
|
||||
}
|
||||
if (rx_dma_channel != -1) {
|
||||
flags = MXC_DMA_ChannelGetFlags(rx_dma_channel);
|
||||
retRx = MXC_DMA_ChannelClearFlags(rx_dma_channel, flags);
|
||||
}
|
||||
|
||||
if (retTx != E_NO_ERROR) {
|
||||
return retTx;
|
||||
} else {
|
||||
return retRx;
|
||||
}
|
||||
}
|
||||
|
||||
int MXC_I2S_RevA_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count)
|
||||
{
|
||||
int retTx = E_NO_ERROR;
|
||||
int retRx = E_NO_ERROR;
|
||||
|
||||
mxc_dma_srcdst_t srcdst;
|
||||
srcdst.ch = dma_channel;
|
||||
srcdst.source = src_addr;
|
||||
srcdst.dest = dst_addr;
|
||||
srcdst.len = count;
|
||||
return MXC_DMA_SetSrcDst(srcdst);
|
||||
|
||||
if (tx_dma_channel != -1) {
|
||||
srcdst.ch = tx_dma_channel;
|
||||
srcdst.source = src_addr;
|
||||
srcdst.dest = dst_addr;
|
||||
srcdst.len = count;
|
||||
retTx = MXC_DMA_SetSrcDst(srcdst);
|
||||
}
|
||||
if (rx_dma_channel != -1) {
|
||||
srcdst.ch = rx_dma_channel;
|
||||
srcdst.source = src_addr;
|
||||
srcdst.dest = dst_addr;
|
||||
srcdst.len = count;
|
||||
retRx = MXC_DMA_SetSrcDst(srcdst);
|
||||
}
|
||||
|
||||
if (retTx != E_NO_ERROR) {
|
||||
return retTx;
|
||||
} else {
|
||||
return retRx;
|
||||
}
|
||||
}
|
||||
|
||||
int MXC_I2S_RevA_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count)
|
||||
{
|
||||
int retTx = E_NO_ERROR;
|
||||
int retRx = E_NO_ERROR;
|
||||
|
||||
mxc_dma_srcdst_t srcdst;
|
||||
srcdst.ch = dma_channel;
|
||||
srcdst.source = src_addr;
|
||||
srcdst.dest = dst_addr;
|
||||
srcdst.len = count;
|
||||
return MXC_DMA_SetSrcReload(srcdst);
|
||||
|
||||
if (tx_dma_channel != -1) {
|
||||
srcdst.ch = tx_dma_channel;
|
||||
srcdst.source = src_addr;
|
||||
srcdst.dest = dst_addr;
|
||||
srcdst.len = count;
|
||||
retTx = MXC_DMA_SetSrcReload(srcdst);
|
||||
}
|
||||
if (rx_dma_channel != -1) {
|
||||
srcdst.ch = rx_dma_channel;
|
||||
srcdst.source = src_addr;
|
||||
srcdst.dest = dst_addr;
|
||||
srcdst.len = count;
|
||||
retRx = MXC_DMA_SetSrcReload(srcdst);
|
||||
}
|
||||
|
||||
if (retTx != E_NO_ERROR) {
|
||||
return retTx;
|
||||
} else {
|
||||
return retRx;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,7 +29,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_I2S_REVA_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_I2S_REVA_H_
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stddef.h>
|
||||
|
|
@ -37,9 +40,8 @@
|
|||
#include "i2s.h"
|
||||
#include "spimss_reva_regs.h"
|
||||
|
||||
|
||||
|
||||
int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *req, void (*dma_ctz_cb)(int, int));
|
||||
int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *req,
|
||||
void (*dma_ctz_cb)(int, int));
|
||||
int MXC_I2S_RevA_Shutdown(mxc_spimss_reva_regs_t *spimss);
|
||||
int MXC_I2S_RevA_Mute(mxc_spimss_reva_regs_t *spimss);
|
||||
int MXC_I2S_RevA_Unmute(mxc_spimss_reva_regs_t *spimss);
|
||||
|
|
@ -50,3 +52,5 @@ int MXC_I2S_RevA_Start(mxc_spimss_reva_regs_t *spimss);
|
|||
int MXC_I2S_RevA_DMA_ClearFlags(void);
|
||||
int MXC_I2S_RevA_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count);
|
||||
int MXC_I2S_RevA_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count);
|
||||
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_I2S_REVA_H_
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stddef.h>
|
||||
|
|
@ -42,11 +42,17 @@
|
|||
#include "spimss_reva_regs.h"
|
||||
#include "spimss_reva.h"
|
||||
|
||||
/* **** Functions **** */
|
||||
/* **** Functions **** */
|
||||
|
||||
/* ************************************************************************** */
|
||||
int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg, unsigned drv_ssel)
|
||||
int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg)
|
||||
{
|
||||
int spi_num;
|
||||
|
||||
spi_num = MXC_SPIMSS_GET_IDX(spi);
|
||||
|
||||
MXC_ASSERT(spi_num >= 0);
|
||||
|
||||
if (mode > 3) {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
|
@ -59,73 +65,67 @@ int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const
|
|||
// Configure GPIO for spimss
|
||||
if (spi == MXC_SPIMSS) {
|
||||
MXC_GCR->rst0 |= MXC_F_GCR_RST0_SPI1;
|
||||
while (MXC_GCR->rst0 & MXC_F_GCR_RST0_SPI1);
|
||||
MXC_GCR->pclk_dis0 &= ~ (MXC_F_GCR_PCLK_DIS0_SPI1D);
|
||||
if(sys_cfg == MAP_A){
|
||||
MXC_GPIO_Config(&gpio_cfg_spi1a); // SPI1A chosen
|
||||
}else if(sys_cfg == MAP_B){
|
||||
MXC_GPIO_Config(&gpio_cfg_spi1b); // SPI1B chosen
|
||||
}else{
|
||||
while (MXC_GCR->rst0 & MXC_F_GCR_RST0_SPI1) {}
|
||||
MXC_GCR->pclk_dis0 &= ~(MXC_F_GCR_PCLK_DIS0_SPI1D);
|
||||
if (sys_cfg == MAP_A) {
|
||||
MXC_GPIO_Config(&gpio_cfg_spi1a); // SPI1A chosen
|
||||
} else if (sys_cfg == MAP_B) {
|
||||
MXC_GPIO_Config(&gpio_cfg_spi1b); // SPI1B chosen
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
} else {
|
||||
return E_NO_DEVICE;
|
||||
}
|
||||
|
||||
return MXC_SPIMSS_RevA_Init((mxc_spimss_reva_regs_t*) spi, mode, freq, drv_ssel);
|
||||
return MXC_SPIMSS_RevA_Init((mxc_spimss_reva_regs_t *)spi, mode, freq);
|
||||
}
|
||||
/* ************************************************************************* */
|
||||
int MXC_SPIMSS_Shutdown(mxc_spimss_regs_t *spi)
|
||||
{
|
||||
if(spi != MXC_SPIMSS) {
|
||||
return E_NO_DEVICE;
|
||||
int spi_num;
|
||||
spi_num = MXC_SPIMSS_GET_IDX(spi);
|
||||
MXC_ASSERT(spi_num >= 0);
|
||||
|
||||
MXC_SPIMSS_RevA_Shutdown((mxc_spimss_reva_regs_t *)spi);
|
||||
|
||||
if (spi == MXC_SPIMSS) {
|
||||
MXC_GCR->pclk_dis0 |= (MXC_F_GCR_PCLK_DIS0_SPI1D);
|
||||
}
|
||||
|
||||
MXC_SPIMSS_RevA_Shutdown((mxc_spimss_reva_regs_t*) spi);
|
||||
//
|
||||
MXC_GCR->pclk_dis0 |= (MXC_F_GCR_PCLK_DIS0_SPI1D);
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
/* ************************************************************************** */
|
||||
void MXC_SPIMSS_Handler(mxc_spimss_regs_t *spi) // From the IRQ
|
||||
void MXC_SPIMSS_Handler(mxc_spimss_regs_t *spi) // From the IRQ
|
||||
{
|
||||
MXC_SPIMSS_RevA_Handler((mxc_spimss_reva_regs_t*) spi);
|
||||
MXC_SPIMSS_RevA_Handler((mxc_spimss_reva_regs_t *)spi);
|
||||
}
|
||||
|
||||
/* ************************************************************************** */
|
||||
int MXC_SPIMSS_MasterTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req)
|
||||
{
|
||||
return MXC_SPIMSS_RevA_MasterTrans((mxc_spimss_reva_regs_t*) spi, (spimss_reva_req_t*) req);
|
||||
return MXC_SPIMSS_RevA_MasterTrans((mxc_spimss_reva_regs_t *)spi, (spimss_reva_req_t *)req);
|
||||
}
|
||||
|
||||
|
||||
/* ************************************************************************** */
|
||||
int MXC_SPIMSS_SlaveTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req)
|
||||
{
|
||||
return MXC_SPIMSS_RevA_SlaveTrans((mxc_spimss_reva_regs_t*) spi, (spimss_reva_req_t*) req);
|
||||
return MXC_SPIMSS_RevA_SlaveTrans((mxc_spimss_reva_regs_t *)spi, (spimss_reva_req_t *)req);
|
||||
}
|
||||
|
||||
/* ************************************************************************** */
|
||||
int MXC_SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req)
|
||||
{
|
||||
return MXC_SPIMSS_RevA_MasterTransAsync((mxc_spimss_reva_regs_t*) spi, (spimss_reva_req_t*) req);
|
||||
return MXC_SPIMSS_RevA_MasterTransAsync((mxc_spimss_reva_regs_t *)spi,
|
||||
(spimss_reva_req_t *)req);
|
||||
}
|
||||
|
||||
/* ************************************************************************** */
|
||||
int MXC_SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req)
|
||||
{
|
||||
return MXC_SPIMSS_RevA_SlaveTransAsync((mxc_spimss_reva_regs_t*) spi, (spimss_reva_req_t*) req);
|
||||
return MXC_SPIMSS_RevA_SlaveTransAsync((mxc_spimss_reva_regs_t *)spi, (spimss_reva_req_t *)req);
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int MXC_SPIMSS_SetDefaultTXData(mxc_spimss_req_t* spi, unsigned int defaultTXData)
|
||||
{
|
||||
return MXC_SPIMSS_RevA_SetDefaultTXData((spimss_reva_req_t*) spi, defaultTXData);
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int MXC_SPIMSS_AbortAsync(mxc_spimss_req_t *req)
|
||||
{
|
||||
return MXC_SPIMSS_RevA_AbortAsync((spimss_reva_req_t*) req);
|
||||
return MXC_SPIMSS_RevA_AbortAsync((spimss_reva_req_t *)req);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
/**
|
||||
/**
|
||||
* @file spimss.c
|
||||
* @brief This file contains the function implementations for the
|
||||
* Serial Peripheral Interface (SPIMSS) peripheral module.
|
||||
*/
|
||||
|
||||
/* *****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -35,9 +35,8 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
**************************************************************************** */
|
||||
|
||||
******************************************************************************/
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
|
|
@ -55,48 +54,46 @@
|
|||
|
||||
/* **** Definitions **** */
|
||||
|
||||
|
||||
|
||||
/* **** Globals **** */
|
||||
typedef struct {
|
||||
spimss_reva_req_t *req;
|
||||
unsigned defaultTXData;
|
||||
unsigned drv_ssel;
|
||||
} spimss_reva_req_state_t;
|
||||
|
||||
static spimss_reva_req_state_t states[MXC_SPIMSS_INSTANCES];
|
||||
|
||||
|
||||
/* **** Functions **** */
|
||||
static int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req, int master);
|
||||
static uint32_t MXC_SPIMSS_RevA_MasterTransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
|
||||
static int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req,
|
||||
int master);
|
||||
static uint32_t MXC_SPIMSS_RevA_MasterTransHandler(mxc_spimss_reva_regs_t *spi,
|
||||
spimss_reva_req_t *req);
|
||||
static uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
|
||||
static uint32_t MXC_SPIMSS_RevA_SlaveTransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
|
||||
static uint32_t MXC_SPIMSS_RevA_SlaveTransHandler(mxc_spimss_reva_regs_t *spi,
|
||||
spimss_reva_req_t *req);
|
||||
|
||||
/* ************************************************************************** */
|
||||
int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq, unsigned drv_ssel)
|
||||
int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq)
|
||||
{
|
||||
int spi_num;
|
||||
unsigned int spimss_clk;
|
||||
unsigned int pol, pha; // Polarity and phase of the clock (SPI mode)
|
||||
unsigned int pol, pha; // Polarity and phase of the clock (SPI mode)
|
||||
|
||||
spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
|
||||
spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t *)spi);
|
||||
states[spi_num].req = NULL;
|
||||
states[spi_num].defaultTXData = 0;
|
||||
states[spi_num].drv_ssel = drv_ssel;
|
||||
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Keep the SPI Disabled (This is the SPI Start)
|
||||
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Keep the SPI Disabled (This is the SPI Start)
|
||||
|
||||
// Set the bit rate
|
||||
// Set the bit rate
|
||||
spimss_clk = PeripheralClock;
|
||||
spi->brg = (spimss_clk / freq) >> 1;
|
||||
|
||||
// Set the mode
|
||||
pol = mode >> 1; // Get the polarity out of the mode input value
|
||||
pha = mode & 1; // Get the phase out of the mode input value
|
||||
pol = mode >> 1; // Get the polarity out of the mode input value
|
||||
pha = mode & 1; // Get the phase out of the mode input value
|
||||
|
||||
spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_REVA_CTRL_CLKPOL)) | (pol << MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS); // polarity
|
||||
|
||||
spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_REVA_CTRL_PHASE)) | (pha << MXC_F_SPIMSS_REVA_CTRL_PHASE_POS); // phase
|
||||
spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_REVA_CTRL_CLKPOL)) |
|
||||
(pol << MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS); // polarity
|
||||
|
||||
spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_REVA_CTRL_PHASE)) |
|
||||
(pha << MXC_F_SPIMSS_REVA_CTRL_PHASE_POS); // phase
|
||||
|
||||
spi->int_fl &= ~(MXC_F_SPIMSS_REVA_INT_FL_IRQ);
|
||||
|
||||
|
|
@ -109,22 +106,21 @@ int MXC_SPIMSS_RevA_Shutdown(mxc_spimss_reva_regs_t *spi)
|
|||
spimss_reva_req_t *temp_req;
|
||||
|
||||
// Disable and turn off the SPI transaction.
|
||||
spi->ctrl = 0; // Interrupts, SPI transaction all turned off
|
||||
spi->ctrl = 0; // Interrupts, SPI transaction all turned off
|
||||
spi->int_fl = 0;
|
||||
spi->mode = 0;
|
||||
spi->mode = 0;
|
||||
|
||||
// Reset FIFO counters
|
||||
spi->dma &= ~(MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT|MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT);
|
||||
spi->dma &= ~(MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT | MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT);
|
||||
|
||||
// Call all of the pending callbacks for this SPI
|
||||
spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
|
||||
spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t *)spi);
|
||||
if (states[spi_num].req != NULL) {
|
||||
|
||||
// Save the request
|
||||
temp_req = states[spi_num].req;
|
||||
|
||||
// Unlock this SPI
|
||||
MXC_FreeLock((uint32_t*)&states[spi_num].req);
|
||||
MXC_FreeLock((uint32_t *)&states[spi_num].req);
|
||||
|
||||
// Callback if not NULL
|
||||
if (temp_req->callback != NULL) {
|
||||
|
|
@ -142,17 +138,17 @@ int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *r
|
|||
{
|
||||
int spi_num;
|
||||
|
||||
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Make sure the Initiation
|
||||
// of SPI Start is disabled.
|
||||
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Make sure the Initiation
|
||||
// of SPI Start is disabled.
|
||||
|
||||
spi->mode |= MXC_F_SPIMSS_REVA_MODE_TX_LJ; // Making sure data is left
|
||||
// justified.
|
||||
spi->mode |= MXC_F_SPIMSS_REVA_MODE_TX_LJ; // Making sure data is left
|
||||
// justified.
|
||||
|
||||
if ((req->tx_data == NULL) && (req->rx_data == NULL)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
|
||||
spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t *)spi);
|
||||
MXC_ASSERT(spi_num >= 0);
|
||||
|
||||
if (req->len == 0) {
|
||||
|
|
@ -162,50 +158,41 @@ int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *r
|
|||
req->tx_num = 0;
|
||||
req->rx_num = 0;
|
||||
|
||||
if (MXC_GetLock((uint32_t*)&states[spi_num].req, (uint32_t)req) != E_NO_ERROR) {
|
||||
if (MXC_GetLock((uint32_t *)&states[spi_num].req, (uint32_t)req) != E_NO_ERROR) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
if (master) { // Enable master mode
|
||||
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_MMEN; // SPI configured as master.
|
||||
if (states[spi_num].drv_ssel) {
|
||||
spi->mode |= MXC_F_SPIMSS_REVA_MODE_SS_IO; // SSEL pin is an output.
|
||||
}
|
||||
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_MMEN; // SPI configured as master.
|
||||
spi->mode |= MXC_F_SPIMSS_REVA_CTRL_MMEN; // SSEL pin is an output.
|
||||
} else { // Enable slave mode
|
||||
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_MMEN); // SPI configured as slave.
|
||||
spi->mode &= ~(MXC_F_SPIMSS_REVA_MODE_SS_IO); // SSEL pin is an input.
|
||||
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_MMEN); // SPI configured as slave.
|
||||
spi->mode &= ~(MXC_F_SPIMSS_REVA_CTRL_MMEN); // SSEL pin is an input.
|
||||
}
|
||||
|
||||
// Setup the character size
|
||||
|
||||
if (req->bits <16) {
|
||||
MXC_SETFIELD(spi->mode, MXC_F_SPIMSS_REVA_MODE_NUMBITS , req->bits << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS);
|
||||
|
||||
if (req->bits < 16) {
|
||||
MXC_SETFIELD(spi->mode, MXC_F_SPIMSS_REVA_MODE_NUMBITS,
|
||||
req->bits << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS);
|
||||
|
||||
} else {
|
||||
MXC_SETFIELD(spi->mode, MXC_F_SPIMSS_REVA_MODE_NUMBITS , 0 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS);
|
||||
|
||||
MXC_SETFIELD(spi->mode, MXC_F_SPIMSS_REVA_MODE_NUMBITS,
|
||||
0 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS);
|
||||
}
|
||||
|
||||
if (req->tx_data == NULL) {
|
||||
// Must have something to send, so we'll use the rx_data buffer initialized to 0.
|
||||
memset(req->rx_data, states[spi_num].defaultTXData, (req->bits > 8 ? req->len << 1 : req->len));
|
||||
req->tx_data = req->rx_data;
|
||||
}
|
||||
// Setup the slave select
|
||||
spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV; // Assert a high on Slave Select,
|
||||
// to get the line ready for active low later
|
||||
|
||||
// Clear the TX and RX FIFO
|
||||
spi->dma |= (MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR | MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR);
|
||||
|
||||
if (states[spi_num].drv_ssel) {
|
||||
// Setup the slave select
|
||||
spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV; // Assert a high on Slave Select,
|
||||
// to get the line ready for active low later
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************** */
|
||||
void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi) // From the IRQ
|
||||
void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi) // From the IRQ
|
||||
{
|
||||
int spi_num;
|
||||
uint32_t flags;
|
||||
|
|
@ -213,23 +200,22 @@ void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi) // From the IRQ
|
|||
|
||||
flags = spi->int_fl;
|
||||
spi->int_fl = flags;
|
||||
spi->int_fl|= 0x80; // clear interrupt
|
||||
spi->int_fl |= 0x80; // clear interrupt
|
||||
|
||||
spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
|
||||
spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t *)spi);
|
||||
|
||||
int_enable = 0;
|
||||
if (states[spi_num].req != NULL) {
|
||||
if ((spi->ctrl & MXC_F_SPIMSS_REVA_CTRL_MMEN) >> MXC_F_SPIMSS_REVA_CTRL_MMEN_POS) {
|
||||
if ((spi->ctrl & MXC_F_SPIMSS_REVA_CTRL_MMEN) >> MXC_F_SPIMSS_REVA_CTRL_MMEN_POS) {
|
||||
int_enable = MXC_SPIMSS_RevA_MasterTransHandler(spi, states[spi_num].req);
|
||||
|
||||
|
||||
} else {
|
||||
int_enable = MXC_SPIMSS_RevA_SlaveTransHandler(spi, states[spi_num].req);
|
||||
int_enable = MXC_SPIMSS_RevA_SlaveTransHandler(spi, states[spi_num].req);
|
||||
}
|
||||
}
|
||||
|
||||
if (int_enable==1) {
|
||||
spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE );
|
||||
|
||||
if (int_enable == 1) {
|
||||
spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -237,48 +223,43 @@ void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi) // From the IRQ
|
|||
int MXC_SPIMSS_RevA_MasterTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req)
|
||||
{
|
||||
int error;
|
||||
int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
|
||||
|
||||
if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 1)) != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
|
||||
|
||||
req->callback = NULL;
|
||||
|
||||
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI
|
||||
if (states[spi_num].drv_ssel) {
|
||||
spi->mode &= ~(MXC_F_SPIMSS_REVA_MODE_SSV); // This will assert the Slave Select.
|
||||
}
|
||||
spi->mode &= ~(MXC_F_SPIMSS_REVA_MODE_SSV); // This will assert the Slave Select.
|
||||
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI
|
||||
|
||||
while (MXC_SPIMSS_RevA_MasterTransHandler(spi,req)!=0) {
|
||||
;
|
||||
}
|
||||
while (MXC_SPIMSS_RevA_MasterTransHandler(spi, req) != 0) {}
|
||||
|
||||
if (states[spi_num].drv_ssel) {
|
||||
spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV;
|
||||
}
|
||||
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted...
|
||||
// stop the transmission...
|
||||
spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV;
|
||||
|
||||
spi->ctrl &=
|
||||
~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted...
|
||||
// stop the transmission...
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
||||
/* ************************************************************************** */
|
||||
int MXC_SPIMSS_RevA_SlaveTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req)
|
||||
{
|
||||
int error;
|
||||
|
||||
if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req,0)) != E_NO_ERROR) {
|
||||
|
||||
if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 0)) != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
|
||||
while (MXC_SPIMSS_RevA_SlaveTransHandler(spi,req)!=0) {
|
||||
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI
|
||||
while ((spi->int_fl & MXC_F_SPIMSS_REVA_INT_FL_TXST) == MXC_F_SPIMSS_REVA_INT_FL_TXST) {}
|
||||
}
|
||||
while (MXC_SPIMSS_RevA_SlaveTransHandler(spi, req) != 0) {
|
||||
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI
|
||||
while ((spi->int_fl & MXC_F_SPIMSS_REVA_INT_FL_TXST) == MXC_F_SPIMSS_REVA_INT_FL_TXST) {}
|
||||
}
|
||||
|
||||
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted...
|
||||
// stop the transmission...
|
||||
spi->ctrl &=
|
||||
~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted...
|
||||
// stop the transmission...
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
|
@ -287,20 +268,21 @@ int MXC_SPIMSS_RevA_MasterTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_re
|
|||
{
|
||||
int error;
|
||||
uint8_t int_enable;
|
||||
int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
|
||||
|
||||
if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 1) )!= E_NO_ERROR) {
|
||||
return error;
|
||||
// Clear state for next transaction
|
||||
MXC_SPIMSS_AbortAsync((mxc_spimss_req_t *)req);
|
||||
|
||||
if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 1)) != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
|
||||
int_enable = MXC_SPIMSS_RevA_MasterTransHandler(spi,req);
|
||||
int_enable = MXC_SPIMSS_RevA_MasterTransHandler(spi, req);
|
||||
|
||||
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI
|
||||
if (states[spi_num].drv_ssel) {
|
||||
spi->mode ^= MXC_F_SPIMSS_REVA_MODE_SSV; // This will assert the Slave Select.
|
||||
}
|
||||
spi->mode ^= MXC_F_SPIMSS_REVA_MODE_SSV; // This will assert the Slave Select.
|
||||
|
||||
if (int_enable==1) {
|
||||
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI
|
||||
|
||||
if (int_enable == 1) {
|
||||
spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR);
|
||||
}
|
||||
|
||||
|
|
@ -316,12 +298,12 @@ int MXC_SPIMSS_RevA_SlaveTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req
|
|||
return error;
|
||||
}
|
||||
|
||||
int_enable = MXC_SPIMSS_RevA_SlaveTransHandler(spi,req);
|
||||
int_enable = MXC_SPIMSS_RevA_SlaveTransHandler(spi, req);
|
||||
|
||||
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI
|
||||
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI
|
||||
|
||||
if (int_enable==1) { // Trigger a SPI Interrupt
|
||||
spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE );
|
||||
if (int_enable == 1) { // Trigger a SPI Interrupt
|
||||
spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE);
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
|
|
@ -334,8 +316,8 @@ uint32_t MXC_SPIMSS_RevA_MasterTransHandler(mxc_spimss_reva_regs_t *spi, spimss_
|
|||
uint32_t retval;
|
||||
|
||||
if (!start_set) {
|
||||
start_set = 1;
|
||||
retval = MXC_SPIMSS_RevA_TransHandler(spi,req);
|
||||
start_set = 1;
|
||||
retval = MXC_SPIMSS_RevA_TransHandler(spi, req);
|
||||
}
|
||||
|
||||
return retval;
|
||||
|
|
@ -344,7 +326,7 @@ uint32_t MXC_SPIMSS_RevA_MasterTransHandler(mxc_spimss_reva_regs_t *spi, spimss_
|
|||
/* ************************************************************************** */
|
||||
uint32_t MXC_SPIMSS_RevA_SlaveTransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req)
|
||||
{
|
||||
return MXC_SPIMSS_RevA_TransHandler(spi,req);
|
||||
return MXC_SPIMSS_RevA_TransHandler(spi, req);
|
||||
}
|
||||
|
||||
/* ************************************************************************** */
|
||||
|
|
@ -352,40 +334,88 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r
|
|||
{
|
||||
unsigned tx_avail, rx_avail;
|
||||
int remain, spi_num;
|
||||
uint32_t int_en =0;
|
||||
uint32_t length =req->len;
|
||||
uint32_t int_en = 0;
|
||||
uint32_t length = req->len;
|
||||
|
||||
spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
|
||||
if (spi_num < 0) {
|
||||
MXC_ASSERT(0);
|
||||
spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t *)spi);
|
||||
|
||||
// Read the RX FIFO
|
||||
if (req->rx_data != NULL) {
|
||||
// Wait for there to be data in the RX FIFO
|
||||
rx_avail = ((spi->dma & MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) >>
|
||||
MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS);
|
||||
if ((length - req->rx_num) < rx_avail) {
|
||||
rx_avail = (length - req->rx_num);
|
||||
}
|
||||
|
||||
// Read from the FIFO
|
||||
while (rx_avail) {
|
||||
// Don't read less than 2 bytes if we are using greater than 8 bit characters
|
||||
if (req->bits > 8) {
|
||||
((uint16_t *)req->rx_data)[req->rx_num++] = spi->data;
|
||||
rx_avail -= 1;
|
||||
|
||||
} else {
|
||||
((uint8_t *)req->rx_data)[req->rx_num++] = spi->data;
|
||||
rx_avail -= 1;
|
||||
}
|
||||
rx_avail = ((spi->dma & MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) >>
|
||||
MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS);
|
||||
if ((length - req->rx_num) < rx_avail) {
|
||||
rx_avail = (length - req->rx_num);
|
||||
}
|
||||
}
|
||||
|
||||
remain = length - req->rx_num;
|
||||
|
||||
if (remain) {
|
||||
if (remain > MXC_SPIMSS_FIFO_DEPTH) {
|
||||
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) |
|
||||
((2) << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS));
|
||||
} else {
|
||||
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) |
|
||||
((remain - 1) << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS));
|
||||
}
|
||||
|
||||
int_en = 1;
|
||||
}
|
||||
|
||||
// Break out if we've received all the bytes and we're not transmitting
|
||||
if ((req->tx_data == NULL) && (req->rx_num == length)) {
|
||||
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR);
|
||||
int_en = 0;
|
||||
MXC_FreeLock((uint32_t *)&states[spi_num].req);
|
||||
// Callback if not NULL
|
||||
if (req->callback != NULL) {
|
||||
req->callback(req, E_NO_ERROR);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Note:- spi->dma shows the FIFO TX count and FIFO RX count in
|
||||
// Words, while the calculation below is in bytes.
|
||||
if (req->tx_data != NULL) {
|
||||
|
||||
if (req->tx_num < length) {
|
||||
|
||||
// Calculate how many bytes we can write to the FIFO (tx_avail holds that value)
|
||||
tx_avail = MXC_SPIMSS_FIFO_DEPTH - (((spi->dma & MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) >> MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS)); // in bytes
|
||||
tx_avail =
|
||||
MXC_SPIMSS_FIFO_DEPTH - (((spi->dma & MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) >>
|
||||
MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS)); // in bytes
|
||||
|
||||
if ((length - req->tx_num) < tx_avail) {
|
||||
tx_avail = (length - req->tx_num); // This is for the last spin
|
||||
tx_avail = (length - req->tx_num); // This is for the last spin
|
||||
}
|
||||
if (req->bits > 8) {
|
||||
tx_avail &= ~(unsigned)0x1;
|
||||
}
|
||||
// Write the FIFO
|
||||
while (tx_avail) {
|
||||
if (req->bits >8) {
|
||||
spi->data = ((uint16_t*)req->tx_data)[req->tx_num++];
|
||||
if (req->bits > 8) {
|
||||
spi->data = ((uint16_t *)req->tx_data)[req->tx_num++];
|
||||
|
||||
tx_avail -= 1;
|
||||
tx_avail -= 1;
|
||||
} else {
|
||||
spi->data = ((uint8_t*)req->tx_data)[req->tx_num++];
|
||||
tx_avail -=1;
|
||||
spi->data = ((uint8_t *)req->tx_data)[req->tx_num++];
|
||||
tx_avail -= 1;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -394,10 +424,13 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r
|
|||
// If there are values remaining to be transmitted, this portion will get
|
||||
// executed and int_en set, to indicate that this must spin and come back again...
|
||||
if (remain) {
|
||||
if (remain > MXC_SPIMSS_FIFO_DEPTH) { // more tx rounds will happen... Transfer the maximum,
|
||||
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) | ((MXC_SPIMSS_FIFO_DEPTH) << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS));
|
||||
} else { // only one more tx round will be done... Transfer whatever remains,
|
||||
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) | ((remain) << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS));
|
||||
if (remain >
|
||||
MXC_SPIMSS_FIFO_DEPTH) { // more tx rounds will happen... Transfer the maximum,
|
||||
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) |
|
||||
((MXC_SPIMSS_FIFO_DEPTH) << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS));
|
||||
} else { // only one more tx round will be done... Transfer whatever remains,
|
||||
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) |
|
||||
((remain) << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS));
|
||||
}
|
||||
int_en = 1; // This will act as a trigger for the next round...
|
||||
}
|
||||
|
|
@ -406,7 +439,7 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r
|
|||
if ((req->rx_data == NULL) && (req->tx_num == length)) {
|
||||
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR);
|
||||
int_en = 0;
|
||||
MXC_FreeLock((uint32_t*)&states[spi_num].req);
|
||||
MXC_FreeLock((uint32_t *)&states[spi_num].req);
|
||||
// Callback if not NULL
|
||||
if (req->callback != NULL) {
|
||||
req->callback(req, E_NO_ERROR);
|
||||
|
|
@ -414,50 +447,11 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r
|
|||
}
|
||||
}
|
||||
|
||||
// Read the RX FIFO
|
||||
// Wait for there to be data in the RX FIFO
|
||||
uint16_t rx_data;
|
||||
|
||||
rx_avail = ((spi->dma & MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) >> MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS);
|
||||
if ((length - req->rx_num) < rx_avail) {
|
||||
rx_avail = (length - req->rx_num);
|
||||
}
|
||||
|
||||
// Read from the FIFO
|
||||
while (rx_avail) {
|
||||
rx_data = spi->data;
|
||||
rx_avail -= 1;
|
||||
|
||||
if (req->rx_data != NULL) {
|
||||
if (req->bits>8) {
|
||||
((uint16_t*)req->rx_data)[req->rx_num] = rx_data;
|
||||
} else {
|
||||
((uint8_t*)req->rx_data)[req->rx_num] = rx_data;
|
||||
}
|
||||
}
|
||||
req->rx_num++; // assume read one byte
|
||||
|
||||
rx_avail = ((spi->dma & MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) >> MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS);
|
||||
if ((length - req->rx_num) < rx_avail) {
|
||||
rx_avail = (length - req->rx_num);
|
||||
}
|
||||
}
|
||||
|
||||
remain = length - req->rx_num;
|
||||
if (remain) {
|
||||
if (remain > MXC_SPIMSS_FIFO_DEPTH) {
|
||||
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) | ((2) << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS));
|
||||
} else {
|
||||
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) | ((remain-1) << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS));
|
||||
}
|
||||
int_en = 1;
|
||||
}
|
||||
|
||||
// Break out once we've transmitted and received all of the data
|
||||
if ((req->rx_num == length) && (req->tx_num == length)) {
|
||||
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR);
|
||||
int_en = 0;
|
||||
MXC_FreeLock((uint32_t*)&states[spi_num].req);
|
||||
MXC_FreeLock((uint32_t *)&states[spi_num].req);
|
||||
// Callback if not NULL
|
||||
if (req->callback != NULL) {
|
||||
req->callback(req, E_NO_ERROR);
|
||||
|
|
@ -467,15 +461,6 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r
|
|||
return int_en;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int MXC_SPIMSS_RevA_SetDefaultTXData (spimss_reva_req_t* spi, unsigned int defaultTXData)
|
||||
{
|
||||
int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
|
||||
MXC_ASSERT (spi_num >= 0);
|
||||
states[spi_num].defaultTXData = defaultTXData;
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int MXC_SPIMSS_RevA_AbortAsync(spimss_reva_req_t *req)
|
||||
{
|
||||
|
|
@ -490,17 +475,16 @@ int MXC_SPIMSS_RevA_AbortAsync(spimss_reva_req_t *req)
|
|||
// Find the request, set to NULL
|
||||
for (spi_num = 0; spi_num < MXC_SPIMSS_INSTANCES; spi_num++) {
|
||||
if (req == states[spi_num].req) {
|
||||
|
||||
spi =(mxc_spimss_reva_regs_t *) MXC_SPIMSS_GET_SPI(spi_num);
|
||||
spi = (mxc_spimss_reva_regs_t *)MXC_SPIMSS_GET_SPI(spi_num);
|
||||
|
||||
// Disable interrupts, clear the flags
|
||||
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR);
|
||||
|
||||
// Disable and turn off the SPI transaction.
|
||||
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE);
|
||||
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE);
|
||||
|
||||
// Unlock this SPI
|
||||
MXC_FreeLock((uint32_t*)&states[spi_num].req);
|
||||
MXC_FreeLock((uint32_t *)&states[spi_num].req);
|
||||
|
||||
// Callback if not NULL
|
||||
if (req->callback != NULL) {
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,7 +29,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_SPIMSS_REVA_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_SPIMSS_REVA_H_
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stddef.h>
|
||||
|
|
@ -44,13 +47,13 @@
|
|||
#include "spimss_reva_regs.h"
|
||||
#include "spimss.h"
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief Enumeration type for setting the number data lines to use for communication.
|
||||
*/
|
||||
typedef enum { // ONLY FOR COMPATIBILITY FOR CONSOLIDATION WITH SPY17, NOT USED OR NEEDED
|
||||
DUMMY_1_RevA, /**< NOT USED */
|
||||
DUMMY_2_RevA, /**< NOT USED */
|
||||
DUMMY_3_RevA, /**< NOT USED */
|
||||
typedef enum { // ONLY FOR COMPATIBILITY FOR CONSOLIDATION WITH SPY17, NOT USED OR NEEDED
|
||||
DUMMY_1_RevA, /**< NOT USED */
|
||||
DUMMY_2_RevA, /**< NOT USED */
|
||||
DUMMY_3_RevA, /**< NOT USED */
|
||||
} spimss_reva_width_t;
|
||||
|
||||
/**
|
||||
|
|
@ -71,7 +74,7 @@ typedef struct spimss_reva_req spimss_reva_req_t;
|
|||
* @note Callback will execute in interrupt context
|
||||
* @addtogroup spi_async
|
||||
*/
|
||||
typedef void (*spimss_reva_callback_fn)(spimss_reva_req_t * req, int error_code);
|
||||
typedef void (*spimss_reva_callback_fn)(spimss_reva_req_t *req, int error_code);
|
||||
|
||||
/**
|
||||
* @brief Structure definition for an SPI Master Transaction request.
|
||||
|
|
@ -80,25 +83,25 @@ typedef void (*spimss_reva_callback_fn)(spimss_reva_req_t * req, int error_code)
|
|||
* @addtogroup spi_async
|
||||
*/
|
||||
struct spimss_reva_req {
|
||||
uint8_t ssel; /**< Not Used*/
|
||||
uint8_t deass; /**< Not Used*/
|
||||
const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */
|
||||
void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/
|
||||
spimss_reva_width_t width; /**< Not Used */
|
||||
unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */
|
||||
unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */
|
||||
unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */
|
||||
unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */
|
||||
spimss_reva_callback_fn callback; /**< Callback function if desired, NULL otherwise */
|
||||
uint8_t ssel; /**< Not Used*/
|
||||
uint8_t deass; /**< Not Used*/
|
||||
const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */
|
||||
void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/
|
||||
spimss_reva_width_t width; /**< Not Used */
|
||||
unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */
|
||||
unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */
|
||||
unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */
|
||||
unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */
|
||||
spimss_reva_callback_fn callback; /**< Callback function if desired, NULL otherwise */
|
||||
};
|
||||
|
||||
|
||||
int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq, unsigned drv_ssel);
|
||||
int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq);
|
||||
int MXC_SPIMSS_RevA_Shutdown(mxc_spimss_reva_regs_t *spi);
|
||||
void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi);
|
||||
int MXC_SPIMSS_RevA_MasterTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
|
||||
int MXC_SPIMSS_RevA_SlaveTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
|
||||
int MXC_SPIMSS_RevA_MasterTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
|
||||
int MXC_SPIMSS_RevA_SlaveTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
|
||||
int MXC_SPIMSS_RevA_SetDefaultTXData (spimss_reva_req_t* spi, unsigned int defaultTXData);
|
||||
int MXC_SPIMSS_RevA_AbortAsync(spimss_reva_req_t *req);
|
||||
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_SPIMSS_REVA_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,8 +34,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _SPIMSS_REVA_REGS_H_
|
||||
#define _SPIMSS_REVA_REGS_H_
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* *****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,8 +29,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_device.h"
|
||||
|
|
@ -42,7 +41,7 @@
|
|||
/* **** Functions **** */
|
||||
|
||||
/* ************************************************************************** */
|
||||
__weak void mxc_assert(const char* expr, const char* file, int line)
|
||||
__weak void mxc_assert(const char *expr, const char *file, int line)
|
||||
{
|
||||
while (1) {}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* *****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,8 +29,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
|
@ -41,7 +40,7 @@
|
|||
|
||||
#ifdef __riscv
|
||||
|
||||
int MXC_Delay(unsigned long us)
|
||||
int MXC_Delay(uint32_t us)
|
||||
{
|
||||
// Check if there is nothing to do
|
||||
if (us == 0) {
|
||||
|
|
@ -51,18 +50,18 @@ int MXC_Delay(unsigned long us)
|
|||
// Calculate number of cycles needed.
|
||||
uint32_t ticks = (MXC_SYS_RiscVClockRate() / 1000000) * us;
|
||||
|
||||
CSR_SetPCMR(0); // Turn off counter
|
||||
CSR_SetPCCR(0); // Clear counter register
|
||||
CSR_SetPCER(1); // Enable counting of cycles
|
||||
CSR_SetPCMR(3); // Turn on counter
|
||||
CSR_SetPCMR(0); // Turn off counter
|
||||
CSR_SetPCCR(0); // Clear counter register
|
||||
CSR_SetPCER(1); // Enable counting of cycles
|
||||
CSR_SetPCMR(3); // Turn on counter
|
||||
|
||||
while(CSR_GetPCCR() < ticks) {
|
||||
while (CSR_GetPCCR() < ticks) {
|
||||
// Wait for counter to reach the tick count.
|
||||
}
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_DelayAsync(unsigned long us, mxc_delay_complete_t callback)
|
||||
int MXC_DelayAsync(uint32_t us, mxc_delay_complete_t callback)
|
||||
{
|
||||
return E_NOT_SUPPORTED;
|
||||
}
|
||||
|
|
@ -72,9 +71,7 @@ int MXC_DelayCheck(void)
|
|||
return E_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
void MXC_DelayAbort(void)
|
||||
{
|
||||
}
|
||||
void MXC_DelayAbort(void) {}
|
||||
|
||||
#else
|
||||
|
||||
|
|
@ -84,7 +81,7 @@ static uint32_t endtick;
|
|||
static uint32_t ctrl_save;
|
||||
static mxc_delay_complete_t cbFunc;
|
||||
|
||||
static void MXC_DelayInit(unsigned long us);
|
||||
static void MXC_DelayInit(uint32_t us);
|
||||
extern void SysTick_Handler(void);
|
||||
|
||||
/* ************************************************************************** */
|
||||
|
|
@ -101,10 +98,9 @@ void MXC_DelayHandler(void)
|
|||
// Decrement overflow flag if delay is still ongoing
|
||||
if (overflows > 0) {
|
||||
overflows--;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
MXC_DelayAbort();
|
||||
|
||||
|
||||
if (cbFunc != NULL) {
|
||||
cbFunc(E_NO_ERROR);
|
||||
cbFunc = NULL;
|
||||
|
|
@ -114,16 +110,16 @@ void MXC_DelayHandler(void)
|
|||
}
|
||||
|
||||
/* ************************************************************************** */
|
||||
static void MXC_DelayInit(unsigned long us)
|
||||
static void MXC_DelayInit(uint32_t us)
|
||||
{
|
||||
uint32_t starttick, reload, ticks, lastticks;
|
||||
|
||||
|
||||
// Record the current tick value and clear the overflow flag
|
||||
starttick = SysTick->VAL;
|
||||
|
||||
|
||||
// Save the state of control register (and clear the overflow flag)
|
||||
ctrl_save = SysTick->CTRL & ~SysTick_CTRL_COUNTFLAG_Msk;
|
||||
|
||||
|
||||
// If the SysTick is not running, configure and start it
|
||||
if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) {
|
||||
SysTick->LOAD = SysTick_LOAD_RELOAD_Msk;
|
||||
|
|
@ -131,53 +127,51 @@ static void MXC_DelayInit(unsigned long us)
|
|||
SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk;
|
||||
starttick = SysTick_VAL_CURRENT_Msk;
|
||||
reload = SysTick_LOAD_RELOAD_Msk + 1;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
reload = SysTick->LOAD + 1; // get the current reload value
|
||||
}
|
||||
|
||||
|
||||
// Calculate the total number of ticks to delay
|
||||
ticks = (uint32_t)(((uint64_t) us * (uint64_t) SystemCoreClock) / 1000000);
|
||||
|
||||
ticks = (uint32_t)(((uint64_t)us * (uint64_t)SystemCoreClock) / 1000000);
|
||||
|
||||
// How many overflows of the SysTick will occur
|
||||
overflows = ticks / reload;
|
||||
|
||||
|
||||
// How many remaining ticks after the last overflow
|
||||
lastticks = ticks % reload;
|
||||
|
||||
|
||||
// Check if there will be another overflow due to the current value of the SysTick
|
||||
if (lastticks >= starttick) {
|
||||
overflows++;
|
||||
endtick = reload - (lastticks - starttick);
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
endtick = starttick - lastticks;
|
||||
}
|
||||
}
|
||||
|
||||
/* ************************************************************************** */
|
||||
int MXC_DelayAsync(unsigned long us, mxc_delay_complete_t callback)
|
||||
int MXC_DelayAsync(uint32_t us, mxc_delay_complete_t callback)
|
||||
{
|
||||
cbFunc = callback;
|
||||
|
||||
|
||||
// Check if timeout currently ongoing
|
||||
if (overflows > 0) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
||||
// Check if there is nothing to do
|
||||
if (us == 0) {
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
||||
// Calculate the necessary delay and start the timer
|
||||
MXC_DelayInit(us);
|
||||
|
||||
|
||||
// Enable SysTick interrupt if necessary
|
||||
if (overflows > 0) {
|
||||
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
|
@ -190,22 +184,22 @@ int MXC_DelayCheck(void)
|
|||
cbFunc(E_NO_ERROR);
|
||||
cbFunc = NULL;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
||||
// Check the global values
|
||||
if ((overflows == 0) && (SysTick->VAL <= endtick)) {
|
||||
MXC_DelayAbort();
|
||||
|
||||
|
||||
if (cbFunc != NULL) {
|
||||
cbFunc(E_NO_ERROR);
|
||||
cbFunc = NULL;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
|
@ -216,27 +210,27 @@ void MXC_DelayAbort(void)
|
|||
cbFunc(E_ABORT);
|
||||
cbFunc = NULL;
|
||||
}
|
||||
|
||||
|
||||
SysTick->CTRL = ctrl_save;
|
||||
overflows = -1;
|
||||
}
|
||||
|
||||
/* ************************************************************************** */
|
||||
int MXC_Delay(unsigned long us)
|
||||
int MXC_Delay(uint32_t us)
|
||||
{
|
||||
// Check if timeout currently ongoing
|
||||
if (overflows > 0) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
||||
// Check if there is nothing to do
|
||||
if (us == 0) {
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
||||
// Calculate the necessary delay and start the timer
|
||||
MXC_DelayInit(us);
|
||||
|
||||
|
||||
// Wait for the number of overflows
|
||||
while (overflows > 0) {
|
||||
// If SysTick interrupts are enabled, COUNTFLAG will never be set here and
|
||||
|
|
@ -246,12 +240,12 @@ int MXC_Delay(unsigned long us)
|
|||
overflows--;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// Wait for the counter value
|
||||
while (SysTick->VAL > endtick);
|
||||
|
||||
while (SysTick->VAL > endtick) {}
|
||||
|
||||
MXC_DelayAbort();
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
#endif // __riscv
|
||||
#endif // __riscv
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,37 +29,33 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_device.h"
|
||||
#include "mxc_lock.h"
|
||||
|
||||
#if USE_LOCK_IN_DRIVERS
|
||||
|
||||
#ifndef __riscv
|
||||
/* ************************************************************************** */
|
||||
int MXC_GetLock(uint32_t* lock, uint32_t value)
|
||||
int MXC_GetLock(uint32_t *lock, uint32_t value)
|
||||
{
|
||||
do {
|
||||
|
||||
// Return if the lock is taken by a different thread
|
||||
if (__LDREXW((volatile unsigned long*) lock) != 0) {
|
||||
if (__LDREXW((volatile uint32_t *)lock) != 0) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
|
||||
// Attempt to take the lock
|
||||
}
|
||||
while (__STREXW(value, (volatile unsigned long*) lock) != 0);
|
||||
|
||||
} while (__STREXW(value, (volatile uint32_t *)lock) != 0);
|
||||
|
||||
// Do not start any other memory access until memory barrier is complete
|
||||
__DMB();
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************** */
|
||||
void MXC_FreeLock(uint32_t* lock)
|
||||
void MXC_FreeLock(uint32_t *lock)
|
||||
{
|
||||
// Ensure memory operations complete before releasing lock
|
||||
__DMB();
|
||||
|
|
@ -67,17 +63,15 @@ void MXC_FreeLock(uint32_t* lock)
|
|||
}
|
||||
#else // __riscv
|
||||
/* ************************************************************************** */
|
||||
int MXC_GetLock(uint32_t* lock, uint32_t value)
|
||||
{
|
||||
#warning "Unimplemented for RISCV"
|
||||
int MXC_GetLock(uint32_t *lock, uint32_t value)
|
||||
{
|
||||
#warning "Unimplemented for RISCV"
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************** */
|
||||
void MXC_FreeLock(uint32_t* lock)
|
||||
void MXC_FreeLock(uint32_t *lock)
|
||||
{
|
||||
#warning "Unimplemented for RISCV"
|
||||
#warning "Unimplemented for RISCV"
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // USE_LOCK_IN_DRIVERS
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief This file contains constant pin configurations for the peripherals.
|
||||
*/
|
||||
|
||||
/* *****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,8 +34,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#include "gpio.h"
|
||||
#include "mxc_device.h"
|
||||
|
|
@ -43,34 +42,55 @@
|
|||
/***** Definitions *****/
|
||||
|
||||
/***** Global Variables *****/
|
||||
const mxc_gpio_cfg_t gpio_cfg_swda = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
|
||||
const mxc_gpio_cfg_t gpio_cfg_swdb = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
|
||||
const mxc_gpio_cfg_t gpio_cfg_swda = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1),
|
||||
MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
|
||||
const mxc_gpio_cfg_t gpio_cfg_swdb = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9),
|
||||
MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
|
||||
|
||||
const mxc_gpio_cfg_t gpio_cfg_i2c0 = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, MXC_GPIO_VSSEL_VDDIO};
|
||||
const mxc_gpio_cfg_t gpio_cfg_i2c1 = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, MXC_GPIO_VSSEL_VDDIO};
|
||||
const mxc_gpio_cfg_t gpio_cfg_i2c0 = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9),
|
||||
MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP,
|
||||
MXC_GPIO_VSSEL_VDDIO };
|
||||
const mxc_gpio_cfg_t gpio_cfg_i2c1 = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3),
|
||||
MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP,
|
||||
MXC_GPIO_VSSEL_VDDIO };
|
||||
|
||||
const mxc_gpio_cfg_t gpio_cfg_uart0 = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5),
|
||||
MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
|
||||
const mxc_gpio_cfg_t gpio_cfg_uart0_flow = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7),
|
||||
MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
|
||||
const mxc_gpio_cfg_t gpio_cfg_uart1a = { MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11),
|
||||
MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
|
||||
const mxc_gpio_cfg_t gpio_cfg_uart1b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1),
|
||||
MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE };
|
||||
const mxc_gpio_cfg_t gpio_cfg_uart1c = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7),
|
||||
MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE };
|
||||
const mxc_gpio_cfg_t gpio_cfg_uart1_flow = { MXC_GPIO0, (MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13),
|
||||
MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
|
||||
|
||||
const mxc_gpio_cfg_t gpio_cfg_uart0 = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
|
||||
const mxc_gpio_cfg_t gpio_cfg_uart0_flow = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
|
||||
const mxc_gpio_cfg_t gpio_cfg_uart1a = { MXC_GPIO0, (MXC_GPIO_PIN_10|MXC_GPIO_PIN_11), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
|
||||
const mxc_gpio_cfg_t gpio_cfg_uart1b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE };
|
||||
const mxc_gpio_cfg_t gpio_cfg_uart1c = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE };
|
||||
const mxc_gpio_cfg_t gpio_cfg_uart1_flow = { MXC_GPIO0, (MXC_GPIO_PIN_12|MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
|
||||
|
||||
//SPI0
|
||||
const mxc_gpio_cfg_t gpio_cfg_spi0 = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
|
||||
const mxc_gpio_cfg_t gpio_cfg_spi0_ss = { MXC_GPIO0, MXC_GPIO_PIN_7, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
|
||||
// SPI1A
|
||||
const mxc_gpio_cfg_t gpio_cfg_spi1a = { MXC_GPIO0, (MXC_GPIO_PIN_10| MXC_GPIO_PIN_11| MXC_GPIO_PIN_12), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
|
||||
const mxc_gpio_cfg_t gpio_cfg_spi1a_ss = { MXC_GPIO0, MXC_GPIO_PIN_13, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
|
||||
//SPI1B
|
||||
const mxc_gpio_cfg_t gpio_cfg_spi1b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
|
||||
const mxc_gpio_cfg_t gpio_cfg_spi1b_ss = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
|
||||
|
||||
const mxc_gpio_cfg_t gpio_cfg_spi0 = {
|
||||
MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7),
|
||||
MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE
|
||||
};
|
||||
const mxc_gpio_cfg_t gpio_cfg_spi1a = {
|
||||
MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11 | MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13),
|
||||
MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE
|
||||
};
|
||||
const mxc_gpio_cfg_t gpio_cfg_spi1b = {
|
||||
MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3),
|
||||
MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE
|
||||
};
|
||||
|
||||
// Timers are only defined once, depending on package, each timer could be mapped to other pins
|
||||
const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO};
|
||||
const mxc_gpio_cfg_t gpio_cfg_32kcal = { MXC_GPIO0, MXC_GPIO_PIN_2, MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO};
|
||||
const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT3,
|
||||
MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO };
|
||||
const mxc_gpio_cfg_t gpio_cfg_32kcal = { MXC_GPIO0, MXC_GPIO_PIN_2, MXC_GPIO_FUNC_ALT3,
|
||||
MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO };
|
||||
|
||||
const mxc_gpio_cfg_t gpio_cfg_i2s0a = { MXC_GPIO0, (MXC_GPIO_PIN_10| MXC_GPIO_PIN_11| MXC_GPIO_PIN_12|MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
|
||||
const mxc_gpio_cfg_t gpio_cfg_i2s0b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
|
||||
const mxc_gpio_cfg_t gpio_cfg_i2s0a = {
|
||||
MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11 | MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13),
|
||||
MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE
|
||||
};
|
||||
const mxc_gpio_cfg_t gpio_cfg_i2s0b = {
|
||||
MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3),
|
||||
MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,8 +29,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @file mxc_sys.c
|
||||
|
|
@ -45,6 +44,7 @@
|
|||
#include "mxc_assert.h"
|
||||
#include "mxc_sys.h"
|
||||
#include "mxc_delay.h"
|
||||
#include "flc.h"
|
||||
#include "gcr_regs.h"
|
||||
#include "fcr_regs.h"
|
||||
|
||||
|
|
@ -54,48 +54,98 @@
|
|||
*/
|
||||
|
||||
/* **** Definitions **** */
|
||||
#define MXC_SYS_CLOCK_TIMEOUT MXC_DELAY_MSEC(1)
|
||||
#define MXC_SYS_CLOCK_TIMEOUT MXC_DELAY_MSEC(1)
|
||||
|
||||
/* **** Globals **** */
|
||||
|
||||
/* **** Functions **** */
|
||||
|
||||
/* ************************************************************************** */
|
||||
int MXC_SYS_IsClockEnabled (mxc_sys_periph_clock_t clock)
|
||||
int MXC_SYS_GetUSN(uint8_t *usn, int len, int part)
|
||||
{
|
||||
if (len != MXC_SYS_USN_LEN) {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
uint32_t infoblock[6];
|
||||
|
||||
MXC_FLC_UnlockInfoBlock(0x0000);
|
||||
infoblock[0] = *(uint32_t *)MXC_INFO_MEM_BASE;
|
||||
infoblock[1] = *(uint32_t *)(MXC_INFO_MEM_BASE + 4);
|
||||
infoblock[2] = *(uint32_t *)(MXC_INFO_MEM_BASE + 8);
|
||||
infoblock[3] = *(uint32_t *)(MXC_INFO_MEM_BASE + 12);
|
||||
infoblock[4] = *(uint32_t *)(MXC_INFO_MEM_BASE + 16);
|
||||
infoblock[5] = *(uint32_t *)(MXC_INFO_MEM_BASE + 20);
|
||||
MXC_FLC_LockInfoBlock(0x0000);
|
||||
|
||||
if (part == 0) {
|
||||
usn[0] = (infoblock[0] & 0x000000FF);
|
||||
usn[1] = (infoblock[0] & 0x0000FF00) >> 8;
|
||||
usn[2] = (infoblock[0] & 0x00FF0000) >> 16;
|
||||
usn[3] = (infoblock[0] & 0x3F000000) >> 24;
|
||||
usn[3] |= (infoblock[1] & 0x00000003) << 30;
|
||||
usn[4] = (infoblock[1] & 0x000003FC) >> 2;
|
||||
usn[5] = (infoblock[1] & 0x0003FC00) >> 10;
|
||||
usn[6] = (infoblock[1] & 0x03FC0000) >> 18;
|
||||
usn[7] = (infoblock[1] & 0x3C000000) >> 26;
|
||||
} else if (part == 1) {
|
||||
usn[0] = (infoblock[2] & 0x000000FF);
|
||||
usn[1] = (infoblock[2] & 0x0000FF00) >> 8;
|
||||
usn[2] = (infoblock[2] & 0x00FF0000) >> 16;
|
||||
usn[3] = (infoblock[2] & 0xFF000000) >> 24;
|
||||
usn[4] = (infoblock[3] & 0x000000FF);
|
||||
usn[5] = (infoblock[3] & 0x0000FF00) >> 8;
|
||||
usn[6] = (infoblock[3] & 0x00FF0000) >> 16;
|
||||
usn[7] = (infoblock[3] & 0xFF000000) >> 24;
|
||||
} else if (part == 2) {
|
||||
usn[0] = (infoblock[4] & 0x000000FF);
|
||||
usn[1] = (infoblock[4] & 0x0000FF00) >> 8;
|
||||
usn[2] = (infoblock[4] & 0x00FF0000) >> 16;
|
||||
usn[3] = (infoblock[4] & 0xFF000000) >> 24;
|
||||
usn[4] = (infoblock[5] & 0x000000FF);
|
||||
usn[5] = (infoblock[5] & 0x0000FF00) >> 8;
|
||||
usn[6] = (infoblock[5] & 0x00FF0000) >> 16;
|
||||
usn[7] = (infoblock[5] & 0xFF000000) >> 24;
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************** */
|
||||
int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock)
|
||||
{
|
||||
/* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 for the pclkdis1 register. */
|
||||
if (clock > 31) {
|
||||
clock -= 32;
|
||||
return ! (MXC_GCR->pclk_dis1 & (0x1 << clock));
|
||||
}
|
||||
else {
|
||||
return ! (MXC_GCR->pclk_dis0 & (0x1 << clock));
|
||||
return !(MXC_GCR->pclk_dis1 & (0x1 << clock));
|
||||
} else {
|
||||
return !(MXC_GCR->pclk_dis0 & (0x1 << clock));
|
||||
}
|
||||
}
|
||||
|
||||
/* ************************************************************************** */
|
||||
void MXC_SYS_ClockDisable (mxc_sys_periph_clock_t clock)
|
||||
void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock)
|
||||
{
|
||||
/* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 for the pclkdis1 register. */
|
||||
if (clock > 31) {
|
||||
clock -= 32;
|
||||
MXC_GCR->pclk_dis1 |= (0x1 << clock);
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
MXC_GCR->pclk_dis0 |= (0x1 << clock);
|
||||
}
|
||||
}
|
||||
|
||||
/* ************************************************************************** */
|
||||
void MXC_SYS_ClockEnable (mxc_sys_periph_clock_t clock)
|
||||
void MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock)
|
||||
{
|
||||
/* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 for the pclkdis1 register. */
|
||||
if (clock > 31) {
|
||||
clock -= 32;
|
||||
MXC_GCR->pclk_dis1 &= ~ (0x1 << clock);
|
||||
}
|
||||
else {
|
||||
MXC_GCR->pclk_dis0 &= ~ (0x1 << clock);
|
||||
MXC_GCR->pclk_dis1 &= ~(0x1 << clock);
|
||||
} else {
|
||||
MXC_GCR->pclk_dis0 &= ~(0x1 << clock);
|
||||
}
|
||||
}
|
||||
/* ************************************************************************** */
|
||||
|
|
@ -105,38 +155,36 @@ void MXC_SYS_RTCClockEnable()
|
|||
}
|
||||
|
||||
/* ************************************************************************** */
|
||||
int MXC_SYS_RTCClockDisable (void)
|
||||
int MXC_SYS_RTCClockDisable(void)
|
||||
{
|
||||
/* Check that the RTC is not the system clock source */
|
||||
if ((MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL) != MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN) {
|
||||
MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_X32K_EN;
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
return E_BAD_STATE;
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
int MXC_SYS_ClockSourceEnable (mxc_sys_system_clock_t clock)
|
||||
int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock)
|
||||
{
|
||||
switch (clock) {
|
||||
case MXC_SYS_CLOCK_HIRC:
|
||||
MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC_EN;
|
||||
return MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_HIRC_RDY);
|
||||
return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_HIRC_RDY);
|
||||
break;
|
||||
|
||||
|
||||
case MXC_SYS_CLOCK_HFXIN:
|
||||
MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN;
|
||||
return MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_X32K_RDY);
|
||||
return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_X32K_RDY);
|
||||
break;
|
||||
|
||||
|
||||
case MXC_SYS_CLOCK_NANORING:
|
||||
// MXC_GCR->clk_ctrl |= MXC_F_GCR_CLKCTRL_EXTCLK_EN;
|
||||
// return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_EXTCLK_RDY);
|
||||
return E_NOT_SUPPORTED;
|
||||
// 80khz nanoring is always enabled
|
||||
return E_NO_ERROR;
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
return E_BAD_PARAM;
|
||||
break;
|
||||
|
|
@ -144,146 +192,135 @@ int MXC_SYS_ClockSourceEnable (mxc_sys_system_clock_t clock)
|
|||
}
|
||||
|
||||
/******************************************************************************/
|
||||
int MXC_SYS_ClockSourceDisable (mxc_sys_system_clock_t clock)
|
||||
int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock)
|
||||
{
|
||||
uint32_t current_clock;
|
||||
|
||||
|
||||
current_clock = MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL;
|
||||
|
||||
|
||||
// Don't turn off the clock we're running on
|
||||
if (clock == current_clock) {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
switch (clock) {
|
||||
case MXC_SYS_CLOCK_HIRC:
|
||||
MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_HIRC_EN;
|
||||
break;
|
||||
|
||||
|
||||
case MXC_SYS_CLOCK_HFXIN:
|
||||
MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_X32K_EN;
|
||||
break;
|
||||
|
||||
|
||||
case MXC_SYS_CLOCK_NANORING:
|
||||
// MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLKCTRL_EXTCLK_EN;
|
||||
// 80khz nanoring is always enabled
|
||||
return E_BAD_PARAM;
|
||||
|
||||
|
||||
default:
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************** */
|
||||
int MXC_SYS_Clock_Timeout (uint32_t ready)
|
||||
int MXC_SYS_Clock_Timeout(uint32_t ready)
|
||||
{
|
||||
// Start timeout, wait for ready
|
||||
MXC_DelayAsync (MXC_SYS_CLOCK_TIMEOUT, NULL);
|
||||
|
||||
MXC_DelayAsync(MXC_SYS_CLOCK_TIMEOUT, NULL);
|
||||
|
||||
do {
|
||||
if (MXC_GCR->clk_ctrl & ready) {
|
||||
MXC_DelayAbort();
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
}
|
||||
while (MXC_DelayCheck() == E_BUSY);
|
||||
|
||||
} while (MXC_DelayCheck() == E_BUSY);
|
||||
|
||||
return E_TIME_OUT;
|
||||
}
|
||||
|
||||
/* ************************************************************************** */
|
||||
int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock)
|
||||
int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock)
|
||||
{
|
||||
uint32_t current_clock;
|
||||
|
||||
|
||||
// Save the current system clock
|
||||
current_clock = MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL;
|
||||
|
||||
|
||||
switch (clock) {
|
||||
case MXC_SYS_CLOCK_HIRC:
|
||||
|
||||
|
||||
// Enable HIRC clock
|
||||
if (! (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_HIRC_EN)) {
|
||||
|
||||
if (!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_HIRC_EN)) {
|
||||
MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC_EN;
|
||||
|
||||
|
||||
// Check if HIRC clock is ready
|
||||
if (MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_HIRC_RDY) != E_NO_ERROR) {
|
||||
if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_HIRC_RDY) != E_NO_ERROR) {
|
||||
return E_TIME_OUT;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// Set HIRC clock as System Clock
|
||||
MXC_SETFIELD (MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, MXC_S_GCR_CLK_CTRL_CLKSEL_HIRC);
|
||||
|
||||
MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, MXC_S_GCR_CLK_CTRL_CLKSEL_HIRC);
|
||||
|
||||
break;
|
||||
|
||||
|
||||
case MXC_SYS_CLOCK_HFXIN:
|
||||
|
||||
|
||||
// Enable HFXtal clock
|
||||
if (! (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_X32K_EN)) {
|
||||
MXC_GCR->clk_ctrl |=MXC_F_GCR_CLK_CTRL_X32K_EN;
|
||||
|
||||
if (!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_X32K_EN)) {
|
||||
MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN;
|
||||
|
||||
// Check if HFXtal clock is ready
|
||||
if (MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_X32K_RDY) != E_NO_ERROR) {
|
||||
if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_X32K_RDY) != E_NO_ERROR) {
|
||||
return E_TIME_OUT;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// Set HFXtal clock as System Clock
|
||||
MXC_SETFIELD (MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN);
|
||||
|
||||
MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN);
|
||||
|
||||
break;
|
||||
|
||||
|
||||
case MXC_SYS_CLOCK_NANORING:
|
||||
// Enable HIRC clock
|
||||
// if(!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLKCTRL_EXTCLK_EN)) {
|
||||
// MXC_GCR->clk_ctrl |=MXC_F_GCR_CLKCTRL_EXTCLK_EN;
|
||||
|
||||
// // Check if HIRC clock is ready
|
||||
// if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_EXTCLK_RDY) != E_NO_ERROR) {
|
||||
// return E_TIME_OUT;
|
||||
// }
|
||||
// }
|
||||
|
||||
// Set HIRC clock as System Clock
|
||||
// MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK);
|
||||
MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING);
|
||||
|
||||
if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_LIRC8K_RDY) != E_NO_ERROR) {
|
||||
return E_TIME_OUT;
|
||||
}
|
||||
|
||||
MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL,
|
||||
MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING);
|
||||
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
// Wait for system clock to be ready
|
||||
if (MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_CLKRDY) != E_NO_ERROR) {
|
||||
|
||||
if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_CLKRDY) != E_NO_ERROR) {
|
||||
// Restore the old system clock if timeout
|
||||
MXC_SETFIELD (MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, current_clock);
|
||||
|
||||
MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, current_clock);
|
||||
|
||||
return E_TIME_OUT;
|
||||
}
|
||||
|
||||
|
||||
// Update the system core clock
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
||||
/* ************************************************************************** */
|
||||
void MXC_SYS_Reset_Periph (mxc_sys_reset_t reset)
|
||||
void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset)
|
||||
{
|
||||
/* The mxc_sys_reset_t enum uses enum values that are the offset by 32 for the rstr1 register. */
|
||||
if (reset > 31) {
|
||||
reset -= 32;
|
||||
MXC_GCR->rst1 = (0x1 << reset);
|
||||
}
|
||||
else {
|
||||
while (MXC_GCR->rst1 & (0x1 << reset)) {}
|
||||
} else {
|
||||
MXC_GCR->rst0 = (0x1 << reset);
|
||||
while (MXC_GCR->rst0 & (0x1 << reset)) {}
|
||||
}
|
||||
}
|
||||
/**@} end of mxc_sys */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* *****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stddef.h>
|
||||
|
|
@ -39,92 +39,92 @@
|
|||
|
||||
/* **** Functions **** */
|
||||
|
||||
void MXC_TMR_Common_Delay(mxc_tmr_regs_t* tmr, unsigned long us)
|
||||
void MXC_TMR_Common_Delay(mxc_tmr_regs_t *tmr, uint32_t us)
|
||||
{
|
||||
// Return immediately if delay is 0
|
||||
if (!us) {
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
MXC_TMR_TO_Start(tmr, us);
|
||||
|
||||
|
||||
while (MXC_TMR_TO_Check(tmr) != E_TIME_OUT) {}
|
||||
}
|
||||
|
||||
int MXC_TMR_Common_TO_Check(mxc_tmr_regs_t* tmr)
|
||||
int MXC_TMR_Common_TO_Check(mxc_tmr_regs_t *tmr)
|
||||
{
|
||||
if (MXC_TMR_GetFlags(tmr)) {
|
||||
return E_TIME_OUT;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
void MXC_TMR_Common_TO_Stop(mxc_tmr_regs_t* tmr)
|
||||
void MXC_TMR_Common_TO_Stop(mxc_tmr_regs_t *tmr)
|
||||
{
|
||||
MXC_TMR_Stop(tmr);
|
||||
MXC_TMR_SetCount(tmr, 0x0);
|
||||
}
|
||||
|
||||
void MXC_TMR_Common_TO_Clear(mxc_tmr_regs_t* tmr)
|
||||
void MXC_TMR_Common_TO_Clear(mxc_tmr_regs_t *tmr)
|
||||
{
|
||||
MXC_TMR_ClearFlags(tmr);
|
||||
MXC_TMR_SetCount(tmr, 0x0);
|
||||
}
|
||||
|
||||
unsigned int MXC_TMR_Common_TO_Remaining(mxc_tmr_regs_t* tmr)
|
||||
unsigned int MXC_TMR_Common_TO_Remaining(mxc_tmr_regs_t *tmr)
|
||||
{
|
||||
uint32_t remaining_ticks, remaining_time;
|
||||
mxc_tmr_unit_t units;
|
||||
|
||||
|
||||
remaining_ticks = MXC_TMR_GetCompare(tmr) - MXC_TMR_GetCount(tmr);
|
||||
MXC_TMR_GetTime(tmr, remaining_ticks, &remaining_time, &units);
|
||||
|
||||
|
||||
switch (units) {
|
||||
case TMR_UNIT_NANOSEC:
|
||||
default:
|
||||
return (remaining_time / 1000);
|
||||
|
||||
|
||||
case TMR_UNIT_MICROSEC:
|
||||
return (remaining_time);
|
||||
|
||||
|
||||
case TMR_UNIT_MILLISEC:
|
||||
return (remaining_time * 1000);
|
||||
|
||||
|
||||
case TMR_UNIT_SEC:
|
||||
return (remaining_time * 1000000);
|
||||
}
|
||||
}
|
||||
|
||||
void MXC_TMR_Common_SW_Start(mxc_tmr_regs_t* tmr)
|
||||
void MXC_TMR_Common_SW_Start(mxc_tmr_regs_t *tmr)
|
||||
{
|
||||
MXC_TMR_TO_Start(tmr, 0xFFFFFFFF);
|
||||
}
|
||||
|
||||
unsigned int MXC_TMR_Common_SW_Stop(mxc_tmr_regs_t* tmr)
|
||||
unsigned int MXC_TMR_Common_SW_Stop(mxc_tmr_regs_t *tmr)
|
||||
{
|
||||
unsigned int elapsed = MXC_TMR_TO_Elapsed(tmr);
|
||||
MXC_TMR_TO_Stop(tmr);
|
||||
return elapsed;
|
||||
}
|
||||
|
||||
unsigned int MXC_TMR_Common_TO_Elapsed(mxc_tmr_regs_t* tmr)
|
||||
unsigned int MXC_TMR_Common_TO_Elapsed(mxc_tmr_regs_t *tmr)
|
||||
{
|
||||
uint32_t elapsed;
|
||||
mxc_tmr_unit_t units;
|
||||
MXC_TMR_GetTime (tmr, tmr->cnt, &elapsed, &units);
|
||||
|
||||
MXC_TMR_GetTime(tmr, tmr->cnt, &elapsed, &units);
|
||||
|
||||
switch (units) {
|
||||
case TMR_UNIT_NANOSEC:
|
||||
default:
|
||||
return (elapsed / 1000);
|
||||
|
||||
|
||||
case TMR_UNIT_MICROSEC:
|
||||
return (elapsed);
|
||||
|
||||
|
||||
case TMR_UNIT_MILLISEC:
|
||||
return (elapsed * 1000);
|
||||
|
||||
|
||||
case TMR_UNIT_SEC:
|
||||
return (elapsed * 1000000);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* *****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,7 +29,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_COMMON_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_COMMON_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stddef.h>
|
||||
|
|
@ -37,12 +40,14 @@
|
|||
#include "tmr.h"
|
||||
|
||||
/* **** Functions **** */
|
||||
void MXC_TMR_Common_Delay (mxc_tmr_regs_t *tmr, unsigned long us);
|
||||
void MXC_TMR_Common_TO_Start (mxc_tmr_regs_t *tmr, unsigned long us);
|
||||
int MXC_TMR_Common_TO_Check (mxc_tmr_regs_t *tmr);
|
||||
void MXC_TMR_Common_TO_Stop (mxc_tmr_regs_t *tmr);
|
||||
void MXC_TMR_Common_TO_Clear (mxc_tmr_regs_t *tmr);
|
||||
unsigned int MXC_TMR_Common_TO_Elapsed (mxc_tmr_regs_t *tmr);
|
||||
unsigned int MXC_TMR_Common_TO_Remaining (mxc_tmr_regs_t *tmr);
|
||||
void MXC_TMR_Common_SW_Start (mxc_tmr_regs_t *tmr);
|
||||
unsigned int MXC_TMR_Common_SW_Stop (mxc_tmr_regs_t *tmr);
|
||||
void MXC_TMR_Common_Delay(mxc_tmr_regs_t *tmr, uint32_t us);
|
||||
void MXC_TMR_Common_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us);
|
||||
int MXC_TMR_Common_TO_Check(mxc_tmr_regs_t *tmr);
|
||||
void MXC_TMR_Common_TO_Stop(mxc_tmr_regs_t *tmr);
|
||||
void MXC_TMR_Common_TO_Clear(mxc_tmr_regs_t *tmr);
|
||||
unsigned int MXC_TMR_Common_TO_Elapsed(mxc_tmr_regs_t *tmr);
|
||||
unsigned int MXC_TMR_Common_TO_Remaining(mxc_tmr_regs_t *tmr);
|
||||
void MXC_TMR_Common_SW_Start(mxc_tmr_regs_t *tmr);
|
||||
unsigned int MXC_TMR_Common_SW_Stop(mxc_tmr_regs_t *tmr);
|
||||
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_COMMON_H_
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/* *****************************************************************************
|
||||
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files(the "Software"),
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
|
|
@ -15,7 +15,7 @@
|
|||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
|
|
@ -24,61 +24,44 @@
|
|||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#include "tmr.h"
|
||||
#include "tmr_reva.h"
|
||||
#include "tmr_common.h"
|
||||
|
||||
int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t* cfg)
|
||||
int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg)
|
||||
{
|
||||
int tmr_id = MXC_TMR_GET_IDX(tmr);
|
||||
|
||||
MXC_ASSERT(tmr_id >= 0);
|
||||
|
||||
switch(cfg->clock){
|
||||
case MXC_TMR_EXT_CLK:
|
||||
MXC_GPIO_Config(&gpio_cfg_32kcal);
|
||||
break;
|
||||
|
||||
case MXC_TMR_HFIO_CLK:
|
||||
MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_HIRC);
|
||||
break;
|
||||
|
||||
case MXC_TMR_NANORING_CLK:
|
||||
MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_NANORING);
|
||||
break;
|
||||
|
||||
default:
|
||||
return E_BAD_PARAM;
|
||||
break;
|
||||
}
|
||||
|
||||
//enable peripheral clock and configure gpio pins
|
||||
switch(tmr_id) {
|
||||
switch (tmr_id) {
|
||||
case 0:
|
||||
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TIMER0);
|
||||
while(MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER0);
|
||||
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TIMER0);
|
||||
while (MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER0) {}
|
||||
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR0);
|
||||
MXC_GPIO_Config(&gpio_cfg_tmr0);
|
||||
break;
|
||||
case 1:
|
||||
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TIMER1);
|
||||
while(MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER1);
|
||||
while (MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER1) {}
|
||||
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR1);
|
||||
break;
|
||||
case 2:
|
||||
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TIMER2);
|
||||
while(MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER2);
|
||||
while (MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER2) {}
|
||||
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR2);
|
||||
break;
|
||||
}
|
||||
MXC_TMR_RevA_Init((mxc_tmr_reva_regs_t*) tmr, cfg);
|
||||
|
||||
MXC_TMR_RevA_Init((mxc_tmr_reva_regs_t *)tmr, cfg);
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
|
@ -87,11 +70,11 @@ void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr)
|
|||
int tmr_id = MXC_TMR_GET_IDX(tmr);
|
||||
MXC_ASSERT(tmr_id >= 0);
|
||||
|
||||
MXC_TMR_RevA_Shutdown((mxc_tmr_reva_regs_t*) tmr);
|
||||
|
||||
MXC_TMR_RevA_Shutdown((mxc_tmr_reva_regs_t *)tmr);
|
||||
|
||||
// System settigns
|
||||
//diasble peripheral clock
|
||||
switch(tmr_id) {
|
||||
switch (tmr_id) {
|
||||
case 0:
|
||||
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR0);
|
||||
break;
|
||||
|
|
@ -106,91 +89,77 @@ void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr)
|
|||
}
|
||||
}
|
||||
|
||||
void MXC_TMR_Start(mxc_tmr_regs_t* tmr)
|
||||
void MXC_TMR_Start(mxc_tmr_regs_t *tmr)
|
||||
{
|
||||
MXC_TMR_RevA_Start((mxc_tmr_reva_regs_t*) tmr);
|
||||
MXC_TMR_RevA_Start((mxc_tmr_reva_regs_t *)tmr);
|
||||
}
|
||||
|
||||
void MXC_TMR_Stop(mxc_tmr_regs_t* tmr)
|
||||
void MXC_TMR_Stop(mxc_tmr_regs_t *tmr)
|
||||
{
|
||||
MXC_TMR_RevA_Stop((mxc_tmr_reva_regs_t*) tmr);
|
||||
MXC_TMR_RevA_Stop((mxc_tmr_reva_regs_t *)tmr);
|
||||
}
|
||||
|
||||
int MXC_TMR_SetPWM(mxc_tmr_regs_t* tmr, uint32_t pwm)
|
||||
int MXC_TMR_SetPWM(mxc_tmr_regs_t *tmr, uint32_t pwm)
|
||||
{
|
||||
return MXC_TMR_RevA_SetPWM((mxc_tmr_reva_regs_t*) tmr, pwm);
|
||||
return MXC_TMR_RevA_SetPWM((mxc_tmr_reva_regs_t *)tmr, pwm);
|
||||
}
|
||||
|
||||
uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t* tmr)
|
||||
uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t *tmr)
|
||||
{
|
||||
return MXC_TMR_RevA_GetCompare((mxc_tmr_reva_regs_t*) tmr);
|
||||
return MXC_TMR_RevA_GetCompare((mxc_tmr_reva_regs_t *)tmr);
|
||||
}
|
||||
|
||||
uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t* tmr)
|
||||
uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t *tmr)
|
||||
{
|
||||
return MXC_TMR_RevA_GetCapture((mxc_tmr_reva_regs_t*) tmr);
|
||||
return MXC_TMR_RevA_GetCapture((mxc_tmr_reva_regs_t *)tmr);
|
||||
}
|
||||
|
||||
uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t* tmr, mxc_tmr_clock_t clock, uint32_t prescalar, uint32_t frequency)
|
||||
uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, uint32_t prescalar, uint32_t frequency)
|
||||
{
|
||||
uint32_t retVal, clkFreq;
|
||||
switch(clock) {
|
||||
case MXC_TMR_HFIO_CLK:
|
||||
clkFreq = PeripheralClock;
|
||||
break;
|
||||
case MXC_TMR_NANORING_CLK:
|
||||
clkFreq = 80000;
|
||||
break;
|
||||
case MXC_TMR_EXT_CLK:
|
||||
clkFreq = HFX_FREQ;
|
||||
break;
|
||||
default:
|
||||
clkFreq = PeripheralClock;
|
||||
break;
|
||||
}
|
||||
if(frequency == 0) {
|
||||
uint32_t retVal;
|
||||
|
||||
if (frequency == 0) {
|
||||
return 0;
|
||||
}
|
||||
else {
|
||||
retVal = clkFreq / (prescalar * frequency);
|
||||
} else {
|
||||
retVal = PeripheralClock / (prescalar * frequency);
|
||||
return retVal;
|
||||
}
|
||||
return retVal;
|
||||
}
|
||||
|
||||
uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t* tmr)
|
||||
uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t *tmr)
|
||||
{
|
||||
return MXC_TMR_RevA_GetCount((mxc_tmr_reva_regs_t*) tmr);
|
||||
return MXC_TMR_RevA_GetCount((mxc_tmr_reva_regs_t *)tmr);
|
||||
}
|
||||
|
||||
void MXC_TMR_ClearFlags(mxc_tmr_regs_t* tmr)
|
||||
void MXC_TMR_ClearFlags(mxc_tmr_regs_t *tmr)
|
||||
{
|
||||
MXC_TMR_RevA_ClearFlags((mxc_tmr_reva_regs_t*) tmr);
|
||||
MXC_TMR_RevA_ClearFlags((mxc_tmr_reva_regs_t *)tmr);
|
||||
}
|
||||
|
||||
uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t* tmr)
|
||||
uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t *tmr)
|
||||
{
|
||||
return MXC_TMR_RevA_GetFlags((mxc_tmr_reva_regs_t*) tmr);
|
||||
return MXC_TMR_RevA_GetFlags((mxc_tmr_reva_regs_t *)tmr);
|
||||
}
|
||||
|
||||
void MXC_TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt)
|
||||
{
|
||||
MXC_TMR_RevA_SetCompare((mxc_tmr_reva_regs_t*) tmr, cmp_cnt);
|
||||
MXC_TMR_RevA_SetCompare((mxc_tmr_reva_regs_t *)tmr, cmp_cnt);
|
||||
}
|
||||
|
||||
void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt)
|
||||
{
|
||||
MXC_TMR_RevA_SetCount((mxc_tmr_reva_regs_t*) tmr, cnt);
|
||||
MXC_TMR_RevA_SetCount((mxc_tmr_reva_regs_t *)tmr, cnt);
|
||||
}
|
||||
|
||||
void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, unsigned long us)
|
||||
void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us)
|
||||
{
|
||||
MXC_TMR_Common_Delay(tmr, us);
|
||||
}
|
||||
|
||||
void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, unsigned long us)
|
||||
void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us)
|
||||
{
|
||||
MXC_TMR_RevA_TO_Start((mxc_tmr_reva_regs_t*) tmr, us);
|
||||
MXC_TMR_RevA_TO_Start((mxc_tmr_reva_regs_t *)tmr, us);
|
||||
}
|
||||
|
||||
int MXC_TMR_TO_Check(mxc_tmr_regs_t *tmr)
|
||||
|
|
@ -230,5 +199,5 @@ unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t *tmr)
|
|||
|
||||
int MXC_TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units)
|
||||
{
|
||||
return MXC_TMR_RevA_GetTime((mxc_tmr_reva_regs_t*) tmr, ticks, time, units);
|
||||
return MXC_TMR_RevA_GetTime((mxc_tmr_reva_regs_t *)tmr, ticks, time, units);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
/* *****************************************************************************
|
||||
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files(the "Software"),
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
|
|
@ -29,10 +29,11 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stddef.h>
|
||||
#include <string.h>
|
||||
#include "mxc_assert.h"
|
||||
#include "tmr.h"
|
||||
#include "tmr_reva.h"
|
||||
|
|
@ -41,72 +42,72 @@
|
|||
#include "mxc_lock.h"
|
||||
|
||||
/* **** Functions **** */
|
||||
void MXC_TMR_RevA_Init(mxc_tmr_reva_regs_t *tmr, mxc_tmr_cfg_t* cfg)
|
||||
void MXC_TMR_RevA_Init(mxc_tmr_reva_regs_t *tmr, mxc_tmr_cfg_t *cfg)
|
||||
{
|
||||
// Clear interrupt flag
|
||||
tmr->intr = MXC_F_TMR_REVA_INTR_IRQ;
|
||||
|
||||
|
||||
// Set the prescaler
|
||||
switch(cfg->pres) {
|
||||
switch (cfg->pres) {
|
||||
case TMR_PRES_1:
|
||||
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV1);
|
||||
break;
|
||||
|
||||
|
||||
case TMR_PRES_2:
|
||||
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV2);
|
||||
break;
|
||||
|
||||
|
||||
case TMR_PRES_4:
|
||||
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV4);
|
||||
break;
|
||||
|
||||
|
||||
case TMR_PRES_8:
|
||||
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV8);
|
||||
break;
|
||||
|
||||
|
||||
case TMR_PRES_16:
|
||||
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV16);
|
||||
break;
|
||||
|
||||
|
||||
case TMR_PRES_32:
|
||||
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV32);
|
||||
break;
|
||||
|
||||
|
||||
case TMR_PRES_64:
|
||||
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV64);
|
||||
break;
|
||||
|
||||
|
||||
case TMR_PRES_128:
|
||||
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV128);
|
||||
break;
|
||||
|
||||
|
||||
case TMR_PRES_256:
|
||||
tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3);
|
||||
tmr->cn &= ~(MXC_S_TMR_REVA_CN_PRES_DIV1);
|
||||
break;
|
||||
|
||||
|
||||
case TMR_PRES_512:
|
||||
tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3);
|
||||
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV4);
|
||||
break;
|
||||
|
||||
|
||||
case TMR_PRES_1024:
|
||||
tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3);
|
||||
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV8);
|
||||
break;
|
||||
|
||||
|
||||
case TMR_PRES_2048:
|
||||
tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3);
|
||||
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV16);
|
||||
break;
|
||||
|
||||
|
||||
case TMR_PRES_4096:
|
||||
tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3);
|
||||
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV128);
|
||||
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV32);
|
||||
break;
|
||||
|
||||
default:
|
||||
tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3);
|
||||
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV128);
|
||||
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV1);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -119,186 +120,168 @@ void MXC_TMR_RevA_Init(mxc_tmr_reva_regs_t *tmr, mxc_tmr_cfg_t* cfg)
|
|||
|
||||
void MXC_TMR_RevA_Shutdown(mxc_tmr_reva_regs_t *tmr)
|
||||
{
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
|
||||
if (tmr_id < 0) {
|
||||
MXC_ASSERT(0);
|
||||
}
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
|
||||
MXC_ASSERT(tmr_id >= 0);
|
||||
|
||||
// Disable timer and clear settings
|
||||
tmr->cn = 0;
|
||||
}
|
||||
|
||||
void MXC_TMR_RevA_Start(mxc_tmr_reva_regs_t* tmr)
|
||||
void MXC_TMR_RevA_Start(mxc_tmr_reva_regs_t *tmr)
|
||||
{
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
|
||||
if (tmr_id < 0) {
|
||||
MXC_ASSERT(0);
|
||||
}
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
|
||||
MXC_ASSERT(tmr_id >= 0);
|
||||
|
||||
tmr->cn |= MXC_F_TMR_REVA_CN_TEN;
|
||||
}
|
||||
|
||||
void MXC_TMR_RevA_Stop(mxc_tmr_reva_regs_t* tmr)
|
||||
void MXC_TMR_RevA_Stop(mxc_tmr_reva_regs_t *tmr)
|
||||
{
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
|
||||
if (tmr_id < 0) {
|
||||
MXC_ASSERT(0);
|
||||
}
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
|
||||
MXC_ASSERT(tmr_id >= 0);
|
||||
|
||||
tmr->cn &= ~MXC_F_TMR_REVA_CN_TEN;
|
||||
}
|
||||
|
||||
int MXC_TMR_RevA_SetPWM(mxc_tmr_reva_regs_t* tmr, uint32_t pwm)
|
||||
int MXC_TMR_RevA_SetPWM(mxc_tmr_reva_regs_t *tmr, uint32_t pwm)
|
||||
{
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
|
||||
if (tmr_id < 0) {
|
||||
MXC_ASSERT(0);
|
||||
}
|
||||
|
||||
if(pwm > (tmr->cmp)) {
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
|
||||
MXC_ASSERT(tmr_id >= 0);
|
||||
|
||||
if (pwm > (tmr->cmp)) {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
tmr->pwm = pwm;
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
uint32_t MXC_TMR_RevA_GetCompare(mxc_tmr_reva_regs_t* tmr)
|
||||
uint32_t MXC_TMR_RevA_GetCompare(mxc_tmr_reva_regs_t *tmr)
|
||||
{
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
|
||||
if (tmr_id < 0) {
|
||||
MXC_ASSERT(0);
|
||||
}
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
|
||||
MXC_ASSERT(tmr_id >= 0);
|
||||
|
||||
return tmr->cmp;
|
||||
}
|
||||
|
||||
uint32_t MXC_TMR_RevA_GetCapture(mxc_tmr_reva_regs_t* tmr)
|
||||
uint32_t MXC_TMR_RevA_GetCapture(mxc_tmr_reva_regs_t *tmr)
|
||||
{
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
|
||||
if (tmr_id < 0) {
|
||||
MXC_ASSERT(0);
|
||||
}
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
|
||||
MXC_ASSERT(tmr_id >= 0);
|
||||
|
||||
return tmr->pwm;//check this
|
||||
return tmr->pwm; //check this
|
||||
}
|
||||
|
||||
uint32_t MXC_TMR_RevA_GetCount(mxc_tmr_reva_regs_t* tmr)
|
||||
uint32_t MXC_TMR_RevA_GetCount(mxc_tmr_reva_regs_t *tmr)
|
||||
{
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
|
||||
if (tmr_id < 0) {
|
||||
MXC_ASSERT(0);
|
||||
}
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
|
||||
MXC_ASSERT(tmr_id >= 0);
|
||||
|
||||
return tmr->cnt;
|
||||
}
|
||||
|
||||
void MXC_TMR_RevA_ClearFlags(mxc_tmr_reva_regs_t* tmr)
|
||||
void MXC_TMR_RevA_ClearFlags(mxc_tmr_reva_regs_t *tmr)
|
||||
{
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
|
||||
if (tmr_id < 0) {
|
||||
MXC_ASSERT(0);
|
||||
}
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
|
||||
MXC_ASSERT(tmr_id >= 0);
|
||||
|
||||
tmr->intr = MXC_F_TMR_REVA_INTR_IRQ;
|
||||
}
|
||||
|
||||
uint32_t MXC_TMR_RevA_GetFlags(mxc_tmr_reva_regs_t* tmr)
|
||||
uint32_t MXC_TMR_RevA_GetFlags(mxc_tmr_reva_regs_t *tmr)
|
||||
{
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
|
||||
if (tmr_id < 0) {
|
||||
MXC_ASSERT(0);
|
||||
}
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
|
||||
MXC_ASSERT(tmr_id >= 0);
|
||||
|
||||
return tmr->intr;
|
||||
}
|
||||
|
||||
void MXC_TMR_RevA_SetCompare(mxc_tmr_reva_regs_t *tmr, uint32_t cmp_cnt)
|
||||
{
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
|
||||
if (tmr_id < 0) {
|
||||
MXC_ASSERT(0);
|
||||
}
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
|
||||
MXC_ASSERT(tmr_id >= 0);
|
||||
|
||||
tmr->cmp = cmp_cnt;
|
||||
}
|
||||
|
||||
void MXC_TMR_RevA_SetCount(mxc_tmr_reva_regs_t *tmr, uint32_t cnt)
|
||||
{
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
|
||||
if (tmr_id < 0) {
|
||||
MXC_ASSERT(0);
|
||||
}
|
||||
|
||||
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t *)tmr);
|
||||
MXC_ASSERT(tmr_id >= 0);
|
||||
|
||||
tmr->cnt = cnt;
|
||||
}
|
||||
|
||||
void MXC_TMR_RevA_TO_Start(mxc_tmr_reva_regs_t *tmr, unsigned long us)
|
||||
void MXC_TMR_RevA_TO_Start(mxc_tmr_reva_regs_t *tmr, uint32_t us)
|
||||
{
|
||||
uint64_t ticks;
|
||||
int clk_shift = 0;
|
||||
|
||||
ticks = (uint64_t) us * (uint64_t) PeripheralClock / (uint64_t) 1000000;
|
||||
|
||||
while(ticks > 0xFFFFFFFFUL) {
|
||||
mxc_tmr_cfg_t cfg;
|
||||
|
||||
ticks = (uint64_t)us * (uint64_t)PeripheralClock / (uint64_t)1000000;
|
||||
|
||||
while (ticks > 0xFFFFFFFFUL) {
|
||||
ticks >>= 1;
|
||||
++clk_shift;
|
||||
}
|
||||
|
||||
mxc_tmr_pres_t prescale = (mxc_tmr_pres_t) clk_shift << MXC_F_TMR_REVA_CN_PRES_POS;
|
||||
mxc_tmr_cfg_t cfg = {0, 0, 0, 0}; // = (mxc_tmr_cfg_t) {.pres=0, .mode=0, .cmp_cnt=0, .pol=0};
|
||||
|
||||
|
||||
mxc_tmr_pres_t prescale = (mxc_tmr_pres_t)clk_shift << MXC_F_TMR_REVA_CN_PRES_POS;
|
||||
|
||||
memset(&cfg, 0, sizeof(mxc_tmr_cfg_t));
|
||||
|
||||
// Initialize the timer in one-shot mode
|
||||
cfg.pres = prescale;
|
||||
cfg.mode = TMR_MODE_ONESHOT;
|
||||
cfg.cmp_cnt = ticks;
|
||||
cfg.pol = 0;
|
||||
|
||||
MXC_TMR_Stop((mxc_tmr_regs_t*) tmr);
|
||||
MXC_TMR_Init((mxc_tmr_regs_t*) tmr, &cfg);
|
||||
MXC_TMR_ClearFlags((mxc_tmr_regs_t*) tmr);
|
||||
MXC_TMR_Start((mxc_tmr_regs_t*) tmr);
|
||||
|
||||
MXC_TMR_Stop((mxc_tmr_regs_t *)tmr);
|
||||
MXC_TMR_Init((mxc_tmr_regs_t *)tmr, &cfg);
|
||||
MXC_TMR_ClearFlags((mxc_tmr_regs_t *)tmr);
|
||||
MXC_TMR_Start((mxc_tmr_regs_t *)tmr);
|
||||
}
|
||||
|
||||
int MXC_TMR_RevA_GetTime(mxc_tmr_reva_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units)
|
||||
int MXC_TMR_RevA_GetTime(mxc_tmr_reva_regs_t *tmr, uint32_t ticks, uint32_t *time,
|
||||
mxc_tmr_unit_t *units)
|
||||
{
|
||||
uint64_t temp_time = 0;
|
||||
uint32_t timerClock = PeripheralClock;
|
||||
uint32_t prescale = ((tmr->cn & MXC_F_TMR_REVA_CN_PRES) >> MXC_F_TMR_REVA_CN_PRES_POS)
|
||||
|(((tmr->cn & MXC_F_TMR_REVA_CN_PRES3) >> (MXC_F_TMR_REVA_CN_PRES3_POS)) <<3);
|
||||
|
||||
temp_time = (uint64_t) ticks * 1000 * (1 <<(prescale & 0xF)) / (timerClock / 1000000);
|
||||
|
||||
if(!(temp_time & 0xffffffff00000000)) {
|
||||
uint32_t prescale =
|
||||
((tmr->cn & MXC_F_TMR_REVA_CN_PRES) >> MXC_F_TMR_REVA_CN_PRES_POS) |
|
||||
(((tmr->cn & MXC_F_TMR_REVA_CN_PRES3) >> (MXC_F_TMR_REVA_CN_PRES3_POS)) << 3);
|
||||
|
||||
temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / (timerClock / 1000000);
|
||||
|
||||
if (!(temp_time & 0xffffffff00000000)) {
|
||||
*time = temp_time;
|
||||
*units = TMR_UNIT_NANOSEC;
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
temp_time = (uint64_t) ticks * 1000 * (1 <<(prescale & 0xF)) / (timerClock / 1000);
|
||||
|
||||
if(!(temp_time & 0xffffffff00000000)) {
|
||||
|
||||
temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / (timerClock / 1000);
|
||||
|
||||
if (!(temp_time & 0xffffffff00000000)) {
|
||||
*time = temp_time;
|
||||
*units = TMR_UNIT_MICROSEC;
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
temp_time = (uint64_t) ticks * 1000 * (1 <<(prescale & 0xF)) / timerClock;
|
||||
|
||||
if(!(temp_time & 0xffffffff00000000)) {
|
||||
|
||||
temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / timerClock;
|
||||
|
||||
if (!(temp_time & 0xffffffff00000000)) {
|
||||
*time = temp_time;
|
||||
*units = TMR_UNIT_MILLISEC;
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
temp_time = (uint64_t) ticks * (1 <<(prescale & 0xF)) / timerClock;
|
||||
|
||||
if(!(temp_time & 0xffffffff00000000)) {
|
||||
|
||||
temp_time = (uint64_t)ticks * (1 << (prescale & 0xF)) / timerClock;
|
||||
|
||||
if (!(temp_time & 0xffffffff00000000)) {
|
||||
*time = temp_time;
|
||||
*units = TMR_UNIT_SEC;
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
||||
return E_INVALID;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
/* *****************************************************************************
|
||||
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files(the "Software"),
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
|
|
@ -29,7 +29,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_REVA_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_REVA_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stddef.h>
|
||||
|
|
@ -41,18 +44,20 @@
|
|||
#include "tmr_reva_regs.h"
|
||||
|
||||
/* **** Functions **** */
|
||||
void MXC_TMR_RevA_Init(mxc_tmr_reva_regs_t *tmr, mxc_tmr_cfg_t* cfg);
|
||||
void MXC_TMR_RevA_Init(mxc_tmr_reva_regs_t *tmr, mxc_tmr_cfg_t *cfg);
|
||||
void MXC_TMR_RevA_Shutdown(mxc_tmr_reva_regs_t *tmr);
|
||||
void MXC_TMR_RevA_Start(mxc_tmr_reva_regs_t* tmr);
|
||||
void MXC_TMR_RevA_Stop(mxc_tmr_reva_regs_t* tmr);
|
||||
int MXC_TMR_RevA_SetPWM(mxc_tmr_reva_regs_t* tmr, uint32_t pwm);
|
||||
uint32_t MXC_TMR_RevA_GetCompare(mxc_tmr_reva_regs_t* tmr);
|
||||
uint32_t MXC_TMR_RevA_GetCapture(mxc_tmr_reva_regs_t* tmr);
|
||||
uint32_t MXC_TMR_RevA_GetCount(mxc_tmr_reva_regs_t* tmr);
|
||||
void MXC_TMR_RevA_ClearFlags(mxc_tmr_reva_regs_t* tmr);
|
||||
uint32_t MXC_TMR_RevA_GetFlags(mxc_tmr_reva_regs_t* tmr);
|
||||
void MXC_TMR_RevA_Start(mxc_tmr_reva_regs_t *tmr);
|
||||
void MXC_TMR_RevA_Stop(mxc_tmr_reva_regs_t *tmr);
|
||||
int MXC_TMR_RevA_SetPWM(mxc_tmr_reva_regs_t *tmr, uint32_t pwm);
|
||||
uint32_t MXC_TMR_RevA_GetCompare(mxc_tmr_reva_regs_t *tmr);
|
||||
uint32_t MXC_TMR_RevA_GetCapture(mxc_tmr_reva_regs_t *tmr);
|
||||
uint32_t MXC_TMR_RevA_GetCount(mxc_tmr_reva_regs_t *tmr);
|
||||
void MXC_TMR_RevA_ClearFlags(mxc_tmr_reva_regs_t *tmr);
|
||||
uint32_t MXC_TMR_RevA_GetFlags(mxc_tmr_reva_regs_t *tmr);
|
||||
void MXC_TMR_RevA_SetCompare(mxc_tmr_reva_regs_t *tmr, uint32_t cmp_cnt);
|
||||
void MXC_TMR_RevA_SetCount(mxc_tmr_reva_regs_t *tmr, uint32_t cnt);
|
||||
void MXC_TMR_RevA_TO_Start(mxc_tmr_reva_regs_t *tmr, unsigned long us);
|
||||
int MXC_TMR_RevA_GetTime(mxc_tmr_reva_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units);
|
||||
void MXC_TMR_RevA_TO_Start(mxc_tmr_reva_regs_t *tmr, uint32_t us);
|
||||
int MXC_TMR_RevA_GetTime(mxc_tmr_reva_regs_t *tmr, uint32_t ticks, uint32_t *time,
|
||||
mxc_tmr_unit_t *units);
|
||||
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_REVA_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,8 +34,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _TMR_REVA_REGS_H_
|
||||
#define _TMR_REVA_REGS_H_
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,25 +29,25 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#include "uart_common.h"
|
||||
#include "uart.h"
|
||||
|
||||
int MXC_UART_Common_ReadCharacter(mxc_uart_regs_t* uart)
|
||||
int MXC_UART_Common_ReadCharacter(mxc_uart_regs_t *uart)
|
||||
{
|
||||
// Wait until FIFO has a character ready.
|
||||
while (MXC_UART_GetRXFIFOAvailable(uart) < 1);
|
||||
|
||||
while (MXC_UART_GetRXFIFOAvailable(uart) < 1) {}
|
||||
|
||||
// Read the character using the non-blocking function.
|
||||
return MXC_UART_ReadCharacterRaw(uart);
|
||||
}
|
||||
|
||||
int MXC_UART_Common_WriteCharacter(mxc_uart_regs_t* uart, uint8_t character)
|
||||
int MXC_UART_Common_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character)
|
||||
{
|
||||
// Wait until FIFO has space for the character.
|
||||
while (MXC_UART_GetTXFIFOAvailable(uart) < 1);
|
||||
|
||||
while (MXC_UART_GetTXFIFOAvailable(uart) < 1) {}
|
||||
|
||||
// Write the character using the non-blocking function.
|
||||
return MXC_UART_WriteCharacterRaw(uart, character);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,10 +29,14 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_COMMON_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_COMMON_H_
|
||||
|
||||
#include "uart_regs.h"
|
||||
|
||||
int MXC_UART_Common_ReadCharacter (mxc_uart_regs_t* uart);
|
||||
int MXC_UART_Common_WriteCharacter (mxc_uart_regs_t* uart, uint8_t character);
|
||||
int MXC_UART_Common_ReadCharacter(mxc_uart_regs_t *uart);
|
||||
int MXC_UART_Common_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character);
|
||||
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_COMMON_H_
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#include "uart.h"
|
||||
#include "mxc_device.h"
|
||||
|
|
@ -39,335 +39,374 @@
|
|||
#include "uart_common.h"
|
||||
#include "dma.h"
|
||||
|
||||
void MXC_UART_DMACallback (int ch, int error)
|
||||
void MXC_UART_DMACallback(int ch, int error)
|
||||
{
|
||||
return MXC_UART_RevA_DMACallback (ch, error);
|
||||
MXC_UART_RevA_DMACallback(ch, error);
|
||||
}
|
||||
|
||||
int MXC_UART_AsyncCallback (mxc_uart_regs_t* uart, int retVal)
|
||||
int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal)
|
||||
{
|
||||
return MXC_UART_RevA_AsyncCallback ((mxc_uart_reva_regs_t*) uart, retVal);
|
||||
return MXC_UART_RevA_AsyncCallback((mxc_uart_reva_regs_t *)uart, retVal);
|
||||
}
|
||||
|
||||
int MXC_UART_AsyncStop (mxc_uart_regs_t* uart)
|
||||
int MXC_UART_TxAsyncCallback(mxc_uart_regs_t *uart, int retVal)
|
||||
{
|
||||
return MXC_UART_RevA_AsyncStop ((mxc_uart_reva_regs_t*) uart);
|
||||
return MXC_UART_RevA_TxAsyncCallback((mxc_uart_reva_regs_t *)uart, retVal);
|
||||
}
|
||||
|
||||
int MXC_UART_Init (mxc_uart_regs_t* uart, unsigned int baud, sys_map_t map)
|
||||
int MXC_UART_RxAsyncCallback(mxc_uart_regs_t *uart, int retVal)
|
||||
{
|
||||
return MXC_UART_RevA_RxAsyncCallback((mxc_uart_reva_regs_t *)uart, retVal);
|
||||
}
|
||||
|
||||
int MXC_UART_AsyncStop(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_AsyncStop((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_TxAsyncStop(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_TxAsyncStop((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_RxAsyncStop(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_RxAsyncStop((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, sys_map_t map)
|
||||
{
|
||||
int retval;
|
||||
|
||||
retval = MXC_UART_Shutdown (uart);
|
||||
|
||||
|
||||
retval = MXC_UART_Shutdown(uart);
|
||||
|
||||
if (retval) {
|
||||
return retval;
|
||||
}
|
||||
|
||||
switch (MXC_UART_GET_IDX (uart)) {
|
||||
|
||||
switch (MXC_UART_GET_IDX(uart)) {
|
||||
case 0:
|
||||
MXC_GPIO_Config (&gpio_cfg_uart0);
|
||||
MXC_SYS_ClockEnable (MXC_SYS_PERIPH_CLOCK_UART0);
|
||||
MXC_GPIO_Config(&gpio_cfg_uart0);
|
||||
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART0);
|
||||
break;
|
||||
|
||||
|
||||
case 1:
|
||||
switch (map) {
|
||||
case MAP_A:
|
||||
MXC_GPIO_Config (&gpio_cfg_uart1a);
|
||||
break;
|
||||
case MAP_B:
|
||||
MXC_GPIO_Config (&gpio_cfg_uart1b);
|
||||
break;
|
||||
case MAP_C:
|
||||
MXC_GPIO_Config (&gpio_cfg_uart1c);
|
||||
break;
|
||||
}
|
||||
MXC_SYS_ClockEnable (MXC_SYS_PERIPH_CLOCK_UART1);
|
||||
switch (map) {
|
||||
case MAP_A:
|
||||
MXC_GPIO_Config(&gpio_cfg_uart1a);
|
||||
break;
|
||||
case MAP_B:
|
||||
MXC_GPIO_Config(&gpio_cfg_uart1b);
|
||||
break;
|
||||
case MAP_C:
|
||||
MXC_GPIO_Config(&gpio_cfg_uart1c);
|
||||
break;
|
||||
}
|
||||
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART1);
|
||||
break;
|
||||
|
||||
default:
|
||||
return E_BAD_PARAM;
|
||||
break;
|
||||
}
|
||||
|
||||
return MXC_UART_RevA_Init (((mxc_uart_reva_regs_t*) uart), baud);
|
||||
|
||||
return MXC_UART_RevA_Init(((mxc_uart_reva_regs_t *)uart), baud);
|
||||
}
|
||||
|
||||
int MXC_UART_Shutdown (mxc_uart_regs_t* uart)
|
||||
int MXC_UART_Shutdown(mxc_uart_regs_t *uart)
|
||||
{
|
||||
switch (MXC_UART_GET_IDX (uart)) {
|
||||
switch (MXC_UART_GET_IDX(uart)) {
|
||||
case 0:
|
||||
MXC_SYS_Reset_Periph (MXC_SYS_RESET0_UART0);
|
||||
MXC_SYS_ClockDisable (MXC_SYS_PERIPH_CLOCK_UART0);
|
||||
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART0);
|
||||
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART0);
|
||||
break;
|
||||
|
||||
|
||||
case 1:
|
||||
MXC_SYS_Reset_Periph (MXC_SYS_RESET0_UART1);
|
||||
MXC_SYS_ClockDisable (MXC_SYS_PERIPH_CLOCK_UART1);
|
||||
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART1);
|
||||
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART1);
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
return E_BAD_PARAM;
|
||||
break;
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_UART_ReadyForSleep (mxc_uart_regs_t* uart)
|
||||
int MXC_UART_ReadyForSleep(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_ReadyForSleep ((mxc_uart_reva_regs_t*) uart);
|
||||
return MXC_UART_RevA_ReadyForSleep((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_SetFrequency (mxc_uart_regs_t* uart, unsigned int baud)
|
||||
int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud)
|
||||
{
|
||||
return MXC_UART_RevA_SetFrequency ((mxc_uart_reva_regs_t*) uart, baud);
|
||||
return MXC_UART_RevA_SetFrequency((mxc_uart_reva_regs_t *)uart, baud);
|
||||
}
|
||||
|
||||
int MXC_UART_GetFrequency (mxc_uart_regs_t* uart)
|
||||
int MXC_UART_GetFrequency(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_GetFrequency ((mxc_uart_reva_regs_t*) uart);
|
||||
return MXC_UART_RevA_GetFrequency((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_SetDataSize (mxc_uart_regs_t* uart, int dataSize)
|
||||
int MXC_UART_SetDataSize(mxc_uart_regs_t *uart, int dataSize)
|
||||
{
|
||||
return MXC_UART_RevA_SetDataSize ((mxc_uart_reva_regs_t*) uart, dataSize);
|
||||
return MXC_UART_RevA_SetDataSize((mxc_uart_reva_regs_t *)uart, dataSize);
|
||||
}
|
||||
|
||||
int MXC_UART_SetStopBits (mxc_uart_regs_t* uart, mxc_uart_stop_t stopBits)
|
||||
int MXC_UART_SetStopBits(mxc_uart_regs_t *uart, mxc_uart_stop_t stopBits)
|
||||
{
|
||||
return MXC_UART_RevA_SetStopBits ((mxc_uart_reva_regs_t*) uart, stopBits);
|
||||
return MXC_UART_RevA_SetStopBits((mxc_uart_reva_regs_t *)uart, stopBits);
|
||||
}
|
||||
|
||||
int MXC_UART_SetParity (mxc_uart_regs_t* uart, mxc_uart_parity_t parity)
|
||||
int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity)
|
||||
{
|
||||
return MXC_UART_RevA_SetParity ((mxc_uart_reva_regs_t*) uart, parity);
|
||||
return MXC_UART_RevA_SetParity((mxc_uart_reva_regs_t *)uart, parity);
|
||||
}
|
||||
|
||||
int MXC_UART_SetFlowCtrl (mxc_uart_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold)
|
||||
int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold)
|
||||
{
|
||||
switch (MXC_UART_GET_IDX (uart)) {
|
||||
switch (MXC_UART_GET_IDX(uart)) {
|
||||
case 0:
|
||||
MXC_GPIO_Config (&gpio_cfg_uart0_flow);
|
||||
MXC_GPIO_Config(&gpio_cfg_uart0_flow);
|
||||
break;
|
||||
|
||||
|
||||
case 1:
|
||||
MXC_GPIO_Config (&gpio_cfg_uart1_flow);
|
||||
MXC_GPIO_Config(&gpio_cfg_uart1_flow);
|
||||
break;
|
||||
}
|
||||
|
||||
return MXC_UART_RevA_SetFlowCtrl ((mxc_uart_reva_regs_t*) uart, flowCtrl, rtsThreshold);
|
||||
|
||||
return MXC_UART_RevA_SetFlowCtrl((mxc_uart_reva_regs_t *)uart, flowCtrl, rtsThreshold);
|
||||
}
|
||||
|
||||
int MXC_UART_SetClockSource (mxc_uart_regs_t* uart, int usePCLK)
|
||||
int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, int usePCLK)
|
||||
{
|
||||
return MXC_UART_RevA_SetClockSource ((mxc_uart_reva_regs_t*) uart, usePCLK);
|
||||
return MXC_UART_RevA_SetClockSource((mxc_uart_reva_regs_t *)uart, usePCLK);
|
||||
}
|
||||
|
||||
int MXC_UART_SetNullModem (mxc_uart_regs_t* uart, int nullModem)
|
||||
int MXC_UART_SetNullModem(mxc_uart_regs_t *uart, int nullModem)
|
||||
{
|
||||
return MXC_UART_RevA_SetNullModem ((mxc_uart_reva_regs_t*) uart, nullModem);
|
||||
return MXC_UART_RevA_SetNullModem((mxc_uart_reva_regs_t *)uart, nullModem);
|
||||
}
|
||||
|
||||
int MXC_UART_SendBreak (mxc_uart_regs_t* uart)
|
||||
int MXC_UART_SendBreak(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_SendBreak ((mxc_uart_reva_regs_t*) uart);
|
||||
return MXC_UART_RevA_SendBreak((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_GetActive (mxc_uart_regs_t* uart)
|
||||
int MXC_UART_GetActive(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_GetActive ((mxc_uart_reva_regs_t*) uart);
|
||||
return MXC_UART_RevA_GetActive((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_AbortTransmission (mxc_uart_regs_t* uart)
|
||||
int MXC_UART_AbortTransmission(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_AbortTransmission ((mxc_uart_reva_regs_t*) uart);
|
||||
return MXC_UART_RevA_AbortTransmission((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_ReadCharacterRaw (mxc_uart_regs_t* uart)
|
||||
int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_ReadCharacterRaw ((mxc_uart_reva_regs_t*) uart);
|
||||
return MXC_UART_RevA_ReadCharacterRaw((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_WriteCharacterRaw (mxc_uart_regs_t* uart, uint8_t character)
|
||||
int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character)
|
||||
{
|
||||
return MXC_UART_RevA_WriteCharacterRaw ((mxc_uart_reva_regs_t*) uart, character);
|
||||
return MXC_UART_RevA_WriteCharacterRaw((mxc_uart_reva_regs_t *)uart, character);
|
||||
}
|
||||
|
||||
int MXC_UART_ReadCharacter (mxc_uart_regs_t* uart)
|
||||
int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_Common_ReadCharacter (uart);
|
||||
return MXC_UART_Common_ReadCharacter(uart);
|
||||
}
|
||||
|
||||
int MXC_UART_WriteCharacter (mxc_uart_regs_t* uart, uint8_t character)
|
||||
int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character)
|
||||
{
|
||||
return MXC_UART_Common_WriteCharacter (uart, character);
|
||||
return MXC_UART_Common_WriteCharacter(uart, character);
|
||||
}
|
||||
|
||||
int MXC_UART_Read (mxc_uart_regs_t* uart, uint8_t* buffer, int* len)
|
||||
int MXC_UART_Read(mxc_uart_regs_t *uart, uint8_t *buffer, int *len)
|
||||
{
|
||||
return MXC_UART_RevA_Read ((mxc_uart_reva_regs_t*) uart, buffer, len);
|
||||
return MXC_UART_RevA_Read((mxc_uart_reva_regs_t *)uart, buffer, len);
|
||||
}
|
||||
|
||||
int MXC_UART_Write (mxc_uart_regs_t* uart, uint8_t* byte, int* len)
|
||||
int MXC_UART_Write(mxc_uart_regs_t *uart, uint8_t *byte, int *len)
|
||||
{
|
||||
return MXC_UART_RevA_Write ((mxc_uart_reva_regs_t*) uart, byte, len);
|
||||
return MXC_UART_RevA_Write((mxc_uart_reva_regs_t *)uart, byte, len);
|
||||
}
|
||||
|
||||
unsigned int MXC_UART_ReadRXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes,
|
||||
unsigned int len)
|
||||
unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len)
|
||||
{
|
||||
return MXC_UART_RevA_ReadRXFIFO ((mxc_uart_reva_regs_t*) uart, bytes, len);
|
||||
|
||||
return MXC_UART_RevA_ReadRXFIFO((mxc_uart_reva_regs_t *)uart, bytes, len);
|
||||
}
|
||||
|
||||
int MXC_UART_ReadRXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes,
|
||||
unsigned int len, mxc_uart_dma_complete_cb_t callback)
|
||||
int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len,
|
||||
mxc_uart_dma_complete_cb_t callback)
|
||||
{
|
||||
mxc_dma_config_t config;
|
||||
|
||||
int uart_num = MXC_UART_GET_IDX (uart);
|
||||
|
||||
// Only UART 0, 1 and 2 are supported for DMA transaction
|
||||
int uart_num = MXC_UART_GET_IDX(uart);
|
||||
|
||||
// Only UART 0, 1 and 2 are supported for DMA transaction
|
||||
switch (uart_num) {
|
||||
case 0:
|
||||
config.reqsel = MXC_DMA_REQUEST_UART0RX;
|
||||
break;
|
||||
|
||||
|
||||
case 1:
|
||||
config.reqsel = MXC_DMA_REQUEST_UART1RX;
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
return E_BAD_PARAM;
|
||||
break;
|
||||
}
|
||||
|
||||
return MXC_UART_RevA_ReadRXFIFODMA ((mxc_uart_reva_regs_t*) uart, MXC_DMA, bytes, len, callback, config);
|
||||
return MXC_UART_RevA_ReadRXFIFODMA((mxc_uart_reva_regs_t *)uart, MXC_DMA, bytes, len, callback,
|
||||
config);
|
||||
}
|
||||
|
||||
unsigned int MXC_UART_GetRXFIFOAvailable (mxc_uart_regs_t* uart)
|
||||
unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_GetRXFIFOAvailable ((mxc_uart_reva_regs_t*) uart);
|
||||
return MXC_UART_RevA_GetRXFIFOAvailable((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
unsigned int MXC_UART_WriteTXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes,
|
||||
unsigned int len)
|
||||
unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len)
|
||||
{
|
||||
return MXC_UART_RevA_WriteTXFIFO ((mxc_uart_reva_regs_t*) uart, bytes, len);
|
||||
return MXC_UART_RevA_WriteTXFIFO((mxc_uart_reva_regs_t *)uart, bytes, len);
|
||||
}
|
||||
|
||||
int MXC_UART_WriteTXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes,
|
||||
unsigned int len, mxc_uart_dma_complete_cb_t callback)
|
||||
int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len,
|
||||
mxc_uart_dma_complete_cb_t callback)
|
||||
{
|
||||
mxc_dma_config_t config;
|
||||
|
||||
int uart_num = MXC_UART_GET_IDX (uart);
|
||||
int uart_num = MXC_UART_GET_IDX(uart);
|
||||
|
||||
// Only UART 0, 1 and 2 are supported for DMA transaction
|
||||
// Only UART 0, 1 and 2 are supported for DMA transaction
|
||||
switch (uart_num) {
|
||||
case 0:
|
||||
config.reqsel = MXC_DMA_REQUEST_UART0TX;
|
||||
break;
|
||||
|
||||
|
||||
case 1:
|
||||
config.reqsel = MXC_DMA_REQUEST_UART1TX;
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
return E_BAD_PARAM;
|
||||
break;
|
||||
}
|
||||
|
||||
return MXC_UART_RevA_WriteTXFIFODMA ((mxc_uart_reva_regs_t*) uart, MXC_DMA, bytes, len, callback, config);
|
||||
return MXC_UART_RevA_WriteTXFIFODMA((mxc_uart_reva_regs_t *)uart, MXC_DMA, bytes, len, callback,
|
||||
config);
|
||||
}
|
||||
|
||||
unsigned int MXC_UART_GetTXFIFOAvailable (mxc_uart_regs_t* uart)
|
||||
unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_GetTXFIFOAvailable ((mxc_uart_reva_regs_t*) uart);
|
||||
return MXC_UART_RevA_GetTXFIFOAvailable((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_ClearRXFIFO (mxc_uart_regs_t* uart)
|
||||
int MXC_UART_ClearRXFIFO(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_ClearRXFIFO ((mxc_uart_reva_regs_t*) uart);
|
||||
return MXC_UART_RevA_ClearRXFIFO((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_ClearTXFIFO (mxc_uart_regs_t* uart)
|
||||
int MXC_UART_ClearTXFIFO(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_ClearTXFIFO ((mxc_uart_reva_regs_t*) uart);
|
||||
return MXC_UART_RevA_ClearTXFIFO((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_SetRXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes)
|
||||
int MXC_UART_SetRXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes)
|
||||
{
|
||||
return MXC_UART_RevA_SetRXThreshold ((mxc_uart_reva_regs_t*) uart, numBytes);
|
||||
return MXC_UART_RevA_SetRXThreshold((mxc_uart_reva_regs_t *)uart, numBytes);
|
||||
}
|
||||
|
||||
unsigned int MXC_UART_GetRXThreshold (mxc_uart_regs_t* uart)
|
||||
unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_GetRXThreshold ((mxc_uart_reva_regs_t*) uart);
|
||||
return MXC_UART_RevA_GetRXThreshold((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_SetTXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes)
|
||||
int MXC_UART_SetTXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes)
|
||||
{
|
||||
return MXC_UART_RevA_SetTXThreshold ((mxc_uart_reva_regs_t*) uart, numBytes);
|
||||
return MXC_UART_RevA_SetTXThreshold((mxc_uart_reva_regs_t *)uart, numBytes);
|
||||
}
|
||||
|
||||
unsigned int MXC_UART_GetTXThreshold (mxc_uart_regs_t* uart)
|
||||
unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_GetTXThreshold ((mxc_uart_reva_regs_t*) uart);
|
||||
return MXC_UART_RevA_GetTXThreshold((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
unsigned int MXC_UART_GetFlags (mxc_uart_regs_t* uart)
|
||||
unsigned int MXC_UART_GetFlags(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_GetFlags ((mxc_uart_reva_regs_t*) uart);
|
||||
return MXC_UART_RevA_GetFlags((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_ClearFlags (mxc_uart_regs_t* uart, unsigned int flags)
|
||||
int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags)
|
||||
{
|
||||
return MXC_UART_RevA_ClearFlags ((mxc_uart_reva_regs_t*) uart, flags);
|
||||
return MXC_UART_RevA_ClearFlags((mxc_uart_reva_regs_t *)uart, flags);
|
||||
}
|
||||
|
||||
int MXC_UART_EnableInt (mxc_uart_regs_t* uart, unsigned int mask)
|
||||
int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int mask)
|
||||
{
|
||||
return MXC_UART_RevA_EnableInt ((mxc_uart_reva_regs_t*) uart, mask);
|
||||
return MXC_UART_RevA_EnableInt((mxc_uart_reva_regs_t *)uart, mask);
|
||||
}
|
||||
|
||||
int MXC_UART_DisableInt (mxc_uart_regs_t* uart, unsigned int mask)
|
||||
int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int mask)
|
||||
{
|
||||
return MXC_UART_RevA_DisableInt ((mxc_uart_reva_regs_t*) uart, mask);
|
||||
return MXC_UART_RevA_DisableInt((mxc_uart_reva_regs_t *)uart, mask);
|
||||
}
|
||||
|
||||
unsigned int MXC_UART_GetStatus (mxc_uart_regs_t* uart)
|
||||
unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_GetStatus ((mxc_uart_reva_regs_t*) uart);
|
||||
return MXC_UART_RevA_GetStatus((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_Busy(mxc_uart_regs_t* uart)
|
||||
int MXC_UART_Busy(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_Busy((mxc_uart_reva_regs_t*) uart);
|
||||
return MXC_UART_RevA_Busy((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_Transaction (mxc_uart_req_t* req)
|
||||
int MXC_UART_Transaction(mxc_uart_req_t *req)
|
||||
{
|
||||
return MXC_UART_RevA_Transaction ((mxc_uart_reva_req_t*) req);
|
||||
return MXC_UART_RevA_Transaction((mxc_uart_reva_req_t *)req);
|
||||
}
|
||||
|
||||
int MXC_UART_TransactionAsync (mxc_uart_req_t* req)
|
||||
int MXC_UART_TransactionAsync(mxc_uart_req_t *req)
|
||||
{
|
||||
return MXC_UART_RevA_TransactionAsync ((mxc_uart_reva_req_t*) req);
|
||||
return MXC_UART_RevA_TransactionAsync((mxc_uart_reva_req_t *)req);
|
||||
}
|
||||
|
||||
int MXC_UART_TransactionDMA (mxc_uart_req_t* req)
|
||||
int MXC_UART_TransactionDMA(mxc_uart_req_t *req)
|
||||
{
|
||||
return MXC_UART_RevA_TransactionDMA ((mxc_uart_reva_req_t*) req, MXC_DMA);
|
||||
return MXC_UART_RevA_TransactionDMA((mxc_uart_reva_req_t *)req, MXC_DMA);
|
||||
}
|
||||
|
||||
int MXC_UART_AbortAsync (mxc_uart_regs_t* uart)
|
||||
int MXC_UART_AbortAsync(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_AbortAsync ((mxc_uart_reva_regs_t*) uart);
|
||||
return MXC_UART_RevA_AbortAsync((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_AsyncHandler (mxc_uart_regs_t* uart)
|
||||
int MXC_UART_TxAbortAsync(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_AsyncHandler ((mxc_uart_reva_regs_t*) uart);
|
||||
return MXC_UART_RevA_TxAbortAsync((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_RxAbortAsync(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_RxAbortAsync((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart)
|
||||
{
|
||||
return MXC_UART_RevA_AsyncHandler((mxc_uart_reva_regs_t *)uart);
|
||||
}
|
||||
|
||||
uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req)
|
||||
{
|
||||
return req->txCnt;
|
||||
}
|
||||
|
||||
uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t *req)
|
||||
{
|
||||
return req->rxCnt;
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,5 +1,5 @@
|
|||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,7 +29,10 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_REVA_H_
|
||||
#define LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_REVA_H_
|
||||
|
||||
#include "mxc_device.h"
|
||||
#include "mxc_assert.h"
|
||||
|
|
@ -40,61 +43,73 @@
|
|||
typedef struct _mxc_uart_reva_req_t mxc_uart_reva_req_t;
|
||||
|
||||
struct _mxc_uart_reva_req_t {
|
||||
mxc_uart_reva_regs_t* uart;
|
||||
uint8_t *txData;
|
||||
uint8_t *rxData;
|
||||
uint32_t txLen;
|
||||
uint32_t rxLen;
|
||||
uint32_t txCnt;
|
||||
uint32_t rxCnt;
|
||||
mxc_uart_reva_regs_t *uart;
|
||||
uint8_t *txData;
|
||||
uint8_t *rxData;
|
||||
uint32_t txLen;
|
||||
uint32_t rxLen;
|
||||
uint32_t txCnt;
|
||||
uint32_t rxCnt;
|
||||
mxc_uart_complete_cb_t callback;
|
||||
};
|
||||
|
||||
int MXC_UART_RevA_Init (mxc_uart_reva_regs_t* uart, unsigned int baud);
|
||||
int MXC_UART_RevA_Shutdown (mxc_uart_reva_regs_t* uart);
|
||||
int MXC_UART_RevA_ReadyForSleep (mxc_uart_reva_regs_t* uart);
|
||||
int MXC_UART_RevA_SetFrequency (mxc_uart_reva_regs_t* uart, unsigned int baud);
|
||||
int MXC_UART_RevA_GetFrequency (mxc_uart_reva_regs_t* uart);
|
||||
int MXC_UART_RevA_SetDataSize (mxc_uart_reva_regs_t* uart, int dataSize);
|
||||
int MXC_UART_RevA_SetStopBits (mxc_uart_reva_regs_t* uart, mxc_uart_stop_t stopBits);
|
||||
int MXC_UART_RevA_SetParity (mxc_uart_reva_regs_t* uart, mxc_uart_parity_t parity);
|
||||
int MXC_UART_RevA_SetFlowCtrl (mxc_uart_reva_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold);
|
||||
int MXC_UART_RevA_SetClockSource (mxc_uart_reva_regs_t* uart, int usePCLK);
|
||||
int MXC_UART_RevA_SetNullModem (mxc_uart_reva_regs_t* uart, int nullModem);
|
||||
int MXC_UART_RevA_SendBreak (mxc_uart_reva_regs_t* uart);
|
||||
int MXC_UART_RevA_GetActive (mxc_uart_reva_regs_t* uart);
|
||||
int MXC_UART_RevA_AbortTransmission (mxc_uart_reva_regs_t* uart);
|
||||
int MXC_UART_RevA_ReadCharacterRaw (mxc_uart_reva_regs_t* uart);
|
||||
int MXC_UART_RevA_WriteCharacterRaw (mxc_uart_reva_regs_t* uart, uint8_t character);
|
||||
int MXC_UART_RevA_Read (mxc_uart_reva_regs_t* uart, uint8_t* buffer, int* len);
|
||||
int MXC_UART_RevA_Write (mxc_uart_reva_regs_t* uart, uint8_t* byte, int* len);
|
||||
unsigned int MXC_UART_RevA_ReadRXFIFO (mxc_uart_reva_regs_t* uart, unsigned char* bytes,
|
||||
int MXC_UART_RevA_Init(mxc_uart_reva_regs_t *uart, unsigned int baud);
|
||||
int MXC_UART_RevA_Shutdown(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_ReadyForSleep(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_SetFrequency(mxc_uart_reva_regs_t *uart, unsigned int baud);
|
||||
int MXC_UART_RevA_GetFrequency(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_SetDataSize(mxc_uart_reva_regs_t *uart, int dataSize);
|
||||
int MXC_UART_RevA_SetStopBits(mxc_uart_reva_regs_t *uart, mxc_uart_stop_t stopBits);
|
||||
int MXC_UART_RevA_SetParity(mxc_uart_reva_regs_t *uart, mxc_uart_parity_t parity);
|
||||
int MXC_UART_RevA_SetFlowCtrl(mxc_uart_reva_regs_t *uart, mxc_uart_flow_t flowCtrl,
|
||||
int rtsThreshold);
|
||||
int MXC_UART_RevA_SetClockSource(mxc_uart_reva_regs_t *uart, int usePCLK);
|
||||
int MXC_UART_RevA_SetNullModem(mxc_uart_reva_regs_t *uart, int nullModem);
|
||||
int MXC_UART_RevA_SendBreak(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_GetActive(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_AbortTransmission(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_ReadCharacterRaw(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_WriteCharacterRaw(mxc_uart_reva_regs_t *uart, uint8_t character);
|
||||
int MXC_UART_RevA_Read(mxc_uart_reva_regs_t *uart, uint8_t *buffer, int *len);
|
||||
int MXC_UART_RevA_Write(mxc_uart_reva_regs_t *uart, uint8_t *byte, int *len);
|
||||
unsigned int MXC_UART_RevA_ReadRXFIFO(mxc_uart_reva_regs_t *uart, unsigned char *bytes,
|
||||
unsigned int len);
|
||||
int MXC_UART_RevA_ReadRXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma,
|
||||
unsigned char *bytes, unsigned int len,
|
||||
mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config);
|
||||
unsigned int MXC_UART_RevA_GetRXFIFOAvailable(mxc_uart_reva_regs_t *uart);
|
||||
unsigned int MXC_UART_RevA_WriteTXFIFO(mxc_uart_reva_regs_t *uart, unsigned char *bytes,
|
||||
unsigned int len);
|
||||
int MXC_UART_RevA_ReadRXFIFODMA (mxc_uart_reva_regs_t* uart, mxc_dma_regs_t* dma, unsigned char* bytes,
|
||||
unsigned int len, mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config);
|
||||
unsigned int MXC_UART_RevA_GetRXFIFOAvailable (mxc_uart_reva_regs_t* uart);
|
||||
unsigned int MXC_UART_RevA_WriteTXFIFO (mxc_uart_reva_regs_t* uart, unsigned char* bytes,
|
||||
unsigned int len);
|
||||
unsigned int MXC_UART_RevA_WriteTXFIFODMA (mxc_uart_reva_regs_t* uart, mxc_dma_regs_t* dma, unsigned char* bytes,
|
||||
unsigned int len, mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config);
|
||||
unsigned int MXC_UART_RevA_GetTXFIFOAvailable (mxc_uart_reva_regs_t* uart);
|
||||
int MXC_UART_RevA_ClearRXFIFO (mxc_uart_reva_regs_t* uart);
|
||||
int MXC_UART_RevA_ClearTXFIFO (mxc_uart_reva_regs_t* uart);
|
||||
int MXC_UART_RevA_SetRXThreshold (mxc_uart_reva_regs_t* uart, unsigned int numBytes);
|
||||
unsigned int MXC_UART_RevA_GetRXThreshold (mxc_uart_reva_regs_t* uart);
|
||||
int MXC_UART_RevA_SetTXThreshold (mxc_uart_reva_regs_t* uart, unsigned int numBytes);
|
||||
unsigned int MXC_UART_RevA_GetTXThreshold (mxc_uart_reva_regs_t* uart);
|
||||
unsigned int MXC_UART_RevA_GetFlags (mxc_uart_reva_regs_t* uart);
|
||||
int MXC_UART_RevA_ClearFlags (mxc_uart_reva_regs_t* uart, unsigned int flags);
|
||||
int MXC_UART_RevA_EnableInt (mxc_uart_reva_regs_t* uart, unsigned int mask);
|
||||
int MXC_UART_RevA_DisableInt (mxc_uart_reva_regs_t* uart, unsigned int mask);
|
||||
unsigned int MXC_UART_RevA_GetStatus (mxc_uart_reva_regs_t* uart);
|
||||
int MXC_UART_RevA_Busy(mxc_uart_reva_regs_t* uart);
|
||||
int MXC_UART_RevA_Transaction (mxc_uart_reva_req_t* req);
|
||||
int MXC_UART_RevA_TransactionAsync (mxc_uart_reva_req_t* req);
|
||||
int MXC_UART_RevA_TransactionDMA (mxc_uart_reva_req_t* req, mxc_dma_regs_t* dma);
|
||||
int MXC_UART_RevA_AbortAsync (mxc_uart_reva_regs_t* uart);
|
||||
int MXC_UART_RevA_AsyncHandler (mxc_uart_reva_regs_t* uart);
|
||||
int MXC_UART_RevA_AsyncStop (mxc_uart_reva_regs_t* uart);
|
||||
int MXC_UART_RevA_AsyncCallback (mxc_uart_reva_regs_t* uart, int retVal);
|
||||
void MXC_UART_RevA_DMACallback (int ch, int error);
|
||||
unsigned int MXC_UART_RevA_WriteTXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma,
|
||||
unsigned char *bytes, unsigned int len,
|
||||
mxc_uart_dma_complete_cb_t callback,
|
||||
mxc_dma_config_t config);
|
||||
unsigned int MXC_UART_RevA_GetTXFIFOAvailable(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_ClearRXFIFO(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_ClearTXFIFO(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_SetRXThreshold(mxc_uart_reva_regs_t *uart, unsigned int numBytes);
|
||||
unsigned int MXC_UART_RevA_GetRXThreshold(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_SetTXThreshold(mxc_uart_reva_regs_t *uart, unsigned int numBytes);
|
||||
unsigned int MXC_UART_RevA_GetTXThreshold(mxc_uart_reva_regs_t *uart);
|
||||
unsigned int MXC_UART_RevA_GetFlags(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_ClearFlags(mxc_uart_reva_regs_t *uart, unsigned int flags);
|
||||
int MXC_UART_RevA_EnableInt(mxc_uart_reva_regs_t *uart, unsigned int mask);
|
||||
int MXC_UART_RevA_DisableInt(mxc_uart_reva_regs_t *uart, unsigned int mask);
|
||||
unsigned int MXC_UART_RevA_GetStatus(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_Busy(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_Transaction(mxc_uart_reva_req_t *req);
|
||||
int MXC_UART_RevA_TransactionAsync(mxc_uart_reva_req_t *req);
|
||||
int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma);
|
||||
int MXC_UART_RevA_TxAbortAsync(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_RxAbortAsync(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_AbortAsync(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_AsyncHandler(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_TxAsyncStop(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_RxAsyncStop(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_AsyncStop(mxc_uart_reva_regs_t *uart);
|
||||
int MXC_UART_RevA_AsyncCallback(mxc_uart_reva_regs_t *uart, int retVal);
|
||||
int MXC_UART_RevA_TxAsyncCallback(mxc_uart_reva_regs_t *uart, int retVal);
|
||||
int MXC_UART_RevA_RxAsyncCallback(mxc_uart_reva_regs_t *uart, int retVal);
|
||||
void MXC_UART_RevA_DMACallback(int ch, int error);
|
||||
|
||||
#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_REVA_H_
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
* @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -34,8 +34,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
*************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _UART_REVA_REGS_H_
|
||||
#define _UART_REVA_REGS_H_
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* *****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_device.h"
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* *****************************************************************************
|
||||
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
**************************************************************************** */
|
||||
******************************************************************************/
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_device.h"
|
||||
|
|
@ -42,90 +42,88 @@
|
|||
|
||||
/* **** Functions **** */
|
||||
|
||||
int MXC_WDT_Init (mxc_wdt_regs_t* wdt)
|
||||
int MXC_WDT_Init(mxc_wdt_regs_t *wdt)
|
||||
{
|
||||
if (wdt == MXC_WDT0) {
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int MXC_WDT_Shutdown (mxc_wdt_regs_t* wdt)
|
||||
int MXC_WDT_Shutdown(mxc_wdt_regs_t *wdt)
|
||||
{
|
||||
if (wdt == MXC_WDT0) {
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
void MXC_WDT_SetIntPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_period_t period)
|
||||
void MXC_WDT_SetIntPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_period_t period)
|
||||
{
|
||||
MXC_WDT_RevA_SetIntPeriod ((mxc_wdt_reva_regs_t*) wdt,period);
|
||||
MXC_WDT_RevA_SetIntPeriod((mxc_wdt_reva_regs_t *)wdt, period);
|
||||
}
|
||||
|
||||
void MXC_WDT_SetResetPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_period_t period)
|
||||
void MXC_WDT_SetResetPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_period_t period)
|
||||
{
|
||||
MXC_WDT_RevA_SetResetPeriod ((mxc_wdt_reva_regs_t*) wdt,period);
|
||||
MXC_WDT_RevA_SetResetPeriod((mxc_wdt_reva_regs_t *)wdt, period);
|
||||
}
|
||||
|
||||
void MXC_WDT_Enable (mxc_wdt_regs_t* wdt)
|
||||
void MXC_WDT_Enable(mxc_wdt_regs_t *wdt)
|
||||
{
|
||||
MXC_WDT_RevA_Enable ((mxc_wdt_reva_regs_t*) wdt);
|
||||
MXC_WDT_RevA_Enable((mxc_wdt_reva_regs_t *)wdt);
|
||||
}
|
||||
|
||||
void MXC_WDT_Disable (mxc_wdt_regs_t* wdt)
|
||||
void MXC_WDT_Disable(mxc_wdt_regs_t *wdt)
|
||||
{
|
||||
MXC_WDT_RevA_Disable ((mxc_wdt_reva_regs_t*) wdt);
|
||||
MXC_WDT_RevA_Disable((mxc_wdt_reva_regs_t *)wdt);
|
||||
}
|
||||
|
||||
void MXC_WDT_EnableInt (mxc_wdt_regs_t* wdt)
|
||||
void MXC_WDT_EnableInt(mxc_wdt_regs_t *wdt)
|
||||
{
|
||||
MXC_WDT_RevA_EnableInt ((mxc_wdt_reva_regs_t*) wdt, MXC_WDT_REVA_ENABLE);
|
||||
MXC_WDT_RevA_EnableInt((mxc_wdt_reva_regs_t *)wdt, MXC_WDT_REVA_ENABLE);
|
||||
}
|
||||
|
||||
void MXC_WDT_EnableReset (mxc_wdt_regs_t* wdt)
|
||||
void MXC_WDT_EnableReset(mxc_wdt_regs_t *wdt)
|
||||
{
|
||||
MXC_WDT_RevA_EnableReset ((mxc_wdt_reva_regs_t*) wdt, MXC_WDT_REVA_ENABLE);
|
||||
MXC_WDT_RevA_EnableReset((mxc_wdt_reva_regs_t *)wdt, MXC_WDT_REVA_ENABLE);
|
||||
}
|
||||
|
||||
void MXC_WDT_DisableInt (mxc_wdt_regs_t* wdt)
|
||||
void MXC_WDT_DisableInt(mxc_wdt_regs_t *wdt)
|
||||
{
|
||||
MXC_WDT_RevA_EnableInt ((mxc_wdt_reva_regs_t*) wdt, MXC_WDT_REVA_DISABLE);
|
||||
MXC_WDT_RevA_EnableInt((mxc_wdt_reva_regs_t *)wdt, MXC_WDT_REVA_DISABLE);
|
||||
}
|
||||
|
||||
void MXC_WDT_DisableReset (mxc_wdt_regs_t* wdt)
|
||||
void MXC_WDT_DisableReset(mxc_wdt_regs_t *wdt)
|
||||
{
|
||||
MXC_WDT_RevA_EnableReset ((mxc_wdt_reva_regs_t*) wdt, MXC_WDT_REVA_DISABLE);
|
||||
MXC_WDT_RevA_EnableReset((mxc_wdt_reva_regs_t *)wdt, MXC_WDT_REVA_DISABLE);
|
||||
}
|
||||
|
||||
void MXC_WDT_ResetTimer (mxc_wdt_regs_t* wdt)
|
||||
void MXC_WDT_ResetTimer(mxc_wdt_regs_t *wdt)
|
||||
{
|
||||
MXC_WDT_RevA_ResetTimer ((mxc_wdt_reva_regs_t*) wdt);
|
||||
MXC_WDT_RevA_ResetTimer((mxc_wdt_reva_regs_t *)wdt);
|
||||
}
|
||||
|
||||
int MXC_WDT_GetResetFlag (mxc_wdt_regs_t* wdt)
|
||||
int MXC_WDT_GetResetFlag(mxc_wdt_regs_t *wdt)
|
||||
{
|
||||
return MXC_WDT_RevA_GetResetFlag ((mxc_wdt_reva_regs_t*) wdt);
|
||||
return MXC_WDT_RevA_GetResetFlag((mxc_wdt_reva_regs_t *)wdt);
|
||||
}
|
||||
|
||||
void MXC_WDT_ClearResetFlag (mxc_wdt_regs_t* wdt)
|
||||
void MXC_WDT_ClearResetFlag(mxc_wdt_regs_t *wdt)
|
||||
{
|
||||
MXC_WDT_RevA_ClearResetFlag ((mxc_wdt_reva_regs_t*) wdt);
|
||||
MXC_WDT_RevA_ClearResetFlag((mxc_wdt_reva_regs_t *)wdt);
|
||||
}
|
||||
|
||||
int MXC_WDT_GetIntFlag (mxc_wdt_regs_t* wdt)
|
||||
int MXC_WDT_GetIntFlag(mxc_wdt_regs_t *wdt)
|
||||
{
|
||||
return MXC_WDT_RevA_GetIntFlag ((mxc_wdt_reva_regs_t*) wdt);
|
||||
return MXC_WDT_RevA_GetIntFlag((mxc_wdt_reva_regs_t *)wdt);
|
||||
}
|
||||
|
||||
void MXC_WDT_ClearIntFlag (mxc_wdt_regs_t* wdt)
|
||||
void MXC_WDT_ClearIntFlag(mxc_wdt_regs_t *wdt)
|
||||
{
|
||||
MXC_WDT_RevA_ClearIntFlag ((mxc_wdt_reva_regs_t*) wdt);
|
||||
MXC_WDT_RevA_ClearIntFlag((mxc_wdt_reva_regs_t *)wdt);
|
||||
}
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue