mirror of https://github.com/ARMmbed/mbed-os.git
system_MK20DX256.c 96MHz default set up
Added/changed clock set ups for Teensy3.1.pull/1314/merge
Paul Staron
0xc0170
parent
f2f31c82e1
commit
3ee5d7ac62
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@ -7,7 +7,7 @@
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**
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**
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**
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** Version: rev. 1.0, 2015-08-30
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** Version: rev. 1.0, 2011-12-15
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**
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** Abstract:
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** Provides a system configuration function and a global variable that
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@ -20,7 +20,7 @@
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** mail: support@freescale.com
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**
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** Revisions:
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** - rev. 1.0 (2015-08-30)
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** - rev. 1.0 (2011-12-15)
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** Initial version
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**
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** ###################################################################
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@ -29,7 +29,7 @@
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/**
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* @file MK20DX256
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* @version 1.0
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* @date 2015-08-30
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* @date 2011-12-15
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* @brief Device specific configuration file for MK20DX256 (implementation file)
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*
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* Provides a system configuration function and a global variable that contains
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@ -42,22 +42,20 @@
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#define DISABLE_WDOG 1
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#define CLOCK_SETUP 3
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#define CLOCK_SETUP 1
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/* Predefined clock setups
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0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
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Reference clock source for MCG module is the slow internal clock source 32.768kHz
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Core clock = 41.94MHz, BusClock = 41.94MHz
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This works on Teensy3.1
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Works on Teensy3.1 but no USB support
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1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
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Reference clock source for MCG module is an external crystal 8MHz
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Core clock = 48MHz, BusClock = 48MHz
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2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
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Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
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Core clock = 8MHz, BusClock = 8MHz
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3 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
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Reference clock source for MCG module is an external crystal 16MHz
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Core clock = 72MHz, BusClock = 36MHz, FlashClock 24MHz
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This is the default Teensy3.1 72Mhz set up
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Core clock = 96MHz, BusClock = 48MHz
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Default high speed Teensy3.1 96Mhz set up
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2 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
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Reference clock source for MCG module is an external crystal 16MHz
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Core clock = 72MHz, BusClock = 36MHz
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Alternative standard 'slower' Teensy3.1 72Mhz set up
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*/
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/*----------------------------------------------------------------------------
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@ -70,24 +68,18 @@
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#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
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#define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
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#elif (CLOCK_SETUP == 1)
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#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
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#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
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#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
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#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
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#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
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#elif (CLOCK_SETUP == 2)
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#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
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#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
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#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
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#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
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#define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
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#elif (CLOCK_SETUP == 3)
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#define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */
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#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
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#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
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#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
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#define DEFAULT_SYSTEM_CLOCK 72000000u /* Default System clock value */
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#endif
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#define DEFAULT_SYSTEM_CLOCK 96000000u /* Default System clock value */
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#elif (CLOCK_SETUP == 2)
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#define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */
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#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
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#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
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#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
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#define DEFAULT_SYSTEM_CLOCK 72000000u /* Default System clock value */
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#endif /* (CLOCK_SETUP == 2) */
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/* ----------------------------------------------------------------------------
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@ -130,64 +122,43 @@ void SystemInit (void) {
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while((MCG->S & 0x0Cu) != 0x00u) { } /* Wait until output of the FLL is selected */
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#elif (CLOCK_SETUP == 1)
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/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 48MHz cpu, 48MHz system, 24MHz flash*/
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SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
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/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=3 Set Prescalers 96MHz cpu, 48MHz bus, 24MHz flash*/
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SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3);
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/* SIM->CLKDIV2: USBDIV=2, Divide 96MHz system clock for USB 48MHz */
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SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1);
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/* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/
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OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK;
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/* Switch to FBE Mode */
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/* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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OSC0->CR = (uint8_t)0x00u;
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/* MCG->C7: OSCSEL=0 */
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MCG->C7 = (uint8_t)0x00u;
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/* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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MCG->C2 = MCG_C2_RANGE0(2);
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MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
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//MCG->C2 = (uint8_t)0x24u;
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/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
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/* MCG->C4: DMX32=0,DRST_DRS=0 */
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MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
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/* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
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MCG->C5 = MCG_C5_PRDIV0(3);
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/* MCG->C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
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MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
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/* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=7 */
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MCG->C5 = MCG_C5_PRDIV0(7);
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/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
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MCG->C6 = (uint8_t)0x00u;
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while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
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while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
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/* Switch to PBE Mode */
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/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
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MCG->C5 = MCG_C5_PRDIV0(3);
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/* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */
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MCG->C6 = MCG_C6_PLLS_MASK;
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/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=5 */
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MCG->C5 = MCG_C5_PRDIV0(3); // config PLL input for 16 MHz Crystal / 4 = 4 MHz
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/* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 */
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MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0);// config PLL for 96 MHz output
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while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */
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while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
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/* Switch to PEE Mode */
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/* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
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/* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;
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while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */
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while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
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while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
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#elif (CLOCK_SETUP == 2)
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/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 8MHz cpu, 8MHz system, 8MHz flash*/
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SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
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/* Switch to FBE Mode */
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/* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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OSC0->CR = (uint8_t)0x00u;
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/* MCG->C7: OSCSEL=0 */
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MCG->C7 = (uint8_t)0x00u;
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/* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
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/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
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/* MCG->C4: DMX32=0,DRST_DRS=0 */
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MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
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/* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
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MCG->C5 = (uint8_t)0x00u;
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/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
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MCG->C6 = (uint8_t)0x00u;
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while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
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while((MCG->S & 0x0CU) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
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/* Switch to BLPE Mode */
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/* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
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#elif (CLOCK_SETUP == 3)
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/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 72MHz cpu, 36MHz system, 24MHz flash*/
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/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 72MHz cpu, 36MHz bus, 24MHz flash*/
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SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(2);
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/* SIM->CLKDIV2: USBDIV=2,USBFRAC=1 Divide 72MHz system clock for USB 48MHz */
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SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC_MASK;
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@ -220,7 +191,7 @@ void SystemInit (void) {
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/* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;
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while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */
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while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
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while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
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#endif /* (CLOCK_SETUP) */
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}
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