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Remove LPC1549 target

pull/12864/head
MarceloSalazar 2020-04-21 09:10:29 +01:00 committed by Marcelo Salazar
parent 9167b2d1d6
commit 3ed5491ae5
38 changed files with 6 additions and 6704 deletions
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60
targets/TARGET_NXP/TARGET_LPC15XX/PeripheralNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2,
ADC0_3,
ADC0_4,
ADC0_5,
ADC0_6,
ADC0_7,
ADC0_8,
ADC0_9,
ADC0_10,
ADC0_11,
ADC1_0,
ADC1_1,
ADC1_2,
ADC1_3,
ADC1_4,
ADC1_5,
ADC1_6,
ADC1_7,
ADC1_8,
ADC1_9,
ADC1_10,
ADC1_11,
} ADCName;
typedef enum {
DAC0_0 = 0,
} DACName;
#ifdef __cplusplus
}
#endif
#endif

103
targets/TARGET_NXP/TARGET_LPC15XX/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
// LPC Pin Names
P0_0 = 0,
P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12,
LED_RED = P0_25,
LED_GREEN = P0_3,
LED_BLUE = P1_1,
// mbed original LED naming
LED1 = LED_RED,
LED2 = LED_GREEN,
LED3 = LED_BLUE,
LED4 = LED_BLUE,
// Serial to USB pins
USBTX = P0_18,
USBRX = P0_13,
// Arduino Shield Receptacles Names
D0 = P0_13,
D1 = P0_18,
D2 = P0_29,
D3 = P0_9,
D4 = P0_10,
D5 = P0_16, // same port as D13
D6 = P1_3,
D7 = P0_0,
D8 = P0_24,
D9 = P1_0,
D10= P0_27,
D11= P0_28,
D12= P0_12,
D13= P0_16, // same port as D5
D14= P0_23,
D15= P0_22,
A0 = P0_8,
A1 = P0_7,
A2 = P0_6,
A3 = P0_5,
A4 = P0_23, // same port as SDA
A5 = P0_22, // same port as SCL
SDA= P0_23, // same port as A4
SCL= P0_22, // same port as A5
// Not connected
NC = (int)0xFFFFFFFF,
} PinName;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
typedef struct {
unsigned char n;
unsigned char offset;
} SWM_Map;
#ifdef __cplusplus
}
#endif
#endif

32
targets/TARGET_NXP/TARGET_LPC15XX/PortNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
Port0 = 0,
Port1 = 1,
Port2 = 2
} PortName;
#ifdef __cplusplus
}
#endif
#endif

159
targets/TARGET_NXP/TARGET_LPC15XX/analogin_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogin_api.h"
#include "cmsis.h"
#include "pinmap.h"
#define ANALOGIN_MEDIAN_FILTER 1
#define ADC_10BIT_RANGE 0x3FF
#define ADC_12BIT_RANGE 0xFFF
#define ADC_RANGE ADC_12BIT_RANGE
static const PinMap PinMap_ADC[] = {
{P0_8 , ADC0_0, 0},
{P0_7 , ADC0_1, 0},
{P0_6 , ADC0_2, 0},
{P0_5 , ADC0_3, 0},
{P0_4 , ADC0_4, 0},
{P0_3 , ADC0_5, 0},
{P0_2 , ADC0_6, 0},
{P0_1 , ADC0_7, 0},
{P1_0 , ADC0_8, 0},
{P0_31, ADC0_9, 0},
{P0_0 , ADC0_10,0},
{P0_30, ADC0_11,0},
{P1_1 , ADC1_0, 0},
{P0_9 , ADC1_1, 0},
{P0_10, ADC1_2, 0},
{P0_11, ADC1_3, 0},
{P1_2 , ADC1_4, 0},
{P1_3 , ADC1_5, 0},
{P0_13, ADC1_6, 0},
{P0_14, ADC1_7, 0},
{P0_15, ADC1_8, 0},
{P0_16, ADC1_9, 0},
{P1_4 , ADC1_10,0},
{P1_5 , ADC1_11,0},
};
void analogin_init(analogin_t *obj, PinName pin) {
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
uint32_t port = (pin >> 5);
// enable clock for GPIOx
LPC_SYSCON->SYSAHBCLKCTRL0 |= (1UL << (14 + port));
// pin enable
LPC_SWM->PINENABLE0 &= ~(1UL << obj->adc);
// configure GPIO as input
LPC_GPIO_PORT->DIR[port] &= ~(1UL << (pin & 0x1F));
// power up ADC
if (obj->adc < ADC1_0)
{
// ADC0
LPC_SYSCON->PDRUNCFG &= ~(1 << 10);
LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 27);
}
else {
// ADC1
LPC_SYSCON->PDRUNCFG &= ~(1 << 11);
LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 28);
}
__IO LPC_ADC0_Type *adc_reg = (obj->adc < ADC1_0) ? (__IO LPC_ADC0_Type*)(LPC_ADC0) : (__IO LPC_ADC0_Type*)(LPC_ADC1);
// determine the system clock divider for a 500kHz ADC clock during calibration
uint32_t clkdiv = (SystemCoreClock / 500000) - 1;
// perform a self-calibration
adc_reg->CTRL = (1UL << 30) | (clkdiv & 0xFF);
while ((adc_reg->CTRL & (1UL << 30)) != 0);
// Sampling clock: SystemClock divided by 1
adc_reg->CTRL = 0;
}
static inline uint32_t adc_read(analogin_t *obj) {
uint32_t channels;
__IO LPC_ADC0_Type *adc_reg = (obj->adc < ADC1_0) ? (__IO LPC_ADC0_Type*)(LPC_ADC0) : (__IO LPC_ADC0_Type*)(LPC_ADC1);
if (obj->adc >= ADC1_0)
channels = ((obj->adc - ADC1_0) & 0x1F);
else
channels = (obj->adc & 0x1F);
// select channel
adc_reg->SEQA_CTRL &= ~(0xFFF);
adc_reg->SEQA_CTRL |= (1UL << channels);
// start conversion and sequence enable
adc_reg->SEQA_CTRL |= ((1UL << 26) | (1UL << 31));
// Repeatedly get the sample data until DONE bit
volatile uint32_t data;
do {
data = adc_reg->SEQA_GDAT;
} while ((data & (1UL << 31)) == 0);
// Stop conversion
adc_reg->SEQA_CTRL &= ~(1UL << 31);
return ((data >> 4) & ADC_RANGE);
}
static inline void order(uint32_t *a, uint32_t *b) {
if (*a > *b) {
uint32_t t = *a;
*a = *b;
*b = t;
}
}
static inline uint32_t adc_read_u32(analogin_t *obj) {
uint32_t value;
#if ANALOGIN_MEDIAN_FILTER
uint32_t v1 = adc_read(obj);
uint32_t v2 = adc_read(obj);
uint32_t v3 = adc_read(obj);
order(&v1, &v2);
order(&v2, &v3);
order(&v1, &v2);
value = v2;
#else
value = adc_read(obj);
#endif
return value;
}
uint16_t analogin_read_u16(analogin_t *obj) {
uint32_t value = adc_read_u32(obj);
return (value << 4) | ((value >> 8) & 0x000F); // 12 bit
}
float analogin_read(analogin_t *obj) {
uint32_t value = adc_read_u32(obj);
return (float)value * (1.0f / (float)ADC_RANGE);
}
const PinMap *analogin_pinmap()
{
return PinMap_ADC;
}

82
targets/TARGET_NXP/TARGET_LPC15XX/analogout_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogout_api.h"
#include "cmsis.h"
#include "pinmap.h"
static const PinMap PinMap_DAC[] = {
{P0_12, 0, 0},
{NC, NC, 0}
};
void analogout_init(dac_t *obj, PinName pin) {
MBED_ASSERT(pin == P0_12);
LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 29);
LPC_SYSCON->PDRUNCFG &= ~(1 << 12);
LPC_IOCON->PIO0_12 = 0;
LPC_SWM->PINENABLE0 &= ~(1 << 24);
LPC_DAC->CTRL = 0;
analogout_write_u16(obj, 0);
}
void analogout_free(dac_t *obj)
{
LPC_SYSCON->SYSAHBCLKCTRL0 &= ~(1 << 29);
LPC_SWM->PINENABLE0 |= (1 << 24);
}
static inline void dac_write(int value) {
value &= 0xFFF; // 12-bit
// Set the DAC output
LPC_DAC->VAL = (value << 4);
}
static inline int dac_read() {
return ((LPC_DAC->VAL >> 4) & 0xFFF);
}
void analogout_write(dac_t *obj, float value) {
if (value < 0.0f) {
dac_write(0);
} else if (value > 1.0f) {
dac_write(0xFFF);
} else {
dac_write((uint32_t)(value * (float)0xFFF));
}
}
void analogout_write_u16(dac_t *obj, uint16_t value) {
dac_write(value);
}
float analogout_read(dac_t *obj) {
uint32_t value = dac_read();
return (float)value * (1.0f / (float)0xFFF);
}
uint16_t analogout_read_u16(dac_t *obj) {
return (uint16_t)dac_read();
}
const PinMap *analogout_pinmap()
{
return PinMap_DAC;
}

721
targets/TARGET_NXP/TARGET_LPC15XX/can_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "can_api.h"
#include "cmsis.h"
#include "mbed_error.h"
#include <math.h>
#include <string.h>
/* Handy defines */
#define RX_MSG_OBJ_COUNT 31
#define TX_MSG_OBJ_COUNT 1
#define DLC_MAX 8
#define ID_STD_MASK 0x07FF
#define ID_EXT_MASK 0x1FFFFFFF
#define DLC_MASK 0x0F
#define CANIFn_ARB2_DIR (1UL << 13)
#define CANIFn_ARB2_XTD (1UL << 14)
#define CANIFn_ARB2_MSGVAL (1UL << 15)
#define CANIFn_MSK2_MXTD (1UL << 15)
#define CANIFn_MSK2_MDIR (1UL << 14)
#define CANIFn_MCTRL_EOB (1UL << 7)
#define CANIFn_MCTRL_TXRQST (1UL << 8)
#define CANIFn_MCTRL_RMTEN (1UL << 9)
#define CANIFn_MCTRL_RXIE (1UL << 10)
#define CANIFn_MCTRL_TXIE (1UL << 11)
#define CANIFn_MCTRL_UMASK (1UL << 12)
#define CANIFn_MCTRL_INTPND (1UL << 13)
#define CANIFn_MCTRL_MSGLST (1UL << 14)
#define CANIFn_MCTRL_NEWDAT (1UL << 15)
#define CANIFn_CMDMSK_DATA_B (1UL << 0)
#define CANIFn_CMDMSK_DATA_A (1UL << 1)
#define CANIFn_CMDMSK_TXRQST (1UL << 2)
#define CANIFn_CMDMSK_NEWDAT (1UL << 2)
#define CANIFn_CMDMSK_CLRINTPND (1UL << 3)
#define CANIFn_CMDMSK_CTRL (1UL << 4)
#define CANIFn_CMDMSK_ARB (1UL << 5)
#define CANIFn_CMDMSK_MASK (1UL << 6)
#define CANIFn_CMDMSK_WR (1UL << 7)
#define CANIFn_CMDMSK_RD (0UL << 7)
#define CANIFn_CMDREQ_BUSY (1UL << 15)
#define CANSTAT_TXOK (1 << 3) // Transmitted a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller.
#define CANSTAT_RXOK (1 << 4) // Received a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller.
#define CANSTAT_EPASS (1 << 5) // Error passive
#define CANSTAT_EWARN (1 << 6) // Warning status
#define CANSTAT_BOFF (1 << 7) // Busoff status
#define CANCNTL_INIT (1 << 0) // Initialization
#define CANCNTL_IE (1 << 1) // Module interrupt enable
#define CANCNTL_SIE (1 << 2) // Status change interrupt enable
#define CANCNTL_EIE (1 << 3) // Error interrupt enable
#define CANCNTL_DAR (1 << 5) // Disable automatic retransmission
#define CANCNTL_CCE (1 << 6) // Configuration change enable
#define CANCNTL_TEST (1 << 7) // Test mode enable
#define CANTEST_BASIC (1 << 2) // Basic mode
#define CANTEST_SILENT (1 << 3) // Silent mode
#define CANTEST_LBACK (1 << 4) // Loop back mode
#define CANTEST_TX_MASK 0x0060 // Control of CAN_TXD pins
#define CANTEST_TX_SHIFT 5
#define CANTEST_RX (1 << 7) // Monitors the actual value of the CAN_RXD pin.
static uint32_t can_irq_id = 0;
static can_irq_handler irq_handler;
#define IRQ_ENABLE_TX (1 << 0)
#define IRQ_ENABLE_RX (1 << 1)
#define IRQ_ENABLE_EW (1 << 2)
#define IRQ_ENABLE_EP (1 << 3)
#define IRQ_ENABLE_BE (1 << 4)
#define IRQ_ENABLE_STATUS (IRQ_ENABLE_TX | IRQ_ENABLE_RX)
#define IRQ_ENABLE_ERROR (IRQ_ENABLE_EW | IRQ_ENABLE_EP | IRQ_ENABLE_BE)
#define IRQ_ENABLE_ANY (IRQ_ENABLE_STATUS | IRQ_ENABLE_ERROR)
static uint32_t enabled_irqs = 0;
// Pinmap used for testing only
static const PinMap PinMap_CAN_testing[] = {
{P0_0, 0, 0},
{P0_1, 0, 0},
{P0_2, 0, 0},
{P0_3, 0, 0},
{P0_4, 0, 0},
{P0_5, 0, 0},
{P0_6, 0, 0},
{P0_7, 0, 0},
{P0_8, 0, 0},
{P0_9, 0, 0},
{P0_10, 0, 0},
{P0_11, 0, 0},
{P0_12, 0, 0},
{P0_13, 0, 0},
{P0_14, 0, 0},
{P0_15, 0, 0},
{P0_16, 0, 0},
{P0_17, 0, 0},
{P0_18, 0, 0},
{P0_19, 0, 0},
{P0_20, 0, 0},
{P0_21, 0, 0},
{P0_22, 0, 0},
{P0_23, 0, 0},
{P0_24, 0, 0},
{P0_25, 0, 0},
{P0_26, 0, 0},
{P0_27, 0, 0},
{P0_28, 0, 0},
{P0_29, 0, 0},
{P0_30, 0, 0},
{P0_31, 0, 0},
{P1_0, 0, 0},
{P1_1, 0, 0},
{P1_2, 0, 0},
{P1_3, 0, 0},
{P1_4, 0, 0},
{P1_5, 0, 0},
{P1_6, 0, 0},
{P1_7, 0, 0},
{P1_8, 0, 0},
{P1_9, 0, 0},
{P1_10, 0, 0},
{P1_11, 0, 0},
{P1_12, 0, 0},
{P1_13, 0, 0},
{P1_14, 0, 0},
{P1_15, 0, 0},
{P1_16, 0, 0},
{P1_17, 0, 0},
{P1_18, 0, 0},
{P1_19, 0, 0},
{P1_20, 0, 0},
{P1_21, 0, 0},
{P1_22, 0, 0},
{P1_23, 0, 0},
{P1_24, 0, 0},
{P1_25, 0, 0},
{P1_26, 0, 0},
{P1_27, 0, 0},
{P1_28, 0, 0},
{P1_29, 0, 0},
{P1_30, 0, 0},
{P1_31, 0, 0},
{P2_0, 0, 0},
{P2_1, 0, 0},
{P2_2, 0, 0},
{P2_3, 0, 0},
{P2_4, 0, 0},
{P2_5, 0, 0},
{P2_6, 0, 0},
{P2_7, 0, 0},
{P2_8, 0, 0},
{P2_9, 0, 0},
{P2_10, 0, 0},
{P2_11, 0, 0},
{P2_12, 0, 0},
{NC, NC, 0}
};
static inline void can_disable(can_t *obj) {
LPC_C_CAN0->CANCNTL |= 0x1;
}
static inline void can_enable(can_t *obj) {
if (LPC_C_CAN0->CANCNTL & 0x1) {
LPC_C_CAN0->CANCNTL &= ~(0x1);
}
}
int can_mode(can_t *obj, CanMode mode) {
int success = 0;
switch (mode) {
case MODE_RESET:
LPC_C_CAN0->CANCNTL &=~CANCNTL_TEST;
can_disable(obj);
success = 1;
break;
case MODE_NORMAL:
LPC_C_CAN0->CANCNTL &=~CANCNTL_TEST;
can_enable(obj);
success = 1;
break;
case MODE_SILENT:
LPC_C_CAN0->CANCNTL |= CANCNTL_TEST;
LPC_C_CAN0->CANTEST |= CANTEST_SILENT;
LPC_C_CAN0->CANTEST &=~ CANTEST_LBACK;
success = 1;
break;
case MODE_TEST_LOCAL:
LPC_C_CAN0->CANCNTL |= CANCNTL_TEST;
LPC_C_CAN0->CANTEST &=~CANTEST_SILENT;
LPC_C_CAN0->CANTEST |= CANTEST_LBACK;
success = 1;
break;
case MODE_TEST_SILENT:
LPC_C_CAN0->CANCNTL |= CANCNTL_TEST;
LPC_C_CAN0->CANTEST |= (CANTEST_LBACK | CANTEST_SILENT);
success = 1;
break;
case MODE_TEST_GLOBAL:
default:
success = 0;
break;
}
return success;
}
int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
uint16_t i;
// Find first free message object
if (handle == 0) {
uint32_t msgval = LPC_C_CAN0->CANMSGV1 | (LPC_C_CAN0->CANMSGV2 << 16);
// Find first free messagebox
for (i = 0; i < 32; i++) {
if ((msgval & (1 << i)) == 0) {
handle = i+1;
break;
}
}
}
if (handle > 0 && handle <= 32) {
if (format == CANExtended) {
// Mark message valid, Direction = TX, Extended Frame, Set Identifier and mask everything
LPC_C_CAN0->CANIF1_ARB1 = (id & 0xFFFF);
LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | CANIFn_ARB2_XTD | ((id >> 16) & 0x1FFF);
LPC_C_CAN0->CANIF1_MSK1 = (mask & 0xFFFF);
LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MXTD /*| CANIFn_MSK2_MDIR*/ | ((mask >> 16) & 0x1FFF);
} else {
// Mark message valid, Direction = TX, Set Identifier and mask everything
LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | ((id << 2) & 0x1FFF);
LPC_C_CAN0->CANIF1_MSK2 = /*CANIFn_MSK2_MDIR |*/ ((mask << 2) & 0x1FFF);
}
// Use mask, single message object and set DLC
LPC_C_CAN0->CANIF1_MCTRL = CANIFn_MCTRL_UMASK | CANIFn_MCTRL_EOB | (DLC_MAX & 0xF);
// Transfer all fields to message object
LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL;
// Start Transfer to given message number
LPC_C_CAN0->CANIF1_CMDREQ = (handle & 0x3F);
// Wait until transfer to message ram complete - TODO: maybe not block??
while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
}
return handle;
}
static inline void can_irq() {
uint32_t intid = LPC_C_CAN0->CANINT & 0xFFFF;
if (intid == 0x8000) {
uint32_t status = LPC_C_CAN0->CANSTAT;
// Note that since it's impossible to tell which specific status caused
// the interrupt to fire, this just fires them all.
// In particular, EWARN is not mutually exclusive with the others and
// may fire multiple times with other status transitions, including
// transmit and receive completion (if enabled). Ignoring EWARN with a
// priority system (i.e. blocking EWARN interrupts if EPASS or BOFF is
// set) may discard some EWARN interrupts.
if (status & CANSTAT_BOFF) {
if (enabled_irqs & IRQ_ENABLE_BE) {
irq_handler(can_irq_id, IRQ_BUS);
}
}
if (status & CANSTAT_EPASS) {
if (enabled_irqs & IRQ_ENABLE_EP) {
irq_handler(can_irq_id, IRQ_PASSIVE);
}
}
if (status & CANSTAT_EWARN) {
if (enabled_irqs & IRQ_ENABLE_EW) {
irq_handler(can_irq_id, IRQ_ERROR);
}
}
if ((status & CANSTAT_RXOK) != 0) {
LPC_C_CAN0->CANSTAT &= ~CANSTAT_RXOK;
irq_handler(can_irq_id, IRQ_RX);
}
if ((status & CANSTAT_TXOK) != 0) {
LPC_C_CAN0->CANSTAT &= ~CANSTAT_TXOK;
irq_handler(can_irq_id, IRQ_TX);
}
}
}
// Register CAN object's irq handler
void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
irq_handler = handler;
can_irq_id = id;
}
// Unregister CAN object's irq handler
void can_irq_free(can_t *obj) {
LPC_C_CAN0->CANCNTL &= ~(1UL << 1); // Disable Interrupts :)
can_irq_id = 0;
NVIC_DisableIRQ(C_CAN0_IRQn);
}
// Clear or set a irq
void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
uint32_t mask_enable;
switch (type) {
case IRQ_RX:
mask_enable = IRQ_ENABLE_RX;
break;
case IRQ_TX:
mask_enable = IRQ_ENABLE_TX;
break;
case IRQ_BUS:
mask_enable = IRQ_ENABLE_BE;
break;
case IRQ_PASSIVE:
mask_enable = IRQ_ENABLE_EP;
break;
case IRQ_ERROR:
mask_enable = IRQ_ENABLE_EW;
break;
default:
return;
}
if (enable) {
enabled_irqs = enabled_irqs | mask_enable;
} else {
enabled_irqs = enabled_irqs & ~mask_enable;
}
// Put CAN in Reset Mode and enable interrupt
can_disable(obj);
if (!(enabled_irqs & IRQ_ENABLE_ANY)) {
LPC_C_CAN0->CANCNTL &= ~(1UL << 1 | 1UL << 2 | 1UL << 3);
} else {
LPC_C_CAN0->CANCNTL |= 1UL << 1;
// Use status interrupts instead of message interrupts to avoid
// stomping over potential filter configurations.
if (enabled_irqs & IRQ_ENABLE_STATUS) {
LPC_C_CAN0->CANCNTL |= 1UL << 2;
} else {
LPC_C_CAN0->CANCNTL &= ~(1UL << 2);
}
if (enabled_irqs & IRQ_ENABLE_ERROR) {
LPC_C_CAN0->CANCNTL |= 1UL << 3;
} else {
LPC_C_CAN0->CANCNTL &= ~(1UL << 3);
}
}
// Take it out of reset...
can_enable(obj);
// Enable NVIC if at least 1 interrupt is active
NVIC_SetVector(C_CAN0_IRQn, (uint32_t) &can_irq);
NVIC_EnableIRQ(C_CAN0_IRQn);
}
// This table has the sampling points as close to 75% as possible. The first
// value is TSEG1, the second TSEG2.
static const int timing_pts[23][2] = {
{0x0, 0x0}, // 2, 50%
{0x1, 0x0}, // 3, 67%
{0x2, 0x0}, // 4, 75%
{0x3, 0x0}, // 5, 80%
{0x3, 0x1}, // 6, 67%
{0x4, 0x1}, // 7, 71%
{0x5, 0x1}, // 8, 75%
{0x6, 0x1}, // 9, 78%
{0x6, 0x2}, // 10, 70%
{0x7, 0x2}, // 11, 73%
{0x8, 0x2}, // 12, 75%
{0x9, 0x2}, // 13, 77%
{0x9, 0x3}, // 14, 71%
{0xA, 0x3}, // 15, 73%
{0xB, 0x3}, // 16, 75%
{0xC, 0x3}, // 17, 76%
{0xD, 0x3}, // 18, 78%
{0xD, 0x4}, // 19, 74%
{0xE, 0x4}, // 20, 75%
{0xF, 0x4}, // 21, 76%
{0xF, 0x5}, // 22, 73%
{0xF, 0x6}, // 23, 70%
{0xF, 0x7}, // 24, 67%
};
static unsigned int can_speed(unsigned int sclk, unsigned int cclk, unsigned char psjw) {
uint32_t btr;
uint32_t clkdiv = 1;
uint16_t brp = 0;
uint32_t calcbit;
uint32_t bitwidth;
int hit = 0;
int bits = 0;
bitwidth = sclk / cclk;
brp = bitwidth / 0x18;
while ((!hit) && (brp < bitwidth / 4)) {
brp++;
for (bits = 22; bits > 0; bits--) {
calcbit = (bits + 3) * (brp + 1);
if (calcbit == bitwidth) {
hit = 1;
break;
}
}
}
clkdiv = clkdiv - 1;
if (hit) {
btr = (timing_pts[bits][1] & 0x7) << 12
| (timing_pts[bits][0] & 0xf) << 8
| (psjw & 0x3) << 6
| (brp & 0x3F);
btr = btr | (clkdiv << 16);
} else {
btr = 0;
}
return btr;
}
int can_config_rxmsgobj(can_t *obj) {
uint16_t i = 0;
// Make sure the interface is available
while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
// Mark message valid, Direction = RX, Don't care about anything else
LPC_C_CAN0->CANIF1_ARB1 = 0;
LPC_C_CAN0->CANIF1_ARB2 = 0;
LPC_C_CAN0->CANIF1_MCTRL = 0;
for ( i = 1; i <= RX_MSG_OBJ_COUNT; i++ ) {
// Transfer arb and control fields to message object
LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL;
// Start Transfer to given message number
LPC_C_CAN0->CANIF1_CMDREQ = (i & 0x3F);
// Wait until transfer to message ram complete - TODO: maybe not block??
while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
}
// Accept all messages
can_filter(obj, 0, 0, CANStandard, 1);
return 1;
}
int can_config_txmsgobj(can_t *obj) {
uint16_t i = 0;
// Make sure the interface is available
while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
// Mark message valid, Direction = TX, Don't care about anything else
LPC_C_CAN0->CANIF1_ARB1 = 0;
LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_DIR;
LPC_C_CAN0->CANIF1_MCTRL = 0;
for ( i = RX_MSG_OBJ_COUNT + 1; i <= (TX_MSG_OBJ_COUNT + RX_MSG_OBJ_COUNT); i++ )
{
// Transfer arb and control fields to message object
LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL;
// In a union with CANIF1_CMDMSK_R
// Start Transfer to given message number
LPC_C_CAN0->CANIF1_CMDREQ = i & 0x3F;
// Wait until transfer to message ram complete - TODO: maybe not block??
while( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
}
return 1;
}
void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) {
// Enable power and clock
LPC_SYSCON->SYSAHBCLKCTRL1 |= (1UL << 7);
LPC_SYSCON->PRESETCTRL1 |= (1UL << 7);
LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
// Enable Initialization mode
if (!(LPC_C_CAN0->CANCNTL & (1UL << 0))) {
LPC_C_CAN0->CANCNTL |= (1UL << 0);
}
LPC_SWM->PINASSIGN[6] &= ~(0x00FFFF00L);
LPC_SWM->PINASSIGN[6] |= (rd << 16) | (td << 8);
can_frequency(obj, hz);
// Resume operation
LPC_C_CAN0->CANCNTL &= ~(1UL << 0);
while ( LPC_C_CAN0->CANCNTL & (1UL << 0) );
// Initialize RX message object
can_config_rxmsgobj(obj);
// Initialize TX message object
can_config_txmsgobj(obj);
}
void can_init(can_t *obj, PinName rd, PinName td) {
can_init_freq(obj, rd, td, 100000);
}
void can_free(can_t *obj) {
LPC_SYSCON->SYSAHBCLKCTRL1 &= ~(1UL << 7);
LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
}
int can_frequency(can_t *obj, int f) {
int btr = can_speed(SystemCoreClock, (unsigned int)f, 1);
int clkdiv = (btr >> 16) & 0x0F;
btr = btr & 0xFFFF;
if (btr > 0) {
// Set the bit clock
LPC_C_CAN0->CANCNTL |= (1UL << 6 | 1UL << 0); // set CCE and INIT
LPC_C_CAN0->CANCLKDIV = clkdiv;
LPC_C_CAN0->CANBT = btr;
LPC_C_CAN0->CANBRPE = 0x0000;
LPC_C_CAN0->CANCNTL &= ~(1UL << 6 | 1UL << 0); // clear CCE and INIT
return 1;
}
return 0;
}
int can_write(can_t *obj, CAN_Message msg, int cc) {
// Make sure controller is enabled
can_enable(obj);
// Find first message object that isn't pending to send
uint16_t msgnum = 0;
uint32_t txPending = (LPC_C_CAN0->CANTXREQ1 & 0xFF) | (LPC_C_CAN0->CANTXREQ2 << 16);
uint16_t i = 0;
for(i = RX_MSG_OBJ_COUNT; i < 32; i++) {
if ((txPending & (1 << i)) == 0) {
msgnum = i+1;
break;
}
}
// If no messageboxes are available, stop and return failure
if (msgnum == 0) {
return 0;
}
// Make sure the interface is available
while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
// Set the direction bit based on the message type
uint32_t direction = 0;
if (msg.type == CANData) {
direction = CANIFn_ARB2_DIR;
}
if (msg.format == CANExtended) {
// Mark message valid, Extended Frame, Set Identifier and mask everything
LPC_C_CAN0->CANIF1_ARB1 = (msg.id & 0xFFFF);
LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | CANIFn_ARB2_XTD | direction | ((msg.id >> 16) & 0x1FFFF);
LPC_C_CAN0->CANIF1_MSK1 = (ID_EXT_MASK & 0xFFFF);
LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MXTD | CANIFn_MSK2_MDIR | ((ID_EXT_MASK >> 16) & 0x1FFF);
} else {
// Mark message valid, Set Identifier and mask everything
LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | direction | ((msg.id << 2) & 0x1FFF);
LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MDIR | ((ID_STD_MASK << 2) & 0x1FFF);
}
// Use mask, request transmission, single message object and set DLC
LPC_C_CAN0->CANIF1_MCTRL = CANIFn_MCTRL_UMASK | CANIFn_MCTRL_TXRQST | CANIFn_MCTRL_EOB | (msg.len & 0xF);
LPC_C_CAN0->CANIF1_DA1 = ((msg.data[1] & 0xFF) << 8) | (msg.data[0] & 0xFF);
LPC_C_CAN0->CANIF1_DA2 = ((msg.data[3] & 0xFF) << 8) | (msg.data[2] & 0xFF);
LPC_C_CAN0->CANIF1_DB1 = ((msg.data[5] & 0xFF) << 8) | (msg.data[4] & 0xFF);
LPC_C_CAN0->CANIF1_DB2 = ((msg.data[7] & 0xFF) << 8) | (msg.data[6] & 0xFF);
// Transfer all fields to message object
LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_TXRQST | CANIFn_CMDMSK_DATA_A | CANIFn_CMDMSK_DATA_B;
// Start Transfer to given message number
LPC_C_CAN0->CANIF1_CMDREQ = (msgnum & 0x3F);
// Wait until transfer to message ram complete - TODO: maybe not block??
while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY);
// Wait until TXOK is set, then clear it - TODO: maybe not block
//while ( !(LPC_C_CAN0->STAT & CANSTAT_TXOK) );
LPC_C_CAN0->CANSTAT &= ~(1UL << 3);
return 1;
}
int can_read(can_t *obj, CAN_Message *msg, int handle) {
uint16_t i;
// Make sure controller is enabled
can_enable(obj);
// Find first message object with new data
if (handle == 0) {
uint32_t newdata = LPC_C_CAN0->CANND1 | (LPC_C_CAN0->CANND2 << 16);
// Find first free messagebox
for (i = 0; i < RX_MSG_OBJ_COUNT; i++) {
if (newdata & (1 << i)) {
handle = i+1;
break;
}
}
}
if (handle > 0 && handle <= 32) {
// Wait until message interface is free
while ( LPC_C_CAN0->CANIF2_CMDREQ & CANIFn_CMDREQ_BUSY );
// Transfer all fields to message object
LPC_C_CAN0->CANIF2_CMDMSK_W = CANIFn_CMDMSK_RD | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_CLRINTPND | CANIFn_CMDMSK_TXRQST | CANIFn_CMDMSK_DATA_A | CANIFn_CMDMSK_DATA_B;
// Start Transfer from given message number
LPC_C_CAN0->CANIF2_CMDREQ = (handle & 0x3F);
// Wait until transfer to message ram complete
while ( LPC_C_CAN0->CANIF2_CMDREQ & CANIFn_CMDREQ_BUSY );
if (LPC_C_CAN0->CANIF2_ARB2 & CANIFn_ARB2_XTD) {
msg->format = CANExtended;
msg->id = (LPC_C_CAN0->CANIF2_ARB1 & 0x1FFF) << 16;
msg->id |= (LPC_C_CAN0->CANIF2_ARB2 & 0x1FFF);
} else {
msg->format = CANStandard;
msg->id = (LPC_C_CAN0->CANIF2_ARB2 & 0x1FFF) >> 2;
}
if (LPC_C_CAN0->CANIF2_ARB2 & CANIFn_ARB2_DIR) {
msg->type = CANRemote;
}
else {
msg->type = CANData;
}
msg->len = (LPC_C_CAN0->CANIF2_MCTRL & 0xF); // TODO: If > 8, len = 8
msg->data[0] = ((LPC_C_CAN0->CANIF2_DA1 >> 0) & 0xFF);
msg->data[1] = ((LPC_C_CAN0->CANIF2_DA1 >> 8) & 0xFF);
msg->data[2] = ((LPC_C_CAN0->CANIF2_DA2 >> 0) & 0xFF);
msg->data[3] = ((LPC_C_CAN0->CANIF2_DA2 >> 8) & 0xFF);
msg->data[4] = ((LPC_C_CAN0->CANIF2_DB1 >> 0) & 0xFF);
msg->data[5] = ((LPC_C_CAN0->CANIF2_DB1 >> 8) & 0xFF);
msg->data[6] = ((LPC_C_CAN0->CANIF2_DB2 >> 0) & 0xFF);
msg->data[7] = ((LPC_C_CAN0->CANIF2_DB2 >> 8) & 0xFF);
LPC_C_CAN0->CANSTAT &= ~(1UL << 4);
return 1;
}
return 0;
}
void can_reset(can_t *obj) {
LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
LPC_C_CAN0->CANSTAT = 0;
can_config_rxmsgobj(obj);
can_config_txmsgobj(obj);
can_enable(obj); // clears a bus-off condition if necessary
}
unsigned char can_rderror(can_t *obj) {
return ((LPC_C_CAN0->CANEC >> 8) & 0x7F);
}
unsigned char can_tderror(can_t *obj) {
return (LPC_C_CAN0->CANEC & 0xFF);
}
void can_monitor(can_t *obj, int silent) {
if (silent) {
LPC_C_CAN0->CANCNTL |= (1UL << 7);
LPC_C_CAN0->CANTEST |= (1UL << 3);
} else {
LPC_C_CAN0->CANCNTL &= ~(1UL << 7);
LPC_C_CAN0->CANTEST &= ~(1UL << 3);
}
if (!(LPC_C_CAN0->CANCNTL & (1UL << 0))) {
LPC_C_CAN0->CANCNTL |= (1UL << 0);
}
}
const PinMap *can_rd_pinmap()
{
return PinMap_CAN_testing;
}
const PinMap *can_td_pinmap()
{
return PinMap_CAN_testing;
}

38
targets/TARGET_NXP/TARGET_LPC15XX/device.h
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@ -1,38 +0,0 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

1725
targets/TARGET_NXP/TARGET_LPC15XX/device/LPC15xx.h
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File diff suppressed because it is too large Load Diff

48
targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_ARM_MICRO/LPC15xx.sct
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@ -1,48 +0,0 @@
#! armcc -E
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
; 256k flash
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x40000
#endif
; 36kB(0x9000)
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x02000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x00009000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; 8_byte_aligned(16+47 vect * 4 bytes) = 0x100
#define VECTOR_SIZE 0x100
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

287
targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_ARM_MICRO/startup_LPC15xx.S
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@ -1,287 +0,0 @@
;/**************************************************************************//**
; * @file startup_LPC15xx.s
; * @brief CMSIS Cortex-M3 Core Device Startup File for
; * NXP LPC15xx Device Series
; * @version V1.00
; * @date 17. July 2013
; *
; * @note
; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 16+ 0 Windowed watchdog timer interrupt
DCD BOD_IRQHandler ; 16+ 1 BOD interrupt
DCD FLASH_IRQHandler ; 16+ 2 Flash controller interrupt
DCD EE_IRQHandler ; 16+ 3 EEPROM controller interrupt
DCD DMA_IRQHandler ; 16+ 4 DMA interrupt
DCD GINT0_IRQHandler ; 16+ 5 GPIO group0 interrupt
DCD GINT1_IRQHandler ; 16+ 6 GPIO group1 interrupt
DCD PIN_INT0_IRQHandler ; 16+ 7 Pin interrupt 0 or pattern match engine slice 0 interrupt
DCD PIN_INT1_IRQHandler ; 16+ 8 Pin interrupt 1 or pattern match engine slice 1 interrupt
DCD PIN_INT2_IRQHandler ; 16+ 9 Pin interrupt 2 or pattern match engine slice 2 interrupt
DCD PIN_INT3_IRQHandler ; 16+10 Pin interrupt 3 or pattern match engine slice 3 interrupt
DCD PIN_INT4_IRQHandler ; 16+11 Pin interrupt 4 or pattern match engine slice 4 interrupt
DCD PIN_INT5_IRQHandler ; 16+12 Pin interrupt 5 or pattern match engine slice 5 interrupt
DCD PIN_INT6_IRQHandler ; 16+13 Pin interrupt 6 or pattern match engine slice 6 interrupt
DCD PIN_INT7_IRQHandler ; 16+14 Pin interrupt 7 or pattern match engine slice 7 interrupt
DCD RIT_IRQHandler ; 16+15 RIT interrupt
DCD SCT0_IRQHandler ; 16+16 State configurable timer interrupt
DCD SCT1_IRQHandler ; 16+17 State configurable timer interrupt
DCD SCT2_IRQHandler ; 16+18 State configurable timer interrupt
DCD SCT3_IRQHandler ; 16+19 State configurable timer interrupt
DCD MRT_IRQHandler ; 16+20 Multi-rate timer interrupt
DCD UART0_IRQHandler ; 16+21 USART0 interrupt
DCD UART1_IRQHandler ; 16+22 USART1 interrupt
DCD UART2_IRQHandler ; 16+23 USART2 interrupt
DCD I2C0_IRQHandler ; 16+24 I2C0 interrupt
DCD SPI0_IRQHandler ; 16+25 SPI0 interrupt
DCD SPI1_IRQHandler ; 16+26 SPI1 interrupt
DCD C_CAN0_IRQHandler ; 16+27 C_CAN0 interrupt
DCD USB_IRQ_IRQHandler ; 16+28 USB interrupt
DCD USB_FIQ_IRQHandler ; 16+29 USB interrupt
DCD USBWAKEUP_IRQHandler ; 16+30 USB wake-up interrupt
DCD ADC0_SEQA_IRQHandler ; 16+31 ADC0 sequence A completion.
DCD ADC0_SEQB_IRQHandler ; 16+32 ADC0 sequence B completion.
DCD ADC0_THCMP_IRQHandler ; 16+33 ADC0 threshold compare
DCD ADC0_OVR_IRQHandler ; 16+34 ADC0 overrun
DCD ADC1_SEQA_IRQHandler ; 16+35 ADC1 sequence A completion.
DCD ADC1_SEQB_IRQHandler ; 16+36 ADC1 sequence B completion.
DCD ADC1_THCMP_IRQHandler ; 16+37 ADC1 threshold compare
DCD ADC1_OVR_IRQHandler ; 16+38 ADC1 overrun
DCD DAC_IRQHandler ; 16+39 DAC interrupt
DCD CMP0_IRQHandler ; 16+40 Analog comparator 0 interrupt (ACMP0)
DCD CMP1_IRQHandler ; 16+41 Analog comparator 1 interrupt (ACMP1)
DCD CMP2_IRQHandler ; 16+42 Analog comparator 2 interrupt (ACMP2)
DCD CMP3_IRQHandler ; 16+43 Analog comparator 3 interrupt (ACMP3)
DCD QEI_IRQHandler ; 16+44 QEI interrupt
DCD RTC_ALARM_IRQHandler ; 16+45 RTC alarm interrupt
DCD RTC_WAKE_IRQHandler ; 16+46 RTC wake-up interrut
; <h> Code Read Protection
; <o> Code Read Protection <0xFFFFFFFF=>CRP Disabled
; <0x12345678=>CRP Level 1
; <0x87654321=>CRP Level 2
; <0x43218765=>CRP Level 3 (ARE YOU SURE?)
; <0x4E697370=>NO ISP (ARE YOU SURE?)
; </h>
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
;--- enable SRAM1 and SRAM2 memory
LDR R0, =0x400740C4 ; SYSAHBCLKCTRL0 register addr
LDR R2, [R0] ; read SYSAHBCLKCTRL0
ORR R2, R2, #0x18 ; enable SRAM1, SRAM2
STR R2, [R0] ; store SYSAHBCLKCTRL0
;---
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT EE_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT PIN_INT0_IRQHandler [WEAK]
EXPORT PIN_INT1_IRQHandler [WEAK]
EXPORT PIN_INT2_IRQHandler [WEAK]
EXPORT PIN_INT3_IRQHandler [WEAK]
EXPORT PIN_INT4_IRQHandler [WEAK]
EXPORT PIN_INT5_IRQHandler [WEAK]
EXPORT PIN_INT6_IRQHandler [WEAK]
EXPORT PIN_INT7_IRQHandler [WEAK]
EXPORT RIT_IRQHandler [WEAK]
EXPORT SCT0_IRQHandler [WEAK]
EXPORT SCT1_IRQHandler [WEAK]
EXPORT SCT2_IRQHandler [WEAK]
EXPORT SCT3_IRQHandler [WEAK]
EXPORT MRT_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT C_CAN0_IRQHandler [WEAK]
EXPORT USB_IRQ_IRQHandler [WEAK]
EXPORT USB_FIQ_IRQHandler [WEAK]
EXPORT USBWAKEUP_IRQHandler [WEAK]
EXPORT ADC0_SEQA_IRQHandler [WEAK]
EXPORT ADC0_SEQB_IRQHandler [WEAK]
EXPORT ADC0_THCMP_IRQHandler [WEAK]
EXPORT ADC0_OVR_IRQHandler [WEAK]
EXPORT ADC1_SEQA_IRQHandler [WEAK]
EXPORT ADC1_SEQB_IRQHandler [WEAK]
EXPORT ADC1_THCMP_IRQHandler [WEAK]
EXPORT ADC1_OVR_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT CMP1_IRQHandler [WEAK]
EXPORT CMP2_IRQHandler [WEAK]
EXPORT CMP3_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
EXPORT RTC_ALARM_IRQHandler [WEAK]
EXPORT RTC_WAKE_IRQHandler [WEAK]
WDT_IRQHandler
BOD_IRQHandler
FLASH_IRQHandler
EE_IRQHandler
DMA_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
PIN_INT0_IRQHandler
PIN_INT1_IRQHandler
PIN_INT2_IRQHandler
PIN_INT3_IRQHandler
PIN_INT4_IRQHandler
PIN_INT5_IRQHandler
PIN_INT6_IRQHandler
PIN_INT7_IRQHandler
RIT_IRQHandler
SCT0_IRQHandler
SCT1_IRQHandler
SCT2_IRQHandler
SCT3_IRQHandler
MRT_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
I2C0_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
C_CAN0_IRQHandler
USB_IRQ_IRQHandler
USB_FIQ_IRQHandler
USBWAKEUP_IRQHandler
ADC0_SEQA_IRQHandler
ADC0_SEQB_IRQHandler
ADC0_THCMP_IRQHandler
ADC0_OVR_IRQHandler
ADC1_SEQA_IRQHandler
ADC1_SEQB_IRQHandler
ADC1_THCMP_IRQHandler
ADC1_OVR_IRQHandler
DAC_IRQHandler
CMP0_IRQHandler
CMP1_IRQHandler
CMP2_IRQHandler
CMP3_IRQHandler
QEI_IRQHandler
RTC_ALARM_IRQHandler
RTC_WAKE_IRQHandler
B .
ENDP
ALIGN
END

162
targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_GCC_ARM/LPC1549.ld
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@ -1,162 +0,0 @@
/* Linker script for mbed LPC1549 */
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Linker script to configure memory regions. */
MEMORY
{
/* Define each memory region */
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K
Ram0_16 (rwx) : ORIGIN = 0x2000000 + 0x100, LENGTH = (16K - 0x100)
Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 16K
Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 4K
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
Image$$RW_IRAM1$$Base = .;
*(vtable)
*(.data*)
. = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(8);
/* All data end */
__data_end__ = .;
} > Ram0_16
.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
Image$$RW_IRAM1$$ZI$$Limit = . ;
} > Ram0_16
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
. = ORIGIN(Ram1_16) + LENGTH(Ram1_16);
__HeapLimit = .;
} > Ram1_16
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > Ram2_4
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(Ram2_4) + LENGTH(Ram2_4);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

247
targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_GCC_ARM/startup_LPC15xx.S
View File

@ -1,247 +0,0 @@
/* File: startup_ARMCM3.s
* Purpose: startup file for Cortex-M3/M4 devices. Should use with
* GNU Tools for ARM Embedded Processors
* Version: V1.1
* Date: 17 June 2011
*
* Copyright (C) 2011 ARM Limited. All rights reserved.
* ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*/
.syntax unified
.arch armv7-m
/* Memory Model
The HEAP starts at the end of the DATA section and grows upward.
The STACK starts at the end of the RAM and grows downward.
The HEAP and stack STACK are only checked at compile time:
(DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
This is just a check for the bare minimum for the Heap+Stack area before
aborting compilation, it is not the run time limit:
Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
*/
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0xc00
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x800
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.space Heap_Size
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long WDT_IRQHandler /* 0: Windowed watchdog timer */
.long BOD_IRQHandler /* 1: Brown-Out Detect */
.long FMC_IRQHandler /* 2: Flash controller */
.long EEPROM_IRQHandler /* 3: EEPROM controller */
.long DMA_IRQHandler /* 4: DMA */
.long GINT0_IRQHandler /* 5: GPIO group 0 */
.long GINT1_IRQHandler /* 6: GPIO group 1 */
.long PIN_INT0_IRQHandler /* 7: PIO INT0 */
.long PIN_INT1_IRQHandler /* 8: PIO INT1 */
.long PIN_INT2_IRQHandler /* 9: PIO INT2 */
.long PIN_INT3_IRQHandler /* 10: PIO INT3 */
.long PIN_INT4_IRQHandler /* 11: PIO INT4 */
.long PIN_INT5_IRQHandler /* 12: PIO INT5 */
.long PIN_INT6_IRQHandler /* 13: PIO INT6 */
.long PIN_INT7_IRQHandler /* 14: PIO INT7 */
.long RIT_IRQHandler /* 15: Repetitive Interrupt Timer */
.long SCT0_IRQHandler /* 16: State configurable timer */
.long SCT1_IRQHandler /* 17: State configurable timer */
.long SCT2_IRQHandler /* 18: State configurable timer */
.long SCT3_IRQHandler /* 19: State configurable timer */
.long MRT_IRQHandler /* 20: Multi-Rate Timer */
.long UART0_IRQHandler /* 21: UART0 */
.long UART1_IRQHandler /* 22: UART1 */
.long UART2_IRQHandler /* 23: UART2 */
.long I2C0_IRQHandler /* 24: I2C0 controller */
.long SPI0_IRQHandler /* 25: SPI0 controller */
.long SPI1_IRQHandler /* 26: SPI1 controller */
.long CAN_IRQHandler /* 27: C_CAN0 */
.long USB_IRQHandler /* 28: USB IRQ */
.long USB_FIQHandler /* 29: USB FIQ */
.long USBWakeup_IRQHandler /* 30: USB wake-up */
.long ADC0A_IRQHandler /* 31: ADC0 sequence A completion */
.long ADC0B_IRQHandler /* 32: ADC0 sequence B completion */
.long ADC0_THCMP_IRQHandler /* 33: ADC0 threshold compare */
.long ADC0_OVR_IRQHandler /* 34: ADC0 overrun */
.long ADC1A_IRQHandler /* 35: ADC1 sequence A completion */
.long ADC1B_IRQHandler /* 36: ADC1 sequence B completion */
.long ADC1_THCMP_IRQHandler /* 37: ADC1 threshold compare */
.long ADC1_OVR_IRQHandler /* 38: ADC1 overrun */
.long DAC_IRQHandler /* 39: DAC */
.long ACMP0_IRQHandler /* 40: Analog Comparator 0 */
.long ACMP1_IRQHandler /* 41: Analog Comparator 1 */
.long ACMP2_IRQHandler /* 42: Analog Comparator 2 */
.long ACMP3_IRQHandler /* 43: Analog Comparator 3 */
.long QEI_IRQHandler /* 44: Quadrature Encoder Interface */
.long RTC_ALARM_IRQHandler /* 45: RTC alarm */
.long RTC_WAKE_IRQHandler /* 46: RTC wake-up */
.size __isr_vector, . - __isr_vector
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* _etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.Lflash_to_ram_loop:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .Lflash_to_ram_loop
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
def_default_handler BusFault_Handler
def_default_handler UsageFault_Handler
def_default_handler SVC_Handler
def_default_handler DebugMon_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_default_handler WDT_IRQHandler
def_irq_default_handler BOD_IRQHandler
def_irq_default_handler FMC_IRQHandler
def_irq_default_handler EEPROM_IRQHandler
def_irq_default_handler DMA_IRQHandler
def_irq_default_handler GINT0_IRQHandler
def_irq_default_handler GINT1_IRQHandler
def_irq_default_handler PIN_INT0_IRQHandler
def_irq_default_handler PIN_INT1_IRQHandler
def_irq_default_handler PIN_INT2_IRQHandler
def_irq_default_handler PIN_INT3_IRQHandler
def_irq_default_handler PIN_INT4_IRQHandler
def_irq_default_handler PIN_INT5_IRQHandler
def_irq_default_handler PIN_INT6_IRQHandler
def_irq_default_handler PIN_INT7_IRQHandler
def_irq_default_handler RIT_IRQHandler
def_irq_default_handler SCT0_IRQHandler
def_irq_default_handler SCT1_IRQHandler
def_irq_default_handler SCT2_IRQHandler
def_irq_default_handler SCT3_IRQHandler
def_irq_default_handler MRT_IRQHandler
def_irq_default_handler UART0_IRQHandler
def_irq_default_handler UART1_IRQHandler
def_irq_default_handler UART2_IRQHandler
def_irq_default_handler I2C0_IRQHandler
def_irq_default_handler SPI0_IRQHandler
def_irq_default_handler SPI1_IRQHandler
def_irq_default_handler CAN_IRQHandler
def_irq_default_handler USB_IRQHandler
def_irq_default_handler USB_FIQHandler
def_irq_default_handler USBWakeup_IRQHandler
def_irq_default_handler ADC0A_IRQHandler
def_irq_default_handler ADC0B_IRQHandler
def_irq_default_handler ADC0_THCMP_IRQHandler
def_irq_default_handler ADC0_OVR_IRQHandler
def_irq_default_handler ADC1A_IRQHandler
def_irq_default_handler ADC1B_IRQHandler
def_irq_default_handler ADC1_THCMP_IRQHandler
def_irq_default_handler ADC1_OVR_IRQHandler
def_irq_default_handler DAC_IRQHandler
def_irq_default_handler ACMP0_IRQHandler
def_irq_default_handler ACMP1_IRQHandler
def_irq_default_handler ACMP2_IRQHandler
def_irq_default_handler ACMP3_IRQHandler
def_irq_default_handler QEI_IRQHandler
def_irq_default_handler RTC_ALARM_IRQHandler
def_irq_default_handler RTC_WAKE_IRQHandler
def_irq_default_handler DEF_IRQHandler
.end

40
targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_IAR/LPC15xx.icf
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@ -1,40 +0,0 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_NVIC_start__ = 0x02000000;
define symbol __ICFEDIT_region_NVIC_end__ = 0x020000FF;
define symbol __ICFEDIT_region_RAM_start__ = 0x02000100;
define symbol __ICFEDIT_region_RAM_end__ = 0x02008FDF;
/*-Sizes-*/
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_heap__ = 0x2400;
/**** End of ICF editor section. ###ICF###*/
define symbol __CRP_start__ = 0x000002FC;
define symbol __CRP_end__ = 0x000002FF;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block HEAP, block CSTACK };
place in CRP_region { section .crp };

274
targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_IAR/startup_LPC15xx.S
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@ -1,274 +0,0 @@
/**************************************************
*
* Part one of the system initialization code, contains low-level
* initialization, plain thumb variant.
*
* Copyright 2009 IAR Systems. All rights reserved.
*
* $Revision: 28 $
*
**************************************************/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK) ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
__vector_table_0x1c
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; Watchdog timer
DCD BOD_IRQHandler ; Brown Out Detect
DCD FLASH_IRQHandler ; NVMC Flash Controller
DCD EE_IRQHandler ; NVMC EE Controller
DCD DMA_IRQHandler ; DMA Controller
DCD GINT0_IRQHandler
DCD GINT1_IRQHandler ; PIO0 (0:7)
DCD PIN_INT0_IRQHandler ; 16+ 7 Pin interrupt 0 or pattern match engine slice 0 interrupt
DCD PIN_INT1_IRQHandler ; 16+ 8 Pin interrupt 1 or pattern match engine slice 1 interrupt
DCD PIN_INT2_IRQHandler ; 16+ 9 Pin interrupt 2 or pattern match engine slice 2 interrupt
DCD PIN_INT3_IRQHandler ; 16+10 Pin interrupt 3 or pattern match engine slice 3 interrupt
DCD PIN_INT4_IRQHandler ; 16+11 Pin interrupt 4 or pattern match engine slice 4 interrupt
DCD PIN_INT5_IRQHandler ; 16+12 Pin interrupt 5 or pattern match engine slice 5 interrupt
DCD PIN_INT6_IRQHandler ; 16+13 Pin interrupt 6 or pattern match engine slice 6 interrupt
DCD PIN_INT7_IRQHandler ; 16+14 Pin interrupt 7 or pattern match engine slice 7 interrupt
DCD RIT_IRQHandler ; RIT Timer
DCD SCT0_IRQHandler ; SCT Timer0
DCD SCT1_IRQHandler ; SCT Timer1
DCD SCT2_IRQHandler ; SCT Timer2
DCD SCT3_IRQHandler ; SCT Timer3
DCD MRT_IRQHandler ; MRT timer
DCD UART0_IRQHandler ; MIN UART0
DCD UART1_IRQHandler ; MIN UART1
DCD UART2_IRQHandler ; MIN UART2
DCD I2C0_IRQHandler ; BI2C
DCD SPI0_IRQHandler ; LSPI0
DCD SPI1_IRQHandler ; LSPI1
DCD C_CAN0_IRQHandler ; CAN
DCD USB_IRQ_IRQHandler ; USB IRQ
DCD USB_FIQ_IRQHandler ; USB FIQ
DCD USBWakeup_IRQHandler ; USB wake up
DCD ADC0_SEQA_IRQHandler ; ADC0 SEQA
DCD ADC0_SEQB_IRQHandler ; ADC0 SEQB
DCD ADC0_THCMP_IRQHandler ; ADC0 THCMP
DCD ADC0_OVR_IRQHandler ; ADC0 OVR
DCD ADC1_SEQA_IRQHandler ; ADC1 SEQA
DCD ADC1_SEQB_IRQHandler ; ADC1 SEQB
DCD ADC1_THCMP_IRQHandler ; ADC1 THCMP
DCD ADC1_OVR_IRQHandler ; ADC1 OVR
DCD DAC_IRQHandler ; D/A Converter
DCD CMP0_IRQHandler ; Comparator 0
DCD CMP1_IRQHandler ; Comparator 1
DCD CMP2_IRQHandler ; Comparator 2
DCD CMP3_IRQHandler ; Comparator 3
DCD QEI_IRQHandler ; QEI
DCD RTC_ALARM_IRQHandler ; RTC Alarm
DCD RTC_WAKE_IRQHandler ; RTC Wake
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
PUBWEAK HardFault_Handler
PUBWEAK MemManage_Handler
PUBWEAK BusFault_Handler
PUBWEAK UsageFault_Handler
PUBWEAK SVC_Handler
PUBWEAK DebugMon_Handler
PUBWEAK PendSV_Handler
PUBWEAK SysTick_Handler
PUBWEAK WDT_IRQHandler
PUBWEAK BOD_IRQHandler
PUBWEAK FLASH_IRQHandler
PUBWEAK EE_IRQHandler
PUBWEAK DMA_IRQHandler
PUBWEAK GINT0_IRQHandler
PUBWEAK GINT1_IRQHandler
PUBWEAK PIN_INT0_IRQHandler
PUBWEAK PIN_INT1_IRQHandler
PUBWEAK PIN_INT2_IRQHandler
PUBWEAK PIN_INT3_IRQHandler
PUBWEAK PIN_INT4_IRQHandler
PUBWEAK PIN_INT5_IRQHandler
PUBWEAK PIN_INT6_IRQHandler
PUBWEAK PIN_INT7_IRQHandler
PUBWEAK RIT_IRQHandler
PUBWEAK SCT0_IRQHandler
PUBWEAK SCT1_IRQHandler
PUBWEAK SCT2_IRQHandler
PUBWEAK SCT3_IRQHandler
PUBWEAK MRT_IRQHandler
PUBWEAK UART0_IRQHandler
PUBWEAK UART1_IRQHandler
PUBWEAK UART2_IRQHandler
PUBWEAK I2C0_IRQHandler
PUBWEAK SPI0_IRQHandler
PUBWEAK SPI1_IRQHandler
PUBWEAK C_CAN0_IRQHandler
PUBWEAK USB_IRQ_IRQHandler
PUBWEAK USB_FIQ_IRQHandler
PUBWEAK USBWakeup_IRQHandler
PUBWEAK ADC0_SEQA_IRQHandler
PUBWEAK ADC0_SEQB_IRQHandler
PUBWEAK ADC0_THCMP_IRQHandler
PUBWEAK ADC0_OVR_IRQHandler
PUBWEAK ADC1_SEQA_IRQHandler
PUBWEAK ADC1_SEQB_IRQHandler
PUBWEAK ADC1_THCMP_IRQHandler
PUBWEAK ADC1_OVR_IRQHandler
PUBWEAK DAC_IRQHandler
PUBWEAK CMP0_IRQHandler
PUBWEAK CMP1_IRQHandler
PUBWEAK CMP2_IRQHandler
PUBWEAK CMP3_IRQHandler
PUBWEAK QEI_IRQHandler
PUBWEAK RTC_ALARM_IRQHandler
PUBWEAK RTC_WAKE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
THUMB
NMI_Handler
HardFault_Handler
MemManage_Handler
BusFault_Handler
UsageFault_Handler
SVC_Handler
DebugMon_Handler
PendSV_Handler
SysTick_Handler
WDT_IRQHandler
BOD_IRQHandler
FLASH_IRQHandler
EE_IRQHandler
DMA_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
PIN_INT0_IRQHandler
PIN_INT1_IRQHandler
PIN_INT2_IRQHandler
PIN_INT3_IRQHandler
PIN_INT4_IRQHandler
PIN_INT5_IRQHandler
PIN_INT6_IRQHandler
PIN_INT7_IRQHandler
RIT_IRQHandler
SCT0_IRQHandler
SCT1_IRQHandler
SCT2_IRQHandler
SCT3_IRQHandler
MRT_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
I2C0_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
C_CAN0_IRQHandler
USB_IRQ_IRQHandler
USB_FIQ_IRQHandler
USBWakeup_IRQHandler
ADC0_SEQA_IRQHandler
ADC0_SEQB_IRQHandler
ADC0_THCMP_IRQHandler
ADC0_OVR_IRQHandler
ADC1_SEQA_IRQHandler
ADC1_SEQB_IRQHandler
ADC1_THCMP_IRQHandler
ADC1_OVR_IRQHandler
DAC_IRQHandler
CMP0_IRQHandler
CMP1_IRQHandler
CMP2_IRQHandler
CMP3_IRQHandler
QEI_IRQHandler
RTC_ALARM_IRQHandler
RTC_WAKE_IRQHandler
Default_Handler
B Default_Handler
SECTION .crp:CODE:ROOT(2)
DATA
/* Code Read Protection
CRP1 0x12345678 - Write to RAM command can not access RAM below 0x10000200.
- Read Memory command: disabled.
- Copy RAM to Flash command: cannot write to Sector 0.
- "Go" command: disabled.
- Erase sector(s) command: can erase any individual sector except
sector 0 only, or can erase all sectors at once.
- Compare command: disabled
CRP2 0x87654321 - Write to RAM command: disabled.
- Copy RAM to Flash: disabled.
- Erase command: only allows erase of all sectors.
CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
by pulling PIO0_1 LOW is disabled if a valid user code is
present in flash sector 0.
Caution: If CRP3 is selected, no future factory testing can be
performed on the device.
*/
DCD 0xFFFFFFFF
END

13
targets/TARGET_NXP/TARGET_LPC15XX/device/cmsis.h
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@ -1,13 +0,0 @@
/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in LPC8xx specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "LPC15xx.h"
#include "cmsis_nvic.h"
#endif

37
targets/TARGET_NXP/TARGET_LPC15XX/device/cmsis_nvic.h
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@ -1,37 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2011 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 47) // CORE + MCU Peripherals
#define NVIC_RAM_VECTOR_ADDRESS 0x02000000 // Vectors positioned at start of RAM
#endif

517
targets/TARGET_NXP/TARGET_LPC15XX/device/system_LPC15xx.c
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@ -1,517 +0,0 @@
/**************************************************************************//**
* @file system_LPC15xx.c
* @brief CMSIS Cortex-M3 Device System Source File for
* NXP LPC15xx Device Series
* @version V1.00
* @date 19. July 2013
*
* @note
* Copyright (C) 2013 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include "LPC15xx.h"
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*- SystemCoreClock Configuration -------------------------------------------*/
// <e0> SystemCoreClock Configuration
#define CLOCK_SETUP 1
//
// <h> System Oscillator Control (SYSOSCCTRL)
// <o.0> BYPASS: System Oscillator Bypass Enable
// <i> If enabled then PLL input (sys_osc_clk) is fed
// <i> directly from XTALIN and XTALOUT pins.
// <o.1> FREQRANGE: System Oscillator Frequency Range
// <i> Determines frequency range for Low-power oscillator.
// <0=> 1 - 20 MHz
// <1=> 15 - 25 MHz
// </h>
#define SYSOSCCTRL_Val 0x00000000 // Reset value: 0x000
//
// <o.0..1> System PLL Clock Source Select (SYSPLLCLKSEL)
// <0=> IRC Oscillator
// <1=> Crystal Oscillator (SYSOSC)
#define SYSPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
//
// <e> Clock Configuration (Manual)
#define CLOCK_SETUP_REG 1
//
// <o.0..1> Main Clock Source Select A (MAINCLKSELA)
// <0=> IRC Oscillator
// <1=> System Oscillator
// <2=> WD Oscillator
#define MAINCLKSELA_Val 0x00000001 // Reset value: 0x000
//
// <o.0..1> Main Clock Source Select B (MAINCLKSELB)
// <0=> MAINCLKSELA
// <1=> System PLL Input
// <2=> System PLL Output
// <3=> RTC Oscillator
#define MAINCLKSELB_Val 0x00000002 // Reset value: 0x000
//
// <h> System PLL Setting (SYSPLLCTRL)
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
// <o.0..5> MSEL: Feedback Divider Selection
// <i> M = MSEL + 1
// <0-31>
// <o.6..7> PSEL: Post Divider Selection
// <i> Post divider ratio P. Division ratio is 2 * P
// <0=> P = 1
// <1=> P = 2
// <2=> P = 4
// <3=> P = 8
// </h>
#define SYSPLLCTRL_Val 0x00000045 // Reset value: 0x000
//
// <o.0..7> System AHB Clock Divider (SYSAHBCLKDIV.DIV)
// <i> Divides main clock to provide system clock to core, memories, and peripherals.
// <i> 0 = is disabled
// <0-255>
#define SYSAHBCLKDIV_Val 0x00000001 // Reset value: 0x001
// </e>
//
// <e> Clock Configuration (via ROM PLL API)
#define CLOCK_SETUP_API 0
//
// <o> PLL API Mode Select
// <0=> Exact
// <1=> Less than or equal
// <2=> Greater than or equal
// <3=> As close as possible
#define PLL_API_MODE_Val 0
//
// <o> CPU Frequency [Hz] <1000000-72000000:1000>
#define PLL_API_FREQ_Val 72000000
// </e>
//
// <e> USB Clock Configuration
#define USB_CLOCK_SETUP 0
// <h> USB PLL Control (USBPLLCTRL)
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
// <o.0..5> MSEL: Feedback Divider Selection
// <i> M = MSEL + 1
// <0-31>
// <o.7..6> PSEL: Post Divider Selection
// <i> Post divider ratio P. Division ratio is 2 * P
// <0=> P = 1
// <1=> P = 2
// <2=> P = 4
// <3=> P = 8
// </h>
#define USBPLLCTRL_Val 0x00000023 // Reset value: 0x000
//
// <o.0..1> USB PLL Clock Source Select (USBPLLCLKSEL.SEL)
// <0=> IRC Oscillator
// <1=> System Oscillator
#define USBPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
//
// <o.0..1> USB Clock Source Select (USBCLKSEL.SEL)
// <0=> IRC Oscillator
// <1=> System Oscillator
// <2=> USB PLL out
// <3=> Main clock
#define USBCLKSEL_Val 0x00000002 // Reset value: 0x000
//
// <o.0..7> USB Clock Divider (USBCLKDIV.DIV)
// <i> Divides USB clock to 48 MHz.
// <i> 0 = is disabled
// <0-255>
#define USBCLKDIV_Val 0x00000001 // Reset Value: 0x001
// </e>
//
// <e> SCT Clock Configuration
#define SCT_CLOCK_SETUP 1
// <h> SCT PLL Control (SCTPLLCTRL)
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
// <o.0..5> MSEL: Feedback Divider Selection
// <i> M = MSEL + 1
// <0-31>
// <o.7..6> PSEL: Post Divider Selection
// <i> Post divider ratio P. Division ratio is 2 * P
// <0=> P = 1
// <1=> P = 2
// <2=> P = 4
// <3=> P = 8
// </h>
#define SCTPLLCTRL_Val 0x00000045 // Reset value: 0x000
//
// <o.0..1> SCT PLL Clock Source Select (SCTPLLCLKSEL.SEL)
// <0=> IRC Oscillator
// <1=> System Oscillator
#define SCTPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
// </e>
//
// </e>
//
// <o0>System Oscillator (XTAL) Frequency [Hz] <1000000-25000000>
// <i> XTAL frequency must be in the range of 1 MHz to 25 MHz
//
#define XTAL_CLK_Val 12000000
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __XTAL_CLK ( XTAL_CLK_Val) /* Oscillator freq */
#define __SYS_OSC_CLK ( __XTAL_CLK) /* System oscillator freq */
#define __IRC_OSC_CLK ( 12000000UL) /* Internal RC oscillator freq */
#define __RTC_OSC_CLK ( 32768UL) /* RTC oscillator freq */
#define __WDT_OSC_CLK ( 503000UL) /* WDT oscillator freq */
/*----------------------------------------------------------------------------
Check the register settings
*----------------------------------------------------------------------------*/
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
#define CHECK_RSVD(val, mask) (val & mask)
#if (CHECK_RANGE((SYSOSCCTRL_Val), 0, 1))
#error "SYSOSCCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
#error "SYSPLLCLKSEL: Value out of range!"
#endif
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000000FF))
#error "SYSPLLCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((MAINCLKSELA_Val), 0, 2))
#error "MAINCLKSELA: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((MAINCLKSELB_Val), ~0x00000003))
#error "MAINCLKSELB: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
#error "SYSAHBCLKDIV: Value out of range!"
#endif
#if ( CLOCK_SETUP_REG == CLOCK_SETUP_API )
#error "You must select either manual or API based Clock Configuration!"
#endif
#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
#error "USBPLLCLKSEL: Value out of range!"
#endif
#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x00000FF))
#error "USBPLLCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((USBCLKSEL_Val), 0, 3))
#error "USBCLKSEL: Value out of range!"
#endif
#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
#error "USBCLKDIV: Value out of range!"
#endif
#if (CHECK_RANGE((SCTPLLCLKSEL_Val), 0, 1))
#error "SCTPLLCLKSEL: Value out of range!"
#endif
#if (CHECK_RSVD((SCTPLLCTRL_Val), ~0x00000FF))
#error "SCTPLLCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE(XTAL_CLK_Val, 1000000, 25000000))
#error "XTAL frequency is out of bounds"
#endif
#if (CHECK_RANGE(PLL_API_MODE_Val, 0, 3))
#error "PLL API Mode Select not valid"
#endif
#if (CHECK_RANGE(PLL_API_FREQ_Val, 1000000, 72000000))
#error "CPU Frequency (API mode) not valid"
#endif
/*----------------------------------------------------------------------------
Calculate system core clock
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP) /* Clock Setup */
/* sys_pllclkin calculation */
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
#else
#error "Oops"
#endif
#if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
#if ((MAINCLKSELA_Val & 0x03) == 0)
#define __MAINA_CLOCK (__IRC_OSC_CLK)
#elif ((MAINCLKSELA_Val & 0x03) == 1)
#define __MAINA_CLOCK (__SYS_OSC_CLK)
#elif ((MAINCLKSELA_Val & 0x03) == 2)
#define __MAINA_CLOCK (__WDT_OSC_CLK)
#else
#error "Oops"
#endif
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
/* main clock calculation */
#if ((MAINCLKSELB_Val & 0x03) == 0)
#define __MAINB_CLOCK (__MAINA_CLOCK)
#elif ((MAINCLKSELB_Val & 0x03) == 1)
#define __MAINB_CLOCK (__SYS_PLLCLKIN)
#elif ((MAINCLKSELB_Val & 0x03) == 2)
#define __MAINB_CLOCK (__SYS_PLLCLKOUT)
#elif ((MAINCLKSELB_Val & 0x03) == 3)
#define __MAINB_CLOCK (__RTC_OSC_CLK)
#else
#error "Oops"
#endif
#define __SYSTEM_CLOCK (__MAINB_CLOCK / SYSAHBCLKDIV_Val)
#endif /* Clock Setup via Register */
#if (CLOCK_SETUP_API == 1) /* Clock Setup via ROM API */
#define __SYSTEM_CLOCK (PLL_API_FREQ_Val)
#endif /* Clock Setup via PLL API */
#else
#define __SYSTEM_CLOCK (__IRC_OSC_CLK)
#endif /* CLOCK_SETUP */
#if ((CLOCK_SETUP == 1) && (CLOCK_SETUP_API == 1)) /* PLL Setup via PLL API */
#include "power_api.h"
typedef struct _ROM {
const unsigned p_dev0;
const unsigned p_dev1;
const unsigned p_dev2;
const PWRD * pPWRD; /* ROM Power Management API */
const unsigned p_dev4;
const unsigned p_dev5;
const unsigned p_dev6;
const unsigned p_dev7;
} ROM;
/*----------------------------------------------------------------------------
PLL API Function
*----------------------------------------------------------------------------*/
static void setPLL(const uint32_t pllMode, const uint32_t pllInFreq, const uint32_t reqCpuFreq)
{
uint32_t cmd[5], res[5];
ROM ** rom = (ROM **) 0x03000200; /* pointer to power API calls */
cmd[0] = pllInFreq; /* PLL's input freq in KHz */
cmd[1] = reqCpuFreq; /* requested CPU freq in KHz */
cmd[2] = pllMode;
cmd[3] = 0; /* no timeout for PLL to lock */
/* Execute API call */
(*rom)->pPWRD->set_pll(cmd, res); /* call API function */
if ((res[0] != PLL_CMD_SUCCESS)){ /* in case of an error ... */
while(1); /* ... stay here */
}
}
#endif
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /* System Clock Frequency */
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
/* Determine clock frequency according to clock register values */
switch (LPC_SYSCON->MAINCLKSELB & 0x03) {
case 0: /* MAINCLKSELA clock sel */
switch (LPC_SYSCON->MAINCLKSELA & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK;
break;
case 1: /* System oscillator */
SystemCoreClock = __SYS_OSC_CLK;
break;
case 2: /* Watchdog oscillator */
SystemCoreClock = __WDT_OSC_CLK;
break;
case 3: /* Reserved */
SystemCoreClock = 0;
break;
}
break;
case 1: /* Input Clock to System PLL */
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK;
break;
case 1: /* System oscillator */
SystemCoreClock = __SYS_OSC_CLK;
break;
case 2: /* Reserved */
case 3: /* Reserved */
SystemCoreClock = 0;
break;
}
break;
case 2: /* System PLL Clock Out */
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
break;
case 1: /* System oscillator */
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
break;
case 2: /* Reserved */
case 3: /* Reserved */
SystemCoreClock = 0;
break;
}
break;
case 3: /* WDT Oscillator */
SystemCoreClock = __WDT_OSC_CLK;
break;
}
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
*/
void SystemInit (void) {
#if (CLOCK_SETUP)
volatile uint32_t i;
#endif
#if (CLOCK_SETUP) /* Clock Setup */
#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
LPC_SYSCON->PDRUNCFG &= ~(1 << 21); /* Power-up sysosc */
for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
#endif
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
#if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
#if (((MAINCLKSELA_Val & 0x03) == 1) )
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
LPC_SYSCON->PDRUNCFG &= ~(1 << 21); /* Power-up sysosc */
for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
#endif
#if (((MAINCLKSELA_Val & 0x03) == 2) )
LPC_SYSCON->PDRUNCFG &= ~(1 << 20); /* Power-up WDT Clock */
for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
#endif
#if ((MAINCLKSELB_Val & 0x03) == 3)
LPC_SYSCON->RTCOSCCTRL = (1 << 0); /* Enable 32 kHz output */
for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
#endif
LPC_SYSCON->MAINCLKSELA = MAINCLKSELA_Val; /* select MAINCLKA clock */
#if ((MAINCLKSELB_Val & 0x03) == 2) /* Main Clock is PLL Out */
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
LPC_SYSCON->PDRUNCFG &= ~(1 << 22); /* Power-up SYSPLL */
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
#endif
LPC_SYSCON->MAINCLKSELB = MAINCLKSELB_Val; /* select Main clock */
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
#endif /* Clock Setup via Register */
#if (CLOCK_SETUP_API == 1) /* Clock Setup via PLL API */
// LPC_SYSCON->SYSPLLCLKSEL = 0x00; /* Use IRC */
LPC_SYSCON->MAINCLKSELB = (1 << 2); /* Select System PLL output */
LPC_SYSCON->SYSAHBCLKDIV = 1;
setPLL(PLL_API_MODE_Val, __SYS_PLLCLKIN / 1000, PLL_API_FREQ_Val / 1000);
#endif /* Clock Setup via PLL API */
#if (USB_CLOCK_SETUP == 1) /* USB clock is used */
LPC_SYSCON->PDRUNCFG &= ~(1 << 9); /* Power-up USB PHY */
#if ((USBCLKSEL_Val & 0x003) == 2) /* USB clock is USB PLL out */
LPC_SYSCON->PDRUNCFG &= ~(1 << 23); /* Power-up USB PLL */
LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
LPC_SYSCON->USBCLKSEL = 0x02; /* Select USB PLL */
#endif
LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
#else /* USB clock is not used */
LPC_SYSCON->PDRUNCFG |= (1 << 9); /* Power-down USB PHY */
LPC_SYSCON->PDRUNCFG |= (1 << 23); /* Power-down USB PLL */
#endif
#if (SCT_CLOCK_SETUP == 1) /* SCT clock is used */
LPC_SYSCON->PDRUNCFG &= ~(1 << 24); /* Power-up SCT PLL */
LPC_SYSCON->SCTPLLCLKSEL = SCTPLLCLKSEL_Val; /* Select PLL Input */
LPC_SYSCON->SCTPLLCTRL = SCTPLLCTRL_Val;
while (!(LPC_SYSCON->SCTPLLSTAT & 0x01)); /* Wait Until PLL Locked */
#else /* SCT clock is not used */
LPC_SYSCON->PDRUNCFG |= (1 << 24); /* Power-down SCT PLL */
#endif
#endif /* Clock Setup */
LPC_SYSCON->SYSAHBCLKCTRL0 |= (1UL << 12); /* enable clock for SWM */
}

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targets/TARGET_NXP/TARGET_LPC15XX/device/system_LPC15xx.h
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@ -1,72 +0,0 @@
/**************************************************************************//**
* @file system_LPC15xx.h
* @brief CMSIS Cortex-M3 Device System Header File for
* NXP LPC15xx Device Series
* @version V1.00
* @date 19. July 2013
*
* @note
* Copyright (C) 2013 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __SYSTEM_LPC15xx_H
#define __SYSTEM_LPC15xx_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/** @addtogroup LPC15xx_System
* @{
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
#endif /* __SYSTEM_LPC15xx_H */

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targets/TARGET_NXP/TARGET_LPC15XX/gpio_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "gpio_api.h"
#include "pinmap.h"
static int gpio_enabled = 0;
static void gpio_enable(void) {
gpio_enabled = 1;
/* Enable AHB clock to the GPIO0/1/2 and IOCON domain. */
LPC_SYSCON->SYSAHBCLKCTRL0 |= (0xFUL << 13);
}
uint32_t gpio_set(PinName pin) {
MBED_ASSERT(pin != (PinName)NC);
if (!gpio_enabled)
gpio_enable();
return (1UL << ((int)pin & 0x1f));
}
void gpio_init(gpio_t *obj, PinName pin) {
obj->pin = pin;
if (pin == (PinName)NC)
return;
obj->mask = gpio_set(pin);
unsigned int port = (unsigned int)(pin >> 5);
obj->reg_set = &LPC_GPIO_PORT->SET[port];
obj->reg_clr = &LPC_GPIO_PORT->CLR[port];
obj->reg_in = &LPC_GPIO_PORT->PIN[port];
obj->reg_dir = &LPC_GPIO_PORT->DIR[port];
}
void gpio_mode(gpio_t *obj, PinMode mode) {
pin_mode(obj->pin, mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction) {
MBED_ASSERT(obj->pin != (PinName)NC);
switch (direction) {
case PIN_INPUT :
*obj->reg_dir &= ~obj->mask;
break;
case PIN_OUTPUT:
*obj->reg_dir |= obj->mask;
break;
}
}

139
targets/TARGET_NXP/TARGET_LPC15XX/gpio_irq_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "cmsis.h"
#include "gpio_irq_api.h"
#include "mbed_error.h"
#define CHANNEL_NUM 8
#define LPC_GPIO_X LPC_PINT
#define PININT_IRQ PIN_INT0_IRQn
static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler irq_handler;
static inline void handle_interrupt_in(uint32_t channel) {
uint32_t ch_bit = (1 << channel);
// Return immediately if:
// * The interrupt was already served
// * There is no user handler
// * It is a level interrupt, not an edge interrupt
if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
(channel_ids[channel] == 0 ) ||
(LPC_GPIO_X->ISEL & ch_bit ) ) return;
if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE);
LPC_GPIO_X->RISE = ch_bit;
}
if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_FALL);
LPC_GPIO_X->FALL = ch_bit;
}
LPC_GPIO_X->IST = ch_bit;
}
void gpio_irq0(void) {handle_interrupt_in(0);}
void gpio_irq1(void) {handle_interrupt_in(1);}
void gpio_irq2(void) {handle_interrupt_in(2);}
void gpio_irq3(void) {handle_interrupt_in(3);}
void gpio_irq4(void) {handle_interrupt_in(4);}
void gpio_irq5(void) {handle_interrupt_in(5);}
void gpio_irq6(void) {handle_interrupt_in(6);}
void gpio_irq7(void) {handle_interrupt_in(7);}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
// PINT only supprt GPIO port 0 and 1 interrupt
if (pin >= P2_0) return -1;
irq_handler = handler;
int found_free_channel = 0;
int i = 0;
for (i=0; i<CHANNEL_NUM; i++) {
if (channel_ids[i] == 0) {
channel_ids[i] = id;
obj->ch = i;
found_free_channel = 1;
break;
}
}
if (!found_free_channel) return -1;
/* Enable AHB clock to the PIN, GPIO0/1, IOCON and MUX domain. */
LPC_SYSCON->SYSAHBCLKCTRL0 |= ((1 << 18) | (0x1D << 11));
LPC_INMUX->PINTSEL[obj->ch] = pin;
// Interrupt Wake-Up Enable
LPC_SYSCON->STARTERP0 |= (1 << (obj->ch + 5));
LPC_GPIO_PORT->DIR[pin >> 5] &= ~(1 << (pin & 0x1F));
void (*channels_irq)(void) = NULL;
switch (obj->ch) {
case 0: channels_irq = &gpio_irq0; break;
case 1: channels_irq = &gpio_irq1; break;
case 2: channels_irq = &gpio_irq2; break;
case 3: channels_irq = &gpio_irq3; break;
case 4: channels_irq = &gpio_irq4; break;
case 5: channels_irq = &gpio_irq5; break;
case 6: channels_irq = &gpio_irq6; break;
case 7: channels_irq = &gpio_irq7; break;
}
NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
return 0;
}
void gpio_irq_free(gpio_irq_t *obj) {
channel_ids[obj->ch] = 0;
LPC_SYSCON->STARTERP0 &= ~(1 << (obj->ch + 5));
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
unsigned int ch_bit = (1 << obj->ch);
// Clear interrupt
if (!(LPC_GPIO_X->ISEL & ch_bit))
LPC_GPIO_X->IST = ch_bit;
// Edge trigger
LPC_GPIO_X->ISEL &= ~ch_bit;
if (event == IRQ_RISE) {
if (enable) {
LPC_GPIO_X->IENR |= ch_bit;
} else {
LPC_GPIO_X->IENR &= ~ch_bit;
}
} else {
if (enable) {
LPC_GPIO_X->IENF |= ch_bit;
} else {
LPC_GPIO_X->IENF &= ~ch_bit;
}
}
}
void gpio_irq_enable(gpio_irq_t *obj) {
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
}
void gpio_irq_disable(gpio_irq_t *obj) {
NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
}

57
targets/TARGET_NXP/TARGET_LPC15XX/gpio_object.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#include "mbed_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
PinName pin;
uint32_t mask;
__IO uint32_t *reg_dir;
__IO uint32_t *reg_set;
__IO uint32_t *reg_clr;
__I uint32_t *reg_in;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value) {
MBED_ASSERT(obj->pin != (PinName)NC);
if (value)
*obj->reg_set = obj->mask;
else
*obj->reg_clr = obj->mask;
}
static inline int gpio_read(gpio_t *obj) {
MBED_ASSERT(obj->pin != (PinName)NC);
return ((*obj->reg_in & obj->mask) ? 1 : 0);
}
static inline int gpio_is_connected(const gpio_t *obj) {
return obj->pin != (PinName)NC;
}
#ifdef __cplusplus
}
#endif
#endif

254
targets/TARGET_NXP/TARGET_LPC15XX/i2c_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "i2c_api.h"
#if DEVICE_I2C
#include "cmsis.h"
#include "pinmap.h"
static uint8_t repeated_start = 0;
#define I2C_STAT(x) ((LPC_I2C0->STAT >> 1) & (0x07))
static const PinMap PinMap_I2C_SDA[] = {
{P0_23, 0, 0},
{NC, NC, 0}
};
static const PinMap PinMap_I2C_SCL[] = {
{P0_22, 0, 0},
{NC, NC, 0}
};
static inline int i2c_status(i2c_t *obj) {
return I2C_STAT(obj);
}
// Wait until the Serial Interrupt (SI) is set
static int i2c_wait_SI(i2c_t *obj) {
volatile int timeout = 0;
while (!(LPC_I2C0->STAT & (1 << 0))) {
timeout++;
if (timeout > 100000) return -1;
}
return 0;
}
static inline void i2c_interface_enable(i2c_t *obj) {
LPC_I2C0->CFG |= (1 << 0);
}
void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
MBED_ASSERT((sda == P0_23) && (scl == P0_22));
// Enables clock for I2C0
LPC_SYSCON->SYSAHBCLKCTRL1 |= (1 << 13);
LPC_SYSCON->PRESETCTRL1 |= (1 << 13);
LPC_SYSCON->PRESETCTRL1 &= ~(1 << 13);
// pin enable
LPC_SWM->PINENABLE1 &= ~(0x3 << 3);
// set default frequency at 100kHz
i2c_frequency(obj, 100000);
i2c_interface_enable(obj);
}
inline int i2c_start(i2c_t *obj) {
int status = 0;
if (repeated_start) {
LPC_I2C0->MSTCTL = (1 << 1) | (1 << 0);
repeated_start = 0;
} else {
LPC_I2C0->MSTCTL = (1 << 1);
}
return status;
}
inline int i2c_stop(i2c_t *obj) {
volatile int timeout = 0;
LPC_I2C0->MSTCTL = (1 << 2) | (1 << 0);
while ((LPC_I2C0->STAT & ((1 << 0) | (7 << 1))) != ((1 << 0) | (0 << 1))) {
timeout ++;
if (timeout > 100000) return 1;
}
return 0;
}
static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
// write the data
LPC_I2C0->MSTDAT = value;
if (!addr)
LPC_I2C0->MSTCTL = (1 << 0);
// wait and return status
i2c_wait_SI(obj);
return i2c_status(obj);
}
static inline int i2c_do_read(i2c_t *obj, int last) {
// wait for it to arrive
i2c_wait_SI(obj);
if (!last)
LPC_I2C0->MSTCTL = (1 << 0);
// return the data
return (LPC_I2C0->MSTDAT & 0xFF);
}
void i2c_frequency(i2c_t *obj, int hz) {
// No peripheral clock divider on the M0
uint32_t PCLK = SystemCoreClock;
uint32_t clkdiv = PCLK / (hz * 4) - 1;
LPC_I2C0->DIV = clkdiv;
LPC_I2C0->MSTTIME = 0;
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
int count, status;
i2c_start(obj);
LPC_I2C0->MSTDAT = (address | 0x01);
LPC_I2C0->MSTCTL |= 0x20;
if (i2c_wait_SI(obj) == -1)
return -1;
status = ((LPC_I2C0->STAT >> 1) & (0x07));
if (status != 0x01) {
i2c_stop(obj);
return I2C_ERROR_NO_SLAVE;
}
// Read in all except last byte
for (count = 0; count < (length - 1); count++) {
if (i2c_wait_SI(obj) == -1)
return -1;
LPC_I2C0->MSTCTL = (1 << 0);
data[count] = (LPC_I2C0->MSTDAT & 0xFF);
status = ((LPC_I2C0->STAT >> 1) & (0x07));
if (status != 0x01) {
i2c_stop(obj);
return count;
}
}
// read in last byte
if (i2c_wait_SI(obj) == -1)
return -1;
data[count] = (LPC_I2C0->MSTDAT & 0xFF);
status = i2c_status(obj);
if (status != 0x01) {
i2c_stop(obj);
return length - 1;
}
// If not repeated start, send stop.
if (stop) {
i2c_stop(obj);
} else {
repeated_start = 1;
}
return length;
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
int i, status;
i2c_start(obj);
LPC_I2C0->MSTDAT = (address & 0xFE);
LPC_I2C0->MSTCTL |= 0x20;
if (i2c_wait_SI(obj) == -1)
return -1;
status = ((LPC_I2C0->STAT >> 1) & (0x07));
if (status != 0x02) {
i2c_stop(obj);
return I2C_ERROR_NO_SLAVE;
}
for (i=0; i<length; i++) {
LPC_I2C0->MSTDAT = data[i];
LPC_I2C0->MSTCTL = (1 << 0);
if (i2c_wait_SI(obj) == -1)
return -1;
status = ((LPC_I2C0->STAT >> 1) & (0x07));
if (status != 0x02) {
i2c_stop(obj);
return i;
}
}
// If not repeated start, send stop.
if (stop) {
i2c_stop(obj);
} else {
repeated_start = 1;
}
return length;
}
void i2c_reset(i2c_t *obj) {
i2c_stop(obj);
}
int i2c_byte_read(i2c_t *obj, int last) {
return (i2c_do_read(obj, last) & 0xFF);
}
int i2c_byte_write(i2c_t *obj, int data) {
if (i2c_do_write(obj, (data & 0xFF), 0) == 2) {
return 1;
} else {
return 0;
}
}
const PinMap *i2c_master_sda_pinmap()
{
return PinMap_I2C_SDA;
}
const PinMap *i2c_master_scl_pinmap()
{
return PinMap_I2C_SCL;
}
const PinMap *i2c_slave_sda_pinmap()
{
return PinMap_I2C_SDA;
}
const PinMap *i2c_slave_scl_pinmap()
{
return PinMap_I2C_SCL;
}
#endif // #if DEVICE_I2C

69
targets/TARGET_NXP/TARGET_LPC15XX/objects.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
struct gpio_irq_s {
uint32_t ch;
};
struct pwmout_s {
LPC_SCT0_Type* pwm;
uint32_t pwm_ch;
};
struct serial_s {
LPC_USART0_Type *uart;
unsigned char index;
};
struct analogin_s {
ADCName adc;
};
struct dac_s {
DACName dac;
};
struct i2c_s {
LPC_I2C0_Type *i2c;
};
struct spi_s {
LPC_SPI0_Type *spi;
unsigned char spi_n;
};
struct can_s {
int index;
};
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif
#endif

41
targets/TARGET_NXP/TARGET_LPC15XX/pinmap.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "pinmap.h"
#include "mbed_error.h"
void pin_function(PinName pin, int function) {
}
void pin_mode(PinName pin, PinMode mode) {
MBED_ASSERT(pin != (PinName)NC);
if ((pin == P0_22) || (pin == P0_23)) {
// The true open-drain pins PIO0_22 and PIO0_23 can be configured for different I2C-bus speeds.
return;
}
__IO uint32_t *reg = (__IO uint32_t*)(LPC_IOCON_BASE + (pin * 4));
if (mode == OpenDrain) {
*reg |= (1 << 10);
} else {
uint32_t tmp = *reg;
tmp &= ~(0x3 << 3);
tmp |= (mode & 0x3) << 3;
*reg = tmp;
}
}

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targets/TARGET_NXP/TARGET_LPC15XX/pwmout_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "pwmout_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
static LPC_SCT0_Type *SCTs[4] = {
(LPC_SCT0_Type*)LPC_SCT0,
(LPC_SCT0_Type*)LPC_SCT1,
(LPC_SCT0_Type*)LPC_SCT2,
(LPC_SCT0_Type*)LPC_SCT3,
};
// Pinmap used for testing only
static const PinMap PinMap_PWM_testing[] = {
{P0_0, 0, 0},
{P0_1, 0, 0},
{P0_2, 0, 0},
{P0_3, 0, 0},
{P0_4, 0, 0},
{P0_5, 0, 0},
{P0_6, 0, 0},
{P0_7, 0, 0},
{P0_8, 0, 0},
{P0_9, 0, 0},
{P0_10, 0, 0},
{P0_11, 0, 0},
{P0_12, 0, 0},
{P0_13, 0, 0},
{P0_14, 0, 0},
{P0_15, 0, 0},
{P0_16, 0, 0},
{P0_17, 0, 0},
{P0_18, 0, 0},
{P0_19, 0, 0},
{P0_20, 0, 0},
{P0_21, 0, 0},
{P0_22, 0, 0},
{P0_23, 0, 0},
{P0_24, 0, 0},
{P0_25, 0, 0},
{P0_26, 0, 0},
{P0_27, 0, 0},
{P0_28, 0, 0},
{P0_29, 0, 0},
{P0_30, 0, 0},
{P0_31, 0, 0},
{P1_0, 0, 0},
{P1_1, 0, 0},
{P1_2, 0, 0},
{P1_3, 0, 0},
{P1_4, 0, 0},
{P1_5, 0, 0},
{P1_6, 0, 0},
{P1_7, 0, 0},
{P1_8, 0, 0},
{P1_9, 0, 0},
{P1_10, 0, 0},
{P1_11, 0, 0},
{P1_12, 0, 0},
{P1_13, 0, 0},
{P1_14, 0, 0},
{P1_15, 0, 0},
{P1_16, 0, 0},
{P1_17, 0, 0},
{P1_18, 0, 0},
{P1_19, 0, 0},
{P1_20, 0, 0},
{P1_21, 0, 0},
{P1_22, 0, 0},
{P1_23, 0, 0},
{P1_24, 0, 0},
{P1_25, 0, 0},
{P1_26, 0, 0},
{P1_27, 0, 0},
{P1_28, 0, 0},
{P1_29, 0, 0},
{P1_30, 0, 0},
{P1_31, 0, 0},
{P2_0, 0, 0},
{P2_1, 0, 0},
{P2_2, 0, 0},
{P2_3, 0, 0},
{P2_4, 0, 0},
{P2_5, 0, 0},
{P2_6, 0, 0},
{P2_7, 0, 0},
{P2_8, 0, 0},
{P2_9, 0, 0},
{P2_10, 0, 0},
{P2_11, 0, 0},
{P2_12, 0, 0},
{NC, NC, 0}
};
// bit flags for used SCTs
static unsigned char sct_used = (1 << 3);
static int get_available_sct(void) {
int i;
for (i=0; i<4; i++) {
if ((sct_used & (1 << i)) == 0)
return i;
}
return -1;
}
void pwmout_init(pwmout_t* obj, PinName pin) {
MBED_ASSERT(pin != (uint32_t)NC);
int sct_n = get_available_sct();
if (sct_n == -1) {
error("No available SCT");
}
sct_used |= (1 << sct_n);
obj->pwm = SCTs[sct_n];
obj->pwm_ch = sct_n;
LPC_SCT0_Type* pwm = obj->pwm;
// Enable the SCT clock
LPC_SYSCON->SYSAHBCLKCTRL1 |= (1 << (obj->pwm_ch + 2));
// Clear peripheral reset the SCT:
LPC_SYSCON->PRESETCTRL1 |= (1 << (obj->pwm_ch + 2));
LPC_SYSCON->PRESETCTRL1 &= ~(1 << (obj->pwm_ch + 2));
switch(obj->pwm_ch) {
case 0:
// SCT0_OUT0
LPC_SWM->PINASSIGN[7] &= ~0x0000FF00;
LPC_SWM->PINASSIGN[7] |= (pin << 8);
break;
case 1:
// SCT1_OUT0
LPC_SWM->PINASSIGN[8] &= ~0x000000FF;
LPC_SWM->PINASSIGN[8] |= (pin);
break;
case 2:
// SCT2_OUT0
LPC_SWM->PINASSIGN[8] &= ~0xFF000000;
LPC_SWM->PINASSIGN[8] |= (pin << 24);
break;
case 3:
// SCT3_OUT0
LPC_SWM->PINASSIGN[9] &= ~0x00FF0000;
LPC_SWM->PINASSIGN[9] |= (pin << 16);
break;
default:
break;
}
// Unified 32-bit counter, autolimit
pwm->CONFIG |= ((0x3 << 17) | 0x01);
// halt and clear the counter
pwm->CTRL |= (1 << 2) | (1 << 3);
pwm->OUT0_SET = (1 << 0); // event 0
pwm->OUT0_CLR = (1 << 1); // event 1
// Resolve conflicts on output 0 to set output
// This allows duty cycle = 1.0 to work, where the MATCH registers for set and clear are equal
pwm->RES = 0x01;
pwm->EV0_CTRL = (1 << 12);
pwm->EV0_STATE = 0xFFFFFFFF;
pwm->EV1_CTRL = (1 << 12) | (1 << 0);
pwm->EV1_STATE = 0xFFFFFFFF;
// default to 20ms: standard for servos, and fine for e.g. brightness control
pwmout_period_ms(obj, 20);
pwmout_write (obj, 0);
}
void pwmout_free(pwmout_t* obj) {
// Disable the SCT clock
LPC_SYSCON->SYSAHBCLKCTRL1 &= ~(1 << (obj->pwm_ch + 2));
sct_used &= ~(1 << obj->pwm_ch);
}
void pwmout_write(pwmout_t* obj, float value) {
LPC_SCT0_Type* pwm = obj->pwm;
if (value < 0.0f) {
value = 0.0;
} else if (value > 1.0f) {
value = 1.0;
}
uint32_t t_on = (uint32_t)((float)(pwm->MATCHREL0 + 1) * value);
if (t_on > 0) {
pwm->MATCHREL1 = t_on - 1;
// Un-halt the timer and ensure the new pulse-width takes immediate effect if necessary
if (pwm->CTRL & (1 << 2)) {
pwm->MATCH1 = pwm->MATCHREL1;
pwm->CTRL &= ~(1 << 2);
}
} else {
// Halt the timer and force the output low
pwm->CTRL |= (1 << 2) | (1 << 3);
pwm->OUTPUT = 0x00000000;
}
}
float pwmout_read(pwmout_t* obj) {
LPC_SCT0_Type* pwm = obj->pwm;
uint32_t t_off = pwm->MATCHREL0 + 1;
uint32_t t_on = (!(pwm->CTRL & (1 << 2))) ? pwm->MATCHREL1 + 1 : 0;
float v = (float)t_on/(float)t_off;
return (v > 1.0f) ? (1.0f) : (v);
}
void pwmout_period(pwmout_t* obj, float seconds) {
pwmout_period_us(obj, seconds * 1000000.0f);
}
void pwmout_period_ms(pwmout_t* obj, int ms) {
pwmout_period_us(obj, ms * 1000);
}
// Set the PWM period, keeping the duty cycle the same.
void pwmout_period_us(pwmout_t* obj, int us) {
LPC_SCT0_Type* pwm = obj->pwm;
uint32_t t_off = pwm->MATCHREL0 + 1;
uint32_t t_on = (!(pwm->CTRL & (1 << 2))) ? pwm->MATCHREL1 + 1 : 0;
float v = (float)t_on/(float)t_off;
uint32_t period_ticks = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000);
uint32_t pulsewidth_ticks = period_ticks * v;
pwm->MATCHREL0 = period_ticks - 1;
if (pulsewidth_ticks > 0) {
pwm->MATCHREL1 = pulsewidth_ticks - 1;
// Un-halt the timer and ensure the new period & pulse-width take immediate effect if necessary
if (pwm->CTRL & (1 << 2)) {
pwm->MATCH0 = pwm->MATCHREL0;
pwm->MATCH1 = pwm->MATCHREL1;
pwm->CTRL &= ~(1 << 2);
}
} else {
// Halt the timer and force the output low
pwm->CTRL |= (1 << 2) | (1 << 3);
pwm->OUTPUT = 0x00000000;
// Ensure the new period will take immediate effect when the timer is un-halted
pwm->MATCH0 = pwm->MATCHREL0;
}
}
void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
pwmout_pulsewidth_us(obj, ms * 1000);
}
void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
LPC_SCT0_Type* pwm = obj->pwm;
if (us > 0) {
pwm->MATCHREL1 = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000) - 1;
// Un-halt the timer and ensure the new pulse-width takes immediate effect if necessary
if (pwm->CTRL & (1 << 2)) {
pwm->MATCH1 = pwm->MATCHREL1;
pwm->CTRL &= ~(1 << 2);
}
} else {
// Halt the timer and force the output low
pwm->CTRL |= (1 << 2) | (1 << 3);
pwm->OUTPUT = 0x00000000;
}
}
const PinMap *pwmout_pinmap()
{
return PinMap_PWM_testing;
}

64
targets/TARGET_NXP/TARGET_LPC15XX/rtc_api.c
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@ -1,64 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "rtc_api.h"
#if DEVICE_RTC
void rtc_init(void)
{
// Enables clock for RTC
LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 23);
// Software reset
LPC_RTC->CTRL |= 1;
LPC_RTC->COUNT = 0;
// Enabled RTC
LPC_RTC->CTRL |= (1 << 7);
// clear reset
LPC_RTC->CTRL &= ~1;
}
void rtc_free(void)
{
LPC_SYSCON->SYSAHBCLKCTRL0 &= ~(1 << 23);
LPC_RTC->CTRL &= ~(1 << 7);
}
int rtc_isenabled(void)
{
return (((LPC_RTC->CTRL) & 0x80) != 0);
}
time_t rtc_read(void)
{
return (time_t)LPC_RTC->COUNT;
}
void rtc_write(time_t t)
{
// Disabled RTC
LPC_RTC->CTRL &= ~(1 << 7);
// Set count
LPC_RTC->COUNT = t;
//Enabled RTC
LPC_RTC->CTRL |= (1 << 7);
}
#endif

419
targets/TARGET_NXP/TARGET_LPC15XX/serial_api.c
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@ -1,419 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// math.h required for floating point operations for baud rate calculation
#include "mbed_assert.h"
#include <math.h>
#include <string.h>
#include "serial_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
/******************************************************************************
* INITIALIZATION
******************************************************************************/
#define UART_NUM 3
static const SWM_Map SWM_UART_TX[] = {
{0, 0}, // Pin assign register0, 7:0bit
{1, 8}, // Pin assign register1, 15:8bit
{2, 16}, // Pin assign register2, 23:16bit
};
static const SWM_Map SWM_UART_RX[] = {
{0, 8},
{1, 16},
{2, 24},
};
static const SWM_Map SWM_UART_RTS[] = {
{0, 16},
{1, 24},
{3, 0}, // not available
};
static const SWM_Map SWM_UART_CTS[] = {
{0, 24},
{2, 0},
{3, 8} // not available
};
// Pinmap used for testing only
static const PinMap PinMap_UART_testing[] = {
{P0_0, 0, 0},
{P0_1, 0, 0},
{P0_2, 0, 0},
{P0_3, 0, 0},
{P0_4, 0, 0},
{P0_5, 0, 0},
{P0_6, 0, 0},
{P0_7, 0, 0},
{P0_8, 0, 0},
{P0_9, 0, 0},
{P0_10, 0, 0},
{P0_11, 0, 0},
{P0_12, 0, 0},
{P0_13, 0, 0},
{P0_14, 0, 0},
{P0_15, 0, 0},
{P0_16, 0, 0},
{P0_17, 0, 0},
{P0_18, 0, 0},
{P0_19, 0, 0},
{P0_20, 0, 0},
{P0_21, 0, 0},
{P0_22, 0, 0},
{P0_23, 0, 0},
{P0_24, 0, 0},
{P0_25, 0, 0},
{P0_26, 0, 0},
{P0_27, 0, 0},
{P0_28, 0, 0},
{P0_29, 0, 0},
{P0_30, 0, 0},
{P0_31, 0, 0},
{P1_0, 0, 0},
{P1_1, 0, 0},
{P1_2, 0, 0},
{P1_3, 0, 0},
{P1_4, 0, 0},
{P1_5, 0, 0},
{P1_6, 0, 0},
{P1_7, 0, 0},
{P1_8, 0, 0},
{P1_9, 0, 0},
{P1_10, 0, 0},
{P1_11, 0, 0},
{P1_12, 0, 0},
{P1_13, 0, 0},
{P1_14, 0, 0},
{P1_15, 0, 0},
{P1_16, 0, 0},
{P1_17, 0, 0},
{P1_18, 0, 0},
{P1_19, 0, 0},
{P1_20, 0, 0},
{P1_21, 0, 0},
{P1_22, 0, 0},
{P1_23, 0, 0},
{P1_24, 0, 0},
{P1_25, 0, 0},
{P1_26, 0, 0},
{P1_27, 0, 0},
{P1_28, 0, 0},
{P1_29, 0, 0},
{P1_30, 0, 0},
{P1_31, 0, 0},
{P2_0, 0, 0},
{P2_1, 0, 0},
{P2_2, 0, 0},
{P2_3, 0, 0},
{P2_4, 0, 0},
{P2_5, 0, 0},
{P2_6, 0, 0},
{P2_7, 0, 0},
{P2_8, 0, 0},
{P2_9, 0, 0},
{P2_10, 0, 0},
{P2_11, 0, 0},
{P2_12, 0, 0},
{NC, NC, 0}
};
// bit flags for used UARTs
static unsigned char uart_used = 0;
static int get_available_uart(void) {
int i;
for (i=0; i<3; i++) {
if ((uart_used & (1 << i)) == 0)
return i;
}
return -1;
}
#define UART_EN (0x01<<0)
#define CTS_DELTA (0x01<<5)
#define RXBRK (0x01<<10)
#define DELTA_RXBRK (0x01<<11)
#define RXRDY (0x01<<0)
#define TXRDY (0x01<<2)
#define TXBRKEN (0x01<<1)
#define CTSEN (0x01<<9)
static uint32_t UARTSysClk;
static uint32_t serial_irq_ids[UART_NUM] = {0};
static uart_irq_handler irq_handler;
int stdio_uart_inited = 0;
serial_t stdio_uart;
static void switch_pin(const SWM_Map *swm, PinName pn)
{
uint32_t regVal;
if (pn != NC)
{
// check if we have any function mapped to this pin already and remove it
for (uint32_t n = 0; n < sizeof(LPC_SWM->PINASSIGN)/sizeof(*LPC_SWM->PINASSIGN); n ++) {
regVal = LPC_SWM->PINASSIGN[n];
for (uint32_t j = 0; j <= 24; j += 8) {
if (((regVal >> j) & 0xFF) == (uint32_t)pn)
regVal |= (0xFF << j);
}
LPC_SWM->PINASSIGN[n] = regVal;
}
}
// now map it
regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
LPC_SWM->PINASSIGN[swm->n] = regVal | (pn << swm->offset);
}
void serial_init(serial_t *obj, PinName tx, PinName rx) {
int is_stdio_uart = 0;
int uart_n = get_available_uart();
if (uart_n == -1) {
error("No available UART");
}
obj->index = uart_n;
switch (uart_n) {
case 0: obj->uart = (LPC_USART0_Type *)LPC_USART0_BASE; break;
case 1: obj->uart = (LPC_USART0_Type *)LPC_USART1_BASE; break;
case 2: obj->uart = (LPC_USART0_Type *)LPC_USART2_BASE; break;
}
uart_used |= (1 << uart_n);
switch_pin(&SWM_UART_TX[uart_n], tx);
switch_pin(&SWM_UART_RX[uart_n], rx);
/* uart clock divided by 6 */
LPC_SYSCON->UARTCLKDIV =6;
/* disable uart interrupts */
NVIC_DisableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
/* Enable UART clock */
LPC_SYSCON->SYSAHBCLKCTRL1 |= (1 << (17 + uart_n));
/* Peripheral reset control to UART, a "1" bring it out of reset. */
LPC_SYSCON->PRESETCTRL1 |= (0x1 << (17 + uart_n));
LPC_SYSCON->PRESETCTRL1 &= ~(0x1 << (17 + uart_n));
UARTSysClk = SystemCoreClock / LPC_SYSCON->UARTCLKDIV;
// set default baud rate and format
serial_baud (obj, 9600);
serial_format(obj, 8, ParityNone, 1);
/* Clear all status bits. */
obj->uart->STAT = CTS_DELTA | DELTA_RXBRK;
/* enable uart interrupts */
NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
/* Enable UART */
obj->uart->CFG |= UART_EN;
is_stdio_uart = ((tx == USBTX) && (rx == USBRX));
if (is_stdio_uart) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj) {
uart_used &= ~(1 << obj->index);
serial_irq_ids[obj->index] = 0;
}
// serial_baud
// set the baud rate, taking in to account the current SystemFrequency
void serial_baud(serial_t *obj, int baudrate) {
/* Integer divider:
BRG = UARTSysClk/(Baudrate * 16) - 1
Frational divider:
FRG = ((UARTSysClk / (Baudrate * 16 * (BRG + 1))) - 1)
where
FRG = (LPC_SYSCON->UARTFRDADD + 1) / (LPC_SYSCON->UARTFRDSUB + 1)
(1) The easiest way is set SUB value to 256, -1 encoded, thus SUB
register is 0xFF.
(2) In ADD register value, depending on the value of UartSysClk,
baudrate, BRG register value, and SUB register value, be careful
about the order of multiplier and divider and make sure any
multiplier doesn't exceed 32-bit boundary and any divider doesn't get
down below one(integer 0).
(3) ADD should be always less than SUB.
*/
obj->uart->BRG = UARTSysClk / 16 / baudrate - 1;
// To use of the fractional baud rate generator, you must write 0xFF to the DIV
// value to yield a denominator value of 256. All other values are not supported.
LPC_SYSCON->FRGCTRL = 0xFF;
LPC_SYSCON->FRGCTRL |= ( ( ((UARTSysClk / 16) * (0xFF + 1)) /
(baudrate * (obj->uart->BRG + 1))
) - (0xFF + 1) ) << 8;
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits
MBED_ASSERT((parity == ParityNone) || (parity == ParityEven) || (parity == ParityOdd));
stop_bits -= 1;
data_bits -= 7;
int paritysel = 0;
switch (parity) {
case ParityNone: paritysel = 0; break;
case ParityEven: paritysel = 2; break;
case ParityOdd : paritysel = 3; break;
default:
break;
}
// First disable the the usart as described in documentation and then enable while updating CFG
// 24.6.1 USART Configuration register
// Remark: If software needs to change configuration values, the following sequence should
// be used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable
// the USART by writing a 0 to the Enable bit (0 may be written to the entire register). 3)
// Write the new configuration value, with the ENABLE bit set to 1.
obj->uart->CFG &= ~(1 << 0);
obj->uart->CFG = (1 << 0) // this will enable the usart
| (data_bits << 2)
| (paritysel << 4)
| (stop_bits << 6);
}
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
static inline void uart_irq(SerialIrq irq_type, uint32_t index) {
if (serial_irq_ids[index] != 0)
irq_handler(serial_irq_ids[index], irq_type);
}
void uart0_irq() {uart_irq((LPC_USART0->INTSTAT & 1) ? RxIrq : TxIrq, 0);}
void uart1_irq() {uart_irq((LPC_USART1->INTSTAT & 1) ? RxIrq : TxIrq, 1);}
void uart2_irq() {uart_irq((LPC_USART2->INTSTAT & 1) ? RxIrq : TxIrq, 2);}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0;
switch ((int)obj->uart) {
case LPC_USART0_BASE: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
case LPC_USART1_BASE: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
case LPC_USART2_BASE: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
}
if (enable) {
NVIC_DisableIRQ(irq_n);
obj->uart->INTENSET |= (1 << ((irq == RxIrq) ? 0 : 2));
NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n);
} else { // disable
int all_disabled = 0;
SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
obj->uart->INTENCLR |= (1 << ((irq == RxIrq) ? 0 : 2)); // disable the interrupt
all_disabled = (obj->uart->INTENSET & (1 << ((other_irq == RxIrq) ? 0 : 2))) == 0;
if (all_disabled)
NVIC_DisableIRQ(irq_n);
}
}
/******************************************************************************
* READ/WRITE
******************************************************************************/
int serial_getc(serial_t *obj) {
while (!serial_readable(obj));
return obj->uart->RXDATA;
}
void serial_putc(serial_t *obj, int c) {
while (!serial_writable(obj));
obj->uart->TXDATA = c;
}
int serial_readable(serial_t *obj) {
return obj->uart->STAT & RXRDY;
}
int serial_writable(serial_t *obj) {
return obj->uart->STAT & TXRDY;
}
void serial_clear(serial_t *obj) {
// [TODO]
}
void serial_pinout_tx(PinName tx) {
}
void serial_break_set(serial_t *obj) {
obj->uart->CTRL |= TXBRKEN;
}
void serial_break_clear(serial_t *obj) {
obj->uart->CTRL &= ~TXBRKEN;
}
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
if ((FlowControlNone == type || FlowControlRTS == type)) txflow = NC;
if ((FlowControlNone == type || FlowControlCTS == type)) rxflow = NC;
switch_pin(&SWM_UART_RTS[obj->index], rxflow);
switch_pin(&SWM_UART_CTS[obj->index], txflow);
if (txflow == NC) obj->uart->CFG &= ~CTSEN;
else obj->uart->CFG |= CTSEN;
}
const PinMap *serial_tx_pinmap()
{
return PinMap_UART_testing;
}
const PinMap *serial_rx_pinmap()
{
return PinMap_UART_testing;
}
const PinMap *serial_cts_pinmap()
{
return PinMap_UART_testing;
}
const PinMap *serial_rts_pinmap()
{
return PinMap_UART_testing;
}

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targets/TARGET_NXP/TARGET_LPC15XX/spi_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include <math.h>
#include "spi_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
static const SWM_Map SWM_SPI_SSEL[] = {
{4, 0},
{5, 24},
};
static const SWM_Map SWM_SPI_SCLK[] = {
{3, 8},
{5, 0},
};
static const SWM_Map SWM_SPI_MOSI[] = {
{3, 16},
{5, 8},
};
static const SWM_Map SWM_SPI_MISO[] = {
{3, 24},
{5, 16},
};
// Pinmap used for testing only
static const PinMap PinMap_SPI_testing[] = {
{P0_0, 0, 0},
{P0_1, 0, 0},
{P0_2, 0, 0},
{P0_3, 0, 0},
{P0_4, 0, 0},
{P0_5, 0, 0},
{P0_6, 0, 0},
{P0_7, 0, 0},
{P0_8, 0, 0},
{P0_9, 0, 0},
{P0_10, 0, 0},
{P0_11, 0, 0},
{P0_12, 0, 0},
{P0_13, 0, 0},
{P0_14, 0, 0},
{P0_15, 0, 0},
{P0_16, 0, 0},
{P0_17, 0, 0},
{P0_18, 0, 0},
{P0_19, 0, 0},
{P0_20, 0, 0},
{P0_21, 0, 0},
{P0_22, 0, 0},
{P0_23, 0, 0},
{P0_24, 0, 0},
{P0_25, 0, 0},
{P0_26, 0, 0},
{P0_27, 0, 0},
{P0_28, 0, 0},
{P0_29, 0, 0},
{P0_30, 0, 0},
{P0_31, 0, 0},
{P1_0, 0, 0},
{P1_1, 0, 0},
{P1_2, 0, 0},
{P1_3, 0, 0},
{P1_4, 0, 0},
{P1_5, 0, 0},
{P1_6, 0, 0},
{P1_7, 0, 0},
{P1_8, 0, 0},
{P1_9, 0, 0},
{P1_10, 0, 0},
{P1_11, 0, 0},
{P1_12, 0, 0},
{P1_13, 0, 0},
{P1_14, 0, 0},
{P1_15, 0, 0},
{P1_16, 0, 0},
{P1_17, 0, 0},
{P1_18, 0, 0},
{P1_19, 0, 0},
{P1_20, 0, 0},
{P1_21, 0, 0},
{P1_22, 0, 0},
{P1_23, 0, 0},
{P1_24, 0, 0},
{P1_25, 0, 0},
{P1_26, 0, 0},
{P1_27, 0, 0},
{P1_28, 0, 0},
{P1_29, 0, 0},
{P1_30, 0, 0},
{P1_31, 0, 0},
{P2_0, 0, 0},
{P2_1, 0, 0},
{P2_2, 0, 0},
{P2_3, 0, 0},
{P2_4, 0, 0},
{P2_5, 0, 0},
{P2_6, 0, 0},
{P2_7, 0, 0},
{P2_8, 0, 0},
{P2_9, 0, 0},
{P2_10, 0, 0},
{P2_11, 0, 0},
{P2_12, 0, 0},
{NC, NC, 0}
};
// bit flags for used SPIs
static unsigned char spi_used = 0;
static int get_available_spi(PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
if (spi_used == 0) {
return 0; // The first user
}
const SWM_Map *swm;
uint32_t regVal;
// Investigate if same pins as the used SPI0/1 - to be able to reuse it
for (int spi_n = 0; spi_n < 2; spi_n++) {
if (spi_used & (1<<spi_n)) {
if (sclk != NC) {
swm = &SWM_SPI_SCLK[spi_n];
regVal = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
if (regVal != (sclk << swm->offset)) {
// Existing pin is not the same as the one we want
continue;
}
}
if (mosi != NC) {
swm = &SWM_SPI_MOSI[spi_n];
regVal = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
if (regVal != (mosi << swm->offset)) {
// Existing pin is not the same as the one we want
continue;
}
}
if (miso != NC) {
swm = &SWM_SPI_MISO[spi_n];
regVal = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
if (regVal != (miso << swm->offset)) {
// Existing pin is not the same as the one we want
continue;
}
}
if (ssel != NC) {
swm = &SWM_SPI_SSEL[spi_n];
regVal = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
if (regVal != (ssel << swm->offset)) {
// Existing pin is not the same as the one we want
continue;
}
}
// The pins for the currently used SPIx are the same as the
// ones we want so we will reuse it
return spi_n;
}
}
// None of the existing SPIx pin setups match the pins we want
// so the last hope is to select one unused SPIx
if ((spi_used & 1) == 0) {
return 0;
} else if ((spi_used & 2) == 0) {
return 1;
}
// No matching setup and no free SPIx
return -1;
}
static inline void spi_disable(spi_t *obj);
static inline void spi_enable(spi_t *obj);
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
int spi_n = get_available_spi(mosi, miso, sclk, ssel);
if (spi_n == -1) {
error("No available SPI");
}
obj->spi_n = spi_n;
spi_used |= (1 << spi_n);
obj->spi = (spi_n) ? (LPC_SPI0_Type *)(LPC_SPI1_BASE) : (LPC_SPI0_Type *)(LPC_SPI0_BASE);
const SWM_Map *swm;
uint32_t regVal;
if (sclk != NC) {
swm = &SWM_SPI_SCLK[obj->spi_n];
regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
LPC_SWM->PINASSIGN[swm->n] = regVal | (sclk << swm->offset);
}
if (mosi != NC) {
swm = &SWM_SPI_MOSI[obj->spi_n];
regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
LPC_SWM->PINASSIGN[swm->n] = regVal | (mosi << swm->offset);
}
if (miso != NC) {
swm = &SWM_SPI_MISO[obj->spi_n];
regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
LPC_SWM->PINASSIGN[swm->n] = regVal | (miso << swm->offset);
}
if (ssel != NC) {
swm = &SWM_SPI_SSEL[obj->spi_n];
regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
LPC_SWM->PINASSIGN[swm->n] = regVal | (ssel << swm->offset);
}
// clear interrupts
obj->spi->INTENCLR = 0x3f;
// enable power and clocking
LPC_SYSCON->SYSAHBCLKCTRL1 |= (0x1 << (obj->spi_n + 9));
LPC_SYSCON->PRESETCTRL1 |= (0x1 << (obj->spi_n + 9));
LPC_SYSCON->PRESETCTRL1 &= ~(0x1 << (obj->spi_n + 9));
}
void spi_free(spi_t *obj)
{
}
void spi_format(spi_t *obj, int bits, int mode, int slave)
{
spi_disable(obj);
MBED_ASSERT((bits >= 1 && bits <= 16) && (mode >= 0 && mode <= 3));
int polarity = (mode & 0x2) ? 1 : 0;
int phase = (mode & 0x1) ? 1 : 0;
// set it up
int LEN = bits - 1; // LEN - Data Length
int CPOL = (polarity) ? 1 : 0; // CPOL - Clock Polarity select
int CPHA = (phase) ? 1 : 0; // CPHA - Clock Phase select
uint32_t tmp = obj->spi->CFG;
tmp &= ~((1 << 5) | (1 << 4) | (1 << 2));
tmp |= (CPOL << 5) | (CPHA << 4) | ((slave ? 0 : 1) << 2);
obj->spi->CFG = tmp;
// select frame length
tmp = obj->spi->TXCTL;
tmp &= ~(0xf << 24);
tmp |= (LEN << 24);
obj->spi->TXCTL = tmp;
spi_enable(obj);
}
void spi_frequency(spi_t *obj, int hz)
{
spi_disable(obj);
// rise DIV value if it cannot be divided
obj->spi->DIV = (SystemCoreClock + (hz - 1))/hz - 1;
obj->spi->DLY = 0;
spi_enable(obj);
}
static inline void spi_disable(spi_t *obj)
{
obj->spi->CFG &= ~(1 << 0);
}
static inline void spi_enable(spi_t *obj)
{
obj->spi->CFG |= (1 << 0);
}
static inline int spi_readable(spi_t *obj)
{
return obj->spi->STAT & (1 << 0);
}
static inline int spi_writeable(spi_t *obj)
{
return obj->spi->STAT & (1 << 1);
}
static inline void spi_write(spi_t *obj, int value)
{
while (!spi_writeable(obj));
// end of transfer
obj->spi->TXCTL |= (1 << 20);
obj->spi->TXDAT = (value & 0xffff);
}
static inline int spi_read(spi_t *obj)
{
while (!spi_readable(obj));
return obj->spi->RXDAT & 0xffff; // Only the lower 16 bits contain data
}
int spi_busy(spi_t *obj)
{
// checking RXOV(Receiver Overrun interrupt flag)
return obj->spi->STAT & (1 << 2);
}
int spi_master_write(spi_t *obj, int value)
{
spi_write(obj, value);
return spi_read(obj);
}
int spi_master_block_write(spi_t *obj, const char *tx_buffer,
int tx_length, char *rx_buffer, int rx_length, char write_fill) {
int total = (tx_length > rx_length) ? tx_length : rx_length;
for (int i = 0; i < total; i++) {
char out = (i < tx_length) ? tx_buffer[i] : write_fill;
char in = spi_master_write(obj, out);
if (i < rx_length) {
rx_buffer[i] = in;
}
}
return total;
}
int spi_slave_receive(spi_t *obj)
{
return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
}
int spi_slave_read(spi_t *obj)
{
return obj->spi->RXDAT & 0xffff; // Only the lower 16 bits contain data
}
void spi_slave_write(spi_t *obj, int value)
{
while (spi_writeable(obj) == 0) ;
obj->spi->TXDAT = value;
}
const PinMap *spi_master_mosi_pinmap()
{
return PinMap_SPI_testing;
}
const PinMap *spi_master_miso_pinmap()
{
return PinMap_SPI_testing;
}
const PinMap *spi_master_clk_pinmap()
{
return PinMap_SPI_testing;
}
const PinMap *spi_master_cs_pinmap()
{
return PinMap_SPI_testing;
}
const PinMap *spi_slave_mosi_pinmap()
{
return PinMap_SPI_testing;
}
const PinMap *spi_slave_miso_pinmap()
{
return PinMap_SPI_testing;
}
const PinMap *spi_slave_clk_pinmap()
{
return PinMap_SPI_testing;
}
const PinMap *spi_slave_cs_pinmap()
{
return PinMap_SPI_testing;
}

93
targets/TARGET_NXP/TARGET_LPC15XX/us_ticker.c
View File

@ -1,93 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "us_ticker_api.h"
#include "PeripheralNames.h"
#include "mbed_critical.h"
#define US_TICKER_TIMER_IRQn SCT3_IRQn
int us_ticker_inited = 0;
void us_ticker_init(void) {
if (us_ticker_inited)
return;
us_ticker_inited = 1;
// Enable the SCT3 clock
LPC_SYSCON->SYSAHBCLKCTRL1 |= (1 << 5);
// Clear peripheral reset the SCT3
LPC_SYSCON->PRESETCTRL1 |= (1 << 5);
LPC_SYSCON->PRESETCTRL1 &= ~(1 << 5);
// Configure SCT3 as a 1MHz 32-bit counter with no auto limiting or match reload
char sctClkDiv = ((SystemCoreClock + 1000000 - 1) / 1000000) - 1;
LPC_SCT3->CONFIG = (1 << 7) | (1 << 0);
LPC_SCT3->CTRL = (sctClkDiv << 5) | (1 << 3) | (1 << 2);
// Configure SCT3 event 0 to fire on match register 0
LPC_SCT3->EV0_STATE = (1 << 0);
LPC_SCT3->EV0_CTRL = (0x1 << 12);
// Start SCT3
LPC_SCT3->CTRL &= ~(1 << 2);
// Set SCT3 interrupt vector
NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
}
uint32_t us_ticker_read() {
if (!us_ticker_inited)
us_ticker_init();
// Return SCT3 count value
return LPC_SCT3->COUNT;
}
void us_ticker_set_interrupt(timestamp_t timestamp) {
// Set SCT3 match register 0 (critical section)
core_util_critical_section_enter();
LPC_SCT3->CTRL |= (1 << 2);
LPC_SCT3->MATCH0 = (uint32_t)timestamp;
LPC_SCT3->CTRL &= ~(1 << 2);
core_util_critical_section_exit();
// Enable interrupt on SCT3 event 0
LPC_SCT3->EVEN = (1 << 0);
}
void us_ticker_fire_interrupt(void)
{
NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
}
void us_ticker_disable_interrupt(void) {
// Disable interrupt on SCT3 event 0
LPC_SCT3->EVEN = 0;
}
void us_ticker_clear_interrupt(void) {
// Clear SCT3 event 0 interrupt flag
LPC_SCT3->EVFLAG = (1 << 0);
}
void us_ticker_free(void)
{
}

1
targets/TARGET_NXP/TARGET_LPC81X/pwmout_api.c
View File

@ -115,7 +115,6 @@ void pwmout_init(pwmout_t* obj, PinName pin) {
// LPC81x has only one SCT and 4 Outputs
// LPC82x has only one SCT and 6 Outputs
// LPC1549 has 4 SCTs and 16 Outputs
switch(sct_n) {
case 0:
// SCTx_OUT0

6
targets/TARGET_NXP/mbed_rtx.h
View File

@ -41,12 +41,6 @@
#define INITIAL_SP (0x10001000UL)
#endif
#elif defined(TARGET_LPC1549)
#ifndef INITIAL_SP
#define INITIAL_SP (0x02009000UL)
#endif
#elif defined(TARGET_LPC1768)
#ifndef INITIAL_SP

39
targets/targets.json
View File

@ -347,45 +347,6 @@
],
"device_name": "LPC11U68JBD100"
},
"LPC1549": {
"supported_form_factors": [
"ARDUINO"
],
"core": "Cortex-M3",
"default_toolchain": "uARM",
"extra_labels": [
"NXP",
"LPC15XX"
],
"supported_toolchains": [
"uARM",
"GCC_ARM",
"IAR"
],
"inherits": [
"LPCTarget"
],
"detect_code": [
"1549"
],
"device_has": [
"ANALOGIN",
"ANALOGOUT",
"CAN",
"I2C",
"INTERRUPTIN",
"PWMOUT",
"SERIAL",
"SERIAL_FC",
"SPI",
"SPISLAVE"
],
"default_lib": "small",
"release_versions": [
"2"
],
"device_name": "LPC1549JBD64"
},
"LPC1768": {
"inherits": [
"LPCTarget"

1
tools/export/lpcxpresso/__init__.py
View File

@ -32,7 +32,6 @@ class LPCXpresso(Exporter):
'LPC11U35_501',
'UBLOX_C027',
'ARCH_PRO',
'LPC1549',
'LPC11U68',
'LPCCAPPUCCINO',
'LPC824',

69
tools/export/lpcxpresso/lpc1549_cproject.tmpl
View File

@ -1,69 +0,0 @@
{% extends "lpcxpresso/cproject_cortexm3_common.tmpl" %}
{% block startup_file %}cr_startup_lpc15xx.c{% endblock %}
{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
&lt;TargetConfig&gt;&#13;
&lt;Properties property_0="" property_2="LPC15xx_256K.cfx" property_3="NXP" property_4="LPC1549" property_count="5" version="70200"/&gt;&#13;
&lt;infoList vendor="NXP"&gt;&#13;
&lt;info chip="LPC1549" connectscript="LPC15RunBootRomConnect.scp" flash_driver="LPC15xx_256K.cfx" match_id="0x0" name="LPC1549" resetscript="LPC15RunBootRomReset.scp" stub="crt_emu_cm3_gen"&gt;&#13;
&lt;chip&gt;&#13;
&lt;name&gt;LPC1549&lt;/name&gt;&#13;
&lt;family&gt;LPC15xx&lt;/family&gt;&#13;
&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
&lt;memory id="RAM" type="RAM"/&gt;&#13;
&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
&lt;memoryInstance derived_from="Flash" id="MFlash256" location="0x0" size="0x40000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="Ram0_16" location="0x2000000" size="0x4000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="Ram1_16" location="0x2004000" size="0x4000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="Ram2_4" location="0x2008000" size="0x1000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC15_MPU" determined="infoFile" id="MPU" location="0xe000ed90"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC15_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC15_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC15_ITM" determined="infoFile" id="ITM" location="0xe0000000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x1c000000"/&gt;&#13;
&lt;peripheralInstance derived_from="DMA" determined="infoFile" id="DMA" location="0x1c004000"/&gt;&#13;
&lt;peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x1c00c000"/&gt;&#13;
&lt;peripheralInstance derived_from="CRC" determined="infoFile" id="CRC" location="0x1c010000"/&gt;&#13;
&lt;peripheralInstance derived_from="SCT0" determined="infoFile" id="SCT0" location="0x1c018000"/&gt;&#13;
&lt;peripheralInstance derived_from="SCT1" determined="infoFile" id="SCT1" location="0x1c01c000"/&gt;&#13;
&lt;peripheralInstance derived_from="SCT2" determined="infoFile" id="SCT2" location="0x1c020000"/&gt;&#13;
&lt;peripheralInstance derived_from="SCT3" determined="infoFile" id="SCT3" location="0x1c024000"/&gt;&#13;
&lt;peripheralInstance derived_from="ADC0" determined="infoFile" id="ADC0" location="0x40000000"/&gt;&#13;
&lt;peripheralInstance derived_from="DAC" determined="infoFile" id="DAC" location="0x40004000"/&gt;&#13;
&lt;peripheralInstance derived_from="ACMP" determined="infoFile" id="ACMP" location="0x40008000"/&gt;&#13;
&lt;peripheralInstance derived_from="INMUX" determined="infoFile" id="INMUX" location="0x40014000"/&gt;&#13;
&lt;peripheralInstance derived_from="RTC" determined="infoFile" id="RTC" location="0x40028000"/&gt;&#13;
&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x4002c000"/&gt;&#13;
&lt;peripheralInstance derived_from="SWM" determined="infoFile" id="SWM" location="0x40038000"/&gt;&#13;
&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x4003c000"/&gt;&#13;
&lt;peripheralInstance derived_from="USART0" determined="infoFile" id="USART0" location="0x40040000"/&gt;&#13;
&lt;peripheralInstance derived_from="USART1" determined="infoFile" id="USART1" location="0x40044000"/&gt;&#13;
&lt;peripheralInstance derived_from="SPI0" determined="infoFile" id="SPI0" location="0x40048000"/&gt;&#13;
&lt;peripheralInstance derived_from="SPI1" determined="infoFile" id="SPI1" location="0x4004c000"/&gt;&#13;
&lt;peripheralInstance derived_from="I2C0" determined="infoFile" id="I2C0" location="0x40050000"/&gt;&#13;
&lt;peripheralInstance derived_from="QEI" determined="infoFile" id="QEI" location="0x40058000"/&gt;&#13;
&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40074000"/&gt;&#13;
&lt;peripheralInstance derived_from="ADC1" determined="infoFile" id="ADC1" location="0x40080000"/&gt;&#13;
&lt;peripheralInstance derived_from="MRT" determined="infoFile" id="MRT" location="0x400a0000"/&gt;&#13;
&lt;peripheralInstance derived_from="PINT" determined="infoFile" id="PINT" location="0x400a4000"/&gt;&#13;
&lt;peripheralInstance derived_from="GINT0" determined="infoFile" id="GINT0" location="0x400a8000"/&gt;&#13;
&lt;peripheralInstance derived_from="GINT1" determined="infoFile" id="GINT1" location="0x400ac000"/&gt;&#13;
&lt;peripheralInstance derived_from="RIT" determined="infoFile" id="RIT" location="0x400b4000"/&gt;&#13;
&lt;peripheralInstance derived_from="SCTIPU" determined="infoFile" id="SCTIPU" location="0x400b8000"/&gt;&#13;
&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x400bc000"/&gt;&#13;
&lt;peripheralInstance derived_from="USART2" determined="infoFile" id="USART2" location="0x400c0000"/&gt;&#13;
&lt;peripheralInstance derived_from="C-CAN0" determined="infoFile" id="C-CAN0" location="0x400f0000"/&gt;&#13;
&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x400f8000"/&gt;&#13;
&lt;/chip&gt;&#13;
&lt;processor&gt;&#13;
&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
&lt;/processor&gt;&#13;
&lt;link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
&lt;/info&gt;&#13;
&lt;/infoList&gt;&#13;
&lt;/TargetConfig&gt;{% endblock %}

1
tools/export/lpcxpresso/lpc1549_project.tmpl
View File

@ -1 +0,0 @@
{% extends "lpcxpresso/project_common.tmpl" %}

63
tools/export/mcuxpresso/LPC1549_cproject.tmpl
View File

@ -1,63 +0,0 @@
{% extends "mcuxpresso/.cproject.tmpl" %}
{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
&lt;TargetConfig&gt;&#13;
&lt;Properties property_2="LPC15xx_256K.cfx" property_3="NXP" property_4="LPC1549" property_count="5" version="70200"/&gt;&#13;
&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC1549" connectscript="LPC15RunBootRomConnect.scp" flash_driver="LPC15xx_256K.cfx" match_id="0x0" name="LPC1549" resetscript="LPC15RunBootRomReset.scp" stub="crt_emu_cm3_gen"&gt;&lt;chip&gt;&lt;name&gt;LPC1549&lt;/name&gt;&#13;
&lt;family&gt;LPC15xx&lt;/family&gt;&#13;
&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
&lt;memory id="RAM" type="RAM"/&gt;&#13;
&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
&lt;memoryInstance derived_from="Flash" id="MFlash256" location="0x0" size="0x40000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="Ram0_16" location="0x2000000" size="0x4000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="Ram1_16" location="0x2004000" size="0x4000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="Ram2_4" location="0x2008000" size="0x1000"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x1c000000"/&gt;&#13;
&lt;peripheralInstance derived_from="DMA" id="DMA" location="0x1c004000"/&gt;&#13;
&lt;peripheralInstance derived_from="USB" id="USB" location="0x1c00c000"/&gt;&#13;
&lt;peripheralInstance derived_from="CRC" id="CRC" location="0x1c010000"/&gt;&#13;
&lt;peripheralInstance derived_from="SCT0" id="SCT0" location="0x1c018000"/&gt;&#13;
&lt;peripheralInstance derived_from="SCT1" id="SCT1" location="0x1c01c000"/&gt;&#13;
&lt;peripheralInstance derived_from="SCT2" id="SCT2" location="0x1c020000"/&gt;&#13;
&lt;peripheralInstance derived_from="SCT3" id="SCT3" location="0x1c024000"/&gt;&#13;
&lt;peripheralInstance derived_from="ADC0" id="ADC0" location="0x40000000"/&gt;&#13;
&lt;peripheralInstance derived_from="DAC" id="DAC" location="0x40004000"/&gt;&#13;
&lt;peripheralInstance derived_from="ACMP" id="ACMP" location="0x40008000"/&gt;&#13;
&lt;peripheralInstance derived_from="INMUX" id="INMUX" location="0x40014000"/&gt;&#13;
&lt;peripheralInstance derived_from="RTC" id="RTC" location="0x40028000"/&gt;&#13;
&lt;peripheralInstance derived_from="WWDT" id="WWDT" location="0x4002c000"/&gt;&#13;
&lt;peripheralInstance derived_from="SWM" id="SWM" location="0x40038000"/&gt;&#13;
&lt;peripheralInstance derived_from="PMU" id="PMU" location="0x4003c000"/&gt;&#13;
&lt;peripheralInstance derived_from="USART0" id="USART0" location="0x40040000"/&gt;&#13;
&lt;peripheralInstance derived_from="USART1" id="USART1" location="0x40044000"/&gt;&#13;
&lt;peripheralInstance derived_from="SPI0" id="SPI0" location="0x40048000"/&gt;&#13;
&lt;peripheralInstance derived_from="SPI1" id="SPI1" location="0x4004c000"/&gt;&#13;
&lt;peripheralInstance derived_from="I2C0" id="I2C0" location="0x40050000"/&gt;&#13;
&lt;peripheralInstance derived_from="QEI" id="QEI" location="0x40058000"/&gt;&#13;
&lt;peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x40074000"/&gt;&#13;
&lt;peripheralInstance derived_from="ADC1" id="ADC1" location="0x40080000"/&gt;&#13;
&lt;peripheralInstance derived_from="MRT" id="MRT" location="0x400a0000"/&gt;&#13;
&lt;peripheralInstance derived_from="PINT" id="PINT" location="0x400a4000"/&gt;&#13;
&lt;peripheralInstance derived_from="GINT0" id="GINT0" location="0x400a8000"/&gt;&#13;
&lt;peripheralInstance derived_from="GINT1" id="GINT1" location="0x400ac000"/&gt;&#13;
&lt;peripheralInstance derived_from="RIT" id="RIT" location="0x400b4000"/&gt;&#13;
&lt;peripheralInstance derived_from="SCTIPU" id="SCTIPU" location="0x400b8000"/&gt;&#13;
&lt;peripheralInstance derived_from="FLASHCTRL" id="FLASHCTRL" location="0x400bc000"/&gt;&#13;
&lt;peripheralInstance derived_from="USART2" id="USART2" location="0x400c0000"/&gt;&#13;
&lt;peripheralInstance derived_from="C-CAN0" id="C-CAN0" location="0x400f0000"/&gt;&#13;
&lt;peripheralInstance derived_from="IOCON" id="IOCON" location="0x400f8000"/&gt;&#13;
&lt;/chip&gt;&#13;
&lt;processor&gt;&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
&lt;/processor&gt;&#13;
&lt;link href="LPC15xx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
&lt;/info&gt;&#13;
&lt;/infoList&gt;&#13;
&lt;/TargetConfig&gt;{% endblock %}

2
tools/test/run_icetea/TEST_DIR_HW/test_predefined_platforms.py
View File

@ -33,7 +33,7 @@ class Testcase(Bench):
"count": 1,
"type": "hardware",
"allowed_platforms": [
"LPC1768", "KL25Z", "K64F", "K66F", "K22F", "LPC1549",
"LPC1768", "KL25Z", "K64F", "K66F", "K22F",
"NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_F302R8", "NUCLEO_F303K8",
"NUCLEO_F303RE", "NUCLEO_F207ZG", "NUCLEO_F334R8", "NUCLEO_F303ZE",
"NUCLEO_L053R8", "DISCO_L072CZ_LRWAN1", "NUCLEO_L073RZ", "NUCLEO_L152RE",

13
tools/tests.py
View File

@ -61,7 +61,6 @@ Wiring:
* digital_loop (Digital(In|Out|InOut), InterruptIn):
* Arduino headers: (D0 <-> D7)
* NUCLEO_*: (D2 <-> D9)
* LPC1549: (D2 <-> D7)
* LPC1*: (p5 <-> p25 )
* KL25Z: (PTA5<-> PTC6)
* MAXWSNENV: (TP3 <-> TP4)
@ -81,7 +80,6 @@ Wiring:
* Arduino headers: (A0 <-> A5)
* NUCLEO64: (A0 <-> A2)
* NUCLEO144: (A0 <-> D13)
* LPC1549: (A0 <-> D12)
* LPC1*: (p17 <-> p18 )
* KL25Z: (PTE30 <-> PTC2)
@ -108,7 +106,6 @@ Wiring:
* can_transceiver:
* LPC1768: (RX=p9, TX=p10)
* LPC1549: (RX=D9, TX=D8)
* VK_RZ_A1H:(RX=P5_9, TX=P5_10)
* NUCLEO_F091RC: (RX=PA_11, TX=PA_12)
* NUCLEO_F072RB: (RX=PA_11, TX=PA_12)
@ -194,7 +191,7 @@ TESTS = [
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
"automated": True,
"peripherals": ["analog_loop"],
"mcu": ["LPC1768", "KL25Z", "K64F", "K66F", "K22F", "LPC1549",
"mcu": ["LPC1768", "KL25Z", "K64F", "K66F", "K22F",
"NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_F302R8", "NUCLEO_F303K8", "NUCLEO_F303RE", "NUCLEO_F207ZG",
"NUCLEO_F334R8", "NUCLEO_F303ZE", "NUCLEO_L053R8", "DISCO_L072CZ_LRWAN1", "NUCLEO_L073RZ", "NUCLEO_L152RE",
"NUCLEO_F410RB", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F429ZI",
@ -308,7 +305,7 @@ TESTS = [
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
"automated": True,
"peripherals": ["can_transceiver"],
"mcu": ["LPC1549", "LPC1768","B96B_F446VE", "VK_RZ_A1H",
"mcu": ["LPC1768","B96B_F446VE", "VK_RZ_A1H",
"NUCLEO_F091RC", "NUCLEO_F072RB", "NUCLEO_F042K6", "NUCLEO_F334R8", "NUCLEO_F207ZG",
"NUCLEO_F303RE", "NUCLEO_F303K8", "NUCLEO_F302R8", "NUCLEO_F446RE","NUCLEO_F446ZE",
"DISCO_F469NI", "DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG",
@ -342,7 +339,7 @@ TESTS = [
"source_dir": join(TEST_DIR, "mbed", "can_api"),
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
"automated": True,
"mcu": ["LPC1549", "LPC1768","B96B_F446VE", "VK_RZ_A1H",
"mcu": ["LPC1768","B96B_F446VE", "VK_RZ_A1H",
"NUCLEO_F091RC", "NUCLEO_F072RB", "NUCLEO_F042K6", "NUCLEO_F334R8", "NUCLEO_F207ZG",
"NUCLEO_F303RE", "NUCLEO_F303K8", "NUCLEO_F303ZE", "NUCLEO_F302R8", "NUCLEO_F446RE","NUCLEO_F446ZE",
"DISCO_F469NI", "DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG",
@ -575,7 +572,7 @@ TESTS = [
"id": "MBED_29", "description": "CAN network test",
"source_dir": join(TEST_DIR, "mbed", "can"),
"dependencies": [MBED_LIBRARIES],
"mcu": ["LPC1768", "LPC1549", "RZ_A1H", "GR_LYCHEE", "B96B_F446VE", "NUCLEO_F091RC",
"mcu": ["LPC1768", "RZ_A1H", "GR_LYCHEE", "B96B_F446VE", "NUCLEO_F091RC",
"NUCLEO_F072RB", "NUCLEO_F042K6", "NUCLEO_F334R8", "NUCLEO_F303RE",
"NUCLEO_F303K8", "NUCLEO_F302R8", "NUCLEO_F446RE","NUCLEO_F446ZE", "DISCO_F469NI", "NUCLEO_F207ZG",
"DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG", "DISCO_F746NG",
@ -586,7 +583,7 @@ TESTS = [
"id": "MBED_30", "description": "CAN network test using interrupts",
"source_dir": join(TEST_DIR, "mbed", "can_interrupt"),
"dependencies": [MBED_LIBRARIES],
"mcu": ["LPC1768", "LPC1549", "RZ_A1H", "GR_LYCHEE", "B96B_F446VE", "NUCLEO_F091RC", "NUCLEO_F207ZG",
"mcu": ["LPC1768", "RZ_A1H", "GR_LYCHEE", "B96B_F446VE", "NUCLEO_F091RC", "NUCLEO_F207ZG",
"NUCLEO_F072RB", "NUCLEO_F042K6", "NUCLEO_F334R8", "NUCLEO_F303RE",
"NUCLEO_F303K8", "NUCLEO_F302R8", "NUCLEO_F446RE", "NUCLEO_F446ZE", "DISCO_F469NI",
"DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG", "DISCO_F746NG",