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RTX5: Pre-processor defines used for assembly 

CMSIS repo does not support pre-processor defines, hence multiple assembly
files are added for secure/non-secure and floating point tools.

Mbed OS tools support assembly file pre-processing, but the build system
does not support multiple assembly files for each target, hence updating
the assembly files.
pull/6201/head
deepikabhavnani 2018-02-06 21:52:19 -06:00 committed by Cruz Monrreal II
parent c37f25a090
commit 3e181422d8
14 changed files with 12 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl.S
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@ -24,9 +24,9 @@
; */
IF :LNOT::DEF:__DOMAIN_NS
#ifndef __DOMAIN_NS
__DOMAIN_NS EQU 0
ENDIF
#endif
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SM_OFS EQU 48 ; TCB.stack_mem offset

3
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl_ns.S
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@ -1,3 +0,0 @@
__DOMAIN_NS EQU 1
INCLUDE irq_armv8mbl.s
END

10
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml.S
View File

@ -24,15 +24,13 @@
; */
IF :LNOT::DEF:__DOMAIN_NS
#ifndef __DOMAIN_NS
__DOMAIN_NS EQU 0
ENDIF
#endif
IF ({FPU}="FPv5-SP") || ({FPU}="FPv5_D16")
__FPU_USED EQU 1
ELSE
#ifndef __FPU_USED
__FPU_USED EQU 0
ENDIF
#endif
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SM_OFS EQU 48 ; TCB.stack_mem offset

3
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml_ns.S
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@ -1,3 +0,0 @@
__DOMAIN_NS EQU 1
INCLUDE irq_armv8mml.s
END

4
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl.S
View File

@ -27,9 +27,9 @@
.file "irq_armv8mbl.S"
.syntax unified
.ifndef __DOMAIN_NS
#ifndef __DOMAIN_NS
.equ __DOMAIN_NS, 0
.endif
#endif
.equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset
.equ TCB_SM_OFS, 48 // TCB.stack_mem offset

3
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl_ns.S
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@ -1,3 +0,0 @@
.equ __DOMAIN_NS, 1
.include "../Source/GCC/irq_armv8mbl.S"
.end

8
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S
View File

@ -27,13 +27,13 @@
.file "irq_armv8mml.S"
.syntax unified
.ifndef __DOMAIN_NS
+#ifndef __DOMAIN_NS
.equ __DOMAIN_NS, 0
.endif
#endif
.ifndef __FPU_USED
#ifndef __FPU_USED
.equ __FPU_USED, 0
.endif
#endif
.equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset
.equ TCB_SM_OFS, 48 // TCB.stack_mem offset

3
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml_fp.S
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@ -1,3 +0,0 @@
.equ __FPU_USED, 1
.include "../Source/GCC/irq_armv8mml.S"
.end

4
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml_fp_ns.S
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@ -1,4 +0,0 @@
.equ __FPU_USED, 1
.equ __DOMAIN_NS, 1
.include "../Source/GCC/irq_armv8mml.S"
.end

3
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml_ns.S
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@ -1,3 +0,0 @@
.equ __DOMAIN_NS, 1
.include "../Source/GCC/irq_armv8mml.S"
.end

5
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl.S
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@ -1,5 +0,0 @@
NAME irq_armv8mbl.s
#define __DOMAIN_NS 0
INCLUDE irq_armv8mbl_common.s
END

5
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_ns.S
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@ -1,5 +0,0 @@
NAME irq_armv8mbl_ns.s
#define __DOMAIN_NS 1
INCLUDE irq_armv8mbl_common.s
END

5
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml.S
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@ -1,5 +0,0 @@
NAME irq_armv8mml.s
#define __DOMAIN_NS 0
INCLUDE irq_armv8mml_common.s
END

5
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_ns.S
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@ -1,5 +0,0 @@
NAME irq_armv8mml_ns.s
#define __DOMAIN_NS 1
INCLUDE irq_armv8mml_common.s
END