mirror of https://github.com/ARMmbed/mbed-os.git
Attempt to fix the interrupts problem.
parent
a125a25a97
commit
3d08be9700
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@ -17,13 +17,13 @@
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#include "cmsis.h"
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#include "gpio_irq_api.h"
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#include "error.h"
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#include "gpio_api.h"
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// The chip is capable of 4 external interrupts.
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#define CHANNEL_NUM 4
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static uint32_t channel_ids[CHANNEL_NUM] = {0};
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static gpio_irq_handler irq_handler;
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static int channel = 0;
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static PinName pin_names[CHANNEL_NUM] = {};
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static inline void handle_interrupt_in(uint32_t channel) {
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@ -32,12 +32,12 @@ static inline void handle_interrupt_in(uint32_t channel) {
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// the level of the pin as if it were just a normal input...
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// Get the number of the pin being used and the port typedef
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uint32_t pin = (pin_names[channel] & (0x0f << 8)) >> 8;
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LPC_GPIO_TypeDef *port_reg = ((LPC_GPIO_TypeDef *) (LPC_GPIO0_BASE + (((pin & 0xF000) >> PORT_SHIFT) * 0x10000)));
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uint32_t logiclevel = port_reg->DATA;
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logiclevel &= (uint32_t)(1 << pin) >> pin;
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LPC_GPIO_TypeDef *port_reg = ((LPC_GPIO_TypeDef *) (LPC_GPIO0_BASE + (((pin_names[channel] & 0xF000) >> PORT_SHIFT) * 0x10000)));
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int logic_level = port_reg->MASKED_ACCESS[gpio_set(pin_names[channel]) + 1];
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if (logiclevel == 1) {
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printf("%i\r\n", logic_level);
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if (logic_level == 1) {
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// High, therefore rising edge...
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irq_handler(channel_ids[channel], IRQ_RISE);
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}
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@ -63,36 +63,45 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
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if (pin == ... ||
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pin == ...) {
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error("This pin does not suppor interrupts.");
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error("This pin does not support interrupts.");
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return -1;
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}
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*/
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// Which port are we using?
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int channel;
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uint32_t port_reg = (LPC_GPIO0_BASE + (((pin & 0xF000) >> PORT_SHIFT) * 0x10000));
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switch (port_reg) {
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case LPC_GPIO0_BASE:
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NVIC_SetVector(EINT0_IRQn, (uint32_t)gpio_irq0);
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NVIC_EnableIRQ(EINT0_IRQn);
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channel = 0;
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break;
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case LPC_GPIO1_BASE:
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NVIC_SetVector(EINT1_IRQn, (uint32_t)gpio_irq1);
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NVIC_EnableIRQ(EINT1_IRQn);
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channel = 1;
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break;
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case LPC_GPIO2_BASE:
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NVIC_SetVector(EINT2_IRQn, (uint32_t)gpio_irq2);
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NVIC_EnableIRQ(EINT2_IRQn);
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channel = 2;
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break;
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case LPC_GPIO3_BASE:
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NVIC_SetVector(EINT3_IRQn, (uint32_t)gpio_irq3);
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NVIC_EnableIRQ(EINT3_IRQn);
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channel = 3;
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break;
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default:
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channel = -1;
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error("Invalid interrupt choice.");
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break;
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}
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channel_ids[channel] = id;
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pin_names[channel] = pin;
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obj->ch = channel;
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// Which port are we using?
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switch (channel) {
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case 0:
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NVIC_SetVector(EINT0_IRQn, (uint32_t)gpio_irq0);
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NVIC_EnableIRQ(EINT0_IRQn);
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break;
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case 1:
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NVIC_SetVector(EINT1_IRQn, (uint32_t)gpio_irq1);
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NVIC_EnableIRQ(EINT1_IRQn);
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break;
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case 2:
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NVIC_SetVector(EINT2_IRQn, (uint32_t)gpio_irq2);
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NVIC_EnableIRQ(EINT2_IRQn);
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break;
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case 3:
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NVIC_SetVector(EINT3_IRQn, (uint32_t)gpio_irq3);
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NVIC_EnableIRQ(EINT3_IRQn);
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break;
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}
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channel++;
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return 0;
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}
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@ -109,7 +118,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
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Enable the interrupt,
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And set it to only respond to interrupts on one edge.
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*/
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// Clear
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port_reg->IC |= 1 << obj->pin;
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@ -28,6 +28,7 @@ extern "C" {
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struct gpio_irq_s {
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uint32_t ch;
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PinName pin;
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__I uint32_t *reg_mask_read;
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};
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struct port_s {
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