mirror of https://github.com/ARMmbed/mbed-os.git
[EFM32] Update emlib to version 5.0.0 in preparation for new targets
* Updated cmsis headers to match emlib 5.0.0 * Updated GPIO handling to match new header guards in use * Updated linker scripts to match emlib 5.0.0pull/3122/head
Steven Cooreman
parent
c60dacfccf
commit
3c450f1b37
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@ -9,9 +9,6 @@
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/* Version 4.2.0 */
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/* */
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STACK_SIZE = 0x400;
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HEAP_SIZE = 0xC00;
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 1048576
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@ -56,11 +53,6 @@ __vector_size = 0xDC;
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*/
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ENTRY(Reset_Handler)
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/* Note: The uVisor expects the text section at a fixed location, as specified
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by the porting process configuration parameter: FLASH_OFFSET. */
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__UVISOR_TEXT_OFFSET = 0x100;
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__UVISOR_TEXT_START = ORIGIN(FLASH) + __UVISOR_TEXT_OFFSET;
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SECTIONS
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{
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.text :
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@ -70,13 +62,6 @@ SECTIONS
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__Vectors_Size = __Vectors_End - __Vectors;
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__end__ = .;
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/* uVisor code and data */
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. = __UVISOR_TEXT_OFFSET;
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. = ALIGN(4);
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__uvisor_main_start = .;
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*(.uvisor.main)
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__uvisor_main_end = .;
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*(.text*)
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KEEP(*(.init))
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@ -147,51 +132,10 @@ SECTIONS
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} > FLASH
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*/
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/* Ensure that the uVisor BSS section is put first in SRAM. */
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/* Note: The uVisor expects this section at a fixed location, as specified
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by the porting process configuration parameter: SRAM_OFFSET. */
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__UVISOR_SRAM_OFFSET = 0x0;
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__UVISOR_BSS_START = ORIGIN(RAM) + __UVISOR_SRAM_OFFSET;
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.uvisor.bss __UVISOR_BSS_START (NOLOAD):
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__etext = .;
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.data : AT (__etext)
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{
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. = ALIGN(32);
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__uvisor_bss_start = .;
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/* uVisor main BSS section */
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. = ALIGN(32);
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__uvisor_bss_main_start = .;
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KEEP(*(.keep.uvisor.bss.main))
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. = ALIGN(32);
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__uvisor_bss_main_end = .;
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/* Secure boxes BSS section */
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. = ALIGN(32);
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__uvisor_bss_boxes_start = .;
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KEEP(*(.keep.uvisor.bss.boxes))
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. = ALIGN(32);
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__uvisor_bss_boxes_end = .;
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. = ALIGN(32);
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__uvisor_bss_end = .;
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} > RAM
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/* Heap space for the page allocator */
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.page_heap (NOLOAD) :
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{
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. = ALIGN(32);
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__uvisor_page_start = .;
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KEEP(*(.keep.uvisor.page_heap))
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. = ALIGN( (1 << LOG2CEIL(LENGTH(RAM))) / 8);
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__uvisor_page_end = .;
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} > RAM
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.data :
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{
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PROVIDE(__etext = LOADADDR(.data)); /* Define a global symbol at end of code, */
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PROVIDE(__DATA_ROM = LOADADDR(.data)); /* Symbol is used by startup for data initialization. */
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__data_start__ = .;
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*("dma")
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PROVIDE( __start_vector_table__ = .);
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@ -227,51 +171,6 @@ SECTIONS
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/* All data end */
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__data_end__ = .;
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} > RAM AT > FLASH
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/* uVisor configuration section
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* This section must be located after all other flash regions. */
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.uvisor.secure :
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{
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. = ALIGN(32);
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__uvisor_secure_start = .;
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/* uVisor secure boxes configuration tables */
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. = ALIGN(32);
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__uvisor_cfgtbl_start = .;
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KEEP(*(.keep.uvisor.cfgtbl))
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. = ALIGN(32);
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__uvisor_cfgtbl_end = .;
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/* Pointers to the uVisor secure boxes configuration tables */
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/* Note: Do not add any further alignment here, as uVisor will need to
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have access to the exact list of pointers. */
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__uvisor_cfgtbl_ptr_start = .;
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KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
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KEEP(*(.keep.uvisor.cfgtbl_ptr))
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__uvisor_cfgtbl_ptr_end = .;
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/* Pointers to all boxes register gateways. These are grouped here to
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allow discoverability and firmware verification. */
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__uvisor_register_gateway_ptr_start = .;
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KEEP(*(.keep.uvisor.register_gateway_ptr))
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__uvisor_register_gateway_ptr_end = .;
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. = ALIGN(32);
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__uvisor_secure_end = .;
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} > FLASH
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/* Uninitialized data section
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* This region is not initialized by the C/C++ library and can be used to
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* store state across soft reboots. */
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.uninitialized (NOLOAD):
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{
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. = ALIGN(32);
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__uninitialized_start = .;
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*(.uninitialized)
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KEEP(*(.keep.uninitialized))
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. = ALIGN(32);
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__uninitialized_end = .;
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} > RAM
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.bss :
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@ -284,29 +183,33 @@ SECTIONS
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__bss_end__ = .;
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} > RAM
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__StackTop = ORIGIN(RAM) + LENGTH(RAM);
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__stack = __StackTop;
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__StackLimit = __StackTop - STACK_SIZE;
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.heap (NOLOAD):
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.heap (COPY):
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{
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__uvisor_heap_start = .;
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__HeapBase = .;
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__end__ = .;
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end = __end__;
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_end = __end__;
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. += HEAP_SIZE;
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KEEP(*(.heap*))
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__HeapLimit = .;
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} > RAM
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__HeapLimit = __StackLimit;
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__uvisor_heap_end = __StackLimit;
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/* .stack_dummy section doesn't contains any symbols. It is only
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* used for linker to calculate size of stack sections, and assign
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* values to stack symbols later */
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.stack_dummy (COPY):
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{
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KEEP(*(.stack*))
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} > RAM
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/* Provide physical memory boundaries for uVisor. */
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__uvisor_flash_start = ORIGIN(FLASH);
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__uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
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__uvisor_sram_start = ORIGIN(RAM);
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__uvisor_sram_end = ORIGIN(RAM) + LENGTH(RAM);
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/* Set stack top to end of RAM, and stack limit move down by
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* size of stack_dummy section */
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__StackTop = ORIGIN(RAM) + LENGTH(RAM);
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__StackLimit = __StackTop - SIZEOF(.stack_dummy);
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PROVIDE(__stack = __StackTop);
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/* Check if FLASH usage exceeds FLASH size. */
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ASSERT(LENGTH(FLASH) >= __uvisor_secure_end, "FLASH memory overflowed!")
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/* Check if data + heap + stack exceeds RAM limit */
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ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
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/* Check if FLASH usage exceeds FLASH size */
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ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !")
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}
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@ -49,6 +49,23 @@ __StackLimit:
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__StackTop:
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.size __StackTop, . - __StackTop
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.section .heap
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.align 3
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#ifdef __HEAP_SIZE
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.equ Heap_Size, __HEAP_SIZE
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#else
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.equ Heap_Size, 0x00000C00
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#endif
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.globl __HeapBase
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.globl __HeapLimit
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__HeapBase:
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.if Heap_Size
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.space Heap_Size
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.endif
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.size __HeapBase, . - __HeapBase
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__HeapLimit:
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.size __HeapLimit, . - __HeapLimit
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.section .vectors
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.align 2
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.globl __Vectors
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@ -127,11 +144,6 @@ Reset_Handler:
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blx r0
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#endif
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#if defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)
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ldr r0, =uvisor_init
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blx r0
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#endif /* defined(FEATURE_UVISOR) && defined(UVISOR_SUPPORTED) */
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/* Firstly it copies data from read only memory to RAM. There are two schemes
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* to copy. One can copy more than one sections. Another can only copy
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* one section. The former scheme needs more instructions and read-only
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@ -0,0 +1,483 @@
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/**************************************************************************//**
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* @file efm32gg900f1024.h
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* @brief CMSIS Cortex-M Peripheral Access Layer Header File
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* for EFM32GG900F1024
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* @version 5.0.0
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******************************************************************************
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* @section License
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* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
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******************************************************************************
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software.@n
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.@n
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* 3. This notice may not be removed or altered from any source distribution.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
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* has no obligation to support this Software. Silicon Laboratories, Inc. is
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* providing the Software "AS IS", with no express or implied warranties of any
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* kind, including, but not limited to, any implied warranties of
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* merchantability or fitness for any particular purpose or warranties against
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* infringement of any proprietary rights of a third party.
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*
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* Silicon Laboratories, Inc. will not be liable for any consequential,
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* incidental, or special damages, or any other relief, or for any claim by
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* any third party, arising from your use of this Software.
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*
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*****************************************************************************/
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#ifndef EFM32GG900F1024_H
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#define EFM32GG900F1024_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**************************************************************************//**
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* @addtogroup Parts
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* @{
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*****************************************************************************/
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/**************************************************************************//**
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* @defgroup EFM32GG900F1024 EFM32GG900F1024
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* @{
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*****************************************************************************/
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/** Interrupt Number Definition */
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typedef enum IRQn
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{
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/****** Cortex-M3 Processor Exceptions Numbers ********************************************/
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NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M3 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< -13 Cortex-M3 Hard Fault Interrupt */
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MemoryManagement_IRQn = -12, /*!< -12 Cortex-M3 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< -11 Cortex-M3 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< -10 Cortex-M3 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< -5 Cortex-M3 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< -4 Cortex-M3 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< -2 Cortex-M3 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< -1 Cortex-M3 System Tick Interrupt */
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/****** EFM32G Peripheral Interrupt Numbers ***********************************************/
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DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
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GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
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TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
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USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */
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USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */
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USB_IRQn = 5, /*!< 5 EFM32 USB Interrupt */
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ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */
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ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */
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DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */
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I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */
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I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */
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GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */
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TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */
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TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */
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TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */
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USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */
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USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */
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LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */
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USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */
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USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */
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UART0_RX_IRQn = 20, /*!< 20 EFM32 UART0_RX Interrupt */
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UART0_TX_IRQn = 21, /*!< 21 EFM32 UART0_TX Interrupt */
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UART1_RX_IRQn = 22, /*!< 22 EFM32 UART1_RX Interrupt */
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UART1_TX_IRQn = 23, /*!< 23 EFM32 UART1_TX Interrupt */
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LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */
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LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */
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LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
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PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */
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PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */
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PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */
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RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */
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BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */
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CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */
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VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */
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LCD_IRQn = 34, /*!< 34 EFM32 LCD Interrupt */
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MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */
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AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */
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EBI_IRQn = 37, /*!< 37 EFM32 EBI Interrupt */
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EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */
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} IRQn_Type;
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/**************************************************************************//**
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* @defgroup EFM32GG900F1024_Core EFM32GG900F1024 Core
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* @{
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* @brief Processor and Core Peripheral Section
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*****************************************************************************/
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#define __MPU_PRESENT 1 /**< Presence of MPU */
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#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
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#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
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#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
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/** @} End of group EFM32GG900F1024_Core */
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/**************************************************************************//**
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* @defgroup EFM32GG900F1024_Part EFM32GG900F1024 Part
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* @{
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******************************************************************************/
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/** Part family */
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#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
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#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
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#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
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#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
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#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
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#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
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/* If part number is not defined as compiler option, define it */
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#if !defined(EFM32GG900F1024)
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#define EFM32GG900F1024 1 /**< Giant/Leopard Gecko Part */
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#endif
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/** Configure part number */
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#define PART_NUMBER "EFM32GG900F1024" /**< Part Number */
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/** Memory Base addresses and limits */
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#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
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#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
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#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
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#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
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#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
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#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
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#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
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#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
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#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
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#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
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#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
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#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
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#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
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#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
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#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
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#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
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#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32GG900F1024 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
|
||||
#define EXT_IRQ_COUNT 39 /**< Number of External (NVIC) interrupts */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 163
|
||||
#define AFCHANLOC_MAX 7
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 53
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 2 /**< 2 UARTs available */
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 4 /**< 4 TIMERs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 2 /**< 2 I2Cs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define USBC_PRESENT
|
||||
#define USBC_COUNT 1
|
||||
#define USB_PRESENT
|
||||
#define USB_COUNT 1
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define LESENSE_PRESENT
|
||||
#define LESENSE_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define OPAMP_PRESENT
|
||||
#define OPAMP_COUNT 1
|
||||
#define BU_PRESENT
|
||||
#define BU_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define BURTC_PRESENT
|
||||
#define BURTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
#define ETM_PRESENT
|
||||
#define ETM_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define ANALOG_PRESENT
|
||||
#define ANALOG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32gg.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32GG900F1024_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F1024_Peripheral_TypeDefs EFM32GG900F1024 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_dma_ch.h"
|
||||
#include "efm32gg_dma.h"
|
||||
#include "efm32gg_aes.h"
|
||||
#include "efm32gg_usb_hc.h"
|
||||
#include "efm32gg_usb_diep.h"
|
||||
#include "efm32gg_usb_doep.h"
|
||||
#include "efm32gg_usb.h"
|
||||
#include "efm32gg_msc.h"
|
||||
#include "efm32gg_emu.h"
|
||||
#include "efm32gg_rmu.h"
|
||||
#include "efm32gg_cmu.h"
|
||||
#include "efm32gg_lesense_st.h"
|
||||
#include "efm32gg_lesense_buf.h"
|
||||
#include "efm32gg_lesense_ch.h"
|
||||
#include "efm32gg_lesense.h"
|
||||
#include "efm32gg_rtc.h"
|
||||
#include "efm32gg_letimer.h"
|
||||
#include "efm32gg_ebi.h"
|
||||
#include "efm32gg_usart.h"
|
||||
#include "efm32gg_timer_cc.h"
|
||||
#include "efm32gg_timer.h"
|
||||
#include "efm32gg_acmp.h"
|
||||
#include "efm32gg_i2c.h"
|
||||
#include "efm32gg_gpio_p.h"
|
||||
#include "efm32gg_gpio.h"
|
||||
#include "efm32gg_vcmp.h"
|
||||
#include "efm32gg_prs_ch.h"
|
||||
#include "efm32gg_prs.h"
|
||||
#include "efm32gg_leuart.h"
|
||||
#include "efm32gg_pcnt.h"
|
||||
#include "efm32gg_adc.h"
|
||||
#include "efm32gg_dac.h"
|
||||
#include "efm32gg_lcd.h"
|
||||
#include "efm32gg_burtc_ret.h"
|
||||
#include "efm32gg_burtc.h"
|
||||
#include "efm32gg_wdog.h"
|
||||
#include "efm32gg_etm.h"
|
||||
#include "efm32gg_dma_descriptor.h"
|
||||
#include "efm32gg_devinfo.h"
|
||||
#include "efm32gg_romtable.h"
|
||||
#include "efm32gg_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32GG900F1024_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F1024_Peripheral_Base EFM32GG900F1024 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define USB_BASE (0x400C4000UL) /**< USB base address */
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define UART1_BASE (0x4000E400UL) /**< UART1 base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define BURTC_BASE (0x40081000UL) /**< BURTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
|
||||
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
|
||||
|
||||
/** @} End of group EFM32GG900F1024_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F1024_Peripheral_Declaration EFM32GG900F1024 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32GG900F1024_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F1024_BitFields EFM32GG900F1024 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_prs_signals.h"
|
||||
#include "efm32gg_dmareq.h"
|
||||
#include "efm32gg_dmactrl.h"
|
||||
#include "efm32gg_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F1024_UNLOCK EFM32GG900F1024 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
|
||||
|
||||
/** @} End of group EFM32GG900F1024_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32GG900F1024_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F1024_Alternate_Function EFM32GG900F1024 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_af_ports.h"
|
||||
#include "efm32gg_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32GG900F1024_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32GG900F1024 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* EFM32GG900F1024_H */
|
||||
|
|
@ -0,0 +1,483 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg900f512.h
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32GG900F512
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef EFM32GG900F512_H
|
||||
#define EFM32GG900F512_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F512 EFM32GG900F512
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ********************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M3 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< -13 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< -11 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< -10 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< -5 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< -2 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< -1 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers ***********************************************/
|
||||
DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */
|
||||
USB_IRQn = 5, /*!< 5 EFM32 USB Interrupt */
|
||||
ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */
|
||||
I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */
|
||||
GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */
|
||||
TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */
|
||||
USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */
|
||||
LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */
|
||||
USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 20, /*!< 20 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 21, /*!< 21 EFM32 UART0_TX Interrupt */
|
||||
UART1_RX_IRQn = 22, /*!< 22 EFM32 UART1_RX Interrupt */
|
||||
UART1_TX_IRQn = 23, /*!< 23 EFM32 UART1_TX Interrupt */
|
||||
LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */
|
||||
BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */
|
||||
CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 34, /*!< 34 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */
|
||||
EBI_IRQn = 37, /*!< 37 EFM32 EBI Interrupt */
|
||||
EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F512_Core EFM32GG900F512 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32GG900F512_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F512_Part EFM32GG900F512 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
|
||||
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
|
||||
#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32GG900F512)
|
||||
#define EFM32GG900F512 1 /**< Giant/Leopard Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32GG900F512" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
|
||||
#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
|
||||
#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
|
||||
#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
|
||||
#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
|
||||
#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
|
||||
#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
|
||||
#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32GG900F512 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
|
||||
#define EXT_IRQ_COUNT 39 /**< Number of External (NVIC) interrupts */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 163
|
||||
#define AFCHANLOC_MAX 7
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 53
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 2 /**< 2 UARTs available */
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 4 /**< 4 TIMERs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 2 /**< 2 I2Cs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define USBC_PRESENT
|
||||
#define USBC_COUNT 1
|
||||
#define USB_PRESENT
|
||||
#define USB_COUNT 1
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define LESENSE_PRESENT
|
||||
#define LESENSE_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define OPAMP_PRESENT
|
||||
#define OPAMP_COUNT 1
|
||||
#define BU_PRESENT
|
||||
#define BU_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define BURTC_PRESENT
|
||||
#define BURTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
#define ETM_PRESENT
|
||||
#define ETM_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define ANALOG_PRESENT
|
||||
#define ANALOG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32gg.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32GG900F512_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F512_Peripheral_TypeDefs EFM32GG900F512 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_dma_ch.h"
|
||||
#include "efm32gg_dma.h"
|
||||
#include "efm32gg_aes.h"
|
||||
#include "efm32gg_usb_hc.h"
|
||||
#include "efm32gg_usb_diep.h"
|
||||
#include "efm32gg_usb_doep.h"
|
||||
#include "efm32gg_usb.h"
|
||||
#include "efm32gg_msc.h"
|
||||
#include "efm32gg_emu.h"
|
||||
#include "efm32gg_rmu.h"
|
||||
#include "efm32gg_cmu.h"
|
||||
#include "efm32gg_lesense_st.h"
|
||||
#include "efm32gg_lesense_buf.h"
|
||||
#include "efm32gg_lesense_ch.h"
|
||||
#include "efm32gg_lesense.h"
|
||||
#include "efm32gg_rtc.h"
|
||||
#include "efm32gg_letimer.h"
|
||||
#include "efm32gg_ebi.h"
|
||||
#include "efm32gg_usart.h"
|
||||
#include "efm32gg_timer_cc.h"
|
||||
#include "efm32gg_timer.h"
|
||||
#include "efm32gg_acmp.h"
|
||||
#include "efm32gg_i2c.h"
|
||||
#include "efm32gg_gpio_p.h"
|
||||
#include "efm32gg_gpio.h"
|
||||
#include "efm32gg_vcmp.h"
|
||||
#include "efm32gg_prs_ch.h"
|
||||
#include "efm32gg_prs.h"
|
||||
#include "efm32gg_leuart.h"
|
||||
#include "efm32gg_pcnt.h"
|
||||
#include "efm32gg_adc.h"
|
||||
#include "efm32gg_dac.h"
|
||||
#include "efm32gg_lcd.h"
|
||||
#include "efm32gg_burtc_ret.h"
|
||||
#include "efm32gg_burtc.h"
|
||||
#include "efm32gg_wdog.h"
|
||||
#include "efm32gg_etm.h"
|
||||
#include "efm32gg_dma_descriptor.h"
|
||||
#include "efm32gg_devinfo.h"
|
||||
#include "efm32gg_romtable.h"
|
||||
#include "efm32gg_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32GG900F512_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F512_Peripheral_Base EFM32GG900F512 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define USB_BASE (0x400C4000UL) /**< USB base address */
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define UART1_BASE (0x4000E400UL) /**< UART1 base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define BURTC_BASE (0x40081000UL) /**< BURTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
|
||||
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
|
||||
|
||||
/** @} End of group EFM32GG900F512_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F512_Peripheral_Declaration EFM32GG900F512 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32GG900F512_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F512_BitFields EFM32GG900F512 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_prs_signals.h"
|
||||
#include "efm32gg_dmareq.h"
|
||||
#include "efm32gg_dmactrl.h"
|
||||
#include "efm32gg_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F512_UNLOCK EFM32GG900F512 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
|
||||
|
||||
/** @} End of group EFM32GG900F512_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32GG900F512_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG900F512_Alternate_Function EFM32GG900F512 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_af_ports.h"
|
||||
#include "efm32gg_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32GG900F512_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32GG900F512 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* EFM32GG900F512_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,483 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg980f1024.h
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32GG980F1024
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef EFM32GG980F1024_H
|
||||
#define EFM32GG980F1024_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F1024 EFM32GG980F1024
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ********************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M3 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< -13 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< -11 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< -10 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< -5 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< -2 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< -1 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers ***********************************************/
|
||||
DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */
|
||||
USB_IRQn = 5, /*!< 5 EFM32 USB Interrupt */
|
||||
ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */
|
||||
I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */
|
||||
GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */
|
||||
TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */
|
||||
USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */
|
||||
LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */
|
||||
USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 20, /*!< 20 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 21, /*!< 21 EFM32 UART0_TX Interrupt */
|
||||
UART1_RX_IRQn = 22, /*!< 22 EFM32 UART1_RX Interrupt */
|
||||
UART1_TX_IRQn = 23, /*!< 23 EFM32 UART1_TX Interrupt */
|
||||
LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */
|
||||
BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */
|
||||
CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 34, /*!< 34 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */
|
||||
EBI_IRQn = 37, /*!< 37 EFM32 EBI Interrupt */
|
||||
EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F1024_Core EFM32GG980F1024 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32GG980F1024_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F1024_Part EFM32GG980F1024 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
|
||||
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
|
||||
#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32GG980F1024)
|
||||
#define EFM32GG980F1024 1 /**< Giant/Leopard Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32GG980F1024" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
|
||||
#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
|
||||
#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
|
||||
#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
|
||||
#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
|
||||
#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
|
||||
#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
|
||||
#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32GG980F1024 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
|
||||
#define EXT_IRQ_COUNT 39 /**< Number of External (NVIC) interrupts */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 163
|
||||
#define AFCHANLOC_MAX 7
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 53
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 2 /**< 2 UARTs available */
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 4 /**< 4 TIMERs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 2 /**< 2 I2Cs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define USBC_PRESENT
|
||||
#define USBC_COUNT 1
|
||||
#define USB_PRESENT
|
||||
#define USB_COUNT 1
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define LESENSE_PRESENT
|
||||
#define LESENSE_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define OPAMP_PRESENT
|
||||
#define OPAMP_COUNT 1
|
||||
#define BU_PRESENT
|
||||
#define BU_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define BURTC_PRESENT
|
||||
#define BURTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
#define ETM_PRESENT
|
||||
#define ETM_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define ANALOG_PRESENT
|
||||
#define ANALOG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32gg.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32GG980F1024_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F1024_Peripheral_TypeDefs EFM32GG980F1024 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_dma_ch.h"
|
||||
#include "efm32gg_dma.h"
|
||||
#include "efm32gg_aes.h"
|
||||
#include "efm32gg_usb_hc.h"
|
||||
#include "efm32gg_usb_diep.h"
|
||||
#include "efm32gg_usb_doep.h"
|
||||
#include "efm32gg_usb.h"
|
||||
#include "efm32gg_msc.h"
|
||||
#include "efm32gg_emu.h"
|
||||
#include "efm32gg_rmu.h"
|
||||
#include "efm32gg_cmu.h"
|
||||
#include "efm32gg_lesense_st.h"
|
||||
#include "efm32gg_lesense_buf.h"
|
||||
#include "efm32gg_lesense_ch.h"
|
||||
#include "efm32gg_lesense.h"
|
||||
#include "efm32gg_rtc.h"
|
||||
#include "efm32gg_letimer.h"
|
||||
#include "efm32gg_ebi.h"
|
||||
#include "efm32gg_usart.h"
|
||||
#include "efm32gg_timer_cc.h"
|
||||
#include "efm32gg_timer.h"
|
||||
#include "efm32gg_acmp.h"
|
||||
#include "efm32gg_i2c.h"
|
||||
#include "efm32gg_gpio_p.h"
|
||||
#include "efm32gg_gpio.h"
|
||||
#include "efm32gg_vcmp.h"
|
||||
#include "efm32gg_prs_ch.h"
|
||||
#include "efm32gg_prs.h"
|
||||
#include "efm32gg_leuart.h"
|
||||
#include "efm32gg_pcnt.h"
|
||||
#include "efm32gg_adc.h"
|
||||
#include "efm32gg_dac.h"
|
||||
#include "efm32gg_lcd.h"
|
||||
#include "efm32gg_burtc_ret.h"
|
||||
#include "efm32gg_burtc.h"
|
||||
#include "efm32gg_wdog.h"
|
||||
#include "efm32gg_etm.h"
|
||||
#include "efm32gg_dma_descriptor.h"
|
||||
#include "efm32gg_devinfo.h"
|
||||
#include "efm32gg_romtable.h"
|
||||
#include "efm32gg_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32GG980F1024_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F1024_Peripheral_Base EFM32GG980F1024 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define USB_BASE (0x400C4000UL) /**< USB base address */
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define UART1_BASE (0x4000E400UL) /**< UART1 base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define BURTC_BASE (0x40081000UL) /**< BURTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
|
||||
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
|
||||
|
||||
/** @} End of group EFM32GG980F1024_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F1024_Peripheral_Declaration EFM32GG980F1024 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32GG980F1024_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F1024_BitFields EFM32GG980F1024 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_prs_signals.h"
|
||||
#include "efm32gg_dmareq.h"
|
||||
#include "efm32gg_dmactrl.h"
|
||||
#include "efm32gg_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F1024_UNLOCK EFM32GG980F1024 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
|
||||
|
||||
/** @} End of group EFM32GG980F1024_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32GG980F1024_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F1024_Alternate_Function EFM32GG980F1024 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_af_ports.h"
|
||||
#include "efm32gg_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32GG980F1024_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32GG980F1024 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* EFM32GG980F1024_H */
|
||||
|
|
@ -0,0 +1,483 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg980f512.h
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32GG980F512
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef EFM32GG980F512_H
|
||||
#define EFM32GG980F512_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F512 EFM32GG980F512
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ********************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M3 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< -13 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< -11 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< -10 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< -5 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< -2 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< -1 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers ***********************************************/
|
||||
DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */
|
||||
USB_IRQn = 5, /*!< 5 EFM32 USB Interrupt */
|
||||
ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */
|
||||
I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */
|
||||
GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */
|
||||
TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */
|
||||
USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */
|
||||
LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */
|
||||
USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 20, /*!< 20 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 21, /*!< 21 EFM32 UART0_TX Interrupt */
|
||||
UART1_RX_IRQn = 22, /*!< 22 EFM32 UART1_RX Interrupt */
|
||||
UART1_TX_IRQn = 23, /*!< 23 EFM32 UART1_TX Interrupt */
|
||||
LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */
|
||||
BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */
|
||||
CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 34, /*!< 34 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */
|
||||
EBI_IRQn = 37, /*!< 37 EFM32 EBI Interrupt */
|
||||
EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F512_Core EFM32GG980F512 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32GG980F512_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F512_Part EFM32GG980F512 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
|
||||
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
|
||||
#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32GG980F512)
|
||||
#define EFM32GG980F512 1 /**< Giant/Leopard Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32GG980F512" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
|
||||
#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
|
||||
#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
|
||||
#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
|
||||
#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
|
||||
#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
|
||||
#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
|
||||
#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32GG980F512 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
|
||||
#define EXT_IRQ_COUNT 39 /**< Number of External (NVIC) interrupts */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 163
|
||||
#define AFCHANLOC_MAX 7
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 53
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 2 /**< 2 UARTs available */
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 4 /**< 4 TIMERs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 2 /**< 2 I2Cs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define USBC_PRESENT
|
||||
#define USBC_COUNT 1
|
||||
#define USB_PRESENT
|
||||
#define USB_COUNT 1
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define LESENSE_PRESENT
|
||||
#define LESENSE_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define OPAMP_PRESENT
|
||||
#define OPAMP_COUNT 1
|
||||
#define BU_PRESENT
|
||||
#define BU_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define BURTC_PRESENT
|
||||
#define BURTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
#define ETM_PRESENT
|
||||
#define ETM_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define ANALOG_PRESENT
|
||||
#define ANALOG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32gg.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32GG980F512_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F512_Peripheral_TypeDefs EFM32GG980F512 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_dma_ch.h"
|
||||
#include "efm32gg_dma.h"
|
||||
#include "efm32gg_aes.h"
|
||||
#include "efm32gg_usb_hc.h"
|
||||
#include "efm32gg_usb_diep.h"
|
||||
#include "efm32gg_usb_doep.h"
|
||||
#include "efm32gg_usb.h"
|
||||
#include "efm32gg_msc.h"
|
||||
#include "efm32gg_emu.h"
|
||||
#include "efm32gg_rmu.h"
|
||||
#include "efm32gg_cmu.h"
|
||||
#include "efm32gg_lesense_st.h"
|
||||
#include "efm32gg_lesense_buf.h"
|
||||
#include "efm32gg_lesense_ch.h"
|
||||
#include "efm32gg_lesense.h"
|
||||
#include "efm32gg_rtc.h"
|
||||
#include "efm32gg_letimer.h"
|
||||
#include "efm32gg_ebi.h"
|
||||
#include "efm32gg_usart.h"
|
||||
#include "efm32gg_timer_cc.h"
|
||||
#include "efm32gg_timer.h"
|
||||
#include "efm32gg_acmp.h"
|
||||
#include "efm32gg_i2c.h"
|
||||
#include "efm32gg_gpio_p.h"
|
||||
#include "efm32gg_gpio.h"
|
||||
#include "efm32gg_vcmp.h"
|
||||
#include "efm32gg_prs_ch.h"
|
||||
#include "efm32gg_prs.h"
|
||||
#include "efm32gg_leuart.h"
|
||||
#include "efm32gg_pcnt.h"
|
||||
#include "efm32gg_adc.h"
|
||||
#include "efm32gg_dac.h"
|
||||
#include "efm32gg_lcd.h"
|
||||
#include "efm32gg_burtc_ret.h"
|
||||
#include "efm32gg_burtc.h"
|
||||
#include "efm32gg_wdog.h"
|
||||
#include "efm32gg_etm.h"
|
||||
#include "efm32gg_dma_descriptor.h"
|
||||
#include "efm32gg_devinfo.h"
|
||||
#include "efm32gg_romtable.h"
|
||||
#include "efm32gg_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32GG980F512_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F512_Peripheral_Base EFM32GG980F512 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define USB_BASE (0x400C4000UL) /**< USB base address */
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define UART1_BASE (0x4000E400UL) /**< UART1 base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define BURTC_BASE (0x40081000UL) /**< BURTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
|
||||
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
|
||||
|
||||
/** @} End of group EFM32GG980F512_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F512_Peripheral_Declaration EFM32GG980F512 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32GG980F512_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F512_BitFields EFM32GG980F512 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_prs_signals.h"
|
||||
#include "efm32gg_dmareq.h"
|
||||
#include "efm32gg_dmactrl.h"
|
||||
#include "efm32gg_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F512_UNLOCK EFM32GG980F512 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
|
||||
|
||||
/** @} End of group EFM32GG980F512_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32GG980F512_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG980F512_Alternate_Function EFM32GG980F512 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_af_ports.h"
|
||||
#include "efm32gg_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32GG980F512_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32GG980F512 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* EFM32GG980F512_H */
|
||||
|
|
@ -2,10 +2,10 @@
|
|||
* @file efm32gg990f1024.h
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32GG990F1024
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -51,57 +51,57 @@ extern "C" {
|
|||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers *******************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ********************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M3 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< -13 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< -11 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< -10 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< -5 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< -2 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< -1 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers **********************************************/
|
||||
DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
|
||||
USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */
|
||||
ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */
|
||||
I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */
|
||||
GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */
|
||||
TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */
|
||||
USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */
|
||||
LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */
|
||||
USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */
|
||||
UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */
|
||||
UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */
|
||||
LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */
|
||||
BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */
|
||||
CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */
|
||||
EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */
|
||||
EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */
|
||||
/****** EFM32G Peripheral Interrupt Numbers ***********************************************/
|
||||
DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */
|
||||
USB_IRQn = 5, /*!< 5 EFM32 USB Interrupt */
|
||||
ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */
|
||||
I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */
|
||||
GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */
|
||||
TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */
|
||||
USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */
|
||||
LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */
|
||||
USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 20, /*!< 20 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 21, /*!< 21 EFM32 UART0_TX Interrupt */
|
||||
UART1_RX_IRQn = 22, /*!< 22 EFM32 UART1_RX Interrupt */
|
||||
UART1_TX_IRQn = 23, /*!< 23 EFM32 UART1_TX Interrupt */
|
||||
LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */
|
||||
BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */
|
||||
CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 34, /*!< 34 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */
|
||||
EBI_IRQn = 37, /*!< 37 EFM32 EBI Interrupt */
|
||||
EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -110,6 +110,7 @@ typedef enum IRQn
|
|||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
|
|
@ -123,6 +124,8 @@ typedef enum IRQn
|
|||
/** Part family */
|
||||
#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
|
||||
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
|
||||
#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
|
||||
|
||||
|
|
@ -181,6 +184,7 @@ typedef enum IRQn
|
|||
#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
|
||||
#define EXT_IRQ_COUNT 39 /**< Number of External (NVIC) interrupts */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 163
|
||||
|
|
|
|||
|
|
@ -0,0 +1,483 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg990f512.h
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32GG990F512
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef EFM32GG990F512_H
|
||||
#define EFM32GG990F512_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG990F512 EFM32GG990F512
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ********************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M3 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< -13 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< -11 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< -10 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< -5 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< -2 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< -1 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers ***********************************************/
|
||||
DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */
|
||||
USB_IRQn = 5, /*!< 5 EFM32 USB Interrupt */
|
||||
ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */
|
||||
I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */
|
||||
GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */
|
||||
TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */
|
||||
USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */
|
||||
LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */
|
||||
USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 20, /*!< 20 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 21, /*!< 21 EFM32 UART0_TX Interrupt */
|
||||
UART1_RX_IRQn = 22, /*!< 22 EFM32 UART1_RX Interrupt */
|
||||
UART1_TX_IRQn = 23, /*!< 23 EFM32 UART1_TX Interrupt */
|
||||
LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */
|
||||
BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */
|
||||
CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 34, /*!< 34 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */
|
||||
EBI_IRQn = 37, /*!< 37 EFM32 EBI Interrupt */
|
||||
EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG990F512_Core EFM32GG990F512 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32GG990F512_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG990F512_Part EFM32GG990F512 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
|
||||
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
|
||||
#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32GG990F512)
|
||||
#define EFM32GG990F512 1 /**< Giant/Leopard Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32GG990F512" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
|
||||
#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
|
||||
#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
|
||||
#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
|
||||
#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
|
||||
#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
|
||||
#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
|
||||
#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32GG990F512 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
|
||||
#define EXT_IRQ_COUNT 39 /**< Number of External (NVIC) interrupts */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 163
|
||||
#define AFCHANLOC_MAX 7
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 53
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 2 /**< 2 UARTs available */
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 4 /**< 4 TIMERs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 2 /**< 2 I2Cs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define USBC_PRESENT
|
||||
#define USBC_COUNT 1
|
||||
#define USB_PRESENT
|
||||
#define USB_COUNT 1
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define LESENSE_PRESENT
|
||||
#define LESENSE_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define OPAMP_PRESENT
|
||||
#define OPAMP_COUNT 1
|
||||
#define BU_PRESENT
|
||||
#define BU_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define BURTC_PRESENT
|
||||
#define BURTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
#define ETM_PRESENT
|
||||
#define ETM_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define ANALOG_PRESENT
|
||||
#define ANALOG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32gg.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32GG990F512_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG990F512_Peripheral_TypeDefs EFM32GG990F512 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_dma_ch.h"
|
||||
#include "efm32gg_dma.h"
|
||||
#include "efm32gg_aes.h"
|
||||
#include "efm32gg_usb_hc.h"
|
||||
#include "efm32gg_usb_diep.h"
|
||||
#include "efm32gg_usb_doep.h"
|
||||
#include "efm32gg_usb.h"
|
||||
#include "efm32gg_msc.h"
|
||||
#include "efm32gg_emu.h"
|
||||
#include "efm32gg_rmu.h"
|
||||
#include "efm32gg_cmu.h"
|
||||
#include "efm32gg_lesense_st.h"
|
||||
#include "efm32gg_lesense_buf.h"
|
||||
#include "efm32gg_lesense_ch.h"
|
||||
#include "efm32gg_lesense.h"
|
||||
#include "efm32gg_rtc.h"
|
||||
#include "efm32gg_letimer.h"
|
||||
#include "efm32gg_ebi.h"
|
||||
#include "efm32gg_usart.h"
|
||||
#include "efm32gg_timer_cc.h"
|
||||
#include "efm32gg_timer.h"
|
||||
#include "efm32gg_acmp.h"
|
||||
#include "efm32gg_i2c.h"
|
||||
#include "efm32gg_gpio_p.h"
|
||||
#include "efm32gg_gpio.h"
|
||||
#include "efm32gg_vcmp.h"
|
||||
#include "efm32gg_prs_ch.h"
|
||||
#include "efm32gg_prs.h"
|
||||
#include "efm32gg_leuart.h"
|
||||
#include "efm32gg_pcnt.h"
|
||||
#include "efm32gg_adc.h"
|
||||
#include "efm32gg_dac.h"
|
||||
#include "efm32gg_lcd.h"
|
||||
#include "efm32gg_burtc_ret.h"
|
||||
#include "efm32gg_burtc.h"
|
||||
#include "efm32gg_wdog.h"
|
||||
#include "efm32gg_etm.h"
|
||||
#include "efm32gg_dma_descriptor.h"
|
||||
#include "efm32gg_devinfo.h"
|
||||
#include "efm32gg_romtable.h"
|
||||
#include "efm32gg_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32GG990F512_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG990F512_Peripheral_Base EFM32GG990F512 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define USB_BASE (0x400C4000UL) /**< USB base address */
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define UART1_BASE (0x4000E400UL) /**< UART1 base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define BURTC_BASE (0x40081000UL) /**< BURTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
|
||||
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
|
||||
|
||||
/** @} End of group EFM32GG990F512_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG990F512_Peripheral_Declaration EFM32GG990F512 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32GG990F512_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG990F512_BitFields EFM32GG990F512 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_prs_signals.h"
|
||||
#include "efm32gg_dmareq.h"
|
||||
#include "efm32gg_dmactrl.h"
|
||||
#include "efm32gg_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG990F512_UNLOCK EFM32GG990F512 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
|
||||
|
||||
/** @} End of group EFM32GG990F512_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32GG990F512_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG990F512_Alternate_Function EFM32GG990F512 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_af_ports.h"
|
||||
#include "efm32gg_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32GG990F512_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32GG990F512 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* EFM32GG990F512_H */
|
||||
|
|
@ -0,0 +1,483 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg995f1024.h
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32GG995F1024
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef EFM32GG995F1024_H
|
||||
#define EFM32GG995F1024_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F1024 EFM32GG995F1024
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ********************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M3 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< -13 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< -11 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< -10 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< -5 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< -2 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< -1 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers ***********************************************/
|
||||
DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */
|
||||
USB_IRQn = 5, /*!< 5 EFM32 USB Interrupt */
|
||||
ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */
|
||||
I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */
|
||||
GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */
|
||||
TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */
|
||||
USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */
|
||||
LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */
|
||||
USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 20, /*!< 20 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 21, /*!< 21 EFM32 UART0_TX Interrupt */
|
||||
UART1_RX_IRQn = 22, /*!< 22 EFM32 UART1_RX Interrupt */
|
||||
UART1_TX_IRQn = 23, /*!< 23 EFM32 UART1_TX Interrupt */
|
||||
LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */
|
||||
BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */
|
||||
CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 34, /*!< 34 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */
|
||||
EBI_IRQn = 37, /*!< 37 EFM32 EBI Interrupt */
|
||||
EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F1024_Core EFM32GG995F1024 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32GG995F1024_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F1024_Part EFM32GG995F1024 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
|
||||
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
|
||||
#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32GG995F1024)
|
||||
#define EFM32GG995F1024 1 /**< Giant/Leopard Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32GG995F1024" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
|
||||
#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
|
||||
#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
|
||||
#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
|
||||
#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
|
||||
#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
|
||||
#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
|
||||
#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32GG995F1024 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
|
||||
#define EXT_IRQ_COUNT 39 /**< Number of External (NVIC) interrupts */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 163
|
||||
#define AFCHANLOC_MAX 7
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 53
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 2 /**< 2 UARTs available */
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 4 /**< 4 TIMERs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 2 /**< 2 I2Cs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define USBC_PRESENT
|
||||
#define USBC_COUNT 1
|
||||
#define USB_PRESENT
|
||||
#define USB_COUNT 1
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define LESENSE_PRESENT
|
||||
#define LESENSE_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define OPAMP_PRESENT
|
||||
#define OPAMP_COUNT 1
|
||||
#define BU_PRESENT
|
||||
#define BU_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define BURTC_PRESENT
|
||||
#define BURTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
#define ETM_PRESENT
|
||||
#define ETM_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define ANALOG_PRESENT
|
||||
#define ANALOG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32gg.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32GG995F1024_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F1024_Peripheral_TypeDefs EFM32GG995F1024 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_dma_ch.h"
|
||||
#include "efm32gg_dma.h"
|
||||
#include "efm32gg_aes.h"
|
||||
#include "efm32gg_usb_hc.h"
|
||||
#include "efm32gg_usb_diep.h"
|
||||
#include "efm32gg_usb_doep.h"
|
||||
#include "efm32gg_usb.h"
|
||||
#include "efm32gg_msc.h"
|
||||
#include "efm32gg_emu.h"
|
||||
#include "efm32gg_rmu.h"
|
||||
#include "efm32gg_cmu.h"
|
||||
#include "efm32gg_lesense_st.h"
|
||||
#include "efm32gg_lesense_buf.h"
|
||||
#include "efm32gg_lesense_ch.h"
|
||||
#include "efm32gg_lesense.h"
|
||||
#include "efm32gg_rtc.h"
|
||||
#include "efm32gg_letimer.h"
|
||||
#include "efm32gg_ebi.h"
|
||||
#include "efm32gg_usart.h"
|
||||
#include "efm32gg_timer_cc.h"
|
||||
#include "efm32gg_timer.h"
|
||||
#include "efm32gg_acmp.h"
|
||||
#include "efm32gg_i2c.h"
|
||||
#include "efm32gg_gpio_p.h"
|
||||
#include "efm32gg_gpio.h"
|
||||
#include "efm32gg_vcmp.h"
|
||||
#include "efm32gg_prs_ch.h"
|
||||
#include "efm32gg_prs.h"
|
||||
#include "efm32gg_leuart.h"
|
||||
#include "efm32gg_pcnt.h"
|
||||
#include "efm32gg_adc.h"
|
||||
#include "efm32gg_dac.h"
|
||||
#include "efm32gg_lcd.h"
|
||||
#include "efm32gg_burtc_ret.h"
|
||||
#include "efm32gg_burtc.h"
|
||||
#include "efm32gg_wdog.h"
|
||||
#include "efm32gg_etm.h"
|
||||
#include "efm32gg_dma_descriptor.h"
|
||||
#include "efm32gg_devinfo.h"
|
||||
#include "efm32gg_romtable.h"
|
||||
#include "efm32gg_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32GG995F1024_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F1024_Peripheral_Base EFM32GG995F1024 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define USB_BASE (0x400C4000UL) /**< USB base address */
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define UART1_BASE (0x4000E400UL) /**< UART1 base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define BURTC_BASE (0x40081000UL) /**< BURTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
|
||||
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
|
||||
|
||||
/** @} End of group EFM32GG995F1024_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F1024_Peripheral_Declaration EFM32GG995F1024 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32GG995F1024_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F1024_BitFields EFM32GG995F1024 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_prs_signals.h"
|
||||
#include "efm32gg_dmareq.h"
|
||||
#include "efm32gg_dmactrl.h"
|
||||
#include "efm32gg_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F1024_UNLOCK EFM32GG995F1024 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
|
||||
|
||||
/** @} End of group EFM32GG995F1024_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32GG995F1024_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F1024_Alternate_Function EFM32GG995F1024 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_af_ports.h"
|
||||
#include "efm32gg_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32GG995F1024_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32GG995F1024 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* EFM32GG995F1024_H */
|
||||
|
|
@ -0,0 +1,483 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg995f512.h
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32GG995F512
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef EFM32GG995F512_H
|
||||
#define EFM32GG995F512_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F512 EFM32GG995F512
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ********************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M3 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< -13 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< -11 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< -10 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< -5 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< -2 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< -1 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers ***********************************************/
|
||||
DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */
|
||||
USB_IRQn = 5, /*!< 5 EFM32 USB Interrupt */
|
||||
ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */
|
||||
I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */
|
||||
GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */
|
||||
TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */
|
||||
USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */
|
||||
LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */
|
||||
USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 20, /*!< 20 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 21, /*!< 21 EFM32 UART0_TX Interrupt */
|
||||
UART1_RX_IRQn = 22, /*!< 22 EFM32 UART1_RX Interrupt */
|
||||
UART1_TX_IRQn = 23, /*!< 23 EFM32 UART1_TX Interrupt */
|
||||
LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */
|
||||
BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */
|
||||
CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 34, /*!< 34 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */
|
||||
EBI_IRQn = 37, /*!< 37 EFM32 EBI Interrupt */
|
||||
EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F512_Core EFM32GG995F512 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32GG995F512_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F512_Part EFM32GG995F512 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
|
||||
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
|
||||
#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32GG995F512)
|
||||
#define EFM32GG995F512 1 /**< Giant/Leopard Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32GG995F512" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
|
||||
#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
|
||||
#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
|
||||
#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
|
||||
#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
|
||||
#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
|
||||
#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
|
||||
#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32GG995F512 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
|
||||
#define EXT_IRQ_COUNT 39 /**< Number of External (NVIC) interrupts */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 163
|
||||
#define AFCHANLOC_MAX 7
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 53
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 2 /**< 2 UARTs available */
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 4 /**< 4 TIMERs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 2 /**< 2 I2Cs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define USBC_PRESENT
|
||||
#define USBC_COUNT 1
|
||||
#define USB_PRESENT
|
||||
#define USB_COUNT 1
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define LESENSE_PRESENT
|
||||
#define LESENSE_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define OPAMP_PRESENT
|
||||
#define OPAMP_COUNT 1
|
||||
#define BU_PRESENT
|
||||
#define BU_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define BURTC_PRESENT
|
||||
#define BURTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
#define ETM_PRESENT
|
||||
#define ETM_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define ANALOG_PRESENT
|
||||
#define ANALOG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32gg.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32GG995F512_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F512_Peripheral_TypeDefs EFM32GG995F512 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_dma_ch.h"
|
||||
#include "efm32gg_dma.h"
|
||||
#include "efm32gg_aes.h"
|
||||
#include "efm32gg_usb_hc.h"
|
||||
#include "efm32gg_usb_diep.h"
|
||||
#include "efm32gg_usb_doep.h"
|
||||
#include "efm32gg_usb.h"
|
||||
#include "efm32gg_msc.h"
|
||||
#include "efm32gg_emu.h"
|
||||
#include "efm32gg_rmu.h"
|
||||
#include "efm32gg_cmu.h"
|
||||
#include "efm32gg_lesense_st.h"
|
||||
#include "efm32gg_lesense_buf.h"
|
||||
#include "efm32gg_lesense_ch.h"
|
||||
#include "efm32gg_lesense.h"
|
||||
#include "efm32gg_rtc.h"
|
||||
#include "efm32gg_letimer.h"
|
||||
#include "efm32gg_ebi.h"
|
||||
#include "efm32gg_usart.h"
|
||||
#include "efm32gg_timer_cc.h"
|
||||
#include "efm32gg_timer.h"
|
||||
#include "efm32gg_acmp.h"
|
||||
#include "efm32gg_i2c.h"
|
||||
#include "efm32gg_gpio_p.h"
|
||||
#include "efm32gg_gpio.h"
|
||||
#include "efm32gg_vcmp.h"
|
||||
#include "efm32gg_prs_ch.h"
|
||||
#include "efm32gg_prs.h"
|
||||
#include "efm32gg_leuart.h"
|
||||
#include "efm32gg_pcnt.h"
|
||||
#include "efm32gg_adc.h"
|
||||
#include "efm32gg_dac.h"
|
||||
#include "efm32gg_lcd.h"
|
||||
#include "efm32gg_burtc_ret.h"
|
||||
#include "efm32gg_burtc.h"
|
||||
#include "efm32gg_wdog.h"
|
||||
#include "efm32gg_etm.h"
|
||||
#include "efm32gg_dma_descriptor.h"
|
||||
#include "efm32gg_devinfo.h"
|
||||
#include "efm32gg_romtable.h"
|
||||
#include "efm32gg_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32GG995F512_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F512_Peripheral_Base EFM32GG995F512 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define USB_BASE (0x400C4000UL) /**< USB base address */
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define UART1_BASE (0x4000E400UL) /**< UART1 base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define BURTC_BASE (0x40081000UL) /**< BURTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
|
||||
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
|
||||
|
||||
/** @} End of group EFM32GG995F512_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F512_Peripheral_Declaration EFM32GG995F512 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32GG995F512_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F512_BitFields EFM32GG995F512 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_prs_signals.h"
|
||||
#include "efm32gg_dmareq.h"
|
||||
#include "efm32gg_dmactrl.h"
|
||||
#include "efm32gg_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F512_UNLOCK EFM32GG995F512 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
|
||||
|
||||
/** @} End of group EFM32GG995F512_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32GG995F512_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG995F512_Alternate_Function EFM32GG995F512 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32gg_af_ports.h"
|
||||
#include "efm32gg_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32GG995F512_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32GG995F512 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* EFM32GG995F512_H */
|
||||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_acmp.h
|
||||
* @brief EFM32GG_ACMP register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,15 +40,15 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t INPUTSEL; /**< Input Selection Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
} ACMP_TypeDef; /** @} */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t INPUTSEL; /**< Input Selection Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t ROUTE; /**< I/O Routing Register */
|
||||
} ACMP_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_ACMP_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_adc.h
|
||||
* @brief EFM32GG_ADC register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,24 +40,24 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t SINGLECTRL; /**< Single Sample Control Register */
|
||||
__IO uint32_t SCANCTRL; /**< Scan Control Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__I uint32_t SINGLEDATA; /**< Single Conversion Result Data */
|
||||
__I uint32_t SCANDATA; /**< Scan Conversion Result Data */
|
||||
__I uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */
|
||||
__I uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */
|
||||
__IO uint32_t CAL; /**< Calibration Register */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t SINGLECTRL; /**< Single Sample Control Register */
|
||||
__IOM uint32_t SCANCTRL; /**< Scan Control Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IM uint32_t SINGLEDATA; /**< Single Conversion Result Data */
|
||||
__IM uint32_t SCANDATA; /**< Scan Conversion Result Data */
|
||||
__IM uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */
|
||||
__IM uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */
|
||||
__IOM uint32_t CAL; /**< Calibration Register */
|
||||
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t BIASPROG; /**< Bias Programming Register */
|
||||
} ADC_TypeDef; /** @} */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t BIASPROG; /**< Bias Programming Register */
|
||||
} ADC_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_ADC_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_aes.h
|
||||
* @brief EFM32GG_AES register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,25 +40,25 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t DATA; /**< DATA Register */
|
||||
__IO uint32_t XORDATA; /**< XORDATA Register */
|
||||
uint32_t RESERVED0[3]; /**< Reserved for future use **/
|
||||
__IO uint32_t KEYLA; /**< KEY Low Register */
|
||||
__IO uint32_t KEYLB; /**< KEY Low Register */
|
||||
__IO uint32_t KEYLC; /**< KEY Low Register */
|
||||
__IO uint32_t KEYLD; /**< KEY Low Register */
|
||||
__IO uint32_t KEYHA; /**< KEY High Register */
|
||||
__IO uint32_t KEYHB; /**< KEY High Register */
|
||||
__IO uint32_t KEYHC; /**< KEY High Register */
|
||||
__IO uint32_t KEYHD; /**< KEY High Register */
|
||||
} AES_TypeDef; /** @} */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t DATA; /**< DATA Register */
|
||||
__IOM uint32_t XORDATA; /**< XORDATA Register */
|
||||
uint32_t RESERVED0[3]; /**< Reserved for future use **/
|
||||
__IOM uint32_t KEYLA; /**< KEY Low Register */
|
||||
__IOM uint32_t KEYLB; /**< KEY Low Register */
|
||||
__IOM uint32_t KEYLC; /**< KEY Low Register */
|
||||
__IOM uint32_t KEYLD; /**< KEY Low Register */
|
||||
__IOM uint32_t KEYHA; /**< KEY High Register */
|
||||
__IOM uint32_t KEYHB; /**< KEY High Register */
|
||||
__IOM uint32_t KEYHC; /**< KEY High Register */
|
||||
__IOM uint32_t KEYHD; /**< KEY High Register */
|
||||
} AES_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_AES_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_af_pins.h
|
||||
* @brief EFM32GG_AF_PINS register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_af_ports.h
|
||||
* @brief EFM32GG_AF_PORTS register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_burtc.h
|
||||
* @brief EFM32GG_BURTC register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,23 +40,23 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t LPMODE; /**< Low power mode configuration */
|
||||
__I uint32_t CNT; /**< Counter Value Register */
|
||||
__IO uint32_t COMP0; /**< Counter Compare Value */
|
||||
__I uint32_t TIMESTAMP; /**< Backup mode timestamp */
|
||||
__IO uint32_t LFXOFDET; /**< LFXO */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__IO uint32_t POWERDOWN; /**< Retention RAM power-down Register */
|
||||
__IO uint32_t LOCK; /**< Configuration Lock Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t LPMODE; /**< Low power mode configuration */
|
||||
__IM uint32_t CNT; /**< Counter Value Register */
|
||||
__IOM uint32_t COMP0; /**< Counter Compare Value */
|
||||
__IM uint32_t TIMESTAMP; /**< Backup mode timestamp */
|
||||
__IOM uint32_t LFXOFDET; /**< LFXO */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IOM uint32_t POWERDOWN; /**< Retention RAM power-down Register */
|
||||
__IOM uint32_t LOCK; /**< Configuration Lock Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
|
||||
__IO uint32_t FREEZE; /**< Freeze Register */
|
||||
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
__IOM uint32_t FREEZE; /**< Freeze Register */
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
|
||||
uint32_t RESERVED0[48]; /**< Reserved registers */
|
||||
BURTC_RET_TypeDef RET[128]; /**< RetentionReg */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_burtc_ret.h
|
||||
* @brief EFM32GG_BURTC_RET register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -38,7 +38,7 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t REG; /**< Retention Register */
|
||||
__IOM uint32_t REG; /**< Retention Register */
|
||||
} BURTC_RET_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_calibrate.h
|
||||
* @brief EFM32GG_CALIBRATE register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -41,9 +41,9 @@
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__I uint32_t ADDRESS; /**< Address of calibration register */
|
||||
__I uint32_t VALUE; /**< Default value for calibration register */
|
||||
} CALIBRATE_TypeDef; /** @} */
|
||||
__IM uint32_t ADDRESS; /**< Address of calibration register */
|
||||
__IM uint32_t VALUE; /**< Default value for calibration register */
|
||||
} CALIBRATE_TypeDef; /** @} */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_cmu.h
|
||||
* @brief EFM32GG_CMU register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,41 +40,41 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< CMU Control Register */
|
||||
__IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */
|
||||
__IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */
|
||||
__IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */
|
||||
__IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */
|
||||
__IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
|
||||
__IO uint32_t CALCTRL; /**< Calibration Control Register */
|
||||
__IO uint32_t CALCNT; /**< Calibration Counter Register */
|
||||
__IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */
|
||||
__IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
|
||||
uint32_t RESERVED0[2]; /**< Reserved for future use **/
|
||||
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
__IO uint32_t FREEZE; /**< Freeze Register */
|
||||
__IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */
|
||||
uint32_t RESERVED1[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
|
||||
__IOM uint32_t CTRL; /**< CMU Control Register */
|
||||
__IOM uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */
|
||||
__IOM uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */
|
||||
__IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */
|
||||
__IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */
|
||||
__IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
|
||||
__IOM uint32_t CALCTRL; /**< Calibration Control Register */
|
||||
__IOM uint32_t CALCNT; /**< Calibration Counter Register */
|
||||
__IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IOM uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */
|
||||
__IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
|
||||
uint32_t RESERVED0[2]; /**< Reserved for future use **/
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
__IOM uint32_t FREEZE; /**< Freeze Register */
|
||||
__IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */
|
||||
uint32_t RESERVED1[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
|
||||
|
||||
uint32_t RESERVED2[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */
|
||||
uint32_t RESERVED3[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
|
||||
uint32_t RESERVED4[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t PCNTCTRL; /**< PCNT Control Register */
|
||||
__IO uint32_t LCDCTRL; /**< LCD Control Register */
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
__IO uint32_t LOCK; /**< Configuration Lock Register */
|
||||
} CMU_TypeDef; /** @} */
|
||||
uint32_t RESERVED2[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */
|
||||
uint32_t RESERVED3[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
|
||||
uint32_t RESERVED4[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t PCNTCTRL; /**< PCNT Control Register */
|
||||
__IOM uint32_t LCDCTRL; /**< LCD Control Register */
|
||||
__IOM uint32_t ROUTE; /**< I/O Routing Register */
|
||||
__IOM uint32_t LOCK; /**< Configuration Lock Register */
|
||||
} CMU_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_CMU_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_dac.h
|
||||
* @brief EFM32GG_DAC register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,26 +40,26 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t CH0CTRL; /**< Channel 0 Control Register */
|
||||
__IO uint32_t CH1CTRL; /**< Channel 1 Control Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t CH0DATA; /**< Channel 0 Data Register */
|
||||
__IO uint32_t CH1DATA; /**< Channel 1 Data Register */
|
||||
__IO uint32_t COMBDATA; /**< Combined Data Register */
|
||||
__IO uint32_t CAL; /**< Calibration Register */
|
||||
__IO uint32_t BIASPROG; /**< Bias Programming Register */
|
||||
uint32_t RESERVED0[8]; /**< Reserved for future use **/
|
||||
__IO uint32_t OPACTRL; /**< Operational Amplifier Control Register */
|
||||
__IO uint32_t OPAOFFSET; /**< Operational Amplifier Offset Register */
|
||||
__IO uint32_t OPA0MUX; /**< Operational Amplifier Mux Configuration Register */
|
||||
__IO uint32_t OPA1MUX; /**< Operational Amplifier Mux Configuration Register */
|
||||
__IO uint32_t OPA2MUX; /**< Operational Amplifier Mux Configuration Register */
|
||||
} DAC_TypeDef; /** @} */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t CH0CTRL; /**< Channel 0 Control Register */
|
||||
__IOM uint32_t CH1CTRL; /**< Channel 1 Control Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t CH0DATA; /**< Channel 0 Data Register */
|
||||
__IOM uint32_t CH1DATA; /**< Channel 1 Data Register */
|
||||
__IOM uint32_t COMBDATA; /**< Combined Data Register */
|
||||
__IOM uint32_t CAL; /**< Calibration Register */
|
||||
__IOM uint32_t BIASPROG; /**< Bias Programming Register */
|
||||
uint32_t RESERVED0[8]; /**< Reserved for future use **/
|
||||
__IOM uint32_t OPACTRL; /**< Operational Amplifier Control Register */
|
||||
__IOM uint32_t OPAOFFSET; /**< Operational Amplifier Offset Register */
|
||||
__IOM uint32_t OPA0MUX; /**< Operational Amplifier Mux Configuration Register */
|
||||
__IOM uint32_t OPA1MUX; /**< Operational Amplifier Mux Configuration Register */
|
||||
__IOM uint32_t OPA2MUX; /**< Operational Amplifier Mux Configuration Register */
|
||||
} DAC_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_DAC_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_devinfo.h
|
||||
* @brief EFM32GG_DEVINFO register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -39,25 +39,25 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__I uint32_t CAL; /**< Calibration temperature and checksum */
|
||||
__I uint32_t ADC0CAL0; /**< ADC0 Calibration register 0 */
|
||||
__I uint32_t ADC0CAL1; /**< ADC0 Calibration register 1 */
|
||||
__I uint32_t ADC0CAL2; /**< ADC0 Calibration register 2 */
|
||||
uint32_t RESERVED0[2]; /**< Reserved */
|
||||
__I uint32_t DAC0CAL0; /**< DAC calibrartion register 0 */
|
||||
__I uint32_t DAC0CAL1; /**< DAC calibrartion register 1 */
|
||||
__I uint32_t DAC0CAL2; /**< DAC calibrartion register 2 */
|
||||
__I uint32_t AUXHFRCOCAL0; /**< AUXHFRCO calibration register 0 */
|
||||
__I uint32_t AUXHFRCOCAL1; /**< AUXHFRCO calibration register 1 */
|
||||
__I uint32_t HFRCOCAL0; /**< HFRCO calibration register 0 */
|
||||
__I uint32_t HFRCOCAL1; /**< HFRCO calibration register 1 */
|
||||
__I uint32_t MEMINFO; /**< Memory information */
|
||||
uint32_t RESERVED2[2]; /**< Reserved */
|
||||
__I uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
|
||||
__I uint32_t UNIQUEH; /**< High 32 bits of device unique number */
|
||||
__I uint32_t MSIZE; /**< Flash and SRAM Memory size in KiloBytes */
|
||||
__I uint32_t PART; /**< Part description */
|
||||
} DEVINFO_TypeDef; /** @} */
|
||||
__IM uint32_t CAL; /**< Calibration temperature and checksum */
|
||||
__IM uint32_t ADC0CAL0; /**< ADC0 Calibration register 0 */
|
||||
__IM uint32_t ADC0CAL1; /**< ADC0 Calibration register 1 */
|
||||
__IM uint32_t ADC0CAL2; /**< ADC0 Calibration register 2 */
|
||||
uint32_t RESERVED0[2]; /**< Reserved */
|
||||
__IM uint32_t DAC0CAL0; /**< DAC calibrartion register 0 */
|
||||
__IM uint32_t DAC0CAL1; /**< DAC calibrartion register 1 */
|
||||
__IM uint32_t DAC0CAL2; /**< DAC calibrartion register 2 */
|
||||
__IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO calibration register 0 */
|
||||
__IM uint32_t AUXHFRCOCAL1; /**< AUXHFRCO calibration register 1 */
|
||||
__IM uint32_t HFRCOCAL0; /**< HFRCO calibration register 0 */
|
||||
__IM uint32_t HFRCOCAL1; /**< HFRCO calibration register 1 */
|
||||
__IM uint32_t MEMINFO; /**< Memory information */
|
||||
uint32_t RESERVED2[2]; /**< Reserved */
|
||||
__IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
|
||||
__IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */
|
||||
__IM uint32_t MSIZE; /**< Flash and SRAM Memory size in KiloBytes */
|
||||
__IM uint32_t PART; /**< Part description */
|
||||
} DEVINFO_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_DEVINFO_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_dma.h
|
||||
* @brief EFM32GG_DMA register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,43 +40,43 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__I uint32_t STATUS; /**< DMA Status Registers */
|
||||
__O uint32_t CONFIG; /**< DMA Configuration Register */
|
||||
__IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */
|
||||
__I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */
|
||||
__I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */
|
||||
__O uint32_t CHSWREQ; /**< Channel Software Request Register */
|
||||
__IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */
|
||||
__O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */
|
||||
__IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */
|
||||
__O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */
|
||||
__IO uint32_t CHENS; /**< Channel Enable Set Register */
|
||||
__O uint32_t CHENC; /**< Channel Enable Clear Register */
|
||||
__IO uint32_t CHALTS; /**< Channel Alternate Set Register */
|
||||
__O uint32_t CHALTC; /**< Channel Alternate Clear Register */
|
||||
__IO uint32_t CHPRIS; /**< Channel Priority Set Register */
|
||||
__O uint32_t CHPRIC; /**< Channel Priority Clear Register */
|
||||
__IM uint32_t STATUS; /**< DMA Status Registers */
|
||||
__OM uint32_t CONFIG; /**< DMA Configuration Register */
|
||||
__IOM uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */
|
||||
__IM uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */
|
||||
__IM uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */
|
||||
__OM uint32_t CHSWREQ; /**< Channel Software Request Register */
|
||||
__IOM uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */
|
||||
__OM uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */
|
||||
__IOM uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */
|
||||
__OM uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */
|
||||
__IOM uint32_t CHENS; /**< Channel Enable Set Register */
|
||||
__OM uint32_t CHENC; /**< Channel Enable Clear Register */
|
||||
__IOM uint32_t CHALTS; /**< Channel Alternate Set Register */
|
||||
__OM uint32_t CHALTC; /**< Channel Alternate Clear Register */
|
||||
__IOM uint32_t CHPRIS; /**< Channel Priority Set Register */
|
||||
__OM uint32_t CHPRIC; /**< Channel Priority Clear Register */
|
||||
uint32_t RESERVED0[3]; /**< Reserved for future use **/
|
||||
__IO uint32_t ERRORC; /**< Bus Error Clear Register */
|
||||
__IOM uint32_t ERRORC; /**< Bus Error Clear Register */
|
||||
|
||||
uint32_t RESERVED1[880]; /**< Reserved for future use **/
|
||||
__I uint32_t CHREQSTATUS; /**< Channel Request Status */
|
||||
__IM uint32_t CHREQSTATUS; /**< Channel Request Status */
|
||||
uint32_t RESERVED2[1]; /**< Reserved for future use **/
|
||||
__I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */
|
||||
__IM uint32_t CHSREQSTATUS; /**< Channel Single Request Status */
|
||||
|
||||
uint32_t RESERVED3[121]; /**< Reserved for future use **/
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable register */
|
||||
__IO uint32_t CTRL; /**< DMA Control Register */
|
||||
__IO uint32_t RDS; /**< DMA Retain Descriptor State */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable register */
|
||||
__IOM uint32_t CTRL; /**< DMA Control Register */
|
||||
__IOM uint32_t RDS; /**< DMA Retain Descriptor State */
|
||||
|
||||
uint32_t RESERVED4[2]; /**< Reserved for future use **/
|
||||
__IO uint32_t LOOP0; /**< Channel 0 Loop Register */
|
||||
__IO uint32_t LOOP1; /**< Channel 1 Loop Register */
|
||||
__IOM uint32_t LOOP0; /**< Channel 0 Loop Register */
|
||||
__IOM uint32_t LOOP1; /**< Channel 1 Loop Register */
|
||||
uint32_t RESERVED5[14]; /**< Reserved for future use **/
|
||||
__IO uint32_t RECT0; /**< Channel 0 Rectangle Register */
|
||||
__IOM uint32_t RECT0; /**< Channel 0 Rectangle Register */
|
||||
|
||||
uint32_t RESERVED6[39]; /**< Reserved registers */
|
||||
DMA_CH_TypeDef CH[12]; /**< Channel registers */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_dma_ch.h
|
||||
* @brief EFM32GG_DMA_CH register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -38,7 +38,7 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Channel Control Register */
|
||||
__IOM uint32_t CTRL; /**< Channel Control Register */
|
||||
} DMA_CH_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_dma_descriptor.h
|
||||
* @brief EFM32GG_DMA_DESCRIPTOR register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -39,12 +39,12 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
/* Note! Use of double __IO (volatile) qualifier to ensure that both */
|
||||
/* Note! Use of double __IOM (volatile) qualifier to ensure that both */
|
||||
/* pointer and referenced memory are declared volatile. */
|
||||
__IO void * __IO SRCEND; /**< DMA source address end */
|
||||
__IO void * __IO DSTEND; /**< DMA destination address end */
|
||||
__IO uint32_t CTRL; /**< DMA control register */
|
||||
__IO uint32_t USER; /**< DMA padding register, available for user */
|
||||
__IOM void * __IOM SRCEND; /**< DMA source address end */
|
||||
__IOM void * __IOM DSTEND; /**< DMA destination address end */
|
||||
__IOM uint32_t CTRL; /**< DMA control register */
|
||||
__IOM uint32_t USER; /**< DMA padding register, available for user */
|
||||
} DMA_DESCRIPTOR_TypeDef; /** @} */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_dmactrl.h
|
||||
* @brief EFM32GG_DMACTRL register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_dmareq.h
|
||||
* @brief EFM32GG_DMAREQ register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_ebi.h
|
||||
* @brief EFM32GG_EBI register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,49 +40,49 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t ADDRTIMING; /**< Address Timing Register */
|
||||
__IO uint32_t RDTIMING; /**< Read Timing Register */
|
||||
__IO uint32_t WRTIMING; /**< Write Timing Register */
|
||||
__IO uint32_t POLARITY; /**< Polarity Register */
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
__IO uint32_t ADDRTIMING1; /**< Address Timing Register 1 */
|
||||
__IO uint32_t RDTIMING1; /**< Read Timing Register 1 */
|
||||
__IO uint32_t WRTIMING1; /**< Write Timing Register 1 */
|
||||
__IO uint32_t POLARITY1; /**< Polarity Register 1 */
|
||||
__IO uint32_t ADDRTIMING2; /**< Address Timing Register 2 */
|
||||
__IO uint32_t RDTIMING2; /**< Read Timing Register 2 */
|
||||
__IO uint32_t WRTIMING2; /**< Write Timing Register 2 */
|
||||
__IO uint32_t POLARITY2; /**< Polarity Register 2 */
|
||||
__IO uint32_t ADDRTIMING3; /**< Address Timing Register 3 */
|
||||
__IO uint32_t RDTIMING3; /**< Read Timing Register 3 */
|
||||
__IO uint32_t WRTIMING3; /**< Write Timing Register 3 */
|
||||
__IO uint32_t POLARITY3; /**< Polarity Register 3 */
|
||||
__IO uint32_t PAGECTRL; /**< Page Control Register */
|
||||
__IO uint32_t NANDCTRL; /**< NAND Control Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__I uint32_t ECCPARITY; /**< ECC Parity register */
|
||||
__IO uint32_t TFTCTRL; /**< TFT Control Register */
|
||||
__I uint32_t TFTSTATUS; /**< TFT Status Register */
|
||||
__IO uint32_t TFTFRAMEBASE; /**< TFT Frame Base Register */
|
||||
__IO uint32_t TFTSTRIDE; /**< TFT Stride Register */
|
||||
__IO uint32_t TFTSIZE; /**< TFT Size Register */
|
||||
__IO uint32_t TFTHPORCH; /**< TFT Horizontal Porch Register */
|
||||
__IO uint32_t TFTVPORCH; /**< TFT Vertical Porch Register */
|
||||
__IO uint32_t TFTTIMING; /**< TFT Timing Register */
|
||||
__IO uint32_t TFTPOLARITY; /**< TFT Polarity Register */
|
||||
__IO uint32_t TFTDD; /**< TFT Direct Drive Data Register */
|
||||
__IO uint32_t TFTALPHA; /**< TFT Alpha Blending Register */
|
||||
__IO uint32_t TFTPIXEL0; /**< TFT Pixel 0 Register */
|
||||
__IO uint32_t TFTPIXEL1; /**< TFT Pixel 1 Register */
|
||||
__I uint32_t TFTPIXEL; /**< TFT Alpha Blending Result Pixel Register */
|
||||
__IO uint32_t TFTMASK; /**< TFT Masking Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
} EBI_TypeDef; /** @} */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t ADDRTIMING; /**< Address Timing Register */
|
||||
__IOM uint32_t RDTIMING; /**< Read Timing Register */
|
||||
__IOM uint32_t WRTIMING; /**< Write Timing Register */
|
||||
__IOM uint32_t POLARITY; /**< Polarity Register */
|
||||
__IOM uint32_t ROUTE; /**< I/O Routing Register */
|
||||
__IOM uint32_t ADDRTIMING1; /**< Address Timing Register 1 */
|
||||
__IOM uint32_t RDTIMING1; /**< Read Timing Register 1 */
|
||||
__IOM uint32_t WRTIMING1; /**< Write Timing Register 1 */
|
||||
__IOM uint32_t POLARITY1; /**< Polarity Register 1 */
|
||||
__IOM uint32_t ADDRTIMING2; /**< Address Timing Register 2 */
|
||||
__IOM uint32_t RDTIMING2; /**< Read Timing Register 2 */
|
||||
__IOM uint32_t WRTIMING2; /**< Write Timing Register 2 */
|
||||
__IOM uint32_t POLARITY2; /**< Polarity Register 2 */
|
||||
__IOM uint32_t ADDRTIMING3; /**< Address Timing Register 3 */
|
||||
__IOM uint32_t RDTIMING3; /**< Read Timing Register 3 */
|
||||
__IOM uint32_t WRTIMING3; /**< Write Timing Register 3 */
|
||||
__IOM uint32_t POLARITY3; /**< Polarity Register 3 */
|
||||
__IOM uint32_t PAGECTRL; /**< Page Control Register */
|
||||
__IOM uint32_t NANDCTRL; /**< NAND Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IM uint32_t ECCPARITY; /**< ECC Parity register */
|
||||
__IOM uint32_t TFTCTRL; /**< TFT Control Register */
|
||||
__IM uint32_t TFTSTATUS; /**< TFT Status Register */
|
||||
__IOM uint32_t TFTFRAMEBASE; /**< TFT Frame Base Register */
|
||||
__IOM uint32_t TFTSTRIDE; /**< TFT Stride Register */
|
||||
__IOM uint32_t TFTSIZE; /**< TFT Size Register */
|
||||
__IOM uint32_t TFTHPORCH; /**< TFT Horizontal Porch Register */
|
||||
__IOM uint32_t TFTVPORCH; /**< TFT Vertical Porch Register */
|
||||
__IOM uint32_t TFTTIMING; /**< TFT Timing Register */
|
||||
__IOM uint32_t TFTPOLARITY; /**< TFT Polarity Register */
|
||||
__IOM uint32_t TFTDD; /**< TFT Direct Drive Data Register */
|
||||
__IOM uint32_t TFTALPHA; /**< TFT Alpha Blending Register */
|
||||
__IOM uint32_t TFTPIXEL0; /**< TFT Pixel 0 Register */
|
||||
__IOM uint32_t TFTPIXEL1; /**< TFT Pixel 1 Register */
|
||||
__IM uint32_t TFTPIXEL; /**< TFT Alpha Blending Result Pixel Register */
|
||||
__IOM uint32_t TFTMASK; /**< TFT Masking Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
} EBI_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_EBI_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_emu.h
|
||||
* @brief EFM32GG_EMU register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,28 +40,28 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t MEMCTRL; /**< Memory Control Register */
|
||||
__IO uint32_t LOCK; /**< Configuration Lock Register */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t MEMCTRL; /**< Memory Control Register */
|
||||
__IOM uint32_t LOCK; /**< Configuration Lock Register */
|
||||
|
||||
uint32_t RESERVED0[6]; /**< Reserved for future use **/
|
||||
__IO uint32_t AUXCTRL; /**< Auxiliary Control Register */
|
||||
uint32_t RESERVED0[6]; /**< Reserved for future use **/
|
||||
__IOM uint32_t AUXCTRL; /**< Auxiliary Control Register */
|
||||
|
||||
uint32_t RESERVED1[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t EM4CONF; /**< Energy mode 4 configuration register */
|
||||
__IO uint32_t BUCTRL; /**< Backup Power configuration register */
|
||||
__IO uint32_t PWRCONF; /**< Power connection configuration register */
|
||||
__IO uint32_t BUINACT; /**< Backup mode inactive configuration register */
|
||||
__IO uint32_t BUACT; /**< Backup mode active configuration register */
|
||||
__I uint32_t STATUS; /**< Status register */
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IO uint32_t BUBODBUVINCAL; /**< BU_VIN Backup BOD calibration */
|
||||
__IO uint32_t BUBODUNREGCAL; /**< Unregulated power Backup BOD calibration */
|
||||
} EMU_TypeDef; /** @} */
|
||||
uint32_t RESERVED1[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t EM4CONF; /**< Energy mode 4 configuration register */
|
||||
__IOM uint32_t BUCTRL; /**< Backup Power configuration register */
|
||||
__IOM uint32_t PWRCONF; /**< Power connection configuration register */
|
||||
__IOM uint32_t BUINACT; /**< Backup mode inactive configuration register */
|
||||
__IOM uint32_t BUACT; /**< Backup mode active configuration register */
|
||||
__IM uint32_t STATUS; /**< Status register */
|
||||
__IOM uint32_t ROUTE; /**< I/O Routing Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t BUBODBUVINCAL; /**< BU_VIN Backup BOD calibration */
|
||||
__IOM uint32_t BUBODUNREGCAL; /**< Unregulated power Backup BOD calibration */
|
||||
} EMU_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_EMU_BitFields
|
||||
|
|
@ -169,35 +169,40 @@ typedef struct
|
|||
#define EMU_EM4CONF_LOCKCONF_DEFAULT (_EMU_EM4CONF_LOCKCONF_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CONF */
|
||||
|
||||
/* Bit fields for EMU BUCTRL */
|
||||
#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */
|
||||
#define _EMU_BUCTRL_MASK 0x00000067UL /**< Mask for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable backup mode */
|
||||
#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
|
||||
#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
|
||||
#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable backup mode status export */
|
||||
#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */
|
||||
#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */
|
||||
#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_BODCAL (0x1UL << 2) /**< Enable BOD calibration mode */
|
||||
#define _EMU_BUCTRL_BODCAL_SHIFT 2 /**< Shift value for EMU_BODCAL */
|
||||
#define _EMU_BUCTRL_BODCAL_MASK 0x4UL /**< Bit mask for EMU_BODCAL */
|
||||
#define _EMU_BUCTRL_BODCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_BODCAL_DEFAULT (_EMU_BUCTRL_BODCAL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */
|
||||
#define _EMU_BUCTRL_PROBE_SHIFT 5 /**< Shift value for EMU_PROBE */
|
||||
#define _EMU_BUCTRL_PROBE_MASK 0x60UL /**< Bit mask for EMU_PROBE */
|
||||
#define _EMU_BUCTRL_PROBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
|
||||
#define _EMU_BUCTRL_PROBE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_BUCTRL */
|
||||
#define _EMU_BUCTRL_PROBE_VDDDREG 0x00000001UL /**< Mode VDDDREG for EMU_BUCTRL */
|
||||
#define _EMU_BUCTRL_PROBE_BUIN 0x00000002UL /**< Mode BUIN for EMU_BUCTRL */
|
||||
#define _EMU_BUCTRL_PROBE_BUOUT 0x00000003UL /**< Mode BUOUT for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_PROBE_DEFAULT (_EMU_BUCTRL_PROBE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_PROBE_DISABLE (_EMU_BUCTRL_PROBE_DISABLE << 5) /**< Shifted mode DISABLE for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_PROBE_VDDDREG (_EMU_BUCTRL_PROBE_VDDDREG << 5) /**< Shifted mode VDDDREG for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_PROBE_BUIN (_EMU_BUCTRL_PROBE_BUIN << 5) /**< Shifted mode BUIN for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_PROBE_BUOUT (_EMU_BUCTRL_PROBE_BUOUT << 5) /**< Shifted mode BUOUT for EMU_BUCTRL */
|
||||
#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */
|
||||
#define _EMU_BUCTRL_MASK 0x0000006FUL /**< Mask for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable backup mode */
|
||||
#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
|
||||
#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
|
||||
#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable backup mode status export */
|
||||
#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */
|
||||
#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */
|
||||
#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_BODCAL (0x1UL << 2) /**< Enable BOD calibration mode */
|
||||
#define _EMU_BUCTRL_BODCAL_SHIFT 2 /**< Shift value for EMU_BODCAL */
|
||||
#define _EMU_BUCTRL_BODCAL_MASK 0x4UL /**< Bit mask for EMU_BODCAL */
|
||||
#define _EMU_BUCTRL_BODCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_BODCAL_DEFAULT (_EMU_BUCTRL_BODCAL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_BUMODEBODEN (0x1UL << 3) /**< Enable brown out detection on BU_VIN when in backup mode */
|
||||
#define _EMU_BUCTRL_BUMODEBODEN_SHIFT 3 /**< Shift value for EMU_BUMODEBODEN */
|
||||
#define _EMU_BUCTRL_BUMODEBODEN_MASK 0x8UL /**< Bit mask for EMU_BUMODEBODEN */
|
||||
#define _EMU_BUCTRL_BUMODEBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_BUMODEBODEN_DEFAULT (_EMU_BUCTRL_BUMODEBODEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUCTRL */
|
||||
#define _EMU_BUCTRL_PROBE_SHIFT 5 /**< Shift value for EMU_PROBE */
|
||||
#define _EMU_BUCTRL_PROBE_MASK 0x60UL /**< Bit mask for EMU_PROBE */
|
||||
#define _EMU_BUCTRL_PROBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
|
||||
#define _EMU_BUCTRL_PROBE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_BUCTRL */
|
||||
#define _EMU_BUCTRL_PROBE_VDDDREG 0x00000001UL /**< Mode VDDDREG for EMU_BUCTRL */
|
||||
#define _EMU_BUCTRL_PROBE_BUIN 0x00000002UL /**< Mode BUIN for EMU_BUCTRL */
|
||||
#define _EMU_BUCTRL_PROBE_BUOUT 0x00000003UL /**< Mode BUOUT for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_PROBE_DEFAULT (_EMU_BUCTRL_PROBE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_PROBE_DISABLE (_EMU_BUCTRL_PROBE_DISABLE << 5) /**< Shifted mode DISABLE for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_PROBE_VDDDREG (_EMU_BUCTRL_PROBE_VDDDREG << 5) /**< Shifted mode VDDDREG for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_PROBE_BUIN (_EMU_BUCTRL_PROBE_BUIN << 5) /**< Shifted mode BUIN for EMU_BUCTRL */
|
||||
#define EMU_BUCTRL_PROBE_BUOUT (_EMU_BUCTRL_PROBE_BUOUT << 5) /**< Shifted mode BUOUT for EMU_BUCTRL */
|
||||
|
||||
/* Bit fields for EMU PWRCONF */
|
||||
#define _EMU_PWRCONF_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCONF */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_etm.h
|
||||
* @brief EFM32GG_ETM register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,65 +40,65 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ETMCR; /**< Main Control Register */
|
||||
__I uint32_t ETMCCR; /**< Configuration Code Register */
|
||||
__IO uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t ETMSR; /**< ETM Status Register */
|
||||
__I uint32_t ETMSCR; /**< ETM System Configuration Register */
|
||||
uint32_t RESERVED1[2]; /**< Reserved for future use **/
|
||||
__IO uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */
|
||||
__IO uint32_t ETMTECR1; /**< ETM Trace control Register */
|
||||
uint32_t RESERVED2[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */
|
||||
uint32_t RESERVED3[68]; /**< Reserved for future use **/
|
||||
__IO uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */
|
||||
uint32_t RESERVED4[39]; /**< Reserved for future use **/
|
||||
__IO uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */
|
||||
__I uint32_t ETMIDR; /**< ID Register */
|
||||
__I uint32_t ETMCCER; /**< Configuration Code Extension Register */
|
||||
uint32_t RESERVED5[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */
|
||||
uint32_t RESERVED6[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t ETMTSEVR; /**< Timestamp Event Register */
|
||||
uint32_t RESERVED7[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */
|
||||
uint32_t RESERVED8[1]; /**< Reserved for future use **/
|
||||
__I uint32_t ETMIDR2; /**< ETM ID Register 2 */
|
||||
uint32_t RESERVED9[66]; /**< Reserved for future use **/
|
||||
__I uint32_t ETMPDSR; /**< Device Power-down Status Register */
|
||||
uint32_t RESERVED10[754]; /**< Reserved for future use **/
|
||||
__IO uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */
|
||||
uint32_t RESERVED11[1]; /**< Reserved for future use **/
|
||||
__O uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */
|
||||
uint32_t RESERVED12[1]; /**< Reserved for future use **/
|
||||
__I uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */
|
||||
uint32_t RESERVED13[1]; /**< Reserved for future use **/
|
||||
__O uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */
|
||||
uint32_t RESERVED14[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t ETMITCTRL; /**< ETM Integration Control Register */
|
||||
uint32_t RESERVED15[39]; /**< Reserved for future use **/
|
||||
__IO uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */
|
||||
__IO uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */
|
||||
uint32_t RESERVED16[2]; /**< Reserved for future use **/
|
||||
__IO uint32_t ETMLAR; /**< ETM Lock Access Register */
|
||||
__I uint32_t ETMLSR; /**< Lock Status Register */
|
||||
__I uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */
|
||||
uint32_t RESERVED17[4]; /**< Reserved for future use **/
|
||||
__I uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */
|
||||
__I uint32_t ETMPIDR4; /**< Peripheral ID4 Register */
|
||||
__O uint32_t ETMPIDR5; /**< Peripheral ID5 Register */
|
||||
__O uint32_t ETMPIDR6; /**< Peripheral ID6 Register */
|
||||
__O uint32_t ETMPIDR7; /**< Peripheral ID7 Register */
|
||||
__I uint32_t ETMPIDR0; /**< Peripheral ID0 Register */
|
||||
__I uint32_t ETMPIDR1; /**< Peripheral ID1 Register */
|
||||
__I uint32_t ETMPIDR2; /**< Peripheral ID2 Register */
|
||||
__I uint32_t ETMPIDR3; /**< Peripheral ID3 Register */
|
||||
__I uint32_t ETMCIDR0; /**< Component ID0 Register */
|
||||
__I uint32_t ETMCIDR1; /**< Component ID1 Register */
|
||||
__I uint32_t ETMCIDR2; /**< Component ID2 Register */
|
||||
__I uint32_t ETMCIDR3; /**< Component ID3 Register */
|
||||
} ETM_TypeDef; /** @} */
|
||||
__IOM uint32_t ETMCR; /**< Main Control Register */
|
||||
__IM uint32_t ETMCCR; /**< Configuration Code Register */
|
||||
__IOM uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMSR; /**< ETM Status Register */
|
||||
__IM uint32_t ETMSCR; /**< ETM System Configuration Register */
|
||||
uint32_t RESERVED1[2]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */
|
||||
__IOM uint32_t ETMTECR1; /**< ETM Trace control Register */
|
||||
uint32_t RESERVED2[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */
|
||||
uint32_t RESERVED3[68]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */
|
||||
uint32_t RESERVED4[39]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */
|
||||
__IM uint32_t ETMIDR; /**< ID Register */
|
||||
__IM uint32_t ETMCCER; /**< Configuration Code Extension Register */
|
||||
uint32_t RESERVED5[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */
|
||||
uint32_t RESERVED6[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMTSEVR; /**< Timestamp Event Register */
|
||||
uint32_t RESERVED7[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */
|
||||
uint32_t RESERVED8[1]; /**< Reserved for future use **/
|
||||
__IM uint32_t ETMIDR2; /**< ETM ID Register 2 */
|
||||
uint32_t RESERVED9[66]; /**< Reserved for future use **/
|
||||
__IM uint32_t ETMPDSR; /**< Device Power-down Status Register */
|
||||
uint32_t RESERVED10[754]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */
|
||||
uint32_t RESERVED11[1]; /**< Reserved for future use **/
|
||||
__OM uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */
|
||||
uint32_t RESERVED12[1]; /**< Reserved for future use **/
|
||||
__IM uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */
|
||||
uint32_t RESERVED13[1]; /**< Reserved for future use **/
|
||||
__OM uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */
|
||||
uint32_t RESERVED14[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMITCTRL; /**< ETM Integration Control Register */
|
||||
uint32_t RESERVED15[39]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */
|
||||
__IOM uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */
|
||||
uint32_t RESERVED16[2]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMLAR; /**< ETM Lock Access Register */
|
||||
__IM uint32_t ETMLSR; /**< Lock Status Register */
|
||||
__IM uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */
|
||||
uint32_t RESERVED17[4]; /**< Reserved for future use **/
|
||||
__IM uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */
|
||||
__IM uint32_t ETMPIDR4; /**< Peripheral ID4 Register */
|
||||
__OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */
|
||||
__OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */
|
||||
__OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */
|
||||
__IM uint32_t ETMPIDR0; /**< Peripheral ID0 Register */
|
||||
__IM uint32_t ETMPIDR1; /**< Peripheral ID1 Register */
|
||||
__IM uint32_t ETMPIDR2; /**< Peripheral ID2 Register */
|
||||
__IM uint32_t ETMPIDR3; /**< Peripheral ID3 Register */
|
||||
__IM uint32_t ETMCIDR0; /**< Component ID0 Register */
|
||||
__IM uint32_t ETMCIDR1; /**< Component ID1 Register */
|
||||
__IM uint32_t ETMCIDR2; /**< Component ID2 Register */
|
||||
__IM uint32_t ETMCIDR3; /**< Component ID3 Register */
|
||||
} ETM_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_ETM_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_gpio.h
|
||||
* @brief EFM32GG_GPIO register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -43,23 +43,23 @@ typedef struct
|
|||
GPIO_P_TypeDef P[6]; /**< Port configuration bits */
|
||||
|
||||
uint32_t RESERVED0[10]; /**< Reserved for future use **/
|
||||
__IO uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */
|
||||
__IO uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */
|
||||
__IO uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */
|
||||
__IO uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */
|
||||
__IOM uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */
|
||||
__IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */
|
||||
__IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
__IO uint32_t INSENSE; /**< Input Sense Register */
|
||||
__IO uint32_t LOCK; /**< Configuration Lock Register */
|
||||
__IO uint32_t CTRL; /**< GPIO Control Register */
|
||||
__IO uint32_t CMD; /**< GPIO Command Register */
|
||||
__IO uint32_t EM4WUEN; /**< EM4 Wake-up Enable Register */
|
||||
__IO uint32_t EM4WUPOL; /**< EM4 Wake-up Polarity Register */
|
||||
__I uint32_t EM4WUCAUSE; /**< EM4 Wake-up Cause Register */
|
||||
__IOM uint32_t ROUTE; /**< I/O Routing Register */
|
||||
__IOM uint32_t INSENSE; /**< Input Sense Register */
|
||||
__IOM uint32_t LOCK; /**< Configuration Lock Register */
|
||||
__IOM uint32_t CTRL; /**< GPIO Control Register */
|
||||
__IOM uint32_t CMD; /**< GPIO Command Register */
|
||||
__IOM uint32_t EM4WUEN; /**< EM4 Wake-up Enable Register */
|
||||
__IOM uint32_t EM4WUPOL; /**< EM4 Wake-up Polarity Register */
|
||||
__IM uint32_t EM4WUCAUSE; /**< EM4 Wake-up Cause Register */
|
||||
} GPIO_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_gpio_p.h
|
||||
* @brief EFM32GG_GPIO_P register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -38,15 +38,15 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Port Control Register */
|
||||
__IO uint32_t MODEL; /**< Port Pin Mode Low Register */
|
||||
__IO uint32_t MODEH; /**< Port Pin Mode High Register */
|
||||
__IO uint32_t DOUT; /**< Port Data Out Register */
|
||||
__O uint32_t DOUTSET; /**< Port Data Out Set Register */
|
||||
__O uint32_t DOUTCLR; /**< Port Data Out Clear Register */
|
||||
__O uint32_t DOUTTGL; /**< Port Data Out Toggle Register */
|
||||
__I uint32_t DIN; /**< Port Data In Register */
|
||||
__IO uint32_t PINLOCKN; /**< Port Unlocked Pins Register */
|
||||
__IOM uint32_t CTRL; /**< Port Control Register */
|
||||
__IOM uint32_t MODEL; /**< Port Pin Mode Low Register */
|
||||
__IOM uint32_t MODEH; /**< Port Pin Mode High Register */
|
||||
__IOM uint32_t DOUT; /**< Port Data Out Register */
|
||||
__OM uint32_t DOUTSET; /**< Port Data Out Set Register */
|
||||
__OM uint32_t DOUTCLR; /**< Port Data Out Clear Register */
|
||||
__OM uint32_t DOUTTGL; /**< Port Data Out Toggle Register */
|
||||
__IM uint32_t DIN; /**< Port Data In Register */
|
||||
__IOM uint32_t PINLOCKN; /**< Port Unlocked Pins Register */
|
||||
} GPIO_P_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_i2c.h
|
||||
* @brief EFM32GG_I2C register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,22 +40,22 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__I uint32_t STATE; /**< State Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t CLKDIV; /**< Clock Division Register */
|
||||
__IO uint32_t SADDR; /**< Slave Address Register */
|
||||
__IO uint32_t SADDRMASK; /**< Slave Address Mask Register */
|
||||
__I uint32_t RXDATA; /**< Receive Buffer Data Register */
|
||||
__I uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */
|
||||
__IO uint32_t TXDATA; /**< Transmit Buffer Data Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
} I2C_TypeDef; /** @} */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATE; /**< State Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t CLKDIV; /**< Clock Division Register */
|
||||
__IOM uint32_t SADDR; /**< Slave Address Register */
|
||||
__IOM uint32_t SADDRMASK; /**< Slave Address Mask Register */
|
||||
__IM uint32_t RXDATA; /**< Receive Buffer Data Register */
|
||||
__IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */
|
||||
__IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t ROUTE; /**< I/O Routing Register */
|
||||
} I2C_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_I2C_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_lcd.h
|
||||
* @brief EFM32GG_LCD register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,42 +40,42 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t DISPCTRL; /**< Display Control Register */
|
||||
__IO uint32_t SEGEN; /**< Segment Enable Register */
|
||||
__IO uint32_t BACTRL; /**< Blink and Animation Control Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t AREGA; /**< Animation Register A */
|
||||
__IO uint32_t AREGB; /**< Animation Register B */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t DISPCTRL; /**< Display Control Register */
|
||||
__IOM uint32_t SEGEN; /**< Segment Enable Register */
|
||||
__IOM uint32_t BACTRL; /**< Blink and Animation Control Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t AREGA; /**< Animation Register A */
|
||||
__IOM uint32_t AREGB; /**< Animation Register B */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
|
||||
uint32_t RESERVED0[5]; /**< Reserved for future use **/
|
||||
__IO uint32_t SEGD0L; /**< Segment Data Low Register 0 */
|
||||
__IO uint32_t SEGD1L; /**< Segment Data Low Register 1 */
|
||||
__IO uint32_t SEGD2L; /**< Segment Data Low Register 2 */
|
||||
__IO uint32_t SEGD3L; /**< Segment Data Low Register 3 */
|
||||
__IO uint32_t SEGD0H; /**< Segment Data High Register 0 */
|
||||
__IO uint32_t SEGD1H; /**< Segment Data High Register 1 */
|
||||
__IO uint32_t SEGD2H; /**< Segment Data High Register 2 */
|
||||
__IO uint32_t SEGD3H; /**< Segment Data High Register 3 */
|
||||
uint32_t RESERVED0[5]; /**< Reserved for future use **/
|
||||
__IOM uint32_t SEGD0L; /**< Segment Data Low Register 0 */
|
||||
__IOM uint32_t SEGD1L; /**< Segment Data Low Register 1 */
|
||||
__IOM uint32_t SEGD2L; /**< Segment Data Low Register 2 */
|
||||
__IOM uint32_t SEGD3L; /**< Segment Data Low Register 3 */
|
||||
__IOM uint32_t SEGD0H; /**< Segment Data High Register 0 */
|
||||
__IOM uint32_t SEGD1H; /**< Segment Data High Register 1 */
|
||||
__IOM uint32_t SEGD2H; /**< Segment Data High Register 2 */
|
||||
__IOM uint32_t SEGD3H; /**< Segment Data High Register 3 */
|
||||
|
||||
__IO uint32_t FREEZE; /**< Freeze Register */
|
||||
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
__IOM uint32_t FREEZE; /**< Freeze Register */
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
|
||||
uint32_t RESERVED1[19]; /**< Reserved for future use **/
|
||||
__IO uint32_t SEGD4H; /**< Segment Data High Register 4 */
|
||||
__IO uint32_t SEGD5H; /**< Segment Data High Register 5 */
|
||||
__IO uint32_t SEGD6H; /**< Segment Data High Register 6 */
|
||||
__IO uint32_t SEGD7H; /**< Segment Data High Register 7 */
|
||||
uint32_t RESERVED2[2]; /**< Reserved for future use **/
|
||||
__IO uint32_t SEGD4L; /**< Segment Data Low Register 4 */
|
||||
__IO uint32_t SEGD5L; /**< Segment Data Low Register 5 */
|
||||
__IO uint32_t SEGD6L; /**< Segment Data Low Register 6 */
|
||||
__IO uint32_t SEGD7L; /**< Segment Data Low Register 7 */
|
||||
} LCD_TypeDef; /** @} */
|
||||
uint32_t RESERVED1[19]; /**< Reserved for future use **/
|
||||
__IOM uint32_t SEGD4H; /**< Segment Data High Register 4 */
|
||||
__IOM uint32_t SEGD5H; /**< Segment Data High Register 5 */
|
||||
__IOM uint32_t SEGD6H; /**< Segment Data High Register 6 */
|
||||
__IOM uint32_t SEGD7H; /**< Segment Data High Register 7 */
|
||||
uint32_t RESERVED2[2]; /**< Reserved for future use **/
|
||||
__IOM uint32_t SEGD4L; /**< Segment Data Low Register 4 */
|
||||
__IOM uint32_t SEGD5L; /**< Segment Data Low Register 5 */
|
||||
__IOM uint32_t SEGD6L; /**< Segment Data Low Register 6 */
|
||||
__IOM uint32_t SEGD7L; /**< Segment Data Low Register 7 */
|
||||
} LCD_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_LCD_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_lesense.h
|
||||
* @brief EFM32GG_LESENSE register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,29 +40,29 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t TIMCTRL; /**< Timing Control Register */
|
||||
__IO uint32_t PERCTRL; /**< Peripheral Control Register */
|
||||
__IO uint32_t DECCTRL; /**< Decoder control Register */
|
||||
__IO uint32_t BIASCTRL; /**< Bias Control Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__IO uint32_t CHEN; /**< Channel enable Register */
|
||||
__I uint32_t SCANRES; /**< Scan result register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__I uint32_t PTR; /**< Result buffer pointers */
|
||||
__I uint32_t BUFDATA; /**< Result buffer data register */
|
||||
__I uint32_t CURCH; /**< Current channel index */
|
||||
__IO uint32_t DECSTATE; /**< Current decoder state */
|
||||
__IO uint32_t SENSORSTATE; /**< Decoder input register */
|
||||
__IO uint32_t IDLECONF; /**< GPIO Idle phase configuration */
|
||||
__IO uint32_t ALTEXCONF; /**< Alternative excite pin configuration */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
__IO uint32_t POWERDOWN; /**< LESENSE RAM power-down register */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t TIMCTRL; /**< Timing Control Register */
|
||||
__IOM uint32_t PERCTRL; /**< Peripheral Control Register */
|
||||
__IOM uint32_t DECCTRL; /**< Decoder control Register */
|
||||
__IOM uint32_t BIASCTRL; /**< Bias Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IOM uint32_t CHEN; /**< Channel enable Register */
|
||||
__IM uint32_t SCANRES; /**< Scan result register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IM uint32_t PTR; /**< Result buffer pointers */
|
||||
__IM uint32_t BUFDATA; /**< Result buffer data register */
|
||||
__IM uint32_t CURCH; /**< Current channel index */
|
||||
__IOM uint32_t DECSTATE; /**< Current decoder state */
|
||||
__IOM uint32_t SENSORSTATE; /**< Decoder input register */
|
||||
__IOM uint32_t IDLECONF; /**< GPIO Idle phase configuration */
|
||||
__IOM uint32_t ALTEXCONF; /**< Alternative excite pin configuration */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
__IOM uint32_t ROUTE; /**< I/O Routing Register */
|
||||
__IOM uint32_t POWERDOWN; /**< LESENSE RAM power-down register */
|
||||
|
||||
uint32_t RESERVED0[105]; /**< Reserved registers */
|
||||
LESENSE_ST_TypeDef ST[16]; /**< Decoding states */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_lesense_buf.h
|
||||
* @brief EFM32GG_LESENSE_BUF register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -38,7 +38,7 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t DATA; /**< Scan results */
|
||||
__IOM uint32_t DATA; /**< Scan results */
|
||||
} LESENSE_BUF_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_lesense_ch.h
|
||||
* @brief EFM32GG_LESENSE_CH register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -38,10 +38,10 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t TIMING; /**< Scan configuration */
|
||||
__IO uint32_t INTERACT; /**< Scan configuration */
|
||||
__IO uint32_t EVAL; /**< Scan configuration */
|
||||
uint32_t RESERVED0[1]; /**< Reserved future */
|
||||
__IOM uint32_t TIMING; /**< Scan configuration */
|
||||
__IOM uint32_t INTERACT; /**< Scan configuration */
|
||||
__IOM uint32_t EVAL; /**< Scan configuration */
|
||||
uint32_t RESERVED0[1]; /**< Reserved future */
|
||||
} LESENSE_CH_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_lesense_st.h
|
||||
* @brief EFM32GG_LESENSE_ST register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -38,8 +38,8 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t TCONFA; /**< State transition configuration A */
|
||||
__IO uint32_t TCONFB; /**< State transition configuration B */
|
||||
__IOM uint32_t TCONFA; /**< State transition configuration A */
|
||||
__IOM uint32_t TCONFB; /**< State transition configuration B */
|
||||
} LESENSE_ST_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_letimer.h
|
||||
* @brief EFM32GG_LETIMER register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,25 +40,25 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t CNT; /**< Counter Value Register */
|
||||
__IO uint32_t COMP0; /**< Compare Value Register 0 */
|
||||
__IO uint32_t COMP1; /**< Compare Value Register 1 */
|
||||
__IO uint32_t REP0; /**< Repeat Counter Register 0 */
|
||||
__IO uint32_t REP1; /**< Repeat Counter Register 1 */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t CNT; /**< Counter Value Register */
|
||||
__IOM uint32_t COMP0; /**< Compare Value Register 0 */
|
||||
__IOM uint32_t COMP1; /**< Compare Value Register 1 */
|
||||
__IOM uint32_t REP0; /**< Repeat Counter Register 0 */
|
||||
__IOM uint32_t REP1; /**< Repeat Counter Register 1 */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
|
||||
__IO uint32_t FREEZE; /**< Freeze Register */
|
||||
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
__IOM uint32_t FREEZE; /**< Freeze Register */
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
|
||||
uint32_t RESERVED0[2]; /**< Reserved for future use **/
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
} LETIMER_TypeDef; /** @} */
|
||||
uint32_t RESERVED0[2]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ROUTE; /**< I/O Routing Register */
|
||||
} LETIMER_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_LETIMER_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_leuart.h
|
||||
* @brief EFM32GG_LEUART register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,31 +40,31 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t CLKDIV; /**< Clock Control Register */
|
||||
__IO uint32_t STARTFRAME; /**< Start Frame Register */
|
||||
__IO uint32_t SIGFRAME; /**< Signal Frame Register */
|
||||
__I uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */
|
||||
__I uint32_t RXDATA; /**< Receive Buffer Data Register */
|
||||
__I uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */
|
||||
__IO uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */
|
||||
__IO uint32_t TXDATA; /**< Transmit Buffer Data Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IO uint32_t PULSECTRL; /**< Pulse Control Register */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t CLKDIV; /**< Clock Control Register */
|
||||
__IOM uint32_t STARTFRAME; /**< Start Frame Register */
|
||||
__IOM uint32_t SIGFRAME; /**< Signal Frame Register */
|
||||
__IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */
|
||||
__IM uint32_t RXDATA; /**< Receive Buffer Data Register */
|
||||
__IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */
|
||||
__IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */
|
||||
__IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t PULSECTRL; /**< Pulse Control Register */
|
||||
|
||||
__IO uint32_t FREEZE; /**< Freeze Register */
|
||||
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
__IOM uint32_t FREEZE; /**< Freeze Register */
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
|
||||
uint32_t RESERVED0[3]; /**< Reserved for future use **/
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
uint32_t RESERVED1[21]; /**< Reserved for future use **/
|
||||
__IO uint32_t INPUT; /**< LEUART Input Register */
|
||||
} LEUART_TypeDef; /** @} */
|
||||
uint32_t RESERVED0[3]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ROUTE; /**< I/O Routing Register */
|
||||
uint32_t RESERVED1[21]; /**< Reserved for future use **/
|
||||
__IOM uint32_t INPUT; /**< LEUART Input Register */
|
||||
} LEUART_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_LEUART_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_msc.h
|
||||
* @brief EFM32GG_MSC register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,29 +40,29 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Memory System Control Register */
|
||||
__IO uint32_t READCTRL; /**< Read Control Register */
|
||||
__IO uint32_t WRITECTRL; /**< Write Control Register */
|
||||
__IO uint32_t WRITECMD; /**< Write Command Register */
|
||||
__IO uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
|
||||
__IOM uint32_t CTRL; /**< Memory System Control Register */
|
||||
__IOM uint32_t READCTRL; /**< Read Control Register */
|
||||
__IOM uint32_t WRITECTRL; /**< Write Control Register */
|
||||
__IOM uint32_t WRITECMD; /**< Write Command Register */
|
||||
__IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
|
||||
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t WDATA; /**< Write Data Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t WDATA; /**< Write Data Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
|
||||
uint32_t RESERVED1[3]; /**< Reserved for future use **/
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IO uint32_t LOCK; /**< Configuration Lock Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__I uint32_t CACHEHITS; /**< Cache Hits Performance Counter */
|
||||
__I uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */
|
||||
uint32_t RESERVED2[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t TIMEBASE; /**< Flash Write and Erase Timebase */
|
||||
__IO uint32_t MASSLOCK; /**< Mass Erase Lock Register */
|
||||
} MSC_TypeDef; /** @} */
|
||||
uint32_t RESERVED1[3]; /**< Reserved for future use **/
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t LOCK; /**< Configuration Lock Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */
|
||||
__IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */
|
||||
uint32_t RESERVED2[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t TIMEBASE; /**< Flash Write and Erase Timebase */
|
||||
__IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */
|
||||
} MSC_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_MSC_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_pcnt.h
|
||||
* @brief EFM32GG_PCNT register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,25 +40,25 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__I uint32_t CNT; /**< Counter Value Register */
|
||||
__I uint32_t TOP; /**< Top Value Register */
|
||||
__IO uint32_t TOPB; /**< Top Value Buffer Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IM uint32_t CNT; /**< Counter Value Register */
|
||||
__IM uint32_t TOP; /**< Top Value Register */
|
||||
__IOM uint32_t TOPB; /**< Top Value Buffer Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t ROUTE; /**< I/O Routing Register */
|
||||
|
||||
__IO uint32_t FREEZE; /**< Freeze Register */
|
||||
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
__IOM uint32_t FREEZE; /**< Freeze Register */
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t AUXCNT; /**< Auxiliary Counter Value Register */
|
||||
__IO uint32_t INPUT; /**< PCNT Input Register */
|
||||
} PCNT_TypeDef; /** @} */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */
|
||||
__IOM uint32_t INPUT; /**< PCNT Input Register */
|
||||
} PCNT_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_PCNT_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_prs.h
|
||||
* @brief EFM32GG_PRS register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,9 +40,9 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t SWPULSE; /**< Software Pulse Register */
|
||||
__IO uint32_t SWLEVEL; /**< Software Level Register */
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
__IOM uint32_t SWPULSE; /**< Software Pulse Register */
|
||||
__IOM uint32_t SWLEVEL; /**< Software Level Register */
|
||||
__IOM uint32_t ROUTE; /**< I/O Routing Register */
|
||||
|
||||
uint32_t RESERVED0[1]; /**< Reserved registers */
|
||||
PRS_CH_TypeDef CH[12]; /**< Channel registers */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_prs_ch.h
|
||||
* @brief EFM32GG_PRS_CH register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -38,7 +38,7 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Channel Control Register */
|
||||
__IOM uint32_t CTRL; /**< Channel Control Register */
|
||||
} PRS_CH_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_prs_signals.h
|
||||
* @brief EFM32GG_PRS_SIGNALS register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_rmu.h
|
||||
* @brief EFM32GG_RMU register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,10 +40,10 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__I uint32_t RSTCAUSE; /**< Reset Cause Register */
|
||||
__O uint32_t CMD; /**< Command Register */
|
||||
} RMU_TypeDef; /** @} */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IM uint32_t RSTCAUSE; /**< Reset Cause Register */
|
||||
__OM uint32_t CMD; /**< Command Register */
|
||||
} RMU_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_RMU_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_romtable.h
|
||||
* @brief EFM32GG_ROMTABLE register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,16 +40,16 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__I uint32_t PID4; /**< JEP_106_BANK */
|
||||
__I uint32_t PID5; /**< Unused */
|
||||
__I uint32_t PID6; /**< Unused */
|
||||
__I uint32_t PID7; /**< Unused */
|
||||
__I uint32_t PID0; /**< Chip family LSB, chip major revision */
|
||||
__I uint32_t PID1; /**< JEP_106_NO, Chip family MSB */
|
||||
__I uint32_t PID2; /**< Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */
|
||||
__I uint32_t PID3; /**< Chip minor rev LSB */
|
||||
__I uint32_t CID0; /**< Unused */
|
||||
} ROMTABLE_TypeDef; /** @} */
|
||||
__IM uint32_t PID4; /**< JEP_106_BANK */
|
||||
__IM uint32_t PID5; /**< Unused */
|
||||
__IM uint32_t PID6; /**< Unused */
|
||||
__IM uint32_t PID7; /**< Unused */
|
||||
__IM uint32_t PID0; /**< Chip family LSB, chip major revision */
|
||||
__IM uint32_t PID1; /**< JEP_106_NO, Chip family MSB */
|
||||
__IM uint32_t PID2; /**< Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */
|
||||
__IM uint32_t PID3; /**< Chip minor rev LSB */
|
||||
__IM uint32_t CID0; /**< Unused */
|
||||
} ROMTABLE_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_ROMTABLE_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_rtc.h
|
||||
* @brief EFM32GG_RTC register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,18 +40,18 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t CNT; /**< Counter Value Register */
|
||||
__IO uint32_t COMP0; /**< Compare Value Register 0 */
|
||||
__IO uint32_t COMP1; /**< Compare Value Register 1 */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CNT; /**< Counter Value Register */
|
||||
__IOM uint32_t COMP0; /**< Compare Value Register 0 */
|
||||
__IOM uint32_t COMP1; /**< Compare Value Register 1 */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
|
||||
__IO uint32_t FREEZE; /**< Freeze Register */
|
||||
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
} RTC_TypeDef; /** @} */
|
||||
__IOM uint32_t FREEZE; /**< Freeze Register */
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
} RTC_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_RTC_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_timer.h
|
||||
* @brief EFM32GG_TIMER register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,29 +40,29 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t TOP; /**< Counter Top Value Register */
|
||||
__IO uint32_t TOPB; /**< Counter Top Value Buffer Register */
|
||||
__IO uint32_t CNT; /**< Counter Value Register */
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t TOP; /**< Counter Top Value Register */
|
||||
__IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */
|
||||
__IOM uint32_t CNT; /**< Counter Value Register */
|
||||
__IOM uint32_t ROUTE; /**< I/O Routing Register */
|
||||
|
||||
uint32_t RESERVED0[1]; /**< Reserved registers */
|
||||
TIMER_CC_TypeDef CC[3]; /**< Compare/Capture Channel */
|
||||
|
||||
uint32_t RESERVED1[4]; /**< Reserved for future use **/
|
||||
__IO uint32_t DTCTRL; /**< DTI Control Register */
|
||||
__IO uint32_t DTTIME; /**< DTI Time Control Register */
|
||||
__IO uint32_t DTFC; /**< DTI Fault Configuration Register */
|
||||
__IO uint32_t DTOGEN; /**< DTI Output Generation Enable Register */
|
||||
__I uint32_t DTFAULT; /**< DTI Fault Register */
|
||||
__O uint32_t DTFAULTC; /**< DTI Fault Clear Register */
|
||||
__IO uint32_t DTLOCK; /**< DTI Configuration Lock Register */
|
||||
__IOM uint32_t DTCTRL; /**< DTI Control Register */
|
||||
__IOM uint32_t DTTIME; /**< DTI Time Control Register */
|
||||
__IOM uint32_t DTFC; /**< DTI Fault Configuration Register */
|
||||
__IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */
|
||||
__IM uint32_t DTFAULT; /**< DTI Fault Register */
|
||||
__OM uint32_t DTFAULTC; /**< DTI Fault Clear Register */
|
||||
__IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */
|
||||
} TIMER_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_timer_cc.h
|
||||
* @brief EFM32GG_TIMER_CC register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -38,10 +38,10 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< CC Channel Control Register */
|
||||
__IO uint32_t CCV; /**< CC Channel Value Register */
|
||||
__I uint32_t CCVP; /**< CC Channel Value Peek Register */
|
||||
__IO uint32_t CCVB; /**< CC Channel Buffer Register */
|
||||
__IOM uint32_t CTRL; /**< CC Channel Control Register */
|
||||
__IOM uint32_t CCV; /**< CC Channel Value Register */
|
||||
__IM uint32_t CCVP; /**< CC Channel Value Peek Register */
|
||||
__IOM uint32_t CCVB; /**< CC Channel Buffer Register */
|
||||
} TIMER_CC_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_uart.h
|
||||
* @brief EFM32GG_UART register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_usart.h
|
||||
* @brief EFM32GG_USART register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,31 +40,31 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t FRAME; /**< USART Frame Format Register */
|
||||
__IO uint32_t TRIGCTRL; /**< USART Trigger Control register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__I uint32_t STATUS; /**< USART Status Register */
|
||||
__IO uint32_t CLKDIV; /**< Clock Control Register */
|
||||
__I uint32_t RXDATAX; /**< RX Buffer Data Extended Register */
|
||||
__I uint32_t RXDATA; /**< RX Buffer Data Register */
|
||||
__I uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */
|
||||
__I uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */
|
||||
__I uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */
|
||||
__I uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */
|
||||
__IO uint32_t TXDATAX; /**< TX Buffer Data Extended Register */
|
||||
__IO uint32_t TXDATA; /**< TX Buffer Data Register */
|
||||
__IO uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */
|
||||
__IO uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IO uint32_t IRCTRL; /**< IrDA Control Register */
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
__IO uint32_t INPUT; /**< USART Input Register */
|
||||
__IO uint32_t I2SCTRL; /**< I2S Control Register */
|
||||
} USART_TypeDef; /** @} */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t FRAME; /**< USART Frame Format Register */
|
||||
__IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATUS; /**< USART Status Register */
|
||||
__IOM uint32_t CLKDIV; /**< Clock Control Register */
|
||||
__IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */
|
||||
__IM uint32_t RXDATA; /**< RX Buffer Data Register */
|
||||
__IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */
|
||||
__IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */
|
||||
__IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */
|
||||
__IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */
|
||||
__IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */
|
||||
__IOM uint32_t TXDATA; /**< TX Buffer Data Register */
|
||||
__IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */
|
||||
__IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t IRCTRL; /**< IrDA Control Register */
|
||||
__IOM uint32_t ROUTE; /**< I/O Routing Register */
|
||||
__IOM uint32_t INPUT; /**< USART Input Register */
|
||||
__IOM uint32_t I2SCTRL; /**< I2S Control Register */
|
||||
} USART_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_USART_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_usb.h
|
||||
* @brief EFM32GG_USB register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,139 +40,139 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< System Control Register */
|
||||
__I uint32_t STATUS; /**< System Status Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
__IOM uint32_t CTRL; /**< System Control Register */
|
||||
__IM uint32_t STATUS; /**< System Status Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t ROUTE; /**< I/O Routing Register */
|
||||
|
||||
uint32_t RESERVED0[61433]; /**< Reserved for future use **/
|
||||
__IO uint32_t GOTGCTL; /**< OTG Control and Status Register */
|
||||
__IO uint32_t GOTGINT; /**< OTG Interrupt Register */
|
||||
__IO uint32_t GAHBCFG; /**< AHB Configuration Register */
|
||||
__IO uint32_t GUSBCFG; /**< USB Configuration Register */
|
||||
__IO uint32_t GRSTCTL; /**< Reset Register */
|
||||
__IO uint32_t GINTSTS; /**< Interrupt Register */
|
||||
__IO uint32_t GINTMSK; /**< Interrupt Mask Register */
|
||||
__I uint32_t GRXSTSR; /**< Receive Status Debug Read Register */
|
||||
__I uint32_t GRXSTSP; /**< Receive Status Read and Pop Register */
|
||||
__IO uint32_t GRXFSIZ; /**< Receive FIFO Size Register */
|
||||
__IO uint32_t GNPTXFSIZ; /**< Non-periodic Transmit FIFO Size Register */
|
||||
__I uint32_t GNPTXSTS; /**< Non-periodic Transmit FIFO/Queue Status Register */
|
||||
__IOM uint32_t GOTGCTL; /**< OTG Control and Status Register */
|
||||
__IOM uint32_t GOTGINT; /**< OTG Interrupt Register */
|
||||
__IOM uint32_t GAHBCFG; /**< AHB Configuration Register */
|
||||
__IOM uint32_t GUSBCFG; /**< USB Configuration Register */
|
||||
__IOM uint32_t GRSTCTL; /**< Reset Register */
|
||||
__IOM uint32_t GINTSTS; /**< Interrupt Register */
|
||||
__IOM uint32_t GINTMSK; /**< Interrupt Mask Register */
|
||||
__IM uint32_t GRXSTSR; /**< Receive Status Debug Read Register */
|
||||
__IM uint32_t GRXSTSP; /**< Receive Status Read and Pop Register */
|
||||
__IOM uint32_t GRXFSIZ; /**< Receive FIFO Size Register */
|
||||
__IOM uint32_t GNPTXFSIZ; /**< Non-periodic Transmit FIFO Size Register */
|
||||
__IM uint32_t GNPTXSTS; /**< Non-periodic Transmit FIFO/Queue Status Register */
|
||||
uint32_t RESERVED1[11]; /**< Reserved for future use **/
|
||||
__IO uint32_t GDFIFOCFG; /**< Global DFIFO Configuration Register */
|
||||
__IOM uint32_t GDFIFOCFG; /**< Global DFIFO Configuration Register */
|
||||
|
||||
uint32_t RESERVED2[40]; /**< Reserved for future use **/
|
||||
__IO uint32_t HPTXFSIZ; /**< Host Periodic Transmit FIFO Size Register */
|
||||
__IO uint32_t DIEPTXF1; /**< Device IN Endpoint Transmit FIFO 1 Size Register */
|
||||
__IO uint32_t DIEPTXF2; /**< Device IN Endpoint Transmit FIFO 2 Size Register */
|
||||
__IO uint32_t DIEPTXF3; /**< Device IN Endpoint Transmit FIFO 3 Size Register */
|
||||
__IO uint32_t DIEPTXF4; /**< Device IN Endpoint Transmit FIFO 4 Size Register */
|
||||
__IO uint32_t DIEPTXF5; /**< Device IN Endpoint Transmit FIFO 5 Size Register */
|
||||
__IO uint32_t DIEPTXF6; /**< Device IN Endpoint Transmit FIFO 6 Size Register */
|
||||
__IOM uint32_t HPTXFSIZ; /**< Host Periodic Transmit FIFO Size Register */
|
||||
__IOM uint32_t DIEPTXF1; /**< Device IN Endpoint Transmit FIFO 1 Size Register */
|
||||
__IOM uint32_t DIEPTXF2; /**< Device IN Endpoint Transmit FIFO 2 Size Register */
|
||||
__IOM uint32_t DIEPTXF3; /**< Device IN Endpoint Transmit FIFO 3 Size Register */
|
||||
__IOM uint32_t DIEPTXF4; /**< Device IN Endpoint Transmit FIFO 4 Size Register */
|
||||
__IOM uint32_t DIEPTXF5; /**< Device IN Endpoint Transmit FIFO 5 Size Register */
|
||||
__IOM uint32_t DIEPTXF6; /**< Device IN Endpoint Transmit FIFO 6 Size Register */
|
||||
|
||||
uint32_t RESERVED3[185]; /**< Reserved for future use **/
|
||||
__IO uint32_t HCFG; /**< Host Configuration Register */
|
||||
__IO uint32_t HFIR; /**< Host Frame Interval Register */
|
||||
__I uint32_t HFNUM; /**< Host Frame Number/Frame Time Remaining Register */
|
||||
__IOM uint32_t HCFG; /**< Host Configuration Register */
|
||||
__IOM uint32_t HFIR; /**< Host Frame Interval Register */
|
||||
__IM uint32_t HFNUM; /**< Host Frame Number/Frame Time Remaining Register */
|
||||
uint32_t RESERVED4[1]; /**< Reserved for future use **/
|
||||
__I uint32_t HPTXSTS; /**< Host Periodic Transmit FIFO/Queue Status Register */
|
||||
__I uint32_t HAINT; /**< Host All Channels Interrupt Register */
|
||||
__IO uint32_t HAINTMSK; /**< Host All Channels Interrupt Mask Register */
|
||||
__IM uint32_t HPTXSTS; /**< Host Periodic Transmit FIFO/Queue Status Register */
|
||||
__IM uint32_t HAINT; /**< Host All Channels Interrupt Register */
|
||||
__IOM uint32_t HAINTMSK; /**< Host All Channels Interrupt Mask Register */
|
||||
uint32_t RESERVED5[9]; /**< Reserved for future use **/
|
||||
__IO uint32_t HPRT; /**< Host Port Control and Status Register */
|
||||
__IOM uint32_t HPRT; /**< Host Port Control and Status Register */
|
||||
|
||||
uint32_t RESERVED6[47]; /**< Reserved registers */
|
||||
USB_HC_TypeDef HC[14]; /**< Host Channel Registers */
|
||||
|
||||
uint32_t RESERVED7[80]; /**< Reserved for future use **/
|
||||
__IO uint32_t DCFG; /**< Device Configuration Register */
|
||||
__IO uint32_t DCTL; /**< Device Control Register */
|
||||
__I uint32_t DSTS; /**< Device Status Register */
|
||||
__IOM uint32_t DCFG; /**< Device Configuration Register */
|
||||
__IOM uint32_t DCTL; /**< Device Control Register */
|
||||
__IM uint32_t DSTS; /**< Device Status Register */
|
||||
uint32_t RESERVED8[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t DIEPMSK; /**< Device IN Endpoint Common Interrupt Mask Register */
|
||||
__IO uint32_t DOEPMSK; /**< Device OUT Endpoint Common Interrupt Mask Register */
|
||||
__I uint32_t DAINT; /**< Device All Endpoints Interrupt Register */
|
||||
__IO uint32_t DAINTMSK; /**< Device All Endpoints Interrupt Mask Register */
|
||||
__IOM uint32_t DIEPMSK; /**< Device IN Endpoint Common Interrupt Mask Register */
|
||||
__IOM uint32_t DOEPMSK; /**< Device OUT Endpoint Common Interrupt Mask Register */
|
||||
__IM uint32_t DAINT; /**< Device All Endpoints Interrupt Register */
|
||||
__IOM uint32_t DAINTMSK; /**< Device All Endpoints Interrupt Mask Register */
|
||||
uint32_t RESERVED9[2]; /**< Reserved for future use **/
|
||||
__IO uint32_t DVBUSDIS; /**< Device VBUS Discharge Time Register */
|
||||
__IO uint32_t DVBUSPULSE; /**< Device VBUS Pulsing Time Register */
|
||||
__IOM uint32_t DVBUSDIS; /**< Device VBUS Discharge Time Register */
|
||||
__IOM uint32_t DVBUSPULSE; /**< Device VBUS Pulsing Time Register */
|
||||
|
||||
uint32_t RESERVED10[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t DIEPEMPMSK; /**< Device IN Endpoint FIFO Empty Interrupt Mask Register */
|
||||
__IOM uint32_t DIEPEMPMSK; /**< Device IN Endpoint FIFO Empty Interrupt Mask Register */
|
||||
|
||||
uint32_t RESERVED11[50]; /**< Reserved for future use **/
|
||||
__IO uint32_t DIEP0CTL; /**< Device IN Endpoint 0 Control Register */
|
||||
__IOM uint32_t DIEP0CTL; /**< Device IN Endpoint 0 Control Register */
|
||||
uint32_t RESERVED12[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t DIEP0INT; /**< Device IN Endpoint 0 Interrupt Register */
|
||||
__IOM uint32_t DIEP0INT; /**< Device IN Endpoint 0 Interrupt Register */
|
||||
uint32_t RESERVED13[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t DIEP0TSIZ; /**< Device IN Endpoint 0 Transfer Size Register */
|
||||
__IO uint32_t DIEP0DMAADDR; /**< Device IN Endpoint 0 DMA Address Register */
|
||||
__I uint32_t DIEP0TXFSTS; /**< Device IN Endpoint 0 Transmit FIFO Status Register */
|
||||
__IOM uint32_t DIEP0TSIZ; /**< Device IN Endpoint 0 Transfer Size Register */
|
||||
__IOM uint32_t DIEP0DMAADDR; /**< Device IN Endpoint 0 DMA Address Register */
|
||||
__IM uint32_t DIEP0TXFSTS; /**< Device IN Endpoint 0 Transmit FIFO Status Register */
|
||||
|
||||
uint32_t RESERVED14[1]; /**< Reserved registers */
|
||||
USB_DIEP_TypeDef DIEP[6]; /**< Device IN Endpoint x+1 Registers */
|
||||
|
||||
uint32_t RESERVED15[72]; /**< Reserved for future use **/
|
||||
__IO uint32_t DOEP0CTL; /**< Device OUT Endpoint 0 Control Register */
|
||||
__IOM uint32_t DOEP0CTL; /**< Device OUT Endpoint 0 Control Register */
|
||||
uint32_t RESERVED16[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t DOEP0INT; /**< Device OUT Endpoint 0 Interrupt Register */
|
||||
__IOM uint32_t DOEP0INT; /**< Device OUT Endpoint 0 Interrupt Register */
|
||||
uint32_t RESERVED17[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t DOEP0TSIZ; /**< Device OUT Endpoint 0 Transfer Size Register */
|
||||
__IO uint32_t DOEP0DMAADDR; /**< Device OUT Endpoint 0 DMA Address Register */
|
||||
__IOM uint32_t DOEP0TSIZ; /**< Device OUT Endpoint 0 Transfer Size Register */
|
||||
__IOM uint32_t DOEP0DMAADDR; /**< Device OUT Endpoint 0 DMA Address Register */
|
||||
|
||||
uint32_t RESERVED18[2]; /**< Reserved registers */
|
||||
USB_DOEP_TypeDef DOEP[6]; /**< Device OUT Endpoint x+1 Registers */
|
||||
|
||||
uint32_t RESERVED19[136]; /**< Reserved for future use **/
|
||||
__IO uint32_t PCGCCTL; /**< Power and Clock Gating Control Register */
|
||||
__IOM uint32_t PCGCCTL; /**< Power and Clock Gating Control Register */
|
||||
|
||||
uint32_t RESERVED20[127]; /**< Reserved registers */
|
||||
__IO uint32_t FIFO0D[512]; /**< Device EP 0/Host Channel 0 FIFO */
|
||||
__IOM uint32_t FIFO0D[512]; /**< Device EP 0/Host Channel 0 FIFO */
|
||||
|
||||
uint32_t RESERVED21[512]; /**< Reserved registers */
|
||||
__IO uint32_t FIFO1D[512]; /**< Device EP 1/Host Channel 1 FIFO */
|
||||
__IOM uint32_t FIFO1D[512]; /**< Device EP 1/Host Channel 1 FIFO */
|
||||
|
||||
uint32_t RESERVED22[512]; /**< Reserved registers */
|
||||
__IO uint32_t FIFO2D[512]; /**< Device EP 2/Host Channel 2 FIFO */
|
||||
__IOM uint32_t FIFO2D[512]; /**< Device EP 2/Host Channel 2 FIFO */
|
||||
|
||||
uint32_t RESERVED23[512]; /**< Reserved registers */
|
||||
__IO uint32_t FIFO3D[512]; /**< Device EP 3/Host Channel 3 FIFO */
|
||||
__IOM uint32_t FIFO3D[512]; /**< Device EP 3/Host Channel 3 FIFO */
|
||||
|
||||
uint32_t RESERVED24[512]; /**< Reserved registers */
|
||||
__IO uint32_t FIFO4D[512]; /**< Device EP 4/Host Channel 4 FIFO */
|
||||
__IOM uint32_t FIFO4D[512]; /**< Device EP 4/Host Channel 4 FIFO */
|
||||
|
||||
uint32_t RESERVED25[512]; /**< Reserved registers */
|
||||
__IO uint32_t FIFO5D[512]; /**< Device EP 5/Host Channel 5 FIFO */
|
||||
__IOM uint32_t FIFO5D[512]; /**< Device EP 5/Host Channel 5 FIFO */
|
||||
|
||||
uint32_t RESERVED26[512]; /**< Reserved registers */
|
||||
__IO uint32_t FIFO6D[512]; /**< Device EP 6/Host Channel 6 FIFO */
|
||||
__IOM uint32_t FIFO6D[512]; /**< Device EP 6/Host Channel 6 FIFO */
|
||||
|
||||
uint32_t RESERVED27[512]; /**< Reserved registers */
|
||||
__IO uint32_t FIFO7D[512]; /**< Host Channel 7 FIFO */
|
||||
__IOM uint32_t FIFO7D[512]; /**< Host Channel 7 FIFO */
|
||||
|
||||
uint32_t RESERVED28[512]; /**< Reserved registers */
|
||||
__IO uint32_t FIFO8D[512]; /**< Host Channel 8 FIFO */
|
||||
__IOM uint32_t FIFO8D[512]; /**< Host Channel 8 FIFO */
|
||||
|
||||
uint32_t RESERVED29[512]; /**< Reserved registers */
|
||||
__IO uint32_t FIFO9D[512]; /**< Host Channel 9 FIFO */
|
||||
__IOM uint32_t FIFO9D[512]; /**< Host Channel 9 FIFO */
|
||||
|
||||
uint32_t RESERVED30[512]; /**< Reserved registers */
|
||||
__IO uint32_t FIFO10D[512]; /**< Host Channel 10 FIFO */
|
||||
__IOM uint32_t FIFO10D[512]; /**< Host Channel 10 FIFO */
|
||||
|
||||
uint32_t RESERVED31[512]; /**< Reserved registers */
|
||||
__IO uint32_t FIFO11D[512]; /**< Host Channel 11 FIFO */
|
||||
__IOM uint32_t FIFO11D[512]; /**< Host Channel 11 FIFO */
|
||||
|
||||
uint32_t RESERVED32[512]; /**< Reserved registers */
|
||||
__IO uint32_t FIFO12D[512]; /**< Host Channel 12 FIFO */
|
||||
__IOM uint32_t FIFO12D[512]; /**< Host Channel 12 FIFO */
|
||||
|
||||
uint32_t RESERVED33[512]; /**< Reserved registers */
|
||||
__IO uint32_t FIFO13D[512]; /**< Host Channel 13 FIFO */
|
||||
__IOM uint32_t FIFO13D[512]; /**< Host Channel 13 FIFO */
|
||||
|
||||
uint32_t RESERVED34[17920]; /**< Reserved registers */
|
||||
__IO uint32_t FIFORAM[512]; /**< Direct Access to Data FIFO RAM for Debugging (2 KB) */
|
||||
__IOM uint32_t FIFORAM[512]; /**< Direct Access to Data FIFO RAM for Debugging (2 KB) */
|
||||
} USB_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -884,7 +884,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for USB GRXSTSR */
|
||||
#define _USB_GRXSTSR_RESETVALUE 0x00000000UL /**< Default value for USB_GRXSTSR */
|
||||
#define _USB_GRXSTSR_MASK 0x0F1FFFFFUL /**< Mask for USB_GRXSTSR */
|
||||
#define _USB_GRXSTSR_MASK 0x01FFFFFFUL /**< Mask for USB_GRXSTSR */
|
||||
#define _USB_GRXSTSR_CHEPNUM_SHIFT 0 /**< Shift value for USB_CHEPNUM */
|
||||
#define _USB_GRXSTSR_CHEPNUM_MASK 0xFUL /**< Bit mask for USB_CHEPNUM */
|
||||
#define _USB_GRXSTSR_CHEPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */
|
||||
|
|
@ -923,10 +923,10 @@ typedef struct
|
|||
#define USB_GRXSTSR_PKTSTS_TGLERR (_USB_GRXSTSR_PKTSTS_TGLERR << 17) /**< Shifted mode TGLERR for USB_GRXSTSR */
|
||||
#define USB_GRXSTSR_PKTSTS_SETUPRCV (_USB_GRXSTSR_PKTSTS_SETUPRCV << 17) /**< Shifted mode SETUPRCV for USB_GRXSTSR */
|
||||
#define USB_GRXSTSR_PKTSTS_CHLT (_USB_GRXSTSR_PKTSTS_CHLT << 17) /**< Shifted mode CHLT for USB_GRXSTSR */
|
||||
#define _USB_GRXSTSR_FN_SHIFT 24 /**< Shift value for USB_FN */
|
||||
#define _USB_GRXSTSR_FN_MASK 0xF000000UL /**< Bit mask for USB_FN */
|
||||
#define _USB_GRXSTSR_FN_SHIFT 21 /**< Shift value for USB_FN */
|
||||
#define _USB_GRXSTSR_FN_MASK 0x1E00000UL /**< Bit mask for USB_FN */
|
||||
#define _USB_GRXSTSR_FN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */
|
||||
#define USB_GRXSTSR_FN_DEFAULT (_USB_GRXSTSR_FN_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_GRXSTSR */
|
||||
#define USB_GRXSTSR_FN_DEFAULT (_USB_GRXSTSR_FN_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GRXSTSR */
|
||||
|
||||
/* Bit fields for USB GRXSTSP */
|
||||
#define _USB_GRXSTSP_RESETVALUE 0x00000000UL /**< Default value for USB_GRXSTSP */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_usb_diep.h
|
||||
* @brief EFM32GG_USB_DIEP register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -38,14 +38,14 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTL; /**< Device IN Endpoint x+1 Control Register */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t INT; /**< Device IN Endpoint x+1 Interrupt Register */
|
||||
uint32_t RESERVED1[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t TSIZ; /**< Device IN Endpoint x+1 Transfer Size Register */
|
||||
__IO uint32_t DMAADDR; /**< Device IN Endpoint x+1 DMA Address Register */
|
||||
__I uint32_t TXFSTS; /**< Device IN Endpoint x+1 Transmit FIFO Status Register */
|
||||
uint32_t RESERVED2[1]; /**< Reserved future */
|
||||
__IOM uint32_t CTL; /**< Device IN Endpoint x+1 Control Register */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t INT; /**< Device IN Endpoint x+1 Interrupt Register */
|
||||
uint32_t RESERVED1[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t TSIZ; /**< Device IN Endpoint x+1 Transfer Size Register */
|
||||
__IOM uint32_t DMAADDR; /**< Device IN Endpoint x+1 DMA Address Register */
|
||||
__IM uint32_t TXFSTS; /**< Device IN Endpoint x+1 Transmit FIFO Status Register */
|
||||
uint32_t RESERVED2[1]; /**< Reserved future */
|
||||
} USB_DIEP_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_usb_doep.h
|
||||
* @brief EFM32GG_USB_DOEP register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -38,13 +38,13 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTL; /**< Device OUT Endpoint x+1 Control Register */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t INT; /**< Device OUT Endpoint x+1 Interrupt Register */
|
||||
uint32_t RESERVED1[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t TSIZ; /**< Device OUT Endpoint x+1 Transfer Size Register */
|
||||
__IO uint32_t DMAADDR; /**< Device OUT Endpoint x+1 DMA Address Register */
|
||||
uint32_t RESERVED2[2]; /**< Reserved future */
|
||||
__IOM uint32_t CTL; /**< Device OUT Endpoint x+1 Control Register */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t INT; /**< Device OUT Endpoint x+1 Interrupt Register */
|
||||
uint32_t RESERVED1[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t TSIZ; /**< Device OUT Endpoint x+1 Transfer Size Register */
|
||||
__IOM uint32_t DMAADDR; /**< Device OUT Endpoint x+1 DMA Address Register */
|
||||
uint32_t RESERVED2[2]; /**< Reserved future */
|
||||
} USB_DOEP_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_usb_hc.h
|
||||
* @brief EFM32GG_USB_HC register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -38,13 +38,13 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CHAR; /**< Host Channel x Characteristics Register */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t INT; /**< Host Channel x Interrupt Register */
|
||||
__IO uint32_t INTMSK; /**< Host Channel x Interrupt Mask Register */
|
||||
__IO uint32_t TSIZ; /**< Host Channel x Transfer Size Register */
|
||||
__IO uint32_t DMAADDR; /**< Host Channel x DMA Address Register */
|
||||
uint32_t RESERVED1[2]; /**< Reserved future */
|
||||
__IOM uint32_t CHAR; /**< Host Channel x Characteristics Register */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t INT; /**< Host Channel x Interrupt Register */
|
||||
__IOM uint32_t INTMSK; /**< Host Channel x Interrupt Mask Register */
|
||||
__IOM uint32_t TSIZ; /**< Host Channel x Transfer Size Register */
|
||||
__IOM uint32_t DMAADDR; /**< Host Channel x DMA Address Register */
|
||||
uint32_t RESERVED1[2]; /**< Reserved future */
|
||||
} USB_HC_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_vcmp.h
|
||||
* @brief EFM32GG_VCMP register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,14 +40,14 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t INPUTSEL; /**< Input Selection Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
} VCMP_TypeDef; /** @} */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t INPUTSEL; /**< Input Selection Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
} VCMP_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_VCMP_BitFields
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32gg_wdog.h
|
||||
* @brief EFM32GG_WDOG register and bit field definitions
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -40,11 +40,11 @@
|
|||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
|
||||
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
} WDOG_TypeDef; /** @} */
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
} WDOG_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32GG_WDOG_BitFields
|
||||
|
|
|
|||
|
|
@ -12,10 +12,10 @@
|
|||
*
|
||||
*
|
||||
* @endverbatim
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/***************************************************************************//**
|
||||
* @file system_efm32gg.c
|
||||
* @brief CMSIS Cortex-M3 System Layer for EFM32GG devices.
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
@ -125,8 +125,6 @@ uint32_t SystemCoreClockGet(void)
|
|||
uint32_t ret;
|
||||
|
||||
ret = SystemHFClockGet();
|
||||
/* Leopard/Giant Gecko has an additional divider */
|
||||
ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT));
|
||||
ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
|
||||
_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;
|
||||
|
||||
|
|
@ -142,7 +140,7 @@ uint32_t SystemCoreClockGet(void)
|
|||
* Get the maximum core clock frequency.
|
||||
*
|
||||
* @note
|
||||
* This is an EFR32 proprietary function, not part of the CMSIS definition.
|
||||
* This is an EFM32 proprietary function, not part of the CMSIS definition.
|
||||
*
|
||||
* @return
|
||||
* The maximum core clock frequency in Hz.
|
||||
|
|
@ -235,7 +233,8 @@ uint32_t SystemHFClockGet(void)
|
|||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
return ret / (1U + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
|
||||
>> _CMU_CTRL_HFCLKDIV_SHIFT));
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
/***************************************************************************//**
|
||||
* @file system_efm32gg.h
|
||||
* @brief CMSIS Cortex-M3 System Layer for EFM32GG devices.
|
||||
* @version 4.2.0
|
||||
* @version 5.0.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
|
|
|
|||
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Reference in New Issue