From 3bfa124f80e55da065f5e2008f17d4b327bee640 Mon Sep 17 00:00:00 2001
From: "Jost, Chris" <79271064+chrJost@users.noreply.github.com>
Date: Tue, 1 Jun 2021 16:40:15 +0200
Subject: [PATCH] enable the power settings register prior to setting them

---
 targets/TARGET_STM/TARGET_STM32L5/system_clock.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/targets/TARGET_STM/TARGET_STM32L5/system_clock.c b/targets/TARGET_STM/TARGET_STM32L5/system_clock.c
index ef740466c4..49252f4f5a 100644
--- a/targets/TARGET_STM/TARGET_STM32L5/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32L5/system_clock.c
@@ -121,18 +121,18 @@ uint8_t SetSysClock_PLL_MSI(void)
 {
     RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
     RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-
-    /* Configure the main internal regulator output voltage */
-    if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE0) != HAL_OK) {
-        return 0; // FAIL
-    }
-
+    
     /* Configure LSE Drive Capability */
     __HAL_RCC_PWR_CLK_ENABLE();
     __HAL_RCC_SYSCFG_CLK_ENABLE();
     HAL_PWR_EnableBkUpAccess();
     __HAL_RCC_RTCAPB_CLK_ENABLE();
 
+    /* Configure the main internal regulator output voltage */
+    if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE0) != HAL_OK) {
+        return 0; // FAIL
+    }
+
 #if MBED_CONF_TARGET_LSE_AVAILABLE
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
     RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE;