From 3b6020c1bea99feaf68db65349841b399c319c11 Mon Sep 17 00:00:00 2001 From: Sree Harsha Angara Date: Mon, 6 Apr 2020 17:12:23 -0700 Subject: [PATCH] Updating BSP files for CYESKIT_064B0S2_4343W --- .../GeneratedSource/cycfg.c | 4 +- .../GeneratedSource/cycfg.h | 4 +- .../GeneratedSource/cycfg.timestamp | 4 +- .../GeneratedSource/cycfg_clocks.c | 10 +-- .../GeneratedSource/cycfg_clocks.h | 6 +- .../GeneratedSource/cycfg_notices.h | 4 +- .../GeneratedSource/cycfg_peripherals.c | 6 +- .../GeneratedSource/cycfg_peripherals.h | 24 +++--- .../GeneratedSource/cycfg_pins.c | 16 ++-- .../GeneratedSource/cycfg_pins.h | 34 ++++---- .../GeneratedSource/cycfg_routing.c | 4 +- .../GeneratedSource/cycfg_routing.h | 4 +- .../GeneratedSource/cycfg_system.c | 82 +++++++------------ .../GeneratedSource/cycfg_system.h | 15 +--- .../cyreservedresources.list | 2 +- .../design.cycapsense | 17 ++-- .../COMPONENT_BSP_DESIGN_MODUS/design.cyqspi | 6 +- .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 71 ++++------------ .../cybsp_types.h | 50 ++++++----- 19 files changed, 142 insertions(+), 221 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index ed8102601f..6fdc767d40 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,8 +4,8 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 55f9bd74fa..8c8d72f88d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,8 +4,8 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp index 46ae60d212..36387c70ae 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,8 +4,8 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 45223d1950..2797add790 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -4,8 +4,8 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -38,9 +38,9 @@ void init_cycfg_clocks(void) { - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U); + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U); #if defined (CY_USING_HAL) cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); #endif //defined (CY_USING_HAL) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index 9512e17264..28b058deac 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -4,8 +4,8 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -39,7 +39,7 @@ extern "C" { #define CYBSP_CSD_CLK_DIV_ENABLED 1U #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_CSD_CLK_DIV_NUM 3U +#define CYBSP_CSD_CLK_DIV_NUM 0U #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 682af2fcd3..c709c9e26c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,8 +5,8 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index 181ef57d60..7975fdc966 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,8 +4,8 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -34,5 +34,5 @@ cy_stc_csd_context_t cy_csd_0_context = void init_cycfg_peripherals(void) { - Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U); + Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 8d437beab5..bdaf8901b6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,8 +4,8 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -38,17 +38,17 @@ extern "C" { #define CYBSP_CSD_ENABLED 1U #define CY_CAPSENSE_CORE 4u #define CY_CAPSENSE_CPU_CLK 100000000u -#define CY_CAPSENSE_PERI_CLK 100000000u +#define CY_CAPSENSE_PERI_CLK 50000000u #define CY_CAPSENSE_VDDA_MV 3300u #define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT -#define CY_CAPSENSE_PERI_DIV_INDEX 3u +#define CY_CAPSENSE_PERI_DIV_INDEX 0u #define Cmod_PORT GPIO_PRT7 #define CintA_PORT GPIO_PRT7 #define CintB_PORT GPIO_PRT7 -#define Button0_Rx0_PORT GPIO_PRT8 -#define Button0_Tx_PORT GPIO_PRT1 -#define Button1_Rx0_PORT GPIO_PRT8 -#define Button1_Tx_PORT GPIO_PRT1 +#define Button0_Rx0_PORT GPIO_PRT1 +#define Button0_Tx_PORT GPIO_PRT8 +#define Button1_Rx0_PORT GPIO_PRT1 +#define Button1_Tx_PORT GPIO_PRT8 #define LinearSlider0_Sns0_PORT GPIO_PRT8 #define LinearSlider0_Sns1_PORT GPIO_PRT8 #define LinearSlider0_Sns2_PORT GPIO_PRT8 @@ -57,10 +57,10 @@ extern "C" { #define Cmod_PIN 7u #define CintA_PIN 1u #define CintB_PIN 2u -#define Button0_Rx0_PIN 1u -#define Button0_Tx_PIN 0u -#define Button1_Rx0_PIN 2u -#define Button1_Tx_PIN 0u +#define Button0_Rx0_PIN 0u +#define Button0_Tx_PIN 1u +#define Button1_Rx0_PIN 0u +#define Button1_Tx_PIN 2u #define LinearSlider0_Sns0_PIN 3u #define LinearSlider0_Sns1_PIN 4u #define LinearSlider0_Sns2_PIN 5u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 9d396e04a2..0880c2f532 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,8 +4,8 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -74,11 +74,11 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_CSD_TX_HSIOM, + .hsiom = CYBSP_CSD_RX_HSIOM, .intEdge = CY_GPIO_INTR_DISABLE, .intMask = 0UL, .vtrip = CY_GPIO_VTRIP_CMOS, @@ -91,11 +91,11 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_TX_obj = + const cyhal_resource_inst_t CYBSP_CSD_RX_obj = { .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_CSD_TX_PORT_NUM, - .channel_num = CYBSP_CSD_TX_PIN, + .block_num = CYBSP_CSD_RX_PORT_NUM, + .channel_num = CYBSP_CSD_RX_PIN, }; #endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_SWO_config = @@ -425,7 +425,7 @@ void init_cycfg_pins(void) #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index 249d1ffc72..a49ede0f6a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,8 +4,8 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -86,29 +86,29 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_CSD_TX_ENABLED 1U -#define CYBSP_CSD_TX_PORT GPIO_PRT1 -#define CYBSP_CSD_TX_PORT_NUM 1U -#define CYBSP_CSD_TX_PIN 0U -#define CYBSP_CSD_TX_NUM 0U -#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_CSD_TX_INIT_DRIVESTATE 1 +#define CYBSP_CSD_RX_ENABLED 1U +#define CYBSP_CSD_RX_PORT GPIO_PRT1 +#define CYBSP_CSD_RX_PORT_NUM 1U +#define CYBSP_CSD_RX_PIN 0U +#define CYBSP_CSD_RX_NUM 0U +#define CYBSP_CSD_RX_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CSD_RX_INIT_DRIVESTATE 1 #ifndef ioss_0_port_1_pin_0_HSIOM #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO #endif -#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM -#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn +#define CYBSP_CSD_RX_HSIOM ioss_0_port_1_pin_0_HSIOM +#define CYBSP_CSD_RX_IRQ ioss_interrupts_gpio_1_IRQn #if defined (CY_USING_HAL) - #define CYBSP_CSD_TX_HAL_PORT_PIN P1_0 + #define CYBSP_CSD_RX_HAL_PORT_PIN P1_0 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CSD_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CSD_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) #define CYBSP_SWO_ENABLED 1U #define CYBSP_SWO_PORT GPIO_PRT6 @@ -431,9 +431,9 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config; +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config; #if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj; + extern const cyhal_resource_inst_t CYBSP_CSD_RX_obj; #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; #if defined (CY_USING_HAL) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index 56e95d20c8..d44e67ee30 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,8 +4,8 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index b26ae3cc61..87481e9a9b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,8 +4,8 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 1e8c349ee2..5c00e4be34 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,8 +4,8 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -38,15 +38,12 @@ #define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 #define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL #define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 -#define CY_CFG_SYSCLK_CLKHF1_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 48UL -#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1 #define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 #define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL #define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 #define CY_CFG_SYSCLK_CLKHF3_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL -#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1 +#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 #define CY_CFG_SYSCLK_CLKHF4_ENABLED 1 #define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL #define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 @@ -59,12 +56,9 @@ #define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO #define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO #define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 #define CY_CFG_SYSCLK_PLL0_ENABLED 1 +#define CY_CFG_SYSCLK_PLL1_ENABLED 1 #define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 #define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1 #define CY_CFG_SYSCLK_WCO_ENABLED 1 @@ -112,23 +106,15 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .channel_num = 0U, }; #endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 3U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 4U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = +{ + .feedbackDiv = 36, + .referenceDiv = 1, + .outputDiv = 2, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, +}; +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig = { .feedbackDiv = 30, .referenceDiv = 1, @@ -148,7 +134,7 @@ __STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit() } __STATIC_INLINE void Cy_SysClk_ClkBakInit() { - Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF); } __STATIC_INLINE void Cy_SysClk_ClkFastInit() { @@ -170,12 +156,6 @@ __STATIC_INLINE void Cy_SysClk_ClkHf0Init() Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); } -__STATIC_INLINE void Cy_SysClk_ClkHf1Init() -{ - Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH); - Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE); - Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1); -} __STATIC_INLINE void Cy_SysClk_ClkHf2Init() { Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH); @@ -217,17 +197,9 @@ __STATIC_INLINE void Cy_SysClk_ClkPath2Init() { Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); } -__STATIC_INLINE void Cy_SysClk_ClkPath3Init() -{ - Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath4Init() -{ - Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); -} __STATIC_INLINE void Cy_SysClk_ClkPeriInit() { - Cy_SysClk_ClkPeriSetDivider(0U); + Cy_SysClk_ClkPeriSetDivider(1U); } __STATIC_INLINE void Cy_SysClk_Pll0Init() { @@ -240,6 +212,17 @@ __STATIC_INLINE void Cy_SysClk_Pll0Init() cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); } } +__STATIC_INLINE void Cy_SysClk_Pll1Init() +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } +} __STATIC_INLINE void Cy_SysClk_ClkSlowInit() { Cy_SysClk_ClkSlowSetDivider(0U); @@ -264,14 +247,14 @@ __STATIC_INLINE void init_cycfg_power(void) { /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + #ifdef CY_CFG_SYSCLK_ILO_ENABLED if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) { Cy_SysLib_ResetBackupDomain(); Cy_SysClk_IloDisable(); Cy_SysClk_IloInit(); } - #else /* Dedicated Supply */ - Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP); + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ /* Configure core regulator */ @@ -553,6 +536,7 @@ void init_cycfg_system(void) Cy_SysClk_IloInit(); #else Cy_SysClk_IloDisable(); + Cy_SysClk_IloHibernateOn(false); #endif #ifndef CY_CFG_SYSCLK_IMO_ENABLED @@ -586,12 +570,4 @@ void init_cycfg_system(void) #if defined (CY_USING_HAL) cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); #endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); -#endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index 0535600be0..645a990b84 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,8 +4,8 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.4.1.2240 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -48,8 +48,6 @@ extern "C" { #define srss_0_clock_0_fll_0_ENABLED 1U #define srss_0_clock_0_hfclk_0_ENABLED 1U #define CY_CFG_SYSCLK_CLKHF0 0UL -#define srss_0_clock_0_hfclk_1_ENABLED 1U -#define CY_CFG_SYSCLK_CLKHF1 1UL #define srss_0_clock_0_hfclk_2_ENABLED 1U #define CY_CFG_SYSCLK_CLKHF2 2UL #define srss_0_clock_0_hfclk_3_ENABLED 1U @@ -63,10 +61,9 @@ extern "C" { #define srss_0_clock_0_pathmux_0_ENABLED 1U #define srss_0_clock_0_pathmux_1_ENABLED 1U #define srss_0_clock_0_pathmux_2_ENABLED 1U -#define srss_0_clock_0_pathmux_3_ENABLED 1U -#define srss_0_clock_0_pathmux_4_ENABLED 1U #define srss_0_clock_0_periclk_0_ENABLED 1U #define srss_0_clock_0_pll_0_ENABLED 1U +#define srss_0_clock_0_pll_1_ENABLED 1U #define srss_0_clock_0_slowclk_0_ENABLED 1U #define srss_0_clock_0_timerclk_0_ENABLED 1U #define srss_0_clock_0_wco_0_ENABLED 1U @@ -96,12 +93,6 @@ extern "C" { #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj; #endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj; -#endif //defined (CY_USING_HAL) void init_cycfg_system(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list index 42a9e417f6..8453a4470f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list @@ -1,4 +1,4 @@ -[Device=CYB0644ABZI-D44] +[Device=CY8C624ABZI-D44] [Blocks] # WIFI diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense index 13cf564a5a..978ea026ca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense @@ -1,13 +1,6 @@ - - + + @@ -121,12 +114,12 @@ + - @@ -223,12 +216,12 @@ + - @@ -325,12 +318,12 @@ + - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi index 3c5fbe94fb..6df618b3a8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -29,7 +29,7 @@ false SPI_MOSI_MISO_DATA_0_1 default_memory.xml - true + false 2 @@ -43,7 +43,7 @@ false SPI_MOSI_MISO_DATA_0_1 default_memory.xml - true + false 3 @@ -57,7 +57,7 @@ false SPI_MOSI_MISO_DATA_0_1 default_memory.xml - true + false diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus index 474024e377..49125e48bd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -75,16 +75,8 @@ - - - - - - - - - + @@ -96,16 +88,6 @@ - - - - - - - - - - @@ -275,20 +257,14 @@ - - - - + - + - - - @@ -299,7 +275,7 @@ - + @@ -319,12 +295,6 @@ - - - - - - @@ -333,7 +303,7 @@ - + @@ -373,22 +343,20 @@ - - - - - - - - - - - + + + + + + + + + @@ -417,7 +385,6 @@ - @@ -435,8 +402,6 @@ - - @@ -453,7 +418,7 @@ - + @@ -473,6 +438,9 @@ + + + @@ -482,9 +450,6 @@ - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/cybsp_types.h index 5e70332211..2db254acac 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/cybsp_types.h @@ -92,13 +92,13 @@ extern "C" { /** LED 8; User LED1 */ #define CYBSP_LED8 (P1_5) /** LED 9; User LED2 */ -#define CYBSP_LED9 (P13_7) +#define CYBSP_LED9 (P11_1) /** LED 5: RGB LED - Red; User LED3 */ -#define CYBSP_LED_RGB_RED (P0_3) +#define CYBSP_LED_RGB_RED (P1_1) /** LED 5: RGB LED - Green; User LED4 */ -#define CYBSP_LED_RGB_GREEN (P1_1) +#define CYBSP_LED_RGB_GREEN (P0_5) /** LED 5: RGB LED - Blue; User LED5 */ -#define CYBSP_LED_RGB_BLUE (P11_1) +#define CYBSP_LED_RGB_BLUE (P7_3) /** LED 8; User LED1 */ #define CYBSP_USER_LED1 (CYBSP_LED8) @@ -152,7 +152,7 @@ extern "C" { /** Pin: WIFI ON */ #define CYBSP_WIFI_WL_REG_ON (P2_6) /** Pin: WIFI Host Wakeup */ -#define CYBSP_WIFI_HOST_WAKE (P2_7) +#define CYBSP_WIFI_HOST_WAKE (P4_1) /** Pin: BT UART RX */ #define CYBSP_BT_UART_RX (P3_0) @@ -166,14 +166,18 @@ extern "C" { /** Pin: BT Power */ #define CYBSP_BT_POWER (P3_4) /** Pin: BT Host Wakeup */ -#define CYBSP_BT_HOST_WAKE (P3_5) +#define CYBSP_BT_HOST_WAKE (P4_0) /** Pin: BT Device Wakeup */ -#define CYBSP_BT_DEVICE_WAKE (P4_0) +#define CYBSP_BT_DEVICE_WAKE (P3_5) /** Pin: UART RX */ #define CYBSP_DEBUG_UART_RX (P5_0) /** Pin: UART TX */ #define CYBSP_DEBUG_UART_TX (P5_1) +/** Pin: UART RX */ +#define CYBSP_DEBUG_UART_RTS (P5_2) +/** Pin: UART TX */ +#define CYBSP_DEBUG_UART_CTS (P5_3) /** Pin: I2C SCL */ #define CYBSP_I2C_SCL (P6_0) @@ -223,17 +227,17 @@ extern "C" { */ /** Arduino A0 */ -#define CYBSP_A0 P10_0 +#define CYBSP_A0 (P10_0) /** Arduino A1 */ -#define CYBSP_A1 P10_1 +#define CYBSP_A1 (P10_1) /** Arduino A2 */ -#define CYBSP_A2 P10_2 +#define CYBSP_A2 (P10_2) /** Arduino A3 */ -#define CYBSP_A3 P10_3 +#define CYBSP_A3 (P10_3) /** Arduino A4 */ -#define CYBSP_A4 P10_4 +#define CYBSP_A4 (P10_4) /** Arduino A5 */ -#define CYBSP_A5 P10_5 +#define CYBSP_A5 (P10_5) /** Arduino D0 */ #define CYBSP_D0 (P5_0) /** Arduino D1 */ @@ -249,11 +253,11 @@ extern "C" { /** Arduino D6 */ #define CYBSP_D6 (P5_6) /** Arduino D7 */ -#define CYBSP_D7 (P0_2) +#define CYBSP_D7 (P5_7) /** Arduino D8 */ -#define CYBSP_D8 (P13_0) +#define CYBSP_D8 (P7_5) /** Arduino D9 */ -#define CYBSP_D9 (P13_1) +#define CYBSP_D9 (P7_6) /** Arduino D10 */ #define CYBSP_D10 (P12_3) /** Arduino D11 */ @@ -302,19 +306,11 @@ extern "C" { /** Cypress J2 Header pin 13 */ #define CYBSP_J2_13 (P10_6) /** Cypress J2 Header pin 14 */ -#define CYBSP_J2_14 (NC) +#define CYBSP_J2_14 (P9_6) /** Cypress J2 Header pin 15 */ -#define CYBSP_J2_15 (P6_2) +#define CYBSP_J2_15 (P10_7) /** Cypress J2 Header pin 16 */ -#define CYBSP_J2_16 (P9_6) -/** Cypress J2 Header pin 17 */ -#define CYBSP_J2_17 (P6_3) -/** Cypress J2 Header pin 18 */ -#define CYBSP_J2_18 (P9_7) -/** Cypress J2 Header pin 19 */ -#define CYBSP_J2_19 (P13_6) -/** Cypress J2 Header pin 20 */ -#define CYBSP_J2_20 (P13_7) +#define CYBSP_J2_16 (P9_7) /** \} group_bsp_pins_j2 */