mirror of https://github.com/ARMmbed/mbed-os.git
Adapt K64F lp ticker driver to the new standards.
Low power ticker time counter is created based on RTC which is driven by 32KHz clock. Additional low power timer is used to generate interrupts. We need to adapt driver to operate on ticks instead of us. Perform the following updates: - provide lp ticker configuration: 32KHz/32 bit counter. - lp_ticker_init() routine disables lp ticker interrupts . - adapt the driver functions to operate on ticks instead us. - adapt comments. - add us_ticker_free() routine.pull/7009/head
Przemyslaw Stekiel
Bartek Szatkowski
parent
c4bd9d125b
commit
39852f772c
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@ -1,5 +1,5 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2016 ARM Limited
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* Copyright (c) 2016 - 2018 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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@ -22,20 +22,33 @@
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#include "cmsis.h"
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#include "rtc_api.h"
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#define MAX_SEC_BITS (12)
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#define MAX_SEC_MASK ((1 << MAX_SEC_BITS) - 1)
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#define SEC_IN_USEC (1000000)
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const ticker_info_t* lp_ticker_get_info()
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{
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static const ticker_info_t info = {
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32768, // 32kHz
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32 // 32 bit counter
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};
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return &info;
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}
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#define SEC_BITS (17)
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#define SEC_SHIFT (15)
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#define SEC_MASK ((1 << SEC_BITS) - 1)
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#define TICKS_BITS (15)
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#define TICKS_SHIFT (0)
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#define TICKS_MASK ((1 << TICKS_BITS) - 1)
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#define OSC32K_CLK_HZ (32768)
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#define MAX_LPTMR_SLEEP ((1 << 16) - 1)
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static bool lp_ticker_inited = false;
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static int lptmr_schedule = 0;
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static timestamp_t lptmr_schedule = 0;
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static void rtc_isr(void)
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{
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uint32_t sr = RTC->SR;
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if (sr & RTC_SR_TOF_MASK) {
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// Reset RTC to 0 so it keeps counting
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/* Reset RTC to 0 so it keeps counting. */
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RTC_StopTimer(RTC);
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RTC->TSR = 0;
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RTC_StartTimer(RTC);
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@ -43,14 +56,23 @@ static void rtc_isr(void)
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RTC_DisableInterrupts(RTC, kRTC_AlarmInterruptEnable);
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RTC->TAR = 0; /* Write clears the IRQ flag */
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/* Wait subsecond remainder if any */
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if (lptmr_schedule) {
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LPTMR_SetTimerPeriod(LPTMR0, lptmr_schedule);
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/* Wait subsecond remainder. */
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const uint32_t now_ticks = lp_ticker_read();
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uint32_t delta_ticks =
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lptmr_schedule >= now_ticks ? lptmr_schedule - now_ticks : (uint32_t)((uint64_t) lptmr_schedule + 0xFFFFFFFF - now_ticks);
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lptmr_schedule = 0;
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if (delta_ticks == 0) {
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lp_ticker_irq_handler();
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} else {
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LPTMR_StopTimer(LPTMR0);
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LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag);
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LPTMR_SetTimerPeriod(LPTMR0, delta_ticks);
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LPTMR_EnableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable);
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LPTMR_StartTimer(LPTMR0);
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} else {
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lp_ticker_irq_handler();
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}
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} else if (sr & RTC_SR_TIF_MASK) {
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RTC_DisableInterrupts(RTC, kRTC_TimeOverflowInterruptEnable);
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}
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@ -71,102 +93,124 @@ void lp_ticker_init(void)
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{
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lptmr_config_t lptmrConfig;
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if (lp_ticker_inited) {
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return;
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}
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lp_ticker_inited = true;
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if (!lp_ticker_inited) {
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/* Setup low resolution clock - RTC */
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if (!rtc_isenabled()) {
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rtc_init();
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/* Setup low resolution clock - RTC */
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if (!rtc_isenabled()) {
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rtc_init();
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RTC_StartTimer(RTC);
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}
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RTC->TAR = 0; /* Write clears the IRQ flag */
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NVIC_ClearPendingIRQ(RTC_IRQn);
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RTC_DisableInterrupts(RTC, kRTC_AlarmInterruptEnable | kRTC_SecondsInterruptEnable);
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RTC_StartTimer(RTC);
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NVIC_SetVector(RTC_IRQn, (uint32_t) rtc_isr);
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NVIC_EnableIRQ(RTC_IRQn);
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/* Setup high resolution clock - LPTMR */
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LPTMR_GetDefaultConfig(&lptmrConfig);
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/* Use 32kHz drive */
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CLOCK_SetXtal32Freq(OSC32K_CLK_HZ);
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lptmrConfig.prescalerClockSource = kLPTMR_PrescalerClock_2;
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LPTMR_Init(LPTMR0, &lptmrConfig);
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LPTMR_DisableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable);
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NVIC_ClearPendingIRQ(LPTMR0_IRQn);
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NVIC_SetVector(LPTMR0_IRQn, (uint32_t) lptmr_isr);
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EnableIRQ(LPTMR0_IRQn);
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lptmr_schedule = 0;
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lp_ticker_inited = true;
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} else {
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/* In case of re-init we need to disable lp ticker interrupt. */
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LPTMR_StopTimer(LPTMR0);
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RTC_DisableInterrupts(RTC, kRTC_AlarmInterruptEnable);
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RTC->TAR = 0; /* Write clears the IRQ flag */
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lptmr_schedule = 0;
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}
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RTC->TAR = 0; /* Write clears the IRQ flag */
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NVIC_ClearPendingIRQ(RTC_IRQn);
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NVIC_SetVector(RTC_IRQn, (uint32_t)rtc_isr);
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NVIC_EnableIRQ(RTC_IRQn);
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/* Setup high resolution clock - LPTMR */
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LPTMR_GetDefaultConfig(&lptmrConfig);
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/* Use 32kHz drive */
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CLOCK_SetXtal32Freq(OSC32K_CLK_HZ);
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lptmrConfig.prescalerClockSource = kLPTMR_PrescalerClock_2;
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LPTMR_Init(LPTMR0, &lptmrConfig);
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LPTMR_EnableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable);
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NVIC_ClearPendingIRQ(LPTMR0_IRQn);
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NVIC_SetVector(LPTMR0_IRQn, (uint32_t)lptmr_isr);
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EnableIRQ(LPTMR0_IRQn);
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}
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/** Read the current counter
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*
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* @return The current timer's counter value in microseconds
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* @return The current timer's counter value in ticks
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*/
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uint32_t lp_ticker_read(void)
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{
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uint32_t sec, pre;
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uint32_t count;
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uint32_t last_count;
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if (!lp_ticker_inited) {
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lp_ticker_init();
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}
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/* TPR is increments every 32.768 kHz clock cycle. The TSR increments when
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* bit 14 of the TPR transitions from a logic one (32768 ticks - 1 sec).
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* After that TPR starts counting from 0.
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*
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* count value is built as follows:
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* count[0 - 14] - ticks (RTC->TPR)
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* count[15 - 31] - seconds (RTC->TSR)
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*/
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sec = RTC->TSR; /* 32b: Seconds */
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pre = RTC->TPR; /* 16b: Increments every 32.768kHz clock cycle (30us) */
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/* Loop until the same tick is read twice since this
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* is ripple counter on a different clock domain.
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*/
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count = ((RTC->TSR << SEC_SHIFT) | (RTC->TPR & TICKS_MASK));
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do {
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last_count = count;
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count = ((RTC->TSR << SEC_SHIFT) | (RTC->TPR & TICKS_MASK));
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} while (last_count != count);
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/* Final value: 11b (4095) for sec and 21b for usec (pre can reach 1,000,000us which is close to 1<<20) */
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uint32_t ret = (((sec & MAX_SEC_MASK) * SEC_IN_USEC) + (((uint64_t)pre * SEC_IN_USEC) / OSC32K_CLK_HZ));
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return ret;
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return count;
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}
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/** Set interrupt for specified timestamp
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*
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* @param timestamp The time in microseconds to be set
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* @param timestamp The time in ticks to be set
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*/
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void lp_ticker_set_interrupt(timestamp_t timestamp)
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{
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uint32_t now_us, delta_us, delta_ticks;
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if (!lp_ticker_inited) {
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lp_ticker_init();
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}
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lptmr_schedule = 0;
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now_us = lp_ticker_read();
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delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us);
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/* Checking if LPTRM can handle this sleep */
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delta_ticks = USEC_TO_COUNT(delta_us, CLOCK_GetFreq(kCLOCK_Er32kClk));
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/* We get here absolute interrupt time-stamp in ticks which takes into account counter overflow.
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* Since we use additional count-down timer to generate interrupt we need to calculate
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* load value based on time-stamp.
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*/
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const uint32_t now_ticks = lp_ticker_read();
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uint32_t delta_ticks =
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timestamp >= now_ticks ? timestamp - now_ticks : (uint32_t)((uint64_t) timestamp + 0xFFFFFFFF - now_ticks);
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if (delta_ticks == 0) {
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/* The requested delay is less than the minimum resolution of this counter */
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/* The requested delay is less than the minimum resolution of this counter. */
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delta_ticks = 1;
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}
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if (delta_ticks > MAX_LPTMR_SLEEP) {
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/* Using RTC if wait time is over 16b (2s @32kHz) */
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uint32_t delta_sec;
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/* Using RTC if wait time is over 16b (2s @32kHz). */
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uint32_t delay_sec = delta_ticks >> 15;
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delta_us += COUNT_TO_USEC(RTC->TPR, CLOCK_GetFreq(kCLOCK_Er32kClk)); /* Accounting for started second */
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delta_sec = delta_us / SEC_IN_USEC;
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delta_us -= delta_sec * SEC_IN_USEC;
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RTC->TAR = RTC->TSR + delta_sec - 1;
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RTC->TAR = RTC->TSR + delay_sec - 1;
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RTC_EnableInterrupts(RTC, kRTC_AlarmInterruptEnable);
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/* Set aditional, subsecond, sleep time */
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if (delta_us) {
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lptmr_schedule = USEC_TO_COUNT(delta_us, CLOCK_GetFreq(kCLOCK_Er32kClk));
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if (lptmr_schedule == 0) {
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/* The requested delay is less than the minimum resolution of this counter */
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lptmr_schedule = 1;
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}
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}
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/* Store absolute interrupt time-stamp value for further processing in
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* RTC interrupt handler (schedule remaining ticks using LPTMR). */
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lptmr_schedule = timestamp;
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} else {
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/* Below RTC resolution using LPTMR */
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/* Below RTC resolution using LPTMR. */
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/* In case of re-schedule we need to disable RTC interrupt. */
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RTC_DisableInterrupts(RTC, kRTC_AlarmInterruptEnable);
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RTC->TAR = 0; /* Write clears the IRQ flag */
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/* When the LPTMR is enabled, the CMR can be altered only when CSR[TCF] is set. When
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* updating the CMR, the CMR must be written and CSR[TCF] must be cleared before the
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* LPTMR counter has incremented past the new LPTMR compare value.
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*
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* When TEN is clear, it resets the LPTMR internal logic, including the CNR and TCF.
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* When TEN is set, the LPTMR is enabled. While writing 1 to this field, CSR[5:1] must
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* not be altered.
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*/
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LPTMR_StopTimer(LPTMR0);
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LPTMR_SetTimerPeriod(LPTMR0, delta_ticks);
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LPTMR_EnableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable);
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LPTMR_StartTimer(LPTMR0);
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@ -194,6 +238,7 @@ void lp_ticker_clear_interrupt(void)
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{
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RTC->TAR = 0; /* Write clears the IRQ flag */
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LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag);
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lptmr_schedule = 0;
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}
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#endif /* DEVICE_LOWPOWERTIMER */
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