mirror of https://github.com/ARMmbed/mbed-os.git
KSDK: Updated version for the flexcan driver
- Add FlexCAN function pointer handler logic to save code size. - CAN driver enter/exit Freeze mode issue Signed-off-by: Mahadevan Mahesh <Mahesh.Mahadevan@nxp.com>pull/2514/head
Mahadevan Mahesh
parent
8e8ccee98e
commit
38aeb4cdce
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@ -73,6 +73,9 @@ enum _flexcan_mb_code_tx
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kFLEXCAN_TxMbNotUsed = 0xF, /*!< Not used.*/
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};
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/* Typedef for interrupt handler. */
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typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle);
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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@ -86,23 +89,24 @@ enum _flexcan_mb_code_tx
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uint32_t FLEXCAN_GetInstance(CAN_Type *base);
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/*!
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* @brief Enter FlexCAN Fraze Mode.
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* @brief Enter FlexCAN Freeze Mode.
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*
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* This function makes the FlexCAN work under Fraze Mode.
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* This function makes the FlexCAN work under Freeze Mode.
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*
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* @param base FlexCAN peripheral base address.
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*/
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static void FLEXCAN_EnterFrazeMode(CAN_Type *base);
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static void FLEXCAN_EnterFreezeMode(CAN_Type *base);
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/*!
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* @brief Exit FlexCAN Fraze Mode.
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* @brief Exit FlexCAN Freeze Mode.
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*
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* This function makes the FlexCAN leave Fraze Mode.
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* This function makes the FlexCAN leave Freeze Mode.
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*
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* @param base FlexCAN peripheral base address.
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*/
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static void FLEXCAN_ExitFrazeMode(CAN_Type *base);
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static void FLEXCAN_ExitFreezeMode(CAN_Type *base);
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#if !defined(NDEBUG)
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/*!
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* @brief Check if Message Buffer is occupied by Rx FIFO.
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*
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@ -112,6 +116,19 @@ static void FLEXCAN_ExitFrazeMode(CAN_Type *base);
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* @param mbIdx The FlexCAN Message Buffer index.
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*/
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static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx);
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#endif
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#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
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/*!
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* @brief Get the first valid Message buffer ID of give FlexCAN instance.
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*
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* This function is a helper function for Errata 5641 workaround.
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*
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* @param base FlexCAN peripheral base address.
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* @return The first valid Message Buffer Number.
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*/
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static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base);
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#endif
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/*!
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* @brief Check if Message Buffer interrupt is enabled.
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@ -165,6 +182,9 @@ static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS;
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/* Array of FlexCAN clock name. */
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static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS;
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/* FlexCAN ISR for transactional APIs. */
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static flexcan_isr_t s_flexcanIsr;
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/*******************************************************************************
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* Code
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******************************************************************************/
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@ -187,10 +207,10 @@ uint32_t FLEXCAN_GetInstance(CAN_Type *base)
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return instance;
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}
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static void FLEXCAN_EnterFrazeMode(CAN_Type *base)
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static void FLEXCAN_EnterFreezeMode(CAN_Type *base)
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{
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/* Set Freeze, Halt bits. */
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base->MCR |= CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK;
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base->MCR |= CAN_MCR_HALT_MASK;
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/* Wait until the FlexCAN Module enter freeze mode. */
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while (!(base->MCR & CAN_MCR_FRZACK_MASK))
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@ -198,10 +218,10 @@ static void FLEXCAN_EnterFrazeMode(CAN_Type *base)
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}
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}
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static void FLEXCAN_ExitFrazeMode(CAN_Type *base)
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static void FLEXCAN_ExitFreezeMode(CAN_Type *base)
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{
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/* Clear Freeze, Halt bits. */
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base->MCR &= ~(CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK);
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base->MCR &= ~CAN_MCR_HALT_MASK;
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/* Wait until the FlexCAN Module exit freeze mode. */
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while (base->MCR & CAN_MCR_FRZACK_MASK)
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@ -209,6 +229,7 @@ static void FLEXCAN_ExitFrazeMode(CAN_Type *base)
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}
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}
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#if !defined(NDEBUG)
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static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx)
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{
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uint8_t lastOccupiedMb;
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@ -221,7 +242,11 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx)
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/* Calculate the number of last Message Buffer occupied by Rx FIFO. */
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lastOccupiedMb = ((lastOccupiedMb + 1) * 2) + 5;
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#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
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if (mbIdx <= (lastOccupiedMb + 1))
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#else
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if (mbIdx <= lastOccupiedMb)
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#endif
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{
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return true;
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}
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@ -231,10 +256,41 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx)
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}
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}
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else
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{
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#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
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if (0 == mbIdx)
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{
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return true;
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}
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else
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{
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return false;
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}
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#else
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return false;
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#endif
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}
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}
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#endif
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#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
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static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base)
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{
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uint32_t firstValidMbNum;
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if (base->MCR & CAN_MCR_RFEN_MASK)
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{
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firstValidMbNum = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT);
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firstValidMbNum = ((firstValidMbNum + 1) * 2) + 6;
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}
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else
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{
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firstValidMbNum = 0;
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}
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return firstValidMbNum;
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}
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#endif
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static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx)
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{
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@ -387,7 +443,7 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc
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/* Reset to known status. */
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FLEXCAN_Reset(base);
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/* Save current MCR value. */
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/* Save current MCR value and enable to enter Freeze mode(enabled by default). */
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mcrTemp = base->MCR;
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/* Set the maximum number of Message Buffers */
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@ -448,8 +504,8 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf
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/* Assertion. */
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assert(config);
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/* Enter Fraze Mode. */
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FLEXCAN_EnterFrazeMode(base);
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/* Enter Freeze Mode. */
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FLEXCAN_EnterFreezeMode(base);
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/* Cleaning previous Timing Setting. */
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base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK |
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@ -460,59 +516,55 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf
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(CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) |
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CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | CAN_CTRL1_PROPSEG(config->propSeg));
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/* Exit Fraze Mode. */
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FLEXCAN_ExitFrazeMode(base);
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/* Exit Freeze Mode. */
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FLEXCAN_ExitFreezeMode(base);
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}
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void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask)
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void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask)
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{
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/* Enter Fraze Mode. */
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FLEXCAN_EnterFrazeMode(base);
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/* Enter Freeze Mode. */
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FLEXCAN_EnterFreezeMode(base);
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/* Setting Rx Message Buffer Global Mask value. */
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base->RXMGMASK = mask;
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base->RX14MASK = mask;
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base->RX15MASK = mask;
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/* Exit Fraze Mode. */
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FLEXCAN_ExitFrazeMode(base);
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/* Exit Freeze Mode. */
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FLEXCAN_ExitFreezeMode(base);
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}
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void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask)
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void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask)
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{
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/* Enter Fraze Mode. */
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FLEXCAN_EnterFrazeMode(base);
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/* Enter Freeze Mode. */
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FLEXCAN_EnterFreezeMode(base);
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/* Setting Rx FIFO Global Mask value. */
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base->RXFGMASK = mask;
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/* Exit Fraze Mode. */
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FLEXCAN_ExitFrazeMode(base);
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/* Exit Freeze Mode. */
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FLEXCAN_ExitFreezeMode(base);
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}
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void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask)
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void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask)
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{
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assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
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/* Enter Fraze Mode. */
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FLEXCAN_EnterFrazeMode(base);
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/* Enter Freeze Mode. */
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FLEXCAN_EnterFreezeMode(base);
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/* Setting Rx Individual Mask value. */
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base->RXIMR[maskIdx] = mask;
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/* Exit Fraze Mode. */
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FLEXCAN_ExitFrazeMode(base);
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/* Exit Freeze Mode. */
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FLEXCAN_ExitFreezeMode(base);
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}
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void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)
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{
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/* Assertion. */
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assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
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if (FLEXCAN_IsMbOccupied(base, mbIdx))
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{
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assert(false);
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}
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assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
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/* Inactivate Message Buffer. */
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if (enable)
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@ -535,14 +587,10 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co
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/* Assertion. */
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assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
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assert(((config) || (false == enable)));
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assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
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uint32_t cs_temp = 0;
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if (FLEXCAN_IsMbOccupied(base, mbIdx))
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{
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assert(false);
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}
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/* Inactivate Message Buffer. */
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base->MB[mbIdx].CS = 0;
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@ -574,7 +622,7 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co
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}
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}
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void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable)
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void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable)
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{
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/* Assertion. */
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assert((config) || (false == enable));
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@ -582,8 +630,8 @@ void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *con
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volatile uint32_t *idFilterRegion = (volatile uint32_t *)(&base->MB[6].CS);
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uint8_t setup_mb, i, rffn = 0;
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/* Enter Fraze Mode. */
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FLEXCAN_EnterFrazeMode(base);
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/* Enter Freeze Mode. */
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FLEXCAN_EnterFreezeMode(base);
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if (enable)
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{
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@ -675,8 +723,8 @@ void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *con
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FLEXCAN_SetRxMbConfig(base, 5, NULL, false);
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}
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/* Exit Fraze Mode. */
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FLEXCAN_ExitFrazeMode(base);
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/* Exit Freeze Mode. */
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FLEXCAN_ExitFreezeMode(base);
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}
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#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA)
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@ -684,25 +732,25 @@ void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable)
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{
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if (enable)
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{
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/* Enter Fraze Mode. */
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FLEXCAN_EnterFrazeMode(base);
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/* Enter Freeze Mode. */
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FLEXCAN_EnterFreezeMode(base);
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/* Enable FlexCAN DMA. */
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base->MCR |= CAN_MCR_DMA_MASK;
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/* Exit Fraze Mode. */
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FLEXCAN_ExitFrazeMode(base);
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/* Exit Freeze Mode. */
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FLEXCAN_ExitFreezeMode(base);
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}
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else
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{
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/* Enter Fraze Mode. */
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FLEXCAN_EnterFrazeMode(base);
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/* Enter Freeze Mode. */
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FLEXCAN_EnterFreezeMode(base);
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/* Disable FlexCAN DMA. */
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base->MCR &= ~CAN_MCR_DMA_MASK;
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/* Exit Fraze Mode. */
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FLEXCAN_ExitFrazeMode(base);
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/* Exit Freeze Mode. */
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FLEXCAN_ExitFreezeMode(base);
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}
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}
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#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */
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@ -713,14 +761,10 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t
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assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
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assert(txFrame);
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assert(txFrame->length <= 8);
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assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
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uint32_t cs_temp = 0;
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if (FLEXCAN_IsMbOccupied(base, mbIdx))
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{
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assert(false);
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}
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/* Check if Message Buffer is available. */
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if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK))
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{
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@ -751,6 +795,11 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t
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/* Activate Tx Message Buffer. */
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base->MB[mbIdx].CS = cs_temp;
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#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
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base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
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base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
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#endif
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return kStatus_Success;
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}
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else
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@ -765,15 +814,11 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram
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/* Assertion. */
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assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
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assert(rxFrame);
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assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
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uint32_t cs_temp;
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uint8_t rx_code;
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if (FLEXCAN_IsMbOccupied(base, mbIdx))
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{
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assert(false);
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}
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/* Read CS field of Rx Message Buffer to lock Message Buffer. */
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cs_temp = base->MB[mbIdx].CS;
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/* Get Rx Message Buffer Code field. */
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@ -819,7 +864,7 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram
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}
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}
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status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame)
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status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame)
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{
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/* Assertion. */
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assert(rxFrame);
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@ -863,7 +908,7 @@ status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame)
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}
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}
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status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame)
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status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame)
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{
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/* Write Tx Message Buffer to initiate a data sending. */
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if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, txFrame))
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@ -884,7 +929,7 @@ status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra
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}
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}
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status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame)
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status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame)
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{
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/* Wait until Rx Message Buffer non-empty. */
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while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx))
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@ -898,7 +943,7 @@ status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_
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return FLEXCAN_ReadRxMb(base, mbIdx, rxFrame);
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}
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status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame)
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status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame)
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{
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status_t rxFifoStatus;
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||||
|
||||
|
|
@ -908,7 +953,7 @@ status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rx
|
|||
}
|
||||
|
||||
/* */
|
||||
rxFifoStatus = FlEXCAN_ReadRxFifo(base, rxFrame);
|
||||
rxFifoStatus = FLEXCAN_ReadRxFifo(base, rxFrame);
|
||||
|
||||
/* Clean Rx Fifo available flag. */
|
||||
FLEXCAN_ClearMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag);
|
||||
|
|
@ -938,6 +983,8 @@ void FLEXCAN_TransferCreateHandle(CAN_Type *base,
|
|||
handle->callback = callback;
|
||||
handle->userData = userData;
|
||||
|
||||
s_flexcanIsr = FLEXCAN_TransferHandleIRQ;
|
||||
|
||||
/* We Enable Error & Status interrupt here, because this interrupt just
|
||||
* report current status of FlexCAN module through Callback function.
|
||||
* It is insignificance without a available callback function.
|
||||
|
|
@ -970,11 +1017,7 @@ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handl
|
|||
assert(handle);
|
||||
assert(xfer);
|
||||
assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
||||
|
||||
if (FLEXCAN_IsMbOccupied(base, xfer->mbIdx))
|
||||
{
|
||||
assert(false);
|
||||
}
|
||||
assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx));
|
||||
|
||||
/* Check if Message Buffer is idle. */
|
||||
if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx])
|
||||
|
|
@ -1017,11 +1060,7 @@ status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *ha
|
|||
assert(handle);
|
||||
assert(xfer);
|
||||
assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
||||
|
||||
if (FLEXCAN_IsMbOccupied(base, xfer->mbIdx))
|
||||
{
|
||||
assert(false);
|
||||
}
|
||||
assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx));
|
||||
|
||||
/* Check if Message Buffer is idle. */
|
||||
if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx])
|
||||
|
|
@ -1073,11 +1112,7 @@ void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t
|
|||
/* Assertion. */
|
||||
assert(handle);
|
||||
assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
||||
|
||||
if (FLEXCAN_IsMbOccupied(base, mbIdx))
|
||||
{
|
||||
assert(false);
|
||||
}
|
||||
assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
|
||||
|
||||
/* Disable Message Buffer Interrupt. */
|
||||
FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx);
|
||||
|
|
@ -1096,11 +1131,7 @@ void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint
|
|||
/* Assertion. */
|
||||
assert(handle);
|
||||
assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
||||
|
||||
if (FLEXCAN_IsMbOccupied(base, mbIdx))
|
||||
{
|
||||
assert(false);
|
||||
}
|
||||
assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
|
||||
|
||||
/* Disable Message Buffer Interrupt. */
|
||||
FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx);
|
||||
|
|
@ -1185,7 +1216,7 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)
|
|||
break;
|
||||
|
||||
case kFLEXCAN_RxFifoFrameAvlFlag:
|
||||
status = FlEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf);
|
||||
status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf);
|
||||
if (kStatus_Success == status)
|
||||
{
|
||||
status = kStatus_FLEXCAN_RxFifoIdle;
|
||||
|
|
@ -1273,7 +1304,7 @@ void CAN0_DriverIRQHandler(void)
|
|||
{
|
||||
assert(s_flexcanHandle[0]);
|
||||
|
||||
FLEXCAN_TransferHandleIRQ(CAN0, s_flexcanHandle[0]);
|
||||
s_flexcanIsr(CAN0, s_flexcanHandle[0]);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -1282,7 +1313,7 @@ void CAN1_DriverIRQHandler(void)
|
|||
{
|
||||
assert(s_flexcanHandle[1]);
|
||||
|
||||
FLEXCAN_TransferHandleIRQ(CAN1, s_flexcanHandle[1]);
|
||||
s_flexcanIsr(CAN1, s_flexcanHandle[1]);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -1291,7 +1322,7 @@ void CAN2_DriverIRQHandler(void)
|
|||
{
|
||||
assert(s_flexcanHandle[2]);
|
||||
|
||||
FLEXCAN_TransferHandleIRQ(CAN2, s_flexcanHandle[2]);
|
||||
s_flexcanIsr(CAN2, s_flexcanHandle[2]);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -1300,7 +1331,7 @@ void CAN3_DriverIRQHandler(void)
|
|||
{
|
||||
assert(s_flexcanHandle[3]);
|
||||
|
||||
FLEXCAN_TransferHandleIRQ(CAN3, s_flexcanHandle[3]);
|
||||
s_flexcanIsr(CAN3, s_flexcanHandle[3]);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -1309,6 +1340,6 @@ void CAN4_DriverIRQHandler(void)
|
|||
{
|
||||
assert(s_flexcanHandle[4]);
|
||||
|
||||
FLEXCAN_TransferHandleIRQ(CAN4, s_flexcanHandle[4]);
|
||||
s_flexcanIsr(CAN4, s_flexcanHandle[4]);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -37,7 +37,6 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
/*! @file*/
|
||||
|
||||
/******************************************************************************
|
||||
* Definitions
|
||||
|
|
@ -87,10 +86,8 @@
|
|||
(((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
|
||||
(FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */
|
||||
#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \
|
||||
( \
|
||||
((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
|
||||
((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \
|
||||
<< 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */
|
||||
(((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
|
||||
((FLEXCAN_ID_EXT(id) & 0x1FFF8000) << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */
|
||||
#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \
|
||||
(((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \
|
||||
((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \
|
||||
|
|
@ -296,13 +293,13 @@ typedef struct _flexcan_frame
|
|||
uint32_t length : 4; /*!< CAN frame payload length in bytes(Range: 0~8). */
|
||||
uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */
|
||||
uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */
|
||||
uint32_t reserve1 : 1; /*!< Reserved for placeholder. */
|
||||
uint32_t : 1; /*!< Reserved. */
|
||||
uint32_t idhit : 9; /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */
|
||||
uint32_t reserve2 : 3; /*!< Reserved for place holder. */
|
||||
uint32_t : 3; /*!< Reserved. */
|
||||
};
|
||||
union
|
||||
{
|
||||
|
|
@ -366,7 +363,7 @@ typedef struct _flexcan_rx_mb_config
|
|||
flexcan_frame_type_t type; /*!< CAN Frame Type(Data or Remote). */
|
||||
} flexcan_rx_mb_config_t;
|
||||
|
||||
/*! @brief FlexCAN Rx FIFO configure structure. */
|
||||
/*! @brief FlexCAN Rx FIFO configuration structure. */
|
||||
typedef struct _flexcan_rx_fifo_config
|
||||
{
|
||||
uint32_t *idFilterTable; /*!< Pointer to FlexCAN Rx FIFO identifier filter table. */
|
||||
|
|
@ -437,7 +434,7 @@ extern "C" {
|
|||
* to call the FLEXCAN_Init function by passing in these parameters:
|
||||
* @code
|
||||
* flexcan_config_t flexcanConfig;
|
||||
* flexcanConfig.clkSrc = KFLEXCAN_ClkSrcOsc;
|
||||
* flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc;
|
||||
* flexcanConfig.baudRate = 125000U;
|
||||
* flexcanConfig.maxMbNum = 16;
|
||||
* flexcanConfig.enableLoopBack = false;
|
||||
|
|
@ -466,7 +463,7 @@ void FLEXCAN_Deinit(CAN_Type *base);
|
|||
/*!
|
||||
* @brief Get the default configuration structure.
|
||||
*
|
||||
* This function initializes the FlexCAN configure structure to default value. The default
|
||||
* This function initializes the FlexCAN configuration structure to default value. The default
|
||||
* value are:
|
||||
* flexcanConfig->clkSrc = KFLEXCAN_ClkSrcOsc;
|
||||
* flexcanConfig->baudRate = 125000U;
|
||||
|
|
@ -512,7 +509,7 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf
|
|||
* @param base FlexCAN peripheral base address.
|
||||
* @param mask Rx Message Buffer Global Mask value.
|
||||
*/
|
||||
void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask);
|
||||
void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Sets the FlexCAN receive FIFO global mask.
|
||||
|
|
@ -522,7 +519,7 @@ void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask);
|
|||
* @param base FlexCAN peripheral base address.
|
||||
* @param mask Rx Fifo Global Mask value.
|
||||
*/
|
||||
void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask);
|
||||
void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Sets the FlexCAN receive individual mask.
|
||||
|
|
@ -538,7 +535,7 @@ void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask);
|
|||
* @param maskIdx The Index of individual Mask.
|
||||
* @param mask Rx Individual Mask value.
|
||||
*/
|
||||
void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask);
|
||||
void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Configures a FlexCAN transmit message buffer.
|
||||
|
|
@ -580,7 +577,7 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co
|
|||
* - true: Enable Rx FIFO.
|
||||
* - false: Disable Rx FIFO.
|
||||
*/
|
||||
void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable);
|
||||
void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable);
|
||||
|
||||
/* @} */
|
||||
|
||||
|
|
@ -629,7 +626,7 @@ static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask)
|
|||
* @param txErrBuf Buffer to store Tx Error Counter value.
|
||||
* @param rxErrBuf Buffer to store Rx Error Counter value.
|
||||
*/
|
||||
static inline void FlEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)
|
||||
static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)
|
||||
{
|
||||
if (txErrBuf)
|
||||
{
|
||||
|
|
@ -890,7 +887,7 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram
|
|||
* @retval kStatus_Success - Read Message from Rx FIFO successfully.
|
||||
* @retval kStatus_Fail - Rx FIFO is not enabled.
|
||||
*/
|
||||
status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame);
|
||||
status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame);
|
||||
|
||||
/* @} */
|
||||
|
||||
|
|
@ -910,7 +907,7 @@ status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame);
|
|||
* @retval kStatus_Success - Write Tx Message Buffer Successfully.
|
||||
* @retval kStatus_Fail - Tx Message Buffer is currently in use.
|
||||
*/
|
||||
status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame);
|
||||
status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame);
|
||||
|
||||
/*!
|
||||
* @brief Performs a polling receive transaction on the CAN bus.
|
||||
|
|
@ -924,7 +921,7 @@ status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra
|
|||
* @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully.
|
||||
* @retval kStatus_Fail - Rx Message Buffer is empty.
|
||||
*/
|
||||
status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame);
|
||||
status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame);
|
||||
|
||||
/*!
|
||||
* @brief Performs a polling receive transaction from Rx FIFO on the CAN bus.
|
||||
|
|
@ -936,7 +933,7 @@ status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_
|
|||
* @retval kStatus_Success - Read Message from Rx FIFO successfully.
|
||||
* @retval kStatus_Fail - Rx FIFO is not enabled.
|
||||
*/
|
||||
status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame);
|
||||
status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame);
|
||||
|
||||
/*!
|
||||
* @brief Initializes the FlexCAN handle.
|
||||
|
|
|
|||
|
|
@ -73,6 +73,9 @@ enum _flexcan_mb_code_tx
|
|||
kFLEXCAN_TxMbNotUsed = 0xF, /*!< Not used.*/
|
||||
};
|
||||
|
||||
/* Typedef for interrupt handler. */
|
||||
typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle);
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
|
@ -86,23 +89,24 @@ enum _flexcan_mb_code_tx
|
|||
uint32_t FLEXCAN_GetInstance(CAN_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Enter FlexCAN Fraze Mode.
|
||||
* @brief Enter FlexCAN Freeze Mode.
|
||||
*
|
||||
* This function makes the FlexCAN work under Fraze Mode.
|
||||
* This function makes the FlexCAN work under Freeze Mode.
|
||||
*
|
||||
* @param base FlexCAN peripheral base address.
|
||||
*/
|
||||
static void FLEXCAN_EnterFrazeMode(CAN_Type *base);
|
||||
static void FLEXCAN_EnterFreezeMode(CAN_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Exit FlexCAN Fraze Mode.
|
||||
* @brief Exit FlexCAN Freeze Mode.
|
||||
*
|
||||
* This function makes the FlexCAN leave Fraze Mode.
|
||||
* This function makes the FlexCAN leave Freeze Mode.
|
||||
*
|
||||
* @param base FlexCAN peripheral base address.
|
||||
*/
|
||||
static void FLEXCAN_ExitFrazeMode(CAN_Type *base);
|
||||
static void FLEXCAN_ExitFreezeMode(CAN_Type *base);
|
||||
|
||||
#if !defined(NDEBUG)
|
||||
/*!
|
||||
* @brief Check if Message Buffer is occupied by Rx FIFO.
|
||||
*
|
||||
|
|
@ -112,6 +116,19 @@ static void FLEXCAN_ExitFrazeMode(CAN_Type *base);
|
|||
* @param mbIdx The FlexCAN Message Buffer index.
|
||||
*/
|
||||
static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx);
|
||||
#endif
|
||||
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
|
||||
/*!
|
||||
* @brief Get the first valid Message buffer ID of give FlexCAN instance.
|
||||
*
|
||||
* This function is a helper function for Errata 5641 workaround.
|
||||
*
|
||||
* @param base FlexCAN peripheral base address.
|
||||
* @return The first valid Message Buffer Number.
|
||||
*/
|
||||
static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base);
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Check if Message Buffer interrupt is enabled.
|
||||
|
|
@ -165,6 +182,9 @@ static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS;
|
|||
/* Array of FlexCAN clock name. */
|
||||
static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS;
|
||||
|
||||
/* FlexCAN ISR for transactional APIs. */
|
||||
static flexcan_isr_t s_flexcanIsr;
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
|
@ -187,10 +207,10 @@ uint32_t FLEXCAN_GetInstance(CAN_Type *base)
|
|||
return instance;
|
||||
}
|
||||
|
||||
static void FLEXCAN_EnterFrazeMode(CAN_Type *base)
|
||||
static void FLEXCAN_EnterFreezeMode(CAN_Type *base)
|
||||
{
|
||||
/* Set Freeze, Halt bits. */
|
||||
base->MCR |= CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK;
|
||||
base->MCR |= CAN_MCR_HALT_MASK;
|
||||
|
||||
/* Wait until the FlexCAN Module enter freeze mode. */
|
||||
while (!(base->MCR & CAN_MCR_FRZACK_MASK))
|
||||
|
|
@ -198,10 +218,10 @@ static void FLEXCAN_EnterFrazeMode(CAN_Type *base)
|
|||
}
|
||||
}
|
||||
|
||||
static void FLEXCAN_ExitFrazeMode(CAN_Type *base)
|
||||
static void FLEXCAN_ExitFreezeMode(CAN_Type *base)
|
||||
{
|
||||
/* Clear Freeze, Halt bits. */
|
||||
base->MCR &= ~(CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK);
|
||||
base->MCR &= ~CAN_MCR_HALT_MASK;
|
||||
|
||||
/* Wait until the FlexCAN Module exit freeze mode. */
|
||||
while (base->MCR & CAN_MCR_FRZACK_MASK)
|
||||
|
|
@ -209,6 +229,7 @@ static void FLEXCAN_ExitFrazeMode(CAN_Type *base)
|
|||
}
|
||||
}
|
||||
|
||||
#if !defined(NDEBUG)
|
||||
static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx)
|
||||
{
|
||||
uint8_t lastOccupiedMb;
|
||||
|
|
@ -221,7 +242,11 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx)
|
|||
/* Calculate the number of last Message Buffer occupied by Rx FIFO. */
|
||||
lastOccupiedMb = ((lastOccupiedMb + 1) * 2) + 5;
|
||||
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
|
||||
if (mbIdx <= (lastOccupiedMb + 1))
|
||||
#else
|
||||
if (mbIdx <= lastOccupiedMb)
|
||||
#endif
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
|
@ -231,10 +256,41 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx)
|
|||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
|
||||
if (0 == mbIdx)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
else
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
|
||||
static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base)
|
||||
{
|
||||
uint32_t firstValidMbNum;
|
||||
|
||||
if (base->MCR & CAN_MCR_RFEN_MASK)
|
||||
{
|
||||
firstValidMbNum = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT);
|
||||
firstValidMbNum = ((firstValidMbNum + 1) * 2) + 6;
|
||||
}
|
||||
else
|
||||
{
|
||||
firstValidMbNum = 0;
|
||||
}
|
||||
|
||||
return firstValidMbNum;
|
||||
}
|
||||
#endif
|
||||
|
||||
static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx)
|
||||
{
|
||||
|
|
@ -387,7 +443,7 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc
|
|||
/* Reset to known status. */
|
||||
FLEXCAN_Reset(base);
|
||||
|
||||
/* Save current MCR value. */
|
||||
/* Save current MCR value and enable to enter Freeze mode(enabled by default). */
|
||||
mcrTemp = base->MCR;
|
||||
|
||||
/* Set the maximum number of Message Buffers */
|
||||
|
|
@ -448,8 +504,8 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf
|
|||
/* Assertion. */
|
||||
assert(config);
|
||||
|
||||
/* Enter Fraze Mode. */
|
||||
FLEXCAN_EnterFrazeMode(base);
|
||||
/* Enter Freeze Mode. */
|
||||
FLEXCAN_EnterFreezeMode(base);
|
||||
|
||||
/* Cleaning previous Timing Setting. */
|
||||
base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK |
|
||||
|
|
@ -460,59 +516,55 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf
|
|||
(CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) |
|
||||
CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | CAN_CTRL1_PROPSEG(config->propSeg));
|
||||
|
||||
/* Exit Fraze Mode. */
|
||||
FLEXCAN_ExitFrazeMode(base);
|
||||
/* Exit Freeze Mode. */
|
||||
FLEXCAN_ExitFreezeMode(base);
|
||||
}
|
||||
|
||||
void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask)
|
||||
void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask)
|
||||
{
|
||||
/* Enter Fraze Mode. */
|
||||
FLEXCAN_EnterFrazeMode(base);
|
||||
/* Enter Freeze Mode. */
|
||||
FLEXCAN_EnterFreezeMode(base);
|
||||
|
||||
/* Setting Rx Message Buffer Global Mask value. */
|
||||
base->RXMGMASK = mask;
|
||||
base->RX14MASK = mask;
|
||||
base->RX15MASK = mask;
|
||||
|
||||
/* Exit Fraze Mode. */
|
||||
FLEXCAN_ExitFrazeMode(base);
|
||||
/* Exit Freeze Mode. */
|
||||
FLEXCAN_ExitFreezeMode(base);
|
||||
}
|
||||
|
||||
void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask)
|
||||
void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask)
|
||||
{
|
||||
/* Enter Fraze Mode. */
|
||||
FLEXCAN_EnterFrazeMode(base);
|
||||
/* Enter Freeze Mode. */
|
||||
FLEXCAN_EnterFreezeMode(base);
|
||||
|
||||
/* Setting Rx FIFO Global Mask value. */
|
||||
base->RXFGMASK = mask;
|
||||
|
||||
/* Exit Fraze Mode. */
|
||||
FLEXCAN_ExitFrazeMode(base);
|
||||
/* Exit Freeze Mode. */
|
||||
FLEXCAN_ExitFreezeMode(base);
|
||||
}
|
||||
|
||||
void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask)
|
||||
void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask)
|
||||
{
|
||||
assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
||||
|
||||
/* Enter Fraze Mode. */
|
||||
FLEXCAN_EnterFrazeMode(base);
|
||||
/* Enter Freeze Mode. */
|
||||
FLEXCAN_EnterFreezeMode(base);
|
||||
|
||||
/* Setting Rx Individual Mask value. */
|
||||
base->RXIMR[maskIdx] = mask;
|
||||
|
||||
/* Exit Fraze Mode. */
|
||||
FLEXCAN_ExitFrazeMode(base);
|
||||
/* Exit Freeze Mode. */
|
||||
FLEXCAN_ExitFreezeMode(base);
|
||||
}
|
||||
|
||||
void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)
|
||||
{
|
||||
/* Assertion. */
|
||||
assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
||||
|
||||
if (FLEXCAN_IsMbOccupied(base, mbIdx))
|
||||
{
|
||||
assert(false);
|
||||
}
|
||||
assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
|
||||
|
||||
/* Inactivate Message Buffer. */
|
||||
if (enable)
|
||||
|
|
@ -535,14 +587,10 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co
|
|||
/* Assertion. */
|
||||
assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
||||
assert(((config) || (false == enable)));
|
||||
assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
|
||||
|
||||
uint32_t cs_temp = 0;
|
||||
|
||||
if (FLEXCAN_IsMbOccupied(base, mbIdx))
|
||||
{
|
||||
assert(false);
|
||||
}
|
||||
|
||||
/* Inactivate Message Buffer. */
|
||||
base->MB[mbIdx].CS = 0;
|
||||
|
||||
|
|
@ -574,7 +622,7 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co
|
|||
}
|
||||
}
|
||||
|
||||
void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable)
|
||||
void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable)
|
||||
{
|
||||
/* Assertion. */
|
||||
assert((config) || (false == enable));
|
||||
|
|
@ -582,8 +630,8 @@ void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *con
|
|||
volatile uint32_t *idFilterRegion = (volatile uint32_t *)(&base->MB[6].CS);
|
||||
uint8_t setup_mb, i, rffn = 0;
|
||||
|
||||
/* Enter Fraze Mode. */
|
||||
FLEXCAN_EnterFrazeMode(base);
|
||||
/* Enter Freeze Mode. */
|
||||
FLEXCAN_EnterFreezeMode(base);
|
||||
|
||||
if (enable)
|
||||
{
|
||||
|
|
@ -675,8 +723,8 @@ void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *con
|
|||
FLEXCAN_SetRxMbConfig(base, 5, NULL, false);
|
||||
}
|
||||
|
||||
/* Exit Fraze Mode. */
|
||||
FLEXCAN_ExitFrazeMode(base);
|
||||
/* Exit Freeze Mode. */
|
||||
FLEXCAN_ExitFreezeMode(base);
|
||||
}
|
||||
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA)
|
||||
|
|
@ -684,25 +732,25 @@ void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable)
|
|||
{
|
||||
if (enable)
|
||||
{
|
||||
/* Enter Fraze Mode. */
|
||||
FLEXCAN_EnterFrazeMode(base);
|
||||
/* Enter Freeze Mode. */
|
||||
FLEXCAN_EnterFreezeMode(base);
|
||||
|
||||
/* Enable FlexCAN DMA. */
|
||||
base->MCR |= CAN_MCR_DMA_MASK;
|
||||
|
||||
/* Exit Fraze Mode. */
|
||||
FLEXCAN_ExitFrazeMode(base);
|
||||
/* Exit Freeze Mode. */
|
||||
FLEXCAN_ExitFreezeMode(base);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enter Fraze Mode. */
|
||||
FLEXCAN_EnterFrazeMode(base);
|
||||
/* Enter Freeze Mode. */
|
||||
FLEXCAN_EnterFreezeMode(base);
|
||||
|
||||
/* Disable FlexCAN DMA. */
|
||||
base->MCR &= ~CAN_MCR_DMA_MASK;
|
||||
|
||||
/* Exit Fraze Mode. */
|
||||
FLEXCAN_ExitFrazeMode(base);
|
||||
/* Exit Freeze Mode. */
|
||||
FLEXCAN_ExitFreezeMode(base);
|
||||
}
|
||||
}
|
||||
#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */
|
||||
|
|
@ -713,14 +761,10 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t
|
|||
assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
||||
assert(txFrame);
|
||||
assert(txFrame->length <= 8);
|
||||
assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
|
||||
|
||||
uint32_t cs_temp = 0;
|
||||
|
||||
if (FLEXCAN_IsMbOccupied(base, mbIdx))
|
||||
{
|
||||
assert(false);
|
||||
}
|
||||
|
||||
/* Check if Message Buffer is available. */
|
||||
if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK))
|
||||
{
|
||||
|
|
@ -751,6 +795,11 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t
|
|||
/* Activate Tx Message Buffer. */
|
||||
base->MB[mbIdx].CS = cs_temp;
|
||||
|
||||
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
|
||||
base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
|
||||
base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
|
||||
#endif
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
else
|
||||
|
|
@ -765,15 +814,11 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram
|
|||
/* Assertion. */
|
||||
assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
||||
assert(rxFrame);
|
||||
assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
|
||||
|
||||
uint32_t cs_temp;
|
||||
uint8_t rx_code;
|
||||
|
||||
if (FLEXCAN_IsMbOccupied(base, mbIdx))
|
||||
{
|
||||
assert(false);
|
||||
}
|
||||
|
||||
/* Read CS field of Rx Message Buffer to lock Message Buffer. */
|
||||
cs_temp = base->MB[mbIdx].CS;
|
||||
/* Get Rx Message Buffer Code field. */
|
||||
|
|
@ -819,7 +864,7 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram
|
|||
}
|
||||
}
|
||||
|
||||
status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame)
|
||||
status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame)
|
||||
{
|
||||
/* Assertion. */
|
||||
assert(rxFrame);
|
||||
|
|
@ -863,7 +908,7 @@ status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame)
|
|||
}
|
||||
}
|
||||
|
||||
status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame)
|
||||
status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame)
|
||||
{
|
||||
/* Write Tx Message Buffer to initiate a data sending. */
|
||||
if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, txFrame))
|
||||
|
|
@ -884,7 +929,7 @@ status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra
|
|||
}
|
||||
}
|
||||
|
||||
status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame)
|
||||
status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame)
|
||||
{
|
||||
/* Wait until Rx Message Buffer non-empty. */
|
||||
while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx))
|
||||
|
|
@ -898,7 +943,7 @@ status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_
|
|||
return FLEXCAN_ReadRxMb(base, mbIdx, rxFrame);
|
||||
}
|
||||
|
||||
status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame)
|
||||
status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame)
|
||||
{
|
||||
status_t rxFifoStatus;
|
||||
|
||||
|
|
@ -908,7 +953,7 @@ status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rx
|
|||
}
|
||||
|
||||
/* */
|
||||
rxFifoStatus = FlEXCAN_ReadRxFifo(base, rxFrame);
|
||||
rxFifoStatus = FLEXCAN_ReadRxFifo(base, rxFrame);
|
||||
|
||||
/* Clean Rx Fifo available flag. */
|
||||
FLEXCAN_ClearMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag);
|
||||
|
|
@ -938,6 +983,8 @@ void FLEXCAN_TransferCreateHandle(CAN_Type *base,
|
|||
handle->callback = callback;
|
||||
handle->userData = userData;
|
||||
|
||||
s_flexcanIsr = FLEXCAN_TransferHandleIRQ;
|
||||
|
||||
/* We Enable Error & Status interrupt here, because this interrupt just
|
||||
* report current status of FlexCAN module through Callback function.
|
||||
* It is insignificance without a available callback function.
|
||||
|
|
@ -970,11 +1017,7 @@ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handl
|
|||
assert(handle);
|
||||
assert(xfer);
|
||||
assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
||||
|
||||
if (FLEXCAN_IsMbOccupied(base, xfer->mbIdx))
|
||||
{
|
||||
assert(false);
|
||||
}
|
||||
assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx));
|
||||
|
||||
/* Check if Message Buffer is idle. */
|
||||
if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx])
|
||||
|
|
@ -1017,11 +1060,7 @@ status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *ha
|
|||
assert(handle);
|
||||
assert(xfer);
|
||||
assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
||||
|
||||
if (FLEXCAN_IsMbOccupied(base, xfer->mbIdx))
|
||||
{
|
||||
assert(false);
|
||||
}
|
||||
assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx));
|
||||
|
||||
/* Check if Message Buffer is idle. */
|
||||
if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx])
|
||||
|
|
@ -1073,11 +1112,7 @@ void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t
|
|||
/* Assertion. */
|
||||
assert(handle);
|
||||
assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
||||
|
||||
if (FLEXCAN_IsMbOccupied(base, mbIdx))
|
||||
{
|
||||
assert(false);
|
||||
}
|
||||
assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
|
||||
|
||||
/* Disable Message Buffer Interrupt. */
|
||||
FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx);
|
||||
|
|
@ -1096,11 +1131,7 @@ void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint
|
|||
/* Assertion. */
|
||||
assert(handle);
|
||||
assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
||||
|
||||
if (FLEXCAN_IsMbOccupied(base, mbIdx))
|
||||
{
|
||||
assert(false);
|
||||
}
|
||||
assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
|
||||
|
||||
/* Disable Message Buffer Interrupt. */
|
||||
FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx);
|
||||
|
|
@ -1185,7 +1216,7 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)
|
|||
break;
|
||||
|
||||
case kFLEXCAN_RxFifoFrameAvlFlag:
|
||||
status = FlEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf);
|
||||
status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf);
|
||||
if (kStatus_Success == status)
|
||||
{
|
||||
status = kStatus_FLEXCAN_RxFifoIdle;
|
||||
|
|
@ -1273,7 +1304,7 @@ void CAN0_DriverIRQHandler(void)
|
|||
{
|
||||
assert(s_flexcanHandle[0]);
|
||||
|
||||
FLEXCAN_TransferHandleIRQ(CAN0, s_flexcanHandle[0]);
|
||||
s_flexcanIsr(CAN0, s_flexcanHandle[0]);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -1282,7 +1313,7 @@ void CAN1_DriverIRQHandler(void)
|
|||
{
|
||||
assert(s_flexcanHandle[1]);
|
||||
|
||||
FLEXCAN_TransferHandleIRQ(CAN1, s_flexcanHandle[1]);
|
||||
s_flexcanIsr(CAN1, s_flexcanHandle[1]);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -1291,7 +1322,7 @@ void CAN2_DriverIRQHandler(void)
|
|||
{
|
||||
assert(s_flexcanHandle[2]);
|
||||
|
||||
FLEXCAN_TransferHandleIRQ(CAN2, s_flexcanHandle[2]);
|
||||
s_flexcanIsr(CAN2, s_flexcanHandle[2]);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -1300,7 +1331,7 @@ void CAN3_DriverIRQHandler(void)
|
|||
{
|
||||
assert(s_flexcanHandle[3]);
|
||||
|
||||
FLEXCAN_TransferHandleIRQ(CAN3, s_flexcanHandle[3]);
|
||||
s_flexcanIsr(CAN3, s_flexcanHandle[3]);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -1309,6 +1340,6 @@ void CAN4_DriverIRQHandler(void)
|
|||
{
|
||||
assert(s_flexcanHandle[4]);
|
||||
|
||||
FLEXCAN_TransferHandleIRQ(CAN4, s_flexcanHandle[4]);
|
||||
s_flexcanIsr(CAN4, s_flexcanHandle[4]);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -37,7 +37,6 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
/*! @file*/
|
||||
|
||||
/******************************************************************************
|
||||
* Definitions
|
||||
|
|
@ -87,10 +86,8 @@
|
|||
(((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
|
||||
(FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */
|
||||
#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \
|
||||
( \
|
||||
((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
|
||||
((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \
|
||||
<< 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */
|
||||
(((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
|
||||
((FLEXCAN_ID_EXT(id) & 0x1FFF8000) << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */
|
||||
#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \
|
||||
(((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \
|
||||
((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \
|
||||
|
|
@ -296,13 +293,13 @@ typedef struct _flexcan_frame
|
|||
uint32_t length : 4; /*!< CAN frame payload length in bytes(Range: 0~8). */
|
||||
uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */
|
||||
uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */
|
||||
uint32_t reserve1 : 1; /*!< Reserved for placeholder. */
|
||||
uint32_t : 1; /*!< Reserved. */
|
||||
uint32_t idhit : 9; /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */
|
||||
uint32_t reserve2 : 3; /*!< Reserved for place holder. */
|
||||
uint32_t : 3; /*!< Reserved. */
|
||||
};
|
||||
union
|
||||
{
|
||||
|
|
@ -366,7 +363,7 @@ typedef struct _flexcan_rx_mb_config
|
|||
flexcan_frame_type_t type; /*!< CAN Frame Type(Data or Remote). */
|
||||
} flexcan_rx_mb_config_t;
|
||||
|
||||
/*! @brief FlexCAN Rx FIFO configure structure. */
|
||||
/*! @brief FlexCAN Rx FIFO configuration structure. */
|
||||
typedef struct _flexcan_rx_fifo_config
|
||||
{
|
||||
uint32_t *idFilterTable; /*!< Pointer to FlexCAN Rx FIFO identifier filter table. */
|
||||
|
|
@ -437,7 +434,7 @@ extern "C" {
|
|||
* to call the FLEXCAN_Init function by passing in these parameters:
|
||||
* @code
|
||||
* flexcan_config_t flexcanConfig;
|
||||
* flexcanConfig.clkSrc = KFLEXCAN_ClkSrcOsc;
|
||||
* flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc;
|
||||
* flexcanConfig.baudRate = 125000U;
|
||||
* flexcanConfig.maxMbNum = 16;
|
||||
* flexcanConfig.enableLoopBack = false;
|
||||
|
|
@ -466,7 +463,7 @@ void FLEXCAN_Deinit(CAN_Type *base);
|
|||
/*!
|
||||
* @brief Get the default configuration structure.
|
||||
*
|
||||
* This function initializes the FlexCAN configure structure to default value. The default
|
||||
* This function initializes the FlexCAN configuration structure to default value. The default
|
||||
* value are:
|
||||
* flexcanConfig->clkSrc = KFLEXCAN_ClkSrcOsc;
|
||||
* flexcanConfig->baudRate = 125000U;
|
||||
|
|
@ -512,7 +509,7 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf
|
|||
* @param base FlexCAN peripheral base address.
|
||||
* @param mask Rx Message Buffer Global Mask value.
|
||||
*/
|
||||
void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask);
|
||||
void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Sets the FlexCAN receive FIFO global mask.
|
||||
|
|
@ -522,7 +519,7 @@ void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask);
|
|||
* @param base FlexCAN peripheral base address.
|
||||
* @param mask Rx Fifo Global Mask value.
|
||||
*/
|
||||
void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask);
|
||||
void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Sets the FlexCAN receive individual mask.
|
||||
|
|
@ -538,7 +535,7 @@ void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask);
|
|||
* @param maskIdx The Index of individual Mask.
|
||||
* @param mask Rx Individual Mask value.
|
||||
*/
|
||||
void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask);
|
||||
void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Configures a FlexCAN transmit message buffer.
|
||||
|
|
@ -580,7 +577,7 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co
|
|||
* - true: Enable Rx FIFO.
|
||||
* - false: Disable Rx FIFO.
|
||||
*/
|
||||
void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable);
|
||||
void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable);
|
||||
|
||||
/* @} */
|
||||
|
||||
|
|
@ -629,7 +626,7 @@ static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask)
|
|||
* @param txErrBuf Buffer to store Tx Error Counter value.
|
||||
* @param rxErrBuf Buffer to store Rx Error Counter value.
|
||||
*/
|
||||
static inline void FlEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)
|
||||
static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)
|
||||
{
|
||||
if (txErrBuf)
|
||||
{
|
||||
|
|
@ -890,7 +887,7 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram
|
|||
* @retval kStatus_Success - Read Message from Rx FIFO successfully.
|
||||
* @retval kStatus_Fail - Rx FIFO is not enabled.
|
||||
*/
|
||||
status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame);
|
||||
status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame);
|
||||
|
||||
/* @} */
|
||||
|
||||
|
|
@ -910,7 +907,7 @@ status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame);
|
|||
* @retval kStatus_Success - Write Tx Message Buffer Successfully.
|
||||
* @retval kStatus_Fail - Tx Message Buffer is currently in use.
|
||||
*/
|
||||
status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame);
|
||||
status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame);
|
||||
|
||||
/*!
|
||||
* @brief Performs a polling receive transaction on the CAN bus.
|
||||
|
|
@ -924,7 +921,7 @@ status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra
|
|||
* @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully.
|
||||
* @retval kStatus_Fail - Rx Message Buffer is empty.
|
||||
*/
|
||||
status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame);
|
||||
status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame);
|
||||
|
||||
/*!
|
||||
* @brief Performs a polling receive transaction from Rx FIFO on the CAN bus.
|
||||
|
|
@ -936,7 +933,7 @@ status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_
|
|||
* @retval kStatus_Success - Read Message from Rx FIFO successfully.
|
||||
* @retval kStatus_Fail - Rx FIFO is not enabled.
|
||||
*/
|
||||
status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame);
|
||||
status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame);
|
||||
|
||||
/*!
|
||||
* @brief Initializes the FlexCAN handle.
|
||||
|
|
|
|||
Loading…
Reference in New Issue