mirror of https://github.com/ARMmbed/mbed-os.git
Manually resolved GigaDevice target addition.
Cruz Monrreal II
parent
55fe7129a0
commit
35f9ab070c
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/* mbed Microcontroller Library
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* Copyright (c) 2018 GigaDevice Semiconductor Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_PERIPHERALNAMES_H
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#define MBED_PERIPHERALNAMES_H
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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ADC_0 = (int)ADC0,
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ADC_1 = (int)ADC1
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} ADCName;
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typedef enum {
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DAC_0 = (int)DAC0,
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DAC_1 = (int)DAC1,
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} DACName;
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typedef enum {
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UART_0 = (int)USART0,
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UART_1 = (int)USART1,
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UART_2 = (int)USART2,
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UART_3 = (int)UART3,
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UART_4 = (int)UART4
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} UARTName;
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#define STDIO_UART_TX PORTA_9
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#define STDIO_UART_RX PORTA_10
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#define STDIO_UART UART_0
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typedef enum {
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SPI_0 = (int)SPI0,
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SPI_1 = (int)SPI1,
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SPI_2 = (int)SPI2
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} SPIName;
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typedef enum {
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I2C_0 = (int)I2C0,
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I2C_1 = (int)I2C1
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} I2CName;
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typedef enum {
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PWM_0 = (int)TIMER0,
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PWM_1 = (int)TIMER1,
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PWM_2 = (int)TIMER2,
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PWM_3 = (int)TIMER3,
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PWM_4 = (int)TIMER4,
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PWM_5 = (int)TIMER7,
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PWM_6 = (int)TIMER8,
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PWM_7 = (int)TIMER9,
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PWM_8 = (int)TIMER10,
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PWM_9 = (int)TIMER11,
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PWM_10 = (int)TIMER12,
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PWM_11 = (int)TIMER13
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} PWMName;
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typedef enum {
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CAN_0 = (int)CAN0,
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CAN_1 = (int)CAN1
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} CANName;
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -1,358 +0,0 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2018 GigaDevice Semiconductor Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "PeripheralPins.h"
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/* void pin_function(PinName pin, int function);
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configure the speed, mode,and remap function of pins
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the parameter function contains the configuration information,show as below
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bit 0:2 gpio mode
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bit 3:8 remap
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bit 9:10 gpio speed
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bit 11:15 adc /timer channel
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*/
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const int GD_GPIO_REMAP[] = {
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0x00000000,
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GPIO_SPI0_REMAP, /* 1 */
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GPIO_I2C0_REMAP, /* 2 */
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GPIO_USART0_REMAP, /* 3 */
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GPIO_USART1_REMAP, /* 4 */
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GPIO_USART2_PARTIAL_REMAP, /* 5 */
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GPIO_USART2_FULL_REMAP, /* 6 */
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GPIO_TIMER0_PARTIAL_REMAP, /* 7 */
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GPIO_TIMER0_FULL_REMAP, /* 8 */
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GPIO_TIMER1_PARTIAL_REMAP0, /* 9 */
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GPIO_TIMER1_PARTIAL_REMAP1, /* 10 */
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GPIO_TIMER1_FULL_REMAP, /* 11 */
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GPIO_TIMER2_PARTIAL_REMAP, /* 12 */
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GPIO_TIMER2_FULL_REMAP, /* 13 */
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GPIO_TIMER3_REMAP, /* 14 */
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GPIO_PD01_REMAP, /* 15 */
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#if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
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GPIO_CAN_PARTIAL_REMAP, /* 16 */
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GPIO_CAN_FULL_REMAP, /* 17 */
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#else
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0,
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0,
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#endif
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#if (defined(GD32F30X_CL) || defined(GD32F30X_HD))
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GPIO_TIMER4CH3_IREMAP, /* 18 */
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#else
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0,
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#endif
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#if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
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GPIO_ADC0_ETRGINS_REMAP, /* 19 */
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GPIO_ADC0_ETRGREG_REMAP, /* 20 */
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GPIO_ADC1_ETRGINS_REMAP, /* 21 */
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GPIO_ADC1_ETRGREG_REMAP, /* 22 */
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#else
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0,
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0,
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0,
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0,
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#endif
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GPIO_SWJ_NONJTRST_REMAP, /* 23 */
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GPIO_SWJ_SWDPENABLE_REMAP, /* 24 */
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GPIO_SWJ_DISABLE_REMAP, /* 25 */
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#if (defined(GD32F30X_CL))
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GPIO_CAN0_PARTIAL_REMAP, /* 26 */
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GPIO_CAN0_FULL_REMAP, /* 27 */
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GPIO_ENET_REMAP, /* 28 */
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GPIO_CAN1_REMAP, /* 29 */
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GPIO_SPI2_REMAP, /* 30 */
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GPIO_TIMER1ITR0_REMAP, /* 31 */
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GPIO_PTP_PPS_REMAP, /* 32 */
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#else
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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#endif
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GPIO_TIMER8_REMAP, /* 33 */
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GPIO_TIMER9_REMAP, /* 34 */
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GPIO_TIMER10_REMAP, /* 35 */
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GPIO_TIMER12_REMAP, /* 36 */
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GPIO_TIMER13_REMAP, /* 37 */
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GPIO_EXMC_NADV_REMAP, /* 38 */
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GPIO_CTC_REMAP0, /* 39 */
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GPIO_CTC_REMAP1, /* 40 */
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#if (defined(GD32F30X_CL))
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GPIO_ENET_PHY_MII, /* 41 */
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GPIO_ENET_PHY_RMII, /* 42 */
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#else
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0,
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0,
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#endif
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};
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/* GPIO MODE */
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const int GD_GPIO_MODE[] = {
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GPIO_MODE_AIN, /* 0 */
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GPIO_MODE_IN_FLOATING, /* 1 */
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GPIO_MODE_IPD, /* 2 */
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GPIO_MODE_IPU, /* 3 */
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GPIO_MODE_OUT_OD, /* 4 */
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GPIO_MODE_OUT_PP, /* 5 */
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GPIO_MODE_AF_OD, /* 6 */
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GPIO_MODE_AF_PP, /* 7 */
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};
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/* GPIO SPEED */
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const int GD_GPIO_SPEED[] = {
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GPIO_OSPEED_50MHZ, /* 0 */
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GPIO_OSPEED_10MHZ, /* 1 */
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GPIO_OSPEED_2MHZ, /* 2 */
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};
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/* ADC PinMap */
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const PinMap PinMap_ADC[] = {
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{PORTA_0, ADC_0, 0 | (0 << 11)}, /* ADC0_IN0 */
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{PORTA_1, ADC_0, 0 | (1 << 11)}, /* ADC0_IN1 */
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{PORTA_2, ADC_0, 0 | (2 << 11)}, /* ADC0_IN2 */
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{PORTA_3, ADC_0, 0 | (3 << 11)}, /* ADC0_IN3 */
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{PORTA_4, ADC_0, 0 | (4 << 11)}, /* ADC0_IN4 */
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{PORTA_5, ADC_0, 0 | (5 << 11)}, /* ADC0_IN5 */
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{PORTA_6, ADC_0, 0 | (6 << 11)}, /* ADC0_IN6 */
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{PORTA_7, ADC_0, 0 | (7 << 11)}, /* ADC0_IN7 */
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{PORTB_0, ADC_0, 0 | (8 << 11)}, /* ADC0_IN8 */
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{PORTB_1, ADC_0, 0 | (9 << 11)}, /* ADC0_IN9 */
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{PORTC_0, ADC_0, 0 | (10 << 11)}, /* ADC0_IN10 */
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{PORTC_1, ADC_0, 0 | (11 << 11)}, /* ADC0_IN11 */
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{PORTC_2, ADC_0, 0 | (12 << 11)}, /* ADC0_IN12 */
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{PORTC_3, ADC_0, 0 | (13 << 11)}, /* ADC0_IN13 */
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{PORTC_4, ADC_0, 0 | (14 << 11)}, /* ADC0_IN14 */
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{PORTC_5, ADC_0, 0 | (15 << 11)}, /* ADC0_IN15 */
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{ADC_TEMP, ADC_0, 0 | (16 << 11)}, /* ADC0_IN16 */
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{ADC_VREF, ADC_0, 0 | (17 << 11)}, /* ADC0_IN17 */
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{PORTA_0_MUL0, ADC_1, 0 | (0 << 11)}, /* ADC1_IN0 */
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{PORTA_1_MUL0, ADC_1, 0 | (1 << 11)}, /* ADC1_IN1 */
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{PORTA_2_MUL0, ADC_1, 0 | (2 << 11)}, /* ADC1_IN2 */
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{PORTA_3_MUL0, ADC_1, 0 | (3 << 11)}, /* ADC1_IN3 */
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{PORTA_4_MUL0, ADC_1, 0 | (4 << 11)}, /* ADC1_IN4 */
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{PORTA_5_MUL0, ADC_1, 0 | (5 << 11)}, /* ADC1_IN5 */
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{PORTA_6_MUL0, ADC_1, 0 | (6 << 11)}, /* ADC1_IN6 */
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{PORTA_7_MUL0, ADC_1, 0 | (7 << 11)}, /* ADC1_IN7 */
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{PORTB_0_MUL0, ADC_1, 0 | (8 << 11)}, /* ADC1_IN8 */
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{PORTB_1_MUL0, ADC_1, 0 | (9 << 11)}, /* ADC1_IN9 */
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{PORTC_0_MUL0, ADC_1, 0 | (10 << 11)}, /* ADC1_IN10 */
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{PORTC_1_MUL0, ADC_1, 0 | (11 << 11)}, /* ADC1_IN11 */
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{PORTC_2_MUL0, ADC_1, 0 | (12 << 11)}, /* ADC1_IN12 */
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{PORTC_3_MUL0, ADC_1, 0 | (13 << 11)}, /* ADC1_IN13 */
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{PORTC_4_MUL0, ADC_1, 0 | (14 << 11)}, /* ADC1_IN14 */
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{PORTC_5_MUL0, ADC_1, 0 | (15 << 11)}, /* ADC1_IN15 */
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{NC, NC, 0}
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};
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/* DAC PinMap */
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const PinMap PinMap_DAC[] = {
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{PORTA_4, DAC_0, 0 | (0 << 11)}, /* DAC_OUT0 */
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{PORTA_5, DAC_0, 0 | (1 << 11)}, /* DAC_OUT1 */
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{NC, NC, 0}
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};
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/* I2C PinMap */
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const PinMap PinMap_I2C_SDA[] = {
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{PORTB_7, I2C_0, 6},
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{PORTB_9, I2C_0, 6 | (2 << 3)}, /* GPIO_I2C0_REMAP */
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{PORTB_11, I2C_1, 6},
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{NC, NC, 0}
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};
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const PinMap PinMap_I2C_SCL[] = {
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{PORTB_6, I2C_0, 6},
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{PORTB_8, I2C_0, 6 | (2 << 3)}, /* GPIO_I2C0_REMAP */
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{PORTB_10, I2C_1, 6},
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{NC, NC, 0}
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};
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/* PWM PinMap */
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const PinMap PinMap_PWM[] = {
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{PORTA_8, PWM_0, 7 | (0 << 11)}, /* TIMER0_CH0 - Default */
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{PORTA_9, PWM_0, 7 | (1 << 11)}, /* TIMER0_CH1 - Default */
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{PORTA_10, PWM_0, 7 | (2 << 11)}, /* TIMER0_CH2 - Default */
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{PORTA_11, PWM_0, 7 | (3 << 11)}, /* TIMER0_CH3 - Default */
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{PORTE_9, PWM_0, 7 | (8 << 3) | (0 << 11)}, /* TIMER0_CH0 - GPIO_TIMER0_FULL_REMAP */
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{PORTE_11, PWM_0, 7 | (8 << 3) | (1 << 11)}, /* TIMER0_CH1 - GPIO_TIMER0_FULL_REMAP */
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{PORTE_13, PWM_0, 7 | (8 << 3) | (2 << 11)}, /* TIMER0_CH2 - GPIO_TIMER0_FULL_REMAP */
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{PORTE_14, PWM_0, 7 | (8 << 3) | (3 << 11)}, /* TIMER0_CH3 - GPIO_TIMER0_FULL_REMAP */
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{PORTA_0, PWM_1, 7 | (0 << 11)}, /* TIMER1_CH0_ETI - Default */
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{PORTA_1, PWM_1, 7 | (1 << 11)}, /* TIMER1_CH1_ETI - Default */
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{PORTA_2, PWM_1, 7 | (2 << 11)}, /* TIMER1_CH2_ETI - Default */
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{PORTA_3, PWM_1, 7 | (3 << 11)}, /* TIMER1_CH3_ETI - Default */
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{PORTA_15, PWM_1, 7 | (9 << 3) | (0 << 11)}, /* TIMER1_CH0_ETI- GPIO_TIMER1_PARTIAL_REMAP0 */
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{PORTB_3, PWM_1, 7 | (9 << 3) | (1 << 11)}, /* TIMER1_CH1 - GPIO_TIMER1_PARTIAL_REMAP0 */
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{PORTB_10, PWM_1, 7 | (10 << 3) | (2 << 11)}, /* TIMER1_CH2 - GPIO_TIMER1_PARTIAL_REMAP1 */
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{PORTB_11, PWM_1, 7 | (10 << 3) | (3 << 11)}, /* TIMER1_CH3 - GPIO_TIMER1_PARTIAL_REMAP1 */
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{PORTA_15, PWM_1, 7 | (11 << 3) | (0 << 11)}, /* TIMER1_CH0_ETI - GPIO_TIMER1_FULL_REMAP */
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{PORTB_3, PWM_1, 7 | (11 << 3) | (1 << 11)}, /* TIMER1_CH1 - GPIO_TIMER1_FULL_REMAP */
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{PORTB_10, PWM_1, 7 | (11 << 3) | (2 << 11)}, /* TIMER1_CH2 - GPIO_TIMER1_FULL_REMAP */
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{PORTB_11, PWM_1, 7 | (11 << 3) | (3 << 11)}, /* TIMER1_CH3 - GPIO_TIMER1_FULL_REMAP */
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{PORTA_6, PWM_2, 7 | (0 << 11)}, /* TIMER2_CH0 - Default */
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{PORTA_7, PWM_2, 7 | (1 << 11)}, /* TIMER2_CH1 - Default */
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{PORTB_0, PWM_2, 7 | (2 << 11)}, /* TIMER2_CH2 - Default */
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{PORTB_1, PWM_2, 7 | (3 << 11)}, /* TIMER2_CH3 - Default */
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{PORTB_4, PWM_2, 7 | (12 << 3) | (0 << 11)}, /* TIMER2_CH0 - GPIO_TIMER2_PARTIAL_REMAP */
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{PORTB_5, PWM_2, 7 | (12 << 3) | (1 << 11)}, /* TIMER2_CH1 - GPIO_TIMER2_PARTIAL_REMAP */
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{PORTC_6, PWM_2, 7 | (13 << 3) | (0 << 11)}, /* TIMER2_CH0 - GPIO_TIMER2_FULL_REMAP */
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{PORTC_7, PWM_2, 7 | (13 << 3) | (1 << 11)}, /* TIMER2_CH1 - GPIO_TIMER2_FULL_REMAP */
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{PORTC_8, PWM_2, 7 | (13 << 3) | (2 << 11)}, /* TIMER2_CH2 - GPIO_TIMER2_FULL_REMAP */
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{PORTC_9, PWM_2, 7 | (13 << 3) | (3 << 11)}, /* TIMER2_CH3 - GPIO_TIMER2_FULL_REMAP */
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{PORTB_6, PWM_3, 7 | (0 << 11)}, /* TIMER3_CH0 - Default */
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{PORTB_7, PWM_3, 7 | (1 << 11)}, /* TIMER3_CH1 - Default */
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{PORTB_8, PWM_3, 7 | (2 << 11)}, /* TIMER3_CH2 - Default */
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{PORTB_9, PWM_3, 7 | (3 << 11)}, /* TIMER3_CH3 - Default */
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{PORTD_12, PWM_3, 7 | (14 << 3) | (0 << 11)}, /* TIMER3_CH0 - GPIO_TIMER3_REMAP */
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{PORTD_13, PWM_3, 7 | (14 << 3) | (1 << 11)}, /* TIMER3_CH1 - GPIO_TIMER3_REMAP */
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{PORTD_14, PWM_3, 7 | (14 << 3) | (2 << 11)}, /* TIMER3_CH2 - GPIO_TIMER3_REMAP */
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{PORTD_15, PWM_3, 7 | (14 << 3) | (3 << 11)}, /* TIMER3_CH3 - GPIO_TIMER3_REMAP */
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{PORTA_0_MUL0, PWM_4, 7 | (0 << 11)}, /* TIMER4_CH0 - Default */
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{PORTA_1_MUL0, PWM_4, 7 | (1 << 11)}, /* TIMER4_CH1 - Default */
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{PORTA_2_MUL0, PWM_4, 7 | (2 << 11)}, /* TIMER4_CH2 - Default */
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{PORTA_3_MUL0, PWM_4, 7 | (3 << 11)}, /* TIMER4_CH3 - Default */
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{PORTC_6_MUL0, PWM_5, 7 | (0 << 11)}, /* TIMER7_CH0 - Default */
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{PORTC_7_MUL0, PWM_5, 7 | (1 << 11)}, /* TIMER7_CH1 - Default */
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{PORTC_8_MUL0, PWM_5, 7 | (2 << 11)}, /* TIMER7_CH2 - Default */
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{PORTC_9_MUL0, PWM_5, 7 | (3 << 11)}, /* TIMER7_CH3 - Default */
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{PORTA_2_MUL1, PWM_6, 7 | (0 << 11)}, /* TIMER8_CH0 - Default */
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{PORTA_3_MUL1, PWM_6, 7 | (1 << 11)}, /* TIMER8_CH1 - Default */
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{PORTE_5, PWM_6, 7 | (33 << 3) | (0 << 11)}, /* TIMER8_CH0 - GPIO_TIMER8_REMAP */
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{PORTE_6, PWM_6, 7 | (33 << 3) | (1 << 11)}, /* TIMER8_CH1 - GPIO_TIMER8_REMAP */
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{PORTB_8_MUL0, PWM_7, 7 | (0 << 11)}, /* TIMER9_CH0 - Default */
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{PORTB_9_MUL0, PWM_8, 7 | (0 << 11)}, /* TIMER10_CH0 - Default */
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{PORTB_14, PWM_9, 7 | (0 << 11)}, /* TIMER11_CH0 - Default */
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{PORTB_15, PWM_9, 7 | (1 << 11)}, /* TIMER11_CH1 - Default */
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{PORTA_6_MUL0, PWM_10, 7 | (0 << 11)}, /* TIMER12_CH0 - Default */
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{PORTA_7_MUL0, PWM_11, 7 | (0 << 11)}, /* TIMER13_CH0 - Default */
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{NC, NC, 0}
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};
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/* USART PinMap */
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const PinMap PinMap_UART_TX[] = {
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{PORTA_9, UART_0, 7},
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{PORTB_6, UART_0, 7 | (3 << 3)}, /* GPIO_USART0_TX_REMAP */
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{PORTA_2, UART_1, 7},
|
||||
{PORTD_5, UART_1, 7 | (4 << 3)}, /* GPIO_USART1_TX_REMAP */
|
||||
{PORTB_10, UART_2, 7},
|
||||
{PORTC_10, UART_2, 7 | (5 << 3)}, /* GPIO_USART2_TX_PARTIAL_REMAP */
|
||||
{PORTD_8, UART_2, 7 | (6 << 3)}, /* GPIO_USART2_TX_FULL_REMAP */
|
||||
{PORTC_10, UART_3, 7},
|
||||
{PORTC_12, UART_4, 7},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_UART_RX[] = {
|
||||
{PORTA_10, UART_0, 1},
|
||||
{PORTB_7, UART_0, 1 | (3 << 3)}, /* GPIO_USART0_RX_REMAP */
|
||||
{PORTA_3, UART_1, 1},
|
||||
{PORTD_6, UART_1, 1 | (4 << 3)}, /* GPIO_USART1_RX_REMAP */
|
||||
{PORTB_11, UART_2, 1},
|
||||
{PORTC_11, UART_2, 1 | (5 << 3)}, /* GPIO_USART2_RX_PARTIAL_REMAP */
|
||||
{PORTD_9, UART_2, 1 | (6 << 3)}, /* PGPIO_USART2_RX_PARTIAL_REMAP */
|
||||
{PORTC_11, UART_3, 1},
|
||||
{PORTD_2, UART_4, 1},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_UART_RTS[] = {
|
||||
{PORTA_12, UART_0, 7},
|
||||
{PORTA_1, UART_1, 7},
|
||||
{PORTD_4, UART_1, 7 | (4 << 3)}, /* GPIO_USART1_RTS_REMAP */
|
||||
{PORTB_14, UART_2, 7},
|
||||
{PORTD_12, UART_2, 7 | (6 << 3)}, /* GPIO_USART2_RTS_FULL_REMAP */
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_UART_CTS[] = {
|
||||
{PORTA_11, UART_0, 7},
|
||||
{PORTA_0, UART_1, 7},
|
||||
{PORTD_3, UART_1, 7 | (4 << 3)}, /* GPIO_USART1_CTS_REMAP */
|
||||
{PORTB_13, UART_2, 7},
|
||||
{PORTD_11, UART_2, 7 | (6 << 3)}, /* GPIO_USART2_CTS_FULL_REMAP */
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
/* SPI PinMap */
|
||||
const PinMap PinMap_SPI_MOSI[] = {
|
||||
{PORTA_7, SPI_0, 7},
|
||||
{PORTB_5, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */
|
||||
{PORTB_15, SPI_1, 7},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_MISO[] = {
|
||||
{PORTA_6, SPI_0, 1},
|
||||
{PORTB_4, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */
|
||||
{PORTB_14, SPI_1, 7},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_SCLK[] = {
|
||||
{PORTA_5, SPI_0, 7},
|
||||
{PORTB_3, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */
|
||||
{PORTB_13, SPI_1, 7},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_SSEL[] = {
|
||||
{PORTA_4, SPI_0, 7},
|
||||
{PORTA_15, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */
|
||||
{PORTB_12, SPI_1, 7},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
/* CAN PinMap */
|
||||
const PinMap PinMap_CAN_RD[] = {
|
||||
{PORTA_11, CAN_0, 3},
|
||||
{PORTB_8, CAN_0, 3 | (26 << 3)}, /* GPIO_CAN0_PARTIAL_REMAP */
|
||||
{PORTD_0, CAN_0, 3 | (27 << 3)}, /* GPIO_CAN0_FULL_REMAP */
|
||||
{PORTB_12, CAN_1, 3},
|
||||
{PORTB_5, CAN_1, 3 | (29 << 3)}, /* GPIO_CAN1_REMAP */
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_CAN_TD[] = {
|
||||
{PORTA_12, CAN_0, 7},
|
||||
{PORTB_9, CAN_0, 7 | (26 << 3)}, /* GPIO_CAN0_PARTIAL_REMAP */
|
||||
{PORTD_1, CAN_0, 7 | (27 << 3)}, /* GPIO_CAN0_FULL_REMAP */
|
||||
{PORTB_13, CAN_1, 7},
|
||||
{PORTB_6, CAN_1, 7 | (29 << 3)}, /* GPIO_CAN1_REMAP */
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
|
|
@ -1,239 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2018 GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Multiplex GPIO flag*/
|
||||
typedef enum {
|
||||
MUL0 = 0x100,
|
||||
MUL1 = 0x200,
|
||||
MUL2 = 0x300,
|
||||
MUL3 = 0x400
|
||||
} MULx;
|
||||
|
||||
typedef enum {
|
||||
PORTA_0 = 0x00,
|
||||
PORTA_0_MUL0 = PORTA_0 | MUL0,
|
||||
PORTA_1 = 0x01,
|
||||
PORTA_1_MUL0 = PORTA_1 | MUL0,
|
||||
PORTA_2 = 0x02,
|
||||
PORTA_2_MUL0 = PORTA_2 | MUL0,
|
||||
PORTA_2_MUL1 = PORTA_2 | MUL1,
|
||||
PORTA_3 = 0x03,
|
||||
PORTA_3_MUL0 = PORTA_3 | MUL0,
|
||||
PORTA_3_MUL1 = PORTA_3 | MUL1,
|
||||
PORTA_4 = 0x04,
|
||||
PORTA_4_MUL0 = PORTA_4 | MUL0,
|
||||
PORTA_5 = 0x05,
|
||||
PORTA_5_MUL0 = PORTA_5 | MUL0,
|
||||
PORTA_6 = 0x06,
|
||||
PORTA_6_MUL0 = PORTA_6 | MUL0,
|
||||
PORTA_7 = 0x07,
|
||||
PORTA_7_MUL0 = PORTA_7 | MUL0,
|
||||
PORTA_8 = 0x08,
|
||||
PORTA_9 = 0x09,
|
||||
PORTA_10 = 0x0A,
|
||||
PORTA_11 = 0x0B,
|
||||
PORTA_12 = 0x0C,
|
||||
PORTA_13 = 0x0D,
|
||||
PORTA_14 = 0x0E,
|
||||
PORTA_15 = 0x0F,
|
||||
|
||||
PORTB_0 = 0x10,
|
||||
PORTB_0_MUL0 = PORTB_0 | MUL0,
|
||||
PORTB_1 = 0x11,
|
||||
PORTB_1_MUL0 = PORTB_1 | MUL0,
|
||||
PORTB_2 = 0x12,
|
||||
PORTB_3 = 0x13,
|
||||
PORTB_4 = 0x14,
|
||||
PORTB_5 = 0x15,
|
||||
PORTB_6 = 0x16,
|
||||
PORTB_7 = 0x17,
|
||||
PORTB_8 = 0x18,
|
||||
PORTB_8_MUL0 = PORTB_8 | MUL0,
|
||||
PORTB_9 = 0x19,
|
||||
PORTB_9_MUL0 = PORTB_9 | MUL0,
|
||||
PORTB_10 = 0x1A,
|
||||
PORTB_11 = 0x1B,
|
||||
PORTB_12 = 0x1C,
|
||||
PORTB_13 = 0x1D,
|
||||
PORTB_14 = 0x1E,
|
||||
PORTB_15 = 0x1F,
|
||||
|
||||
PORTC_0 = 0x20,
|
||||
PORTC_0_MUL0 = PORTC_0 | MUL0,
|
||||
PORTC_1 = 0x21,
|
||||
PORTC_1_MUL0 = PORTC_1 | MUL0,
|
||||
PORTC_2 = 0x22,
|
||||
PORTC_2_MUL0 = PORTC_2 | MUL0,
|
||||
PORTC_3 = 0x23,
|
||||
PORTC_3_MUL0 = PORTC_3 | MUL0,
|
||||
PORTC_4 = 0x24,
|
||||
PORTC_4_MUL0 = PORTC_4 | MUL0,
|
||||
PORTC_5 = 0x25,
|
||||
PORTC_5_MUL0 = PORTC_5 | MUL0,
|
||||
PORTC_6 = 0x26,
|
||||
PORTC_6_MUL0 = PORTC_6 | MUL0,
|
||||
PORTC_7 = 0x27,
|
||||
PORTC_7_MUL0 = PORTC_7 | MUL0,
|
||||
PORTC_8 = 0x28,
|
||||
PORTC_8_MUL0 = PORTC_8 | MUL0,
|
||||
PORTC_9 = 0x29,
|
||||
PORTC_9_MUL0 = PORTC_9 | MUL0,
|
||||
PORTC_10 = 0x2A,
|
||||
PORTC_11 = 0x2B,
|
||||
PORTC_12 = 0x2C,
|
||||
PORTC_13 = 0x2D,
|
||||
PORTC_14 = 0x2E,
|
||||
PORTC_15 = 0x2F,
|
||||
|
||||
PORTD_0 = 0x30,
|
||||
PORTD_1 = 0x31,
|
||||
PORTD_2 = 0x32,
|
||||
PORTD_3 = 0x33,
|
||||
PORTD_4 = 0x34,
|
||||
PORTD_5 = 0x35,
|
||||
PORTD_6 = 0x36,
|
||||
PORTD_7 = 0x37,
|
||||
PORTD_8 = 0x38,
|
||||
PORTD_9 = 0x39,
|
||||
PORTD_10 = 0x3A,
|
||||
PORTD_11 = 0x3B,
|
||||
PORTD_12 = 0x3C,
|
||||
PORTD_13 = 0x3D,
|
||||
PORTD_14 = 0x3E,
|
||||
PORTD_15 = 0x3F,
|
||||
|
||||
PORTE_0 = 0x40,
|
||||
PORTE_1 = 0x41,
|
||||
PORTE_2 = 0x42,
|
||||
PORTE_3 = 0x43,
|
||||
PORTE_4 = 0x44,
|
||||
PORTE_5 = 0x45,
|
||||
PORTE_6 = 0x46,
|
||||
PORTE_7 = 0x47,
|
||||
PORTE_8 = 0x48,
|
||||
PORTE_9 = 0x49,
|
||||
PORTE_10 = 0x4A,
|
||||
PORTE_11 = 0x4B,
|
||||
PORTE_12 = 0x4C,
|
||||
PORTE_13 = 0x4D,
|
||||
PORTE_14 = 0x4E,
|
||||
PORTE_15 = 0x4F,
|
||||
|
||||
/* ADC internal channels */
|
||||
ADC_TEMP = 0xF0,
|
||||
ADC_VREF = 0xF1,
|
||||
|
||||
|
||||
/* Arduino connector namings */
|
||||
A0 = PORTC_0,
|
||||
A1 = PORTC_1,
|
||||
A2 = PORTC_2,
|
||||
A3 = PORTC_3,
|
||||
A4 = PORTC_4,
|
||||
A4_I2C_SDA = PORTC_11,
|
||||
A4_I2C_SCL = PORTC_10,
|
||||
A5 = PORTC_5,
|
||||
D0 = PORTA_3,
|
||||
D1 = PORTA_2,
|
||||
D2 = PORTA_4,
|
||||
D3 = PORTC_6,
|
||||
D4 = PORTB_3,
|
||||
D5 = PORTC_7,
|
||||
D6 = PORTC_8,
|
||||
D7 = PORTB_4,
|
||||
D8 = PORTB_5,
|
||||
D9 = PORTC_9,
|
||||
D10 = PORTA_1,
|
||||
D11 = PORTB_15,
|
||||
D12 = PORTB_14,
|
||||
D13 = PORTB_13,
|
||||
D14 = PORTB_9,
|
||||
D15 = PORTB_8,
|
||||
|
||||
LED1 = PORTE_0,
|
||||
LED2 = PORTE_1,
|
||||
LED3 = PORTE_6,
|
||||
|
||||
KEY2 = PORTA_0,
|
||||
KEY3 = PORTB_1,
|
||||
|
||||
BUTTON1 = KEY2,
|
||||
BUTTON2 = KEY3,
|
||||
|
||||
SERIAL_TX = PORTA_9,
|
||||
SERIAL_RX = PORTA_10,
|
||||
USBTX = PORTA_9,
|
||||
USBRX = PORTA_10,
|
||||
|
||||
I2C_SCL = PORTB_6,
|
||||
I2C_SDA = PORTB_7,
|
||||
SPI_MOSI = PORTA_7,
|
||||
SPI_MISO = PORTA_6,
|
||||
SPI_SCK = PORTA_5,
|
||||
SPI_CS = PORTE_3,
|
||||
PWM_OUT = PORTA_7,
|
||||
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
/* BIT[7:4] port number (0=PORTA, 1=PORTB, 2=PORTC, 3=PORTD, 4=PORTE, 5=PORTF)
|
||||
BIT[3:0] pin number */
|
||||
#define GD_PORT_GET(X) (((uint32_t)(X) >> 4) & 0xF)
|
||||
#define GD_PIN_GET(X) (((uint32_t)(X) & 0xF))
|
||||
|
||||
/* Get mode,speed,remap function,channel of GPIO pin */
|
||||
#define GD_PIN_MODE_GET(X) (X & 0x07)
|
||||
#define GD_PIN_SPEED_GET(X) ((X >> 9) & 0x03)
|
||||
#define GD_PIN_REMAP_GET(X) ((X >> 3) & 0x3F)
|
||||
#define GD_PIN_CHANNEL_GET(X) ((X >> 11) & 0x0F)
|
||||
|
||||
/* Defines GPIO pin direction */
|
||||
typedef enum {
|
||||
PIN_INPUT = 0,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
/* Defines mode types of GPIO pin */
|
||||
typedef enum {
|
||||
MODE_AIN = 0,
|
||||
MODE_IN_FLOATING,
|
||||
MODE_IPD,
|
||||
MODE_IPU,
|
||||
MODE_OUT_OD,
|
||||
MODE_OUT_PP,
|
||||
MODE_AF_OD,
|
||||
MODE_AF_PP,
|
||||
PullDefault = MODE_IN_FLOATING,
|
||||
PullUp = MODE_IPU,
|
||||
PullDown = MODE_IPD,
|
||||
PullNone = 11
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
#! armcc -E
|
||||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *****
|
||||
|
||||
#if !defined(MBED_APP_START)
|
||||
#define MBED_APP_START 0x08000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_APP_SIZE)
|
||||
#define MBED_APP_SIZE 0x100000
|
||||
#endif
|
||||
|
||||
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (1024K)
|
||||
|
||||
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
; 84 vectors (16 core + 68 peripheral) * 4 bytes = 336 bytes to reserve (0x150)
|
||||
RW_IRAM1 (0x20000000+0x150) (0x18000-0x150) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1,362 +0,0 @@
|
|||
;/*!
|
||||
; \file startup_gd32f30x_cl.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed)
|
||||
;*/
|
||||
;
|
||||
;/*
|
||||
; Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without modification,
|
||||
;are permitted provided that the following conditions are met:
|
||||
;
|
||||
; 1. Redistributions of source code must retain the above copyright notice, this
|
||||
; list of conditions and the following disclaimer.
|
||||
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
; this list of conditions and the following disclaimer in the documentation
|
||||
; and/or other materials provided with the distribution.
|
||||
; 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
; may be used to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
;OF SUCH DAMAGE.
|
||||
;*/
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
EXPORT __initial_sp
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp EQU 0x20010000 ; Top of RAM
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000400
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit EQU (__initial_sp - Stack_Size)
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; /* reset Vector Mapped to at Address 0 */
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; /* external interrupts handler */
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; 19:RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; 20:FMC
|
||||
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
|
||||
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
|
||||
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD SPI0_IRQHandler ; 51:SPI0
|
||||
DCD SPI1_IRQHandler ; 52:SPI1
|
||||
DCD USART0_IRQHandler ; 53:USART0
|
||||
DCD USART1_IRQHandler ; 54:USART1
|
||||
DCD USART2_IRQHandler ; 55:USART2
|
||||
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
|
||||
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||
DCD 0 ; Reserved
|
||||
DCD EXMC_IRQHandler ; 64:EXMC
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||
DCD SPI2_IRQHandler ; 67:SPI2
|
||||
DCD UART3_IRQHandler ; 68:UART3
|
||||
DCD UART4_IRQHandler ; 69:UART4
|
||||
DCD TIMER5_IRQHandler ; 70:TIMER5
|
||||
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||
DCD ENET_IRQHandler ; 77:Ethernet
|
||||
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||
DCD USBFS_IRQHandler ; 83:USBFS
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
;/* reset Handler */
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
;/* dummy Exception Handlers */
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; /* external interrupts handler */
|
||||
EXPORT WWDGT_IRQHandler [WEAK]
|
||||
EXPORT LVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT RCU_CTC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||
EXPORT ADC0_1_IRQHandler [WEAK]
|
||||
EXPORT CAN0_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT USBFS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_Channel_IRQHandler [WEAK]
|
||||
EXPORT EXMC_IRQHandler [WEAK]
|
||||
EXPORT TIMER4_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT TIMER5_IRQHandler [WEAK]
|
||||
EXPORT TIMER6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT ENET_WKUP_IRQHandler [WEAK]
|
||||
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_EWMC_IRQHandler [WEAK]
|
||||
EXPORT USBFS_IRQHandler [WEAK]
|
||||
|
||||
;/* external interrupts handler */
|
||||
WWDGT_IRQHandler
|
||||
LVD_IRQHandler
|
||||
TAMPER_IRQHandler
|
||||
RTC_IRQHandler
|
||||
FMC_IRQHandler
|
||||
RCU_CTC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA0_Channel0_IRQHandler
|
||||
DMA0_Channel1_IRQHandler
|
||||
DMA0_Channel2_IRQHandler
|
||||
DMA0_Channel3_IRQHandler
|
||||
DMA0_Channel4_IRQHandler
|
||||
DMA0_Channel5_IRQHandler
|
||||
DMA0_Channel6_IRQHandler
|
||||
ADC0_1_IRQHandler
|
||||
CAN0_TX_IRQHandler
|
||||
CAN0_RX0_IRQHandler
|
||||
CAN0_RX1_IRQHandler
|
||||
CAN0_EWMC_IRQHandler
|
||||
EXTI5_9_IRQHandler
|
||||
TIMER0_BRK_TIMER8_IRQHandler
|
||||
TIMER0_UP_TIMER9_IRQHandler
|
||||
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
TIMER0_Channel_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
I2C0_EV_IRQHandler
|
||||
I2C0_ER_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
USART0_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
EXTI10_15_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
USBFS_WKUP_IRQHandler
|
||||
TIMER7_BRK_TIMER11_IRQHandler
|
||||
TIMER7_UP_TIMER12_IRQHandler
|
||||
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
TIMER7_Channel_IRQHandler
|
||||
EXMC_IRQHandler
|
||||
TIMER4_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
TIMER5_IRQHandler
|
||||
TIMER6_IRQHandler
|
||||
DMA1_Channel0_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
ENET_IRQHandler
|
||||
ENET_WKUP_IRQHandler
|
||||
CAN1_TX_IRQHandler
|
||||
CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_EWMC_IRQHandler
|
||||
USBFS_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
END
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
#! armcc -E
|
||||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *****
|
||||
|
||||
#if !defined(MBED_APP_START)
|
||||
#define MBED_APP_START 0x08000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_APP_SIZE)
|
||||
#define MBED_APP_SIZE 0x100000
|
||||
#endif
|
||||
|
||||
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (1024K)
|
||||
|
||||
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
; 84 vectors (16 core + 68 peripheral) * 4 bytes = 336 bytes to reserve (0x150)
|
||||
RW_IRAM1 (0x20000000+0x150) (0x18000-0x150) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1,359 +0,0 @@
|
|||
;/*!
|
||||
; \file startup_gd32f30x_cl.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed)
|
||||
;*/
|
||||
;
|
||||
;/*
|
||||
; Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without modification,
|
||||
;are permitted provided that the following conditions are met:
|
||||
;
|
||||
; 1. Redistributions of source code must retain the above copyright notice, this
|
||||
; list of conditions and the following disclaimer.
|
||||
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
; this list of conditions and the following disclaimer in the documentation
|
||||
; and/or other materials provided with the distribution.
|
||||
; 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
; may be used to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
;OF SUCH DAMAGE.
|
||||
;*/
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp EQU 0x20018000
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000400
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; /* reset Vector Mapped to at Address 0 */
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; /* external interrupts handler */
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; 19:RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; 20:FMC
|
||||
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
|
||||
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
|
||||
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD SPI0_IRQHandler ; 51:SPI0
|
||||
DCD SPI1_IRQHandler ; 52:SPI1
|
||||
DCD USART0_IRQHandler ; 53:USART0
|
||||
DCD USART1_IRQHandler ; 54:USART1
|
||||
DCD USART2_IRQHandler ; 55:USART2
|
||||
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
|
||||
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||
DCD 0 ; Reserved
|
||||
DCD EXMC_IRQHandler ; 64:EXMC
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||
DCD SPI2_IRQHandler ; 67:SPI2
|
||||
DCD UART3_IRQHandler ; 68:UART3
|
||||
DCD UART4_IRQHandler ; 69:UART4
|
||||
DCD TIMER5_IRQHandler ; 70:TIMER5
|
||||
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||
DCD ENET_IRQHandler ; 77:Ethernet
|
||||
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||
DCD USBFS_IRQHandler ; 83:USBFS
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
;/* reset Handler */
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
;/* dummy Exception Handlers */
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; /* external interrupts handler */
|
||||
EXPORT WWDGT_IRQHandler [WEAK]
|
||||
EXPORT LVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT RCU_CTC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||
EXPORT ADC0_1_IRQHandler [WEAK]
|
||||
EXPORT CAN0_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT USBFS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_Channel_IRQHandler [WEAK]
|
||||
EXPORT EXMC_IRQHandler [WEAK]
|
||||
EXPORT TIMER4_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT TIMER5_IRQHandler [WEAK]
|
||||
EXPORT TIMER6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT ENET_WKUP_IRQHandler [WEAK]
|
||||
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_EWMC_IRQHandler [WEAK]
|
||||
EXPORT USBFS_IRQHandler [WEAK]
|
||||
|
||||
;/* external interrupts handler */
|
||||
WWDGT_IRQHandler
|
||||
LVD_IRQHandler
|
||||
TAMPER_IRQHandler
|
||||
RTC_IRQHandler
|
||||
FMC_IRQHandler
|
||||
RCU_CTC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA0_Channel0_IRQHandler
|
||||
DMA0_Channel1_IRQHandler
|
||||
DMA0_Channel2_IRQHandler
|
||||
DMA0_Channel3_IRQHandler
|
||||
DMA0_Channel4_IRQHandler
|
||||
DMA0_Channel5_IRQHandler
|
||||
DMA0_Channel6_IRQHandler
|
||||
ADC0_1_IRQHandler
|
||||
CAN0_TX_IRQHandler
|
||||
CAN0_RX0_IRQHandler
|
||||
CAN0_RX1_IRQHandler
|
||||
CAN0_EWMC_IRQHandler
|
||||
EXTI5_9_IRQHandler
|
||||
TIMER0_BRK_TIMER8_IRQHandler
|
||||
TIMER0_UP_TIMER9_IRQHandler
|
||||
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
TIMER0_Channel_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
I2C0_EV_IRQHandler
|
||||
I2C0_ER_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
USART0_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
EXTI10_15_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
USBFS_WKUP_IRQHandler
|
||||
TIMER7_BRK_TIMER11_IRQHandler
|
||||
TIMER7_UP_TIMER12_IRQHandler
|
||||
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
TIMER7_Channel_IRQHandler
|
||||
EXMC_IRQHandler
|
||||
TIMER4_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
TIMER5_IRQHandler
|
||||
TIMER6_IRQHandler
|
||||
DMA1_Channel0_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
ENET_IRQHandler
|
||||
ENET_WKUP_IRQHandler
|
||||
CAN1_TX_IRQHandler
|
||||
CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_EWMC_IRQHandler
|
||||
USBFS_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
END
|
||||
|
|
@ -1,123 +0,0 @@
|
|||
/* specify memory regions */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||
RAM (rwx) : ORIGIN = 0x20000150, LENGTH = 96K - 0x150
|
||||
}
|
||||
|
||||
/* define output sections */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text*)
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
__etext = .;
|
||||
_sidata = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
_sdata = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
_edata = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
_sbss = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
_ebss = .;
|
||||
} > RAM
|
||||
|
||||
.heap (COPY):
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
.stack_dummy (COPY):
|
||||
{
|
||||
*(.stack*)
|
||||
} > RAM
|
||||
|
||||
/* initializes stack on the end of block */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
_estack = __StackTop;
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
|
||||
|
|
@ -1,413 +0,0 @@
|
|||
;/*!
|
||||
; \file startup_gd32f30x_cl.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed)
|
||||
;*/
|
||||
;
|
||||
;/*
|
||||
; Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without modification,
|
||||
;are permitted provided that the following conditions are met:
|
||||
;
|
||||
; 1. Redistributions of source code must retain the above copyright notice, this
|
||||
; list of conditions and the following disclaimer.
|
||||
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
; this list of conditions and the following disclaimer in the documentation
|
||||
; and/or other materials provided with the distribution.
|
||||
; 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
; may be used to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
;OF SUCH DAMAGE.
|
||||
;*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global VecTab
|
||||
.global Default_Handler
|
||||
|
||||
/* start address of the initialization .data */
|
||||
.word _sidata
|
||||
/* start address of the .data section */
|
||||
.word _sdata
|
||||
/* end address of the .data section */
|
||||
.word _edata
|
||||
|
||||
/* reset Handler */
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
|
||||
/* copy the data segment into RAM */
|
||||
movs r1, #0
|
||||
b DataInit
|
||||
|
||||
CopyData:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
DataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyData
|
||||
|
||||
/* system clock intitialization*/
|
||||
bl SystemInit
|
||||
/* static constructors */
|
||||
// bl __libc_init_array
|
||||
/* jump to application's entry point */
|
||||
// bl main
|
||||
bl _start
|
||||
/* infinite loop */
|
||||
b .
|
||||
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
/* infinite loop */
|
||||
b .
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type VecTab, %object
|
||||
.size VecTab, .-VecTab
|
||||
|
||||
|
||||
VecTab:
|
||||
|
||||
.word _estack /* Top of Stack */
|
||||
.word Reset_Handler /* 1,Reset Handler */
|
||||
.word NMI_Handler /* 2,NMI Handler */
|
||||
.word HardFault_Handler /* 3,Hard Fault Handler */
|
||||
.word MemManage_Handler /* 4,MPU Fault Handler */
|
||||
.word BusFault_Handler /* 5,Bus Fault Handler */
|
||||
.word UsageFault_Handler /* 6,Usage Fault Handler */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word SVC_Handler /* 11,SVCall Handler */
|
||||
.word DebugMon_Handler /* 12,Debug Monitor Handler */
|
||||
.word 0 /* Reserved */
|
||||
.word PendSV_Handler /* 14,PendSV Handler */
|
||||
.word SysTick_Handler /* 15,SysTick Handler */
|
||||
/* External Interrupts */
|
||||
.word WWDGT_IRQHandler /* 16,Window Watchdog Timer */
|
||||
.word LVD_IRQHandler /* 17,LVD through EXTI Line detect */
|
||||
.word TAMPER_IRQHandler /* 18,Tamper through EXTI Line detect */
|
||||
.word RTC_IRQHandler /* 19,RTC through EXTI Line */
|
||||
.word FMC_IRQHandler /* 20,FMC */
|
||||
.word RCU_CTC_IRQHandler /* 21,RCU and CTC */
|
||||
.word EXTI0_IRQHandler /* 22,EXTI Line 0 */
|
||||
.word EXTI1_IRQHandler /* 23,EXTI Line 1 */
|
||||
.word EXTI2_IRQHandler /* 24,EXTI Line 2 */
|
||||
.word EXTI3_IRQHandler /* 25,EXTI Line 3 */
|
||||
.word EXTI4_IRQHandler /* 26,EXTI Line 4 */
|
||||
.word DMA0_Channel0_IRQHandler /* 27,DMA0 Channel 0 */
|
||||
.word DMA0_Channel1_IRQHandler /* 28,DMA0 Channel 1 */
|
||||
.word DMA0_Channel2_IRQHandler /* 29,DMA0 Channel 2 */
|
||||
.word DMA0_Channel3_IRQHandler /* 30,DMA0 Channel 3 */
|
||||
.word DMA0_Channel4_IRQHandler /* 31,DMA0 Channel 4 */
|
||||
.word DMA0_Channel5_IRQHandler /* 32,DMA0 Channel 5 */
|
||||
.word DMA0_Channel6_IRQHandler /* 33,DMA0 Channel 6 */
|
||||
.word ADC0_1_IRQHandler /* 34,ADC0 and ADC1 */
|
||||
.word CAN0_TX_IRQHandler /* 35,CAN0 TX */
|
||||
.word CAN0_RX0_IRQHandler /* 36,CAN0 RX0 */
|
||||
.word CAN0_RX1_IRQHandler /* 37,CAN0 RX1 */
|
||||
.word CAN0_EWMC_IRQHandler /* 38,CAN0 EWMC */
|
||||
.word EXTI5_9_IRQHandler /* 39,EXTI5 to EXTI9 */
|
||||
.word TIMER0_BRK_TIMER8_IRQHandler /* 40,TIMER0 Break and TIMER8 */
|
||||
.word TIMER0_UP_TIMER9_IRQHandler /* 41,TIMER0 Update and TIMER9 */
|
||||
.word TIMER0_TRG_CMT_TIMER10_IRQHandler /* 42,TIMER0 Trigger and Commutation and TIMER10 */
|
||||
.word TIMER0_Channel_IRQHandler /* 43,TIMER0 Channel Capture Compare */
|
||||
.word TIMER1_IRQHandler /* 44,TIMER4 */
|
||||
.word TIMER2_IRQHandler /* 45,TIMER2 */
|
||||
.word TIMER3_IRQHandler /* 46,TIMER3 */
|
||||
.word I2C0_EV_IRQHandler /* 47,I2C0 Event */
|
||||
.word I2C0_ER_IRQHandler /* 48,I2C0 Error */
|
||||
.word I2C1_EV_IRQHandler /* 49,I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* 50,I2C1 Error */
|
||||
.word SPI0_IRQHandler /* 51,SPI0 */
|
||||
.word SPI1_IRQHandler /* 52,SPI1 */
|
||||
.word USART0_IRQHandler /* 53,USART0 */
|
||||
.word USART1_IRQHandler /* 54,USART1 */
|
||||
.word USART2_IRQHandler /* 55,USART2 */
|
||||
.word EXTI10_15_IRQHandler /* 56,EXTI10 to EXTI15 */
|
||||
.word RTC_Alarm_IRQHandler /* 57,RTC Alarm */
|
||||
.word USBFS_WKUP_IRQHandler /* 58,USBFS Wakeup */
|
||||
.word TIMER7_BRK_TIMER11_IRQHandler /* 59,TIMER7 Break and TIMER11 */
|
||||
.word TIMER7_UP_TIMER12_IRQHandler /* 60:TIMER7 Update and TIMER12 */
|
||||
.word TIMER7_TRG_CMT_TIMER13_IRQHandler /* 61:TIMER7 Trigger and Commutation and TIMER13 */
|
||||
.word TIMER7_Channel_IRQHandler /* 62,TIMER7 Capture Compare */
|
||||
.word 0 /* Reserved */
|
||||
.word EXMC_IRQHandler /* 64,EXMC */
|
||||
.word 0 /* Reserved */
|
||||
.word TIMER4_IRQHandler /* 66,TIMER4 */
|
||||
.word SPI2_IRQHandler /* 67,SPI2 */
|
||||
.word UART3_IRQHandler /* 68,UART3 */
|
||||
.word UART4_IRQHandler /* 69,UART4 */
|
||||
.word TIMER5_IRQHandler /* 70,TIMER5 */
|
||||
.word TIMER6_IRQHandler /* 71,TIMER6 */
|
||||
.word DMA1_Channel0_IRQHandler /* 72,DMA1 Channel0 */
|
||||
.word DMA1_Channel1_IRQHandler /* 73,DMA1 Channel1 */
|
||||
.word DMA1_Channel2_IRQHandler /* 74,DMA1 Channel2 */
|
||||
.word DMA1_Channel3_IRQHandler /* 75,DMA1 Channel3 */
|
||||
.word DMA1_Channel4_IRQHandler /* 76,DMA1 Channel4 */
|
||||
.word ENET_IRQHandler /* 77,Ethernet */
|
||||
.word ENET_WKUP_IRQHandler /* 78,Ethernet Wakeup through EXTI line */
|
||||
.word CAN1_TX_IRQHandler /* 79,CAN1 TX */
|
||||
.word CAN1_RX0_IRQHandler /* 80,CAN1 RX0 */
|
||||
.word CAN1_RX1_IRQHandler /* 81,CAN1 RX1 */
|
||||
.word CAN1_EWMC_IRQHandler /* 82,CAN1 EWMC */
|
||||
.word USBFS_IRQHandler /* 83,USBFS */
|
||||
|
||||
/* dummy Exception Handlers */
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDGT_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak LVD_IRQHandler
|
||||
.thumb_set LVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMPER_IRQHandler
|
||||
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCU_CTC_IRQHandler
|
||||
.thumb_set RCU_CTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel0_IRQHandler
|
||||
.thumb_set DMA0_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel1_IRQHandler
|
||||
.thumb_set DMA0_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel2_IRQHandler
|
||||
.thumb_set DMA0_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel3_IRQHandler
|
||||
.thumb_set DMA0_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel4_IRQHandler
|
||||
.thumb_set DMA0_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel5_IRQHandler
|
||||
.thumb_set DMA0_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel6_IRQHandler
|
||||
.thumb_set DMA0_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC0_1_IRQHandler
|
||||
.thumb_set ADC0_1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_TX_IRQHandler
|
||||
.thumb_set CAN0_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_RX0_IRQHandler
|
||||
.thumb_set CAN0_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_RX1_IRQHandler
|
||||
.thumb_set CAN0_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_EWMC_IRQHandler
|
||||
.thumb_set CAN0_EWMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI5_9_IRQHandler
|
||||
.thumb_set EXTI5_9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_BRK_TIMER8_IRQHandler
|
||||
.thumb_set TIMER0_BRK_TIMER8_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_UP_TIMER9_IRQHandler
|
||||
.thumb_set TIMER0_UP_TIMER9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
.thumb_set TIMER0_TRG_CMT_TIMER10_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_Channel_IRQHandler
|
||||
.thumb_set TIMER0_Channel_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER1_IRQHandler
|
||||
.thumb_set TIMER1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER2_IRQHandler
|
||||
.thumb_set TIMER2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER3_IRQHandler
|
||||
.thumb_set TIMER3_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C0_EV_IRQHandler
|
||||
.thumb_set I2C0_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C0_ER_IRQHandler
|
||||
.thumb_set I2C0_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI0_IRQHandler
|
||||
.thumb_set SPI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART0_IRQHandler
|
||||
.thumb_set USART0_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI10_15_IRQHandler
|
||||
.thumb_set EXTI10_15_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBFS_WKUP_IRQHandler
|
||||
.thumb_set USBFS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_BRK_TIMER11_IRQHandler
|
||||
.thumb_set TIMER7_BRK_TIMER11_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_UP_TIMER12_IRQHandler
|
||||
.thumb_set TIMER7_UP_TIMER12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
.thumb_set TIMER7_TRG_CMT_TIMER13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_Channel_IRQHandler
|
||||
.thumb_set TIMER7_Channel_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXMC_IRQHandler
|
||||
.thumb_set EXMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER4_IRQHandler
|
||||
.thumb_set TIMER4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART3_IRQHandler
|
||||
.thumb_set UART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER5_IRQHandler
|
||||
.thumb_set TIMER5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER6_IRQHandler
|
||||
.thumb_set TIMER6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel0_IRQHandler
|
||||
.thumb_set DMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ENET_IRQHandler
|
||||
.thumb_set ENET_IRQHandler,Default_Handler
|
||||
|
||||
.weak ENET_WKUP_IRQHandler
|
||||
.thumb_set ENET_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_TX_IRQHandler
|
||||
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX0_IRQHandler
|
||||
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_EWMC_IRQHandler
|
||||
.thumb_set CAN1_EWMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBFS_IRQHandler
|
||||
.thumb_set USBFS_IRQHandler,Default_Handler
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
|
||||
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
|
||||
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
|
||||
define symbol __ICFEDIT_region_NVIC_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_NVIC_end__ = 0x2000014F;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000150;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF;
|
||||
/*-Sizes-*/
|
||||
/*Heap 1/4 of ram and stack 1/8*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x3000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x6000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block HEAP, block CSTACK };
|
||||
|
|
@ -1,526 +0,0 @@
|
|||
;/*!
|
||||
; \file startup_gd32f30x_cl.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed)
|
||||
;*/
|
||||
;
|
||||
;/*
|
||||
; Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without modification,
|
||||
;are permitted provided that the following conditions are met:
|
||||
;
|
||||
; 1. Redistributions of source code must retain the above copyright notice, this
|
||||
; list of conditions and the following disclaimer.
|
||||
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
; this list of conditions and the following disclaimer in the documentation
|
||||
; and/or other materials provided with the distribution.
|
||||
; 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
; may be used to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
;OF SUCH DAMAGE.
|
||||
;*/
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; top of stack
|
||||
DCD Reset_Handler ; Vector Number 1,Reset Handler
|
||||
|
||||
DCD NMI_Handler ; Vector Number 2,NMI Handler
|
||||
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
|
||||
DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
|
||||
DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; Vector Number 11,SVCall Handler
|
||||
DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
|
||||
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; 19:RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; 20:FMC
|
||||
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
|
||||
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10
|
||||
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD SPI0_IRQHandler ; 51:SPI0
|
||||
DCD SPI1_IRQHandler ; 52:SPI1
|
||||
DCD USART0_IRQHandler ; 53:USART0
|
||||
DCD USART1_IRQHandler ; 54:USART1
|
||||
DCD USART2_IRQHandler ; 55:USART2
|
||||
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13
|
||||
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||
DCD 0 ; 63:Reserved
|
||||
DCD EXMC_IRQHandler ; 64:EXMC
|
||||
DCD 0 ; 65:Reserved
|
||||
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||
DCD SPI2_IRQHandler ; 67:SPI2
|
||||
DCD UART3_IRQHandler ; 68:UART3
|
||||
DCD UART4_IRQHandler ; 69:UART4
|
||||
DCD TIMER5_IRQHandler ; 70:TIMER5
|
||||
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||
DCD ENET_IRQHandler ; 77:Ethernet
|
||||
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||
DCD USBFS_IRQHandler ; 83:USBFS
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDGT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDGT_IRQHandler
|
||||
B WWDGT_IRQHandler
|
||||
|
||||
PUBWEAK LVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LVD_IRQHandler
|
||||
B LVD_IRQHandler
|
||||
|
||||
PUBWEAK TAMPER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMPER_IRQHandler
|
||||
B TAMPER_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK RCU_CTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCU_CTC_IRQHandler
|
||||
B RCU_CTC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel0_IRQHandler
|
||||
B DMA0_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel1_IRQHandler
|
||||
B DMA0_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel2_IRQHandler
|
||||
B DMA0_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel3_IRQHandler
|
||||
B DMA0_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel4_IRQHandler
|
||||
B DMA0_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel5_IRQHandler
|
||||
B DMA0_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel6_IRQHandler
|
||||
B DMA0_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK ADC0_1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC0_1_IRQHandler
|
||||
B ADC0_1_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_TX_IRQHandler
|
||||
B CAN0_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_RX0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_RX0_IRQHandler
|
||||
B CAN0_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_RX1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_RX1_IRQHandler
|
||||
B CAN0_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_EWMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_EWMC_IRQHandler
|
||||
B CAN0_EWMC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI5_9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI5_9_IRQHandler
|
||||
B EXTI5_9_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_BRK_TIMER8_IRQHandler
|
||||
B TIMER0_BRK_TIMER8_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_UP_TIMER9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_UP_TIMER9_IRQHandler
|
||||
B TIMER0_UP_TIMER9_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
B TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_Channel_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_Channel_IRQHandler
|
||||
B TIMER0_Channel_IRQHandler
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER1_IRQHandler
|
||||
B TIMER1_IRQHandler
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER2_IRQHandler
|
||||
B TIMER2_IRQHandler
|
||||
|
||||
PUBWEAK TIMER3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER3_IRQHandler
|
||||
B TIMER3_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_EV_IRQHandler
|
||||
B I2C0_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_ER_IRQHandler
|
||||
B I2C0_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI0_IRQHandler
|
||||
B SPI0_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK USART0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART0_IRQHandler
|
||||
B USART0_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI10_15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI10_15_IRQHandler
|
||||
B EXTI10_15_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBFS_WKUP_IRQHandler
|
||||
B USBFS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_BRK_TIMER11_IRQHandler
|
||||
B TIMER7_BRK_TIMER11_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_UP_TIMER12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_UP_TIMER12_IRQHandler
|
||||
B TIMER7_UP_TIMER12_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
B TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_Channel_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_Channel_IRQHandler
|
||||
B TIMER7_Channel_IRQHandler
|
||||
|
||||
PUBWEAK EXMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXMC_IRQHandler
|
||||
B EXMC_IRQHandler
|
||||
|
||||
PUBWEAK TIMER4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER4_IRQHandler
|
||||
B TIMER4_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK UART3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART3_IRQHandler
|
||||
B UART3_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK TIMER5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER5_IRQHandler
|
||||
B TIMER5_IRQHandler
|
||||
|
||||
PUBWEAK TIMER6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER6_IRQHandler
|
||||
B TIMER6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel0_IRQHandler
|
||||
B DMA1_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK ENET_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ENET_IRQHandler
|
||||
B ENET_IRQHandler
|
||||
|
||||
PUBWEAK ENET_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ENET_WKUP_IRQHandler
|
||||
B ENET_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_TX_IRQHandler
|
||||
B CAN1_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_RX0_IRQHandler
|
||||
B CAN1_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_RX1_IRQHandler
|
||||
B CAN1_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_EWMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_EWMC_IRQHandler
|
||||
B CAN1_EWMC_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBFS_IRQHandler
|
||||
B USBFS_IRQHandler
|
||||
END
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* A generic CMSIS include header
|
||||
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc. All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_H
|
||||
#define MBED_CMSIS_H
|
||||
|
||||
#include "gd32f30x.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#endif /* MBED_CMSIS_H */
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
#define NVIC_NUM_VECTORS (16 + 68) /* ARM CORE:16 Vectors; MCU Peripherals:68 Vectors */
|
||||
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000
|
||||
|
||||
|
||||
#endif /* MBED_CMSIS_NVIC_H */
|
||||
|
|
@ -1,386 +0,0 @@
|
|||
/*!
|
||||
\file gd32f30x.h
|
||||
\brief general definitions for GD32F30x
|
||||
|
||||
\version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed)
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F30X_H
|
||||
#define GD32F30X_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* define GD32F30x */
|
||||
#if !defined (GD32F30X_HD) && !defined (GD32F30X_XD) && !defined (GD32F30X_CL)
|
||||
/* #define GD32F30X_HD */
|
||||
/* #define GD32F30X_XD */
|
||||
/* #define GD32F30X_CL */
|
||||
#endif /* define GD32F30x */
|
||||
|
||||
#if !defined (GD32F30X_HD) && !defined (GD32F30X_XD) && !defined (GD32F30X_CL)
|
||||
#error "Please select the target GD32F30x device in gd32f30x.h file"
|
||||
#endif /* undefine GD32F30x tip */
|
||||
|
||||
|
||||
/* define value of high speed crystal oscillator (HXTAL) in Hz */
|
||||
#if !defined HXTAL_VALUE
|
||||
#ifdef GD32F30X_CL
|
||||
#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */
|
||||
#else
|
||||
#define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 16M *!< value of the external oscillator in Hz*/
|
||||
#endif /* HXTAL_VALUE */
|
||||
#endif /* high speed crystal oscillator value */
|
||||
|
||||
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
|
||||
#if !defined (HXTAL_STARTUP_TIMEOUT)
|
||||
#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800)
|
||||
#endif /* high speed crystal oscillator startup timeout */
|
||||
|
||||
/* define value of internal 48MHz RC oscillator (IRC48M) in Hz */
|
||||
#if !defined (IRC48M_VALUE)
|
||||
#define IRC48M_VALUE ((uint32_t)48000000)
|
||||
#endif /* internal 48MHz RC oscillator value */
|
||||
|
||||
/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
|
||||
#if !defined (IRC8M_VALUE)
|
||||
#define IRC8M_VALUE ((uint32_t)8000000)
|
||||
#endif /* internal 8MHz RC oscillator value */
|
||||
|
||||
/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
|
||||
#if !defined (IRC8M_STARTUP_TIMEOUT)
|
||||
#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
|
||||
#endif /* internal 8MHz RC oscillator startup timeout */
|
||||
|
||||
/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
|
||||
#if !defined (IRC40K_VALUE)
|
||||
#define IRC40K_VALUE ((uint32_t)40000)
|
||||
#endif /* internal 40KHz RC oscillator value */
|
||||
|
||||
/* define value of low speed crystal oscillator (LXTAL)in Hz */
|
||||
#if !defined (LXTAL_VALUE)
|
||||
#define LXTAL_VALUE ((uint32_t)32768)
|
||||
#endif /* low speed crystal oscillator value */
|
||||
|
||||
/* GD32F30x firmware library version number V1.0 */
|
||||
#define __GD32F30x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __GD32F30x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
||||
#define __GD32F30x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __GD32F30x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __GD32F30x_STDPERIPH_VERSION ((__GD32F30x_STDPERIPH_VERSION_MAIN << 24)\
|
||||
|(__GD32F30x_STDPERIPH_VERSION_SUB1 << 16)\
|
||||
|(__GD32F30x_STDPERIPH_VERSION_SUB2 << 8)\
|
||||
|(__GD32F30x_STDPERIPH_VERSION_RC))
|
||||
|
||||
/* configuration of the Cortex-M4 processor and core peripherals */
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< GD32F30x do not provide MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< GD32F30x uses 4 bits for the priority levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
/* define interrupt number */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/* Cortex-M4 processor exceptions numbers */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV call interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 debug monitor interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M4 pend SV interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M4 system tick interrupt */
|
||||
/* interruput numbers */
|
||||
WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */
|
||||
LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
|
||||
TAMPER_IRQn = 2, /*!< tamper through EXTI line detect */
|
||||
RTC_IRQn = 3, /*!< RTC through EXTI line interrupt */
|
||||
FMC_IRQn = 4, /*!< FMC interrupt */
|
||||
RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */
|
||||
EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */
|
||||
EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */
|
||||
EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */
|
||||
EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */
|
||||
EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */
|
||||
DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 interrupt */
|
||||
DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 interrupt */
|
||||
DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */
|
||||
DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */
|
||||
DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */
|
||||
DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */
|
||||
DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */
|
||||
ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 interrupt */
|
||||
#ifdef GD32F30X_HD
|
||||
USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
|
||||
USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
|
||||
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
|
||||
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
|
||||
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
||||
TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */
|
||||
TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */
|
||||
TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */
|
||||
TIMER0_CC_IRQn = 27, /*!< TIMER0 capture compare interrupts */
|
||||
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
||||
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
||||
TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
|
||||
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
||||
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
||||
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
||||
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
||||
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
||||
SPI1_IRQn = 36, /*!< SPI1 interrupt */
|
||||
USART0_IRQn = 37, /*!< USART0 interrupt */
|
||||
USART1_IRQn = 38, /*!< USART1 interrupt */
|
||||
USART2_IRQn = 39, /*!< USART2 interrupt */
|
||||
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
||||
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
|
||||
USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */
|
||||
TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupts */
|
||||
TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupts */
|
||||
TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupts */
|
||||
TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */
|
||||
ADC2_IRQn = 47, /*!< ADC2 global interrupt */
|
||||
EXMC_IRQn = 48, /*!< EXMC global interrupt */
|
||||
SDIO_IRQn = 49, /*!< SDIO global interrupt */
|
||||
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
|
||||
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
|
||||
UART3_IRQn = 52, /*!< UART3 global interrupt */
|
||||
UART4_IRQn = 53, /*!< UART4 global interrupt */
|
||||
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
|
||||
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
|
||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
|
||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
|
||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
|
||||
DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */
|
||||
#endif /* GD32F30X_HD */
|
||||
|
||||
#ifdef GD32F30X_XD
|
||||
USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
|
||||
USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
|
||||
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
|
||||
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
|
||||
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
||||
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */
|
||||
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */
|
||||
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */
|
||||
TIMER0_CC_IRQn = 27, /*!< TIMER0 Capture Compare interrupts */
|
||||
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
||||
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
||||
TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
|
||||
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
||||
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
||||
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
||||
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
||||
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
||||
SPI1_IRQn = 36, /*!< SPI1 interrupt */
|
||||
USART0_IRQn = 37, /*!< USART0 interrupt */
|
||||
USART1_IRQn = 38, /*!< USART1 interrupt */
|
||||
USART2_IRQn = 39, /*!< USART2 interrupt */
|
||||
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
||||
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
|
||||
USBD_WKUP_IRQn = 42, /*!< USBD wakeup interrupt */
|
||||
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */
|
||||
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */
|
||||
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */
|
||||
TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */
|
||||
ADC2_IRQn = 47, /*!< ADC2 global interrupt */
|
||||
EXMC_IRQn = 48, /*!< EXMC global interrupt */
|
||||
SDIO_IRQn = 49, /*!< SDIO global interrupt */
|
||||
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
|
||||
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
|
||||
UART3_IRQn = 52, /*!< UART3 global interrupt */
|
||||
UART4_IRQn = 53, /*!< UART4 global interrupt */
|
||||
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
|
||||
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
|
||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
|
||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
|
||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
|
||||
DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global interrupt */
|
||||
#endif /* GD32F30X_XD */
|
||||
|
||||
#ifdef GD32F30X_CL
|
||||
CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
|
||||
CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
|
||||
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
|
||||
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
|
||||
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
||||
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */
|
||||
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */
|
||||
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */
|
||||
TIMER0_CC_IRQn = 27, /*!< TIMER0 capture compare interrupts */
|
||||
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
||||
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
||||
TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
|
||||
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
||||
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
||||
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
||||
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
||||
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
||||
SPI1_IRQn = 36, /*!< SPI1 interrupt */
|
||||
USART0_IRQn = 37, /*!< USART0 interrupt */
|
||||
USART1_IRQn = 38, /*!< USART1 interrupt */
|
||||
USART2_IRQn = 39, /*!< USART2 interrupt */
|
||||
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
||||
RTC_ALARM_IRQn = 41, /*!< RTC alarm interrupt */
|
||||
USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */
|
||||
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */
|
||||
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */
|
||||
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */
|
||||
TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */
|
||||
EXMC_IRQn = 48, /*!< EXMC global interrupt */
|
||||
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
|
||||
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
|
||||
UART3_IRQn = 52, /*!< UART3 global interrupt */
|
||||
UART4_IRQn = 53, /*!< UART4 global interrupt */
|
||||
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
|
||||
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
|
||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
|
||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
|
||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
|
||||
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */
|
||||
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */
|
||||
ENET_IRQn = 61, /*!< ENET global interrupt */
|
||||
ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */
|
||||
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
|
||||
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
|
||||
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
|
||||
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
|
||||
USBFS_IRQn = 67, /*!< USBFS global interrupt */
|
||||
#endif /* GD32F30X_CL */
|
||||
|
||||
} IRQn_Type;
|
||||
|
||||
/* includes */
|
||||
#include "core_cm4.h"
|
||||
#include "system_gd32f30x.h"
|
||||
#include <stdint.h>
|
||||
|
||||
#define GD_MBED_USED
|
||||
|
||||
#ifdef GD_MBED_USED
|
||||
typedef enum
|
||||
{
|
||||
GD_OK = 0x00U,
|
||||
GD_ERROR = 0x01U,
|
||||
GD_BUSY = 0x02U,
|
||||
GD_TIMEOUT = 0x03U
|
||||
}gd_status_enum;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
OP_STATE_RESET = 0x00U,
|
||||
OP_STATE_READY = 0x01U,
|
||||
OP_STATE_BUSY = 0x02U,
|
||||
OP_STATE_TIMEOUT = 0x03U,
|
||||
OP_STATE_ERROR = 0x04U,
|
||||
OP_STATE_ABORT = 0x05U,
|
||||
OP_STATE_LISTEN = 0x06U,
|
||||
|
||||
OP_STATE_BUSY_TX = 0x21U, /* (OP_STATE_BUSY << 4) + 1 */
|
||||
OP_STATE_BUSY_RX = 0x22U, /* (OP_STATE_BUSY << 4) + 2 */
|
||||
|
||||
OP_STATE_BUSY_TX_LISTEN = 0x61U, /* (OP_STATE_LISTEN << 4) + 1 */
|
||||
OP_STATE_BUSY_RX_LISTEN = 0x62U, /* (OP_STATE_LISTEN << 4) + 2 */
|
||||
|
||||
OP_STATE_BUTT
|
||||
}operation_state_enum;
|
||||
#endif
|
||||
|
||||
/* enum definitions */
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
|
||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
|
||||
|
||||
/* bit operations */
|
||||
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
|
||||
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
|
||||
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
|
||||
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
|
||||
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
|
||||
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
|
||||
|
||||
/* main flash and SRAM memory map */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
|
||||
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
|
||||
#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
|
||||
#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
|
||||
|
||||
/* peripheral memory map */
|
||||
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
|
||||
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
|
||||
#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */
|
||||
#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */
|
||||
|
||||
/* advanced peripheral bus 1 memory map */
|
||||
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
|
||||
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
|
||||
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
|
||||
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
|
||||
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
|
||||
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
|
||||
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
|
||||
#define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */
|
||||
#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
|
||||
#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */
|
||||
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
|
||||
#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
|
||||
#define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address */
|
||||
|
||||
/* advanced peripheral bus 2 memory map */
|
||||
#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */
|
||||
#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
|
||||
#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */
|
||||
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
|
||||
|
||||
/* advanced high performance bus 1 memory map */
|
||||
#define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address */
|
||||
#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */
|
||||
#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */
|
||||
#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */
|
||||
#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */
|
||||
#define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */
|
||||
#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */
|
||||
|
||||
/* define marco USE_STDPERIPH_DRIVER */
|
||||
#if !defined USE_STDPERIPH_DRIVER
|
||||
#define USE_STDPERIPH_DRIVER
|
||||
#endif
|
||||
#ifdef USE_STDPERIPH_DRIVER
|
||||
#include "gd32f30x_libopt.h"
|
||||
#endif /* USE_STDPERIPH_DRIVER */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -1,65 +0,0 @@
|
|||
/*!
|
||||
\file gd32f30x_libopt.h
|
||||
\brief library optional for gd32f30x
|
||||
|
||||
\version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed)
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2018, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F30X_LIBOPT_H
|
||||
#define GD32F30X_LIBOPT_H
|
||||
|
||||
#include "gd32f30x_rcu.h"
|
||||
#include "gd32f30x_adc.h"
|
||||
#include "gd32f30x_can.h"
|
||||
#include "gd32f30x_crc.h"
|
||||
#include "gd32f30x_ctc.h"
|
||||
#include "gd32f30x_dac.h"
|
||||
#include "gd32f30x_dbg.h"
|
||||
#include "gd32f30x_dma.h"
|
||||
#include "gd32f30x_exti.h"
|
||||
#include "gd32f30x_fmc.h"
|
||||
#include "gd32f30x_fwdgt.h"
|
||||
#include "gd32f30x_gpio.h"
|
||||
#include "gd32f30x_i2c.h"
|
||||
#include "gd32f30x_pmu.h"
|
||||
#include "gd32f30x_bkp.h"
|
||||
#include "gd32f30x_rtc.h"
|
||||
#include "gd32f30x_sdio.h"
|
||||
#include "gd32f30x_spi.h"
|
||||
#include "gd32f30x_timer.h"
|
||||
#include "gd32f30x_usart.h"
|
||||
#include "gd32f30x_wwdgt.h"
|
||||
#include "gd32f30x_misc.h"
|
||||
#include "gd32f30x_enet.h"
|
||||
#include "gd32f30x_exmc.h"
|
||||
|
||||
#endif /* GD32F30X_LIBOPT_H */
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2018 GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef __HAL_TICK_H
|
||||
#define __HAL_TICK_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "gd32f30x.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#define TICKER_TIMER TIMER2
|
||||
#define TICKER_TIMER_IRQ TIMER2_IRQn
|
||||
#define TICKER_TIMER_RCU_CLOCK_ENABLE rcu_periph_clock_enable(RCU_TIMER2);
|
||||
#define TICKER_TIMER_DEBUG_STOP dbg_periph_enable(DBG_TIMER2_HOLD);
|
||||
|
||||
#define TICKER_TIMER_RESET_ENABLE rcu_periph_reset_enable(RCU_TIMER2RST)
|
||||
#define TICKER_TIMER_RESET_DISABLE rcu_periph_reset_disable(RCU_TIMER2RST)
|
||||
|
||||
/* 16 for 16-bit timer, 32 for 32-bit timer */
|
||||
#define TICKER_TIMER_WIDTH_BIT 16
|
||||
|
||||
/* 0 for CK_APB1, 1 for CK_APB2 */
|
||||
#define TICKER_TIMER_CKAPB 1
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HAL_TICK_H */
|
||||
|
|
@ -1,987 +0,0 @@
|
|||
/*!
|
||||
\file system_gd32f30x.c
|
||||
\brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for
|
||||
GD32F30x Device Series
|
||||
*/
|
||||
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
#include "gd32f30x.h"
|
||||
|
||||
/* system frequency define */
|
||||
#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
|
||||
#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
|
||||
#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */
|
||||
|
||||
/* select a system clock by uncommenting the following line */
|
||||
/* use IRC8M */
|
||||
//#define __SYSTEM_CLOCK_IRC8M (uint32_t)(__IRC8M)
|
||||
//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000)
|
||||
//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000)
|
||||
//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000)
|
||||
//#define __SYSTEM_CLOCK_120M_PLL_IRC8M (uint32_t)(120000000)
|
||||
|
||||
/* use HXTAL(XD series CK_HXTAL = 8M, CL series CK_HXTAL = 25M) */
|
||||
//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL)
|
||||
//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000)
|
||||
//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000)
|
||||
//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000)
|
||||
#define __SYSTEM_CLOCK_120M_PLL_HXTAL (uint32_t)(120000000)
|
||||
|
||||
#define SEL_IRC8M 0x00U
|
||||
#define SEL_HXTAL 0x01U
|
||||
#define SEL_PLL 0x02U
|
||||
|
||||
/* set the system clock frequency and declare the system clock configuration function */
|
||||
#ifdef __SYSTEM_CLOCK_IRC8M
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC8M;
|
||||
static void system_clock_8m_irc8m(void);
|
||||
#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M;
|
||||
static void system_clock_48m_irc8m(void);
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M;
|
||||
static void system_clock_72m_irc8m(void);
|
||||
#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M;
|
||||
static void system_clock_108m_irc8m(void);
|
||||
#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_IRC8M;
|
||||
static void system_clock_120m_irc8m(void);
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_HXTAL)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL;
|
||||
static void system_clock_hxtal(void);
|
||||
#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL;
|
||||
static void system_clock_48m_hxtal(void);
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
|
||||
static void system_clock_72m_hxtal(void);
|
||||
#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL;
|
||||
static void system_clock_108m_hxtal(void);
|
||||
#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_HXTAL;
|
||||
static void system_clock_120m_hxtal(void);
|
||||
#endif /* __SYSTEM_CLOCK_IRC8M */
|
||||
|
||||
/* configure the system clock */
|
||||
static void system_clock_config(void);
|
||||
|
||||
/*!
|
||||
\brief setup the microcontroller system, initialize the system
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
/* FPU settings */
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
/* reset the RCU clock configuration to the default reset state */
|
||||
/* Set IRC8MEN bit */
|
||||
RCU_CTL |= RCU_CTL_IRC8MEN;
|
||||
|
||||
/* Reset CFG0 and CFG1 registers */
|
||||
RCU_CFG0 = 0x00000000U;
|
||||
RCU_CFG1 = 0x00000000U;
|
||||
|
||||
#if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
|
||||
/* reset HXTALEN, CKMEN and PLLEN bits */
|
||||
RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
|
||||
/* disable all interrupts */
|
||||
RCU_INT = 0x009f0000U;
|
||||
#elif defined(GD32F30X_CL)
|
||||
/* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */
|
||||
RCU_CTL &= ~(RCU_CTL_PLLEN |RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
|
||||
/* disable all interrupts */
|
||||
RCU_INT = 0x00ff0000U;
|
||||
#endif
|
||||
|
||||
/* reset HXTALBPS bit */
|
||||
RCU_CTL &= ~(RCU_CTL_HXTALBPS);
|
||||
|
||||
/* configure the system clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */
|
||||
system_clock_config();
|
||||
}
|
||||
/*!
|
||||
\brief configure the system clock
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_config(void)
|
||||
{
|
||||
#ifdef __SYSTEM_CLOCK_IRC8M
|
||||
system_clock_8m_irc8m();
|
||||
#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M)
|
||||
system_clock_48m_irc8m();
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
|
||||
system_clock_72m_irc8m();
|
||||
#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
|
||||
system_clock_108m_irc8m();
|
||||
#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M)
|
||||
system_clock_120m_irc8m();
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_HXTAL)
|
||||
system_clock_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
|
||||
system_clock_48m_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
|
||||
system_clock_72m_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
|
||||
system_clock_108m_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL)
|
||||
system_clock_120m_hxtal();
|
||||
#endif /* __SYSTEM_CLOCK_IRC8M */
|
||||
}
|
||||
|
||||
#ifdef __SYSTEM_CLOCK_IRC8M
|
||||
/*!
|
||||
\brief configure the system clock to 8M by IRC8M
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_8m_irc8m(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable IRC8M */
|
||||
RCU_CTL |= RCU_CTL_IRC8MEN;
|
||||
|
||||
/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
|
||||
}
|
||||
while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
/* select IRC8M as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_IRC8M;
|
||||
|
||||
/* wait until IRC8M is selected as system clock */
|
||||
while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M)
|
||||
/*!
|
||||
\brief configure the system clock to 48M by PLL which selects IRC8M as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_48m_irc8m(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable IRC8M */
|
||||
RCU_CTL |= RCU_CTL_IRC8MEN;
|
||||
|
||||
/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
|
||||
}
|
||||
while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
/* LDO output voltage high mode */
|
||||
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||
PMU_CTL |= PMU_CTL_LDOVS;
|
||||
|
||||
/* IRC8M is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
/* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
||||
RCU_CFG0 |= RCU_PLL_MUL12;
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* enable the high-drive to extend the clock frequency to 120 MHz */
|
||||
PMU_CTL |= PMU_CTL_HDEN;
|
||||
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||
}
|
||||
|
||||
/* select the high-drive mode */
|
||||
PMU_CTL |= PMU_CTL_HDS;
|
||||
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
|
||||
/*!
|
||||
\brief configure the system clock to 72M by PLL which selects IRC8M as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_72m_irc8m(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable IRC8M */
|
||||
RCU_CTL |= RCU_CTL_IRC8MEN;
|
||||
|
||||
/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
|
||||
}while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
/* LDO output voltage high mode */
|
||||
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||
PMU_CTL |= PMU_CTL_LDOVS;
|
||||
|
||||
/* IRC8M is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
/* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
||||
RCU_CFG0 |= RCU_PLL_MUL18;
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* enable the high-drive to extend the clock frequency to 120 MHz */
|
||||
PMU_CTL |= PMU_CTL_HDEN;
|
||||
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||
}
|
||||
|
||||
/* select the high-drive mode */
|
||||
PMU_CTL |= PMU_CTL_HDS;
|
||||
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
|
||||
/*!
|
||||
\brief configure the system clock to 108M by PLL which selects IRC8M as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_108m_irc8m(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable IRC8M */
|
||||
RCU_CTL |= RCU_CTL_IRC8MEN;
|
||||
|
||||
/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
|
||||
}while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
/* LDO output voltage high mode */
|
||||
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||
PMU_CTL |= PMU_CTL_LDOVS;
|
||||
|
||||
/* IRC8M is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
/* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
||||
RCU_CFG0 |= RCU_PLL_MUL27;
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* enable the high-drive to extend the clock frequency to 120 MHz */
|
||||
PMU_CTL |= PMU_CTL_HDEN;
|
||||
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||
}
|
||||
|
||||
/* select the high-drive mode */
|
||||
PMU_CTL |= PMU_CTL_HDS;
|
||||
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M)
|
||||
/*!
|
||||
\brief configure the system clock to 120M by PLL which selects IRC8M as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_120m_irc8m(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable IRC8M */
|
||||
RCU_CTL |= RCU_CTL_IRC8MEN;
|
||||
|
||||
/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
|
||||
}while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
/* LDO output voltage high mode */
|
||||
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||
PMU_CTL |= PMU_CTL_LDOVS;
|
||||
|
||||
/* IRC8M is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
/* CK_PLL = (CK_IRC8M/2) * 30 = 120 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
||||
RCU_CFG0 |= RCU_PLL_MUL30;
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* enable the high-drive to extend the clock frequency to 120 MHz */
|
||||
PMU_CTL |= PMU_CTL_HDEN;
|
||||
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||
}
|
||||
|
||||
/* select the high-drive mode */
|
||||
PMU_CTL |= PMU_CTL_HDS;
|
||||
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to HXTAL
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
/* select HXTAL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
|
||||
|
||||
/* wait until HXTAL is selected as system clock */
|
||||
while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 48M by PLL which selects HXTAL(8M) as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_48m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||
PMU_CTL |= PMU_CTL_LDOVS;
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
#if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
|
||||
/* select HXTAL/2 as clock source */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
|
||||
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);
|
||||
|
||||
/* CK_PLL = (CK_HXTAL/2) * 12 = 48 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
||||
RCU_CFG0 |= RCU_PLL_MUL12;
|
||||
|
||||
#elif defined(GD32F30X_CL)
|
||||
/* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
||||
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL12);
|
||||
|
||||
/* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
|
||||
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
|
||||
RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
|
||||
|
||||
/* enable PLL1 */
|
||||
RCU_CTL |= RCU_CTL_PLL1EN;
|
||||
/* wait till PLL1 is ready */
|
||||
while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
|
||||
}
|
||||
#endif /* GD32F30X_HD and GD32F30X_XD */
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* enable the high-drive to extend the clock frequency to 120 MHz */
|
||||
PMU_CTL |= PMU_CTL_HDEN;
|
||||
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||
}
|
||||
|
||||
/* select the high-drive mode */
|
||||
PMU_CTL |= PMU_CTL_HDS;
|
||||
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||||
}
|
||||
}
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 72M by PLL which selects HXTAL(8M) as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_72m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||
PMU_CTL |= PMU_CTL_LDOVS;
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
#if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
|
||||
/* select HXTAL/2 as clock source */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
|
||||
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);
|
||||
|
||||
/* CK_PLL = (CK_HXTAL/2) * 18 = 72 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
||||
RCU_CFG0 |= RCU_PLL_MUL18;
|
||||
|
||||
#elif defined(GD32F30X_CL)
|
||||
/* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
||||
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL18);
|
||||
|
||||
/* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
|
||||
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
|
||||
RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
|
||||
|
||||
/* enable PLL1 */
|
||||
RCU_CTL |= RCU_CTL_PLL1EN;
|
||||
/* wait till PLL1 is ready */
|
||||
while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
|
||||
}
|
||||
#endif /* GD32F30X_HD and GD32F30X_XD */
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* enable the high-drive to extend the clock frequency to 120 MHz */
|
||||
PMU_CTL |= PMU_CTL_HDEN;
|
||||
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||
}
|
||||
|
||||
/* select the high-drive mode */
|
||||
PMU_CTL |= PMU_CTL_HDS;
|
||||
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 108M by PLL which selects HXTAL(8M) as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_108m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||
PMU_CTL |= PMU_CTL_LDOVS;
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
#if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
|
||||
/* select HXTAL/2 as clock source */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
|
||||
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);
|
||||
|
||||
/* CK_PLL = (CK_HXTAL/2) * 27 = 108 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
||||
RCU_CFG0 |= RCU_PLL_MUL27;
|
||||
|
||||
#elif defined(GD32F30X_CL)
|
||||
/* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
||||
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL27);
|
||||
|
||||
/* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
|
||||
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
|
||||
RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
|
||||
|
||||
/* enable PLL1 */
|
||||
RCU_CTL |= RCU_CTL_PLL1EN;
|
||||
/* wait till PLL1 is ready */
|
||||
while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
|
||||
}
|
||||
#endif /* GD32F30X_HD and GD32F30X_XD */
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* enable the high-drive to extend the clock frequency to 120 MHz */
|
||||
PMU_CTL |= PMU_CTL_HDEN;
|
||||
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||
}
|
||||
|
||||
/* select the high-drive mode */
|
||||
PMU_CTL |= PMU_CTL_HDS;
|
||||
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_120m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||
PMU_CTL |= PMU_CTL_LDOVS;
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
#if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
|
||||
/* select HXTAL/2 as clock source */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
|
||||
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);
|
||||
|
||||
/* CK_PLL = (CK_HXTAL/2) * 30 = 120 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
||||
RCU_CFG0 |= RCU_PLL_MUL30;
|
||||
|
||||
#elif defined(GD32F30X_CL)
|
||||
/* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
||||
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30);
|
||||
|
||||
/* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
|
||||
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
|
||||
RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
|
||||
|
||||
/* enable PLL1 */
|
||||
RCU_CTL |= RCU_CTL_PLL1EN;
|
||||
/* wait till PLL1 is ready */
|
||||
while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){
|
||||
}
|
||||
#endif /* GD32F30X_HD and GD32F30X_XD */
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* enable the high-drive to extend the clock frequency to 120 MHz */
|
||||
PMU_CTL |= PMU_CTL_HDEN;
|
||||
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||
}
|
||||
|
||||
/* select the high-drive mode */
|
||||
PMU_CTL |= PMU_CTL_HDS;
|
||||
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||||
}
|
||||
}
|
||||
#endif /* __SYSTEM_CLOCK_IRC8M */
|
||||
|
||||
/*!
|
||||
\brief update the SystemCoreClock with current core clock retrieved from cpu registers
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t sws;
|
||||
uint32_t pllsel, pllpresel, predv0sel, pllmf,ck_src;
|
||||
#ifdef GD32F30X_CL
|
||||
uint32_t predv0, predv1, pll1mf;
|
||||
#endif /* GD32F30X_CL */
|
||||
|
||||
sws = GET_BITS(RCU_CFG0, 2, 3);
|
||||
switch(sws){
|
||||
/* IRC8M is selected as CK_SYS */
|
||||
case SEL_IRC8M:
|
||||
SystemCoreClock = IRC8M_VALUE;
|
||||
break;
|
||||
/* HXTAL is selected as CK_SYS */
|
||||
case SEL_HXTAL:
|
||||
SystemCoreClock = HXTAL_VALUE;
|
||||
break;
|
||||
/* PLL is selected as CK_SYS */
|
||||
case SEL_PLL:
|
||||
/* PLL clock source selection, HXTAL, IRC48M or IRC8M/2 */
|
||||
pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL);
|
||||
|
||||
if (RCU_PLLSRC_HXTAL_IRC48M == pllsel) {
|
||||
/* PLL clock source is HXTAL or IRC48M */
|
||||
pllpresel = (RCU_CFG1 & RCU_CFG1_PLLPRESEL);
|
||||
|
||||
if(RCU_PLLPRESRC_HXTAL == pllpresel){
|
||||
/* PLL clock source is HXTAL */
|
||||
ck_src = HXTAL_VALUE;
|
||||
}else{
|
||||
/* PLL clock source is IRC48 */
|
||||
ck_src = IRC48M_VALUE;
|
||||
}
|
||||
|
||||
#if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
|
||||
predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0);
|
||||
/* PREDV0 input source clock divided by 2 */
|
||||
if(RCU_CFG0_PREDV0 == predv0sel){
|
||||
ck_src = HXTAL_VALUE/2U;
|
||||
}
|
||||
#elif defined(GD32F30X_CL)
|
||||
predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL);
|
||||
/* source clock use PLL1 */
|
||||
if(RCU_PREDV0SRC_CKPLL1 == predv0sel){
|
||||
predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U;
|
||||
pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U;
|
||||
if(17U == pll1mf){
|
||||
pll1mf = 20U;
|
||||
}
|
||||
ck_src = (ck_src/predv1)*pll1mf;
|
||||
}
|
||||
predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U;
|
||||
ck_src /= predv0;
|
||||
#endif /* GD32F30X_HD and GD32F30X_XD */
|
||||
}else{
|
||||
/* PLL clock source is IRC8M/2 */
|
||||
ck_src = IRC8M_VALUE/2U;
|
||||
}
|
||||
|
||||
/* PLL multiplication factor */
|
||||
pllmf = GET_BITS(RCU_CFG0, 18, 21);
|
||||
|
||||
if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){
|
||||
pllmf |= 0x10U;
|
||||
}
|
||||
if((RCU_CFG0 & RCU_CFG0_PLLMF_5)){
|
||||
pllmf |= 0x20U;
|
||||
}
|
||||
|
||||
if( pllmf >= 15U){
|
||||
pllmf += 1U;
|
||||
}else{
|
||||
pllmf += 2U;
|
||||
}
|
||||
if(pllmf > 61U){
|
||||
pllmf = 63U;
|
||||
}
|
||||
SystemCoreClock = ck_src*pllmf;
|
||||
#ifdef GD32F30X_CL
|
||||
if(15U == pllmf){
|
||||
SystemCoreClock = ck_src*6U + ck_src/2U;
|
||||
}
|
||||
#endif /* GD32F30X_CL */
|
||||
|
||||
break;
|
||||
/* IRC8M is selected as CK_SYS */
|
||||
default:
|
||||
SystemCoreClock = IRC8M_VALUE;
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -1,58 +0,0 @@
|
|||
/*!
|
||||
\file system_gd32f30x.h
|
||||
\brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for
|
||||
GD32F30x Device Series
|
||||
*/
|
||||
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
#ifndef SYSTEM_GD32F30X_H
|
||||
#define SYSTEM_GD32F30X_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* system clock frequency (core clock) */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/* function declarations */
|
||||
/* initialize the system and update the SystemCoreClock variable */
|
||||
extern void SystemInit (void);
|
||||
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_GD32F30X_H */
|
||||
|
|
@ -89,7 +89,7 @@ void analogin_init(analogin_t *obj, PinName pin)
|
|||
adc_channel_length_config(obj->adc, ADC_REGULAR_CHANNEL, 1);
|
||||
adc_special_function_config(obj->adc, ADC_SCAN_MODE, DISABLE);
|
||||
adc_special_function_config(obj->adc, ADC_CONTINUOUS_MODE, DISABLE);
|
||||
adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE);
|
||||
adc_external_trigger_config(obj->adc, ADC_REGULAR_CHANNEL, ENABLE);
|
||||
adc_external_trigger_source_config(obj->adc, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_REGULAR_NONE);
|
||||
|
||||
/* ADC enable */
|
||||
|
|
|
|||
|
|
@ -192,4 +192,14 @@ uint32_t flash_get_size(const flash_t *obj)
|
|||
return FLASH_SIZE;
|
||||
}
|
||||
|
||||
/** Get the flash erase value
|
||||
*
|
||||
* @param obj The flash object
|
||||
* @return The flash erase value
|
||||
*/
|
||||
uint8_t flash_get_erase_value(const flash_t *obj)
|
||||
{
|
||||
return 0xFF;
|
||||
}
|
||||
|
||||
#endif /* DEVICE_FLASH */
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
int mbed_sdk_inited = 0;
|
||||
|
||||
/*!
|
||||
\brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source
|
||||
\brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
|
|
@ -34,7 +34,7 @@ extern void ticker_32bits_timer_init(void);
|
|||
#endif
|
||||
|
||||
/*!
|
||||
\brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source
|
||||
\brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
|
|
|
|||
|
|
@ -177,7 +177,7 @@ void serial_baud(serial_t *obj, int baudrate)
|
|||
struct serial_s *p_obj = GET_SERIAL_S(obj);
|
||||
|
||||
/* store the UEN flag */
|
||||
uen_flag = USART_CTL0(USART0) & USART_CTL0_UEN;
|
||||
uen_flag = USART_CTL0(p_obj->uart) & USART_CTL0_UEN;
|
||||
|
||||
/* disable the USART clock first */
|
||||
usart_disable(p_obj->uart);
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ extern void ticker_timer_data_restore(void);
|
|||
extern int serial_busy_state_check(void);
|
||||
|
||||
/*!
|
||||
\brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source
|
||||
\brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
|
|
|
|||
|
|
@ -29,6 +29,22 @@
|
|||
|
||||
#endif
|
||||
|
||||
#if defined(TARGET_GD32E103VB)
|
||||
|
||||
#ifndef INITIAL_SP
|
||||
#define INITIAL_SP (0x20008000UL)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(TARGET_GD32F450ZI)
|
||||
|
||||
#ifndef INITIAL_SP
|
||||
#define INITIAL_SP (0x20070000UL)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(__GNUC__) && !defined(__CC_ARM) && !defined(__ARMCC_VERSION) && defined(TWO_RAM_REGIONS))
|
||||
extern uint32_t __StackLimit[];
|
||||
extern uint32_t __StackTop[];
|
||||
|
|
|
|||
Loading…
Reference in New Issue