From 35a4ba5c4eb3f9af2cb8be1a037eaa50d0eb59e6 Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Mon, 27 Apr 2015 19:31:00 -0700 Subject: [PATCH] * Silence bunch of compiler warnings on Silicon Labs platforms * Remove "ARM" as compiler for Silicon Labs' CM0 platforms * Define LED3 and LED4 on Silicon Labs platforms --- .../TOOLCHAIN_ARM_STD/startup_efm32gg.s | 10 - .../TOOLCHAIN_ARM_MICRO/startup_efm32hg.s | 19 -- .../TOOLCHAIN_ARM_STD/efm32hg.sct | 15 -- .../TOOLCHAIN_ARM_STD/startup_efm32hg.s | 221 ------------------ .../TARGET_EFM32HG_STK3400/arm_math.h | 2 +- .../TARGET_EFM32HG_STK3400/efm32hg322f64.h | 1 - .../TOOLCHAIN_ARM_STD/efm32zg.sct | 15 -- .../TOOLCHAIN_ARM_STD/startup_efm32zg.s | 193 --------------- .../TARGET_EFM32ZG_STK3200/arm_math.h | 2 +- .../TARGET_EFM32ZG_STK3200/efm32zg222f32.h | 1 - .../TARGET_EFM32GG_STK3700/PinNames.h | 2 + .../TARGET_EFM32HG_STK3400/PinNames.h | 2 + .../TARGET_EFM32LG_STK3600/PinNames.h | 2 + .../TARGET_EFM32WG_STK3800/PinNames.h | 2 + .../TARGET_EFM32ZG_STK3200/PinNames.h | 2 + .../TARGET_EFM32/clocking.h | 2 +- .../TARGET_EFM32/i2c_api.c | 8 +- .../TARGET_EFM32/serial_api.c | 32 ++- .../TARGET_EFM32/spi_api.c | 2 +- workspace_tools/targets.py | 8 +- 20 files changed, 46 insertions(+), 495 deletions(-) delete mode 100644 libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_STD/efm32hg.sct delete mode 100644 libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_STD/startup_efm32hg.s delete mode 100644 libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_ARM_STD/efm32zg.sct delete mode 100644 libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_ARM_STD/startup_efm32zg.s diff --git a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_STD/startup_efm32gg.s b/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_STD/startup_efm32gg.s index 83c9b90f24..a39a3fa04b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_STD/startup_efm32gg.s +++ b/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_STD/startup_efm32gg.s @@ -272,14 +272,6 @@ EMU_IRQHandler ; User Initial Stack & Heap - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - IMPORT __use_two_region_memory EXPORT __user_initial_stackheap @@ -293,6 +285,4 @@ __user_initial_stackheap PROC ALIGN - ENDIF - END diff --git a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_MICRO/startup_efm32hg.s b/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_MICRO/startup_efm32hg.s index 111ef5a989..36f966a9a0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_MICRO/startup_efm32hg.s +++ b/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_MICRO/startup_efm32hg.s @@ -195,27 +195,8 @@ TIMER2_IRQHandler ; User Initial Stack & Heap - IF :DEF:__MICROLIB - EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - END diff --git a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_STD/efm32hg.sct b/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_STD/efm32hg.sct deleted file mode 100644 index 63ebda1bde..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_STD/efm32hg.sct +++ /dev/null @@ -1,15 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x00000000 0x00010000 { ; load region size_region - ER_IROM1 0x00000000 0x00010000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000080 0x00001F80 { ; RW data - .ANY (+RW +ZI) - } -} - diff --git a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_STD/startup_efm32hg.s b/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_STD/startup_efm32hg.s deleted file mode 100644 index 111ef5a989..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_STD/startup_efm32hg.s +++ /dev/null @@ -1,221 +0,0 @@ -;/**************************************************************************//** -; * @file startup_efm32hg.s -; * @brief CMSIS Core Device Startup File for -; * Silicon Labs EFM32HG Device Series -; * @version 3.20.12 -; * @date 03. February 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x0 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY, ALIGN=8 - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - - DCD DMA_IRQHandler ; 0: DMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt - DCD ACMP0_IRQHandler ; 3: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 4: ADC0 Interrupt - DCD I2C0_IRQHandler ; 5: I2C0 Interrupt - DCD GPIO_ODD_IRQHandler ; 6: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 7: TIMER1 Interrupt - DCD USART1_RX_IRQHandler ; 8: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 9: USART1_TX Interrupt - DCD LEUART0_IRQHandler ; 10: LEUART0 Interrupt - DCD PCNT0_IRQHandler ; 11: PCNT0 Interrupt - DCD RTC_IRQHandler ; 12: RTC Interrupt - DCD CMU_IRQHandler ; 13: CMU Interrupt - DCD VCMP_IRQHandler ; 14: VCMP Interrupt - DCD MSC_IRQHandler ; 15: MSC Interrupt - DCD AES_IRQHandler ; 16: AES Interrupt - DCD USART0_RX_IRQHandler ; 17: USART0_RX Interrupt - DCD USART0_TX_IRQHandler ; 18: USART0_TX Interrupt - DCD USB_IRQHandler ; 19: USB Interrupt - DCD TIMER2_IRQHandler ; 20: TIMER2 Interrupt - -__Vectors_End -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT DMA_IRQHandler [WEAK] - EXPORT GPIO_EVEN_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT ACMP0_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT GPIO_ODD_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT USART1_RX_IRQHandler [WEAK] - EXPORT USART1_TX_IRQHandler [WEAK] - EXPORT LEUART0_IRQHandler [WEAK] - EXPORT PCNT0_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT CMU_IRQHandler [WEAK] - EXPORT VCMP_IRQHandler [WEAK] - EXPORT MSC_IRQHandler [WEAK] - EXPORT AES_IRQHandler [WEAK] - EXPORT USART0_RX_IRQHandler [WEAK] - EXPORT USART0_TX_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - - -DMA_IRQHandler -GPIO_EVEN_IRQHandler -TIMER0_IRQHandler -ACMP0_IRQHandler -ADC0_IRQHandler -I2C0_IRQHandler -GPIO_ODD_IRQHandler -TIMER1_IRQHandler -USART1_RX_IRQHandler -USART1_TX_IRQHandler -LEUART0_IRQHandler -PCNT0_IRQHandler -RTC_IRQHandler -CMU_IRQHandler -VCMP_IRQHandler -MSC_IRQHandler -AES_IRQHandler -USART0_RX_IRQHandler -USART0_TX_IRQHandler -USB_IRQHandler -TIMER2_IRQHandler - B . - ENDP - - ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/arm_math.h b/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/arm_math.h index 65304c127d..741fce75e7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/arm_math.h +++ b/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/arm_math.h @@ -485,7 +485,7 @@ extern "C" #define __CLZ __clz #endif -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) && !defined (__CC_ARM) static __INLINE uint32_t __CLZ( q31_t data); diff --git a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg322f64.h b/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg322f64.h index 5e8349002f..9960c988f2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg322f64.h +++ b/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg322f64.h @@ -224,7 +224,6 @@ typedef enum IRQn /** @} End of group EFM32HG322F64_Part */ -#define ARM_MATH_CM0PLUS #include "arm_math.h" /* To get __CLZ definitions etc. */ #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ #include "system_efm32hg.h" /* System Header */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_ARM_STD/efm32zg.sct b/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_ARM_STD/efm32zg.sct deleted file mode 100644 index ba4678a154..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_ARM_STD/efm32zg.sct +++ /dev/null @@ -1,15 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x00000000 0x00008000 { ; load region size_region - ER_IROM1 0x00000000 0x00008000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000080 0x00000F80 { ; RW data - .ANY (+RW +ZI) - } -} - diff --git a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_ARM_STD/startup_efm32zg.s b/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_ARM_STD/startup_efm32zg.s deleted file mode 100644 index ede95180f5..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_ARM_STD/startup_efm32zg.s +++ /dev/null @@ -1,193 +0,0 @@ -;/**************************************************************************//** -; * @file startup_efm32zg.s -; * @brief CMSIS Core Device Startup File for -; * Silicon Labs EFM32ZG Device Series -; * @version 3.20.6 -; * @date 03. February 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x0 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY, ALIGN=8 - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - - DCD DMA_IRQHandler ; 0: DMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt - DCD ACMP0_IRQHandler ; 3: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 4: ADC0 Interrupt - DCD I2C0_IRQHandler ; 5: I2C0 Interrupt - DCD GPIO_ODD_IRQHandler ; 6: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 7: TIMER1 Interrupt - DCD USART1_RX_IRQHandler ; 8: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 9: USART1_TX Interrupt - DCD LEUART0_IRQHandler ; 10: LEUART0 Interrupt - DCD PCNT0_IRQHandler ; 11: PCNT0 Interrupt - DCD RTC_IRQHandler ; 12: RTC Interrupt - DCD CMU_IRQHandler ; 13: CMU Interrupt - DCD VCMP_IRQHandler ; 14: VCMP Interrupt - DCD MSC_IRQHandler ; 15: MSC Interrupt - DCD AES_IRQHandler ; 16: AES Interrupt - -__Vectors_End -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT DMA_IRQHandler [WEAK] - EXPORT GPIO_EVEN_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT ACMP0_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT GPIO_ODD_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT USART1_RX_IRQHandler [WEAK] - EXPORT USART1_TX_IRQHandler [WEAK] - EXPORT LEUART0_IRQHandler [WEAK] - EXPORT PCNT0_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT CMU_IRQHandler [WEAK] - EXPORT VCMP_IRQHandler [WEAK] - EXPORT MSC_IRQHandler [WEAK] - EXPORT AES_IRQHandler [WEAK] - - -DMA_IRQHandler -GPIO_EVEN_IRQHandler -TIMER0_IRQHandler -ACMP0_IRQHandler -ADC0_IRQHandler -I2C0_IRQHandler -GPIO_ODD_IRQHandler -TIMER1_IRQHandler -USART1_RX_IRQHandler -USART1_TX_IRQHandler -LEUART0_IRQHandler -PCNT0_IRQHandler -RTC_IRQHandler -CMU_IRQHandler -VCMP_IRQHandler -MSC_IRQHandler -AES_IRQHandler - - - B . - - ENDP - - ALIGN - -; User Initial Stack & Heap - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - END diff --git a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/arm_math.h b/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/arm_math.h index 65304c127d..741fce75e7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/arm_math.h +++ b/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/arm_math.h @@ -485,7 +485,7 @@ extern "C" #define __CLZ __clz #endif -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) && !defined (__CC_ARM) static __INLINE uint32_t __CLZ( q31_t data); diff --git a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg222f32.h b/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg222f32.h index 9d4b270157..ce9ede3329 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg222f32.h +++ b/libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg222f32.h @@ -199,7 +199,6 @@ typedef enum IRQn /** @} End of group EFM32ZG222F32_Part */ -#define ARM_MATH_CM0PLUS #include "arm_math.h" /* To get __CLZ definitions etc. */ #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ #include "system_efm32zg.h" /* System Header */ diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PinNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PinNames.h index 6cce0cb9c6..6643048906 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PinNames.h @@ -45,6 +45,8 @@ typedef enum { LED0 = PE2, LED1 = PE3, LED2 = LED0, + LED3 = LED0, + LED4 = LED1, /* Push Buttons */ SW0 = PB9, diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PinNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PinNames.h index 138e813e46..815340b129 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PinNames.h @@ -44,6 +44,8 @@ typedef enum { LED0 = PF4, LED1 = PF5, LED2 = LED0, + LED3 = LED0, + LED4 = LED1, /* Push Buttons */ SW0 = PC9, diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PinNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PinNames.h index 7256f4cfb4..2f907b500d 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PinNames.h @@ -44,6 +44,8 @@ typedef enum { LED0 = PE2, LED1 = PE3, LED2 = LED0, + LED3 = LED0, + LED4 = LED1, /* Push Buttons */ SW0 = PB9, diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PinNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PinNames.h index 7256f4cfb4..2f907b500d 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PinNames.h @@ -44,6 +44,8 @@ typedef enum { LED0 = PE2, LED1 = PE3, LED2 = LED0, + LED3 = LED0, + LED4 = LED1, /* Push Buttons */ SW0 = PB9, diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PinNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PinNames.h index ce3e0999d3..df85387eeb 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PinNames.h @@ -44,6 +44,8 @@ typedef enum { LED0 = PC10, LED1 = PC11, LED2 = LED0, + LED3 = LED0, + LED4 = LED1, /* Push Buttons */ SW0 = PC8, diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/clocking.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/clocking.h index 044baf75f7..5693234d81 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/clocking.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/clocking.h @@ -55,4 +55,4 @@ #define LEUART_REF_FREQ (REFERENCE_FREQUENCY / 4) #else #define LEUART_REF_FREQ (REFERENCE_FREQUENCY / 2) -#endif \ No newline at end of file +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c index 46c5efe517..e9969ff32d 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c @@ -63,9 +63,9 @@ static uint8_t i2c_get_index(i2c_t *obj) return index; } -static uint32_t i2c_get_clock(i2c_t *obj) +static CMU_Clock_TypeDef i2c_get_clock(i2c_t *obj) { - uint32_t clock; + CMU_Clock_TypeDef clock; switch ((int)obj->i2c.i2c) { #ifdef I2C0 case I2C_0: @@ -428,14 +428,14 @@ void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) void i2c_transfer_asynch(i2c_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) { I2C_TransferReturn_TypeDef retval; if(i2c_active(obj)) return; - + if((tx_length == 0) && (rx_length == 0)) return; // For now, we are assuming a solely interrupt-driven implementation. // Store transfer config obj->i2c.xfer.addr = address; // Some combination of tx_length and rx_length will tell us what to do - if((tx_length >= 0) && (rx_length == 0)) { + if((tx_length > 0) && (rx_length == 0)) { obj->i2c.xfer.flags = I2C_FLAG_WRITE; //Store buffer info obj->i2c.xfer.buf[0].data = tx; diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c index a954bda053..184c45c220 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c @@ -65,8 +65,8 @@ serial_t stdio_uart; static void uart_irq(UARTName, int, SerialIrq); uint8_t serial_get_index(serial_t *obj); -uint32_t serial_get_rx_irq_index(serial_t *obj); -uint32_t serial_get_tx_irq_index(serial_t *obj); +IRQn_Type serial_get_rx_irq_index(serial_t *obj); +IRQn_Type serial_get_tx_irq_index(serial_t *obj); CMU_Clock_TypeDef serial_get_clock(serial_t *obj); /* ISRs for RX and TX events */ @@ -91,10 +91,22 @@ static void usart2_rx_irq() { uart_irq(USART_2, 4, RxIrq); } static void usart2_tx_irq() { uart_irq(USART_2, 4, TxIrq); USART_IntClear((USART_TypeDef*)USART_2, USART_IFC_TXC);} #endif #ifdef LEUART0 -static void leuart0_irq() { uart_irq(LEUART_0, 5, TxIrq | RxIrq); } +static void leuart0_irq() { + if(LEUART_IntGetEnabled(LEUART0) && (LEUART_IF_RXDATAV | LEUART_IF_FERR | LEUART_IFC_PERR | LEUART_IF_RXOF)) { + uart_irq(LEUART_0, 5, RxIrq); + } else { + uart_irq(LEUART_0, 5, TxIrq); + } +} #endif #ifdef LEUART1 -static void leuart1_irq() { uart_irq(LEUART_1, 6, TxIrq | RxIrq); } +static void leuart1_irq() { + if(LEUART_IntGetEnabled(LEUART1) && (LEUART_IF_RXDATAV | LEUART_IF_FERR | LEUART_IFC_PERR | LEUART_IF_RXOF)) { + uart_irq(LEUART_1, 6, RxIrq); + } else { + uart_irq(LEUART_1, 6, TxIrq); + } +} #endif /** @@ -181,7 +193,7 @@ inline uint8_t serial_get_index(serial_t *obj) * @param obj pointer to serial object * @return internal NVIC RX IRQ index of U(S)ART peripheral */ -inline uint32_t serial_get_rx_irq_index(serial_t *obj) +inline IRQn_Type serial_get_rx_irq_index(serial_t *obj) { switch ((uint32_t)obj->serial.periph.uart) { #ifdef UART0 @@ -212,6 +224,8 @@ inline uint32_t serial_get_rx_irq_index(serial_t *obj) case LEUART_1: return LEUART1_IRQn; #endif + default: + MBED_ASSERT(0); } return 0; } @@ -222,7 +236,7 @@ inline uint32_t serial_get_rx_irq_index(serial_t *obj) * @param obj pointer to serial object * @return internal NVIC TX IRQ index of U(S)ART peripheral */ -inline uint32_t serial_get_tx_irq_index(serial_t *obj) +inline IRQn_Type serial_get_tx_irq_index(serial_t *obj) { switch ((uint32_t)obj->serial.periph.uart) { #ifdef UART0 @@ -253,6 +267,8 @@ inline uint32_t serial_get_tx_irq_index(serial_t *obj) case LEUART_1: return LEUART1_IRQn; #endif + default: + MBED_ASSERT(0); } return 0; } @@ -400,7 +416,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) uart_init(obj); /* Limitations of board controller: CDC port only supports 115kbaud */ - if((tx == STDIO_UART_TX) && (rx == STDIO_UART_RX) && (obj->serial.periph.uart == STDIO_UART )) { + if((tx == STDIO_UART_TX) && (rx == STDIO_UART_RX) && (obj->serial.periph.uart == (USART_TypeDef*)STDIO_UART )) { serial_baud(obj, 115200); } @@ -414,7 +430,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) } /* If this is the UART to be used for stdio, copy it to the stdio_uart struct */ - if (obj->serial.periph.uart == STDIO_UART ) { + if (obj->serial.periph.uart == (USART_TypeDef*)STDIO_UART ) { stdio_uart_inited = 1; memcpy(&stdio_uart, obj, sizeof(serial_t)); diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c index 83f358c408..471570cbd2 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c @@ -226,7 +226,7 @@ void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable) ****************************************************************************/ void spi_enable_interrupt(spi_t *obj, uint32_t handler, uint8_t enable) { - uint32_t IRQvector; + IRQn_Type IRQvector; switch ((uint32_t)obj->spi.spi) { #ifdef USART0 diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 54d278d501..55bc26fec6 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -1182,8 +1182,8 @@ class EFM32ZG_STK3200(Target): self.core = "Cortex-M0+" self.extra_labels = ['Silicon_Labs', 'EFM32'] self.macros = ['EFM32ZG222F32'] - self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"] - self.default_toolchain = "ARM" + self.supported_toolchains = ["GCC_ARM", "uARM"] + self.default_toolchain = "uARM" class EFM32HG_STK3400(Target): def __init__(self): @@ -1191,8 +1191,8 @@ class EFM32HG_STK3400(Target): self.core = "Cortex-M0+" self.extra_labels = ['Silicon_Labs', 'EFM32'] self.macros = ['EFM32HG322F64'] - self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"] - self.default_toolchain = "ARM" + self.supported_toolchains = ["GCC_ARM", "uARM"] + self.default_toolchain = "uARM" # Get a single instance for each target TARGETS = [