From d116c9d031986547500c38d3b26d0d9ad7874a1f Mon Sep 17 00:00:00 2001 From: Senthil Ramakrishnan Date: Sun, 8 Oct 2017 15:19:55 -0500 Subject: [PATCH 01/80] RealTek WiFi test configuration --- tools/test_configs/RealtekInterface.json | 27 ++++++++++++++++++++++++ tools/test_configs/config_paths.json | 3 ++- tools/test_configs/target_configs.json | 4 ++++ 3 files changed, 33 insertions(+), 1 deletion(-) create mode 100644 tools/test_configs/RealtekInterface.json diff --git a/tools/test_configs/RealtekInterface.json b/tools/test_configs/RealtekInterface.json new file mode 100644 index 0000000000..ad4a9ef31b --- /dev/null +++ b/tools/test_configs/RealtekInterface.json @@ -0,0 +1,27 @@ +{ + "config": { + "header-file": { + "help" : "String for including your driver header file", + "value" : "\"RTWInterface.h\"" + }, + "object-construction" : { + "value" : "new RTWInterface()" + }, + "connect-statement" : { + "help" : "Must use 'net' variable name, replace WIFI_SSID, WIFI_PASSWORD, WIFI_SECURITY, WIFI_CHANNEL with your WiFi settings", + "value" : "((RTWInterface *)net)->connect(WIFI_SSID, WIFI_PASSWORD, WIFI_SECURITY, WIFI_CHANNEL)" + }, + "echo-server-addr" : { + "help" : "IP address of echo server", + "value" : "\"195.34.89.241\"" + }, + "echo-server-port" : { + "help" : "Port of echo server", + "value" : "7" + }, + "tcp-echo-prefix" : { + "help" : "Some servers send a prefix before echoed message", + "value" : "\"Realtek Ameba TCP/UDP test service\\n\"" + } + } +} diff --git a/tools/test_configs/config_paths.json b/tools/test_configs/config_paths.json index c543176906..098c9442c3 100644 --- a/tools/test_configs/config_paths.json +++ b/tools/test_configs/config_paths.json @@ -1,5 +1,6 @@ { "ETHERNET" : "EthernetInterface.json", "ODIN_WIFI" : "OdinInterface.json", - "ODIN_ETHERNET" : "Odin_EthernetInterface.json" + "ODIN_ETHERNET" : "Odin_EthernetInterface.json", + "REALTEK_WIFI" : "RealtekInterface.json" } diff --git a/tools/test_configs/target_configs.json b/tools/test_configs/target_configs.json index eaff8b55b9..346901bf6a 100644 --- a/tools/test_configs/target_configs.json +++ b/tools/test_configs/target_configs.json @@ -6,5 +6,9 @@ "K64F": { "default_test_configuration": "ETHERNET", "test_configurations": ["ETHERNET"] + }, + "REALTEK_RTL8195AM": { + "default_test_configuration": "REALTEK_WIFI", + "test_configurations": ["REALTEK_WIFI"] } } From 889e22cce9a2c71b36135c8511f2177d3ecb9fb8 Mon Sep 17 00:00:00 2001 From: danclement Date: Fri, 27 Oct 2017 16:19:03 -0600 Subject: [PATCH 02/80] Checking in the fixes related to I2C issues. Three main issues: 1) The 0x13 special case section in write data in ncs36510_i2c.c didn't have a write++ command. 2) In the same write function, the WDAT8 command was put before the 0x13 section and this is not correct 3) Needed to add wait_us(0) before and after the register writes for apparent clock domain crossing delay times until registers are stable in HW There were also a handful of other tweaks related to general code maintenance and moving some status register checks to the proper locations. --- targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h | 8 ++-- .../TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c | 6 +-- .../TARGET_NCS36510/ncs36510_i2c.c | 40 ++++++++----------- 3 files changed, 23 insertions(+), 31 deletions(-) diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h index bcbafbe000..2b5f323343 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h @@ -48,7 +48,6 @@ #define I2C_SPEED_400K_AT_8MHZ (uint8_t)0x03 #define I2C_SPEED_400K_AT_16MHZ (uint8_t)0x08 - /* I2C commands */ #define I2C_CMD_NULL 0x00 #define I2C_CMD_WDAT0 0x10 @@ -93,7 +92,10 @@ #define I2C_API_STATUS_SUCCESS 0 #define PAD_REG_ADRS_BYTE_SIZE 4 -#define SEND_COMMAND(cmd) while(!I2C_FIFO_EMPTY); wait_us(1); obj->membase->CMD_REG = cmd; +// The wait_us(0) command is needed so the I2C state machines have enough +// time for data to settle across all clock domain crossings in their +// synchronizers, both directions. +#define SEND_COMMAND(cmd) wait_us(0); obj->membase->CMD_REG = cmd; wait_us(0); /** Init I2C device. * @details @@ -158,4 +160,4 @@ extern int32_t fI2cReadB(i2c_t *d, char *buf, int len); */ extern int32_t fI2cWriteB(i2c_t *d, const char *buf, int len); -#endif /* I2C_H_ */ \ No newline at end of file +#endif /* I2C_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c index cc57ed834d..12845ed069 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c @@ -169,9 +169,7 @@ int i2c_byte_write(i2c_t *obj, int data) return Count; } - while(obj->membase->STATUS.WORD & I2C_STATUS_CMD_FIFO_OFL_BIT); /* Wait till command overflow ends */ - - if(obj->membase->STATUS.WORD & I2C_STATUS_BUS_ERR_BIT) { + if(I2C_BUS_ERR_CHECK) { /* Bus error means NAK received */ return 0; } else { @@ -180,4 +178,4 @@ int i2c_byte_write(i2c_t *obj, int data) } } -#endif /* DEVICE_I2C */ \ No newline at end of file +#endif /* DEVICE_I2C */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c index 1b3e5daf20..8ae4a9b935 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c @@ -65,7 +65,6 @@ /* See i2c.h for details */ void fI2cInit(i2c_t *obj,PinName sda,PinName scl) { - uint32_t clockDivisor; /* determine the I2C to use */ I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); @@ -93,9 +92,7 @@ void fI2cInit(i2c_t *obj,PinName sda,PinName scl) obj->membase->CR.BITS.I2C_APB_CD_EN = True; /* set default baud rate at 100k */ - clockDivisor = ((fClockGetPeriphClockfrequency() / 100000) >> 2) - 2; - obj->membase->CR.BITS.CD_VAL = (clockDivisor & I2C_CLOCKDIVEDER_VAL_MASK); - obj->membase->PRE_SCALE_REG = (clockDivisor & I2C_APB_CLK_DIVIDER_VAL_MASK) >> 5; /**< Zero pre-scale value not allowed */ + fI2cFrequency(obj, 100000); /* Cross bar setting */ pinmap_pinout(sda, PinMap_I2C_SDA); @@ -110,8 +107,8 @@ void fI2cInit(i2c_t *obj,PinName sda,PinName scl) PadReg_t *padRegScl = (PadReg_t*)(PADREG_BASE + (scl * PAD_REG_ADRS_BYTE_SIZE)); CLOCK_ENABLE(CLOCK_PAD); - padRegSda->PADIO0.BITS.POWER = 1; /* sda: Drive strength */ - padRegScl->PADIO0.BITS.POWER = 1; /* scl: Drive strength */ + padRegSda->PADIO0.BITS.POWER = 3; /* sda: Drive strength */ + padRegScl->PADIO0.BITS.POWER = 3; /* scl: Drive strength */ CLOCK_DISABLE(CLOCK_PAD); CLOCK_ENABLE(CLOCK_GPIO); @@ -160,7 +157,10 @@ int32_t fI2cReadB(i2c_t *obj, char *buf, int len) int32_t read = 0; while (read < len) { - /* Send read command */ + + while(FIFO_OFL_CHECK); /* Wait till command overflow ends */ + + /* Send read command */ SEND_COMMAND(I2C_CMD_RDAT8); while(!RD_DATA_READY) { if (I2C_BUS_ERR_CHECK) { @@ -170,8 +170,8 @@ int32_t fI2cReadB(i2c_t *obj, char *buf, int len) } buf[read++] = obj->membase->RD_FIFO_REG; /**< Reading 'read FIFO register' will clear status register */ - if(!(read>=len)) { /* No ACK will be generated for the last read, upper level I2C protocol should generate */ - SEND_COMMAND(I2C_CMD_WDAT0); /* TODO based on requirement generate ACK or NACK Based on the requirement. */ + if(!(read>=len)) { + SEND_COMMAND(I2C_CMD_WDAT0); } else { /* No ack */ SEND_COMMAND(I2C_CMD_WDAT1); @@ -179,7 +179,7 @@ int32_t fI2cReadB(i2c_t *obj, char *buf, int len) /* check for FIFO underflow */ if(I2C_UFL_CHECK) { - return I2C_ERROR_NO_SLAVE; /* TODO No error available for this in i2c_api.h */ + return I2C_EVENT_ERROR; } if(I2C_BUS_ERR_CHECK) { /* Bus error */ @@ -196,8 +196,8 @@ int32_t fI2cWriteB(i2c_t *obj, const char *buf, int len) int32_t write = 0; while (write < len) { - /* Send write command */ - SEND_COMMAND(I2C_CMD_WDAT8); + + while(FIFO_OFL_CHECK); /* Wait till command overflow ends */ if(buf[write] == I2C_CMD_RDAT8) { /* SW work around to counter FSM issue. If the only command in the CMD FIFO is the WDAT8 command (data of 0x13) @@ -205,35 +205,27 @@ int32_t fI2cWriteB(i2c_t *obj, const char *buf, int len) RDAT8 command by the data FSM; resulting in an I2C bus error (NACK instead of an ACK). */ /* Send 0x13 bit wise */ SEND_COMMAND(I2C_CMD_WDAT0); - SEND_COMMAND(I2C_CMD_WDAT0); - SEND_COMMAND(I2C_CMD_WDAT0); - SEND_COMMAND(I2C_CMD_WDAT1); - SEND_COMMAND(I2C_CMD_WDAT0); - SEND_COMMAND(I2C_CMD_WDAT0); - SEND_COMMAND(I2C_CMD_WDAT1); - SEND_COMMAND(I2C_CMD_WDAT1); + write++; } else { /* Send data */ + SEND_COMMAND(I2C_CMD_WDAT8); SEND_COMMAND(buf[write++]); } - SEND_COMMAND(I2C_CMD_VRFY_ACK); /* TODO Verify ACK based on requirement, Do we need? */ + SEND_COMMAND(I2C_CMD_VRFY_ACK); if (I2C_BUS_ERR_CHECK) { /* Bus error */ return I2C_ERROR_BUS_BUSY; } - - while(FIFO_OFL_CHECK); /* Wait till command overflow ends */ } - return write; } -#endif /* DEVICE_I2C */ \ No newline at end of file +#endif /* DEVICE_I2C */ From 2f36cd78d671e92154a8b3d6dce19a44af41d094 Mon Sep 17 00:00:00 2001 From: Martin Kojtal <0xc0170@gmail.com> Date: Tue, 7 Nov 2017 09:12:16 +0000 Subject: [PATCH 03/80] test: realtek net config default to none Changing this to none as result of build failures. Wifi needs own configuration per an enviroment. By setting this to none, net tests are skipped for Realtek platform. --- tools/test_configs/target_configs.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/test_configs/target_configs.json b/tools/test_configs/target_configs.json index 346901bf6a..c6d9a9b259 100644 --- a/tools/test_configs/target_configs.json +++ b/tools/test_configs/target_configs.json @@ -8,7 +8,7 @@ "test_configurations": ["ETHERNET"] }, "REALTEK_RTL8195AM": { - "default_test_configuration": "REALTEK_WIFI", + "default_test_configuration": "NONE", "test_configurations": ["REALTEK_WIFI"] } } From c2bba672dfa1a9e21c1190a2094c8a4e19512faf Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 9 Nov 2017 09:45:07 +0100 Subject: [PATCH 04/80] STM32F412 IAR linker file issue --- .../TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf index f702047a09..46363c1caf 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf @@ -10,7 +10,7 @@ define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE; define symbol __NVIC_start__ = 0x20000000; define symbol __NVIC_end__ = 0x200001C7; /* Aligned on 8 bytes */ define symbol __region_RAM_start__ = 0x200001C8; -define symbol __region_RAM_end__ = 0x2001FFFF; +define symbol __region_RAM_end__ = 0x2003FFFF; /* Memory regions */ define memory mem with size = 4G; From e20d35df27059e8ab5ea0289cf4cb74bb0616a25 Mon Sep 17 00:00:00 2001 From: Laurent MEUNIER Date: Wed, 8 Nov 2017 09:02:21 +0100 Subject: [PATCH 05/80] STM32F4: Flash: fix 2MB GetSector computation The computation of the sector number in GetSector for 2MB flash sizes consists in adding an extra constant for 2MB dual bank (12 as in ADDR_FLASH_SECTOR_12), then going through the same address check as if it was an address of the first sector. That means that we need to modify tmp and address as if it was a first bank address, which we're doing here by sub_stracting 0x100000 delta. --- targets/TARGET_STM/TARGET_STM32F4/flash_api.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32F4/flash_api.c b/targets/TARGET_STM/TARGET_STM32F4/flash_api.c index 1455f07aab..f3f1be95ac 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F4/flash_api.c @@ -180,8 +180,10 @@ static uint32_t GetSector(uint32_t address) /* This function supports 1Mb and 2Mb flash sizes */ #if defined(ADDR_FLASH_SECTOR_16) if (address & 0x100000) { // handle 2nd bank + /* Sector will be at least 12 */ sector = FLASH_SECTOR_12; - tmp = address - ADDR_FLASH_SECTOR_12; + tmp -= 0x100000; + address -= 0x100000; } #endif if (address < ADDR_FLASH_SECTOR_4) { // 16k sectorsize From f81521adcc2cf19df7912ac7d44f0d4d6c9bf593 Mon Sep 17 00:00:00 2001 From: Laurent MEUNIER Date: Wed, 8 Nov 2017 09:02:39 +0100 Subject: [PATCH 06/80] STM32: remove trailing white spaces --- targets/TARGET_STM/TARGET_STM32F4/flash_api.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F4/flash_api.c b/targets/TARGET_STM/TARGET_STM32F4/flash_api.c index f3f1be95ac..5ba7fb9e49 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F4/flash_api.c @@ -145,7 +145,6 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { - if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) { return MBED_FLASH_INVALID_SIZE; } @@ -165,7 +164,7 @@ uint32_t flash_get_start_address(const flash_t *obj) } uint32_t flash_get_size(const flash_t *obj) { - return FLASH_SIZE; + return FLASH_SIZE; } /** @@ -175,7 +174,7 @@ uint32_t flash_get_size(const flash_t *obj) */ static uint32_t GetSector(uint32_t address) { - uint32_t sector = 0; + uint32_t sector = 0; uint32_t tmp = address - ADDR_FLASH_SECTOR_0; /* This function supports 1Mb and 2Mb flash sizes */ #if defined(ADDR_FLASH_SECTOR_16) @@ -191,14 +190,14 @@ static uint32_t GetSector(uint32_t address) } #if defined(ADDR_FLASH_SECTOR_5) else if (address < ADDR_FLASH_SECTOR_5) { //64k sector size - sector += FLASH_SECTOR_4; + sector += FLASH_SECTOR_4; } else { sector += 4 + (tmp >>17); } #else // In case ADDR_FLASH_SECTOR_5 is not defined, sector 4 is the last one. else { //64k sector size - sector += FLASH_SECTOR_4; + sector += FLASH_SECTOR_4; } #endif return sector; @@ -227,7 +226,7 @@ if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_ sectorsize = 64 * 1024; } else { sectorsize = 128 * 1024; - } + } return sectorsize; } From ce04e3db087a288f8a1f5cfb59cb992c349978f3 Mon Sep 17 00:00:00 2001 From: Marcus Chang Date: Tue, 7 Nov 2017 09:25:24 -0800 Subject: [PATCH 07/80] Increase flash size on Realtek RTL8195AM The Realtek RTL8195AM has 2 MiB of external flash. This change enables the FlashIAP driver to gain access to the full flash. --- targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.h b/targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.h index 6ad5c799da..b2d287bf61 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.h +++ b/targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.h @@ -24,7 +24,7 @@ extern "C" { #endif #define FLASH_PAGE_SIZE 256 -#define FLASH_SIZE 0x100000 +#define FLASH_SIZE 0x200000 #define FLASH_OFS_START 0x0 #define FLASH_OFS_END (FLASH_OFS_START + FLASH_SIZE) From 157150ec91fb48dba13dd6c729756dbcf52e6e32 Mon Sep 17 00:00:00 2001 From: Laurent MEUNIER Date: Thu, 2 Nov 2017 13:10:57 +0100 Subject: [PATCH 08/80] STM32: Extend Ethernet RMII workaround to all applicable devices part of F77x/F76x series. --- .../lwip-eth/arch/TARGET_STM/stm32xx_emac.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/stm32xx_emac.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/stm32xx_emac.c index 0ec2b16e48..134cea811d 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/stm32xx_emac.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/stm32xx_emac.c @@ -46,7 +46,8 @@ static sys_mutex_t tx_lock_mutex; /* function */ static void _eth_arch_rx_task(void *arg); static void _eth_arch_phy_task(void *arg); -#if defined (TARGET_NUCLEO_F767ZI) +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx)\ + || defined (STM32F779xx) static void _rmii_watchdog(void *arg); #endif @@ -375,9 +376,10 @@ static void _eth_arch_phy_task(void *arg) } } -#if defined (TARGET_NUCLEO_F767ZI) +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx)\ + || defined (STM32F779xx) /** - * workaround for the ETH RMII bug in STM32F769 Cut1.0 + * workaround for the ETH RMII bug in STM32F76x and STM32F77x revA * * \param[in] netif the lwip network interface structure */ @@ -497,7 +499,8 @@ err_t eth_arch_enetif_init(struct netif *netif) /* initialize the hardware */ _eth_arch_low_level_init(netif); -#if defined (TARGET_NUCLEO_F767ZI) +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx)\ + || defined (STM32F779xx) sys_thread_new("stm32_rmii_watchdog", _rmii_watchdog, netif, DEFAULT_THREAD_STACKSIZE, osPriorityLow); #endif From 3aa46e6af0e5f176cbfe147d1727bf16dc9472b9 Mon Sep 17 00:00:00 2001 From: Maciej Bocianski Date: Fri, 3 Nov 2017 15:32:08 +0100 Subject: [PATCH 09/80] small supplement for PR #5338 --- TESTS/mbedmicro-rtos-mbed/malloc/main.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp b/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp index daf80719f9..e0fcd355e0 100644 --- a/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp @@ -56,7 +56,7 @@ int main() { // static stack for threads to reduce heap usage on devices with small RAM // and eliminate run out of heap memory problem - MBED_ALIGN(8) uint8_t stack[THREAD_STACK_SIZE * NUM_THREADS]; + uint8_t stack[NUM_THREADS][THREAD_STACK_SIZE]; Thread *thread_list[NUM_THREADS]; int test_time = 15; @@ -64,7 +64,7 @@ int main() // Allocate threads for the test for (int i = 0; i < NUM_THREADS; i++) { - thread_list[i] = new Thread(osPriorityNormal, THREAD_STACK_SIZE, stack + i * THREAD_STACK_SIZE); + thread_list[i] = new Thread(osPriorityNormal, THREAD_STACK_SIZE, stack[i]); if (NULL == thread_list[i]) { allocation_failure = true; } else { From 781c0c7105077711a1707bd64e42dfcb81265a7f Mon Sep 17 00:00:00 2001 From: Kevin Bracey Date: Fri, 3 Nov 2017 15:15:57 +0200 Subject: [PATCH 10/80] Shrink RTOS classes Various RTOS classes were storing their CMSIS-RTOS creation attribute structure as a member, when it's not required after construction. Reduce memory by eliminating this member. --- rtos/EventFlags.cpp | 10 +++++----- rtos/EventFlags.h | 1 - rtos/MemoryPool.h | 13 ++++++------- rtos/Mutex.cpp | 12 ++++++------ rtos/Mutex.h | 1 - rtos/Queue.h | 13 ++++++------- rtos/RtosTimer.cpp | 8 ++++---- rtos/RtosTimer.h | 1 - rtos/Semaphore.cpp | 8 ++++---- rtos/Semaphore.h | 1 - 10 files changed, 31 insertions(+), 37 deletions(-) diff --git a/rtos/EventFlags.cpp b/rtos/EventFlags.cpp index abd88a1142..3d6b79321f 100644 --- a/rtos/EventFlags.cpp +++ b/rtos/EventFlags.cpp @@ -39,11 +39,11 @@ EventFlags::EventFlags(const char *name) void EventFlags::constructor(const char *name) { memset(&_obj_mem, 0, sizeof(_obj_mem)); - memset(&_attr, 0, sizeof(_attr)); - _attr.name = name ? name : "application_unnamed_event_flags"; - _attr.cb_mem = &_obj_mem; - _attr.cb_size = sizeof(_obj_mem); - _id = osEventFlagsNew(&_attr); + osEventFlagsAttr_t attr; + attr.name = name ? name : "application_unnamed_event_flags"; + attr.cb_mem = &_obj_mem; + attr.cb_size = sizeof(_obj_mem); + _id = osEventFlagsNew(&attr); MBED_ASSERT(_id); } diff --git a/rtos/EventFlags.h b/rtos/EventFlags.h index 8f0e2b20ed..02df107773 100644 --- a/rtos/EventFlags.h +++ b/rtos/EventFlags.h @@ -90,7 +90,6 @@ private: void constructor(const char *name = NULL); uint32_t wait(uint32_t flags, uint32_t opt, uint32_t timeout, bool clear); osEventFlagsId_t _id; - osEventFlagsAttr_t _attr; mbed_rtos_storage_event_flags_t _obj_mem; }; diff --git a/rtos/MemoryPool.h b/rtos/MemoryPool.h index 361ae6518f..0eab4de792 100644 --- a/rtos/MemoryPool.h +++ b/rtos/MemoryPool.h @@ -50,12 +50,12 @@ public: MemoryPool() { memset(_pool_mem, 0, sizeof(_pool_mem)); memset(&_obj_mem, 0, sizeof(_obj_mem)); - memset(&_attr, 0, sizeof(_attr)); - _attr.mp_mem = _pool_mem; - _attr.mp_size = sizeof(_pool_mem); - _attr.cb_mem = &_obj_mem; - _attr.cb_size = sizeof(_obj_mem); - _id = osMemoryPoolNew(pool_sz, sizeof(T), &_attr); + osMemoryPoolAttr_t attr = { 0 }; + attr.mp_mem = _pool_mem; + attr.mp_size = sizeof(_pool_mem); + attr.cb_mem = &_obj_mem; + attr.cb_size = sizeof(_obj_mem); + _id = osMemoryPoolNew(pool_sz, sizeof(T), &attr); MBED_ASSERT(_id); } @@ -95,7 +95,6 @@ public: private: osMemoryPoolId_t _id; - osMemoryPoolAttr_t _attr; /* osMemoryPoolNew requires that pool block size is a multiple of 4 bytes. */ char _pool_mem[((sizeof(T) + 3) & ~3) * pool_sz]; mbed_rtos_storage_mem_pool_t _obj_mem; diff --git a/rtos/Mutex.cpp b/rtos/Mutex.cpp index 359af10536..874af4608c 100644 --- a/rtos/Mutex.cpp +++ b/rtos/Mutex.cpp @@ -40,12 +40,12 @@ Mutex::Mutex(const char *name) void Mutex::constructor(const char *name) { memset(&_obj_mem, 0, sizeof(_obj_mem)); - memset(&_attr, 0, sizeof(_attr)); - _attr.name = name ? name : "aplication_unnamed_mutex"; - _attr.cb_mem = &_obj_mem; - _attr.cb_size = sizeof(_obj_mem); - _attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust; - _id = osMutexNew(&_attr); + osMutexAttr_t attr = { 0 }; + attr.name = name ? name : "aplication_unnamed_mutex"; + attr.cb_mem = &_obj_mem; + attr.cb_size = sizeof(_obj_mem); + attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust; + _id = osMutexNew(&attr); MBED_ASSERT(_id); } diff --git a/rtos/Mutex.h b/rtos/Mutex.h index 4f1ed8a6aa..5490012d46 100644 --- a/rtos/Mutex.h +++ b/rtos/Mutex.h @@ -82,7 +82,6 @@ private: void constructor(const char *name = NULL); osMutexId_t _id; - osMutexAttr_t _attr; mbed_rtos_storage_mutex_t _obj_mem; }; diff --git a/rtos/Queue.h b/rtos/Queue.h index 56739522ae..8f32d7a4e2 100644 --- a/rtos/Queue.h +++ b/rtos/Queue.h @@ -51,12 +51,12 @@ public: /** Create and initialize a message Queue. */ Queue() { memset(&_obj_mem, 0, sizeof(_obj_mem)); - memset(&_attr, 0, sizeof(_attr)); - _attr.mq_mem = _queue_mem; - _attr.mq_size = sizeof(_queue_mem); - _attr.cb_mem = &_obj_mem; - _attr.cb_size = sizeof(_obj_mem); - _id = osMessageQueueNew(queue_sz, sizeof(T*), &_attr); + osMessageQueueAttr_t attr = { 0 }; + attr.mq_mem = _queue_mem; + attr.mq_size = sizeof(_queue_mem); + attr.cb_mem = &_obj_mem; + attr.cb_size = sizeof(_obj_mem); + _id = osMessageQueueNew(queue_sz, sizeof(T*), &attr); MBED_ASSERT(_id); } @@ -115,7 +115,6 @@ public: private: osMessageQueueId_t _id; - osMessageQueueAttr_t _attr; char _queue_mem[queue_sz * (sizeof(T*) + sizeof(mbed_rtos_storage_message_t))]; mbed_rtos_storage_msg_queue_t _obj_mem; }; diff --git a/rtos/RtosTimer.cpp b/rtos/RtosTimer.cpp index acec84ed98..3e6c19718b 100644 --- a/rtos/RtosTimer.cpp +++ b/rtos/RtosTimer.cpp @@ -31,10 +31,10 @@ namespace rtos { void RtosTimer::constructor(mbed::Callback func, os_timer_type type) { _function = func; memset(&_obj_mem, 0, sizeof(_obj_mem)); - memset(&_attr, 0, sizeof(_attr)); - _attr.cb_mem = &_obj_mem; - _attr.cb_size = sizeof(_obj_mem); - _id = osTimerNew((void (*)(void *))Callback::thunk, type, &_function, &_attr); + osTimerAttr_t attr = { 0 }; + attr.cb_mem = &_obj_mem; + attr.cb_size = sizeof(_obj_mem); + _id = osTimerNew((void (*)(void *))Callback::thunk, type, &_function, &attr); MBED_ASSERT(_id); } diff --git a/rtos/RtosTimer.h b/rtos/RtosTimer.h index d96de829e1..d75f49c8b2 100644 --- a/rtos/RtosTimer.h +++ b/rtos/RtosTimer.h @@ -157,7 +157,6 @@ private: void constructor(mbed::Callback func, os_timer_type type); osTimerId_t _id; - osTimerAttr_t _attr; mbed_rtos_storage_timer_t _obj_mem; mbed::Callback _function; }; diff --git a/rtos/Semaphore.cpp b/rtos/Semaphore.cpp index 107dccb33f..fb082d3c44 100644 --- a/rtos/Semaphore.cpp +++ b/rtos/Semaphore.cpp @@ -36,10 +36,10 @@ Semaphore::Semaphore(int32_t count, uint16_t max_count) { void Semaphore::constructor(int32_t count, uint16_t max_count) { memset(&_obj_mem, 0, sizeof(_obj_mem)); - memset(&_attr, 0, sizeof(_attr)); - _attr.cb_mem = &_obj_mem; - _attr.cb_size = sizeof(_obj_mem); - _id = osSemaphoreNew(max_count, count, &_attr); + osSemaphoreAttr_t attr = { 0 }; + attr.cb_mem = &_obj_mem; + attr.cb_size = sizeof(_obj_mem); + _id = osSemaphoreNew(max_count, count, &attr); MBED_ASSERT(_id != NULL); } diff --git a/rtos/Semaphore.h b/rtos/Semaphore.h index 80dc928ede..07ce078277 100644 --- a/rtos/Semaphore.h +++ b/rtos/Semaphore.h @@ -71,7 +71,6 @@ private: void constructor(int32_t count, uint16_t max_count); osSemaphoreId_t _id; - osSemaphoreAttr_t _attr; mbed_rtos_storage_semaphore_t _obj_mem; }; From 5fe9ee557178c5177b94a5a898125908d6c1e493 Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Tue, 31 Oct 2017 18:19:36 +0100 Subject: [PATCH 11/80] Tests: RTOS: RtosTimer: Fix tests for NRF51_DK board Additional delay is needed to prevent random failures when waiting for a semaphore. --- TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp | 24 ++++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp b/TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp index 581336bcdc..59c26cc4f2 100644 --- a/TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp @@ -23,7 +23,7 @@ using namespace utest::v1; #define TEST_DELAY_MS 50 #define TEST_DELAY2_MS 30 -#define TEST_DELAY_MS_DELTA 1 +#define TEST_DELAY_MS_DELTA 5 #define TEST_RESTART_DELAY_MS 10 #if TEST_RESTART_DELAY_MS >= TEST_DELAY_MS @@ -71,12 +71,12 @@ void test_oneshot_not_restarted() t.start(); TEST_ASSERT_EQUAL(osOK, stat); - int32_t slots = sem.wait(TEST_DELAY_MS + 1); + int32_t slots = sem.wait(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); t.stop(); TEST_ASSERT_EQUAL(1, slots); TEST_ASSERT_INT_WITHIN(TEST_DELAY_MS_DELTA * 1000, TEST_DELAY_MS * 1000, t.read_us()); - slots = sem.wait(TEST_DELAY_MS + 1); + slots = sem.wait(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); TEST_ASSERT_EQUAL(0, slots); stat = timer.stop(); @@ -105,12 +105,12 @@ void test_periodic_repeats() t.start(); TEST_ASSERT_EQUAL(osOK, stat); - int32_t slots = sem.wait(TEST_DELAY_MS + 1); + int32_t slots = sem.wait(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); int t1 = t.read_us(); TEST_ASSERT_EQUAL(1, slots); TEST_ASSERT_INT_WITHIN(TEST_DELAY_MS_DELTA * 1000, TEST_DELAY_MS * 1000, t1); - slots = sem.wait(TEST_DELAY_MS + 1); + slots = sem.wait(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); t.stop(); TEST_ASSERT_EQUAL(1, slots); TEST_ASSERT_INT_WITHIN(TEST_DELAY_MS_DELTA * 1000, TEST_DELAY_MS * 1000, t.read_us() - t1); @@ -118,7 +118,7 @@ void test_periodic_repeats() stat = timer.stop(); TEST_ASSERT_EQUAL(osOK, stat); - slots = sem.wait(TEST_DELAY_MS + 1); + slots = sem.wait(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); TEST_ASSERT_EQUAL(0, slots); stat = timer.stop(); @@ -153,7 +153,7 @@ void test_restart() stat = timer.start(TEST_DELAY_MS); TEST_ASSERT_EQUAL(osOK, stat); - slots = sem.wait(TEST_DELAY_MS + 1); + slots = sem.wait(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); t.stop(); TEST_ASSERT_EQUAL(1, slots); TEST_ASSERT_INT_WITHIN(TEST_DELAY_MS_DELTA * 1000, (TEST_DELAY_MS + TEST_RESTART_DELAY_MS) * 1000, t.read_us()); @@ -183,7 +183,7 @@ void test_start_again() stat = timer.start(TEST_DELAY_MS); TEST_ASSERT_EQUAL(osOK, stat); - int32_t slots = sem.wait(TEST_DELAY_MS + 1); + int32_t slots = sem.wait(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); TEST_ASSERT_EQUAL(1, slots); stat = timer.stop(); @@ -192,7 +192,7 @@ void test_start_again() stat = timer.start(TEST_DELAY_MS); TEST_ASSERT_EQUAL(osOK, stat); - slots = sem.wait(TEST_DELAY_MS + 1); + slots = sem.wait(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); TEST_ASSERT_EQUAL(1, slots); stat = timer.stop(); @@ -227,7 +227,7 @@ void test_restart_updates_delay() t.start(); TEST_ASSERT_EQUAL(osOK, stat); - slots = sem.wait(TEST_DELAY2_MS + 1); + slots = sem.wait(TEST_DELAY2_MS + TEST_DELAY_MS_DELTA); t.stop(); TEST_ASSERT_EQUAL(1, slots); TEST_ASSERT_INT_WITHIN(TEST_DELAY_MS_DELTA * 1000, TEST_DELAY2_MS * 1000, t.read_us()); @@ -273,7 +273,7 @@ void test_stop() stat = timer.stop(); TEST_ASSERT_EQUAL(osOK, stat); - slots = sem.wait(TEST_DELAY_MS + 1); + slots = sem.wait(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); TEST_ASSERT_EQUAL(0, slots); stat = timer.stop(); @@ -337,7 +337,7 @@ void test_isr_calls_fail() Ticker ticker; ticker.attach(mbed::callback(timer_isr_call, (void const *) &timer), (float) TEST_DELAY_MS / 1000.0); - wait_ms(TEST_DELAY_MS + 1); + wait_ms(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); } utest::v1::status_t test_setup(const size_t number_of_cases) From 5ead8eccebf4722c45ab28352258685cd1fa5f32 Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Fri, 3 Nov 2017 10:57:20 +0100 Subject: [PATCH 12/80] Tests: RTOS: RtosTimer: Refactor for readability --- TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp | 320 +++++++++---------- 1 file changed, 151 insertions(+), 169 deletions(-) diff --git a/TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp b/TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp index 59c26cc4f2..694ea04bf3 100644 --- a/TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp @@ -21,18 +21,55 @@ using namespace utest::v1; -#define TEST_DELAY_MS 50 -#define TEST_DELAY2_MS 30 -#define TEST_DELAY_MS_DELTA 5 -#define TEST_RESTART_DELAY_MS 10 +#define DELAY_MS 50 +#define DELTA_MS 5 +#define RESTART_DELAY_MS 10 +#define DELAY2_MS 30 -#if TEST_RESTART_DELAY_MS >= TEST_DELAY_MS -#error invalid TEST_RESTART_DELAY_MS value +#if RESTART_DELAY_MS >= DELAY_MS +#error invalid RESTART_DELAY_MS value #endif -void timer_callback(void const *arg) +class Stopwatch: public Timer { +private: + Semaphore _sem; + +public: + Stopwatch() : + Timer(), _sem(1) + { + } + + ~Stopwatch() + { + } + + void start(void) + { + _sem.wait(0); + Timer::start(); + } + + void stop(void) + { + Timer::stop(); + _sem.release(); + } + + int32_t wait_until_stopped(uint32_t millisec = osWaitForever) + { + core_util_critical_section_enter(); + int running = _running; + core_util_critical_section_exit(); + if (!running) { + return 1; + } + return _sem.wait(millisec); + } +}; + +void sem_callback(Semaphore *sem) { - Semaphore *sem = (Semaphore *) arg; sem->release(); } @@ -44,14 +81,15 @@ void timer_callback(void const *arg) * which aborts test program. */ #if defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED -void error(const char* format, ...) { +void error(const char* format, ...) +{ (void) format; } #endif /** Test one-shot not restarted when elapsed * - * Given a one-shot timer + * Given a one-shot RtosTimer * When the timer is started * and given time elapses * Then timer stops @@ -60,32 +98,27 @@ void error(const char* format, ...) { */ void test_oneshot_not_restarted() { - Semaphore sem(1); - RtosTimer timer(mbed::callback(timer_callback, (void const *) &sem), osTimerOnce); - osStatus stat = timer.stop(); - TEST_ASSERT_EQUAL(osErrorResource, stat); + Stopwatch stopwatch; + RtosTimer rtostimer(mbed::callback(&stopwatch, &Stopwatch::stop), osTimerOnce); - Timer t; - sem.wait(0); - stat = timer.start(TEST_DELAY_MS); - t.start(); - TEST_ASSERT_EQUAL(osOK, stat); + stopwatch.start(); + osStatus status = rtostimer.start(DELAY_MS); + TEST_ASSERT_EQUAL(osOK, status); - int32_t slots = sem.wait(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); - t.stop(); + int32_t slots = stopwatch.wait_until_stopped(); TEST_ASSERT_EQUAL(1, slots); - TEST_ASSERT_INT_WITHIN(TEST_DELAY_MS_DELTA * 1000, TEST_DELAY_MS * 1000, t.read_us()); + TEST_ASSERT_INT_WITHIN(DELTA_MS, DELAY_MS, stopwatch.read_ms()); + stopwatch.start(); - slots = sem.wait(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); + slots = stopwatch.wait_until_stopped(DELAY_MS + DELTA_MS); TEST_ASSERT_EQUAL(0, slots); - - stat = timer.stop(); - TEST_ASSERT_EQUAL(osErrorResource, stat); + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osErrorResource, status); } /** Test periodic repeats continuously * - * Given a periodic timer + * Given a periodic RtosTimer * When timer is started * and given time elapses * Then timer repeats its operation @@ -94,77 +127,37 @@ void test_oneshot_not_restarted() */ void test_periodic_repeats() { - Semaphore sem(1); - RtosTimer timer(mbed::callback(timer_callback, (void const *) &sem), osTimerPeriodic); - osStatus stat = timer.stop(); - TEST_ASSERT_EQUAL(osErrorResource, stat); + Stopwatch stopwatch; + RtosTimer rtostimer(mbed::callback(&stopwatch, &Stopwatch::stop), osTimerPeriodic); - Timer t; - sem.wait(0); - stat = timer.start(TEST_DELAY_MS); - t.start(); - TEST_ASSERT_EQUAL(osOK, stat); + stopwatch.start(); + osStatus status = rtostimer.start(DELAY_MS); + TEST_ASSERT_EQUAL(osOK, status); - int32_t slots = sem.wait(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); - int t1 = t.read_us(); + int32_t slots = stopwatch.wait_until_stopped(); + int t1 = stopwatch.read_ms(); + stopwatch.reset(); + stopwatch.start(); TEST_ASSERT_EQUAL(1, slots); - TEST_ASSERT_INT_WITHIN(TEST_DELAY_MS_DELTA * 1000, TEST_DELAY_MS * 1000, t1); + TEST_ASSERT_INT_WITHIN(DELTA_MS, DELAY_MS, t1); - slots = sem.wait(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); - t.stop(); + slots = stopwatch.wait_until_stopped(); TEST_ASSERT_EQUAL(1, slots); - TEST_ASSERT_INT_WITHIN(TEST_DELAY_MS_DELTA * 1000, TEST_DELAY_MS * 1000, t.read_us() - t1); + TEST_ASSERT_INT_WITHIN(DELTA_MS, DELAY_MS, stopwatch.read_ms()); + stopwatch.start(); - stat = timer.stop(); - TEST_ASSERT_EQUAL(osOK, stat); + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osOK, status); - slots = sem.wait(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); + slots = stopwatch.wait_until_stopped(DELAY_MS + DELTA_MS); TEST_ASSERT_EQUAL(0, slots); - - stat = timer.stop(); - TEST_ASSERT_EQUAL(osErrorResource, stat); -} - -/** Test timer can be restarted - * - * Given a one-shot timer - * When the timer is started - * and @a start is called again before given time elapses - * and given time elapses - * Then timer stops - * and elapsed time is greater than original delay - */ -void test_restart() -{ - Semaphore sem(1); - RtosTimer timer(mbed::callback(timer_callback, (void const *) &sem), osTimerOnce); - osStatus stat = timer.stop(); - TEST_ASSERT_EQUAL(osErrorResource, stat); - - Timer t; - sem.wait(0); - stat = timer.start(TEST_DELAY_MS); - t.start(); - TEST_ASSERT_EQUAL(osOK, stat); - - int32_t slots = sem.wait(TEST_RESTART_DELAY_MS); - TEST_ASSERT_EQUAL(0, slots); - - stat = timer.start(TEST_DELAY_MS); - TEST_ASSERT_EQUAL(osOK, stat); - - slots = sem.wait(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); - t.stop(); - TEST_ASSERT_EQUAL(1, slots); - TEST_ASSERT_INT_WITHIN(TEST_DELAY_MS_DELTA * 1000, (TEST_DELAY_MS + TEST_RESTART_DELAY_MS) * 1000, t.read_us()); - - stat = timer.stop(); - TEST_ASSERT_EQUAL(osErrorResource, stat); + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osErrorResource, status); } /** Test timer can be started again * - * Given a one-shot timer + * Given a one-shot Rtosimer * When the timer is started * and given time elapses * Then timer stops @@ -174,34 +167,31 @@ void test_restart() */ void test_start_again() { - Semaphore sem(1); - RtosTimer timer(mbed::callback(timer_callback, (void const *) &sem), osTimerOnce); - osStatus stat = timer.stop(); - TEST_ASSERT_EQUAL(osErrorResource, stat); + Semaphore sem(0, 1); + RtosTimer rtostimer(mbed::callback(sem_callback, &sem), osTimerOnce); - sem.wait(0); - stat = timer.start(TEST_DELAY_MS); - TEST_ASSERT_EQUAL(osOK, stat); + osStatus status = rtostimer.start(DELAY_MS); + TEST_ASSERT_EQUAL(osOK, status); - int32_t slots = sem.wait(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); + int32_t slots = sem.wait(DELAY_MS + DELTA_MS); TEST_ASSERT_EQUAL(1, slots); - stat = timer.stop(); - TEST_ASSERT_EQUAL(osErrorResource, stat); + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osErrorResource, status); - stat = timer.start(TEST_DELAY_MS); - TEST_ASSERT_EQUAL(osOK, stat); + status = rtostimer.start(DELAY_MS); + TEST_ASSERT_EQUAL(osOK, status); - slots = sem.wait(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); + slots = sem.wait(DELAY_MS + DELTA_MS); TEST_ASSERT_EQUAL(1, slots); - stat = timer.stop(); - TEST_ASSERT_EQUAL(osErrorResource, stat); + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osErrorResource, status); } /** Test timer restart updates delay * - * Given a one-shot timer + * Given a one-shot RtosTimer * When the timer is started * and @a start is called again with a different delay before given time elapses * and updated delay elapses @@ -210,134 +200,127 @@ void test_start_again() */ void test_restart_updates_delay() { - Semaphore sem(1); - RtosTimer timer(mbed::callback(timer_callback, (void const *) &sem), osTimerOnce); - osStatus stat = timer.stop(); - TEST_ASSERT_EQUAL(osErrorResource, stat); + Stopwatch stopwatch; + RtosTimer rtostimer(mbed::callback(&stopwatch, &Stopwatch::stop), osTimerOnce); - sem.wait(0); - stat = timer.start(TEST_DELAY_MS); - TEST_ASSERT_EQUAL(osOK, stat); + stopwatch.start(); + osStatus status = rtostimer.start(DELAY_MS); + TEST_ASSERT_EQUAL(osOK, status); - int32_t slots = sem.wait(TEST_RESTART_DELAY_MS); + int32_t slots = stopwatch.wait_until_stopped(RESTART_DELAY_MS); TEST_ASSERT_EQUAL(0, slots); - Timer t; - stat = timer.start(TEST_DELAY2_MS); - t.start(); - TEST_ASSERT_EQUAL(osOK, stat); + stopwatch.reset(); + stopwatch.start(); + status = rtostimer.start(DELAY2_MS); + TEST_ASSERT_EQUAL(osOK, status); - slots = sem.wait(TEST_DELAY2_MS + TEST_DELAY_MS_DELTA); - t.stop(); + slots = stopwatch.wait_until_stopped(); TEST_ASSERT_EQUAL(1, slots); - TEST_ASSERT_INT_WITHIN(TEST_DELAY_MS_DELTA * 1000, TEST_DELAY2_MS * 1000, t.read_us()); + TEST_ASSERT_INT_WITHIN(DELTA_MS, DELAY2_MS, stopwatch.read_ms()); - stat = timer.stop(); - TEST_ASSERT_EQUAL(osErrorResource, stat); + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osErrorResource, status); } /** Test timer is created in stopped state * - * Given a one-shot timer + * Given a one-shot RtosTimer * When the timer has not been started * Then the timer is stopped */ void test_created_stopped() { - RtosTimer timer(mbed::callback(timer_callback, (void const *) NULL), osTimerOnce); - osStatus stat = timer.stop(); - TEST_ASSERT_EQUAL(osErrorResource, stat); + RtosTimer rtostimer(mbed::callback(sem_callback, (Semaphore *) NULL), osTimerOnce); + osStatus status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osErrorResource, status); } /** Test one-shot can be stopped * - * Given a one-shot timer + * Given a one-shot RtosTimer * When the timer is started * and timer is stopped while still running * Then timer stops operation */ void test_stop() { - Semaphore sem(1); - RtosTimer timer(mbed::callback(timer_callback, (void const *) &sem), osTimerOnce); - osStatus stat = timer.stop(); - TEST_ASSERT_EQUAL(osErrorResource, stat); + Semaphore sem(0, 1); + RtosTimer rtostimer(mbed::callback(sem_callback, &sem), osTimerOnce); - sem.wait(0); - stat = timer.start(TEST_DELAY_MS); - TEST_ASSERT_EQUAL(osOK, stat); + osStatus status = rtostimer.start(DELAY_MS); + TEST_ASSERT_EQUAL(osOK, status); - int32_t slots = sem.wait(TEST_RESTART_DELAY_MS); + int32_t slots = sem.wait(RESTART_DELAY_MS); TEST_ASSERT_EQUAL(0, slots); - stat = timer.stop(); - TEST_ASSERT_EQUAL(osOK, stat); + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osOK, status); - slots = sem.wait(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); + slots = sem.wait(DELAY_MS + DELTA_MS); TEST_ASSERT_EQUAL(0, slots); - stat = timer.stop(); - TEST_ASSERT_EQUAL(osErrorResource, stat); + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osErrorResource, status); } /** Test timer started with infinite delay * - * Given a one-shot timer + * Given a one-shot RtosTimer * When the timer is started with @a osWaitForever delay * Then @a start return status is @a osOK */ void test_wait_forever() { - RtosTimer timer(mbed::callback(timer_callback, (void const *) NULL), osTimerOnce); + RtosTimer rtostimer(mbed::callback(sem_callback, (Semaphore *) NULL), osTimerOnce); - osStatus stat = timer.start(osWaitForever); - TEST_ASSERT_EQUAL(osOK, stat); + osStatus status = rtostimer.start(osWaitForever); + TEST_ASSERT_EQUAL(osOK, status); - stat = timer.stop(); - TEST_ASSERT_EQUAL(osOK, stat); + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osOK, status); } /** Test timer started with zero delay * - * Given a one-shot timer + * Given a one-shot RtosTimer * When the timer is started with 0 delay * Then @a start return status is @a osErrorParameter */ void test_no_wait() { - RtosTimer timer(mbed::callback(timer_callback, (void const *) NULL), osTimerOnce); + RtosTimer rtostimer(mbed::callback(sem_callback, (Semaphore *) NULL), osTimerOnce); - osStatus stat = timer.start(0); - TEST_ASSERT_EQUAL(osErrorParameter, stat); + osStatus status = rtostimer.start(0); + TEST_ASSERT_EQUAL(osErrorParameter, status); - stat = timer.stop(); - TEST_ASSERT_EQUAL(osErrorResource, stat); + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osErrorResource, status); } -void timer_isr_call(void const *arg) +void rtostimer_isr_call(RtosTimer *rtostimer) { - RtosTimer *timer = (RtosTimer *) arg; - osStatus stat = timer->start(TEST_DELAY_MS); - TEST_ASSERT_EQUAL(osErrorISR, stat); + osStatus status = rtostimer->start(DELAY_MS); + TEST_ASSERT_EQUAL(osErrorISR, status); - stat = timer->stop(); - TEST_ASSERT_EQUAL(osErrorISR, stat); + status = rtostimer->stop(); + TEST_ASSERT_EQUAL(osErrorISR, status); } /** Test timer method calls from an ISR fail * - * Given a one-shot timer + * Given a one-shot RtosTimer * When a timer method is called from an ISR * Then method return status is @a osErrorISR */ void test_isr_calls_fail() { - RtosTimer timer(mbed::callback(timer_callback, (void const *) NULL), osTimerOnce); + RtosTimer rtostimer(mbed::callback(sem_callback, (Semaphore *) NULL), osTimerOnce); Ticker ticker; - ticker.attach(mbed::callback(timer_isr_call, (void const *) &timer), (float) TEST_DELAY_MS / 1000.0); + ticker.attach(mbed::callback(rtostimer_isr_call, &rtostimer), (float) DELAY_MS / 1000.0); - wait_ms(TEST_DELAY_MS + TEST_DELAY_MS_DELTA); + wait_ms(DELAY_MS + DELTA_MS); } utest::v1::status_t test_setup(const size_t number_of_cases) @@ -347,16 +330,15 @@ utest::v1::status_t test_setup(const size_t number_of_cases) } Case cases[] = { - Case("Test one-shot not restarted when elapsed", test_oneshot_not_restarted), - Case("Test periodic repeats continuously", test_periodic_repeats), - Case("Test timer can be restarted while running", test_restart), - Case("Test stopped timer can be started again", test_start_again), - Case("Test restart changes timeout", test_restart_updates_delay), - Case("Test can be stopped", test_stop), - Case("Test timer is created in stopped state", test_created_stopped), - Case("Test timer started with infinite delay", test_wait_forever), - Case("Test timer started with zero delay", test_no_wait), - Case("Test calls from ISR fail", test_isr_calls_fail) + Case("One-shot not restarted when elapsed", test_oneshot_not_restarted), + Case("Periodic repeats continuously", test_periodic_repeats), + Case("Stopped timer can be started again", test_start_again), + Case("Restart changes timeout", test_restart_updates_delay), + Case("Timer can be stopped", test_stop), + Case("Timer is created in stopped state", test_created_stopped), + Case("Timer started with infinite delay", test_wait_forever), + Case("Timer started with zero delay", test_no_wait), + Case("Calls from ISR fail", test_isr_calls_fail) }; Specification specification(test_setup, cases); From 27d4b52a5f1e40e01164b1bbc904c223990b5837 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Fri, 6 Oct 2017 09:56:20 +0200 Subject: [PATCH 13/80] NUCLEO_L496ZG minor update --- .../TARGET_NUCLEO_L496ZG/PeripheralPins.c | 4 +-- .../TARGET_NUCLEO_L496ZG/PinNames.h | 9 +++++ .../TARGET_NUCLEO_L496ZG/system_clock.c | 35 +++++++++++++------ 3 files changed, 36 insertions(+), 12 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c index 4795a9c4d2..890c0e7842 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c @@ -258,8 +258,8 @@ const PinMap PinMap_UART_TX[] = { {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // ARDUINO D1 - {PG_7, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PG_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX + {PG_7, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX + {PG_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h index 741cd43383..e51ea37f50 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h @@ -266,6 +266,15 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_NOE_ALT = PA_13, + USB_OTG_FS_SOF_ALT = PA_14, + USB_OTG_FS_NOE = PC_9, + // Not connected NC = (int)0xFFFFFFFF } PinName; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c index e80f723dde..e8d5be0049 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c @@ -190,10 +190,10 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { return 0; // FAIL } @@ -217,6 +217,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update HAL_RCC_OscConfig(&RCC_OscInitStruct); + /* Select HSI as clock source for LPUART1 */ + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 2 if (bypass == 0) @@ -289,6 +296,13 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update HAL_RCC_OscConfig(&RCC_OscInitStruct); + /* Select HSI as clock source for LPUART1 */ + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 3 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz @@ -322,7 +336,6 @@ uint8_t SetSysClock_PLL_MSI(void) RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.HSEState = RCC_HSE_OFF; RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; @@ -342,11 +355,6 @@ uint8_t SetSysClock_PLL_MSI(void) PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - /* Select LSE as clock source for LPUART1 */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ @@ -357,6 +365,13 @@ uint8_t SetSysClock_PLL_MSI(void) return 0; // FAIL } + /* Select LSE as clock source for LPUART1 */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + return 0; // FAIL + } + // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 4 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz From 538208120635a2e0462e8a521be0ca8c64d6eb2d Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Fri, 3 Nov 2017 11:05:54 +0100 Subject: [PATCH 14/80] NUCLEO_L496ZG_P support --- targets/targets.json | 4 ++++ tools/export/sw4stm32/__init__.py | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/targets/targets.json b/targets/targets.json index dbfaa724fa..97ad2d6562 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3396,6 +3396,10 @@ "release_versions": ["2", "5"], "device_name": "STM32L496ZG" }, + "NUCLEO_L496ZG_P": { + "inherits": ["NUCLEO_L496ZG"], + "detect_code": ["0828"] + }, "VBLUNO52": { "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF52"], diff --git a/tools/export/sw4stm32/__init__.py b/tools/export/sw4stm32/__init__.py index ce15e09657..9d55dae8fe 100644 --- a/tools/export/sw4stm32/__init__.py +++ b/tools/export/sw4stm32/__init__.py @@ -259,6 +259,11 @@ class Sw4STM32(GNUARMEclipse): 'name': 'NUCLEO-L496ZG', 'mcuId': 'STM32L496ZGTx' }, + 'NUCLEO_L496ZG_P': + { + 'name': 'NUCLEO-L496ZG', + 'mcuId': 'STM32L496ZGTx' + }, } TARGETS = BOARDS.keys() From c4a034fba7d1d953b4e0da375b0d555089cf0c29 Mon Sep 17 00:00:00 2001 From: Boting Ren Date: Fri, 3 Nov 2017 05:15:38 +0900 Subject: [PATCH 15/80] Add mbed-cloud-client support on DISCO_L475VG_IOT01A with wifi_esp8266_v4.json. --- targets/targets.json | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 97ad2d6562..b66213ecac 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1606,7 +1606,8 @@ "macros_add": ["USBHOST_OTHER"], "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"], "release_versions": ["2", "5"], - "device_name": "STM32L475VG" + "device_name": "STM32L475VG", + "bootloader_supported": true }, "DISCO_L476VG": { "inherits": ["FAMILY_STM32"], From b66b28c08ace1527bd0c93e4438372d15ed4a712 Mon Sep 17 00:00:00 2001 From: Ryan Kurte Date: Fri, 6 Oct 2017 15:17:31 +1300 Subject: [PATCH 16/80] Threaded wrapper for rail driver on EFR32 platforms Updated NanostackRfPhyEfr32 with a receive queue. Cleaned up debug messages, re-added to non-threaded calls. Removed debug print override Removed tr_debug override Removed normal-operation prints that could have timing implications if enabled Removed dead NVIC code (and a couple of dead log outputs) --- .../TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp | 198 ++++++++++++++++-- 1 file changed, 176 insertions(+), 22 deletions(-) diff --git a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp index 875abbb48a..5b9805bf0a 100644 --- a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp +++ b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp @@ -14,6 +14,7 @@ * limitations under the License. */ #include "NanostackRfPhyEfr32.h" +#include "mbed.h" #include "ns_types.h" #include "platform/arm_hal_interrupt.h" #include "nanostack/platform/arm_hal_phy.h" @@ -23,6 +24,38 @@ #include "mbed-trace/mbed_trace.h" #define TRACE_GROUP "SLRF" +#ifndef RF_THREAD_STACK_SIZE +#define RF_THREAD_STACK_SIZE 1024 +#endif + +#ifndef RF_QUEUE_SIZE +#define RF_QUEUE_SIZE 8 +#endif + +enum RFThreadSignal { + SL_RX_DONE = (1 << 1), + SL_TX_DONE = (1 << 2), + SL_TX_ERR = (1 << 3), + SL_TX_TIMEOUT = (1 << 4), + SL_ACK_RECV = (1 << 5), + SL_ACK_TIMEOUT = (1 << 6), + SL_TXFIFO_ERR = (1 << 7), + SL_RXFIFO_ERR = (1 << 8), + SL_CAL_REQ = (1 << 9), + SL_RSSI_DONE = (1 << 10), + SL_QUEUE_FULL = (1 << 11), + + SL_ACK_PEND = (1 << 31), +}; + +static void rf_thread_loop(const void *arg); +static osThreadDef(rf_thread_loop, osPriorityRealtime, RF_THREAD_STACK_SIZE); +static osThreadId rf_thread_id; + +static volatile void* rx_queue[8]; +static volatile size_t rx_queue_head; +static volatile size_t rx_queue_tail; + /* Silicon Labs headers */ extern "C" { #include "rail/rail.h" @@ -64,10 +97,11 @@ typedef enum { static const RAIL_CsmaConfig_t csma_config = RAIL_CSMA_CONFIG_802_15_4_2003_2p4_GHz_OQPSK_CSMA; -#if defined(TARGET_EFR32MG1) +#if defined(TARGET_EFR32MG1) || defined(TARGET_EFR32FG1) #include "ieee802154_subg_efr32xg1_configurator_out.h" #include "ieee802154_efr32xg1_configurator_out.h" -#elif defined(TARGET_EFR32MG12) +#elif defined(TARGET_EFR32MG12) || defined(TARGET_EFR32FG12) +#include "ieee802154_efr32xg12_configurator_out.h" #include "ieee802154_efr32xg12_configurator_out.h" #else #error "Not a valid target." @@ -152,6 +186,76 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h /* Local function prototypes */ static bool rail_checkAndSwitchChannel(uint8_t channel); +static void rf_thread_loop(const void *arg) +{ + tr_debug("rf_thread_loop: starting (id: %d)\n", rf_thread_id); + for (;;) { + osEvent event = osSignalWait(0, osWaitForever); + + if (event.status != osEventSignal) { + continue; + } + + platform_enter_critical(); + + if (event.value.signals & SL_RX_DONE) { + while(rx_queue_tail != rx_queue_head) { + void* handle = (void*) rx_queue[rx_queue_tail]; + RAIL_RxPacketInfo_t* info = (RAIL_RxPacketInfo_t*) memoryPtrFromHandle(handle); + device_driver.phy_rx_cb( + info->dataPtr + 1, + info->dataLength - 1, + info->appendedInfo.lqi, + info->appendedInfo.rssiLatch, + rf_radio_driver_id); + + memoryFree(handle); + rx_queue[rx_queue_tail] = NULL; + + rx_queue_tail = (rx_queue_tail + 1) % RF_QUEUE_SIZE; + } + + } else if (event.value.signals & SL_TX_DONE) { + device_driver.phy_tx_done_cb(rf_radio_driver_id, + current_tx_handle, + PHY_LINK_TX_SUCCESS, + 1, + 1); + } else if (event.value.signals & SL_ACK_RECV) { + device_driver.phy_tx_done_cb( rf_radio_driver_id, + current_tx_handle, + (event.value.signals & SL_ACK_PEND) ? PHY_LINK_TX_DONE_PENDING : PHY_LINK_TX_DONE, + 1, + 1); + } else if (event.value.signals & SL_ACK_TIMEOUT) { + waiting_for_ack = false; + device_driver.phy_tx_done_cb(rf_radio_driver_id, + current_tx_handle, + PHY_LINK_TX_FAIL, + 1, + 1); + } else if(event.value.signals & SL_TX_ERR) { + device_driver.phy_tx_done_cb( rf_radio_driver_id, + current_tx_handle, + PHY_LINK_CCA_FAIL, + 8, + 1); + } else if(event.value.signals & SL_CAL_REQ) { + tr_debug("rf_thread_loop: SL_CAL_REQ signal received (unhandled)\n"); + } else if(event.value.signals & SL_RXFIFO_ERR) { + tr_debug("rf_thread_loop: SL_RXFIFO_ERR signal received (unhandled)\n"); + } else if(event.value.signals & SL_TXFIFO_ERR) { + tr_debug("rf_thread_loop: SL_TXFIFO_ERR signal received (unhandled)\n"); + } else if(event.value.signals & SL_QUEUE_FULL) { + tr_debug("rf_thread_loop: SL_QUEUE_FULL signal received (packet dropped)\n"); + } else { + tr_debug("rf_thread_loop unhandled event status: %d value: %d\n", event.status, event.value.signals); + } + + platform_exit_critical(); + } +} + /*============ CODE =========*/ /* @@ -168,6 +272,8 @@ static int8_t rf_device_register(void) return -1; } + tr_debug("rf_device_register: entry\n"); + #if MBED_CONF_SL_RAIL_BAND == 2400 RADIO_PA_Init((RADIO_PAInit_t*)&paInit2p4); #elif (MBED_CONF_SL_RAIL_BAND == 915) || (MBED_CONF_SL_RAIL_BAND == 868) @@ -254,6 +360,12 @@ static int8_t rf_device_register(void) radio_state = RADIO_INITING; } +#ifdef MBED_CONF_RTOS_PRESENT + rx_queue_head = 0; + rx_queue_tail = 0; + rf_thread_id = osThreadCreate(osThread(rf_thread_loop), NULL); +#endif + return rf_radio_driver_id; } @@ -288,26 +400,26 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h switch(radio_state) { case RADIO_UNINIT: - tr_debug("Radio uninit\n"); + tr_debug("rf_start_cca: Radio uninit\n"); return -1; case RADIO_INITING: - tr_debug("Radio initing\n"); + tr_debug("rf_start_cca: Radio initing\n"); return -1; case RADIO_CALIBRATION: - tr_debug("Radio calibrating\n"); + tr_debug("rf_start_cca: Radio calibrating\n"); return -1; case RADIO_TX: - tr_debug("Radio in TX mode\n"); + tr_debug("rf_start_cca: Radio in TX mode\n"); return -1; case RADIO_IDLE: case RADIO_RX: // If we're still waiting for an ACK, don't mess up the internal state if(waiting_for_ack || RAIL_RfStateGet() == RAIL_RF_STATE_TX) { if((RAIL_GetTime() - last_tx) < 30000) { - tr_debug("Still waiting on previous ACK\n"); + tr_debug("rf_start_cca: Still waiting on previous ACK\n"); return -1; } else { - tr_debug("TXerr\n"); + tr_debug("rf_start_cca: TXerr\n"); } } @@ -325,7 +437,7 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h txOpt.waitForAck = false; } - //tr_debug("Called TX, len %d, chan %d, ack %d\n", data_length, channel, waiting_for_ack ? 1 : 0); + tr_debug("rf_start_cca: Called TX, len %d, chan %d, ack %d\n", data_length, channel, waiting_for_ack ? 1 : 0); if(RAIL_TxStartWithOptions(channel, &txOpt, &RAIL_CcaCsma, (RAIL_CsmaConfig_t*) &csma_config) == 0) { //Save packet number and sequence @@ -378,7 +490,7 @@ static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_ break; /* Enable wireless interface ED scan mode */ case PHY_INTERFACE_RX_ENERGY_STATE: - tr_debug("Energy det req\n"); + tr_debug("rf_interface_state_control: Energy det req\n"); // TODO: implement energy detection break; /* Enable RX in promiscuous mode (aka no address filtering) */ @@ -435,12 +547,15 @@ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_pt /* Read status of the link */ case PHY_EXTENSION_READ_LINK_STATUS: // TODO: return accurate value here - tr_debug("Trying to read link status\n"); + tr_debug("rf_extension: Trying to read link status\n"); break; /* Convert between LQI and RSSI */ case PHY_EXTENSION_CONVERT_SIGNAL_INFO: // TODO: return accurate value here - tr_debug("Trying to read signal info\n"); + tr_debug("rf_extension: Trying to read signal info\n"); + break; + case PHY_EXTENSION_ACCEPT_ANY_BEACON: + tr_debug("rf_extension: Trying to accept any beacon\n"); break; } return 0; @@ -468,7 +583,7 @@ static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address case PHY_MAC_64BIT: /* Store MAC in MSB order */ memcpy(MAC_address, address_ptr, 8); - tr_debug("MACw "); + tr_debug("rf_address_write: MACw "); for(unsigned int i = 0; i < sizeof(MAC_address); i ++) { tr_debug("%02x:", MAC_address[i]); } @@ -483,13 +598,11 @@ static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address /*Set 16-bit address*/ case PHY_MAC_16BIT: short_address = address_ptr[0] << 8 | address_ptr[1]; - tr_debug("Filter EUI16 %04x\n", short_address); RAIL_IEEE802154_SetShortAddress(short_address); break; /*Set PAN Id*/ case PHY_MAC_PANID: PAN_address = address_ptr[0] << 8 | address_ptr[1]; - tr_debug("Filter PAN %04x\n", PAN_address); RAIL_IEEE802154_SetPanId(PAN_address); break; } @@ -618,7 +731,11 @@ void RAILCb_TxRadioStatus(uint8_t status) { status == RAIL_TX_CONFIG_TX_ABORTED || status == RAIL_TX_CONFIG_TX_BLOCKED) { waiting_for_ack = false; - device_driver.phy_tx_done_cb( rf_radio_driver_id, +#ifdef MBED_CONF_RTOS_PRESENT + osSignalSet(rf_thread_id, SL_TX_ERR); + } +#else + device_driver.phy_tx_done_cb(rf_radio_driver_id, current_tx_handle, PHY_LINK_CCA_FAIL, 8, @@ -626,6 +743,7 @@ void RAILCb_TxRadioStatus(uint8_t status) { } else { tr_debug("Packet TX error %d\n", status); } +#endif } radio_state = RADIO_RX; } @@ -648,7 +766,6 @@ void RAILCb_RxRadioStatus(uint8_t status) { case RAIL_RX_CONFIG_ADDRESS_FILTERED: break; default: - tr_debug("RXE %d\n", status); break; } } @@ -663,7 +780,11 @@ void RAILCb_RxRadioStatus(uint8_t status) { */ void RAILCb_CalNeeded(void) { // TODO: Implement on-the-fly recalibration +#ifdef MBED_CONF_RTOS_PRESENT + osSignalSet(rf_thread_id, SL_CAL_REQ); +#else tr_debug("!!!! Calling for calibration\n"); +#endif } /** @@ -691,6 +812,9 @@ void RAILCb_TimerExpired(void) { * callback. */ void RAILCb_TxPacketSent(RAIL_TxPacketInfo_t *txPacketInfo) { +#ifdef MBED_CONF_RTOS_PRESENT + osSignalSet(rf_thread_id, SL_TX_DONE); +#else if(device_driver.phy_tx_done_cb != NULL) { device_driver.phy_tx_done_cb( rf_radio_driver_id, current_tx_handle, @@ -700,6 +824,7 @@ void RAILCb_TxPacketSent(RAIL_TxPacketInfo_t *txPacketInfo) { 1, 1); } +#endif last_tx = RAIL_GetTime(); radio_state = RADIO_RX; } @@ -731,12 +856,16 @@ void RAILCb_RxPacketReceived(void *rxPacketHandle) { /* Save the pending bit */ last_ack_pending_bit = (rxPacketInfo->dataPtr[1] & (1 << 4)) != 0; /* Tell the stack we got an ACK */ - //tr_debug("rACK\n"); +#ifdef MBED_CONF_RTOS_PRESENT + osSignalSet(rf_thread_id, SL_ACK_RECV | SL_ACK_PEND); +#else + tr_debug("rACK\n"); device_driver.phy_tx_done_cb( rf_radio_driver_id, current_tx_handle, last_ack_pending_bit ? PHY_LINK_TX_DONE_PENDING : PHY_LINK_TX_DONE, 1, 1); +#endif } else { /* Figure out whether we want to not ACK this packet */ @@ -752,14 +881,24 @@ void RAILCb_RxPacketReceived(void *rxPacketHandle) { RAIL_AutoAckCancelAck(); } - //tr_debug("rPKT %d\n", rxPacketInfo->dataLength); /* Feed the received packet into the stack */ +#ifdef MBED_CONF_RTOS_PRESENT + if (((rx_queue_head + 1) % RF_QUEUE_SIZE) != rx_queue_tail) { + memoryTakeReference(rxPacketHandle); + rx_queue[rx_queue_head] = rxPacketHandle; + rx_queue_head = (rx_queue_head + 1) % RF_QUEUE_SIZE; + osSignalSet(rf_thread_id, SL_RX_DONE); + } else { + osSignalSet(rf_thread_id, SL_QUEUE_FULL); + } +#else + tr_debug("rPKT %d\n", rxPacketInfo->dataLength); device_driver.phy_rx_cb(rxPacketInfo->dataPtr + 1, rxPacketInfo->dataLength - 1, - //TODO: take a new RAIL release that exposes LQI, or have LQI as function of RSSI - 255, + rxPacketInfo->appendedInfo.lqi, rxPacketInfo->appendedInfo.rssiLatch, rf_radio_driver_id); +#endif } } } @@ -792,13 +931,16 @@ void RAILCb_IEEE802154_DataRequestCommand(RAIL_IEEE802154_Address_t *address) { */ void RAILCb_RxAckTimeout(void) { if(waiting_for_ack) { - tr_debug("nACK\n"); waiting_for_ack = false; +#ifdef MBED_CONF_RTOS_PRESENT + osSignalSet(rf_thread_id, SL_ACK_TIMEOUT); +#else device_driver.phy_tx_done_cb( rf_radio_driver_id, current_tx_handle, PHY_LINK_TX_FAIL, 1, 1); +#endif } } @@ -849,7 +991,11 @@ static bool rail_checkAndSwitchChannel(uint8_t newChannel) { * time of the callback dispatch. */ void RAILCb_RxFifoAlmostFull(uint16_t bytesAvailable) { +#ifdef MBED_CONF_RTOS_PRESENT + osSignalSet(rf_thread_id, SL_RXFIFO_ERR); +#else tr_debug("RX near full (%d)\n", bytesAvailable); +#endif } /** @@ -871,7 +1017,11 @@ void RAILCb_RxFifoAlmostFull(uint16_t bytesAvailable) { * callback dispatch. */ void RAILCb_TxFifoAlmostEmpty(uint16_t spaceAvailable) { +#ifdef MBED_CONF_RTOS_PRESENT + osSignalSet(rf_thread_id, SL_TXFIFO_ERR); +#else tr_debug("TX near empty (%d)\n", spaceAvailable); +#endif } /** @@ -886,5 +1036,9 @@ void RAILCb_TxFifoAlmostEmpty(uint16_t spaceAvailable) { * get the result. */ void RAILCb_RssiAverageDone(int16_t avgRssi) { +#ifdef MBED_CONF_RTOS_PRESENT + osSignalSet(rf_thread_id, SL_RSSI_DONE); +#else tr_debug("RSSI done (%d)\n", avgRssi); +#endif } \ No newline at end of file From b1c4fa3f3429a2379bd068fcd8ab508de4abdfe6 Mon Sep 17 00:00:00 2001 From: Ryan Kurte Date: Thu, 12 Oct 2017 10:15:12 +1300 Subject: [PATCH 17/80] Added critical section around rf_start_cca --- .../targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp index 5b9805bf0a..117ccdf306 100644 --- a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp +++ b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp @@ -211,7 +211,6 @@ static void rf_thread_loop(const void *arg) memoryFree(handle); rx_queue[rx_queue_tail] = NULL; - rx_queue_tail = (rx_queue_tail + 1) % RF_QUEUE_SIZE; } @@ -423,6 +422,8 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h } } + platform_enter_critical(); + data_ptr[0] = data_length + 2; RAIL_RfIdleExt(RAIL_IDLE_ABORT , true); RAIL_TxDataLoad(&txData); @@ -443,15 +444,18 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h //Save packet number and sequence current_tx_handle = tx_handle; current_tx_sequence = data_ptr[3]; + platform_exit_critical(); return 0; } else { RAIL_RfIdle(); RAIL_RxStart(channel); radio_state = RADIO_RX; + platform_exit_critical(); return -1; } } //Should never get here... + platform_exit_critical(); return -1; } From a95fcbf40bfcf17bbc2c15110afbe5eb348bd54e Mon Sep 17 00:00:00 2001 From: Ryan Kurte Date: Wed, 1 Nov 2017 11:02:08 +1300 Subject: [PATCH 18/80] Swapped to macro definition for debug prints --- .../TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp | 76 ++++++++++++------- 1 file changed, 47 insertions(+), 29 deletions(-) diff --git a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp index 117ccdf306..3b91b01aa6 100644 --- a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp +++ b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp @@ -14,24 +14,39 @@ * limitations under the License. */ #include "NanostackRfPhyEfr32.h" + +#include + #include "mbed.h" #include "ns_types.h" #include "platform/arm_hal_interrupt.h" #include "nanostack/platform/arm_hal_phy.h" #include "mbed_toolchain.h" -#include #include "mbed-trace/mbed_trace.h" #define TRACE_GROUP "SLRF" +/* Enable debug printing with SL_RADIO_DEBUG, override debug printer with SL_DEBUG_PRINT. */ +#ifdef SL_RADIO_DEBUG +#ifndef SL_DEBUG_PRINT +#define SL_DEBUG_PRINT(...) tr_debug(__VA_ARGS__) +#endif +#else +#define SL_DEBUG_PRINT(...) +#endif + +/* RF_THREAD_STACK_SIZE defines tack size for the RF adaptor thread */ #ifndef RF_THREAD_STACK_SIZE #define RF_THREAD_STACK_SIZE 1024 #endif +/* RF_QUEUE_SIZE defines queue size for incoming messages */ #ifndef RF_QUEUE_SIZE #define RF_QUEUE_SIZE 8 #endif + +/* RFThreadSignal used to signal from interrupts to the adaptor thread */ enum RFThreadSignal { SL_RX_DONE = (1 << 1), SL_TX_DONE = (1 << 2), @@ -45,13 +60,16 @@ enum RFThreadSignal { SL_RSSI_DONE = (1 << 10), SL_QUEUE_FULL = (1 << 11), + // ACK pend flag can be signalled in addition to RX_DONE SL_ACK_PEND = (1 << 31), }; +/* Adaptor thread definitions */ static void rf_thread_loop(const void *arg); static osThreadDef(rf_thread_loop, osPriorityRealtime, RF_THREAD_STACK_SIZE); static osThreadId rf_thread_id; +/* Queue for passing messages from interrupt to adaptor thread */ static volatile void* rx_queue[8]; static volatile size_t rx_queue_head; static volatile size_t rx_queue_tail; @@ -188,7 +206,7 @@ static bool rail_checkAndSwitchChannel(uint8_t channel); static void rf_thread_loop(const void *arg) { - tr_debug("rf_thread_loop: starting (id: %d)\n", rf_thread_id); + SL_DEBUG_PRINT("rf_thread_loop: starting (id: %d)\n", rf_thread_id); for (;;) { osEvent event = osSignalWait(0, osWaitForever); @@ -240,15 +258,15 @@ static void rf_thread_loop(const void *arg) 8, 1); } else if(event.value.signals & SL_CAL_REQ) { - tr_debug("rf_thread_loop: SL_CAL_REQ signal received (unhandled)\n"); + SL_DEBUG_PRINT("rf_thread_loop: SL_CAL_REQ signal received (unhandled)\n"); } else if(event.value.signals & SL_RXFIFO_ERR) { - tr_debug("rf_thread_loop: SL_RXFIFO_ERR signal received (unhandled)\n"); + SL_DEBUG_PRINT("rf_thread_loop: SL_RXFIFO_ERR signal received (unhandled)\n"); } else if(event.value.signals & SL_TXFIFO_ERR) { - tr_debug("rf_thread_loop: SL_TXFIFO_ERR signal received (unhandled)\n"); + SL_DEBUG_PRINT("rf_thread_loop: SL_TXFIFO_ERR signal received (unhandled)\n"); } else if(event.value.signals & SL_QUEUE_FULL) { - tr_debug("rf_thread_loop: SL_QUEUE_FULL signal received (packet dropped)\n"); + SL_DEBUG_PRINT("rf_thread_loop: SL_QUEUE_FULL signal received (packet dropped)\n"); } else { - tr_debug("rf_thread_loop unhandled event status: %d value: %d\n", event.status, event.value.signals); + SL_DEBUG_PRINT("rf_thread_loop unhandled event status: %d value: %d\n", event.status, event.value.signals); } platform_exit_critical(); @@ -271,7 +289,7 @@ static int8_t rf_device_register(void) return -1; } - tr_debug("rf_device_register: entry\n"); + SL_DEBUG_PRINT("rf_device_register: entry\n"); #if MBED_CONF_SL_RAIL_BAND == 2400 RADIO_PA_Init((RADIO_PAInit_t*)&paInit2p4); @@ -399,26 +417,26 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h switch(radio_state) { case RADIO_UNINIT: - tr_debug("rf_start_cca: Radio uninit\n"); + SL_DEBUG_PRINT("rf_start_cca: Radio uninit\n"); return -1; case RADIO_INITING: - tr_debug("rf_start_cca: Radio initing\n"); + SL_DEBUG_PRINT("rf_start_cca: Radio initing\n"); return -1; case RADIO_CALIBRATION: - tr_debug("rf_start_cca: Radio calibrating\n"); + SL_DEBUG_PRINT("rf_start_cca: Radio calibrating\n"); return -1; case RADIO_TX: - tr_debug("rf_start_cca: Radio in TX mode\n"); + SL_DEBUG_PRINT("rf_start_cca: Radio in TX mode\n"); return -1; case RADIO_IDLE: case RADIO_RX: // If we're still waiting for an ACK, don't mess up the internal state if(waiting_for_ack || RAIL_RfStateGet() == RAIL_RF_STATE_TX) { if((RAIL_GetTime() - last_tx) < 30000) { - tr_debug("rf_start_cca: Still waiting on previous ACK\n"); + SL_DEBUG_PRINT("rf_start_cca: Still waiting on previous ACK\n"); return -1; } else { - tr_debug("rf_start_cca: TXerr\n"); + SL_DEBUG_PRINT("rf_start_cca: TXerr\n"); } } @@ -438,7 +456,7 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h txOpt.waitForAck = false; } - tr_debug("rf_start_cca: Called TX, len %d, chan %d, ack %d\n", data_length, channel, waiting_for_ack ? 1 : 0); + SL_DEBUG_PRINT("rf_start_cca: Called TX, len %d, chan %d, ack %d\n", data_length, channel, waiting_for_ack ? 1 : 0); if(RAIL_TxStartWithOptions(channel, &txOpt, &RAIL_CcaCsma, (RAIL_CsmaConfig_t*) &csma_config) == 0) { //Save packet number and sequence @@ -494,7 +512,7 @@ static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_ break; /* Enable wireless interface ED scan mode */ case PHY_INTERFACE_RX_ENERGY_STATE: - tr_debug("rf_interface_state_control: Energy det req\n"); + SL_DEBUG_PRINT("rf_interface_state_control: Energy det req\n"); // TODO: implement energy detection break; /* Enable RX in promiscuous mode (aka no address filtering) */ @@ -551,15 +569,15 @@ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_pt /* Read status of the link */ case PHY_EXTENSION_READ_LINK_STATUS: // TODO: return accurate value here - tr_debug("rf_extension: Trying to read link status\n"); + SL_DEBUG_PRINT("rf_extension: Trying to read link status\n"); break; /* Convert between LQI and RSSI */ case PHY_EXTENSION_CONVERT_SIGNAL_INFO: // TODO: return accurate value here - tr_debug("rf_extension: Trying to read signal info\n"); + SL_DEBUG_PRINT("rf_extension: Trying to read signal info\n"); break; case PHY_EXTENSION_ACCEPT_ANY_BEACON: - tr_debug("rf_extension: Trying to accept any beacon\n"); + SL_DEBUG_PRINT("rf_extension: Trying to accept any beacon\n"); break; } return 0; @@ -587,11 +605,11 @@ static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address case PHY_MAC_64BIT: /* Store MAC in MSB order */ memcpy(MAC_address, address_ptr, 8); - tr_debug("rf_address_write: MACw "); + SL_DEBUG_PRINT("rf_address_write: MACw "); for(unsigned int i = 0; i < sizeof(MAC_address); i ++) { - tr_debug("%02x:", MAC_address[i]); + SL_DEBUG_PRINT("%02x:", MAC_address[i]); } - tr_debug("\n"); + SL_DEBUG_PRINT("\n"); /* Pass MAC to the RF driver in LSB order */ uint8_t MAC_reversed[8]; for(unsigned int i = 0; i < sizeof(MAC_address); i ++) { @@ -745,7 +763,7 @@ void RAILCb_TxRadioStatus(uint8_t status) { 8, 1); } else { - tr_debug("Packet TX error %d\n", status); + SL_DEBUG_PRINT("Packet TX error %d\n", status); } #endif } @@ -787,7 +805,7 @@ void RAILCb_CalNeeded(void) { #ifdef MBED_CONF_RTOS_PRESENT osSignalSet(rf_thread_id, SL_CAL_REQ); #else - tr_debug("!!!! Calling for calibration\n"); + SL_DEBUG_PRINT("!!!! Calling for calibration\n"); #endif } @@ -863,7 +881,7 @@ void RAILCb_RxPacketReceived(void *rxPacketHandle) { #ifdef MBED_CONF_RTOS_PRESENT osSignalSet(rf_thread_id, SL_ACK_RECV | SL_ACK_PEND); #else - tr_debug("rACK\n"); + SL_DEBUG_PRINT("rACK\n"); device_driver.phy_tx_done_cb( rf_radio_driver_id, current_tx_handle, last_ack_pending_bit ? PHY_LINK_TX_DONE_PENDING : PHY_LINK_TX_DONE, @@ -896,7 +914,7 @@ void RAILCb_RxPacketReceived(void *rxPacketHandle) { osSignalSet(rf_thread_id, SL_QUEUE_FULL); } #else - tr_debug("rPKT %d\n", rxPacketInfo->dataLength); + SL_DEBUG_PRINT("rPKT %d\n", rxPacketInfo->dataLength); device_driver.phy_rx_cb(rxPacketInfo->dataPtr + 1, rxPacketInfo->dataLength - 1, rxPacketInfo->appendedInfo.lqi, @@ -998,7 +1016,7 @@ void RAILCb_RxFifoAlmostFull(uint16_t bytesAvailable) { #ifdef MBED_CONF_RTOS_PRESENT osSignalSet(rf_thread_id, SL_RXFIFO_ERR); #else - tr_debug("RX near full (%d)\n", bytesAvailable); + SL_DEBUG_PRINT("RX near full (%d)\n", bytesAvailable); #endif } @@ -1024,7 +1042,7 @@ void RAILCb_TxFifoAlmostEmpty(uint16_t spaceAvailable) { #ifdef MBED_CONF_RTOS_PRESENT osSignalSet(rf_thread_id, SL_TXFIFO_ERR); #else - tr_debug("TX near empty (%d)\n", spaceAvailable); + SL_DEBUG_PRINT("TX near empty (%d)\n", spaceAvailable); #endif } @@ -1043,6 +1061,6 @@ void RAILCb_RssiAverageDone(int16_t avgRssi) { #ifdef MBED_CONF_RTOS_PRESENT osSignalSet(rf_thread_id, SL_RSSI_DONE); #else - tr_debug("RSSI done (%d)\n", avgRssi); + SL_DEBUG_PRINT("RSSI done (%d)\n", avgRssi); #endif } \ No newline at end of file From bb3bd003c515f40a6087f3644cb5604c5a813648 Mon Sep 17 00:00:00 2001 From: Martin Kojtal <0xc0170@gmail.com> Date: Fri, 27 Oct 2017 17:46:24 +0100 Subject: [PATCH 19/80] ncs36510: fire interrupt correct timer fix Use Timer1, it is used for us ticker isr handling. Plus reset target counter, that should be 0, go to upper ticker isr handler immediately. --- targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c index 75fa1b398b..e0b07b9cbc 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c @@ -130,7 +130,8 @@ uint32_t us_ticker_read() void us_ticker_fire_interrupt(void) { - NVIC_SetPendingIRQ(Tim0_IRQn); + us_ticker_target = 0; + NVIC_SetPendingIRQ(Tim1_IRQn); } /******************************************************************************* From d3ca63edd58b19d9305ff1a527cd59a47ccaa88b Mon Sep 17 00:00:00 2001 From: Senthil Ramakrishnan Date: Tue, 24 Oct 2017 10:05:45 -0500 Subject: [PATCH 20/80] Doxygen comment updates and fixes --- doxyfile_options | 2 +- drivers/UARTSerial.h | 7 +++++++ platform/ATCmdParser.h | 16 ++++++++++++++-- platform/CThunk.h | 10 ++++++++-- platform/CallChain.h | 19 ++++++++++++++----- platform/Callback.h | 16 ++++++++-------- platform/CircularBuffer.h | 10 +++++++++- platform/CriticalSectionLock.h | 10 ++++++++++ platform/DeepSleepLock.h | 11 +++++++++++ platform/DirHandle.h | 8 +++++++- platform/FileBase.h | 19 +++++++++++++------ platform/FileHandle.h | 11 ++++++++++- platform/FileLike.h | 14 ++++++++++---- platform/FilePath.h | 20 ++++++++++++++++---- platform/FileSystemHandle.h | 6 ++++++ platform/FileSystemLike.h | 9 ++++++++- platform/FunctionPointer.h | 16 +++++++++------- platform/LocalFileSystem.h | 9 ++++++++- platform/PlatformMutex.h | 9 ++++++++- platform/SingletonPtr.h | 8 ++++++-- platform/Stream.h | 8 ++++++-- platform/Transaction.h | 9 +++++++-- platform/mbed_application.h | 5 +---- platform/mbed_assert.h | 22 +++++++++++++++++++++- platform/mbed_critical.h | 13 ++++++++++--- platform/mbed_debug.h | 10 +++++++++- platform/mbed_error.h | 5 +++++ platform/mbed_interface.h | 11 +++++++++++ platform/mbed_mem_trace.h | 8 ++++++++ platform/mbed_mktime.h | 7 +++++++ platform/mbed_poll.h | 10 +++++++++- platform/mbed_preprocessor.h | 6 ++++++ platform/mbed_retarget.h | 12 ++++++++++++ platform/mbed_rtc_time.h | 5 +++++ platform/mbed_semihost_api.h | 4 +--- platform/mbed_sleep.h | 6 ++++++ platform/mbed_stats.h | 12 ++++++++++++ platform/mbed_toolchain.h | 6 ++++++ platform/mbed_wait_api.h | 6 ++++++ rtos/EventFlags.h | 10 ++++++++-- rtos/Mail.h | 11 +++++++++-- rtos/MemoryPool.h | 10 ++++++++-- rtos/Mutex.h | 11 ++++++++--- rtos/Queue.h | 9 +++++++-- rtos/RtosTimer.h | 10 ++++++++-- rtos/Semaphore.h | 9 +++++++-- rtos/Thread.h | 9 +++++++-- rtos/rtos_idle.h | 11 +++++++++++ 48 files changed, 404 insertions(+), 81 deletions(-) diff --git a/doxyfile_options b/doxyfile_options index be46e1346e..4ee6b29a87 100644 --- a/doxyfile_options +++ b/doxyfile_options @@ -32,7 +32,7 @@ DOXYFILE_ENCODING = UTF-8 # title of most generated pages and in a few other places. # The default value is: My Project. -PROJECT_NAME = "My Project" +PROJECT_NAME = "Mbed OS Reference" # The PROJECT_NUMBER tag can be used to enter a project or revision number. This # could be handy for archiving the generated documentation or if some version diff --git a/drivers/UARTSerial.h b/drivers/UARTSerial.h index c0069adcb7..f6ff523f8f 100644 --- a/drivers/UARTSerial.h +++ b/drivers/UARTSerial.h @@ -39,6 +39,13 @@ namespace mbed { +/** \addtogroup drivers */ + +/** Class providing buffered UART communication functionality using separate circular buffer for send and receive channels + * + * @ingroup drivers + */ + class UARTSerial : private SerialBase, public FileHandle, private NonCopyable { public: diff --git a/platform/ATCmdParser.h b/platform/ATCmdParser.h index 1201a6055f..c8fb040634 100644 --- a/platform/ATCmdParser.h +++ b/platform/ATCmdParser.h @@ -24,6 +24,15 @@ #include #include "Callback.h" +namespace mbed { + +/** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_ATCmdParser ATCmdParser class + * @{ + */ + /** * Parser class for parsing AT commands * @@ -43,8 +52,6 @@ * @endcode */ -namespace mbed { - class ATCmdParser : private NonCopyable { private: @@ -299,6 +306,11 @@ public: */ bool process_oob(void); }; + +/**@}*/ + +/**@}*/ + } //namespace mbed #endif //MBED_ATCMDPARSER_H diff --git a/platform/CThunk.h b/platform/CThunk.h index 90e150b6a9..73c3aba138 100644 --- a/platform/CThunk.h +++ b/platform/CThunk.h @@ -1,6 +1,10 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_CThunk CThunk class + * @{ + */ /* General C++ Object Thunking class * * - allows direct callbacks to non-static C++ class functions @@ -73,13 +77,11 @@ /* IRQ/Exception compatible thunk entry function */ typedef void (*CThunkEntry)(void); -/** @}*/ /** * Class for created a pointer with data bound to it * * @note Synchronization level: Not protected - * @ingroup platform */ template class CThunk @@ -243,5 +245,9 @@ class CThunk } }; +/**@}*/ + +/**@}*/ + #endif/*__CTHUNK_H__*/ diff --git a/platform/CallChain.h b/platform/CallChain.h index 42e97e6d28..ffb786d2c2 100644 --- a/platform/CallChain.h +++ b/platform/CallChain.h @@ -22,7 +22,17 @@ #include namespace mbed { + + +typedef Callback *pFunctionPointer_t; +class CallChainLink; + /** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_CallChain CallChain class + * @{ + */ /** Group one or more functions in an instance of a CallChain, then call them in * sequence using CallChain::call(). Used mostly by the interrupt chaining code, @@ -60,12 +70,7 @@ namespace mbed { * chain.call(); * } * @endcode - * @ingroup platform */ - -typedef Callback *pFunctionPointer_t; -class CallChainLink; - class CallChain : private NonCopyable { public: /** Create an empty chain @@ -183,6 +188,10 @@ private: CallChainLink *_chain; }; +/**@}*/ + +/**@}*/ + } // namespace mbed #endif diff --git a/platform/Callback.h b/platform/Callback.h index cb2c5a95b3..b300afefad 100644 --- a/platform/Callback.h +++ b/platform/Callback.h @@ -24,12 +24,15 @@ namespace mbed { /** \addtogroup platform */ - +/** @{*/ +/** + * \defgroup platform_Callback Callback class + * @{ + */ /** Callback class based on template specialization * * @note Synchronization level: Not protected - * @ingroup platform */ template class Callback; @@ -67,7 +70,6 @@ namespace detail { /** Callback class based on template specialization * * @note Synchronization level: Not protected - * @ingroup platform */ template class Callback { @@ -642,7 +644,6 @@ private: /** Callback class based on template specialization * * @note Synchronization level: Not protected - * @ingroup platform */ template class Callback { @@ -1218,7 +1219,6 @@ private: /** Callback class based on template specialization * * @note Synchronization level: Not protected - * @ingroup platform */ template class Callback { @@ -1795,7 +1795,6 @@ private: /** Callback class based on template specialization * * @note Synchronization level: Not protected - * @ingroup platform */ template class Callback { @@ -2373,7 +2372,6 @@ private: /** Callback class based on template specialization * * @note Synchronization level: Not protected - * @ingroup platform */ template class Callback { @@ -2952,7 +2950,6 @@ private: /** Callback class based on template specialization * * @note Synchronization level: Not protected - * @ingroup platform */ template class Callback { @@ -4546,6 +4543,9 @@ Callback callback(const volatile U *obj, R (*func)(const return Callback(func, obj); } +/**@}*/ + +/**@}*/ } // namespace mbed diff --git a/platform/CircularBuffer.h b/platform/CircularBuffer.h index bb7fd38c54..b721791b81 100644 --- a/platform/CircularBuffer.h +++ b/platform/CircularBuffer.h @@ -20,11 +20,15 @@ namespace mbed { /** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_CircularBuffer CircularBuffer functions + * @{ + */ /** Templated Circular buffer class * * @note Synchronization level: Interrupt safe - * @ingroup platform */ template class CircularBuffer { @@ -112,6 +116,10 @@ private: volatile bool _full; }; +/**@}*/ + +/**@}*/ + } #endif diff --git a/platform/CriticalSectionLock.h b/platform/CriticalSectionLock.h index 5199fbaf69..cb619769c8 100644 --- a/platform/CriticalSectionLock.h +++ b/platform/CriticalSectionLock.h @@ -22,6 +22,13 @@ namespace mbed { +/** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_CriticalSectionLock CriticalSectionLock functions + * @{ + */ + /** RAII object for disabling, then restoring, interrupt state * Usage: * @code @@ -65,6 +72,9 @@ public: } }; +/**@}*/ + +/**@}*/ } // namespace mbed diff --git a/platform/DeepSleepLock.h b/platform/DeepSleepLock.h index 17abe15614..6b64022fc0 100644 --- a/platform/DeepSleepLock.h +++ b/platform/DeepSleepLock.h @@ -22,6 +22,12 @@ namespace mbed { +/** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_DeepSleepLock DeepSleepLock functions + * @{ + */ /** RAII object for disabling, then restoring the deep sleep mode * Usage: @@ -82,6 +88,11 @@ public: } }; +/**@}*/ + +/**@}*/ + + } #endif diff --git a/platform/DirHandle.h b/platform/DirHandle.h index b1dcfe2b1f..116ebf581d 100644 --- a/platform/DirHandle.h +++ b/platform/DirHandle.h @@ -23,6 +23,11 @@ namespace mbed { /** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_DirHandle DirHandle functions + * @{ + */ /** Represents a directory stream. Objects of this type are returned @@ -40,7 +45,6 @@ namespace mbed { * * @note to create a directory, @see Dir * @note Synchronization level: Set by subclass - * @ingroup platform */ class DirHandle : private NonCopyable { public: @@ -142,7 +146,9 @@ public: virtual void seekdir(off_t location) { seek(location); } }; +/**@}*/ +/**@}*/ } // namespace mbed #endif /* MBED_DIRHANDLE_H */ diff --git a/platform/FileBase.h b/platform/FileBase.h index 5df9ef8550..4f6371923b 100644 --- a/platform/FileBase.h +++ b/platform/FileBase.h @@ -27,19 +27,22 @@ typedef int FILEHANDLE; #include "platform/NonCopyable.h" namespace mbed { -/** \addtogroup platform */ -/** @{*/ - + typedef enum { FilePathType, FileSystemPathType } PathType; -/** @}*/ +/** \addtogroup platform */ +/** @{*/ /** - * @class FileBase - * @ingroup platform + * \defgroup platform_FileBase FileBase class + * @{ */ +/** Class FileBase + * + */ + class FileBase : private NonCopyable { public: FileBase(const char *name, PathType t); @@ -62,6 +65,10 @@ private: const PathType _path_type; }; +/**@}*/ + +/**@}*/ + } // namespace mbed #endif diff --git a/platform/FileHandle.h b/platform/FileHandle.h index a6b306b3fa..6a769b4b8f 100644 --- a/platform/FileHandle.h +++ b/platform/FileHandle.h @@ -26,6 +26,11 @@ typedef int FILEHANDLE; namespace mbed { /** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_FileHandle FileHandle functions + * @{ + */ /** Class FileHandle @@ -36,7 +41,6 @@ namespace mbed { * * @note to create a file, @see File * @note Synchronization level: Set by subclass - * @ingroup platform */ class FileHandle : private NonCopyable { public: @@ -254,6 +258,11 @@ public: std::FILE *fdopen(FileHandle *fh, const char *mode); +/**@}*/ + +/**@}*/ + + } // namespace mbed #endif diff --git a/platform/FileLike.h b/platform/FileLike.h index 91a3f304d0..e75be50bfd 100644 --- a/platform/FileLike.h +++ b/platform/FileLike.h @@ -23,14 +23,17 @@ namespace mbed { /** \addtogroup platform */ - - -/* Class FileLike +/** @{*/ +/** + * \defgroup platform_FileLike FileLike class + * @{ + */ +/** Class FileLike + * * A file-like object is one that can be opened with fopen by * fopen("/name", mode). * * @note Synchronization level: Set by subclass - * @ingroup platform */ class FileLike : public FileHandle, public FileBase, private NonCopyable { public: @@ -42,6 +45,9 @@ public: virtual ~FileLike() {} }; +/**@}*/ + +/**@}*/ } // namespace mbed diff --git a/platform/FilePath.h b/platform/FilePath.h index 4c4dc65e15..d380041ca0 100644 --- a/platform/FilePath.h +++ b/platform/FilePath.h @@ -23,15 +23,23 @@ namespace mbed { /** \addtogroup platform */ - +/** @{*/ /** - * @class FileSystem - * @ingroup platform + * \defgroup platform_FilePath FilePath class + * @{ */ -class FileSystem; +class FileSystem; +/** Class FilePath + * + */ + class FilePath { public: + /** Constructor FilePath + * + * @param file_path The path of file. + */ FilePath(const char* file_path); const char* fileName(void); @@ -48,6 +56,10 @@ private: FileBase* fb; }; +/**@}*/ + +/**@}*/ + } // namespace mbed #endif diff --git a/platform/FileSystemHandle.h b/platform/FileSystemHandle.h index bf2c33561d..713d6e5d7a 100644 --- a/platform/FileSystemHandle.h +++ b/platform/FileSystemHandle.h @@ -26,6 +26,10 @@ namespace mbed { /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_FileSystemHandle FileSystemHandle functions + * @{ + */ /** A filesystem-like object is one that can be used to open file-like @@ -91,7 +95,9 @@ public: */ virtual int mkdir(const char *path, mode_t mode); }; +/**@}*/ +/**@}*/ } // namespace mbed diff --git a/platform/FileSystemLike.h b/platform/FileSystemLike.h index d8923391d6..aef7913cf6 100644 --- a/platform/FileSystemLike.h +++ b/platform/FileSystemLike.h @@ -25,6 +25,11 @@ namespace mbed { /** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_FileSystemLike FileSystemLike functions + * @{ + */ /** A filesystem-like object is one that can be used to open file-like @@ -34,7 +39,6 @@ namespace mbed { * of the rest of the functions just return error values). * * @note Synchronization level: Set by subclass - * @ingroup platform */ class FileSystemLike : public FileSystemHandle, public FileBase, private NonCopyable { public: @@ -79,6 +83,9 @@ public: } }; +/**@}*/ + +/**@}*/ } // namespace mbed diff --git a/platform/FunctionPointer.h b/platform/FunctionPointer.h index a57195f7a8..18c34c2106 100644 --- a/platform/FunctionPointer.h +++ b/platform/FunctionPointer.h @@ -23,13 +23,14 @@ namespace mbed { /** \addtogroup platform */ - +/** @{*/ +/** + * \defgroup platform_FunctionPointer FunctionPointer class + * @{ + */ // Declarations for backwards compatibility // To be foward compatible, code should adopt the Callback class -/** - * @ingroup platform - */ template class FunctionPointerArg1 : public Callback { public: @@ -61,9 +62,6 @@ public: } }; -/** - * @ingroup platform - */ template class FunctionPointerArg1 : public Callback { public: @@ -97,6 +95,10 @@ public: typedef FunctionPointerArg1 FunctionPointer; +/**@}*/ + +/**@}*/ + } // namespace mbed diff --git a/platform/LocalFileSystem.h b/platform/LocalFileSystem.h index 3bd64d8377..ce0baafaf0 100644 --- a/platform/LocalFileSystem.h +++ b/platform/LocalFileSystem.h @@ -27,9 +27,12 @@ namespace mbed { /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_LocalFileSystem LocalFileSystem functions + * @{ + */ FILEHANDLE local_file_open(const char* name, int flags); -/** @}*/ /** * @class LocalFileHandle @@ -112,6 +115,10 @@ public: virtual int remove(const char *filename); }; +/**@}*/ + +/**@}*/ + } // namespace mbed #endif diff --git a/platform/PlatformMutex.h b/platform/PlatformMutex.h index 517fd3ad05..dc3b82bee6 100644 --- a/platform/PlatformMutex.h +++ b/platform/PlatformMutex.h @@ -1,5 +1,10 @@ /** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_PlatformMutex PlatformMutex class + * @{ + */ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -25,7 +30,6 @@ typedef rtos::Mutex PlatformMutex; #else /** A stub mutex for when an RTOS is not present - * @ingroup platform */ class PlatformMutex : private mbed::NonCopyable { public: @@ -50,3 +54,6 @@ public: #endif +/**@}*/ + +/**@}*/ diff --git a/platform/SingletonPtr.h b/platform/SingletonPtr.h index 369d6dbe2f..848fd099f4 100644 --- a/platform/SingletonPtr.h +++ b/platform/SingletonPtr.h @@ -1,6 +1,10 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_SingletonPtr SingletonPtr class + * @{ + */ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -55,7 +59,6 @@ inline static void singleton_unlock(void) osMutexRelease (singleton_mutex_id); #endif } -/** @}*/ /** Utility class for creating an using a singleton * @@ -68,7 +71,6 @@ inline static void singleton_unlock(void) * @note: This class is lazily initialized on first use. * This class is a POD type so if it is not used it will * be garbage collected. - * @ingroup platform */ template struct SingletonPtr { @@ -108,4 +110,6 @@ struct SingletonPtr { }; #endif +/**@}*/ +/**@}*/ diff --git a/platform/Stream.h b/platform/Stream.h index fd74b0520f..20b7e44afc 100644 --- a/platform/Stream.h +++ b/platform/Stream.h @@ -26,16 +26,18 @@ namespace mbed { /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_Stream Stream class + * @{ + */ extern void mbed_set_unbuffered_stream(std::FILE *_file); extern int mbed_getc(std::FILE *_file); extern char* mbed_gets(char *s, int size, std::FILE *_file); -/** @}*/ /** File stream * * @note Synchronization level: Set by subclass - * @ingroup platform */ class Stream : public FileLike, private NonCopyable { @@ -82,7 +84,9 @@ protected: // Stub } }; +/**@}*/ +/**@}*/ } // namespace mbed #endif diff --git a/platform/Transaction.h b/platform/Transaction.h index 8e26236880..23f03e07f2 100644 --- a/platform/Transaction.h +++ b/platform/Transaction.h @@ -21,9 +21,13 @@ namespace mbed { /** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_Transaction Transaction class + * @{ + */ /** Transaction structure - * @ingroup platform */ typedef struct { void *tx_buffer; /**< Tx buffer */ @@ -38,7 +42,6 @@ typedef struct { /** Transaction class defines a transaction. * * @note Synchronization level: Not protected - * @ingroup platform */ template class Transaction { @@ -72,7 +75,9 @@ private: Class* _obj; transaction_t _data; }; +/**@}*/ +/**@}*/ } #endif diff --git a/platform/mbed_application.h b/platform/mbed_application.h index 633b6a8572..43b4813f75 100644 --- a/platform/mbed_application.h +++ b/platform/mbed_application.h @@ -1,6 +1,3 @@ - -/** \addtogroup platform */ -/** @{*/ /* mbed Microcontroller Library * Copyright (c) 2017-2017 ARM Limited * @@ -16,6 +13,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ + #ifndef MBED_APPLICATION_H #define MBED_APPLICATION_H @@ -52,4 +50,3 @@ void mbed_start_application(uintptr_t address); #endif -/** @}*/ diff --git a/platform/mbed_assert.h b/platform/mbed_assert.h index bd86983fc8..d651f1e8c0 100644 --- a/platform/mbed_assert.h +++ b/platform/mbed_assert.h @@ -1,6 +1,10 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_Assert Assert macros + * @{ + */ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -39,6 +43,19 @@ void mbed_assert_internal(const char *expr, const char *file, int line); } #endif +/** MBED_ASSERT + * Declare runtime assertions: results in runtime error if condition is false + * + * @note + * Use of MBED_ASSERT is limited debug builds only. + * + * @code + * + * int Configure(serial_t *obj) { + * MBED_ASSERT(obj); + * } + * @endcode + */ #ifdef NDEBUG #define MBED_ASSERT(expr) ((void)0) @@ -110,4 +127,7 @@ do { \ #endif -/** @}*/ +/**@}*/ + +/**@}*/ + diff --git a/platform/mbed_critical.h b/platform/mbed_critical.h index 8aa314a8e9..0b7cb2a8b1 100644 --- a/platform/mbed_critical.h +++ b/platform/mbed_critical.h @@ -1,6 +1,4 @@ -/** \addtogroup platform */ -/** @{*/ /* * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 @@ -29,6 +27,12 @@ extern "C" { #endif +/** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_critical critical section function + * @{ + */ /** Determine the current interrupts enabled state * @@ -363,8 +367,11 @@ void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta); #ifdef __cplusplus } // extern "C" #endif +/**@}*/ +/**@}*/ #endif // __MBED_UTIL_CRITICAL_H__ -/** @}*/ + + diff --git a/platform/mbed_debug.h b/platform/mbed_debug.h index 761c1eb99f..5f9a19805d 100644 --- a/platform/mbed_debug.h +++ b/platform/mbed_debug.h @@ -1,6 +1,11 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_debug Debug functions + * @{ + */ + /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -68,4 +73,7 @@ static inline void debug_if(int condition, const char *format, ...) { #endif -/** @}*/ +/**@}*/ + +/**@}*/ + diff --git a/platform/mbed_error.h b/platform/mbed_error.h index 1da55135b9..8f5cd9baff 100644 --- a/platform/mbed_error.h +++ b/platform/mbed_error.h @@ -1,6 +1,10 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_error Error functions + * @{ + */ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -75,3 +79,4 @@ void error(const char* format, ...); #endif /** @}*/ +/** @}*/ diff --git a/platform/mbed_interface.h b/platform/mbed_interface.h index 538a6a7cbf..94baa34f77 100644 --- a/platform/mbed_interface.h +++ b/platform/mbed_interface.h @@ -1,6 +1,11 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_interface Network interface and other utility functions + * @{ + */ + /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -42,6 +47,11 @@ extern "C" { #if DEVICE_SEMIHOST +/** + * \defgroup platform_interface interface functions + * @{ + */ + /** Functions to control the mbed interface * * mbed Microcontrollers have a built-in interface to provide functionality such as @@ -137,6 +147,7 @@ void mbed_error_printf(const char* format, ...); * */ void mbed_error_vfprintf(const char * format, va_list arg); +/** @}*/ #ifdef __cplusplus } diff --git a/platform/mbed_mem_trace.h b/platform/mbed_mem_trace.h index 0267255ba7..59da721e2f 100644 --- a/platform/mbed_mem_trace.h +++ b/platform/mbed_mem_trace.h @@ -1,6 +1,7 @@ /** \addtogroup platform */ /** @{*/ + /* mbed Microcontroller Library * Copyright (c) 2006-2016 ARM Limited * @@ -35,6 +36,11 @@ enum { MBED_MEM_TRACE_FREE }; +/** + * \defgroup platform_mem_trace mem_trace functions + * @{ + */ + /* Prefix for the output of the default tracer */ #define MBED_MEM_DEFAULT_TRACER_PREFIX "#" @@ -133,6 +139,8 @@ void mbed_mem_trace_free(void *ptr, void *caller); */ void mbed_mem_trace_default_callback(uint8_t op, void *res, void *caller, ...); +/** @}*/ + #ifdef __cplusplus } #endif diff --git a/platform/mbed_mktime.h b/platform/mbed_mktime.h index b28525224c..dd302702e4 100644 --- a/platform/mbed_mktime.h +++ b/platform/mbed_mktime.h @@ -28,6 +28,11 @@ extern "C" { #endif +/** + * \defgroup platform_mktime mktime functions + * @{ + */ + /** Compute if a year is a leap year or not. * * @param year The year to test it shall be in the range [70:138]. Year 0 is @@ -89,6 +94,8 @@ time_t _rtc_mktime(const struct tm* calendar_time); */ bool _rtc_localtime(time_t timestamp, struct tm* calendar_time); +/** @}*/ + #ifdef __cplusplus } #endif diff --git a/platform/mbed_poll.h b/platform/mbed_poll.h index 635733bb98..f9c894c21f 100644 --- a/platform/mbed_poll.h +++ b/platform/mbed_poll.h @@ -27,7 +27,11 @@ namespace mbed { class FileHandle; /** \addtogroup platform */ - +/** @{*/ +/** + * \defgroup platform_poll poll functions + * @{ + */ struct pollfh { FileHandle *fh; @@ -47,6 +51,10 @@ struct pollfh { */ int poll(pollfh fhs[], unsigned nfhs, int timeout); +/**@}*/ + +/**@}*/ + } // namespace mbed #endif //MBED_POLL_H diff --git a/platform/mbed_preprocessor.h b/platform/mbed_preprocessor.h index 5e72d99f87..63312e8b13 100644 --- a/platform/mbed_preprocessor.h +++ b/platform/mbed_preprocessor.h @@ -1,5 +1,10 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_preprocessor preprocessor macros + * @{ + */ + /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -51,3 +56,4 @@ #endif /** @}*/ +/** @}*/ diff --git a/platform/mbed_retarget.h b/platform/mbed_retarget.h index a12abc219b..0f3e30b5e5 100644 --- a/platform/mbed_retarget.h +++ b/platform/mbed_retarget.h @@ -58,13 +58,21 @@ typedef unsigned int gid_t; ///< Group ID #endif +/** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_retarget Retarget functions + * @{ + */ /* DIR declarations must also be here */ #if __cplusplus namespace mbed { + class FileHandle; class DirHandle; std::FILE *mbed_fdopen(FileHandle *fh, const char *mode); + } typedef mbed::DirHandle DIR; #else @@ -438,4 +446,8 @@ enum { DT_SOCK, ///< This is a UNIX domain socket. }; +/**@}*/ + +/**@}*/ + #endif /* RETARGET_H */ diff --git a/platform/mbed_rtc_time.h b/platform/mbed_rtc_time.h index 84a3739ec3..ee3e7ec7a1 100644 --- a/platform/mbed_rtc_time.h +++ b/platform/mbed_rtc_time.h @@ -1,6 +1,10 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_rtc_time rtc_time functions + * @{ + */ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -90,3 +94,4 @@ void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init #endif /** @}*/ +/** @}*/ diff --git a/platform/mbed_semihost_api.h b/platform/mbed_semihost_api.h index 9127c5ff00..611cce69c0 100644 --- a/platform/mbed_semihost_api.h +++ b/platform/mbed_semihost_api.h @@ -1,6 +1,4 @@ -/** \addtogroup platform */ -/** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -95,4 +93,4 @@ int semihost_disabledebug(void); #endif -/** @}*/ + diff --git a/platform/mbed_sleep.h b/platform/mbed_sleep.h index 4f635d452a..23fa5150f4 100644 --- a/platform/mbed_sleep.h +++ b/platform/mbed_sleep.h @@ -1,6 +1,11 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_sleep Sleep functions + * @{ + */ + /* mbed Microcontroller Library * Copyright (c) 2006-2017 ARM Limited * @@ -169,3 +174,4 @@ __INLINE static void deepsleep(void) #endif /** @}*/ +/** @}*/ diff --git a/platform/mbed_stats.h b/platform/mbed_stats.h index 99662af414..c997baefab 100644 --- a/platform/mbed_stats.h +++ b/platform/mbed_stats.h @@ -1,6 +1,10 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_stats stats functions + * @{ + */ /* mbed Microcontroller Library * Copyright (c) 2016-2016 ARM Limited * @@ -25,6 +29,9 @@ extern "C" { #endif +/** + * struct mbed_stats_heap_t definition + */ typedef struct { uint32_t current_size; /**< Bytes allocated currently. */ uint32_t max_size; /**< Max bytes allocated at a given time. */ @@ -41,6 +48,9 @@ typedef struct { */ void mbed_stats_heap_get(mbed_stats_heap_t *stats); +/** + * struct mbed_stats_stack_t definition + */ typedef struct { uint32_t thread_id; /**< Identifier for thread that owns the stack or 0 if multiple threads. */ uint32_t max_size; /**< Maximum number of bytes used on the stack. */ @@ -73,3 +83,5 @@ size_t mbed_stats_stack_get_each(mbed_stats_stack_t *stats, size_t count); #endif /** @}*/ + +/** @}*/ diff --git a/platform/mbed_toolchain.h b/platform/mbed_toolchain.h index f5d5e79e61..a911e9c997 100644 --- a/platform/mbed_toolchain.h +++ b/platform/mbed_toolchain.h @@ -1,6 +1,11 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_toolchain Toolchain functions + * @{ + */ + /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -382,3 +387,4 @@ typedef int FILEHANDLE; #endif /** @}*/ +/** @}*/ diff --git a/platform/mbed_wait_api.h b/platform/mbed_wait_api.h index 91619def4a..a58509f741 100644 --- a/platform/mbed_wait_api.h +++ b/platform/mbed_wait_api.h @@ -1,6 +1,11 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_wait_api wait_api functions + * @{ + */ + /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -70,3 +75,4 @@ void wait_us(int us); #endif /** @}*/ +/** @}*/ diff --git a/rtos/EventFlags.h b/rtos/EventFlags.h index 02df107773..5beb5e5ef1 100644 --- a/rtos/EventFlags.h +++ b/rtos/EventFlags.h @@ -32,7 +32,11 @@ namespace rtos { /** \addtogroup rtos */ /** @{*/ - +/** + * \defgroup rtos_EventFlags EventFlags class + * @{ + */ + /** The EventFlags class is used to signal or wait for an arbitrary event or events. @note EventFlags support 31 flags so the MSB flag is ignored, it is used to return an error code (@a osFlagsError) @@ -93,7 +97,9 @@ private: mbed_rtos_storage_event_flags_t _obj_mem; }; +/** @}*/ +/** @}*/ + } #endif -/** @}*/ diff --git a/rtos/Mail.h b/rtos/Mail.h index 602907e34e..83a3a24656 100644 --- a/rtos/Mail.h +++ b/rtos/Mail.h @@ -38,7 +38,11 @@ using namespace rtos; namespace rtos { /** \addtogroup rtos */ /** @{*/ - +/** + * \defgroup rtos_Mail Mail class + * @{ + */ + /** The Mail class allow to control, send, receive, or wait for mail. A mail is a memory block that is send to a thread or interrupt service routine. @tparam T data type of a single message element. @@ -103,9 +107,12 @@ private: MemoryPool _pool; }; +/** @}*/ +/** @}*/ + } #endif -/** @}*/ + diff --git a/rtos/MemoryPool.h b/rtos/MemoryPool.h index 0eab4de792..d76a99e794 100644 --- a/rtos/MemoryPool.h +++ b/rtos/MemoryPool.h @@ -33,7 +33,11 @@ namespace rtos { /** \addtogroup rtos */ /** @{*/ - +/** + * \defgroup rtos_MemoryPool MemoryPool class + * @{ + */ + /** Define and manage fixed-size memory pools of objects of a given type. @tparam T data type of a single object (element). @tparam queue_sz maximum number of objects (elements) in the memory pool. @@ -99,8 +103,10 @@ private: char _pool_mem[((sizeof(T) + 3) & ~3) * pool_sz]; mbed_rtos_storage_mem_pool_t _obj_mem; }; +/** @}*/ +/** @}*/ } #endif -/** @}*/ + diff --git a/rtos/Mutex.h b/rtos/Mutex.h index 5490012d46..e84631e64f 100644 --- a/rtos/Mutex.h +++ b/rtos/Mutex.h @@ -32,7 +32,11 @@ namespace rtos { /** \addtogroup rtos */ /** @{*/ - +/** + * \defgroup rtos_Mutex Mutex class + * @{ + */ + /** The Mutex class is used to synchronize the execution of threads. This is for example used to protect access to a shared resource. @@ -84,8 +88,9 @@ private: osMutexId_t _id; mbed_rtos_storage_mutex_t _obj_mem; }; - +/** @}*/ +/** @}*/ } #endif -/** @}*/ + diff --git a/rtos/Queue.h b/rtos/Queue.h index 8f32d7a4e2..556c9b8f0d 100644 --- a/rtos/Queue.h +++ b/rtos/Queue.h @@ -34,7 +34,11 @@ namespace rtos { /** \addtogroup rtos */ /** @{*/ - +/** + * \defgroup rtos_EventFlags EventFlags class + * @{ + */ + /** The Queue class allow to control, send, receive, or wait for messages. A message can be a integer or pointer value to a certain type T that is send to a thread or interrupt service routine. @@ -118,8 +122,9 @@ private: char _queue_mem[queue_sz * (sizeof(T*) + sizeof(mbed_rtos_storage_message_t))]; mbed_rtos_storage_msg_queue_t _obj_mem; }; +/** @}*/ +/** @}*/ } #endif -/** @}*/ diff --git a/rtos/RtosTimer.h b/rtos/RtosTimer.h index d75f49c8b2..c5e6276468 100644 --- a/rtos/RtosTimer.h +++ b/rtos/RtosTimer.h @@ -33,7 +33,11 @@ namespace rtos { /** \addtogroup rtos */ /** @{*/ - +/** + * \defgroup rtos_RtosTimer RtosTimer class + * @{ + */ + /** The RtosTimer class allow creating and and controlling of timer functions in the system. A timer function is called when a time period expires whereby both on-shot and periodic timers are possible. A timer can be started, restarted, or stopped. @@ -160,9 +164,11 @@ private: mbed_rtos_storage_timer_t _obj_mem; mbed::Callback _function; }; +/** @}*/ +/** @}*/ } #endif -/** @}*/ + diff --git a/rtos/Semaphore.h b/rtos/Semaphore.h index 07ce078277..88b479c5e4 100644 --- a/rtos/Semaphore.h +++ b/rtos/Semaphore.h @@ -31,6 +31,10 @@ namespace rtos { /** \addtogroup rtos */ /** @{*/ +/** + * \defgroup rtos_Semaphore Semaphore class + * @{ + */ /** The Semaphore class is used to manage and protect access to a set of shared resources. * @@ -73,8 +77,9 @@ private: osSemaphoreId_t _id; mbed_rtos_storage_semaphore_t _obj_mem; }; - +/** @}*/ +/** @}*/ } #endif -/** @}*/ + diff --git a/rtos/Thread.h b/rtos/Thread.h index cf92877d7e..d67ad3acf8 100644 --- a/rtos/Thread.h +++ b/rtos/Thread.h @@ -35,6 +35,10 @@ namespace rtos { /** \addtogroup rtos */ /** @{*/ +/** + * \defgroup rtos_Thread Thread class + * @{ + */ /** The Thread class allow defining, creating, and controlling thread functions in the system. * @@ -370,8 +374,9 @@ private: mbed_rtos_storage_thread_t _obj_mem; bool _finished; }; - +/** @}*/ +/** @}*/ } #endif -/** @}*/ + diff --git a/rtos/rtos_idle.h b/rtos/rtos_idle.h index 5fa9fb776c..c2894c23e3 100644 --- a/rtos/rtos_idle.h +++ b/rtos/rtos_idle.h @@ -31,7 +31,17 @@ extern "C" { #endif +/** + * \defgroup rtos_Idle Idle hook function + * @{ + */ +/** + @note + Sets the hook function called by idle task + @param fptr Hook function pointer. + */ void rtos_attach_idle_hook(void (*fptr)(void)); +/** @}*/ #ifdef __cplusplus } @@ -40,3 +50,4 @@ void rtos_attach_idle_hook(void (*fptr)(void)); #endif /** @}*/ + From 88a91a5a9be2db2eecd76d84f9a9b7b8b786dfa6 Mon Sep 17 00:00:00 2001 From: Senthil Ramakrishnan Date: Fri, 27 Oct 2017 15:38:18 -0500 Subject: [PATCH 21/80] Fix comments on mbed_assert.h --- platform/mbed_assert.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/mbed_assert.h b/platform/mbed_assert.h index d651f1e8c0..8aecdcc3fa 100644 --- a/platform/mbed_assert.h +++ b/platform/mbed_assert.h @@ -47,7 +47,7 @@ void mbed_assert_internal(const char *expr, const char *file, int line); * Declare runtime assertions: results in runtime error if condition is false * * @note - * Use of MBED_ASSERT is limited debug builds only. + * Use of MBED_ASSERT is limited to Debug and Develop builds. * * @code * From 6d967bbb54622769d04029428808a20ba8e7f863 Mon Sep 17 00:00:00 2001 From: Senthil Ramakrishnan Date: Tue, 31 Oct 2017 16:17:07 -0500 Subject: [PATCH 22/80] Fixed doxygen_options.json --- doxygen_options.json | 1 + 1 file changed, 1 insertion(+) diff --git a/doxygen_options.json b/doxygen_options.json index c4ebdc0308..834cac9270 100644 --- a/doxygen_options.json +++ b/doxygen_options.json @@ -1,4 +1,5 @@ { + "PROJECT_NAME": "Mbed OS Reference", "ENABLE_PREPROCESSING": "YES", "MACRO_EXPANSION": "YES", "EXPAND_ONLY_PREDEF": "NO", From 69df251916bb81138c84db2d2e540ef298c325cd Mon Sep 17 00:00:00 2001 From: Maciej Bocianski Date: Tue, 24 Oct 2017 13:10:02 +0200 Subject: [PATCH 23/80] event queue test: fix out of memory problem for NUCLEO_F070RB --- TESTS/events/queue/main.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/TESTS/events/queue/main.cpp b/TESTS/events/queue/main.cpp index f779ee0c24..738fdd0d8d 100644 --- a/TESTS/events/queue/main.cpp +++ b/TESTS/events/queue/main.cpp @@ -22,7 +22,10 @@ using namespace utest::v1; -#define TEST_EQUEUE_SIZE 1024 +// TEST_EQUEUE_SIZE was reduced below 1024B to fit this test to devices with small RAM (RAM <= 16kB) +// additionally TEST_EQUEUE_SIZE was expressed in EVENTS_EVENT_SIZE to increase readability +// (for more details about EVENTS_EVENT_SIZE see EventQueue constructor) +#define TEST_EQUEUE_SIZE (18*EVENTS_EVENT_SIZE) // flag for called volatile bool touched = false; From 9f9666ecede69a954cf83ad9367987e39b8a0c0a Mon Sep 17 00:00:00 2001 From: gorazd Date: Wed, 18 Oct 2017 22:14:12 +0200 Subject: [PATCH 24/80] add new target L-Tek FF-LPC546XX --- .../TARGET_FF_LPC546XX/PeripheralNames.h | 113 ++++++++ .../TARGET_FF_LPC546XX/PeripheralPins.c | 125 +++++++++ .../TARGET_FF_LPC546XX/PinNames.h | 250 ++++++++++++++++++ .../TARGET_FF_LPC546XX/clock_config.c | 248 +++++++++++++++++ .../TARGET_FF_LPC546XX/clock_config.h | 144 ++++++++++ .../TARGET_FF_LPC546XX/device.h | 39 +++ .../TARGET_FF_LPC546XX/mbed_overrides.c | 121 +++++++++ targets/targets.json | 6 + 8 files changed, 1046 insertions(+) create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.c create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.h create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/device.h create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h new file mode 100644 index 0000000000..7efa1e5c20 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h @@ -0,0 +1,113 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PortNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OSC32KCLK = 0, +} RTCName; + +typedef enum { + UART_0 = Flexcomm0, + UART_2 = Flexcomm2, + UART_7 = Flexcomm7 +} UARTName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +typedef enum { + I2C_7 = Flexcomm7, + I2C_2 = Flexcomm2 +} I2CName; + +#define TPM_SHIFT 8 +typedef enum { + PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 + PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 + PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 + PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 + PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 + PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 + PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 + PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2 + PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3 + PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4 + PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5 + PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6 + PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7 + PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 + PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 + PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2 + PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3 + PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4 + PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5 + PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6 + PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7 + PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 + PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 + PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 + PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 + PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 + PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 + PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 + PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 +} PWMName; + +#define ADC_INSTANCE_SHIFT 8 +#define ADC_B_CHANNEL_SHIFT 5 + +typedef enum { + ADC0_SE0 = 0, + ADC0_SE1 = 1, + ADC0_SE2 = 2, + ADC0_SE3 = 3, + ADC0_SE4 = 4, + ADC0_SE5 = 5, + ADC0_SE6 = 6, + ADC0_SE7 = 7, + ADC0_SE8 = 8, + ADC0_SE9 = 9, + ADC0_SE10 = 10, + ADC0_SE11 = 11, +} ADCName; + +typedef enum { + CAN_1 = 1 +} CANName; + +typedef enum { + SPI_0 = Flexcomm0, + SPI_2 = Flexcomm2, + SPI_3 = Flexcomm3 +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c new file mode 100644 index 0000000000..bb555ca3b7 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c @@ -0,0 +1,125 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, OSC32KCLK, 0}, +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {P0_15, ADC0_SE3, 0}, + {P0_16, ADC0_SE4, 0}, + {P0_23, ADC0_SE11, 0}, + {P0_31, ADC0_SE5, 0}, + {P1_0, ADC0_SE6, 0}, + {P0_10, ADC0_SE0, 0}, + {NC , NC , 0} +}; + +/************CAN***************/ +const PinMap PinMap_CAN_TD[] = { + {P0_1, CAN_1, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_CAN_RD[] = { + {P0_0, CAN_1, 1}, + {NC , NC , 0} +}; + + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {NC , NC , 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {P0_26, I2C_2, 1}, + {P1_29, I2C_7, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {P0_27, I2C_2, 1}, + {P1_30, I2C_7, 1}, + {NC , NC , 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {P0_30, UART_0, 1}, + {P0_27, UART_2, 1}, + {P1_30, UART_7, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {P0_29, UART_0, 1}, + {P0_26, UART_2, 1}, + {P1_29, UART_7, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {P1_4, SPI_0, 1}, + {P1_23, SPI_2, 1}, + {P0_6, SPI_3, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {P1_5, SPI_0, 1}, + {P1_24, SPI_2, 1}, + {P0_8, SPI_3, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {P1_6, SPI_0, 1}, + {P1_25, SPI_2, 1}, + {P0_9, SPI_3, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {P1_7, SPI_0, 1}, + {P0_7, SPI_3, 1}, + {NC , NC , 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {P0_17 , PWM_1, 4}, + {P0_18 , PWM_2, 4}, + {P0_19 , PWM_3, 4}, + {P0_22 , PWM_4, 4}, + {P0_28 , PWM_8, 4}, + {P0_29 , PWM_9, 4}, + {NC , NC, 0} +}; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h new file mode 100644 index 0000000000..bc22e8e4bc --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h @@ -0,0 +1,250 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 5 + +typedef enum { + P0_0 = (0 << PORT_SHIFT | 0), + P0_1 = (0 << PORT_SHIFT | 1), + P0_2 = (0 << PORT_SHIFT | 2), + P0_3 = (0 << PORT_SHIFT | 3), + P0_4 = (0 << PORT_SHIFT | 4), + P0_5 = (0 << PORT_SHIFT | 5), + P0_6 = (0 << PORT_SHIFT | 6), + P0_7 = (0 << PORT_SHIFT | 7), + P0_8 = (0 << PORT_SHIFT | 8), + P0_9 = (0 << PORT_SHIFT | 9), + P0_10 = (0 << PORT_SHIFT | 10), + P0_11 = (0 << PORT_SHIFT | 11), + P0_12 = (0 << PORT_SHIFT | 12), + P0_13 = (0 << PORT_SHIFT | 13), + P0_14 = (0 << PORT_SHIFT | 14), + P0_15 = (0 << PORT_SHIFT | 15), + P0_16 = (0 << PORT_SHIFT | 16), + P0_17 = (0 << PORT_SHIFT | 17), + P0_18 = (0 << PORT_SHIFT | 18), + P0_19 = (0 << PORT_SHIFT | 19), + P0_20 = (0 << PORT_SHIFT | 20), + P0_21 = (0 << PORT_SHIFT | 21), + P0_22 = (0 << PORT_SHIFT | 22), + P0_23 = (0 << PORT_SHIFT | 23), + P0_24 = (0 << PORT_SHIFT | 24), + P0_25 = (0 << PORT_SHIFT | 25), + P0_26 = (0 << PORT_SHIFT | 26), + P0_27 = (0 << PORT_SHIFT | 27), + P0_28 = (0 << PORT_SHIFT | 28), + P0_29 = (0 << PORT_SHIFT | 29), + P0_30 = (0 << PORT_SHIFT | 30), + P0_31 = (0 << PORT_SHIFT | 31), + + P1_0 = (1 << PORT_SHIFT | 0), + P1_1 = (1 << PORT_SHIFT | 1), + P1_2 = (1 << PORT_SHIFT | 2), + P1_3 = (1 << PORT_SHIFT | 3), + P1_4 = (1 << PORT_SHIFT | 4), + P1_5 = (1 << PORT_SHIFT | 5), + P1_6 = (1 << PORT_SHIFT | 6), + P1_7 = (1 << PORT_SHIFT | 7), + P1_8 = (1 << PORT_SHIFT | 8), + P1_9 = (1 << PORT_SHIFT | 9), + P1_10 = (1 << PORT_SHIFT | 10), + P1_11 = (1 << PORT_SHIFT | 11), + P1_12 = (1 << PORT_SHIFT | 12), + P1_13 = (1 << PORT_SHIFT | 13), + P1_14 = (1 << PORT_SHIFT | 14), + P1_15 = (1 << PORT_SHIFT | 15), + P1_16 = (1 << PORT_SHIFT | 16), + P1_17 = (1 << PORT_SHIFT | 17), + P1_18 = (1 << PORT_SHIFT | 18), + P1_19 = (1 << PORT_SHIFT | 19), + P1_20 = (1 << PORT_SHIFT | 20), + P1_21 = (1 << PORT_SHIFT | 21), + P1_22 = (1 << PORT_SHIFT | 22), + P1_23 = (1 << PORT_SHIFT | 23), + P1_24 = (1 << PORT_SHIFT | 24), + P1_25 = (1 << PORT_SHIFT | 25), + P1_26 = (1 << PORT_SHIFT | 26), + P1_27 = (1 << PORT_SHIFT | 27), + P1_28 = (1 << PORT_SHIFT | 28), + P1_29 = (1 << PORT_SHIFT | 29), + P1_30 = (1 << PORT_SHIFT | 30), + P1_31 = (1 << PORT_SHIFT | 31), + + P2_0 = (2 << PORT_SHIFT | 0), + P2_1 = (2 << PORT_SHIFT | 1), + P2_2 = (2 << PORT_SHIFT | 2), + P2_3 = (2 << PORT_SHIFT | 3), + P2_4 = (2 << PORT_SHIFT | 4), + P2_5 = (2 << PORT_SHIFT | 5), + P2_6 = (2 << PORT_SHIFT | 6), + P2_7 = (2 << PORT_SHIFT | 7), + P2_8 = (2 << PORT_SHIFT | 8), + P2_9 = (2 << PORT_SHIFT | 9), + P2_10 = (2 << PORT_SHIFT | 10), + P2_11 = (2 << PORT_SHIFT | 11), + P2_12 = (2 << PORT_SHIFT | 12), + P2_13 = (2 << PORT_SHIFT | 13), + P2_14 = (2 << PORT_SHIFT | 14), + P2_15 = (2 << PORT_SHIFT | 15), + P2_16 = (2 << PORT_SHIFT | 16), + P2_17 = (2 << PORT_SHIFT | 17), + P2_18 = (2 << PORT_SHIFT | 18), + P2_19 = (2 << PORT_SHIFT | 19), + P2_20 = (2 << PORT_SHIFT | 20), + P2_21 = (2 << PORT_SHIFT | 21), + P2_22 = (2 << PORT_SHIFT | 22), + P2_23 = (2 << PORT_SHIFT | 23), + P2_24 = (2 << PORT_SHIFT | 24), + P2_25 = (2 << PORT_SHIFT | 25), + P2_26 = (2 << PORT_SHIFT | 26), + P2_27 = (2 << PORT_SHIFT | 27), + P2_28 = (2 << PORT_SHIFT | 28), + P2_29 = (2 << PORT_SHIFT | 29), + P2_30 = (2 << PORT_SHIFT | 30), + P2_31 = (2 << PORT_SHIFT | 31), + + P3_0 = (3 << PORT_SHIFT | 0), + P3_1 = (3 << PORT_SHIFT | 1), + P3_2 = (3 << PORT_SHIFT | 2), + P3_3 = (3 << PORT_SHIFT | 3), + P3_4 = (3 << PORT_SHIFT | 4), + P3_5 = (3 << PORT_SHIFT | 5), + P3_6 = (3 << PORT_SHIFT | 6), + P3_7 = (3 << PORT_SHIFT | 7), + P3_8 = (3 << PORT_SHIFT | 8), + P3_9 = (3 << PORT_SHIFT | 9), + P3_10 = (3 << PORT_SHIFT | 10), + P3_11 = (3 << PORT_SHIFT | 11), + P3_12 = (3 << PORT_SHIFT | 12), + P3_13 = (3 << PORT_SHIFT | 13), + P3_14 = (3 << PORT_SHIFT | 14), + P3_15 = (3 << PORT_SHIFT | 15), + P3_16 = (3 << PORT_SHIFT | 16), + P3_17 = (3 << PORT_SHIFT | 17), + P3_18 = (3 << PORT_SHIFT | 18), + P3_19 = (3 << PORT_SHIFT | 19), + P3_20 = (3 << PORT_SHIFT | 20), + P3_21 = (3 << PORT_SHIFT | 21), + P3_22 = (3 << PORT_SHIFT | 22), + P3_23 = (3 << PORT_SHIFT | 23), + P3_24 = (3 << PORT_SHIFT | 24), + P3_25 = (3 << PORT_SHIFT | 25), + P3_26 = (3 << PORT_SHIFT | 26), + P3_27 = (3 << PORT_SHIFT | 27), + P3_28 = (3 << PORT_SHIFT | 28), + P3_29 = (3 << PORT_SHIFT | 29), + P3_30 = (3 << PORT_SHIFT | 30), + P3_31 = (3 << PORT_SHIFT | 31), + + P4_0 = (4 << PORT_SHIFT | 0), + P4_1 = (4 << PORT_SHIFT | 1), + P4_2 = (4 << PORT_SHIFT | 2), + P4_3 = (4 << PORT_SHIFT | 3), + P4_4 = (4 << PORT_SHIFT | 4), + P4_5 = (4 << PORT_SHIFT | 5), + P4_6 = (4 << PORT_SHIFT | 6), + P4_7 = (4 << PORT_SHIFT | 7), + P4_8 = (4 << PORT_SHIFT | 8), + P4_9 = (4 << PORT_SHIFT | 9), + P4_10 = (4 << PORT_SHIFT | 10), + P4_11 = (4 << PORT_SHIFT | 11), + P4_12 = (4 << PORT_SHIFT | 12), + P4_13 = (4 << PORT_SHIFT | 13), + P4_14 = (4 << PORT_SHIFT | 14), + P4_15 = (4 << PORT_SHIFT | 15), + P4_16 = (4 << PORT_SHIFT | 16), + + + + // mbed original LED naming + LED1 = P0_13, + LED2 = P1_27, + LED3 = P0_14, + LED4 = P1_28, + + + // USB Pins + USBTX = P0_30, + USBRX = P0_29, + + + A0 = P0_16, + A1 = P0_31, + A2 = P1_0, + A3 = P2_0, + A4 = P3_4, + A5 = P1_1, + + + p5 = P1_24, + p6 = P1_25, + p7 = P1_23, + p8 = P1_8, + p9 = P0_26, + p10 = P0_27, + p11 = P1_4, + p12 = P1_5, + p13 = P1_6, + p14 = P1_7, + p15 = P0_15, + p16 = P0_16, + p17 = P0_23, + p18 = P0_31, + p19 = P1_0, + p20 = P0_10, + p21 = P0_17, + p22 = P0_18, + p23 = P0_19, + p24 = P0_22, + p25 = P0_28, + p26 = P0_29, + p27 = P1_30, + p28 = P1_29, + p29 = P0_0, + p30 = P0_1, + + + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.c new file mode 100644 index 0000000000..cea986a6c0 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Setup voltage for the fastest of the clock outputs + * + * 3. Set up wait states of the flash. + * + * 4. Set up all dividers. + * + * 5. Set up all selectors to provide selected clocks. + */ + +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!ClocksProfile +product: Clocks v1.0 +processor: LPC54618J512 +package_id: LPC54618J512ET180 +mcu_data: ksdk2_0 +processor_version: 0.0.0 +board: LPCXpresso54618 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFRO12M *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: System_clock.outFreq, value: 12 MHz} +settings: +- {id: SYSCON.EMCCLKDIV.scale, value: '1', locked: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk( + kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + POWER_SetVoltageForFreq( + 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockFROHF48M *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockFROHF48M +outputs: +- {id: System_clock.outFreq, value: 48 MHz} +settings: +- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF48M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk( + kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + POWER_SetVoltageForFreq( + 48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */ + + CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK; +} + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFROHF96M ********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} +sources: +- {id: SYSCON.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk( + kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + POWER_SetVoltageForFreq( + 96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +} + +/******************************************************************************* + ********************* Configuration BOARD_BootClockPLL180M ********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockPLL180M +outputs: +- {id: FRO12M_clock.outFreq, value: 12 MHz} +- {id: FROHF_clock.outFreq, value: 48 MHz} +- {id: SYSPLL_clock.outFreq, value: 180 MHz} +- {id: System_clock.outFreq, value: 180 MHz} +settings: +- {id: SYSCON.M_MULT.scale, value: '30', locked: true} +- {id: SYSCON.N_DIV.scale, value: '1', locked: true} +- {id: SYSCON.PDEC.scale, value: '2', locked: true} +- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up} +sources: +- {id: SYSCON._clk_in.outFreq, value: 12 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL180M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL180M configuration + ******************************************************************************/ +void BOARD_BootClockPLL180M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk( + kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + POWER_SetVoltageForFreq( + 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up SYS PLL */ + const pll_setup_t pllSetup = { + .pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U), + .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)), + .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)), + .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)), + .pllRate = 180000000U, + .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP}; + CLOCK_AttachClk(kEXT_CLK_to_SYS_PLL); /*!< Set sys pll clock source from external crystal */ + CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */ + POWER_SetVoltageForFreq( + 180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(180000000U); /*!< Set FLASH wait states for core */ + CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch System clock to SYS PLL 180MHz */ + + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BootClockPLL180M_CORE_CLOCK; +} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.h new file mode 100644 index 0000000000..f9cdab4d95 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 12000000U /*!< Board xtal0 frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ +#define BOARD_BootClockRUN BOARD_BootClockFROHF48M + + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFRO12M *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency:12000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockFROHF48M *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency:48000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF48M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFROHF96M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency:96000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************* Configuration BOARD_BootClockPLL180M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL180M configuration + ******************************************************************************/ +#define BOARD_BootClockPLL180M_CORE_CLOCK 180000000U /*!< Core clock frequency:180000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockPLL180M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL180M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/device.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/device.h new file mode 100644 index 0000000000..de347c375d --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/device.h @@ -0,0 +1,39 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define NUMBER_OF_GPIO_INTS 8 + +#define APP_EXCLUDE_FROM_DEEPSLEEP \ + (SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK | SYSCON_PDRUNCFG_PDEN_SRAMX_MASK | \ + SYSCON_PDRUNCFG_PDEN_SRAM0_MASK | SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK) + +/* Defines used by the sleep code */ +#define LPC_CLOCK_INTERNAL_IRC BOARD_BootClockFRO12M +#define LPC_CLOCK_RUN BOARD_BootClockFROHF48M + +#define DEVICE_ID_LENGTH 24 + + + + + +#include "objects.h" + +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c new file mode 100644 index 0000000000..b727924a6a --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c @@ -0,0 +1,121 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "clock_config.h" +#include "fsl_emc.h" +#include "fsl_power.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* The SDRAM timing. */ +#define SDRAM_REFRESHPERIOD_NS (64 * 1000000 / 4096) /* 4096 rows/ 64ms */ +#define SDRAM_TRP_NS (18u) +#define SDRAM_TRAS_NS (42u) +#define SDRAM_TSREX_NS (67u) +#define SDRAM_TAPR_NS (18u) +#define SDRAM_TWRDELT_NS (6u) +#define SDRAM_TRC_NS (60u) +#define SDRAM_RFC_NS (60u) +#define SDRAM_XSR_NS (67u) +#define SDRAM_RRD_NS (12u) +#define SDRAM_MRD_NCLK (2u) +#define SDRAM_RAS_NCLK (2u) +#define SDRAM_MODEREG_VALUE (0x23u) +#define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/ + +// called before main +void mbed_sdk_init() +{ + BOARD_BootClockFROHF48M(); +} + +// Change the NMI pin to an input. This allows NMI pin to +// be used as a low power mode wakeup. The application will +// need to change the pin back to NMI_b or wakeup only occurs once! +void NMI_Handler(void) +{ + //gpio_t gpio; + //gpio_init_in(&gpio, PTA4); +} + +// Enable the RTC oscillator if available on the board +void rtc_setup_oscillator(void) +{ + /* Enable the RTC 32K Oscillator */ + SYSCON->RTCOSCCTRL |= SYSCON_RTCOSCCTRL_EN_MASK; +} + +void ADC_ClockPower_Configuration(void) +{ + /* SYSCON power. */ + POWER_DisablePD(kPDRUNCFG_PD_VDDA); /* Power on VDDA. */ + POWER_DisablePD(kPDRUNCFG_PD_ADC0); /* Power on the ADC converter. */ + POWER_DisablePD(kPDRUNCFG_PD_VD2_ANA); /* Power on the analog power supply. */ + POWER_DisablePD(kPDRUNCFG_PD_VREFP); /* Power on the reference voltage source. */ + POWER_DisablePD(kPDRUNCFG_PD_TS); /* Power on the temperature sensor. */ + + /* Enable the clock. */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); + + /* CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); */ + /* Sync clock source is not used. Using sync clock source and would be divided by 2. + * The divider would be set when configuring the converter. + */ + CLOCK_EnableClock(kCLOCK_Adc0); /* SYSCON->AHBCLKCTRL[0] |= SYSCON_AHBCLKCTRL_ADC0_MASK; */ +} + +/* Initialize the external memory. */ +void BOARD_InitSDRAM(void) +{ + emc_basic_config_t basicConfig; + emc_dynamic_timing_config_t dynTiming; + emc_dynamic_chip_config_t dynChipConfig; + + /* Basic configuration. */ + basicConfig.endian = kEMC_LittleEndian; + basicConfig.fbClkSrc = kEMC_IntloopbackEmcclk; + /* EMC Clock = CPU FREQ/2 here can fit CPU freq from 12M ~ 180M. + * If you change the divide to 0 and EMC clock is larger than 100M + * please take refer to emc.dox to adjust EMC clock delay. + */ + basicConfig.emcClkDiv = 1; + /* Dynamic memory timing configuration. */ + dynTiming.readConfig = kEMC_Cmddelay; + dynTiming.refreshPeriod_Nanosec = SDRAM_REFRESHPERIOD_NS; + dynTiming.tRp_Ns = SDRAM_TRP_NS; + dynTiming.tRas_Ns = SDRAM_TRAS_NS; + dynTiming.tSrex_Ns = SDRAM_TSREX_NS; + dynTiming.tApr_Ns = SDRAM_TAPR_NS; + dynTiming.tWr_Ns = (1000000000 / CLOCK_GetFreq(kCLOCK_EMC) + SDRAM_TWRDELT_NS); /* one clk + 6ns */ + dynTiming.tDal_Ns = dynTiming.tWr_Ns + dynTiming.tRp_Ns; + dynTiming.tRc_Ns = SDRAM_TRC_NS; + dynTiming.tRfc_Ns = SDRAM_RFC_NS; + dynTiming.tXsr_Ns = SDRAM_XSR_NS; + dynTiming.tRrd_Ns = SDRAM_RRD_NS; + dynTiming.tMrd_Nclk = SDRAM_MRD_NCLK; + /* Dynamic memory chip specific configuration: Chip 0 - MTL48LC8M16A2B4-6A */ + dynChipConfig.chipIndex = 0; + dynChipConfig.dynamicDevice = kEMC_Sdram; + dynChipConfig.rAS_Nclk = SDRAM_RAS_NCLK; + dynChipConfig.sdramModeReg = SDRAM_MODEREG_VALUE; + dynChipConfig.sdramExtModeReg = 0; /* it has no use for normal sdram */ + dynChipConfig.devAddrMap = SDRAM_DEV_MEMORYMAP; + /* EMC Basic configuration. */ + EMC_Init(EMC, &basicConfig); + /* EMC Dynamc memory configuration. */ + EMC_DynamicMemInit(EMC, &dynTiming, &dynChipConfig, 1); +} diff --git a/targets/targets.json b/targets/targets.json index b66213ecac..68b18fadeb 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -711,6 +711,12 @@ "release_versions": ["2", "5"], "device_name" : "LPC54618J512ET180" }, + "FF_LPC546XX": { + "inherits": ["LPC546XX"], + "extra_labels_remove" : ["LPCXpresso"], + "supported_form_factors": [""], + "detect_code": ["8081"] + }, "NUCLEO_F030R8": { "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO", "MORPHO"], From 761c57876bb42a3c008e228c6eba6c572f7fd2e1 Mon Sep 17 00:00:00 2001 From: Chris Snow Date: Sun, 15 Oct 2017 17:05:45 +0100 Subject: [PATCH 25/80] Fix ETHMEM_SECTION placement for ARM on LPC1768 --- .../lwip-interface/lwip-eth/arch/TARGET_NXP/lpc17_emac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lpc17_emac.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lpc17_emac.c index d39be116e1..5b3b326435 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lpc17_emac.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lpc17_emac.c @@ -153,7 +153,7 @@ struct lpc_enetdata { # define ETHMEM_SECTION __attribute__((section("AHBSRAM1"),aligned)) # endif #elif defined(TARGET_LPC17XX) -# if defined(TOOLCHAIN_GCC_ARM) +# if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_ARM) # define ETHMEM_SECTION __attribute__((section("AHBSRAM1"),aligned)) # endif #endif From 05a36aafe89d6d37dccb1c590ff0319e979cc6cb Mon Sep 17 00:00:00 2001 From: Kevin Gilbert Date: Fri, 13 Oct 2017 17:22:21 -0500 Subject: [PATCH 26/80] Remove build warnings in LWIP --- .../FEATURE_LWIP/lwip-interface/lwip/src/core/lwip_tcp.c | 1 - features/FEATURE_LWIP/lwip-interface/lwip_stack.c | 6 ++++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/features/FEATURE_LWIP/lwip-interface/lwip/src/core/lwip_tcp.c b/features/FEATURE_LWIP/lwip-interface/lwip/src/core/lwip_tcp.c index ec2e1f92ce..17b681e590 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip/src/core/lwip_tcp.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip/src/core/lwip_tcp.c @@ -358,7 +358,6 @@ tcp_close_shutdown_fin(struct tcp_pcb *pcb) default: /* Has already been closed, do nothing. */ return ERR_OK; - break; } if (err == ERR_OK) { diff --git a/features/FEATURE_LWIP/lwip-interface/lwip_stack.c b/features/FEATURE_LWIP/lwip-interface/lwip_stack.c index 064612ba6f..513c3830e5 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip_stack.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip_stack.c @@ -293,7 +293,9 @@ static int get_ip_addr_type(const ip_addr_t *ip_addr) return IPADDR_TYPE_V4; } #endif +#if LWIP_IPV6 && LWIP_IPV4 return IPADDR_TYPE_ANY; +#endif } void add_dns_addr(struct netif *lwip_netif) @@ -658,7 +660,7 @@ nsapi_error_t mbed_lwip_bringup_2(bool dhcp, bool ppp, const char *ip, const cha if (!netif_is_link_up(&lwip_netif)) { if (sys_arch_sem_wait(&lwip_netif_linked, 15000) == SYS_ARCH_TIMEOUT) { if (ppp) { - ppp_lwip_disconnect(); + (void) ppp_lwip_disconnect(); } return NSAPI_ERROR_NO_CONNECTION; } @@ -686,7 +688,7 @@ nsapi_error_t mbed_lwip_bringup_2(bool dhcp, bool ppp, const char *ip, const cha if (!mbed_lwip_get_ip_addr(true, &lwip_netif)) { if (sys_arch_sem_wait(&lwip_netif_has_any_addr, DHCP_TIMEOUT * 1000) == SYS_ARCH_TIMEOUT) { if (ppp) { - ppp_lwip_disconnect(); + (void) ppp_lwip_disconnect(); } return NSAPI_ERROR_DHCP_FAILURE; } From 8dceef0492e718588b72da67c2ca548e11ba64f0 Mon Sep 17 00:00:00 2001 From: Jammu Kekkonen Date: Fri, 3 Nov 2017 18:25:02 +0200 Subject: [PATCH 27/80] HEXIWEAR: define HEXIWEAR target to support bootloader. --- targets/targets.json | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 68b18fadeb..d4f6a93f2c 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -642,7 +642,8 @@ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"], "default_lib": "std", "release_versions": ["2", "5"], - "device_name": "MK64FN1M0xxx12" + "device_name": "MK64FN1M0xxx12", + "bootloader_supported": true }, "K66F": { "supported_form_factors": ["ARDUINO"], From 6de5b39f3f6576a4b88eb668c7a14a6778f10f8a Mon Sep 17 00:00:00 2001 From: Andrea Corrado Date: Thu, 12 Oct 2017 11:21:20 +0100 Subject: [PATCH 28/80] introduced mbed Connect Cloud board based on ODIN-W2 Module rety commit, added ublox changes Corrected error Corrected error in targets json Reworked JSON Added lwip-eth to Connect ODIN removes ARM CC error Fixed formating issues Correct formating error in .json Indentation errors --- .../stm32f4_eth_conf.c | 61 ++++++ .../stm32f4_eth_init.c | 143 +++++++++++++++ .../stm32f4_eth_conf.c | 6 +- .../stm32f4_eth_init.c | 14 +- .../PeripheralNames.h | 0 .../PeripheralPins.c | 0 .../TARGET_MBED_CONNECT_ODIN/PinNames.h | 173 ++++++++++++++++++ .../TARGET_UBLOX_EVK_ODIN_W2/PinNames.h | 13 ++ .../sdk/LICENSE | 0 .../LICENSE-permissive-binary-license-1.0.txt | 0 .../TOOLCHAIN_ARM/libublox-odin-w2-driver.ar | Bin .../libublox-odin-w2-driver.a | Bin .../TOOLCHAIN_IAR/libublox-odin-w2-driver.a | Bin .../ublox-odin-w2-drivers/OdinWiFiInterface.h | 0 .../sdk/ublox-odin-w2-drivers/bt_types.h | 0 .../sdk/ublox-odin-w2-drivers/cb_assert.h | 0 .../ublox-odin-w2-drivers/cb_bt_conn_man.h | 0 .../sdk/ublox-odin-w2-drivers/cb_bt_man.h | 0 .../sdk/ublox-odin-w2-drivers/cb_bt_pan.h | 0 .../sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h | 0 .../sdk/ublox-odin-w2-drivers/cb_bt_serial.h | 0 .../ublox-odin-w2-drivers/cb_bt_serial_le.h | 0 .../ublox-odin-w2-drivers/cb_bt_test_man.h | 0 .../sdk/ublox-odin-w2-drivers/cb_bt_utils.h | 0 .../sdk/ublox-odin-w2-drivers/cb_cert_utils.h | 0 .../sdk/ublox-odin-w2-drivers/cb_comdefs.h | 0 .../sdk/ublox-odin-w2-drivers/cb_gatt.h | 0 .../ublox-odin-w2-drivers/cb_gatt_client.h | 0 .../ublox-odin-w2-drivers/cb_gatt_server.h | 0 .../sdk/ublox-odin-w2-drivers/cb_gatt_utils.h | 0 .../sdk/ublox-odin-w2-drivers/cb_hw.h | 0 .../sdk/ublox-odin-w2-drivers/cb_main.h | 0 .../sdk/ublox-odin-w2-drivers/cb_otp.h | 0 .../cb_platform_basic_types.h | 0 .../sdk/ublox-odin-w2-drivers/cb_port_types.h | 0 .../sdk/ublox-odin-w2-drivers/cb_status.h | 0 .../sdk/ublox-odin-w2-drivers/cb_types.h | 0 .../sdk/ublox-odin-w2-drivers/cb_watchdog.h | 0 .../sdk/ublox-odin-w2-drivers/cb_wlan.h | 0 .../cb_wlan_target_data.h | 0 .../sdk/ublox-odin-w2-drivers/cb_wlan_types.h | 0 .../sdk/wifi_emac/wifi_emac_api.cpp | 0 .../sdk/wifi_emac/wifi_emac_api.h | 0 .../system_clock.c | 0 targets/targets.json | 30 ++- 45 files changed, 425 insertions(+), 15 deletions(-) create mode 100644 features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_conf.c create mode 100644 features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_init.c rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/PeripheralNames.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/PeripheralPins.c (100%) create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{ => TARGET_MODULE_UBLOX_ODIN_W2}/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h (95%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/LICENSE (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/LICENSE-permissive-binary-license-1.0.txt (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/bt_types.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_assert.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_bt_man.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_bt_pan.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_bt_serial.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_bt_serial_le.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_bt_utils.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_cert_utils.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_comdefs.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_gatt.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_gatt_client.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_gatt_server.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_hw.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_main.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_otp.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_port_types.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_status.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_types.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_watchdog.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_wlan.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/ublox-odin-w2-drivers/cb_wlan_types.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/wifi_emac/wifi_emac_api.cpp (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/sdk/wifi_emac/wifi_emac_api.h (100%) rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/{TARGET_UBLOX_EVK_ODIN_W2 => TARGET_MODULE_UBLOX_ODIN_W2}/system_clock.c (100%) mode change 100644 => 100755 targets/targets.json diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_conf.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_conf.c new file mode 100644 index 0000000000..56f754a4f4 --- /dev/null +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_conf.c @@ -0,0 +1,61 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "stm32f4xx_hal.h" + +void _eth_config_mac(ETH_HandleTypeDef *heth) +{ + ETH_MACInitTypeDef macconf = + { + .Watchdog = ETH_WATCHDOG_ENABLE, + .Jabber = ETH_JABBER_ENABLE, + .InterFrameGap = ETH_INTERFRAMEGAP_96BIT, + .CarrierSense = ETH_CARRIERSENCE_ENABLE, + .ReceiveOwn = ETH_RECEIVEOWN_ENABLE, + .LoopbackMode = ETH_LOOPBACKMODE_DISABLE, + .ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE, + .RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE, + .AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE, + .BackOffLimit = ETH_BACKOFFLIMIT_10, + .DeferralCheck = ETH_DEFFERRALCHECK_DISABLE, + .ReceiveAll = ETH_RECEIVEAll_DISABLE, + .SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE, + .PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL, + .BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE, + .DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL, + .PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE, + .MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_NONE, // Disable multicast filter + .UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT, + .HashTableHigh = 0x0U, + .HashTableLow = 0x0U, + .PauseTime = 0x0U, + .ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE, + .PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4, + .UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE, + .ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE, + .TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE, + .VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT, + .VLANTagIdentifier = 0x0U + }; + + if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) { + macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; + } else { + macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE; + } + + (void) HAL_ETH_ConfigMAC(heth, &macconf); +} diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_init.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_init.c new file mode 100644 index 0000000000..f9ee0771e7 --- /dev/null +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_init.c @@ -0,0 +1,143 @@ +#include +#include "stm32f4xx_hal.h" +#include "mbed_toolchain.h" + +#define C029_OTP_START_ADDRESS (0x1FFF7800U) +#define C029_OTP_END_ADDRESS (C029_OTP_START_ADDRESS + (16*32)) +#define C029_MAC_ETHERNET_ID (3) + +typedef MBED_PACKED(struct) C029_OTP_Header { + uint8_t id; + uint8_t len; + uint8_t data[]; +} C029_OTP_Header; + +static int _macRetrieved = 0; +static char _macAddr[6] = { 0x02, 0x02, 0xF7, 0xF0, 0x00, 0x00 }; + +static C029_OTP_Header *increment(C029_OTP_Header *pTemp) +{ + uint8_t len = 0; + uint8_t id = 0; + uint8_t *p = (uint8_t*)pTemp; + + memcpy((void*)&id, (void*)pTemp, 1); + + if (id == 0xFF){ + p++; + } else { + p++; + memcpy((void*)&len, (void*)p++, 1); + p += len; + } + return (C029_OTP_Header*)p; +} + +/** + * Override HAL Eth Init function + */ +void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +{ + GPIO_InitTypeDef GPIO_InitStructure; + if (heth->Instance == ETH) { + + /* Enable GPIOs clocks */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + + /** ETH GPIO Configuration + RMII_REF_CLK ----------------------> PA1 + RMII_MDIO -------------------------> PA2 + RMII_MDC --------------------------> PC1 + RMII_MII_CRS_DV -------------------> PA7 + RMII_MII_RXD0 ---------------------> PC4 + RMII_MII_RXD1 ---------------------> PC5 + RMII_MII_RXER ---------------------> PG2 + RMII_MII_TX_EN --------------------> PB11 + RMII_MII_TXD0 ---------------------> PB12 + RMII_MII_TXD1 ---------------------> PB13 + */ + /* Configure PA1, PA2 and PA7 */ + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; + GPIO_InitStructure.Pull = GPIO_PULLUP; + GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_7; + GPIO_InitStructure.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); + + GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Pin = GPIO_PIN_1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Configure PB13 */ + GPIO_InitStructure.Pin = GPIO_PIN_13 | GPIO_PIN_11 | GPIO_PIN_12; + HAL_GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Configure PC1, PC4 and PC5 */ + GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; + HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Enable the Ethernet global Interrupt */ + HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0); + HAL_NVIC_EnableIRQ(ETH_IRQn); + + /* Enable ETHERNET clock */ + __HAL_RCC_ETH_CLK_ENABLE(); + } +} + +/** + * Override HAL Eth DeInit function + */ +void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +{ + if (heth->Instance == ETH) { + /* Peripheral clock disable */ + __HAL_RCC_ETH_CLK_DISABLE(); + + /** ETH GPIO Configuration + RMII_REF_CLK ----------------------> PA1 + RMII_MDIO -------------------------> PA2 + RMII_MDC --------------------------> PC1 + RMII_MII_CRS_DV -------------------> PA7 + RMII_MII_RXD0 ---------------------> PC4 + RMII_MII_RXD1 ---------------------> PC5 + RMII_MII_RXER ---------------------> PG2 + RMII_MII_TX_EN --------------------> PB11 + RMII_MII_TXD0 ---------------------> PB12 + RMII_MII_TXD1 ---------------------> PB13 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13 | GPIO_PIN_11 | GPIO_PIN_12); + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); + + /* Disable the Ethernet global Interrupt */ + NVIC_DisableIRQ(ETH_IRQn); + } +} + +uint8_t mbed_otp_mac_address(char *mac) +{ + C029_OTP_Header *pFound = NULL; + C029_OTP_Header *pTemp = (C029_OTP_Header*)C029_OTP_START_ADDRESS; + C029_OTP_Header temp; + + if (_macRetrieved == 0) { + while ((pTemp >= (C029_OTP_Header*)C029_OTP_START_ADDRESS) && (pTemp < (C029_OTP_Header*)C029_OTP_END_ADDRESS)){ + memcpy((void*)&temp, (void*)pTemp, sizeof(temp)); + if (temp.id == C029_MAC_ETHERNET_ID){ + pFound = pTemp; + break; + } + pTemp = increment(pTemp); + } + if (pFound != NULL) { + memcpy(_macAddr, pFound->data, 6); + _macRetrieved = 1; + } + } + memcpy(mac, _macAddr, 6); + + return 1; +} diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_conf.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_conf.c index 7325f42caf..56f754a4f4 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_conf.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_conf.c @@ -19,7 +19,7 @@ void _eth_config_mac(ETH_HandleTypeDef *heth) { ETH_MACInitTypeDef macconf = - { + { .Watchdog = ETH_WATCHDOG_ENABLE, .Jabber = ETH_JABBER_ENABLE, .InterFrameGap = ETH_INTERFRAMEGAP_96BIT, @@ -48,8 +48,8 @@ void _eth_config_mac(ETH_HandleTypeDef *heth) .ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE, .TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE, .VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT, - .VLANTagIdentifier = 0x0U, - }; + .VLANTagIdentifier = 0x0U + }; if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) { macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_init.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_init.c index 89fd896139..f9ee0771e7 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_init.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_init.c @@ -25,8 +25,7 @@ static C029_OTP_Header *increment(C029_OTP_Header *pTemp) if (id == 0xFF){ p++; - } - else { + } else { p++; memcpy((void*)&len, (void*)p++, 1); p += len; @@ -59,31 +58,30 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) RMII_MII_TXD0 ---------------------> PB12 RMII_MII_TXD1 ---------------------> PB13 */ - /* Configure PA1, PA2 and PA7 */ + /* Configure PA1, PA2 and PA7 */ GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; GPIO_InitStructure.Pull = GPIO_PULLUP; GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_7; GPIO_InitStructure.Alternate = GPIO_AF11_ETH; HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); - + GPIO_InitStructure.Pull = GPIO_NOPULL; GPIO_InitStructure.Pin = GPIO_PIN_1; HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); /* Configure PB13 */ - GPIO_InitStructure.Pin = GPIO_PIN_13 | GPIO_PIN_11 | GPIO_PIN_12; + GPIO_InitStructure.Pin = GPIO_PIN_13 | GPIO_PIN_11 | GPIO_PIN_12; HAL_GPIO_Init(GPIOB, &GPIO_InitStructure); /* Configure PC1, PC4 and PC5 */ GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; - HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); - + HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); /* Enable the Ethernet global Interrupt */ HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0); HAL_NVIC_EnableIRQ(ETH_IRQn); - + /* Enable ETHERNET clock */ __HAL_RCC_ETH_CLK_ENABLE(); } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PeripheralNames.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralPins.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PeripheralPins.c rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralPins.c diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h new file mode 100644 index 0000000000..ea26b94807 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h @@ -0,0 +1,173 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, PA_3 = 0x03, + PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07, + PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, + PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, + + PB_0 = 0x10, PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13, + PB_4 = 0x14, PB_5 = 0x15, PB_6 = 0x16, PB_7 = 0x17, + PB_8 = 0x18, PB_9 = 0x19, PB_10 = 0x1A, PB_11 = 0x1B, + PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F, + + PC_0 = 0x20, PC_1 = 0x21, PC_2 = 0x22, PC_3 = 0x23, + PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, PC_7 = 0x27, + PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, PC_11 = 0x2B, + PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, PC_15 = 0x2F, + + PD_0 = 0x30, PD_1 = 0x31, PD_2 = 0x32, PD_3 = 0x33, + PD_4 = 0x34, PD_5 = 0x35, PD_6 = 0x36, PD_7 = 0x37, + PD_8 = 0x38, PD_9 = 0x39, PD_10 = 0x3A, PD_11 = 0x3B, + PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F, + + PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, PE_3 = 0x43, + PE_4 = 0x44, PE_5 = 0x45, PE_6 = 0x46, PE_7 = 0x47, + PE_8 = 0x48, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B, + PE_12 = 0x4C, PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F, + + PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, PF_3 = 0x53, + PF_4 = 0x54, PF_5 = 0x55, PF_6 = 0x56, PF_7 = 0x57, + PF_8 = 0x58, PF_9 = 0x59, PF_10 = 0x5A, PF_11 = 0x5B, + PF_12 = 0x5C, PF_13 = 0x5D, PF_14 = 0x5E, PF_15 = 0x5F, + + PG_0 = 0x60, PG_1 = 0x61, PG_2 = 0x62, PG_3 = 0x63, + PG_4 = 0x64, PG_5 = 0x65, PG_6 = 0x66, PG_7 = 0x67, + PG_8 = 0x68, PG_9 = 0x69, PG_10 = 0x6A, PG_11 = 0x6B, + PG_12 = 0x6C, PG_13 = 0x6D, PG_14 = 0x6E, PG_15 = 0x6F, + + PH_0 = 0x70, PH_1 = 0x71, PH_2 = 0x72, PH_3 = 0x73, + PH_4 = 0x74, PH_5 = 0x75, PH_6 = 0x76, PH_7 = 0x77, + PH_8 = 0x78, PH_9 = 0x79, PH_10 = 0x7A, PH_11 = 0x7B, + PH_12 = 0x7C, PH_13 = 0x7D, PH_14 = 0x7E, PH_15 = 0x7F, + + // Module Pins + // A + P_A5 = PC_2, // UART-DTR + P_A6 = PF_2, // Switch-0 + P_A7 = PE_0, // Red, Mode + P_A8 = PB_6, // Green, Switch-1 + P_A9 = PB_8, // Blue + P_A10 = PA_11, // UART-CTS + P_A11 = PA_9, // UART-TXD + P_A12 = PA_12, // UART-RTS + P_A13 = PA_10, // UART-RXD + P_A14 = PD_9, // GPIO-0 + P_A15 = PD_8, // GPIO-1 + P_A16 = PD_11, // GPIO-2 + P_A17 = PD_12, // GPIO-3 + P_A18 = PA_3, // UART-DSR + // B + // C + P_C5 = PG_4, // SPI-IRQ + P_C6 = PE_13, // SPI-MISO + P_C8 = PE_12, // Res + P_C10 = PE_14, // SPI-MOSI + P_C11 = PE_11, // SPI-CS0 + P_C12 = PE_9, // Res + P_C13 = PF_6, // GPIO-4 + P_C14 = PC_1, // RMII-MDC + P_C15 = PA_2, // RMII-MDIO + P_C16 = PF_7, // GPIO-7 + P_C17 = PF_1, // I2C-SCL + P_C18 = PF_0, // I2C-SDA + // D + P_D1 = PB_12, // RMII-TXD0 + P_D2 = PB_13, // RMII-TXD1 + P_D3 = PB_11, // RMII-TXEN + P_D4 = PA_7, // RMII-CRSDV + P_D5 = PC_4, // RMII-RXD0 + P_D6 = PC_5, // RMII-RXD1 + P_D8 = PA_1, // RMII-REFCLK + // TP + P_TP5 = PB_4, // NTRST + P_TP7 = PA_13, // TMS SWDIO + P_TP8 = PA_15, // TDI + P_TP9 = PA_14, // TCK SWCLK + P_TP10 = PB_3, // TDO + //P_TP11, // BOOT0 + + // Internal + LED1 = PD_9, + LED2 = PA_12, + LED3 = PD_8, + LED4 = PA_11, + LED5 = PC_2, + LED6 = PA_3, + LED7 = PF_6, + LED_RED = PE_0, + LED_GREEN = PB_6, + LED_BLUE = PB_8, + SW1 = PF_2, + SW2 = PG_4, + + // Standardized button names + BUTTON1 = SW1, + BUTTON2 = SW2, + + I2C_SDA = PF_0, + I2C_SCL = PF_1, + SPI0_MOSI = PE_14, + SPI0_MISO = PE_13, + SPI0_SCK = PE_12, + SPI0_CS = PE_11, + SPI1_CS = PE_9, + + SPI_MOSI = SPI0_MOSI, + SPI_MISO = SPI0_MISO, + SPI_SCK = SPI0_SCK, + SPI_CS = SPI0_CS, + + // DAPLink + USBRX = MBED_CONF_TARGET_USB_RX, + USBTX = MBED_CONF_TARGET_USB_TX, + SWDIO = PA_15, + SWCLK = PA_14, + NTRST = PB_4, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h similarity index 95% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h index 1be288b161..e6b09b7502 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h @@ -159,6 +159,19 @@ typedef enum { LED_BLUE = LED3, SW0 = PF_2, // Switch-0 SW1 = PB_6, // Green / Switch-1 + + I2C_SCL = D15, + I2C_SDA = D14, + SPI0_MOSI = D11, + SPI0_MISO = D12, + SPI0_SCK = D13, + SPI0_CS = D10, + SPI1_CS = D9, + + SPI_MOSI = SPI0_MOSI, + SPI_MISO = SPI0_MISO, + SPI_SCK = SPI0_SCK, + SPI_CS = SPI0_CS, // Standardized button names diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/LICENSE b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/LICENSE similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/LICENSE rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/LICENSE diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/LICENSE-permissive-binary-license-1.0.txt b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/LICENSE-permissive-binary-license-1.0.txt similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/LICENSE-permissive-binary-license-1.0.txt rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/LICENSE-permissive-binary-license-1.0.txt diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_assert.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_assert.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_assert.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_assert.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial_le.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial_le.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial_le.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial_le.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_cert_utils.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_cert_utils.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_cert_utils.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_cert_utils.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/wifi_emac/wifi_emac_api.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/wifi_emac/wifi_emac_api.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/system_clock.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/system_clock.c rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/system_clock.c diff --git a/targets/targets.json b/targets/targets.json old mode 100644 new mode 100755 index d4f6a93f2c..ccfcd28528 --- a/targets/targets.json +++ b/targets/targets.json @@ -1725,18 +1725,21 @@ "device_has_add": [], "device_name": "STM32F401VC" }, - "UBLOX_EVK_ODIN_W2": { + "MODULE_UBLOX_ODIN_W2": { "inherits": ["FAMILY_STM32"], - "supported_form_factors": ["ARDUINO"], "core": "Cortex-M4F", "extra_labels_add": ["STM32F4", "STM32F439", "STM32F439ZI","STM32F439xx", "STM32F439xI"], "macros": ["MBEDTLS_CONFIG_HW_SUPPORT", "HSE_VALUE=24000000", "HSE_STARTUP_TIMEOUT=5000", "CB_INTERFACE_SDIO","CB_CHIP_WL18XX","SUPPORT_80211D_ALWAYS","WLAN_ENABLED","MBEDTLS_ARC4_C","MBEDTLS_DES_C","MBEDTLS_MD4_C","MBEDTLS_MD5_C","MBEDTLS_SHA1_C"], "device_has_add": ["CAN", "EMAC", "TRNG", "FLASH"], "device_has_remove": ["RTC", "SLEEP"], "features": ["LWIP"], - "release_versions": ["5"], "device_name": "STM32F439ZI", - "bootloader_supported": true, + "bootloader_supported": true + }, + "UBLOX_EVK_ODIN_W2": { + "inherits": ["MODULE_UBLOX_ODIN_W2"], + "supported_form_factors": ["ARDUINO"], + "release_versions": ["5"], "config": { "usb_tx": { "help": "Value: D8(default) or D1", @@ -1753,6 +1756,25 @@ } } }, + "MBED_CONNECT_ODIN": { + "inherits": ["MODULE_UBLOX_ODIN_W2"], + "release_versions": ["5"], + "config": { + "usb_tx": { + "help": "Value: PA_9(default) or PD_8", + "value": "PA_9" + }, + "usb_rx": { + "help": "Value: PA_10(default) or PD_9", + "value": "PA_10" + }, + "stdio_uart": { + "help": "Value: UART_1(default) or UART_3", + "value": "UART_1", + "macro_name": "STDIO_UART" + } + } + }, "UBLOX_C030": { "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO"], From 0105347b93ff07ba4bae94a4dd41e88d827538d0 Mon Sep 17 00:00:00 2001 From: Dave Wu Date: Wed, 20 Sep 2017 14:37:22 +1000 Subject: [PATCH 29/80] Added support for ADI EV-COG-AD4050LZ platform. --- .../TARGET_ADUCM4050/.mbedignore | 28 + .../TARGET_EV_COG_AD4050LZ/PeripheralNames.h | 136 + .../TARGET_EV_COG_AD4050LZ/PinNames.h | 221 + .../device/startup_ADuCM4050.c | 286 + .../device/startup_ADuCM4050.h | 236 + .../device/system_ADuCM4050.c | 322 + .../TOOLCHAIN_ARM_STD/ADuCM4050.sct | 52 + .../TOOLCHAIN_GCC_ARM/ADuCM4050.ld | 214 + .../TOOLCHAIN_IAR/ADuCM4050.icf | 48 + .../TARGET_ADUCM4050/api/PeripheralPins.c | 138 + .../TARGET_ADUCM4050/api/PeripheralPins.h | 67 + .../TARGET_ADUCM4050/api/analogin_api.c | 216 + .../TARGET_ADUCM4050/api/cmsis.h | 46 + .../TARGET_ADUCM4050/api/cmsis_nvic.h | 78 + .../TARGET_ADUCM4050/api/device.h | 48 + .../TARGET_ADUCM4050/api/flash_api.c | 89 + .../TARGET_ADUCM4050/api/gpio_api.c | 144 + .../TARGET_ADUCM4050/api/gpio_dev_mem.c | 47 + .../TARGET_ADUCM4050/api/gpio_irq_api.c | 317 + .../TARGET_ADUCM4050/api/gpio_object.h | 61 + .../TARGET_ADUCM4050/api/i2c_api.c | 238 + .../TARGET_ADUCM4050/api/lp_ticker_api.c | 269 + .../TARGET_ADUCM4050/api/objects.h | 112 + .../TARGET_ADUCM4050/api/pinmap.c | 103 + .../TARGET_ADUCM4050/api/rtc_api.c | 94 + .../TARGET_ADUCM4050/api/serial_api.c | 352 + .../TARGET_ADUCM4050/api/sleep.c | 255 + .../TARGET_ADUCM4050/api/sleep.h | 69 + .../TARGET_ADUCM4050/api/spi_api.c | 346 + .../TARGET_ADUCM4050/api/trng_api.c | 96 + .../TARGET_ADUCM4050/api/us_ticker.c | 346 + .../TARGET_ADUCM4050/bsp/ADuCM4050.h | 26 + .../TARGET_ADUCM4050/bsp/ADuCM4050_cdef.h | 18 + .../TARGET_ADUCM4050/bsp/ADuCM4050_def.h | 34 + .../TARGET_ADUCM4050/bsp/ADuCM4050_device.h | 29 + .../TARGET_ADUCM4050/bsp/ADuCM4050_typedefs.h | 31 + .../TARGET_ADUCM4050/bsp/adc/adi_adc.c | 2371 ++++ .../TARGET_ADUCM4050/bsp/adc/adi_adc_data.c | 19 + .../TARGET_ADUCM4050/bsp/adc/adi_adc_def.h | 120 + .../TARGET_ADUCM4050/bsp/adi_callback.h | 60 + .../TARGET_ADUCM4050/bsp/adi_cyclecount.h | 137 + .../TARGET_ADUCM4050/bsp/adi_processor.h | 67 + .../TARGET_ADUCM4050/bsp/adi_types.h | 18 + .../TARGET_ADUCM4050/bsp/adi_version.h | 63 + .../TARGET_ADUCM4050/bsp/beep/adi_beep.c | 751 ++ .../TARGET_ADUCM4050/bsp/beep/adi_beep_def.h | 128 + .../TARGET_ADUCM4050/bsp/common.h | 127 + .../bsp/config/adi_adc_config.h | 342 + .../bsp/config/adi_beep_config.h | 164 + .../bsp/config/adi_crc_config.h | 100 + .../bsp/config/adi_crypto_config.h | 138 + .../bsp/config/adi_cycle_counting_config.h | 105 + .../bsp/config/adi_flash_config.h | 299 + .../bsp/config/adi_global_config.h | 131 + .../bsp/config/adi_i2c_config.h | 226 + .../bsp/config/adi_pwr_config.h | 638 + .../bsp/config/adi_rng_config.h | 106 + .../bsp/config/adi_rtc_config.h | 397 + .../bsp/config/adi_spi_config.h | 592 + .../bsp/config/adi_sport_config.h | 355 + .../bsp/config/adi_tmr_config.h | 902 ++ .../bsp/config/adi_uart_config.h | 496 + .../bsp/config/adi_wdt_config.h | 119 + .../TARGET_ADUCM4050/bsp/crc/adi_crc.c | 1279 ++ .../TARGET_ADUCM4050/bsp/crc/adi_crc_def.h | 92 + .../TARGET_ADUCM4050/bsp/crypto/adi_crypto.c | 1577 +++ .../bsp/crypto/adi_crypto_def.h | 209 + .../TARGET_ADUCM4050/bsp/dma/adi_dma.c | 346 + .../bsp/drivers/adc/adi_adc.h | 346 + .../bsp/drivers/beep/adi_beep.h | 277 + .../bsp/drivers/crc/adi_crc.h | 236 + .../bsp/drivers/crypto/adi_crypto.h | 235 + .../bsp/drivers/dma/adi_dma.h | 274 + .../bsp/drivers/flash/adi_flash.h | 185 + .../bsp/drivers/general/adi_data_transfer.h | 127 + .../bsp/drivers/general/adi_drivers_general.h | 98 + .../bsp/drivers/gpio/adi_gpio.h | 174 + .../bsp/drivers/i2c/adi_i2c.h | 243 + .../bsp/drivers/pwr/adi_pwr.h | 689 + .../bsp/drivers/rng/adi_rng.h | 204 + .../bsp/drivers/rtc/adi_rtc.h | 521 + .../bsp/drivers/spi/adi_spi.h | 386 + .../bsp/drivers/sport/adi_sport.h | 236 + .../bsp/drivers/tmr/adi_tmr.h | 253 + .../bsp/drivers/uart/adi_uart.h | 498 + .../bsp/drivers/wdt/adi_wdt.h | 77 + .../bsp/drivers/xint/adi_xint.h | 120 + .../TARGET_ADUCM4050/bsp/flash/adi_flash.c | 1812 +++ .../bsp/flash/adi_flash_data.c | 116 + .../bsp/flash/adi_flash_def.h | 181 + .../TARGET_ADUCM4050/bsp/gpio/adi_gpio.c | 975 ++ .../TARGET_ADUCM4050/bsp/gpio/adi_gpio_def.h | 94 + .../TARGET_ADUCM4050/bsp/i2c/adi_i2c.c | 1169 ++ .../TARGET_ADUCM4050/bsp/i2c/adi_i2c_data.c | 120 + .../TARGET_ADUCM4050/bsp/i2c/adi_i2c_def.h | 129 + .../TARGET_ADUCM4050/bsp/pwr/adi_pwr.c | 1904 +++ .../TARGET_ADUCM4050/bsp/pwr/adi_pwr_def.h | 172 + .../bsp/retarget_uart_config.h | 27 + .../TARGET_ADUCM4050/bsp/rng/adi_rng.c | 796 ++ .../TARGET_ADUCM4050/bsp/rng/adi_rng_def.h | 69 + .../TARGET_ADUCM4050/bsp/rtc/adi_rtc.c | 2608 ++++ .../TARGET_ADUCM4050/bsp/rtc/adi_rtc_data.c | 190 + .../TARGET_ADUCM4050/bsp/rtc/adi_rtc_def.h | 163 + .../bsp/rtos_map/adi_rtos_map.h | 71 + .../bsp/rtos_map/adi_rtos_map_freertos.h | 144 + .../bsp/rtos_map/adi_rtos_map_noos.h | 180 + .../bsp/rtos_map/adi_rtos_map_ucos_ii.h | 149 + .../bsp/rtos_map/adi_rtos_map_ucos_iii.h | 167 + .../TARGET_ADUCM4050/bsp/spi/adi_spi.c | 1892 +++ .../TARGET_ADUCM4050/bsp/spi/adi_spi_data.c | 162 + .../TARGET_ADUCM4050/bsp/spi/adi_spi_def.h | 148 + .../TARGET_ADUCM4050/bsp/sport/adi_sport.c | 1771 +++ .../bsp/sport/adi_sport_def.h | 193 + .../TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050.h | 5339 ++++++++ .../bsp/sys/adi_ADuCM4050_cdef.h | 788 ++ .../bsp/sys/adi_ADuCM4050_device.h | 1338 ++ .../bsp/sys/adi_ADuCM4050_typedefs.h | 11252 ++++++++++++++++ .../TARGET_ADUCM4050/bsp/sys/adi_cio_macros.h | 50 + .../TARGET_ADUCM4050/bsp/sys/platform.h | 56 + .../TARGET_ADUCM4050/bsp/system_ADuCM4050.h | 159 + .../TARGET_ADUCM4050/bsp/tmr/adi_tmr.c | 611 + .../TARGET_ADUCM4050/bsp/tmr/adi_tmr_data.c | 155 + .../TARGET_ADUCM4050/bsp/uart/adi_uart.c | 2779 ++++ .../TARGET_ADUCM4050/bsp/uart/adi_uart_def.h | 214 + .../TARGET_ADUCM4050/bsp/wdt/adi_wdt.c | 225 + .../TARGET_ADUCM4050/bsp/xint/adi_xint.c | 413 + .../TARGET_ADUCM4050/bsp/xint/adi_xint_def.h | 61 + targets/TARGET_Analog_Devices/mbed_rtx.h | 58 + targets/targets.json | 19 +- 129 files changed, 61780 insertions(+), 4 deletions(-) create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/.mbedignore create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PeripheralNames.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PinNames.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/system_ADuCM4050.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_ARM_STD/ADuCM4050.sct create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_GCC_ARM/ADuCM4050.ld create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_IAR/ADuCM4050.icf create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis_nvic.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/device.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/flash_api.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_dev_mem.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_object.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/lp_ticker_api.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/pinmap.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/rtc_api.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/us_ticker.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_cdef.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_def.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_device.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_typedefs.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_data.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_def.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_callback.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_cyclecount.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_processor.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_types.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_version.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep_def.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/common.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_adc_config.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_beep_config.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crc_config.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crypto_config.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_cycle_counting_config.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_flash_config.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_global_config.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_i2c_config.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_pwr_config.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rng_config.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rtc_config.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_spi_config.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_sport_config.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_tmr_config.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_uart_config.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_wdt_config.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc_def.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto_def.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/dma/adi_dma.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/adc/adi_adc.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/beep/adi_beep.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crc/adi_crc.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crypto/adi_crypto.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/dma/adi_dma.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/flash/adi_flash.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_data_transfer.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_drivers_general.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/gpio/adi_gpio.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/i2c/adi_i2c.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/pwr/adi_pwr.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rng/adi_rng.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rtc/adi_rtc.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/spi/adi_spi.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/sport/adi_sport.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/tmr/adi_tmr.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/uart/adi_uart.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/wdt/adi_wdt.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/xint/adi_xint.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_data.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_def.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio_def.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_data.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_def.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr_def.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/retarget_uart_config.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng_def.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_data.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_def.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_freertos.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_noos.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_ii.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_iii.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_data.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_def.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport_def.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_cdef.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_device.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_typedefs.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_cio_macros.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/platform.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/system_ADuCM4050.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr_data.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart_def.h create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/wdt/adi_wdt.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint.c create mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint_def.h create mode 100755 targets/TARGET_Analog_Devices/mbed_rtx.h diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/.mbedignore b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/.mbedignore new file mode 100755 index 0000000000..94a9f73e3f --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/.mbedignore @@ -0,0 +1,28 @@ +bsp/adc/adi_adc_data.c +bsp/adc/adi_adc_data_v1.c +bsp/adc/adi_adc_v1.c +bsp/beep/adi_beep_v1.c +bsp/crc/adi_crc_data.c +bsp/crc/adi_crc_v1.c +bsp/crypto/adi_crypto_v1.c +bsp/dma/adi_dma_pl230_v2.c +bsp/flash/adi_flash_data.c +bsp/flash/adi_flash_v1.c +bsp/gpio/adi_gpio_v1.c +bsp/i2c/adi_i2c_data.c +bsp/i2c/adi_i2c_v1.c +bsp/pwr/adi_pwr_v1.c +bsp/rtc/adi_rtc_data.c +bsp/rtc/adi_rtc_data_v1.c +bsp/rtc/adi_rtc_v1.c +bsp/sport/adi_sport_data_v1.c +bsp/sport/adi_sport_v1.c +bsp/uart/adi_uart_data_v1.c +bsp/uart/adi_uart_v1.c +bsp/spi/adi_spi_data.c +bsp/spi/adi_spi_data_v1.c +bsp/spi/adi_spi_v1.c +bsp/tmr/adi_tmr_data.c +bsp/tmr/adi_tmr_data_v1.c +bsp/tmr/adi_tmr_v1.c +bsp/wdt/adi_wdt_v1.c diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PeripheralNames.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PeripheralNames.h new file mode 100755 index 0000000000..c1cfd6c14a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PeripheralNames.h @@ -0,0 +1,136 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OSC32KCLK = 0, +} RTCName; + +typedef enum { + UART_0 = 0, + UART_1 = 1, + UART_2 = 2, + UART_3 = 3, + UART_4 = 4, +} UARTName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +typedef enum { + I2C_0 = 0, + I2C_1 = 1, + I2C_2 = 2, +} I2CName; + +#define TPM_SHIFT 8 +typedef enum { + PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 + PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 + PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 + PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 + PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 + PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 + PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 + PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2 + PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3 + PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4 + PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5 + PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6 + PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7 + PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 + PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 + PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2 + PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3 + PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4 + PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5 + PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6 + PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7 + // could be 4 or could be 3... not sure what register + // this is for... too much abstraction + PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 + PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 + PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 + PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 + PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 + PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 + PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 + PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 +} PWMName; + +typedef enum { + ADC0_VIN0 = 0, + ADC0_VIN1 = 1, + ADC0_VIN2 = 2, + ADC0_VIN3 = 3, + ADC0_VIN4 = 4, + ADC0_VIN5 = 5, + ADC0_VIN6 = 6, + ADC0_VIN7 = 7 +} ADCName; + +typedef enum { + DAC_0 = 0 +} DACName; + + +typedef enum { + SPI_0 = 0, + SPI_1 = 1, + SPI_2 = 2, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PinNames.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PinNames.h new file mode 100755 index 0000000000..3192608f78 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PinNames.h @@ -0,0 +1,221 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +/* + The ADuCM4050 is made in two package variants. + + 64 lead LFCSP & 72 ball WLCSP + + There are some differences for Port 2 between the two variants + WLCSP also has Port 3. + + The #define ADUCM4050_LFCSP is used to determine which variant the code + is built for. + + For LFCSP leave the #define in, to build for ADUCM4050_WLCSP remove. +*/ +#define ADUCM4050_LFCSP + +#include "cmsis.h" + +#include "adi_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +//update + +#define GPIO_PORT_SHIFT 12 + + +typedef enum { + P0_00 = (0 << GPIO_PORT_SHIFT | 0 ), + P0_01 = (0 << GPIO_PORT_SHIFT | 1 ), + P0_02 = (0 << GPIO_PORT_SHIFT | 2 ), + P0_03 = (0 << GPIO_PORT_SHIFT | 3 ), + P0_04 = (0 << GPIO_PORT_SHIFT | 4 ), + P0_05 = (0 << GPIO_PORT_SHIFT | 5 ), + P0_06 = (0 << GPIO_PORT_SHIFT | 6 ), + P0_07 = (0 << GPIO_PORT_SHIFT | 7 ), + P0_08 = (0 << GPIO_PORT_SHIFT | 8 ), + P0_09 = (0 << GPIO_PORT_SHIFT | 9 ), + P0_10 = (0 << GPIO_PORT_SHIFT | 10), + P0_11 = (0 << GPIO_PORT_SHIFT | 11), + P0_12 = (0 << GPIO_PORT_SHIFT | 12), + P0_13 = (0 << GPIO_PORT_SHIFT | 13), + P0_14 = (0 << GPIO_PORT_SHIFT | 14), + P0_15 = (0 << GPIO_PORT_SHIFT | 15), + P1_00 = (1 << GPIO_PORT_SHIFT | 0 ), + P1_01 = (1 << GPIO_PORT_SHIFT | 1 ), + P1_02 = (1 << GPIO_PORT_SHIFT | 2 ), + P1_03 = (1 << GPIO_PORT_SHIFT | 3 ), + P1_04 = (1 << GPIO_PORT_SHIFT | 4 ), + P1_05 = (1 << GPIO_PORT_SHIFT | 5 ), + P1_06 = (1 << GPIO_PORT_SHIFT | 6 ), + P1_07 = (1 << GPIO_PORT_SHIFT | 7 ), + P1_08 = (1 << GPIO_PORT_SHIFT | 8 ), + P1_09 = (1 << GPIO_PORT_SHIFT | 9 ), + P1_10 = (1 << GPIO_PORT_SHIFT | 10), + P1_11 = (1 << GPIO_PORT_SHIFT | 11), + P1_12 = (1 << GPIO_PORT_SHIFT | 12), + P1_13 = (1 << GPIO_PORT_SHIFT | 13), + P1_14 = (1 << GPIO_PORT_SHIFT | 14), + P1_15 = (1 << GPIO_PORT_SHIFT | 15), + P2_00 = (2 << GPIO_PORT_SHIFT | 0 ), + P2_01 = (2 << GPIO_PORT_SHIFT | 1 ), + P2_02 = (2 << GPIO_PORT_SHIFT | 2 ), + P2_03 = (2 << GPIO_PORT_SHIFT | 3 ), + P2_04 = (2 << GPIO_PORT_SHIFT | 4 ), + P2_05 = (2 << GPIO_PORT_SHIFT | 5 ), + P2_06 = (2 << GPIO_PORT_SHIFT | 6 ), + P2_07 = (2 << GPIO_PORT_SHIFT | 7 ), + P2_08 = (2 << GPIO_PORT_SHIFT | 8 ), + P2_09 = (2 << GPIO_PORT_SHIFT | 9 ), + P2_10 = (2 << GPIO_PORT_SHIFT | 10), + P2_11 = (2 << GPIO_PORT_SHIFT | 11), + + // USB Pins + USBTX = P0_10, + USBRX = P0_11, + USBTX1 = P1_15, + USBRX1 = P2_00, + + // mbed original LED naming + LED1 = P2_02, + LED2 = P2_10, + LED3 = LED2, + LED4 = LED1, + + //Push buttons + PB0 = P1_00, // BTN1 + PB1 = P0_09, // BTN2 + BOOT = P1_01, + WAKE0 = P0_15, // JP15 to select + WAKE1 = P1_00, // JP8 (BTN1 jumper) to select + WAKE2 = P0_13, // JP4 to select + WAKE3 = P2_01, // JP15 to select + + // SPI Pins + SPI0_SCLK = P0_00, + SPI0_MOSI = P0_01, + SPI0_MISO = P0_02, + SPI0_CS0 = P0_03, + SPI0_CS1 = P1_10, + SPI0_CS2 = P2_08, + SPI0_CS3 = P2_09, + + SPI1_SCLK = P1_06, + SPI1_MOSI = P1_07, + SPI1_MISO = P1_08, + SPI1_CS0 = P1_09, + SPI1_CS1 = P2_11, + SPI1_CS2 = P2_02, + SPI1_CS3 = P1_10, + + SPI2_SCLK = P1_02, + SPI2_MOSI = P1_03, + SPI2_MISO = P1_04, + SPI2_CS0 = P1_05, + SPI2_CS1 = P0_09, + SPI2_CS2 = P2_10, + SPI2_CS3 = P2_07, + + // ADC Pins + ADC_VIN0 = P2_03, + ADC_VIN1 = P2_04, + ADC_VIN2 = P2_05, + ADC_VIN3 = P2_06, + ADC_VIN4 = P2_07, + ADC_VIN5 = P2_08, + ADC_VIN6 = P2_09, + ADC_VIN7 = P2_10, + + // Arduino Headers + D0 = P0_10, // UART0_TXD + D1 = P0_11, // UART0_RXD + D2 = P0_15, // INT_WAKE0 + D3 = P0_13, // EXT_INT_WAKE2 + D4 = P0_09, // EXT_SPI2_CS1 + D5 = P2_01, // INT_WAKE3 or EXT_RTC1_SS1 via JP8 + D6 = P1_11, // GPIO_27 + D7 = P0_12, // GPIO_08 or GPIO_12 via JP7 + + D8 = P1_12, // GPIO_28 + D9 = P1_14, // GPIO_30 + D10 = SPI0_CS2, // P2_08 + D11 = SPI0_MOSI, // P0_01 + D12 = SPI0_MISO, // P0_02 + D13 = SPI0_SCLK, // P0_00 + I2C_SCL = P0_04, // I2C_SCL + I2C_SDA = P0_05, // I2C_SDA + + A0 = P2_03, // ADC0 + A1 = P2_04, // EXT_ADC1 + A2 = P2_05, // EXT_ADC2 + A3 = P2_06, // ADC3 + A4 = P2_07, // SPI2_CS3 + A5 = P2_10, // EXT_GPIO42 + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + PullDefault = PullNone +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c new file mode 100755 index 0000000000..b48cc0f83c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c @@ -0,0 +1,286 @@ +/*! + ***************************************************************************** + * @file: startup_ADuCM4050.c + * @brief: Interrupt table and default handlers for ADuCM4x50 + * @version: $Revision: $ + * @date: $Date: $ + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2017 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ +#ifdef __CC_ARM +#include +#include +#endif +#include +#include +#include + +/*---------------------------------------------------------------------------- + Checksum options + *----------------------------------------------------------------------------*/ +#if defined (__CC_ARM) +__attribute__ ((at(0x000001A0u))) +#elif defined(__ICCARM__) +__root +#endif +const uint32_t SECTION_PLACE(blank_checksum[],".checksum") = +{ + BLANKX60,BLANKX600 +}; + +/*---------------------------------------------------------------------------- + A relocated IVT is requested. Provision for IVT relocation + to RAM during startup. This allows for dynamic interrupt + vector patching required by RTOS. Places the relocated IVT + at the start of RAM. We need (72 + 15 + 1)*4 = 352 bytes, + which address 0x20000000. +*----------------------------------------------------------------------------*/ +#ifdef __ICCARM__ +void (*__Relocated___Vectors[NVIC_NUM_VECTORS])(void) @(NVIC_RAM_VECTOR_ADDRESS); +#else +void (*__Relocated___Vectors[NVIC_NUM_VECTORS])(void) __attribute__((at(NVIC_RAM_VECTOR_ADDRESS))); +#endif /* __ICCARM__ */ + +/*---------------------------------------------------------------------------- + External function Declaration + *----------------------------------------------------------------------------*/ +extern void SramInit(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +WEAK_FUNCTION( NMI_Handler ) +WEAK_FUNCTION( HardFault_Handler ) +WEAK_FUNCTION( MemManage_Handler ) +WEAK_FUNCTION( BusFault_Handler ) +WEAK_FUNCTION( UsageFault_Handler ) +WEAK_FUNCTION( SVC_Handler ) +WEAK_FUNCTION( DebugMon_Handler ) +WEAK_FUNCTION( PendSV_Handler ) +WEAK_FUNCTION( SysTick_Handler ) +WEAK_FUNCTION( RTC1_Int_Handler ) +WEAK_FUNCTION( Ext_Int0_Handler ) +WEAK_FUNCTION( Ext_Int1_Handler ) +WEAK_FUNCTION( Ext_Int2_Handler ) +WEAK_FUNCTION( Ext_Int3_Handler ) +WEAK_FUNCTION( WDog_Tmr_Int_Handler ) +WEAK_FUNCTION( Vreg_over_Int_Handler ) +WEAK_FUNCTION( Battery_Voltage_Int_Handler) +WEAK_FUNCTION( RTC0_Int_Handler ) +WEAK_FUNCTION( GPIO_A_Int_Handler ) +WEAK_FUNCTION( GPIO_B_Int_Handler ) +WEAK_FUNCTION( GP_Tmr0_Int_Handler ) +WEAK_FUNCTION( GP_Tmr1_Int_Handler ) +WEAK_FUNCTION( Flash0_Int_Handler ) +WEAK_FUNCTION( UART0_Int_Handler ) +WEAK_FUNCTION( SPI0_Int_Handler ) +WEAK_FUNCTION( SPI2_Int_Handler ) +WEAK_FUNCTION( I2C0_Slave_Int_Handler ) +WEAK_FUNCTION( I2C0_Master_Int_Handler ) +WEAK_FUNCTION( DMA_Err_Int_Handler ) +WEAK_FUNCTION( DMA_SPIH_TX_Int_Handler ) +WEAK_FUNCTION( DMA_SPIH_RX_Int_Handler ) +WEAK_FUNCTION( DMA_SPORT0A_Int_Handler ) +WEAK_FUNCTION( DMA_SPORT0B_Int_Handler ) +WEAK_FUNCTION( DMA_SPI0_TX_Int_Handler ) +WEAK_FUNCTION( DMA_SPI0_RX_Int_Handler ) +WEAK_FUNCTION( DMA_SPI1_TX_Int_Handler ) +WEAK_FUNCTION( DMA_SPI1_RX_Int_Handler ) +WEAK_FUNCTION( DMA_UART0_TX_Int_Handler ) +WEAK_FUNCTION( DMA_UART0_RX_Int_Handler ) +WEAK_FUNCTION( DMA_I2C0_STX_Int_Handler ) +WEAK_FUNCTION( DMA_I2C0_SRX_Int_Handler ) +WEAK_FUNCTION( DMA_I2C0_MX_Int_Handler ) +WEAK_FUNCTION( DMA_AES0_IN_Int_Handler ) +WEAK_FUNCTION( DMA_AES0_OUT_Int_Handler ) +WEAK_FUNCTION( DMA_FLASH0_Int_Handler ) +WEAK_FUNCTION( SPORT0A_Int_Handler ) +WEAK_FUNCTION( SPORT0B_Int_Handler ) +WEAK_FUNCTION( Crypto_Int_Handler ) +WEAK_FUNCTION( DMA_ADC0_Int_Handler ) +WEAK_FUNCTION( GP_Tmr2_Int_Handler ) +WEAK_FUNCTION( Crystal_osc_Int_Handler ) +WEAK_FUNCTION( SPI1_Int_Handler ) +WEAK_FUNCTION( PLL_Int_Handler ) +WEAK_FUNCTION( RNG_Int_Handler ) +WEAK_FUNCTION( Beep_Int_Handler ) +WEAK_FUNCTION( ADC0_Int_Handler ) +WEAK_FUNCTION( DMA_SIP0_Int_Handler ) +WEAK_FUNCTION( DMA_SIP1_Int_Handler ) +WEAK_FUNCTION( DMA_SIP2_Int_Handler ) +WEAK_FUNCTION( DMA_SIP3_Int_Handler ) +WEAK_FUNCTION( DMA_SIP4_Int_Handler ) +WEAK_FUNCTION( DMA_SIP5_Int_Handler ) +WEAK_FUNCTION( DMA_SIP6_Int_Handler ) +WEAK_FUNCTION( DMA_SIP7_Int_Handler ) +WEAK_FUNCTION( UART1_Int_Handler ) +WEAK_FUNCTION( DMA_UART1_TX_Int_Handler ) +WEAK_FUNCTION( DMA_UART1_RX_Int_Handler ) +WEAK_FUNCTION( RGB_Tmr_Int_Handler ) +WEAK_FUNCTION( Root_Clk_Err_Handler ) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +const pFunc SECTION_PLACE(IVT_NAME[104],VECTOR_SECTION) = { + (pFunc) INITIAL_SP, /* Initial Stack Pointer */ + ADUCM4050_VECTORS +}; + +/*---------------------------------------------------------------------------- +* Initialize .bss and .data for GNU +*----------------------------------------------------------------------------*/ +#if defined( __GNUC__) && !defined (__CC_ARM) +void zero_bss(void) +{ + uint32_t *pSrc, *pDest; + uint32_t *pTable __attribute__((unused)); +#ifdef __STARTUP_COPY_MULTIPLE + /* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + pTable = &__copy_table_start__; + + for (; pTable < &__copy_table_end__; pTable = pTable + 3) { + pSrc = (uint32_t*)*(pTable + 0); + pDest = (uint32_t*)*(pTable + 1); + for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) { + *pDest++ = *pSrc++; + } + } +#else + /* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + pSrc = &__etext; + pDest = &__data_start__; + + for ( ; pDest < &__data_end__ ; ) { + *pDest++ = *pSrc++; + } +#endif /*__STARTUP_COPY_MULTIPLE */ + + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE + /* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + pTable = &__zero_table_start__; + + for (; pTable < &__zero_table_end__; pTable = pTable + 2) { + pDest = (uint32_t*)*(pTable + 0); + for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) { + *pDest++ = 0; + } + } +#elif defined (__STARTUP_CLEAR_BSS) + /* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + pDest = &__bss_start__; + + for ( ; pDest < &__bss_end__ ; ) { + *pDest++ = 0ul; + } +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ +} +#endif + +/*---------------------------------------------------------------------------- +* Function : Reset_Handler (-15) +* Description : Reset event handler +*----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + /* Initialize SRAM configuration. */ + SramInit(); + +#if defined(__GNUC__) && !defined (__CC_ARM) + zero_bss(); +#endif + + /* Setup system. */ + SystemInit(); + + /* Call remaining startup code and then main. */ + RESET_EXCPT_HNDLR(); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +#if defined(__CC_ARM) || defined (__GNUC__) +void Default_Handler(void) +{ + while(1); +} +#endif + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.h new file mode 100755 index 0000000000..98da5428c3 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.h @@ -0,0 +1,236 @@ +/*! +***************************************************************************** + * @file: startup_ADuCM4050.h + * @brief: CMSIS Cortex-M4 Core Peripheral Access Layer Header File for + * ADI ADuCxxx Device Series + * @version: $Revision: $ + * @date: $Date: $ + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2017 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/* +WEAK_FUNC(func) + If this is available for a compiler, apply whatever attributes are needed + to a function definition ("func") to flag that the function is a "weak" one. +VECTOR_SECTION + A particular setup may have a requirement that the vector table be placed + in a particular section. This specifies the name of that section +RESET_EXCPT_HNDLR + A particular setup may have a requirement for a different reset handler. + This specifies the name of that handler. +*/ + +#ifndef __STARTUP_H__ +#define __STARTUP_H__ + +#include +#define VECTOR_SECTION ".vectors" +#ifdef __CC_ARM +extern unsigned Image$$ADUCM_HEAP$$Base[]; +extern unsigned Image$$ADUCM_HEAP$$ZI$$Limit[]; +void Default_Handler(void); +#define SECTION_NAME(sectionname) __attribute__ ((section(sectionname))) +#define SECTION_PLACE(def,sectionname) def __attribute__ ((section(sectionname))) +#define IVT_NAME __Vectors +#define RESET_EXCPT_HNDLR __main +#define COMPILER_NAME "ARMCC" +#define WEAK_FUNCTION(x) void x (void) __attribute__ ((weak, alias("Default_Handler"))); +#elif defined(__ICCARM__) +/* +* IAR MISRA C 2004 error suppressions: +* +* Pm093 (rule 18.4): use of union - overlapping storage shall not be used. +* Required for interrupt vector table entries. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +*/ +#pragma diag_suppress=Pm093,Pm140 +#define SECTION_PLACE(def,sectionname) def @ sectionname +#define SECTION_NAME(sectionname) def @ sectionname +#define IVT_NAME __vector_table +#define WEAK_FUNC(func) __weak func +#define RESET_EXCPT_HNDLR __iar_program_start +#define COMPILER_NAME "ICCARM" +#define WEAK_FUNCTION(x) WEAK_FUNC ( void x (void)) { while(1){} } +#elif defined(__GNUC__) +extern unsigned __etext; +extern unsigned __data_start__; +extern unsigned __data_end__; +extern unsigned __copy_table_start__; +extern unsigned __copy_table_end__; +extern unsigned __zero_table_start__; +extern unsigned __zero_table_end__; +extern unsigned __bss_start__; +extern unsigned __bss_end__; +extern unsigned __StackTop; +void Default_Handler(void); +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +#ifndef __START +extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */ +#define RESET_EXCPT_HNDLR _start +#else +extern int __START(void) __attribute__((noreturn)); /* main entry point */ +#define RESET_EXCPT_HNDLR __START +#endif +#ifndef __STACK_SIZE +#define __STACK_SIZE 0x00000400 +#endif +#if !defined(__HEAP_SIZE) || (__HEAP_SIZE <= 0) +#define __HEAP_SIZE 0x00000C00 +#endif +#define SECTION_NAME(sectionname) __attribute__ ((section(sectionname))) +#define SECTION_PLACE(def,sectionname) def __attribute__ ((section(sectionname))) +#define IVT_NAME __Vectors +#define COMPILER_NAME "GNUC" +#define WEAK_FUNCTION(x) void x (void) __attribute__ ((weak, alias("Default_Handler"))); +#define __STARTUP_CLEAR_BSS_MULTIPLE +#endif // __GNUC__ +#define LASTCRCPAGE 0 +#define BLANKX4 0xFFFFFFFF +#define BLANKX20 BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4 +#define BLANKX100 BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20 +#define BLANKX600 BLANKX100,BLANKX100,BLANKX100,BLANKX100,BLANKX100,BLANKX100 +#define BLANKX60 BLANKX20,BLANKX20,BLANKX20 +void RESET_EXCPT_HNDLR(void); +void Reset_Handler(void); +/* IVT typedefs. */ +typedef void( *pFunc )( void ); + +#define ADUCM4050_VECTORS \ + /* Configure Initial Stack Pointer, using linker-generated symbols */\ + Reset_Handler, /* -15 */ \ + NMI_Handler, /* -14 */ \ + HardFault_Handler, /* -13 */ \ + MemManage_Handler, /* -12 */ \ + BusFault_Handler, /* -11 */ \ + UsageFault_Handler, /* -10 */ \ + 0, /* -9 */ \ + 0, /* -8 */ \ + 0, /* -7 */ \ + 0, /* -6 */ \ + SVC_Handler, /* -5 */ \ + DebugMon_Handler, /* -4 */ \ + 0, /* -3 */ \ + PendSV_Handler, /* -2 */ \ + SysTick_Handler, /* -1 */ \ + /* External interrupts */ \ + RTC1_Int_Handler, /* 0 */ \ + Ext_Int0_Handler, /* 1 */ \ + Ext_Int1_Handler, /* 2 */ \ + Ext_Int2_Handler, /* 3 */ \ + Ext_Int3_Handler, /* 4 */ \ + WDog_Tmr_Int_Handler, /* 5 */ \ + Vreg_over_Int_Handler, /* 6 */ \ + Battery_Voltage_Int_Handler, /* 7 */ \ + RTC0_Int_Handler, /* 8 */ \ + GPIO_A_Int_Handler, /* 9 */ \ + GPIO_B_Int_Handler, /* 10 */ \ + GP_Tmr0_Int_Handler, /* 11 */ \ + GP_Tmr1_Int_Handler, /* 12 */ \ + Flash0_Int_Handler, /* 13 */ \ + UART0_Int_Handler, /* 14 */ \ + SPI0_Int_Handler, /* 15 */ \ + SPI2_Int_Handler, /* 16 */ \ + I2C0_Slave_Int_Handler, /* 17 */ \ + I2C0_Master_Int_Handler, /* 18 */ \ + DMA_Err_Int_Handler, /* 19 */ \ + DMA_SPIH_TX_Int_Handler, /* 20 */ \ + DMA_SPIH_RX_Int_Handler, /* 21 */ \ + DMA_SPORT0A_Int_Handler, /* 22 */ \ + DMA_SPORT0B_Int_Handler, /* 23 */ \ + DMA_SPI0_TX_Int_Handler, /* 24 */ \ + DMA_SPI0_RX_Int_Handler, /* 25 */ \ + DMA_SPI1_TX_Int_Handler, /* 26 */ \ + DMA_SPI1_RX_Int_Handler, /* 27 */ \ + DMA_UART0_TX_Int_Handler, /* 28 */ \ + DMA_UART0_RX_Int_Handler, /* 29 */ \ + DMA_I2C0_STX_Int_Handler, /* 30 */ \ + DMA_I2C0_SRX_Int_Handler, /* 31 */ \ + DMA_I2C0_MX_Int_Handler, /* 32 */ \ + DMA_AES0_IN_Int_Handler, /* 33 */ \ + DMA_AES0_OUT_Int_Handler, /* 34 */ \ + DMA_FLASH0_Int_Handler, /* 35 */ \ + SPORT0A_Int_Handler, /* 36 */ \ + SPORT0B_Int_Handler, /* 37 */ \ + Crypto_Int_Handler, /* 38 */ \ + DMA_ADC0_Int_Handler, /* 39 */ \ + GP_Tmr2_Int_Handler, /* 40 */ \ + Crystal_osc_Int_Handler, /* 41 */ \ + SPI1_Int_Handler, /* 42 */ \ + PLL_Int_Handler, /* 43 */ \ + RNG_Int_Handler, /* 44 */ \ + Beep_Int_Handler, /* 45 */ \ + ADC0_Int_Handler, /* 46 */ \ + 0, /* 47 */ \ + 0, /* 48 */ \ + 0, /* 49 */ \ + 0, /* 50 */ \ + 0, /* 51 */ \ + 0, /* 52 */ \ + 0, /* 53 */ \ + 0, /* 54 */ \ + 0, /* 55 */ \ + DMA_SIP0_Int_Handler, /* 56 */ \ + DMA_SIP1_Int_Handler, /* 57 */ \ + DMA_SIP2_Int_Handler, /* 58 */ \ + DMA_SIP3_Int_Handler, /* 59 */ \ + DMA_SIP4_Int_Handler, /* 60 */ \ + DMA_SIP5_Int_Handler, /* 61 */ \ + DMA_SIP6_Int_Handler, /* 62 */ \ + DMA_SIP7_Int_Handler, /* 63 */ \ + 0, /* 64 */ \ + 0, /* 65 */ \ + UART1_Int_Handler, /* 66 */ \ + DMA_UART1_TX_Int_Handler, /* 67 */ \ + DMA_UART1_RX_Int_Handler, /* 68 */ \ + RGB_Tmr_Int_Handler, /* 69 */ \ + 0, /* 70 */ \ + Root_Clk_Err_Handler, /* 71 */ \ + 0,0,0,0,0,0,0,0, /* 72 - 79 */ \ + (pFunc)BLANKX4, (pFunc)BLANKX4, /* security_options */ \ + (pFunc)BLANKX4, (pFunc)BLANKX4, \ + (pFunc)0xA79C3203u, (pFunc)LASTCRCPAGE, \ + (pFunc)BLANKX4, (pFunc)BLANKX4 /* 80 - 87 */ + +#endif /* __STARTUP_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/system_ADuCM4050.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/system_ADuCM4050.c new file mode 100755 index 0000000000..df75af10d2 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/system_ADuCM4050.c @@ -0,0 +1,322 @@ +/**************************************************************************//** + * @file system_ADuCM4050.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for + * Device ADuCM4x50 + * @version V3.10 + * @date 23. November 2012 + * + ******************************************************************************/ +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + + Portions Copyright (c) 2016 - 2017 Analog Devices, Inc. + ---------------------------------------------------------------------------*/ + +#include +#include +#include + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef ADI_DEBUG +/* only needed in debug mode */ +uint32_t lfClock = 0u; /* "lf_clk" coming out of LF mux */ +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/* Note that these variables will be re-initialized to the value set here by the + LIBC startup code, so if other clock values are required, make sure set them + here. +*/ +uint32_t hfClock = __HFOSC; /* "root_clk" output of HF mux */ +uint32_t gpioClock = 0u; /* external GPIO clock */ +uint32_t SystemCoreClock = __HFOSC; /*!< System Clock Frequency (Core Clock) */ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ + +/*! + * Update the clock. + * + * @param none + * @return none + * + * @brief Updates the variable SystemCoreClock and must be called whenever + * the core clock is changed during program execution. + */ +void SystemCoreClockUpdate(void) +{ + uint32_t val, nDivisor, nMulfactor, div2, mul2; + +#ifdef ADI_DEBUG + /* "lfclock" is only used during debug checks... */ + /* LF clock is always 32k, whether osc or xtal */ + lfClock = __LFCLK; /* for beep, wdt and lcd */ + if (lfClock == 0u) { + while (1) {} + } +#endif + /* Update Core Clock sources */ + /* update the HF clock */ + switch (pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_CLKMUX ) { + + case HFMUX_INTERNAL_OSC_VAL: + hfClock = __HFOSC; + break; + + case HFMUX_EXTERNAL_XTAL_VAL: + hfClock = __HFXTAL; + break; + + case HFMUX_SYSTEM_SPLL_VAL: + /* Calculate System PLL output frequency */ + if ((pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_PLL_IPSEL) != 0u) { + /* PLL input from HFXTAL */ + val = __HFXTAL; + } else { + /* PLL input from HFOSC */ + val = __HFOSC; + } + + /* PLL NSEL multiplier */ + nMulfactor = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLNSEL) >> BITP_CLKG_CLK_CTL3_SPLLNSEL; + /* PLL MSEL divider */ + nDivisor = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLMSEL) >> BITP_CLKG_CLK_CTL3_SPLLMSEL; + + /* PLL NSEL multiplier */ + mul2 = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLMUL2) >> BITP_CLKG_CLK_CTL3_SPLLMUL2; + /* PLL MSEL divider */ + div2 = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLDIV2) >> BITP_CLKG_CLK_CTL3_SPLLDIV2; + + val = ((val << mul2) * nMulfactor / nDivisor) >> div2; + + hfClock = val; + break; + + case HFMUX_GPIO_VAL: + hfClock = gpioClock; + break; + + default: + return; + } /* end switch */ + + SystemCoreClock = hfClock; +} + +/*! + * Configure the SRAM banks + * + * @return none + * + * @brief Setup the SRAM banks. + * Initialize the SRAM configuration and retention. + */ +void SramInit(void) +{ + /* On reset, there is no SRAM retention. Any retention has to be explicitly + * set here. */ + adi_system_EnableRetention(ADI_SRAM_BANK_1 | + ADI_SRAM_BANK_3 | + ADI_SRAM_BANK_4 | + ADI_SRAM_BANK_5 | + ADI_SRAM_BANK_6 | + ADI_SRAM_BANK_7, true); + /* To disable the instruction SRAM and entire 64K of SRAM is used as DSRAM */ + adi_system_EnableISRAM(false); + /* To disable the instruction cache */ + adi_system_EnableCache(false); +} + +/*! + * Initialize the system + * + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the relocate vector table. + */ +void SystemInit (void) +{ + uint32_t IntStatus; + + IntStatus = __get_PRIMASK(); + __disable_irq(); + + /* Set boot ROM IVT. */ + SCB->VTOR = (uint32_t)NVIC_FLASH_VECTOR_ADDRESS; + + /* Set all three (USGFAULTENA, BUSFAULTENA, and MEMFAULTENA) fault enable bits + * in the System Control Block, System Handler Control and State Register + * otherwise these faults are handled as hard faults. + */ + SCB->SHCSR = SCB_SHCSR_USGFAULTENA_Msk | + SCB_SHCSR_BUSFAULTENA_Msk | + SCB_SHCSR_MEMFAULTENA_Msk ; + +#if (__FPU_PRESENT == 1u) && (__FPU_USED == 1u) + /* the FPU is disabled by default so enable FPU (NEON and VFP) + * set the System Control Block, Coprocessor Access Control Register bits: + * CP10 = grant CP10 coprocessor privileges and user mode access (full access) + * CP11 = grant CP11 coprocessor privileged and user mode access (full access) + * (CP10 and CP11 MUST be the same or "BEHAVIOR IS UNPREDICTABLE") + */ + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 for Full Access */ +#endif + + /* Flush instruction and data pipelines to insure assertion of new settings. */ + __ISB(); + __DSB(); + + adi_pwr_Init(); + adi_pwr_SetClockDivider(ADI_CLOCK_HCLK,1); + adi_pwr_SetClockDivider(ADI_CLOCK_PCLK,1); + + /* Set up the LF clock MUX. Currently LFXTAL is unstable so use the + internal LF Oscillator instead. LFXTAL is still required to be enabled + as it is required by RTC0. This LFXTAL issue is going to be fixed + in the next revision of the silicon. */ + adi_pwr_EnableClockSource(ADI_CLOCK_SOURCE_LFXTAL,true); + adi_pwr_SetLFClockMux(ADI_CLOCK_MUX_LFCLK_LFOSC); + adi_pwr_EnableClockSource(ADI_CLOCK_SOURCE_LFOSC,true); + + __set_PRIMASK(IntStatus); +} + +/*! + * @brief Enables or disables the cache. + * @param bEnable Specify whether to enable/disable cache. + * - true : Enable cache. + * - false: Disable cache. + * @return none + */ +void adi_system_EnableCache(bool bEnable) +{ + pADI_FLCC0_CACHE->KEY = CACHE_CONTROLLER_KEY; + if( bEnable == true ) { + pADI_FLCC0_CACHE->SETUP |= BITM_FLCC_CACHE_SETUP_ICEN; + } else { + pADI_FLCC0_CACHE->SETUP &= ~BITM_FLCC_CACHE_SETUP_ICEN; + } +} + +/*! + * @brief This enables or disables instruction SRAM + * + * @param bEnable Enable/disable the instruction SRAM. + * - true : Enable instruction SRAM. + * - false : Disable instruction SRAM. + * @return none + * @note The appropriate linker file needs to support the configuration. + */ +void adi_system_EnableISRAM(bool bEnable) +{ + + if( bEnable == true ) { + pADI_PMG0_TST->SRAM_CTL |= BITM_PMG_TST_SRAM_CTL_INSTREN; + } else { + pADI_PMG0_TST->SRAM_CTL &= ~BITM_PMG_TST_SRAM_CTL_INSTREN; + } +} + +/*! + * @brief This enables/disable SRAM retention during the hibernation. + * @param eBank: Specify which SRAM banks. Multiple banks can be set + / using a logical OR of the banks. + * @param bEnable Enable/disable the retention for specified SRAM bank. + * - true : Enable retention during hibernation. + * - false: Disable retention during hibernation. + * @return ADI_SYS_SUCCESS Configured successfully. + * @return ADI_SYS_FAILURE Invalid bank, or banks, specified. Any incorrect + * or invalid bank options will result in failure and + * no changes will have been applied. + * @note The appropriate linker file needs to support the configuration. + * BANK 0 is always retained. + * BANKS 1 can be retained individually. + * BANK 2 is never retained. + * BANKS 3 and 4 can only be mutually retained. + * BANKS 5 can be retained individually. + * BANKS 6 and 7 can only be mutually retained. + */ +ADI_SYS_RESULT adi_system_EnableRetention(ADI_SRAM_BANK eBank, bool bEnable) +{ + uint32_t retainBits = 0u; + +#ifdef ADI_DEBUG + if((0u != (eBank & ADI_SRAM_BANK_0)) || + (0u != (eBank & ADI_SRAM_BANK_2))) { + /* Banks 0 and 2 are not selectable */ + return ADI_SYS_FAILURE; + } + + /* Are banks 3 or 4 selected? */ + if(0u != (eBank & (ADI_SRAM_BANK_3 | ADI_SRAM_BANK_4))) { + /* If so, the only valid option is for both to be retained. */ + if((eBank & (ADI_SRAM_BANK_3 | ADI_SRAM_BANK_4)) != (ADI_SRAM_BANK_3 | ADI_SRAM_BANK_4)) { + return ADI_SYS_FAILURE; + } + } + + /* Are banks 6 or 7 selected? */ + if(0u != (eBank & (ADI_SRAM_BANK_6 | ADI_SRAM_BANK_7))) { + /* If so, the only valid option is for both to be retained */ + if((eBank & (ADI_SRAM_BANK_6 | ADI_SRAM_BANK_7)) != (ADI_SRAM_BANK_6 | ADI_SRAM_BANK_7)) { + return ADI_SYS_FAILURE; + } + } +#endif + if((eBank & ADI_SRAM_BANK_1) != 0u) { + retainBits |= BITM_PMG_SRAMRET_RET1; + } + if((eBank & (ADI_SRAM_BANK_3 | ADI_SRAM_BANK_4)) != 0u) { + retainBits |= BITM_PMG_SRAMRET_RET2; + } + if((eBank & ADI_SRAM_BANK_5) != 0u) { + retainBits |= BITM_PMG_SRAMRET_RET3; + } + if((eBank & (ADI_SRAM_BANK_6 | ADI_SRAM_BANK_7)) != 0u) { + retainBits |= BITM_PMG_SRAMRET_RET4; + } + + /* Unlock the SRAMRET register using the PWRKEY. + * If there is any chance that this sequence can be interrupted then it + * should be protected by disabling interrupts. A write to any other + * register on the APB bus before writing to PMG_SRAMRET will return the + * protection to the lock state. */ + pADI_PMG0->PWRKEY = PWRKEY_VALUE_KEY; + if(bEnable) { + pADI_PMG0->SRAMRET |= retainBits; + } else { + pADI_PMG0->SRAMRET &= ~(retainBits); + } + + return ADI_SYS_SUCCESS; +} diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_ARM_STD/ADuCM4050.sct b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_ARM_STD/ADuCM4050.sct new file mode 100755 index 0000000000..0f7791ae5e --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_ARM_STD/ADuCM4050.sct @@ -0,0 +1,52 @@ +;****************************************************************************** +; File: ADuCM4050.sct +; Scatter loading file for Analog Devices ADuCM4050 processor +; +; Copyright (c) 2011 - 2014 ARM LIMITED +; Copyright (c) 2016 - 2017 Analog Devices, Inc. +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +LR_IROM1 0x00000000 0x0007F000 { + FLASH0 0x00000000 0x00000800 { + *(.vectors, +First) + *(.checksum) + } + + ER_IROM1 AlignExpr(ImageLimit(FLASH0), 16) 0x0007E800 { + ; load address = execution address + *(InRoot$$Sections) + *(+RO) + } + + RW_IRAM1 0x20040000 EMPTY 0 { } + + ADUCM_IRAM2 0x20000200 0x7E00 { *(+RW) } + + ADUCM_IRAM3 0x20048000 0x10000 { *(+ZI) } + + ADUCM_HEAP AlignExpr(ImageLimit(RW_IRAM1), 16) EMPTY + (ImageBase(ADUCM_IRAM3) - 0x2000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) { } ; heap +} diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_GCC_ARM/ADuCM4050.ld b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_GCC_ARM/ADuCM4050.ld new file mode 100755 index 0000000000..2ead54a157 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_GCC_ARM/ADuCM4050.ld @@ -0,0 +1,214 @@ +/* + * Portions Copyright (c) 2016 Analog Devices, Inc. + * + * Based on Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld file in + * ARM.CMSIS.4.5.0.pack. + */ + +/* Linker script to configure memory regions. */ +MEMORY +{ + /* The first 0x800 bytes of flash */ + FLASH0 (rx) : ORIGIN = 0x00000000, LENGTH = 0x800 + /* The remaining bytes of flash minus 4KB Protected Key Storage */ + FLASH (rx) : ORIGIN = 0x00000800, LENGTH = 512k - 4k - 0x800 + /* SRAM bank 0 */ + DSRAM_A (rwx) : ORIGIN = 0x20000200, LENGTH = 32k - 0x200 + /* SRAM bank 3+4+5+6+7 */ + DSRAM_B (rwx) : ORIGIN = 0x20048000, LENGTH = 64k + /* stack must not be in bank 1,2,7 where ISRAM or CACHE + are set at power on */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Custom stack and heap sizes */ +__stack_size__ = 0x2000; +__heap_size__ = 0x6000; + +/* select custom or default sizes for stack and heap */ +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0C00; + + +/* Linker script to place sections and symbol values. + * It references the following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines the following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + KEEP(*(.checksum)) + } > FLASH0 + + .security_options : + { + . = ALIGN(4); + KEEP(*(.security_options)) + . = ALIGN(4); + } > FLASH0 + + .text : + { + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > DSRAM_A + + .bss : + { + . = ALIGN(16); + __bss2_start__ = .; + *(COMMON) + . = ALIGN(16); + __bss2_end__ = .; + __bss_start__ = .; + *(.bss*) + . = ALIGN(16); + __bss_end__ = .; + } > DSRAM_B + + __StackTop = ORIGIN(DSRAM_B); + __StackLimit = __StackTop - STACK_SIZE; + __HeapLimit = __StackLimit; + __HeapBase = __HeapLimit - HEAP_SIZE; + __end__ = __HeapBase; + PROVIDE(end = __end__); + PROVIDE(__stack = __StackTop); +} diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_IAR/ADuCM4050.icf b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_IAR/ADuCM4050.icf new file mode 100755 index 0000000000..318ad52023 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_IAR/ADuCM4050.icf @@ -0,0 +1,48 @@ +/****************************************************************************** +* File: ADuCM4050.icf +* ILINK Configuration File for Analog Devices ADuCM4050 processor +* +* Copyright (c) 2011 - 2014 ARM LIMITED +* Copyright (c) 2016 - 2017 Analog Devices, Inc. +* +* All rights reserved. +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* - Neither the name of ARM nor the names of its contributors may be used +* to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ +define memory mem with size = 4G; +define region ROM_PAGE0_INTVEC = mem:[from 0x00000000 size 0x000001A0]; +define region ROM_PAGE0_CHECKSUM = mem:[from 0x000001A0 size 0x00000660]; +define region ROM_REGION = mem:[from 0x00000800 size 506K]; +define region RAM_bank1_region = mem:[from 0x20040000 size 0x00008000]; +define region RAM_bank2_region = mem:[from 0x20000200 size 0x00007E00] + | mem:[from 0x20048000 size 0x00010000]; +define block CSTACK with alignment = 16, size = 0x2000 { }; +define block HEAP with alignment = 16, size = 0x6000 { }; +do not initialize { section .noinit }; +initialize by copy { rw }; +place at start of ROM_PAGE0_INTVEC { ro section .vectors }; +place in ROM_PAGE0_CHECKSUM { ro section .checksum }; +place in ROM_REGION { ro }; +place at end of RAM_bank1_region { block CSTACK }; +place at start of RAM_bank1_region { block HEAP }; +place in RAM_bank2_region { rw }; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.c new file mode 100755 index 0000000000..8257894757 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.c @@ -0,0 +1,138 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +/* + The ADuCM4050 is made in two package variants. + + 64 lead LFCSP & 72 ball WLCSP + + There are some differences for Port 2 between the two variants + WLCSP also has Port 3. + + The #define ADUCM4050_LFCSP is used to determine which variant the code + is built for. + + For LFCSP leave the #define in, to build for ADUCM4050_WLCSP remove. +*/ +#define ADUCM4050_LFCSP + +#include "PeripheralPins.h" + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {P0_10, UART_0, 1}, + {P1_15, UART_1, 2}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {P0_11, UART_0, 1}, + {P2_00, UART_1, 2}, + {NC, NC, 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {P0_00, SPI_0, 1}, + {P1_06, SPI_1, 1}, + {P1_02, SPI_2, 1}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {P0_01, SPI_0, 1}, + {P1_07, SPI_1, 1}, + {P1_03, SPI_2, 1}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {P0_02, SPI_0, 1}, + {P1_08, SPI_1, 1}, + {P1_04, SPI_2, 1}, + {NC, NC, 0} +}; + +#if defined(ADUCM4050_LFCSP) +const PinMap PinMap_SPI_SSEL[] = { + {P0_03, SPI_0, 1}, + {P1_09, SPI_1, 1}, + {P2_10, SPI_2, 1}, + {NC, NC, 0} +}; +#else +const PinMap PinMap_SPI_SSEL[] = { + {P0_03, SPI_0, 1}, + {P1_09, SPI_1, 1}, + {P2_15, SPI_2, 1}, + {NC, NC, 0} +}; +#endif + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {P0_05, I2C_0, 1}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {P0_04, I2C_0, 1}, + {NC, NC, 0} +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {P2_03, ADC0_VIN0, 1}, + {P2_04, ADC0_VIN1, 1}, + {P2_05, ADC0_VIN2, 1}, + {P2_06, ADC0_VIN3, 1}, + {P2_07, ADC0_VIN4, 1}, + {P2_08, ADC0_VIN5, 1}, + {P2_09, ADC0_VIN6, 1}, +#ifdef ADUCM4050_LFCSP + {P2_10, ADC0_VIN7, 1}, +#endif + {NC, NC, 0} +}; + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, OSC32KCLK, 0}, +}; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.h new file mode 100755 index 0000000000..40ef7f85b1 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.h @@ -0,0 +1,67 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************RTC***************/ +extern const PinMap PinMap_RTC[]; + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************I2C***************/ +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c new file mode 100755 index 0000000000..d007006439 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c @@ -0,0 +1,216 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "mbed_assert.h" +#include "analogin_api.h" + +#if DEVICE_ANALOGIN + +#include "adi_adc_def.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +/** Analogin hal structure. analogin_s is declared in the target's hal + */ +typedef struct analogin_s analogin_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/* ADC Device number */ +#define ADC_DEV_NUM (0u) + +/* Memory Required for adc driver */ +static uint32_t DeviceMemory[(ADI_ADC_MEMORY_SIZE+3)/4]; +/* Active channel */ +static uint32_t adi_pin2channel(PinName pin); + +/** + * \defgroup hal_analogin Analogin hal functions + * @{ + */ + +/** Initialize the analogin peripheral + * + * Configures the pin used by analogin. + * @param obj The analogin object to initialize + * @param pin The analogin pin name + */ +void analogin_init(analogin_t *obj, PinName pin) +{ + ADI_ADC_HANDLE hDevice; + bool bCalibrationDone = false; + bool bReady = false; + + ADCName peripheral; + uint32_t function, channel; + + peripheral = (ADCName)pinmap_peripheral(pin, &PinMap_ADC[0]); // gives peripheral + MBED_ASSERT(peripheral != (ADCName)NC); + + /* verify read function */ + function = pinmap_function(pin, &PinMap_ADC[0]); + MBED_ASSERT(function == 1); + + /* Configure PORT2_MUX registers */ + pin_function(pin, function); + + /* Configure active channel */ + channel = adi_pin2channel(pin); + MBED_ASSERT(channel != 0xFFFFFFFF); + obj->UserBuffer.nChannels = channel; + + /* Open the ADC device */ + adi_adc_Open(ADC_DEV_NUM, DeviceMemory, sizeof(DeviceMemory),&hDevice); + obj->hDevice = hDevice; + + /* Power up ADC */ + adi_adc_PowerUp (hDevice, true); + + /* Set ADC reference */ + adi_adc_SetVrefSource (hDevice, ADI_ADC_VREF_SRC_INT_2_50_V); + + /* Enable ADC sub system */ + adi_adc_EnableADCSubSystem (hDevice, true); + + /* Wait untilthe ADC is ready for sampling */ + while(bReady == false) { + adi_adc_IsReady (hDevice, &bReady); + } + + /* Start calibration */ + adi_adc_StartCalibration (hDevice); + + /* Wait until calibration is done */ + while (!bCalibrationDone) { + adi_adc_IsCalibrationDone (hDevice, &bCalibrationDone); + } + + /* Set the delay time */ + adi_adc_SetDelayTime ( hDevice, obj->DelayCycles); + + /* Set the acquisition time. (Application need to change it based on the impedence) */ + adi_adc_SetAcquisitionTime ( hDevice, obj->SampleCycles); + +} + +/** Read the input voltage, represented as a float in the range [0.0, 1.0] + * + * @param obj The analogin object + * @return A floating value representing the current input voltage + */ +float analogin_read(analogin_t *obj) +{ + float fl32 = (float)analogin_read_u16(obj)/(float)4095.0; + + return(fl32); +} + +/** Read the value from analogin pin, represented as an unsigned 16bit value + * + * @param obj The analogin object + * @return An unsigned 16bit value representing the current input voltage + */ +uint16_t analogin_read_u16(analogin_t *obj) +{ + ADI_ADC_HANDLE hDevice = obj->hDevice; + ADI_ADC_BUFFER *pAdcBuffer; + + /* Submit the buffer to the driver */ + adi_adc_SubmitBuffer (hDevice, &obj->UserBuffer); + + /* Enable the ADC */ + adi_adc_Enable (hDevice, true); + + adi_adc_GetBuffer (hDevice, &pAdcBuffer); + MBED_ASSERT(pAdcBuffer == &obj->UserBuffer); + + return( (uint16_t) ( ((uint16_t *)pAdcBuffer->pDataBuffer)[(pAdcBuffer->nNumConversionPasses) - 1]) ); +} + +/* Retrieve te active channel correspondoing to the input pin */ +static uint32_t adi_pin2channel(PinName pin) +{ + + uint32_t activech; + + switch(pin) { + case ADC_VIN0: + activech = ADI_ADC_CHANNEL_0; + break; + case ADC_VIN1: + activech = ADI_ADC_CHANNEL_1; + break; + case ADC_VIN2: + activech = ADI_ADC_CHANNEL_2; + break; + case ADC_VIN3: + activech = ADI_ADC_CHANNEL_3; + break; + case ADC_VIN4: + activech = ADI_ADC_CHANNEL_4; + break; + case ADC_VIN5: + activech = ADI_ADC_CHANNEL_5; + break; + case ADC_VIN6: + activech = ADI_ADC_CHANNEL_6; + break; + case ADC_VIN7: + activech = ADI_ADC_CHANNEL_7; + break; + default: + activech = (uint32_t) 0xFFFFFFFF; + break; + } + + return((uint32_t) activech); +} + + + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif // #if DEVICE_ANALOGIN diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis.h new file mode 100755 index 0000000000..2d2850cc2e --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis.h @@ -0,0 +1,46 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H +#define __C +#include "adi_processor.h" +#include "cmsis_nvic.h" +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis_nvic.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis_nvic.h new file mode 100755 index 0000000000..3a866a5d72 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis_nvic.h @@ -0,0 +1,78 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include "cmsis.h" + +#define NVIC_USER_IRQ_OFFSET 16 +#define NVIC_USER_IRQ_NUMBER 72 +#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER) + +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 +#define NVIC_FLASH_VECTOR_ADDRESS 0x0 + +#ifdef __cplusplus +extern "C" { +#endif + +/** Set the ISR for IRQn + * + * Sets an Interrupt Service Routine vector for IRQn; if the feature is available, the vector table is relocated to SRAM + * the first time this function is called + * @param[in] IRQn The Interrupt Request number for which a vector will be registered + * @param[in] vector The ISR vector to register for IRQn + */ +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); + +/** Get the ISR registered for IRQn + * + * Reads the Interrupt Service Routine currently registered for IRQn + * @param[in] IRQn The Interrupt Request number the vector of which will be read + * @return Returns the ISR registered for IRQn + */ +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/device.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/device.h new file mode 100755 index 0000000000..0d46738ec1 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/device.h @@ -0,0 +1,48 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_ID_LENGTH 24 + +#include "objects.h" + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/flash_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/flash_api.c new file mode 100755 index 0000000000..25afcc193f --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/flash_api.c @@ -0,0 +1,89 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifdef DEVICE_FLASH +#include "flash_api.h" +#include "flash_data.h" +#include "mbed_critical.h" + +// This file is automagically generated + +// This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM + +static unsigned FLASH_ALGO[] = { + 0x20004A4B,0x60111E41,0x6211494A,0x60912107,0x074B6811,0xF011D5FC,0xD0000F30,0x21002001, + 0x47706211,0x2400B510,0xD1082A01,0xF872F000,0x6D09493F,0xD00207C8,0xFFE2F7FF,0x46204604, + 0x493BBD10,0x62082000,0xB5104770,0xF862F000,0x4010E8BD,0x4601E7D4,0x20004A35,0x60131E43, + 0x49346191,0x21066211,0x68116091,0xD5FC074B,0x0F30F011,0x2001D000,0x62112100,0xB57C4770, + 0x4B2C4C2B,0x62232500,0xF04FE03E,0x602333FF,0xD3042908,0x61236813,0x61636853,0xF04FE025, + 0xE9CD33FF,0x29083300,0xE8DFD21A,0x1619F001,0x0A0D1013,0x79910407,0x1006F88D,0xF88D7951, + 0x79111005,0x1004F88D,0xF88D78D1,0x78911003,0x1002F88D,0xF88D7851,0x78111001,0x1000F88D, + 0x1300E9DD,0x61636121,0x60E02108,0x60A32304,0xF0136823,0xD0010F30,0xE0072501,0x075B6823, + 0x3008D5FC,0x32083908,0xD1BE2900,0x62202000,0xBD7C4628,0x21004806,0x4A066041,0x4A066202, + 0x22046342,0x22016382,0x62016542,0x00004770,0x40018000,0x676C7565,0xB8950950,0 +}; + +static const flash_algo_t flash_algo_config = { + .init = 0x00000025, + .uninit = 0x00000043, + .erase_sector = 0x00000057, + .program_page = 0x0000007F, + .static_base = 0x0000013C, + .algo_blob = FLASH_ALGO +}; + +static const sector_info_t sectors_info[] = { + {0x0, 0x800}, +}; + +static const flash_target_config_t flash_target_config = { + .page_size = 0x800, + .flash_start = 0x0, + .flash_size = 0x0007F000, + .sectors = sectors_info, + .sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t) +}; + +void flash_set_target_config(flash_t *obj) +{ + obj->flash_algo = &flash_algo_config; + obj->target_config = &flash_target_config; +} +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c new file mode 100755 index 0000000000..c338d84275 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c @@ -0,0 +1,144 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "mbed_assert.h" +#include "gpio_api.h" +#include "pinmap.h" +#include "adi_gpio.h" + + +#define MUX_FUNC_0 0x0 +#define NUM_GPIO_PORTS 4 + +extern uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE]; +extern uint8_t gpio_initialized; + +static uint16_t gpio_oen[NUM_GPIO_PORTS] = {0}; +static uint16_t gpio_output_val[NUM_GPIO_PORTS] = {0}; + + +/****************************************************************************** + Function definitions + *****************************************************************************/ +uint32_t gpio_set(PinName pin) +{ + MBED_ASSERT(pin != (PinName)NC); + uint32_t pin_num = pin & 0xFF; + + pin_function(pin, MUX_FUNC_0); + + return (1 << pin_num); +} + +void gpio_init(gpio_t *obj, PinName pin) +{ + obj->pin = pin; + + if (pin == (PinName)NC) + return; + + // Initialize the GPIO driver. This function + // initializes the GPIO driver only once globally. + if (!gpio_initialized) + adi_gpio_Init(gpioMemory, ADI_GPIO_MEMORY_SIZE); + + pin_function(pin, MUX_FUNC_0); +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + uint32_t pin = obj->pin; + + pin_mode((PinName)pin, mode); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t port = obj->pin >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pin & 0xFF; + + if (direction == PIN_OUTPUT) { + adi_gpio_OutputEnable((ADI_GPIO_PORT)port, 1 << pin_num, true); + // save the input/output configuration + gpio_oen[port] |= (1 << pin_num); + } else { + adi_gpio_InputEnable((ADI_GPIO_PORT)port, 1 << pin_num, true); + // save the input/output configuration + gpio_oen[port] &= (~(1 << pin_num)); + } +} + +void gpio_write(gpio_t *obj, int value) +{ + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t port = obj->pin >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pin & 0xFF; + + if (value & 1) { + adi_gpio_SetHigh((ADI_GPIO_PORT)port, (1 << pin_num)); + + // save the output port value + gpio_output_val[port] |= ((value & 1) << pin_num); + } else { + adi_gpio_SetLow((ADI_GPIO_PORT)port, (1 << pin_num)); + + // save the output port value + gpio_output_val[port] &= (~(1 << pin_num)); + } +} + + +int gpio_read(gpio_t *obj) +{ + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t port = obj->pin >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pin & 0xFF; + uint16_t Data; + + // check whether the pin is configured as input or output + if ((gpio_oen[port] >> pin_num) & 1) + Data = gpio_output_val[port] & (1 << pin_num); + else + // otherwise call GetData + adi_gpio_GetData((ADI_GPIO_PORT)port, (1 << pin_num), &Data); + + return ((((uint32_t)Data) >> pin_num) & 1); +} diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_dev_mem.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_dev_mem.c new file mode 100755 index 0000000000..5e0d99ad8b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_dev_mem.c @@ -0,0 +1,47 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include + +// ADI GPIO device driver state memory. Only one state memory is required globally. +uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE]; + +// Flag to indicate whether the GPIO driver has been initialized +uint8_t gpio_initialized = 0; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c new file mode 100755 index 0000000000..ae5b8234c3 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c @@ -0,0 +1,317 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "gpio_irq_api.h" +#include "adi_gpio.h" +#include "adi_gpio_def.h" + +#ifdef DEVICE_INTERRUPTIN + +#define MAX_GPIO_LINES 16 +#define MAX_GPIO_PORTS ADI_GPIO_NUM_PORTS + +typedef struct { + unsigned int id; + gpio_irq_event event; + uint8_t int_enable; +} gpio_chan_info_t; + +extern uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE]; +extern uint8_t gpio_initialized; +static gpio_chan_info_t channel_ids[MAX_GPIO_PORTS][MAX_GPIO_LINES]; +static gpio_irq_handler irq_handler = NULL; + + +/** Local interrupt callback routine. + */ +static void gpio_irq_callback(void *pCBParam, uint32_t Event, void *pArg) +{ + uint16_t pin = *(ADI_GPIO_DATA*)pArg; + int index = 0; + + // determine the index of the pin that caused the interrupt + while (pin) { + if (pin & 0x01) { + // call the user ISR. The argument Event is the port number of the GPIO line. + if (irq_handler != NULL) + irq_handler((uint32_t)channel_ids[Event][index].id, channel_ids[Event][index].event); + } + index++; + pin >>= 1; + } +} + + +/** Function to get the IENA and IENB register values. + * Added here based on code from ADuCM302x + */ +static ADI_GPIO_RESULT adi_gpio_GetGroupInterruptPins(const ADI_GPIO_PORT Port, const IRQn_Type eIrq, + const ADI_GPIO_DATA Pins, uint16_t* const pValue) +{ + ADI_GPIO_TypeDef *pReg[ADI_GPIO_NUM_PORTS] = {pADI_GPIO0, pADI_GPIO1, pADI_GPIO2, pADI_GPIO3}; + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + uint16_t Value = 0u; + + pPort = pReg[Port]; + + switch (eIrq) { + case SYS_GPIO_INTA_IRQn: + Value = pPort->IENA; + break; + case SYS_GPIO_INTB_IRQn: + Value = pPort->IENB; + break; + default: + break; /* This shall never reach */ + } + + *pValue = (Value & Pins); + return (ADI_GPIO_SUCCESS); +} + + +/** Function to get the interrupt polarity register content. + * Added here based on code from ADuCM302x + */ +static ADI_GPIO_RESULT adi_gpio_GetGroupInterruptPolarity(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, + uint16_t* const pValue) +{ + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + ADI_GPIO_TypeDef *pReg[ADI_GPIO_NUM_PORTS] = {pADI_GPIO0, pADI_GPIO1, pADI_GPIO2, pADI_GPIO3}; + + pPort = pReg[Port]; + + *pValue = (pPort->POL & Pins); + + return (ADI_GPIO_SUCCESS); +} + + +/** Function to clear the relevant interrupt enable bits in both the IENA and IENB registers + * for the given GPIO pin. + */ +static void disable_pin_interrupt(ADI_GPIO_PORT port, uint32_t pin_number) +{ + uint16_t int_reg_val; + + // Read the current content of the IENA register + adi_gpio_GetGroupInterruptPins(port, SYS_GPIO_INTA_IRQn, 1 << pin_number, &int_reg_val); + + // clear the bit for the pin + int_reg_val &= ~(1 << pin_number); + + // write the interrupt register + adi_gpio_SetGroupInterruptPins(port, SYS_GPIO_INTA_IRQn, int_reg_val); + + // Do the same to IENB + adi_gpio_GetGroupInterruptPins(port, SYS_GPIO_INTB_IRQn, 1 << pin_number, &int_reg_val); + + // clear the bit for the pin + int_reg_val &= ~(1 << pin_number); + + // write the interrupt register + adi_gpio_SetGroupInterruptPins(port, SYS_GPIO_INTB_IRQn, int_reg_val); +} + + +/** Function to set the relevant interrupt enable bits in either the IENA and IENB registers + * for the given GPIO pin. + */ +static void enable_pin_interrupt(ADI_GPIO_PORT port, uint32_t pin_number, IRQn_Type eIrq) +{ + uint16_t int_reg_val; + + // Read the current interrupt enable register content + adi_gpio_GetGroupInterruptPins(port, eIrq, 1 << pin_number, &int_reg_val); + + // set the bit for the pin + int_reg_val |= (1 << pin_number); + + // write the interrupt register + adi_gpio_SetGroupInterruptPins(port, eIrq, int_reg_val); +} + + +/** Initialize the GPIO IRQ pin + * + * @param obj The GPIO object to initialize + * @param pin The GPIO pin name + * @param handler The handler to be attached to GPIO IRQ + * @param id The object ID (id != 0, 0 is reserved) + * @return -1 if pin is NC, 0 otherwise + */ +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + uint32_t port = pin >> GPIO_PORT_SHIFT; + uint32_t pin_num = pin & 0xFF; + + // check for valid pin and ID + if ((pin == NC) || (id == 0)) + return -1; + + // make sure gpio driver has been initialized + if (!gpio_initialized) { + adi_gpio_Init(gpioMemory,ADI_GPIO_MEMORY_SIZE); + gpio_initialized = 1; + } + + // save the handler + if (handler) + irq_handler = handler; + + // disable the interrupt for the given pin + disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num); + + // set the port pin as input + adi_gpio_InputEnable(port, 1 << pin_num, true); + + // save the ID for future reference + channel_ids[port][pin_num].id = id; + channel_ids[port][pin_num].event = IRQ_NONE; + channel_ids[port][pin_num].int_enable = 0; + obj->id = id; + obj->pinname = pin; + + return 0; +} + +/** Release the GPIO IRQ PIN + * + * @param obj The gpio object + */ +void gpio_irq_free(gpio_irq_t *obj) +{ + uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pinname & 0xFF; + + // disable interrupt for the given pin + gpio_irq_disable(obj); + + // clear the status table + channel_ids[port][pin_num].id = 0; + channel_ids[port][pin_num].event = IRQ_NONE; + channel_ids[port][pin_num].int_enable = 0; +} + +/** Enable/disable pin IRQ event + * + * @param obj The GPIO object + * @param event The GPIO IRQ event + * @param enable The enable flag + */ +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + uint16_t int_polarity_reg; + uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pinname & 0xFF; + + if (event == IRQ_NONE) + return; + + // read the current polarity register + adi_gpio_GetGroupInterruptPolarity((ADI_GPIO_PORT)port, 1 << pin_num, &int_polarity_reg); + + if (event == IRQ_RISE) + int_polarity_reg |= (1 << pin_num); + else + int_polarity_reg &= ~(1 << pin_num); + + // set the polarity register + adi_gpio_SetGroupInterruptPolarity((ADI_GPIO_PORT)port, int_polarity_reg); + + channel_ids[port][pin_num].event = event; + + // enable interrupt for this pin if enable flag is set + if (enable) + gpio_irq_enable(obj); + else + gpio_irq_disable(obj); +} + +/** Enable GPIO IRQ + * + * This is target dependent, as it might enable the entire port or just a pin + * @param obj The GPIO object + */ +void gpio_irq_enable(gpio_irq_t *obj) +{ + uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pinname & 0xFF; + + if (channel_ids[port][pin_num].event == IRQ_NONE) + return; + + // Group all RISE interrupts in INTA and FALL interrupts in INTB + if (channel_ids[port][pin_num].event == IRQ_RISE) { + // set the callback routine + adi_gpio_RegisterCallback(SYS_GPIO_INTA_IRQn, gpio_irq_callback, obj); + enable_pin_interrupt((ADI_GPIO_PORT)port, pin_num, SYS_GPIO_INTA_IRQn); + } else if (channel_ids[port][pin_num].event == IRQ_FALL) { + // set the callback routine + adi_gpio_RegisterCallback(SYS_GPIO_INTB_IRQn, gpio_irq_callback, obj); + enable_pin_interrupt((ADI_GPIO_PORT)port, pin_num, SYS_GPIO_INTB_IRQn); + } + + channel_ids[port][pin_num].int_enable = 1; +} + +/** Disable GPIO IRQ + * + * This is target dependent, as it might disable the entire port or just a pin + * @param obj The GPIO object + */ +void gpio_irq_disable(gpio_irq_t *obj) +{ + uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pinname & 0xFF; + + if (channel_ids[port][pin_num].event == IRQ_NONE) + return; + + // Group all RISE interrupts in INTA and FALL interrupts in INTB + if (channel_ids[port][pin_num].event == IRQ_RISE) + disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num); + else if (channel_ids[port][pin_num].event == IRQ_FALL) + disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num); + + channel_ids[port][pin_num].int_enable = 0; +} + +#endif // #ifdef DEVICE_INTERRUPTIN diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_object.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_object.h new file mode 100755 index 0000000000..8d59616b7f --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_object.h @@ -0,0 +1,61 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; +} gpio_t; + +static inline int gpio_is_connected(const gpio_t *obj) +{ + return obj->pin != (PinName)NC; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c new file mode 100755 index 0000000000..7a883ff245 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c @@ -0,0 +1,238 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "mbed_assert.h" +#include "i2c_api.h" + +#if DEVICE_I2C + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" +#include "drivers/i2c/adi_i2c.h" + + + +#if defined(BUILD_I2C_MI_DYNAMIC) +#if defined(ADI_DEBUG) +#warning "BUILD_I2C_MI_DYNAMIC is defined. Memory allocation for I2C will be dynamic" +int adi_i2c_memtype = 0; +#endif +#else +static uint8_t i2c_Mem[ADI_I2C_MEMORY_SIZE]; +static ADI_I2C_HANDLE i2c_Handle; +#if defined(ADI_DEBUG) +#warning "BUILD_I2C_MI_DYNAMIC is NOT defined. Memory allocation for I2C will be static" +int adi_i2c_memtype = 1; +#endif +#endif + + + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA); + uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL); + ADI_I2C_HANDLE *pI2C_Handle; + uint8_t *I2C_Mem; + ADI_I2C_RESULT I2C_Return = ADI_I2C_SUCCESS; + uint32_t I2C_DevNum = I2C_0; /* ADuCM4050 only has 1 I2C port */ + + +#if defined(BUILD_I2C_MI_DYNAMIC) + I2C_DevNum = I2C_0; + pI2C_Handle = &obj->I2C_Handle; + obj->pI2C_Handle = pI2C_Handle; + I2C_Mem = obj->I2C_Mem; +#else + I2C_DevNum = I2C_0; + pI2C_Handle = &i2c_Handle; + obj->pI2C_Handle = pI2C_Handle; + I2C_Mem = &i2c_Mem[0]; +#endif + + + obj->instance = pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)obj->instance != NC); + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + SystemCoreClockUpdate(); + I2C_Return = adi_i2c_Open(I2C_DevNum, I2C_Mem, ADI_I2C_MEMORY_SIZE, pI2C_Handle); + if (I2C_Return) { + obj->error = I2C_EVENT_ERROR; + return; + } + I2C_Return = adi_i2c_Reset(*pI2C_Handle); + if (I2C_Return) { + obj->error = I2C_EVENT_ERROR; + return; + } +} + + +int i2c_start(i2c_t *obj) +{ + return 0; +} + + +int i2c_stop(i2c_t *obj) +{ + return 0; +} + + +void i2c_frequency(i2c_t *obj, int hz) +{ + ADI_I2C_HANDLE I2C_Handle; + ADI_I2C_RESULT I2C_Return = ADI_I2C_SUCCESS; + + + I2C_Handle = *obj->pI2C_Handle; + I2C_Return = adi_i2c_SetBitRate(I2C_Handle, (uint32_t) hz); + if (I2C_Return) { + obj->error = I2C_EVENT_ERROR; + return; + } +} + + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + ADI_I2C_RESULT I2C_Return; + ADI_I2C_TRANSACTION I2C_inst; + uint8_t I2C_PrologueData = 0x00; + uint32_t I2C_Errors; /* HW Error result */ + ADI_I2C_HANDLE I2C_Handle; + + + I2C_Handle = *obj->pI2C_Handle; + I2C_Return = adi_i2c_SetSlaveAddress(I2C_Handle, (address & 0x0000FFFF)); + I2C_inst.pPrologue = &I2C_PrologueData; + I2C_inst.nPrologueSize = 0; + I2C_inst.pData = (uint8_t*) data; + I2C_inst.nDataSize = length; + I2C_inst.bReadNotWrite = true; + I2C_inst.bRepeatStart = stop; + I2C_Return = adi_i2c_ReadWrite(I2C_Handle, &I2C_inst, &I2C_Errors); + if (I2C_Return) { + obj->error = I2C_EVENT_ERROR; + return -1; + } else { + return length; + } +} + + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + ADI_I2C_RESULT I2C_Return = ADI_I2C_SUCCESS; + ADI_I2C_TRANSACTION I2C_inst; + uint8_t I2C_PrologueData = 0x00; + uint32_t I2C_Errors; /* HW Error result */ + ADI_I2C_HANDLE I2C_Handle; + + + I2C_Handle = *obj->pI2C_Handle; + I2C_Return = adi_i2c_SetSlaveAddress(I2C_Handle, (address & 0x0000FFFF)); + I2C_inst.pPrologue = &I2C_PrologueData; + I2C_inst.nPrologueSize = 0; + I2C_inst.pData = (uint8_t*) data; + I2C_inst.nDataSize = length; + I2C_inst.bReadNotWrite = false; + I2C_inst.bRepeatStart = stop; + I2C_Return = adi_i2c_ReadWrite(I2C_Handle, &I2C_inst, &I2C_Errors); + if (I2C_Return) { + obj->error = I2C_EVENT_ERROR; + return -1; + } else { + return length; + } +} + + +void i2c_reset(i2c_t *obj) +{ + return; +} + + +int i2c_byte_read(i2c_t *obj, int last) +{ + return 0; +} + + +int i2c_byte_write(i2c_t *obj, int data) +{ + return 0; +} + + + +#if DEVICE_I2CSLAVE +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ + +} + +int i2c_slave_receive(i2c_t *obj) +{ + +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ + return length; +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ + return length; +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ + +} +#endif // #if DEVICE_I2CSLAVE + +#endif // #if DEVICE_I2C diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/lp_ticker_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/lp_ticker_api.c new file mode 100755 index 0000000000..5d46471c4a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/lp_ticker_api.c @@ -0,0 +1,269 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include +#include "lp_ticker_api.h" +#include +#include +#include "adi_rtc_def.h" + + +#ifdef DEVICE_LOWPOWERTIMER + +// define base LF clock frequncy in Hz +#define LFCLK_FREQUENCY_HZ 32768 +// RTC prescaler for the LF clock +#define RTC_PRESCALER 0 + +/* time for each tick of the LF clock in us */ +#define TIME_US_PER_TICK ((float)1000000/(float)(LFCLK_FREQUENCY_HZ>>RTC_PRESCALER)) + +// The number of RTC clock ticks it takes to set & enable the alarm +#define TICKS_TO_ENABLE_ALARM 10 + +// Mask to limit the value of the RTC value to 27 bits so the converted time in us fits +// in 32-bits +#define MAX_TICK_MASK ((1 << 27) - 1) + +static unsigned char rtc1_memory[ADI_RTC_MEMORY_SIZE]; +static ADI_RTC_HANDLE hRTC1_Device; + + +/** + * \defgroup hal_LpTicker Low Power Ticker Functions + * @{ + */ +/** + * Local stream-lined alarm setting function. + * + */ +static int set_rtc_alarm_interrupt(ADI_RTC_HANDLE const hDevice, uint32_t nAlarm) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint16_t cr0; + ADI_INT_STATUS_ALLOC(); + + // Section to enable interrupts + // The interrupt used is ADI_RTC_ALARM_INT + // Set the Alarm interrupt enable and Alarm enable bits in cr0 + cr0 = BITM_RTC_CR0_ALMEN | (1u << BITP_RTC_CR0_ALMINTEN); + + // Set the alarm value + /* Wait till previously posted write to Alram Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1)) + + ADI_ENTER_CRITICAL_REGION(); + /* Program the alarm count registers. */ + pDevice->pRTCRegs->ALM0 = (uint16_t)nAlarm; + pDevice->pRTCRegs->ALM1 = (uint16_t)(nAlarm >> 16); + pDevice->pRTCRegs->ALM2 = 0u; + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1)) + + // Enable alarm + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDALM1|BITM_RTC_SR1_WPNDALM0) + + ADI_ENTER_CRITICAL_REGION(); + /* set RTC alarm and interrupt enable */ + pDevice->pRTCRegs->CR0 |= cr0; + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; +} + + + +/** + * Local RTC 1 ISR callback function. + * + */ +static void rtc1_Callback (void *pCBParam, uint32_t nEvent, void *EventArg) +{ + /* process RTC interrupts (cleared by driver) */ + if (ADI_RTC_ALARM_INT & nEvent) { + lp_ticker_irq_handler(); + } +} + + +/** Get low power ticker's data + * + * @return The low power ticker data + */ +/* +const ticker_data_t* get_lp_ticker_data() +{ +}*/ + + +/* HAL lp ticker */ + +/** Initialize the low power ticker + * + */ +void lp_ticker_init() +{ + // open the rtc device + adi_rtc_Open(1, rtc1_memory, ADI_RTC_MEMORY_SIZE, &hRTC1_Device); + + // set the prescaler value + adi_rtc_SetPreScale(hRTC1_Device, RTC_PRESCALER); + + // register call back for events + adi_rtc_RegisterCallback(hRTC1_Device, rtc1_Callback, hRTC1_Device); + + // reset the RTC counter + adi_rtc_SetCount(hRTC1_Device, 0); + + // set the trim value + adi_rtc_SetTrim(hRTC1_Device, ADI_RTC_TRIM_INTERVAL_14, ADI_RTC_TRIM_1, ADI_RTC_TRIM_SUB); + + adi_rtc_EnableTrim(hRTC1_Device, true); + + // enable the RTC + adi_rtc_Enable(hRTC1_Device, true); +} + +/** Read the current counter + * + * @return The current timer's counter value in microseconds + */ +uint32_t lp_ticker_read() +{ + uint32_t count; + float t; + + // get current count + adi_rtc_GetCount(hRTC1_Device, &count); + + // Throw away top 5 bits to avoid overflow and convert ticks to us + count &= MAX_TICK_MASK; + t = (float)count * TIME_US_PER_TICK; + + return (uint32_t)t; +} + +/** Set interrupt for specified timestamp + * + * @param timestamp The time in microseconds to be set + */ +void lp_ticker_set_interrupt(timestamp_t timestamp) +{ + uint32_t rtcCount, trunc_rtcCount, set_tick, tick_delta, alarm_tick; + + // compute the tick value based on the given alarm time + set_tick = (uint32_t)((float)(timestamp) / TIME_US_PER_TICK); + + // get current count + adi_rtc_GetCount(hRTC1_Device, &rtcCount); + + // compute the number of ticks required for the alarm + trunc_rtcCount = rtcCount & MAX_TICK_MASK; + + // if set_tick is less than the current RTC count, the counter has + // missed the desired time, so set tick_delta to 0 + if (set_tick >= trunc_rtcCount) { + tick_delta = set_tick - trunc_rtcCount; + } else { + tick_delta = 0; + } + + // compute the absolute RTC alarm count required + alarm_tick = rtcCount + tick_delta; + + // check if the desired alarm duration is less than TICKS_TO_ENABLE_ALARM, + // if so just wait it out rather than setting the alarm + if (tick_delta <= TICKS_TO_ENABLE_ALARM) { + // otherwise if the alarm time is less than the current RTC count + the time + // it takes to enable the alarm, just wait until the desired number of counts + // has expired rather than using the interrupt, then call the user ISR directly. + do { + adi_rtc_GetCount(hRTC1_Device, &rtcCount); + } while (rtcCount < alarm_tick); + + rtc1_Callback(NULL, ADI_RTC_ALARM_INT, NULL); + return; + } + + // set the alarm otherwise + set_rtc_alarm_interrupt(hRTC1_Device, alarm_tick); +} + +/** Disable low power ticker interrupt + * + */ +void lp_ticker_disable_interrupt() +{ + adi_rtc_EnableInterrupts(hRTC1_Device, ADI_RTC_ALARM_INT, false); +} + +/** Clear the low power ticker interrupt + * + */ +void lp_ticker_clear_interrupt() +{ + ADI_RTC_DEVICE *pDevice = hRTC1_Device; + + NVIC_ClearPendingIRQ(pDevice->eIRQn); + + return; +} + + +/** Set pending interrupt that should be fired right away. + * + * The ticker should be initialized prior calling this function. + */ +void lp_ticker_fire_interrupt(void) +{ + ADI_RTC_DEVICE *pDevice = hRTC1_Device; + + NVIC_SetPendingIRQ(pDevice->eIRQn); +} + + +#endif +/**@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h new file mode 100755 index 0000000000..7b316f5c32 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h @@ -0,0 +1,112 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PeripheralNames.h" +#include "PinNames.h" +//#include "target_config.h" +#include "gpio_object.h" + +#include "adi_i2c.h" +#include "adi_spi.h" +#include "adi_adc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + unsigned int id; + PinName pinname; +}; + +struct sleep_s { + int temp; +}; + +struct serial_s { + int index; +}; + +struct trng_s { + uint8_t dummy; +}; + +#define BUILD_I2C_MI_DYNAMIC +struct i2c_s { + uint32_t instance; + uint32_t error; + ADI_I2C_HANDLE *pI2C_Handle; +#if defined(BUILD_I2C_MI_DYNAMIC) + ADI_I2C_HANDLE I2C_Handle; + uint8_t I2C_Mem[ADI_I2C_MEMORY_SIZE]; +#endif +}; + +#define BUILD_SPI_MI_DYNAMIC +struct spi_s { + uint32_t instance; + uint32_t error; + ADI_SPI_HANDLE *pSPI_Handle; +#if defined(BUILD_SPI_MI_DYNAMIC) + ADI_SPI_HANDLE SPI_Handle; + uint8_t SPI_Mem[ADI_SPI_MEMORY_SIZE]; +#endif +}; + +#include "gpio_object.h" + +struct analogin_s { + ADI_ADC_HANDLE hDevice; + ADI_ADC_BUFFER UserBuffer; + uint8_t DelayCycles; + uint8_t SampleCycles; +}; + + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/pinmap.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/pinmap.c new file mode 100755 index 0000000000..bb061e0ba4 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/pinmap.c @@ -0,0 +1,103 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "mbed_assert.h" +#include "pinmap.h" +#include "mbed_error.h" + +#include "PinNames.h" +#include "adi_gpio.h" + +void pin_function(PinName pin, int function) +{ + // pin is composed of port and pin + // function is the function number (the mux selection number shifted by the pin value + // and written to pin mux register, each pin mux takes 2 bits hence multiplying by 2) + + MBED_ASSERT(pin != (PinName)NC); + + uint8_t port = pin >> GPIO_PORT_SHIFT; + uint32_t cfg_reg, mask; + volatile uint32_t *pGPIO_CFG; + + switch (port) { + case 0: + pGPIO_CFG = (volatile uint32_t *)REG_GPIO0_CFG; + break; + case 1: + pGPIO_CFG = (volatile uint32_t *)REG_GPIO1_CFG; + break; + case 2: + pGPIO_CFG = (volatile uint32_t *)REG_GPIO2_CFG; + break; + + default: + return; + } + + cfg_reg = *pGPIO_CFG; + // clear the corresponding 2 bit field first before writing the function + // bits + mask = ~(3 << (pin * 2)); + cfg_reg = cfg_reg & mask | (function << (pin*2)); + *pGPIO_CFG = cfg_reg; +} + +void pin_mode(PinName pin, PinMode mode) +{ + MBED_ASSERT(pin != (PinName)NC); + + uint8_t port = pin >> GPIO_PORT_SHIFT; + uint32_t pin_reg_value = 2 ^ (0xFF & pin); + + switch (mode) { + case PullNone: + adi_gpio_PullUpEnable((ADI_GPIO_PORT)port, (ADI_GPIO_DATA) pin_reg_value,false); + break; + + case PullDown: + case PullUp: + adi_gpio_PullUpEnable((ADI_GPIO_PORT)port, (ADI_GPIO_DATA) pin_reg_value,true); + break; + + default: + break; + } +} diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/rtc_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/rtc_api.c new file mode 100755 index 0000000000..8b650705fc --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/rtc_api.c @@ -0,0 +1,94 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "rtc_api.h" + +#if DEVICE_RTC + +#include "adi_rtc.h" +#include "adi_pwr.h" + +#define RTC_DEVICE_NUM 0 +static uint8_t aRtcDevMem0[ADI_RTC_MEMORY_SIZE]; +static ADI_RTC_HANDLE hDevice0 = NULL; + + +void rtc_init(void) +{ + /* initialize driver */ + adi_rtc_Open(RTC_DEVICE_NUM,aRtcDevMem0,ADI_RTC_MEMORY_SIZE,&hDevice0); + + adi_rtc_Enable(hDevice0, true); +} + +void rtc_free(void) +{ + adi_rtc_Close(hDevice0); +} + +/* + * Little check routine to see if the RTC has been enabled + * 0 = Disabled, 1 = Enabled + */ +int rtc_isenabled(void) +{ + uint32_t ControlReg; + + adi_rtc_GetControl (hDevice0, ADI_RTC_CONTROL_REGISTER_0,&ControlReg); + + return((int) (ControlReg & BITM_RTC_CR0_CNTEN)); +} + +time_t rtc_read(void) +{ + time_t currentCount; + + adi_rtc_GetCount(hDevice0, (uint32_t *)(¤tCount)); + + return(currentCount); +} + +void rtc_write(time_t t) +{ + adi_rtc_SetCount (hDevice0, t); +} + +#endif // #if DEVICE_RTC + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c new file mode 100755 index 0000000000..8764be8803 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c @@ -0,0 +1,352 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "serial_api.h" + +#if DEVICE_SERIAL + +// math.h required for floating point operations for baud rate calculation +#include +#include "mbed_assert.h" + +#include + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "drivers/uart/adi_uart.h" +#define ADI_UART_MEMORY_SIZE (ADI_UART_BIDIR_MEMORY_SIZE) +#define ADI_UART_NUM_DEVICES 2 + +static ADI_UART_HANDLE hDevice[ADI_UART_NUM_DEVICES]; +static uint32_t UartDeviceMem[ADI_UART_NUM_DEVICES][(ADI_UART_MEMORY_SIZE + 3)/4]; +static uint32_t serial_irq_ids[ADI_UART_NUM_DEVICES] = {0}; +static uart_irq_handler irq_handler = NULL; +int stdio_uart_inited = 0; +serial_t stdio_uart; +int rxbuffer[2]; +int txbuffer[2]; + +static void uart_callback(void *pCBParam, uint32_t Event, void *pArg) +{ + MBED_ASSERT(irq_handler); + serial_t *obj = pCBParam; + if (Event == ADI_UART_EVENT_TX_BUFFER_PROCESSED) + irq_handler(serial_irq_ids[obj->index], TxIrq); + else if (Event == ADI_UART_EVENT_RX_BUFFER_PROCESSED) + irq_handler(serial_irq_ids[obj->index], RxIrq); +} + + +void serial_free(serial_t *obj) +{ + adi_uart_Close(hDevice[obj->index]); +} + +void serial_baud(serial_t *obj, int baudrate) +{ + uint32_t uartdivc,uartdivm,uartdivn,uartosr; + + // figures based on PCLK of 26MHz + switch (baudrate) { + case 9600: + uartdivc= 28; + uartdivm= 3; + uartdivn= 46; + uartosr= 3; + break; + case 19200: + uartdivc= 14; + uartdivm= 3; + uartdivn= 46; + uartosr= 3; + break; + case 38400: + uartdivc= 07; + uartdivm= 3; + uartdivn= 46; + uartosr= 3; + break; + case 57600: + uartdivc= 14; + uartdivm= 1; + uartdivn= 15; + uartosr= 3; + break; + case 115200: + uartdivc= 03; + uartdivm= 2; + uartdivn= 719; + uartosr= 3; + break; + case 230400: + uartdivc= 03; + uartdivm= 1; + uartdivn= 359; + uartosr= 3; + break; + default: // default of 9600kbps + uartdivc= 28; + uartdivm= 3; + uartdivn= 46; + uartosr= 3; + break; + } + + adi_uart_ConfigBaudRate(hDevice[obj->index],uartdivc,uartdivm,uartdivn,uartosr); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + int convertedparity = ADI_UART_NO_PARITY; + int convertedstopbits = ADI_UART_ONE_STOPBIT; + + if (stop_bits) + convertedstopbits = ADI_UART_ONE_AND_HALF_TWO_STOPBITS; + + if (parity == ParityOdd) + convertedparity = ADI_UART_ODD_PARITY; + else if (parity == ParityEven) + convertedparity = ADI_UART_EVEN_PARITY; + else if (parity == ParityForced1) + convertedparity = ADI_UART_ODD_PARITY_STICKY; + else if (parity == ParityForced0) + convertedparity = ADI_UART_EVEN_PARITY_STICKY; + + adi_uart_SetConfiguration(hDevice[obj->index], convertedparity, convertedstopbits, (data_bits - 5)); +} +#ifndef ADI_UART_TRANSFER_MODE + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); + uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); + obj->index = pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)obj->index != NC); + adi_uart_Open(obj->index,ADI_UART_DIR_BIDIRECTION,UartDeviceMem[obj->index],ADI_UART_MEMORY_SIZE,&hDevice[obj->index]); + serial_baud(obj, 9600); + serial_format(obj, 8, ParityNone, 1); + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + if (tx != NC) { + pin_mode(tx, PullUp); + } + if (rx != NC) { + pin_mode(rx, PullUp); + } + if (obj->index == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +int serial_readable(serial_t *obj) +{ + bool bAvailable = false; + adi_uart_IsRxBufferAvailable(hDevice[obj->index], &bAvailable); + return bAvailable; +} + +int serial_getc(serial_t *obj) +{ + int c; + void *pBuff; + uint32_t pHwError; + adi_uart_SubmitRxBuffer(hDevice[obj->index], &rxbuffer[obj->index], 1, 1); + adi_uart_GetRxBuffer(hDevice[obj->index], &pBuff, &pHwError); + c = (unsigned) rxbuffer[obj->index]; + return (c); +} + +int serial_writable(serial_t *obj) +{ + bool bAvailable = false; + adi_uart_IsTxBufferAvailable(hDevice[obj->index], &bAvailable); + return bAvailable; +} + +void serial_putc(serial_t *obj, int c) +{ + void *pBuff; + uint32_t pHwError; + txbuffer[obj->index]= (char) c; + adi_uart_SubmitTxBuffer(hDevice[obj->index],&txbuffer[obj->index], 1, 1); + adi_uart_GetTxBuffer(hDevice[obj->index], &pBuff, &pHwError); + return; +} + +#else + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); + uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); + + obj->index = pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)obj->index != NC); + + adi_uart_Open(obj->index, ADI_UART_DIR_BIDIRECTION, UartDeviceMem[obj->index], ADI_UART_MEMORY_SIZE, &hDevice[obj->index]); + + serial_baud(obj, 9600); + serial_format(obj, 8, ParityNone, 1); + + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + if (tx != NC) { + pin_mode(tx, PullUp); + } + + if (rx != NC) { + pin_mode(rx, PullUp); + } + + if (obj->index == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } + + // set maximum FIFO depth + adi_uart_SetRxFifoTriggerLevel(hDevice[obj->index], ADI_UART_RX_FIFO_TRIG_LEVEL_14BYTE); + + // enable FIFO + adi_uart_EnableFifo(hDevice[obj->index], true); +} + +int serial_getc(serial_t *obj) +{ + int c; + uint32_t hwErr; + + adi_uart_Read(hDevice[obj->index], (void *) &c, 1, false, &hwErr); + return (c); +} + +void serial_putc(serial_t *obj, int c) +{ + uint32_t hwErr; + + adi_uart_Write(hDevice[obj->index], &c, 1, false, &hwErr); + return; +} + +int serial_readable(serial_t *obj) +{ + return 0; +} + +int serial_writable(serial_t *obj) +{ + return 0; +} +#endif +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + MBED_ASSERT(obj); + + adi_uart_RegisterCallback(hDevice[obj->index], &uart_callback, obj); + if (enable) { + } else { + } +} + +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) +{ + adi_uart_ForceTxBreak(hDevice[obj->index], true); +} + +void serial_break_clear(serial_t *obj) +{ + adi_uart_ForceTxBreak(hDevice[obj->index], false); +} + +#if DEVICE_SERIAL_ASYNCH +uint8_t serial_tx_active(serial_t *obj) +{ + return 0; +} + +uint8_t serial_rx_active(serial_t *obj) +{ + return 0; +} + +int serial_irq_handler_asynch(serial_t *obj) +{ + return 0; +} + + + +int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) +{ + return 0; +} + +void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) +{ + +} + +void serial_tx_abort_asynch(serial_t *obj) +{ + +} + +void serial_rx_abort_asynch(serial_t *obj) +{ + +} +#endif +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + + MBED_ASSERT(obj); + + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.c new file mode 100755 index 0000000000..c323b51ca5 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.c @@ -0,0 +1,255 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "sleep_api.h" + +#ifdef DEVICE_SLEEP + +#include "adi_pwr.h" +#include "adi_pwr_def.h" +#include "adi_rtos_map.h" +#include "adi_ADuCM4050_device.h" +#include "sleep.h" + +/** + * Function to put processor into sleep (FLEXI mode only). + */ +static void go_into_WFI(const ADI_PWR_POWER_MODE PowerMode) +{ + uint32_t savedPriority; + uint16_t savedWDT; + uint16_t ActiveWDT; + uint32_t scrSetBits = 0u; + uint32_t scrClrBits = 0u; + uint32_t IntStatus = 0u; + + /* pre-calculate the sleep-on-exit set/clear bits */ + scrSetBits |= SCB_SCR_SLEEPONEXIT_Msk; + + /* wfi without deepsleep or sleep-on-exit */ + scrClrBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT); + + ADI_ENTER_CRITICAL_REGION(); + + { /* these lines must be in a success-checking loop if they are not inside critical section */ + /* Uninterruptable unlock sequence */ + pADI_PMG0->PWRKEY = ADI_PMG_KEY; + + /* Clear the previous mode and set new mode */ + pADI_PMG0->PWRMOD = (uint32_t) ( ( pADI_PMG0->PWRMOD & (uint32_t) (~BITM_PMG_PWRMOD_MODE) ) | PowerMode ); + } + + /* Update the SCR (sleepdeep and sleep-on-exit bits) */ + SCB->SCR = ((SCB->SCR | scrSetBits) & ~scrClrBits); + + /* save/restore current Base Priority Level */ + savedPriority = __get_BASEPRI(); + + /* assert caller's priority threshold (left-justified), currently set to 0, i.e. disable interrupt masking */ + __set_BASEPRI(0); + + /* save/restore WDT control register (which is not retained during hibernation) */ + savedWDT = pADI_WDT0->CTL; + + /* optimization: compute local WDT enable flag once (outside the loop) */ + ActiveWDT = ((savedWDT & BITM_WDT_CTL_EN) >> BITP_WDT_CTL_EN); + + /* SAR-51938: insure WDT is fully synchronized or looping on interrupts + in hibernate mode may lock out the sync bits. + + In hibernate mode (during which the WDT registers are not retained), + the WDT registers will have been reset to default values after each + interrupt exit and we require a WDT clock domain sync. + + We also need to insure a clock domain sync before (re)entering the WFI + in case an interrupt did a watchdog kick. + + Optimization: only incur WDT sync overhead (~100us) if the WDT is enabled. + */ + if (ActiveWDT > 0u) { + while ((pADI_WDT0->STAT & (uint32_t)(BITM_WDT_STAT_COUNTING | BITM_WDT_STAT_LOADING | BITM_WDT_STAT_CLRIRQ)) != 0u) { + ; + } + } + + __DSB(); /* bus sync to insure register writes from interrupt handlers are always complete before WFI */ + + /* NOTE: aggressive compiler optimizations can muck up critical timing here, so reduce if hangs are present */ + + /* The WFI loop MUST reside in a critical section because we need to insure that the interrupt + that is planned to take us out of WFI (via a call to adi_pwr_ExitLowPowerMode()) is not + dispatched until we get into the WFI. If that interrupt sneaks in prior to our getting to the + WFI, then we may end up waiting (potentially forever) for an interrupt that has already occurred. + */ + __WFI(); + + /* Recycle the critical section so that other (non-wakeup) interrupts are dispatched. + This allows *pnInterruptOccurred to be set from any interrupt context. + */ + ADI_EXIT_CRITICAL_REGION(); + /* nop */ + ADI_ENTER_CRITICAL_REGION(); + + /* ...still within critical section... */ + + /* Restore previous base priority */ + __set_BASEPRI(savedPriority); + + /* conditionally, restore WDT control register. + avoid unnecessary WDT writes which will invoke a sync problem + described above as SAR-51938: going into hibernation with pending, + unsynchronized WDT writes may lock out the sync bits. + + Note: it takes over 1000us to sync WDT writes between the 26MHz and + 32kHz clock domains, so this write may actually impact the NEXT + low-power entry. + */ + if (ActiveWDT > 0u) { + pADI_WDT0->CTL = savedWDT; + } + + /* clear sleep-on-exit bit to avoid sleeping on exception return to thread level */ + SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk; + + __DSB(); /* bus sync before re-enabling interrupts */ + + ADI_EXIT_CRITICAL_REGION(); +} + + +/** + * Function to enable/disable clock gating for the available clocks. + * PCLK overrides all the other clocks. + */ +void set_clock_gating(peripheral_clk_t eClk, int enable) +{ + uint32_t flag; + + switch (eClk) { + case PCLK: + flag = 1 << BITP_CLKG_CLK_CTL5_PERCLKOFF; + break; + case GPT0_CLOCK: + flag = 1 << BITP_CLKG_CLK_CTL5_GPTCLK0OFF; + break; + case GPT1_CLOCK: + flag = 1 << BITP_CLKG_CLK_CTL5_GPTCLK1OFF; + break; + case GPT2_CLOCK: + flag = 1 << BITP_CLKG_CLK_CTL5_GPTCLK2OFF; + break; + case I2C_CLOCK: + flag = 1 << BITP_CLKG_CLK_CTL5_UCLKI2COFF; + break; + case GPIO_CLOCK: + flag = 1 << BITP_CLKG_CLK_CTL5_GPIOCLKOFF; + break; + case TIMER_RGB_CLOCK: + flag = 1 << BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF; + break; + default: + return; + } + + // if enable, set the bit otherwise clear the bit + if (enable) + pADI_CLKG0_CLK->CTL5 |= flag; + else + pADI_CLKG0_CLK->CTL5 &= (~flag); +} + + + +/** Send the microcontroller to sleep + * + * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the + * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates + * dynamic power used by the processor, memory systems and buses. The processor, peripheral and + * memory state are maintained, and the peripherals continue to work and can generate interrupts. + * + * The processor can be woken up by any internal peripheral interrupt or external pin interrupt. + * + * @note + * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored. + * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be + * able to access the LocalFileSystem + * + * This mode puts the processor into FLEXI mode however the peripheral clocks are not gated + * hence they are still active. + */ +void hal_sleep(void) +{ + // set to go into the FLEXI mode where the processor is asleep and all peripherals are + // still active + go_into_WFI(ADI_PWR_MODE_FLEXI); +} + + +/** Send the microcontroller to deep sleep + * + * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode + * has the same sleep features as sleep plus it powers down peripherals and clocks. All state + * is still maintained. + * + * The processor can only be woken up by an external interrupt on a pin or a watchdog timer. + * + * @note + * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored. + * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be + * able to access the LocalFileSystem + * + * This mode puts the processor into FLEXI mode and all the peripheral clocks are clock gated + * hence they are inactive until interrupts are generated in which case the processor is awaken + * from sleep. + */ +void hal_deepsleep(void) +{ + // set clock gating to all the peripheral clocks + set_clock_gating(PCLK, 1); + + // set to go into the FLEXI mode with peripheral clocks gated. + go_into_WFI(ADI_PWR_MODE_FLEXI); + + // when exiting, clear all peripheral clock gating bits. This is done to enable clocks that aren't + // automatically re-enabled out of sleep such as the GPIO clock. + pADI_CLKG0_CLK->CTL5 = 0; +} + +#endif // #ifdef DEVICE_SLEEP diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.h new file mode 100755 index 0000000000..5ba806dbee --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.h @@ -0,0 +1,69 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef __SLEEP__H__ +#define __SLEEP__H__ + + +/* Enumeration to specify peripheral clock types: + General purpose timer clocks 0-2, + I2C clock, + GPIO clock, + RGB timer clock. + Peripheral clock (PCLK) controls all the peripheral clocks, including + all the clocks mentioned previously +*/ +typedef enum { + GPT0_CLOCK = 0, + GPT1_CLOCK, + GPT2_CLOCK, + I2C_CLOCK, + GPIO_CLOCK, + TIMER_RGB_CLOCK, + PCLK +} peripheral_clk_t; + + +/* Function to enable/disable clock gating for the available clocks. + PCLK overrides all the other clocks. +*/ +void set_clock_gating(peripheral_clk_t eClk, int enable); + +#endif // #ifndef __SLEEP_H__ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c new file mode 100755 index 0000000000..a17dea1ab6 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c @@ -0,0 +1,346 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include +#include "mbed_assert.h" + +#include + +#include "spi_api.h" + +#if DEVICE_SPI + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" +#include "drivers/spi/adi_spi.h" + + + +#if defined(BUILD_SPI_MI_DYNAMIC) +#if defined(ADI_DEBUG) +#warning "BUILD_SPI_MI_DYNAMIC is defined. Memory allocation for SPI will be dynamic" +int adi_spi_memtype = 0; +#endif +#else +ADI_SPI_HANDLE spi_Handle0; +uint8_t spi_Mem0[ADI_SPI_MEMORY_SIZE]; +ADI_SPI_HANDLE spi_Handle1; +uint8_t spi_Mem1[ADI_SPI_MEMORY_SIZE]; +ADI_SPI_HANDLE spi_Handle2; +uint8_t spi_Mem2[ADI_SPI_MEMORY_SIZE]; +#if defined(ADI_DEBUG) +#warning "BUILD_SPI_MI_DYNAMIC is NOT defined. Memory allocation for SPI will be static" +int adi_spi_memtype = 1; +#endif +#endif + + + +/** Initialize the SPI peripheral + * + * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral + * @param[out] obj The SPI object to initialize + * @param[in] mosi The pin to use for MOSI + * @param[in] miso The pin to use for MISO + * @param[in] sclk The pin to use for SCLK + * @param[in] ssel The pin to use for SSEL + */ +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + // determine the SPI to use + uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); + uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); + uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); + uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); + uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); + uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); + ADI_SPI_HANDLE *pSPI_Handle; + uint8_t *SPI_Mem; + ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; + uint32_t nDeviceNum = 0; + ADI_SPI_CHIP_SELECT spi_cs = ADI_SPI_CS_NONE; + + +#if defined(BUILD_SPI_MI_DYNAMIC) + if (mosi == SPI0_MOSI) { + nDeviceNum = SPI_0; + } else if (mosi == SPI1_MOSI) { + nDeviceNum = SPI_1; + } else if (mosi == SPI2_MOSI) { + nDeviceNum = SPI_2; + } + pSPI_Handle = &obj->SPI_Handle; + obj->pSPI_Handle = pSPI_Handle; + SPI_Mem = obj->SPI_Mem; +#else + if (mosi == SPI0_MOSI) { + nDeviceNum = SPI_0; + pSPI_Handle = &spi_Handle0; + SPI_Mem = &spi_Mem0[0]; + } else if (mosi == SPI1_MOSI) { + nDeviceNum = SPI_1; + pSPI_Handle = &spi_Handle1; + SPI_Mem = &spi_Mem1[0]; + } else if (mosi == SPI2_MOSI) { + nDeviceNum = SPI_2; + pSPI_Handle = &spi_Handle2; + SPI_Mem = &spi_Mem2[0]; + } + obj->pSPI_Handle = pSPI_Handle; +#endif + + + obj->instance = pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->instance != NC); + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } + + SystemCoreClockUpdate(); + SPI_Return = adi_spi_Open(nDeviceNum, SPI_Mem, ADI_SPI_MEMORY_SIZE, pSPI_Handle); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return; + } + + if (ssel != NC) { + if ( (ssel == SPI0_CS0) || (ssel == SPI1_CS0) || (ssel == SPI2_CS0)) { + spi_cs = ADI_SPI_CS0; + } else if ( (ssel == SPI0_CS1) || (ssel == SPI1_CS1) || (ssel == SPI2_CS1)) { + spi_cs = ADI_SPI_CS1; + } else if ( (ssel == SPI0_CS2) || (ssel == SPI1_CS2) || (ssel == SPI2_CS2)) { + spi_cs = ADI_SPI_CS2; + } else if ( (ssel == SPI0_CS3) || (ssel == SPI1_CS3) || (ssel == SPI2_CS3)) { + spi_cs = ADI_SPI_CS3; + } + + SPI_Return = adi_spi_SetChipSelect(*pSPI_Handle, spi_cs); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return; + } + } +} + + +/** Release a SPI object + * + * TODO: spi_free is currently unimplemented + * This will require reference counting at the C++ level to be safe + * + * Return the pins owned by the SPI object to their reset state + * Disable the SPI peripheral + * Disable the SPI clock + * @param[in] obj The SPI object to deinitialize + */ +void spi_free(spi_t *obj) +{ + ADI_SPI_HANDLE SPI_Handle; + ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; + + SPI_Handle = *obj->pSPI_Handle; + SPI_Return = adi_spi_Close(SPI_Handle); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return; + } +} + + +/** Configure the SPI format + * + * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode. + * The default bit order is MSB. + * @param[in,out] obj The SPI object to configure + * @param[in] bits The number of bits per frame + * @param[in] mode The SPI mode (clock polarity, phase, and shift direction) + * @param[in] slave Zero for master mode or non-zero for slave mode + * + ** Configure the data transmission format + * + * @param bits Number of bits per SPI frame (4 - 16) + * @param mode Clock polarity and phase mode (0 - 3) + * + * @code + * mode | POL PHA + * -----+-------- + * 0 | 0 0 + * 1 | 0 1 + * 2 | 1 0 + * 3 | 1 1 + * @endcode + */ +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + ADI_SPI_HANDLE SPI_Handle; + ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; + bool_t master; + + master = !((bool_t)slave); + SPI_Handle = *obj->pSPI_Handle; + SPI_Return = adi_spi_SetMasterMode(SPI_Handle, master); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return; + } +} + + +/** Set the SPI baud rate + * + * Actual frequency may differ from the desired frequency due to available dividers and bus clock + * Configures the SPI peripheral's baud rate + * @param[in,out] obj The SPI object to configure + * @param[in] hz The baud rate in Hz + */ +void spi_frequency(spi_t *obj, int hz) +{ + ADI_SPI_HANDLE SPI_Handle; + ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; + + SPI_Handle = *obj->pSPI_Handle; + SPI_Return = adi_spi_SetBitrate(SPI_Handle, (uint32_t) hz); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return; + } +} + + +/** Write a byte out in master mode and receive a value + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] value The value to send + * @return Returns the value received during send + */ +int spi_master_write(spi_t *obj, int value) +{ + ADI_SPI_TRANSCEIVER transceive; + uint8_t TxBuf; + uint8_t RxBuf; + ADI_SPI_HANDLE SPI_Handle; + ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; + + TxBuf = (uint8_t)value; + + transceive.pReceiver = &RxBuf; + transceive.ReceiverBytes = 1; /* link transceive data size to the remaining count */ + transceive.nRxIncrement = 1; /* auto increment buffer */ + transceive.pTransmitter = &TxBuf; /* initialize data attributes */ + transceive.TransmitterBytes = 1; /* link transceive data size to the remaining count */ + transceive.nTxIncrement = 1; /* auto increment buffer */ + + transceive.bDMA = false; + transceive.bRD_CTL = false; + SPI_Handle = *obj->pSPI_Handle; + SPI_Return = adi_spi_MasterReadWrite(SPI_Handle, &transceive); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return 1; + } + + return((int)RxBuf); +} + + +/** Check if a value is available to read + * + * @param[in] obj The SPI peripheral to check + * @return non-zero if a value is available + */ +int spi_slave_receive(spi_t *obj) +{ + return 0; +} + + +/** Get a received value out of the SPI receive buffer in slave mode + * + * Blocks until a value is available + * @param[in] obj The SPI peripheral to read + * @return The value received + */ +int spi_slave_read(spi_t *obj) +{ + return 0; +} + + +/** Write a value to the SPI peripheral in slave mode + * + * Blocks until the SPI peripheral can be written to + * @param[in] obj The SPI peripheral to write + * @param[in] value The value to write + */ +void spi_slave_write(spi_t *obj, int value) +{ + return; +} + + +/** Write a block out in master mode and receive a value + * + * The total number of bytes sent and recieved will be the maximum of + * tx_length and rx_length. The bytes written will be padded with the + * value 0xff. + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] tx_buffer Pointer to the byte-array of data to write to the device + * @param[in] tx_length Number of bytes to write, may be zero + * @param[in] rx_buffer Pointer to the byte-array of data to read from the device + * @param[in] rx_length Number of bytes to read, may be zero + * @param[in] write_fill Default data transmitted while performing a read + * @returns + * The number of bytes written and read from the device. This is + * maximum of tx_length and rx_length. + */ +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) +{ + return 0; +} + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c new file mode 100755 index 0000000000..4012775454 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c @@ -0,0 +1,96 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#if defined(DEVICE_TRNG) + +#include +#include +#include +#include "cmsis.h" +#include "trng_api.h" + +// Sampling counter values +// Prescaler: 0 - 10 +// LenReload: 0 - 4095 +#define TRNG_CNT_VAL 4095 +#define TRNG_PRESCALER 2 + +static ADI_RNG_HANDLE RNGhDevice; /* Memory to handle CRC Device */ +static uint32_t RngDevMem[(ADI_RNG_MEMORY_SIZE + 3)/4]; /* Data buffers for Random numbers */ + +void trng_init(trng_t *obj) +{ + (void)obj; + adi_rng_Open(0,RngDevMem,sizeof(RngDevMem),&RNGhDevice); + + // Set sample length for the H/W RN accumulator + adi_rng_SetSampleLen(RNGhDevice, TRNG_PRESCALER, TRNG_CNT_VAL); + + // Enable the RNG + adi_rng_Enable(RNGhDevice, true); +} + +void trng_free(trng_t *obj) +{ + (void)obj; + adi_rng_Enable(RNGhDevice, false); + adi_rng_Close(RNGhDevice); +} + +int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) +{ + (void)obj; + bool bRNGRdy; + uint32_t nRandomNum, i; + + for (i = 0; i < length; ) { + // wait for the RNG ready to give a random number + adi_rng_GetRdyStatus(RNGhDevice, &bRNGRdy); + if (bRNGRdy) { + // read the random number + adi_rng_GetRngData(RNGhDevice, &nRandomNum); + output[i++] = (uint8_t) nRandomNum; + } + } + *output_length = length; + return 0; +} + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/us_ticker.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/us_ticker.c new file mode 100755 index 0000000000..f782e4745a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/us_ticker.c @@ -0,0 +1,346 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include +#include +#include +#include +#include + +#ifndef BITM_TMR_RGB_CTL_EN +#define BITM_TMR_RGB_CTL_EN BITM_TMR_CTL_EN +#endif + +typedef uint32_t timestamp_t; + +// defined in mbed_us_ticker_api.c which calls the ticker_irq_handler() routine +// defined in mbed_ticker_api.c +void us_ticker_irq_handler(void); + +static int us_ticker_inited = 0; + +static ADI_TMR_CONFIG tmrConfig, tmr2Config; + +static volatile uint32_t Upper_count = 0, largecnt = 0; + +static ADI_TMR_TypeDef * adi_tmr_registers[ADI_TMR_DEVICE_NUM] = {pADI_TMR0, pADI_TMR1, pADI_TMR2}; + +#if defined(__ADUCM302x__) +static const IRQn_Type adi_tmr_interrupt[ADI_TMR_DEVICE_NUM] = {TMR0_EVT_IRQn, TMR1_EVT_IRQn, TMR2_EVT_IRQn}; +#elif defined(__ADUCM4x50__) +static const IRQn_Type adi_tmr_interrupt[ADI_TMR_DEVICE_NUM] = {TMR0_EVT_IRQn, TMR1_EVT_IRQn, TMR2_EVT_IRQn, TMR_RGB_EVT_IRQn}; +#else +#error TMR is not ported for this processor +#endif + + +/*---------------------------------------------------------------------------* + Local functions + *---------------------------------------------------------------------------*/ +static void GP1CallbackFunction(void *pCBParam, uint32_t Event, void * pArg) +{ + Upper_count++; +} + + +static uint32_t get_current_time(void) +{ + uint16_t tmrcnt0, tmrcnt1; + uint32_t totaltmr0, totaltmr1; + uint32_t uc1, tmrpend0, tmrpend1; + + do { + volatile uint32_t *ucptr = &Upper_count; + + /* + * Carefully coded to prevent race conditions. Do not make changes unless you understand all the + * implications. + * + * Note this function can be called with interrupts globally disabled or enabled. It has been coded to work in both cases. + * + * TMR0 and TMR1 both run from the same synchronous clock. TMR0 runs at 26MHz and TMR1 runs at 26/256MHz. + * TMR1 generates an interrupt every time it overflows its 16 bit counter. TMR0 runs faster and provides + * the lowest 8 bits of the current time count. When TMR0 and TMR1 are combined, they provide 24 bits of + * timer precision. i.e. (TMR0.CURCNT & 0xff) + (TMR1.CURCNT << 8) + * + * There are several race conditions protected against: + * 1. TMR0 and TMR1 are both read at the same time, however, on rare occasions, one will have incremented before the other. + * Therefore we read both timer counters, and check if the middle 8 bits match, if they don't then read the counts again + * until they do. This ensures that one or the other counters are stable with respect to each other. + * + * 2. TMR1.CURCNT and Upper_count racing. Prevent this by disabling the TMR1 interrupt, which stops Upper_count increment interrupt (GP1CallbackFunction). + * Then check pending bit of TMR1 to see if we missed Upper_count interrupt, and add it manually later. + * + * 3. Race between the TMR1 pend, and the TMR1.CURCNT read. Even with TMR1 interrupt disabled, the pend bit + * may be set while TMR1.CURCNT is being read. We don't know if the pend bit matches the TMR1 state. + * To prevent this, the pending bit is read twice, and we see if it matches; if it doesn't, loop around again. + * + * Note the TMR1 interrupt is enabled on each iteration of the loop to flush out any pending TMR1 interrupt, + * thereby clearing any TMR1 pend's. This have no effect if this routine is called with interrupts globally disabled. + */ + + NVIC_DisableIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]); // Prevent Upper_count increment + tmrpend0 = NVIC_GetPendingIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]); + // Check if there is a pending interrupt for timer 1 + + __DMB(); // memory barrier: read GP0 before GP1 + + tmrcnt0 = adi_tmr_registers[ADI_TMR_DEVICE_GP0]->CURCNT; // to minimize skew, read both timers manually + + __DMB(); // memory barrier: read GP0 before GP1 + + tmrcnt1 = adi_tmr_registers[ADI_TMR_DEVICE_GP1]->CURCNT; // read both timers manually + + totaltmr0 = tmrcnt0; // expand to u32 bits + totaltmr1 = tmrcnt1; // expand to u32 bits + + tmrcnt0 &= 0xff00u; + tmrcnt1 <<= 8; + + __DMB(); + + uc1 = *ucptr; // Read Upper_count + + tmrpend1 = NVIC_GetPendingIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]); + // Check for a pending interrupt again. Only leave loop if they match + + NVIC_EnableIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]); // enable interrupt on every loop to allow TMR1 interrupt to run + } while ((tmrcnt0 != tmrcnt1) || (tmrpend0 != tmrpend1)); + + totaltmr1 <<= 8; // Timer1 runs 256x slower + totaltmr1 += totaltmr0 & 0xffu; // Use last 8 bits of Timer0 as it runs faster + // totaltmr1 now contain 24 bits of significance + + if (tmrpend0) { // If an interrupt is pending, then increment local copy of upper count + uc1++; + } + + uint64_t Uc = totaltmr1; // expand out to 64 bits unsigned + Uc += ((uint64_t) uc1) << 24; // Add on the upper count to get the full precision count + + // Divide Uc by 26 (26MHz converted to 1MHz) todo scale for other clock freqs + + Uc *= 1290555u; // Divide total(1/26) << 25 + Uc >>= 25; // shift back. Fixed point avoid use of floating point divide. + // Compiler does this inline using shifts and adds. + + return Uc; +} + + +static void calc_event_counts(uint32_t timestamp) +{ + uint32_t calc_time, blocks, offset; + uint64_t aa; + + calc_time = get_current_time(); + offset = timestamp - calc_time; // offset in useconds + + if (offset > 0xf0000000u) // if offset is a really big number, assume that timer has already expired (i.e. negative) + offset = 0u; + + if (offset > 10u) { // it takes 10us to user timer routine after interrupt. Offset timer to account for that. + offset -= 10u; + } else + offset = 0u; + + aa = (uint64_t) offset; + aa *= 26u; // convert from 1MHz to 26MHz clock. todo scale for other clock freqs + + blocks = aa >> 7; + blocks++; // round + + largecnt = blocks>>1; // communicate to event_timer() routine +} + +static void event_timer() +{ + if (largecnt) { + uint32_t cnt = largecnt; + + if (cnt > 65535u) { + cnt = 0u; + } else + cnt = 65536u - cnt; + + tmr2Config.nLoad = cnt; + tmr2Config.nAsyncLoad = cnt; + adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP2, tmr2Config); + adi_tmr_Enable(ADI_TMR_DEVICE_GP2, true); + } else { + us_ticker_irq_handler(); + } +} + + +/* + * Interrupt routine for timer 2 + * + * largecnt counts how many timer ticks should be counted to reach timer event. + * Each interrupt happens every 65536 timer ticks, unless there are less than 65536 ticks to count. + * In that case do the remaining timers ticks. + * + * largecnt is a global that is used to communicate between event_timer and the interrupt routine + * On entry, largecnt will be any value larger than 0. + */ +static void GP2CallbackFunction(void *pCBParam, uint32_t Event, void * pArg) +{ + if (largecnt >= 65536u) { + largecnt -= 65536u; + } else + largecnt = 0; + + if (largecnt < 65536u) { + adi_tmr_Enable(ADI_TMR_DEVICE_GP2, false); + event_timer(); + } +} + + +/*---------------------------------------------------------------------------* + us_ticker HAL APIs + *---------------------------------------------------------------------------*/ +void us_ticker_init(void) +{ + if (us_ticker_inited) { + return; + } + + us_ticker_inited = 1; + + /*--------------------- GP TIMER INITIALIZATION --------------------------*/ + + /* Set up GP0 callback function */ + adi_tmr_Init(ADI_TMR_DEVICE_GP0, NULL, NULL, false); + + /* Set up GP1 callback function */ + adi_tmr_Init(ADI_TMR_DEVICE_GP1, GP1CallbackFunction, NULL, true); + + /* Set up GP1 callback function */ + adi_tmr_Init(ADI_TMR_DEVICE_GP2, GP2CallbackFunction, NULL, true); + + /* Configure GP0 to run at 26MHz */ + tmrConfig.bCountingUp = true; + tmrConfig.bPeriodic = true; + tmrConfig.ePrescaler = ADI_TMR_PRESCALER_1; // TMR0 at 26MHz + tmrConfig.eClockSource = ADI_TMR_CLOCK_PCLK; // TMR source is PCLK (most examples use HFOSC) + tmrConfig.nLoad = 0; + tmrConfig.nAsyncLoad = 0; + tmrConfig.bReloading = false; + tmrConfig.bSyncBypass = true; // Allow x1 prescale: requires PCLK as a clk + adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP0, tmrConfig); + + /* Configure GP1 to have a period 256 times longer than GP0 */ + tmrConfig.nLoad = 0; + tmrConfig.nAsyncLoad = 0; + tmrConfig.ePrescaler = ADI_TMR_PRESCALER_256; // TMR1 = 26MHz/256 + adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP1, tmrConfig); + + /* Configure GP2 for doing event counts */ + tmr2Config.bCountingUp = true; + tmr2Config.bPeriodic = true; + tmr2Config.ePrescaler = ADI_TMR_PRESCALER_256; // TMR2 at 26MHz/256 + tmr2Config.eClockSource = ADI_TMR_CLOCK_PCLK; // TMR source is PCLK (most examples use HFOSC) + tmr2Config.nLoad = 0; + tmr2Config.nAsyncLoad = 0; + tmr2Config.bReloading = false; + tmr2Config.bSyncBypass = true; // Allow x1 prescale + adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP2, tmr2Config); + + + /*------------------------- GP TIMER ENABLE ------------------------------*/ + + /* Manually enable both timers to get them started at the same time + * + */ + adi_tmr_registers[ADI_TMR_DEVICE_GP0]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EN; + adi_tmr_registers[ADI_TMR_DEVICE_GP1]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EN; +} + +uint32_t us_ticker_read() +{ + uint32_t curr_time; + + if (!us_ticker_inited) { + us_ticker_init(); + } + + curr_time = get_current_time(); + + return curr_time; +} + +void us_ticker_disable_interrupt(void) +{ + adi_tmr_Enable(ADI_TMR_DEVICE_GP2, false); +} + +void us_ticker_clear_interrupt(void) +{ + NVIC_ClearPendingIRQ(TMR2_EVT_IRQn); +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + + /* timestamp is when interrupt should fire. + * + * This MUST not be called if another timer event is currently enabled. + * + */ + calc_event_counts(timestamp); // use timestamp to calculate largecnt to control number of timer interrupts + event_timer(); // uses largecnt to initiate timer interrupts +} + +/** Set pending interrupt that should be fired right away. + * + * The ticker should be initialized prior calling this function. + * + * This MUST not be called if another timer event is currently enabled. + */ +void us_ticker_fire_interrupt(void) +{ + NVIC_SetPendingIRQ(TMR2_EVT_IRQn); +} + + +/* +** EOF +*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050.h new file mode 100755 index 0000000000..39158f2f9c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050.h @@ -0,0 +1,26 @@ +/* +** ADuCM4050.h +** +** Copyright (C) 2016 Analog Devices, Inc. All Rights Reserved. +** +*/ + +#ifndef ADUCM4050_H +#define ADUCM4050_H + +#include +#include + +#define __CM4_REV 0x0001U /*!< CM4 Core Revision r0p1 */ +#define __MPU_PRESENT 1u /*!< MPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1u /*!< FPU present */ +#endif +#define __NVIC_PRIO_BITS 3u /*!< Number of Bits for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< 1 if different SysTick Config is used */ + +#include + +#include "system_ADuCM4050.h" + +#endif /* ADUCM4050_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_cdef.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_cdef.h new file mode 100755 index 0000000000..8b6f35d28c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_cdef.h @@ -0,0 +1,18 @@ +/* +** ADuCM4050_cdef.h +** +** Copyright (C) 2016 Analog Devices, Inc. All Rights Reserved. +** +*/ + +#ifndef _WRAP_ADUCM4050_CDEF_H +#define _WRAP_ADUCM4050_CDEF_H + +#include + +#include + +#include +#include + +#endif /* _WRAP_ADUCM4050_CDEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_def.h new file mode 100755 index 0000000000..222e865aa4 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_def.h @@ -0,0 +1,34 @@ +/* +** ADuCM4050_def.h +** +** Copyright (C) 2016-2017 Analog Devices, Inc. All Rights Reserved. +** +*/ + +#ifndef _WRAP_ADUCM4050_DEF_H +#define _WRAP_ADUCM4050_DEF_H + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions: + * + * Pm008 (rule 2.4): sections of code should not be 'commented out'. + * Some comments are wrongly identified as code. + * + * Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters. + * The YODA-generated headers rely on more. The IAR compiler supports that. + */ +_Pragma("diag_suppress=Pm008,Pm009") +#endif /* __ICCARM__ */ + +#ifdef __IASMARM__ +/* Define masks to plain numeric literal for IAR assembler. */ +#define _ADI_MSK_3( mask, smask, type ) (mask) +#endif /* __IASMARM__ */ + +#include + +#ifdef __ICCARM__ +_Pragma("diag_default=Pm008,Pm009") +#endif /* __ICCARM__ */ + +#endif /* _WRAP_ADUCM4050_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_device.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_device.h new file mode 100755 index 0000000000..28b096bfc0 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_device.h @@ -0,0 +1,29 @@ +/* +** ADuCM4050_device.h +** +** Copyright (C) 2016 Analog Devices, Inc. All Rights Reserved. +** +*/ + +#ifndef _WRAP_ADUCM4050_DEVICE_H +#define _WRAP_ADUCM4050_DEVICE_H + +#include +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions: + * + * Pm093 (rule 18.4): use of union - overlapping storage shall not be used. + * Unions are required by sys/adi_ADuCM4050_device.h. + */ +_Pragma("diag_suppress=Pm093") +#endif /* __ICCARM__ */ + +#include + +#ifdef __ICCARM__ +_Pragma("diag_default=Pm093") +#endif /* __ICCARM__ */ + +#endif /* _WRAP_ADUCM4050_DEVICE_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_typedefs.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_typedefs.h new file mode 100755 index 0000000000..6354190e97 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_typedefs.h @@ -0,0 +1,31 @@ +/* +** ADuCM4050_typedefs.h +** +** Copyright (C) 2016 Analog Devices, Inc. All Rights Reserved. +** +*/ + +#ifndef _WRAP_ADUCM4050_TYPEDEFS_H +#define _WRAP_ADUCM4050_TYPEDEFS_H + +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions: + * + * Pm008 (rule 2.4): sections of code should not be 'commented out'. + * Some comments are wrongly identified as code. + * + * Pm093 (rule 18.4): use of union - overlapping storage shall not be used. + * Unions are required by sys/adi_ADuCM4050_typedefs.h. + */ +_Pragma("diag_suppress=Pm008,Pm093") +#endif /* __ICCARM__ */ + +#include + +#ifdef __ICCARM__ +_Pragma("diag_default=Pm008,Pm093") +#endif /* __ICCARM__ */ + +#endif /* _WRAP_ADUCM4050_TYPEDEFS_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc.c new file mode 100755 index 0000000000..ea473df8de --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc.c @@ -0,0 +1,2371 @@ +/*! ***************************************************************************** + * @file: adi_adc.c + * @brief: ADC device driver global file. + * @details: This file contain the ADC device driver implementation. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +/** @addtogroup ADC_Driver ADC Driver + * @{ + * @brief ADC Driver + * @details The ADC driver manages all instances of the ADC peripheral. + * @note - The application must include drivers/adc/adi_adc.h to use this driver. + * @note - This driver also requires the DMA driver. The application must include + the DMA driver sources to avoid link errors. + */ + +#ifndef ADI_ADC_C +/*! \cond PRIVATE */ +#define ADI_ADC_C + +/*============= I N C L U D E S =============*/ + + +/* Header file with definitions specific to ADC driver implementation */ + +/*============= A D C I M P L E M E N T A T I O N S O U R C E F I L E S =============*/ +#include +#include +#include +#include +#include +#include +#include + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Needed for null expansion of ADI_INSTALL_HANDLER and others. +* +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Relying on pointer arithmetic for buffer handling. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +* +* Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type +* Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors + +*/ +#pragma diag_suppress=Pm123,Pm073,Pm143,Pm050,Pm088,Pm140,Pm152 +#endif /* __ICCARM__ */ + +#include "adi_adc_def.h" +#include "adi_adc_data.c" + +/*============== D E F I N E S ===============*/ +#ifdef ADI_DEBUG +#define ADI_ADC_INVALID_HANDLE(h) (AdcDevInfo[0].hDevice != (h)) +#endif + +/* Specify the maximum acquisition time, based on the width of the SAMPTIME field. */ +#define ADI_MAX_ACQUISITION_TIME (((uint32_t)BITM_ADC_CNV_TIME_SAMPTIME << BITP_ADC_CNV_TIME_SAMPTIME) + 1u) + +/* The 12bit maximum sample value */ +#define ADI_ADC_SAMPLE_MAX ((uint16_t)(4095u)) + +/*============= C O D E =============*/ + +/*============= D E B U G F U N C T I O N P R O T O T Y P E S =============*/ + +/* Override "weak" default binding in startup_*.c */ +/*! \cond PRIVATE */ +extern void ADC0_Int_Handler(void); +extern void DMA_ADC0_Int_Handler (void); + +/*! \endcond */ + +/* Prototypes for static functions (required by MISRA-C:2004 Rule 8.1) */ +/*============= L O C A L F U N C T I O N S P R O T O T Y P E S =============*/ +static uint16_t ReadOutReg(uint32_t nChannelNum); + +/* ADC management functions, based on transfer method */ +#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 +static ADI_ADC_RESULT DmaFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode); +#else +static ADI_ADC_RESULT InterruptFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode); +#endif + +/* Channel helper functions */ +static uint32_t GetNumChannels(uint32_t nChannels); +static int32_t nGetChannelNumber(ADI_ADC_CHANNEL eChannel); + +/* Buffer management functions */ +static void ManageFifoCompletion(ADI_ADC_DEVICE *pDevice); +static bool InitBufferProcessing(ADI_ADC_DEVICE *pDevice); +static void FlushFifo(ADI_ADC_DEVICE *pDevice, uint32_t nChannels); + +/* Internal configuration functions */ +static void EnableComparator(ADI_ADC_DEVICE *pDevice, bool bEnable); +static void StaticConfiguration(ADI_ADC_DEVICE *pDevice); + +/*! \endcond */ + +/*============= P U B L I C F U N C T I O N S =============*/ + +/** + * @brief Opens an ADC device instance. + * + * @param [in] nDeviceNum Device number to open + * @param [in] pMemory Pointer to a #ADI_ADC_MEMORY_SIZE sized buffer to manage the device + * instance. + * @param [in] nMemorySize Size of the buffer to which "pMemory" points + * @param [out] phDevice Pointer to a location where ADC device handle is to be written. + * + * @return Status + * - #ADI_ADC_SUCCESS Call completed successfully + * - #ADI_ADC_INVALID_DEVICE_NUM [D] Invalid Device Number + * - #ADI_ADC_INSUFFICIENT_MEMORY [D] Memory passed is not sufficient + * - #ADI_ADC_IN_USE [D] ADC driver was already opened + */ +ADI_ADC_RESULT adi_adc_Open ( + uint32_t nDeviceNum, + void *pMemory, + uint32_t nMemorySize, + ADI_ADC_HANDLE *phDevice) +{ + ADI_INT_STATUS_ALLOC(); + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)pMemory; + +#ifdef ADI_DEBUG + if (nDeviceNum > (sizeof (AdcDevInfo)/sizeof(AdcDevInfo[0]))) + { + return ADI_ADC_INVALID_DEVICE_NUM; + } + + if (nMemorySize < ADI_ADC_MEMORY_SIZE) + { + return ADI_ADC_INSUFFICIENT_MEMORY; + } + + if (AdcDevInfo[nDeviceNum].hDevice != NULL) + { + return ADI_ADC_IN_USE; + } + + assert (ADI_ADC_MEMORY_SIZE >= sizeof (ADI_ADC_DEVICE)); +#endif /* ADI_DEBUG */ + + memset (pMemory, 0, nMemorySize); + + ADI_ENTER_CRITICAL_REGION(); + AdcDevInfo[nDeviceNum].hDevice = (ADI_ADC_HANDLE)pDevice; + pDevice->pReg = AdcDevInfo[nDeviceNum].pReg; + ADI_EXIT_CRITICAL_REGION(); + + /* Reset the ADC */ + pDevice->pReg->CFG = BITM_ADC_CFG_RST; + + /* Enable the IRQs */ + NVIC_ClearPendingIRQ(ADC0_EVT_IRQn); + NVIC_EnableIRQ(ADC0_EVT_IRQn); + + /* Initialize the registers to known value */ + pDevice->pReg->IRQ_EN = BITM_ADC_IRQ_EN_RDY | BITM_ADC_IRQ_EN_ALERT | BITM_ADC_IRQ_EN_OVF | BITM_ADC_IRQ_EN_CALDONE | BITM_ADC_IRQ_EN_CNVDONE; + + /* Do the static configuration */ + StaticConfiguration(pDevice); + + /* Create a semaphore for buffer management */ + SEM_CREATE(pDevice, "ADC Sem", ADI_ADC_ERR_RTOS); + + /* Set the default FIFO Manage function */ +#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 + pDevice->pfManageFifo = DmaFIFOManage; + /* Make sure the DMA controller and its SRAM based descriptors are initialized */ + adi_dma_Init(); +#else + pDevice->pfManageFifo = InterruptFIFOManage; +#endif + + /* Return the device handle back to the application */ + *phDevice = AdcDevInfo[nDeviceNum].hDevice; + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief Close the given device instance + * + * @param [in] hDevice Handle to the device instance + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully closed the device + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle based to the function + */ +ADI_ADC_RESULT adi_adc_Close (ADI_ADC_HANDLE hDevice) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + ADI_ADC_RESULT eResult; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } +#endif /* ADI_DEBUG */ + + /* Power down the device */ + if ((eResult = adi_adc_PowerUp (hDevice, false)) != ADI_ADC_SUCCESS) { + return eResult; + } + + /* Disable the IRQ */ + pDevice->pReg->IRQ_EN = 0u; + + /* Clear the conversion cfg register to stop any transaction */ + pDevice->pReg->CNV_CFG = 0u; + +#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 + /* Close the DMA if configured */ + NVIC_DisableIRQ(DMA0_CH24_DONE_IRQn); +#endif /* ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 */ + + /* Disable the ADC interrupt */ + NVIC_DisableIRQ(ADC0_EVT_IRQn); + + /* Destroy the semaphore */ + SEM_DELETE(pDevice, ADI_ADC_ERR_RTOS); + + /* Finally, zero the device */ + AdcDevInfo[0].hDevice = (NULL); + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief Power up ADC + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] bPowerUp 'true' to power up and 'false' to power down the ADC. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully closed the device + * - #ADI_ADC_BAD_SYS_CLOCK Unable to obtain PCLK which is needed to calculate + * powerup values. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the function + */ +ADI_ADC_RESULT adi_adc_PowerUp (ADI_ADC_HANDLE hDevice, bool bPowerUp) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint32_t nClock = 0u; + uint16_t nCount = 0u; + ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } +#endif /* ADI_DEBUG */ + + if (bPowerUp == true) + { + if (IS_NOT_IN_ANY_STATE(ADC_STATUS_POWERED_UP)) + { + if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &nClock) == ADI_PWR_SUCCESS) + { + /* We need the cycles equivelent of 20us entered here, based on the PCLK + * clock. nClock is the frequency of the PCLK, 50000 is the equivalent frequency of 20us + * e.g. 26,000,000Hz, 0.00002s produces 520 cycles.*/ + nCount = (uint16_t)(nClock / 50000u); + + /* Powering up ADC */ + pDevice->pReg->CFG |= BITM_ADC_CFG_PWRUP; + + /* Set ADC_PWRUP.WAIT bits for the new count */ + pDevice->pReg->PWRUP = (uint16_t)(((uint32_t)nCount << BITP_ADC_PWRUP_WAIT) & BITM_ADC_PWRUP_WAIT); + + SET_STATE(ADC_STATUS_POWERED_UP); + } + else + { + eResult = ADI_ADC_BAD_SYS_CLOCK; + } + } + } + else + { + if (IS_IN_STATE(ADC_STATUS_POWERED_UP)) + { + /* If the ADC system is up then disable the ADC subsystem */ + if ( IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN) ) + { + eResult = adi_adc_EnableADCSubSystem (hDevice, false); + if (eResult != ADI_ADC_SUCCESS) + { + return eResult; + } + } + + /* Powering down ADC */ + pDevice->pReg->CFG &= (uint16_t)(~(BITM_ADC_CFG_PWRUP)); + CLR_STATE(ADC_STATUS_POWERED_UP); + } + } + + return eResult; +} + + +/** + * @brief Registering a callback function + * + * @param [in] hDevice Handle to the device instance + * @param [in] pfCallback Function pointer to callback function. Passing a NULL pointer will + * unregister the call back function. + * @param [in] pCBParam Call back function parameter + * + * @details This function registers a call back function. Registered function will be called when + * the given computation is over. It will also be called when the digital comparitor is being + * used and a limit has been broken. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully registerd the callback + * - #ADI_ADC_INVALID_SEQUENCE [D] Callback cannot be registered when ADC is enabled for sampling. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the function + */ +ADI_ADC_RESULT adi_adc_RegisterCallback ( + ADI_ADC_HANDLE hDevice, + ADI_CALLBACK pfCallback, + void *pCBParam) +{ + ADI_INT_STATUS_ALLOC(); + + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + +#endif /* ADI_DEBUG */ + + ADI_ENTER_CRITICAL_REGION(); + pDevice->pfCallback = pfCallback; + pDevice->pCBParam = pCBParam; + ADI_EXIT_CRITICAL_REGION(); + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Enable/Disables the ADC Subsystem + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] bEnable 'true' to Enable and 'false' to Disable` + * + * @details Enables/Disables the ADC Subsystem. The ADC subsystem need to be enabled before using the ADC + * for sampling the signal. The driver should check whether the ADC is ready by calling adi_adc_IsReady + * API before continuing. If internal reference buffer is used as voltage reference then application + * has to wait at least 3.5ms after enabling irrespective of whether adi_adc_IsReady returns ready or not. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully enabled/disabled the ADC subsystem + * - #ADI_ADC_INVALID_SEQUENCE [D] Can only be called if the ADC is powered up, + * and cannot be disabled when sampling or using + * the camparator. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the function + */ +ADI_ADC_RESULT adi_adc_EnableADCSubSystem ( + ADI_ADC_HANDLE hDevice, + bool bEnable) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (IS_NOT_IN_STATE(ADC_STATUS_POWERED_UP)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + + if (bEnable == true) { + if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) { + return ADI_ADC_INVALID_SEQUENCE; + } + } else { + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) { + return ADI_ADC_INVALID_SEQUENCE; + } + } +#endif /* ADI_DEBUG */ + + if (bEnable == true) + { + pDevice->pReg->CFG |= BITM_ADC_CFG_EN; + SET_STATE(ADC_STATUS_SUB_SYSTEM_EN); + } + else + { + pDevice->pReg->CFG &= (uint16_t)(~BITM_ADC_CFG_EN); + CLR_STATE(ADC_STATUS_SUB_SYSTEM_EN | ADC_STATUS_SUB_SYSTEM_READY); + } + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief Returns whether the ADC Subsystem is ready + * + * @param [in] hDevice Handle to the device instance + * + +* @param [in] pbReady Pointer to a bool variable. The variable will be set to 'true' if the ADC is ready else 'false' + * + * @details Returns whether the ADC is ready for sampling. This API should be called after enabling the ADC sub-system using + * adi_adc_EnableADCSubSystem API. If internal reference buffer is used as voltage reference then application + * has to wait at least 3.5ms after enabling irrespective of whether adi_adc_IsReady returns ready or not. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully returned the ready status + * - #ADI_ADC_INVALID_SEQUENCE [D] Cannot be called if the subsystem is not enabled. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the function + * - #ADI_ADC_NULL_POINTER [D] pbReady is NULL + */ + +ADI_ADC_RESULT adi_adc_IsReady ( + ADI_ADC_HANDLE hDevice, + bool *pbReady +) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (pbReady == NULL) + { + return ADI_ADC_NULL_POINTER; + } + + if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } +#endif /* ADI_DEBUG */ + + if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_READY)) + { + *pbReady = true; + } + else + { + *pbReady = false; + } + return ADI_ADC_SUCCESS; +} + +/** + * @brief Set the Voltage Reference source + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] eVrefSrc Voltage Reference source to be used + * + * @details The API can be used to select the voltage reference to be used by the ADC. This option need to be + * set before enabling the ADC subsystem. + * + * @return Status + * - #ADI_ADC_SUCCESS Succesfully set the Vref source + * - #ADI_ADC_INVALID_PARAMETER Vref source enum passed is invalid. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle based to the function. + * - #ADI_ADC_INVALID_SEQUENCE [D] VREF cannot be changed once the ADC subsystem is enabled. + */ + +ADI_ADC_RESULT adi_adc_SetVrefSource ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_VREF_SRC eVrefSrc) +{ + ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS; + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } +#endif /* ADI_DEBUG */ + + pDevice->pReg->CFG &= (uint16_t)(~(BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL | BITM_ADC_CFG_VREFVBAT)); + + switch (eVrefSrc) + { + case ADI_ADC_VREF_SRC_INT_1_25_V: + pDevice->pReg->CFG |= BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL; + break; + + case ADI_ADC_VREF_SRC_INT_2_50_V: + pDevice->pReg->CFG |= BITM_ADC_CFG_REFBUFEN; + break; + + case ADI_ADC_VREF_SRC_VBAT: + pDevice->pReg->CFG |= BITM_ADC_CFG_VREFVBAT; + break; + + case ADI_ADC_VREF_SRC_EXT: + break; + + default: + eResult = ADI_ADC_INVALID_PARAMETER; + break; + } + + return eResult; +} + + +/** + * @brief Enable/Disable Current Sink + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] bEnable 'true' to Enable and 'false' to Disable current sink + * + * @details If the volatage reference is required to sink current then this option need to be enabled. + * The ADC subsystem has the capability to sink upto 50uA at Vref of 1.25V and 100uA at Vref of 2.5V + + * @return Status + * - #ADI_ADC_SUCCESS Successfully enabled sink + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + */ + +ADI_ADC_RESULT adi_adc_SinkEnable ( + ADI_ADC_HANDLE hDevice, + bool bEnable) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } +#endif /* ADI_DEBUG */ + + if (bEnable == true) + { + pDevice->pReg->CFG |= BITM_ADC_CFG_SINKEN; + } + else + { + pDevice->pReg->CFG &= (uint16_t)~(BITM_ADC_CFG_SINKEN); + } + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief Start the ADC calibration + * + * @param [in] hDevice Handle to the device instance + * + * @details The call to this function initiate calibration of the ADC. The user is recommended to do calibration of the ADC after + * enabling the ADC subsystem. The status of the calibration can be checked using adi_adc_IsCalibrationDone API. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully initiated calibration of ADC + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_SEQUENCE [D] Sampling cannot be enabled if the ADC is enabled. + */ +ADI_ADC_RESULT adi_adc_StartCalibration(ADI_ADC_HANDLE hDevice) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + /* Calibration cannot be done when ADC is processing the buffers */ + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + +#endif /* ADI_DEBUG */ + + /* Clear the calibration done state */ + CLR_STATE(ADC_STATUS_CALIBRATION_DONE); + + /* Clear ADC_STAT.CALDONE */ + pDevice->pReg->STAT = BITM_ADC_STAT_CALDONE; + + /* Set the state as calibration enabled. This state will be cleared when we get the + calibration done interrupt. */ + SET_STATE (ADC_STATUS_CALIBRATION_EN); + + /* Start ADC calibration */ + pDevice->pReg->CFG |= BITM_ADC_CFG_STARTCAL; + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Returns the status of the calibration which was initiated. + * + * @param [in] hDevice Handle to the device instance + * + * @param [out] pbCalibrationDone Pointer to the location to which the status of calibration is written. + * 'true' if the calibration started by call to is done else 'false' + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully retrieved the status of ADC calibration. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_NULL_POINTER [D] pbCalibrationDone is NULL + */ + +ADI_ADC_RESULT adi_adc_IsCalibrationDone ( + ADI_ADC_HANDLE hDevice, + bool *pbCalibrationDone) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (pbCalibrationDone == NULL) + { + return ADI_ADC_NULL_POINTER; + } +#endif /* ADI_DEBUG */ + + /* The driver will check whether the driver is set to calibration done state. This state will + * be set in the driver when the calibration done interrupt is received by the driver + */ + if (IS_IN_STATE(ADC_STATUS_CALIBRATION_DONE)) + { + *pbCalibrationDone = true; + } + else + { + *pbCalibrationDone = false; + } + + return ADI_ADC_SUCCESS; +} + + + +/** + * @brief Set the acquisition time of ADC in ADC clock cycles + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] nAcqTimeInAClkCycles Acquisition time in ADC clock cycles. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully set the acquisition time of ADC + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_SEQUENCE [D] Acquisition time cannot be set when the ADC is enabled for sampling + * - #ADI_ADC_INVALID_PARAMETER [D] nAcqTimeInAClkCycles is not in the valid range + */ +ADI_ADC_RESULT adi_adc_SetAcquisitionTime ( + ADI_ADC_HANDLE hDevice, + uint32_t nAcqTimeInAClkCycles + ) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint16_t nCnvTime; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + + /* A valid range is 1u to the width of the SAMPTIME field + 1. */ + if ((nAcqTimeInAClkCycles == 0u) || (nAcqTimeInAClkCycles > (ADI_MAX_ACQUISITION_TIME))) + { + return ADI_ADC_INVALID_PARAMETER; + } + +#endif /* ADI_DEBUG */ + + /* Acquisition phase is (ADC_CNV_TIME.SAMPTIME + 1) ACLK cycles */ + nCnvTime = pDevice->pReg->CNV_TIME; + nCnvTime &= (uint16_t)(~BITM_ADC_CNV_TIME_SAMPTIME); + nCnvTime |= (uint16_t)((nAcqTimeInAClkCycles - ((uint32_t)1u)) << BITP_ADC_CNV_TIME_SAMPTIME); + pDevice->pReg->CNV_TIME = nCnvTime; + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Set the delay time of ADC in ADC cycles for multi iteration mode. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] nDelayInAClkCycles Delay time in ADC clock cycles. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully set delay time + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_PARAMETER [D] nDelayInAClkCycles is not in the valid range + */ +ADI_ADC_RESULT adi_adc_SetDelayTime ( + ADI_ADC_HANDLE hDevice, + uint32_t nDelayInAClkCycles) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint16_t nCnvTime; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (nDelayInAClkCycles > (BITM_ADC_CNV_TIME_DLY >> BITP_ADC_CNV_TIME_DLY)) + { + return ADI_ADC_INVALID_PARAMETER; + } +#endif /* ADI_DEBUG */ + + nCnvTime = pDevice->pReg->CNV_TIME; + nCnvTime &= (uint16_t)(~BITM_ADC_CNV_TIME_DLY); + nCnvTime |= (uint16_t)(nDelayInAClkCycles << BITP_ADC_CNV_TIME_DLY); + pDevice->pReg->CNV_TIME = nCnvTime; + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Set the resolution of ADC. he default resolution of ADC is 12-bit and the ADC increases the resolution + * by oversampling. Averaging will be disabled when the resolution is more than 12-bits. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] eResolution Enum of ADC resolution + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully set the resolution of the ADC. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_SEQUENCE [D] Resolution cannot be changed when the ADC is enabled for sampling + * - #ADI_ADC_INVALID_STATE [D] Resolution cannot be changed from 12-bit if averaging is enabled + * - #ADI_ADC_INVALID_PARAMETER eResolution parameter passed is invalid. + */ +ADI_ADC_RESULT adi_adc_SetResolution ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_RESOLUTION eResolution) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint16_t nFactor; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + if (IS_IN_ANY_STATE(ADC_STATUS_AVGERAGING_EN) && (eResolution != ADI_ADC_RESOLUTION_12_BIT)) + { + return ADI_ADC_INVALID_STATE; + } +#endif /* ADI_DEBUG */ + + switch (eResolution) + { + case ADI_ADC_RESOLUTION_12_BIT: + pDevice->pReg->AVG_CFG &= (uint16_t)(~BITM_ADC_AVG_CFG_OS); + if (IS_NOT_IN_STATE(ADC_STATUS_AVGERAGING_EN)) { + pDevice->pReg->AVG_CFG = 0u; + } + CLR_STATE(ADC_STATUS_OVERSAMPLING_EN); + break; + + case ADI_ADC_RESOLUTION_13_BIT: + case ADI_ADC_RESOLUTION_14_BIT: + case ADI_ADC_RESOLUTION_15_BIT: + case ADI_ADC_RESOLUTION_16_BIT: + /* factor = 0x02 for 13-bit + 0x08 for 14-bit + 0x20 for 15-bit + 0x80 for 16-bit */ + nFactor = (uint16_t)1u << (((uint16_t)eResolution * 2u) - ((uint16_t)1u)); + pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN + | (uint16_t)(nFactor << BITP_ADC_AVG_CFG_FACTOR); + SET_STATE(ADC_STATUS_OVERSAMPLING_EN); + + break; + + default: + return ADI_ADC_INVALID_PARAMETER; + } + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Enable Averaging for all ADC channels. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] nAveragingSamples Specifies the number of samples used for averaging. The valid value is between 1-256, in the steps of power of 2. 1 is for disabling averaging. + * The averaging require that the resolution of ADC is 12-bit. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully enabled averaging. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_STATE [D] Averaging cannot be enabled if the resolution is above 12bits + * - #ADI_ADC_INVALID_PARAMETER [D] nAveragingSamples parameter passed is invalid. + */ +ADI_ADC_RESULT adi_adc_EnableAveraging ( + ADI_ADC_HANDLE hDevice, + uint16_t nAveragingSamples + ) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint16_t nFactor; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if ((nAveragingSamples == 0u) || (nAveragingSamples > 256u) + /* Or nAveragingSamples is not a power of 2 */ + || ((nAveragingSamples & (nAveragingSamples - 1u)) != 0u)) + { + return ADI_ADC_INVALID_PARAMETER; + } + if (IS_IN_STATE(ADC_STATUS_OVERSAMPLING_EN)) + { + return ADI_ADC_INVALID_STATE; + } +#endif /* ADI_DEBUG */ + + /* Disable averaging */ + if (nAveragingSamples == 1u) + { + pDevice->pReg->AVG_CFG &= (uint16_t)(~BITM_ADC_AVG_CFG_EN); + CLR_STATE(ADC_STATUS_AVGERAGING_EN); + } + else + { + nFactor = nAveragingSamples >> 1; + pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_EN | (uint16_t)(nFactor << BITP_ADC_AVG_CFG_FACTOR); + SET_STATE(ADC_STATUS_AVGERAGING_EN); + } + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Configure low limit for an ADC channel when it is used as a digital comparator. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] eChannel The ADC channel for which to configure the comparator + * + * @param [in] bEnable Enable or disable the low limit of the digital comparator + * + * @param [in] nLowLimit The low limit of the digital comparator. If bEnable is false, this paramter is omitted. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully configured set the low limit. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_PARAMETER [D] Parameters passed is not valid. + */ +ADI_ADC_RESULT adi_adc_SetLowLimit ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + bool bEnable, + uint16_t nLowLimit + ) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + static volatile uint16_t* pRegister[4] = { + pREG_ADC0_LIM0_LO, pREG_ADC0_LIM1_LO, pREG_ADC0_LIM2_LO, pREG_ADC0_LIM3_LO + }; + int32_t nChannelNum = 0; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if ((nLowLimit > (BITM_ADC_LIM0_LO_VALUE >> BITP_ADC_LIM0_LO_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3)) + { + return ADI_ADC_INVALID_PARAMETER; + } +#endif /* ADI_DEBUG */ + + nChannelNum = nGetChannelNumber(eChannel); + + if((nChannelNum >= 0) && (nChannelNum <= 3)) { + if (bEnable == true) { + + *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_LIM0_LO_VALUE)) | + (uint16_t)(nLowLimit << BITP_ADC_LIM0_LO_VALUE); + + /* Now enable this channel comparitor - unused until the comparitor is enabled */ + pDevice->ComparitorLo |= (1u << nChannelNum); + } + else { + pDevice->ComparitorLo &= ~(1u << nChannelNum); + } + } + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Configure high limit for an ADC channel when it's used as a digital comparator. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] eChannel The ADC channel for which to configure the comparator + * + * @param [in] bEnable Enable or disable the high limit of the digital comparator + * + * @param [in] nHighLimit The high limit of the digital comparator. If bEnable is false, this paramter is omitted. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully set the high limit + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_PARAMETER [D] Parameters passed is not valid. + */ +ADI_ADC_RESULT adi_adc_SetHighLimit ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + bool bEnable, + uint16_t nHighLimit) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + static volatile uint16_t* pRegister[4] = { + pREG_ADC0_LIM0_HI, pREG_ADC0_LIM1_HI, pREG_ADC0_LIM2_HI, pREG_ADC0_LIM3_HI + }; + int32_t nChannelNum = 0; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if ((nHighLimit > (BITM_ADC_LIM0_HI_VALUE >> BITP_ADC_LIM0_HI_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3)) + { + return ADI_ADC_INVALID_PARAMETER; + } +#endif /* ADI_DEBUG */ + + nChannelNum = nGetChannelNumber(eChannel); + + if((nChannelNum >= 0) && (nChannelNum <= 3)) { + if (bEnable == true) { + /* Set the given high value - only relevant if the limit is enabled. */ + *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_LIM0_HI_VALUE)) + | (uint16_t)(nHighLimit << BITP_ADC_LIM0_HI_VALUE); + + /* Now enable this channel comparitor - unused until the comparitor is enabled */ + pDevice->ComparitorHi |= (1u << nChannelNum); + } + else { + pDevice->ComparitorHi &= ~(1u << nChannelNum); + } + } + return ADI_ADC_SUCCESS; +} + +/** + * @brief Configure hysteresis for an ADC channel when it's used as a digital comparator. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] eChannel The ADC channel for which to configure the comparator + * + * @param [in] bEnable Enable or disable the hysteresis of the digital comparator + * + * @param [in] nHysteresis The hysteresis to be used. If bEnable is false, this paramter is omitted. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully configured the comparator + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_PARAMETER [D] Parameters passed is not valid. + */ +ADI_ADC_RESULT adi_adc_SetHysteresis ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + bool bEnable, + uint16_t nHysteresis) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + static volatile uint16_t* pRegister[4] = { + pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3 + }; + int32_t nChannelNum = 0; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if ((nHysteresis > (BITM_ADC_HYS0_VALUE >> BITP_ADC_HYS0_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3)) + { + return ADI_ADC_INVALID_PARAMETER; + } +#endif /* ADI_DEBUG */ + + nChannelNum = nGetChannelNumber(eChannel); + + if((nChannelNum >= 0) && (nChannelNum <= 3)) { + if (bEnable == true) { + *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_HYS0_VALUE)) + | (uint16_t)(nHysteresis << BITP_ADC_HYS0_VALUE); + + /* Now enable this channel hysteresis - unused until the comparitor is enabled */ + pDevice->ComparitorHys |= (1u << nChannelNum); + } + else { + pDevice->ComparitorHys &= ~(1u << nChannelNum); + } + } + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Configure number of monitor cycles for an ADC channel when it's used as a digital comparator. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] eChannel The ADC channel for which to configure the comparator + * + * @param [in] nNumMonitorCycles Number of Monitor cycles before giving interrupt + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully configured the comparator + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_PARAMETER [D] Parameters passed is not valid. + */ +ADI_ADC_RESULT adi_adc_SetNumMonitorCycles( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + uint32_t nNumMonitorCycles) +{ + #ifdef ADI_DEBUG + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; +#endif /* ADI_DEBUG */ + + static volatile uint16_t* pRegister[4] = { + pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3 + }; + int32_t nChannelNum = 0; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if ((nNumMonitorCycles > (BITM_ADC_HYS0_MONCYC >> BITP_ADC_HYS0_MONCYC)) || (nChannelNum < 0) || (nChannelNum > 3)) + { + return ADI_ADC_INVALID_PARAMETER; + } +#endif /* ADI_DEBUG */ + + nChannelNum = nGetChannelNumber(eChannel); + + if((nChannelNum >= 0) && (nChannelNum <= 3)) { + *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_HYS0_MONCYC)) + | (uint16_t)(nNumMonitorCycles << BITP_ADC_HYS0_MONCYC); + } + return ADI_ADC_SUCCESS; +} + + + +/** + * @brief Enable/Disable digital comparator for the given channel(s) + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] bEnableComparator 'true' to Enable and 'false' to disable + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully enabled/disabled digital comparator for the given channels + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_STATE [D] Digital comparator cannot be enabled if sampling resolution is more than 12-bit or + * averaging is enabled. Comparator for a given channel cannot be enbaled if none of the limits + * are enabled for the given channel. + * - #ADI_ADC_INVALID_SEQUENCE [D] Comparator cannot be enabled when ADC is enabled for sampling. + * - #ADI_ADC_INVALID_OPERATION [D] Comparator require callback to be registered. + */ +ADI_ADC_RESULT adi_adc_EnableDigitalComparator ( + ADI_ADC_HANDLE hDevice, + bool bEnableComparator +) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_AVGERAGING_EN | ADC_STATUS_OVERSAMPLING_EN)) + { + return ADI_ADC_INVALID_STATE; + } + + if (pDevice->pfCallback == NULL) { + return ADI_ADC_INVALID_OPERATION; + } + + if (bEnableComparator == true) { + if((pDevice->ComparitorHi | pDevice->ComparitorLo) == 0u) { + return ADI_ADC_INVALID_STATE; + } + } +#endif /* ADI_DEBUG */ + + EnableComparator(pDevice, bEnableComparator); + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Submit the ADC buffer for processing to the ADC Module + * + * @param [in] hDevice Handle to the device instance. + * @param [in] pBuffer Pointer to the #ADI_ADC_BUFFER structure which contains details + * of the buffers required by the driver. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully submitted the buffer + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_NULL_POINTER [D] pBuffer is NULL + * - #ADI_ADC_INVALID_BUFFER [D] Buffer parameters are invalid. + * + * @note The driver will take ownership of the ADI_ADC_BUFFER structure passed to the driver. + * The application has to make sure the structure is not used and it's scope is valid till + * the structure is returned back to the application. + */ +ADI_ADC_RESULT adi_adc_SubmitBuffer ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_BUFFER* pBuffer +) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint32_t nNumChannels = 0u; + + ADC_INT_BUFFER* pIntBuffer; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if (pBuffer == NULL) { + return ADI_ADC_NULL_POINTER; + } + if ((pBuffer->nChannels == 0u) || (pBuffer->pDataBuffer == NULL) || (pBuffer->nNumConversionPasses == 0u)) + { + return ADI_ADC_INVALID_BUFFER; + } +#endif /* ADI_DEBUG */ + + nNumChannels = GetNumChannels(pBuffer->nChannels); + + pIntBuffer = &pDevice->s_Buffer; + + pIntBuffer->nConfig = ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN; + pIntBuffer->nStatus = ADC_BUFFER_STATUS_OK; + if (pBuffer->nNumConversionPasses == 1u) + { + pIntBuffer->nConfig |= ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN; + } + pIntBuffer->pUserBuffer = pBuffer; + pIntBuffer->pCurDataBuffer = pBuffer->pDataBuffer; + pIntBuffer->nNumSamplesRemaining = nNumChannels * pBuffer->nNumConversionPasses; + pIntBuffer->nChannels = pBuffer->nChannels; + + pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INIT); + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Get a processed buffer from the ADC Driver. This function is a blocking call and will only return + * once it has the buffer or if any error occurred. If a callback is registered then any call to this + * function will fail. + * + * @param [in] hDevice Handle to the device instance. + * @param [out] ppBuffer Pointer to a pointer to ADI_ADC_BUFFER structure. The returned pointer + * to ADI_ADC_BUFFER is written here. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully returned the buffer + * - #ADI_ADC_INVALID_STATE adi_adc_GetBuffer cannot be called when no buffer is given to the driver for processing. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_OPERATION [D] adi_adc_GetBuffer cannot be used when callback is registered. + * - #ADI_ADC_NULL_POINTER [D] ppBuffer is NULL + * - #ADI_ADC_INVALID_SEQUENCE [D] adi_adc_GetBuffer cannot be used if non-blocking is not enabled. + * + */ +ADI_ADC_RESULT adi_adc_GetBuffer ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_BUFFER **ppBuffer) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + ADI_ADC_RESULT eADCresult = ADI_ADC_SUCCESS; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if (ppBuffer == NULL) { + return ADI_ADC_NULL_POINTER; + } + if (pDevice->pfCallback != NULL) { + return ADI_ADC_INVALID_OPERATION; + } + if (IS_NOT_IN_STATE(ADC_STATUS_NON_BLOCKING_EN)) { + return ADI_ADC_INVALID_SEQUENCE; + } +#endif /* ADI_DEBUG */ + + if (pDevice->s_Buffer.pUserBuffer == NULL) { + return ADI_ADC_INVALID_STATE; + } + + /* Wait for read completion */ + SEM_PEND(pDevice, ADI_ADC_ERR_RTOS); + + if ((uint16_t)(pDevice->s_Buffer.nStatus & ADC_BUFFER_STATUS_OVERFLOW) != 0u) { + eADCresult = ADI_ADC_BUFFER_OVERFLOW; + } + *ppBuffer = pDevice->s_Buffer.pUserBuffer; + pDevice->s_Buffer.pUserBuffer = NULL; + CLR_STATE(ADC_STATUS_NON_BLOCKING_EN); + + return eADCresult; +} + +/** + * @brief Enable/Disable ADC for sampling + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] bEnable 'true' to Enable and 'false' to disable + * + * @details + * + * @return Status + * - #ADI_ADC_SUCCESS Succesfully Enabled or disabled ADC for sampling + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_STATE [D] Non-blocking cannot be enabled if comparator is enabled or any blocking API is in progress. + */ +ADI_ADC_RESULT adi_adc_Enable ( + ADI_ADC_HANDLE hDevice, + bool bEnable) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) { + return ADI_ADC_INVALID_STATE; + } +#endif /* ADI_DEBUG */ + + if (bEnable == true) { + /* Set the driver to be in non-blocking mode */ + SET_STATE(ADC_STATUS_NON_BLOCKING_EN); + + /* Enable the IRQs */ + NVIC_EnableIRQ(ADC0_EVT_IRQn); + + /* Try to submit possible number of buffers */ + InitBufferProcessing(pDevice); + } else { + /* Disble the IRQs */ + NVIC_DisableIRQ(ADC0_EVT_IRQn); + + /* Abort any transaction if present */ + pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_ABORT); + + CLR_STATE(ADC_STATUS_NON_BLOCKING_EN); + } + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief This function return whether a filled buffer is available to be returned to the user. + * If this function return true, then a call to adi_adc_GetBuffer will not block + * + * @param [in] hDevice Handle to the device instance. + * @param [out] pbIsBufferAvailable Pointer to a bool variable to which the availability of buffer will be written. + * The variable will be set to 'true' if buffer is available else 'false' + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully returned the status of the buffer availability + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_NULL_POINTER [D] pbIsBufferAvailable is valid + * - #ADI_ADC_INVALID_OPERATION [D] adi_adc_IsBufferAvailable cannot be used when callback is registered. + * + */ +ADI_ADC_RESULT adi_adc_IsBufferAvailable ( + ADI_ADC_HANDLE hDevice, + bool *pbIsBufferAvailable) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if (pbIsBufferAvailable == NULL) + { + return ADI_ADC_NULL_POINTER; + } + if (pDevice->pfCallback != NULL) { + return ADI_ADC_INVALID_OPERATION; + } +#endif /* ADI_DEBUG */ + + if(IS_IN_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS)) + { + *pbIsBufferAvailable = false; + } + else + { + *pbIsBufferAvailable = true; + } + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief Sample the given channels for the given number of conversion passes and put it into the given buffer. This function only return after + * the channels are sampled the given number of conversion times or if any error occurs. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] nChannels Channels to sample. Should be an ORed value of ADI_ADC_CHANNEL types. + * + * @param [in] nNumConversionPasses Number of conversion passes. In one conversion pass, the ADC will sample all the given channel(s) once. + * + * @param [in] pBuffer Pointer to the buffer to which the sampled data is put. + * + * @param [in] nBuffLength Length of the buffer. The length of the buffer should be at least + * 2*(Num of Channels)*nNumConversionPasses bytes. + * + * @details Sample all the given channels for the given number of conversion passes and put the samples values into the given buffers. + * The channels will be sampled starting from the lower number. This function only return after + * the channels are sampled the given number of conversion times or if any error occurs. + * + * @return Status + * - #ADI_ADC_SUCCESS Succesfully Enabled or disabled ADC for sampling + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_PARAMETER [D] Some parameter passed to the function is not valid + * - #ADI_ADC_INVALID_SEQUENCE [D] adi_adc_ReadChannels cannot be called if camparator is enabled or if + * Non-blocking is enabled or if another blocking API is in progress. + */ + +ADI_ADC_RESULT adi_adc_ReadChannels ( + ADI_ADC_HANDLE hDevice, + uint32_t nChannels, + uint32_t nNumConversionPasses, + void *pBuffer, + uint32_t nBuffLength) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint32_t nNumChannels = 0u; + ADI_ADC_RESULT eADCresult = ADI_ADC_SUCCESS; + + ADC_INT_BUFFER* pIntBuffer; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if ((nChannels == 0u) || (nNumConversionPasses == 0u) || (pBuffer == NULL)) + { + return ADI_ADC_INVALID_PARAMETER; + } + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } +#endif /* ADI_DEBUG */ + + nNumChannels = GetNumChannels(nChannels); + + if (nBuffLength < ((nNumChannels * sizeof(uint16_t)) * nNumConversionPasses)) + { + return ADI_ADC_INSUFFICIENT_MEMORY; + } + + /* Clear ADC status */ + pDevice->pReg->STAT = 0xFFFFu; + + /* Set the driver to be in blocking mode */ + SET_STATE(ADC_STATUS_BLOCKING_EN); + + /* Get the buffer */ + pIntBuffer = &pDevice->s_Buffer; + + pIntBuffer->nConfig = ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN; + if (nNumConversionPasses == 1u) { + pIntBuffer->nConfig |= ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN; + } + + pIntBuffer->nStatus = ADC_BUFFER_STATUS_OK; + pIntBuffer->pUserBuffer = NULL; + pIntBuffer->pCurDataBuffer = pBuffer; + pIntBuffer->nNumSamplesRemaining = nNumChannels * nNumConversionPasses; + pIntBuffer->nChannels = nChannels; + + pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INIT); + + InitBufferProcessing(pDevice); + + /* Wait for read completion */ + SEM_PEND(pDevice, ADI_ADC_ERR_RTOS); + + if ((uint16_t)(pDevice->s_Buffer.nStatus & ADC_BUFFER_STATUS_OVERFLOW) != 0u) { + eADCresult = ADI_ADC_BUFFER_OVERFLOW; + } + + /* Driver is no longer in blocking mode */ + CLR_STATE(ADC_STATUS_BLOCKING_EN); + + /* Enable the IRQs */ + NVIC_DisableIRQ(ADC0_EVT_IRQn); + + return eADCresult; +} + + +/** + * @brief Returns the battery voltage. + * + * @param [in] hDevice Handle to the device instance. + * + * @param [in] nRefVoltage Reference voltage in fixed point(16.16) format. + * + * @param [out] pnBatVoltage Pointer to a variable to which the voltage of the battery will be written. + * The battery voltage will be in fixed point (16.16) format. + * + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully retrieved the battery voltage. + * - #ADI_ADC_BAD_SYS_CLOCK Unable to obtain CLK which is needed to calculate + * voltage conversion timing values. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_NULL_POINTER [D] pnBatVoltage is NULL + * - #ADI_ADC_INVALID_SEQUENCE [D] ADC sub system should be up and ADC should be free for getting the battery voltage. + */ +ADI_ADC_RESULT adi_adc_GetBatteryVoltage ( + ADI_ADC_HANDLE hDevice, + uint32_t nRefVoltage, + uint32_t *pnBatVoltage) +{ + ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS; + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint16_t nConvTimeBackup; + uint16_t nAvgCfgBackup; + uint32_t nAdcValue = 0u; + uint32_t nClock = 0u; + uint32_t nACLKDIVCNT; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if (pnBatVoltage == NULL) + { + return ADI_ADC_NULL_POINTER; + } + + if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) { + return ADI_ADC_INVALID_SEQUENCE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) { + return ADI_ADC_INVALID_SEQUENCE; + } +#endif /* ADI_DEBUG */ + + if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &nClock) == ADI_PWR_SUCCESS) + { + /* Take the backup of registers that need to be changed */ + nConvTimeBackup = pDevice->pReg->CNV_TIME; + nAvgCfgBackup = pDevice->pReg->AVG_CFG; + + /* Set the required value in the registers. */ + nACLKDIVCNT = (*pREG_CLKG0_CLK_CTL1 & BITM_CLKG_CLK_CTL1_ACLKDIVCNT) >> BITP_CLKG_CLK_CTL1_ACLKDIVCNT; + + /* Calculate the number of cycles required for conversion. + * The conversion time required is 500ns = 2000000Hz + */ + nClock = nClock/nACLKDIVCNT; /* nClock = ACLK frequency Hz */ + pDevice->pReg->CNV_TIME = (uint16_t)((nClock/2000000u) + ((uint16_t)1u)); + pDevice->pReg->AVG_CFG = 0u; + + /* Clear the battery done status */ + pDevice->pReg->STAT = BITM_ADC_STAT_BATDONE; + + /* Clear the battery done state */ + CLR_STATE(ADC_STATUS_BATTERY_DONE); + + /* Set the registers */ + pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_BAT); + + /* Wait for the Battery done status */ + while (IS_NOT_IN_STATE(ADC_STATUS_BATTERY_DONE)) { ; } + + /* Clear the conversion register */ + pDevice->pReg->CNV_CFG = 0u; + + /* Restore the changed registers */ + pDevice->pReg->CNV_TIME = nConvTimeBackup; + pDevice->pReg->AVG_CFG = nAvgCfgBackup; + + /* Calculate the battery voltage */ + + /* From HRM: converting ADC result to battery voltage, following calculations should be done: + * VBAT = 4 * (adc_out) * Vref / (2^12 - 1) */ + nAdcValue = pDevice->pReg->BAT_OUT; + *pnBatVoltage = (4u * nAdcValue * nRefVoltage) / ADI_ADC_SAMPLE_MAX; + } + else + { + eResult = ADI_ADC_BAD_SYS_CLOCK; + } + + return eResult; +} +/** + * @brief Enable or disable the temperature sensor + * + * @param [in] hDevice Handle to the device instance. + * + * @param [in] bEnable 'true' to enable and 'false' to disable the temperature sensor + * + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully enabled/disabled the temperature sensor + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + */ +ADI_ADC_RESULT adi_adc_EnableTemperatureSensor ( + ADI_ADC_HANDLE hDevice, + bool bEnable) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } +#endif /* ADI_DEBUG */ + + if (bEnable == true) + { + pDevice->pReg->CFG |= (uint16_t)BITM_ADC_CFG_TMPEN; + SET_STATE(ADC_STATUS_TEMP_SENSOR_EN); + } + else + { + pDevice->pReg->CFG &= (uint16_t)(~BITM_ADC_CFG_TMPEN); + CLR_STATE(ADC_STATUS_TEMP_SENSOR_EN); + } + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief Return the temperature in fixed point format in degree Celcius. + * + * @param [in] hDevice Handle to the device instance. + * + * @param [in] nRefVoltage Reference voltage in fixed point(16.16) format. + * + * @param [out] pnTemperature Pointer to a variable to which the ADC die temperature (in degree Celsius) will be written. + * The temperature will be in fixed point (16.16) format. + * + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully retrieved the die temperature + * - #ADI_ADC_BAD_SYS_CLOCK Unable to obtain CLK which is needed to calculate + * temperature conversion timing values. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_NULL_POINTER [D] pnBatVoltage is NULL + * - #ADI_ADC_INVALID_SEQUENCE [D] ADC sub system should be up and ADC should be free for getting the battery voltage. The Temperator + * sensor also need to be enabled. + * - #ADI_ADC_INVALID_STATE [D] Temperature sensor require an aquisition time of 65us and that cannot be set with the current + * ACLK since only ACLK of 255 can be stored to the sampling register. Decrease the ACLK clock to + * rectify this. + */ +ADI_ADC_RESULT adi_adc_GetTemperature ( + ADI_ADC_HANDLE hDevice, + uint32_t nRefVoltage, + int32_t* pnTemperature + ) +{ + ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS; + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint16_t nConvTimeBackup; + uint16_t nAvgCfgBackup; + uint32_t nAdcTmpValue = 0u; + uint32_t nAdcTmp2Value = 0u; + uint32_t nClock = 0u; + uint32_t nACLKDIVCNT; + uint32_t nCnvTime; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if (pnTemperature == NULL) + { + return ADI_ADC_NULL_POINTER; + } + + if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN | ADC_STATUS_TEMP_SENSOR_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } +#endif + + + if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &nClock) == ADI_PWR_SUCCESS) + { + /* Calculate the conversion time */ + nACLKDIVCNT = (*pREG_CLKG0_CLK_CTL1 & BITM_CLKG_CLK_CTL1_ACLKDIVCNT) >> BITP_CLKG_CLK_CTL1_ACLKDIVCNT; + nCnvTime = ((nClock / nACLKDIVCNT) / (uint16_t)15385u) + 1u; /* 65us acquisition time required = 15385Hz sample */ + + #ifdef ADI_DEBUG + if (nCnvTime >= 256u) { + return ADI_ADC_INVALID_STATE; + } + #endif + /* Take the backup of registers that need to be changed */ + nConvTimeBackup = pDevice->pReg->CNV_TIME; + nAvgCfgBackup = pDevice->pReg->AVG_CFG; + + /* Set the required value in the registers. */ + + pDevice->pReg->CNV_TIME = (uint16_t)((nCnvTime << BITP_ADC_CNV_TIME_SAMPTIME) & BITM_ADC_CNV_TIME_SAMPTIME); + pDevice->pReg->AVG_CFG = 0u; + + /* Clear the temperature done status */ + pDevice->pReg->STAT = BITM_ADC_STAT_TMPDONE | BITM_ADC_STAT_TMP2DONE; + + /* Clear the temperature done state */ + CLR_STATE(ADC_STATUS_TMP_DONE | ADC_STATUS_TMP2_DONE); + + /* Sample Tmp register */ + pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_TMP); + while (IS_NOT_IN_STATE(ADC_STATUS_TMP_DONE)) { ; } + nAdcTmpValue = pDevice->pReg->TMP_OUT; + pDevice->pReg->CNV_CFG = 0u; + + + /* Sample Tmp2 register */ + pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_TMP2); + while (IS_NOT_IN_STATE(ADC_STATUS_TMP2_DONE)) { ; } + pDevice->pReg->CNV_CFG = 0u; + nAdcTmp2Value = pDevice->pReg->TMP2_OUT; + + /* Restore the changed registers */ + pDevice->pReg->CNV_TIME = nConvTimeBackup; + pDevice->pReg->AVG_CFG = nAvgCfgBackup; + + /* Calculate the temperature voltage. + * From the HRM: Temperature can be calculated as: + * + * T(^0 C)= code1/(code2+RG*code1)*Rvirtualreference/(ideal_sensitivity )-273.15 + * + * Some of these values are constants, and some have been read from registers. + * The above formula, when populated with variables and constants, would look like this: + * T(^0 C)= (nAdcTmpValue/(nAdcTmp2Value + nTempRG * nAdcTmpValue)) * (1.2256/1.2411e-3)) -273.15 + */ + { + uint32_t nRVirRefByIdealSensitivity = 2070960834u; /* 1.2256/1.2411e-3 in 11.21 format */ + + uint32_t nTempRG = 19380u; /* 1.1829 in 2.14 format */ + uint32_t nTmp2 = ((nAdcTmp2Value << 14u) + (nTempRG * nAdcTmpValue)); /* in 14.14 format */ + + uint32_t nOffsetPart = (335544320u/nRefVoltage); /* (1.25 in 4.28 format / ReferenceVoltage(16.16)) = Result in format *.12 */ + uint32_t nOffset = (161u * nOffsetPart); /* 12.12 format */ + + uint32_t nTmp3 = ((nAdcTmpValue << 12) - nOffset) << 8u; /* Format 12.20 */ + uint32_t nRatio = (nTmp3/(nTmp2 >> 10u)); /* nTmp2 resolution reduced by 10 to 14.4 and the result resolution is 0.16 */ + uint32_t nTemp = (nRatio * (nRVirRefByIdealSensitivity >> 16u)) >> 5u; /* Temperature in degree kelvin in 16.16 format */ + + int32_t iTemp = (int32_t)nTemp - ((int32_t)17901158); /* Subtract 273.15 (in 16.16) to get the temperature in degree celcius */ + *pnTemperature = iTemp; + } + } + else + { + eResult = ADI_ADC_BAD_SYS_CLOCK; + } + + return eResult; +} + + +/*! \cond PRIVATE */ + +/*========== S T A T I C F U N C T I O N S ==========*/ +/* Read the output register for the given channel number */ +static uint16_t ReadOutReg(uint32_t nChannelNum) +{ + const volatile uint16_t* pOutRegister = pREG_ADC0_CH0_OUT; + pOutRegister += nChannelNum*2u; + return *pOutRegister; +} + +/* Init buffer processing */ +static bool InitBufferProcessing(ADI_ADC_DEVICE *pDevice) +{ + uint32_t nCnvReg = ((uint32_t)(pDevice->pReg->CNV_CFG) & BITM_ADC_CNV_CFG_DMAEN); + ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer; + + if (IS_NOT_IN_ANY_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS)) + { + /* Clear conversion done flags */ + pDevice->pReg->STAT = 0xFFFFu; + + /* Clear the overflow and alert register */ + pDevice->pReg->OVF = 0xFFFFu; + } + + /* Calculate the conversion register value for the given configuration */ + nCnvReg |= pIntBuffer->nChannels; + if ((uint16_t)(pIntBuffer->nConfig & ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN) != 0u) { + nCnvReg |= BITM_ADC_CNV_CFG_AUTOMODE; + } + if ((pIntBuffer->nConfig & ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN) != 0u) { + nCnvReg |= BITM_ADC_CNV_CFG_SINGLE; + } else { + nCnvReg |= BITM_ADC_CNV_CFG_MULTI; + } + + SET_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS); + + pDevice->pReg->CNV_CFG |= (uint16_t)nCnvReg; + + pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_ENABLED); + + return true; +} + + +#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 +/* DMA Callback Handler */ +void DMA_ADC0_Int_Handler (void) +{ + ISR_PROLOG(); + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *) AdcDevInfo[0].hDevice; + + DmaFIFOManage(pDevice, ADC_FIFO_MODE_DMA_BUFFER_PROCESS); + + ISR_EPILOG(); +} + +static ADI_ADC_RESULT DmaFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode) +{ + uint16_t nCount = 0u; + uint16_t chanNum = ADC0_CHANn; + uint16_t IRQ_Backup; + + ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer; + + if(pDevice->s_Buffer.pCurDataBuffer == NULL) { + /* If there is nothing active... */ + if (eFifoMode == ADC_FIFO_MODE_INTERRUPT_PROCESS) { + /* ...it's something leftover, so cleanup. */ + uint16_t nStat = pDevice->pReg->STAT & 0x00FFu; + FlushFifo(pDevice, (uint32_t)nStat); + pDevice->pReg->STAT = nStat; + } + } + else { + switch (eFifoMode) + { + case ADC_FIFO_MODE_INIT: + + /* Enable the interrupt for the given DMA */ + NVIC_EnableIRQ(DMA0_CH24_DONE_IRQn); + + pADI_DMA0->SRCADDR_CLR = 1U << chanNum; + + /* Enable the channel */ + pADI_DMA0->EN_SET = 1U << chanNum; + + /* Enables peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1U << chanNum; + + /* Set the primary as the current DMA descriptor */ + pADI_DMA0->ALT_CLR = 1U << chanNum; /* Should be default */ + + /* Setup the DMA registers */ + nCount = (uint16_t)pIntBuffer->nNumSamplesRemaining; + + /* Point to the end of the DMA source */ + pPrimaryCCD[chanNum].DMASRCEND = (uint32_t)(&(pDevice->pReg->DMA_OUT)); + + /* Point to the end of the DMA write-to destination */ + pPrimaryCCD[chanNum].DMADSTEND = (uint32_t)((void*)pIntBuffer->pCurDataBuffer) + ((nCount * 2u) - 1u); + + /* Configure the DMA itself */ + pPrimaryCCD[chanNum].DMACDC = ((ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_DST_INC) | /* Increment destination address */ + (ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) | /* Don't increment the source address */ + ((uint32_t)ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) | /* 16bit transfers */ + ((nCount - (uint32_t)1U)<< DMA_BITP_CTL_N_MINUS_1) | /* Data size? */ + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) | /* Basic only */ + ((uint32_t)ADI_DMA_RPOWER_1 << DMA_BITP_CTL_R_POWER)); /* Arbitration */ + + /* Enable DMA */ + pDevice->pReg->CNV_CFG |= BITM_ADC_CNV_CFG_DMAEN; + break; + + case ADC_FIFO_MODE_ENABLED: + break; + + case ADC_FIFO_MODE_INTERRUPT_PROCESS: + /* Clear the status registers */ + pDevice->pReg->STAT = (pDevice->pReg->STAT & 0x00FFu); + break; + + case ADC_FIFO_MODE_INTERRUPT_OVERFLOW: + pIntBuffer->nStatus |= ADC_BUFFER_STATUS_OVERFLOW; + break; + + case ADC_FIFO_MODE_DMA_BUFFER_PROCESS: + pIntBuffer->nNumSamplesRemaining = 0u; + ManageFifoCompletion(pDevice); + break; + + case ADC_FIFO_MODE_ABORT: + + /* Take backup of IRQ */ + IRQ_Backup = pDevice->pReg->IRQ_EN; + + /* Disable the IRQ */ + pDevice->pReg->IRQ_EN = 0u; + + /* Clear the conversion cfg register to stop any transaction */ + pDevice->pReg->CNV_CFG = 0u; + + /* Disable the DMA channel */ + pADI_DMA0->EN_CLR = 1U << chanNum; + + /* Clear the status bits */ + pDevice->pReg->STAT = pDevice->pReg->STAT; + + /* Clear the sampling in progress state */ + CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS); + + /* Read and flush all the buffers */ + FlushFifo(pDevice, 0x00FFu); + + /* Restore the IRQ */ + pDevice->pReg->IRQ_EN = IRQ_Backup; + + break; + + default: + break; + } + } + + return ADI_ADC_SUCCESS; +} +#else /* else ADI_ADC_ENABLE_MULTI_ACQUIRE == 0 */ + +static ADI_ADC_RESULT InterruptFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode) +{ + ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer; + + if(pDevice->s_Buffer.pCurDataBuffer == NULL) { + if (eFifoMode == ADC_FIFO_MODE_INTERRUPT_PROCESS) { + uint16_t nStat = pDevice->pReg->STAT & 0x00FFu; + FlushFifo(pDevice, (uint32_t)nStat); + pDevice->pReg->STAT = nStat; + } + return ADI_ADC_SUCCESS; + } + + switch (eFifoMode) + { + case ADC_FIFO_MODE_INIT: + { + /* Enable the conversion done and overflow interrupt */ + pDevice->ActData.nCurChannel = 0u; + } + break; + + case ADC_FIFO_MODE_ENABLED: + break; + + case ADC_FIFO_MODE_INTERRUPT_PROCESS: + { + while (pIntBuffer->nNumSamplesRemaining > 0u) { + uint32_t nConvStatus = ((uint32_t)pDevice->pReg->STAT & (uint32_t)0x00FFu); + if ((nConvStatus & 0x00FFu) == 0u) + { + break; + } + + uint32_t nCurChannelBitM = ((uint32_t)1u << pDevice->ActData.nCurChannel); + while ((nCurChannelBitM & nConvStatus) == 0u) { + pDevice->ActData.nCurChannel++; + if (pDevice->ActData.nCurChannel >= NUM_ADC_CHANNELS) { + pDevice->ActData.nCurChannel = 0u; + } + nCurChannelBitM = ((uint32_t)1u << pDevice->ActData.nCurChannel); + } + + assert ((pIntBuffer->nChannels & ((uint32_t)1u << pDevice->ActData.nCurChannel)) != 0u); + + *pIntBuffer->pCurDataBuffer = ReadOutReg( pDevice->ActData.nCurChannel); + pIntBuffer->pCurDataBuffer++; + + + pDevice->pReg->STAT = (uint16_t)nCurChannelBitM; + pIntBuffer->nNumSamplesRemaining -= 1u; + + pDevice->ActData.nCurChannel += 1u; + if ( pDevice->ActData.nCurChannel >= NUM_ADC_CHANNELS) { + pDevice->ActData.nCurChannel = 0u; + } + } + + if (pIntBuffer->nNumSamplesRemaining == 0u) { + ManageFifoCompletion(pDevice); + } + } + break; + + case ADC_FIFO_MODE_INTERRUPT_OVERFLOW: + { + pIntBuffer->nStatus |= ADC_BUFFER_STATUS_OVERFLOW; + } + break; + + case ADC_FIFO_MODE_ABORT: + { + uint16_t IRQ_Backup; + + /* Take backup of IRQ */ + IRQ_Backup = pDevice->pReg->IRQ_EN; + + /* Disable the IRQ */ + pDevice->pReg->IRQ_EN = 0u; + + /* Clear the conversion cfg register to stop any transaction */ + pDevice->pReg->CNV_CFG = 0u; + + /* Clear the status bits */ + pDevice->pReg->STAT = pDevice->pReg->STAT; + + /* Clear the sampling in progress state */ + CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS); + + /* Read and flush all the buffers */ + FlushFifo(pDevice, 0x00FFu); + + /* Restore the IRQ */ + pDevice->pReg->IRQ_EN = IRQ_Backup; + } + break; + + default: + break; + } + + return ADI_ADC_SUCCESS; +} +#endif + +static void FlushFifo(ADI_ADC_DEVICE *pDevice, uint32_t nChannels) +{ + uint32_t x; + for (x = 0u; x < 8u; x++) { + if ((nChannels & ((uint32_t)1u << x)) != 0u) { + ReadOutReg(x); + } + } +} + + +/* Called when a transfer is complete */ +static void ManageFifoCompletion(ADI_ADC_DEVICE *pDevice) +{ + /* Clear the conversion configuration */ + pDevice->pReg->CNV_CFG = 0u; + CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS); + + SEM_POST(pDevice); +} + + +/* Internal function to extract the number of channels + * in a 32bit word. */ +static uint32_t GetNumChannels(uint32_t nChannels) +{ + uint32_t n = nChannels & 0x000000FFu; + + n = (n & 0x00000055u) + ((n >> 1u) & 0x00000055u); + n = (n & 0x00000033u) + ((n >> 2u) & 0x00000033u); + n = (n + (n >> 4u)) & (0x0000000Fu); + + return n; +} + +/* Returns the channel number based on the ADI_ADC_CHANNEL type. + * i.e. ADI_ADC_CHANNEL1 returns 1. */ +static int32_t nGetChannelNumber(ADI_ADC_CHANNEL eChannel) +{ + int32_t retVal = 0; + uint32_t nChannel = (uint32_t)eChannel & 0x000000FFu; + + if ((nChannel & (nChannel - (uint32_t)1u)) != 0u) { + return -1; + } + if ((nChannel & 0x000000AAu) != 0u) { retVal += 1; } + if ((nChannel & 0x000000CCu) != 0u) { retVal += 2; } + if ((nChannel & 0x000000F0u) != 0u) { retVal += 4; } + + return retVal; +} + +/* Internal function to set static configuration options. */ +static void StaticConfiguration(ADI_ADC_DEVICE *pDevice) +{ + uint16_t nCfgReg = 0u; + + /* Configure the resolution */ +#if ADI_ADC_CFG_RESOLUTION == 12 + pDevice->pReg->AVG_CFG = 0u; +#else + +#if ADI_ADC_CFG_RESOLUTION == 13 + pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0002u << BITP_ADC_AVG_CFG_FACTOR); +#elif ADI_ADC_CFG_RESOLUTION == 14 + pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0008u << BITP_ADC_AVG_CFG_FACTOR); +#elif ADI_ADC_CFG_RESOLUTION == 15 + pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0020u << BITP_ADC_AVG_CFG_FACTOR); +#elif ADI_ADC_CFG_RESOLUTION == 16 + pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0080u << BITP_ADC_AVG_CFG_FACTOR); +#else +#error "Invalid Resolution" +#endif + + SET_STATE(ADC_STATUS_OVERSAMPLING_EN); +#endif + + /* Configure the VREF */ +#if ADI_ADC_CFG_VREF == 0 /* 1.25V Internal Reference*/ + nCfgReg |= BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL; +#elif ADI_ADC_CFG_VREF == 1 /* 2.5V Internal Reference */ + nCfgReg |= BITM_ADC_CFG_REFBUFEN; +#elif ADI_ADC_CFG_VREF == 2 /* Battery Voltage */ + nCfgReg |= BITM_ADC_CFG_VREFVBAT; +#endif + + pDevice->pReg->CFG = nCfgReg; + +#if ADI_ADC_ENABLE_STATIC_COMPARATOR == 1 + /* High limit registers */ +#if ADI_ADC_COMPARATOR_AIN0_HI_EN == 1 + pDevice->pReg->LIM0_HI = ADI_ADC_COMPARATOR_AIN0_HI_VAL; + pDevice->ComparitorHi |= ADI_ADC_CHANNEL_0; +#endif +#if ADI_ADC_COMPARATOR_AIN1_HI_EN == 1 + pDevice->pReg->LIM1_HI = ADI_ADC_COMPARATOR_AIN1_HI_VAL; + pDevice->ComparitorHi |= ADI_ADC_CHANNEL_1; +#endif +#if ADI_ADC_COMPARATOR_AIN2_HI_EN == 1 + pDevice->pReg->LIM2_HI = ADI_ADC_COMPARATOR_AIN2_HI_VAL; + pDevice->ComparitorHi |= ADI_ADC_CHANNEL_2; +#endif +#if ADI_ADC_COMPARATOR_AIN3_HI_EN == 1 + pDevice->pReg->LIM3_HI = ADI_ADC_COMPARATOR_AIN3_HI_VAL; + pDevice->ComparitorHi |= ADI_ADC_CHANNEL_3; +#endif + /* Low limit registers */ +#if ADI_ADC_COMPARATOR_AIN0_LO_EN == 1 + pDevice->pReg->LIM0_LO = (uint16_t)ADI_ADC_COMPARATOR_AIN0_LO_VAL; + pDevice->ComparitorLo |= ADI_ADC_CHANNEL_0; +#endif +#if ADI_ADC_COMPARATOR_AIN1_LO_EN == 1 + pDevice->pReg->LIM1_LO = ADI_ADC_COMPARATOR_AIN1_LO_VAL; + pDevice->ComparitorLo |= ADI_ADC_CHANNEL_1; +#endif +#if ADI_ADC_COMPARATOR_AIN2_LO_EN == 1 + pDevice->pReg->LIM2_LO = ADI_ADC_COMPARATOR_AIN2_LO_VAL; + pDevice->ComparitorLo |= ADI_ADC_CHANNEL_2; +#endif +#if ADI_ADC_COMPARATOR_AIN3_LO_EN == 1 + pDevice->pReg->LIM3_LO = ADI_ADC_COMPARATOR_AIN3_LO_VAL; + pDevice->ComparitorLo |= ADI_ADC_CHANNEL_3; +#endif + + /* Hysteresis registers */ +#if ADI_ADC_COMPARATOR_AIN0_HYS_EN == 1 + pDevice->pReg->HYS0 = (uint16_t)(ADI_ADC_COMPARATOR_AIN0_HYS_VAL | (ADI_ADC_COMPARATOR_AIN0_HYS_CYC << BITP_ADC_HYS0_MONCYC)); + pDevice->ComparitorHys |= ADI_ADC_CHANNEL_0; +#endif +#if ADI_ADC_COMPARATOR_AIN1_HYS_EN == 1 + pDevice->pReg->HYS1 = (ADI_ADC_COMPARATOR_AIN1_HYS_VAL | (ADI_ADC_COMPARATOR_AIN1_HYS_CYC << BITP_ADC_HYS0_MONCYC)); + pDevice->ComparitorHys |= ADI_ADC_CHANNEL_1; +#endif +#if ADI_ADC_COMPARATOR_AIN2_HYS_EN == 1 + pDevice->pReg->HYS2 = (ADI_ADC_COMPARATOR_AIN2_HYS_VAL | (ADI_ADC_COMPARATOR_AIN2_HYS_CYC << BITP_ADC_HYS0_MONCYC)); + pDevice->ComparitorHys |= ADI_ADC_CHANNEL_2; +#endif +#if ADI_ADC_COMPARATOR_AIN3_HYS_EN == 1 + pDevice->pReg->HYS3 = (ADI_ADC_COMPARATOR_AIN3_HYS_VAL | (ADI_ADC_COMPARATOR_AIN3_HYS_CYC << BITP_ADC_HYS0_MONCYC)); + pDevice->ComparitorHys |= ADI_ADC_CHANNEL_3; +#endif +#endif + +} + +/* Internal function to enable the comparitor for previously-configured channels + * Does not set the limits, only enables. +*/ +static void EnableComparator(ADI_ADC_DEVICE *pDevice, bool bEnable) +{ + uint32_t x; + uint16_t nCnvCfg = 0u; + volatile uint16_t* pLO_Register[4] = {pREG_ADC0_LIM0_LO, pREG_ADC0_LIM1_LO, pREG_ADC0_LIM2_LO, pREG_ADC0_LIM3_LO}; + volatile uint16_t* pHI_Register[4] = {pREG_ADC0_LIM0_HI, pREG_ADC0_LIM1_HI, pREG_ADC0_LIM2_HI, pREG_ADC0_LIM3_HI}; + volatile uint16_t* pHYS_Register[4] = {pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3}; + + if (bEnable == true) + { + /* Loop round all the channels enabling each part if required. */ + for (x = 0u; x < NUM_ADC_COMPARATOR_CHANNELS; x++) { + if((pDevice->ComparitorHi & (1u << x)) > 0u) { + *pHI_Register[x] |= BITM_ADC_LIM0_HI_EN; + } + if((pDevice->ComparitorLo & (1u << x)) > 0u) { + *pLO_Register[x] |= BITM_ADC_LIM0_LO_EN; + } + if((pDevice->ComparitorHys & (1u << x)) > 0u) { + *pHYS_Register[x] |= BITM_ADC_HYS0_EN; + } + } + nCnvCfg = (uint16_t)((uint16_t)pDevice->ComparitorHi | (uint16_t)pDevice->ComparitorLo); + + pDevice->pReg->IRQ_EN &= (uint16_t)(~BITM_ADC_IRQ_EN_CNVDONE); + pDevice->pReg->CNV_CFG = (uint16_t)nCnvCfg | (uint16_t)(BITM_ADC_CNV_CFG_MULTI | BITM_ADC_CNV_CFG_AUTOMODE); + SET_STATE(ADC_STATUS_COMPARATOR_EN); + } + else { + /* Loop round disabling all. */ + for (x = 0u; x < NUM_ADC_COMPARATOR_CHANNELS; x++) { + *pHI_Register[x] &= (uint16_t)(~(BITM_ADC_LIM0_HI_EN)); + *pLO_Register[x] &= (uint16_t)(~(BITM_ADC_LIM0_LO_EN)); + *pHYS_Register[x] &= (uint16_t)(~(BITM_ADC_HYS0_EN)); + } + pDevice->pReg->CNV_CFG = 0u; + pDevice->pReg->STAT = pDevice->pReg->STAT & 0x00FFu; + CLR_STATE(ADC_STATUS_COMPARATOR_EN); + pDevice->pReg->IRQ_EN |= BITM_ADC_IRQ_EN_CNVDONE; + } +} + + +/* In Handler handles the following cases: + * ADI_ADC_EVENT_ADC_READY + * ADI_ADC_EVENT_CALIBRATION_DONE + * ADC_STATUS_BATTERY_DONE + * ADC_STATUS_TMP_DONE + * ADC_STATUS_TMP2_DONE + * ADI_ADC_EVENT_HIGH_LIMIT_CROSSED + * ADI_ADC_EVENT_LOW_LIMIT_CROSSED +*/ +void ADC0_Int_Handler(void) +{ + ADI_ADC_DEVICE *pDevice; + ISR_PROLOG(); + + pDevice = (ADI_ADC_DEVICE *) AdcDevInfo[0].hDevice; + + if ((pDevice->pReg->STAT & 0x00FFu) != 0u) { + if (IS_NOT_IN_STATE(ADC_STATUS_COMPARATOR_EN)) { + pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INTERRUPT_PROCESS); + } else { + pDevice->pReg->STAT = pDevice->pReg->STAT & (0x00FFu); + } + } + if ((uint16_t)(pDevice->pReg->STAT & 0xFF00u) != 0u) { + if ((pDevice->pReg->STAT & BITM_ADC_STAT_RDY) != 0u) { + SET_STATE(ADC_STATUS_SUB_SYSTEM_READY); + pDevice->pReg->STAT = BITM_ADC_STAT_RDY; + if (pDevice->pfCallback != NULL) { + pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_ADC_READY, NULL); + } + } + if ((pDevice->pReg->STAT & BITM_ADC_STAT_CALDONE) != 0u) { + SET_STATE(ADC_STATUS_CALIBRATION_DONE); + pDevice->pReg->STAT = BITM_ADC_STAT_CALDONE; + if (pDevice->pfCallback != NULL) { + pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_CALIBRATION_DONE, NULL); + } + } + if ((pDevice->pReg->STAT & BITM_ADC_STAT_BATDONE) != 0u) { + SET_STATE(ADC_STATUS_BATTERY_DONE); + pDevice->pReg->STAT = BITM_ADC_STAT_BATDONE; + } + + if ((pDevice->pReg->STAT & BITM_ADC_STAT_TMPDONE) != 0u) { + SET_STATE(ADC_STATUS_TMP_DONE); + pDevice->pReg->STAT = BITM_ADC_STAT_TMPDONE; + } + + if ((pDevice->pReg->STAT & BITM_ADC_STAT_TMP2DONE) != 0u) { + SET_STATE(ADC_STATUS_TMP2_DONE); + pDevice->pReg->STAT = BITM_ADC_STAT_TMP2DONE; + } + } + if (pDevice->pReg->OVF) { + uint16_t nOvrFlowValue = pDevice->pReg->OVF; + if (IS_NOT_IN_STATE(ADC_STATUS_COMPARATOR_EN)) { + pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INTERRUPT_OVERFLOW); + } + pDevice->pReg->OVF = nOvrFlowValue; + } + if (pDevice->pReg->ALERT) { + uint32_t nAlertValue = pDevice->pReg->ALERT; + uint32_t channel; + if (IS_IN_STATE(ADC_STATUS_COMPARATOR_EN) && (pDevice->pfCallback != NULL)) { + for (channel = 0u; channel < (NUM_ADC_COMPARATOR_CHANNELS); channel++) { + /* Alert bit positions: hi limits are 0b01, + * lo limit alerts are 0b10. + */ + if((nAlertValue & (1u << (2u * channel))) > 0u) { + pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_HIGH_LIMIT_CROSSED, (void*)channel); + } + if((nAlertValue & (1u << ((2u * channel) + ((uint32_t)1u)))) > 0u) + { + pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_LOW_LIMIT_CROSSED, (void*)channel); + } + } + } + pDevice->pReg->ALERT = (uint16_t)nAlertValue; + } + ISR_EPILOG(); +} + + +/*! \endcond */ + +#endif /* ADI_ADC_C */ + +/*****/ + +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_data.c new file mode 100755 index 0000000000..9ebc296297 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_data.c @@ -0,0 +1,19 @@ +#ifndef ADI_ADC_DATA_C +#define ADI_ADC_DATA_C + +#include +#include +#include "adi_adc_def.h" + +/*! \cond PRIVATE */ + +static ADI_ADC_INFO AdcDevInfo[] = { + { + NULL, + (ADI_ADC_TypeDef*)REG_ADC0_CFG + } +}; + +/*! \endcond */ + +#endif /* ADI_ADC_DATA_C */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_def.h new file mode 100755 index 0000000000..6568f6f277 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_def.h @@ -0,0 +1,120 @@ +/*! \cond PRIVATE */ + +#ifndef ADI_ADC_DEF +#define ADI_ADC_DEF + +#include +#include + +#if defined(__ECC__) +#define ALIGN +#define ALIGN4 _Pragma("align(4)") +#elif defined(__ICCARM__) +#define ALIGN _Pragma("pack()") +#define ALIGN4 _Pragma("pack(4)") +#elif defined (__GNUC__) +#define ALIGN _Pragma("pack()") +#define ALIGN4 _Pragma("pack(4)") +#endif + + +#define IS_IN_STATE(X) ((pDevice->nDriverStatus & (uint32_t)(X)) == (uint32_t)(X)) +#define IS_NOT_IN_STATE(X) ((pDevice->nDriverStatus & (uint32_t)(X)) == 0u) +#define IS_IN_ALL_STATES(X) ((pDevice->nDriverStatus & (uint32_t)(X)) == (uint32_t)(X)) +#define IS_IN_ANY_STATE(X) ((pDevice->nDriverStatus & (uint32_t)(X)) != 0u) +#define IS_NOT_IN_ANY_STATE(X) ((pDevice->nDriverStatus & (uint32_t)(X)) == 0u) + +#define SET_STATE(X) (pDevice->nDriverStatus |= (uint32_t)(X)) +#define CLR_STATE(X) (pDevice->nDriverStatus &= ~((uint32_t)(X))) + +#define NUM_ADC_CHANNELS (8u) +#define NUM_ADC_COMPARATOR_CHANNELS (4u) + +/* To keep state for the driver for error checking */ +typedef enum __ADC_STATUS { + ADC_STATUS_POWERED_UP = (1u << 0), + ADC_STATUS_SUB_SYSTEM_EN = (1u << 1), + ADC_STATUS_SUB_SYSTEM_READY = (1u << 2), + + ADC_STATUS_NON_BLOCKING_EN = (1u << 3), + ADC_STATUS_BLOCKING_EN = (1u << 4), + ADC_STATUS_COMPARATOR_EN = (1u << 5), + + ADC_STATUS_SAMPLING_IN_PROGRESS = (1u << 6), + ADC_STATUS_CALIBRATION_EN = (1u << 7), + ADC_STATUS_CALIBRATION_DONE = (1u << 8), + + ADC_STATUS_BATTERY_DONE = (1u << 9), + + ADC_STATUS_OVERSAMPLING_EN = (1u << 10), + ADC_STATUS_AVGERAGING_EN = (1u << 11), + + ADC_STATUS_TEMP_SENSOR_EN = (1u << 12), + + ADC_STATUS_TMP_DONE = (1u << 13), + ADC_STATUS_TMP2_DONE = (1u << 14), +} ADC_STATUS; + +typedef enum __ADC_FIFO_MODE { + ADC_FIFO_MODE_INIT, + ADC_FIFO_MODE_ENABLED, + ADC_FIFO_MODE_INTERRUPT_PROCESS, + ADC_FIFO_MODE_INTERRUPT_OVERFLOW, + ADC_FIFO_MODE_DMA_BUFFER_PROCESS, + ADC_FIFO_MODE_DMA_INVALID_DESC, + ADC_FIFO_MODE_ABORT +} ADC_FIFO_MODE; + +typedef enum __ADC_BUFFER_CONFIG { + ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN = ((uint32_t)1u << 1u), + ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN = ((uint32_t)1u << 0u), +} ADC_BUFFER_CONFIG; + + +typedef enum __ADC_BUFFER_STATUS { + ADC_BUFFER_STATUS_OK = ((uint32_t)1u << 0u), + ADC_BUFFER_STATUS_OVERFLOW = ((uint32_t)1u << 1u) +} ADC_BUFFER_STATUS; + +typedef struct __ADC_INT_BUFFER { + uint16_t nConfig; + uint16_t nStatus; + ADI_ADC_BUFFER *pUserBuffer; + uint16_t* pCurDataBuffer; + uint32_t nNumSamplesRemaining; + uint32_t nChannels; +} ADC_INT_BUFFER; + +typedef struct __ADC_ACTIVE_DATA { + uint32_t nCurChannel; +} ADC_ACTIVE_DATA; + +typedef ADI_ADC_RESULT (*ADC_MANAGE_FIFO_FUNC)(struct __ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode); + +typedef struct __ADI_ADC_DEVICE +{ + volatile uint32_t nDriverStatus; + ADI_ADC_TypeDef *pReg; + void* pCBParam; + ADI_CALLBACK pfCallback; + + ADC_ACTIVE_DATA ActData; + ADC_MANAGE_FIFO_FUNC pfManageFifo; + + ADC_INT_BUFFER s_Buffer; + uint8_t ComparitorHi; + uint8_t ComparitorLo; + uint8_t ComparitorHys; + + SEM_VAR_DECLR +} ADI_ADC_DEVICE; + +typedef struct __ADI_ADC_INFO +{ + ADI_ADC_HANDLE hDevice; + ADI_ADC_TypeDef* pReg; +} ADI_ADC_INFO; + +#endif /* ADI_ADC_DEF */ + +/*! \endcond */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_callback.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_callback.h new file mode 100755 index 0000000000..fd2e04f282 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_callback.h @@ -0,0 +1,60 @@ +/*! + ***************************************************************************** + @file: adi_callback.h + @brief: callback APIs. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ +/*****************************************************************************/ + +#ifndef ADI_CALLBACK_H +#define ADI_CALLBACK_H + +#include + +/** + * @brief Device Drivers Callback function definition + */ +typedef void (* ADI_CALLBACK) ( /*!< Callback function pointer */ + void *pCBParam, /*!< Client supplied callback param */ + uint32_t Event, /*!< Event ID specific to the Driver/Service */ + void *pArg); /*!< Pointer to the event specific argument */ + +#endif /* ADI_CALLBACK_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_cyclecount.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_cyclecount.h new file mode 100755 index 0000000000..a2b5807a62 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_cyclecount.h @@ -0,0 +1,137 @@ +/* + ******************************************************************************* + * @brief: Framework to preform cycle count measurements + * + * @details this is a framework for monitoring the cycle counts + * for ISRs and APIs. The framework uses systick. + +******************************************************************************* + + Copyright(c) 2016 Analog Devices, Inc. All Rights Reserved. + + This software is proprietary and confidential. By using this software you agree + to the terms of the associated Analog Devices License Agreement. + + ******************************************************************************/ + +#ifndef ADI_CYCLECOUNT_H +#define ADI_CYCLECOUNT_H + +#include +#include +#include + + + /** @addtogroup cyclecount_logging Cycle Counting Framework + * @{ + */ + +/*! + * 64-bit integer to record cycle counts. + * Since UINT32_MAX = 4,294,967,296 cycles + * at 26 MHz this would allow us to record for 165 seconds + * before the system would wrap around. + * By moving to a 64-bit integer we can record for 11,248 years. + */ +typedef uint64_t adi_cyclecount_t; + + +/*! + * The systick timer is a 24-bit count down timer + * The initial value can, therefore, be up to 0xFFFFFF + * The larger the value the fewer interrupts that will be taken + * and the less impact cycle counting will have on the system + */ +#define ADI_CYCLECOUNT_SYSTICKS (0xFFFFFFu) + +/*! + * Cycle counting nesting is supported via a cycle counting stack. The initial + * value of the stack index is one less than the starting stack + * index (0) + */ +#define ADI_CYCLECOUNT_INITIAL_STACK_INDEX (-1) + +/*! + * Cycle Count API function return values. + */ +typedef enum { + + ADI_CYCLECOUNT_SUCCESS, /*!< API completed successfully */ + ADI_CYCLECOUNT_ADD_ENTITY_FAILURE, /*!< There is not enough space in the cycle counting entity array. Consider increasing the size via the #ADI_CYCLECOUNT_NUMBER_USER_DEFINED_APIS static configuration macro */ + ADI_CYCLECOUNT_INVALID_ID, /*!< The API/ISR ID is invalid. */ + ADI_CYCLECOUNT_FAILURE /*!< API did not complete successfully. */ +} ADI_CYCLECOUNT_RESULT; + + +/*! + * List of cycle counting IDs for the ISRs and APIs that can record cycle counts. + * Items enumerated here must be aligned with adi_cyclecounting_identifiers + * + * Note that the ID numbering starts at 1. ID==0 is not used. + * Note that the application can extend this list via static configuration (see adi_cycle_counting_config.h) and + * via the adi_cyclecount_addEntity() API. + */ +#define ADI_CYCLECOUNT_ISR_EXT_3 1u /*!< Cycle count ID for EXT3 Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_UART 2u /*!< Cycle count ID for UART Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_DMA_UART_TX 3u /*!< Cycle count ID for UART DMA TX Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_DMA_UART_RX 4u /*!< Cycle count ID for UART DMA RX Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_TMR_COMMON 5u /*!< Cycle count ID for Timer Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_RTC 6u /*!< Cycle count ID for RTC Interrupt Handler.*/ +#define ADI_CYCLECOUNT_ISR_SPI 7u /*!< Cycle count ID for SPI Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_CRC 8u /*!< Cycle count ID for CRC Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_SPORT 9u /*!< Cycle count ID for SPORT Interrupt Handler. */ +#define ADI_CYCLECOUNT_ID_COUNT 10u /*!< Number of cycle count ISRs and APIs. Must be one greater than the last ID. */ + + +/*! + * The following are tracked when cycle counting + * Maximum number of cycle counts + * Minimum number of cycle counts + * Average number of cycle counts + */ +typedef struct +{ + adi_cyclecount_t max_cycles_adjusted; /*!< Tracks the adjusted max cycle count */ + adi_cyclecount_t min_cycles_adjusted; /*!< Tracks the adjusted min cycle count */ + adi_cyclecount_t average_cycles_adjusted; /*!< Tracks the adjusted average cycle count */ + + adi_cyclecount_t max_cycles_unadjusted; /*!< Tracks the unadjusted max cycle count */ + adi_cyclecount_t min_cycles_unadjusted; /*!< Tracks the unadjusted min cycle count */ + adi_cyclecount_t average_cycles_unadjusted; /*!< Tracks the unadjusted average cycle count */ + + uint32_t sample_count; /*!< Number of cycle count samples recorded, used to compute the average */ + +} ADI_CYCLECOUNT_LOG; + +/*! + * Cycle counting has to be enabled in the cycle counting configuration file + * If enabled then cycle counting related macros map to the cycle counting APIs. + * If not enabled, then the macros maps to a NOP + */ +#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1u) + + #define ADI_CYCLECOUNT_INITIALIZE() adi_cyclecount_init() /*!< Initialize the cycle counting data structures */ + #define ADI_CYCLECOUNT_STORE(id) adi_cyclecount_store(id) /*!< Record the number of cycles for the specified ISR or API */ + #define ADI_CYCLECOUNT_REPORT() adi_cyclecount_report() /*!< Generate a cycle counting report */ + +#else + + #define ADI_CYCLECOUNT_INITIALIZE() do{}while(0) /*!< Initialize the cycle counting data structures */ + #define ADI_CYCLECOUNT_STORE(id) do{}while(0) /*!< Record the number of cycles for the specified ISR or API */ + #define ADI_CYCLECOUNT_REPORT() do{}while(0) /*!< Generate a cycle counting report */ +#endif + + +/* Forward API declarations */ +extern ADI_CYCLECOUNT_RESULT adi_cyclecount_start(void); +extern ADI_CYCLECOUNT_RESULT adi_cyclecount_stop(void); +extern adi_cyclecount_t adi_cyclecount_get(void); +extern ADI_CYCLECOUNT_RESULT adi_cyclecount_store(uint32_t id); +extern void adi_cyclecount_init(void); +extern void adi_cyclecount_report(void); +extern ADI_CYCLECOUNT_RESULT adi_cyclecount_addEntity(const char *EntityName, uint32_t *pid); + +/**@}*/ + +#endif /* ADI_CYCLECOUNT_H */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_processor.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_processor.h new file mode 100755 index 0000000000..3032a13ac1 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_processor.h @@ -0,0 +1,67 @@ +/*! + ***************************************************************************** + * @file: adi_processor.h + * @brief: Include appropriate CMSIS device header. + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __ADI_PROCESSOR_H__ +#define __ADI_PROCESSOR_H__ + +/* Default to ADuCM4050 if no processor macro is defined. */ + +#if !defined(__ADUCM4050__) + #define __ADUCM4050__ +#endif + +/* Define a family macro */ + +#if !defined(__ADUCM4x50__) + #define __ADUCM4x50__ +#endif + +/* Include CMSIS device header for selected target processor. */ + +#if defined(__ADUCM4050__) +#include +#endif + +#endif /* __ADI_PROCESSOR_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_types.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_types.h new file mode 100755 index 0000000000..ca221b8360 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_types.h @@ -0,0 +1,18 @@ +#ifndef __ADI_TYPES_H__ +#define __ADI_TYPES_H__ + +/* obtain integer types ... */ +#include + +/* obtain boolean types ... */ +#include + +/* define required types that are not provided by stdint.h or stdbool.h ... */ +typedef bool bool_t; +typedef char char_t; +typedef float float32_t; +#if !defined(__NO_FLOAT64) +typedef long double float64_t; +#endif + +#endif /* __ADI_TYPES_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_version.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_version.h new file mode 100755 index 0000000000..6dd08f49bb --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_version.h @@ -0,0 +1,63 @@ +/*! + ***************************************************************************** + * @file: adi_version.h + * @brief: Version macros for ADI ADuCMxxx Device Series + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + + THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY + EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL + PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __ADI_VERSION_H__ +#define __ADI_VERSION_H__ + +/* use a 32-bit versioning scheme that supports numerical compares */ +#define ADI_VERSION_MAJOR 1u /* must be <= 255 */ +#define ADI_VERSION_MINOR 0u /* must be <= 255 */ +#define ADI_VERSION_BUILD 0u /* must be <= 255 */ +#define ADI_VERSION_PATCH 0u /* must be <= 255 */ + +#define ADI_CONSTRUCT_VERSION(a,b,c,d) (((a) << 24u) | ((b) << 16u) | ((c) << 8u) | (d)) + +/* known versions */ +#define ADI_VERSION_1_0_0_0 ADI_CONSTRUCT_VERSION(1u,0u,0u,0u) + +/* test current version against known predefines (see SystemInit() example in system.c) */ +#define ADI_VERSION_CURRENT ADI_CONSTRUCT_VERSION(ADI_VERSION_MAJOR, ADI_VERSION_MINOR, ADI_VERSION_BUILD, ADI_VERSION_PATCH) + +#endif /* __ADI_VERSION_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep.c new file mode 100755 index 0000000000..0d0054c432 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep.c @@ -0,0 +1,751 @@ +/*! ***************************************************************************** + * @file: adi_beep.c + * @brief: BEEP device driver global file. + * @details: This a global file which includes a specific file based on the processor family. + * This included file will be containing BEEP device driver functions. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#include + +#include +#include + +#include +#include +#include "adi_beep_def.h" + +/** @addtogroup BEEP_Driver BEEP Driver + * @{ + * @brief Beeper Driver + * @note The application must include drivers/beep/adi_beep.h to use this driver. + */ + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit. +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function. +* Multiple returns are used for error handling. +* +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Needed for null expansion of ADI_INSTALL_HANDLER and others. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* Required for MMR addresses and callback parameters. +* +* Pm031: (MISRA C 2004 rule 12.7) bitwise operations shall not be performed on signed integer types +* Required for MMR manipulations. +* +* Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type +* Required for adi_beep_PlaySequence() to access the user-supplied array of notes. +* +* Pm141: (MISRA C 2004 rule 11.4) a cast should not be performed between a pointer to object type and a +* different pointer to object type, this casts from type. +* Required to store a an array of varying size in a device structure. +* +* Required for adi_beep_PlaySequence() to access the user-supplied array of notes. +*/ +#pragma diag_suppress=Pm123,Pm073,Pm143,Pm050,Pm140,Pm031,Pm152,Pm141 +#endif /* __ICCARM__ */ + +/*========== D A T A ==========*/ +static ADI_BEEP_DRIVER adi_beep_Device[1]; + +/*! \cond PRIVATE */ +/* Handler for the BEEP interrupt */ +void Beep_Int_Handler(void); + +/* debug handle checker */ +#ifdef ADI_DEBUG +#define ADI_BEEP_INVALID_HANDLE(h) (&adi_beep_Device[0] != (h)) +#endif + +/* definition for the BEEP IRQ - there is only ever one instance of the + * BEEP driver, so reducing space by using a #define rather than including + * it in the device structure. */ +#define BEEP_IRQ (BEEP_EVT_IRQn) + +#if ADI_BEEP_CFG_SEQUENCE_REPEAT_VALUE == 0 +/* A single note is requested. Only enable the AEND int. */ +#define INTERRUPT_ON_SEQEND (0) +#define INTERRUPT_ON_AEND (1) +#else +/* A two-tone sequence is requested. Only enable the SEQEND int. */ +#define INTERRUPT_ON_SEQEND (1) +#define INTERRUPT_ON_AEND (0) +#endif + +/*! \endcond */ + +static const ADI_BEEP_STATIC_INIT gBeeperStaticConfigData[ADI_BEEP_MAX_DEVID] = { + /* single instance of Beeper device */ + { + /* configuration register */ + ( (INTERRUPT_ON_SEQEND << BITP_BEEP_CFG_SEQATENDIRQ) + | (INTERRUPT_ON_AEND << BITP_BEEP_CFG_AENDIRQ) + | (ADI_BEEP_CFG_SEQUENCE_REPEAT_VALUE << BITP_BEEP_CFG_SEQREPEAT) + ), + + /* Status register (interrupt clears) */ + (ADI_BEEP_ALL_INTERRUPTS), + + /* ToneA control register */ + ( ((uint32_t)ADI_BEEP_TONEA_DISABLE << BITP_BEEP_TONEA_DIS) + | ((uint32_t)ADI_BEEP_TONEA_FREQUENCY << BITP_BEEP_TONEA_FREQ) + | ((uint32_t)ADI_BEEP_TONEA_DURATION << BITP_BEEP_TONEA_DUR) + ), + + /* ToneB control register */ + ( ((uint32_t)ADI_BEEP_TONEB_DISABLE << BITP_BEEP_TONEB_DIS) + | ((uint32_t)ADI_BEEP_TONEB_FREQUENCY << BITP_BEEP_TONEB_FREQ) + | ((uint32_t)ADI_BEEP_TONEB_DURATION << BITP_BEEP_TONEB_DUR) + ) + } +}; + +/*! \endcond */ + + +/*! + * @brief BEEP Initialization + * + * @param[in] DeviceNum Integer specifying the ID of Beeper to use. + * @param[in] pMemory Pointer to the memory to be used by the driver. + * Size of the memory should be at least #ADI_BEEP_MEMORY_SIZE bytes. + * @param[in] MemorySize Size of the memory passed in pMemory parameter. + * @param[out] phDevice Pointer to a location that the device data pointer + * will be written upon successful initialization. + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: BEEP device driver initialized successfully. + * - #ADI_BEEP_SEMAPHORE_FAILED The BEEP sempahore could not be created. + * - #ADI_BEEP_ALREADY_INITIALIZED [D] The BEEP is already initialized. + * - #ADI_BEEP_NULL_PTR [D] Null pointer. + * - #ADI_BEEP_BAD_DEV_ID [D] The device number is invalid. + * + * Initialize the BEEP device for use. The core NVIC BEEP interrupt is enabled. This API + * must preceed all other beeper API calls and the handle returned must be passed to all other beeper API + * calls. + * + * + * @note The contents of \a phDevice will be set to NULL upon failure.\n\n + * + * @note The BEEP device driver will clear all pending interrupts and disable all beeper + * interrupts during beeper device initialization. + * + * @note CALLBACKS: If a callback is registered, it will be called on + * completion of the note or sequence. The "Event" parameter will + * contain which event occurred, either ADI_BEEP_INTERRUPT_SEQUENCE_END + * or ADI_BEEP_INTERRUPT_NOTE_END. + * + * @warning This API will put the beeper in preconfigured mode as defined in + * adi_beep_config.h file. + * Refer adi_beep_config.h file to see which all features can be preconfigured. + * + * @sa adi_beep_Close(). + */ +ADI_BEEP_RESULT adi_beep_Open(ADI_BEEP_DEV_ID const DeviceNum, + void* const pMemory, + uint32_t const MemorySize, + ADI_BEEP_HANDLE* const phDevice) +{ + ADI_BEEP_DRIVER *pDevice; + ADI_BEEP_DEV_DATA *pData; + /* store a bad handle in case of failure */ + *phDevice = (ADI_BEEP_HANDLE) NULL; + +#ifdef ADI_DEBUG + if (DeviceNum >= ADI_BEEP_MAX_DEVID) + { + return ADI_BEEP_BAD_DEV_ID; + } + + if (pMemory == NULL) + { + return ADI_BEEP_NULL_PTR; + } + + assert (MemorySize >= sizeof(ADI_BEEP_DRIVER)); +#endif + + /* local pointer to instance data */ + pDevice = &adi_beep_Device[DeviceNum]; + pDevice->pReg = pADI_BEEP0; + pDevice->pData = (ADI_BEEP_DEV_DATA*)pMemory; + pData = pDevice->pData; + +#ifdef ADI_DEBUG + if (ADI_BEEP_STATE_UNINITIALIZED != adi_beep_Device[DeviceNum].pData->state) + { + return ADI_BEEP_ALREADY_INITIALIZED; + } +#endif + + pData->cbFunc = NULL; + pData->cbParam = NULL; + SEM_CREATE(pDevice->pData, "BEEP_SEM", ADI_BEEP_SEMAPHORE_FAILED); + + /* set statically configured initialization data */ + ADI_BEEP_STATIC_INIT const* pInitData = &gBeeperStaticConfigData[DeviceNum]; + ADI_BEEP_TypeDef *pReg = pDevice->pReg; + + pReg->CFG = pInitData->BEEP_CFG; + pReg->STAT = pInitData->BEEP_STAT; + pReg->TONEA = pInitData->BEEP_TONEA; + pReg->TONEB = pInitData->BEEP_TONEB; + + /* enable beeper interrupts in NVIC */ + NVIC_EnableIRQ(BEEP_IRQ); + + /* mark driver initialized */ + pData->state = ADI_BEEP_STATE_INITIALIZED; + + /* store handle at application handle pointer */ + *phDevice = (ADI_BEEP_HANDLE)pDevice; + + return ADI_BEEP_SUCCESS; /* initialized */ +} + + +/*! + * @brief Uninitialize and deallocate a BEEP device. + * +* @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: Call completed successfully. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Error: Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Error: Device has not been initialized for use, see #adi_beep_Open(). + * + * Uninitialize and release an allocated BEEP device for other use. The core NVIC BEEP interrupt is disabled. + * + * @sa adi_beep_Open(). + */ +ADI_BEEP_RESULT adi_beep_Close(ADI_BEEP_HANDLE const hDevice) +{ + + ADI_BEEP_DRIVER *pDevice; + ADI_BEEP_DEV_DATA *pData; + ADI_BEEP_TypeDef *pReg; + + pDevice = (ADI_BEEP_DRIVER*)hDevice; + pData = pDevice->pData; + pReg = pDevice->pReg; + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) + { + return ADI_BEEP_BAD_DEV_HANDLE; + } + if (ADI_BEEP_STATE_UNINITIALIZED == pData->state) + { + return ADI_BEEP_NOT_INITIALIZED; + } +#endif + + /* uninitialize */ + NVIC_DisableIRQ(BEEP_IRQ); + + pData->state = ADI_BEEP_STATE_UNINITIALIZED; + pData->cbFunc = NULL; + pReg->CFG = 0u; + pReg->STAT = 0u; + pReg->TONEA = 0u; + pReg->TONEB = 0u; + SEM_DELETE(pDevice->pData, ADI_BEEP_SEMAPHORE_FAILED); + return ADI_BEEP_SUCCESS; +} + +/*! + * @brief Register a callback for the beeper driver. + * + * @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * @param[in] pfCallback The application supplied callback which will be called to notify device + * related events. + * @param[in] pCBParam The application supplied callback parameter which can be passed back in + * the callback function. + * + * @return Status + * - #ADI_BEEP_SUCCESS Call completed successfully. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_beep_Open(). + * + * Registers a callback for the beeper interrupts. When an interrupt occurs, the + * driver will handle any required interaction with the hardware and then call + * the registered callback. + * + * @sa adi_beep_Open(). + */ +ADI_BEEP_RESULT adi_beep_RegisterCallback(ADI_BEEP_HANDLE const hDevice, + ADI_CALLBACK pfCallback, + void* const pCBParam) +{ + ADI_BEEP_DRIVER *pDevice = (ADI_BEEP_DRIVER*)hDevice; + + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) { + return ADI_BEEP_BAD_DEV_HANDLE; + } + + if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) { + return ADI_BEEP_NOT_INITIALIZED; + } +#endif + /* Assign the callback within a critical region. */ + ADI_ENTER_CRITICAL_REGION(); + pDevice->pData->cbFunc = pfCallback; + pDevice->pData->cbParam = pCBParam; + ADI_EXIT_CRITICAL_REGION(); + + return ADI_BEEP_SUCCESS; +} + + +#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1 +/*! + * @brief Play a beeper tone sequence. + * + * @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * @param[in] aSequence The sequence of notes to be played by the beeper. + * @param[in] count The number of notes in the sequence, must be a multiple + * of two, and a maximum size of 254 notes. + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: Call completed successfully. + * - #ADI_BEEP_INVALID_COUNT Sequence count must be multiples of two. + * - #ADI_BEEP_NULL_PTR [D] Null pointer. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_beep_Open(). + * + * Programs the A/B tone pair to play a sequence of notes. The sequnce can be + * stopped by calling adi_beep_Enable(..., false). The beeper will be enabled + * and disabled internally by the driver. This code, and supporting data, can + * be removed by setting ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 0 in the + * adi_beep_config.h configuration file. + * + * @sa adi_beep_Open(). + * @sa adi_beep_Enable() + */ +ADI_BEEP_RESULT adi_beep_PlaySequence(ADI_BEEP_HANDLE const hDevice, + ADI_BEEP_NOTE aSequence[], + uint8_t count) +{ + ADI_BEEP_DRIVER *pDevice = (ADI_BEEP_DRIVER*)hDevice; + ADI_BEEP_TypeDef *pReg = pDevice->pReg; + uint16_t nSeqCnt = 0u; + + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) { + return ADI_BEEP_BAD_DEV_HANDLE; + } + + if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) { + return ADI_BEEP_NOT_INITIALIZED; + } + + if (NULL == aSequence) { + return ADI_BEEP_NULL_PTR; + } + + /* The sequence count must be a multiple of two, be greater than 1 + * and must be a maximum of (127 * 2) notes in length. The hardware supports a + * sequence of up to 127, and there are two notes associated with that. */ + if (((127u * 2u) < count) || + ((count % 2u) != 0u) || + (count < 2u)) { + return ADI_BEEP_INVALID_COUNT; + } +#endif + + /* Two notes are loaded at a time, and the sequence count refers to + * the number of times that both tone registers should be played. */ + nSeqCnt = ((uint16_t)count) >> 1u; + + ADI_ENTER_CRITICAL_REGION(); + + /* make a hole, and disable the beeper */ + pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_SEQREPEAT | BITM_BEEP_CFG_AENDIRQ | BITM_BEEP_CFG_EN); + + pReg->TONEA = ( (uint16_t)((uint16_t)aSequence[0].frequency << ADI_BEEP_TONE_FREQ_BITPOS) + |(uint16_t)((uint16_t)aSequence[0].duration << ADI_BEEP_TONE_DUR_BITPOS) ); + + pReg->TONEB = ( (uint16_t)((uint16_t)aSequence[1].frequency << ADI_BEEP_TONE_FREQ_BITPOS) + |(uint16_t)((uint16_t)aSequence[1].duration << ADI_BEEP_TONE_DUR_BITPOS) ); + + + /* program new sequence count, while preserving everything else */ + pReg->CFG |= (BITM_BEEP_CFG_EN | + BITM_BEEP_CFG_BSTARTIRQ | + BITM_BEEP_CFG_SEQATENDIRQ | + (uint16_t)((uint16_t)(nSeqCnt) << BITP_BEEP_CFG_SEQREPEAT)); + + pDevice->pData->pSeqArray = (ADI_BEEP_NOTE(*)[])aSequence; + pDevice->pData->nSeqMax = count; + pDevice->pData->nSeqIndex = 2u; + + /* We're now playing, but not blocked */ + pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING); + + ADI_EXIT_CRITICAL_REGION(); + + return ADI_BEEP_SUCCESS; +} +#endif + +/*! + * @brief Play a single note/beep. + * +* @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * @param[in] note The note to play. + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: Call completed successfully. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Error: Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Error: Device has not been initialized for use, see #adi_beep_Open(). + * + * Programs the A tone to play a single note. + * + * @sa adi_beep_Open(). + */ +ADI_BEEP_RESULT adi_beep_PlayNote(ADI_BEEP_HANDLE const hDevice, + ADI_BEEP_NOTE note) +{ + ADI_BEEP_DRIVER *pDevice; + ADI_BEEP_TypeDef *pReg; + ADI_INT_STATUS_ALLOC(); + + pDevice = (ADI_BEEP_DRIVER*)hDevice; + pReg = pDevice->pReg; + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) { + return ADI_BEEP_BAD_DEV_HANDLE; + } + + if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) { + return ADI_BEEP_NOT_INITIALIZED; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + + /* Clear any previous sequence setup, and disable the beeper */ + pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_SEQREPEAT | BITM_BEEP_CFG_EN); + + /* Set Tone A */ + pReg->TONEA = ( (uint16_t)((uint16_t)note.frequency << ADI_BEEP_TONE_FREQ_BITPOS) + |(uint16_t)((uint16_t)note.duration << ADI_BEEP_TONE_DUR_BITPOS) ); + + /* program new sequence count, while preserving everything else */ + pReg->CFG |= (BITM_BEEP_CFG_EN | BITM_BEEP_CFG_AENDIRQ); + + /* We're now playing but not blocked */ + pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING); + ADI_EXIT_CRITICAL_REGION(); + + return ADI_BEEP_SUCCESS; +} + + +/*! + * @brief Play a a repeating two-tone beep. Similar to an alarm. + * +* @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * @param[in] noteA The note to play first. + * @param[in] noteB The note to play second. + * @param[in] count The number of times to repeat the two-note signal, + * maximum of 127. + * + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: Call completed successfully. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Error: Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Error: Device has not been initialized for use, see #adi_beep_Open(). + * + * Programs the beeper to play a repeating two-tone signal. + * The count argument refers to the number of iterations of both notes, not + * just a single note. + * + * @sa adi_beep_Open(). + * @sa adi_beep_PlayNote(). + * @sa adi_beep_PlayNSequence(). + */ +ADI_BEEP_RESULT adi_beep_PlayTwoTone(ADI_BEEP_HANDLE const hDevice, + ADI_BEEP_NOTE noteA, + ADI_BEEP_NOTE noteB, + uint8_t count) +{ + ADI_BEEP_DRIVER *pDevice; + ADI_BEEP_TypeDef *pReg; + ADI_INT_STATUS_ALLOC(); + + pDevice = (ADI_BEEP_DRIVER*)hDevice; + pReg = pDevice->pReg; + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) { + return ADI_BEEP_BAD_DEV_HANDLE; + } + + if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) { + return ADI_BEEP_NOT_INITIALIZED; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + + /* make a hole, and disable the beeper */ + pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_SEQREPEAT | BITM_BEEP_CFG_AENDIRQ |BITM_BEEP_CFG_EN); + + pReg->TONEA = ( (uint16_t)((uint16_t)noteA.frequency << ADI_BEEP_TONE_FREQ_BITPOS) + |(uint16_t)((uint16_t)noteA.duration << ADI_BEEP_TONE_DUR_BITPOS) ); + + pReg->TONEB = ( (uint16_t)((uint16_t)noteB.frequency << ADI_BEEP_TONE_FREQ_BITPOS) + |(uint16_t)((uint16_t)noteB.duration << ADI_BEEP_TONE_DUR_BITPOS) ); + + /* program new sequence count, while preserving everything else */ + pReg->CFG |= (BITM_BEEP_CFG_EN | BITM_BEEP_CFG_SEQATENDIRQ |(uint16_t)((uint16_t)count << BITP_BEEP_CFG_SEQREPEAT)); + + /* We're now playing but not blocked */ + pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING); + ADI_EXIT_CRITICAL_REGION(); + + return ADI_BEEP_SUCCESS; +} + +/*! + * @brief Enable or disable the beeper. Other APIs will automatically enable the beeper if required, + * so this function is best used in the following situations: + * - when only using static configuration, i.e. start playing the notes + * set up in static adi_beep_config.h. + * - Otherwise, this can be used to stop the beeper during playback, + * when started from any other API. + * + * @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * @param[in] bFlag true to enable the device, false to stop playback. + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: Call completed successfully. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Error: Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Error: Device has not been initialized for use, see #adi_beep_Open(). + * + * @sa adi_beep_Open(). + */ +ADI_BEEP_RESULT adi_beep_Enable(ADI_BEEP_HANDLE const hDevice, bool const bFlag) +{ + ADI_BEEP_DRIVER *pDevice; + ADI_BEEP_TypeDef *pReg; + ADI_INT_STATUS_ALLOC(); + + pDevice = (ADI_BEEP_DRIVER*)hDevice; + pReg = pDevice->pReg; + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) { + return ADI_BEEP_BAD_DEV_HANDLE; + } + + if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) { + return ADI_BEEP_NOT_INITIALIZED; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + + if (bFlag == true) { + /* All the registers should already be set - just enable the beep */ + pReg->CFG |= BITM_BEEP_CFG_EN; + pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING); + } + else { + pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_EN); + pDevice->pData->state &= ~(ADI_BEEP_STATE_PLAYING); + } + + ADI_EXIT_CRITICAL_REGION(); + + return ADI_BEEP_SUCCESS; +} + +/*! + * @brief Wait for the current playback to finish. This is a blocking call, + * that will not return until the current playback (if any) has finished. + * If there is no current playback, it will return immediately. + * +* @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: Call completed successfully. + * - #ADI_BEEP_FAILURE Error: Semaphore failure. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Error: Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Error: Device has not been initialized for use, see #adi_beep_Open(). + * + * @sa adi_beep_Open(). + */ +ADI_BEEP_RESULT adi_beep_Wait(ADI_BEEP_HANDLE const hDevice) +{ + ADI_BEEP_DRIVER *pDevice; + bool wait = false; + ADI_INT_STATUS_ALLOC(); + + pDevice = (ADI_BEEP_DRIVER*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) { + return ADI_BEEP_BAD_DEV_HANDLE; + } + + if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) { + return ADI_BEEP_NOT_INITIALIZED; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + + if((pDevice->pData->state | ADI_BEEP_STATE_PLAYING) > 0u) { + /* We are going to pend on the semaphore, no matter what. */ + pDevice->pData->state |= ADI_BEEP_STATE_BLOCKED; + wait = true; + } + + ADI_EXIT_CRITICAL_REGION(); + + if(wait == true) { + /* Wait for the completion interrupt to post */ + SEM_PEND(pDevice->pData, ADI_BEEP_SEMAPHORE_FAILED); + } + + return ADI_BEEP_SUCCESS; +} + +/*! \cond PRIVATE */ + +/*! @brief BEEP device driver interrupt handler. Overrides weakly-bound + * default interrupt handler in the startup file. */ +void Beep_Int_Handler(void) +{ + ISR_PROLOG(); +#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1 + ADI_BEEP_DEV_DATA *pData; + ADI_BEEP_NOTE noteA, noteB; +#endif + ADI_BEEP_DRIVER *pDevice = &adi_beep_Device[ADI_BEEP_DEVID_0]; /* so far, there is only one BEEP, so this is safe */ + ADI_BEEP_TypeDef *pReg = pDevice->pReg; + uint16_t fired = ADI_BEEP_ALL_INTERRUPTS; + register uint16_t candidate; + + /* Make sure our driver is up and running. */ + if (ADI_BEEP_STATE_UNINITIALIZED != pDevice->pData->state) { + + /* read both status and mask registers */ + candidate = pReg->CFG & ADI_BEEP_ALL_INTERRUPTS; /* Take the fired interrupts */ + fired = candidate; /* ...and a copy. */ + candidate = candidate & pReg->STAT; /* ...and remove the unused set interrupt bits */ + + /* From this driver's perspective, there are only two states + * to watch for - finished playing, or continuing the playing sequence. + * Finished will be handled here. */ + if((candidate & (BITM_BEEP_CFG_SEQATENDIRQ | BITM_BEEP_CFG_AENDIRQ)) > 0u) { + + /* If we are blocked, unblock by posting the semaphore */ + if((pDevice->pData->state | ADI_BEEP_STATE_BLOCKED) > 0u) { + SEM_POST(pDevice->pData); + } + + /* Reset the device playing status. */ + pDevice->pData->state &= ~(ADI_BEEP_STATE_PLAYING | ADI_BEEP_STATE_BLOCKED); + + /* ...and disable the device. */ + pReg->CFG &= (uint16_t)(~(BITM_BEEP_CFG_EN)); + + /* forward the interrupt to the user if they are watching it and it has fired */ + /* pass the interrupt as the event. */ + if (pDevice->pData->cbFunc != NULL) { + pDevice->pData->cbFunc (pDevice->pData->cbParam, (uint32_t)candidate, NULL); + } + } + + #if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1 + /* The second state is if we are playing a longer sequence, so this + * interrupt may be to move the sequence along. */ + if ((BITM_BEEP_CFG_BSTARTIRQ & candidate) != 0u) { + + /* Get a local copy of data, to shorten the following code. */ + pData = pDevice->pData; + + /* If there's still data to play */ + if(pData->nSeqIndex < pData->nSeqMax) { + /* Move the sequence along.*/ + noteA = (*pData->pSeqArray)[pData->nSeqIndex]; + pData->nSeqIndex++; + noteB = (*pData->pSeqArray)[pData->nSeqIndex]; + pData->nSeqIndex++; + + /* Any values written will not impact the current tones, + * they will take effect after the current tone is completed */ + pReg->TONEA = ( (uint16_t)((uint16_t)noteA.frequency << ADI_BEEP_TONE_FREQ_BITPOS) + | (uint16_t)((uint16_t)noteA.duration << ADI_BEEP_TONE_DUR_BITPOS) ); + + pReg->TONEB = ( (uint16_t)((uint16_t)noteB.frequency << ADI_BEEP_TONE_FREQ_BITPOS) + | (uint16_t)((uint16_t)noteB.duration << ADI_BEEP_TONE_DUR_BITPOS) ); + } + } +#endif + } + + /* clear the watched interrupt(s) that fired */ + pReg->STAT |= (uint16_t)(fired & ADI_BEEP_ALL_INTERRUPTS); /* only write allowed interrupt bits */ + ISR_EPILOG(); +} +/*! \endcond */ + +/*@}*/ + + + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep_def.h new file mode 100755 index 0000000000..22e0b3a949 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep_def.h @@ -0,0 +1,128 @@ +/*! + ***************************************************************************** + * @file: adi_beep_def.h + * @brief: BEEP Device Driver definition + *----------------------------------------------------------------------------- + * + * Copyright (c) 2016 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL + * PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef _ADI_BEEP_DEF_H_ +#define _ADI_BEEP_DEF_H_ + +/*! \cond PRIVATE */ +#include + +/*! + ***************************************************************************** + * An interrupt mask covering all Beeper interrupts. + *****************************************************************************/ +#define ADI_BEEP_ALL_INTERRUPTS ( BITM_BEEP_CFG_SEQATENDIRQ \ + | BITM_BEEP_CFG_SEQNEARENDIRQ \ + | BITM_BEEP_CFG_BENDIRQ \ + | BITM_BEEP_CFG_BSTARTIRQ \ + | BITM_BEEP_CFG_AENDIRQ \ + | BITM_BEEP_CFG_ASTARTIRQ) + +#define ADI_BEEP_TONE_DISABLE (BITM_BEEP_TONEA_DIS) /*!< Beeper tone disable bit */ + +#define ADI_BEEP_TONE_FREQ_BITPOS (BITP_BEEP_TONEA_FREQ) /*!< Beeper tone frequency bitfield position */ +#define ADI_BEEP_TONE_DUR_BITPOS (BITP_BEEP_TONEA_DUR) /*!< Beeper tone duration bitfield position */ + +#define ADI_BEEP_TONE_FREQ_MASK (BITM_BEEP_TONEA_FREQ) /*!< Beeper tone frequency bitfield mask */ +#define ADI_BEEP_TONE_DUR_MASK (BITM_BEEP_TONEA_DUR) /*!< Beeper tone duration bitfield mask */ + +/*! + ***************************************************************************** + * ADI_BEEP_STATE + * + * BEEP driver state. Used for internal tracking of the BEEP device initialization + * progress during the adi_beep_Open(). Also used to insure the BEEP device has been + * properly initialized as a prerequisite to using the balance of the BEEP API. + * + *****************************************************************************/ +typedef uint8_t ADI_BEEP_STATE; +#define ADI_BEEP_STATE_UNINITIALIZED 0u /*!< BEEP is not initialized. */ +#define ADI_BEEP_STATE_INITIALIZED (1u << 1u) /*!< BEEP is initialized. */ +#define ADI_BEEP_STATE_PLAYING (1u << 2u) /*!< BEEP is currently playing. */ +#define ADI_BEEP_STATE_BLOCKED (1u << 3u) /*!< BEEP has blocked, waiting completion. */ + +/*! + * \struct ADI_BEEP_DEV_DATA + * Beeper device internal instance data structure. + */ +typedef struct _ADI_BEEP_DEV_DATA +{ + volatile ADI_BEEP_STATE state; /*!< Device state */ + ADI_CALLBACK cbFunc; /*!< Callback function */ + void *cbParam; /*!< Callback parameter */ +#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1 + ADI_BEEP_NOTE (*pSeqArray)[]; /*!< Pointer to a user-allocated array of notes. */ + volatile uint8_t nSeqIndex; /*!< Index for incrementing sequence */ + uint8_t nSeqMax; /*!< Size of the sequence */ +#endif + SEM_VAR_DECLR +} ADI_BEEP_DEV_DATA; + + +/*! \struct ADI_BEEP_DRIVER_STRUCT + * BEEP Device Structure + */ +typedef struct _ADI_BEEP_DRIVER_STRUCT +{ + ADI_BEEP_TypeDef *pReg; /*!< Pointer to register base */ + ADI_BEEP_DEV_DATA *pData; /*!< Pointer to device data structure */ +} ADI_BEEP_DRIVER_STRUCT; + +/*! \struct ADI_BEEP_STATIC_INIT + * conditionally create static initialization data based on adi_beep_config.h settings + */ +typedef struct { + uint16_t BEEP_CFG; /*!< Beeper configuration register */ + uint16_t BEEP_STAT; /*!< Beeper status register */ + uint16_t BEEP_TONEA; /*!< Beeper ToneA register */ + uint16_t BEEP_TONEB; /*!< Beeper ToneB register */ +} ADI_BEEP_STATIC_INIT; + +/* alias for the actual device structure */ +typedef ADI_BEEP_DRIVER_STRUCT ADI_BEEP_DRIVER; + +/*! \endcond */ + +#endif /* _ADI_BEEP_DEF_H_ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/common.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/common.h new file mode 100755 index 0000000000..e35f0bd8c2 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/common.h @@ -0,0 +1,127 @@ +/*! + ***************************************************************************** + * @file: common.h + * @brief: Common include file for all example + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + + +#ifndef COMMON_H +#define COMMON_H + +#ifdef __ICCARM__ +/* +* Pm106 (rule 20.9): the input/output library shall not be used in + production code +* The purpose of this header is to provide I/O facilities based on stdio. +*/ +#pragma diag_suppress=Pm106 +#endif /* __ICCARM__ */ + +#include +#include +#include +#include +#include + + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): The basic types of char, int, short, long, float shall not be used. +* Pm064 (rule 16.1): functions with variable number of arguments shall not be used. +*/ +#pragma diag_suppress=Pm011,Pm064 +#endif /* __ICCARM__ */ + + +#ifdef __cplusplus +extern "C" { +#endif + +/* Enable REDIRECT_OUTPUT_TO_UART to send the output to UART terminal. */ +/* #define REDIRECT_OUTPUT_TO_UART */ + +extern char aDebugString[150]; + +#ifdef __ICCARM__ +/* +* Pm154 (rule 19.10): in the definition of a function-like macro, each instance +* of a parameter shall be enclosed in parentheses +* The __VA_ARGS__ macro cannot be enclosed in parentheses. +*/ +#pragma diag_suppress=Pm154 +#endif /* __ICCARM__ */ + +#define DEBUG_MESSAGE(...) \ + do { \ + sprintf(aDebugString,__VA_ARGS__); \ + common_Perf(aDebugString); \ + } while(0) + +#ifdef __ICCARM__ +#pragma diag_default=Pm154 +#endif /* __ICCARM__ */ + +#define DEBUG_RESULT(s,result,expected_value) \ + do { \ + if ((result) != (expected_value)) { \ + sprintf(aDebugString,"%s %d", __FILE__,__LINE__); \ + common_Fail(aDebugString); \ + sprintf(aDebugString,"%s Error Code: 0x%08X\n\rFailed\n\r",(s),(result)); \ + common_Perf(aDebugString); \ + exit(0); \ + } \ + } while (0) + +/******************************************************************************** +* API function prototypes +*********************************************************************************/ +void common_Init(void); +void common_Pass(void); +void common_Fail(char *FailureReason); +void common_Perf(char *InfoString); + +#ifdef __cplusplus +} +#endif + +#endif /* COMMON_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_adc_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_adc_config.h new file mode 100755 index 0000000000..733f75771c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_adc_config.h @@ -0,0 +1,342 @@ +/*! + ***************************************************************************** + @file: adi_adc_config.h + @brief: Configuration options for ADC driver. + This is specific to the ADC driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_ADC_CONFIG_H +#define ADI_ADC_CONFIG_H +#include +/** @defgroup ADC_Driver_Cfg Static Configuration + * @ingroup ADC_Driver + */ + +/** @addtogroup ADC_Driver_Cfg Static Configuration +* @{ +*/ + +/************* ADC Driver configurations ***************/ + + +/*! Configure the default ADC configuration. Oversampling support must be enabled for resolution >12-bits.\n + Valid values are 12 to 16 +*/ +#define ADI_ADC_CFG_RESOLUTION (12) + +/*! Configure the default Vref\n + 3 - External Reference + 2 - Battery Voltage + 1 - 2.5V Internal Reference\n + 0 - 1.25V Internal Reference\n + +*/ +#define ADI_ADC_CFG_VREF (1) + +/*! Enable/Disable MULTI acquisitions of ADC data. + When enabled, DMA will be used for ADC readings which is + the preferred transfer method for multiple transactions. + Otherwise all will be interrupt driven. \n + 1 - Enable MULTI (DMA) acquisitions \n + 0 - Disable MULTI (use Interrupt) acquisitions \n +*/ +#define ADI_ADC_ENABLE_MULTI_ACQUIRE (1) + +/*! Enable/Disable HI/LO Digital Comparator limits \n + 1 - Enable HI/LO Digital Comparator limits\n + 0 - Disable HI/LO Digital Comparator limits\n +*/ +#define ADI_ADC_ENABLE_STATIC_COMPARATOR (1) + +/*! Enable/Disable Channel0 limit comparator \n + 1 - Enable HI Digital Comparator limit\n + 0 - Disable HI Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_HI_EN (0) /* 0 or 1 */ + +/*! Set the Channel0 limit comparator value \n + Sets the HI limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN0_HI_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_HI_VAL (4095) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel0 limit comparator \n + 1 - Enable LO Digital Comparator limit\n + 0 - Disable LO Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_LO_EN (1) /* 0 or 1 */ + +/*! Set the Channel0 limit comparator value. \n + Sets the LO limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN0_LO_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_LO_VAL (0) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel0 hysteresis and monitor cycles \n + 1 - Enable hysteresis and monitor cycles\n + 0 - Disable hysteresis and monitor cycles\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_HYS_EN (1) /* 0 or 1 */ + +/*! Set the Channel0 limit comparator hysteresis value. \n + Sets the hysteresis value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN0_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_HYS_VAL (0) /* 9 bits, 0 to 511 */ + +/*! Set the Channel0 limit comparator hysteresis monitor value. \n + Sets the monitor value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN0_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_HYS_CYC (0) /* 3 bits, 0 to 7 */ + +/*! Enable/Disable Channel1 limit comparator \n + 1 - Enable HI Digital Comparator limit\n + 0 - Disable HI Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN1_HI_EN (0) /* 0 or 1 */ + +/*! Set the Channel1 limit comparator value \n + Sets the HI limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN1_HI_EN is set to 1. \n +*/ +#define ADI_ADC_COMPARATOR_AIN1_HI_VAL (4095) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel1 limit comparator \n + 1 - Enable LO Digital Comparator limit\n + 0 - Disable LO Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN1_LO_EN (0) /* 0 or 1 */ + +/*! Set the Channel1 limit comparator value. \n + Sets the LO limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN1_LO_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN1_LO_VAL (0) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel1 hysteresis and monitor cycles \n + 1 - Enable hysteresis and monitor cycles\n + 0 - Disable hysteresis and monitor cycles\n +*/ +#define ADI_ADC_COMPARATOR_AIN1_HYS_EN (0) /* 0 or 1 */ + +/*! Set the Channel1 limit comparator hysteresis value. \n + Sets the hysteresis value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN1_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN1_HYS_VAL (0) /* 9 bits, 0 to 511 */ + +/*! Set the Channel1 limit comparator hysteresis monitor value. \n + Sets the monitor value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN1_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN1_HYS_CYC (0) /* 3 bits, 0 to 7 */ + +/*! Enable/Disable Channel2 limit comparator \n + 1 - Enable HI Digital Comparator limit\n + 0 - Disable HI Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN2_HI_EN (0) /* 0 or 1 */ + +/*! Set the Channel2 limit comparator value \n + Sets the HI limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN2_HI_EN is set to 1. \n +*/ +#define ADI_ADC_COMPARATOR_AIN2_HI_VAL (4095) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel2 limit comparator \n + 1 - Enable LO Digital Comparator limit\n + 0 - Disable LO Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN2_LO_EN (0) /* 0 or 1 */ + +/*! Set the Channel2 limit comparator value. \n + Sets the LO limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN2_LO_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN2_LO_VAL (0) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel2 hysteresis and monitor cycles \n + 1 - Enable hysteresis and monitor cycles\n + 0 - Disable hysteresis and monitor cycles\n +*/ +#define ADI_ADC_COMPARATOR_AIN2_HYS_EN (0) /* 0 or 1 */ + +/*! Set the Channel2 limit comparator hysteresis value. \n + Sets the hysteresis value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN2_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN2_HYS_VAL (0) /* 9 bits, 0 to 511 */ + +/*! Set the Channel2 limit comparator hysteresis monitor value. \n + Sets the monitor value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN2_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN2_HYS_CYC (0) /* 3 bits, 0 to 7 */ + +/*! Enable/Disable Channel3 limit comparator \n + 1 - Enable HI Digital Comparator limit\n + 0 - Disable HI Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN3_HI_EN (0) /* 0 or 1 */ + +/*! Set the Channel3 limit comparator value \n + Sets the HI limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN3_HI_EN is set to 1. \n +*/ +#define ADI_ADC_COMPARATOR_AIN3_HI_VAL (4095) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel3 limit comparator \n + 1 - Enable LO Digital Comparator limit\n + 0 - Disable LO Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN3_LO_EN (0) /* 0 or 1 */ + +/*! Set the Channel3 limit comparator value. \n + Sets the LO limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN3_LO_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN3_LO_VAL (0) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel3 hysteresis and monitor cycles \n + 1 - Enable hysteresis and monitor cycles\n + 0 - Disable hysteresis and monitor cycles\n +*/ +#define ADI_ADC_COMPARATOR_AIN3_HYS_EN (0) /* 0 or 1 */ + +/*! Set the Channel3 limit comparator hysteresis value. \n + Sets the hysteresis value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN3_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN3_HYS_VAL (0) /* 9 bits, 0 to 511 */ + +/*! Set the Channel3 limit comparator hysteresis monitor value. \n + Sets the monitor value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN3_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN3_HYS_CYC (0) /* 3 bits, 0 to 7 */ + + +/************** Macro validation *****************************/ + +#if (ADI_ADC_CFG_RESOLUTION < 12) || (ADI_ADC_CFG_RESOLUTION > 16) +#error "ADI_ADC_CFG_RESOLUTION is invalid" +#endif + +#if (ADI_ADC_CFG_VREF < 0) || (ADI_ADC_CFG_VREF > 3) +#error "ADI_ADC_CFG_VREF is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN0_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN0_HI_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN0_HI_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN1_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN1_HI_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN1_HI_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN2_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN2_HI_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN2_HI_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN3_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN3_HI_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN3_HI_VAL is invalid" +#endif + + +#if (ADI_ADC_COMPARATOR_AIN0_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN0_LO_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN0_LO_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN1_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN1_LO_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN1_LO_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN2_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN2_LO_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN2_LO_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN3_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN3_LO_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN3_HI_VAL is invalid" +#endif + + +#if (ADI_ADC_COMPARATOR_AIN0_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN0_HYS_VAL > (511)) +#error "ADI_ADC_COMPARATOR_AIN0_HYS_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN1_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN1_HYS_VAL > (511)) +#error "ADI_ADC_COMPARATOR_AIN1_HYS_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN2_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN2_HYS_VAL > (511)) +#error "ADI_ADC_COMPARATOR_AIN2_HYS_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN3_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN3_HYS_VAL > (511)) +#error "ADI_ADC_COMPARATOR_AIN3_HYS_VAL is invalid" +#endif + + +#if (ADI_ADC_COMPARATOR_AIN0_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN0_HYS_CYC > (7)) +#error "ADI_ADC_COMPARATOR_AIN0_HYS_CYC is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN1_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN1_HYS_CYC > (7)) +#error "ADI_ADC_COMPARATOR_AIN1_HYS_CYC is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN2_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN2_HYS_CYC > (7)) +#error "ADI_ADC_COMPARATOR_AIN2_HYS_CYC is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN3_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN3_HYS_CYC > (7)) +#error "ADI_ADC_COMPARATOR_AIN3_HYS_CYC is invalid" +#endif + + + + +/*! @} */ + +#endif /* ADI_ADC_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_beep_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_beep_config.h new file mode 100755 index 0000000000..a78814b0c7 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_beep_config.h @@ -0,0 +1,164 @@ +/*! + ***************************************************************************** + @file: adi_beep_config.h + @brief: Configuration options for BEEP driver. + This is specific to the BEEP driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_BEEP_CONFIG_H +#define ADI_BEEP_CONFIG_H +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions. + * + * Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters. + * IAR compiler supports longer identifiers. + */ +#pragma diag_suppress=Pm009 +#endif /* __ICCARM__ */ + +/** @addtogroup BEEP_Driver_Config Static Configuration + * @ingroup BEEP_Driver + * @{ + */ + +/************* BEEP Driver configurations ***************/ +/*! Enable the inclusion of adi_beep_PlaySequence(). This \n + API requires more data in the device structures to manage \n + the longer playing sequences, along with extra code in \n + the interrupt handler. \n + 0 - adi_beep_PlaySequence() omitted.\n + 1 - adi_beep_PlaySequence() is included. */ +#define ADI_BEEP_INCLUDE_PLAY_SEQUENCE 1 + +/************* BEEP controller static configurations ***************/ + +/*! Configure beeper disable.\n + 0 - Beeper enabled.\n + 1 - Beeper disabled. */ +#define ADI_BEEP_CFG_BEEPER_DISABLE 0 + +/*! Configure beeper sequence, when using static configuration. \n + 0 - Single note (Tone A only).\n + 1-255 - Sequence mode repeat count (Tone A then B sequentially). */ +#define ADI_BEEP_CFG_SEQUENCE_REPEAT_VALUE 5 + + +/* TONEA CONTROL REGISTER */ + +/*! Initial ToneA Disable.\n + 0 - ToneA Enabled.\n + 1 - ToneA Disabled. */ +#define ADI_BEEP_TONEA_DISABLE 0 + +/*! Initial ToneA Frequency.\n + 0-3 - Rest Tone (no oscillation).\n + 4-127 - Oscillate at 32kHz/freq Hz. */ +#define ADI_BEEP_TONEA_FREQUENCY 20 + +/*! Initial ToneA Duration.\n + 0-254 - Play for 4ms*duration.\n + 255 - Play for infinite duration. */ +#define ADI_BEEP_TONEA_DURATION 2 + + + +/* TONEB CONTROL REGISTER */ + +/*! Initial ToneB Disable.\n + 0 - ToneB Enabled.\n + 1 - ToneB Disabled. */ +#define ADI_BEEP_TONEB_DISABLE 0 + +/*! Initial ToneB Frequency. \n + 0-3 - Rest Tone (no oscillation).\n + 4-127 - Oscillate at 32kHz/freq Hz. */ +#define ADI_BEEP_TONEB_FREQUENCY 50 + +/*! Initial ToneB Duration.\n + 0-254 - Play for 4ms*duration.\n + 255 - Play for infinite duration. */ +#define ADI_BEEP_TONEB_DURATION 2 + + + +#ifdef __ICCARM__ +/* +* Pm085 (rule 19.11): identifiers in pre-processor directives should be defined before use +* The macros in the the following #if directives are defined to enum constants by default. +*/ +#pragma diag_suppress=Pm085 +#endif /* __ICCARM__ */ + +#if (ADI_BEEP_TONEA_DISABLE > 1) +#error "Invalid configuration" +#endif + +#if ( ADI_BEEP_TONEA_FREQUENCY > 127 ) +#error "Invalid configuration" +#endif + +#if ( ADI_BEEP_TONEA_DURATION > 255 ) +#error "Invalid configuration" +#endif + +#if (ADI_BEEP_TONEB_DISABLE > 1) +#error "Invalid configuration" +#endif + +#if ( ADI_BEEP_TONEB_FREQUENCY > 127 ) +#error "Invalid configuration" +#endif + +#if ( ADI_BEEP_TONEB_DURATION > 255 ) +#error "Invalid configuration" +#endif + +#ifdef __ICCARM__ +#pragma diag_default=Pm009,Pm085 +#endif /* __ICCARM__ */ + +/*! @} */ + +#endif /* ADI_BEEP_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crc_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crc_config.h new file mode 100755 index 0000000000..19737e3a88 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crc_config.h @@ -0,0 +1,100 @@ +/*! + ***************************************************************************** + @file: adi_crc_config.h + @brief: Configuration options for CRC driver. + This is specific to the CRC driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_CRC_CONFIG_H +#define ADI_CRC_CONFIG_H + +#include + +/** @defgroup CRC_Driver_Cfg Static Configuration + * @ingroup CRC_Driver + */ + +/** @addtogroup CRC_Driver_Cfg Static Configuration +* @{ +*/ + +/************* CRC Driver configurations ***************/ +/*! + Enable DMA support in the driver code.\n + 1 - To have the DMA support code in the driver.\n + 0 - To eliminate the DMA support. Operates in core mode.\n +*/ +#define ADI_CRC_CFG_ENABLE_DMA_SUPPORT 0 + +/*! + Enable Byte mirroring option\n + 1 - To enable byte mirroring \n + 0 - To disable the byte mirroring. +*/ +#define ADI_CFG_CRC_ENABLE_BYTE_MIRRORING 0 +/*! + Enable Bit mirroring option\n + 1 - To enable bit mirroring \n + 0 - To disable the bit mirroring. +*/ +#define ADI_CFG_CRC_ENABLE_BIT_MIRRORING 0 + +/*! + To specify the seed value for CRC computation +*/ + +#define ADI_CFG_CRC_SEED_VALUE (0xFFFFFFFFu) + +/*! + To specify the polynomial to be used for CRC computation +*/ +#define ADI_CFG_CRC_POLYNOMIAL (0x04C11DB7u) + +/*! + To specify the Software DMA channel to be used for the CRC computation + 0 -> DMA channel SIP0, ..., 7 -> DMA channel SIP7 +*/ +#define ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID 7 + +#endif /* ADI_CRC_CONFIG_H */ +/*! @} */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crypto_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crypto_config.h new file mode 100755 index 0000000000..d67f6ab81c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crypto_config.h @@ -0,0 +1,138 @@ +/*! + ***************************************************************************** + @file: adi_crypto_config.h + @brief: Configuration options for Crypto driver. + This is specific to the Crypto driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2014-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef __ADI_CRYPTO_CONFIG_H__ +#define __ADI_CRYPTO_CONFIG_H__ +#include + +/** @addtogroup Crypto_Driver_Config Static Configuration + * @ingroup Crypto_Driver + * @{ + */ + +/************* Crypto Driver configurations ***************/ + +/*! Enable/Disable ECB Support\n + 1 - Enable ECB Support\n + 0 - Disable ECB Support\n +*/ +#define ADI_CRYPTO_ENABLE_ECB_SUPPORT (1) + +/*! Enable/Disable CTR Support\n + 1 - Enable CTR Support\n + 0 - Disable CTR Support\n +*/ +#define ADI_CRYPTO_ENABLE_CTR_SUPPORT (1) + +/*! Enable/Disable CBC Support\n + 1 - Enable CBC Support\n + 0 - Disable CBC Support\n +*/ +#define ADI_CRYPTO_ENABLE_CBC_SUPPORT (1) + +/*! Enable/Disable CCM Support\n + 1 - Enable CCM Support\n + 0 - Disable CCM Support\n +*/ +#define ADI_CRYPTO_ENABLE_CCM_SUPPORT (1) + +/*! Enable/Disable CMAC Support\n + 1 - Enable CMAC Support\n + 0 - Disable CMAC Support\n +*/ +#define ADI_CRYPTO_ENABLE_CMAC_SUPPORT (1) + +/*! Enable/Disable HMAC Support\n + 1 - Enable HMAC Support\n + 0 - Disable HMAC Support\n +*/ +#define ADI_CRYPTO_ENABLE_HMAC_SUPPORT (1) + +/*! Enable/Disable SHA Support\n + 1 - Enable SHA Support\n + 0 - Disable SHA Support\n +*/ +#define ADI_CRYPTO_ENABLE_SHA_SUPPORT (1) + + +/*! Enable/Disable DMA Support\n + 1 - Enable DMA Support\n + 0 - Disable DMA Support +*/ +#define ADI_CRYPTO_ENABLE_DMA_SUPPORT (1) + +/*! Enable/Disable DMA Transfer by default\n + 1 - Enable DMA \n + 0 - Disable DMA +*/ +#define ADI_CRYPTO_ENABLE_DMA (1) + +/*! SHA output format\n + 1 - Big-Endian \n + 0 - Little-Endian +*/ +#define ADI_CRYPTO_SHA_OUTPUT_FORMAT (1) + + + +/************** Macro validation *****************************/ + +#if ((ADI_CRYPTO_ENABLE_DMA_SUPPORT != 0) && (ADI_CRYPTO_ENABLE_DMA_SUPPORT != 1)) +#error "ADI_CRYPTO_ENABLE_DMA_SUPPORT is invalid" +#endif + +#if ((ADI_CRYPTO_ENABLE_DMA != 0) && (ADI_CRYPTO_ENABLE_DMA != 1)) +#error "ADI_CRYPTO_ENABLE_DMA is invalid" +#endif + +#if ((ADI_CRYPTO_ENABLE_DMA == 1) && (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 0)) +#error "DMA cannot be enabled if DMA support is disabled" +#endif + +/*! @} */ + +#endif /* __ADI_CRYPTO_CONFIG_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_cycle_counting_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_cycle_counting_config.h new file mode 100755 index 0000000000..4b83c46fd7 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_cycle_counting_config.h @@ -0,0 +1,105 @@ +/*! ***************************************************************************** + * @file adi_cycle_counting_config.h + * @brief Cycle Counting Framework configuration + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifndef ADI_CYCLE_COUNTING_CONFIG_H +#define ADI_CYCLE_COUNTING_CONFIG_H + +/** @addtogroup CYCLE_COUNTING_Config Static Configuration + * @ingroup cyclecount_logging + * @{ + */ + + +/************* Cycle Counting Configuration ***************/ + +/*! Global enable. This must be enabled for any other functionality to work\n + 0u disabled + 1u enabled +*/ +#define ADI_CYCLECOUNT_ENABLED (0u) + +/*! SPI Interrupt Mode ISR Cycle Counting Enabled\n + 0 - Disables the recording of SPI ISR cycle counting. + 1 - Enables the recording of SPI ISR cycle counting. +*/ +#define ADI_CYCLECOUNT_SPI_ISR_ENABLED (0u) + + +/*! CRC Interrupt Mode ISR Cycle Counting Enabled\n + 0 - Disables the recording of CRC ISR cycle counting. + 1 - Enables the recording of CRC ISR cycle counting. +*/ +#define ADI_CYCLECOUNT_CRC_ISR_ENABLED (0u) + + +/*! SPORT Interrupt Mode ISR Cycle Counting Enabled\n + 0 - Disables the recording of SPORT ISR cycle counting. + 1 - Enables the recording of SPORT ISR cycle counting. +*/ +#define ADI_CYCLECOUNT_SPORT_ISR_ENABLED (0u) + +/*! UART Interrupt Mode ISR Cycle Counting Enabled\n + 0 - Disables the recording of UART ISR cycle counting. + 1 - Enables the recording of UART ISR cycle counting. +*/ +#define ADI_CYCLECOUNT_UART_ISR_ENABLED (0u) + + +/*! A user application may desire/require cycle counting in an application defined API + or ISR. Set this macro to the number of required. +*/ +#define ADI_CYCLECOUNT_NUMBER_USER_DEFINED_APIS (0u) + +/*! + * Cycle count 'stack' nesting depth. Adjust as needed. + * This should map to the maximum number of nested interrupts an application might experience. + */ +#define ADI_CYCLECOUNT_STACK_SIZE 10 + +/** + * @} + */ + +#endif /* ADI_CYCLE_COUNTING_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_flash_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_flash_config.h new file mode 100755 index 0000000000..5eb4e5a779 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_flash_config.h @@ -0,0 +1,299 @@ +/*! + ***************************************************************************** + @file: adi_flash_config.h + @brief: Configuration options for flash driver. + This is specific to the flash driver and will be included by the driver. + It is not required for the application to include this header file. + @version: $Revision: 33205 $ + @date: $Date: 2016-01-11 05:46:07 -0500 (Mon, 11 Jan 2016) $ + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_FLASH_CONFIG_H +#define ADI_FLASH_CONFIG_H +#include + +/** @addtogroup Flash_Driver_Config Static Configuration + * @ingroup Flash_Driver + * @{ + */ + + +/****SETTINGS THAT LIVE IN FEE INTERRUPT ENABLE (IEN) REGISTER****/ + + +/*! + * Configure a response to the 2-bit ECC ERROR events (in IEN). + * - 0 Do not generate a response to ECC Error Events. + * - 1 Generate Bus Errors in response to ECC Error Events. + * - 2 Generate IRQs in response to ECC Error Events. + */ +#define ADI_FEE_CFG_ECC_ERROR_RESPONSE (1u) +/*! + * Configure a response to the 1-bit ECC CORRECTION events (in IEN). + * - 0 Do not generate a response to ECC correction Events. + * - 1 Generate Bus Errors in response to ECC correction Events. + * - 2 Generate IRQs in response to ECC correction Events. + */ +#define ADI_FEE_CFG_ECC_CORRECTION_RESPONSE (2u) + + + +/****SETTINGS THAT LIVE IN FEE TIME PARAMETER 0 (TIME_PARAM0) REGISTER****/ + + +/* It is recommended to NOT MODIFY flash timing parameters without keen insight and caution */ +/*! + * Configure flash non-volatile mass erase hold time.\n + * Upper 4-bits of 11-bit value.\n + * (Lower bits are hard-coded to 0x14.)\n + * Hardware default value is 0xb. + */ +#define ADI_FEE_CFG_PARAM0_TNVH1 (0xbu) + +/*! + * Configure flash erase time.\n + * Upper 4-bits of 19-bit value.\n + * (Lower bits are hard-coded to 0x7370.)\n + * Hardware default value is 0x8. + */ +#define ADI_FEE_CFG_PARAM0_TERASE (0x8u) + +/*! + * Configure flash recovery time.\n + * Upper 4-bits of 8-bit value.\n + * (Lower bits are hard-coded to 0x2.)\n + * Hardware default value is 0x9. + */ +#define ADI_FEE_CFG_PARAM0_TRCV (0x9u) + +/*! + * Configure flash non-volatile hold time.\n + * Upper 4-bits of 8-bit value.\n + * (Lower bits are hard-coded to 0x1.)\n + * Hardware default value is 0x5. + */ +#define ADI_FEE_CFG_PARAM0_TNVH (0x5u) + +/*! + * Configure flash program time.\n + * Upper 4-bits of 10-bit value.\n + * (Lower bits are hard-coded to 0x7.)\n + * Hardware default value is 0x0. + */ +#define ADI_FEE_CFG_PARAM0_TPROG (0x0u) + +/*! + * Configure flash NVSTR-to-program setup time.\n + * Upper 4-bits of 8-bit value.\n + * (Lower bits are hard-coded to 0x2.)\n + * Hardware default value is 0x9. + */ +#define ADI_FEE_CFG_PARAM0_TPGS (0x9u) + +/*! + * Configure flash program/erase-to-NVSTR setup time.\n + * Upper 4-bits of 8-bit value.\n + * (Lower bits are hard-coded to 0x1.)\n + * Hardware default value is 0x5. + */ +#define ADI_FEE_CFG_PARAM0_TNVS (0x5u) + +/*! + * Configure flash reference clock divide-by-2 setting.\n + * All timing parameters are referenced to this parameter. + * - 0 Reference clock is not divided. + * - 1 Reference clock is divided by 2.\n + * Hardware default value is 0x0. + */ +#define ADI_FEE_CFG_PARAM0_CLKDIV (0x0u) + + + +/****SETTINGS THAT LIVE IN FEE TIME PARAMETER 1 (TIME_PARAM1) REGISTER****/ + + +/* It is recommended to NOT MODIFY flash timing parameters without keen insight and caution */ +/*! + * Configure flash read access wait states.\n + * Number of 3-bit read access wait states to use.\n + * Maximum allowed value is 0x4.\n + * Hardware default value is 0x0. + */ +#define ADI_FEE_CFG_PARAM1_WAITESTATES (0x0u) + +/*! + * Configure flash sleep mode wake-up time.\n + * Upper 4-bits of 8-bit value.\n + * (Lower bits are hard-coded to 0xb.)\n + * Hardware default value is 0x4. + */ +#define ADI_FEE_CFG_PARAM1_TWK (0x4u) + + + +/****SETTINGS THAT LIVE IN FEE SYSTEM ABOUT ENABLE (ABOUT_EN_XX) REGISTERS****/ + + +/*! + * Configure lower (0-31) flash system interrupt abort enables.\n + * Allows system interrupts to abort an ongoing flash command.\n + * Only 64 system interrupts are supported.\n + * Lower interrupts (0-31) are encoded in ADI_FEE_CFG_ABORT_EN_LO, + * - 0 Corresponding interrupt is prevented from aborting flash command. + * - 1 Corresponding interrupt is allowed to abort flash command.\n + * Hardware default value is 0x0. + */ +#define ADI_FEE_CFG_ABORT_EN_LO (0x0u) + +/*! + * Configure upper (32-63) flash system interrupt abort enables.\n + * Allows system interrupts to abort an ongoing flash command.\n + * Only 64 system interrupts are supported.\n + * Upper interrupts (32-63) are encoded in ADI_FEE_CFG_ABORT_EN_HI. + * - 0 Corresponding interrupt is prevented from aborting flash command. + * - 1 Corresponding interrupt is allowed to abort flash command.\n + * Hardware default value is 0x0. + */ +#define ADI_FEE_CFG_ABORT_EN_HI (0x0u) + + + +/****SETTINGS THAT LIVE IN ECC CONFIG REGISTER (ECC_CFG) REGISTER****/ + + +/*! + * ECC Start Page Pointer (in ECC_CFG). + */ +#define ADI_FEE_CFG_ECC_START_PAGE (0u) + +/*! + * Enable/Disable ECC for info space (in ECC_CFG). + * - 1 Enable Info Space. + * - 0 Disable Info Space. + */ +#define ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE (0u) + +/*! + * Enable/Disable ECC (in ECC_CFG). + * - 1 Enable ECC. + * - 0 Disable ECC. + */ +#define ADI_FEE_CFG_ENABLE_ECC (0u) + + + +/************* Flash Driver Configuration Settings Checkers ***************/ + + + +/* IEN CHECKS */ +#if ((ADI_FEE_CFG_ECC_ERROR_RESPONSE < 0u) || (ADI_FEE_CFG_ECC_ERROR_RESPONSE > 2u)) +#error "ADI_FEE_CFG_ECC_ERROR_RESPONSE should be in the range 0-2." +#endif +#if ((ADI_FEE_CFG_ECC_CORRECTION_RESPONSE < 0u) || (ADI_FEE_CFG_ECC_CORRECTION_RESPONSE > 2u)) +#error "ADI_FEE_CFG_ECC_CORRECTION_RESPONSE should be in the range 0-2." +#endif + + + +/* PARAM0 CHECKS */ +#if ((ADI_FEE_CFG_PARAM0_TNVH1 < 0u) || (ADI_FEE_CFG_PARAM0_TNVH1 > 15u)) +#error "ADI_FEE_CFG_PARAM0_TNVH1 should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_TERASE < 0u) || (ADI_FEE_CFG_PARAM0_TERASE > 15u)) +#error "ADI_FEE_CFG_PARAM0_TERASE should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_TRCV < 0u) || (ADI_FEE_CFG_PARAM0_TRCV > 15u)) +#error "ADI_FEE_CFG_PARAM0_TRCV should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_TNVH1 < 0u) || (ADI_FEE_CFG_PARAM0_TNVH1 > 15u)) +#error "ADI_FEE_CFG_PARAM0_TNVH1 should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_TPROG < 0u) || (ADI_FEE_CFG_PARAM0_TPROG > 15u)) +#error "ADI_FEE_CFG_PARAM0_TPROG should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_TPGS < 0u) || (ADI_FEE_CFG_PARAM0_TPGS > 15u)) +#error "ADI_FEE_CFG_PARAM0_TPGS should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_TNVS < 0u) || (ADI_FEE_CFG_PARAM0_TNVS > 15u)) +#error "ADI_FEE_CFG_PARAM0_TNVS should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_CLKDIV < 0u) || (ADI_FEE_CFG_PARAM0_CLKDIV > 1u)) +#error "ADI_FEE_CFG_PARAM0_CLKDIV should be in the range 0-1." +#endif + + + +/* PARAM1 CHECKS */ +#if ((ADI_FEE_CFG_PARAM1_WAITESTATES < 0u) || (ADI_FEE_CFG_PARAM1_WAITESTATES > 4u)) +#error "ADI_FEE_CFG_PARAM1_WAITESTATES should be in the range 0-4." +#endif +#if ((ADI_FEE_CFG_PARAM1_TWK < 0u) || (ADI_FEE_CFG_PARAM1_TWK > 15u)) +#error "ADI_FEE_CFG_PARAM1_TWK should be in the range 0-15." +#endif + + + +/* ABORT_EN_XX CHECKS */ +#if ((ADI_FEE_CFG_ABORT_EN_LO < 0u) || (ADI_FEE_CFG_ABORT_EN_LO > 0XFFFFu)) +#error "ADI_FEE_CFG_ABORT_EN_LO should be in 32-bit range." +#endif +#if ((ADI_FEE_CFG_ABORT_EN_HI < 0u) || (ADI_FEE_CFG_ABORT_EN_HI > 0XFFFFu)) +#error "ADI_FEE_CFG_ABORT_EN_HI should be in 32-bit range." +#endif + + + +/* ECC_CFG CHECKS */ +#if (((ADI_FEE_CFG_ECC_START_PAGE >> 8u) << 8) != ADI_FEE_CFG_ECC_START_PAGE) +#error "ADI_FEE_CFG_ECC_START_PAGE has invalid bits set in lower 8-bits." +#endif +#if ((ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE != 0u) && (ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE != 1u)) +#error "ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE should be 1 or 0." +#endif +#if ((ADI_FEE_CFG_ENABLE_ECC != 0u) && (ADI_FEE_CFG_ENABLE_ECC != 1u)) +#error "ADI_FEE_CFG_ENABLE_ECC should be 1 or 0." +#endif + +/*! @} */ + +#endif /* ADI_FLASH_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_global_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_global_config.h new file mode 100755 index 0000000000..6d205577a3 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_global_config.h @@ -0,0 +1,131 @@ +/*! + ***************************************************************************** + @file: adi_global_config.h + @brief: Configuration options for all the drivers. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_GLOBAL_CONFIG_H +#define ADI_GLOBAL_CONFIG_H + +/** @addtogroup GLOBAL_Driver_Config Global Static Configuration + * @brief Configuration options for all the drivers. + * @{ + */ + +/*! @name RTOS used + * In order to be used in a multi-threaded application, the device drivers + * may require the use of some RTOS-specific signals like semaphores or actions + * may be required when entering/exiting an interrupt. By specifying the RTOS + * that the application uses, the drivers can map their requirements to the + * specific RTOS, without requiring an OS abstraction layer. + * @note This macros do not add the RTOS sources to the application, users need + * to set up the source and include paths in their application themselves + * @note If the RTOS specified is not in the list of supported RTOS the build + * mechanism fails + */ +/**@{*/ + +/*! @hideinitializer Indicates that no RTOS is used (bare-metal applications) */ +#define ADI_CFG_RTOS_NO_OS (1) +/*! @hideinitializer Indicates that Micrium uCOS-III is used */ +#define ADI_CFG_RTOS_MICRIUM_III (2) +/*! @hideinitializer Indicates that Micrium FreeRTOS is used */ +#define ADI_CFG_RTOS_FREERTOS (3) + +/*! Configure the RTOS required across the project. + It can be configured to one of the following macros: + - #ADI_CFG_RTOS_NO_OS + - #ADI_CFG_RTOS_MICRIUM_III + - #ADI_CFG_RTOS_FREERTOS + */ +#define ADI_CFG_RTOS ADI_CFG_RTOS_NO_OS + +/**@}*/ + +/*! @name Low power mode support + All applications may have to block when a buffer is being processed. In the + case of an RTOS application, when a task is blocked waiting for a buffer, a + different task can run. If no tasks are available then the idle task runs. + In many RTOS the idle task can be configured so it perform actions like + entering low power modes. + + In the case of a bare-metal (no RTOS) application, since there are no other + tasks to be run, the driver can enter low power modes itself when it blocks. + */ + +/*! Configures the drivers to enter low power mode (Flexi mode) + when waiting for a buffer to be processed. This macro is applicable + only when the drivers are operating in the bare metal mode (No RTOS). + + The possible values it can be configured to are: + + - 1 : Low power mode support required. + - 0 : Low power mode support not required. +*/ +#define ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT (1) +/**@}*/ + + + +/* +** Verify the macro configuration +*/ +#if ((ADI_CFG_RTOS != ADI_CFG_RTOS_NO_OS) && \ + (ADI_CFG_RTOS != ADI_CFG_RTOS_MICRIUM_III) && \ + (ADI_CFG_RTOS != ADI_CFG_RTOS_FREERTOS)) +#error "ADI_CFG_RTOS macro wrongly configured" +#endif /* ADI_CFG_RTOS verification */ + +#if ((ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT != 0) && \ + (ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT != 1)) +#error "ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT macro is wrongly configured" +#endif + +#if ((ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT == 1) && \ + (ADI_CFG_RTOS != ADI_CFG_RTOS_NO_OS)) +#error "ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT cannot be set to 1 in multi-threaded applications" +#endif +/** + * @} + */ + +#endif /* ADI_GLOBAL_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_i2c_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_i2c_config.h new file mode 100755 index 0000000000..0f6bbca875 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_i2c_config.h @@ -0,0 +1,226 @@ +/*! + ***************************************************************************** + @file: adi_i2c_config.h + @brief: Configuration options for I2C driver. + This is specific to the I2C driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_I2C_CONFIG_H +#define ADI_I2C_CONFIG_H +#include + +/** @addtogroup I2C_Driver_Config Static Configuration + * @ingroup I2C_Driver + * @{ + */ + +/************* I2C Driver configurations ***************/ + +/*! Master control register TX FIFO decrement control bit.\n + 1 - Decrement master TX FIFO status when a byte has been fully serialized.\n + 0 - Decrement master TX FIFO status when a byte is unloaded from the TX FIFO, + but not yet serialized on the bus. */ +#define ADI_I2C_CFG_MCTL_MXMITDEC (0) + +/*! Master control register STOP condition interrupt enable.\n + 1 - Enable completion interrupt when a STOP condition is detected.\n + 0 - Disable completion interrupt when a STOP condition is detected. */ +#define ADI_I2C_CFG_MCTL_IENCMP (1) + +/*! Master control register NACK (NotACKnowledge) interrupt enable.\n + 1 - Enable NACK interrupt when an acknowledge is not received.\n + 0 - Disable NACK interrupt when an acknowledge is not received. */ +#define ADI_I2C_CFG_MCTL_IENACK (1) + +/*! Master control register ALOST (Arbitration LOST) interrupt enable.\n + 1 - Enable ALOST interrupt when bus arbitration is lost.\n + 0 - Disable ALOST interrupt when bus arbitration is lost. */ +#define ADI_I2C_CFG_MCTL_IENALOST (1) + +/*! Master control register clock stretch enable.\n + 1 - Enable clock stretch by slave device.\n + 0 - Disable clock stretch by slave device. */ +#define ADI_I2C_CFG_MCTL_STRETCHSCL (0) + +/*! Master control register internal loopback enable.\n + 1 - Enable internal looping of SCL and SDA outputs onto their corresponding inputs.\n + 0 - Disable internal looping of SCL and SDA outputs onto their corresponding inputs. */ +#define ADI_I2C_CFG_MCTL_LOOPBACK (0) + +/*! Master control register start condition back-off disable.\n + 1 - Enables controller to compete for bus ownership even if another device is driving a START condition.\n + 0 - Disables controller to compete for bus ownership even if another device is driving a START condition. */ +#define ADI_I2C_CFG_MCTL_COMPLETE (0) + +/*! Master control register device enable.\n + 1 - Enable controller as a Master device.\n + 0 - Disables controller as a Master device. */ +#define ADI_I2C_CFG_MCTL_MASEN (0) + +/*! + * Standard Clock divider Clock-HI settings. + * Assuming a 26 MHz core clock, the following settings + * will be useful: \n + * - For STANDARD (100 kHz) rate, use: HI= 25, LO= 31. \n + * - For FAST (400 kHz) rate, use: HI=123, LO=129. \n + * \n + * @note The clock high setting varies with pull-up loading, + * board layout, slew-rate, etc., so exact settings are somewhat + * empirical. The clock high counter does not start until + * a logic high transition is sensed on the clock line, so + * variability in this logic transaction will alter the + * effective clock rate. This results from the internal + * clock-stretch hardware feature supporting a slave slow device + * that may hold off the master by holding the clock line low. + * + * @sa ADI_I2C_CFG_DIV_LOW + */ +#define ADI_I2C_CFG_DIV_HIGH (25) + +/*! Standard Clock divider Clock-LO setting + * + * @sa ADI_I2C_CFG_DIV_HIGH + */ +#define ADI_I2C_CFG_DIV_LOW (31) + +/*! Shared control reset START/STOP detect circuit.\n + 1 - Reset the SCL and SDA synchronizers, START/STOP detect logic, and LINEBUSY detect logic.\n + 0 - Do nothing. */ +#define ADI_I2C_CFG_SHCTL_RST (0) + +/*! Timing control filter disable.\n + 1 - Disable digital input clock filter.\n + 0 - Enable digital input clock filter (1 PCLK). */ +#define ADI_I2C_CFG_TCTL_FILTEROFF (0) + +/*! Timing control data input hold time requirement to recognize START/STOP condition (5-bit max).\n + Value - Minimum data input hold time count in units of PCLK period. (Value = Thd/PCLK-period) */ +#define ADI_I2C_CFG_TCTL_THDATIN (1) + +/*! Master automatic stretch mode duration (4-bit), e.g., (in binary):\n + - 0b0000 - No SCL clock stretching.\n + - 0b0001 - Timeout after hold SCL LOW 2^1 = 2 bit-times.\n + - 0b0010 - Timeout after hold SCL LOW 2^2 = 4 bit-times.\n + - ...\n + - 0b1110 - Timeout after hold SCL LOW 2^14 = 16,384 bit-times.\n + - 0b1111 - Hold SCL LOW with no timeout.\n +\n + Where "bit-time" is computed by CLKDIV values and incoming UCLK (see HRM). */ +#define ADI_I2C_CFG_ASTRETCH_MST (0) + +/*! Unformatted, 7-bit max width I2C "7-bit Addressing" slave device address value (unshifted and excluding R/W direction bit).\n + For example, the value:\n + 0x50 - Is the "raw" (unencoded) slave address for the "Aardvark Activity Board" ATMEL AT24C02 I2C slave EEPROM device.\n + It is encoded (upshifted by one and ORed with R/W direction bit) on the I2C bus as:\n + - 0xA0 for write operations, or\n + - 0xA1 for read operations */ +#define ADI_I2C_CFG_SLAVE_ADDRESS (0x50) + + +/***********************************\ +|* Check for overflowing values... *| +\***********************************/ + +#if (ADI_I2C_CFG_MCTL_MXMITDEC >> 1) +#error "Decrement TX FIFO status config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_IENCMP >> 1) +#error "Transaction complete (STOP) interrupt enable config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_IENACK >> 1) +#error "NACK interrupt enable config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_IENALOST >> 1) +#error "ALOST interrupt enable config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_STRETCHSCL >> 1) +#error "Clock stretch enable config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_LOOPBACK >> 1) +#error "Loopback enable config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_COMPLETE >> 1) +#error "Start back-off disable config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_MASEN >> 1) +#error "Master device enable config value too wide" +#endif + +#if (ADI_I2C_CFG_DIV_HIGH >> 8) +#error "Clock HIGH time config value too wide" +#endif + +#if (ADI_I2C_CFG_DIV_LOW >> 8) +#error "Clock LOW time config value too wide" +#endif + +#if (ADI_I2C_CFG_SHCTL_RST >> 1) +#error "Shared control reset config value too wide" +#endif + +#if (ADI_I2C_CFG_TCTL_FILTEROFF >> 1) +#error "Timing control filter-off config value too wide" +#endif + +#if (ADI_I2C_CFG_TCTL_THDATIN >> 5) +#error "Timing control filter-off config value too wide" +#endif + +#if (ADI_I2C_CFG_ASTRETCH_MST >> 4) +#error "Master clock stretch config value too wide" +#endif + +#if (ADI_I2C_CFG_SLAVE_ADDRESS >> 7) +#error "Slave address config value too wide" +#endif + +/*! @} */ + +#endif /* ADI_I2C_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_pwr_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_pwr_config.h new file mode 100755 index 0000000000..11207b9947 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_pwr_config.h @@ -0,0 +1,638 @@ +/* + ***************************************************************************** + @file: adi_pwr_config.h + @brief: Configuration options for PWR driver. + This is specific to the PWR driver and will be included by the source file. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_PWR_CONFIG_H +#define ADI_PWR_CONFIG_H +#include +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions. +* +* Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters. +* The YODA-generated headers rely on more. The IAR compiler supports that. +*/ +#pragma diag_suppress=Pm009 +#endif /* __ICCARM__ */ + +/** @addtogroup PWR_Driver_Config Static Configuration + * @ingroup Power_Driver + * @{ + */ + +/*! Enable the code to support input clock through the GPIO pin + 0 - No support for input clock through the GPIO pin. + 1 - Support for input clock through the GPIO pin. + +*/ +#define ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO 0 + +/*------------------------------------------------------------------------------- + Set of MACROs for configuring the clock +--------------------------------------------------------------------------------*/ +/* Oscillator Control Register */ + +/*! + 32 KHz clock select mux. This clock connects to beeper, RTC.\n + 0 - Internal 32 KHz oscillator is selected.\n + 1 - External 32 KHz crystal is selected.. +*/ +#define ADI_PWR_LF_CLOCK_MUX 0 + + +/*! + High frequency internal oscillator enable\n + 0 - The HFOSC oscillator is disabled and placed in a low power state\n + 1 - The HFOSC oscillator is enabled. +*/ +#define ADI_PWR_HFOSC_CLOCK_ENABLE 1 + +/*! + Low frequency external oscillator enable and placed in a low power state\n + 0 - The LFXTAL oscillator is disabled\n + 1 - The LFXTAL oscillator is enabled. +*/ +#define ADI_PWR_LFXTAL_CLOCK_ENABLE 0 + +/*! + High frequency external oscillator enable\n + 0 - The HFXTAL oscillator is disabled and placed in a low power state\n + 1 - The HFXTAL oscillator is enabled. +*/ +#define ADI_PWR_HFXTAL_CLOCK_ENABLE 0 + +/*! + Low frequency external clock fail interrupt enable \n + 0 - The LFXTAL clock monitor and clock fail interrupt disabled \n + 1 - The LFXTAL clock monitor and clock fail interrupt enabled. +*/ +#define ADI_PWR_LFXTAL_CLOCK_MON_ENABLE 0 + +/*! + Automatic switching of the LF Mux to LF Oscillator on LFXTAL failure. \n + 0 - Disables Automatic switching of LF Mux to LF Oscillator on LFXTAL failure \n + 1 - Disables Automatic switching of LF Mux to LF Oscillator on LFXTAL failure. +*/ +#define ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE 0 + +/*! + Low frequency crystal Robust mode enable. The Robust mode enables the LFXTAL oscillator to work also when an + additional resistive load is placed between the crystal pins and GND. \n + 0 - Selects Normal mode \n + 1 - Selects Robust mode +*/ +#define ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE 0 + +/*! + Low frequency crystal Robust mode load select. The amount of loading tolerated when robust mode is enabled. \n + 0 - No Trim, and big resistive loads not tolerated. \n + 1 - 20 Mohm load mode, greater than 20 Mohm load allowed. \n + 2 - 10 Mohm load mode, greater than 10 Mohm load allowed. \n + 3 - 5 Mohm load mode, 5 Mohm load allowed on both IO pins. +*/ +#define ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT 0 + + +/*! + Root clock monitor and Clock Fail interrupt enable. + 0 - Disable Root Clock Monitor and Clock Fail interrupt. + 1 - Enable Root Clock Monitor and Clock Fail interrupt. +*/ +#define ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE 0 + + +/*! + Enable Auto switch to High Frequency Oscillator (HFOSC) when Root Clock Fails. + 0 - Disable Automatic switching of the Root Clock. + 1 - Enable Automatic switching of the Root Clock. +*/ +#define ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE 0 + + +/********** Miscellaneous clock setting register CTL0 *************/ + +/*! + Selecting the input clock for Root Clock mux. Determines which single shared clock source + is used by the PCLK, and HCLK dividers. \n + 0 - HFOSC High frequency internal oscillator \n + 1 - HFXTAL High frequency external oscillator\n + 2 - SPLL Output of System PLL is selected\n + 3 - External GPIO port is selected +*/ +#define ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX 0 + +/*! + GPIO clock out select. Selects the clock to be routed to the GPIO clock out pin. \n + 0 - Root Clock (ROOT_CLK)\n + 1 - Low Frequency Clock (LF_CLK) \n + 2 - ADC Clock (ACLK) \n + 3 - HCLK_BUS \n + 4 - HCLK_CORE \n + 5 - Peripheral Clock (PCLK) + 6 - Reference Clock for Flash controller timer (RCLK)\n + 7 - Mux of HFOSC, HFXTAL clock (RHP_CLK)\n + 8 - GP Timer 0 clock (GPT0_CLK)\n + 9 - GP Timer 1 clock (GPT1_CLK)\n + 10 - Peripherals operating at HCLK (HCLK_P)\n + 11 - PLL Clock out (PCLK)\n + 12 - RTC0 Clock \n + 13 - HP Buck Clock (HPBUCK_CLK)\n + 14 - HP Buck Non overlap clock\n + 15 - RTC1 generated clock +*/ +#define ADI_PWR_GPIO_CLOCK_OUT_SELECT 0 + +/*! + Flash reference clock and HPBUCK clock source mux. \n + 0 - sourcing from HFOSC (High frequency internal oscillator) \n + 2 - sourcing from external HFXTAL( High frequency external oscillator 26M Hz )\n + 3 - sourcing from external HFXTAL( High frequency external oscillator 16M Hz ) + +*/ +#define ADI_PWR_INPUT_TO_RCLK_MUX 0 + +/*! + Selecting the input clock for the system PLL clock. \n + 0 - sourcing from HFOSC (High frequency internal oscillator) \n + 1 - sourcing from HFXTAL(High frequency external oscillator) \n + 2 - GPIO Input clock. \n + 3 - GPIO Input clock. +*/ +#define ADI_PWR_INPUT_TO_SPLL_MUX 0 + +/*! + External Low frequency crystal interrupt enable.\n + 0 - Disable the interrupt for LF clock \n + 1 - Enable the interrupt for LF clock +*/ +#define ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE 0 + +/*! + External Hight frequency crystal interrupt enable.\n + 0 - Disable the interrupt for HFXTAL clock \n + 1 - Enable the interrupt for HFXTAL clock +*/ +#define ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE 0 + + + +/********** Clock divider register CTL1 ***************/ + +/*! + HCLK divide count.Determines the HCLK rate based on the following equation: HCLK = ROOT_CLK/HCLKDIVCNT. + 0 - 63 is valid range. +*/ +#define ADI_PWR_HCLK_DIVIDE_COUNT 4 + +/*! + PCLK divide count.Determines the PCLK rate based on the following equation: PCLK = ROOT_CLK/PCLKDIVCNT. + 0 - 63 is valid range. +*/ +#define ADI_PWR_PCLK_DIVIDE_COUNT 4 + +/*! + ACLK divide count.Determines the ACLK rate based on the following equation: ACLK = ROOT_CLK/ACLKDIVCNT. + 0 - 63 is valid range. +*/ +#define ADI_PWR_ACLK_DIVIDE_COUNT 16 + + +/************* HF Oscillator divide clock select register CTL2 ***********/ + +/*! + HF Oscillator auto divide by one clock selection during wakeup from Flexi power mode. + + When enabled enabled (Set to 1), the frequency undivided 26MHz HF oscillator clock itself will be used during the wake up. + The undivided HFOSC clock is selected automatically by clearing the HFOSCDIVCLKSEL register content to 0, which selects the HFOSC/1 clock.This updated divided by 1 clock selection will remain same until the new divider value is written to this register. + + When disabled (Set to 0), this fast wake up feature will be disabled and the HFOSCDIVCLKSEL register will remain unchanged + during the wakeup. + + 0 - Auto select HFOSC/1 clock during wakeup from Flexi mode is disable. + 1 - Auto select HFOSC/1 clock during wakeup from Flexi mode is enabled. +*/ +#define ADI_PWR_HFOSC_AUTO_DIV_BY_1 0 + +/*! + HF Oscillator divide select. + 0 - HFOSC/1. \n + 1 - HFOSC/2. \n + 2 - HFOSC/4. \n + 3 - HFOSC/8. \n + 4 - HFOSC/16. \n + 5 - HFOSC/32. +*/ +#define ADI_PWR_HFOSC_DIVIDE_SELECT 0 + + + +/****** System PLL Register CTL3 *****/ +/*! + System PLL N multiplier(SPLL_NSEL). Sets the N value used to obtain the multiplication + factor N/M of the PLL. + 8 - 31 is valid range. +*/ +#define ADI_PWR_SPLL_MUL_FACTOR 26 + +/*! + System PLL division by 2. Controls if an optional divide by two is placed on the PLL output.\n + 0 - The System PLL is not divided. Its output frequency equals that selected by the N/M ratio \n + 1 - The System PLL is divided by two. Its output frequency equals that selected by the N/M ratio + with an additional divide by 2 +*/ +#define ADI_PWR_SPLL_ENABLE_DIV2 0 + +/*! + System PLL enable. Controls if the PLL should be enabled or placed in its low power state. \n + 0 - The system PLL is disabled and is in its power down state\n + 1 - The system PLL is enabled. +*/ +#define ADI_PWR_SPLL_ENABLE 0 + +/*! + System PLL interrupt enable.Controls if the core should be interrupted on a PLL lock/PLL unlock or no interrupt generated.\n + 0 - Disable the SPLL interrupt generation\n + 1 - Enable the SPLL interrupt generation +*/ +#define ADI_PWR_SPLL_INTERRUPT_ENABLE 0 + +/*! + System PLL M Divider(SPLL_MSEL). Sets the M value used to obtain the multiplication + factor N/M of the PLL. + 2 - 15 is valid range. +*/ +#define ADI_PWR_SPLL_DIV_FACTOR 13 + +/*! + system PLL multiply by 2. This bit is used to configure if the VCO clock frequency should be multiplied by 2 or 1.\n + 0 - The System PLL is multiplied by 1.\n + 1 - The System PLL is multiplied by 2. +*/ +#define ADI_PWR_SPLL_ENABLE_MUL2 0 + + +/********** User Clock Gating Control CTL5 ********************/ + +/*! + This can be used to enable/disable clock to GPT0. \n + 0 - Disable the clock to GPT0\n + 1 - Enable the clock to GPT0 +*/ +#define ADI_PWR_GPT0_CLOCK_ENABLE 1 + +/*! + This can be used to enable/disable clock to GPT1. \n + 0 - Disable the clock to GPT1\n + 1 - Enable the clock to GPT1 +*/ +#define ADI_PWR_GPT1_CLOCK_ENABLE 1 +/*! + This can be used to enable/disable clock to GPT2. \n + 0 - Disable the clock to GPT2\n + 1 - Enable the clock to GPT2 +*/ +#define ADI_PWR_GPT2_CLOCK_ENABLE 1 + +/*! + This can be used to enable/disable clock to I2C. \n + 0 - Disable the clock to I2C\n + 1 - Enable the clock to I2C +*/ +#define ADI_PWR_I2C_CLOCK_ENABLE 1 + +/*! + This can be used to enable/disable clock to GPIO. \n + 0 - Disable the clock to GPIO\n + 1 - Enable the clock to GPIO +*/ +#define ADI_PWR_GPIO_CLOCK_ENABLE 1 + + +/*! + This can be used to enable/disable all clocks connected to peripherals. \n + 0 - Disable the Clock supply to peripherals\n + 1 - Enable the Clock supply to peripherals +*/ +#define ADI_PWR_PCLK_ENABLE 0 + + +/*! + This can be used to enable/disable clocks to Timer RGB. \n + 0 - Disable the Clock supply to Timer RGB \n + 1 - Enable the Clock supply to Timer RGB +*/ +#define ADI_PWR_TIMER_RGB_ENABLE 1 + +/*------------------------------------------------------------------------------- + Set of macros for configuring the power management module +--------------------------------------------------------------------------------*/ + +/********* Interrupt enable register IEN ********/ + +/*! + Enabling the interrupt if the Battery voltage falls below 1.8V.\n + 0 - Disable Battery voltage interrupt \n + 1 - Enable Battery voltage interrupt. +*/ +#define ADI_PWR_ENABLE_VBAT_INTERRUPT 0 + +/*! + Enabling the interrupt for under VREG voltage (i.e less than 1V).\n + 0 - Disable VREG under voltage interrupt \n + 1 - Enable VREG under voltage interrupt. +*/ +#define ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT 0 + +/*! + Enabling the interrupt for over VREG voltage (i.e above than 1.32V).\n + 0 - Disable VREG over voltage interrupt \n + 1 - Enable VREG over voltage interrupt. +*/ +#define ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT 0 + +/*! + Enabling the interrupt for Battery range.\n + 0 - Disable battery voltage range interrupt \n + 1 - Enable battery voltage range interrupt +*/ +#define ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT 0 + +/*! + Battery voltage range for generating the interrupt.\n + 0 - Configure to generate interrupt if VBAT > 2.75V \n + 1 - Configure to generate interrupt if VBAT is between 2.75 and 1.6V \n + 2 - Configure to generate interrupt if VBAT is between 2.3V and 1.6V +*/ +#define ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT 0 + +/********* HP Buck control register CTL1 ********/ +/*! + Enable or disable HP Buck.\n + 0 - Disable HP Buck. + 1 - Enable HP Buck. +*/ +#define ADI_PWR_HP_BUCK_ENABLE 0 + +/*! + HP Buck Load mode.\n + 0 - HP Buck low load mode. Can be set when the system is running at + less than 26 Mhz. \n + 1 - HP Buck High load mode. Can be set when the system is running at + more than 26 Mh. +*/ +#define ADI_PWR_HP_BUCK_LOAD_MODE 0 + +/*! + HP Buck low power mode.\n + The HPBUCK Low Power mode can be selected, when the Chip is in Flexi Power mode + and low power modules such as Timer, Beeper only are enabled + + 0 - HPBUCK Low power mode is disabled. \n + 1 - HPBUCK Low power mode is enabled. +*/ +#define ADI_PWR_HP_BUCK_LOW_POWER_MODE 0 + + +/********* Power mode register ********/ + +/*! + Enable or disable monitoring battery voltage (VBAT) during HIBERNATE Mode. \n + 0 - Battery voltage monitoring is enabled. + 1 - Battery voltage monitoring is disabled. + + By default battery voltage monitoring during hibernate is enabled. +*/ +#define ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING 0 + + +/******************************************************************************* + M A C R O V A L I D A T I O N +*******************************************************************************/ + +#if ( ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO > 1 ) +#error "Invalid configuration set for ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO" +#endif + +#if ( ADI_PWR_LF_CLOCK_MUX > 1 ) +#error "Invalid configuration set for ADI_PWR_LF_CLOCK_MUX" +#endif + +#if ( ADI_PWR_HFOSC_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_HFOSC_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_LFXTAL_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_LFXTAL_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_HFXTAL_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_HFXTAL_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_LFXTAL_CLOCK_MON_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_LFXTAL_CLOCK_MON_ENABLE" +#endif + +#if ( ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE" +#endif + +#if ( ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE" +#endif + +#if ( ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT > 3 ) +#error "Invalid configuration set for ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT" +#endif + +#if ( ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE" +#endif + +#if ( ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE" +#endif + +#if ( ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX > 3 ) +#error "Invalid configuration set for ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX" +#endif + +#if ( ADI_PWR_GPIO_CLOCK_OUT_SELECT > 15 ) +#error "Invalid configuration set for ADI_PWR_GPIO_CLOCK_OUT_SELECT" +#endif + +#if ( ADI_PWR_INPUT_TO_RCLK_MUX > 3 ) +#error "Invalid configuration set for ADI_PWR_INPUT_TO_RCLK_MUX" +#endif + +#if ( ADI_PWR_INPUT_TO_SPLL_MUX > 3 ) +#error "Invalid configuration set for ADI_PWR_INPUT_TO_SPLL_MUX" +#endif + +#if ( ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE" +#endif + +#if ( ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE" +#endif + +#if ( ADI_PWR_HCLK_DIVIDE_COUNT > 63 ) +#error "Invalid configuration set for ADI_PWR_HCLK_DIVIDE_COUNT" +#endif + +#if ( ADI_PWR_PCLK_DIVIDE_COUNT > 63 ) +#error "Invalid configuration set for ADI_PWR_PCLK_DIVIDE_COUNT" +#endif + +#if ( ADI_PWR_ACLK_DIVIDE_COUNT > 63 ) +#error "Invalid configuration set for ADI_PWR_ACLK_DIVIDE_COUNT" +#endif + +#if ( ADI_PWR_HFOSC_AUTO_DIV_BY_1 > 1 ) +#error "Invalid configuration set for ADI_PWR_HFOSC_AUTO_DIV_BY_1" +#endif + +#if ( ADI_PWR_HFOSC_DIVIDE_SELECT > 5 ) +#error "Invalid configuration set for ADI_PWR_HFOSC_DIVIDE_SELECT" +#endif + +#if ( ADI_PWR_SPLL_MUL_FACTOR < 8 || ADI_PWR_SPLL_MUL_FACTOR > 31 ) +#error "Invalid configuration set for ADI_PWR_SPLL_MUL_FACTOR" +#endif + +#if ( ADI_PWR_SPLL_ENABLE_DIV2 > 1 ) +#error "Invalid configuration set for ADI_PWR_SPLL_ENABLE_DIV2" +#endif + +#if ( ADI_PWR_SPLL_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_SPLL_ENABLE" +#endif + +#if ( ADI_PWR_SPLL_INTERRUPT_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_SPLL_INTERRUPT_ENABLE" +#endif + +#if ( ADI_PWR_SPLL_DIV_FACTOR < 2 || ADI_PWR_SPLL_DIV_FACTOR > 15 ) +#error "Invalid configuration set for ADI_PWR_SPLL_DIV_FACTOR" +#endif + +#if ( ADI_PWR_SPLL_ENABLE_MUL2 > 1 ) +#error "Invalid configuration set for ADI_PWR_SPLL_ENABLE_MUL2" +#endif + +#if ( ADI_PWR_GPT0_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_GPT0_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_GPT1_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_GPT1_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_GPT2_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_GPT2_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_I2C_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_I2C_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_GPIO_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_GPIO_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_PCLK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_PCLK_ENABLE" +#endif + +#if ( ADI_PWR_TIMER_RGB_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_TIMER_RGB_ENABLE" +#endif + +#if ( ADI_PWR_ENABLE_VBAT_INTERRUPT > 1 ) +#error "Invalid configuration set for ADI_PWR_ENABLE_VBAT_INTERRUPT" +#endif + +#if ( ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT > 1 ) +#error "Invalid configuration set for ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT" +#endif + +#if ( ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT > 1 ) +#error "Invalid configuration set for ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT" +#endif + +#if ( ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT > 1 ) +#error "Invalid configuration set for ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT" +#endif + +#if ( ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT > 2 ) +#error "Invalid configuration set for ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT" +#endif + +#if ( ADI_PWR_HP_BUCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_HP_BUCK_ENABLE" +#endif + +#if ( ADI_PWR_HP_BUCK_LOAD_MODE > 1 ) +#error "Invalid configuration set for ADI_PWR_HP_BUCK_LOAD_MODE" +#endif + +#if ( ADI_PWR_HP_BUCK_LOW_POWER_MODE > 1 ) +#error "Invalid configuration set for ADI_PWR_HP_BUCK_LOW_POWER_MODE" +#endif + +#if ( ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING > 1 ) +#error "Invalid configuration set for ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING" +#endif + + + +/*! @} */ + +#ifdef __ICCARM__ +#pragma diag_default=Pm009 +#endif /* __ICCARM__ */ + +#endif /* ADI_PWR_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rng_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rng_config.h new file mode 100755 index 0000000000..76afe147cf --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rng_config.h @@ -0,0 +1,106 @@ +/*! + ***************************************************************************** + @file: adi_rng_config.h + @brief: Configuration options for RNG driver. + This is specific to the RNG driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_RNG_CONFIG_H__ +#define ADI_RNG_CONFIG_H__ +#include +/** @defgroup RNG_Driver_Cfg RNG Driver Configuration + * @ingroup RNG_Driver + + */ + +/*! \addtogroup RNG_Driver_Cfg RNG Driver Configuration + * @{ + */ + +/************* RNG Driver configurations ***************/ + +/************* RNG controller configurations ***************/ + +/*! RNG Control Register, bit 3\n + Enable only 8-bit generation\n + 0 - Generate 32-bit random number\n + 1 - Generate only 8-bit random number +*/ +#define RNG0_CFG_ONLY_8_BIT 1 + +/*! RNG Sample Length Register, bits [11:0]\n + The register defines the number of samples to accumulate in the + CRC register when generating a random number.\n + + Bits [11:0] contains the reload value of the sample counter + + */ +#define RNG0_CFG_LENGTH_RELOAD 256u + +/*! RNG Sample Length Register, bits [15:12]\n + The register defines the number of samples to accumulate in the + CRC register when generating a random number. The number of values + accumulated in the counter reload value is scaled by 2^prescaler.\n + + Bits [15:12] contains the prescaler for the sample counter + + */ +#define RNG0_CFG_LENGTH_PRESCALER 0u + +/************** Macro validation *****************************/ + +#if ( RNG0_CFG_ONLY_8_BIT > 1 ) +#error "Invalid configuration" +#endif + +#if ( RNG0_CFG_LENGTH_RELOAD > 4095u ) +#error "Invalid value for reload" +#endif + +#if ( RNG0_CFG_LENGTH_PRESCALER > 10u ) +#error "Invalid value for prescaler" +#endif + +/*! @} */ + +#endif /* __ADI_RNG_CONFIG_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rtc_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rtc_config.h new file mode 100755 index 0000000000..ef97a3b0a4 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rtc_config.h @@ -0,0 +1,397 @@ +/*! + ***************************************************************************** + @file: adi_rtc_config.h + @brief: Configuration options for Real Time Clock device driver. + This is specific to the RTC driver and will be included by the driver. + It is not required for the application to include this header file. + @version: $Revision: 33005 $ + @date: $Date: 2015-12-12 10:43:13 -0500 (Sat, 12 Dec 2015) $ + ----------------------------------------------------------------------------- + +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_RTC_CONFIG_H__ +#define ADI_RTC_CONFIG_H__ +#include + +/** @addtogroup RTC_Driver_Config Static Configuration + * @ingroup RTC_Driver + * @{ + */ + +/*! + * The safe write mode insures any pending writes that have not yet synchronized between the faster core clock + * domain and the internal RTC 32kHz clock domain are reconciled before multiple writes to the same RTC register + * are allowed +*/ + +#define ADI_RTC_CFG_ENABLE_SAFE_WRITE 1 + + +/** @addtogroup RTC_Driver_Config_RTC0 RTC0 Static Configuration + * @ingroup RTC_Driver_Config + * @{ + */ + +/* +=================================================================== + ------------------------RTC-0 CONFIGURATION MACRO----------------- +=================================================================== +*/ +/*! Enable the Alarm */ +#define RTC0_CFG_ENABLE_ALARM 0 + +/*! Enable the Alarm interrupt*/ +#define RTC0_CFG_ENABLE_ALARM_INTERRUPT 0 + +/*! Enable the Trim */ +#define RTC0_CFG_ENABLE_TRIM 0 + +/*! Enable the PENDERROR interrupt*/ +#define RTC0_CFG_ENABLE_PENDERROR_INTERRUPT 0 + +/*! Enable the write sync interrupt*/ +#define RTC0_CFG_ENABLE_WSYNC_INTERRUPT 0 + +/*! Enable the pend write interrupt*/ +#define RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT 0 + +/*! Initial the count Value*/ +#define RTC0_CFG_COUNT_VALUE 0 + +/*! Initial the count Value-0*/ +#define RTC0_CFG_COUNT_VALUE_0 0 + +/*! Initial the count Value-1*/ +#define RTC0_CFG_COUNT_VALUE_1 0 + +/*! Alarm-0 Value*/ +#define RTC0_CFG_ALARM_VALUE_0 0 + +/*! Alarm-1 Value*/ +#define RTC0_CFG_ALARM_VALUE_1 0 + +/*! Trim interval*/ +#define RTC0_CFG_TRIM_INTERVAL 0 + +/*! Trim interval with power of 2*/ +#define RTC0_CFG_POW2_TRIM_INTERVAL 0 + +/*! Trim operation to be performed for RTC0*/ +#define RTC0_CFG_TRIM_OPERATION 0 + +/*! Trim Value for RTC-0*/ +#define RTC0_CFG_TRIM_VALUE 0 + +/*! GPIO Sample around Rising Edge of Sensor Strobe Channel 3. + * Enables sampling of Sensor Strobe GPIO inputs around rising edge of Sensor Strobe Channel 3 pulse. + * + * 0 No sampling of input around rising edge. + * 1 Input sampled one clock cycle before rising edge of Sensor Strobe. + * 10 Input sampled at rising edge of Sensor Strobe. + * 11 Input sampled one clock cycle after rising edge of Sensor Strobe. + */ +#define RTC0_SS3_SMPONRE 0 + +/*! GPIO Sample around Falling Edge of Sensor Strobe Channel 3. + * Enables sampling of Sensor Strobe GPIO inputs around falling edge of Sensor Strobe Channel 3 pulse. + * + * 0 No sampling of input around rising edge. + * 1 Input sampled one clock cycle before rising edge of Sensor Strobe. + * 10 Input sampled at rising edge of Sensor Strobe. + * 11 Input sampled one clock cycle after rising edge of Sensor Strobe. + */ +#define RTC0_SS3_SMPONFE 0 +/*! GPIO Sample around Falling Edge of Sensor Strobe Channel 2. */ +#define RTC0_SS2_SMPONFE 0 +/*! GPIO Sample around Rising Edge of Sensor Strobe Channel 1. */ +#define RTC0_SS1_SMPONRE 0 +/*! GPIO Sample around Falling Edge of Sensor Strobe Channel 1. */ +#define RTC0_SS1_SMPONFE 0 + + +/*! Sensor Strobe's GP Input Sampling Mux + * SS 2 GPIO Pin 1 + * + * GPMUX0/1.SSxGPINySEL 3’b000 3’b001 3’b010 3’b011 3’b100 3’b101 3’b110 3’b111 + * RTCSSxGPIny p0[12] p2[0] p0[9] p0[8] p1[13] p1[2] p2[7] p2[9] + */ +#define RTC0_SS2_GPIN1SEL 0x4 +/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 0*/ +#define RTC0_SS2_GPIN0SEL 0x3 +/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 2*/ +#define RTC0_SS1_GPIN2SEL 0x2 +/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 1*/ +#define RTC0_SS1_GPIN1SEL 0x1 +/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 0*/ +#define RTC0_SS1_GPIN0SEL 0x0 +/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 2*/ +#define RTC0_SS3_GPIN2SEL 0x0 +/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 1*/ +#define RTC0_SS3_GPIN1SEL 0x7 +/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 0*/ +#define RTC0_SS3_GPIN0SEL 0x6 +/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 2*/ +#define RTC0_SS2_GPIN2SEL 0x5 + +/*! Differential output option for Sensor Strobe channel 3. + * Sensor Strobe channel3 is used as differential signal, actual RTC_SS3 out + * for this channel is available in corresponding GPIO. + * RTC_SS4 of Sensor Strobe channel 4 is used to provided inverted signal of RTC_SS3. + */ +#define RTC0_SS3_DIFFOUT 0 +/*! Differential output option for Sensor Strobe channel 1. + * Sensor Strobe channel 1 is used as differential signal, actual RTC_SS1 out + * for this channel is available in corresponding GPIO. + * RTC_SS1 of Sensor Strobe channel 2 is used to provided inverted signal of RTC_SS1. + */ +#define RTC0_SS1_DIFFOUT 0 + + + +/*! @} */ + +/* +=================================================================== + ------------------------RTC-1 CONFIGURATION MACRO----------------- +=================================================================== +*/ + +/** @addtogroup RTC_Driver_Config_RTC1 RTC1 Static Configuration + * @ingroup RTC_Driver_Config + * @{ + */ + + + +/*! Enable the Alarm */ +#define RTC1_CFG_ENABLE_ALARM 0 + +/*! Enable the Alarm interrupt*/ +#define RTC1_CFG_ENABLE_ALARM_INTERRUPT 0 + +/*! Enable the Trim */ +#define RTC1_CFG_ENABLE_TRIM 0 + +/*! Enable the mod-60 Alarm */ +#define RTC1_CFG_ENABLE_MOD60_ALARM 0 + +/*! Enable the mod-60 Alarm period*/ +#define RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD 0 + +/*! Enable the Alarm interrupt*/ +#define RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT 0 + +/*! Enable the ISOINT interrupt*/ +#define RTC1_CFG_ENABLE_ISO_INTERRUPT 0 + +/*! Enable the PENDERROR interrupt*/ +#define RTC1_CFG_ENABLE_PENDERROR_INTERRUPT 0 + +/*! Enable the write sync interrupt*/ +#define RTC1_CFG_ENABLE_WSYNC_INTERRUPT 0 + +/*! Enable the pend write interrupt*/ +#define RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT 0 + +/*! Enable the RTC count interrupt*/ +#define RTC1_CFG_ENABLE_COUNT_INTERRUPT 0 + +/*! Enable the prescaled modulo-1 interrupt*/ +#define RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT 0 + +/*! Enable the Trim interrupt*/ +#define RTC1_CFG_ENABLE_TRIM_INTERRUPT 0 + +/*! Enable the Mod60 roll over interrupt*/ +#define RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT 0 + +/*! Prescale value for the RTC1*/ +#define RTC1_CFG_PRESCALE 0 + +/*! Enable the counter roll over interrupt*/ +#define RTC1_CFG_CNT_ROLLLOVER_INTERRUPT 0 + +/*! Initial the count Value-0*/ +#define RTC1_CFG_COUNT_VALUE_0 0 + +/*! Initial the count Value-1*/ +#define RTC1_CFG_COUNT_VALUE_1 0 + +/*! Alarm Value-0*/ +#define RTC1_CFG_ALARM_VALUE_0 0 + +/*! Alarm Value-1*/ +#define RTC1_CFG_ALARM_VALUE_1 0 + +/*! Alarm Value-2*/ +#define RTC1_CFG_ALARM_VALUE_2 0 + +/*! Trim interval*/ +#define RTC1_CFG_TRIM_INTERVAL 0 + +/*! Trim interval with power of 2*/ +#define RTC1_CFG_POW2_TRIM_INTERVAL 0 + +/*! Trim operation to be performed for RTC1*/ +#define RTC1_CFG_TRIM_OPERATION 0 + +/*! Trim Value for RTC-1*/ +#define RTC1_CFG_TRIM_VALUE 0 + +/*! Enable the input capture channel-0*/ +#define RTC1_CFG_IC0_ENABLE 0 + +/*! Enable the input capture channel-2*/ +#define RTC1_CFG_IC2_ENABLE 0 + +/*! Enable the input capture channel-3*/ +#define RTC1_CFG_IC3_ENABLE 0 + +/*! Enable the input capture channel-4*/ +#define RTC1_CFG_IC4_ENABLE 0 + +/*! Enable the Sensor Strobe channel-1*/ +#define RTC1_CFG_SS1_ENABLE 0 +/*! Enable the Sensor Strobe channel-2*/ +#define RTC1_CFG_SS2_ENABLE 0 +/*! Enable the Sensor Strobe channel-3*/ +#define RTC1_CFG_SS3_ENABLE 0 +/*! Enable the Sensor Strobe channel-4*/ +#define RTC1_CFG_SS4_ENABLE 0 + +/*! Enable the interrupt for input capture channel-0*/ +#define RTC1_CFG_IC0_INT_ENABLE 0 + +/*! Enable the interrupt for input capture channel-2*/ +#define RTC1_CFG_IC2_INT_ENABLE 0 + +/*! Enable the interrupt for input capture channel-3*/ +#define RTC1_CFG_IC3_INT_ENABLE 0 + +/*! Enable the interrupt for input capture channel-4*/ +#define RTC1_CFG_IC4_INT_ENABLE 0 + +/*! Enable the over write input capture channels*/ +#define RTC1_CFG_IC_OVER_WRITE_ENABLE 0 + +/*! Polarity for input capture channel-0*/ +#define RTC1_CFG_IC0_EDGE_POLARITY 0 + +/*! Polarity for input capture channel-2*/ +#define RTC1_CFG_IC2_EDGE_POLARITY 0 + +/*! Polarity for input capture channel-3*/ +#define RTC1_CFG_IC3_EDGE_POLARITY 0 + +/*! Polarity for input capture channel-4*/ +#define RTC1_CFG_IC4_EDGE_POLARITY 0 + +/*! Enable the interrupt for Sensor Strobe channel-1*/ +#define RTC1_CFG_SS1_INT_ENABLE 0 +/*! Enable the interrupt for Sensor Strobe channel-2*/ +#define RTC1_CFG_SS2_INT_ENABLE 0 +/*! Enable the interrupt for Sensor Strobe channel-3*/ +#define RTC1_CFG_SS3_INT_ENABLE 0 +/*! Enable the interrupt for Sensor Strobe channel-4*/ +#define RTC1_CFG_SS4_INT_ENABLE 0 + +/*! Enable the masking for Sensor Strobe channel-1*/ +#define RTC1_CFG_SS1_MASK_ENABLE 0 +/*! Enable the masking for Sensor Strobe channel-2*/ +#define RTC1_CFG_SS2_MASK_ENABLE 0 +/*! Enable the masking for Sensor Strobe channel-3*/ +#define RTC1_CFG_SS3_MASK_ENABLE 0 +/*! Enable the masking for Sensor Strobe channel-4*/ +#define RTC1_CFG_SS4_MASK_ENABLE 0 + +/*! Enable the auto-reloading for Sensor Strobe channel-0*/ +#define RTC1_CFG_SS1_AUTO_RELOADING_ENABLE 0 + +/*! Mask for Sensor Strobe channel-0 */ +#define RTC1_CFG_SS1_MASK_VALUE 0 + + +/*! Auto reload value for Sensor Strobe channel-0 */ +#define RTC1_CFG_SS1_AUTO_RELOAD_VALUE 32768/2 + + +/*! Sensor Strobe GP Input Sampling Mux + * SS2 GPIO Pin 1 + * + * GPMUX0/1.SSxGPINySEL 3’b000 3’b001 3’b010 3’b011 3’b100 3’b101 3’b110 3’b111 + * RTCSSxGPIny p0[12] p2[0] p0[9] p0[8] p1[13] p1[2] p2[7] p2[9] + */ +#define RTC1_SS2_GPIN1SEL 0x4 +/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 0*/ +#define RTC1_SS2_GPIN0SEL 0x3 +/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 2*/ +#define RTC1_SS1_GPIN2SEL 0x2 +/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 1*/ +#define RTC1_SS1_GPIN1SEL 0x1 +/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 0*/ +#define RTC1_SS1_GPIN0SEL 0x0 +/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 2*/ +#define RTC1_SS3_GPIN2SEL 0x0 +/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 1*/ +#define RTC1_SS3_GPIN1SEL 0x7 +/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 0*/ +#define RTC1_SS3_GPIN0SEL 0x6 +/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 2*/ +#define RTC1_SS2_GPIN2SEL 0x5 + +/*! Differential output option for Sensor Strobe channel 3. + * Sensor Strobe channel3 is used as differential signal, actual RTC_SS3 out + * for this channel is available in corresponding GPIO. + * RTC_SS4 of Sensor Strobe channel 4 is used to provided inverted signal of RTC_SS3. + */ +#define RTC1_SS3_DIFFOUT 0 +/*! Differential output option for Sensor Strobe channel 1. + * Sensor Strobe channel 1 is used as differential signal, actual RTC_SS1 out + * for this channel is available in corresponding GPIO. + * RTC_SS1 of Sensor Strobe channel 2 is used to provided inverted signal of RTC_SS1. + */ +#define RTC1_SS1_DIFFOUT 0 + + +/*! @} */ + +/*! @} */ +#endif /* ADI_RTC_CONFIG_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_spi_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_spi_config.h new file mode 100755 index 0000000000..e2a8ccd572 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_spi_config.h @@ -0,0 +1,592 @@ +/*! + ***************************************************************************** + @file: adi_spi_config.h + @brief: Configuration options for SPI driver. + This is specific to the SPI driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_SPI_CONFIG_H__ +#define ADI_SPI_CONFIG_H__ +#include +/** @addtogroup SPI_Driver_Config Static Configuration + * @ingroup SPI_Driver + * @{ + */ + + +/*! Set this macro to the system clock frequency in hertz*/ +#define ADI_CFG_SYSTEM_CLOCK_HZ (26000000u) + +/************* SPI controller configurations ***************/ + +/* There are three SPI instances SPI0, SPI1 and SPI2 */ +/* Each SPI has its own configuration macros */ + + +/*----------------------------------------------------------*/ +/* -------------------- SPI0 -------------------------------*/ +/*----------------------------------------------------------*/ + +/** @addtogroup SPI_Driver_Config_SPI0 SPI0 Static Configuration + * @ingroup SPI_Driver_Config + * @{ + */ + + /*! If using SPI0 in master mode set this macro to 1. For slave mode set this macro to 0. */ +#define ADI_SPI0_MASTER_MODE (1u) + + +/*! Set this macro to the SPI0 bit rate in hertz */ +#define ADI_SPI0_CFG_BIT_RATE (2000000u) + +/*! SPI0 enable\n + SPI configuration register: Bit[0]\n + 1 - Enable SPI\n + 0 - Disable SPI */ +#define ADI_SPI0_CFG_ENABLE (0u) + +/*! SPI0 clock phase mode\n + SPI configuration register: Bit[2]\n + 1 - Serial clock pulses at the beginning of each serial bit transfer.\n + 0 - Serial clock pulses at the end of each serial bit transfer. */ +#define ADI_SPI0_CFG_CLK_PHASE (0u) + + + + + +/*! SPI0 clock polarity\n + SPI configuration register: Bit[3]\n + 1 - Serial clock idles high.\n + 0 - Serial clock idles low. */ +#define ADI_SPI0_CFG_CLK_POLARITY (0u) + + +/*! SPI0 wired OR mode\n + SPI configuration register: Bit[4]\n + 1 - Enables open circuit output enable.\n + 0 - Normal output levels. */ +#define ADI_SPI0_CFG_WIRED_OR (0u) + + +/*! SPI0 LSB/MSB\n + SPI configuration register: Bit[5]\n + 1 - MSB transmitted first.\n + 0 - LSB transmitted first. */ +#define ADI_SPI0_CFG_LSB_MSB (0u) + + +/*! SPI0 transfer initiate\n + SPI configuration register: Bit[6]\n + 1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n + 0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/ +#define ADI_SPI0_CFG_TRANSFER_INITIATE (0u) + + +/*! SPI0 Tx FIFO transfers zeros or last bit upon underflow\n + SPI configuration register: Bit[7]\n + 1 - Tx FIFO sends zeros upon underflow.\n + 0 - Tx FIFO repeats last bit upon underflow. */ +#define ADI_SPI0_CFG_TX_UNDERFLOW (0u) + + +/*! SPI0 Rx FIFO overflows with received data or data is discarded\n + SPI configuration register: Bit[8]\n + 1 - Rx FIFO receives data upon overflow.\n + 0 - Rx FIFO discards received data upon overflow. */ +#define ADI_SPI0_CFG_RX_OVERFLOW (0u) + + +/*! SPI0 slave mode MISO enable\n + SPI configuration register: Bit[9]\n + 1 - MISO operates as normal in slave mode.\n + 0 - MISO is disabled in slave mode. */ +#define ADI_SPI0_CFG_MISO_ENABLE (0u) + + +/*! SPI0 internal loopback enable\n + SPI configuration register: Bit[10]\n + 1 - MISO and MOSI is loopbacked internally.\n + 0 - MISO and MOSI operates normally. */ +#define ADI_SPI0_CFG_LOOPBACK (0u) + +/*! SPI0 transfer and interrupt mode\n + SPI configuration register: Bit[11]\n + 1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n + 0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/ +#define ADI_SPI0_CFG_CONTINUOUS (0u) + +/*! SPI0 Rx FIFO flush enable\n + SPI configuration register: Bit[12]\n + 1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n + 0 - Rx FIFO flush is disabled. */ +#define ADI_SPI0_CFG_RX_FLUSH (0u) + + +/*! SPI0 Tx FIFO flush enable\n + SPI configuration register: Bit[13]\n + 1 - Tx FIFO is flushed.\n + 0 - Tx FIFO flush is disabled. */ +#define ADI_SPI0_CFG_TX_FLUSH (0u) + + +/*! Reset Mode for CSERR. \n + SPI0 configuration register: Bit[14]\n + 0 - To continue from where it stopped. SPI can receive the remaining bits + when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n + 1 - To enable resetting the bit counter and reset if there is a + CS error condition and the Cortex is expected to clear the SPI_EN bit. +*/ +#define ADI_SPI0_CFG_CSERR_RESET (0u) + + +/*! SPI0 clock divide\n + SPI baud rate selection register: Bit[0:5]\n + Value between 0-63 that is used to divide the UCLK to generate + the SPI serial clock. */ +#define ADI_SPI0_CFG_CLK_DIV (0u) + + +/*! SPI0 high frequency mode\n + SPI baud rate selection register: Bit[6]\n + 1 - High frequency mode enabled.\n + 0 - High frequency mode disabled. */ +#define ADI_SPI0_CFG_HFM (0u) + + +/*! SPI0 reset mode for CSERR\n + SPI baud rate selection register: Bit[7]\n + 1 - clear bit counter on CS error.\n + 0 - do not clear bit counter on CS error. */ +#define ADI_SPI0_CFG_CS_ERR (0u) + + +/*! SPI0 CS interrupt\n + SPI baud rate selection register: Bit[8]\n + 1 - In continuous mode, generate interrupt on CS.\n + 0 - In continuous mode, do not generate interrupt on CS. */ +#define ADI_SPI0_CFG_CS_IRQ (0u) + + +/*! @} */ + +/*----------------------------------------------------------*/ +/* -------------------- SPI1 -------------------------------*/ +/*----------------------------------------------------------*/ + +/** @addtogroup SPI_Driver_Config_SPI1 SPI1 Static Configuration + * @ingroup SPI_Driver_Config + * @{ + */ + + /*! If using SPI1 in master mode set this macro to 1. For slave mode set this macro to 0. */ +#define ADI_SPI1_MASTER_MODE (1u) + +/*! Set this macro to the SPI1 bit rate in hertz */ +#define ADI_SPI1_CFG_BIT_RATE (2000000u) + +/*! SPI1 enable\n + SPI configuration register: Bit[0]\n + 1 - Enable SPI\n + 0 - Disable SPI */ +#define ADI_SPI1_CFG_ENABLE (0u) + +/*! SPI1 clock phase mode\n + SPI configuration register: Bit[2]\n + 1 - Serial clock pulses at the beginning of each serial bit transfer.\n + 0 - Serial clock pulses at the end of each serial bit transfer. */ +#define ADI_SPI1_CFG_CLK_PHASE (0u) + + + + + +/*! SPI1 clock polarity\n + SPI configuration register: Bit[3]\n + 1 - Serial clock idles high.\n + 0 - Serial clock idles low. */ +#define ADI_SPI1_CFG_CLK_POLARITY (0u) + + +/*! SPI1 wired OR mode\n + SPI configuration register: Bit[4]\n + 1 - Enables open circuit output enable.\n + 0 - Normal output levels. */ +#define ADI_SPI1_CFG_WIRED_OR (0u) + + +/*! SPI1 LSB/MSB\n + SPI configuration register: Bit[5]\n + 1 - MSB transmitted first.\n + 0 - LSB transmitted first. */ +#define ADI_SPI1_CFG_LSB_MSB (0u) + + +/*! SPI1 transfer initiate\n + SPI configuration register: Bit[6]\n + 1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n + 0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/ +#define ADI_SPI1_CFG_TRANSFER_INITIATE (0u) + + +/*! SPI1 Tx FIFO transfers zeros or last bit upon underflow\n + SPI configuration register: Bit[7]\n + 1 - Tx FIFO sends zeros upon underflow.\n + 0 - Tx FIFO repeats last bit upon underflow. */ +#define ADI_SPI1_CFG_TX_UNDERFLOW (0u) + + +/*! SPI1 Rx FIFO overflows with received data or data is discarded\n + SPI configuration register: Bit[8]\n + 1 - Rx FIFO receives data upon overflow.\n + 0 - Rx FIFO discards received data upon overflow. */ +#define ADI_SPI1_CFG_RX_OVERFLOW (0u) + + +/*! SPI1 slave mode MISO enable\n + SPI configuration register: Bit[9]\n + 1 - MISO operates as normal in slave mode.\n + 0 - MISO is disabled in slave mode. */ +#define ADI_SPI1_CFG_MISO_ENABLE (0u) + + +/*! SPI1 internal loopback enable\n + SPI configuration register: Bit[10]\n + 1 - MISO and MOSI is loopbacked internally.\n + 0 - MISO and MOSI operates normally. */ +#define ADI_SPI1_CFG_LOOPBACK (0u) + +/*! SPI1 transfer and interrupt mode\n + SPI configuration register: Bit[11]\n + 1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n + 0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/ +#define ADI_SPI1_CFG_CONTINUOUS (0u) + +/*! SPI1 Rx FIFO flush enable\n + SPI configuration register: Bit[12]\n + 1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n + 0 - Rx FIFO flush is disabled. */ +#define ADI_SPI1_CFG_RX_FLUSH (0u) + + +/*! SPI1 Tx FIFO flush enable\n + SPI configuration register: Bit[13]\n + 1 - Tx FIFO is flushed.\n + 0 - Tx FIFO flush is disabled. */ +#define ADI_SPI1_CFG_TX_FLUSH (0u) + + +/*! Reset Mode for CSERR. \n + SPI1 configuration register: Bit[14]\n + 0 - To continue from where it stopped. SPI can receive the remaining bits + when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n + 1 - To enable resetting the bit counter and reset if there is a + CS error condition and the Cortex is expected to clear the SPI_EN bit. +*/ +#define ADI_SPI1_CFG_CSERR_RESET (0u) + + +/*! SPI1 clock divide\n + SPI baud rate selection register: Bit[0:5]\n + Value between 0-63 that is used to divide the UCLK to generate + the SPI serial clock. */ +#define ADI_SPI1_CFG_CLK_DIV (0u) + + +/*! SPI1 high frequency mode\n + SPI baud rate selection register: Bit[6]\n + 1 - High frequency mode enabled.\n + 0 - High frequency mode disabled. */ +#define ADI_SPI1_CFG_HFM (0u) + + +/*! SPI1 reset mode for CSERR\n + SPI baud rate selection register: Bit[7]\n + 1 - clear bit counter on CS error.\n + 0 - do not clear bit counter on CS error. */ +#define ADI_SPI1_CFG_CS_ERR (0u) + + +/*! SPI1 CS interrupt\n + SPI baud rate selection register: Bit[8]\n + 1 - In continuous mode, generate interrupt on CS.\n + 0 - In continuous mode, do not generate interrupt on CS. */ +#define ADI_SPI1_CFG_CS_IRQ + +/*! @} */ + +/*----------------------------------------------------------*/ +/* -------------------- SPI2 -------------------------------*/ +/*----------------------------------------------------------*/ + +/** @addtogroup SPI_Driver_Config_SPI2 SPI2 Static Configuration + * @ingroup SP2_Driver_Config + * @{ + */ + +/*! If using SPI2 in master mode set this macro to 1. For slave mode set this macro to 0. */ +#define ADI_SPI2_MASTER_MODE (1u) + +/*! Set this macro to the SPI2 bit rate in hertz */ +#define ADI_SPI2_CFG_BIT_RATE (2000000u) + +/*! SPI2 enable\n + SPI configuration register: Bit[0]\n + 1 - Enable SPI\n + 0 - Disable SPI */ +#define ADI_SPI2_CFG_ENABLE (0u) + +/*! SPI2 clock phase mode\n + SPI configuration register: Bit[2]\n + 1 - Serial clock pulses at the beginning of each serial bit transfer.\n + 0 - Serial clock pulses at the end of each serial bit transfer. */ +#define ADI_SPI2_CFG_CLK_PHASE (0u) + + + + + +/*! SPI2 clock polarity\n + SPI configuration register: Bit[3]\n + 1 - Serial clock idles high.\n + 0 - Serial clock idles low. */ +#define ADI_SPI2_CFG_CLK_POLARITY (0u) + + +/*! SPI2 wired OR mode\n + SPI configuration register: Bit[4]\n + 1 - Enables open circuit output enable.\n + 0 - Normal output levels. */ +#define ADI_SPI2_CFG_WIRED_OR (0u) + + +/*! SPI2 LSB/MSB\n + SPI configuration register: Bit[5]\n + 1 - MSB transmitted first.\n + 0 - LSB transmitted first. */ +#define ADI_SPI2_CFG_LSB_MSB (0u) + + +/*! SPI2 transfer initiate\n + SPI configuration register: Bit[6]\n + 1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n + 0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/ +#define ADI_SPI2_CFG_TRANSFER_INITIATE (0u) + + +/*! SPI2 Tx FIFO transfers zeros or last bit upon underflow\n + SPI configuration register: Bit[7]\n + 1 - Tx FIFO sends zeros upon underflow.\n + 0 - Tx FIFO repeats last bit upon underflow. */ +#define ADI_SPI2_CFG_TX_UNDERFLOW (0u) + + +/*! SPI2 Rx FIFO overflows with received data or data is discarded\n + SPI configuration register: Bit[8]\n + 1 - Rx FIFO receives data upon overflow.\n + 0 - Rx FIFO discards received data upon overflow. */ +#define ADI_SPI2_CFG_RX_OVERFLOW (0u) + + +/*! SPI2 slave mode MISO enable\n + SPI configuration register: Bit[9]\n + 1 - MISO operates as normal in slave mode.\n + 0 - MISO is disabled in slave mode. */ +#define ADI_SPI2_CFG_MISO_ENABLE (0u) + + +/*! SPI2 internal loopback enable\n + SPI configuration register: Bit[10]\n + 1 - MISO and MOSI is loopbacked internally.\n + 0 - MISO and MOSI operates normally. */ +#define ADI_SPI2_CFG_LOOPBACK (0u) + +/*! SPI2 transfer and interrupt mode\n + SPI configuration register: Bit[11]\n + 1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n + 0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/ +#define ADI_SPI2_CFG_CONTINUOUS (0u) + +/*! SPI2 Rx FIFO flush enable\n + SPI configuration register: Bit[12]\n + 1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n + 0 - Rx FIFO flush is disabled. */ +#define ADI_SPI2_CFG_RX_FLUSH (0u) + + +/*! SPI2 Tx FIFO flush enable\n + SPI configuration register: Bit[13]\n + 1 - Tx FIFO is flushed.\n + 0 - Tx FIFO flush is disabled. */ +#define ADI_SPI2_CFG_TX_FLUSH (0u) + + +/*! Reset Mode for CSERR. \n + SPI2 configuration register: Bit[14]\n + 0 - To continue from where it stopped. SPI can receive the remaining bits + when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n + 1 - To enable resetting the bit counter and reset if there is a + CS error condition and the Cortex is expected to clear the SPI_EN bit. +*/ +#define ADI_SPI2_CFG_CSERR_RESET (0u) + + +/*! SPI2 clock divide\n + SPI baud rate selection register: Bit[0:5]\n + Value between 0-63 that is used to divide the UCLK to generate + the SPI serial clock. */ +#define ADI_SPI2_CFG_CLK_DIV (0u) + + +/*! SPI2 high frequency mode\n + SPI baud rate selection register: Bit[6]\n + 1 - High frequency mode enabled.\n + 0 - High frequency mode disabled. */ +#define ADI_SPI2_CFG_HFM (0u) + + +/*! SPI2 reset mode for CSERR\n + SPI baud rate selection register: Bit[7]\n + 1 - clear bit counter on CS error.\n + 0 - do not clear bit counter on CS error. */ +#define ADI_SPI2_CFG_CS_ERR (0u) + + +/*! SPI2 CS interrupt\n + SPI baud rate selection register: Bit[8]\n + 1 - In continuous mode, generate interrupt on CS.\n + 0 - In continuous mode, do not generate interrupt on CS. */ +#define ADI_SPI2_CFG_CS_IRQ + +/*! @} */ + +/************** Macro validation *****************************/ + +#if ( ADI_SPI0_CFG_BIT_RATE > (13000000u) ) || \ + ( ADI_SPI0_CFG_BIT_RATE > (13000000u) ) || \ + ( ADI_SPI0_CFG_BIT_RATE > (13000000u) ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_ENABLE > 1u ) || \ + ( ADI_SPI1_CFG_ENABLE > 1u ) || \ + ( ADI_SPI2_CFG_ENABLE > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_CLK_PHASE > 1u ) || \ + ( ADI_SPI1_CFG_CLK_PHASE > 1u ) || \ + ( ADI_SPI2_CFG_CLK_PHASE > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_CLK_POLARITY > 1u ) || \ + ( ADI_SPI1_CFG_CLK_POLARITY > 1u ) || \ + ( ADI_SPI2_CFG_CLK_POLARITY > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_WIRED_OR > 1u ) || \ + ( ADI_SPI1_CFG_WIRED_OR > 1u ) || \ + ( ADI_SPI2_CFG_WIRED_OR > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_LSB_MSB > 1u ) || \ + ( ADI_SPI1_CFG_LSB_MSB > 1u ) || \ + ( ADI_SPI2_CFG_LSB_MSB > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_TRANSFER_INITIATE > 1u ) || \ + ( ADI_SPI1_CFG_TRANSFER_INITIATE > 1u ) || \ + ( ADI_SPI2_CFG_TRANSFER_INITIATE > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_TX_UNDERFLOW > 1u ) || \ + ( ADI_SPI1_CFG_TX_UNDERFLOW > 1u ) || \ + ( ADI_SPI2_CFG_TX_UNDERFLOW > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_RX_OVERFLOW > 1u ) || \ + ( ADI_SPI1_CFG_RX_OVERFLOW > 1u ) || \ + ( ADI_SPI2_CFG_RX_OVERFLOW > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_MISO_ENABLE > 1u ) || \ + ( ADI_SPI1_CFG_MISO_ENABLE > 1u ) || \ + ( ADI_SPI2_CFG_MISO_ENABLE > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_LOOPBACK > 1u ) || \ + ( ADI_SPI1_CFG_LOOPBACK > 1u ) || \ + ( ADI_SPI2_CFG_LOOPBACK > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_CONTINUOUS > 1u ) || \ + ( ADI_SPI1_CFG_CONTINUOUS > 1u ) || \ + ( ADI_SPI2_CFG_CONTINUOUS > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_RX_FLUSH > 1u ) || \ + ( ADI_SPI1_CFG_RX_FLUSH > 1u ) || \ + ( ADI_SPI2_CFG_RX_FLUSH > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_TX_FLUSH > 1u ) || \ + ( ADI_SPI1_CFG_TX_FLUSH > 1u ) || \ + ( ADI_SPI2_CFG_TX_FLUSH > 1u ) +#error "Invalid configuration" +#endif + + +/*! @} */ + +#endif /* ADI_SPI_CONFIG_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_sport_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_sport_config.h new file mode 100755 index 0000000000..db0fdb6636 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_sport_config.h @@ -0,0 +1,355 @@ +/*! **************************************************************************** + * @file adi_sport_config.h + * @brief Configuration options for SPORT driver. + * @details This is specific to the SPORT driver and will be included by the + * driver. It is not required for the application to include this + * header file. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef ADI_SPORT_CONFIG_H +#define ADI_SPORT_CONFIG_H +#include + +/** @addtogroup SPORT_Driver_Config Static Configuration + * @ingroup SPORT_Driver + * @{ + */ + +/************* SPORT Driver configurations FOR SPORT-0-A ***************/ +/*! + Frame Sync Multiplexer Select.\n + 0 - Disable frame sync multiplexing\n + 1 - Enable frame sync multiplexing. +*/ +#define ADI_CFG_SPORT0A_ENABLE_FSMUXSEL (0u) + +/*! + Clock Multiplexer Select.\n + 0 - Disable serial clock multiplexing\n + 1 - Enable serial clock multiplexing. +*/ +#define ADI_CFG_SPORT0A_ENABLE_CKMUXSEL (1u) + +/*! + Least-Significant Bit First.\n + 0 - MSB first sent/received.\n + 1 - LSB first sent/received. +*/ +#define ADI_CFG_SPORT0A_LSB_FIRST (0u) + + +/*! + Serial Word Length in bits.\n + 1 - 32 - SPORT word length +*/ +#define ADI_CFG_SPORT0A_SERIAL_WLEN (32u) + + +/*! + Internal Clock.\n + 0 - External clock.\n + 1 - Internal clock. +*/ +#define ADI_CFG_SPORT0A_INTERNAL_CLK (1u) + +/*! + Operation Mode\n + 0 - DSP standard.\n + 1 - Timer_enable mode. +*/ +#define ADI_CFG_SPORT0A_OPERATION_MODE (0u) + + +/*! + Clock Rising Edge\n + 0 - Clock falling edge\n + 1 - Clock rising edge. +*/ +#define ADI_CFG_SPORT0A_CLOCK_EDGE (0u) + +/*! + Frame Sync Required\n + 0 - No frame sync required \n + 1 - Frame sync required. +*/ +#define ADI_CFG_SPORT0A_FS_REQUIRED (1u) + +/*! + Internal Frame Sync\n + 0 - External frame sync\n + 1 - Internal frame sync +*/ +#define ADI_CFG_SPORT0A_INTERNAL_FS (0u) + + +/*! + Data-Independent Frame Sync\n + 0 - Data-dependent frame sync\n + 1 - Data-independent frame +*/ +#define ADI_CFG_SPORT0A_DATA_INDEPENDENT_FS (0u) + +/*! + Active-Low Frame Sync\n + 0 - Active high frame sync\n + 1 - Active low frame sync +*/ +#define ADI_CFG_SPORT0A_ACTIVE_LOW_FS (0u) + +/*! + Late Frame Sync\n + 0 - Early frame sync\n + 1 - Late frame sync +*/ +#define ADI_CFG_SPORT0A_LATE_FS (0u) + +/*! + Enable Packing \n + 0 - Disable\n + 1 - 8-bit packing enable\n + 2 - 16-bit packing enable +*/ +#define ADI_CFG_SPORT0A_ENABLE_PACKING (0u) + +/*! + Frame Sync Error Operation + 0 - Flag the Frame Sync error\n + 1 - When frame Sync error occurs, discard the receive data +*/ +#define ADI_CFG_SPORT0A_FS_ERROR_OPERATION (1u) + +/*! + Enabling Gated Clock\n + 0 - Disable Gated Clock\n + 1 - Enable Gated Clock +*/ +#define ADI_CFG_SPORT0A_GATED_CLOCK (0u) + +/*! + Serial Clock divisor.\n + 0 - 65535 - Serial Clock Divisor which SPORT device use to calculate the serial + clock (ACLK) from the processor system clock (PCLK). +*/ +#define ADI_CFG_SPORT0A_CLOCK_DIVISOR (2u) + +/*! + Frame Sync Divisor.\n + 0 - 128 - Frame Sync Divisor which select the number of transmit or receive clock + cycles that the half SPORT counts before generating a frame sync pulse. +*/ +#define ADI_CFG_SPORT0A_FS_DIVISOR (0x40u) + + +/*! + CONVT to FS duration.\n + 0 - 128 - Specify the value of the number of clocks which would be programmed + corresponding to the desired time duration from assertion of CONVT + signal to Frame sync signal +*/ +#define ADI_CFG_SPORT0A_CONVT_FS_DURATION (1u) + +/*! + Polarity of the Convt signal.\n + 0 - Active High Polarity\n + 1 - Active low Polarity +*/ +#define ADI_CFG_SPORT0A_CONVT_POLARITY (0u) + +/*! + CONVT signal width.\n + 0 - 15 - Specify the value of the number of serial clocks for which CONVT + signal should be active + +*/ +#define ADI_CFG_SPORT0A_CONVT_WIDTH (1u) + +#if defined(ADI_CFG_SPORT0A_SERIAL_WLEN) +#if (ADI_CFG_SPORT0A_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0A_SERIAL_WLEN > 32u) +#error "Invalid word length : it must be between 4 and 32" +#endif +#else +#error "ADI_CFG_SPORT0A_SERIAL_WLEN undefined!!! " +#endif + +/************* SPORT Driver configurations FOR SPORT-0-B ***************/ +/*! + Least-Significant Bit First.\n + 0 - MSB first sent/received.\n + 1 - LSB first sent/received. +*/ +#define ADI_CFG_SPORT0B_LSB_FIRST (0u) + + +/*! + Serial Word Length in bits.\n + 1 - 32 - SPORT word length +*/ +#define ADI_CFG_SPORT0B_SERIAL_WLEN (32u) + + +/*! + Internal Clock.\n + 0 - External clock.\n + 1 - Internal clock. +*/ +#define ADI_CFG_SPORT0B_INTERNAL_CLK (1u) + +/*! + Operation Mode\n + 0 - DSP standard.\n + 1 - Timer_enable mode. +*/ +#define ADI_CFG_SPORT0B_OPERATION_MODE (0u) + + +/*! + Clock Rising Edge\n + 0 - Clock falling edge\n + 1 - Clock rising edge. +*/ +#define ADI_CFG_SPORT0B_CLOCK_EDGE (0u) + +/*! + Frame Sync Required\n + 0 - No frame sync required \n + 1 - Frame sync required. +*/ +#define ADI_CFG_SPORT0B_FS_REQUIRED (1u) + +/*! + Internal Frame Sync\n + 0 - External frame sync\n + 1 - Internal frame sync +*/ +#define ADI_CFG_SPORT0B_INTERNAL_FS (1u) + + +/*! + Data-Independent Frame Sync\n + 0 - Data-dependent frame sync\n + 1 - Data-independent frame +*/ +#define ADI_CFG_SPORT0B_DATA_INDEPENDENT_FS (0u) + +/*! + Active-Low Frame Sync\n + 0 - Active high frame sync\n + 1 - Active low frame sync +*/ +#define ADI_CFG_SPORT0B_ACTIVE_LOW_FS (0u) + +/*! + Late Frame Sync\n + 0 - Early frame sync\n + 1 - Late frame sync +*/ +#define ADI_CFG_SPORT0B_LATE_FS (0u) + +/*! + Enable Packing \n + 0 - Disable\n + 1 - 8-bit packing enable\n + 2 - 16-bit packing enable\n +*/ +#define ADI_CFG_SPORT0B_ENABLE_PACKING (0u) + +/*! + Frame Sync Error Operation\n + 0 - Flag the Frame Sync error\n + 1 - When frame Sync error occurs, discard the receive data +*/ +#define ADI_CFG_SPORT0B_FS_ERROR_OPERATION (1u) + +/*! + Enabling Gated Clock\n + 0 - Disable Gated Clock\n + 1 - Enable Gated Clock +*/ +#define ADI_CFG_SPORT0B_GATED_CLOCK (0u) + +/*! + Serial Clock divisor.\n + 0 - 65535 - Serial Clock Divisor which SPORT device use to calculate the serial + clock (ACLK) from the processor system clock (PCLK). +*/ +#define ADI_CFG_SPORT0B_CLOCK_DIVISOR (2u) + +/*! + Frame Sync Divisor.\n + 0 - 128 - Frame Sync Divisor which select the number of transmit or receive clock + cycles that the half SPORT counts before generating a frame sync pulse. +*/ +#define ADI_CFG_SPORT0B_FS_DIVISOR (0x40u) + + +/*! + CONVT to FS duration.\n + 0 - 128 - Specify the value of the number of clocks which would be programmed + corresponding to the desired time duration from assertion of CONVT + signal to Frame sync signal +*/ +#define ADI_CFG_SPORT0B_CONVT_FS_DURATION (1u) + +/*! + Polarity of the Convt signal.\n + 0 - Active High Polarity\n + 1 - Active low Polarity +*/ +#define ADI_CFG_SPORT0B_CONVT_POLARITY (0u) + +/*! + CONVT signal width.\n + 0-15 - Specify the value of the number of serial clocks for which CONVT + signal should be active + +*/ +#define ADI_CFG_SPORT0B_CONVT_WIDTH (1u) + +#if defined(ADI_CFG_SPORT0B_SERIAL_WLEN) +#if (ADI_CFG_SPORT0B_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0B_SERIAL_WLEN > 32u) +#error "Invalid word length : it must be between 4 and 32" +#endif +#else +#error "ADI_CFG_SPORT0B_SERIAL_WLEN undefined!!! " +#endif + +/*! @} */ + +#endif /* ADI_SPORT_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_tmr_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_tmr_config.h new file mode 100755 index 0000000000..8d6ee10347 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_tmr_config.h @@ -0,0 +1,902 @@ +/*! ***************************************************************************** + * @file adi_tmr_config.h + * @brief GP and RGB timer device driver configuration + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifndef ADI_TMR_CONFIG_H +#define ADI_TMR_CONFIG_H + + +#include + + +/** @addtogroup TMR_Driver_Config Static Configuration + * @ingroup TMR_Driver + * @{ + */ + + +/*! Static configuration allows all 3 GP timers and the RGB timer to be configured + with the parameters in this file by simply calling #adi_tmr_Init. The user can + then call any of the configuration API's to override the static configuration, + or simply call #adi_tmr_Enable to start the timer. Since all of these parameters + must be stored in arrays for abstraction, using static configuration will increase the + data footprint. If the user doesn't call any of the runtime configuration API's, the + linker will throw them out and the code footprint will be reduced significantly. Using + static configuration also reduces cycle count and simplifies the user application. + Static configuration should be used if the timers need to be configured once and do not + need to be changed during the system lifetime. + + 0 - Disable static confiscation support. User must call #adi_tmr_ConfigTimer and other + configuration API's after calling #adi_tmr_Init and prior to calling #adi_tmr_Enable + in order to set up the timer. + + 1 - Enable static configuration support. The timer registers will be set based on the + settings in this file when #adi_tmr_Init is called. +*/ +#define ADI_TIMER_ENABLE_STATIC_CONFIG_SUPPORT (0u) + + +/************************************************************* + GP Timer 0 Configuration + *************************************************************/ + + /** @addtogroup GPTimer0_Driver_Config GP Timer 0 Static Configuration + * @ingroup TMR_Driver_Config + * @{ + */ + + +/*! Count up or down. Used to control whether the timer increments (counts up) + or decrements (counts down) the Up/Down counter, it can be set to\n + 0 - Timer is set to count down.\n + 1 - Timer is set to count up. +*/ +#define TMR0_CFG_COUNT_UP (0u) + +/*! Timer mode. Used to control whether the timer runs in periodic or + free running mode, it can be set to\n + 0 - Timer is in free running mode.\n + 1 - Timer is in periodic mode. +*/ +#define TMR0_CFG_MODE (1u) + +/*! Prescale factor. Controls the prescaler division factor + to the timer's selected clock. It can be set to\n + + 0 - source_clock/[1 or 4]\n + 1 - source_clock/16\n + 2 - source_clock/64\n + 3 - source_clock/256 +*/ +#define TMR0_CFG_PRESCALE_FACTOR (0u) + +/*! Timer clock source. Used to select a timer clock from the four + available clock sources, it can be set to\n + 0 - Select PCLK\n + 1 - Select HFOSC\n + 2 - Select LFOSC\n + 3 - Select LFXTAL +*/ +#define TMR0_CFG_CLOCK_SOURCE (0u) + +/*! Timer load value. The Up/Down counter is periodically loaded with this + value if periodic mode is selected. LOAD writes during Up/Down counter timeout events + are delayed until the event has passed. It can be set to any value from 0 to 65535. + +*/ +#define TMR0_CFG_LOAD_VALUE (0x8F9Cu) + +/*! Timer asynchrounous load value. The Up/Down counter is periodically loaded with + this value if periodic mode is selected. Writing Asynchronous Load value takes + advantage of having the timer run on PCLK by bypassing clock synchronization + logic otherwise required. It can be set to any value from 0 to 65535. + +*/ +#define TMR0_CFG_ASYNC_LOAD_VALUE (0x8F9Cu) + +/*! Reload control. This allows the user to select whether the Up/Down counter should be + reset only on a timeout event or also when interrupt is cleared. It can be set to\n + 0 - Up/down counter is only reset on a time out event.\n + 1 - Resets the up/down counter when the interrupt is cleared. +*/ +#define TMR0_CFG_ENABLE_RELOADING (0u) + +/*! Enable or disable Synchronization bypass\n + 0 - Disable Synchronization bypass.\n + 1 - Enable Synchronization bypass. +*/ +#define TMR0_CFG_ENABLE_SYNC_BYPASS (0u) + +/************************************************************* + GP Timer 0 Event Configuration + *************************************************************/ + +/*! Enable or disable event capture. It can be set to\n + 0 - Disable event capturing.\n + 1 - Enable event capturing. +*/ +#define TMR0_CFG_ENABLE_EVENT_CAPTURE (1u) + +/*! Enable or disable prescale reset\n + 0 - Disable rescale reset.\n + 1 - Enable rescale reset. +*/ +#define TMR0_CFG_ENABLE_PRESCALE_RESET (0u) + +/*! Event to be captured. One of the selected 40 events associated + with a general purpose time can be captured. It can be set to + a value of 0 - 39. Please refer hardware reference manual to know + which events can be captured by a particular GP timer. +*/ +#define TMR0_CFG_EVENT_CAPTURE (27u) + +/************************************************************* + GP Timer 0 PWM0 Configuration + *************************************************************/ + +/*! Timer PWM Enable Match. This will control PWM operation mode of the timer. + Toggle mode provides a 50% duty cycle and match mode provides a configurable + duty cycle by using the match value. This vlaue can be set to\n + 0 - PWM in toggle mode.\n + 1 - PWM in match mode. +*/ +#define TMR0_CFG_ENABLE_PWM0_MATCH_MODE (1u) + + +/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n + 0 - PWM idles low.\n + 1 - PWM idles high. +*/ +#define TMR0_CFG_PWM0_IDLE_STATE (1u) + + +/*! PWM Match value. The value is used when the PWM is operating in match mode. + The PWM output is asserted when the Up/Down counter is equal to this match value. + PWM output is deasserted again when a timeout event occurs. + If the match value is never reached, or occurs simultaneous to a timeout event, + the PWM output remains idle. It can be any value from 0 to 65535. +*/ +#define TMR0_CFG_PWM0_MATCH_VALUE (0x0E5Cu) + +/*! @} */ + + +/************************************************************* + GP Timer 1 Configuration + *************************************************************/ + + /** @addtogroup GPTimer1_Driver_Config GP Timer 1 Static Configuration + * @ingroup TMR_Driver_Config + * @{ + */ + + +/*! Count up or down. Used to control whether the timer increments (counts up) + or decrements (counts down) the Up/Down counter, it can be set to\n + 0 - Timer is set to count down.\n + 1 - Timer is set to count up. +*/ +#define TMR1_CFG_COUNT_UP (0u) + +/*! Timer mode. Used to control whether the timer runs in periodic or + free running mode, it can be set to\n + 0 - Timer is in free running mode.\n + 1 - Timer is in periodic mode. +*/ +#define TMR1_CFG_MODE (1u) + +/*! Prescale factor. Controls the prescaler division factor + to the timer's selected clock. It can be set to\n + + 0 - source_clock/[1 or 4]\n + 1 - source_clock/16\n + 2 - source_clock/64\n + 3 - source_clock/256 +*/ +#define TMR1_CFG_PRESCALE_FACTOR (0u) + +/*! Timer clock source. Used to select a timer clock from the four + available clock sources, it can be set to\n + 0 - Select PCLK\n + 1 - Select HFOSC\n + 2 - Select LFOSC\n + 3 - Select LFXTAL +*/ +#define TMR1_CFG_CLOCK_SOURCE (0u) + +/*! Timer load value. The Up/Down counter is periodically loaded with this + value if periodic mode is selected. LOAD writes during Up/Down counter timeout events + are delayed until the event has passed. It can be set to any value from 0 to 65535. + +*/ +#define TMR1_CFG_LOAD_VALUE (0x23E7u) + +/*! Timer asynchronous load value. The Up/Down counter is periodically loaded with + this value if periodic mode is selected. Writing Asynchronous Load value takes + advantage of having the timer run on PCLK by bypassing clock synchronization + logic otherwise required. It can be set to any value from 0 to 65535. + +*/ +#define TMR1_CFG_ASYNC_LOAD_VALUE (0x23E7u) + +/*! Reload control. This allows the user to select whether the Up/Down counter should be + reset only on a timeout event or also when interrupt is cleared. It can be set to\n + 0 - Up/down counter is only reset on a time out event.\n + 1 - Resets the up/down counter when the interrupt is cleared. +*/ +#define TMR1_CFG_ENABLE_RELOADING (0u) + +/*! Enable or disable Synchronization bypass\n + 0 - Disable Synchronization bypass.\n + 1 - Enable Synchronization bypass. +*/ +#define TMR1_CFG_ENABLE_SYNC_BYPASS (0u) + + +/************************************************************* + GP Timer 1 Event Configuration + *************************************************************/ + +/*! Enable or disable event capture. It can be set to\n + 0 - Disable event capturing.\n + 1 - Enable event capturing. +*/ +#define TMR1_CFG_ENABLE_EVENT_CAPTURE (1u) + +/*! Enable or disable prescale reset\n + 0 - Disable rescale reset.\n + 1 - Enable rescale reset. +*/ +#define TMR1_CFG_ENABLE_PRESCALE_RESET (0u) + +/*! Event to be captured. One of the selected 40 events associated + with a general purpose time can be captured. It can be set to + a value of 0 - 39. Please refer hardware reference manual to know + which events can be captured by a particular GP timer. +*/ +#define TMR1_CFG_EVENT_CAPTURE (28u) + +/************************************************************* + GP Timer 1 PWM0 Configuration + *************************************************************/ + +/*! Timer PWM Enable Match. This will control PWM operation mode of the timer. + Toggle mode provides a 50% duty cycle and match mode provides a configurable + duty cycle by using the match value. This value can be set to\n + 0 - PWM in toggle mode.\n + 1 - PWM in match mode. +*/ +#define TMR1_CFG_ENABLE_PWM0_MATCH_MODE (1u) + + +/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n + 0 - PWM idles low.\n + 1 - PWM idles high. +*/ +#define TMR1_CFG_PWM0_IDLE_STATE (1u) + + +/*! PWM Match value. The value is used when the PWM is operating in match mode. + The PWM output is asserted when the Up/Down counter is equal to this match value. + PWM output is deasserted again when a timeout event occurs. + If the match value is never reached, or occurs simultaneous to a timeout event, + the PWM output remains idle. It can be any value from 0 to 65535. +*/ +#define TMR1_CFG_PWM0_MATCH_VALUE (0x08F9u) + +/*! @} */ + +/************************************************************* + GP Timer 2 Configuration + *************************************************************/ + + /** @addtogroup GPTimer2_Driver_Config GP Timer 2 Static Configuration + * @ingroup TMR_Driver_Config + * @{ + */ + + +/*! Count up or down. Used to control whether the timer increments (counts up) + or decrements (counts down) the Up/Down counter, it can be set to\n + 0 - Timer is set to count down.\n + 1 - Timer is set to count up. +*/ +#define TMR2_CFG_COUNT_UP (0u) + +/*! Timer mode. Used to control whether the timer runs in periodic or + free running mode, it can be set to\n + 0 - Timer is in free running mode.\n + 1 - Timer is in periodic mode. +*/ +#define TMR2_CFG_MODE (1u) + +/*! Prescale factor. Controls the prescaler division factor + to the timer's selected clock. It can be set to\n + + 0 - source_clock/[1 or 4]\n + 1 - source_clock/16\n + 2 - source_clock/64\n + 3 - source_clock/256 +*/ +#define TMR2_CFG_PRESCALE_FACTOR (0u) + +/*! Timer clock source. Used to select a timer clock from the four + available clock sources, it can be set to\n + 0 - Select PCLK\n + 1 - Select HFOSC\n + 2 - Select LFOSC\n + 3 - Select LFXTAL +*/ +#define TMR2_CFG_CLOCK_SOURCE (0u) + +/*! Timer load value. The Up/Down counter is periodically loaded with this + value if periodic mode is selected. LOAD writes during Up/Down counter timeout events + are delayed until the event has passed. It can be set to any value from 0 to 65535. + +*/ +#define TMR2_CFG_LOAD_VALUE (0x0E5Cu) + +/*! Timer asynchronous load value. The Up/Down counter is periodically loaded with + this value if periodic mode is selected. Writing Asynchronous Load value takes + advantage of having the timer run on PCLK by bypassing clock synchronization + logic otherwise required. It can be set to any value from 0 to 65535. + +*/ +#define TMR2_CFG_ASYNC_LOAD_VALUE (0x0E5Cu) + +/*! Reload control. This allows the user to select whether the Up/Down counter should be + reset only on a timeout event or also when interrupt is cleared. It can be set to\n + 0 - Up/down counter is only reset on a time out event.\n + 1 - Resets the up/down counter when the interrupt is cleared. +*/ +#define TMR2_CFG_ENABLE_RELOADING (0u) + +/*! Enable or disable Synchronization bypass\n + 0 - Disable Synchronization bypass.\n + 1 - Enable Synchronization bypass. +*/ +#define TMR2_CFG_ENABLE_SYNC_BYPASS (0u) + +/************************************************************* + GP Timer 2 Event Configuration + *************************************************************/ + +/*! Enable or disable event capture. It can be set to\n + 0 - Disable event capturing.\n + 1 - Enable event capturing. +*/ +#define TMR2_CFG_ENABLE_EVENT_CAPTURE (1u) + +/*! Enable or disable prescale reset\n + 0 - Disable rescale reset.\n + 1 - Enable rescale reset. +*/ +#define TMR2_CFG_ENABLE_PRESCALE_RESET (0u) + +/*! Event to be captured. One of the selected 40 events associated + with a general purpose time can be captured. It can be set to + a value of 0 - 39. Please refer hardware reference manual to know + which events can be captured by a particular GP timer. +*/ +#define TMR2_CFG_EVENT_CAPTURE (27u) + +/************************************************************* + GP Timer 2 PWM0 Configuration + *************************************************************/ + +/*! Timer PWM Enable Match. This will control PWM operation mode of the timer. + Toggle mode provides a 50% duty cycle and match mode provides a configurable + duty cycle by using the match value. This value can be set to\n + 0 - PWM in toggle mode.\n + 1 - PWM in match mode. +*/ +#define TMR2_CFG_ENABLE_PWM0_MATCH_MODE (1u) + + +/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n + 0 - PWM idles low.\n + 1 - PWM idles high. +*/ +#define TMR2_CFG_PWM0_IDLE_STATE (1u) + + +/*! PWM Match value. The value is used when the PWM is operating in match mode. + The PWM output is asserted when the Up/Down counter is equal to this match value. + PWM output is deasserted again when a timeout event occurs. + If the match value is never reached, or occurs simultaneous to a timeout event, + the PWM output remains idle. It can be any value from 0 to 65535. +*/ +#define TMR2_CFG_PWM0_MATCH_VALUE (0x02DFu) + +/*! @} */ + + +/************************************************************* + RGB Timer Configuration + *************************************************************/ + +/** @addtogroup RGBTimer_Driver_Config RGB Timer Static Configuration + * @ingroup TMR_Driver_Config + * @{ + */ + + +/*! Count up or down. Used to control whether the timer increments (counts up) + or decrements (counts down) the Up/Down counter, it can be set to\n + 0 - Timer is set to count down.\n + 1 - Timer is set to count up. +*/ +#define TMR3_CFG_COUNT_UP (0u) + +/*! Timer mode. Used to control whether the timer runs in periodic or + free running mode, it can be set to\n + 0 - Timer is in free running mode.\n + 1 - Timer is in periodic mode. +*/ +#define TMR3_CFG_MODE (1u) + +/*! Prescale factor. Controls the prescaler division factor + to the timer's selected clock. It can be set to\n + + 0 - source_clock/[1 or 4]\n + 1 - source_clock/16\n + 2 - source_clock/64\n + 3 - source_clock/256 +*/ +#define TMR3_CFG_PRESCALE_FACTOR (0u) + +/*! Timer clock source. Used to select a timer clock from the four + available clock sources, it can be set to\n + 0 - Select PCLK\n + 1 - Select HFOSC\n + 2 - Select LFOSC\n + 3 - Select LFXTAL +*/ +#define TMR3_CFG_CLOCK_SOURCE (0u) + +/*! Timer load value. The Up/Down counter is periodically loaded with this + value if periodic mode is selected. LOAD writes during Up/Down counter timeout events + are delayed until the event has passed. It can be set to any value from 0 to 65535. + +*/ +#define TMR3_CFG_LOAD_VALUE (0x47CEu) + +/*! Timer asynchronous load value. The Up/Down counter is periodically loaded with + this value if periodic mode is selected. Writing asynchronous Load value takes + advantage of having the timer run on PCLK by bypassing clock synchronization + logic otherwise required. It can be set to any value from 0 to 65535. + +*/ +#define TMR3_CFG_ASYNC_LOAD_VALUE (0x47CEu) + +/*! Reload control. This allows the user to select whether the Up/Down counter should be + reset only on a timeout event or also when interrupt is cleared. It can be set to\n + 0 - Up/down counter is only reset on a time out event.\n + 1 - Resets the up/down counter when the interrupt is cleared. +*/ +#define TMR3_CFG_ENABLE_RELOADING (0u) + +/*! Enable or disable Synchronization bypass\n + 0 - Disable Synchronization bypass.\n + 1 - Enable Synchronization bypass. +*/ +#define TMR3_CFG_ENABLE_SYNC_BYPASS (0u) + +/************************************************************* + RGB Timer Event Configuration + *************************************************************/ + +/*! Enable or disable event capture. It can be set to\n + 0 - Disable event capturing.\n + 1 - Enable event capturing. +*/ +#define TMR3_CFG_ENABLE_EVENT_CAPTURE (1u) + +/*! Enable or disable prescale reset\n + 0 - Disable rescale reset.\n + 1 - Enable rescale reset. +*/ +#define TMR3_CFG_ENABLE_PRESCALE_RESET (0u) + +/*! Event to be captured. One of the selected 40 events associated + with a general purpose time can be captured. It can be set to + a value of 0 - 39. Please refer hardware reference manual to know + which events can be captured by a particular GP timer. +*/ +#define TMR3_CFG_EVENT_CAPTURE (28u) + +/************************************************************* + RGB Timer PWM0 Configuration + *************************************************************/ + +/*! Timer PWM Enable Match. This will control PWM operation mode of the timer. + Toggle mode provides a 50% duty cycle and match mode provides a configurable + duty cycle by using the match value. This value can be set to\n + 0 - PWM in toggle mode.\n + 1 - PWM in match mode. +*/ +#define TMR3_CFG_ENABLE_PWM0_MATCH_MODE (1u) + + +/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n + 0 - PWM idles low.\n + 1 - PWM idles high. +*/ +#define TMR3_CFG_PWM0_IDLE_STATE (1u) + + +/*! PWM Match value. The value is used when the PWM is operating in match mode. + The PWM output is asserted when the Up/Down counter is equal to this match value. + PWM output is deasserted again when a timeout event occurs. + If the match value is never reached, or occurs simultaneous to a timeout event, + the PWM output remains idle. It can be any value from 0 to 65535. +*/ +#define TMR3_CFG_PWM0_MATCH_VALUE (0x23E7u) + +/************************************************************* + RGB Timer PWM1 Configuration + *************************************************************/ + +/*! Timer PWM Enable Match. This will control PWM operation mode of the timer. + Toggle mode provides a 50% duty cycle and match mode provides a configurable + duty cycle by using the match value. This value can be set to\n + 0 - PWM in toggle mode.\n + 1 - PWM in match mode. +*/ +#define TMR3_CFG_ENABLE_PWM1_MATCH_MODE (0u) + + +/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n + 0 - PWM idles low.\n + 1 - PWM idles high. +*/ +#define TMR3_CFG_PWM1_IDLE_STATE (0u) + + +/*! PWM Match value. The value is used when the PWM is operating in match mode. + The PWM output is asserted when the Up/Down counter is equal to this match value. + PWM output is deasserted again when a timeout event occurs. + If the match value is never reached, or occurs simultaneous to a timeout event, + the PWM output remains idle. It can be any value from 0 to 65535. +*/ +#define TMR3_CFG_PWM1_MATCH_VALUE (0u) + +/************************************************************* + RGB Timer PWM2 Configuration + *************************************************************/ + +/*! Timer PWM Enable Match. This will control PWM operation mode of the timer. + Toggle mode provides a 50% duty cycle and match mode provides a configurable + duty cycle by using the match value. This value can be set to\n + 0 - PWM in toggle mode.\n + 1 - PWM in match mode. +*/ +#define TMR3_CFG_ENABLE_PWM2_MATCH_MODE (0u) + + +/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n + 0 - PWM idles low.\n + 1 - PWM idles high. +*/ +#define TMR3_CFG_PWM2_IDLE_STATE (0u) + + +/*! PWM Match value. The value is used when the PWM is operating in match mode. + The PWM output is asserted when the Up/Down counter is equal to this match value. + PWM output is deasserted again when a timeout event occurs. + If the match value is never reached, or occurs simultaneous to a timeout event, + the PWM output remains idle. It can be any value from 0 to 65535. +*/ +#define TMR3_CFG_PWM2_MATCH_VALUE (0u) + +/*! @} */ + +/************************************************************* + GP Timer 0 Macro Validation +**************************************************************/ + +#if TMR0_CFG_COUNT_UP > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_PRESCALE_FACTOR > 3u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_CLOCK_SOURCE > 3u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR0_CFG_ASYNC_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR0_CFG_ENABLE_RELOADING > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_ENABLE_SYNC_BYPASS > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_ENABLE_PRESCALE_RESET > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_ENABLE_EVENT_CAPTURE > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_EVENT_CAPTURE > 39u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_ENABLE_PWM0_MATCH_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_PWM0_IDLE_STATE > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_PWM0_MATCH_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +/************************************************************* + GP Timer 1 Macro Validation +**************************************************************/ + +#if TMR1_CFG_COUNT_UP > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_PRESCALE_FACTOR > 3u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_CLOCK_SOURCE > 3u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR1_CFG_ASYNC_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR1_CFG_ENABLE_RELOADING > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_ENABLE_SYNC_BYPASS > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_ENABLE_PRESCALE_RESET > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_ENABLE_EVENT_CAPTURE > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_EVENT_CAPTURE > 39u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_ENABLE_PWM0_MATCH_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_PWM0_IDLE_STATE > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_PWM0_MATCH_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +/************************************************************* + GP Timer 2 Macro Validation +**************************************************************/ + +#if TMR2_CFG_COUNT_UP > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_PRESCALE_FACTOR > 3u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_CLOCK_SOURCE > 3u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR2_CFG_ASYNC_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR2_CFG_ENABLE_RELOADING > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_ENABLE_SYNC_BYPASS > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_ENABLE_PRESCALE_RESET > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_ENABLE_EVENT_CAPTURE > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_EVENT_CAPTURE > 39u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_ENABLE_PWM0_MATCH_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_PWM0_IDLE_STATE > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_PWM0_MATCH_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +/************************************************************* + RGB Timer Macro Validation +**************************************************************/ + +#if TMR3_CFG_COUNT_UP > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PRESCALE_FACTOR > 3u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_CLOCK_SOURCE > 3u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ASYNC_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_RELOADING > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_SYNC_BYPASS > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_PRESCALE_RESET > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_EVENT_CAPTURE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_EVENT_CAPTURE > 39u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_PWM0_MATCH_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PWM0_IDLE_STATE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PWM0_MATCH_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_PWM1_MATCH_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PWM1_IDLE_STATE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PWM1_MATCH_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_PWM2_MATCH_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PWM2_IDLE_STATE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PWM2_MATCH_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +/*! @} */ + + +#endif /* ADI_TMR_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_uart_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_uart_config.h new file mode 100755 index 0000000000..1cf72a4b91 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_uart_config.h @@ -0,0 +1,496 @@ +/*! + ***************************************************************************** + @file: adi_uart_config.h + @brief: Configuration options for UART driver. + This is specific to the UART driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_UART_CONFIG_H +#define ADI_UART_CONFIG_H + +/** @addtogroup UART_Driver_Config Static Configuration + * @ingroup UART_Driver + * @{ + */ + + +#include + +/************** Common UART Driver configurations ************** */ +/*! + Enable the autobaud detection. \n + Range: 0 to 1. +*/ +#define ADI_UART_CFG_ENABLE_AUTOBAUD 1 + + +/** @addtogroup UART0_Driver_Config UART0 Static Configuration + * @ingroup UART_Driver_Config + * @{ + */ + +/************** UART Driver configurations FOR UART 0 ************** */ +/*! + Word length Select. \n + 0 - 5 Bits word length. \n + 1 - 6 Bits word length. \n + 2 - 7 Bits word length. \n + 3 - 8 Bits word length. +*/ +#define ADI_UART0_CFG_WORD_LENGTH 3 + + +/*! + Stop bit selection. \n + 0 - Send 1 stop bit regardless of the word length. \n + 1 - Send a number of stop bits based on the word length. \n + WORD-LENGTH 5 Bits => 1.5 Stop Bits. \n + WORD-LENGTH (6/7/8) Bits => 2 Stop Bits. +*/ +#define ADI_UART0_CFG_STOP_BIT 1 + + +/*! + Parity Enable. Used to control the parity bit. \n + 0 - Parity will not be transmitted or checked. \n + 1 - Parity will be transmitted and checked. +*/ +#define ADI_UART0_CFG_ENABLE_PARITY 0 + + +/*! + Parity Select. This bit only has meaning if parity is enabled. \n + 0 - Odd parity will be transmitted and checked. \n + 1 - Even parity will be transmitted and checked. +*/ +#define ADI_UART0_CFG_PARITY_SELECTION 0 + + +/*! + Stick Parity. Used to force parity to defined values. \n + 0 - Parity will not be forced. \n + 1 - Set parity based on the following bit settings: \n + EPS = 1 and PEN = 1, parity will be forced to 0. \n + EPS = 0 and PEN = 1, parity will be forced to 1. \n + EPS = 1/0 and PEN = 0, no parity will be transmitted. +*/ +#define ADI_UART0_CFG_ENABLE_STICKY_PARITY 0 + + +/* + Table 21-2: Baud Rate Examples Based on 26 MHz PCLK + Baud Rate OSR COMDIV DIVM DIVN + 9600 3 24 3 1078 + 19200 3 12 3 1078 + 38400 3 8 2 1321 + 57600 3 4 3 1078 + 115200 3 4 1 1563 + 230400 3 2 1 1563 + 460800 3 1 1 1563 + 921,600 2 1 1 1563 + 1,000,000 2 1 1 1280 + 1,500,000 2 1 1 171 + +These are calculated with the UarDivCalculator tool. +*/ + +/*! + Fractional baud rate N divide value. \n + Range: 0 to 2047. +*/ +#define ADI_UART0_CFG_DIVN 1078 + + +/*! + Fractional baud rate M divide value. \n + Range: 1 to 3. +*/ +#define ADI_UART0_CFG_DIVM 3 + + +/*! + Fractional baud rate C divide value. \n + Range: 1 to 65535. +*/ +#define ADI_UART0_CFG_DIVC 24 + + +/*! + Over Sample Rate value. \n + Range: 0 to 3. \n + 0 - Over sample by 4. \n + 1 - Over sample by 8. \n + 2 - Over sample by 16. \n + 3 - Over sample by 32. + +*/ +#define ADI_UART0_CFG_OSR 3 + + +/*! + Enable Internal FIFO. \n + Range: 0 to 1. +*/ +#define ADI_UART0_CFG_ENABLE_FIFO 1 + + +/*! + TRIG Level for UART device. \n + Range: 0 to 3. \n + 0 - 1 byte to trig RX interrupt. \n + 1 - 4 bytes to trig RX interrupt. \n + 2 - 8 bytes to trig RX interrupt. \n + 3 - 14 bytes to trig RX interrupt. +*/ +#define ADI_UART0_CFG_TRIG_LEVEL 0 + + +/*! + Hold TX while RX is active. \n + Range: 0 to 1. +*/ +#define ADI_UART0_CFG_HOLD_TX 0 + + +/*! + Disable RX when TX is active. \n + Range: 0 to 1. \n + 0 - 1 byte to trig RX interrupt. \n + 1 - 4 bytes to trig RX interrupt. +*/ +#define ADI_UART0_CFG_DISABLE_RX 0 + + +/*! + Configure the SOUT de-assertion earlier than full stop bit(s). \n + Range: 0 to 1. \n + 0 - SOUT_EN de-assert same time as full stop bit(s). \n + 1 - SOUT_EN de-assert half-bit earlier than full stop bit(s). +*/ +#define ADI_UART0_CFG_DEASSERTION 0 + + +/*! + Set the SOUT polarity low. \n + Range: 0 to 1. \n + 0 - Active high. \n + 1 - Active low. +*/ +#define ADI_UART0_CFG_SOUT_POLARITY 0 + +/*! + Enable the RX status interrupt. \n + Range: 0 to 1. +*/ +#define ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT 1 + + +/*! + Enable the Modem status interrupt. \n + Range: 0 to 1. +*/ +#define ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT 0 + +/*! @} */ + + +/*************** UART Driver configurations FOR UART 1 **************/ + +/** @addtogroup UART1_Driver_Config UART1 Static Configuration + * @ingroup UART_Driver_Config + * @{ + */ + +/*! + Word length Select. \n + 0 - 5 Bits word length. \n + 1 - 6 Bits word length. \n + 2 - 7 Bits word length. \n + 3 - 8 Bits word length. +*/ +#define ADI_UART1_CFG_WORD_LENGTH 3 + + +/*! + Stop bit selection.\n + 0 - Send 1 stop bit regardless of the word length. \n + 1 - Send a number of stop bits based on the word length. \n + WORD-LENGTH 5 Bits => 1.5 Stop Bits. \n + WORD-LENGTH (6/7/8) Bits => 2 Stop Bits. +*/ +#define ADI_UART1_CFG_STOP_BIT 1 + + +/*! + Parity Enable. Used to control the parity bit. \n + 0 - Parity will not be transmitted or checked. \n + 1 - Parity will be transmitted and checked. +*/ +#define ADI_UART1_CFG_ENABLE_PARITY 0 + + +/*! + Parity Select. This bit only has meaning if parity is enabled. \n + 0 - Odd parity will be transmitted and checked. \n + 1 - Even parity will be transmitted and checked. +*/ +#define ADI_UART1_CFG_PARITY_SELECTION 0 + + +/*! + Stick Parity. Used to force parity to defined values. \n + 0 - Parity will not be forced. \n + 1 - Set parity based on the following bit settings: \n + EPS = 1 and PEN = 1, parity will be forced to 0. \n + EPS = 0 and PEN = 1, parity will be forced to 1. \n + EPS = 1/0 and PEN = 0, no parity will be transmitted. +*/ +#define ADI_UART1_CFG_ENABLE_STICKY_PARITY 0 + + +/* + Table 21-2: Baud Rate Examples Based on 26 MHz PCLK + Baud Rate OSR COMDIV DIVM DIVN + 9600 3 24 3 1078 + 19200 3 12 3 1078 + 38400 3 8 2 1321 + 57600 3 4 3 1078 + 115200 3 4 1 1563 + 230400 3 2 1 1563 + 460800 3 1 1 1563 + 921,600 2 1 1 1563 + 1,000,000 2 1 1 1280 + 1,500,000 2 1 1 171 + +These are calculated with the UarDivCalculator tool. +*/ + +/*! + Fractional baud rate N divide value. \n + Range: 0 to 2047. +*/ +#define ADI_UART1_CFG_DIVN 1563 + + +/*! + Fractional baud rate M divide value. \n + Range: 1 to 3. +*/ +#define ADI_UART1_CFG_DIVM 1 + + +/*! + Fractional baud rate C divide value. \n + Range: 1 to 65535. +*/ +#define ADI_UART1_CFG_DIVC 1 + + +/*! + Over Sample Rate value. \n + Range: 0 to 3. \n + 0 - Over sample by 4. \n + 1 - Over sample by 8. \n + 2 - Over sample by 16. \n + 3 - Over sample by 32. + +*/ +#define ADI_UART1_CFG_OSR 3 + + +/*! + Enable Internal FIFO. \n + Range: 0 to 1. +*/ +#define ADI_UART1_CFG_ENABLE_FIFO 1 + + +/*! + TRIG Level for UART device. \n + Range: 0 to 3. \n + 0 - 1 byte to trig RX interrupt. \n + 1 - 4 bytes to trig RX interrupt. \n + 2 - 8 bytes to trig RX interrupt. \n + 3 - 14 bytes to trig RX interrupt. +*/ +#define ADI_UART1_CFG_TRIG_LEVEL 0 + + +/*! + Hold TX while RX is active. \n + Range: 0 to 1. +*/ +#define ADI_UART1_CFG_HOLD_TX 0 + + +/*! + Disable RX when TX is active. \n + Range: 0 to 1. \n + 0 - 1 byte to trig RX interrupt. \n + 1 - 4 bytes to trig RX interrupt. +*/ +#define ADI_UART1_CFG_DISABLE_RX 0 + + +/*! + Configure the SOUT de-assertion earlier than full stop bit(s). \n + Range: 0 to 1. \n + 0 - SOUT_EN de-assert same time as full stop bit(s). \n + 1 - SOUT_EN de-assert half-bit earlier than full stop bit(s). +*/ +#define ADI_UART1_CFG_DEASSERTION 0 + + +/*! + Set the SOUT polarity low. \n + Range: 0 to 1. \n + 0 - Active high. \n + 1 - Active low. +*/ +#define ADI_UART1_CFG_SOUT_POLARITY 0 + +/*! + Enable the RX status interrupt. \n + Range: 0 to 1. +*/ +#define ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT 1 + + +/*! + Enable the Modem status interrupt. \n + Range: 0 to 1. +*/ +#define ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT 0 +/*! @} */ + +/*! @} */ + + +/*************** UART Driver Debug Checks ************** */ + +/* Check word length */ +#if (((ADI_UART0_CFG_WORD_LENGTH < 0) || (ADI_UART0_CFG_WORD_LENGTH > 3)) || ((ADI_UART1_CFG_WORD_LENGTH < 0) || (ADI_UART1_CFG_WORD_LENGTH > 3))) +#error "Word length needs to be between 0 and 3" +#endif + +/* Check stop bit */ +#if (((ADI_UART0_CFG_STOP_BIT < 0) || (ADI_UART0_CFG_STOP_BIT > 1)) || ((ADI_UART1_CFG_STOP_BIT < 0) || (ADI_UART1_CFG_STOP_BIT > 1))) +#error "Stop bit selection needs to be 0 or 1" +#endif + +/* Check parity enable */ +#if (((ADI_UART0_CFG_ENABLE_PARITY < 0) || (ADI_UART0_CFG_ENABLE_PARITY > 1)) || ((ADI_UART1_CFG_ENABLE_PARITY < 0) || (ADI_UART1_CFG_ENABLE_PARITY > 1))) +#error "Parity Enable bit needs to be 0 or 1" +#endif + +/* Check parity select */ +#if (((ADI_UART0_CFG_PARITY_SELECTION < 0) || (ADI_UART0_CFG_PARITY_SELECTION > 1)) || ((ADI_UART1_CFG_PARITY_SELECTION < 0) || (ADI_UART1_CFG_PARITY_SELECTION > 1))) +#error "Parity bit selection needs to be 0 or 1" +#endif + +/* Check enable sticky parity */ +#if (((ADI_UART0_CFG_ENABLE_STICKY_PARITY < 0) || (ADI_UART0_CFG_ENABLE_STICKY_PARITY > 1)) || ((ADI_UART1_CFG_ENABLE_STICKY_PARITY < 0) || (ADI_UART1_CFG_ENABLE_STICKY_PARITY > 1))) +#error "Sticky parity enable needs to be 0 or 1" +#endif + +/* Check fractional baudrate N divider value */ +#if (((ADI_UART0_CFG_DIVN < 0) || (ADI_UART0_CFG_DIVN > 2047)) || ((ADI_UART1_CFG_DIVN < 0) || (ADI_UART1_CFG_DIVN > 2047))) +#error "Fractional baudrate N divider value needs to be between 0 and 2047" +#endif + +/* Check fractional baudrate M divider value */ +#if (((ADI_UART0_CFG_DIVM < 1) || (ADI_UART0_CFG_DIVM > 3)) || ((ADI_UART1_CFG_DIVM < 1) || (ADI_UART1_CFG_DIVM > 3))) +#error "Fractional baudrate M divider value needs to be between 1 and 3" +#endif + +/* Check fractional baudrate C divider value */ +#if (((ADI_UART0_CFG_DIVC < 1) || (ADI_UART0_CFG_DIVC > 65535)) || ((ADI_UART1_CFG_DIVC < 1) || (ADI_UART1_CFG_DIVC > 65535))) +#error "Fractional baudrate C divider value needs to be between 1 and 65535" +#endif + +/* Check over same rate value */ +#if (((ADI_UART0_CFG_OSR < 0) || (ADI_UART0_CFG_OSR > 3)) || ((ADI_UART1_CFG_OSR < 0) || (ADI_UART1_CFG_OSR > 3))) +#error "over sample rate value needs to be between 0 and 3" +#endif + +/* Check enable internal FIFO */ +#if (((ADI_UART0_CFG_ENABLE_FIFO < 0) || (ADI_UART0_CFG_ENABLE_FIFO > 1)) || ((ADI_UART1_CFG_ENABLE_FIFO < 0) || (ADI_UART1_CFG_ENABLE_FIFO > 1))) +#error "Enable internal FIFO needs to be 0 or 1" +#endif + +/* Check UART trig level */ +#if (((ADI_UART0_CFG_TRIG_LEVEL < 0) || (ADI_UART0_CFG_TRIG_LEVEL > 3)) || ((ADI_UART1_CFG_TRIG_LEVEL < 0) || (ADI_UART1_CFG_TRIG_LEVEL > 3))) +#error "Trig level for the UART device needs to be 0 or 1" +#endif + +/* Check value for holding tx while rx is active */ +#if (((ADI_UART0_CFG_HOLD_TX < 0) || (ADI_UART0_CFG_HOLD_TX > 1)) || ((ADI_UART1_CFG_HOLD_TX < 0) || (ADI_UART1_CFG_HOLD_TX > 1))) +#error "Value for holding Tx while Rx is active needs to be 0 or 1" +#endif + +/* Check value de-assertion */ +#if (((ADI_UART0_CFG_DEASSERTION < 0) || (ADI_UART0_CFG_DEASSERTION > 1)) || ((ADI_UART1_CFG_DEASSERTION < 0) || (ADI_UART1_CFG_DEASSERTION > 1))) +#error "Value for de-assertion needs to be 0 or 1" +#endif + +/* Check value for SOUT polarity */ +#if (((ADI_UART0_CFG_SOUT_POLARITY < 0) || (ADI_UART0_CFG_SOUT_POLARITY > 1)) || ((ADI_UART1_CFG_SOUT_POLARITY < 0) || (ADI_UART1_CFG_SOUT_POLARITY > 1))) +#error "Value for SOUT polarity needs to be 0 or 1" +#endif + +/* Check value to enable autobaud detection */ +#if ((ADI_UART_CFG_ENABLE_AUTOBAUD < 0) || (ADI_UART_CFG_ENABLE_AUTOBAUD > 1)) +#error "Value for autobaud enable needs to be 0 or 1" +#endif + +/* Check value to enable Rx status interrupt */ +#if (((ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT < 0) || (ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT > 1)) || ((ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT < 0) || (ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT > 1))) +#error "Value to enable Rx status interrupt needs to be 0 or 1" +#endif + +/* Check value to enable modem status interrupt */ +#if (((ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT < 0) || (ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT > 1)) || ((ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT < 0) || (ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT > 1))) +#error "Value to enable modem status interrupt needs to be 0 or 1" +#endif + +#endif /* ADI_UART_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_wdt_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_wdt_config.h new file mode 100755 index 0000000000..25e47a7850 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_wdt_config.h @@ -0,0 +1,119 @@ +/*! ***************************************************************************** + * @file adi_wdt_config.h + * @brief WDT device driver configuration + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifndef ADI_WDT_CONFIG_H +#define ADI_WDT_CONFIG_H + + +/** @addtogroup WDT_Driver_Config Static Configuration + * @ingroup WDT_Driver + * @{ + */ + + +/************* WDT Static Configuration ***************/ + +/*! WDT Timer Reload Value\n + Value used to reload the WDT count register after count expires.\n + 0-65535 - WDT reload value (default is 0x0100). +*/ +#define ADI_WDT_LOAD_VALUE (0x1000u) + +/*! WDT Timer Mode\n + Selects WDT operating mode.\n + 0 - WDT operates in free-running mode.\n + 1 - WDT operates in periodic mode (default). +*/ +#define ADI_WDT_CONTROL_TIMER_MODE (1u) + +/*! WDT Clock Prescaler\n + Controls WDT clock prescale.\n + 0 - WDT operates at (source clock)/1.\n + 1 - WDT operates at (source clock)/16.\n + 2 - WDT operates at (source clock)/256 (default).\n +*/ +#define ADI_WDT_CONTROL_CLOCK_PRESCALER (2u) + +/*! WDT Timeout Mode\n + Controls WDT timeout behaviour.\n + 0 - WDT issues RESET on timeout (default).\n + 1 - WDT issues INTERRUPT on timeout. +*/ +#define ADI_WDT_CONTROL_TIMEOUT_MODE (0u) + +/*! WDT Power Mode Disable\n + Controls WDT countdown in hibernate or halted mode.\n + 0 - WDT continues to count down when core is halted or in hibernate.\n + 1 - WDT pauses count down when core is halted or in hibernate (default).\n +*/ +#define ADI_WDT_CONTROL_POWER_MODE (1u) + +/************** Macro Validation *****************************/ + +#if ( ADI_WDT_LOAD_VALUE > 65535u ) +#error "Invalid configuration" +#endif + +#if ( ADI_WDT_CONTROL_TIMER_MODE > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_WDT_CONTROL_CLOCK_PRESCALER > 2u ) +#error "Invalid configuration" +#endif + +#if ( ADI_WDT_CONTROL_TIMEOUT_MODE > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_WDT_CONTROL_POWER_MODE > 1u ) +#error "Invalid configuration" +#endif + +/** + * @} + */ + +#endif /* ADI_WDT_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc.c new file mode 100755 index 0000000000..4ea2233205 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc.c @@ -0,0 +1,1279 @@ +/*! **************************************************************************** + * @file: adi_crc.c + * @brief: CRC device driver global file. + * @details: This file contain the CRC device driver impelementation. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#include +#include + + +/** @addtogroup CRC_Driver CRC Device Driver + * @{ + +@brief Cyclic Redundancy Check (CRC) peripheral driver +@details + +The CRC peripheral is used to perform the Cyclic Redundancy Check (CRC) of the +block of data that is presented to the peripheral. The peripheral provides a +means to periodically verify the integrity of the system memory and it is based +on a CRC32 engine that computes the signature of 32-bit data presented to the +hardware engine. CRC operations can be core driven or DMA driven depending on +static configuration. + + - #ADI_CRC_CFG_ENABLE_DMA_SUPPORT set to 0 defines a core driven CRC driver + - #ADI_CRC_CFG_ENABLE_DMA_SUPPORT set to a non 0 value defines a DMA driven + CRC driver + +Core driven CRC operations + +The adi_crc_Compute function executes core driven CRC operations to calculate the +CRC on the buffer input with the CRC parameters set in the driver. In this mode, +data in the submitted buffer is transmitted to the CRC directly by the core. + +Memory DMA driver CRC operations + +The adi_crc_Compute function executes DMA driven CRC operations to calculate the +CRC on the buffer input with the CRC parameters set in the driver. In this mode, +data in the submitted buffer is transmitted to the CRC through DMA transfers. + +The software DMA channel reserved for the CRC driver is defined by a macro, +ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID, which can take a value between 0 and 7. +If this macro is not defined, e.g. in a configuration file, then its value +is defaulted to 7: in this case, DMA channel SIP7 is used by the CRC driver +and DMA_SIP7_Int_Handler becomes the interrupt used by the DMA when a transfer +to the CRC is complete. + +Computing CRC + +The CRC engine performs a 32-bit CRC operation on the incoming data stream. + +Sequence of function calls for Computing CRC :\n + - #adi_crc_Open() to open CRC device and get a valid CRC handle. + - #adi_crc_SetPolynomialVal() to set the polynomial value to be used in CRC operations. + - #adi_crc_SetBitMirroring() to enable/disable bit mirroring + - #adi_crc_SetByteMirroring() to enable/disable byte mirroring + - #adi_crc_SetLSBFirst() to indicate if data is Big or Little Endian. + - #adi_crc_IsCrcInProgress() to poll the current status of CRC operation or + wait for callback event. + - #adi_crc_GetFinalCrcVal() to get the CRC value of the data stream if its + CRC value is unknown. (Note that #adi_crc_GetFinalCrcVal resets the CRC + seed to the #ADI_CFG_CRC_SEED_VALUE default value.) + + Note that using statically configured parameters such as + #ADI_CFG_CRC_ENABLE_BYTE_MIRRORING, #ADI_CFG_CRC_ENABLE_BIT_MIRRORING, + #ADI_CFG_CRC_POLYNOMIAL and #ADI_CFG_CRC_SEED_VALUE, functions + #adi_crc_SetBitMirroring, #adi_crc_SetByteMirroring, #adi_crc_SetPolynomialVal + and #adi_crc_SetBitMirroring don't need to be called explicitly in your + application: the parameters will be assigned when opening the driver. + + @note - The application must include drivers/crc/adi_crc.h to use this driver. + @note - This driver also requires the DMA driver. The application must include + the DMA driver sources to avoid link errors. + */ + +/*! \cond PRIVATE */ +/*============= I N C L U D E S =============*/ + +#include +#include +#include "adi_crc_def.h" + +/*============= M I S R A =============*/ + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Pm152 (rule 17.4): array indexing shall only be applied to objects defined as an array type +* Relying on pointer arithmetic for buffer handling. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* Casts from pointer to uint32_t needed to determine pointer alignment. +*/ +#pragma diag_suppress=Pm123,Pm088,Pm152,Pm140 +#endif /* __ICCARM__ */ + +/*============== D E F I N E S ===============*/ + +/* CRC Peripheral specific information */ +#define ADI_CRC_NUM_DEVICES (1u) + +/*! \endcond */ + +#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT != 0) + +/** + * If a DMA channel has not been configured for the CRC driver, +* then a default software DMA channel is assigned: SIP7. + */ + +#ifndef ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID +#define ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID 7 +#pragma message("ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID implicitly defaulted to 7!") +#endif + +/** + * The following macros define + * - the Software DMA channel identifier to be used in CRC DMA driven operations + * - the ISR used by the CRC, which depends on the Software DMA channel + * selected to drive the CRC in DMA driven CRC operations. + * - the interrupt identifier mapped to the software DMA channel; selected for + * the CRC operations + */ +#if (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 0) +#define ADI_CFG_CRC_DMA_CHANNEL SIP0_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP0_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH16_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 1) +#define ADI_CFG_CRC_DMA_CHANNEL SIP1_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP1_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH17_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 2) +#define ADI_CFG_CRC_DMA_CHANNEL SIP2_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP2_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH18_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 3) +#define ADI_CFG_CRC_DMA_CHANNEL SIP3_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP3_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH19_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 4) +#define ADI_CFG_CRC_DMA_CHANNEL SIP4_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP4_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH20_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 5) +#define ADI_CFG_CRC_DMA_CHANNEL SIP5_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP5_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH21_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 6) +#define ADI_CFG_CRC_DMA_CHANNEL SIP6_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP6_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH22_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 7) +#define ADI_CFG_CRC_DMA_CHANNEL SIP7_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP7_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH23_DONE_IRQn +#else +#error "Invalid Software DMA channel identifier ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID: it must be between 0 and 7" +#endif + +#endif /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + +/*! \cond PRIVATE */ + +/** Check the validity of a CRC device identifier */ +#define ADI_CRC_VALID_DEVICE_ID(DEVNUM) ((DEVNUM)<(ADI_CRC_NUM_DEVICES)) + +/** Check that a CRC driver is in idle state */ +#define ADI_CRC_DEVICE_IS_IDLE(DEV) (((DEV)->eCrcOpStatus == ADI_CRC_OP_IDLE) ? true : false) + +/*============== D A T A ===============*/ + +/** + * Information for managing all the CRC devices available + */ +static ADI_CRC_INFO crc_device_info[ADI_CRC_NUM_DEVICES] = +{ + { pADI_CRC0, NULL } /* CRC 0 */ +}; + +/*============== M O R E D E F I N E S ===============*/ + +/** Check the validity of a CRC handle for debug mode */ +#define ADI_CRC_INVALID_HANDLE(h) ((NULL == (h)) || (crc_device_info[0].hDevice != (h))) + +/** Condition used to indicate if a CRC driver is already in use */ +#define ADI_CRC_DEVICE_IN_USE(DEVNUM) ((NULL) != crc_device_info[(DEVNUM)].hDevice) + +#ifdef ADI_DEBUG +#define HDL_TO_DEVICE_PTR(HDL) ((ADI_CRC_INVALID_HANDLE(HDL)) ? (NULL) : ((ADI_CRC_DEVICE*) (HDL))) +#else +#define HDL_TO_DEVICE_PTR(HDL) ((ADI_CRC_DEVICE*) (HDL)) +#endif + +/*============= C O D E =============*/ + +#if (ADI_CRC_NUM_DEVICES!=1u) +#error "!!! Current CRC driver implementation can deal with a unique CRC instance !!!" +#endif + +/*============= L O C A L F U N C T I O N S =============*/ + +/* Prototypes for static functions (required by MISRA-C:2004 Rule 8.1) */ + +static ADI_CRC_INFO *crc_DeviceInfo(ADI_CRC_HANDLE hDevice); + +static void crc_ResetRegisters (ADI_CRC_DEVICE *pDevice); + +#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0) + +/* Functions specific to core driven CRC operations */ + +static ADI_CRC_RESULT crc_ExecuteCoreDrivenOperation (ADI_CRC_DEVICE *pDevice, void *pCrcBuf, uint32_t NumBytes, uint32_t NumBits); + +#else + +/* Functions specific to DMA driven CRC operations */ + +static ADI_CRC_RESULT crc_ExecuteDmaDrivenOperation(ADI_CRC_DEVICE *pDevice, void *pCrcBuf, uint32_t NumBytes, uint32_t NumBits); +static void crc_CalculateCrcForRemaining(ADI_CRC_DEVICE *pDevice, uint8_t *pData, uint32_t NumBytes, uint32_t NumBits); +static void CRC_Callback_For_DMA_Err_Int_Handler(void *pcbparam, uint32_t nEvent, void *pArg); +void ADI_DMA_CRC_ISR(void); + +#endif /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + + +/** + * @brief return a pointer to the CRC device information mapped to the CRC + * device identified by a handle + * + * @param [in] hDevice CRC device handle + * + * @return pointer to CRC device information identified by hDevice + * (NULL if the CRC device handle is invalid) + */ +static ADI_CRC_INFO *crc_DeviceInfo(ADI_CRC_HANDLE hDevice) +{ + ADI_CRC_INFO *pCrcInfo = (ADI_CRC_INVALID_HANDLE(hDevice)) + ? NULL + : (&(crc_device_info[0])); + return pCrcInfo; +} + + +/** + * @brief Reset CRC registers to default values + * + * @details Reset CRC registers to default values as defined in configuration. + * + * @param [in] pDevice Pointer to CRC device + * + * @return None + */ +static void crc_ResetRegisters(ADI_CRC_DEVICE *pDevice) +{ + /* Cast the values to be assigned to the targetted types */ + const uint32_t byte_mirroring_val = (uint32_t) ADI_CFG_CRC_ENABLE_BYTE_MIRRORING; + const uint32_t byte_mirroring_pos = (uint32_t) BITP_CRC_CTL_BYTMIRR; + const uint32_t bit_mirroring_val = (uint32_t) ADI_CFG_CRC_ENABLE_BIT_MIRRORING; + const uint32_t bit_mirroring_pos = (uint32_t) BITP_CRC_CTL_BITMIRR; + const uint32_t seed_value = (uint32_t) ADI_CFG_CRC_SEED_VALUE; + const uint32_t polynomial = (uint32_t) ADI_CFG_CRC_POLYNOMIAL; + + /* Set byte mirroring and bit mirroring in CTL register as configured */ + pDevice->pReg->CTL = ( (byte_mirroring_val << byte_mirroring_pos) + | (bit_mirroring_val << bit_mirroring_pos) + ); + pDevice->pReg->RESULT = seed_value; + pDevice->pReg->POLY = polynomial; +} + +#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0) + +/* + * @brief Starts core driven CRC operation. + * + * @param [in] pDevice Pointer to CRC device + * @param [in] pCrcBuf Address of data buffer. + * @param [in] NumBytes Number of bytes in data buffer. + * @param [in] NumBits Number of bits, 0 to 7, in the last partial byte + * in CRC data buffer + * + * @return Status + * - ADI_CRC_SUCCESS: Successfully set expected CRC result. + */ +static ADI_CRC_RESULT crc_ExecuteCoreDrivenOperation( + ADI_CRC_DEVICE *pDevice, + void *pCrcBuf, + uint32_t NumBytes, + uint32_t NumBits) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + uint8_t *pData = (uint8_t *)pCrcBuf; /* initialize the pointer to data to the start of the data buffer */ + uint32_t lsbFirst = pDevice->pReg->CTL & BITM_CRC_CTL_LSBFIRST; + + pDevice->pReg->CTL |= (BITM_CRC_CTL_EN); /*! enable CRC peripheral */ + + if (((uint32_t)pData & 0x3u) != 0u) /* If the buffer is not 4-byte aligned */ + { + /* feed the CRC byte per byte as long as there are data in the input buffer AND + * the data left in the buffer are not 4-byte aligned */ + while ((NumBytes > 0u) && (((uint32_t)pData & 0x3u) != 0u)) + { + pDevice->pReg->IPBYTE = *pData; /* feed the CRC with the first byte in the buffer */ + pData++; /* get the next byte to feed into CRC */ + NumBytes--; /* decrease the number of bytes to be processed */ + } + } + + /* data left in the input buffer are now 4-byte aligned */ + + while (NumBytes >= 4u) /* if the number of bytes left is greater than 4 bytes */ + { /* feed CRC peripheral with 4-byte data */ + uint32_t nData; /* 32-bit variable to be used to feed the CRC peripheral */ + + /* + * Here we assume memory is little endian. We need change the following + * code if we produce a Cortex-M processor with big endian memory. + */ + if (lsbFirst != 0u) + { + nData = pData[3]; + nData = (nData << 8) | pData[2]; + nData = (nData << 8) | pData[1]; + nData = (nData << 8) | pData[0]; + } + else + { + nData = pData[0]; + nData = (nData << 8) | pData[1]; + nData = (nData << 8) | pData[2]; + nData = (nData << 8) | pData[3]; + } + pDevice->pReg->IPDATA = nData; /* feed the CRC peripheral with 32-bit data input */ + pData += 4; /* move the data pointer in the data buffer */ + NumBytes -= 4u; /* decrease the number of data to be processed */ + } + + while (NumBytes > 0u) /* if the number of data left in the input buffer is smaller than 4 */ + { + pDevice->pReg->IPBYTE = *pData; /* feed the CRC peripheral with the remaining bytes */ + pData++; /* move the pointer to the next byte in input data buffer */ + NumBytes--; /* decrease the number of data to be fed into the CRC peripheral */ + } + + if (NumBits > 0u) /* if the last byte is a partial byte containing less than 8 bits */ + { + pDevice->pReg->IPBITS[NumBits] = *pData;/* feed the CRC peripheral with the remaining bits (use IPBITS[N] to feed N bits) */ + } + + pDevice->pReg->CTL &= ~(BITM_CRC_CTL_EN); /* All the data have been fed into the CRC peripheral : disable it */ + pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE; /* CRC back in idle state */ + return result; +} + +#else /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + +/** + * @brief Send a Memory DMA request to the CRC, which triggers a DMA driven + * CRC operation. + * + * @param [in] pDevice Pointer to CRC device + * @param [in] pCrcBuf Address of data buffer. + * @param [in] NumBytes Number of whole bytes in data buffer. + * @param [in] NumBits Number of bits, 0 to 7, in the last partial byte + * in CRC data buffer + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully set expected CRC result. + * - #ADI_CRC_INVALID_DMA_CHANNEL: DMA channel cannot be used with CRC + */ +static ADI_CRC_RESULT crc_ExecuteDmaDrivenOperation( + ADI_CRC_DEVICE *pDevice, + void *pCrcBuf, + uint32_t NumBytes, + uint32_t NumBits) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + uint8_t *pData = (uint8_t *)pCrcBuf; + bool bUseDma = false; /* assume core driven CRC by default */ + +#ifdef ADI_DEBUG + if (!ADI_CRC_VALID_DMA_CHANNEL(ADI_CFG_CRC_DMA_CHANNEL)) + { + /* Report error as Memory DMA not open */ + result = ADI_CRC_INVALID_DMA_CHANNEL; + } + else +#endif /* ADI_DEBUG */ + { + /* If LSBFIRST, it's easy. */ + if ((pDevice->pReg->CTL & BITM_CRC_CTL_LSBFIRST) != 0u) + { + /* If the buffer is not 4-byte aligned */ + if (((uint32_t)pData & 0x3u) != 0u) + { + /* process the first bytes until a 4-byte aligned data location is reached */ + pDevice->pReg->CTL |= (BITM_CRC_CTL_EN); /* enable CRC */ + while ((NumBytes > 0u) && (((uint32_t)pData & 0x3u) != 0u)) + { + pDevice->pReg->IPBYTE = *pData; /* feed byte into CRC */ + pData++; /* get to the next byte */ + NumBytes--; /* decrease the number of bytes still to be processed */ + } + pDevice->pReg->CTL &= ~(BITM_CRC_CTL_EN); /* disable CRC */ + } + + /* 4-byte aligned data transfer */ + if (NumBytes >= 4u) + { + /* there are enough data for kicking off a DMA driven CRC operation */ + const uint32_t channelId = (uint32_t) ADI_CFG_CRC_DMA_CHANNEL; + const uint32_t channelBit = 1ul << channelId; /* get a value with the bit set at position identified by channelId */ + const uint32_t numData = NumBytes / 4u; /* number of 4-byte data to be transferred */ + const uint32_t src = (uint32_t) pData; /* DMA source address */ + const uint32_t dst = (uint32_t) &pDevice->pReg->IPDATA; /* destination is CRC IPDATA 32-bit register */ + const uint32_t numTransData = ( (numData > DMA_TRANSFER_LIMIT) + ? DMA_TRANSFER_LIMIT + : numData + ); + const uint32_t numTransBytes = (numTransData << 2u); + const uint32_t lastDataPos = (numTransBytes - 4u); /* position of last 32-bit data to be transferred in current DMA request */ + + pDevice->pReg->CTL |= ((uint32_t) BITM_CRC_CTL_EN); /* enable CRC (leave other bits unmodified) */ + + pADI_DMA0->EN_SET = channelBit; /* Enable the channel */ + pADI_DMA0->ALT_CLR = channelBit; /* Set the primary as the current DMA descriptor */ + pADI_DMA0->SRCADDR_CLR = channelBit; /* Ensure decrement for source is cleared */ + pADI_DMA0->DSTADDR_CLR = channelBit; /* Ensure decrement for destination is cleared */ + + pPrimaryCCD[channelId].DMADSTEND = dst; /* destination is CRC IPDATA 32-bit register */ + pPrimaryCCD[channelId].DMASRCEND = src + lastDataPos; /* source end address */ + + pPrimaryCCD[channelId].DMACDC = + ( (((uint32_t) ADI_DMA_INCR_NONE) << ((uint32_t) DMA_BITP_CTL_DST_INC)) /* destination address not incremented */ + | (((uint32_t) ADI_DMA_INCR_4_BYTE) << ((uint32_t) DMA_BITP_CTL_SRC_INC)) /* source address incremented by 4 bytes */ + | (((uint32_t) ADI_DMA_WIDTH_4_BYTE) << ((uint32_t) DMA_BITP_CTL_SRC_SIZE)) /* source data size is 4-byte */ + | ((numTransData - 1u) << ((uint32_t) DMA_BITP_CTL_N_MINUS_1))/* number of DMA transfers (minus 1) */ + | (DMA_ENUM_CTL_CYCLE_CTL_AUTO_REQ << DMA_BITP_CTL_CYCLE_CTL) /* DMA Auto Request transmission */ + ); + pDevice->pRemainingData = (void*)(src + numTransBytes); /* remaining data start address */ + pDevice->RemainingBytes = NumBytes - numTransBytes; /* remaining bytes that cannot be processed in this DMA batch */ + pDevice->RemainingBits = NumBits; /* remaining bits if last byte is a partial byte */ + bUseDma = true; /* there are enough data to run 4-byte DMA transfers to CRC */ + } + } + /* + * If ! LSBFIRST, we need the DMA controller support byte swap for fixed destination address. + * But we don't have such luck, although it supports byte swap for fixed source address. + * So we have to set DMA size to one byte, which is slower. + * + * Another option is using mirroring feature of CRC unit, which would be more complicated. + */ + else + { + if (NumBytes > 0u) + { + /** + * There are enough data for kicking off a DMA driven CRC operation. + * DMA transfers are limited to 1024 bytes : if the buffer is larger + * than 1024 then generate repeated DMA request through the CRC DMA + * interrupt handler, i.e. the interrupt handler used by the software + * DMA channel driving the CRC operations. + */ + const uint32_t channelId = (uint32_t) ADI_CFG_CRC_DMA_CHANNEL; + const uint32_t channelBit = 1ul << channelId; /* get a value with the bit set at position identified by channelId */ + const uint32_t src = (uint32_t) pData; /* DMA source address */ + const uint32_t dst = (uint32_t) &pDevice->pReg->IPBYTE; /* destination is CRC IPBYTE 8-bit register */ + const uint32_t numTransData = ( (NumBytes > DMA_TRANSFER_LIMIT) + ? DMA_TRANSFER_LIMIT + : NumBytes + ); + const uint32_t lastDataPos = (numTransData - 1u); /* position of last data to be transferred in buffer */ + + pDevice->pReg->CTL |= (BITM_CRC_CTL_EN); /* enable CRC (leave other bits unmodified) */ + + pADI_DMA0->EN_SET = channelBit; /* Enable the channel */ + pADI_DMA0->ALT_CLR = channelBit; /* Set the primary as the current DMA descriptor */ + pADI_DMA0->SRCADDR_CLR = channelBit; /* Ensure decrement for source is cleared */ + pADI_DMA0->DSTADDR_CLR = channelBit; /* Ensure decrement for destination is cleared */ + + pPrimaryCCD[channelId].DMADSTEND = dst; /* destination is CRC IPBYTE 8-bit register */ + pPrimaryCCD[channelId].DMASRCEND = src + lastDataPos; /* source end address */ + pPrimaryCCD[channelId].DMACDC = + ( (((uint32_t) ADI_DMA_INCR_NONE) << ((uint32_t) DMA_BITP_CTL_DST_INC)) /* destination address not incremented */ + | (((uint32_t) ADI_DMA_INCR_1_BYTE) << ((uint32_t) DMA_BITP_CTL_SRC_INC)) /* source address incremented by 1 byte */ + | (((uint32_t) ADI_DMA_WIDTH_1_BYTE) << ((uint32_t) DMA_BITP_CTL_SRC_SIZE)) /* source data size is 1-byte */ + | ((numTransData - 1u) << ((uint32_t) DMA_BITP_CTL_N_MINUS_1))/* number of DMA transfers (minus 1) */ + | (DMA_ENUM_CTL_CYCLE_CTL_AUTO_REQ << DMA_BITP_CTL_CYCLE_CTL) /* DMA Auto Request transmission */ + ); + pDevice->pRemainingData = (void*) (src + numTransData); /* remaining data start address */ + pDevice->RemainingBytes = NumBytes - numTransData; /* remaining bytes */ + pDevice->RemainingBits = NumBits; /* remaining bits if last byte is a partial byte */ + bUseDma = true; /* there are enough data to run 4-byte DMA transfers to CRC */ + } + } + + /* if we are in a position to use the DMA to transfer data to the CRC */ + if (bUseDma== true) + { + const uint32_t channelId = (uint32_t) ADI_CFG_CRC_DMA_CHANNEL; + const uint32_t channelBit = 1ul << channelId; /* get a value with the bit set at position identified by channelId */ + pADI_DMA0->SWREQ = channelBit; /* Issue a software DMA request */ + } + else + { + pDevice->pReg->CTL |= (BITM_CRC_CTL_EN); + crc_CalculateCrcForRemaining(pDevice, pData, NumBytes, NumBits); + pDevice->pReg->CTL &= ~(BITM_CRC_CTL_EN); + if(pDevice->pfCallback != NULL) + { + pDevice->pfCallback(pDevice->pCBParam, (uint32_t) ADI_CRC_EVENT_BUFFER_PROCESSED, pData); + } + pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE; /* CRC calculation completed */ + } + } + return result; +} + +/** + * @brief Completes a DMA driven CRC operation by dealing with remaining + * data, usually when the number of bytes left is smaller than 4. + * + * @param [in] pDevice Pointer to CRC device + * @param [in] pData Address of data buffer. + * @param [in] NumBytes Number of whole bytes in data buffer. + * @param [in] NumBits Number of bits, 0 to 7, in the last partial byte + * in CRC data buffer + */ +static void crc_CalculateCrcForRemaining(ADI_CRC_DEVICE *pDevice, uint8_t *pData, uint32_t NumBytes, uint32_t NumBits) +{ + /* process the remaining bytes */ + while (NumBytes > 0u) + { + pDevice->pReg->IPBYTE = *pData; + pData++; + NumBytes--; + } + + /* process the remaining bits in the last byte if the number of bits is smaller than 8 */ + if (NumBits > 0u) + { + pDevice->pReg->IPBITS[NumBits] = *pData; + } +} + +/** + * @brief Callback function used by the DMA when a DMA error occurs + * + * @details Callback function used by the DMA when a DMA error must be reported + * to the CRC driver because it affects the DMA channel driving the CRC. + */ +static void CRC_Callback_For_DMA_Err_Int_Handler(void *pcbparam, uint32_t nEvent, void *pArg) +{ + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(pcbparam); + + if (NULL != pDevice) + { + /* DMA error detected */ + pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE; /* mark the CRC peripheral as IDLE */ + pDevice->pReg->CTL &= (uint32_t)(~(BITM_CRC_CTL_EN)); /* disable CRC peripheral */ + } +} + +/** + * @brief interrupt handler used by the software DMA channel driving the CRC + * + * @details interrupt handler used by the software DMA channel driving the CRC + * ADI_DMA_CRC_ISR is a macro with the final interrupt handler name + * being DMA_SIP0_Int_Handler, ..., DMA_SIP7_Int_Handler, depending + * on the software DMA channel driving the CRC. + */ +void ADI_DMA_CRC_ISR(void) +{ + ISR_PROLOG(); + + if (ADI_CRC_DEVICE_IN_USE(0)) + { + ADI_CRC_DEVICE * pDevice = HDL_TO_DEVICE_PTR(crc_device_info[0].hDevice); + if (NULL != pDevice) + { + uint8_t *pData = (uint8_t *)(pDevice->pRemainingData); + uint32_t NumBytes = pDevice->RemainingBytes; + uint32_t NumBits = pDevice->RemainingBits; + bool finishing = (NumBytes < 4u); + + if (!finishing) + { + /* there's enough data left for another DMA transfer */ + ADI_CRC_RESULT result = pDevice->pfSubmitBuffer(pDevice, pData, NumBytes, NumBits); + if (ADI_CRC_SUCCESS != result) + { + /* buffer submission failed: complete the task through core driven operations */ + finishing = true; + } + } + + if (finishing) + { + /* There are a very few bytes/bits left to be processed or + * a DMA transfer request could not be sent */ + crc_CalculateCrcForRemaining(pDevice, pData, NumBytes, NumBits); + + /* if a callback function is registered with the interrupt handler + * associated with the software DMA channel driving the CRC */ + if(pDevice->pfCallback != NULL) + { + pDevice->pfCallback(pDevice->pCBParam, (uint32_t) ADI_CRC_EVENT_BUFFER_PROCESSED, NULL); + } + pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE; /* CRC back in idle state */ + + } + } + } + +#if defined(ADI_CYCLECOUNT_CRC_ISR_ENABLED) && (ADI_CYCLECOUNT_CRC_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_CRC); +#endif + + ISR_EPILOG(); +} + +#endif /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + +/*! \endcond */ + +/*============= P U B L I C F U N C T I O N S =============*/ + +/** + * @brief Opens a CRC device instance. + * + * @param [in] DeviceNum Number identifying the CRC Device to open. + * @param [in] pMemory Pointer to a #ADI_CRC_MEMORY_SIZE. + * sized buffer to manage the device instance. + * @param [in] MemorySize Size of the buffer to which "pMemory" points. + * @param [out] phDevice Pointer to a location where CRC device handle to be written. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully opened a CRC device. + * - #ADI_CRC_BAD_DEVICE_NUMBER [D]: Supplied CRC Device ID is invalid. + * - #ADI_CRC_IN_USE [D]: Supplied CRC Device ID is already in use. + * - #ADI_CRC_INSUFFICIENT_MEMORY [D]: Supplied memory is not sufficient to handle a CRC device instance. + * - #ADI_CRC_FAILURE [D]: callback registration failed for CRC function used by DMA Error Interrupt Handler. + * + * @note For the device memory should be of size #ADI_CRC_MEMORY_SIZE. + * + */ +ADI_CRC_RESULT adi_crc_Open( + uint32_t DeviceNum, + void *pMemory, + uint32_t MemorySize, + ADI_CRC_HANDLE *phDevice) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = (ADI_CRC_DEVICE*) pMemory;/* memory block to be used to manage a CRC driver instance */ + +#ifdef ADI_DEBUG /* IF (Debug information enabled) */ + if (!ADI_CRC_VALID_DEVICE_ID(DeviceNum)) /* IF (This is not a valid CRC device number) */ + { + result = ADI_CRC_BAD_DEVICE_NUMBER; /* Report failure as bad device number */ + } + else if (ADI_CRC_DEVICE_IN_USE(DeviceNum)) /* IF (The device is in use) */ + { + result = ADI_CRC_IN_USE; /* return CRC Device in use error */ + } + else if ( (MemorySize < ADI_CRC_MEMORY_SIZE) /* IF (Supplied memory size is insufficient) */ + || (ADI_CRC_MEMORY_SIZE < sizeof(ADI_CRC_DEVICE)) + ) + { + result = ADI_CRC_INSUFFICIENT_MEMORY; /* Report failure as insufficient memory */ + } + else +#endif /* ADI_DEBUG */ + { + /* check that ADI_CRC_MEMORY_SIZE is accurately defined */ + assert(ADI_CRC_MEMORY_SIZE == sizeof(ADI_CRC_DEVICE)); + + memset(pMemory, 0, MemorySize); /* Clear the given memory */ + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); /* Entering critical region, disable interrupts */ + + /* Save the supplied device memory address */ + crc_device_info[DeviceNum].hDevice = (ADI_CRC_HANDLE)pDevice; + pDevice->pReg = crc_device_info[DeviceNum].pReg; + + ADI_EXIT_CRITICAL_REGION(); /* Re-enable interrupts */ + + crc_ResetRegisters(pDevice); /* Reset CRC registers */ + *phDevice = crc_device_info[DeviceNum].hDevice; /* Pass a valid handle to this CRC device */ + +#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0) + + pDevice->pfSubmitBuffer = &crc_ExecuteCoreDrivenOperation; + +#else /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + + pDevice->pfSubmitBuffer = &crc_ExecuteDmaDrivenOperation; + adi_dma_Init(); + + /* Register CRC DMA callback */ +#ifdef ADI_DEBUG /* IF (Debug information enabled) */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,CRC_Callback_For_DMA_Err_Int_Handler,pDevice)) + { + result = ADI_CRC_FAILURE; + } +#else + adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,CRC_Callback_For_DMA_Err_Int_Handler,pDevice); +#endif + NVIC_EnableIRQ(ADI_CRC_IRQ_ID); /* Enable the interrupt for the DMA channel used by CRC */ +#endif /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + } + return result; +} + +/** + * @brief Closes CRC device instance opened for use. + * + * @param [in] hDevice Handle to CRC Device instance to close. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully closed CRC device. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + * - #ADI_CRC_FAILURE [D]: callback un-registration failed for CRC function used by DMA Error Interrupt Handler. + */ +ADI_CRC_RESULT adi_crc_Close(ADI_CRC_HANDLE const hDevice) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_INFO *pCrcInfo = crc_DeviceInfo(hDevice); /* get CRC info pointer from CRC handle */ +#ifdef ADI_DEBUG + if (NULL == pCrcInfo) + { + result = ADI_CRC_BAD_HANDLE; /* invalid CRC handle being used */ + } + else +#endif + { +#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT != 0) + NVIC_DisableIRQ(ADI_CRC_IRQ_ID); /* Disable the interrupt for the DMA channel used by CRC. */ + /* Register CRC DMA callback */ +#ifdef ADI_DEBUG /* IF (Debug information enabled) */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,NULL,NULL)) + { + result = ADI_CRC_FAILURE; + } +#else + adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,NULL,NULL); +#endif +#endif + pCrcInfo->hDevice = NULL; /* Mark CRC driver as closed */ + } + return result; +} +/*! + * @brief Set the bit mirroring. This function should be called only when device is idle, + * i.e. when no data are being processd by the CRC. + * + * @param[in] hDevice Device handle obtained from adi_crc_Open(). + * @param[in] bEnable Boolean flag to enable/disable bit mirroring. + * true : To Enable bit mirroring. + * false : To Disable bit mirroring. + * + * @return Status + * - #ADI_CRC_SUCCESS: Call completed successfully. + * - #ADI_CRC_BAD_HANDLE [D] :Invalid device handle parameter. + * - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered. + * + * @sa adi_crc_SetByteMirroring(). + * @sa adi_crc_SetWordSwap(). + */ +ADI_CRC_RESULT adi_crc_SetBitMirroring(ADI_CRC_HANDLE const hDevice, const bool bEnable) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); /* get CRC device pointer from CRC handle */ + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* Function not permitted when CRC operation is in progress */ + } + else +#endif + if(bEnable == true) + { + pDevice->pReg->CTL |= (BITM_CRC_CTL_BITMIRR); /* enable bit mirroring */ + } + else + { + pDevice->pReg->CTL &= (uint32_t)(~(BITM_CRC_CTL_BITMIRR)); /* disable bit mirroring */ + } + return result; +} +/*! + * @brief Set the byte mirroring. This function should be called only when device is disabled. + * + * @param[in] hDevice Device handle obtained from adi_crc_Open(). + * @param[in] bEnable Boolean flag to enable/disable byte mirroring. + * true : To Enable byte mirroring. + * false : To Disable byte mirroring. + * + * @return Status + * - #ADI_CRC_SUCCESS: Call completed successfully. + * - #ADI_CRC_BAD_HANDLE [D]: Invalid device handle parameter. + * - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered. + * + * + * @sa adi_crc_EnableBitMirroring(). + * @sa adi_crc_EnableWordSwap(). + */ +ADI_CRC_RESULT adi_crc_SetByteMirroring(ADI_CRC_HANDLE const hDevice, const bool bEnable) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); /* get CRC device pointer from CRC handle */ + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* Function not permitted when CRC operation is in progress */ + } + else +#endif + if(bEnable == true) + { + pDevice->pReg->CTL |= (BITM_CRC_CTL_BYTMIRR); /* enable byte mirroring */ + } + else + { + pDevice->pReg->CTL &= (uint32_t)(~(BITM_CRC_CTL_BYTMIRR)); /* disable byte mirroring */ + } + return result; +} + +/*! + * @brief Enable the LSB first. + * + * @param[in] hDevice Device handle obtained from adi_crc_Open(). + * @param[in] bEnable Boolean flag which indicate whether LSB first OR MSB first for CRC calculation. + * true : For LSB First CRC calculation + * false : For MSB First CRC calculation + * + * @return Status + * - #ADI_CRC_SUCCESS: Call completed successfully. + * - #ADI_CRC_BAD_HANDLE [D]: Invalid device handle parameter. + * - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered. + * + * + * @sa adi_crc_EnableBitmirroring(). + * @sa adi_crc_EnableWordSwap(). + */ + +ADI_CRC_RESULT adi_crc_SetLSBFirst(ADI_CRC_HANDLE const hDevice, const bool bEnable) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); /* get CRC device pointer from CRC handle */ + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* function not permitted when CRC operation is in progress */ + } + else +#endif + if(bEnable == true) + { + pDevice->pReg->CTL |= (BITM_CRC_CTL_LSBFIRST); /* enable LSB first (MSB first disable) */ + } + else + { + pDevice->pReg->CTL &= ~(BITM_CRC_CTL_LSBFIRST); /* disable LSB first (MSB first enable) */ + } + return result; +} +/*! + * @brief To enable/disable the word Swap. This function should be called only when device is disabled. + * + * @param[in] hDevice Device handle obtained from adi_crc_Open(). + * @param[in] bEnable Boolean flag to enable/disable word swap. + * true : To Enable word swap. + * false : To Disable word swap. + * + * @return Status + * - #ADI_CRC_SUCCESS: Call completed successfully. + * - #ADI_CRC_BAD_HANDLE [D]: Invalid device handle parameter. + * - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered. + * + * + * @sa adi_crc_SetBitMirroring(). + * @sa adi_crc_SetByteMirroring(). + */ +ADI_CRC_RESULT adi_crc_EnableWordSwap(ADI_CRC_HANDLE const hDevice, const bool bEnable) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* function not permitted when CRC operation is in progress */ + } + else +#endif + if(bEnable == true) + { + pDevice->pReg->CTL |= BITM_CRC_CTL_W16SWP; /* enable word swap */ + } + else + { + pDevice->pReg->CTL &= ~BITM_CRC_CTL_W16SWP; /* disable word swap */ + } + + return result; +} +/** + * @brief Sets the initial seed value for the CRC operation that is about to take place. + * + * @param [in] hDevice Handle to CRC device instance to work on. + * @param [in] CrcSeedVal Initial seed value for the CRC operation that is about to take place. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully set CRC seed value. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + * - #ADI_CRC_FN_NOT_PERMITTED [D] : Function not permitted when CRC operation is in progress. + * + */ +ADI_CRC_RESULT adi_crc_SetCrcSeedVal( + ADI_CRC_HANDLE const hDevice, + uint32_t CrcSeedVal) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* function not permitted when CRC operation is in progress */ + } + else +#endif /* ADI_DEBUG */ + { + pDevice->pReg->RESULT = CrcSeedVal; /* Load the CRC seed value */ + } + return result; +} + +/** + * @brief Sets the 32-bit polynomial for CRC operations. + * + * @param [in] hDevice Handle to CRC device instance to work on. + * @param [in] PolynomialVal 32-bit CRC polynomial to use for CRC operation. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully set polynomial value. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + * - #ADI_CRC_FN_NOT_PERMITTED [D]: Function not permitted when CRC operation is in progress. + * + */ +ADI_CRC_RESULT adi_crc_SetPolynomialVal( + ADI_CRC_HANDLE const hDevice, + uint32_t PolynomialVal) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* function not permitted when CRC operation is in progress */ + } + else +#endif /* ADI_DEBUG */ + { + pDevice->pReg->POLY = PolynomialVal; /* Load Polynomial value */ + } + return result; +} + +/** + * @brief Submits data buffer for CRC computation + * + * @details This API can be used to submit data buffer for CRC computation. + * If NumBits is in [0..7] then the number of bytes to be processed + * is NumBytes plus one partial byte containing NumBits bits. + * If DMA mode of operation is selected, buffer is processed using + * the specified DMA channel. + * + * @param [in] hDevice Handle of CRC device + * @param [in] pCrcBuf Address of CRC data buffer + * @param [in] NumBytes Number of whole bytes in CRC data buffer + * @param [in] NumBits Number of bits, 0 to 7, in the last partial byte + * in CRC data buffer + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully submitted data buffer. + * - #ADI_CRC_INVALID_PARAMETER [D]: one of the parameter used is invalid. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + * - #ADI_CRC_FN_NOT_SUPPORTED [D]: Function not supported by this CRC revision. + * - #ADI_CRC_FN_NOT_PERMITTED [D]: Function not permitted when CRC operation is in progress. + * - #ADI_CRC_INVALID_DMA_CHANNEL: DMA channel cannot be used with CRC (from crc_DmaDrivenOperation) + */ +ADI_CRC_RESULT adi_crc_Compute( + ADI_CRC_HANDLE const hDevice, + void *pCrcBuf, + uint32_t NumBytes, + uint32_t NumBits) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); +#ifdef ADI_DEBUG + if (NumBits >= 8u) + { + result = ADI_CRC_INVALID_PARAMETER; + } + else if (NULL == pDevice) + { + result = ADI_CRC_BAD_HANDLE; + } + else if (((pDevice->pReg->CTL & BITM_CRC_CTL_REVID) == 0u) && (NumBits != 0u)) + { + result = ADI_CRC_FN_NOT_SUPPORTED; /* Partial byte needs CRC unit revision 1 or up */ + } + else + if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* function not permitted when CRC operation is in progress */ + } + else +#endif /* ADI_DEBUG */ + { + pDevice->eCrcOpStatus = ADI_CRC_OP_IN_PROGRESS; /* mark the CRC as in progress */ + result = pDevice->pfSubmitBuffer(pDevice, pCrcBuf, NumBytes, NumBits); + + /* CRC returns in IDLE mode when it has processed all its data, not after submitting a request */ + } + return result; +} + +/** + * @brief Gets the current CRC peripheral status. + * + * @param [in] hDevice Handle to CRC device instance to work on + * @param [in] pbCrcInProgress Pointer to location to store the current status of CRC peripheral. + * 'true' when CRC peripheral is in currently performing a CRC operation. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully set expected CRC result. + * - #ADI_CRC_BAD_HANDLE [D}: Supplied CRC handle is invalid. + * + * @note This function is valid only when device is operating in DMA mode. + * + */ +ADI_CRC_RESULT adi_crc_IsCrcInProgress( + ADI_CRC_HANDLE const hDevice, + bool *pbCrcInProgress) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else +#endif /* ADI_DEBUG */ + { + + if ((pDevice)->eCrcOpStatus == ADI_CRC_OP_IN_PROGRESS) + { + *pbCrcInProgress = true; + + } + else + { + *pbCrcInProgress = false; + + } + } + return result; +} + +/** + * @brief Gets the final CRC result computed for a data stream + * + * @details This API gets the final CRC result computed for a data stream + * and clears the current and final CRC results register. + * The CRC Current result register holds the current or + * intermediate CRC result. Whenever a CRC operation is initiated, + * the CRC peripheral takes the CRC Current register value as + * initial seed for CRC computation. This API clears both results + * register to start a fresh CRC computation. + * Use the adi_crc_GetCurrentCrcVal() API to get an intermediate + * CRC result without clearing the results register. + * + * @param [in] hDevice Handle to CRC device instance to work on + * @param [out] pFinalCrcVal Pointer to location where the final CRC result of + * a data stream to be processed will be written. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully read final CRC result. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + */ +ADI_CRC_RESULT adi_crc_GetFinalCrcVal( + ADI_CRC_HANDLE const hDevice, + uint32_t *pFinalCrcVal) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else +#endif /* ADI_DEBUG */ + { + const uint32_t seed_value = (uint32_t) ADI_CFG_CRC_SEED_VALUE; + *pFinalCrcVal = pDevice->pReg->RESULT; /* Get the final CRC result */ + pDevice->pReg->RESULT = seed_value; + } + return result; +} + +/** + * @brief Gets the current/intermediate CRC result computed for a data stream. + * + * @param [in] hDevice Handle to CRC device instance to work on + * @param [out] pCurrentCrcVal Pointer to location where the intermediate CRC result of + * a data stream to be processed will be written. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully read current CRC result. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + */ +ADI_CRC_RESULT adi_crc_GetCurrentCrcVal( + ADI_CRC_HANDLE const hDevice, + uint32_t *pCurrentCrcVal) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else +#endif /* ADI_DEBUG */ + { + *pCurrentCrcVal = pDevice->pReg->RESULT; /* Get the current CRC result */ + } + + return result; +} + +/** + * @brief Registers or unregisters a callback with the CRC device + * + * @details It is not required to register a callback for the operation of the + * driver. Data compare or DMA error will be notified via the + * adi_crc_IsCrcInProgress() API. But if an application requires the + * errors/events to be notified immediately it can register a callback + * with the driver which will be called to notify errors/events. + * + * When a callback is registered the API adi_crc_IsCrcInProgress() + * will not return error. + * + * @param [in] hDevice Handle to CRC device instance to work on + * @param [in] pfCallback Pointer to application callback function. The callback function + * has the prototype + * void callback(void *pCBParam, uint32_t nEvent, void *pArg) + * To unregister a callback pass the the pointer to the callback + * function as NULL. + * @param [in] pCBParam Callback parameter which will be returned back to the + * application when the callback function is called. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully registered callback. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + */ +ADI_CRC_RESULT adi_crc_RegisterCallback( + ADI_CRC_HANDLE const hDevice, + ADI_CALLBACK pfCallback, + void *const pCBParam) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); /* Entering critical region, disable interrupts */ + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else +#endif /* ADI_DEBUG */ + { + /* Update CRC Callback information */ + pDevice->pfCallback = pfCallback; + pDevice->pCBParam = pCBParam; + } + + ADI_EXIT_CRITICAL_REGION(); /* Re-enable interrupts */ + + return result; +} + + +/*****/ + +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc_def.h new file mode 100755 index 0000000000..1558146d56 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc_def.h @@ -0,0 +1,92 @@ +/*! ***************************************************************************** + * @file: adi_crc_def.h + * @brief: Private header file for for CRC driver. + * @details + * This is a private header file for the CRC driver, + * which contains the API declarations, data and + * constant definitions used in driver implementation + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_CRC_DEF_H +#define ADI_CRC_DEF_H + +/* CRC Driver includes */ +#include + +/*! \cond PRIVATE */ + +typedef struct __ADI_CRC_DEVICE ADI_CRC_DEVICE; +typedef ADI_CRC_RESULT (*CRC_BUFFER_SUBMIT) (ADI_CRC_DEVICE *pDevice, void *pBuffer, uint32_t NumBytes, uint32_t NumBits); + +/* Enumeration of CRC operation status */ +typedef enum +{ + ADI_CRC_OP_IDLE = 0u, /* CRC idle */ + ADI_CRC_OP_IN_PROGRESS = 0x01u, /* CRC operation in progress */ +} ADI_CRC_OP_STATUS; + + +#pragma pack() + +/* Structure to handle CRC Peripheral instance */ +struct __ADI_CRC_DEVICE +{ + volatile ADI_CRC_TypeDef *pReg; + CRC_BUFFER_SUBMIT pfSubmitBuffer; /* Function for submitting CRC data buffer for calculation */ + ADI_CALLBACK pfCallback; /* Client supplied callback function */ + void *pCBParam; /* Client supplied callback parameter */ + void *pRemainingData; /* Pointer to the buffer containing remaining bytes */ + uint32_t RemainingBytes; /* Remaining bytes */ + uint32_t RemainingBits; /* Remaining bits */ + ADI_CRC_OP_STATUS eCrcOpStatus; /* Current status of the CRC Operation */ +}; + +/* Structure to hold CRC device specific information */ +typedef struct +{ + volatile ADI_CRC_TypeDef *pReg; /* CRC peripheral Registers */ + ADI_CRC_HANDLE hDevice; /* CRC device handle */ +} ADI_CRC_INFO; + +/*! \endcond */ + +#endif /* ADI_CRC_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto.c new file mode 100755 index 0000000000..e940557165 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto.c @@ -0,0 +1,1577 @@ +/*! ***************************************************************************** + * @file: adi_crypto.c + * @brief: CRYPTO device driver source file. + * @details: This is the Crypto driver implementation file. + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/*! \addtogroup Crypto_Driver Crypto Driver + * @{ + * + * @brief Crypto Driver + * + * @details + * + * The Crypto controller provides hardware acceleration of various AES cryptographic + * cipher modes, including: ECB, CBC, CTR, CMAC, CCM, and SGA-256. The Crypto block + * works most efficiently in DMA mode due to the large about of data I/O which would + * otherwise incur a lot of PIO-mode interrupt traffic to manually pump data. + * + * Crypto Driver Static Configuration + * + * A number of Crypto cipher modes are able to be configured statically, such that + * if particular mode(s) are not required, the resulting driver footprint can be reduced + * internally by blocking out chunks of code that are not needed. + * + * @note - The application must include drivers/crypto/adi_crypto.h to use this driver. + * @note - This driver optionally uses the DMA driver if DMA is selected and active. + * In this case, the application must include the DMA driver sources to resolve + * DMA symbols. + */ + + +/*======== I N C L U D E ========*/ + +/*! \cond PRIVATE */ +#include +#include +#include + +/* main crypto include file */ +#include + +/* private crypto defines */ +#include "adi_crypto_def.h" + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +/* dma interface */ +#include +#endif + + +/*======== D E F I N E S ========*/ + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Pm152 (rule 17.4): array indexing shall only be applied to objects defined as an array type +*/ +#pragma diag_suppress=Pm123,Pm140,Pm050,Pm088,Pm073,Pm143,Pm152 +#endif /* __ICCARM__ */ + +/* Utility Macros */ +#define CLR_BITS(REG,BITS) ((REG) &= ~(BITS)) +#define SET_BITS(REG,BITS) ((REG) |= (BITS)) +#define IS_ANY_BIT_SET(REG,BITS) (((REG) & (BITS)) != 0u) + + +/* Number of crypto device for the given processor */ +#define NUM_DEVICES (1u) + +/* Compiler-specific mapping of assebbly-level byte-swap instruction + IAR is "__REV", and we think Keil is "__rev", but lets see how that + goes when it is undefined for Keil. +*/ +#if defined ( __ICCARM__ ) +#define __ADI_BYTE_SWAP(X) __REV(X) +#elif defined (__GNUC__) +#define __ADI_BYTE_SWAP(X) __builtin_bswap32(X) +#elif defined (__CC_ARM) +#define __ADI_BYTE_SWAP(X) __rev(X) +#else +#error "This toolchain is not supported" +#endif + + +/*======== L O C A L F U N C D E C L ========*/ + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +static void dmaCallback (void *pCBParam, uint32_t Event, void *pArg); +#endif + +#ifdef ADI_DEBUG +/* Validatation routines */ +static ADI_CRYPTO_RESULT ValidateHandle (ADI_CRYPTO_HANDLE const hDevice); +static ADI_CRYPTO_RESULT ValidateUserBuffer (ADI_CRYPTO_TRANSACTION * const pBuffer); +#endif + +/* Generate a uint32_t value from a pointer to a uint8_t buffer */ +static uint32_t u32FromU8p (uint8_t * const pData); + +/* Initialize the internal device handle object (user memory) */ +static void InitializeDevData (ADI_CRYPTO_HANDLE const hDevice); + +/* Initiate the computation for a buffer */ +static void StartCompute (ADI_CRYPTO_HANDLE const hDevice); + +/* Stop the device */ +static void StopCompute (ADI_CRYPTO_HANDLE const hDevice); + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +static void programDMA (ADI_CRYPTO_HANDLE const hDevice); +#endif + +/* PIO mode write input data */ +static void writePioInputData (ADI_CRYPTO_HANDLE const hDevice, uint32_t const status); + +/* PIO mode read output data */ +static void readPioOutputData (ADI_CRYPTO_HANDLE const hDevice, uint32_t const status); + +/* Flush the input and output buffers */ +static void FlushInputOutputRegisters (ADI_CRYPTO_HANDLE const hDevice); + + +/* pre-defined Crypto interrupt handler prototypes, as linked in IVT */ +void Crypto_Int_Handler(void); +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +void DMA_AES0_IN_Int_Handler (void); +void DMA_AES0_OUT_Int_Handler (void); +#endif + + +/*======== D A T A ========*/ +/* Internal device structure */ + +static CRYPTO_INFO CryptoDevInfo[] = { + {pADI_CRYPT0, /* physical device controller pointer */ + NULL, /* hDevice */ +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + DMA0_CH13_DONE_IRQn, /* DMA input interrupt number */ + DMA0_CH14_DONE_IRQn, /* DMA output interrupt number */ + AES0_IN_CHANn, /* DMA input channel */ + AES0_OUT_CHANn, /* DMA output channel */ + ADI_CRYPTO_SUCCESS, /* DMA error state */ +#endif + } +}; + +/*! \endcond */ + +/*======== C O D E ========*/ + + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + +/* Internal Crypto registered DMA Callback for receiving DMA + fault notifications from the shared DMA error handler */ +static void dmaCallback(void *pCBParam, uint32_t Event, void *pArg) +{ + /* recover device handle */ + ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice; + + /* recover failing channel number */ + uint32_t failingChannel = (uint32_t)pCBParam; + + /* save the DMA error */ + switch (Event) { + case ADI_DMA_EVENT_ERR_BUS: + hDevice->dmaErrorCode = ADI_CRYPTO_ERR_DMA_BUS_FAULT; + break; + case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR: + hDevice->dmaErrorCode = ADI_CRYPTO_ERR_DMA_INVALID_DESCR; + break; + default: + hDevice->dmaErrorCode = ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR; + break; + } + + /* transfer is toast... post semaphore to unblock any waiters */ + SEM_POST(hDevice); + + /* call user's callback */ + if (0u != hDevice->pfCallback) { + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)hDevice->dmaErrorCode, (void*)failingChannel); + } + + /* game over... */ + StopCompute(hDevice); +} +#endif + + +#ifdef ADI_DEBUG +/* Validate the given handle */ +static ADI_CRYPTO_RESULT ValidateHandle(ADI_CRYPTO_HANDLE const hDevice) +{ + ADI_CRYPTO_RESULT result = ADI_CRYPTO_ERR_BAD_DEV_HANDLE; + uint32_t x; + + for (x = 0u; x < NUM_DEVICES; x++) { + if (CryptoDevInfo[x].hDevice == hDevice) { + result = ADI_CRYPTO_SUCCESS; + break; + } + } + + return result; +} +#endif + + +#ifdef ADI_DEBUG +static ADI_CRYPTO_RESULT ValidateUserBuffer(ADI_CRYPTO_TRANSACTION * const pBuffer) +{ + + /* null pointer and zero count checks */ + if ( + (pBuffer->pInputData == NULL) + || (pBuffer->numInputBytes == 0u) + || (pBuffer->pOutputData == NULL) + || (pBuffer->numOutputBytes == 0u) + || ( + (pBuffer->eAesByteSwap != ADI_CRYPTO_AES_LITTLE_ENDIAN) + && (pBuffer->eAesByteSwap != ADI_CRYPTO_AES_BIG_ENDIAN)) + ) + { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + + /* check buffer pointers for 32-bit alignment */ + if ( (0u != (3u & (uint32_t)pBuffer->pAuthData)) || (0u != (3u & (uint32_t)pBuffer->pInputData)) || (0u != (3u & (uint32_t)pBuffer->pOutputData)) ) { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + /* check buffer sizes for max DMA size */ + if ((MAX_CRYPTO_DMA_BYTES < pBuffer->numAuthBytes) || (MAX_CRYPTO_DMA_BYTES < pBuffer->numInputBytes) || (MAX_CRYPTO_DMA_BYTES < pBuffer->numOutputBytes)) { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } +#endif + +#if ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1 + if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_SHA) + { + /* SHA output digest is 256-bit and hence the output buffer size should be at least 32 bytes */ + if (pBuffer->numOutputBytes < SHA_OUTPUT_SIZE_IN_BYTES) { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + } + else +#endif + { + +#if ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1 + if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_CMAC) { + /* CMAC output is always a 128-bit block */ + if (pBuffer->numOutputBytes < CRYPTO_INPUT_SIZE_IN_BYTES) { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + } + else +#endif + { + if ( + (pBuffer->pKey == NULL) + || ( (pBuffer->eAesKeyLen != ADI_CRYPTO_AES_KEY_LEN_128_BIT) + && (pBuffer->eAesKeyLen != ADI_CRYPTO_AES_KEY_LEN_256_BIT)) + || ( (pBuffer->eCodingMode != ADI_CRYPTO_ENCODE) + && (pBuffer->eCodingMode != ADI_CRYPTO_DECODE))) + { + return ADI_CRYPTO_ERR_BAD_CONFIG; + } + +#if ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1 + if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_CTR) + { + if ((pBuffer->CounterInit & (0xFFF00000u)) != 0u) { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + } +#endif + +#if ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1 + if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_CCM) + { + if ( ((pBuffer->CounterInit & (0xFFFF0000u)) != 0u) + || ( (pBuffer->pAuthData != NULL) + && ( + (pBuffer->numAuthBytes == 0u) + || (pBuffer->numValidBytes == 0u) + || (pBuffer->numValidBytes > CRYPTO_INPUT_SIZE_IN_BYTES) + || (pBuffer->numOutputBytes < (pBuffer->numInputBytes + CRYPTO_INPUT_SIZE_IN_BYTES)) + ) + ) + ) + { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + } + else +#endif + { + if (pBuffer->numOutputBytes < pBuffer->numInputBytes) + { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + } + } + } + +/* FIXME: Issue http://labrea.ad.analog.com/browse/MSKEW-299 describes missing support + for HMAC mode, so reject HMAC submits until support for this mode is implimented. + ***REMOVE THIS BLOCK WHEN HMAC SUPPORT IS ADDED*** +*/ +#if ADI_CRYPTO_ENABLE_HMAC_SUPPORT == 1 + if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_HMAC) + { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } +#endif + + return ADI_CRYPTO_SUCCESS; +} +#endif + + +/** + * @brief Opens a Crypto device instance. + * + * @param [in] nDeviceNum Device number to open. + * @param [in] pMemory Pointer to a #ADI_CRYPTO_MEMORY_SIZE sized buffer to manage the device + * instance. + * @param [in] nMemorySize Size of the buffer to which "pMemory" points. + * @param [out] phDevice Pointer to a location where the Crypto device handle is to be written. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Call completed successfully. + * - #ADI_CRYPTO_ERR_BAD_DEVICE_NUM [D] Error: The device number is invalid. + * - #ADI_CRYPTO_ERR_INVALID_PARAM [D] Error: A parameter is invalid. + * - #ADI_CRYPTO_ERR_INSUFFICIENT_MEM [D] Error: The memory passed to the device is insufficient. + * - #ADI_CRYPTO_ERR_ALREADY_INITIALIZED [D] Error: The device is already opened. + * - #ADI_CRYPTO_ERR_SEMAPHORE_FAILED Error: Unable to create semaphore. + * - #ADI_CRYPTO_ERR_DMA_REGISTER Error: Unable to register DMA error callback function. + * + * @sa adi_crypto_Close(). + */ +ADI_CRYPTO_RESULT adi_crypto_Open (uint32_t const nDeviceNum, void * const pMemory, uint32_t const nMemorySize, ADI_CRYPTO_HANDLE * const phDevice) +{ + ADI_CRYPTO_HANDLE hDevice = NULL; + +#ifdef ADI_DEBUG + if (nDeviceNum >= NUM_DEVICES) { + return ADI_CRYPTO_ERR_BAD_DEVICE_NUM; + } + + if ((pMemory == NULL) || (phDevice == NULL)) { + return ADI_CRYPTO_ERR_INVALID_PARAM; + } + + if (nMemorySize < ADI_CRYPTO_MEMORY_SIZE) { + return ADI_CRYPTO_ERR_INSUFFICIENT_MEM; + } + + if (CryptoDevInfo[nDeviceNum].hDevice != NULL) { + return ADI_CRYPTO_ERR_ALREADY_INITIALIZED; + } + + /* reality checks */ + assert (ADI_CRYPTO_MEMORY_SIZE == sizeof(ADI_CRYPTO_DEV_DATA_TYPE)); + assert (sizeof(ADI_CRYPTO_TRANSACTION) == sizeof(CRYPTO_COMPUTE)); + +#endif /* ADI_DEBUG */ + + /* store a bad handle in case of failure */ + *phDevice = NULL; + + /* point local device handle to the user memory */ + hDevice = (ADI_CRYPTO_HANDLE)pMemory; + + /* link CRYPTO controller register set */ + hDevice->pDev = CryptoDevInfo[nDeviceNum].pDev; + + /* link device info */ + hDevice->pDevInfo = CryptoDevInfo; + + /* cross-link device handle into device info */ + CryptoDevInfo[nDeviceNum].hDevice = hDevice; + + /* Initialize the driver internals */ + InitializeDevData(hDevice); + + /* create the semaphore */ + SEM_CREATE(hDevice, "crypto_sem", ADI_CRYPTO_ERR_SEMAPHORE_FAILED); + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + /* initialize DMA core */ + adi_dma_Init(); + + /* register DMA error callback for INPUT channel */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pDevInfo->dmaInputChanNum, dmaCallback, (void*)hDevice)) { + /* uninitialize crypto driver and fail */ + adi_crypto_Close(hDevice); + return ADI_CRYPTO_ERR_DMA_REGISTER; + } + /* register DMA error callback for OUTPUT channel */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pDevInfo->dmaOutputChanNum, dmaCallback, (void*)hDevice)) { + /* uninitialize crypto driver and fail */ + adi_crypto_Close(hDevice); + return ADI_CRYPTO_ERR_DMA_REGISTER; + } +#endif + + /* Give the handle back to the application */ + *phDevice = hDevice; + + /* Return success */ + return ADI_CRYPTO_SUCCESS; +} + +/** + * @brief Close the given device instance. + * + * @param [in] hDevice Handle to the device instance. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully closed the device. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + * - #ADI_CRYPTO_ERR_SEMAPHORE_FAILED Error: Unable to delete semaphore. + * + * @sa adi_crypto_Open(). + */ +ADI_CRYPTO_RESULT adi_crypto_Close (ADI_CRYPTO_HANDLE const hDevice) +{ + uint32_t x; + ADI_CRYPTO_RESULT result; + +#ifdef ADI_DEBUG + if ((result = ValidateHandle(hDevice)) != ADI_CRYPTO_SUCCESS) { + return result; + } +#endif /* ADI_DEBUG */ + + /* IF (The device is enabled) */ + if (hDevice->bDeviceEnabled) { + result = adi_crypto_Enable(hDevice, false); + if (result != ADI_CRYPTO_SUCCESS) { + return result; + } + } + + /* Destroy the semaphore */ + SEM_DELETE(hDevice, ADI_CRYPTO_ERR_SEMAPHORE_FAILED); + + /* Close the device */ + for (x=0u; x < NUM_DEVICES; x++) { + if (CryptoDevInfo[x].hDevice == hDevice) { + CryptoDevInfo[x].hDevice = NULL; + break; + } + } + + return ADI_CRYPTO_SUCCESS; +} + + +/** + * @brief Register a user callback function. + * + * @param [in] hDevice Handle to the device instance. + * @param [in] pfCallback Function pointer to user callback function. Passing a NULL pointer will + * unregister the callback function. + * @param [in] pCBParam Callback function parameter. + * + * @details This function registers a user callback function. The registered function will be called when + * the given computation is over. Registering an active user callback function implies use of the + * (non-blocking) CALLBACK mode during which any subsequent calls to the (blocking-mode) + * #adi_crypto_GetBuffer() API will be rejected. + * + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully registerd the callback. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + */ + ADI_CRYPTO_RESULT adi_crypto_RegisterCallback (ADI_CRYPTO_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void * const pCBParam) +{ +#ifdef ADI_DEBUG + ADI_CRYPTO_RESULT result; + + if ((result = ValidateHandle(hDevice)) != ADI_CRYPTO_SUCCESS) { + return result; + } +#endif /* ADI_DEBUG */ + + /* store user's callback values (critical section) */ + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + hDevice->pfCallback = pfCallback; + hDevice->pCBParam = pCBParam; + ADI_EXIT_CRITICAL_REGION(); + + return ADI_CRYPTO_SUCCESS; +} + + +/** + * @brief Submit a Crypto transaction buffer for processing. + * + * @param [in] hDevice Handle to the device instance. + * @param [in] pBuffer Pointer to the #ADI_CRYPTO_TRANSACTION structure which contains details + * of the cipher-dependent buffer elements required by the driver. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully submitted the buffer. + * - #ADI_CRYPTO_ERR_COMPUTE_ACTIVE Error: Buffer already submitted. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + * - #ADI_CRYPTO_ERR_BAD_BUFFER [D] Error: The buffer passed to the device is invalid or unsupported. + * + * The buffer submitted is queued for eventual CRYPTO processing. A single buffer may be submitted + * prior to initiating CRYPTO buffer processing. Buffer processing is initiated with the + * #adi_crypto_Enable() call. As buffer processing is completed, the buffer (and result info) + * is retrieved with the #adi_crypto_GetBuffer() API or through the user callback notification. + * + * @note The driver takes ownership of the ADI_CRYPTO_TRANSACTION structure passed to the driver. + * The application must insure the structure is not used and its scope is valid untill + * the structure is returned back to the application. + * + * @warning The #ADI_CRYPTO_TRANSACTION buffer is a common superset of all possible cipher mode parameters. + * As such, not all parameters pertain to each cipher mode. It is recommended users clear unused + * parameters prior to configuration for the particular cipher mode. The example provided + * illustrates this with a call to: "memset(&Buffer, 0, sizeof(ADI_CRYPTO_TRANSACTION));" + * before configuring and then submitting each transaction. + * + * @sa adi_crypto_Enable(). + * @sa adi_crypto_GetBuffer(). + * @sa adi_crypto_IsBufferAvailable(). + */ + ADI_CRYPTO_RESULT adi_crypto_SubmitBuffer (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION * const pBuffer) +{ + ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS; + + /* reject if we already have a user buffer */ + if (NULL != hDevice->pUserBuffer) { + /* computation already active */ + return ADI_CRYPTO_ERR_COMPUTE_ACTIVE; + } + +#ifdef ADI_DEBUG + if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) { + return result; + } + + /* validate user Buffer */ + if (ADI_CRYPTO_SUCCESS != (result = ValidateUserBuffer(pBuffer))) { + return result; + } +#endif + + /* store user buffer pointer to return later */ + hDevice->pUserBuffer = pBuffer; + + /* initialize internal compute state from user buffer */ + memcpy(&hDevice->Computation, pBuffer, sizeof(ADI_CRYPTO_TRANSACTION)); + + /* don't initiate transaction until we get adi_crypto_Enable() */ + + /* reset dma error code */ + hDevice->dmaErrorCode = ADI_CRYPTO_SUCCESS; + + return result; +} + + +/** + * @brief Get the submitted transaction buffer back from the driver. + * + * @param [in] hDevice Handle to the device instance. + * @param [out] ppBuffer Pointer to a location to which the address of the buffer structure is written. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully got a buffer. + * - #ADI_CRYPTO_ERR_INVALID_PARAM [D] Error: Pointer to the buffer is NULL. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + * - #ADI_CRYPTO_ERR_DMA_BUS_FAULT Error: DMA bus fault was reported. + * - #ADI_CRYPTO_ERR_DMA_INVALID_DESCR Error: Invalid DMA descriptor was reported. + * - #ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR Error: An unexpected DMA error was reported. + * - #ADI_CRYPTO_ERR_SEMAPHORE_FAILED Error: Semaphore pend request failed. + * - #ADI_CRYPTO_ERR_INVALID_STATE Error: Invalid call when using callback mode. + * + * This is a blocking call and will await transaction completion (if not already). + * This function should not be called if a callback function is registered. + * + * @sa adi_crypto_SubmitBuffer(). + * @sa adi_crypto_IsBufferAvailable(). + */ +ADI_CRYPTO_RESULT adi_crypto_GetBuffer (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION ** const ppBuffer) +{ + ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS; + +#ifdef ADI_DEBUG + + if (ppBuffer == NULL) { + return ADI_CRYPTO_ERR_INVALID_PARAM; + } + if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) { + return result; + } +#endif /* ADI_DEBUG */ + + if (NULL != hDevice->pfCallback) { + return ADI_CRYPTO_ERR_INVALID_STATE; + } + + /* pend on completion (even if already complete) */ + SEM_PEND(hDevice, ADI_CRYPTO_ERR_SEMAPHORE_FAILED); + + /* give back the user's buffer */ + *ppBuffer = hDevice->pUserBuffer; + + /* clear internal user buffer pointer */ + hDevice->pUserBuffer = NULL; + + /* if we had a DMA error, return that instead of success */ + if (ADI_CRYPTO_SUCCESS != hDevice->dmaErrorCode) { + result = hDevice->dmaErrorCode; + } + + return result; +} + + +/** + * @brief Peek function to know whether a submitted transaction is complete. + * + * @param [in] hDevice Handle to the device instance. + * @param [in] pbAvailable Pointer to a Boolean variable. Set to "true" if there is a completed + * buffer and a call to adi_crypto_GetBuffer is ensured to be successful. + * Set to "false" if there is no completed buffer. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully peeked for a buffer. + * - #ADI_CRYPTO_ERR_INVALID_PARAM [D] Error: The pointer passed is NULL. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + * - #ADI_CRYPTO_ERR_DMA_BUS_FAULT Error: DMA bus fault was reported. + * - #ADI_CRYPTO_ERR_DMA_INVALID_DESCR Error: Invalid DMA descriptor was reported. + * - #ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR Error: An unexpected DMA error was reported. + * + * @sa adi_crypto_SubmitBuffer(). + * @sa adi_crypto_GetBuffer(). + */ +ADI_CRYPTO_RESULT adi_crypto_IsBufferAvailable (ADI_CRYPTO_HANDLE const hDevice, bool * const pbAvailable) +{ + ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS; + +#ifdef ADI_DEBUG + if (pbAvailable == NULL) + { + return ADI_CRYPTO_ERR_INVALID_PARAM; + } + if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) { + return result; + } +#endif /* ADI_DEBUG */ + + /* let the respective PIO/DMA interrupts drive completion... just return that state here */ + *pbAvailable = hDevice->bCompletion; + + /* if we had a DMA error, return that instead of success */ + if (ADI_CRYPTO_SUCCESS != hDevice->dmaErrorCode) { + result = hDevice->dmaErrorCode; + } + + return result; +} + + +/** + * @brief Enable/Disable the device. Enabling the device causes the submitted buffer to be processed. + * + * @param [in] hDevice Handle to the device instance. + * @param [in] bEnable 'true' to enable and 'false' to disable the device. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully enabled/disabled the device. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + * - #ADI_CRYPTO_ERR_INVALID_STATE [D] Error: Calling enable when device is already enabled or + * disable when the device is already disabled. + * + */ +ADI_CRYPTO_RESULT adi_crypto_Enable (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable) +{ + ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS; + +#ifdef ADI_DEBUG + + if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) { + return result; + } + if (bEnable == hDevice->bDeviceEnabled) { + return ADI_CRYPTO_ERR_INVALID_STATE; + } +#endif /* ADI_DEBUG */ + + if (true == bEnable) { + + /* device enable */ + + /* Enable the IRQs */ + NVIC_EnableIRQ(CRYPT_EVT_IRQn); + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + /* Enable the DMA interrupts */ + NVIC_EnableIRQ(hDevice->pDevInfo->dmaInputIrqNum); + NVIC_EnableIRQ(hDevice->pDevInfo->dmaOutputIrqNum); +#endif + + /* Mark the device as enabled */ + hDevice->bDeviceEnabled = true; + + /* Start processing buffer */ + StartCompute(hDevice); + + } else { + + /* device disable */ + + /* Disable the IRQs */ + NVIC_DisableIRQ(CRYPT_EVT_IRQn); + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + /* Enable the DMA interrupts */ + NVIC_DisableIRQ(hDevice->pDevInfo->dmaInputIrqNum); + NVIC_DisableIRQ(hDevice->pDevInfo->dmaOutputIrqNum); +#endif + + /* Stop the device */ + StopCompute(hDevice); + + /* if we had a DMA error, return that instead of success */ + if (ADI_CRYPTO_SUCCESS != hDevice->dmaErrorCode) { + result = hDevice->dmaErrorCode; + } + } + + /* Return success */ + return result; +} + + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +/** + * @brief Dynamically Enable/Disable DMA mode for the device. + * + * @param [in] hDevice Handle to the device instance. + * @param [in] bEnable 'true' will enable DMA and 'false' disables the DMA. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully enabled/disabled the DMA. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + * - #ADI_CRYPTO_ERR_INVALID_STATE [D] Error: DMA cannot be enabled or disabled when the device is already enabled. + * + * Manage use of DMA mode dynamically. Presupposes DMA support has been enabled statically + * in the static configuration files via the ADI_CRYPTO_ENABLE_DMA_SUPPORT macro. + * + * @note In addition to requiring that DMA support is enabled (see ADI_CRYPTO_ENABLE_DMA_SUPPORT static + * configuration macro) for #adi_crypto_EnableDmaMode() to be available, use of DMA mode may + * also be statically configured (see ADI_CRYPTO_ENABLE_DMA). Both these macros may be set statically + * to both enable DMA support and to activate the DMA mode in a fully static manner, without need of + * calling adi_crypto_EnableDmaMode() at all (in which case, this function may be eliminated by the linker). + */ +ADI_CRYPTO_RESULT adi_crypto_EnableDmaMode (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable) +{ +#ifdef ADI_DEBUG + ADI_CRYPTO_RESULT result; + + if ((result = ValidateHandle(hDevice)) != ADI_CRYPTO_SUCCESS) { + return result; + } + if (hDevice->bDeviceEnabled) { + return ADI_CRYPTO_ERR_INVALID_STATE; + } +#endif /* ADI_DEBUG */ + + if (bEnable) + { + /* Enable DMA and map data pump handler */ + hDevice->bDmaEnabled = true; + + /* Enable the DMA interrupts */ + NVIC_EnableIRQ(hDevice->pDevInfo->dmaInputIrqNum); + NVIC_EnableIRQ(hDevice->pDevInfo->dmaOutputIrqNum); + } + else + { + /* Disable DMA and map data pump handler */ + hDevice->bDmaEnabled = false; + + /* Disable the DMA interrupts */ + NVIC_DisableIRQ(hDevice->pDevInfo->dmaInputIrqNum); + NVIC_DisableIRQ(hDevice->pDevInfo->dmaOutputIrqNum); + } + + /* Return success */ + return ADI_CRYPTO_SUCCESS; +} +#endif + + + +/*! \cond PRIVATE */ + +/*======== L O C A L F U N C T I O N D E F I N I T I O N S ========*/ + +/* Generate a u32 from a pointer to u8 buffer */ +static uint32_t u32FromU8p(uint8_t * const pData) +{ + int32_t x = 0; + uint32_t nValue = pData[3]; + + for (x = 2; x >= 0; x--) { + nValue = (nValue << 8u) | pData[x]; + } + return nValue; +} + + +/* Initialize the device structure */ +static void InitializeDevData (ADI_CRYPTO_HANDLE const hDevice) +{ + /* Clear the device structure */ + memset(hDevice, 0, sizeof(ADI_CRYPTO_HANDLE)); + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + #if (ADI_CRYPTO_ENABLE_DMA == 1) + hDevice->bDmaEnabled = true; + NVIC_EnableIRQ(hDevice->pDevInfo->dmaInputIrqNum); + NVIC_EnableIRQ(hDevice->pDevInfo->dmaOutputIrqNum); + #else + hDevice->bDmaEnabled = false; + NVIC_DisableIRQ(hDevice->pDevInfo->dmaInputIrqNum); + NVIC_DisableIRQ(hDevice->pDevInfo->dmaOutputIrqNum); + #endif +#else + /* no DMA support */ + hDevice->bDmaEnabled = false; +#endif +} + + +/* initiate buffer processing (called from crypto enable) */ +static void StartCompute(ADI_CRYPTO_HANDLE const hDevice) +{ + /* clear completion flag */ + hDevice->bCompletion = false; + + /* Get pointer to the compute buffer */ + CRYPTO_COMPUTE* pCompute = &hDevice->Computation; + + /* Clear any pending interrupts (all are R/W1C) */ + hDevice->pDev->STAT = hDevice->pDev->STAT; + + /* reset crypto config register */ + hDevice->pDev->CFG = 0u; + +#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) + /* reset SHA hardware machine state */ + if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) { + SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_SHAINIT); + } +#endif + + /* program main config register settings */ + SET_BITS(hDevice->pDev->CFG, + ( (uint32_t)pCompute->eCipherMode /* cipher mode */ + | (uint32_t)pCompute->eKeyByteSwap /* KEY endianness */ + | (uint32_t)pCompute->eShaByteSwap /* SHA endianness */ + | (uint32_t)pCompute->eAesByteSwap /* AES endianness */ + | (uint32_t)pCompute->eAesKeyLen /* AES key length */ + | (uint32_t)pCompute->eCodingMode /* encode mode */ + ) + ); + +#if (CRYPTO_SUPPORT_KEY_REQUIRED) + if (NULL != pCompute->pKey) { + + /* program user key */ + uint32_t volatile *pKeyReg = &hDevice->pDev->AESKEY0; + uint8_t *pUserKey = pCompute->pKey; + uint32_t numKeyWords; + + /* set key length register */ + SET_BITS(hDevice->pDev->CFG, (uint32_t)pCompute->eAesKeyLen); + + /* Set the number of keywords to write to the 32-bit keyword registers */ + switch (pCompute->eAesKeyLen) { + case ADI_CRYPTO_AES_KEY_LEN_128_BIT: + numKeyWords = 4u; + break; + case ADI_CRYPTO_AES_KEY_LEN_256_BIT: + numKeyWords = 8u; + break; + default: + numKeyWords = 0u; /* hardware only supports only 128-bit and 256-bit key length (no 192-bit) */ + break; + } + + /* load the key (key registers have write-no-read attribute) */ + for (uint32_t count = 0u; count < numKeyWords; count++) { + *pKeyReg = u32FromU8p(pUserKey); + pKeyReg++; + pUserKey += sizeof(uint32_t); + } + } +#endif /* (CRYPTO_SUPPORT_KEY_REQUIRED) */ + +#if (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) + if (ADI_CRYPTO_MODE_CMAC == pCompute->eCipherMode) { + /* program CMAC-specific registers */ + /* DATALEN in CMAC mode is number of 128 bit pages (or 16, 8 byte pages) */ + hDevice->pDev->DATALEN = pCompute->numInputBytesRemaining / CRYPTO_INPUT_SIZE_IN_BYTES; + } +#endif /* (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) */ + +#if (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) + if (ADI_CRYPTO_MODE_CCM == pCompute->eCipherMode) { + /* program CMM-specific registers */ + hDevice->pDev->PREFIXLEN = pCompute->numAuthBytesRemaining / CRYPTO_INPUT_SIZE_IN_BYTES; + hDevice->pDev->DATALEN = pCompute->numInputBytesRemaining / CRYPTO_INPUT_SIZE_IN_BYTES; + hDevice->pDev->CCM_NUM_VALID_BYTES = pCompute->numValidBytes; + } +#endif /* (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) */ + +#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) + + if ( (ADI_CRYPTO_MODE_CBC == pCompute->eCipherMode) || (ADI_CRYPTO_MODE_CCM == pCompute->eCipherMode) || (ADI_CRYPTO_MODE_CTR == pCompute->eCipherMode) ) + { + /* program NONCE/IV for CBC, CCM and CTR modes */ + assert (NULL != pCompute->pNonceIV); + + /* Configure Counter Init and NONCE values */ + hDevice->pDev->CNTRINIT = pCompute->CounterInit; + + hDevice->pDev->NONCE0 = u32FromU8p(&pCompute->pNonceIV[0]); + hDevice->pDev->NONCE1 = u32FromU8p(&pCompute->pNonceIV[4]); + hDevice->pDev->NONCE2 = u32FromU8p(&pCompute->pNonceIV[8]); + + hDevice->pDev->NONCE3 = ((uint32_t)pCompute->pNonceIV[12] << 0u) | ((uint32_t)pCompute->pNonceIV[13] << 8u); + +#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) + if (ADI_CRYPTO_MODE_CBC == pCompute->eCipherMode) { + + /* additionally, CBC mode requires remaining IV data */ + hDevice->pDev->NONCE3 |= ( ((uint32_t)pCompute->pNonceIV[14] << 16u) | ((uint32_t)pCompute->pNonceIV[15] << 24u) ); + } +#endif /* (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) */ + } +#endif /* (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) */ + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + + /* onle enable DMA for non-SHA mode or SHA mode with > 4 bytes of input... */ + if ( ((true == hDevice->bDmaEnabled) && (ADI_CRYPTO_MODE_SHA != pCompute->eCipherMode)) + || ((true == hDevice->bDmaEnabled) && (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) && (4u < pCompute->numInputBytesRemaining)) ) + { + + /* DMA startup... */ + programDMA(hDevice); + + /* mode-specific DMA interrupt enables */ + switch (pCompute->eCipherMode) { + case ADI_CRYPTO_MODE_HMAC: + /* enable HMAC done and overrun interrupts (via PIO handler) */ + SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_HMACDONEEN | BITM_CRYPT_INTEN_INOVREN)); + break; + case ADI_CRYPTO_MODE_SHA: + /* enable SHA done and overrun interrupts */ + SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_SHADONEN | BITM_CRYPT_INTEN_INOVREN)); + SET_BITS(hDevice->pDev->CFG, (BITM_CRYPT_CFG_INDMAEN)); + break; + default: + /* enable DMA I/O interrupts */ + SET_BITS(hDevice->pDev->CFG, (BITM_CRYPT_CFG_OUTDMAEN | BITM_CRYPT_CFG_INDMAEN)); + break; + } + + /* crypto hardware enable */ + SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_BLKEN); + + } else +#endif + { + /* mode-specific PIO interrupt enables */ + switch (pCompute->eCipherMode) { + case ADI_CRYPTO_MODE_HMAC: + /* HMAC done interrupts via PIO handler (do NOT use INRDY in HMAC mode) */ + SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_HMACDONEEN | BITM_CRYPT_INTEN_OUTRDYEN | BITM_CRYPT_INTEN_INOVREN)); + break; + case ADI_CRYPTO_MODE_SHA: + /* SHA done interrupts via PIO handler (do NOT use INRDY in SHA mode) */ + SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_SHADONEN | BITM_CRYPT_INTEN_INOVREN)); + break; + default: + SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_INOVREN | BITM_CRYPT_INTEN_OUTRDYEN | BITM_CRYPT_INTEN_INRDYEN)); + break; + } + + /* crypto hardware enable */ + SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_BLKEN); + + /* manual write of 1st input data batch... (interrupt-driven hereafter...) */ + writePioInputData(hDevice, hDevice->pDev->STAT); + } +} + + +/* halt computation */ +static void StopCompute (ADI_CRYPTO_HANDLE const hDevice) +{ + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + /* disable Crypto DMA */ + CLR_BITS(hDevice->pDev->CFG, (BITM_CRYPT_CFG_INDMAEN | BITM_CRYPT_CFG_OUTDMAEN)); +#endif + + /* clear all interrupt enables */ + hDevice->pDev->INTEN = 0u; + + /* Flush the buffers */ + FlushInputOutputRegisters(hDevice); + + /* device disable */ + CLR_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_BLKEN); + + /* Mark the device as disabled */ + hDevice->bDeviceEnabled = false; +} + + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +static void programDMA(ADI_CRYPTO_HANDLE const hDevice) +{ + CRYPTO_COMPUTE* pCompute = &hDevice->Computation; + ADI_DCC_TypeDef* pCCD; /* pointer to DMA Control Data Descriptor */ + uint32_t channelBit; + uint32_t num32BitWords; + + /* start with INPUT channel */ + channelBit = 1u << hDevice->pDevInfo->dmaInputChanNum; + + /* disable various stuff */ + pADI_DMA0->SRCADDR_CLR = channelBit; /* disable src endpointer decrement mode */ + pADI_DMA0->DSTADDR_CLR = channelBit; /* disable dst endpointer decrement mode */ + pADI_DMA0->EN_SET = channelBit; /* channel enable */ + pADI_DMA0->RMSK_CLR = channelBit; /* allow Crypto to request DMA service */ + +#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) + /* program input descriptor(s) */ + if (0u != pCompute->pNextAuthInput) { + + /* schedule authentication data into primary descriptor (USING ping-pong mode) */ + + pADI_DMA0->ALT_CLR = channelBit; /* activate PRIMARY descriptor */ + pCCD = pPrimaryCCD + hDevice->pDevInfo->dmaInputChanNum; /* point to primary INPUT descriptor */ + + /* setup the endpoints (point to input register & last 4 bytes of input array) */ + pCCD->DMASRCEND = (uint32_t)pCompute->pNextAuthInput + sizeof(uint32_t) * (pCompute->numAuthBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u); + pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->INBUF; + + /* program DMA Control Data Config register */ + num32BitWords = pCompute->numAuthBytesRemaining / sizeof(uint32_t); + pCCD->DMACDC = + ( ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) + | ((uint32_t)ADI_DMA_INCR_4_BYTE << DMA_BITP_CTL_SRC_INC) + | ((uint32_t)ADI_DMA_WIDTH_4_BYTE << DMA_BITP_CTL_SRC_SIZE) + | ((uint32_t)ADI_DMA_RPOWER_4 << DMA_BITP_CTL_R_POWER) + | (uint32_t)((num32BitWords - 1u) << DMA_BITP_CTL_N_MINUS_1) + | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_PING_PONG << DMA_BITP_CTL_CYCLE_CTL) ); + + + /* schedule input data into alternate descriptor (in basic mode) */ + pADI_DMA0->PRI_CLR = channelBit; /* activate ALTERNATE descriptor */ + pCCD = pAlternateCCD + hDevice->pDevInfo->dmaInputChanNum; /* point to alternate INPUT descriptor */ + + /* setup the endpoints (point to input register & last 4 bytes of input array) */ + pCCD->DMASRCEND = (uint32_t)pCompute->pNextInput + sizeof(uint32_t) * (pCompute->numInputBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u); + pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->INBUF; + + /* program DMA Control Data Config register */ + num32BitWords = pCompute->numInputBytesRemaining / sizeof(uint32_t); + pCCD->DMACDC = + ( ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) + | ((uint32_t)ADI_DMA_INCR_4_BYTE << DMA_BITP_CTL_SRC_INC) + | ((uint32_t)ADI_DMA_WIDTH_4_BYTE << DMA_BITP_CTL_SRC_SIZE) + | ((uint32_t)ADI_DMA_RPOWER_4 << DMA_BITP_CTL_R_POWER) + | (uint32_t)((num32BitWords - 1u) << DMA_BITP_CTL_N_MINUS_1) + | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) ); + + } else +#endif /* #if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) */ + { + + /* no authentication data, just schedule input data into primary descriptor (in basic mode) */ + + pADI_DMA0->ALT_CLR = channelBit; /* activate PRIMARY descriptor */ + pCCD = pPrimaryCCD + hDevice->pDevInfo->dmaInputChanNum; /* point to primary INPUT descriptor */ + + /* setup the endpoints (point to input register & last 4 bytes of input array) */ +#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) + if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) { + + /* Stop SHA-mode input writes one short of last 32-bit word so the DMA input interrupt + can manually call PIO write function to handle SHA end flag and last write manually. */ + pCCD->DMASRCEND = (uint32_t)pCompute->pNextInput + sizeof(uint32_t) * (pCompute->numInputBytesRemaining / FIFO_WIDTH_IN_BYTES - 2u); + num32BitWords = (pCompute->numInputBytesRemaining - (pCompute->numInputBytesRemaining % sizeof(uint32_t))) / sizeof(uint32_t) - 1u; /* count - 1 */ + } + else +#endif + { + /* stop at last write end */ + pCCD->DMASRCEND = (uint32_t)pCompute->pNextInput + sizeof(uint32_t) * ( pCompute->numInputBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u); + num32BitWords = pCompute->numInputBytesRemaining / sizeof(uint32_t); /* count */ + } + + pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->INBUF; + + /* program DMA Control Data Config register */ + pCCD->DMACDC = + ( ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) + | ((uint32_t)ADI_DMA_INCR_4_BYTE << DMA_BITP_CTL_SRC_INC) + | ((uint32_t)ADI_DMA_WIDTH_4_BYTE << DMA_BITP_CTL_SRC_SIZE) + | ((uint32_t)ADI_DMA_RPOWER_4 << DMA_BITP_CTL_R_POWER) + | (uint32_t)((num32BitWords - 1u) << DMA_BITP_CTL_N_MINUS_1) + | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) ); + } + +/* don't program output DMA in SHA mode... */ +#if CRYPTO_SUPPORT_MODE_ANY_NON_SHA + + if (ADI_CRYPTO_MODE_SHA != pCompute->eCipherMode) { + + /* switch to OUTPUT channel */ + channelBit = 1u << hDevice->pDevInfo->dmaOutputChanNum; + + /* disable various stuff */ + pADI_DMA0->SRCADDR_CLR = channelBit; /* disable src endpointer decrement mode */ + pADI_DMA0->DSTADDR_CLR = channelBit; /* disable dst endpointer decrement mode */ + pADI_DMA0->EN_SET = channelBit; /* channel enable */ + pADI_DMA0->RMSK_CLR = channelBit; /* allow Crypto to request DMA service */ + + pADI_DMA0->ALT_CLR = channelBit; /* activate primary descriptor */ + pCCD = pPrimaryCCD + hDevice->pDevInfo->dmaOutputChanNum; /* point to crypto OUTPUT descriptor */ + + + /* setup the endpoints (point to output register & last 4 bytes of output array) */ + pCCD->DMASRCEND = (uint32_t)&hDevice->pDev->OUTBUF; + pCCD->DMADSTEND = (uint32_t)pCompute->pNextOutput + sizeof(uint32_t) * (pCompute->numOutputBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u); + + /* program DMA Control Data Config register */ + num32BitWords = pCompute->numOutputBytesRemaining / sizeof(uint32_t); + pCCD->DMACDC = + ( ((uint32_t)ADI_DMA_INCR_4_BYTE << DMA_BITP_CTL_DST_INC) + | ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) + | ((uint32_t)ADI_DMA_WIDTH_4_BYTE << DMA_BITP_CTL_SRC_SIZE) + | ((uint32_t)ADI_DMA_RPOWER_4 << DMA_BITP_CTL_R_POWER) + | (uint32_t)((num32BitWords - 1u) << DMA_BITP_CTL_N_MINUS_1) + | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) ); + + } /* end non-SHA mode */ + +#endif /* CRYPTO_SUPPORT_MODE_ANY_NON_SHA */ +} +#endif /* #if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) */ + + +static void writePioInputData(ADI_CRYPTO_HANDLE const hDevice, uint32_t const status) +{ + CRYPTO_COMPUTE* pCompute = &hDevice->Computation; + uint32_t numWritable = FIFO_DEPTH - ((status & BITM_CRYPT_STAT_INWORDS) >> BITP_CRYPT_STAT_INWORDS); + +#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) + /* always send authentication data before input payload is sent */ + if (0u != pCompute->numAuthBytesRemaining) { + + /* fill input FIFO with 32-bit authentication data */ + while ((0u != numWritable) && (0u != pCompute->numAuthBytesRemaining)) { + hDevice->pDev->INBUF = *pCompute->pNextAuthInput; + pCompute->pNextAuthInput++; + pCompute->numAuthBytesRemaining -= FIFO_WIDTH_IN_BYTES; + numWritable--; + } + } else +#endif /* #if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) */ + { + /* no authentication data, process payload input data */ + +#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) + if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) { + + /* Drive up to a full "chunk" of SHA input message data. + Chunk size is limited to 512-bits (64-bytes) by AES + hardware compute block. + */ + + if (pCompute->numInputBytesRemaining >= SHA_CHUNK_MAX_BYTES) + { + /* This is the simple case, load up an entire chunk and let it go */ + for (uint8_t i = 0u; i < SHA_CHUNK_MAX_WORDS; i++) { + hDevice->pDev->INBUF = *pCompute->pNextInput; + pCompute->pNextInput++; + } + + pCompute->numShaBitsRemaining -= SHA_CHUNK_MAX_BITS; + pCompute->numInputBytesRemaining -= SHA_CHUNK_MAX_BYTES; + } + else + { + /* The final case, we load up any bytes less than a full chunk and trigger the last word */ + while (FIFO_WIDTH_IN_BITS <= pCompute->numShaBitsRemaining) { + hDevice->pDev->INBUF = *pCompute->pNextInput; + pCompute->pNextInput++; + pCompute->numShaBitsRemaining -= FIFO_WIDTH_IN_BITS; + } + + hDevice->pDev->SHA_LAST_WORD = (pCompute->numShaBitsRemaining << BITP_CRYPT_SHA_LAST_WORD_O_BITS_VALID) | BITM_CRYPT_SHA_LAST_WORD_O_LAST_WORD; + + /* Last write is dummy or not, depending on remaining bit count */ + if (0u == pCompute->numShaBitsRemaining) { + /* dummy write */ + hDevice->pDev->INBUF = 0u; + } else { + /* partial data (last remaining message data word) */ + hDevice->pDev->INBUF = *pCompute->pNextInput; + pCompute->pNextInput++; + } + + pCompute->numShaBitsRemaining = 0u; + pCompute->numInputBytesRemaining = 0u; + + /* Use output bytes as a way of confirming that we are really done (can't use input bytes/bits) */ + pCompute->numOutputBytesRemaining -= SHA_OUTPUT_SIZE_IN_BYTES; + } + } /* end of SHA mode */ + else +#endif + { + /* full input FIFO with normal payload write (non-SHA) */ + while ((0u != numWritable) && (0u != pCompute->numInputBytesRemaining)) { + hDevice->pDev->INBUF = *pCompute->pNextInput; + pCompute->pNextInput++; + pCompute->numInputBytesRemaining -= FIFO_WIDTH_IN_BYTES; + numWritable--; + } + } + } +} + + +static void readPioOutputData(ADI_CRYPTO_HANDLE const hDevice, uint32_t const status) +{ + CRYPTO_COMPUTE *pCompute = &hDevice->Computation; + uint32_t numReadable; + +#if ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1 + /* Copy the SHA output if enabled */ + if (pCompute->eCipherMode == ADI_CRYPTO_MODE_SHA) + { + if (IS_ANY_BIT_SET(status, BITM_CRYPT_STAT_SHADONE)) { + + /* Get 1 SHADONE per block + 1 SHADONE when we trigger the last word */ + if (0u == pCompute->numOutputBytesRemaining) { +#if ADI_CRYPTO_SHA_OUTPUT_FORMAT == 0 /* Little Endian */ + pCompute->pNextOutput[0] = hDevice->pDev->SHAH7; + pCompute->pNextOutput[1] = hDevice->pDev->SHAH6; + pCompute->pNextOutput[2] = hDevice->pDev->SHAH5; + pCompute->pNextOutput[3] = hDevice->pDev->SHAH4; + pCompute->pNextOutput[4] = hDevice->pDev->SHAH3; + pCompute->pNextOutput[5] = hDevice->pDev->SHAH2; + pCompute->pNextOutput[6] = hDevice->pDev->SHAH1; + pCompute->pNextOutput[7] = hDevice->pDev->SHAH0; +#else + pCompute->pNextOutput[0] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH0); + pCompute->pNextOutput[1] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH1); + pCompute->pNextOutput[2] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH2); + pCompute->pNextOutput[3] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH3); + pCompute->pNextOutput[4] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH4); + pCompute->pNextOutput[5] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH5); + pCompute->pNextOutput[6] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH6); + pCompute->pNextOutput[7] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH7); +#endif + } + } + } + else +#endif + { + /* read any ready non-SHA output from output FIFO */ + if (IS_ANY_BIT_SET(status, BITM_CRYPT_STAT_OUTRDY)) { + numReadable = ((status & BITM_CRYPT_STAT_OUTWORDS) >> BITP_CRYPT_STAT_OUTWORDS); + while ((0u != numReadable) && (0u != pCompute->numOutputBytesRemaining)) { + *pCompute->pNextOutput = hDevice->pDev->OUTBUF; + pCompute->pNextOutput++; + pCompute->numOutputBytesRemaining -= FIFO_WIDTH_IN_BYTES; + numReadable--; + } + } + } + + /* if output count has gone to zero, set completion flag */ + if (0u == pCompute->numOutputBytesRemaining) { + hDevice->bCompletion = true; + } +} + + +/* Flush the Crypto input and output buffers */ +static void FlushInputOutputRegisters(ADI_CRYPTO_HANDLE const hDevice) +{ + /* Set and clear the flush bits to flush the input and output buffers */ + SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_INFLUSH | BITM_CRYPT_CFG_OUTFLUSH); + CLR_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_INFLUSH | BITM_CRYPT_CFG_OUTFLUSH); +} + + +/*================ INTERRUPT HANDELING ==================*/ + +/* native PIO-mode (non-DMA) interrupt handler */ +void Crypto_Int_Handler(void) +{ + ISR_PROLOG(); + + ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice; + CRYPTO_COMPUTE *pCompute = &hDevice->Computation; + uint32_t status = hDevice->pDev->STAT; + uint32_t event; + + /* clear status */ + hDevice->pDev->STAT = status; + + /* check for overflow */ + if (IS_ANY_BIT_SET(status, BITM_CRYPT_STAT_INOVR)) { + + /* call user's callback */ + if (0u != hDevice->pfCallback) { + hDevice->pfCallback(hDevice->pCBParam, ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW, (void *)status); + } + + /* stop */ + StopCompute(hDevice); + + /* post the semaphore */ + SEM_POST(hDevice); + + return; + } + + /* pull outputs (updates completion flag) */ + readPioOutputData(hDevice, status); + + if (false == hDevice->bCompletion) { + + /* push more inputs, but not in SHA DMA mode (except for when its perfectly aligned block) */ + if ((pCompute->eCipherMode != ADI_CRYPTO_MODE_SHA) || (hDevice->bDmaEnabled == false) || (pCompute->numInputBytesRemaining == 0u)) + { + writePioInputData(hDevice, status); + } + + } else { + + /* we're done */ + + /* dispatch to user callback if we have one */ + if (0u != hDevice->pfCallback) { + + /* check for overflow first */ + if (0u != (BITM_CRYPT_STAT_INOVR & status)) { + event = ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW; + } else { + /* completion message depends on mode */ + switch (hDevice->Computation.eCipherMode) { +#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) + case ADI_CRYPTO_MODE_CBC: event = ADI_CRYPTO_EVENT_STATUS_CBC_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) + case ADI_CRYPTO_MODE_CCM: event = ADI_CRYPTO_EVENT_STATUS_CCM_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) + case ADI_CRYPTO_MODE_CMAC: event = ADI_CRYPTO_EVENT_STATUS_CMAC_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) + case ADI_CRYPTO_MODE_CTR: event = ADI_CRYPTO_EVENT_STATUS_CTR_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1) + case ADI_CRYPTO_MODE_ECB: event = ADI_CRYPTO_EVENT_STATUS_ECB_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_HMAC_SUPPORT == 1) + case ADI_CRYPTO_MODE_HMAC: event = ADI_CRYPTO_EVENT_STATUS_HMAC_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) + case ADI_CRYPTO_MODE_SHA: event = ADI_CRYPTO_EVENT_STATUS_SHA_DONE; break; +#endif + default: event = ADI_CRYPTO_EVENT_STATUS_UNKNOWN; break; + } + } + + /* call user's callback and give back buffer pointer */ + hDevice->pfCallback(hDevice->pCBParam, event, (void*)hDevice->pUserBuffer); + + /* clear private copy of user buffer pointer */ + /* (this is done in GetBuffer in non-Callback mode) */ + hDevice->pUserBuffer = NULL; + } + + /* disable interrupts */ + hDevice->pDev->INTEN = 0u; + + /* post the semaphore */ + SEM_POST(hDevice); + } + + ISR_EPILOG(); +} + + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +/* native DMA input interrupt handler */ +void DMA_AES0_IN_Int_Handler (void) +{ + ISR_PROLOG(); + + ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice; + CRYPTO_COMPUTE *pCompute = &hDevice->Computation; + +#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) + if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) { + + /* Update the compute structure to reflect the "post DMA" state of the transaction */ + uint32_t numTotalBytes = pCompute->numInputBytesRemaining; + uint32_t num32BitWords = (numTotalBytes - (numTotalBytes % sizeof(uint32_t))) / sizeof(uint32_t) - 1u; + pCompute->numInputBytesRemaining -= num32BitWords*4u; + pCompute->numShaBitsRemaining -= num32BitWords*32u; + pCompute->pNextInput += num32BitWords; + + if ((numTotalBytes % SHA_CHUNK_MAX_BYTES) == 0u) + { + /* For perfect block sizes, need to write the last word WITHOUT triggering SHA_LAST_WORD */ + hDevice->pDev->INBUF = *pCompute->pNextInput; + + pCompute->numInputBytesRemaining = 0u; + pCompute->numShaBitsRemaining = 0u; + } + else + { + /* Go ahead and write the remaining word, and its okay to trigger SHA_LAST_WORD */ + writePioInputData(hDevice, hDevice->pDev->STAT); + } + } +#endif + + /* defer post to output interrupt... */ + + ISR_EPILOG(); +} +#endif + + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +/* native DMA output interrupt handler */ +void DMA_AES0_OUT_Int_Handler (void) +{ + ISR_PROLOG(); + ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice; + uint32_t status = hDevice->pDev->STAT; + uint32_t event; + + /* by the time we get here, everything should be complete */ + + /* dispatch to user callback if we have one */ + if (0u != hDevice->pfCallback) { + + /* check for overflow first */ + if (0u != (BITM_CRYPT_STAT_INOVR & status)) { + event = ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW; + } else { + /* completion message depends on mode */ + switch (hDevice->Computation.eCipherMode) { +#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) + case ADI_CRYPTO_MODE_CBC: event = ADI_CRYPTO_EVENT_STATUS_CBC_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) + case ADI_CRYPTO_MODE_CCM: event = ADI_CRYPTO_EVENT_STATUS_CCM_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) + case ADI_CRYPTO_MODE_CMAC: event = ADI_CRYPTO_EVENT_STATUS_CMAC_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) + case ADI_CRYPTO_MODE_CTR: event = ADI_CRYPTO_EVENT_STATUS_CTR_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1) + case ADI_CRYPTO_MODE_ECB: event = ADI_CRYPTO_EVENT_STATUS_ECB_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_HMAC_SUPPORT == 1) + case ADI_CRYPTO_MODE_HMAC: event = ADI_CRYPTO_EVENT_STATUS_HMAC_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) + case ADI_CRYPTO_MODE_SHA: event = ADI_CRYPTO_EVENT_STATUS_SHA_DONE; break; +#endif + default: event = ADI_CRYPTO_EVENT_STATUS_UNKNOWN; break; + } + } + + /* call user's callback and give back buffer pointer */ + hDevice->pfCallback(hDevice->pCBParam, event, (void*)hDevice->pUserBuffer); + + /* clear private copy of user buffer pointer */ + /* this is done in GetBuffer in non-Callback mode */ + hDevice->pUserBuffer = NULL; + } + + /* mark completion */ + hDevice->bCompletion = true; + + /* clear status */ + hDevice->pDev->STAT = status; + + /* post the semaphore */ + SEM_POST(hDevice); + + ISR_EPILOG(); +} +#endif + +/*! \endcond */ + +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto_def.h new file mode 100755 index 0000000000..b9e82e14b3 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto_def.h @@ -0,0 +1,209 @@ +/*! + ***************************************************************************** + @file: adi_crypto_def.h + @brief: Crypto Device Driver definitions for ADuCM4x50 processor + ----------------------------------------------------------------------------- +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_CRYPTO_DEF_H +#define ADI_CRYPTO_DEF_H + +/*! \cond PRIVATE */ + +#include +#include + +/* pick up compiler-specific alignment directives */ +#include +#define ALIGN4 ALIGNED_PRAGMA(4) + +/* Support Check MACROS */ +#define CRYPTO_SUPPORT_KEY_REQUIRED ( \ + (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) \ + ) + +#define CRYPTO_SUPPORT_MODE_CCM_ONLY ( \ + (ADI_CRYPTO_ENABLE_ECB_SUPPORT != 1) \ + && (ADI_CRYPTO_ENABLE_CTR_SUPPORT != 1) \ + && (ADI_CRYPTO_ENABLE_CBC_SUPPORT != 1) \ + && (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) \ + && (ADI_CRYPTO_ENABLE_CMAC_SUPPORT != 1) \ + && (ADI_CRYPTO_ENABLE_SHA_SUPPORT != 1) \ + ) + +#define CRYPTO_SUPPORT_MODE_ANY_NON_CCM ( \ + (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) \ + ) + +#define CRYPTO_SUPPORT_MODE_ANY_NON_SHA ( \ + (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) \ + ) + +/* define local MIN/MAX macros, if not already... */ +#ifndef MIN +#define MIN(a,b) (((a)<(b))?(a):(b)) +#endif +#ifndef MAX +#define MAX(a,b) (((a)>(b))?(a):(b)) +#endif + +/* various size macros */ +#define MAX_CRYPTO_DMA_BYTES (DMA_TRANSFER_LIMIT * sizeof(uint32_t)) + +/* SHA hardware max chunk size attributes */ +#define SHA_CHUNK_MAX_BYTES (64u) +#define SHA_CHUNK_MAX_BITS (SHA_CHUNK_MAX_BYTES * 8U) +#define SHA_CHUNK_MAX_WORDS (16u) + +#define FIFO_WIDTH_IN_BITS (32u) +#define FIFO_WIDTH_IN_BYTES (FIFO_WIDTH_IN_BITS/8u) +#define FIFO_DEPTH (4u) + +#define CRYPTO_INPUT_SIZE_IN_BITS (128u) +#define CRYPTO_INPUT_SIZE_IN_BYTES (CRYPTO_INPUT_SIZE_IN_BITS/8u) + +#define SHA_OUTPUT_SIZE_IN_BITS (256u) +#define SHA_OUTPUT_SIZE_IN_BYTES (SHA_OUTPUT_SIZE_IN_BITS/8u) + + +/* MAKE SURE THIS STRUCT REMAINS *******PERFECTLY ALIGNED******* WITH USER + ADI_CRYPTO_TRANSACTION BECAUSE WE USE BCOPY TO INITIALIZE EACH NEW SUBMIT! + + Internal compute structure reflecting mostly, user ADI_CRYPTO_TRANSACTION, + except for moving data pointers and remaining counts. Contents initialized + directly from from ADI_CRYPTO_TRANSACTION during buffer submit. +*/ +typedef struct _CRYPTO_COMPUTE { + ADI_CRYPTO_CIPHER_MODE eCipherMode; /*!< Cipher mode to use */ + ADI_CRYPTO_CODING_MODE eCodingMode; /*!< Coding Mode (Encryption or Decryption) */ + + ADI_CRYPTO_KEY_BYTE_SWAP eKeyByteSwap; /*!< KEY endianness */ + ADI_CRYPTO_SHA_BYTE_SWAP eShaByteSwap; /*!< SHA endianness */ + ADI_CRYPTO_AES_BYTE_SWAP eAesByteSwap; /*!< AES endianness */ + + uint8_t *pKey; /*!< Pointer to the key data pre-formatted as a byte array, according to eAesKeyLen. */ + ADI_CRYPTO_AES_KEY_LEN eAesKeyLen; /*!< The length of the key */ + + uint32_t *pNextAuthInput; /* CCM mode: pointer to user prefix buffer */ + uint32_t numAuthBytesRemaining; /* Length of the prefix buffer in bytes (should be a multiple of 16 bytes) */ + + uint32_t *pNextInput; /* Pointer to next user 32-bit input location */ + uint32_t numInputBytesRemaining; /* Number of input bytes remaining */ + + uint32_t *pNextOutput; /* Pointer to next user 32-bit output location */ + uint32_t numOutputBytesRemaining; /* Number of output bytes remaining */ + + uint8_t *pNonceIV; /*!< Pointer to user 16-byte array containing one of three values, depending on cipher mode: + CTR mode = 108-bit NONCE + CCM mode = 112-bit NONCE + CBC mode = 128-bit IV (Initialization Vector) + NONCE and IV assume little endian format, for example: CTR NONCE packing is: + NONCE[0] -> 7:0 + NONCE[1] -> 15:8 + ... + NONCE[13] -> 103:96 + NONCE[14](Bits 3:0) -> 107:104 */ + uint32_t CounterInit; /*!< CTR/CCM mode: Counter Initialization Value (CTR=20-bit, CCM=16-bit) */ + uint32_t numValidBytes; /*!< CCM mode: Number of valid bytes in the last (padding) block (1-16) */ + uint32_t numShaBitsRemaining; /*!< SHA mode: Number of bits remaining in the SHA payload, which may be odd-sized */ +} CRYPTO_COMPUTE; + + +/* Crypto device attributes */ +typedef struct _CRYPTO_INFO { + ADI_CRYPT_TypeDef *pDev; /* Pointer to physical Crypto controller */ + ADI_CRYPTO_HANDLE hDevice; /* Device Handle */ +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + IRQn_Type dmaInputIrqNum; + IRQn_Type dmaOutputIrqNum; + DMA_CHANn_TypeDef dmaInputChanNum; + DMA_CHANn_TypeDef dmaOutputChanNum; + volatile ADI_CRYPTO_RESULT dmaError; /* DMA error collector. */ +#endif +} CRYPTO_INFO; + + +#ifdef __ICCARM__ +/* +* Pm123 (RULE 8.5) there shall be no definition of objects or functions in a header file. +* Exception is to allow the Crypto device data type and instance to be declared simultaniously. +*/ +#pragma diag_suppress=Pm123 +#endif /* __ICCARM__ */ + +/* Crypto driver internal data */ +struct __ADI_CRYPTO_DEV_DATA_TYPE { + bool bDeviceEnabled; /* Boolean flag to signify whether the device is enable/disabled */ + bool bDmaEnabled; /* Boolean flag to signify whether the DMA is enable/disabled */ + bool bCompletion; /* Boolean flag to signify whether a transaction is complete */ + + ADI_CRYPT_TypeDef *pDev; /* Pointer to physical Crypto controller */ + + CRYPTO_INFO *pDevInfo; /* access to device info */ + + CRYPTO_COMPUTE Computation; /* Active computation structure */ + + ADI_CRYPTO_TRANSACTION *pUserBuffer; /* saved user buffer pointer from submit */ + ADI_CALLBACK pfCallback; /* User defined callback function */ + void *pCBParam; /* User defined callback param */ + ADI_CRYPTO_RESULT dmaErrorCode; /* saved DMA error code to return via user API */ + + + SEM_VAR_DECLR /* Blocking object abstraction: "Semaphore" for rtos, "bLowPowerExitFlag" for non-rtos, etc. */ +} ADI_CRYPTO_DEV_DATA_TYPE; + +#ifdef __ICCARM__ +#pragma diag_default=Pm123 +#endif /* __ICCARM__ */ + +/*! \endcond */ + +#endif /* ADI_CRYPTO_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/dma/adi_dma.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/dma/adi_dma.c new file mode 100755 index 0000000000..7ced9f0449 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/dma/adi_dma.c @@ -0,0 +1,346 @@ +/*! ***************************************************************************** + * @file: adi_dma.c + * @brief: DMA manager global file. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + + +/*! \addtogroup DMA_Driver DMA Driver + * uDMA Device Driver. + * @{ + */ + +/*============= I N C L U D E S =============*/ +#include +#include +#include +#include +#include + +/*! \cond PRIVATE */ + +/*============= M I S R A =============*/ + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): he basic types of char, int, short, long, float, and double should not be used +* Need to use bool. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +*/ +#pragma diag_suppress=Pm011,Pm140 +#endif /* __ICCARM__ */ + +/*============= D E F I N E S =============*/ + +/* CCD array allocation macros */ +#define CCD_ALIGN (0x400) /* Memory alignment required for CCD array */ +#define CCD_SIZE (32u) /* Configure CCD allocation as an integral power of two, + i.e., 24 channels is allocated as 32 */ + +/*============= R E G I S T E R D E F I N E S =============*/ + + + + +/*============= T Y P E D E F I N E S =============*/ + +/*! DMA Channel callback information structure */ +typedef struct _DMA_CHANNEL { + ADI_CALLBACK pfCallback; /*!< Pointer to the callback func */ + void* pCBParam; /*!< Application Callback param */ +} DMA_CHANNEL_CALLBACK_INFO; + +/*! \struct ADI_DMA_DEV_DATA + * DMA Device instance data structure + * + * CallbackInfo[NUM_DMA_CHANNELSn] + * The semantics of indexes used to access CallbackInfo elements is defined by the semantics + * of the bits in registers DMA_ERRCHNL_CLR and DMA_INVALIDDESC_CLR. The position of these + * bits define the channel nodes of the peripheral they map to, e.g. bit N maps to channel + * node N. + */ +typedef struct { + bool Initialized; /*!< track initialization state. See function adi_dma_Init) */ + DMA_CHANNEL_CALLBACK_INFO CallbackInfo[NUM_DMA_CHANNELSn]; + uint32_t ChannelsInUse; /*!< bits 0 to 26 record active channels */ +} ADI_DMA_DEV_DATA; + + +/*============= D A T A =============*/ + +/* DMA descriptor arrays must be contiguous */ +/* AND impose strict alignment requirements */ +/* Each compiler has different alignment directives */ + +/* ALIGNED: DMA channel control data array declaration */ +ADI_ALIGNED_PRAGMA(CCD_ALIGN) +static ADI_DCC_TypeDef gChannelControlDataArray[CCD_SIZE * 2u] ADI_ALIGNED_ATTRIBUTE(CCD_ALIGN) + +#ifdef ADI_DMA_DESCRIPTORS_IN_VOLATILE_MEMORY + /* conditional placement of DMA descriptor table to volatile memory */ + @ "volatile_ram"; +#else + /* default placement to non-volatile memory (no override) */ + ; +#endif + + +/* pointer to the primary CCD array */ +ADI_DCC_TypeDef* const pPrimaryCCD = &gChannelControlDataArray[0]; + +/* pointer to the alternate CCD array */ +ADI_DCC_TypeDef* const pAlternateCCD = &gChannelControlDataArray[CCD_SIZE]; + + +/*! DMA Device Driver Data instance + * 32 Channel Handles initialized to {0, 0}, i.e. call-back function pointer + * set to NULL and call-back function parameters set to NULL + */ +static ADI_DMA_DEV_DATA DMA_DevData = { + + false, /*!< DMA device data not initialized. (See adi_dma_Init) */ + {{0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, + {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, + {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, + {0,0}, {0,0}, {0,0}}, + 0ul /*!< channels-in-use bitfield */ +}; + +/*! pointer to the DMA Device Driver Data instance */ +static ADI_DMA_DEV_DATA* const pDMA_DevData = &DMA_DevData; + +/*============= Local function declarations =============*/ + +/*========== DMA HANDLERS ==========*/ + +/*! DMA Error Handler */ +void DMA_Err_Int_Handler(void); + +/*========== U T I L I T Y M A C R O S ==========*/ + +/*! \endcond*/ +/*============= A P I I M P L E M E N T A T I O N S =============*/ + +/*! + * @brief Initialize the DMA peripheral + * + * @return none + * + * The application must call this API once + * + */ +void adi_dma_Init(void) +{ + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + + if( false == pDMA_DevData->Initialized ) + { + pDMA_DevData->Initialized = true; + + /* Enable the DMA Controller */ + pADI_DMA0->CFG |= BITM_DMA_CFG_MEN; + + /* Set descriptor memory base pointer on DMA controller */ + pADI_DMA0->PDBPTR = (uint32_t)pPrimaryCCD; + + /* Enable the DMA Error Interrupt */ + NVIC_EnableIRQ(DMA_CHAN_ERR_IRQn); + + /* Reset per-channel, bitmapped control registers (W1C) */ + const uint32_t w1r_value = (uint32_t) ((1 << NUM_DMA_CHANNELSn) - 1); + pADI_DMA0->RMSK_SET = w1r_value; + pADI_DMA0->EN_CLR = w1r_value; + pADI_DMA0->ALT_CLR = w1r_value; + pADI_DMA0->PRI_CLR = w1r_value; + pADI_DMA0->ERRCHNL_CLR = w1r_value; + pADI_DMA0->ERR_CLR = w1r_value; + pADI_DMA0->INVALIDDESC_CLR = w1r_value; + } + + ADI_EXIT_CRITICAL_REGION(); +} + +/** + * @brief Register a call-back function for a DMA channel. + * + * @param [in] eChannelID The ID of the DMA channel being assigned a call-back function. + * @param [in] pfCallback Pointer to the application callback function. + * @param [in] pCBParam Application callback parameter. + * + * @details The function registers a call-back function for the DMA channel node + * identified by eChannelID and stores the extra parameters this call-back function + * may require. A NULL callback function pointer means "DMA channel unused". + * + * @return Status + * - #ADI_DMA_SUCCESS Successfully registered a call-back function for the given DMA channel node. + * - #ADI_DMA_ERR_NOT_INITIALIZED [D] adi_dma_Init must be called prior registering a call-back function. + * - #ADI_DMA_ERR_INVALID_PARAMETER [D] Some parameter(s) passed to the function is invalid. + */ +ADI_DMA_RESULT adi_dma_RegisterCallback ( + DMA_CHANn_TypeDef const eChannelID, + ADI_CALLBACK const pfCallback, + void* const pCBParam + ) +{ + ADI_DMA_RESULT result = ADI_DMA_SUCCESS; + +#ifdef ADI_DEBUG + /* DMA must be initialized first */ + if (false == pDMA_DevData->Initialized) { + result = ADI_DMA_ERR_NOT_INITIALIZED; + }else{ + const size_t numChannelId = sizeof(pDMA_DevData->CallbackInfo) / sizeof(DMA_CHANNEL_CALLBACK_INFO); + if (numChannelId <= eChannelID) /*!< pDMA_DevData->CallbackInfo definition is invalid */ + { + result = ADI_DMA_ERR_INVALID_PARAMETER; + } + } + if (ADI_DMA_SUCCESS == result) /* if no errors previously detected */ +#endif + { + /* eChannelID cannot be out of range by definition (we use DMA_CHANn_TypeDef) */ + DMA_CHANNEL_CALLBACK_INFO * pChannel = &pDMA_DevData->CallbackInfo[eChannelID]; + + /* Set the callback parameters */ + pChannel->pfCallback = pfCallback; /* assign the pointer to a callback function */ + pChannel->pCBParam = pCBParam; /* store the parameters to be used with the callback function */ + + const uint32_t nChannelBit = (1u << eChannelID); + if (NULL != pfCallback) { + pDMA_DevData->ChannelsInUse |= nChannelBit; /* set the bit to mark the channel as "being used" */ + }else{ + pDMA_DevData->ChannelsInUse &= (~nChannelBit); /* clear the bit to mark the channel as "not being used" */ + } + } + return result; +} + +/*! \cond PRIVATE */ + + +#if defined(__ICCARM__) + +/* ARM Cortex-M3/M4, IAR compiler (CMSIS standard) */ +#define ADI_CLZ(X) __CLZ(X) + +#elif defined(__GNUC__) + +/* ARM Cortex-M3/M4, GNU-ARM compiler */ +#define ADI_CLZ(X) __builtin_clz(X) + +#elif defined(__CC_ARM) + +/* ARM Cortex-M3/M4, Keil compiler */ +#define ADI_CLZ(X) __clz(X) + +#else + +#error "Macro ADI_CLZ undefined!!!" + +#endif + +/*! DMA Error Handler + * + * The DMA Error handler looks at the channels in use which are flagged in register ERRCHNL_CLR + * or INVALIDDESC_CLR and calls the associated call-back functions, if defined. If a call-back + * function is undefined (NULL pointer) then it means the associated driver ignores these errors. + * + * Then, all the bits set in ERRCHNL_CLR and INVALIDDESC_CLR at the time the handler is called + * are cleared. + */ +void DMA_Err_Int_Handler(void) +{ + ISR_PROLOG() + + const uint32_t nErrClr = pADI_DMA0->ERR_CLR; /* get all the bits set in ERR_CLR */ + const uint32_t nErrChnClr = pADI_DMA0->ERRCHNL_CLR; /* get all the bits set in ERRCHNL_CLR */ + const uint32_t nInvdDescClr = pADI_DMA0->INVALIDDESC_CLR; /* get all the bits set in INVALIDDESC_CLR */ + + /* if there are invalid channel descriptors or channel errors amongts the channels in use */ + uint32_t functionsToBeCalled = pDMA_DevData->ChannelsInUse & (nErrChnClr | nInvdDescClr); + + if (functionsToBeCalled > 0u) + { + const uint32_t numBits = sizeof(uint32_t) << 3; /* maximum number of bits to be considered */ + uint32_t nlz; /* number of leading zeroes in functionsToBeCalled */ + + /* For all the bits set in functionsToBeCalled, starting from the MSB */ + for (nlz = (uint32_t) ADI_CLZ(functionsToBeCalled); nlz < numBits; nlz = (uint32_t) ADI_CLZ(functionsToBeCalled)) + { + const uint32_t bitSet = numBits - nlz - 1u; /* bit position in functionsToBeCalled */ + const uint32_t selected_bit = ((uint32_t)1u << bitSet); + DMA_CHANNEL_CALLBACK_INFO* pChannel = &pDMA_DevData->CallbackInfo[bitSet]; + + /* if there's a callback function to be called */ + if (NULL != pChannel->pfCallback) + { + /* define the nature of the error: DMA bus error or else invalid descriptor */ + uint32_t nEvent = ((nErrChnClr & selected_bit) != 0u) + ? (uint32_t)ADI_DMA_EVENT_ERR_BUS + : (uint32_t)ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR; + + /* report the error to the peripheral through the callback function */ + pChannel->pfCallback (pChannel->pCBParam, nEvent, NULL ); + } + + functionsToBeCalled &= ~selected_bit; /* clear bit in functionsToBeCalled */ + } + } + + /* Clear the errors processed in the loop above */ + pADI_DMA0->ERRCHNL_CLR = nErrChnClr; /* W1C: clear only all the bits set in nErrChnClr */ + pADI_DMA0->INVALIDDESC_CLR = nInvdDescClr; /* W1C: clear only all the bits set in nInvdDescClr */ + pADI_DMA0->ERR_CLR = nErrClr; /* W1C: clear only all the bits set in nErrClr */ + + ISR_EPILOG() +} + +/*! \endcond*/ + +/**@}*/ + + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/adc/adi_adc.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/adc/adi_adc.h new file mode 100755 index 0000000000..1794f4ab2c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/adc/adi_adc.h @@ -0,0 +1,346 @@ +/*! ***************************************************************************** + * @file adi_adc.h + * @brief Main include file for ADC Device driver definitions + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_ADC_H +#define ADI_ADC_H + +#include +#include +#include +#include /* for ADI_SEM_SIZE */ + +/** @addtogroup ADC_Driver ADC Driver +* @{ +*/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! Amount of memory(In bytes) required by the ADC device driver for managing the operation + * of a ADC controller. The memory is passed to the driver when the driver is opended. + * The memory is completely owned by the driver till the the driver is closed. + * + */ +#define ADI_ADC_MEMORY_SIZE (48u + ADI_SEM_SIZE) /*!< Memory Size of the buffer required by the ADC driver */ + + +/*! + * \enum ADI_ADC_RESULT + * ADC API return codes + */ +typedef enum { + ADI_ADC_SUCCESS = 0, /*!< No Error, API suceeded */ + ADI_ADC_INVALID_DEVICE_NUM, /*!< Invalid device number passed */ + ADI_ADC_INVALID_DEVICE_HANDLE, /*!< Invalid device handle passed */ + ADI_ADC_INVALID_STATE, /*!< Invalid State */ + ADI_ADC_INSUFFICIENT_MEMORY, /*!< Insufficient memory passed to the driver */ + ADI_ADC_IN_USE, /*!< ADC is alreaady in use */ + ADI_ADC_INVALID_PARAMETER, /*!< Invalid parameter passed to the driver */ + ADI_ADC_NULL_POINTER, /*!< Null pointer passed when expecting a valid pointer */ + ADI_ADC_FAILURE, /*!< General ADC Failure */ + ADI_ADC_INVALID_SEQUENCE, /*!< Invalid sequence of API calls */ + ADI_ADC_ERR_RTOS, /*!< RTOS error occurred */ + ADI_ADC_INVALID_OPERATION, /*!< API call is an invalid operation */ + ADI_ADC_INVALID_BUFFER, /*!< Buffer passed to the application is invalid */ + ADI_ADC_BUFFER_OVERFLOW, /*!< Buffer overflow occurred */ + ADI_ADC_DMA_ERROR, /*!< DMA Error occurred */ + ADI_ADC_BAD_SYS_CLOCK, /*!< Could not retrieve core clock value. */ +} ADI_ADC_RESULT; + +/*! + * \enum ADI_ADC_VREF_SRC + * Voltage Reference source selection. + */ +typedef enum { + ADI_ADC_VREF_SRC_INT_1_25_V, /*!< 1.25V Internal Voltage Reference */ + ADI_ADC_VREF_SRC_INT_2_50_V, /*!< 2.50V Internal Voltage Reference */ + ADI_ADC_VREF_SRC_EXT, /*!< External Voltage Reference */ + ADI_ADC_VREF_SRC_VBAT, /*!< Battery Voltage as Voltage Reference source */ +} ADI_ADC_VREF_SRC; + +/*! + * \enum ADI_ADC_RESOLUTION + * Resolution of the ADC. + */ +typedef enum { + ADI_ADC_RESOLUTION_12_BIT, /*!< 12-bit ADC Resolution */ + ADI_ADC_RESOLUTION_13_BIT, /*!< 13-bit ADC Resolution */ + ADI_ADC_RESOLUTION_14_BIT, /*!< 14-bit ADC Resolution */ + ADI_ADC_RESOLUTION_15_BIT, /*!< 15-bit ADC Resolution */ + ADI_ADC_RESOLUTION_16_BIT /*!< 16-bit ADC Resolution */ +} ADI_ADC_RESOLUTION; + +/*! + * \typedef ADI_ADC_CHANNEL + * Typedef for ADC Channels + */ +typedef uint32_t ADI_ADC_CHANNEL; + +/*! + * defines for ADC Channels + */ +#define ADI_ADC_CHANNEL_0 (1u << 0u) /*!< ADC Channel 0 */ +#define ADI_ADC_CHANNEL_1 (1u << 1u) /*!< ADC Channel 1 */ +#define ADI_ADC_CHANNEL_2 (1u << 2u) /*!< ADC Channel 2 */ +#define ADI_ADC_CHANNEL_3 (1u << 3u) /*!< ADC Channel 3 */ +#define ADI_ADC_CHANNEL_4 (1u << 4u) /*!< ADC Channel 4 */ +#define ADI_ADC_CHANNEL_5 (1u << 5u) /*!< ADC Channel 5 */ +#define ADI_ADC_CHANNEL_6 (1u << 6u) /*!< ADC Channel 6 */ +#define ADI_ADC_CHANNEL_7 (1u << 7u) /*!< ADC Channel 7 */ + +/*! + * \enum ADI_ADC_EVENT + * Callback events from the ADC driver. + */ +typedef enum { + ADI_ADC_EVENT_CALIBRATION_DONE, /*!< Calibration done event. arg to the callback function will be NULL. */ + ADI_ADC_EVENT_ADC_READY, /*!< ADC Ready event. arg to the callback function will be null */ + ADI_ADC_EVENT_OVERFLOW, /*!< Overflow event occurred. The channel(#ADI_ADC_CHANNEL) for which the overflow occurred will be passed as arg to the callback function. */ + ADI_ADC_EVENT_HIGH_LIMIT_CROSSED, /*!< High Limit crossed event. The channel(#ADI_ADC_CHANNEL) for which the limit is crossed will be passed as arg to the callback function. */ + ADI_ADC_EVENT_LOW_LIMIT_CROSSED, /*!< Low Limit crossed event. The channel(#ADI_ADC_CHANNEL) for which the limit is crossed will be passed as arg to the callback function. */ +} ADI_ADC_EVENT; + +/*! Structure which hold the details of the buffer and sampling details */ +typedef struct __ADI_ADC_BUFFER { + uint32_t nChannels; /*!< Channels to sample. Should be an ORed value of #ADI_ADC_CHANNEL enum */ + void* pDataBuffer; /*!< Pointer to the Buffer to read the sample value into. If single channel(say Channel 0) is selected + then the format of buffer will be .... but if + multiple channels (say Channel 1 and Channel2) are selected then the format of buffer will be + .... + \n The pBuffer should be 2 byte aligned. + \n + \n If N is the number of channels selected then in single iteration mode the number of samples + written to in the buffer will be N and for multiple iteration, the driver will try to fill the whole + buffer with data and it is preferred that the nBuffSize be able to accommodate a multiple of N samples. + */ + uint32_t nNumConversionPasses; /*!< Num of conversion passes */ + uint32_t nBuffSize; /*!< Size of the buffer supplied */ +} ADI_ADC_BUFFER; + +/* Type def for the ADC Handle. */ +typedef struct __ADI_ADC_DEVICE* ADI_ADC_HANDLE; /*!< ADC Device Handler */ + + +/*============= A P I F U N C T I O N S P R O T O T Y P E S =============*/ + +/* Opens an ADC device instance. */ +ADI_ADC_RESULT adi_adc_Open ( + uint32_t nDeviceNum, + void* pMemory, + uint32_t nMemorySize, + ADI_ADC_HANDLE* phDevice +); + +/* Close the given device instance */ +ADI_ADC_RESULT adi_adc_Close(ADI_ADC_HANDLE hDevice); + +/* Power up or power down the ADC */ +ADI_ADC_RESULT adi_adc_PowerUp (ADI_ADC_HANDLE hDevice, bool bPowerUp); + +/* Register the callback */ +ADI_ADC_RESULT adi_adc_RegisterCallback( + ADI_ADC_HANDLE hDevice, + ADI_CALLBACK pfCallback, + void *pCBParam +); + +/* Enables/Disables the ADC Subsystem */ + ADI_ADC_RESULT adi_adc_EnableADCSubSystem ( + ADI_ADC_HANDLE hDevice, + bool bEnable +); + +/* Returns whether the ADC subsytem is ready */ +ADI_ADC_RESULT adi_adc_IsReady ( + ADI_ADC_HANDLE hDevice, + bool *pbReady +); + +/* Set the voltage reference source */ +ADI_ADC_RESULT adi_adc_SetVrefSource ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_VREF_SRC eVrefSrc +); + +/* Enable/Disable current sink */ +ADI_ADC_RESULT adi_adc_SinkEnable ( + ADI_ADC_HANDLE hDevice, + bool bEnable +); + +/* Start the ADC Calibration */ +ADI_ADC_RESULT adi_adc_StartCalibration ( + ADI_ADC_HANDLE hDevice +); + + ADI_ADC_RESULT adi_adc_IsCalibrationDone ( + ADI_ADC_HANDLE hDevice, + bool* pbCalibrationDone + ); + + +/* Set the acquisition time of ADC in ADC clock cycles */ +ADI_ADC_RESULT adi_adc_SetAcquisitionTime( + ADI_ADC_HANDLE hDevice, + uint32_t nAcqTimeInAClkCycles +); + +/* Set the delay time of ADC in ADC cycles for multi iteration mode */ +ADI_ADC_RESULT adi_adc_SetDelayTime( + ADI_ADC_HANDLE hDevice, + uint32_t nDelayInAClkCycles +); + +/* set the resolution of ADC. The default resolution of ADC is 12-bit and the ADC increases the resolution by oversampling */ +ADI_ADC_RESULT adi_adc_SetResolution ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_RESOLUTION eResolution +); + +/* Enable Averaging for all ADC channels */ +ADI_ADC_RESULT adi_adc_EnableAveraging ( + ADI_ADC_HANDLE hDevice, + uint16_t nAveragingSamples +); + +/* Configure low limit for an ADC channel when it's used as a digital comparator. */ +ADI_ADC_RESULT adi_adc_SetLowLimit ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + bool bEnable, + uint16_t nLowLimit +); + +/* Configure high limit for an ADC channel when it's used as a digital comparator. */ +ADI_ADC_RESULT adi_adc_SetHighLimit ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + bool bEnable, + uint16_t nHighLimit +); + + +/* Configure hysteresis for an ADC channel when it's used as a digital comparator. */ +ADI_ADC_RESULT adi_adc_SetHysteresis( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + bool bEnable, + uint16_t nHysteresis +); + +/* Configure number of monitor cycles for an ADC channel when it's used as a digital comparator. */ +ADI_ADC_RESULT adi_adc_SetNumMonitorCycles( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + uint32_t nNumMonitorCycles +); + +/* Enable/Disable digital comparator for the given channel(s) */ +ADI_ADC_RESULT adi_adc_EnableDigitalComparator ( + ADI_ADC_HANDLE hDevice, + bool bEnableComparator +); + +/* Submit buffer for sampling */ +ADI_ADC_RESULT adi_adc_SubmitBuffer ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_BUFFER* pBuffer +); + +/* Get a completed buffer from the driver */ +ADI_ADC_RESULT adi_adc_GetBuffer( + ADI_ADC_HANDLE hDevice, + ADI_ADC_BUFFER** ppBuffer +); + +/* Enable/Disable buffer processing */ +ADI_ADC_RESULT adi_adc_Enable ( + ADI_ADC_HANDLE hDevice, + bool bEnable +); + +/* Check whether a completed buffer is available in the driver */ +ADI_ADC_RESULT adi_adc_IsBufferAvailable( + ADI_ADC_HANDLE hDevice, + bool* pbIsBufferAvailable +); + +/* Read the given channels. This will only return once the given amount of samples are collected */ +ADI_ADC_RESULT adi_adc_ReadChannels ( + ADI_ADC_HANDLE hDevice, + uint32_t nChannels, + uint32_t nNumConversionPasses, + void* pBuffer, + uint32_t nBuffLength +); + +/* Get Battery Voltage */ +ADI_ADC_RESULT adi_adc_GetBatteryVoltage ( + ADI_ADC_HANDLE hDevice, + uint32_t nRefVoltage, + uint32_t* pnBatVoltage +); + +/* Enable/Disable Temperature Sensor */ +ADI_ADC_RESULT adi_adc_EnableTemperatureSensor ( + ADI_ADC_HANDLE hDevice, + bool bEnable + ); + +/* Get the Temperature Value */ +ADI_ADC_RESULT adi_adc_GetTemperature ( + ADI_ADC_HANDLE hDevice, + uint32_t nRefVoltage, + int32_t* pnTemperature + ); + +#ifdef __cplusplus +} +#endif + +/**@}*/ + + +#endif /* ADI_ADC_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/beep/adi_beep.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/beep/adi_beep.h new file mode 100755 index 0000000000..6fa441895e --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/beep/adi_beep.h @@ -0,0 +1,277 @@ +/*! ***************************************************************************** + * @file adi_beep.h + * @brief Main include file for BEEP device driver definitions + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +/** @addtogroup BEEP_Driver BEEP Driver +* @{ +*/ +#ifndef ADI_BEEP_H +#define ADI_BEEP_H + +#include "adi_processor.h" + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/*! Amount of memory(In bytes) required by the Beep device driver for managing the operation. + * This memory is completely owned by the driver till the end of the operation. + */ +#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1 +/*! @hideinitializer Indicates the size of the BEEP memory to be used */ +#define ADI_BEEP_MEMORY_SIZE (20u + ADI_SEM_SIZE) +#else +/*! @hideinitializer Indicates the size of the BEEP memory to be used */ +#define ADI_BEEP_MEMORY_SIZE (12u + ADI_SEM_SIZE) +#endif + +/*! + * \enum ADI_BEEP_RESULT + * Beeper API return codes + */ +typedef enum +{ + ADI_BEEP_SUCCESS = 0, /*!< No Error, API suceeded */ + + ADI_BEEP_FAILURE, /*!< An unknown error was detected */ + ADI_BEEP_ALREADY_INITIALIZED, /*!< BEEP is already initialized */ + ADI_BEEP_BAD_DEV_HANDLE, /*!< Invalid device handle passed */ + ADI_BEEP_BAD_DEV_ID, /*!< Asking to initialize an unknown device num */ + ADI_BEEP_NOT_INITIALIZED, /*!< BEEP not yet initialized */ + ADI_BEEP_PARAM_OUT_OF_RANGE, /*!< Parameter is out of range. */ + ADI_BEEP_INVALID_COUNT, /*!< Invalid count for supplied beep sequence */ + ADI_BEEP_NULL_PTR, /*!< Null pointer supplied. */ + ADI_BEEP_SEMAPHORE_FAILED, /*!< BEEP semaphore failure. */ +} ADI_BEEP_RESULT; + + +/*! + * \enum ADI_BEEP_DEV_ID + * @brief Beeper Device IDs. + * @details List of all Beeper Device IDs for the current part + */ +typedef enum +{ + ADI_BEEP_DEVID_0 = 0, /*!< BEEP Timer Device 0 */ + ADI_BEEP_MAX_DEVID /*!< max number of BEEP devices */ +} ADI_BEEP_DEV_ID; + +/*! + * \enum ADI_BEEP_INTERRUPT + * @brief Beeper Interrupt Bits. + * @details List of all Beeper interrupt (enables and status) bits. + */ +typedef enum +{ + ADI_BEEP_INTERRUPT_SEQUENCE_END = BITM_BEEP_CFG_SEQATENDIRQ, /*!< Beeper sequence has finished */ + ADI_BEEP_INTERRUPT_NOTE_END = BITM_BEEP_CFG_AENDIRQ, /*!< Beeper note has finished */ +} ADI_BEEP_INTERRUPT; + + +#define LFCLK_FREQ 32768.0f /*!< Beeper main clock frequency. */ +#define FREQUENCY_ENCODE(x) (uint8_t)(LFCLK_FREQ/(x) + 0.5f) /*!< Beeper tone frequency encoder macro */ + +/*! + * \enum ADI_BEEP_NOTE_FREQUENCY + * @brief Beeper tone frequency list. + * @details List of possible Beeper tone frequencies. + */ +typedef enum { + /* Constants are pre-computed note frequencies (Hz). */ + /* See http://www.phy.mtu.edu/~suits/notefreqs.html. */ + /* Encodings are clock divider values for that note. */ + /* Flats are the same as the lower sharp, so only sharps are listed. */ + /* Even though octaves are simple frequency doublings/halvings */ + /* of adjuacient octaves, we pre-compute each constant (as opposed */ + /* to halving/doubling the encodings between octaves) to */ + /* minimize repeated doubling/halving errors across all octaves. */ + /* !!!ALL ENCODINGS MUST BE IN THE RANGE 4-127!!! */ + + ADI_BEEP_FREQ_REST = (0), /*!< silence */ + + ADI_BEEP_FREQ_C4 = FREQUENCY_ENCODE(261.63f), /*!< Middle C (lowest representable frequency @ 32KHz) */ + ADI_BEEP_FREQ_Cs4 = FREQUENCY_ENCODE(277.18f), + ADI_BEEP_FREQ_D4 = FREQUENCY_ENCODE(293.66f), + ADI_BEEP_FREQ_Ds4 = FREQUENCY_ENCODE(311.13f), + ADI_BEEP_FREQ_E4 = FREQUENCY_ENCODE(329.63f), + ADI_BEEP_FREQ_F4 = FREQUENCY_ENCODE(349.23f), + ADI_BEEP_FREQ_Fs4 = FREQUENCY_ENCODE(369.99f), + ADI_BEEP_FREQ_G4 = FREQUENCY_ENCODE(392.00f), + ADI_BEEP_FREQ_Gs4 = FREQUENCY_ENCODE(415.30f), + ADI_BEEP_FREQ_A4 = FREQUENCY_ENCODE(440.00f), + ADI_BEEP_FREQ_As4 = FREQUENCY_ENCODE(466.16f), + ADI_BEEP_FREQ_B4 = FREQUENCY_ENCODE(493.88f), + + ADI_BEEP_FREQ_C5 = FREQUENCY_ENCODE(523.25f), + ADI_BEEP_FREQ_Cs5 = FREQUENCY_ENCODE(554.37f), + ADI_BEEP_FREQ_D5 = FREQUENCY_ENCODE(587.33f), + ADI_BEEP_FREQ_Ds5 = FREQUENCY_ENCODE(622.25f), + ADI_BEEP_FREQ_E5 = FREQUENCY_ENCODE(659.26f), + ADI_BEEP_FREQ_F5 = FREQUENCY_ENCODE(698.46f), + ADI_BEEP_FREQ_Fs5 = FREQUENCY_ENCODE(739.99f), + ADI_BEEP_FREQ_G5 = FREQUENCY_ENCODE(783.99f), + ADI_BEEP_FREQ_Gs5 = FREQUENCY_ENCODE(830.61f), + ADI_BEEP_FREQ_A5 = FREQUENCY_ENCODE(880.00f), + ADI_BEEP_FREQ_As5 = FREQUENCY_ENCODE(932.33f), + ADI_BEEP_FREQ_B5 = FREQUENCY_ENCODE(987.77f), + + ADI_BEEP_FREQ_C6 = FREQUENCY_ENCODE(1046.50f), + ADI_BEEP_FREQ_Cs6 = FREQUENCY_ENCODE(1108.73f), + ADI_BEEP_FREQ_D6 = FREQUENCY_ENCODE(1174.66f), + ADI_BEEP_FREQ_Ds6 = FREQUENCY_ENCODE(1244.51f), + ADI_BEEP_FREQ_E6 = FREQUENCY_ENCODE(1318.51f), + ADI_BEEP_FREQ_F6 = FREQUENCY_ENCODE(1396.91f), + ADI_BEEP_FREQ_Fs6 = FREQUENCY_ENCODE(1479.98f), + ADI_BEEP_FREQ_G6 = FREQUENCY_ENCODE(1567.98f), + ADI_BEEP_FREQ_Gs6 = FREQUENCY_ENCODE(1661.22f), + ADI_BEEP_FREQ_A6 = FREQUENCY_ENCODE(1760.00f), + ADI_BEEP_FREQ_As6 = FREQUENCY_ENCODE(1864.66f), + ADI_BEEP_FREQ_B6 = FREQUENCY_ENCODE(1975.53f), + + ADI_BEEP_FREQ_C7 = FREQUENCY_ENCODE(2093.00f), + ADI_BEEP_FREQ_Cs7 = FREQUENCY_ENCODE(2217.46f), + ADI_BEEP_FREQ_D7 = FREQUENCY_ENCODE(2349.32f), + ADI_BEEP_FREQ_Ds7 = FREQUENCY_ENCODE(2489.02f), + ADI_BEEP_FREQ_E7 = FREQUENCY_ENCODE(2637.02f), + ADI_BEEP_FREQ_F7 = FREQUENCY_ENCODE(2793.83f), + ADI_BEEP_FREQ_Fs7 = FREQUENCY_ENCODE(2959.96f), + ADI_BEEP_FREQ_G7 = FREQUENCY_ENCODE(3135.96f), + ADI_BEEP_FREQ_Gs7 = FREQUENCY_ENCODE(3322.44f), + ADI_BEEP_FREQ_A7 = FREQUENCY_ENCODE(3520.00f), + ADI_BEEP_FREQ_As7 = FREQUENCY_ENCODE(3729.31f), + ADI_BEEP_FREQ_B7 = FREQUENCY_ENCODE(3951.07f), + + ADI_BEEP_FREQ_C8 = FREQUENCY_ENCODE(4186.01f), + ADI_BEEP_FREQ_Cs8 = FREQUENCY_ENCODE(4434.92f), + ADI_BEEP_FREQ_D8 = FREQUENCY_ENCODE(4698.64f), + ADI_BEEP_FREQ_Ds8 = FREQUENCY_ENCODE(4978.03f), + ADI_BEEP_FREQ_E8 = FREQUENCY_ENCODE(5274.04f), + ADI_BEEP_FREQ_F8 = FREQUENCY_ENCODE(5587.65f), + ADI_BEEP_FREQ_Fs8 = FREQUENCY_ENCODE(5919.91f), + ADI_BEEP_FREQ_G8 = FREQUENCY_ENCODE(6271.93f), +} ADI_BEEP_NOTE_FREQUENCY; + +#define ADI_BEEP_DUR_ZERO (0) /*!< Beeper zero tone duration value */ +#define ADI_BEEP_DUR_MIN (1) /*!< Beeper minimum tone duration value */ +#define ADI_BEEP_DUR_MAX (254) /*!< Beeper maximum tone duration value */ +#define ADI_BEEP_DUR_INFINITE (255) /*!< Beeper infinite tone duration value */ + +/*! A device handle used in all API functions to identify the BEEP device. */ +typedef void * ADI_BEEP_HANDLE; + +#define DURATION_ENCODE(x) (uint8_t)((float)ADI_BEEP_DUR_MAX/(float)(x) + 0.5f) /*!< Beeper tone duration encoder macro */ + +/*! + * \enum ADI_BEEP_NOTE_DURATION + * @brief Beeper tone duration list. + * @details List of possible Beeper tone durations. + */ +typedef enum { + ADI_BEEP_DUR_0 = ADI_BEEP_DUR_ZERO, /*!< stop */ + ADI_BEEP_DUR_32_32 = DURATION_ENCODE(1), /*!< whole note (1.016 seconds) */ + ADI_BEEP_DUR_16_32 = DURATION_ENCODE(2), /*!< half note */ + ADI_BEEP_DUR_12_32 = DURATION_ENCODE(8/3), /*!< three eights note */ + ADI_BEEP_DUR_8_32 = DURATION_ENCODE(4), /*!< one quarter note */ + ADI_BEEP_DUR_6_32 = DURATION_ENCODE(16/3), /*!< three sixteenth note */ + ADI_BEEP_DUR_4_32 = DURATION_ENCODE(8), /*!< one eighth note */ + ADI_BEEP_DUR_2_32 = DURATION_ENCODE(16), /*!< one sixteenth note */ + ADI_BEEP_DUR_1_32 = DURATION_ENCODE(32), /*!< one thirty-secondth note */ + ADI_BEEP_DUR_N = ADI_BEEP_DUR_INFINITE, /*!< continuous play */ +} ADI_BEEP_NOTE_DURATION; + +/*! + * \struct ADI_BEEP_NOTE + * @brief Beeper note structure. + * @details Describes a note in terms of frequency and duration. + */ +typedef struct { + ADI_BEEP_NOTE_FREQUENCY frequency; /*!< Frequency of the note */ + ADI_BEEP_NOTE_DURATION duration; /*!< Duration of the note */ +} ADI_BEEP_NOTE; + + +/*================ E X T E R N A L S ==================*/ + +/* + * Beeper API + */ + +ADI_BEEP_RESULT adi_beep_Open (ADI_BEEP_DEV_ID const DeviceNum, + void* const pMemory, + uint32_t const MemorySize, + ADI_BEEP_HANDLE* const phDevice); + +ADI_BEEP_RESULT adi_beep_RegisterCallback (ADI_BEEP_HANDLE const hDevice, + ADI_CALLBACK pfCallback, + void* const pCBParam); + +ADI_BEEP_RESULT adi_beep_PlayNote (ADI_BEEP_HANDLE const hDevice, + ADI_BEEP_NOTE note); + +ADI_BEEP_RESULT adi_beep_PlayTwoTone (ADI_BEEP_HANDLE const hDevice, + ADI_BEEP_NOTE noteA, + ADI_BEEP_NOTE noteB, + uint8_t count); + +ADI_BEEP_RESULT adi_beep_PlaySequence (ADI_BEEP_HANDLE const hDevice, + ADI_BEEP_NOTE aSequence[], + uint8_t count); + +ADI_BEEP_RESULT adi_beep_Enable (ADI_BEEP_HANDLE const hDevice, + bool const bFlag); + +ADI_BEEP_RESULT adi_beep_Wait (ADI_BEEP_HANDLE const hDevice); + +ADI_BEEP_RESULT adi_beep_Close (ADI_BEEP_HANDLE const hDevice); + +#ifdef __cplusplus +} +#endif + + +#endif /* ADI_BEEP_H */ +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crc/adi_crc.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crc/adi_crc.h new file mode 100755 index 0000000000..9fddbc6085 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crc/adi_crc.h @@ -0,0 +1,236 @@ +/*! ***************************************************************************** + * @file adi_crc.h + * @brief CRC (Cyclic Redundancy Check) Device driver global include file + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_CRC_H +#define ADI_CRC_H + +/** @addtogroup CRC_Driver CRC Device Driver + * @{ + */ + +#include + +/*============= I N C L U D E S =============*/ +#include +/* Memory size check */ +#include + +/* DMA Manager includes */ +#include + +/* Include the config file for CRC */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*============== D E F I N E S ===============*/ + +#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0) + + +/** + * The size of types may vary between building tools (int, char, enumerator, etc.). + * This impacts the memory size required by a CRC driver. + * Consequently, ADI_CRC_MEMORY_SIZE is environment dependent. + */ +#if defined(__ICCARM__) +/** + * The amount of application supplied memory required to operate a core driven CRC device + * using a CRC driver built in IAR environment. + */ +#define ADI_CRC_MEMORY_SIZE (32u) +#else +/** + * The amount of application supplied memory required to operate a core driven CRC device + * using a CRC driver built in a generic built environment. + * Note: Create a new macro definition for your targetted development environment + * if this generic value was not appropriate in your development environment. + */ +#define ADI_CRC_MEMORY_SIZE (32u) +#endif + + +#else /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + + +/** + * The size of types may vary between building tools (int, char, enumerator, etc.). + * This impacts the memory size required by a CRC driver. + * Consequently, ADI_CRC_MEMORY_SIZE is environment dependent. + */ +#if defined(__ICCARM__) +/** + * The amount of application supplied memory required to operate a DMA driven CRC device + * using a CRC driver built in IAR environment. + */ +#define ADI_CRC_MEMORY_SIZE (32u) +#else +/** + * The amount of application supplied memory required to operate a DMA driven CRC device + * using a CRC driver built in a generic built environment. + * Note: Create a new macro definition for your targetted development environment + * if this generic value was not appropriate in your development environment. + */ +#define ADI_CRC_MEMORY_SIZE (32u) +#endif + +/** Check that a DMA channel can be used with CRC */ +#define ADI_CRC_VALID_DMA_CHANNEL(DMA_CHANNEL_ID) ((SIP0_CHANn<=(DMA_CHANNEL_ID)) && ((DMA_CHANNEL_ID)<=SIP7_CHANn)) + +/** + * CRC events used in CRC callback functions to report + * - the completion of a DMA driven CRC request + * - errors detected when executing a DMA driven CRC request + */ +typedef enum __ADI_CRC_EVENT +{ + /*! DMA driven CRC peripheral has completed processing a request */ + ADI_CRC_EVENT_BUFFER_PROCESSED = ADI_DMA_EVENT_BUFFER_PROCESSED, + + /*! DMA driven CRC peripheral has encountered a problem when processing a request */ + ADI_CRC_EVENT_ERROR +} ADI_CRC_EVENT; + +#endif /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + +/** + * A device handle used in all API functions to identify a CRC device. + * This handle is obtained when opening a CRC driver using adi_crc_Open. + * It stops being valid after closing the CRC driver using adi_crc_Close. + */ +typedef struct __ADI_CRC_DEVICE* ADI_CRC_HANDLE; + +/** + * CRC driver return codes + */ +typedef enum +{ + ADI_CRC_SUCCESS = 0, /*!< 0x00 - Generic success */ + ADI_CRC_FAILURE, /*!< 0x01 - Generic failure */ + ADI_CRC_IN_USE, /*!< 0x02 - Supplied CRC device number is already open and in use */ + ADI_CRC_INSUFFICIENT_MEMORY, /*!< 0x03 - Supplied memory is insufficient to operate the CRC device */ + ADI_CRC_FN_NOT_SUPPORTED, /*!< 0x04 - Function not supported */ + ADI_CRC_FN_NOT_PERMITTED, /*!< 0x05 - Function not permitted at current stage */ + ADI_CRC_BAD_HANDLE, /*!< 0x06 - Bad CRC device handle (can be caused by a CRC device not opened)*/ + ADI_CRC_BAD_DEVICE_NUMBER, /*!< 0x07 - There is no CRC device identified by this number */ + ADI_CRC_INVALID_DMA_CHANNEL, /*!< 0x08 - Invalid DMA channel assigned to a CRC driver */ + ADI_CRC_INVALID_PARAMETER, /*!< 0x09 - Invalid parameter used in a CRC function */ +} ADI_CRC_RESULT; + +/*======= P U B L I C P R O T O T Y P E S ========*/ +/* (globally-scoped functions) */ + +/* Opens a CRC device instance */ +ADI_CRC_RESULT adi_crc_Open( + uint32_t DeviceNum, + void *pMemory, + uint32_t MemorySize, + ADI_CRC_HANDLE *phDevice); + +/* Closes a CRC device instance */ +ADI_CRC_RESULT adi_crc_Close( + ADI_CRC_HANDLE const hDevice); + +/* Registers or unregisters a callback, used by the CRC interrupt handler or with DMA driven operations, with the CRC device */ +ADI_CRC_RESULT adi_crc_RegisterCallback( + ADI_CRC_HANDLE const hDevice, + ADI_CALLBACK pfCallback, + void *const pCBParam); + +/* Sets the 32-bit polynomial for CRC operations */ +ADI_CRC_RESULT adi_crc_SetPolynomialVal( + ADI_CRC_HANDLE const hDevice, + uint32_t PolynomialVal); + +/* Submits data buffer for CRC operation */ +ADI_CRC_RESULT adi_crc_Compute( + ADI_CRC_HANDLE const hDevice, + void *pCrcBuf, + uint32_t NumBytes, + uint32_t NumBits); + +/* Gets the current CRC peripheral status */ +ADI_CRC_RESULT adi_crc_IsCrcInProgress( + ADI_CRC_HANDLE const hDevice, + bool *pbCrcInProgress); + +/* Gets the final CRC result computed for a data stream */ +ADI_CRC_RESULT adi_crc_GetFinalCrcVal( + ADI_CRC_HANDLE const hDevice, + uint32_t *pFinalCrcVal); + +/* Gets the current/intermediate CRC result computed for a data stream */ +ADI_CRC_RESULT adi_crc_GetCurrentCrcVal( + ADI_CRC_HANDLE const hDevice, + uint32_t *pCurrentCrcVal); + +ADI_CRC_RESULT adi_crc_SetBitMirroring( + ADI_CRC_HANDLE const hDevice, + const bool bEnable); + +ADI_CRC_RESULT adi_crc_SetByteMirroring( + ADI_CRC_HANDLE const hDevice, + const bool bEnable); + +ADI_CRC_RESULT adi_crc_EnableWordSwap( + ADI_CRC_HANDLE const hDevice, + const bool bEnable); + +ADI_CRC_RESULT adi_crc_SetCrcSeedVal( + ADI_CRC_HANDLE const hDevice, + uint32_t CrcSeedVal); + +ADI_CRC_RESULT adi_crc_SetLSBFirst( + ADI_CRC_HANDLE const hDevice, + const bool bEnable); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* ADI_CRC_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crypto/adi_crypto.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crypto/adi_crypto.h new file mode 100755 index 0000000000..54971c2217 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crypto/adi_crypto.h @@ -0,0 +1,235 @@ +/*! ***************************************************************************** + * @file adi_crypto.h + * @brief Main include file for CRYPTO Device driver definitions + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +/** @addtogroup Crypto_Driver Crypto Driver +* @{ +*/ + +#ifndef ADI_CRYPTO_H +#define ADI_CRYPTO_H + + /*! \cond PRIVATE */ +#include +#include +#include /* for ADI_SEM_SIZE */ +/*! \endcond */ +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! + * \enum ADI_CRYPTO_RESULT + * Crypto API return codes + */ +typedef enum +{ + ADI_CRYPTO_SUCCESS = 0, /*!< No Error, API suceeded. */ + ADI_CRYPTO_ERR_ALREADY_INITIALIZED, /*!< Crypto is already initialized. */ + ADI_CRYPTO_ERR_BAD_BUFFER, /*!< Invalid buffer parameters. */ + ADI_CRYPTO_ERR_BAD_CONFIG, /*!< Invalid device config parameters passed. */ + ADI_CRYPTO_ERR_BAD_DEVICE_NUM, /*!< Invalid device instance number. */ + ADI_CRYPTO_ERR_BAD_DEV_HANDLE, /*!< Invalid device handle passed. */ + ADI_CRYPTO_ERR_COMPUTE_ACTIVE, /*!< Computation underway. */ + ADI_CRYPTO_ERR_DMA_BUS_FAULT, /*!< Runtime DMA bus fault detected. */ + ADI_CRYPTO_ERR_DMA_INVALID_DESCR, /*!< Runtime DMA invalid descriptor detected. */ + ADI_CRYPTO_ERR_DMA_REGISTER, /*!< Error registering DMA error callback function. */ + ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR, /*!< Unknown runtime DMA error detected. */ + ADI_CRYPTO_ERR_INSUFFICIENT_MEM, /*!< Insufficient memory passed to the driver. */ + ADI_CRYPTO_ERR_INVALID_PARAM, /*!< Invalid function parameter. */ + ADI_CRYPTO_ERR_INVALID_STATE, /*!< Operation failed since the device is in an invalid state. */ + ADI_CRYPTO_ERR_SEMAPHORE_FAILED, /*!< Failure in semaphore functions. */ +} ADI_CRYPTO_RESULT; + +/*! + * \enum ADI_CRYPTO_EVENT + * Crypto callback events + */ +typedef enum +{ + /* successful buffer completion events */ + ADI_CRYPTO_EVENT_STATUS_CBC_DONE, /*!< CBC operation is complete. */ + ADI_CRYPTO_EVENT_STATUS_CCM_DONE, /*!< CCM operation is complete. */ + ADI_CRYPTO_EVENT_STATUS_CMAC_DONE, /*!< CMAC operation is complete. */ + ADI_CRYPTO_EVENT_STATUS_CTR_DONE, /*!< CTR operation is complete. */ + ADI_CRYPTO_EVENT_STATUS_ECB_DONE, /*!< ECB operation is complete. */ + ADI_CRYPTO_EVENT_STATUS_HMAC_DONE, /*!< HMAC operation is complete. */ + ADI_CRYPTO_EVENT_STATUS_SHA_DONE, /*!< SHA operation is complete. */ + + /* other events */ + ADI_CRYPTO_EVENT_DMA_BUS_ERROR, /*!< DMA bus error encountered. */ + ADI_CRYPTO_EVENT_DMA_DESCRIPTOR_ERROR, /*!< DMA descriptor error encountered. */ + ADI_CRYPTO_EVENT_DMA_UNKNOWN_ERROR, /*!< DMA unknown error encountered. */ + ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW, /*!< Input overflow error encountered. */ + ADI_CRYPTO_EVENT_STATUS_UNKNOWN, /*!< Unknown error encountered. */ +} ADI_CRYPTO_EVENT; + +/*! The amount of application supplied memory used by the CRYPTO driver to store internal state. */ +#define ADI_CRYPTO_MEMORY_SIZE (88u + ADI_SEM_SIZE) + +/*! A device handle used in all API functions to identify the flash device. */ +typedef struct __ADI_CRYPTO_DEV_DATA_TYPE* ADI_CRYPTO_HANDLE; + +/*! Number of bytes to allocate for SHA256 hash outputs */ +#define ADI_CRYPTO_SHA_HASH_BYTES (256u/8u) + +/*! Computation mode(Encryption/Decryption) for given buffers */ +typedef enum +{ + ADI_CRYPTO_DECODE = (0u << BITP_CRYPT_CFG_ENCR), /*!< Encoding mode is decryption. */ + ADI_CRYPTO_ENCODE = (1u << BITP_CRYPT_CFG_ENCR), /*!< Encoding mode is encryption. */ +} ADI_CRYPTO_CODING_MODE; + +/*! Enum for the AES KEY Length */ +typedef enum +{ + ADI_CRYPTO_AES_KEY_LEN_128_BIT = (0u << BITP_CRYPT_CFG_AESKEYLEN), /*!< KEY length is 128 bits. */ + ADI_CRYPTO_AES_KEY_LEN_256_BIT = (2u << BITP_CRYPT_CFG_AESKEYLEN), /*!< KEY length is 256 bits. */ +} ADI_CRYPTO_AES_KEY_LEN; + +/*! Enable byte swapping for KEY writes */ +typedef enum +{ + ADI_CRYPTO_KEY_LITTLE_ENDIAN = (0u << BITP_CRYPT_CFG_KEY_BYTESWAP), /*!< Do not apply KEY write byte swaps. */ + ADI_CRYPTO_KEY_BIG_ENDIAN = (1u << BITP_CRYPT_CFG_KEY_BYTESWAP), /*!< Apply KEY write byte swaps. */ +} ADI_CRYPTO_KEY_BYTE_SWAP; + +/*! Byte-swap the SHA Input Data */ +typedef enum +{ + ADI_CRYPTO_SHA_LITTLE_ENDIAN = (0u << BITP_CRYPT_CFG_SHA_BYTESWAP), /*!< Do not apply SHA data write byte swaps. */ + ADI_CRYPTO_SHA_BIG_ENDIAN = (1u << BITP_CRYPT_CFG_SHA_BYTESWAP), /*!< Apply SHA data write byte swaps. */ +} ADI_CRYPTO_SHA_BYTE_SWAP; + +/*! Byte-swap the AES Input Data */ +typedef enum +{ + ADI_CRYPTO_AES_LITTLE_ENDIAN = (0u << BITP_CRYPT_CFG_AES_BYTESWAP), /*!< Do not apply AES data write byte swaps. */ + ADI_CRYPTO_AES_BIG_ENDIAN = (1u << BITP_CRYPT_CFG_AES_BYTESWAP), /*!< Apply AES data write byte swaps. */ +} ADI_CRYPTO_AES_BYTE_SWAP; + +/*! + * \enum ADI_CRYPTO_CIPHER_MODE + * Enum for the cipher modes. + */ +typedef enum { + ADI_CRYPTO_MODE_CBC = BITM_CRYPT_CFG_CBCEN, /*!< Select CBC cipher mode. */ + ADI_CRYPTO_MODE_CCM = BITM_CRYPT_CFG_CCMEN, /*!< Select CCM cipher mode. */ + ADI_CRYPTO_MODE_CMAC = BITM_CRYPT_CFG_CMACEN, /*!< Select CMAC cipher mode. */ + ADI_CRYPTO_MODE_CTR = BITM_CRYPT_CFG_CTREN, /*!< Select CTR cipher mode. */ + ADI_CRYPTO_MODE_ECB = BITM_CRYPT_CFG_ECBEN, /*!< Select ECB cipher mode. */ + ADI_CRYPTO_MODE_HMAC = BITM_CRYPT_CFG_HMACEN, /*!< Select HMAC cipher mode. */ + ADI_CRYPTO_MODE_SHA = BITM_CRYPT_CFG_SHA256EN, /*!< Select SHA cipher mode. */ +} ADI_CRYPTO_CIPHER_MODE; + +/*! superset user Crypto transaction structure (different elements used for different modes) */ +typedef struct +{ + ADI_CRYPTO_CIPHER_MODE eCipherMode; /*!< Cipher mode to use */ + ADI_CRYPTO_CODING_MODE eCodingMode; /*!< Coding Mode (Encryption or Decryption) */ + + ADI_CRYPTO_KEY_BYTE_SWAP eKeyByteSwap; /*!< KEY endianness */ + ADI_CRYPTO_SHA_BYTE_SWAP eShaByteSwap; /*!< SHA endianness */ + ADI_CRYPTO_AES_BYTE_SWAP eAesByteSwap; /*!< AES endianness */ + + uint8_t *pKey; /*!< Pointer to the KEY data: pre-formatted as a byte array, according to eAesKeyLen. */ + ADI_CRYPTO_AES_KEY_LEN eAesKeyLen; /*!< The length of the AES KEY */ + + uint32_t *pAuthData; /*!< CCM mode: pointer to user prefix buffer */ + uint32_t numAuthBytes; /*!< Length of the prefix buffer in bytes (should be a multiple of 16 bytes) */ + + uint32_t *pInputData; /*!< Pointer to user input data buffer */ + uint32_t numInputBytes; /*!< Length of the data buffer in bytes (should be a multiple of 16bytes) */ + + uint32_t *pOutputData; /*!< Pointer to user output buffer */ + uint32_t numOutputBytes; /*!< Length of the output buffer in bytes (should be a multiple of 16bytes) */ + + uint8_t *pNonceIV; /*!< Pointer to user 16-byte array containing one of three values, depending on cipher mode:\n + - CTR mode = 108-bit NONCE\n + - CCM mode = 112-bit NONCE\n + - CBC mode = 128-bit IV (Initialization Vector)\n\n + NONCE and IV assume little endian format, for example: CTR NONCE packing is:\n + - NONCE[0] -> 7:0\n + - NONCE[1] -> 15:8\n + - ...\n + - NONCE[13] -> 103:96\n + - NONCE[14](Bits 3:0) -> 107:104\n + */ + uint32_t CounterInit; /*!< CTR/CCM mode: Counter Initialization Value (CTR=20-bit, CCM=16-bit) */ + uint32_t numValidBytes; /*!< CCM mode: Number of valid bytes in the last (padding) block (1-16) */ + uint32_t numShaBits; /*!< SHA mode: Number of bits in the SHA payload, which may be odd-sized */ +} ADI_CRYPTO_TRANSACTION; + + +/*================ PUBLIC API ==================*/ + + +ADI_CRYPTO_RESULT adi_crypto_Open (uint32_t const nDeviceNum, void * const pMemory, uint32_t const nMemorySize, ADI_CRYPTO_HANDLE * const phDevice); +ADI_CRYPTO_RESULT adi_crypto_Close (ADI_CRYPTO_HANDLE const hDevice); +ADI_CRYPTO_RESULT adi_crypto_RegisterCallback (ADI_CRYPTO_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void * const pCBParam); +ADI_CRYPTO_RESULT adi_crypto_Enable (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable); + +ADI_CRYPTO_RESULT adi_crypto_SubmitBuffer (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION * const pBuffer); +ADI_CRYPTO_RESULT adi_crypto_GetBuffer (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION ** const ppBuffer); +ADI_CRYPTO_RESULT adi_crypto_IsBufferAvailable (ADI_CRYPTO_HANDLE const hDevice, bool * const pbAvailable); + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +ADI_CRYPTO_RESULT adi_crypto_EnableDmaMode (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable); +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* include guard */ + +/* +** EOF +*/ + +/*@}*/ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/dma/adi_dma.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/dma/adi_dma.h new file mode 100755 index 0000000000..63c3bb2cf9 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/dma/adi_dma.h @@ -0,0 +1,274 @@ +/*! + ***************************************************************************** + * @file: adi_dma.h + * @brief: DMA Device Definitions for ADuCxxx + *----------------------------------------------------------------------------- + * +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ADI_DMA_MODE_PING_PONG +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/*! \addtogroup DMA_Driver DMA Driver + * @{ + * @brief DMA Driver + * @details This driver is intended to be used only by the device drivers and not by the application. + * @note The device drivers must include drivers/dma/adi_dma.h to use this driver + */ + +#ifndef ADI_DMA__H__ +#define ADI_DMA__H__ + +#include + + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*============= D E F I N E S =============*/ +/*! Amount of memory(In bytes) required by the DMA manager for managing the operation + * This memory is completely owned by the driver till the end of the operation. + */ + +/*============= D A T A T Y P E S =============*/ + + +/*! + * Dma Data Increments + */ +typedef enum +{ + ADI_DMA_INCR_1_BYTE = 0x00u, /*!< Byte increment */ + ADI_DMA_INCR_2_BYTE = 0x01u, /*!< Half word increment */ + ADI_DMA_INCR_4_BYTE = 0x02u, /*!< Word increment */ + ADI_DMA_INCR_NONE = 0x03u, /*!< No increment */ + + ADI_DMA_DECR_1_BYTE = 0x10u, /*!< Byte decrement */ + ADI_DMA_DECR_2_BYTE = 0x11u, /*!< Half word decrement */ + ADI_DMA_DECR_4_BYTE = 0x12u /*!< Word decrement */ + +} ADI_DMA_INCR_TYPE; + +/*! + * DMA Callback Events + */ +typedef enum +{ + ADI_DMA_EVENT_BUFFER_PROCESSED, /*!< Buffer processed event */ + ADI_DMA_EVENT_ERR_BUS, /*!< Bus Error Occurred Event */ + ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR /*!< Invalid Descriptor Event */ +} ADI_DMA_EVENT; + + +/*! + * Dma Data Widths + */ +typedef enum +{ + ADI_DMA_WIDTH_1_BYTE = 0x0, /*!< 8-bit */ + ADI_DMA_WIDTH_2_BYTE = 0x1, /*!< 16-bit */ + ADI_DMA_WIDTH_4_BYTE = 0x2 /*!< 32-bit */ +} ADI_DMA_WIDTH_TYPE; + + +/*! + * Dma Rearbitration Intervals (chunk size between bus arbitrations) + */ +typedef enum +{ + ADI_DMA_RPOWER_1 = 0, /*!< Rearbitrate after 1 transfer */ + ADI_DMA_RPOWER_2, /*!< Rearbitrate after 2 transfers */ + ADI_DMA_RPOWER_4, /*!< Rearbitrate after 4 transfers */ + ADI_DMA_RPOWER_8, /*!< Rearbitrate after 8 transfers */ + ADI_DMA_RPOWER_16, /*!< Rearbitrate after 16 transfers */ + ADI_DMA_RPOWER_32, /*!< Rearbitrate after 32 transfers */ + ADI_DMA_RPOWER_64, /*!< Rearbitrate after 64 transfers */ + ADI_DMA_RPOWER_128, /*!< Rearbitrate after 128 transfers */ + ADI_DMA_RPOWER_256, /*!< Rearbitrate after 256 transfers */ + ADI_DMA_RPOWER_512, /*!< Rearbitrate after 512 transfers */ + ADI_DMA_RPOWER_1024 /*!< Rearbitrate after 1024 transfers */ +} ADI_DMA_RPOWER; + + +/*! + * Dma Transfer Modes + */ +typedef enum +{ + ADI_DMA_MODE_BASIC, /*!< Basic mode */ + ADI_DMA_MODE_AUTO, /*!< Auto request mode */ + ADI_DMA_MODE_PING_PONG, /*!< Ping pong mode */ + ADI_DMA_MODE_MSG, /*!< Memory Scatter gather mode (not valid as no Memory DMA support) */ + ADI_DMA_MODE_PSG /*!< Peripheral Scatter mode */ +} ADI_DMA_MODE; + + +/*! + * Dma Channel Priority Settings (only HIGH or DEFAULT priority supported) + */ +typedef enum +{ + ADI_DMA_PRIORITY_DEFAULT = 0, /*!< Use DEFAULT channel priority */ + ADI_DMA_PRIORITY_HIGH /*!< Elevate channel to HIGH priority */ +} ADI_DMA_PRIORITY; + + +/*! + * Result Event Type + */ +typedef enum { + ADI_DMA_SUCCESS, /*!< Successfully Completed */ + ADI_DMA_ERR_NOT_INITIALIZED, /*!< DMA not initialized */ + ADI_DMA_ERR_INVALID_PARAMETER, /*!< Input parameter to the function is invalid */ +} ADI_DMA_RESULT; + +/*! \cond PRIVATE*/ +/*! + * \enum DMA_CHANn_TypeDef + * DMA Channel Assignments + */ +typedef enum +{ + SPI2_TX_CHANn = 0, /*!< SPI2 Transmit DMA channel */ + SPI2_RX_CHANn = 1, /*!< SPI2 Receive DMA channel */ + SPORT0A_CHANn = 2, /*!< SPORT0-A DMA channel */ + SPORT0B_CHANn = 3, /*!< SPORT0-B DMA channel */ + SPI0_TX_CHANn = 4, /*!< SPI0 Transmit DMA channel */ + SPI0_RX_CHANn = 5, /*!< SPI0 Receive DMA channel */ + SPI1_TX_CHANn = 6, /*!< SPI1 Transmit DMA channel */ + SPI1_RX_CHANn = 7, /*!< SPI1 Receive DMA channel */ + UART0_TX_CHANn = 8, /*!< UART0 Transmit DMA channel */ + UART0_RX_CHANn = 9, /*!< UART0 Receive DMA channel */ + I2CS_TX_CHANn = 10, /*!< I2C Slave Transmit DMA channel */ + I2CS_RX_CHANn = 11, /*!< I2C Slave Receive DMA channel */ + I2CM_CHANn = 12, /*!< I2C Master DMA channel */ + AES0_IN_CHANn = 13, /*!< AES0-IN DMA channel */ + AES0_OUT_CHANn = 14, /*!< AES0-OUT DMA channel */ + FLASH_CHANn = 15, /*!< FLASH DMA channel */ + SIP0_CHANn = 16, /*!< SIP-0 DMA channel */ + SIP1_CHANn = 17, /*!< SIP-1 DMA channel */ + SIP2_CHANn = 18, /*!< SIP-2 DMA channel */ + SIP3_CHANn = 19, /*!< SIP-3 DMA channel */ + SIP4_CHANn = 20, /*!< SIP-4 DMA channel */ + SIP5_CHANn = 21, /*!< SIP-5 DMA channel */ + SIP6_CHANn = 22, /*!< SIP-6 DMA channel */ + SIP7_CHANn = 23, /*!< SIP-7 DMA channel */ + ADC0_CHANn = 24, /*!< ADC0 DMA channel */ + UART1_TX_CHANn = 25, /*!< UART1 Transmit DMA channel */ + UART1_RX_CHANn = 26, /*!< UART1 Receive DMA channel */ + NUM_DMA_CHANNELSn = 27 /*!< Total Number of DMA channels */ +} DMA_CHANn_TypeDef; /** typedef name for fixed DMA channel assignments */ +/*! \endcond */ + +/*! + * \struct ADI_DCC_TypeDef + * DMA Channel Control MMR Access Template + */ +typedef struct +{ + __IO uint32_t DMASRCEND; /*!< Source End Pointer */ + __IO uint32_t DMADSTEND; /*!< Destination End Pointer */ + __IO uint32_t DMACDC; /*!< Channel Data Configuration */ + uint32_t RESERVED; /*!< Address gap filler */ +} ADI_DCC_TypeDef; + + +/*! \cond PRIVATE */ +/* Bit Position for DMA Descriptor Control */ +#define DMA_BITP_CTL_DST_INC (30u) +#define DMA_BITP_CTL_SRC_INC (26u) +#define DMA_BITP_CTL_SRC_SIZE (24u) +#define DMA_BITP_CTL_R_POWER (14u) +#define DMA_BITP_CTL_N_MINUS_1 (4u) +#define DMA_BITP_CTL_CYCLE_CTL (0u) + +/* Bit Mask for DMA Descriptor Control */ +#define DMA_BITM_CTL_DST_INC ((0x00000003u) << DMA_BITP_CTL_DST_INC) +#define DMA_BITM_CTL_SRC_INC ((0x00000003u) << DMA_BITP_CTL_SRC_INC) +#define DMA_BITM_CTL_SRC_SIZE ((0x00000003u) << DMA_BITP_CTL_SRC_SIZE) +#define DMA_BITM_CTL_R_POWER ((0x0000000Fu) << DMA_BITP_CTL_R_POWER) +#define DMA_BITM_CTL_N_MINUS_1 ((0x000003FFu) << DMA_BITP_CTL_N_MINUS_1) +#define DMA_BITM_CTL_CYCLE_CTL ((0x00000007u) << DMA_BITP_CTL_CYCLE_CTL) + +/* Enum for the DMA Descriptor Cycle Control */ +#define DMA_ENUM_CTL_CYCLE_CTL_INVALID (0u) +#define DMA_ENUM_CTL_CYCLE_CTL_BASIC (1u) +#define DMA_ENUM_CTL_CYCLE_CTL_AUTO_REQ (2u) +#define DMA_ENUM_CTL_CYCLE_CTL_PING_PONG (3u) +#define DMA_ENUM_CTL_CYCLE_CTL_MSG_PRI (4u) +#define DMA_ENUM_CTL_CYCLE_CTL_MSG_ALT (5u) +#define DMA_ENUM_CTL_CYCLE_CTL_PSG_PRI (6u) +#define DMA_ENUM_CTL_CYCLE_CTL_PSG_ALT (7u) + + +#define DMA_BITM_INCR_TYPE_DECR (0x10u) + +#define DMA_BITM_OCTL_SRC_DECR (0x01u) +#define DMA_BITM_OCTL_DST_DECR (0x02u) + +#define DMA_BITM_OCTL_SRC_INCR (0x04u) +#define DMA_BITM_OCTL_DST_INCR (0x08u) + +#define DMA_TRANSFER_LIMIT (1024u) /*!< Maximum number of transfers handled by the DMA in one request */ + +/* pointer to the primary CCD array */ +extern ADI_DCC_TypeDef* const pPrimaryCCD; +/* pointer to the alternate CCD array */ +extern ADI_DCC_TypeDef* const pAlternateCCD; +/*! \endcond */ +/*========== DMA API DECLARATIONS ==========*/ + +extern void adi_dma_Init(void); + +extern ADI_DMA_RESULT adi_dma_RegisterCallback ( + DMA_CHANn_TypeDef const eChannelID, + ADI_CALLBACK const pfCallback, + void* const pCBParam + ); + +#ifdef __cplusplus +} +#endif + +#endif /* include guard */ + +/* +** EOF +*/ + +/**@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/flash/adi_flash.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/flash/adi_flash.h new file mode 100755 index 0000000000..c72524e3e4 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/flash/adi_flash.h @@ -0,0 +1,185 @@ +/*! + ***************************************************************************** + @file: adi_flash.h + @brief: Flash device driver definitions + @date: $Date: 2016-07-05 00:49:46 -0400 (Tue, 05 Jul 2016) $ + ----------------------------------------------------------------------------- +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/*! @addtogroup Flash_Driver Flash Driver + * @{ + */ + +#ifndef ADI_FLASH_H +#define ADI_FLASH_H + + /*! \cond PRIVATE */ +#include +#include +#include /* for ADI_SEM_SIZE */ +/*! \endcond */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! + * \enum ADI_FEE_RESULT + * Flash Controller return codes. + */ + typedef enum { + ADI_FEE_SUCCESS = 0, /*!< The function completed successfully. */ + ADI_FEE_ERR_ALIGNMENT, /*!< The flash write source data pointer is misaligned. */ + ADI_FEE_ERR_ALREADY_INITIALIZED, /*!< The flash device driver is already initialized. */ + ADI_FEE_ERR_BAD_DEVICE_NUM, /*!< Device number passed is invalid. */ + ADI_FEE_ERR_BUFFER_ERR, /*!< An error occurred while processing a write buffer. */ + ADI_FEE_ERR_DEVICE_BUSY, /*!< The device is busy. */ + ADI_FEE_ERR_DMA_BUS_FAULT, /*!< Runtime DMA bus fault detected. */ + ADI_FEE_ERR_DMA_INVALID_DESCR, /*!< Runtime DMA invalid descriptor detected. */ + ADI_FEE_ERR_DMA_REGISTER, /*!< Error registering DMA error callback function. */ + ADI_FEE_ERR_DMA_UNKNOWN_ERROR, /*!< Unknown runtime DMA error detected. */ + ADI_FEE_ERR_HW_ERROR_DETECTED, /*!< An FEE hardware error occurred (pHwErrors param). */ + ADI_FEE_ERR_INSUFFICIENT_MEM, /*!< The memory passed is undersized. */ + ADI_FEE_ERR_INVALID_HANDLE, /*!< Device Handle is invalid. */ + ADI_FEE_ERR_INVALID_PARAM, /*!< A function parameter is invalid. */ + ADI_FEE_ERR_NO_DATA_TO_TRANSFER, /*!< No transfer data detected. */ + ADI_FEE_ERR_TRANSFER_IN_PROGRESS, /*!< Operation already in progress. */ + ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY, /*!< Unmatched read/write vs. submit/get API call. */ + ADI_FEE_ERR_SEMAPHORE_FAILED, /*!< An semaphore operation failed. */ + } ADI_FEE_RESULT; + + +/*! A device handle used in all API functions to identify the flash device. */ +typedef struct __ADI_FEE_DEV_DATA_TYPE* ADI_FEE_HANDLE; + + +/*! Applications use the "ADI_FEE_MEMORY_SIZE" macro to allocate + required flash driver memory. This memory (and size) are passed + to the flash driver during the "adi_fee_Open()" driver initialization + call. This memory is used to store internal flash driver state. +*/ +#define ADI_FEE_MEMORY_SIZE (44u + ADI_SEM_SIZE) + + +/*! + * \enum ADI_FEE_CALLBACK_EVENT + * Enum for the callback events. + */ +typedef enum { + ADI_FEE_CALLBACK_EVENT_BUFFER_PROCESSED, /*!< Buffer processed successfully event. */ + ADI_FEE_CALLBACK_EVENT_DEVICE_ERROR, /*!< Device error(s) detected during command. */ +} ADI_FEE_CALLBACK_EVENT; + +/*! + * \enum ADI_FEE_ECC_EVENT_TYPE + * Enum for the Error-Correction-Code event type. + */ +typedef enum { + ADI_FEE_ECC_EVENT_TYPE_ERROR, /*!< ECC Error Event. */ + ADI_FEE_ECC_EVENT_TYPE_CORRECT /*!< ECC correction event. */ +} ADI_FEE_ECC_EVENT_TYPE; + +/*! + * \enum ADI_FEE_ECC_RESPONSE + * Error-Correction-Code configuration codes. + */ +typedef enum { + ADI_FEE_ECC_RESPONSE_NONE = 0x0, /*!< No Response. */ + ADI_FEE_ECC_RESPONSE_BUS_ERROR = 0x1, /*!< Generate a Bus Error. */ + ADI_FEE_ECC_RESPONSE_IRQ = 0x2 /*!< Generate an IRQ. */ +} ADI_FEE_ECC_RESPONSE; + + +/*! + * \struct ADI_FEE_TRANSACTION + * Flash write data transaction block. + */ +typedef struct { + uint32_t *pWriteAddr; /*!< Pointer to flash-space (destination) write location. */ + uint32_t *pWriteData; /*!< Pointer to user-space (source) write Data. */ + uint32_t nSize; /*!< Write data size (in bytes). */ + bool bUseDma; /*!< DMA flag controlling use of DMA or not. */ +} ADI_FEE_TRANSACTION; + + +/*================ E X T E R N A L S ==================*/ +/* Flash Controller API */ + +ADI_FEE_RESULT adi_fee_Open (uint32_t const nDeviceNum, void* const pMemory, uint32_t const nMemorySize, ADI_FEE_HANDLE* const phDevice); +ADI_FEE_RESULT adi_fee_Close (ADI_FEE_HANDLE const hDevice); +ADI_FEE_RESULT adi_fee_RegisterCallback (ADI_FEE_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void* const pCBParam); + +ADI_FEE_RESULT adi_fee_PageErase (ADI_FEE_HANDLE const hDevice, uint32_t const nPageNumStart, uint32_t const nPageNumEnd, uint32_t* const pHwErrors); +ADI_FEE_RESULT adi_fee_MassErase (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors); + +ADI_FEE_RESULT adi_fee_Write (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction, uint32_t* const pHwErrors); +ADI_FEE_RESULT adi_fee_SubmitBuffer (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction); + +ADI_FEE_RESULT adi_fee_IsBufferAvailable (ADI_FEE_HANDLE const hDevice, bool* const pbCompletionState); +ADI_FEE_RESULT adi_fee_GetBuffer (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors); + +ADI_FEE_RESULT adi_fee_GetPageNumber (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnPageNum); +ADI_FEE_RESULT adi_fee_GetBlockNumber (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnBlockNum); + +ADI_FEE_RESULT adi_fee_VerifySignature (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, uint32_t const nEndPage, uint32_t* const pSigResult, uint32_t* const pHwErrors); +ADI_FEE_RESULT adi_fee_WriteProtectBlock (ADI_FEE_HANDLE const hDevice, uint32_t const nBlockNum); + +ADI_FEE_RESULT adi_fee_Sleep (ADI_FEE_HANDLE const hDevice, bool const bSleep); +ADI_FEE_RESULT adi_fee_Abort (ADI_FEE_HANDLE const hDevice); +ADI_FEE_RESULT adi_fee_GetAbortAddr (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress); + +ADI_FEE_RESULT adi_fee_ConfigECC (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, bool const bInfoECCEnable); +ADI_FEE_RESULT adi_fee_EnableECC (ADI_FEE_HANDLE const hDevice, bool const bEnable); +ADI_FEE_RESULT adi_fee_ConfigECCEvents (ADI_FEE_HANDLE const hDevice, ADI_FEE_ECC_EVENT_TYPE const eEvent, ADI_FEE_ECC_RESPONSE const eResponse); +ADI_FEE_RESULT adi_fee_GetECCErrAddr (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress); +ADI_FEE_RESULT adi_fee_GetECCCorrections (ADI_FEE_HANDLE const hDevice, uint32_t* const pnNumCorrections); + +#ifdef __cplusplus +} +#endif + +#endif /* include guard */ + +/* +** EOF +*/ + +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_data_transfer.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_data_transfer.h new file mode 100755 index 0000000000..89ab88d841 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_data_transfer.h @@ -0,0 +1,127 @@ +/*! **************************************************************************** + * @file adi_data_transfer.h + * @brief General data transfer types for drivers + * @details General data transfer types for drivers + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef ADI_DATA_TRANSFER_H +#define ADI_DATA_TRANSFER_H + +/*============= I N C L U D E S =============*/ + +#include /* defines types such as uint32_t*/ +#include /* needed for SEM_VAR_DECLR declaration */ + +/*! \cond PRIVATE */ +/** @addtogroup Data_Transfer Common Data Transfer Structures +* @{ +*/ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*============== D E F I N E S ===============*/ + +#define ADI_DT_BUFNUM (2u) /*!< Number of buffers available for data transfers in each communication channel */ + +/*! + ******************************************************************************* + * \struct ADI_DT_BUFF_INFO + * Structure for managing buffers submitted to drivers. + ******************************************************************************/ +struct _ADI_DT_BUFF_INFO; + +/*! + ******************************************************************************* + * Structure for managing buffers submitted to drivers. + ******************************************************************************/ +typedef struct _ADI_DT_BUFF_INFO +{ + void * pStartAddress; /*!< Address of buffer passed down a driver. */ + uint32_t nCount; /*!< Size of buffer in bytes. */ + uint32_t nIndex; /*!< Position of first byte to be transmitted. */ + bool bInUse; /*!< Buffer in use flag. */ + bool bDMA; /*!< Transaction is using the DMA flag. */ + struct _ADI_DT_BUFF_INFO * pNextBuffer; /*!< Pointer to the next buffer in the list. */ +} ADI_DT_BUFF_INFO; + +/*! + ******************************************************************************* + * Enumeration of different data transfer modes supported by drivers. + ******************************************************************************/ +typedef enum _ADI_DT_MODE +{ + ADI_DT_MODE_NONE, /*!< Mode of data transfer is not selected. */ + ADI_DT_MODE_BLOCKING, /*!< Only calls to adi_xxx_Read or adi_xxx_Write are allowed for transferring data. */ + ADI_DT_MODE_NONBLOCKING /*!< Only calls to adi_xxx_SubmitBuffer are allowed for transferring data. */ +} ADI_DT_MODE; + +typedef void * ADI_DEVICE_HANDLE; /*!< Generic device handle */ + +/*! + ******************************************************************************* + * Structure for managing pool of buffers submitted to drivers. + ******************************************************************************/ +typedef struct +{ + ADI_DT_BUFF_INFO BufInfo[ADI_DT_BUFNUM]; /*!< Ping Pong Buffers. */ + ADI_DT_BUFF_INFO * pFreeBuffer; /*!< Pointer to free buffer. (Next buffer to submit). */ + ADI_DT_BUFF_INFO * pFillBuffer; /*!< Pointer to the next buffer to be filled. (Needed for the case + where many buffers are "submitted" before a "get" is called.) */ + ADI_DT_BUFF_INFO * pActiveBuffer; /*!< Pointer to active buffer. (Next buffer waiting for completion.)*/ + ADI_DT_MODE eDataTranferMode; /*!< Data transfer mode (blocking or non-blockig). */ + + SEM_VAR_DECLR +} ADI_DT_CHANNEL; + + +/*============= P U B L I C F U N C T I O N S =============*/ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +/*! \endcond */ + +#endif /* ADI_DATA_TRANSFER_H */ +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_drivers_general.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_drivers_general.h new file mode 100755 index 0000000000..0540cea56e --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_drivers_general.h @@ -0,0 +1,98 @@ +/*! + ***************************************************************************** + * @file: adi_drivers_general.h + * @brief: Macros and types used in multiple drivers + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ +#ifndef ADI_DRIVERS_GENERAL__H +#define ADI_DRIVERS_GENERAL__H + + +/* Macros related to alignment in the different toolchains supported */ + +/* + * These macros are designed to be used as follows: + * ADI_ALIGNED_PRAGMA() + * ADI_ALIGNED_ATTRIBUTE() + */ + +#if defined ( __ICCARM__ ) +/* +* IAR MISRA C 2004 error suppressions. +* +* +* Pm120 (rule 19.10): In the definition of a function-like macro each parameter +* shall be enclosed in parenthesis. +* This is not possible in attributes and pragmas +* Pm154 (rule 19.13): The # and ## preprocessor operators shall not be used. +* We need to do this to abstract the macros for the +* different toolchains +*/ +#pragma diag_suppress=Pm120,Pm154 +#endif + +#define PRAGMA(x) _Pragma(#x) +#define ATTRIBUTE(x) __attribute__((x)) + +#if defined (__GNUC__) + /* Gcc uses attributes */ + #define ADI_ALIGNED_PRAGMA(num) + #define ADI_ALIGNED_ATTRIBUTE(num) ATTRIBUTE(aligned(num)) + #define ADI_UNUSED_ATTRIBUTE ATTRIBUTE(unused) +#elif defined ( __ICCARM__ ) + /* IAR uses a pragma */ + #define ADI_ALIGNED_ATTRIBUTE(num) + #define ADI_ALIGNED_PRAGMA(num) PRAGMA(data_alignment=num) + #define ADI_UNUSED_ATTRIBUTE +#elif defined (__CC_ARM) + /* Keil uses a decorator which is placed in the same position as pragmas */ + #define ADI_ALIGNED_ATTRIBUTE(num) + #define ADI_ALIGNED_PRAGMA(num) __align(##num) + #define ADI_UNUSED_ATTRIBUTE ATTRIBUTE(unused) +#else +#error "Toolchain not supported" +#endif + + +#if defined ( __ICCARM__ ) +#pragma diag_default=Pm120,Pm154 +#endif +#endif /* ADI_DRIVERS_GENERAL__H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/gpio/adi_gpio.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/gpio/adi_gpio.h new file mode 100755 index 0000000000..ad0673a2b5 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/gpio/adi_gpio.h @@ -0,0 +1,174 @@ +/* + ***************************************************************************** + @file: adi_gpio.h + @brief: GPIO definitions and API + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_GPIO_H +#define ADI_GPIO_H + +#include +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions. + * + * Pm008 (rule 2.4): sections of code should not be 'commented out'. + * Allow code example in doxygen comment. + * Pm011 (rule 6.3): The basic types of char, int, long, float cannot be used. + * bool is used in the APIs as it is not affending the rule. Disabling this as IAR treats it as an error. + */ +#pragma diag_suppress=Pm008,Pm011 +#endif /* __ICCARM__ */ + +/*! \addtogroup GPIO_Driver GPIO Driver + * @{ + */ + +#ifdef __ICCARM__ +#pragma diag_default=Pm008 +#endif /* __ICCARM__ */ + +/* C++ linkage */ +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! Amount of memory(in bytes) required by the GPIO device driver for its operation. + * This memory is completely owned by the driver till the end of the operation. + */ +#define ADI_GPIO_MEMORY_SIZE (16u) + +/* typedefs for 16-bit Ports */ +typedef uint16_t ADI_GPIO_DATA; /*!< pin data reg type */ + + +/*! GPIO API function return codes */ +typedef enum +{ + ADI_GPIO_SUCCESS = 0, /*!< No error detected. */ + ADI_GPIO_FAILURE, /*!< The API call failed. */ + ADI_GPIO_ALREADY_INITIALIZED, /*!< GPIO device has already been initialized. */ + ADI_GPIO_NOT_INITIALIZED, /*!< GPIO device has not yet been initialized. */ + ADI_GPIO_NULL_PARAMETER, /*!< The given pointer is pointing to NULL. */ + ADI_GPIO_INVALID_MEMORY_SIZE, /*!< The given memory is not sufficient to operate the driver. */ + ADI_GPIO_INVALID_PINS, /*!< Invalid pin combination. */ + ADI_GPIO_INVALID_INTERRUPT, /*!< Invalid interrupt number. */ + ADI_GPIO_INVALID_TRIGGER, /*!< Invalid trigger condition. */ +} ADI_GPIO_RESULT; + + +/*! GPIO trigger condition enumerations */ +typedef enum { + ADI_GPIO_IRQ_RISING_EDGE =(0x0), /*!< Trigger an interrupt on a rising edge. */ + ADI_GPIO_IRQ_FALLING_EDGE =(0x1), /*!< Trigger an interrupt on a falling edge. */ + ADI_GPIO_IRQ_EITHER_EDGE =(0x2), /*!< Trigger an interrupt on either edge. */ + ADI_GPIO_IRQ_HIGH_LEVEL =(0x3), /*!< Trigger an interrupt on a high level. */ + ADI_GPIO_IRQ_LOW_LEVEL =(0x4) /*!< Trigger an interrupt on a low level. */ +} ADI_GPIO_IRQ_TRIGGER_CONDITION; + +/*! GPIO IRQ enumeration */ +typedef enum { + ADI_GPIO_INTA_IRQ = SYS_GPIO_INTA_IRQn, /*!< GPIO Group Interrupt A. */ + ADI_GPIO_INTB_IRQ = SYS_GPIO_INTB_IRQn, /*!< GPIO Group Interrupt B. */ +} ADI_GPIO_IRQ; + + +/*! GPIO port enumerations */ +typedef enum { + ADI_GPIO_PORT0, /*!< Port 0 */ + ADI_GPIO_PORT1, /*!< Port 1 */ + ADI_GPIO_PORT2, /*!< Port 2 */ + ADI_GPIO_PORT3, /*!< Port 3 */ + ADI_GPIO_NUM_PORTS /*!< maximum number of ports */ +} ADI_GPIO_PORT; + +/* 16-bit port pin defs */ +#define ADI_GPIO_PIN_0 ((ADI_GPIO_DATA)(0x0001)) /*!< Pin 0 */ +#define ADI_GPIO_PIN_1 ((ADI_GPIO_DATA)(0x0002)) /*!< Pin 1 */ +#define ADI_GPIO_PIN_2 ((ADI_GPIO_DATA)(0x0004)) /*!< Pin 2 */ +#define ADI_GPIO_PIN_3 ((ADI_GPIO_DATA)(0x0008)) /*!< Pin 3 */ +#define ADI_GPIO_PIN_4 ((ADI_GPIO_DATA)(0x0010)) /*!< Pin 4 */ +#define ADI_GPIO_PIN_5 ((ADI_GPIO_DATA)(0x0020)) /*!< Pin 5 */ +#define ADI_GPIO_PIN_6 ((ADI_GPIO_DATA)(0x0040)) /*!< Pin 6 */ +#define ADI_GPIO_PIN_7 ((ADI_GPIO_DATA)(0x0080)) /*!< Pin 7 */ +#define ADI_GPIO_PIN_8 ((ADI_GPIO_DATA)(0x0100)) /*!< Pin 8 */ +#define ADI_GPIO_PIN_9 ((ADI_GPIO_DATA)(0x0200)) /*!< Pin 9 */ +#define ADI_GPIO_PIN_10 ((ADI_GPIO_DATA)(0x0400)) /*!< Pin 10 */ +#define ADI_GPIO_PIN_11 ((ADI_GPIO_DATA)(0x0800)) /*!< Pin 11 */ +#define ADI_GPIO_PIN_12 ((ADI_GPIO_DATA)(0x1000)) /*!< Pin 12 */ +#define ADI_GPIO_PIN_13 ((ADI_GPIO_DATA)(0x2000)) /*!< Pin 13 */ +#define ADI_GPIO_PIN_14 ((ADI_GPIO_DATA)(0x4000)) /*!< Pin 14 */ +#define ADI_GPIO_PIN_15 ((ADI_GPIO_DATA)(0x8000)) /*!< Pin 15 */ + +/* GPIO port pins availability mask */ +#define ADI_GPIO_PORT0_PIN_AVL (0xFFFFu) /*!< Port 0 pin mask (16 pins)*/ +#define ADI_GPIO_PORT1_PIN_AVL (0xFFFFu) /*!< Port 1 pin mask (16 pins)*/ +#define ADI_GPIO_PORT2_PIN_AVL (0xFFFFu) /*!< Port 2 pin mask (16 pins)*/ +#define ADI_GPIO_PORT3_PIN_AVL (0x000Fu) /*!< Port 2 pin mask (4 pins) */ + + +/* GPIO API functions */ +ADI_GPIO_RESULT adi_gpio_Init (void* const pMemory, uint32_t const MemorySize); +ADI_GPIO_RESULT adi_gpio_UnInit (void); +ADI_GPIO_RESULT adi_gpio_RegisterCallback (const ADI_GPIO_IRQ eIrq, ADI_CALLBACK const pfCallback, void *const pCBParam ); +ADI_GPIO_RESULT adi_gpio_SetGroupInterruptPins (const ADI_GPIO_PORT Port, const ADI_GPIO_IRQ eIrq, const ADI_GPIO_DATA Pins); +ADI_GPIO_RESULT adi_gpio_SetGroupInterruptPolarity (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins); +ADI_GPIO_RESULT adi_gpio_OutputEnable (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag); +ADI_GPIO_RESULT adi_gpio_InputEnable (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag); +ADI_GPIO_RESULT adi_gpio_PullUpEnable (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag); +ADI_GPIO_RESULT adi_gpio_SetHigh (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins); +ADI_GPIO_RESULT adi_gpio_SetLow (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins); +ADI_GPIO_RESULT adi_gpio_Toggle (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins); +ADI_GPIO_RESULT adi_gpio_SetData (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins); +ADI_GPIO_RESULT adi_gpio_GetData (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, uint16_t* const pValue); + +#if defined (__ICCARM__) +#pragma diag_default=Pm011 +#endif + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* ADI_GPIO_V1_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/i2c/adi_i2c.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/i2c/adi_i2c.h new file mode 100755 index 0000000000..edd398f3f9 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/i2c/adi_i2c.h @@ -0,0 +1,243 @@ +/*! + ***************************************************************************** + @file: adi_i2c.h + @brief: I2C device driver definitions + @details This is the primary header file for the I2C driver, which contains the + API declarations, data and constant definitions used in the APIs. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ + +#ifndef ADI_I2C_H +#define ADI_I2C_H + + /*! \cond PRIVATE */ +#include +#include /* for ADI_SEM_SIZE */ +/*! \endcond */ + + +/** @addtogroup I2C_Driver I2C Driver + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): Types which specify sign and size should be used +* We use bool which is accepted by MISRA but the toolchain does not accept it +* +*/ +#pragma diag_suppress=Pm011 + +#endif + +/*! + ***************************************************************************** + * \enum ADI_I2C_RESULT + * + * I2C Device Error Codes. #ADI_I2C_SUCCESS is always zero + * The return value of all I2C APIs returning #ADI_I2C_RESULT + * should always be tested at the application level for success or failure. + * Specific I2C bus error conditions are returned as elements of + * #ADI_I2C_RESULT. + * + *****************************************************************************/ +typedef enum +{ + ADI_I2C_SUCCESS = 0, /*!< The API call succeeded. */ + ADI_I2C_BAD_BITRATE, /*!< The bit rate is invalid. */ + ADI_I2C_BAD_DEVICE_HANDLE, /*!< The device handle is invalid. */ + ADI_I2C_BAD_DEVICE_NUMBER, /*!< The device number is invalid. */ + ADI_I2C_BAD_SYS_CLOCK, /*!< Unable to obtain system clock rate. */ + ADI_I2C_DEVICE_IN_USE, /*!< The device is in use. */ + ADI_I2C_DEVICE_NOT_OPEN, /*!< The device is not open. */ + ADI_I2C_FAILURE, /*!< Generic API failure code. */ + ADI_I2C_HW_ERROR_DETECTED, /*!< An I2C hardware error occurred. See #ADI_I2C_HW_ERRORS. */ + ADI_I2C_INSUFFICIENT_MEMORY, /*!< The application supplied memory size is insufficient. */ + ADI_I2C_INVALID_PARAMETER, /*!< An invalid parameter is passed to the function. */ + ADI_I2C_INVALID_SLAVE_ADDRESS, /*!< The application supplied slave address is too wide. */ + ADI_I2C_INVALID_SUBMIT_API, /*!< Unmatched read/write vs. submit/get API call. */ + ADI_I2C_SEMAPHORE_FAILED /*!< Semaphore operation failed. */ + +} ADI_I2C_RESULT; + + +/*! + ***************************************************************************** + * \enum ADI_I2C_HW_ERRORS + * + * I2C Device Hardware Error Codes. Contains one or more hardware (I2C protocol) + * errors. Use this enum to decode hardware errors when the main #ADI_I2C_RESULT + * return result value is #ADI_I2C_HW_ERROR_DETECTED. + * + *****************************************************************************/ +typedef enum +{ + ADI_I2C_HW_ERROR_NONE = 0, /*!< No hardware error. */ + ADI_I2C_HW_ERROR_NACK_ADDR = 0x0001, /*!< A no-acknowledgement occurred for the address. */ + ADI_I2C_HW_ERROR_NACK_DATA = 0x0002, /*!< A no-acknowledgement occurred for the data. */ + ADI_I2C_HW_ERROR_ARBITRATION_LOST = 0x0004, /*!< I2C bus arbitration was Lost. */ + ADI_I2C_HW_ERROR_UNEXPECTED_ERROR = 0x0008, /*!< An unexpected error occurred. */ + +} ADI_I2C_HW_ERRORS; + + +/*! A device handle used in all API functions to identify the I2C device. */ +typedef struct __ADI_I2C_DEV_DATA_TYPE* ADI_I2C_HANDLE; + +/*! Use macro "ADI_I2C_MEMORY_SIZE" to know how much memory to + provide the i2c driver during the "adi_i2c_Open()" driver + initialization call. This memory is used to store internal + driver state data. Use map file to verify. +*/ +#define ADI_I2C_MEMORY_SIZE (44u + ADI_SEM_SIZE) + + +/*! + * \struct ADI_I2C_TRANSACTION + ***************************************************************************** + * I2C Device Command/Data Transaction Structure. This is the called-provided + * data structure used by the blocking #adi_i2c_ReadWrite() and non-blocking + * #adi_i2c_SubmitBuffer() calls to describe the caller's transaction parameters, + * consisting of prologue data and size (the addressing phase), transmit/receive + * data pointer and size (the data phase), and various transaction control parameters. + * + * Each transaction may optionally be prefaced with a prologue block, which may + * describe a read/write memory/register address, a slave-specific command, or + * some other slave-specific protocol that may precede the actual read/write + * data. Set the prologue size to zero if no prologue is desired. + * + * Each call to #adi_i2c_ReadWrite or #adi_i2c_SubmitBuffer() must populate the + * following fields of the ADI_I2C_TRANSACTION block: + * + * @par pPrologue + * Byte pointer to an application-supplied prologue byte array. If the value is + * zero, prologue data is ignored. + * + * @par nPrologueSize + * The number of prologue bytes to be transmitted ahead of the data phase. If the + * value is zero, prologue data is ignored. + * + * @par pData + * Byte pointer to the application-supplied data byte array. This buffer is + * either the source or destination address of the data being transmitted or + * received, respectively. + * + * @par nDataSize + * The number of data bytes to be transmitted or received during the data phase. + * If the value is zero, the data phase is ignored. + * + * @par bReadNotWrite + * Direction control for data phase. If "true", data phase is a read (from + * the slave), if "false", data phase is a write (to the slave). Pertains only + * to the data phase. Any prologue data (addressing/command phase) is always + * transmitted (written to the slave) prior to the data phase. + * + * @par bRepeatStart + * Controls suppression of a Stop Condition between the addressing phase and the + * data phase of an I2C transaction. After the prologue (if present), a + * unidirectional data stream (I2C is a half-duplex protocol) is either + * transmitted or received (depending on the transfer direction). Frequently, a + * Repeat-Start Condition (in reality, just the absence of a Stop Condition + * following the prologue/addressing phase) is required between the addressing + * phase (prologue) and the data phase of a transaction to meet slave device + * protocol requirements. The Repeat-Start requirement can be driven by the + * slave device communications protocol, or simply to just prevent any other + * I2C master from rearbitrating the bus between the prologue (addressing) and + * data phases of a so-called "COMBINED FORMAT" (write-followed-by-read). + * When bRepeatStart is set "true", the usual Stop Condition between the addressing + * phase and the data phase is suppressed and the I2C bus controller issues a + * second Start Condition (Repeat-Start) for the data phase. Without + * Repeat-Start (bRepeatStart "false"), the addressing phase ends with a normal + * Stop Condition ahead of the data phase. Repeat-Start conditions are used + * when "turning the bus around" as in writing a read address (for example), + * immediately followed by a data stream from that read address... without + * releasing bus arbitration. + * + *****************************************************************************/ +typedef struct { + uint8_t *pPrologue; /*!< Prologue pointer. */ + uint16_t nPrologueSize; /*!< Prologue byte count. */ + uint8_t *pData; /*!< Data pointer. */ + uint16_t nDataSize; /*!< Data byte count. */ + bool bReadNotWrite; /*!< Read/write flag. */ + bool bRepeatStart; /*!< Repeat start flag. */ +} ADI_I2C_TRANSACTION; + + +/*! Maximum supported bitrate is "FAST" mode (400 kHz). */ +#define ADI_I2C_MAX_RATE (400000u) + +/*************************************************************** + * Eliminable user API that may be optimized out by the linker * + ***************************************************************/ +ADI_I2C_RESULT adi_i2c_Open (uint32_t const DeviceNum, void* const pMemory, uint32_t const MemorySize, ADI_I2C_HANDLE* const phDevice); +ADI_I2C_RESULT adi_i2c_Close (ADI_I2C_HANDLE const hDevice); + +/* blocking calls... */ +ADI_I2C_RESULT adi_i2c_ReadWrite (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction, uint32_t* const pHwErrors); + +/* non-blocking calls... */ +ADI_I2C_RESULT adi_i2c_SubmitBuffer (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction); +ADI_I2C_RESULT adi_i2c_IsBufferAvailable (ADI_I2C_HANDLE const hDevice, bool* const pbCompletionState); +ADI_I2C_RESULT adi_i2c_GetBuffer (ADI_I2C_HANDLE const hDevice, uint32_t* const pHwErrors); + +/* other (blocking) calls... */ +ADI_I2C_RESULT adi_i2c_Reset (ADI_I2C_HANDLE const hDevice); +ADI_I2C_RESULT adi_i2c_SetBitRate (ADI_I2C_HANDLE const hDevice, uint32_t const requestedBitRate32); +ADI_I2C_RESULT adi_i2c_SetSlaveAddress (ADI_I2C_HANDLE const hDevice, uint16_t const SlaveAddress); +ADI_I2C_RESULT adi_i2c_IssueGeneralCall (ADI_I2C_HANDLE const hDevice, uint8_t* const pData, uint8_t const nDataSize, uint32_t* const pHwErrors); + + +#if defined (__ICCARM__) +#pragma diag_default=Pm011 +#endif + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* ADI_I2C_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/pwr/adi_pwr.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/pwr/adi_pwr.h new file mode 100755 index 0000000000..1bb8f41467 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/pwr/adi_pwr.h @@ -0,0 +1,689 @@ +/* + ***************************************************************************** + * @file: adi_pwr.h + * @brief: System clock and power management driver. + *----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +/*! \addtogroup Power_Driver Power Driver + * @{ + */ + +#ifndef ADI_PWR_H +#define ADI_PWR_H + +#include +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions. + * + * Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters. + * IAR compiler supports longer identifiers. + * Pm011 (rule 6.3): The basic types of char, int, long, float cannot be used. + * bool is used in the APIs as it is not affending the rule. Disabling this as IAR treats it as an error. + */ +#pragma diag_suppress=Pm009,Pm011 +#endif /* __ICCARM__ */ + +#ifdef __cplusplus + extern "C" { +#endif + +/*! Enumeration of clock sources for various peripherals. */ +typedef enum { + /*! Source for all peripherals SPI, SPORT, SIP, CRC, AES, SIP interface, I2C, UART, optionally for timers. */ + ADI_CLOCK_PCLK, + /*! Source for Core,Bus etc. */ + ADI_CLOCK_HCLK, + /*! Source for the ADC. */ + ADI_CLOCK_ACLK + +} ADI_CLOCK_ID; + +/*! Enumeration of input clock sources */ +typedef enum { + /*! Clock ID for 16 MHz or 26 MHz external crystal oscillator called HFXTAL. */ + ADI_CLOCK_SOURCE_HFXTAL, + /*! Clock ID 32 kHz external crystal oscillator called LFXTAL. */ + ADI_CLOCK_SOURCE_LFXTAL, + /*! Clock ID for 26 MHz internal oscillator called HFOSC. */ + ADI_CLOCK_SOURCE_HFOSC, + /*! Clock ID 32 kHz a 32 kHz internal oscillator called LFXTAL. */ + ADI_CLOCK_SOURCE_LFOSC, + /*! Clock ID for output clock for System PLL. */ + ADI_CLOCK_SOURCE_SPLL, + /*! Clock ID for external clock from GPIO. */ + ADI_CLOCK_SOURCE_GPIO +} ADI_CLOCK_SOURCE_ID; + + +/*! + * Enumeration of clock sources for each clock multiplexer. + * The processor has the following clock multiplexers. + * - SPLL Mux (System PLL). + * - Reference clock Mux. + * - Root Clock Mux. + */ +typedef enum { + + /*! Input clock for system PLL mux is HFOSC. */ + ADI_CLOCK_MUX_SPLL_HFOSC, + /*! Input clock for system PLL mux is HFXTAL. */ + ADI_CLOCK_MUX_SPLL_HFXTAL, + /*! Input clock for system PLL mux is provided through GPIO. */ + ADI_CLOCK_MUX_SPLL_GPIO, + + /*! Input clock for low frequency clock mux is LFOSC. */ + ADI_CLOCK_MUX_LFCLK_LFOSC, + /*! Input clock for low frequency clock mux is LFXTAL. */ + ADI_CLOCK_MUX_LFCLK_LFXTAL, + + /*! Input clock to the multiplexer which provides reference clock for Flash + and HPBUCK clock is HFOSC. */ + ADI_CLOCK_MUX_REF_HFOSC_CLK, + /*! Reserved. */ + ADI_CLOCK_MUX_REF_RESERVED, + /*! Input clock to the multiplexer which provides reference clock for Flash + and HPBUCK clock is 26 MHz HFXTAL. */ + ADI_CLOCK_MUX_REF_HFXTAL_26MHZ_CLK, + /*! Input clock to the multiplexer which provides reference clock for Flash + and HPBUCK clock is 16 MHz HFXTAL. */ + ADI_CLOCK_MUX_REF_HFXTAL_16MHZ_CLK, + + /*! Input clock to root multiplexer is HFOSC. */ + ADI_CLOCK_MUX_ROOT_HFOSC, + /*! Input clock to root multiplexer is HFXTAL. */ + ADI_CLOCK_MUX_ROOT_HFXTAL, + /*! Input clock to root multiplexer is SPLL. */ + ADI_CLOCK_MUX_ROOT_SPLL, + /*! Input clock to root multiplexer is from GPIO. */ + ADI_CLOCK_MUX_ROOT_GPIO + +} ADI_CLOCK_MUX_ID; + + +/*! + * Enumeration of clock source status. + */ +typedef enum { + /*! Specified clock source is disabled. */ + ADI_CLOCK_SOURCE_DISABLED = 0, + /*! Specified clock source is not stable. */ + ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE, + /*! Specified clock source is enabled and stable. */ + ADI_CLOCK_SOURCE_ENABLED_STABLE, + /*! Invalid clock ID. */ + ADI_CLOCK_SOURCE_ID_NOT_VALID + +} ADI_CLOCK_SOURCE_STATUS; + +/*! Clock output options through GPIO pin. + The GPIO clock output pin can be driven through one of these clocks. +*/ +typedef enum +{ + /*! Root Clock (ROOT_CLK). */ + ADI_CLOCK_OUTPUT_ROOT_CLK, + + /*! Low Frequency Clock (LF_CLK). */ + ADI_CLOCK_OUTPUT_LF_CLK, + + /*! ADC Clock (ACLK). */ + ADI_CLOCK_OUTPUT_ACLK, + + /*! HCLK_BUS. */ + ADI_CLOCK_OUTPUT_HCLK_BUS, + + /*! HCLK_CORE. */ + ADI_CLOCK_OUTPUT_HCLK_CORE, + + /*! Peripheral Clock (PCLK). */ + ADI_CLOCK_OUTPUT_PCLK, + + /*! Reference Clock for Flash controller timer (RCLK). */ + ADI_CLOCK_OUTPUT_RCLK, + + /*! Mux of HFOSC, HFXTAL clock (RHP_CLK). */ + ADI_CLOCK_OUTPUT_RHP_CLK, + + /*! GP Timer 0 clock (GPT0_CLK). */ + ADI_CLOCK_OUTPUT_GPT0_CLK, + + /*! GP Timer 1 clock (GPT1_CLK). */ + ADI_CLOCK_OUTPUT_GPT1_CLK, + + /*! Peripherals operating at HCLK (HCLK_P). */ + ADI_CLOCK_OUTPUT_HCLK_PERIPHERAL, + + /*! PLL Clock out. */ + ADI_CLOCK_OUTPUT_PLL_OUTPUT, + + /*! RTC0 Clock. */ + ADI_CLOCK_OUTPUT_RTC0_CLK, + + /*! HP Buck Clock (HPBUCK_CLK). */ + ADI_CLOCK_OUTPUT_HPBUCK_CLK, + + /*! HP Buck Non overlap clock. */ + ADI_CLOCK_OUTPUT_HPBUCK_NO_OVERLAP_CLK, + + /*! RTC1 generated clock. */ + ADI_CLOCK_OUTPUT_RTC1_CLK + +}ADI_CLOCK_OUTPUT_ID; + + +/*! Enumeration of clock gates using which the clocks can be gated. */ +typedef enum { + /*! Clock Gate for the GP Timer-0. */ + ADI_CLOCK_GATE_GPT0_CLK = 1 << BITP_CLKG_CLK_CTL5_GPTCLK0OFF, + /*! Clock Gate for the GP Timer-1. */ + ADI_CLOCK_GATE_GPT1_CLK = 1 << BITP_CLKG_CLK_CTL5_GPTCLK1OFF, + /*! Clock Gate for the GP Timer-2. */ + ADI_CLOCK_GATE_GPT2_CLK = 1 << BITP_CLKG_CLK_CTL5_GPTCLK2OFF, + /*! Clock Gate for the I2C. */ + ADI_CLOCK_GATE_I2C_CLK = 1 << BITP_CLKG_CLK_CTL5_UCLKI2COFF, + /*! Clock Gate for the GPIO. */ + ADI_CLOCK_GATE_GPIO_CLK = 1 << BITP_CLKG_CLK_CTL5_GPIOCLKOFF, + /*! Clock Gate for the PCLK. */ + ADI_CLOCK_GATE_PCLK = 1 << BITP_CLKG_CLK_CTL5_PERCLKOFF, + /*! Clock Gate for the RGB Timer. */ + ADI_CLOCK_GATE_TMR_RGB_CLK = 1 << BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF + +} ADI_CLOCK_GATE; + +/*! + * Enumeration of HF oscillator clock divide factor. + */ +typedef enum +{ + /*! Divide by 1. */ + ADI_PWR_HFOSC_DIV_BY_1, + /*! Divide by 2. */ + ADI_PWR_HFOSC_DIV_BY_2, + /*! Divide by 4. */ + ADI_PWR_HFOSC_DIV_BY_4, + /*! Divide by 8. */ + ADI_PWR_HFOSC_DIV_BY_8, + /*! Divide by 16. */ + ADI_PWR_HFOSC_DIV_BY_16, + /*! Divide by 32. */ + ADI_PWR_HFOSC_DIV_BY_32 + +} ADI_PWR_HFOSC_DIV; + + /*! + ***************************************************************************** + * Power driver API return codes + *****************************************************************************/ +typedef enum +{ + /*! No error detected. */ + ADI_PWR_SUCCESS = 0, + /*! Generic unknown error occurred. */ + ADI_PWR_FAILURE, + /*! If the given pointer is pointing to NULL. */ + ADI_PWR_NULL_POINTER, + /*! Requested divide value is out of range. */ + ADI_PWR_INVALID_CLOCK_DIVIDER, + /*! Invalid ADI_CLOCK_ID specified. */ + ADI_PWR_INVALID_CLOCK_ID, + /*! PDIV:HDIV ratio must be integral. */ + ADI_PWR_INVALID_CLOCK_RATIO, + /*! Invalid low-power mode requested. */ + ADI_PWR_INVALID_POWER_MODE, + /*! Invalid clock speed. */ + ADI_PWR_INVALID_CLOCK_SPEED, + /*! Specified operation is not allowed. */ + ADI_PWR_OPERATION_NOT_ALLOWED, + /*! Parameter is out of range. */ + ADI_PWR_INVALID_PARAM, + /*! System not initialized, call the API SystemInit. */ + ADI_PWR_SYSTEM_NOT_INITIALIZED + +} ADI_PWR_RESULT; + +/*! + * Enumeration of the power modes supported by the processor. + */ +typedef enum +{ + /*! Core Sleep power-down mode. */ + ADI_PWR_MODE_FLEXI = 0 << BITP_PMG_PWRMOD_MODE, + /*! Fully Active. (piggy-back on bitmode value "1", normally reserved) */ + ADI_PWR_MODE_ACTIVE = 1 << BITP_PMG_PWRMOD_MODE, + /*! Full Hibernate power-down mode. */ + ADI_PWR_MODE_HIBERNATE = 2 << BITP_PMG_PWRMOD_MODE, + /*! System Sleep power-down mode. */ + ADI_PWR_MODE_SHUTDOWN = 3 << BITP_PMG_PWRMOD_MODE + +} ADI_PWR_POWER_MODE; + + +/*! + * Enumeration of power management interrupts. + */ +typedef enum +{ + /*! Interrupt when battery voltage drops below 1.8V.*/ + ADI_PWR_LOW_BATTERY_VOLTAGE_IEN = 1 << BITP_PMG_IEN_VBAT, + /*! Interrupt when VREG under-voltage: below 1V. */ + ADI_PWR_UNDER_VOLATAGE_IEN = 1 << BITP_PMG_IEN_VREGUNDR, + /*! Interrupt when VREG over-voltage: over- 1.32V. */ + ADI_PWR_OVER_VOLATAGE_IEN = 1 << BITP_PMG_IEN_VREGOVR, + /*! Interrupt when battery voltage falls to the specified range.Please see #adi_pwr_SetVoltageRange.*/ + ADI_PWR_BATTERY_VOLTAGE_RANGE_IEN = 1 << BITP_PMG_IEN_IENBAT + +} ADI_PWR_PMG_IRQ; + + +/*! + * Enumeration of system clock module interrupts. + */ +typedef enum +{ + /*! Interrupt for root clock monitor and Clock Fail. */ + ADI_PWR_ROOT_CLOCK_MON_IEN = 1 << BITP_CLKG_OSC_CTL_ROOT_MON_EN, + /*! Interrupt for LFXTAL clock monitor and Clock Fail. */ + ADI_PWR_LFXTAL_CLOCK_MON_IEN = 1 << BITP_CLKG_OSC_CTL_LFX_MON_EN, + /*! Interrupt when LFXTAL clock becomes stable/unstable. */ + ADI_PWR_LFXTAL_STATUS_IEN = 1 << BITP_CLKG_CLK_CTL0_LFXTALIE, + /*! Interrupt when HFXTAL clock becomes stable/unstable. */ + ADI_PWR_HFXTAL_STATUS_IEN = 1 << BITP_CLKG_CLK_CTL0_HFXTALIE, + /*! Interrupt when PLL-LOCK/PLL-UNLOCK. */ + ADI_PWR_PLL_STATUS_IEN = 1 << BITP_CLKG_CLK_CTL3_SPLLIE + +} ADI_PWR_CLOCK_IRQ; + +/** + * Enumeration of the power driver events notified through the callback. + */ +typedef enum +{ + /*! Event for indicating Over voltage VREG > 1.32v. */ + ADI_PWR_EVENT_VREG_OVER_VOLTAGE, + /*! Event for indicating under voltage VREG < 1V. */ + ADI_PWR_EVENT_VREG_UNDER_VOLTAGE, + + /*! Event for indicating battery voltage below 1.8V. */ + ADI_PWR_EVENT_BATTERY_VOLTAGE_LOW, + /*! Event for indicating battery voltage in specified range-1.VBAT range1 (> 2.75v). */ + ADI_PWR_EVENT_BATTERY_VOLTAGE_RANGE_1, + /*! Event for indicating battery voltage in specified range-2.VBAT range2 (2.75v - 2.3v). */ + ADI_PWR_EVENT_BATTERY_VOLTAGE_RANGE_2, + /*! Event for indicating battery voltage in specified range-3.VBAT range3 (2.3v - 1.6v). */ + ADI_PWR_EVENT_BATTERY_VOLTAGE_RANGE_3, + + /*! Event to indicate that LFXTAL failed and hardware automatically switched to LFOSC. */ + ADI_PWR_EVENT_OSC_LFXTAL_AUTO_SWITCH, + /*! Event to indicate the LFXTAL clock is not stable. */ + ADI_PWR_EVENT_OSC_LFXTAL_MON_FAIL, + /*! Event to indicate the Root clock is not stable. */ + ADI_PWR_EVENT_OSC_ROOT_CLOCK_MON_FAIL, + /*! Event to indicate the Root clock failed and hardware automatically switched to HFOSC. */ + ADI_PWR_EVENT_OSC_ROOT_CLOCK_FAIL_AUTO_SWITCH, + + /*! Event to indicate HF crystal stable. */ + ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_OK, + /*! Event to indicate HF crystal is not stable. */ + ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_NO_OK, + /*! Event to indicate LF crystal is stable. */ + ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_OK, + /*! Event to indicate LF crystal is not stable. */ + ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_NO_OK, + /*! Event for indicating PLL is locked. */ + + ADI_PWR_EVENT_PLLC_LOCK, + /*! Event for indicating PLL is unlocked. */ + ADI_PWR_EVENT_PLLC_UNLOCK + +} ADI_PWR_EVENT; + + +/*! + * Enumeration of processor wake up status. +*/ +typedef enum +{ + /*! Interrupt from External Interrupt 0. */ + ADI_PWR_INT_EXT0, + /*! Interrupt from External Interrupt 1. */ + ADI_PWR_INT_EXT1, + /*! Interrupt from External Interrupt 2. */ + ADI_PWR_INT_EXT2, + /*! Interrupt from RTC. */ + ADI_PWR_INT_RTC + +} ADI_PWR_WAKEUP_STATUS; + +/*! + * Enumeration of the battery voltage ranges for voltage monitoring interrupt generation. +*/ +typedef enum +{ + /*! Voltage range is in safe region. */ + ADI_PWR_BAT_VOLTAGE_RANGE_SAFE, + /*! Battery voltage is in the range of 2.2 to 2.75 V. */ + ADI_PWR_VOLTAGE_RANGE_2_2_TO_2_75, + /*! Battery voltage is in the range of 1.6 to 2.2 V. */ + ADI_PWR_VOLTAGE_RANGE_1_6_TO_2_2 +} ADI_PWR_VOLTAGE_RANGE; + +/*! + * Enumeration of LFXTAL Robust Mode Load select. The amount of loading tolerated when + * LFXTAL robust mode is selected, that is when LFXTAL robust mode is enabled. + */ +typedef enum +{ + /*! No Trim, and big resistive loads not tolerated. */ + ADI_PWR_LFXTAL_LOAD_NONE, + /*! 20 MOHM Load mode, greater than 20 MOHM load allowed. */ + ADI_PWR_LFXTAL_LOAD_20MOHM, + /*! 10 MOHM Load mode, greater than 10 MOHM load allowed. */ + ADI_PWR_LFXTAL_LOAD_10MOHM, + /*! 5 MOHM load resistance allowed on both IO pins, the user can scale the current + down if the load is expected to be smaller than 5 MOHM. */ + ADI_PWR_LFXTAL_LOAD_5MOHM + +}ADI_PWR_LFXTAL_LOAD; + +/*! +* Enumeration of HP Buck load modes. The modes can be used to choose the loading capability +* of the HPBUCK. The low load mode and high load mode are based on the loading in the system. +*/ +typedef enum +{ + /*! HPBUCK Low load mode. This mode can be set if the maximum system clock(HCLK) frequency + is 26 MHz. */ + ADI_PWR_HPBUCK_LD_MODE_LOW, + + /*! HPBUCK High load mode. This mode can be set if the system clock(HCLK) frequency is greater + than 26 MHz. */ + ADI_PWR_HPBUCK_LD_MODE_HIGH + +}ADI_PWR_HPBUCK_LD_MODE; + +/* Related clock APIs */ + +/* + * Initialize the dynamic power management service + */ +ADI_PWR_RESULT adi_pwr_Init(void); + +/* + * ================================================================= + * Clock Management related APIs + * ================================================================= +*/ + +/* + * Update the internal clock variable based on current configuration + */ +ADI_PWR_RESULT adi_pwr_UpdateCoreClock(void); + +/* + * Set the external clock frequency. + */ +ADI_PWR_RESULT adi_pwr_SetExtClkFreq( + const uint32_t ExtClkFreq + ); + +/* + * To Configure the root clock muxing + */ +ADI_PWR_RESULT adi_pwr_SetRootClockMux( + const ADI_CLOCK_MUX_ID eClockID + ); + +/* + * To Configure the root clock muxing + */ +ADI_PWR_RESULT adi_pwr_SetPLLClockMux( + const ADI_CLOCK_MUX_ID eClockID + ); + +/* + * To Configure the root clock muxing + */ +ADI_PWR_RESULT adi_pwr_SetLFClockMux( + const ADI_CLOCK_MUX_ID eClockID + ); + + +/* + * To Enable/Disable the LFXTAL robust mode. + */ +ADI_PWR_RESULT adi_pwr_EnableLFXTALRobustMode( + const bool bEnable + ); + +/* + * To configure the LFXTAL robust mode load. + */ +ADI_PWR_RESULT adi_pwr_SetLFXTALRobustModeLoad( + const ADI_PWR_LFXTAL_LOAD eLoad + ); + +/* + * To Enable/Disable the LFXTAL Fail Auto switch. + */ +ADI_PWR_RESULT adi_pwr_EnableLFXTALFailAutoSwitch( + const bool bEnable + ); + +/* + * To enable/disable auto switching of root clock to HFOSC upon detection + * of Root clock failure. + */ +ADI_PWR_RESULT adi_pwr_EnableRootClockFailAutoSwitch( + const bool bEnable + ); + +/* + * To set the HF Oscillator divide factor + */ +ADI_PWR_RESULT adi_pwr_SetHFOscDivFactor( + const ADI_PWR_HFOSC_DIV eDivFactor + ); + +/* + * To set the HF oscillator automatic divide by 1 during wakeup from Flexi mode + */ +ADI_PWR_RESULT adi_pwr_EnableHFOscAutoDivBy1( + const bool bEnable + ); + +/* + * To Configure the reference clock muxing + */ +ADI_PWR_RESULT adi_pwr_SetRefClockMux( + const ADI_CLOCK_MUX_ID eClockID + ); + +/* + * Get external clock frequency. + */ +ADI_PWR_RESULT adi_pwr_GetExtClkFreq( + uint32_t *pExtClock + ); + +/* + * Get current clock frequency. This API can be used to know PCLK, HCLK. + */ +ADI_PWR_RESULT adi_pwr_GetClockFrequency( + const ADI_CLOCK_ID eClockId, + uint32_t *pClock + ); +/* + * To enable/disable the specific clock. + */ +ADI_PWR_RESULT adi_pwr_EnableClock( + const ADI_CLOCK_GATE eClockGate, + const bool bEnable + ); + +/* + * To enable/disable the specific clock source. + */ +ADI_PWR_RESULT adi_pwr_EnableClockSource( + const ADI_CLOCK_SOURCE_ID eClockSource, + const bool bEnable + ); +/* + * To set the specific clock divider. +*/ +ADI_PWR_RESULT adi_pwr_SetClockDivider( + const ADI_CLOCK_ID eClockId, + const uint16_t nDiv + ); +/* + * To Get the clock status. +*/ +ADI_PWR_RESULT adi_pwr_GetClockStatus( + const ADI_CLOCK_SOURCE_ID eClockSource, + ADI_CLOCK_SOURCE_STATUS *peStatus + ); +/* + * To configure the PLL to generate the SPLL +*/ +ADI_PWR_RESULT adi_pwr_SetPll( + uint8_t nDivFactor, + const uint8_t nMulFactor, + const bool bDiv2, + const bool bMul2 + ); + +/* To enable the interrupt for clock monitoring LFXTAL/HFXTAL/PLL.*/ +ADI_PWR_RESULT adi_pwr_EnableClockInterrupt( + const ADI_PWR_CLOCK_IRQ eIrq, + const bool bEnable + ); + +/* Enabling the LFXTAL bypass mode */ +ADI_PWR_RESULT adi_pwr_EnableLFXTALBypass( + const bool bEnable + ); + + +/* Set the clock output through the GPIO */ +ADI_PWR_RESULT adi_pwr_SetGPIOClockOutput( + const ADI_CLOCK_OUTPUT_ID eClockOutput + ); + +/* + * ================================================================= + * Power Management related APIs + * ================================================================= +*/ +/* To enable the interrupt for voltage monitoring.*/ +ADI_PWR_RESULT adi_pwr_EnablePMGInterrupt( + const ADI_PWR_PMG_IRQ eIrq, + const bool bEnable + ); + +/* + * To know which is interrupt caused the processor to wake up from SHUTDOWN mode. + */ +ADI_PWR_RESULT adi_pwr_GetWakeUpStatus( + ADI_PWR_WAKEUP_STATUS *peStatus + ); + +/* + * To select the voltage range of the battery for monitoring. +*/ +ADI_PWR_RESULT adi_pwr_SetVoltageRange( + const ADI_PWR_VOLTAGE_RANGE eRange + ); + +/* + * For entering the low power mode. +*/ +ADI_PWR_RESULT adi_pwr_EnterLowPowerMode( + const ADI_PWR_POWER_MODE PowerMode, + uint32_t volatile * pnInterruptOccurred, + const uint8_t PriorityMask + ); + +/* + * For exiting the low power mode. +*/ +ADI_PWR_RESULT adi_pwr_ExitLowPowerMode( + uint32_t volatile * pnInterruptOccurred + ); + +/* To enable the HPBUCK */ +ADI_PWR_RESULT adi_pwr_EnableHPBuck( + const bool bEnable + ); + + +/* To enable the HPBUCK Low Power mode */ +ADI_PWR_RESULT adi_pwr_EnableHPBuckLowPowerMode( + const bool bEnable + ); + +/* To enable the HPBUCK Load mode */ +ADI_PWR_RESULT adi_pwr_SetHPBuckLoadMode( + const ADI_PWR_HPBUCK_LD_MODE eLoadMode + ); + +/* + * For registering the call back function . +*/ +ADI_PWR_RESULT adi_pwr_RegisterCallback( + const ADI_CALLBACK pfCallback, + void *pcbParam + ); + +#ifdef __cplusplus +} +#endif + +#endif /* ADI_PWR_H */ + + +/*@}*/ + +/* +** EOF +*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rng/adi_rng.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rng/adi_rng.h new file mode 100755 index 0000000000..f5101ef690 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rng/adi_rng.h @@ -0,0 +1,204 @@ +/*! + ***************************************************************************** + @file adi_rng.h + @brief Random Number Generator Driver + ----------------------------------------------------------------------------- +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/*! \addtogroup RNG_Driver RNG Driver + * Random Number Generator Driver + * @{ + */ + +#ifndef ADI_RNG_H +#define ADI_RNG_H + +#include +#include + +#ifndef __ADUCM4x50__ +#error "Unsupported processor" +#endif + +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions. + * + * Pm011 (rule 6.3): The basic types of char, int, long, float cannot be used. + * bool is used in the APIs as it is not affending the rule. Disabling this as IAR treats it as an error. + */ +#pragma diag_suppress=Pm011 +#endif /* __ICCARM__ */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! + * \enum ADI_RNG_RESULT + * Random Number Generator API return codes + */ +typedef enum +{ + ADI_RNG_SUCCESS = 0, /*!< No Error, API suceeded */ + ADI_RNG_UNKNOWN_ERROR, /*!< Unknown error detected */ + ADI_RNG_ALREADY_INITIALIZED, /*!< RNG is already initialized */ + ADI_RNG_INVALID_PARAM, /*!< Invalid function parameter */ + ADI_RNG_BAD_DEV_HANDLE, /*!< Invalid device handle passed */ + ADI_RNG_BAD_DEVICE_NUM, /*!< Invalid device instance */ + ADI_RNG_NOT_INITIALIZED, /*!< RNG not yet initialized */ + ADI_RNG_INVALID_STATE /*!< Device is in an invalid state */ +} ADI_RNG_RESULT; + +/*! + * \enum ADI_RNG_EVENT + * Random Number Generator callback events + */ +typedef enum +{ + ADI_RNG_EVENT_READY, /*!< Random number ready event */ + ADI_RNG_EVENT_STUCK /*!< The ring oscillator got stuck event */ +} ADI_RNG_EVENT; + + +/*! The amount of application supplied memory required by the RNG driver */ +#define ADI_RNG_MEMORY_SIZE (12u) + + +/*! RNG Device handle typedef */ +typedef void* ADI_RNG_HANDLE; + +/*================ E X T E R N A L S ==================*/ + +/* + * RNG API + */ + +/* Open a random number generator device */ +extern ADI_RNG_RESULT adi_rng_Open( + uint32_t const nDeviceNum, + void* const pMemory, + uint32_t const MemorySize, + ADI_RNG_HANDLE* const phDevice + ); + +/* Close the RNG Device */ +extern ADI_RNG_RESULT adi_rng_Close(ADI_RNG_HANDLE hDevice); + +/* Enable/Disable the device */ +extern ADI_RNG_RESULT adi_rng_Enable ( + ADI_RNG_HANDLE const hDevice, + bool const bFlag + ); +/* Enable/Disable buffering */ +extern ADI_RNG_RESULT adi_rng_EnableBuffering ( + ADI_RNG_HANDLE const hDevice, + bool const bFlag + ); + +/* Set the sample length */ +extern ADI_RNG_RESULT adi_rng_SetSampleLen ( + ADI_RNG_HANDLE const hDevice, + uint16_t const nLenPrescaler, + uint16_t const nLenReload + ); + +/* Get whether the random number is ready */ +extern ADI_RNG_RESULT adi_rng_GetRdyStatus ( + ADI_RNG_HANDLE const hDevice, + bool* const pbFlag + ); + +/* Get whether the ring oscillator output is stuck or not */ +extern ADI_RNG_RESULT adi_rng_GetStuckStatus ( + ADI_RNG_HANDLE const hDevice, + bool* const pbFlag + ); + +/* Get the random number */ +extern ADI_RNG_RESULT adi_rng_GetRngData ( + ADI_RNG_HANDLE const hDevice, + uint32_t* const pRegData + ); + +/* Get the oscillator count */ +extern ADI_RNG_RESULT adi_rng_GetOscCount ( + ADI_RNG_HANDLE const hDevice, + uint32_t* const pOscCount + ); + +/* Get the oscillator count difference value */ +extern ADI_RNG_RESULT adi_rng_GetOscDiff ( + ADI_RNG_HANDLE const hDevice, + uint32_t const nIndex, + uint8_t* const pOscDiff + ); + +/* Register a callback */ +extern ADI_RNG_RESULT adi_rng_RegisterCallback ( + ADI_RNG_HANDLE hDevice, + ADI_CALLBACK cbFunc, + void *pCBParam + ); + +/* Retrieve the current RNG sample length prescale and reload value configured in the device. */ +extern ADI_RNG_RESULT adi_rng_GetSampleLen ( + ADI_RNG_HANDLE const hDevice, + uint16_t* const pLenPrescaler, + uint16_t* const pLenReload + ); + +#ifdef __cplusplus +} +#endif + +#ifdef __ICCARM__ +#pragma diag_default=Pm011 +#endif /* __ICCARM__ */ +#endif /* include guard */ + +/* +** EOF +*/ + +/*@}*/ +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rtc/adi_rtc.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rtc/adi_rtc.h new file mode 100755 index 0000000000..739bc47dc0 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rtc/adi_rtc.h @@ -0,0 +1,521 @@ +/*! + ***************************************************************************** + @file adi_rtc.h + @brief Primary include file for Real Time Clock Services. + @version $Revision: 29004 $ + @date $Date: 2014-12-06 10:37:26 -0500 (Sat, 06 Dec 2014) $ + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_RTC_H__ +#define ADI_RTC_H__ +#include "adi_processor.h" + +#include +#include +#include + +/*! \addtogroup RTC_Driver RTC Driver + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + + +/*! Amount of memory(In bytes) required by the RTC device driver for managing the operation. + * This memory is completely owned by the driver till the end of the operation. + */ +#define ADI_RTC_MEMORY_SIZE (24u) + +/*! Emergency flush command to gatweay register */ +#define ADI_RTC_GATEWAY_FLUSH 0xa2c5 + +/*! A device handle used in all API functions to identify the RTC device. */ +typedef void* ADI_RTC_HANDLE; + +/*! Interrupt bit position-1*/ +#define ADI_RTC_INTERRUPT_OFFSET 16 + +/*! Interrupt bit position-2*/ +#define ADI_RTC_INTERRUPT_OFFSET_IO_CAPTURE 21 + +/*! + * RTC API return codes + */ +typedef enum +{ + /*! No Error, API succeeded */ + ADI_RTC_SUCCESS, + /*! Generic failure */ + ADI_RTC_FAILURE, + /*! RTC is in failsafe mode and not reliable */ + ADI_RTC_CLOCK_FAILSAFE, + /*! RTC is already initialized */ + ADI_RTC_IN_USE, + /*! Invalid device handle passed */ + ADI_RTC_INVALID_HANDLE, + /*! Asking to initialize an unknown instance */ + ADI_RTC_INVALID_INSTANCE, + /*! Parameter is out of range */ + ADI_RTC_INVALID_OPTION, + /*! Specified operation not allowed */ + ADI_RTC_OPERATION_NOT_ALLOWED, + /*! One of the parameters is invalid */ + ADI_RTC_INVALID_PARAM, + /*! Input/SensorStrobe channel is invalid for the specified operation */ + ADI_RTC_INVALID_CHANNEL + +} ADI_RTC_RESULT; + + +/*! + * RTC Interrupt Enable Bits. + */ + + +typedef uint32_t ADI_RTC_INT_TYPE; + +#define ADI_RTC_ALARM_INT 0x00000001u /*!< Alarm interrupt enable bit */ +#define ADI_RTC_MOD60ALM_INT 0x00000002u /*!< modulo 60 Alarm interrupt enable */ +#define ADI_RTC_ISO_DONE_INT 0x00000004u /*!< Power isolation done interrupt enable */ +#define ADI_RTC_WRITE_PENDERR_INT 0x00000008u /*!< Write pend error interrupt enable */ +#define ADI_RTC_WRITE_SYNC_INT 0x00000010u /*!< Write sync interrupt enable */ +#define ADI_RTC_WRITE_PEND_INT 0x00000020u /*!< Write pend interrupt enable */ +#define ADI_RTC_COUNT_INT 0x00000040u /*!< RTC count interrupt source enable */ +#define ADI_RTC_PSI_INT 0x00000080u /*!< Precaled Module 1 interrupt */ +#define ADI_RTC_TRIM_INT 0x00000100u /*!< Enable for the RTC trim interrupt source */ +#define ADI_RTC_COUNT_ROLLOVER_INT 0x00000200u /*!< Enable for the RTC count roll-over interrupt source */ +#define ADI_RTC_MOD60_ROLLOVER_INT 0x00000400u /*!< Enable for the RTC modulo-60 count roll-over interrupt source */ +#define ADI_RTC_SENSOR_STROBE_CH1_INT 0x00000800u /*!< Enable interrupt for sensor strobe channel -1*/ +#define ADI_RTC_SENSOR_STROBE_CH2_INT 0x00001000u /*!< Enable interrupt for sensor strobe channel -2*/ +#define ADI_RTC_SENSOR_STROBE_CH3_INT 0x00002000u /*!< Enable interrupt for sensor strobe channel -3*/ +#define ADI_RTC_SENSOR_STROBE_CH4_INT 0x00004000u /*!< Enable interrupt for sensor strobe channel -4*/ +#define ADI_RTC_INPUT_CAPTURE_CH0_INT 0x00008000u /*!< Enable interrupt for input capture channel -0*/ +#define ADI_RTC_INPUT_CAPTURE_CH2_INT 0x00010000u /*!< Enable interrupt for input capture channel -2*/ +#define ADI_RTC_INPUT_CAPTURE_CH3_INT 0x00020000u /*!< Enable interrupt for input capture channel -3*/ +#define ADI_RTC_INPUT_CAPTURE_CH4_INT 0x00040000u /*!< Enable interrupt for input capture channel -4*/ +#define ADI_RTC_LFXTL_FAILURE_INT 0x00080000u /*!< Interrupt for LFXTL failure. LFXTL failure interrupt is mapped to RTC1 interrupt.*/ +#define ADI_RTC_RTCSS4_FE_INT 0x00100000u /*!< Enable interrupt for Sensor Strobe channel 3*/ +#define ADI_RTC_RTCSS3_FE_INT 0x00200000u /*!< Enable interrupt for Sensor Strobe channel 3*/ +#define ADI_RTC_RTCSS2_FE_INT 0x00400000u /*!< Enable interrupt for Sensor Strobe channel 2*/ +#define ADI_RTC_RTCSS1_FE_INT 0x00800000u /*!< Enable interrupt for Sensor Strobe channel 2*/ +#define ADI_RTC_RTCSS4MSKEN 0x01000000u /*!< Enable interrupt for Sensor Strobe channel 4 Mask */ +#define ADI_RTC_RTCSS3MSKEN 0x02000000u /*!< Enable interrupt for Sensor Strobe channel 3 Mask */ +#define ADI_RTC_RTCSS2MSKEN 0x04000000u /*!< Enable interrupt for Sensor Strobe channel 2 Mask */ +#define ADI_RTC_RTCSS1MSKEN 0x08000000u /*!< Enable interrupt for Sensor Strobe channel 1 Mask */ +#define ADI_RTC_CR5OCS_SS3SMPMTCHIRQEN 0x10000000u /*!< Sample activity Interrupt enable for RTC Sensor Strobe Channel 3 */ +#define ADI_RTC_CR5OCS_SS2SMPMTCHIRQEN 0x20000000u /*!< Sample activity Interrupt enable for RTC Sensor Strobe Channel 2 */ +#define ADI_RTC_CR5OCS_SS1SMPMTCHIRQEN 0x40000000u /*!< Sample activity Interrupt enable for RTC Sensor Strobe Channel 1. */ + + +#define ADI_RTC_NUM_INTERRUPTS 31 /*!< Number of RTC interrupts. */ + + +/*! + * RTC Posted Write Status Bits. + */ +typedef enum +{ + /*! Posted write control register-0 status bit */ + ADI_RTC_WRITE_STATUS_CONTROL0 = 1 << BITP_RTC_SR0_WSYNCCR0, + /*! Posted write status0 register status bit */ + ADI_RTC_WRITE_STATUS_STATUS0 = 1 << BITP_RTC_SR0_WSYNCSR0, + /*! Posted write count0 register status bit */ + ADI_RTC_WRITE_STATUS_COUNT0 = 1 << BITP_RTC_SR0_WSYNCCNT0, + /*! Posted write count1 register status bit */ + ADI_RTC_WRITE_STATUS_COUNT1 = 1 << BITP_RTC_SR0_WSYNCCNT1, + /*! Posted write alarm0 register status bit */ + ADI_RTC_WRITE_STATUS_ALARM0 = 1 << BITP_RTC_SR0_WSYNCALM0, + /*! Posted write alarm1 register status bit */ + ADI_RTC_WRITE_STATUS_ALARM1 = 1 << BITP_RTC_SR0_WSYNCALM1, + /*! Posted write trim register status bit */ + ADI_RTC_WRITE_STATUS_TRIM = 1 << BITP_RTC_SR0_WSYNCTRM +} ADI_RTC_WRITE_STATUS; + + +/*! + * RTC Trim intervals. + */ +typedef enum +{ + /*! Trim interval is 2^2 seconds */ + ADI_RTC_TRIM_INTERVAL_2 = (2 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^3 seconds */ + ADI_RTC_TRIM_INTERVAL_3 = (3 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^4 seconds */ + ADI_RTC_TRIM_INTERVAL_4 = (4 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^5 seconds */ + ADI_RTC_TRIM_INTERVAL_5 = (5 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^6 seconds */ + ADI_RTC_TRIM_INTERVAL_6 = (6 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^7 seconds */ + ADI_RTC_TRIM_INTERVAL_7 = (7 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^8 seconds */ + ADI_RTC_TRIM_INTERVAL_8 = (8 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^9 seconds */ + ADI_RTC_TRIM_INTERVAL_9 = (9 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^10 seconds */ + ADI_RTC_TRIM_INTERVAL_10 = (10 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^11 seconds */ + ADI_RTC_TRIM_INTERVAL_11 = (11 << BITP_RTC_TRM_IVL2EXPMIN | 0x1 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^12 seconds */ + ADI_RTC_TRIM_INTERVAL_12 = (12 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^13 seconds */ + ADI_RTC_TRIM_INTERVAL_13 = (13 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^14 seconds */ + ADI_RTC_TRIM_INTERVAL_14 = (14 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^15 seconds */ + ADI_RTC_TRIM_INTERVAL_15 = (14 << BITP_RTC_TRM_IVL2EXPMIN | 0x1 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^16 seconds */ + ADI_RTC_TRIM_INTERVAL_16 = (14 << BITP_RTC_TRM_IVL2EXPMIN | 0x2 << BITP_RTC_TRM_IVL ), + /*! Trim interval is 2^17 seconds */ + ADI_RTC_TRIM_INTERVAL_17 = (14 << BITP_RTC_TRM_IVL2EXPMIN | 0x3 << BITP_RTC_TRM_IVL) + +} ADI_RTC_TRIM_INTERVAL; + +/*! + * RTC input capture channels. + */ +typedef enum +{ + /*! Input capture channel-0 */ + ADI_RTC_INPUT_CHANNEL_0 = 1 << BITP_RTC_CR2IC_IC0EN, + /*! Input capture channel-2 */ + ADI_RTC_INPUT_CHANNEL_2 = 1 << BITP_RTC_CR2IC_IC2EN, + /*! Input capture channel-3 */ + ADI_RTC_INPUT_CHANNEL_3 = 1 << BITP_RTC_CR2IC_IC3EN, + /*! Input capture channel-4 */ + ADI_RTC_INPUT_CHANNEL_4 = 1 << BITP_RTC_CR2IC_IC4EN + +}ADI_RTC_INPUT_CHANNEL; + +/*! + * RTC Sensor Strobe channels. + */ +typedef enum +{ + /*! Sensor Strobe channel-1 */ + ADI_RTC_SS_CHANNEL_1 = 1 << BITP_RTC_CR3SS_SS1EN, + /*! Sensor Strobe channel-2 */ + ADI_RTC_SS_CHANNEL_2 = 1 << BITP_RTC_CR3SS_SS2EN, + /*! Sensor Strobe channel-3 */ + ADI_RTC_SS_CHANNEL_3 = 1 << BITP_RTC_CR3SS_SS3EN, + /*! Sensor Strobe channel-4 */ + ADI_RTC_SS_CHANNEL_4 = 1 << BITP_RTC_CR3SS_SS4EN, + +}ADI_RTC_SS_CHANNEL; + +/*! + * RTC Trim polarity. + */ +typedef enum +{ + /*! Trim value is added every trim interval */ + ADI_RTC_TRIM_ADD = (1 << BITP_RTC_TRM_ADD), + /*! Trim value is subtracted every trim interval */ + ADI_RTC_TRIM_SUB = (0 << BITP_RTC_TRM_ADD), +} ADI_RTC_TRIM_POLARITY; + +/*! + * RTC Trim values. + */ +typedef enum +{ + /*! Trim value is +/- 0 */ + ADI_RTC_TRIM_0 = (0 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 1 */ + ADI_RTC_TRIM_1 = (1 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 2 */ + ADI_RTC_TRIM_2 = (2 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 3 */ + ADI_RTC_TRIM_3 = (3 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 4 */ + ADI_RTC_TRIM_4 = (4 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 5 */ + ADI_RTC_TRIM_5 = (5 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 6 */ + ADI_RTC_TRIM_6 = (6 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 7 */ + ADI_RTC_TRIM_7 = (7 << BITP_RTC_TRM_VALUE) +} ADI_RTC_TRIM_VALUE; + +/*! + * RTC control register set. + */ +typedef enum +{ + /*! Specify the RTC-Control register-0 */ + ADI_RTC_CONTROL_REGISTER_0, + /*! Specify the RTC-Control register-1 */ + ADI_RTC_CONTROL_REGISTER_1 +} ADI_RTC_CONTROL_REGISTER; + +/*================ E X T E R N A L S ==================*/ + +/* + */ + +/*************************************/ +/* RTC API */ +/*************************************/ +ADI_RTC_RESULT adi_rtc_Open( + uint32_t DeviceNumber, + void *pDeviceMemory, + uint32_t MemorySize, + ADI_RTC_HANDLE *phDevice + ); + +ADI_RTC_RESULT adi_rtc_Close( + ADI_RTC_HANDLE const hDevice + ); + +/*************************************/ +/* Enable APIs for RTC Device */ +/*************************************/ + +ADI_RTC_RESULT adi_rtc_EnableAlarm( + ADI_RTC_HANDLE const hDevice, + bool bEnable + ); + +ADI_RTC_RESULT adi_rtc_EnableMod60Alarm( + ADI_RTC_HANDLE const hDevice, + bool bEnable + ); + +ADI_RTC_RESULT adi_rtc_Enable( + ADI_RTC_HANDLE const hDevice, + bool bEnable + ); + +ADI_RTC_RESULT adi_rtc_EnableInterrupts( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_INT_TYPE Interrupts, + bool bEnable + ); + +ADI_RTC_RESULT adi_rtc_EnableTrim( + ADI_RTC_HANDLE const hDevice, + bool bEnable + ); + +ADI_RTC_RESULT adi_rtc_EnableAutoReload( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + bool bEnable); + +ADI_RTC_RESULT adi_rtc_EnableSensorStrobeOutput ( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + bool bEnable); + +ADI_RTC_RESULT adi_rtc_EnableInputCapture ( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_INPUT_CHANNEL eInpChannel, + bool bEnable); + +ADI_RTC_RESULT adi_rtc_EnableSensorStrobeChannelMask( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + bool bEnable); + +ADI_RTC_RESULT adi_rtc_EnableOverwriteSnapshot ( + ADI_RTC_HANDLE const hDevice, + bool bEnable); + +/*************************************/ +/* Set APIs for RTC Device */ +/*************************************/ + + +ADI_RTC_RESULT adi_rtc_SetMod60AlarmPeriod( + ADI_RTC_HANDLE const hDevice, + uint8_t nPeriod + ); + +ADI_RTC_RESULT adi_rtc_SetAlarm( + ADI_RTC_HANDLE const hDevice, + uint32_t nAlarm + ); + +ADI_RTC_RESULT adi_rtc_SetAlarmEx( + ADI_RTC_HANDLE const hDevice, + float fAlarm + ); + + +ADI_RTC_RESULT adi_rtc_SetControlRegister( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_CONTROL_REGISTER eRegister, + uint32_t Control + ); + +ADI_RTC_RESULT adi_rtc_SetCount( + ADI_RTC_HANDLE const hDevice, + uint32_t nCount + ); + +ADI_RTC_RESULT adi_rtc_SetGateway( + ADI_RTC_HANDLE const hDevice, + uint16_t Command + ); + + +ADI_RTC_RESULT adi_rtc_SetPreScale( + ADI_RTC_HANDLE const hDevice, + uint8_t nPreScale + ); + +ADI_RTC_RESULT adi_rtc_SetTrim( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_TRIM_INTERVAL eInterval, + ADI_RTC_TRIM_VALUE eTrimValue, + ADI_RTC_TRIM_POLARITY eOperation + ); + +ADI_RTC_RESULT adi_rtc_SetSensorStrobeChannelMask( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + uint8_t nMask); + +ADI_RTC_RESULT adi_rtc_SetAutoReloadValue( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + uint16_t nValue); + +ADI_RTC_RESULT adi_rtc_SetInputCapturePolarity ( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_INPUT_CHANNEL eInpChannel, + bool bEnable); + +ADI_RTC_RESULT adi_rtc_SetSensorStrobeValue( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + uint16_t nValue); + +/*************************************/ +/* Get APIs for RTC Device */ +/*************************************/ + +ADI_RTC_RESULT adi_rtc_GetAlarm ( + ADI_RTC_HANDLE hDevice, + uint32_t *pAlarm + ); + +ADI_RTC_RESULT adi_rtc_GetAlarmEx ( + ADI_RTC_HANDLE hDevice, + float *pAlarm); + +ADI_RTC_RESULT adi_rtc_GetControl ( + ADI_RTC_HANDLE hDevice, + ADI_RTC_CONTROL_REGISTER eRegister , + uint32_t *pControl); + +ADI_RTC_RESULT adi_rtc_GetTrim( + ADI_RTC_HANDLE hDevice, + ADI_RTC_TRIM_VALUE *peTrim + ); + +ADI_RTC_RESULT adi_rtc_GetCount( + ADI_RTC_HANDLE const hDevice, + uint32_t *pCount + ); + +ADI_RTC_RESULT adi_rtc_GetCountEx( + ADI_RTC_HANDLE const hDevice, + float *pfCount + ); + +ADI_RTC_RESULT adi_rtc_GetSnapShot( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_INPUT_CHANNEL eChannel, + uint32_t *pValue, + uint16_t *pFraction); + +ADI_RTC_RESULT adi_rtc_GetInputCaptureValue( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_INPUT_CHANNEL eChannel, + uint16_t *pValue); + +ADI_RTC_RESULT adi_rtc_GetWritePendStatus( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_WRITE_STATUS *pPendBits + ); + +ADI_RTC_RESULT adi_rtc_GetWriteSyncStatus( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_WRITE_STATUS *pSyncBits + ); + +ADI_RTC_RESULT adi_rtc_GetSensorStrobeValue( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + uint16_t *pValue); + +ADI_RTC_RESULT adi_rtc_GetCountRegs( + ADI_RTC_HANDLE const hDevice, + uint32_t *pnCount, + uint32_t *pfCount); +/************************************************/ +/* RTC APIs for managing interrupt/sync */ +/***********************************************/ + +ADI_RTC_RESULT adi_rtc_SynchronizeAllWrites( + ADI_RTC_HANDLE const hDevice + ); + +ADI_RTC_RESULT adi_rtc_RegisterCallback( + ADI_RTC_HANDLE const hDevice, + ADI_CALLBACK const pfCallback, + void *const pCBparam + ); + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* ADI_RTC_H__ */ + + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/spi/adi_spi.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/spi/adi_spi.h new file mode 100755 index 0000000000..f3aa1118c2 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/spi/adi_spi.h @@ -0,0 +1,386 @@ +/*! ***************************************************************************** + * @file adi_spi.h + * @brief Main include file for SPI Device driver definitions + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here.ADI_SEM_SIZE + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifndef ADI_SPI_H__ +#define ADI_SPI_H__ + +#include +#include +#include + +/** @addtogroup SPI_Driver SPI Driver + * @{ + */ + + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/*! Amount of memory(In bytes) required by the SPI device driver for managing the operation + * of a SPI controller. The memory is passed to the driver when the driver is opened. + * The memory is completely owned by the driver till the the driver is closed. + * + */ + +#define ADI_SPI_MEMORY_SIZE (40u + ADI_SEM_SIZE) + + +/*! + ***************************************************************************** + * \enum ADI_SPI_RESULT + * + * SPI Device Error Codes. #ADI_SPI_SUCCESS is always zero + * The return value of all SPI APIs returning #ADI_SPI_RESULT + * should always be tested at the application level for success or failure. + * + *****************************************************************************/ +typedef enum +{ + /*! Generic success. */ + ADI_SPI_SUCCESS, + /*! Generic Failure. */ + ADI_SPI_FAILURE, + /*! SPI device is already initialized. */ + ADI_SPI_IN_USE, + /*! Invalid device handle. */ + ADI_SPI_INVALID_HANDLE, + /*! Invalid device ID. */ + ADI_SPI_INVALID_DEVICE_NUM, + /*! DMA configuration failure. */ + ADI_SPI_DMA_ERROR , + /*! NULL data pointer not allowed. */ + ADI_SPI_INVALID_POINTER, + /*! Parameter is out of range. */ + ADI_SPI_INVALID_PARAM, + /*! Unsupported mode of operation. */ + ADI_SPI_UNSUPPORTED_MODE, + /*! Semaphore in error . */ + ADI_SPI_SEMAPHORE_FAILED, + /*! Invalid operation */ + ADI_SPI_INVALID_OPERATION, + /*! Buffer Not submitted */ + ADI_SPI_BUFFER_NOT_SUBMITTED, + /*! Could not obtain the system clock */ + ADI_SPI_BAD_SYS_CLOCK, + /*! Blocking PEND failed */ + ADI_SPI_PEND_FAILED, + /*! DMA callback register failed */ + ADI_SPI_DMA_REG_FAILED, + /*! Hardware error occurred */ + ADI_SPI_HW_ERROR_OCCURRED +} ADI_SPI_RESULT; + +/*! + ***************************************************************************** + * \enum ADI_SPI_HW_ERRORS + * + * Enumeration of events notified in the application provided callback. + * More than one event can be recorded at a time so the enumerator symbols + * have to be assigned values of 2^N + *****************************************************************************/ +typedef enum +{ + /*!< The given buffer is processed. Application can use this event to submit + the next buffer to be transmitted. */ + ADI_SPI_HW_ERROR_NONE = 0u, + /*! Tx-underflow interrupt enable */ + ADI_SPI_HW_ERROR_TX_UNDERFLOW = 1u, + /*! Rx-overflow interrupt enable */ + ADI_SPI_HW_ERROR_RX_OVERFLOW = 2u, + /*! Rx DMA channel bus fault detected */ + ADI_SPI_HW_ERROR_RX_CHAN_DMA_BUS_FAULT = 4u, + /*! Tx DMA channel bus fault detected */ + ADI_SPI_HW_ERROR_TX_CHAN_DMA_BUS_FAULT = 8u, + /*! Rx DMA channel bus fault detected */ + ADI_SPI_HW_ERROR_RX_CHAN_DMA_INVALID_DESCR = 16u, + /*! Tx DMA channel bus fault detected */ + ADI_SPI_HW_ERROR_TX_CHAN_DMA_INVALID_DESCR = 32u, + /*! Rx DMA channel unkown error detected */ + ADI_SPI_HW_ERROR_RX_CHAN_DMA_UNKNOWN_ERROR = 64u, + /*! Tx DMA channel unkown error detected */ + ADI_SPI_HW_ERROR_TX_CHAN_DMA_UNKNOWN_ERROR = 128u + +} ADI_SPI_HW_ERRORS; + +/*! + ***************************************************************************** + * \enum ADI_SPI_CHIP_SELECT + * + * SPI Device Chip Select Enumeration. Allows designation of an external + * SPI slave device chip select pin to be driven by the SPI controller. + * Multiple external slave SPI devices may be present on a shared SPI bus, + * and the chip select pin allows each of them to be assigned dedicated selects. + * Use the #adi_spi_SetChipSelect() API to configure the active chip select. + * Note that SPI0 is an internal channel dedicated to the UHF controller and + * hence, has a dedicated SPI0 chip select pin that is not available externally. + * + *****************************************************************************/ +typedef enum +{ + /*! No Slave Chip Select for SPI. */ + ADI_SPI_CS_NONE = 0, + /*! CS0 Slave Chip Select for SPI. */ + ADI_SPI_CS0 = 1, + /*! CS1 Slave Chip Select for SPI. */ + ADI_SPI_CS1 = 2, + /*! CS2 Slave Chip Select for SPI. */ + ADI_SPI_CS2 = 4, + /*! CS3 Slave Chip Select for SPI. */ + ADI_SPI_CS3 = 8 +} ADI_SPI_CHIP_SELECT; + + +/*! SPI Device instance private data handle typedef. */ +typedef struct __ADI_SPI_DEV_DATA_TYPE* ADI_SPI_HANDLE; +/*! SPI Device instance private data handle typedef. 'const' version */ +typedef const struct __ADI_SPI_DEV_DATA_TYPE* ADI_SPI_CONST_HANDLE; + + +/*! + * \struct ADI_SPI_TRANSCEIVER + ***************************************************************************** + * SPI Device Command/Data Transceiver Structure. Data structure used by + * the #adi_spi_MasterReadWrite(),#adi_spi_MasterSubmitBuffer() + * API to convey all parameters, consisting of + * prologue, transmit and receive data and size, and buffer increment flags. + * DMA and Half-Duplex operation are also specified in this structure as T/F. + * + * Each call to #adi_spi_MasterReadWrite or #adi_spi_MasterSubmitBuffer() must populate the following fields of the + * ADI_SPI_TRANSCEIVER block: + * + * @par TransmitterBytes + * The number of bytes to be transmitted. If the value is zero, data will not be transmitted from the + * buffer pointed by pTransmitter. + * + * @par ReceiverBytes + * The number of bytes to be received. If the value is zero, data will not be stored in the + * buffer pointed by pReceiver. + * + * @par pTransmitter + * Pointer to the application-defined transmit data buffer. This is the data sent out + * over the SPI transmit wire (MOSI for Master-mode, MISO for Slave-mode) during the SPI transaction. + * For SPI DMA mode (which is 16-bit based), the transmit buffer must be 16-bit aligned. + * + * @par pReceiver + * Pointer to the application-defined receive data buffer. This is where the receive data + * will be stored from the SPI receive wire (MISO for Master-mode, MOSI for Slave-mode) + * during the SPI transaction. + * For SPI DMA mode (which is 16-bit based), the receive buffer must be 16-bit aligned. + * + * @par bTxIncrement + * Increment to be done for the transmit buffer after every transaction . The transmit data buffer + * pointer is advanced as each byte is sent. If it is set to zero, the transmit data pointer is stationary. + * A stationary buffer pointer is useful for sending the same data to an external device or if + * the source data is from a fixed memory address. + * + * @par bRxIncrement + * Increment to be done for the receive buffer. The transmit data buffer + * pointer is advanced as each byte is sent. If it is value is set to zero, the receive + * data pointer is stationary. A stationary buffer pointer is useful for monitoring commands + * from an external device or if the receive data is going to a fixed memory address. + * + * @par bDMA + * Indicate whether the transaction is to use DMA (true) or not (false). If using DMA SPI + * transactions are limited to 2048 bytes. If more than 2048 bytes are needed then the application + * must use multiple transactions (DMA ping pong mode is not supported in the driver). + * For SPI DMA mode (which is 16-bit based), TransmitterBytes/ReceiverBytes is rounded up to an + * even number by the SPI driver before submitting to DMA. + * Please align the buffer to 16 bit word boundary since the data transfer is 16bit. + * + * + * @par bRD_CTL + * Indicate whether the transaction should enable RD_CTL (true) or not (false). + * RD_CTL effectively provides half-duplex operation as outlined in the HRM. + + *****************************************************************************/ +typedef struct +{ + /*! Pointer to transmit data. */ + uint8_t* pTransmitter; + /*! Pointer to receive data. */ + uint8_t* pReceiver; + /*! Data size for TX(bytes). */ + uint16_t TransmitterBytes; + /*! Data size for RX(bytes). */ + uint16_t ReceiverBytes; + /*! Transmit pointer increment flag. */ + uint8_t nTxIncrement; + /*! Receive pointer increment flag. */ + uint8_t nRxIncrement; + /*! DMA mode operation */ + bool bDMA; + /*! RD_CTL, half-duplex, operation */ + bool bRD_CTL; + +} ADI_SPI_TRANSCEIVER; + + + +/****************************************************************************** + * SPI Device External API function prototypes + *****************************************************************************/ + +/* Device Initialization and Uninitialization Interfaces */ +ADI_SPI_RESULT adi_spi_Open( + uint32_t nDeviceNum, + void *pDevMemory, + uint32_t nMemorySize, + ADI_SPI_HANDLE* const phDevice + ); + +ADI_SPI_RESULT adi_spi_Close( + ADI_SPI_HANDLE const hDevice + ); + +/****************************************************************** + * Eliminatable functions that may be optimized out by the linker * + *****************************************************************/ + +ADI_SPI_RESULT adi_spi_MasterReadWrite( + ADI_SPI_HANDLE const hDevice, + const ADI_SPI_TRANSCEIVER* const pXfr + ); + + +ADI_SPI_RESULT adi_spi_SetMasterMode( + ADI_SPI_CONST_HANDLE const hDevice, + const bool bFlag + ); + +/* Slave Mode APIs */ +ADI_SPI_RESULT adi_spi_SlaveReadWrite( + ADI_SPI_HANDLE const hDevice, + const ADI_SPI_TRANSCEIVER* const pXfr + ); + +/* Command/Data transceiver API */ +ADI_SPI_RESULT adi_spi_MasterSubmitBuffer( + ADI_SPI_HANDLE const hDevice, + const ADI_SPI_TRANSCEIVER* const pXfr + ); + +ADI_SPI_RESULT adi_spi_SlaveSubmitBuffer( + ADI_SPI_HANDLE const hDevice, + const ADI_SPI_TRANSCEIVER* + const pXfr + ); + +ADI_SPI_RESULT adi_spi_RegisterCallback ( + ADI_SPI_HANDLE const hDevice, + ADI_CALLBACK const pfCallback, + void *const pCBParam + ); + + +/* Turn a non-blocking call into a blocking call. Wait for the transaction to complete */ +ADI_SPI_RESULT adi_spi_GetBuffer( + ADI_SPI_HANDLE const hDevice, + uint32_t * const pHWErrors + ); + +/* Query function for the data transfer completion */ +ADI_SPI_RESULT adi_spi_isBufferAvailable( + ADI_SPI_CONST_HANDLE const hDevice, + bool* const bComplete + ); + + + +ADI_SPI_RESULT adi_spi_SetContinuousMode( + ADI_SPI_CONST_HANDLE const hDevice, + const bool bFlag + ); + + +ADI_SPI_RESULT adi_spi_SetLoopback( + ADI_SPI_CONST_HANDLE const hDevice, + const bool bFlag + ); + +ADI_SPI_RESULT adi_spi_SetIrqmode ( + ADI_SPI_CONST_HANDLE const hDevice, + const uint8_t nMode); + +ADI_SPI_RESULT adi_spi_SetReceiveOverflow( + ADI_SPI_CONST_HANDLE const hDevice, + const bool bFlag + ); + +ADI_SPI_RESULT adi_spi_SetTransmitUnderflow( + ADI_SPI_CONST_HANDLE const hDevice, + const bool bFlag + ); + +/* Mode Configuration Interface */ +ADI_SPI_RESULT adi_spi_SetBitrate( + ADI_SPI_CONST_HANDLE const hDevice, + const uint32_t Hertz + ); +ADI_SPI_RESULT adi_spi_SetChipSelect( + ADI_SPI_HANDLE const hDevice, + const ADI_SPI_CHIP_SELECT eChipSelect + ); + +ADI_SPI_RESULT adi_spi_GetBitrate( + ADI_SPI_CONST_HANDLE const hDevice, + uint32_t* const pnBitrate + ); + + +#ifdef __cplusplus +} +#endif + + +/**@}*/ + + +#endif /* ADI_SPI_H__ */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/sport/adi_sport.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/sport/adi_sport.h new file mode 100755 index 0000000000..aaf32f2cb0 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/sport/adi_sport.h @@ -0,0 +1,236 @@ +/*! **************************************************************************** + * @file adi_sport.h + * @brief SPORT (Serial Port) Device driver definitions + * @details Header File for the SPORT driver API functions and definitions + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef ADI_SPORT_H +#define ADI_SPORT_H + +/*============= I N C L U D E S =============*/ + +#include +#include +#include +#include + +/** @addtogroup SPORT_Driver SPORT Driver +* @{ +*/ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/*============== D E F I N E S ===============*/ + +/** + * Amount of memory (bytes) required by the SPORT device driver for managing + * the operation in interrupt mode. This memory is completely owned by the + * driver till the end of the operation. + */ +#define ADI_SPORT_MEMORY_SIZE (76u + ADI_SEM_SIZE) + +typedef void* ADI_SPORT_HANDLE; /*!< Handle to the SPORT Device */ + +/** + * Enumeration of different channels of the SPORT + */ +typedef enum +{ + ADI_HALF_SPORT_A = 0, /*!< First half SPORT */ + ADI_HALF_SPORT_B = 1 /*!< Second half SPORT */ +} ADI_SPORT_CHANNEL; + +/** + * Enumeration for the direction of operation. + */ +typedef enum +{ + ADI_SPORT_DIR_RX, /*!< Sport in Rx mode */ + ADI_SPORT_DIR_TX /*!< Sport in Tx mode */ +} ADI_SPORT_DIRECTION; + +/** + * Enumeration for enabling packing. + */ +typedef enum +{ + ADI_SPORT_NO_PACKING = 0, /*!< No Packing */ + ADI_SPORT_8BIT_PACKING = ENUM_SPORT_CTL_A_CTL_PACK_8BIT, /*!< 8-bit packing */ + ADI_SPORT_16BIT_PACKING = ENUM_SPORT_CTL_A_CTL_PACK_16BIT /*!< 16-Bit packing */ +} ADI_SPORT_PACKING_MODE; + +/** + * Enumeration for Hardware Error encountered by the SPORT device. + */ + typedef enum +{ + ADI_SPORT_HW_NO_ERR = 0x00, /*!< No Hardware error */ + ADI_SPORT_HW_ERR_RX_OVERFLOW = 0x02, /*!< Data overflow for Rx (same value as Tx underflow) */ + ADI_SPORT_HW_ERR_TX_UNDERFLOW = 0x02, /*!< Data underflow for Tx (same value as Rx overflow) */ + ADI_SPORT_HW_ERR_FS = 0x04, /*!< Frame sync error */ + ADI_SPORT_HW_ERR_SYSDATAERR = 0x10, /*!< System Data Error */ + + ADI_SPORT_EVENT_RX_BUFFER_PROCESSED = 0x20, /*!< Processed the submitted RX buffer */ + ADI_SPORT_EVENT_TX_BUFFER_PROCESSED = 0x40, /*!< Processed the submitted TX buffer */ + + ADI_SPORT_DMA_ERR_BUS = 0x100, /*!< SPORT DMA bus error detected */ + ADI_SPORT_DMA_ERR_INVALID_DESCRIPTOR = 0x200 /*!< SPORT DMA invalid descriptor error detected */ +}ADI_SPORT_EVENT; + + +/** + * Enumeration for result code returned from the SPORT device driver functions. + */ +typedef enum +{ + ADI_SPORT_SUCCESS, /*!< Success */ + ADI_SPORT_FAILED, /*!< Generic Failure to indicate a call to SPORT driver function returned unsuccessful */ + ADI_SPORT_INVALID_DEVICE_NUM , /*!< Invalid device number */ + ADI_SPORT_INVALID_NULL_POINTER, /*!< Specified pointer is invalid */ + ADI_SPORT_INVALID_HANDLE, /*!< The given handle is invalid */ + ADI_SPORT_INVALID_PARAMETER, /*!< Specified parameter is not valid */ + ADI_SPORT_DMA_REGISTER_FAILED, /*!< Registering DMA error handler failed */ + ADI_SPORT_DEVICE_IN_USE, /*!< The specified SPORT channel is already open and in use */ + ADI_SPORT_INVALID_CONFIGURATION, /*!< The SPORT configuration is invalid */ + ADI_SPORT_BUFFERS_NOT_SUBMITTED, /*!< Buffer submission failed */ + ADI_SPORT_INVALID_WORD_LENGTH, /*!< Invalid word size */ + ADI_SPORT_OPERATION_NOT_ALLOWED, /*!< Specified operation is not allowed when SPORT is transmitting/receiving data */ + ADI_SPORT_HW_ERROR /*!< SPORT hardware or DMA reports an error */ +} ADI_SPORT_RESULT; + +/*============= P U B L I C F U N C T I O N S =============*/ + +/* Opens a SPORT device */ +ADI_SPORT_RESULT adi_sport_Open( + const uint32_t nDevNum, + const ADI_SPORT_CHANNEL eChannel, + const ADI_SPORT_DIRECTION eDirection, + void *pMemory, + const uint32_t nMemSize, + ADI_SPORT_HANDLE * const phDevice + ); + +/* Closes a SPORT device */ +ADI_SPORT_RESULT adi_sport_Close( + ADI_SPORT_HANDLE const hDevice + ); + +/* Submits a buffer to the driver */ +ADI_SPORT_RESULT adi_sport_SubmitBuffer( + ADI_SPORT_HANDLE const hDevice, + void * const pBuffer, + uint32_t const nNumBytes, + bool const bDMA + ); + +/* Get the processed buffer from the driver */ +ADI_SPORT_RESULT adi_sport_GetBuffer( + ADI_SPORT_HANDLE const hDevice, + void ** const ppBuffer, + uint32_t * pHwError + ); + +/* Peek function to know whether an processed buffer is avilable */ +ADI_SPORT_RESULT adi_sport_IsBufferAvailable( + ADI_SPORT_HANDLE const hDevice, + bool * const pbAvailable + ); + +/* To register the callback function */ +ADI_SPORT_RESULT adi_sport_RegisterCallback( + ADI_SPORT_HANDLE const hDevice, + const ADI_CALLBACK pfCallback, + void * const pCBparam + ); + +/* Configure the data */ +ADI_SPORT_RESULT adi_sport_ConfigData( + ADI_SPORT_HANDLE const hDevice, + const uint8_t nWordLength, + const ADI_SPORT_PACKING_MODE ePackMode, + const bool bLSBFirst + ); + +/* Configure the clock */ +ADI_SPORT_RESULT adi_sport_ConfigClock( + ADI_SPORT_HANDLE const hDevice, + const uint16_t nClockRatio, + const bool bUseIntlClock, + const bool bRisingEdge, + const bool bGatedClk + ); + +/* Configure the frame sync */ +ADI_SPORT_RESULT adi_sport_ConfigFrameSync( + ADI_SPORT_HANDLE const hDevice, + const uint16_t nFsDivisor, + const bool bFSRequired, + const bool bInternalFS, + const bool bDataFS, + const bool bActiveLowFS, + const bool bLateFS, + const bool bFSErrorOperation + ); + +/* To mux the half-SPORT; this makes the device to use FS and Clock from other half-SPORT */ +ADI_SPORT_RESULT adi_sport_MultiplexSportSignal( + ADI_SPORT_HANDLE const hDevice, + const bool bUseOtherFS, + const bool bUseOtherClk + ); + +/* To configure the SPORT in timer mode */ +ADI_SPORT_RESULT adi_sport_ConfigTimerMode( + ADI_SPORT_HANDLE const hDevice, + const uint8_t nFSDuration, + const uint8_t nWidth, + const bool bActiveLow + ); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ADI_SPORT_H */ +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/tmr/adi_tmr.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/tmr/adi_tmr.h new file mode 100755 index 0000000000..9331593a12 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/tmr/adi_tmr.h @@ -0,0 +1,253 @@ +/*! ***************************************************************************** + * @file adi_tmr.h + * @brief GP and RGB timer device driver public header file + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifndef ADI_TMR_H +#define ADI_TMR_H + + +#include +#include +#include + + +/** @addtogroup TMR_Driver Timer Driver + * @{ + */ + + +/*! + ***************************************************************************** + * \enum ADI_TMR_RESULT + * Enumeration for result code returned from the timer device driver functions. + * The return value of all timer APIs returning #ADI_TMR_RESULT should always + * be tested at the application level for success or failure. + *****************************************************************************/ +typedef enum { + /*! Successful operation */ + ADI_TMR_SUCCESS, + /*! Bad device number supplied by user */ + ADI_TMR_BAD_DEVICE_NUM, + /*! Bad PWM output number supplied by user to #adi_tmr_ConfigPwm */ + ADI_TMR_BAD_PWM_NUM, + /*! Bad event number supplied by user to #adi_tmr_ConfigEvent */ + ADI_TMR_BAD_EVENT_ID, + /*! Bad timer configuration, reloading and free running are mutually exclusive options */ + ADI_TMR_BAD_RELOAD_CONFIGURATION, + /*! Setup or enable function called while the timer is running */ + ADI_TMR_OPERATION_NOT_ALLOWED, + /*! Timeout while waiting for busy bit to clear before writing control register */ + ADI_TMR_DEVICE_BUSY, + /*! User attempts to reload the timer when reloading has not been enabled */ + ADI_TMR_RELOAD_DISABLED, + /*! User attempts to read the current or captured count with a NULL pointer */ + ADI_TMR_NULL_POINTER +} ADI_TMR_RESULT; + +/*! + ***************************************************************************** + * \enum ADI_TMR_DEVICE + * Enumeration for the hardware peripheral being used during the API call + *****************************************************************************/ +typedef enum { + /*! General purpose timer 0 */ + ADI_TMR_DEVICE_GP0 = 0u, + /*! General purpose timer 1 */ + ADI_TMR_DEVICE_GP1 = 1u, + /*! General purpose timer 2 */ + ADI_TMR_DEVICE_GP2 = 2u, + /*! RGB timer */ + ADI_TMR_DEVICE_RGB = 3u, + /*! Total number of devices (private) */ + ADI_TMR_DEVICE_NUM = 4u, +} ADI_TMR_DEVICE; + +/*! + ***************************************************************************** + * \enum ADI_TMR_EVENT + * Enumeration of events notified in the application provided callback. + *****************************************************************************/ +typedef enum { + /*! Timeout event occurred */ + ADI_TMR_EVENT_TIMEOUT = 0x01, + /*! Event capture event occurred */ + ADI_TMR_EVENT_CAPTURE = 0x02, +} ADI_TMR_EVENT; + +/*! + ***************************************************************************** + * \enum ADI_TMR_PRESCALER + * Prescale options when configuring the timer + *****************************************************************************/ +typedef enum { + /*! Count every 1 source clock periods */ + ADI_TMR_PRESCALER_1 = 0u, + /*! Count every 16 source clock periods */ + ADI_TMR_PRESCALER_16 = 1u, + /*! Count every 64 source clock periods */ + ADI_TMR_PRESCALER_64 = 2u, + /*! Count every 256 source clock periods */ + ADI_TMR_PRESCALER_256 = 3u, +} ADI_TMR_PRESCALER; + +/*! + ***************************************************************************** + * \enum ADI_TMR_CLOCK_SOURCE + * Source clock options when configuring the timer + *****************************************************************************/ +typedef enum { + /*! Use periphreal clock (PCLK) */ + ADI_TMR_CLOCK_PCLK = 0u, + /*! Use internal high frequency clock (HFOSC) */ + ADI_TMR_CLOCK_HFOSC = 1u, + /*! Use internal low frequency clock (LFOSC) */ + ADI_TMR_CLOCK_LFOSC = 2u, + /*! Use external low frequency clock (LFXTAL) */ + ADI_TMR_CLOCK_LFXTAL = 3u, +} ADI_TMR_CLOCK_SOURCE; + +/*! + ***************************************************************************** + * \enum ADI_TMR_PWM_OUTPUT + * RGB PWM outputs, used to specify which PWM output to configure. For the GP + * timers only #ADI_TMR_PWM_OUTPUT_0 is allowed. The RGB timer has all three + * outputs. + *****************************************************************************/ +typedef enum { + /*! PWM output 0 */ + ADI_TMR_PWM_OUTPUT_0 = 0u, + /*! PWM output 1 */ + ADI_TMR_PWM_OUTPUT_1 = 1u, + /*! PWM output 2 */ + ADI_TMR_PWM_OUTPUT_2 = 2u, + /*! Total number of outputs (private) */ + ADI_TMR_PWM_OUTPUT_NUM = 3u, +} ADI_TMR_PWM_OUTPUT; + +/*! + ***************************************************************************** + * \struct ADI_TMR_CONFIG + * Configuration structure to fill and pass to #adi_tmr_ConfigTimer when + * configuring the GP or RGB timer + *****************************************************************************/ +typedef struct { + /*! True to count up, false to count down */ + bool bCountingUp; + /*! True for periodic (specific load value), false for free running (0xFFFF) */ + bool bPeriodic; + /*! Prescaler */ + ADI_TMR_PRESCALER ePrescaler; + /*! Clock source */ + ADI_TMR_CLOCK_SOURCE eClockSource; + /*! Load value (only relent in periodic mode) */ + uint16_t nLoad; + /*! Asynchronous load value (only relevant in periodic mode, and when PCLK is used) */ + uint16_t nAsyncLoad; + /*! True to enable reloading, false to disable it (only relevant in periodic mode) */ + bool bReloading; + /*! True to enable sync bypass, false to disable it */ + bool bSyncBypass; +} ADI_TMR_CONFIG; + +/*! + ***************************************************************************** + * \struct ADI_TMR_EVENT_CONFIG + * Configuration structure to fill and pass to #adi_tmr_ConfigEvent when + * configuring event capture + *****************************************************************************/ +typedef struct { + /*! True to enable event capture, false to disable it */ + bool bEnable; + /*! True to reset the counter and prescaler when the selected event occurs, false to let it continue */ + bool bPrescaleReset; + /*! Event identifier, see hardware reference manual for details */ + uint8_t nEventID; +} ADI_TMR_EVENT_CONFIG; + +/*! + ***************************************************************************** + * \struct ADI_TMR_PWM_CONFIG + * Configuration structure to fill and pass to #adi_tmr_ConfigPwm when + * configuring pulse width modulation output + *****************************************************************************/ +typedef struct { + /*! PWM output */ + ADI_TMR_PWM_OUTPUT eOutput; + /*! True if match mode (configurable duty cycle), false if toggle mode (50% duty cycle) */ + bool bMatch; + /*! True for PWM idle high, false for PWM idle low */ + bool bIdleHigh; + /*! Match value, only applicable if in match mode */ + uint16_t nMatchValue; +} ADI_TMR_PWM_CONFIG; + +/****************************************************************************** + * PUBLIC API + * 1.) Eliminate functions that may be optimized out by the linker + * 2.) Ordered by designed function call sequence + *****************************************************************************/ + +/* Initialize timer driver */ +ADI_TMR_RESULT adi_tmr_Init (ADI_TMR_DEVICE const eDevice, ADI_CALLBACK const pfCallback, void * const pCBParam, bool bEnableInt); + +/* Configuration interface functions */ +ADI_TMR_RESULT adi_tmr_ConfigTimer (ADI_TMR_DEVICE const eDevice, ADI_TMR_CONFIG timerConfig); +ADI_TMR_RESULT adi_tmr_ConfigEvent (ADI_TMR_DEVICE const eDevice, ADI_TMR_EVENT_CONFIG eventConfig); +ADI_TMR_RESULT adi_tmr_ConfigPwm (ADI_TMR_DEVICE const eDevice, ADI_TMR_PWM_CONFIG pwmConfig ); + +/* Timer start and stop */ +ADI_TMR_RESULT adi_tmr_Enable (ADI_TMR_DEVICE const eDevice, bool bEnable); + +/* Read functions */ +ADI_TMR_RESULT adi_tmr_GetCurrentCount (ADI_TMR_DEVICE const eDevice, uint16_t *pCount); +ADI_TMR_RESULT adi_tmr_GetCaptureCount (ADI_TMR_DEVICE const eDevice, uint16_t *pCount); + +/* Reload function */ +ADI_TMR_RESULT adi_tmr_Reload (ADI_TMR_DEVICE const eDevice); + + +/*! @} */ + + +#endif /* ADI_TMR_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/uart/adi_uart.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/uart/adi_uart.h new file mode 100755 index 0000000000..abb0bf3109 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/uart/adi_uart.h @@ -0,0 +1,498 @@ +/*! ***************************************************************************** + * @file adi_uart.h + * @brief UART device driver global include file. + * @details This a global file which includes a specific file based on the processor family. + * This included file will be containing UART device driver functions. + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_UART_H +#define ADI_UART_H + +/** @addtogroup UART_Driver UART Driver +* @{ +*/ + +/*! \cond PRIVATE */ + +/*============= I N C L U D E S =============*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! \endcond */ + +/*! Amount of memory(bytes) required by the UART device driver for operating unidirectionally(Either RX or TX). + * This memory is completely owned by the driver until the end of the operation. + */ +#define ADI_UART_UNIDIR_MEMORY_SIZE (48u + (60u + ADI_SEM_SIZE)) + +/*! Amount of memory(bytes) required by the UART device driver for operating bidirectionally(Both RX and TX). + * This memory is completely owned by the driver until the end of the operation. + */ +#define ADI_UART_BIDIR_MEMORY_SIZE (48u + (60u + ADI_SEM_SIZE)*2u) + +/*! + * Handle for managing the UART device typedef. + */ +typedef struct _ADI_UART_DEVICE* ADI_UART_HANDLE; + +/*! + * Handle for managing the UART device typedef 'const' version. + */ +typedef const struct _ADI_UART_DEVICE* ADI_UART_CONST_HANDLE; + +/*! + ***************************************************************************** + * \enum ADI_UART_DIRECTION + * Enumeration for the UART direction. + *****************************************************************************/ +typedef enum +{ + ADI_UART_DIR_TRANSMIT, /*!< UART is only transmitting. */ + + ADI_UART_DIR_RECEIVE, /*!< UART is only receiving. */ + + ADI_UART_DIR_BIDIRECTION /*!< UART in bidirectional. */ + +} ADI_UART_DIRECTION; + + +/*! + ***************************************************************************** + * \enum ADI_UART_EVENT + * Enumeration of events notified in the application provided callback. + *****************************************************************************/ + typedef enum +{ + ADI_UART_EVENT_RX_BUFFER_PROCESSED, /*!< Rx buffer is processed. */ + + ADI_UART_EVENT_TX_BUFFER_PROCESSED, /*!< Tx buffer is processed. */ + + ADI_UART_EVENT_NO_RX_BUFFER_EVENT, /*!< No Rx buffer but data is in FIFO. */ + + ADI_UART_EVENT_AUTOBAUD_COMPLETE, /*!< Autobaud is complete. */ + + ADI_UART_EVENT_HW_ERROR_DETECTED, /*!< Hardware error detected. */ + + ADI_UART_EVENT_AUTOBAUD_ERROR_DETECTED /*!< Autobaud error detected. */ + +}ADI_UART_EVENT; + + +/*! + ***************************************************************************** + * \enum ADI_UART_RESULT + * Enumeration for result code returned from the UART device driver functions. + * The return value of all UART APIs returning #ADI_UART_RESULT + * should always be tested at the application level for success or failure. + *****************************************************************************/ + typedef enum +{ + + ADI_UART_SUCCESS, /*!< Generic success. */ + + ADI_UART_FAILED, /*!< Generic failure. */ + + ADI_UART_SEMAPHORE_FAILED, /*!< Semaphore error. */ + + ADI_UART_INVALID_HANDLE, /*!< Invalid device handle. */ + + ADI_UART_DEVICE_IN_USE, /*!< UART device in use. */ + + ADI_UART_INVALID_DEVICE_NUM, /*!< Invalid device number. */ + + ADI_UART_INVALID_POINTER, /*!< NULL data pointer is not allowed. */ + + ADI_UART_INSUFFICIENT_MEMORY, /*!< Insufficent memory. */ + + ADI_UART_INVALID_DIR, /*!< Invalid UART direction. */ + + ADI_UART_OPERATION_NOT_ALLOWED, /*!< Invalid operation. */ + + ADI_UART_INVALID_PARAMETER, /*!< Invalid parameter. */ + + ADI_UART_BUFFER_NOT_SUBMITTED, /*!< Buffer not submitted. */ + + ADI_UART_INVALID_DATA_TRANSFER_MODE, /*!< Invalid transfer mode. + Adi_uart_Read()/adi_uart_Write() is used in nonblocking mode + or adi_uart_SubmitRxBuffer()/adi_uart_SubmitTxBuffer() + is used in blocking mode. */ + + ADI_UART_HW_ERROR_DETECTED, /*!< Hardware error detected. */ + + ADI_UART_AUTOBAUD_ERROR_DETECTED, /*!< Autobaud error detected. */ + + ADI_UART_ERR_DMA_REGISTER, /*!< Error while registering the DMA callback. */ + + ADI_UART_INVALID_DATA_SIZE /*!< Invalid transfer size. Must be less than 1025 bytes */ + +} ADI_UART_RESULT; + +/*! + ***************************************************************************** + * \enum ADI_UART_HW_ERRORS + * Enumeration for UART hardware errors. If hardware error(s) occur in + * either callback or interrupt mode, they are mapped to #ADI_UART_HW_ERRORS. + * Interpretation of the break condition is application specific. + *****************************************************************************/ +typedef enum +{ + ADI_UART_NO_HW_ERROR = 0x00, /*!< No hardware error. */ + + ADI_UART_HW_ERR_FRAMING = 0x10, /*!< Rx framing error. */ + + ADI_UART_HW_ERR_PARITY = 0x20, /*!< Rx parity error. */ + + ADI_UART_HW_ERR_OVERRUN = 0x40, /*!< Receive overrun. */ + + ADI_UART_BREAK_INTERRUPT = 0x80, /*!< Break condition. */ + + ADI_UART_HW_ERR_RX_CHAN_DMA_BUS_FAULT = 0x100, /*!< Rx DMA channel bus fault detected. */ + + ADI_UART_HW_ERR_TX_CHAN_DMA_BUS_FAULT = 0x200, /*!< Tx DMA channel bus fault detected. */ + + ADI_UART_HW_ERR_RX_CHAN_DMA_INVALID_DESCR = 0x400, /*!< Rx DMA channel invalid descriptor detected. */ + + ADI_UART_HW_ERR_TX_CHAN_DMA_INVALID_DESCR = 0x800, /*!< Tx DMA channel invalid descriptor detected. */ + + ADI_UART_HW_ERR_RX_CHAN_DMA_UNKNOWN_ERROR = 0x1000, /*!< Rx DMA channel unknown error detected. */ + + ADI_UART_HW_ERR_TX_CHAN_DMA_UNKNOWN_ERROR = 0x2000, /*!< Tx DMA channel unknown error detected. */ + +}ADI_UART_HW_ERRORS; + +/*! + ***************************************************************************** + * \enum ADI_UART_AUTOBAUD_ERRORS + * Enumeration for UART autobaud errors. If autobaud related error(s) occur + * they are mapped to #ADI_UART_AUTOBAUD_ERRORS. + *****************************************************************************/ +typedef enum +{ + ADI_UART_AUTOBAUD_NO_ERROR = 0x000, /*!< No autobaud error. */ + + ADI_UART_AUTOBAUD_TIMEOUT_NO_START_EDGE = 0x100, /*!< Timeout due to no valid start edge found during autobaud. */ + + ADI_UART_AUTOBAUD_TIMEOUT_LONGBREAK = 0x200, /*!< Timeout due to break condition detected during autobaud. */ + + ADI_UART_AUTOBAUD_TIMEOUT_NO_END_EDGE = 0x400 /*!< Timeout due to no valid end edge found during autobaud. */ + +}ADI_UART_AUTOBAUD_ERRORS; + +/*! + ***************************************************************************** + * \enum ADI_UART_TRIG_LEVEL + * Enumeration for the FIFO trigger level. + *****************************************************************************/ +typedef enum +{ + + ADI_UART_RX_FIFO_TRIG_LEVEL_1BYTE = 0 << BITP_UART_FCR_RFTRIG, /*!< 1-byte to trigger RX interrupt. */ + + ADI_UART_RX_FIFO_TRIG_LEVEL_4BYTE = 1 << BITP_UART_FCR_RFTRIG, /*!< 4-byte to trigger RX interrupt. */ + + ADI_UART_RX_FIFO_TRIG_LEVEL_8BYTE = 2 << BITP_UART_FCR_RFTRIG, /*!< 8-byte to trigger RX interrupt. */ + + ADI_UART_RX_FIFO_TRIG_LEVEL_14BYTE = 3 << BITP_UART_FCR_RFTRIG /*!< 14-byte to trigger RX interrupt. */ + +}ADI_UART_TRIG_LEVEL; + +/*! + ***************************************************************************** + * \enum ADI_UART_WORDLEN + * Enumeration for data width. + *****************************************************************************/ +typedef enum +{ + ADI_UART_WORDLEN_5BITS, /*!< 5 bits wide. */ + + ADI_UART_WORDLEN_6BITS, /*!< 6 bits wide. */ + + ADI_UART_WORDLEN_7BITS, /*!< 7 bits wide. */ + + ADI_UART_WORDLEN_8BITS /*!< 8 bits wide. */ + +} ADI_UART_WORDLEN; + +/*! + ***************************************************************************** + * \enum ADI_UART_PARITY + * Enumeration for parity check. + *****************************************************************************/ +typedef enum +{ + ADI_UART_NO_PARITY = 0x0, /*!< No parity. */ + + ADI_UART_ODD_PARITY = 0x8, /*!< Odd parity. */ + + ADI_UART_EVEN_PARITY = 0x18, /*!< Even Parity. */ + + ADI_UART_ODD_PARITY_STICKY = 0x28, /*!< Sticky odd parity. */ + + ADI_UART_EVEN_PARITY_STICKY = 0x38 /*!< Sticky even parity. */ + +} ADI_UART_PARITY; + +/*! + ***************************************************************************** + * \enum ADI_UART_STOPBITS + * Enumeration for the number of stop bits. + *****************************************************************************/ +typedef enum +{ + + ADI_UART_ONE_STOPBIT = 0x00, /*! One stop bit regardless of the word length */ + + ADI_UART_ONE_AND_HALF_TWO_STOPBITS = 0x04 /*! Number of stop bits based on word length. 1.5 stop bits + for word length of 5 bits and 2 for rest( 6,7,8 bit word length) */ + +} ADI_UART_STOPBITS; + +/*! + ***************************************************************************** + * \enum ADI_UART_TRANSFER_MODE + * Enumeration for data transfer mode. + *****************************************************************************/ +typedef enum +{ + + ADI_UART_DATA_TRANSFER_MODE_NONE, /*! Mode of data transfer is not selected. */ + + ADI_UART_DATA_TRANSFER_MODE_BLOCKING, /*! Blocking mode. Only calls to adi_uart_Read or adi_uart_write + are allowed for sending or receiving data. */ + + ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING /*! Non-Blocking mode. Only calls to adi_uart_SubmitRxBuffer or + adi_uart_SubmitTxBuffer are allowed for sending or receiving data. */ + +} ADI_UART_TRANSFER_MODE; + + +/****************************************************************************** + * UART Device external API function prototypes + *****************************************************************************/ + +/* + * Device initialization and uninitialization interfaces. +*/ +ADI_UART_RESULT adi_uart_Open( + uint32_t const nDeviceNum, + ADI_UART_DIRECTION const eDirection, + void *pMemory, + uint32_t const nMemSize, + ADI_UART_HANDLE *const phDevice +); + +ADI_UART_RESULT adi_uart_Close( + ADI_UART_HANDLE const hDevice +); + + +/****************************************************************************** + * Eliminatable functions that may be optimized out by the linker + *****************************************************************************/ + +/* + * Non-blocking mode functions. +*/ + +ADI_UART_RESULT adi_uart_SubmitTxBuffer( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA +); + +ADI_UART_RESULT adi_uart_SubmitRxBuffer( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA +); + +ADI_UART_RESULT adi_uart_GetTxBuffer( + ADI_UART_HANDLE const hDevice, + void **const ppBuffer, + uint32_t *pHwError +); + +ADI_UART_RESULT adi_uart_GetRxBuffer( + ADI_UART_HANDLE const hDevice, + void **const ppBuffer, + uint32_t *pHwError +); +ADI_UART_RESULT adi_uart_IsTxBufferAvailable( + ADI_UART_HANDLE const hDevice, + bool *const pbAvailable +); + +ADI_UART_RESULT adi_uart_IsRxBufferAvailable( + ADI_UART_HANDLE const hDevice, + bool *const pbAvailable +); + +/* + * Blocking mode functions. +*/ + +ADI_UART_RESULT adi_uart_Write( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA, + uint32_t *pHwError +); + +ADI_UART_RESULT adi_uart_Read( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA, + uint32_t *pHwError +); + + +/* + * Configuration interface functions. +*/ + +ADI_UART_RESULT adi_uart_EnableLoopBack( + ADI_UART_HANDLE const hDevice, + bool const bEnable +); + +ADI_UART_RESULT adi_uart_EnableAutobaud( + ADI_UART_HANDLE const hDevice, + bool const bEnable, + bool const bAutobaudCallbackMode +); + +ADI_UART_RESULT adi_uart_SetRxFifoTriggerLevel( + ADI_UART_CONST_HANDLE const hDevice, + ADI_UART_TRIG_LEVEL const eTriglevel +); + +ADI_UART_RESULT adi_uart_EnableFifo( + ADI_UART_HANDLE const hDevice, + bool const bEnable +); + +ADI_UART_RESULT adi_uart_GetBaudRate( + ADI_UART_HANDLE const hDevice, + uint32_t *pnBaudRate, + uint32_t *pAutobaudError +); + +ADI_UART_RESULT adi_uart_ForceTxBreak( + ADI_UART_HANDLE const hDevice, + bool const bEnable +); + +ADI_UART_RESULT adi_uart_SetConfiguration( + ADI_UART_HANDLE const hDevice, + ADI_UART_PARITY const eParity, + ADI_UART_STOPBITS const eStopBits, + ADI_UART_WORDLEN const eWordLength +); + +ADI_UART_RESULT adi_uart_ConfigBaudRate( + ADI_UART_HANDLE const hDevice, + uint16_t const nDivC, + uint8_t const nDivM, + uint16_t const nDivN, + uint8_t const nOSR +); + +/* + * Channel data control functions. +*/ + +ADI_UART_RESULT adi_uart_FlushTxFifo( + ADI_UART_CONST_HANDLE const hDevice +); + +ADI_UART_RESULT adi_uart_FlushRxFifo( + ADI_UART_CONST_HANDLE const hDevice +); + +ADI_UART_RESULT adi_uart_FlushRxChannel( + ADI_UART_CONST_HANDLE const hDevice +); + + +ADI_UART_RESULT adi_uart_FlushTxChannel( + ADI_UART_CONST_HANDLE const hDevice +); + +ADI_UART_RESULT adi_uart_IsTxComplete( + ADI_UART_HANDLE const hDevice, + bool *const pbComplete +); + +/* + * Callback functions. +*/ + +ADI_UART_RESULT adi_uart_RegisterCallback( + ADI_UART_HANDLE const hDevice, + const ADI_CALLBACK pfCallback, + void *const pCBParam +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +/*@}*/ + +#endif /* ADI_UART_H */ + + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/wdt/adi_wdt.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/wdt/adi_wdt.h new file mode 100755 index 0000000000..834afee018 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/wdt/adi_wdt.h @@ -0,0 +1,77 @@ +/*! ***************************************************************************** + * @file adi_wdt.h + * @brief WDT device driver public header + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_WDT_H +#define ADI_WDT_H + +#include + +/** @addtogroup WDT_Driver WDT Driver + * @{ + */ + +/*! \enum ADI_WDT_RESULT Watchdog Device Error Codes. */ +typedef enum +{ + /*! Generic success. */ + ADI_WDT_SUCCESS, + /*! Timer is locked. */ + ADI_WDT_FAILURE_LOCKED +} ADI_WDT_RESULT; + + +/****************************************************************************** + * PUBLIC API + * 1.) Eliminatable functions that may be optimized out by the linker + * 2.) Ordered by designed function call sequence + *****************************************************************************/ + +ADI_WDT_RESULT adi_wdt_Enable (bool const bEnable, ADI_CALLBACK const pfCallback); +void adi_wdt_Kick (void); +void adi_wdt_GetCount(uint16_t * const pCurCount); + + +/*! @} */ + +#endif /* ADI_WDT_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/xint/adi_xint.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/xint/adi_xint.h new file mode 100755 index 0000000000..ba76911f64 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/xint/adi_xint.h @@ -0,0 +1,120 @@ +/* + ***************************************************************************** + @file: adi_xint.h + @brief: External interrupt driver definitions and API + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_XINT_H +#define ADI_XINT_H + +/*! \addtogroup XINT_Driver External Interrupt Driver + * @{ + */ + +#ifdef __ICCARM__ +#pragma diag_default=Pm008 +#endif /* __ICCARM__ */ + +#include +#include + +#if !defined(__ADUCM4x50__) +#error "Unknown processor family" +#endif + +/* C++ linkage */ +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! Amount of memory(in bytes) required by the External Interrupt device driver for its operation. + * This memory is completely owned by the driver till the end of the operation. + */ +#define ADI_XINT_MEMORY_SIZE (48u) + +/*! External Interrupt Driver API function return codes */ +typedef enum +{ + ADI_XINT_SUCCESS = 0, /*!< API successfully returned. */ + ADI_XINT_FAILURE, /*!< The API call failed. */ + ADI_XINT_ALREADY_INITIALIZED, /*!< External interrupt driver has already been initialized. */ + ADI_XINT_NOT_INITIALIZED, /*!< External interrupt driver has not yet been initialized. */ + ADI_XINT_NULL_PARAMETER, /*!< The given pointer is pointing to NULL. */ + ADI_XINT_INVALID_MEMORY_SIZE, /*!< The given memory is not sufficient to operate the driver. */ + ADI_XINT_INVALID_INTERRUPT /*!< Invalid interrupt number. */ +} ADI_XINT_RESULT; + + +/*! External interrupt trigger condition enumerations */ +typedef enum { + ADI_XINT_IRQ_RISING_EDGE = 0x0, /*!< Trigger an interrupt when a rising edge is detected. */ + ADI_XINT_IRQ_FALLING_EDGE = 0x1, /*!< Trigger an interrupt when on a falling edge is detected. */ + ADI_XINT_IRQ_EITHER_EDGE = 0x2, /*!< Trigger an interrupt on either falling or rising edge is detected. */ + ADI_XINT_IRQ_HIGH_LEVEL = 0x3, /*!< Trigger an interrupt on a logic level high is detected. */ + ADI_XINT_IRQ_LOW_LEVEL = 0x4 /*!< Trigger an interrupt on a logic level low is detected. */ +} ADI_XINT_IRQ_MODE; + +/*! External interrupts. */ +typedef enum { + ADI_XINT_EVENT_INT0 = 0x0, /*!< Event for external interrupt-0 */ + ADI_XINT_EVENT_INT1 = 0x1, /*!< Event for external interrupt-1 */ + ADI_XINT_EVENT_INT2 = 0x2, /*!< Event for external interrupt-2 */ + ADI_XINT_EVENT_INT3 = 0x3, /*!< Event for external interrupt-3 */ + ADI_XINT_EVENT_RESERVED = 0x4, /*!< Event is reserved. */ + ADI_XINT_EVENT_UART_RX = 0x5, /*!< Event for UART Rx activity */ + ADI_XINT_EVENT_MAX = 0x6 /*!< Number of external interrupt events */ +} ADI_XINT_EVENT; + + +/* External Interrupt API functions */ +ADI_XINT_RESULT adi_xint_Init (void* const pMemory, uint32_t const MemorySize); +ADI_XINT_RESULT adi_xint_UnInit (void); +ADI_XINT_RESULT adi_xint_EnableIRQ (const ADI_XINT_EVENT eEvent, const ADI_XINT_IRQ_MODE eMode); +ADI_XINT_RESULT adi_xint_DisableIRQ (const ADI_XINT_EVENT eEvent); +ADI_XINT_RESULT adi_xint_RegisterCallback (const ADI_XINT_EVENT eEvent, ADI_CALLBACK const pfCallback, void *const pCBParam ); + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* ADI_XINT_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash.c new file mode 100755 index 0000000000..66bc3cf1f6 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash.c @@ -0,0 +1,1812 @@ +/*! + ***************************************************************************** + @file: adi_flash.c + @brief: Flash Device Driver Implementation + @date: $Date: 2016-06-30 08:06:37 -0400 (Thu, 30 Jun 2016) $ + ----------------------------------------------------------------------------- +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/** @addtogroup Flash_Driver Flash Driver + * @{ + * + * @brief Flash (FEE) Driver + * + * @details + * + * The flash controller provides access to the embedded flash memory. The embedded + * flash has a 72-bit wide data bus providing for two 32-bit words of data and + * one corresponding 8-bit ECC byte per access. + * + * Flash Driver Hardware Errors + * + * Many of the Flash Controller APIs can result in hardware errors. Each such API has a + * a hardware error parameter (pHwErrors), which is a pointer to an application-defined + * variable into which the failing API will store the failing hardware error status.\n + * + * APIs failing with hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED + * return code.\n + * + * Hardware error details may be decoded according to the flash controller status register + * ("STAT") bit-map, documented in the Hardware Reference Manual (HRM). Flash hardware + * errors are separate and distinct from DMA errors, which have separate and distinct + * return codes (#ADI_FEE_ERR_DMA_BUS_FAULT, #ADI_FEE_ERR_DMA_INVALID_DESCR, and + * #ADI_FEE_ERR_DMA_UNKNOWN_ERROR). + * + * Flash Driver Static Configuration + * + * A number of flash driver APIs manage configurations that very likely do not require + * dynamic (run-time) management. Such cases are documented with the respective APIs. + * In all such cases, the user is encouraged to consider using the static configuration + * equivalents (provided in the adi_flash_config.h file) in lieu of the dynamic APIs. + * In so doing, linker elimination may reduce the resulting code image footprint + * (provided the API is not called). + * + * @note - The application must include drivers/flash/adi_flash.h to use this driver. + * @note - This driver also requires the DMA driver. The application must include + * the DMA driver sources to avoid link errors. + */ + +/*======== I N C L U D E ========*/ + + /*! \cond PRIVATE */ +#include +#include +#include /* for "memset" */ +/*! \endcond */ + +#include + +/*============= M I S R A =============*/ + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Needed for null expansion of ADI_INSTALL_HANDLER and others. +* +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Relying on pointer arithmetic for buffer handling. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* Required for MMR accesses, determining pointer alignment, and a callback argument. +* +* Pm026 (rule 12.4): the right hand operand of an && or || operator shall not contain side effects +* Side effects being mis-reported due to added volatile storage class. +*/ +#pragma diag_suppress=Pm123,Pm073,Pm143,Pm050,Pm088,Pm140,Pm026 +#endif /* __ICCARM__ */ + +/* pull in internal data structures */ +#include "adi_flash_data.c" + +/*======== D E F I N E S ========*/ + +/*! \cond PRIVATE */ + +#ifdef ADI_DEBUG +#define ASSERT(X) assert(X) +#else +#define ASSERT(X) +#endif + +/* internal utility macros */ +#define CLR_BITS(REG, BITS) ((REG) &= ~(BITS)) +#define SET_BITS(REG, BITS) ((REG) |= (BITS)) + +#ifdef ADI_DEBUG +/* Validate Device Handle */ +static bool IsDeviceHandle (ADI_FEE_HANDLE const hDevice); +static bool IsDeviceHandle (ADI_FEE_HANDLE const hDevice) +{ + if ( (fee_device_info[0].hDevice == (hDevice)) && ((hDevice)->pDevInfo->hDevice != NULL) ) { + return true; + } else { + return false; + } +} +#endif + +/* Wait for specified flash status to be clear */ +static void BusyWait (ADI_FEE_HANDLE const hDevice, uint32_t const status); +static void BusyWait (ADI_FEE_HANDLE const hDevice, uint32_t const status) +{ + while ((hDevice->pDev->STAT & status) != 0u) {} +} + +/* Internal DMA Callback for receiving DMA faults from common DMA error handler */ +static void dmaCallback(void *pCBParam, uint32_t Event, void *pArg); +static void dmaCallback(void *pCBParam, uint32_t Event, void *pArg) { + + /* recover the device handle */ + ADI_FEE_HANDLE hDevice = (ADI_FEE_HANDLE)pCBParam; + + /* save the DMA error */ + switch (Event) { + case ADI_DMA_EVENT_ERR_BUS: + hDevice->dmaError = ADI_FEE_ERR_DMA_BUS_FAULT; + break; + case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR: + hDevice->dmaError = ADI_FEE_ERR_DMA_INVALID_DESCR; + break; + default: + hDevice->dmaError = ADI_FEE_ERR_DMA_UNKNOWN_ERROR; + break; + } + + /* transfer is toast... post and callback any waiters */ + + SEM_POST(hDevice); + + if (0u != hDevice->pfCallback) { + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)hDevice->dmaError, (void*)NULL); + } +} + +/*! \endcond */ + + +/*======== C O D E ========*/ +/* + * API Implementation + */ + + +/** + * @brief Open the flash controller. + * + * @param [in] nDeviceNum The zero-based device instance number of flash controller to be opened. + * @param [in] pMemory Application supplied memory space for use by the driver. + * @param [in] nMemorySize Size of the application supplied memory (in bytes). + * @param [in,out] phDevice The caller's device handle pointer for storing the initialized + * device instance data pointer. + * + * @return Status + * - #ADI_FEE_SUCCESS The device is opened successfully. + * - #ADI_FEE_ERR_BAD_DEVICE_NUM [D] The device number passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Some pointer(s) passed to the function is NULL. + * - #ADI_FEE_ERR_ALREADY_INITIALIZED [D] The device is already initialized and hence cannot be opened. + * - #ADI_FEE_ERR_INSUFFICIENT_MEM [D] The memory passed to the driver is insufficient. + * - #ADI_FEE_ERR_DMA_REGISTER The required DMA common error handler registration failed. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore create operation failed. + * + * Initialize an instance of the flash device driver using default user configuration settings + * (from adi_flash_config.h) and allocate the device for use. + * + * No other flash APIs may be called until the device open function is called. The returned + * device handle is required to be passed to all subsequent flash API calls to identify the + * physical device instance in use. The user device handle (pointed to by phDevice) is set + * to NULL on failure. + * + * @note Currently, only a singular flash physical device instance (device ID "0") exists. + * + * @sa adi_fee_Close(). + */ +ADI_FEE_RESULT adi_fee_Open (uint32_t const nDeviceNum, void* const pMemory, uint32_t const nMemorySize, ADI_FEE_HANDLE* const phDevice) +{ + ADI_FEE_HANDLE hDevice = NULL; /* initially */ + +#ifdef ADI_DEBUG + if (nDeviceNum >= ADI_FEE_NUM_INSTANCES) { + return ADI_FEE_ERR_BAD_DEVICE_NUM; + } + + /* verify device is not already open */ + if (fee_device_info[nDeviceNum].hDevice != NULL) { + return ADI_FEE_ERR_ALREADY_INITIALIZED; + } + + if ((pMemory == NULL) || (phDevice == NULL)) { + return ADI_FEE_ERR_INVALID_PARAM; + } + + if (nMemorySize < ADI_FEE_MEMORY_SIZE) { + return ADI_FEE_ERR_INSUFFICIENT_MEM; + } + + assert (ADI_FEE_MEMORY_SIZE == sizeof(ADI_FEE_DEV_DATA_TYPE)); +#endif + + /* store a bad handle in case of failure */ + *phDevice = NULL; + + /* Link user memory (handle) into ADI_FEE_DEVICE_INFO data structure. + * + * ADI_FEE_DEVICE_INFO <==> ADI_FEE_HANDLE + */ + fee_device_info[nDeviceNum].hDevice = (ADI_FEE_DEV_DATA_TYPE *)pMemory; + + /* Clear the ADI_FEE_HANDLE memory. This also sets all bool + * structure members to false so we do not need to waste cycles + * setting these explicitly (e.g. hDevice->bUseDma = false) + */ + memset(pMemory, 0, nMemorySize); + + /* initialize local device handle and link up device info for this device instance */ + hDevice = (ADI_FEE_HANDLE)pMemory; + hDevice->pDevInfo = &fee_device_info[nDeviceNum]; + + /* Although the ADI_FEE_DEVICE_INFO struct has the physical device pointer + * for this instance, copying it to the ADI_FEE_HANDLE struct (in user memory) + * will minimize the runtime footprint and cycle count when accessing the FEE + * registers. + */ + hDevice->pDev = fee_device_info[nDeviceNum].pDev; + + /* store a pointer to user's static configuration settings for this device instance */ + hDevice->pDevInfo->pConfig = (ADI_FEE_CONFIG*)&gConfigInfo[nDeviceNum]; + + /* create the semaphore */ + SEM_CREATE(hDevice, "fee_sem", ADI_FEE_ERR_SEMAPHORE_FAILED); + + /* grant keyed access */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + + /* apply the static initializers */ + hDevice->pDev->IEN = hDevice->pDevInfo->pConfig->eccIrqEnables; + hDevice->pDev->TIME_PARAM0 = hDevice->pDevInfo->pConfig->param0; + hDevice->pDev->TIME_PARAM1 = hDevice->pDevInfo->pConfig->param1; + hDevice->pDev->ABORT_EN_LO = hDevice->pDevInfo->pConfig->abortEnableLo; + hDevice->pDev->ABORT_EN_HI = hDevice->pDevInfo->pConfig->abortEnableHi; + hDevice->pDev->ECC_CFG = hDevice->pDevInfo->pConfig->eccConfig; + + /* clear auto-increment and dma enable bits */ + CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN)); + + /* close keyed access */ + hDevice->pDev->KEY = 0u; + + /* store device handle into user handle */ + *phDevice = (ADI_FEE_HANDLE)hDevice; + + /* initialize DMA service */ + adi_dma_Init(); + + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pDevInfo->dmaChanNum, dmaCallback, (void*)hDevice)) { + /* uninitialize flash driver and fail */ + adi_fee_Close(hDevice); + return ADI_FEE_ERR_DMA_REGISTER; + } + + /* NVIC enables */ + NVIC_EnableIRQ(hDevice->pDevInfo->pioIrqNum); + NVIC_EnableIRQ(hDevice->pDevInfo->dmaIrqNum); + + /* return success */ + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Close the flash controller. + * + * @param [in] hDevice The handle to the flash controller device + * + * @return Status + * - #ADI_FEE_SUCCESS The device is closed successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore delete operation failed. + * + * Uninitialize and release an allocated flash device, and memory associated with it + * for other use. + * + * @note The user memory is released from use by the flash driver, but is not freed. + * + * @sa adi_fee_Open(). + */ +ADI_FEE_RESULT adi_fee_Close (ADI_FEE_HANDLE const hDevice) +{ + uint32_t dev; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } +#endif + + /* Destroy the semaphore */ + SEM_DELETE(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + /* Remove the device handle from the list of possible device instances */ + for (dev = 0u; dev < ADI_FEE_NUM_INSTANCES; dev++) + { + if (fee_device_info[dev].hDevice == hDevice) + { + fee_device_info[dev].hDevice = NULL; + break; + } + } + + /* NVIC disables */ + NVIC_DisableIRQ(hDevice->pDevInfo->pioIrqNum); + NVIC_DisableIRQ(hDevice->pDevInfo->dmaIrqNum); + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Register an application-defined callback function. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] pfCallback A pointer to an application-supplied calllback function + * which is called to notify the application of device-related + * events. A value of NULL disables driver callbacks. + * @param [in] pCBParam An application-supplied callback parameter which will be passed + * back to the callback function. + * + * @return Status + * - #ADI_FEE_SUCCESS The callback is registered successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] A flash write operation is in progress and + * the callback registration is ignored. + * + * Links the user-provided callback function into the #adi_fee_SubmitBuffer() API such that + * rather than polling for buffer completion (with #adi_fee_IsBufferAvailable()) and eventually + * reacquiring the buffer (with #adi_fee_GetBuffer()), the user can simply register a callback + * function that will be called upon buffer completion with no further action needed.\n + * + * Error conditions are also passed to the callback, including DMA errors if DMA is active. Make sure + * to always check the event value passed to the callback, just as the various API return codes should + * always be checked.\n + * + * However, callbacks are always made in context of an interrupt, so applications are strongly encouraged + * to exit the callback as quickly as possible so normal interrupt processing is disrupted as little as + * possible. This is also an argument for not using callbacks at at all. + * + * @note When using callbacks to reacquire buffers, DO NOT use the #adi_fee_GetBuffer() API. The two + * methods are mutually exclusive. + * + * @sa adi_fee_SubmitBuffer(). + * @sa adi_fee_IsBufferAvailable(). + * @sa adi_fee_GetBuffer(). + */ +ADI_FEE_RESULT adi_fee_RegisterCallback (ADI_FEE_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void* const pCBParam) +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } +#endif + + /* Set the callback function and param in the device */ + hDevice->pfCallback = pfCallback; + hDevice->pCBParam = pCBParam; + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Erase the given range of (2kB) page(s) within the flash user space memory. This is a blocking call. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] nPageNumStart Start page number. + * @param [in] nPageNumEnd End page number. + * @param [in,out] pHwErrors Pointer to user location into which any flash hardware errors are reported. + * + * @return Status + * - #ADI_FEE_SUCCESS The page(s) is(are) cleared successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] The page(s) number(s) is(are) incorrect. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is in progress. + * - #ADI_FEE_ERR_HW_ERROR_DETECTED An internal flash controller hardware error was detected. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * + * Erases entire page(s). Callers are expected to save/restore any partial page data prior + * to erasure, as needed. Translate literal flash addresses into flash start and end page + * numbers with #adi_fee_GetPageNumber(). + * + * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code. + * Flash hardware error details are written to the location pointed to by the pHwErrors parameter. + * Hardware error details may be decoded according to the flash controller status register ("STAT") + * bit-map, documented in the Hardware Reference Manual (HRM). + * + * @sa adi_fee_GetPageNumber(). + * @sa adi_fee_MassErase(). + */ +ADI_FEE_RESULT adi_fee_PageErase (ADI_FEE_HANDLE const hDevice, uint32_t const nPageNumStart, uint32_t const nPageNumEnd, uint32_t* const pHwErrors) + +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + + uint32_t page; + +#ifdef ADI_DEBUG + + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + uint32_t nRelAddrStart = (nPageNumStart << FEE_PAGE_SHIFT); + uint32_t nRelAddrStop = (nPageNumEnd << FEE_PAGE_SHIFT); + + if ( (nPageNumStart > nPageNumEnd) + || (nRelAddrStart >= FEE_FLASH_SIZE) + || (nRelAddrStop >= FEE_FLASH_SIZE)) + { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif /* defined (ADI_DEBUG) */ + + for (page = nPageNumStart; page <= nPageNumEnd; page++) + { + /* Wait until not busy */ + BusyWait(hDevice, (BITM_FLCC_STAT_CMDBUSY | BITM_FLCC_STAT_WRCLOSE)); + + /* Set the page address */ + hDevice->pDev->PAGE_ADDR0 = (page << FEE_PAGE_SHIFT); + + /* Issue a page erase command */ + result = SendCommand (hDevice, ENUM_FLCC_CMD_ERASEPAGE); + + /* block on command */ + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + if (result != ADI_FEE_SUCCESS) { + break; + } + } + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->feeError; + if (0u != hDevice->feeError) { + /* return the HW error return code */ + return ADI_FEE_ERR_HW_ERROR_DETECTED; + } + + return result; +} + + +/** + * @brief Erase the entire flash user space memory. This is a blocking call. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in,out] pHwErrors Pointer to user location into which any flash hardware errors are reported. + * + * @return Status + * - #ADI_FEE_SUCCESS The flash is cleared successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is in progress. + * - #ADI_FEE_ERR_HW_ERROR_DETECTED An internal flash controller hardware error was detected. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * + * @note Do not call mass erase on or from code that is running from flash. Doing so will leave + * an indeterminate machine state. + * + * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code. + * Flash hardware error details are written to the location pointed to by the pHwErrors parameter. + * Hardware error details may be decoded according to the flash controller status register ("STAT") + * bit-map, documented in the Hardware Reference Manual (HRM). + * + * @sa adi_fee_PageErase(). + */ +ADI_FEE_RESULT adi_fee_MassErase (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors) +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } +#endif + + /* Call the mass erase command */ + result = SendCommand (hDevice, ENUM_FLCC_CMD_MASSERASE); + + /* block on command */ + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->feeError; + if (0u != hDevice->feeError) { + /* return the HW error return code */ + return ADI_FEE_ERR_HW_ERROR_DETECTED; + } + + return result; +} + + +/** + * @brief Perform a blocking flash data write operation. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] pTransaction Pointer to a user-defined control block describing the data to be transferred, containing: + * - pWriteAddr; Pointer to a 64-bit-aligned destination address in flash. + * - pWriteData; Pointer to a 32-bit-aligned source data buffer in user memory. + * - nSize; Number of bytes to write (must be an integral multiple of 8). + * - bUseDma; Flag controlling use of DMA to perform the write. + * @param [in,out] pHwErrors Pointer to user location into which any flash hardware errors are reported. + * + * @return Status + * - #ADI_FEE_SUCCESS The buffer is successfully written to the flash. + * - #ADI_FEE_ERR_ALIGNMENT [D] The flash write source data pointer is misaligned. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Buffer size is not a multiple of 8-bytes (or too large for DMA). + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * - #ADI_FEE_ERR_BUFFER_ERR Error occurred in processing the buffer. + * - #ADI_FEE_ERR_DEVICE_BUSY The flash controller is busy. + * - #ADI_FEE_ERR_DMA_BUS_FAULT A runtime DMA bus fault was detected. + * - #ADI_FEE_ERR_DMA_INVALID_DESCR A runtime DMA invalid descriptor was detected. + * - #ADI_FEE_ERR_DMA_UNKNOWN_ERROR An unknown runtime DMA error was detected. + * - #ADI_FEE_ERR_HW_ERROR_DETECTED An internal flash controller hardware error was detected. + * - #ADI_FEE_ERR_NO_DATA_TO_TRANSFER Transfer ran out of write data unexpectedly. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * + * Perform a blocking flash data write operation. This API does not return until the write operation is completed. + * + * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code. + * Flash hardware error details are written to the location pointed to by the pHwErrors parameter. + * Hardware error details may be decoded according to the flash controller status register ("STAT") + * bit-map, documented in the Hardware Reference Manual (HRM). Flash hardware errors are separate + * and distinct from DMA errors, which have separate and distinct return codes, as described above. + */ +ADI_FEE_RESULT adi_fee_Write (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction, uint32_t* const pHwErrors) +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + /* check address is 64-bit aligned and data pointer is 32-bit aligned */ + if ( (((uint32_t)pTransaction->pWriteAddr & 0x7u) != 0u) || ((((uint32_t)pTransaction->pWriteData) & 0x3u) != 0u) ) + { + return ADI_FEE_ERR_ALIGNMENT; + } + + /* make sure size is a multiple of 8 */ + if ((pTransaction->nSize & 0x7u) != 0u) { + return ADI_FEE_ERR_INVALID_PARAM; + } + + if (true == pTransaction->bUseDma) { + /* check for max DMA units (32-bit chunks, i.e., 4 bytes at a whack) */ + if (DMA_TRANSFER_LIMIT < (pTransaction->nSize / sizeof(uint32_t))) { + return ADI_FEE_ERR_INVALID_PARAM; + } + } +#endif + + /* reset submit/get safeguard flag */ + hDevice->bSubmitCalled = false; + + /* Fill in the transfer params */ + hDevice->pNextWriteAddress = pTransaction->pWriteAddr; + hDevice->pNextReadAddress = pTransaction->pWriteData; + hDevice->nRemainingBytes = pTransaction->nSize; + hDevice->bUseDma = pTransaction->bUseDma; + + /* Initiate a transfer */ + result = InitiateTransfer (hDevice); + + /* Wait for the completed transfer */ + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + /* issue any flash DMA error status codes... */ + if (0u != hDevice->dmaError) { + return hDevice->dmaError; + } + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->feeError; + if (0u != hDevice->feeError) { + /* return the HW error return code */ + return ADI_FEE_ERR_HW_ERROR_DETECTED; + } + + /* Check for errors in buffer write */ + if (hDevice->nRemainingBytes != 0u) { + return ADI_FEE_ERR_BUFFER_ERR; + } + + return result; +} + + +/** + * @brief Submit a non-blocking flash data write operation for background processing. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] pTransaction Pointer to a user-defined control block describing the data to be transferred, containing: + * - pWriteAddr; Pointer to a 64-bit-aligned destination address in flash. + * - pWriteData; Pointer to a 32-bit-aligned source data buffer in user memory. + * - nSize; Number of bytes to write (must be an integral multiple of 8). + * - bUseDma; Flag controlling use of DMA to perform the write. + * + * @return Status + * - #ADI_FEE_SUCCESS The buffer is successfully written to the flash. + * - #ADI_FEE_ERR_ALIGNMENT [D] The flash write source data pointer is misaligned. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Buffer size is not a multiple of 8-bytes (or too large for DMA). + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * - #ADI_FEE_ERR_BUFFER_ERR Error occurred in processing the buffer. + * - #ADI_FEE_ERR_DEVICE_BUSY The flash controller is busy. + * - #ADI_FEE_ERR_NO_DATA_TO_TRANSFER Transfer ran out of write data unexpectedly. + * + * Submit a flash data write transaction. This is a non-blocking function which returns immediately. + * The application may either: poll for transaction completion through the non-blocking #adi_fee_IsBufferAvailable() + * API, and/or await transaction completion through the blocking mode #adi_fee_GetBuffer() API. If an application + * callback has been registered, the application is advised of completion status through the callback. + * + * @note If using callback mode, DO NOT USE the #adi_fee_GetBuffer() API, which are mutually exclusive protocols. + * + * @sa adi_fee_IsBufferAvailable(). + * @sa adi_fee_GetBuffer(). + */ +ADI_FEE_RESULT adi_fee_SubmitBuffer (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction) +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + /* check address is 64-bit aligned and data pointer is 32-bit aligned */ + if ( (((uint32_t)pTransaction->pWriteAddr & 0x7u) != 0u) || ((((uint32_t)pTransaction->pWriteData) & 0x3u) != 0u) ) + { + return ADI_FEE_ERR_ALIGNMENT; + } + + /* make sure size is a multiple of 8 */ + if ((pTransaction->nSize & 0x7u) != 0u) { + return ADI_FEE_ERR_INVALID_PARAM; + } + + if (true == pTransaction->bUseDma) { + /* check for max DMA units (32-bit channel width means 4 bytes at a whack) */ + if (DMA_TRANSFER_LIMIT < (pTransaction->nSize / sizeof(uint32_t))) { + return ADI_FEE_ERR_INVALID_PARAM; + } + } +#endif + + /* set submit/get safeguard flag */ + hDevice->bSubmitCalled = true; + + /* Fill in the transfer params */ + hDevice->pNextWriteAddress = pTransaction->pWriteAddr; + hDevice->pNextReadAddress = pTransaction->pWriteData; + hDevice->nRemainingBytes = pTransaction->nSize; + hDevice->bUseDma = pTransaction->bUseDma; + + /* initiate a transfer */ + result = InitiateTransfer (hDevice); + + /* no pend here... just return */ + + return result; +} + + +/** + * @brief Non-blocking check if a write transaction complete. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in,out] pbCompletionState True if transfer is complete, false if not. + * + * @return Status + * - #ADI_FEE_SUCCESS The status of buffer is returned successfully. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Pointer passed is NULL. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY No matching buffer submit call found. + * + * Check if a non-blocking write transaction that was submitted via adi_fee_SubmitBuffer() is complete. + * + * @sa adi_fee_SubmitBuffer(). + * @sa adi_fee_GetBuffer(). + */ +ADI_FEE_RESULT adi_fee_IsBufferAvailable (ADI_FEE_HANDLE const hDevice, bool* const pbCompletionState) + +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + if (pbCompletionState == NULL) { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* fail if not a submit-based transaction */ + if (false == hDevice->bSubmitCalled) { + return ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY; + } + + if (true == hDevice->bTransferInProgress) { + *pbCompletionState = false; + } else { + *pbCompletionState = true; + } + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Blocking mode call to await transaction completion. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in,out] pHwErrors Pointer to user location into which any flash hardware errors are reported. + * + * @return Status + * - #ADI_FEE_SUCCESS The buffer is successfully written to the flash. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_BUFFER_ERR Error occurred in processing the buffer. + * - #ADI_FEE_ERR_DMA_BUS_FAULT A runtime DMA bus fault was detected. + * - #ADI_FEE_ERR_DMA_INVALID_DESCR A runtime DMA invalid descriptor was detected. + * - #ADI_FEE_ERR_DMA_UNKNOWN_ERROR An unknown runtime DMA error was detected. + * - #ADI_FEE_ERR_HW_ERROR_DETECTED An internal flash controller hardware error was detected. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * - #ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY No matching buffer submit call found. + * + * This function blocks until a previously-submitted flash write operation has completed. + * + * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code. + * Flash hardware error details are written to the location pointed to by the pHwErrors parameter. + * Hardware error details may be decoded according to the flash controller status register ("STAT") + * bit-map, documented in the Hardware Reference Manual (HRM). + * + * @sa adi_fee_SubmitBuffer(). + * @sa adi_fee_IsBufferAvailable(). + */ +ADI_FEE_RESULT adi_fee_GetBuffer (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors) + +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } +#endif + + /* fail if not a submit-based transaction */ + if (false == hDevice->bSubmitCalled) { + return ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY; + } + + /* Pend for the semaphore */ + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + /* issue any flash DMA error status codes... */ + if (0u != hDevice->dmaError) { + return hDevice->dmaError; + } + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->feeError; + if (0u != hDevice->feeError) { + /* return the HW error return code */ + return ADI_FEE_ERR_HW_ERROR_DETECTED; + } + + /* Check for errors in buffer write or transfer still in progress */ + if ((0u != hDevice->nRemainingBytes) || (true == hDevice->bTransferInProgress)) { + return ADI_FEE_ERR_BUFFER_ERR; + } + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Get the (2kB) page number within which a flash address resides. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] nAddress The flash address for which the page number is required. + * @param [in,out] pnPageNum Pointer to a variable into which the page number corresponding + * to the provided flash address is written. + * + * @return Status + * - #ADI_FEE_SUCCESS The page number is returned successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Parameter(s) are invalid. + * + * Translates a literal flash address into a page number for use with various page-based flash operations. + * + * @sa adi_fee_PageErase(). + * @sa adi_fee_VerifySignature(). + * @sa adi_fee_ConfigECC(). + * @sa adi_fee_GetBlockNumber(). + * + */ +ADI_FEE_RESULT adi_fee_GetPageNumber (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnPageNum) +{ +#ifdef ADI_DEBUG + + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + if ( (pnPageNum == NULL) + || (nAddress >= FEE_FLASH_SIZE)) + { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Set the page number for the given flash address */ + *pnPageNum = (nAddress >> FEE_PAGE_SHIFT); + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Get the (16kB) block number within which a flash address resides. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] nAddress The flash address for which the block number is required. + * @param [in,out] pnBlockNum Pointer to a variable into which the block number corresponding + * to the provided flash address is written. + * + * @return Status + * - #ADI_FEE_SUCCESS The block number is returned successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Parameter(s) are invalid. + * + * Translates a literal flash address into a block number for use with setting flash write protection on a block. + * + * @sa adi_fee_WriteProtectBlock(). + * @sa adi_fee_GetPageNumber(). + */ +ADI_FEE_RESULT adi_fee_GetBlockNumber (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnBlockNum) +{ +#ifdef ADI_DEBUG + + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + if ( (pnBlockNum == NULL) + || (nAddress >= FEE_FLASH_SIZE)) + { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Set the block number */ + *pnBlockNum = (nAddress >> FEE_BLOCK_SHIFT); + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Generate the CRC signature for a range of flash data page(s). This is a blocking call. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] nStartPage The lower page number of the signature range. + * @param [in] nEndPage The upper page number of the signature range. + * @param [in,out] pSigResult Pointer to a variable into which the computed signature is stored. + * @param [in,out] pHwErrors Pointer to user location into which any flash hardware errors are reported. + * + * @return Status + * - #ADI_FEE_SUCCESS The signature is verified successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] The page(s) number(s) is(are) incorrect. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] A flash write operation is in progress. + * - #ADI_FEE_ERR_HW_ERROR_DETECTED An internal flash controller hardware error was detected. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * + * Compute and return a CRC over a range of contiguous whole flash memory pages(s). The computed CRC + * signature may subsequently be written into the most-significant word of the region over which the + * signature was calculated. This is done in context of enabling bootloader enforcement of CRC signature + * verification during system startup. See HRM for signature storage programming requirements and + * bootloader operation. + * + * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code. + * Flash hardware error details are written to the location pointed to by the pHwErrors parameter. + * Hardware error details may be decoded according to the flash controller status register ("STAT") + * bit-map, documented in the Hardware Reference Manual (HRM). + * + * @sa adi_fee_GetPageNumber(). + */ +ADI_FEE_RESULT adi_fee_VerifySignature (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, uint32_t const nEndPage, uint32_t* const pSigResult, uint32_t* const pHwErrors) + +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + if ( (pSigResult == NULL) + || (nStartPage > nEndPage) + || (nStartPage >= FEE_MAX_NUM_PAGES) + || (nEndPage >= FEE_MAX_NUM_PAGES) + ) + { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Wait until not busy */ + BusyWait (hDevice, (BITM_FLCC_STAT_CMDBUSY | BITM_FLCC_STAT_WRCLOSE)); + + /* Set the lower and upper page */ + hDevice->pDev->PAGE_ADDR0 = nStartPage << FEE_PAGE_SHIFT; + hDevice->pDev->PAGE_ADDR1 = nEndPage << FEE_PAGE_SHIFT; + + /* Do a SIGN command */ + result = SendCommand(hDevice, ENUM_FLCC_CMD_SIGN); + + /* block on command */ + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + /* Return the signature to the application */ + if (ADI_FEE_SUCCESS == result) { + *pSigResult = hDevice->pDev->SIGNATURE; + } else { + *pSigResult = 0u; + } + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->feeError; + if (0u != hDevice->feeError) { + /* return the HW error return code */ + return ADI_FEE_ERR_HW_ERROR_DETECTED; + } + + return result; +} + + +/** + * @brief Set write protection on an (16kB) block. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] nBlockNum The block number. + * + * @return Status + * - #ADI_FEE_SUCCESS The block is write protected successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Block number is invalid. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * + * Assert memory write-protection for specified block. Note that only entire blocks are protectable, + * with each block spanning 8 pages. + * + * @note Blocks may only be write-protected during user run-time code. Unprotecting is only + * possible with a power-on-reset or a mass erase; write-protection is not otherwise clearable. + * + * @warning Flash-based code that write-protects blocks will cause the write-protection (and data at + * time of write-protect assertion) to apparently not clear... even after a mass erase or power-on-reset. + * This apparently "stuck" write-protection results from the flash-based write-protect code running + * after reset (as usual), but still prior to the debugger halting the target through the debug + * interrupt. The debugger target halt occurs WELL AFTER the flash code has already run, thereby + * relocking the block and making it appear the write-protection was never reset. This can be difficult + * Catch-22 situation to recover from, requiring repeated hardware resets and reflashing new code that + * does not assert the write-protection. + * + * @sa adi_fee_GetBlockNumber(). + */ +ADI_FEE_RESULT adi_fee_WriteProtectBlock (ADI_FEE_HANDLE const hDevice, uint32_t const nBlockNum) + +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + if (nBlockNum > FEE_MAX_NUM_BLOCKS) { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Set the write protection (by clearing the bit) for the given block */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + CLR_BITS (hDevice->pDev->WRPROT, 1u << nBlockNum); + hDevice->pDev->KEY = 0u; + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Sleep or awake the flash controller. This is a blocking call. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] bSleep 'true' to enable to sleep the flash device + * and 'false' to wake up the device. + * + * @return Status + * - #ADI_FEE_SUCCESS The flash controller is moved to sleep/wake + * up sate successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * + * Places the flash controller into a low-power sleep mode - see details in Hardware Reference Manual (HRM). + * Default wakeup time is approximately 5us, and is configurable with static configuration parameter + * ADI_FEE_CFG_PARAM1_TWK in adi_flash_config.h file. + */ +ADI_FEE_RESULT adi_fee_Sleep (ADI_FEE_HANDLE const hDevice, bool const bSleep) +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } +#endif + + /* TODO: Check that IDLE can take the controller + * out of sleep + */ + + if (true == bSleep) { + result = SendCommand (hDevice, ENUM_FLCC_CMD_SLEEP); + } else { + result = SendCommand (hDevice, ENUM_FLCC_CMD_IDLE); + } + + /* block on command */ + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + return result; +} + + +/** + * @brief Forcefully ABORT an ongoing flash operation. This is a blocking call. + * + * @param [in] hDevice The handle to the flash controller device. + * + * @return Statuus + * - #ADI_FEE_SUCCESS The command is successfully aborted. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * + * @warning Use this command sparingly and as a last resort to satisfy critical + * time-sensitive events. Aborting any flash command results in prematurely ending the + * current flash access and may result in corrupted flash data. + * + * @sa adi_fee_GetAbortAddr(). + */ +ADI_FEE_RESULT adi_fee_Abort (ADI_FEE_HANDLE const hDevice) + +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } +#endif + /* Issue the command (abort is keyed) directly */ + /* (avoid SendCommand() here, as it does a busy wait, which may not clear if we're in a recovery mode) */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + hDevice->pDev->CMD = ENUM_FLCC_CMD_ABORT; + hDevice->pDev->KEY = 0u; + + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Get the address of recently aborted write command. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in,out] pnAddress Pointer to which the address is written. + * + * @return Status + * - #ADI_FEE_SUCCESS The abort address is retrieved successfully + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid + * - #ADI_FEE_ERR_INVALID_PARAM [D] Pointer passed is NULL + * + * Users may use this result to determine the flash location(s) affected by a write abort command. + * Subsequent flash commands invalidate the write abort address register. + * + * + * @sa adi_fee_Abort(). + */ +ADI_FEE_RESULT adi_fee_GetAbortAddr (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress) +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + if (pnAddress == NULL) { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Write the address of the last write abort to the pointer + * supplied by the application + */ + *pnAddress = hDevice->pDev->WR_ABORT_ADDR; + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Configure ECC start page and enablement. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] nStartPage The start page for which ECC will be performed. + * @param [in] bInfoECCEnable Info space ECC enable: + * - 'true' to enable info space ECC, or + * - 'false' to disable info space ECC. + * + * @return Status + * - #ADI_FEE_SUCCESS The ECC was configured successfully + * - #ADI_FEE_ERR_INVALID_PARAM [D] Start page is invalid + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * + * @note The settings this API manages are very likely not needed to be modified dynamically (at run-time). + * If so, consider using the static configuration equivalents (see adi_flash_config.h) in lieu of + * this API... which will reduce the resulting code image footprint through linker elimination. + * + * @warning This API leaves user space ECC disabled. Use #adi_fee_EnableECC() to manage ECC enable/disable. + * + * @sa adi_fee_EnableECC(). + * @sa adi_fee_ConfigECCEvents(). + * @sa adi_fee_GetECCErrAddr(). + * @sa adi_fee_GetECCCorrections(). + */ +ADI_FEE_RESULT adi_fee_ConfigECC (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, bool const bInfoECCEnable) +{ + uint32_t nRelAddress = nStartPage << FEE_PAGE_SHIFT; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + if (nStartPage >= FEE_MAX_NUM_PAGES) { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Clear the ECC config bits */ + CLR_BITS (hDevice->pDev->ECC_CFG, (BITM_FLCC_ECC_CFG_PTR | BITM_FLCC_ECC_CFG_INFOEN)); + + /* Set the start page address in the ECC Cfg register */ + hDevice->pDev->ECC_CFG |= (nRelAddress & BITM_FLCC_ECC_CFG_PTR); + + /* enable ECC on info space... if requested */ + if (true == bInfoECCEnable) { + SET_BITS (hDevice->pDev->ECC_CFG, BITM_FLCC_ECC_CFG_INFOEN); + } + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Enable/Disable user space ECC for the device. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] bEnable User space ECC enable: + * - 'true' to enable user space ECC, or + * - 'false' to disable user space ECC. + * + * @return Status + * - #ADI_FEE_SUCCESS The ECC is enabled/disabled successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * + * Manage enablement of user space ECC function. + * + * @note The settings this API manages are very likely not needed to be modified dynamically (at run-time). + * If so, consider using the static configuration equivalents (see adi_flash_config.h) in lieu of + * this API... which will reduce the resulting code image footprint through linker elimination. + * + * @sa adi_fee_ConfigECC(). + * @sa adi_fee_ConfigECCEvents(). + * @sa adi_fee_GetECCErrAddr(). + * @sa adi_fee_GetECCCorrections(). + */ +ADI_FEE_RESULT adi_fee_EnableECC (ADI_FEE_HANDLE const hDevice, bool const bEnable) +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } +#endif + + /* manage flash ECC enable */ + if (true == bEnable) { + SET_BITS(hDevice->pDev->ECC_CFG, BITM_FLCC_ECC_CFG_EN); + } else { + CLR_BITS(hDevice->pDev->ECC_CFG, BITM_FLCC_ECC_CFG_EN); + } + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Confifure ECC event response. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] eEvent ECC event - Either error or correction event. + * @param [in] eResponse The response to the eEvent - One of none, bus error, or interrupt. + * + * @return Status + * - #ADI_FEE_SUCCESS The ECC events are configured successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Parameters are invalid. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * + * Configures two major aspects of ECC event response: + * - On ECC (2-bit) Error events, generate one of: no response, bus error, or flash interrupt. + * - On ECC (1-bit) Correction events, generate one of: no response, bus error, or flash interrupt. + * + * @note The settings this API manages are very likely not needed to be modified dynamically (at run-time). + * If so, consider using the static configuration equivalents (see adi_flash_config.h) in lieu of + * this API... which will reduce the resulting code image footprint through linker elimination. + * + * @sa adi_fee_ConfigECC(). + * @sa adi_fee_EnableECC(). + * @sa adi_fee_GetECCErrAddr(). + * @sa adi_fee_GetECCCorrections(). + */ +ADI_FEE_RESULT adi_fee_ConfigECCEvents (ADI_FEE_HANDLE const hDevice, ADI_FEE_ECC_EVENT_TYPE const eEvent, ADI_FEE_ECC_RESPONSE const eResponse) + +{ + uint32_t nBitMask; + int32_t nBitPos; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + /* Check the function parameters */ + if ( ( (eEvent != ADI_FEE_ECC_EVENT_TYPE_ERROR) + && (eEvent != ADI_FEE_ECC_EVENT_TYPE_CORRECT)) + + || ( (eResponse != ADI_FEE_ECC_RESPONSE_NONE) + && (eResponse != ADI_FEE_ECC_RESPONSE_BUS_ERROR) + && (eResponse != ADI_FEE_ECC_RESPONSE_IRQ)) + ) + { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Select the correct bit mask and bit pos for the event type */ + if (eEvent == ADI_FEE_ECC_EVENT_TYPE_ERROR) { + nBitMask = BITM_FLCC_IEN_ECC_ERROR; + nBitPos = BITP_FLCC_IEN_ECC_ERROR; + } else { + nBitMask = BITM_FLCC_IEN_ECC_CORRECT; + nBitPos = BITP_FLCC_IEN_ECC_CORRECT; + } + + /* clear the bits */ + CLR_BITS (hDevice->pDev->IEN, nBitMask); + + /* set the response */ + SET_BITS (hDevice->pDev->IEN, ((uint32_t)eResponse) << nBitPos); + + return ADI_FEE_SUCCESS; +} + + +/** + * `@brief Get the address for which the ECC event is detected. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in,out] pnAddress Pointer to which the address is written. + * + * @return Status + * - #ADI_FEE_SUCCESS The ECC error address is retrieved successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Parameters are invalid. + * + * Returns the address of the first ECC error or correction event to generate an + * interrupt since the last time ECC status bits were cleared (or since reset). + * + * @sa adi_fee_ConfigECC(). + * @sa adi_fee_EnableECC(). + * @sa adi_fee_ConfigECCEvents(). + * @sa adi_fee_GetECCCorrections(). + */ +ADI_FEE_RESULT adi_fee_GetECCErrAddr (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress) + +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + if (pnAddress == NULL) { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Write the address of the last ECC error/correction */ + *pnAddress = hDevice->pDev->ECC_ADDR; + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Get the number of 1-bit error corrections. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in,out] pnNumCorrections Pointer to which the number of corrections are written. + * + * @return Status + * - #ADI_FEE_SUCCESS The number of ECC corrections are successfully retrieved. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Parameters are invalid. + * + * See HRM for details on how current ECC configuration affects this reporting. + * + * @sa adi_fee_ConfigECC(). + * @sa adi_fee_EnableECC(). + * @sa adi_fee_ConfigECCEvents(). + * @sa adi_fee_GetECCErrAddr(). + */ +ADI_FEE_RESULT adi_fee_GetECCCorrections (ADI_FEE_HANDLE const hDevice, uint32_t* const pnNumCorrections) +{ + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + if (pnNumCorrections == NULL) { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Get the number of ECC Error corrections */ + *pnNumCorrections = (hDevice->pDev->STAT & BITM_FLCC_STAT_ECCERRCNT) >> BITP_FLCC_STAT_ECCERRCNT; + + return ADI_FEE_SUCCESS; +} + + +/*======== L O C A L F U N C T I O N D E F I N I T I O N S ========*/ + + +/* Send a command to the flash controller... bot don't block on it... + */ +static ADI_FEE_RESULT SendCommand (ADI_FEE_HANDLE const hDevice, uint32_t const cmd) +{ + /* Wait for the flash to be free */ + BusyWait (hDevice, (BITM_FLCC_STAT_CMDBUSY | BITM_FLCC_STAT_WRCLOSE)); + + /* Clear the command completion status bit + * by acknowledging it + */ + hDevice->pDev->STAT = BITM_FLCC_STAT_CMDCOMP; + + /* Enable command-complete and command-fail interrupt */ + SET_BITS(hDevice->pDev->IEN, (BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL)); + + /* Issue the command (most commands are keyed) */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + hDevice->pDev->CMD = cmd; + hDevice->pDev->KEY = 0u; + + return ADI_FEE_SUCCESS; +} + + +static ADI_FEE_RESULT InitiatePioTransfer (ADI_FEE_HANDLE const hDevice) +{ + + /* use PIO interrupt mode in non-burst-mode (burst-mode only spans 256-bytes). + Initiate the 1st write here, then let the interrupt handler feed + the remaining data as we process "almost-complete" interrupts. + */ + + /* write the 1st 64-bits of data */ + if (0u != hDevice->nRemainingBytes) { + + /* enable command interrupts */ + SET_BITS (hDevice->pDev->IEN, (BITM_FLCC_IEN_WRALCMPLT | BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL)); + + /* set initial write address*/ + hDevice->pDev->KH_ADDR = (uint32_t)hDevice->pNextWriteAddress; + hDevice->pNextWriteAddress += 2; + + /* set key-hole data registers */ + hDevice->pDev->KH_DATA0 = *hDevice->pNextReadAddress; + hDevice->pNextReadAddress++; + hDevice->pDev->KH_DATA1 = *hDevice->pNextReadAddress; + hDevice->pNextReadAddress++; + hDevice->nRemainingBytes -= sizeof(uint64_t); + + /* write the command register which launches the burst write */ + hDevice->pDev->CMD = ENUM_FLCC_CMD_WRITE; + + } else { + return ADI_FEE_ERR_NO_DATA_TO_TRANSFER; + } + + return ADI_FEE_SUCCESS; +} + + +/* DMA Transfer to FIFO */ +static ADI_FEE_RESULT InitiateDmaTransfer (ADI_FEE_HANDLE const hDevice) +{ + ADI_DCC_TypeDef* pCCD = pPrimaryCCD; /* pointer to primary DMA descriptor array */ + + if (0u != hDevice->nRemainingBytes) { + + /* local channel number */ + uint16_t chan = hDevice->pDevInfo->dmaChanNum; + + /* disable endpointer decrement modes */ + pADI_DMA0->SRCADDR_CLR = 1u << chan; + pADI_DMA0->DSTADDR_CLR = 1u << chan; + + /* enable the channel */ + pADI_DMA0->EN_SET = 1u << chan; + + /* allow flash to request DMA service */ + pADI_DMA0->RMSK_CLR = 1u << chan; + + /* activate primary descriptor */ + pADI_DMA0->ALT_CLR = 1u << chan; + + /* Note: DMA width is 32-bit for the flash controller, but flash writes require + 64-bit writes at a whack. Set DMA R_Power (bus rearbitration rate) to two so + we get two uninterrupted 32-bit DMA writes to the flash with each DMA transfer. + */ + + /* set DMA source endpoint */ + pCCD += chan; /* offset descriptor pointer to flash channel */ + pCCD->DMASRCEND = (uint32_t)hDevice->pNextReadAddress + hDevice->nRemainingBytes - sizeof(uint32_t); + + /* set DMA destination endpoint (no increment) */ + pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->KH_DATA1; + + /* set the initial write address */ + hDevice->pDev->KH_ADDR = (uint32_t)hDevice->pNextWriteAddress; + + /* set the DMA Control Data Configuration register */ + pCCD->DMACDC = + ( ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) + | ((uint32_t)ADI_DMA_INCR_4_BYTE << DMA_BITP_CTL_SRC_INC) + | ((uint32_t)ADI_DMA_WIDTH_4_BYTE << DMA_BITP_CTL_SRC_SIZE) + | ((uint32_t)ADI_DMA_RPOWER_2 << DMA_BITP_CTL_R_POWER) + | (uint32_t)((hDevice->nRemainingBytes/sizeof(uint32_t) - 1u) << DMA_BITP_CTL_N_MINUS_1) + | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) ); + + /* set auto-increment and DMA enable bits, launching transder */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + SET_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN)); + hDevice->pDev->KEY = 0u; + + } else { + return ADI_FEE_ERR_NO_DATA_TO_TRANSFER; + } + + return ADI_FEE_SUCCESS; +} + + +/* Initiate transfer */ +static ADI_FEE_RESULT InitiateTransfer (ADI_FEE_HANDLE const hDevice) +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + + /* If a transfer is in progress or if the pending buffers are empty + * the return as there is nothing to be done now + */ + if (true == hDevice->bTransferInProgress) + { + return ADI_FEE_ERR_DEVICE_BUSY; + } + + /* Wait for the flash to not be busy */ + BusyWait (hDevice, BITM_FLCC_STAT_CMDBUSY); + + /* clear internal errors */ + hDevice->feeError = 0u; + hDevice->dmaError = ADI_FEE_SUCCESS; + + /* Set the bool variable to signify that a transfer is in progress */ + hDevice->bTransferInProgress = true; + + /* clear any command interrupt enables */ + CLR_BITS(hDevice->pDev->IEN, (BITM_FLCC_IEN_WRALCMPLT | BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL)); + + /* clear any dangeling command-related status */ + hDevice->pDev->STAT = BITM_FLCC_STAT_WRALCOMP | BITM_FLCC_STAT_CMDCOMP | BITM_FLCC_STAT_CMDFAIL; + + /* clear auto-increment and dma enable bits */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN)); + hDevice->pDev->KEY = 0u; + + /* Call the corresponding Transfer functions */ + if (true == hDevice->bUseDma) { + result = InitiateDmaTransfer(hDevice); + } else { + result = InitiatePioTransfer(hDevice); + } + + return result; +} + + +/* hide the interrupt handlers from DoxyGen */ +/*! \cond PRIVATE */ + +/* Flash PIO interrupt handler */ +void Flash0_Int_Handler(void) +{ + ISR_PROLOG(); + + /* post flag */ + bool bPost = false; + bool bError = false; + + /* recover the driver handle */ + ADI_FEE_HANDLE hDevice = fee_device_info[0].hDevice; + +#ifdef ADI_DEBUG + /* Return if the device is not opened - spurious interrupts */ + if (hDevice == NULL) { + return; + } +#endif + + /* update status cache and clear it right away on the controller */ + hDevice->FlashStatusCopy = hDevice->pDev->STAT; + hDevice->pDev->STAT = hDevice->FlashStatusCopy; + + /* check for flash device errors */ + hDevice->feeError = (ADI_FEE_STATUS_ERROR_MASK & hDevice->FlashStatusCopy); + if (0u != hDevice->feeError) { + bError = true; + } + + /* if no errors */ + if (false == bError) { + + if (0u != (BITM_FLCC_STAT_WRALCOMP & hDevice->FlashStatusCopy)) { + + /* write-almost-complete */ + + /* if more data to write... */ + if (0u != hDevice->nRemainingBytes) { + + /* set next write the address */ + hDevice->pDev->KH_ADDR = (uint32_t)hDevice->pNextWriteAddress; + hDevice->pNextWriteAddress += 2; + + /* set next key-hole data */ + hDevice->pDev->KH_DATA0 = *hDevice->pNextReadAddress; + hDevice->pNextReadAddress++; + hDevice->pDev->KH_DATA1 = *hDevice->pNextReadAddress; + hDevice->pNextReadAddress++; + hDevice->nRemainingBytes -= sizeof(uint64_t); + + /* initiate next write */ + hDevice->pDev->CMD = ENUM_FLCC_CMD_WRITE; + + } else { + + /* no more data to write... + wait for current write-almost-complete status to transition to not busy */ + BusyWait (hDevice, BITM_FLCC_STAT_CMDBUSY); + + /* set post flag */ + bPost = true; + } + + } else if (0u != (BITM_FLCC_STAT_CMDCOMP & hDevice->FlashStatusCopy)) { + + /* command-complete */ + + /* this path is for blocking-mode commands (erase, verify, abort, etc.) */ + + /* set post flag */ + bPost = true; + + } else { + /* no other interrupt types expected */ + } + } else { + /* error(s) detected... set the post flag */ + bPost = true; + } + + /* singular post */ + if (true == bPost) { + + /* clear the command interrupt enables */ + CLR_BITS(hDevice->pDev->IEN, (BITM_FLCC_IEN_WRALCMPLT | BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL)); + + /* clear auto-increment and dma enable bits */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN)); + hDevice->pDev->KEY = 0u; + + /* mark transfer complete */ + hDevice->bTransferInProgress = false; + + /* dispatch callback (if we have one...) */ + if (0u != hDevice->pfCallback) { + if (false == bError) { + /* no error, pass success flag to callback */ + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_BUFFER_PROCESSED, (void*)NULL); + } else { + /* error condition, pass error flag and error status to callback */ + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_DEVICE_ERROR, (void*)hDevice->feeError); + } + } + + /* post the semaphore */ + SEM_POST(hDevice); + } + + ISR_EPILOG(); +} + + +/* Flash DMA interrupt handler */ +void DMA_FLASH0_Int_Handler (void) +{ + /* rtos prologue */ + ISR_PROLOG() + ; + + /* recover the driver handle */ + ADI_FEE_HANDLE hDevice = fee_device_info[0].hDevice; + + /* update status cache and clear it right away on the controller */ + hDevice->FlashStatusCopy = hDevice->pDev->STAT; + hDevice->pDev->STAT = hDevice->FlashStatusCopy; + + /* capture any hw error status */ + hDevice->feeError = (ADI_FEE_STATUS_ERROR_MASK & hDevice->FlashStatusCopy); + + /* clear auto-increment and dma enable bits */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN)); + hDevice->pDev->KEY = 0u; + + /* clear the remaining count, as it should all have gone in one swoop */ + hDevice->nRemainingBytes = 0u; + + /* mark transfer complete */ + hDevice->bTransferInProgress = false; + + /* dispatch callback (if we have one...) */ + if (0u != hDevice->pfCallback) { + + /* no errors, notify success */ + if ((0u == hDevice->feeError) && (0u == hDevice->dmaError)) { + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_BUFFER_PROCESSED, (void*)NULL); + + /* flash hardware error */ + } else if (0u == hDevice->feeError) { + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_DEVICE_ERROR, (void*)hDevice->feeError); + + /* flash dma error */ + } else if (0u == hDevice->dmaError) { + /* DMA error */ + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)hDevice->dmaError, NULL); + } else { + /* no other cases... */ + } + } + + /* post the semaphore */ + SEM_POST(hDevice); + + ISR_EPILOG(); +} + +/*! \endcond */ +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_data.c new file mode 100755 index 0000000000..88fe50cf05 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_data.c @@ -0,0 +1,116 @@ +/* + ***************************************************************************** + * @file: adi_flash_data.c + * @brief: Data declaration for Flash Device Driver + * @date: $Date$ + ***************************************************************************** + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be consciously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_FEE_DATA_C +#define ADI_FEE_DATA_C + + /*! \cond PRIVATE */ + +#include "adi_flash_def.h" +#include "adi_flash_config.h" + + +/* Stores the information about the specific device */ +static ADI_FEE_DEVICE_INFO fee_device_info [ADI_FEE_NUM_INSTANCES] = +{ + /* only one flash instance at this time */ + { pADI_FLCC0, /* Flash controller pointer */ + FLCC_EVT_IRQn, /* Flash PIO interrupt number */ + DMA0_CH15_DONE_IRQn, /* Flash DMA interrupt number */ + FLASH_CHANn, /* Flash DMA channel (15) number */ + NULL, /* Flash static config info */ + NULL /* Flash driver handle */ + }, +}; + + +/* build Flash Application configuration array */ +static ADI_FEE_CONFIG gConfigInfo[ADI_FEE_NUM_INSTANCES] = +{ + /* the one-and-only (so far) instance data for FEE0... */ + { + /* ECC interrupt enable settings (IEN register) */ + ( (ADI_FEE_CFG_ECC_ERROR_RESPONSE << BITP_FLCC_IEN_ECC_ERROR) + | (ADI_FEE_CFG_ECC_CORRECTION_RESPONSE << BITP_FLCC_IEN_ECC_CORRECT) + ), + + /* timing parameter settings (TIME_PARAM0 register) */ + ( (ADI_FEE_CFG_PARAM0_TNVH1 << BITP_FLCC_TIME_PARAM0_TNVH1) + | (ADI_FEE_CFG_PARAM0_TERASE << BITP_FLCC_TIME_PARAM0_TERASE) + | (ADI_FEE_CFG_PARAM0_TRCV << BITP_FLCC_TIME_PARAM0_TRCV) + | (ADI_FEE_CFG_PARAM0_TNVH << BITP_FLCC_TIME_PARAM0_TNVH) + | (ADI_FEE_CFG_PARAM0_TPROG << BITP_FLCC_TIME_PARAM0_TPROG) + | (ADI_FEE_CFG_PARAM0_TPGS << BITP_FLCC_TIME_PARAM0_TPGS) + | (ADI_FEE_CFG_PARAM0_TNVS << BITP_FLCC_TIME_PARAM0_TNVS) + | (ADI_FEE_CFG_PARAM0_CLKDIV << BITP_FLCC_TIME_PARAM0_DIVREFCLK) + ), + + /* more timing parameter settings (TIME_PARAM1 register) */ + ( (ADI_FEE_CFG_PARAM1_WAITESTATES << BITP_FLCC_TIME_PARAM1_WAITSTATES) + | (ADI_FEE_CFG_PARAM1_TWK << BITP_FLCC_TIME_PARAM1_TWK) + ), + + /* system interrupt abort enables (ABORT_EN_XX registers) */ + (ADI_FEE_CFG_ABORT_EN_LO), + (ADI_FEE_CFG_ABORT_EN_HI), + + /* ECC configuration register settings (ECC_CFG register) */ + (((ADI_FEE_CFG_ECC_START_PAGE << FEE_PAGE_SHIFT) & BITM_FLCC_ECC_CFG_PTR) +#if (ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE == 1u) + | (BITM_FLCC_ECC_CFG_INFOEN) +#endif +#if (ADI_FEE_CFG_ENABLE_ECC == 1u) + | (BITM_FLCC_ECC_CFG_EN) +#endif + ) + } /* end device 0 settings */ +}; + +/*! \endcond */ + + +#endif /* ADI_FEE_DATA_C */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_def.h new file mode 100755 index 0000000000..c14be74be0 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_def.h @@ -0,0 +1,181 @@ +/*! + ***************************************************************************** + @file: adi_flash_def.h + @brief: Internal Flash device driver definitions and macros + @date: $Date: 2014-11-28 01:48:03 -0500 (Fri, 28 Nov 2014) $ + ----------------------------------------------------------------------------- +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_FLASH_DEF_H +#define ADI_FLASH_DEF_H + +/*! \cond PRIVATE */ + +#include +#include + +#include + +/* fixed number of flash controllers */ +#define ADI_FEE_NUM_INSTANCES (1u) + +/* STATUS register error mask */ +#define ADI_FEE_STATUS_ERROR_MASK ( BITM_FLCC_STAT_ACCESS_MODE \ + | BITM_FLCC_STAT_CACHESRAMPERR \ + | BITM_FLCC_STAT_ECCDCODE \ + | BITM_FLCC_STAT_ECCINFOSIGN \ + | BITM_FLCC_STAT_SIGNERR \ + | BITM_FLCC_STAT_OVERLAP \ + | BITM_FLCC_STAT_ECCRDERR \ + | BITM_FLCC_STAT_ECCERRCMD \ + | BITM_FLCC_STAT_SLEEPING \ + | BITM_FLCC_STAT_CMDFAIL) + + +#if defined(__ECC__) +#define ALIGN +#define ALIGN4 _Pragma("align(4)") +#elif defined(__ICCARM__) +#define ALIGN _Pragma("pack()") +#define ALIGN4 _Pragma("pack(4)") +#elif defined (__GNUC__) +#define ALIGN _Pragma("pack()") +#define ALIGN4 _Pragma("pack(4)") +#endif + +/* Flash Size and Page/Block macros: + 512kB total user space, broken up as + 256-pages, 2kB/page + 32-blocks, 16kB/block + 8 pages/block +*/ +#define FEE_FLASH_SIZE (0x80000u) /* 512kB total */ +#define FEE_PAGE_SHIFT (11u) /* 2kB page size */ +#define FEE_BLOCK_SHIFT (14u) /* 16kB block size */ +#define FEE_MAX_NUM_PAGES (FEE_FLASH_SIZE >> FEE_PAGE_SHIFT) /* max number of pages (256) */ +#define FEE_MAX_NUM_BLOCKS (FEE_FLASH_SIZE >> FEE_BLOCK_SHIFT) /* max number of blocks (32) */ + +#if (ADI_FEE_CFG_ECC_START_PAGE >= FEE_MAX_NUM_PAGES) +#error "ADI_FEE_CFG_ECC_START_PAGE range is invalid" +#endif + + +/* INTERNAL DRIVER STATIC FUNCTION PROTOTYPES */ + +/* Send a command to the flash controller, but does no pend on it... */ +static ADI_FEE_RESULT SendCommand (ADI_FEE_HANDLE const hDevice, uint32_t const cmd); + +/* generic transfer initiator... dispatches to InitiatePioTransfer() or InitiateDmaTransfer() */ +static ADI_FEE_RESULT InitiateTransfer (ADI_FEE_HANDLE const hDevice); + +/* PIO initiator */ +static ADI_FEE_RESULT InitiatePioTransfer (ADI_FEE_HANDLE const hDevice); + +/* DMA initiator */ +static ADI_FEE_RESULT InitiateDmaTransfer (ADI_FEE_HANDLE const hDevice); + +/* interrupt handlers */ +void Flash0_Int_Handler(void); +void DMA_FLASH0_Int_Handler (void); + +/* INTERNAL DRIVER DATATYPES */ + +/* + ***************************************************************************** + * FEE Configuration structure. + *****************************************************************************/ +typedef struct __ADI_FEE_CONFIG { + uint32_t eccIrqEnables; /* ECC interrupt enables. */ + uint32_t param0; /* TIME_PARAM0 register. */ + uint32_t param1; /* TIME_PARAM1 register. */ + uint32_t abortEnableLo; /* Lower interrupt abort enables (IRQs 0-31). */ + uint32_t abortEnableHi; /* Upper interrupt abort enables (IRQs 32-63.) */ + uint32_t eccConfig; /* ECC_CFG register. */ +} ADI_FEE_CONFIG; + + +/* Flash physical device instance data */ +typedef struct __ADI_FEE_DEVICE_INFO { + + ADI_FLCC_TypeDef *pDev; /* Pointer to the physical controller. */ + IRQn_Type pioIrqNum; /* The flash controller PIO interrupt number. */ + IRQn_Type dmaIrqNum; /* The flash controller DMA interrupt number. */ + DMA_CHANn_TypeDef dmaChanNum; /* The flash controller DMA channel number. */ + ADI_FEE_CONFIG *pConfig; /* Pointer to user config info. */ + ADI_FEE_HANDLE hDevice; /* Pointer the device memory (supplied by the application). */ + +} ADI_FEE_DEVICE_INFO; + + +/* Flash driver instance data structure */ +typedef struct __ADI_FEE_DEV_DATA_TYPE { + + /* make sure to synchronize ANY size changes with ADI_FLASH_MEMORY_SIZE macro in adi_flash.h */ + + /* NOTE: "volatile" storage class on all interrupt-modified valuables */ + + /* device attributes */ + ADI_FLCC_TypeDef *pDev; /* Pointer top physical flash controller. */ + ADI_FEE_DEVICE_INFO *pDevInfo; /* Pointer to hardware device attributes. */ + + /* callback info */ + ADI_CALLBACK pfCallback; /* Registered callback function address. */ + void *pCBParam; /* Registered callback user parameter. */ + + /* internal driver state variables */ + bool bUseDma; /* DMA control flag (from user). */ + bool bSubmitCalled; /* Flag to identify if a buffer was "submitted". */ + volatile uint32_t FlashStatusCopy; /* Clop of latest flash status register. */ + volatile uint32_t feeError; /* Flash error collector. */ + volatile ADI_FEE_RESULT dmaError; /* DMA error collector. */ + volatile bool bTransferInProgress; /* Flag indicating if a transfer is in progress. */ + + /* data info */ + volatile uint32_t *pNextWriteAddress; /* Pointer to next write data in flash space. */ + volatile uint32_t *pNextReadAddress; /* Pointer to next read data in user buffer. */ + volatile uint32_t nRemainingBytes; /* Number of remaining bytes still to transfer. */ + + SEM_VAR_DECLR /* Blocking object: "Semaphore" for rtos, "bLowPowerExitFlag" for non-rtos. */ + +} ADI_FEE_DEV_DATA_TYPE; + +/*! \endcond */ + +#endif /* ADI_FLASH_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio.c new file mode 100755 index 0000000000..3725f72ead --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio.c @@ -0,0 +1,975 @@ +/* + ***************************************************************************** + @file: adi_gpio.c + @brief: GPIO device driver implementation. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ +/*****************************************************************************/ + +#include +#include +#include +#include +#include +#include "adi_gpio_def.h" + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +*/ +#pragma diag_suppress=Pm123,Pm073,Pm143,Pm140 +#endif /* __ICCARM__ */ + +/* Debug function declarations */ +#ifdef ADI_DEBUG +static bool ArePinsValid (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins); /*!< tests for pins validity */ +#endif /* ADI_DEBUG */ + + +static void CommonInterruptHandler (const ADI_GPIO_IRQ_INDEX index, const IRQn_Type eIrq); +void GPIO_A_Int_Handler(void); +void GPIO_B_Int_Handler(void); + +/*========== D A T A ==========*/ +static ADI_GPIO_DRIVER adi_gpio_Device = +{ + { + pADI_GPIO0, /* port 0 base address */ + pADI_GPIO1, /* port 1 base address */ + pADI_GPIO2, /* port 2 base address */ + pADI_GPIO3, /* port 3 base address */ + }, + + NULL +}; +/*! \endcond */ + +/*! \addtogroup GPIO_Driver GPIO Driver + * @{ + + @brief GPIO port and pin identifiers + @note The application must include drivers/gpio/adi_gpio.h to use this driver + @details The documented macros can be passed to the following functions: + - adi_gpio_OutputEnable() + - adi_gpio_PullUpEnable() + - adi_gpio_SetHigh() + - adi_gpio_SetLow() + - adi_gpio_Toggle() + - adi_gpio_SetData() + - adi_gpio_GetData() + + To control a single GPIO, these macros can be passed to the functions one + at a time. For example, to set the GPIO on port 2, pin 4 to a logical high + level, the following is used: + + 
+      adi_gpio_SetHigh(ADI_GPIO_PORT2, ADI_GPIO_PIN_4)
+
+ + Multiple GPIOs, so long as they reside on the same port, can be controlled + simultaneously. These macros can be OR-ed together and passed to the + functions. For example, to set the GPIOs on port 2, pins 3, 4 and 7 to + a logical low level, the following is used: + + 
+      adi_gpio_SetLow(ADI_GPIO_PORT2, ADI_GPIO_PIN_3 | ADI_GPIO_PIN_4 | ADI_GPIO_PIN_7)
+
+ + For the sensing, or adi_gpio_Getxxx, functions, the passed pValue parameter is written with + a packed value containing the status of the requested GPIO pins on the given port. + + If information is required for a single pin, return value can be directly used + For example to see if pin 4 on port 2 has the pull up enabled, the following is used: + adi_gpio_GetData(ADI_GPIO_PORT2, ADI_GPIO_PIN_4, &pValue) + pValue will contain the required information. + + If information is required for multiple pins, following method is required: + 
+        adi_gpio_GetData(ADI_GPIO_PORT2, (ADI_GPIO_PIN_3 | ADI_GPIO_PIN_4 | ADI_GPIO_PIN_7), &pValue)
+
+ To test if pin 4 on port 2 has pull up enabled, the following is used: + 
+        if   (pValue & ADI_GPIO_PIN_4) {
+                    the pull up is enabled for pin 4 on port 2
+        } else {
+                    the pull up is disabled for pin 4 on port 2
+        }
+
+ + */ + +/*! + @brief Initializes the GPIO functions. + + @details This function initializes the GPIO driver. This function should be called before calling any of the GPIO + driver APIs. + + @param[in] pMemory Pointer to the memory required for the driver to operate. + The size of the memory should be at least #ADI_GPIO_MEMORY_SIZE bytes. + + @param[in] MemorySize Size of the memory (in bytes) passed in pMemory parameter. + + @return Status + - ADI_GPIO_SUCCESS If successfully initialized the GPIO driver. + - ADI_GPIO_NULL_PARAMETER [D] If the given pointer to the driver memory is pointing to NULL. + - ADI_GPIO_INVALID_MEMORY_SIZE [D] If the given memory size is not sufficient to operate the driver. + + @note This function clears memory reserved for managing the callback function when it is called + for the first time. It is expected from user to call "adi_gpio_UnInit" function when the GPIO service is no longer required. + + @sa adi_gpio_UnInit +*/ +ADI_GPIO_RESULT adi_gpio_Init( + void* const pMemory, + uint32_t const MemorySize +) +{ + +#ifdef ADI_DEBUG + /* Verify the given memory pointer */ + if(NULL == pMemory) + { + return ADI_GPIO_NULL_PARAMETER; + } + /* Check if the memory size is sufficient to operate the driver */ + if(MemorySize < ADI_GPIO_MEMORY_SIZE) + { + return ADI_GPIO_INVALID_MEMORY_SIZE; + } + assert(ADI_GPIO_MEMORY_SIZE == sizeof(ADI_GPIO_DEV_DATA)); +#endif + + /* Only initialize on 1st init call, i.e., preserve callbacks on multiple inits */ + if (NULL == adi_gpio_Device.pData) + { + uint32_t i; + + adi_gpio_Device.pData = (ADI_GPIO_DEV_DATA*)pMemory; + + /* Initialize the callback table */ + for (i = 0u; i < ADI_GPIO_NUM_INTERRUPTS; i++) + { + adi_gpio_Device.pData->CallbackTable[i].pfCallback = NULL; + adi_gpio_Device.pData->CallbackTable[i].pCBParam = NULL; + } + + /* Enable the group interrupts */ + NVIC_EnableIRQ(SYS_GPIO_INTA_IRQn); + NVIC_EnableIRQ(SYS_GPIO_INTB_IRQn); + } + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Un-initialize the GPIO driver. + + @details Terminates the GPIO functions, leaving everything unchanged. + + @return Status + - #ADI_GPIO_SUCCESS if successfully uninitialized + - #ADI_GPIO_NOT_INITIALIZED [D] if not yet initialized + + @sa adi_gpio_Init +*/ +ADI_GPIO_RESULT adi_gpio_UnInit(void) +{ + +#ifdef ADI_DEBUG + /* IF (not initialized) */ + if (NULL == adi_gpio_Device.pData) + { + /* return error if not initialized */ + return (ADI_GPIO_NOT_INITIALIZED); + } +#endif + + /* Clear the data pointer */ + adi_gpio_Device.pData = NULL; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Group the pins for the given group interrupt. + + @details Group the given pins for the Group A/B interrupt. + Applications can register/unregister a callback using the #adi_gpio_RegisterCallback API + to get a notification when the group interrupt occurs. + + @param[in] Port GPIO port number to be operated on. + @param[in] eIrq Interrupt (Group A/B) to which the pin(s) are to be grouped. + @param[in] Pins The GPIO pins which needs to be grouped. + Pin bits that are set enable the interrupt for the group A/B. + Pin bits that are clear disable the interrupt for the group A/B. + @return Status + - #ADI_GPIO_SUCCESS If successfully grouped the given pins. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver is not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] The given pins are invalid. + + @sa adi_gpio_RegisterCallback + @sa adi_gpio_SetGroupInterruptPolarity +*/ +ADI_GPIO_RESULT adi_gpio_SetGroupInterruptPins(const ADI_GPIO_PORT Port, const ADI_GPIO_IRQ eIrq, const ADI_GPIO_DATA Pins) +{ + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + ADI_INT_STATUS_ALLOC(); +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + ADI_ENTER_CRITICAL_REGION(); + switch (eIrq) + { + case SYS_GPIO_INTA_IRQn: + pPort->IENA = Pins; + break; + case SYS_GPIO_INTB_IRQn: + pPort->IENB = Pins; + break; + default: + break; /* This shall never reach */ + } + ADI_EXIT_CRITICAL_REGION(); + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Set the interrupt polarity for the given pins. + + @details Sets the interrupt polarity for the given pins for the given port. + When the corresponding bit is set an interrupt is generated when the pin transitions from low-to-high. When the corresponding bit is cleared an interrupt is generated when the pin transitions from high-to-low. + + @param[in] Port GPIO port number to be operated on. + @param[in] Pins Pins whose polarity to be set. + + @return Status + - #ADI_GPIO_SUCCESS If successfully set the polarity. + - #ADI_GPIO_NOT_INITIALIZED [D] If not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. + + @sa adi_gpio_RegisterCallback + @sa adi_gpio_SetGroupInterruptPins +*/ +ADI_GPIO_RESULT adi_gpio_SetGroupInterruptPolarity(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins) +{ + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + pPort->POL = Pins; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Enables/Disables the Output Drivers for GPIO Pin(s) + + @details Enables/disables the output drivers for the given GPIO pin(s) on + the given port. + + @param[in] Port The GPIO port to be configured. + @param[in] Pins One or more GPIO pins to be configured. GPIO + pins can be passed one at a time or in combination. To + configure a single GPIO pin, a single GPIO value is + passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + @param[in] bFlag Boolean value describing the action to be taken + - true enables the output driver + - false disables the output driver + + @return Status + - #ADI_GPIO_SUCCESS If successfully configured + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. +*/ +ADI_GPIO_RESULT adi_gpio_OutputEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + ADI_ENTER_CRITICAL_REGION(); + if (bFlag) + { + /* enable output */ + pPort->OEN |= Pins; + } else + { + /* disable output */ + pPort->OEN &= (uint16_t)~Pins; + } + ADI_EXIT_CRITICAL_REGION(); + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Enables/Disables the Input Drivers for GPIO Pin(s) + + @details Enables/disables the input drivers for the given GPIO pin(s) on + the given port. + + @param[in] Port The GPIO port to be configured. + @param[in] Pins One or more GPIO pins to be configured. GPIO + pins can be passed one at a time or in combination. To + configure a single GPIO pin, a single GPIO value is + passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + + @param[in] bFlag Boolean value describing the action to be taken + - true enables the input driver + - false disables the input driver + + @return Status + - #ADI_GPIO_SUCCESS If successfully configured. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. +*/ +ADI_GPIO_RESULT adi_gpio_InputEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + ADI_ENTER_CRITICAL_REGION(); + if (bFlag) + { + /* enable input */ + pPort->IEN |= Pins; + } else + { + /* disable input */ + pPort->IEN &= (uint16_t)~Pins; + } + ADI_EXIT_CRITICAL_REGION(); + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Enables/Disables the Pull-Up for GPIO Pin(s) + + @details Enables/disables the internal pull-up for the given GPIO pin(s) on + the given port. API simply enables/disables whatever the hard-wired + pulls (up/down) are. + + @param[in] Port The GPIO port to be configured. + @param[in] Pins One or more GPIO pins to be configured. GPIO + pins can be passed one at a time or in combination. To + configure a single GPIO pin, a single GPIO value is + passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + @param[in] bFlag Boolean value describing the action to be taken + - true enables the pull-up + - false disables the pull-up + + @return Status + - #ADI_GPIO_SUCCESS If successfully configured. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. +*/ +ADI_GPIO_RESULT adi_gpio_PullUpEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + ADI_ENTER_CRITICAL_REGION(); + if (bFlag) + { + pPort->PE |= Pins; + } else + { + pPort->PE &= (uint16_t)(~Pins); + } + ADI_EXIT_CRITICAL_REGION(); + + return (ADI_GPIO_SUCCESS); +} + +/*! + + @brief Sets the Given GPIO pin(s) to a Logical High Level + + @details Sets the given GPIO pin(s) on the given port to a logical high + level. + + @param[in] Port GPIO port whose pins need to be set to logical high level. + @param[in] Pins One or more GPIO pins to be set to logical high. GPIO + pins can be passed one at a time or in combination. To + configure a single GPIO pin, a single GPIO value is + passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + + @return Status + - #ADI_GPIO_SUCCESS If successfully configured. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. + + @sa adi_gpio_SetLow, adi_gpio_Toggle, adi_gpio_SetData, adi_gpio_GetData +*/ +ADI_GPIO_RESULT adi_gpio_SetHigh(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + /* set the given GPIOs high */ + pPort->SET = Pins; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + + @brief Sets the Given GPIO pin(s) to a Logical Low Level + + @details Sets the given GPIO pin(s) on the given port to a logical low + level. + + @param[in] Port The GPIO port whose pins need to be set to logical low level. + @param[in] Pins One or more GPIO pins to be whose logic level to be set. GPIO + pins can be passed one at a time or in combination. To + configure a single GPIO pin, a single GPIO value is + passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + + @return Status + - #ADI_GPIO_SUCCESS If successfully configured. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. + + @sa adi_gpio_SetHigh, adi_gpio_Toggle, adi_gpio_SetData, adi_gpio_GetData +*/ +ADI_GPIO_RESULT adi_gpio_SetLow(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + /* set the given GPIOs low */ + pPort->CLR = Pins; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + + @brief Toggles the Logical Level of the Given GPIO pin(s) + + @details Toggles the logical level of the given GPIO pin(s) on the given port. + If a given GPIO pin is at a logical low level, this function will + change the level to a logical high value. If a given GPIO pin is + at a logical high level, this function will change the level to a + logical low value. + + @param[in] Port The GPIO port whose pins to be toggled. + @param[in] Pins The GPIO pins whose logic level to be toggled. GPIO + pins can be passed one at a time or in combination. To + configure a single GPIO pin, a single GPIO value is + passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + + @return Status + - #ADI_GPIO_SUCCESS If successfully configured. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. + + @sa adi_gpio_SetHigh, adi_gpio_SetLow, adi_gpio_SetData, adi_gpio_GetData +*/ +ADI_GPIO_RESULT adi_gpio_Toggle(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + /* toggle the given GPIOs */ + pPort->TGL = Pins; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + + @brief Sets the logic level of all GPIO pins on the given port to + a given logic level. + + @details Sets the logic level of all the GPIO pins on the given port to the + given value. + + @param[in] Port The GPIO port whose pins logic level to be set. + @param[in] Pins The GPIO pins whose logic level to be set high. All other + GPIO pins on the port will be set to a logical low level. + For example, to set pins 0 and 1 to a logical high level and + all other pins to a logical low level, this parameter should + be passed as #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_1. + + @return Status + - #ADI_GPIO_SUCCESS If successfully set the given data. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. + + @sa adi_gpio_SetHigh, adi_gpio_SetLow, adi_gpio_Toggle, adi_gpio_GetData +*/ +ADI_GPIO_RESULT adi_gpio_SetData(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + /* set the GPIOs as directed */ + pPort->OUT = Pins; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Gets/Senses the input level of all GPIO Pins on the given port. + + @details Gets the level of all GPIO input pins on the given port. + + @param[in] Port The GPIO port whose input level to be sensed. + @param[in] Pins The GPIO pins to be sensed. To sense a single GPIO pin, a single + GPIO value is passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + @param[out] pValue The passed pValue parameter is written with a packed value containing + the status of all the requested GPIO pins on the given port. + + To get the status of a single GPIO pin, return value can be directly used. + For example to see if pin 4 on port 2 is a logical high level, the following is used: + 
+        adi_gpio_GetData(#ADI_GPIO_PORT2, #ADI_GPIO_PIN_4, &pValue)
+
+ pValue will contain the required information. + + If information is required for multiple pins, following method is required: + 
+        adi_gpio_GetData(#ADI_GPIO_PORT2, (#ADI_GPIO_PIN_3 | #ADI_GPIO_PIN_4 | #ADI_GPIO_PIN_7), &pValue)
+
+ + To test if pin 4 on port 2 is a logical high level, the following is used: + 
+        if  (pValue & ADI_GPIO_PIN_4) {
+            pin 4 on port 2 is a logical high value
+        } else {
+            pin 4 on port 2 is a logical low value
+        }
+
+ + @return Status + - #ADI_GPIO_SUCCESS If successfully sensed the input pins. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. + + @sa adi_gpio_SetHigh, adi_gpio_SetLow, adi_gpio_Toggle, adi_gpio_SetData +*/ +ADI_GPIO_RESULT adi_gpio_GetData (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, uint16_t* const pValue) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + /* return the status of the GPIOs */ + *pValue = (pPort->IN) & Pins; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Register or unregister an application callback function for group (A/B) interrupts. + + @details Applications may register a callback function that will be called when a + GPIO group (A/B) interrupt occurs. + + The driver dispatches calls to registered callback functions when the + properly configured pin(s) latches an external interrupt input on the GPIO + pin(s). The callback is dispatched with the following parameters, respectively: + - application-provided callback parameter (\a pCBParam), + - The GPIO Port, + - The GPIO Pins. + + @param[in] eIrq The interrupt for which the callback is being registered. + @param[in] pfCallback Pointer to the callback function. This can be passed as NULL to + unregister the callback. + @param[in] pCBParam Callback parameter which will be passed back to the application + when the callback is called.. + + @return Status + - #ADI_GPIO_SUCCESS if successfully registered the callback. + - #ADI_GPIO_NOT_INITIALIZED [D] if not yet initialized + - #ADI_GPIO_INVALID_INTERRUPT [D] if interrupt ID is invalid + + @sa adi_gpio_SetGroupInterruptPolarity +*/ +ADI_GPIO_RESULT adi_gpio_RegisterCallback (const ADI_GPIO_IRQ eIrq, ADI_CALLBACK const pfCallback, void *const pCBParam ) +{ + uint16_t index = 0u; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } +#endif + + index = (uint16_t)eIrq - (uint16_t)SYS_GPIO_INTA_IRQn + ADI_GPIO_IRQ_GROUPA_INDEX; + + ADI_ENTER_CRITICAL_REGION(); + + adi_gpio_Device.pData->CallbackTable[index].pfCallback = pfCallback; + adi_gpio_Device.pData->CallbackTable[index].pCBParam = pCBParam; + + ADI_EXIT_CRITICAL_REGION(); + + /* return the status */ + return (ADI_GPIO_SUCCESS); +} + + + +/*@}*/ + +/*! \cond PRIVATE */ +/* All of the following is excluded from the doxygen output... */ + +/* Common group (A/B) interrupt handler */ +static void CommonInterruptHandler(const ADI_GPIO_IRQ_INDEX index, const IRQn_Type eIrq) +{ + ADI_GPIO_PORT Port; + ADI_GPIO_TypeDef *pPort; + ADI_GPIO_DATA Pins; + ADI_GPIO_DATA nIntEnabledPins; + + ADI_GPIO_CALLBACK_INFO *pCallbackInfo = &adi_gpio_Device.pData->CallbackTable[index]; + + /* Loop over all the ports. */ + for(Port=ADI_GPIO_PORT0; PortIENA; + } + else /* Is the interrupt is for GROUP B */ + { + nIntEnabledPins = pPort->IENB; + } + + /* Clear only required interrupts */ + Pins = ((pPort->INT) & nIntEnabledPins); + pPort->INT = Pins; + + /* params list is: application-registered cbParam, Port number, and interrupt status */ + if((pCallbackInfo->pfCallback != NULL) && (Pins != 0u)) + { + pCallbackInfo->pfCallback (pCallbackInfo->pCBParam, (uint32_t)Port, &Pins); + } + } +} + +/* Interrupt A handler */ +void GPIO_A_Int_Handler(void) +{ + ISR_PROLOG() + CommonInterruptHandler(ADI_GPIO_IRQ_GROUPA_INDEX, SYS_GPIO_INTA_IRQn); + ISR_EPILOG() +} + +/* Interrupt B handler */ +void GPIO_B_Int_Handler (void) +{ + ISR_PROLOG() + CommonInterruptHandler(ADI_GPIO_IRQ_GROUPB_INDEX, SYS_GPIO_INTB_IRQn); + ISR_EPILOG() +} + +#ifdef ADI_DEBUG + + +/*! + @brief Tests a Pins Parameter for Validity + + @details A debug function that checks a Pins parameter for validity + + @param[in] Pins Logical OR-ing of one or more ADI_GPIO_PIN_x values + + @return Status + - true the Pins value contains valid data + - false the Pins value contains invalid data +*/ +static bool ArePinsValid(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins) +{ + uint32_t PinValid = 0u; + + /* test for a valid pin */ + switch (Port) + { + case ADI_GPIO_PORT0: + PinValid = ~ADI_GPIO_PORT0_PIN_AVL & Pins; + break; + + case ADI_GPIO_PORT1: + PinValid = ~ADI_GPIO_PORT1_PIN_AVL & Pins; + break; + + case ADI_GPIO_PORT2: + PinValid = ~ADI_GPIO_PORT2_PIN_AVL & Pins; + break; + + case ADI_GPIO_PORT3: + PinValid = ~ADI_GPIO_PORT3_PIN_AVL & Pins; + break; + + default: + break; + } + + if (PinValid == 0u) + { + return true; + } + else + { + return false; + } +} +#endif /* ADI_DEBUG */ + +/*! \endcond */ + +/* +** EOF +*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio_def.h new file mode 100755 index 0000000000..90282625df --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio_def.h @@ -0,0 +1,94 @@ +/*! + ***************************************************************************** + * @file: adi_gpio_def.h + * @brief: GPIO Device Driver definition + ***************************************************************************** +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_GPIO_DEF_H +#define ADI_GPIO_DEF_H +/*! \cond PRIVATE */ + + +/*! local enum for callback table indexing */ +typedef enum +{ + /* Group interrupts */ + ADI_GPIO_IRQ_GROUPA_INDEX = (0x0), /*!< GroupA interrupt index. */ + ADI_GPIO_IRQ_GROUPB_INDEX = (0x1), /*!< GroupB interrupt index. */ + + ADI_GPIO_NUM_INTERRUPTS = (0x2), /*!< Number of GPIO interrupts */ + +} ADI_GPIO_IRQ_INDEX; + + +/*! Structure to hold callback function and parameter */ +typedef struct _ADI_GPIO_CALLBACK_INFO +{ + ADI_CALLBACK pfCallback; /*!< Callback function pointer */ + void *pCBParam; /*!< Callback parameter */ +} ADI_GPIO_CALLBACK_INFO; + +/*! Structure to hold callback function and parameter */ +typedef struct _ADI_GPIO_DEV_DATA +{ + ADI_GPIO_CALLBACK_INFO CallbackTable[ADI_GPIO_NUM_INTERRUPTS]; /*!< Callback Info for External interrupts */ +} ADI_GPIO_DEV_DATA; + +/*! \struct ADI_GPIO_DEVICE + + GPIO instance data + + This structure contains the "state" information for the + instance of the device. For GPIO there is only one + of these objects. +*/ +typedef struct _ADI_GPIO_DRIVER_STRUCT +{ + ADI_GPIO_TypeDef *pReg[ADI_GPIO_NUM_PORTS]; /*!< GPIO Ports Register base */ + ADI_GPIO_DEV_DATA *pData; /*!< Pointer to device data */ +} ADI_GPIO_DRIVER_STRUCT; + + +/* alias for the actual device structure */ +typedef ADI_GPIO_DRIVER_STRUCT ADI_GPIO_DRIVER; + +/*! \endcond */ +#endif /* ADI_GPIO_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c.c new file mode 100755 index 0000000000..cb8dba8001 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c.c @@ -0,0 +1,1169 @@ +/*! ***************************************************************************** + * @file: adi_i2c.c + * @brief: I2C device driver global file. + * @details: This a global file which includes a specific file based on the processor family. + * This file contains the I2C device driver functions. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/** @addtogroup I2C_Driver I2C Driver + * @{ + * @brief Inter-Integrated Circuit (I2C) Driver + * @details The I2C Master device driver manages the on-chip I2C hardware to + * control the external two-wire I2C Bus interface, allowing communication with + * multiple I2C slave devices through the I2C slave device addressing scheme. + * @note The application must include drivers/i2c/adi_i2c.h to use this driver + */ + + /*! \cond PRIVATE */ +#include +#include +#include /* for "memset" */ +/*! \endcond */ + +#include +#include + + /*! \cond PRIVATE */ + +#include + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* +* Pm011 (rule 6.3): Types which specify sign and size should be used +* We use bool which is accepted by MISRA but the toolchain does not accept it +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* It is used in the _data.h file which isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Relying on pointer arithmetic for buffer handling. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +*/ + +#pragma diag_suppress=Pm011,Pm123,Pm073,Pm143,Pm088,Pm140 +#endif /* __ICCARM__ */ + +/* pull in internal data structures */ +#include "adi_i2c_data.c" + + +/* handy type-safe zero */ +uint16_t uZero16 = 0u; + +/* central busy checker */ +#define I2C_BUSY (uZero16 != ((hDevice->pDev->MSTAT) & (uint16_t)(BITM_I2C_MSTAT_MBUSY | BITM_I2C_MSTAT_LINEBUSY))) + +/*! + * Read/write bit. + */ + #define READ_NOT_WRITE (1u) + +/* Override "weak" default binding in startup.c */ +/*! \cond PRIVATE */ +extern void I2C0_Master_Int_Handler(void); +/*! \endcond */ + +#if defined(ADI_DEBUG) +/* + * Verifies a pointer to a driver points to one of the driver + * struct's internal to this file. + */ +static bool IsDeviceHandle(ADI_I2C_HANDLE const hDevice); +static bool IsDeviceHandle(ADI_I2C_HANDLE const hDevice) +{ + if ((i2c_device_info[0].hDevice != (hDevice)) && ((hDevice)->pDevInfo->hDevice != NULL)) { + return true; + } else { + return false; + } +} +#endif + + +/*! \endcond */ + + +/**********************************************************************************\ +|**********************************USER INTERFACE**********************************| +\**********************************************************************************/ + + +/*! + * @brief Initialize and allocate an I2C device for use in Master Mode. + * + * @param[in] DeviceNum Zero-based device index designating the I2C device to initialize. + * + * @param [in] pMemory Pointer to a 32-bit aligned buffer of size ADI_I2C_MEMORY_SIZE + * required by the driver for the operation of specified I2C device. + * + * @param [in] MemorySize Size of the buffer to which "pMemory" points. + * + * @param[out] phDevice The caller's device handle pointer for storing the initialized + * device instance data pointer. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_NUMBER [D] Invalid device index. + * - #ADI_I2C_DEVICE_IN_USE [D] Device is already opened. + * - #ADI_I2C_INSUFFICIENT_MEMORY [D] Device memory is not sufficient. + * + * Initialize an I2C device using default user configuration settings (from adi_i2c_config.h) + * and allocate the device for use. Device is opened in Master mode only. + * + * No other I2C APIs may be called until the device open function is called. The returned + * device handle is required to be passed to all subsequent I2C API calls to identify the + * physical device instance to use. The user device handle (pointed to by phDevice) is set + * to NULL on failure. + * + * @note Currently, only a singular I2C physical device instance (device ID "0") exists. + * + * @sa adi_spi_Close(). + */ +ADI_I2C_RESULT adi_i2c_Open (uint32_t const DeviceNum, void* const pMemory, uint32_t const MemorySize, ADI_I2C_HANDLE* const phDevice) { + + /* make a device handle out of the user memory */ + ADI_I2C_HANDLE hDevice = (ADI_I2C_HANDLE)pMemory; + +#if defined(ADI_DEBUG) + /* check requested device number */ + if (DeviceNum >= (uint32_t)ADI_I2C_NUM_INSTANCES) { + return ADI_I2C_BAD_DEVICE_NUMBER; + } + + /* verify device is not already open */ + if (i2c_device_info[DeviceNum].hDevice != NULL) { + return ADI_I2C_DEVICE_IN_USE; + } + + /* verify memory size macro value */ + assert(ADI_I2C_MEMORY_SIZE == sizeof(ADI_I2C_DEV_DATA_TYPE)); + + /* verify user-provided memory meets requirement */ + if ((NULL == pMemory) || (MemorySize < (uint32_t)ADI_I2C_MEMORY_SIZE)) { + return ADI_I2C_INSUFFICIENT_MEMORY; + } +#endif + + /* store a bad handle in case of failure */ + *phDevice = NULL; + + /* + * Link user memory (handle) to ADI_I2C_DEVICE_INFO data structure. + * + * ADI_I2C_DEVICE_INFO <==> ADI_I2C_HANDLE + * + * Clear the ADI_I2C_HANDLE memory. This also sets all bool + * structure members to false so we do not need to waste cycles + * setting these explicitly (e.g. hDevice->bRepearStart = false) + */ + i2c_device_info[DeviceNum].hDevice = (ADI_I2C_DEV_DATA_TYPE *)pMemory; + memset(pMemory, 0, MemorySize); + + /* also link device handle within __ADI_I2C_DEV_DATA_TYPE data structure */ + hDevice->pDevInfo = &i2c_device_info[DeviceNum]; + /* + * Although the ADI_I2C_DEVICE_INFO struct has the physical device pointer + * for this instance, copying it to the ADI_I2C_HANDLE struct (in user memory) + * will minimize the runtime footprint and cycle count when accessing the I2C + * registers. + */ + hDevice->pDev = i2c_device_info[DeviceNum].pDev; + + /* store a pointer to user's static configuration settings */ + hDevice->pDevInfo->pConfig = (ADI_I2C_CONFIG*)&gConfigInfo[DeviceNum]; + + /* create the semaphore */ + SEM_CREATE(hDevice, "i2c_sem", ADI_I2C_SEMAPHORE_FAILED) + ; + + /* reset the driver and HW state */ + ADI_I2C_RESULT ignore ADI_UNUSED_ATTRIBUTE = i2cReset(hDevice); + + /* store device handle into user handle */ + *phDevice = (ADI_I2C_HANDLE)hDevice; + + return ADI_I2C_SUCCESS; +} + + +/*! + * @brief Uninitialize and deallocate an I2C device. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * + * Uninitialize and release an allocated I2C device, and memory associated with it + * for other use. + * + * @note The user memory is released from use by the I2C driver, but is not freed. + * + * @sa adi_spi_Open(). + */ +ADI_I2C_RESULT adi_i2c_Close (ADI_I2C_HANDLE const hDevice) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } +#endif + + /* destroy semaphore */ + SEM_DELETE(hDevice,ADI_I2C_SEMAPHORE_FAILED) + ; + + /* reset the driver and HW state */ + ADI_I2C_RESULT ignore ADI_UNUSED_ATTRIBUTE = i2cReset(hDevice); + + /* stub handle */ + hDevice->pDevInfo->hDevice = NULL; + + return ADI_I2C_SUCCESS; +} + + +/*! + * @brief Blocking I2C Master-Mode data read/write API. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pTransaction Pointer to I2C transaction data struct. + * @param[out] pHwErrors Pointer to hardware error return variable. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_DEVICE_IN_USE [D] An I2C transaction is already underway. + * - #ADI_I2C_INVALID_PARAMETER [D] Invalid data pointer or count is detected. + * - #ADI_I2C_HW_ERROR_DETECTED A hardware error occurred, check \a pHwErrors. + * + * Request a blocking I2C data transfer (read or write, not both as I2C is unidirectional bus) + * with or without preceding prologue transmitted. Control is not returned to the calling + * application until the transfer is complete. Buffer allocations are made by the calling code + * (the application). + * + * The optional prologue (if present) and MANDATORY transaction data pointers are used to read or + * write data over the I2C serial bus according to the prologue and data pointers and corresponding + * size information contained in the \a pTransaction parameter block. The most recently set slave + * target address (set statically with user configuration settings contained in adi_i2c_config.h file + * or set dynamically (at run-time) via the #adi_i2c_SetSlaveAddress() API) is used to address the + * specific destination slave device on the I2C bus. + * + * If present, the prologue (typically, an addressing phase conveying a memory/register address or + * slave device command) is transmitted prior to the data read or write phase, with or without + * an intervening I2C STOP condition. The prologue data is entirely slave device dependent. + * + * In the case of a prologue followed by a data read operation, the I2C bus direction must be + * reversed following the prologue transmit. In this case, The usual I2C STOP condition following + * the prologue (if present) transmit may be suppressed by setting the \a bRepeatStart transaction + * parameter "true". In this case, a second (repeat) START condition is "transmitted" between the + * addressing phase (prologue transmit) and the data phase of the read sequence... \a without an + * intervening STOP condition. This is commonly referred to as the "combined format" in which the + * I2C bus direction is reversed halfway through the transaction without releasing control of the + * I2C bus arbitration. The REPEAT-START condition is a common I2C bus protocol required by many + * I2C slave devices. + * + * In the case of a prologue followed by a data write operation, there is no need to turn the bus + * around and so the \a bRepeatStart parameter is ignored. + * + * @note Application must check the return code to verify if any I2C Bus errors occurred. Hardware + * errors (I2C Protocol errors) are indicated with the #ADI_I2C_HW_ERROR_DETECTED return code, and + * the set of hardware errors (enum #ADI_I2C_HW_ERRORS) that occurred (there may be multiple) are + * indicated in the value set to user variable pointed to by \a pHwErrors. + * + * @sa adi_i2c_SetSlaveAddress(). + * @sa adi_i2c_SubmitBuffer(). + * @sa adi_i2c_IsBufferAvailable(). + * @sa adi_i2c_GetBuffer(). + * @sa ADI_I2C_TRANSACTION. + * @sa ADI_I2C_HW_ERRORS. + */ +ADI_I2C_RESULT adi_i2c_ReadWrite (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction, uint32_t* const pHwErrors) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } + if (I2C_BUSY) { + return ADI_I2C_DEVICE_IN_USE; + } + /* NULL transaction data pointer or zero transaction data count */ + if ((NULL == pTransaction->pData) || (0u == pTransaction->nDataSize)) { + return ADI_I2C_INVALID_PARAMETER; + } +#endif + + /* reset submit/get safeguard flag */ + hDevice->bSubmitCalled = false; + + /* submit/commence the transaction */ + submitTransaction(hDevice, pTransaction); + + /* block on internal transaction completion/error semaphore */ + if (ADI_I2C_SUCCESS == hDevice->result) { + + SEM_PEND(hDevice, ADI_I2C_SEMAPHORE_FAILED); + + /* completion interrupt comes as FIFO unloads, but serialization may not be complete yet... */ + /* must also wait for hardware busy status to clear before giving back control */ + /* i.e., allow any transmit serialization to complete after last FIFO unload */ + while (I2C_BUSY) { + ; + } + } + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->hwErrors; + if (0u != hDevice->hwErrors) { + /* set the HW error return code */ + hDevice->result = ADI_I2C_HW_ERROR_DETECTED; + } + + /* return transaction result code */ + return hDevice->result; +} + + +/*! + * @brief Non-Blocking I2C Master-Mode data read or data write API. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pTransaction Pointer to I2C transaction data struct. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_DEVICE_IN_USE [D] An I2C transaction is already underway. + * - #ADI_I2C_INVALID_PARAMETER [D] Invalid data pointer or count is detected. + * + * Request a non-blocking I2C data transfer (read or write) with or without preceding prologue + * transmitted. Control is returned to the calling application immediately, allowing the application + * process other tasks. The transaction result code is retrieved by #adi_i2c_GetBuffer(). + * + * The application may optionally poll the I2C driver via the #adi_i2c_IsBufferAvailable() API while + * the transaction is underway to determine if and when the submitted transaction is complete. + * Eventually, the application \a MUST call the \a MANDATORY #adi_i2c_GetBuffer() API to obtain the + * transaction result and complete the transaction. Buffer allocations are made by the calling + * code (the application). + * + * The #adi_i2c_GetBuffer() API may be called at any time, even if the transaction is incomplete; + * the #adi_i2c_GetBuffer() call will simply block in incomplete transactions until the + * transaction does complete... at which point #adi_i2c_GetBuffer() returns control with + * the transaction result code. Submitting background transactions is useful if the application has + * housekeeping chores to perform when the I2C transaction is started, but later the application + * decides to just block until the transaction is complete. + * + * The prologue and data buffers are handled as they are in the blocking #adi_i2c_ReadWrite() call, + * it's just that the #adi_i2c_SubmitBuffer() API does not block on the data phase. + * + * @note The non-blocking #adi_i2c_SubmitBuffer() call \a REQUIRES a matching #adi_i2c_GetBuffer() call + * to obtain the final transaction result code and to inform the driver that the application wants to + * regain ownership of the buffers. The application should be prepared to wait for this ownership + * until the current transaction completes. The matching #adi_i2c_GetBuffer() call is required even if + * the transaction may have already completed. The #adi_i2c_GetBuffer() call allows the driver to block + * on completion or error events and then synchronize its internal blocking object. The intermediate + * #adi_i2c_IsBufferAvailable() API is optional.\n\n + * + * @note The #adi_i2c_SubmitBuffer() API is singular, i.e., only a single transaction may be submitted + * at a time. Simultaneous submits (e.g., ping-pong mode) are not supported by the I2C driver. + * + * @sa adi_i2c_ReadWrite(). + * @sa adi_i2c_SetSlaveAddress(). + * @sa adi_i2c_IsBufferAvailable(). + * @sa adi_i2c_GetBuffer(). + * @sa ADI_I2C_TRANSACTION. + */ +ADI_I2C_RESULT adi_i2c_SubmitBuffer (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } + if (I2C_BUSY) { + return ADI_I2C_DEVICE_IN_USE; + } + /* NULL transaction data pointer or zero transaction data count */ + if ((NULL == pTransaction->pData) || (0u == pTransaction->nDataSize)) { + return ADI_I2C_INVALID_PARAMETER; + } +#endif + + /* set submit/get safeguard flag */ + hDevice->bSubmitCalled = true; + + /* submit/commence the transaction */ + submitTransaction(hDevice, pTransaction); + + /* no blocking on submit... just return the submit result */ + return hDevice->result; +} + + +/*! + * @brief Query if a non-blocking I2C transfer is complete. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[out] pbCompletionState Pointer to Boolean into which the I2C bus state is written. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_INVALID_SUBMIT_API No matching submit call. + * + * Sets the application-provided Boolean variable pointed to by pbCompletionState either: + * - true, when the non-blocking transactions is complete, or + * - false, while the non-blocking transactions is still underway. + * + * This API is used in conjunction with a non-blocking #adi_i2c_SubmitBuffer() transfer to + * determine when the transaction is complete. Typically, non-blocking calls are used when the + * calling application has other work to do while I2C controller serializes data over the I2C bus, + * which is an interrupt-driven process. The transaction is submitted as a non-blocking call and + * the submitting API returns immediately, allowing the calling application to perform its other tasks. + * The I2C driver services the interrupts to transfer data while the application performs its + * other tasks. + * + * Non-blocking calls can be polled with this API for completion, or if the application has completed + * its other tasks and wants to just wait on the I2C completion without further polling, it may call + * the associated #adi_i2c_GetBuffer() API to convert the currently unblocked transaction to + * a blocking one. + * + * @note This API is inappropriate in context of blocking calls to #adi_i2c_ReadWrite(). + * + * @sa adi_i2c_ReadWrite(). + * @sa adi_i2c_SubmitBuffer(). + * @sa adi_i2c_GetBuffer(). + * @sa ADI_I2C_TRANSACTION. + */ +ADI_I2C_RESULT adi_i2c_IsBufferAvailable (ADI_I2C_HANDLE const hDevice, bool* const pbCompletionState) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } +#endif + + /* fail if not a submit-based transaction */ + if (false == hDevice->bSubmitCalled) { + return ADI_I2C_INVALID_SUBMIT_API; + } + + /* return true when bus goes quiet */ + if (I2C_BUSY) { + *pbCompletionState = false; + } else { + *pbCompletionState = true; + } + + return ADI_I2C_SUCCESS; +} + + +/*! + * @brief Request ownership of a submitted buffer. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[out] pHwErrors Pointer to hardware error return variable. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_INVALID_SUBMIT_API No matching submit call. + * - #ADI_I2C_HW_ERROR_DETECTED A hardware error occurred, check \a pHwErrors. + * + * This is a potentially blocking MANDATORY call that the application MUST use to reclaim + * ownership of any "submitted" transaction (submitted via a previous #adi_i2c_SubmitBuffer() + * call) and obtain the transaction success/failure result code. This API blocks until the + * transaction is complete and returns the transaction result code. If the transaction is + * already complete, the blocking is trivial and control is returned immediately. + * + * Non-blocking calls can also be (optionally) polled with the non-blocking + * #adi_i2c_IsBufferAvailable() API to see if and when the transaction is complete. + * + * The #adi_i2c_GetBuffer() call is a MANDATORY compliment to #adi_i2c_SubmitBuffer() and + * allows the I2C driver to synchronize its internal blocking object. + * + * @note Application must check the return code to verify if any I2C Bus errors occurred. Hardware + * errors (I2C Protocol errors) are indicated with the #ADI_I2C_HW_ERROR_DETECTED return code, and + * the set of hardware errors (enum #ADI_I2C_HW_ERRORS) that occurred (there may be multiple) are + * indicated in the value set to user variable pointed to by \a pHwErrors. + * + * @sa adi_i2c_ReadWrite(). + * @sa adi_i2c_SubmitBuffer(). + * @sa adi_i2c_IsBufferAvailable(). + * @sa ADI_I2C_TRANSACTION. + * @sa ADI_I2C_HW_ERRORS. + */ +ADI_I2C_RESULT adi_i2c_GetBuffer (ADI_I2C_HANDLE const hDevice, uint32_t* const pHwErrors) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } +#endif + + /* fail if not a submit-based transaction */ + if (false == hDevice->bSubmitCalled) { + return ADI_I2C_INVALID_SUBMIT_API; + } + + /* block until complete or error interrupt sets the semaphore */ + SEM_PEND(hDevice, ADI_I2C_SEMAPHORE_FAILED); + + /* delay until bus goes quiet */ + while (I2C_BUSY) { + ; + } + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->hwErrors; + if (0u != hDevice->hwErrors) { + /* set the HW error return code */ + hDevice->result = ADI_I2C_HW_ERROR_DETECTED; + } + + /* return transaction result code */ + return hDevice->result; +} + +/*! + * @brief Reset an I2C device and driver instance. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * + * Reset the I2C physical controller and device driver internals. + */ +ADI_I2C_RESULT adi_i2c_Reset (ADI_I2C_HANDLE const hDevice) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } +#endif + + /* destroy/recreate the semaphore to force a clear state */ + SEM_DELETE(hDevice, ADI_I2C_SEMAPHORE_FAILED) + ; + SEM_CREATE(hDevice, "i2c_sem", ADI_I2C_SEMAPHORE_FAILED) + ; + + /* reset the driver and HW state */ + return i2cReset(hDevice); +} + + +/*! + * @brief Set the I2C serial bus speed. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] requestedBitRate32 Requested I2C bus clock rate (in Hz). + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_DEVICE_IN_USE [D] Device is busy. + * - #ADI_I2C_BAD_SYS_CLOCK Failure to obtain the current PCLK rate. + * - #ADI_I2C_BAD_BITRATE Requested clock speed exceeds operational specification. + * + * Sets the I2C bus clock speed to the requested user parameter, \a requestedBitRate. + * + * @note Any I2C Bus clock rate may be requested up to and including the "FAST" mode I2C clock + * rate (400 kHz), including the "STANDARD" mode (100 kHz). Faster clock rates beyond "FAST" + * mode (e.g., "FAST+" or "HIGH-SPEED" modes) are not supported by the hardware. Slower clock + * rates below approximately 55 kHz (assuming a 26 MHz system clock) are physically unrealizable + * due to the fixed 8-bit field-width of the 8-bit I2C clock rate divide register.\n\n + * + * @note Default clock rate may be specified statically in the default user configuration file, + * "adi_i2c_config.h". + */ +ADI_I2C_RESULT adi_i2c_SetBitRate (ADI_I2C_HANDLE const hDevice, uint32_t const requestedBitRate32) { + + uint32_t clockFrequency32, halfClock32; + uint16_t halfClock16; + uint16_t highTime16, lowTime16; + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } + if (I2C_BUSY) { + return ADI_I2C_DEVICE_IN_USE; + } +#endif + + /* get input clockrate from power service */ + if (ADI_PWR_SUCCESS != adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &clockFrequency32)) { + return ADI_I2C_BAD_SYS_CLOCK; + } + + /* block requests above max rated 400kHz operation */ + if (ADI_I2C_MAX_RATE < requestedBitRate32) { + return ADI_I2C_BAD_BITRATE; + } + + /* compute half-cycle period in 32-bits (">>1" is divide by 2) */ + halfClock32 = (clockFrequency32 / requestedBitRate32) >> 1; /* HRM equation */ + + /* downcast to 16-bit to match destination field */ + halfClock16 = (uint16_t)(halfClock32 & 0x0000ffffu); + + /* check for lost precision in conversion */ + if (halfClock32 != halfClock16) { + return ADI_I2C_BAD_BITRATE; + } + + /* adjust high and low durations per HRM */ + highTime16 = halfClock16 - 7u; /* empirical: varies with board layout, pullups, etc */ + lowTime16 = halfClock16 - 1u; + + /* shift values into their clock rate divider register positions */ + highTime16 <<= BITP_I2C_DIV_HIGH; + lowTime16 <<= BITP_I2C_DIV_LOW; + + /* check for divider overflows beyond designated (8-bit) field masks */ + if ( (uZero16 != ((uint16_t)highTime16 & (uint16_t)(~(BITM_I2C_DIV_HIGH)))) + || + (uZero16 != ((uint16_t)lowTime16 & (uint16_t)(~(BITM_I2C_DIV_LOW)))) + ) { + return ADI_I2C_BAD_BITRATE; + } + + /* program new values */ + hDevice->pDev->DIV = highTime16 | lowTime16; + + return ADI_I2C_SUCCESS; +} + + +/*! + * @brief Set the I2C serial bus slave address. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] SlaveAddress New 7-bit address for targeting a slave device. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_DEVICE_IN_USE [D] Device is busy. + * - #ADI_I2C_INVALID_SLAVE_ADDRESS Slave address exceeds the 7-bit limit. + * + * Sets the 7-bit (unformatted) slave address for which all subsequent I2C bus traffic is directed. + * Read/write address formatting is performed by the driver, depending on bus direction. + * + * @note This driver does not support the I2C 10-bit extended addressing scheme.\n\n + * + * @note Default slave address may be specified statically in the default user configuration file, + * "adi_i2c_config.h". + */ +ADI_I2C_RESULT adi_i2c_SetSlaveAddress (ADI_I2C_HANDLE const hDevice, uint16_t const SlaveAddress) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } + if (I2C_BUSY) { + return ADI_I2C_DEVICE_IN_USE; + } +#endif + + /* verify no slave address bits fall outside the 7-bit addressing model (10-bit addressing not supported) */ + if (uZero16 != (SlaveAddress & (uint16_t)(~(BITM_I2C_ADDR1_VALUE >> 1)))) { + return ADI_I2C_INVALID_SLAVE_ADDRESS; + } + + /* save new address */ + hDevice->i2cDeviceAddress = SlaveAddress; + + return ADI_I2C_SUCCESS; +} + + +/*! + * @brief Transmit a General Call command to all slave devices on the I2C bus. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pData Pointer to data buffer to transmit. + * @param[in] nDataSize Size of data buffer to transmit. + * @param[out] pHwErrors Pointer to hardware error return variable. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_DEVICE_IN_USE [D] Device is busy. + * + * Broadcasts the given command buffer across the I2C bus to reserved General Call (GC) + * address (address zero). All, some, or none of the slave devices on the I2C bus will + * respond, depending on their capabilities. All responding slave devices will process + * the GC command according to their capabilities. + * + * The GC command is a blocking transaction. + * + * The application is responsible for formatting the GC command into the data buffer + * according to various Philips Semiconductor (now, NXP) documents, such as the 2014 + * Revision 6 document: "UM10204 I2C-Bus Specification and User Manual" + * (see www.nxp.com/documents/user_manual/UM10204.pdf). + * + * No prologue precedes the GC command data; the GC command data is transmitted verbatim. + * + * @note The currently active slave address is saved and restored when transmitting GC + * commands to the reserved GC address (address zero). + * + */ +ADI_I2C_RESULT adi_i2c_IssueGeneralCall (ADI_I2C_HANDLE const hDevice, uint8_t* const pData, uint8_t const nDataSize, uint32_t* const pHwErrors) { + + ADI_I2C_RESULT result; + ADI_I2C_TRANSACTION xfr; + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } + if (I2C_BUSY) { + return ADI_I2C_DEVICE_IN_USE; + } +#endif + + /* force general call reserved target address of zero */ + uint16_t savedSlaveAddress = hDevice->i2cDeviceAddress; + hDevice->i2cDeviceAddress = 0u; + + /* setup the transfer */ + xfr.pPrologue = NULL; + xfr.nPrologueSize = 0u; + xfr.pData = pData; + xfr.nDataSize = nDataSize; + xfr.bReadNotWrite = false; + xfr.bRepeatStart = false; + + /* dispatch as a blocking transmit call */ + result = adi_i2c_ReadWrite(hDevice, &xfr, pHwErrors); + + /* always restore saved slave address */ + hDevice->i2cDeviceAddress = savedSlaveAddress; + + if (ADI_I2C_SUCCESS != result) { + return result; /* read/write failure... */ + } else { + return hDevice->result; /* actual result */ + } +} + + + /*! \cond PRIVATE */ + + +/**********************************************************************************\ +|*****************************static helper functions******************************| +\**********************************************************************************/ + +static void submitTransaction(ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction) { + + /* reset internal return code */ + hDevice->result = ADI_I2C_SUCCESS; + + /* reset hardware error code */ + hDevice->hwErrors = ADI_I2C_HW_ERROR_NONE; + + /* wait for HW to be ready */ + while (I2C_BUSY) { + ; + } + + /* save common user parameters */ + hDevice->pNextPrologueByte = pTransaction->pPrologue; + hDevice->remainingPrologueCount = pTransaction->nPrologueSize; + hDevice->bRepeatStart = pTransaction->bRepeatStart; + + /* encode (mask and upshift) the slave address, leaving room for the r/w control bit (LSB) */ + hDevice->i2cEncodedDeviceAddress = (hDevice->i2cDeviceAddress & (BITM_I2C_ADDR1_VALUE >> 1)) << 1; + + /* dispatch */ + if (pTransaction->bReadNotWrite) { + + /* setup read parameters */ + hDevice->pNextReadByte = pTransaction->pData; + hDevice->remainingReadCount = pTransaction->nDataSize; + hDevice->pNextWriteByte = NULL; + hDevice->remainingWriteCount = 0u; + + /* set read bit */ + hDevice->i2cEncodedDeviceAddress |= READ_NOT_WRITE; + + /* commence receive */ + commenceReceive(hDevice); + + } else { + + /* setup write parameters */ + hDevice->pNextReadByte = NULL; + hDevice->remainingReadCount = 0u; + hDevice->pNextWriteByte = pTransaction->pData; + hDevice->remainingWriteCount = pTransaction->nDataSize; + + /* clear read bit */ + hDevice->i2cEncodedDeviceAddress &= (~READ_NOT_WRITE); + + /* commence transmit */ + commenceTransmit(hDevice); + } +} + + +static void commenceTransmit(ADI_I2C_HANDLE const hDevice) { + + /* transmit is always pure transmit, whether we have a prologue or not... */ + + /* enable PIO interrupts */ + NVIC_EnableIRQ(hDevice->pDevInfo->pioIRQn); + + /* enable i2c for PIO-based transmit interrupts */ + hDevice->pDev->MCTL |= (BITM_I2C_MCTL_IENMTX | BITM_I2C_MCTL_MASEN); + + /* how many bytes are available in the transmit FIFO (2-deep) */ + uint16_t writableBytes = 2u - (hDevice->pDev->MSTAT & (uint16_t)BITM_I2C_MSTAT_MTXF); + + /* prime transmit FIFO with any prologue data */ + while ((0u < writableBytes) && (hDevice->remainingPrologueCount)) { + hDevice->pDev->MTX = *hDevice->pNextPrologueByte; + hDevice->pNextPrologueByte++; + hDevice->remainingPrologueCount--; + writableBytes--; + } + + /* flesh out any remaining FIFO space with transmit data */ + while ((0u < writableBytes) && (hDevice->remainingWriteCount)) { + hDevice->pDev->MTX = *hDevice->pNextWriteByte; + hDevice->pNextWriteByte++; + hDevice->remainingWriteCount--; + writableBytes--; + } + + /* launch the transmit */ + hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress; +} + + +/* initiate receive addressing phase */ +static void commenceReceive(ADI_I2C_HANDLE const hDevice) { + + /* receive can be either pure receive (no prologue), + or a transmit (of prologue) followed by a receive */ + + /* enable PIO interrupts */ + NVIC_EnableIRQ(hDevice->pDevInfo->pioIRQn); + + /* enable i2c for PIO-based receive interrupts */ + hDevice->pDev->MCTL |= (uint16_t)(BITM_I2C_MCTL_IENMRX | BITM_I2C_MCTL_MASEN); + + /* program HW receive count */ + if (hDevice->remainingReadCount > BITM_I2C_MRXCNT_EXTEND) { + hDevice->pDev->MRXCNT = BITM_I2C_MRXCNT_EXTEND; + hDevice->remainingReadCount -= BITM_I2C_MRXCNT_EXTEND; + } else { + hDevice->pDev->MRXCNT = hDevice->remainingReadCount - 1u; + hDevice->remainingReadCount = 0u; + } + + /* if we have prologue (the dreaded "COMBINED FORMAT"), transmit the prologue prior to data receive... */ + if (hDevice->remainingPrologueCount) { + + /* -OR- in transmit interrupt enable if we have prologue data to send */ + hDevice->pDev->MCTL |= BITM_I2C_MCTL_IENMTX; + + /* how many bytes are available in the transmit FIFO (should be 2) */ + uint16_t writableBytes = 2u - (hDevice->pDev->MSTAT & (uint16_t)BITM_I2C_MSTAT_MTXF); + + /* prime transmit FIFO with any prologue data (memory address or command) first */ + while ((0u < writableBytes) && (hDevice->remainingPrologueCount)) { + hDevice->pDev->MTX = *hDevice->pNextPrologueByte; + hDevice->pNextPrologueByte++; + hDevice->remainingPrologueCount--; + writableBytes--; + } + + /* initiate prologue transmit with read bit cleared (for prologue write) */ + /* (read sequence is initiated by transmit handler, *after* prologue is transmitted...) */ + hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress & (uint16_t)(~READ_NOT_WRITE); + + } else { + + /* no prologue... initiate pure receive (read bit already set) */ + hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress; + } +} + + +/* reset the I2C HW */ +static ADI_I2C_RESULT i2cReset(ADI_I2C_HANDLE const hDevice) { + + volatile uint16_t temp; + /* disable interrupts */ + NVIC_DisableIRQ(hDevice->pDevInfo->pioIRQn); + + /* reset any pending interrupts and TX FIFO (W1C) */ + temp = hDevice->pDev->MSTAT; + hDevice->pDev->MSTAT = temp; + + /* discard any rogue RX FIFO data */ + while (uZero16 != (hDevice->pDev->STAT & (uint16_t)BITM_I2C_STAT_MRXF)) { + volatile uint16_t delme ADI_UNUSED_ATTRIBUTE = hDevice->pDev->MTX; + } + + /* reset i2c control register */ + hDevice->pDev->MCTL = 0u; + + /* reset repeat start logic */ + hDevice->pDev->SHCTL = 1u; + + /* (re)assert controller defaults from user config values */ + hDevice->pDev->MCTL = hDevice->pDevInfo->pConfig->MasterControlRegister; + hDevice->pDev->DIV = hDevice->pDevInfo->pConfig->ClockDividerRegister; + hDevice->pDev->SHCTL = hDevice->pDevInfo->pConfig->SharedControlRegister; + hDevice->pDev->TCTL = hDevice->pDevInfo->pConfig->TimingControlRegister; + hDevice->pDev->ASTRETCH_SCL = hDevice->pDevInfo->pConfig->ClockStretchRegister; + hDevice->i2cDeviceAddress = hDevice->pDevInfo->pConfig->TargetSlaveAddress; + + return ADI_I2C_SUCCESS; +} + + +/**********************************************************************************\ +|********************************interrupt handlers********************************| +\**********************************************************************************/ + + +/* transmit interrupt handler */ +static void transmitHandler(ADI_I2C_HANDLE const hDevice) { + + /* how much room in transmit FIFO? */ + /* DO ***NOT*** USE MSTAT:MTXF... FALSELY INDICATES MOSTLY FULL FIFO! */ + uint16_t writableBytes = 2u - ((hDevice->pDev->STAT & (uint16_t)BITM_I2C_STAT_MTXF) >> BITP_I2C_STAT_MTXF); + + /* for extended prologues, continue pushing prologue data out */ + while ((0u < writableBytes) && (hDevice->remainingPrologueCount)) { + hDevice->pDev->MTX = *hDevice->pNextPrologueByte; + hDevice->pNextPrologueByte++; + hDevice->remainingPrologueCount--; + writableBytes--; + } + + /* once the prologue is done... */ + if (0u == hDevice->remainingPrologueCount) { + + /* if we have a completed prologue associated with a read sequence... */ + if (0u < hDevice->remainingReadCount) { + + /* initiate the read (subsequently driven by receive interrupt handler) */ + hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress; + + } else { + + /* normal transmit interrupt: just push transmit data */ + while ((0u < writableBytes) && (hDevice->remainingWriteCount)) { + hDevice->pDev->MTX = *hDevice->pNextWriteByte; + hDevice->pNextWriteByte++; + hDevice->remainingWriteCount--; + writableBytes--; + } + } + } + + /* clear TX interrupt as we complete transmit writes */ + if (0u == hDevice->remainingWriteCount) { + hDevice->pDev->MSTAT = BITM_I2C_MSTAT_MTXREQ; + } +} + + +/* receive interrupt handler */ +static void receiveHandler(ADI_I2C_HANDLE const hDevice) { + + /* note: we never need to deal with prologue data here... it will already be transmitted... */ + + /* how many bytes in receive FIFO? */ + uint16_t readableBytes = (hDevice->pDev->STAT & (uint16_t)BITM_I2C_STAT_MRXF) >> BITP_I2C_STAT_MRXF; + + /* pull bytes from fifo */ + while (0u < readableBytes) { + + readableBytes--; + + /* pull one byte */ + *hDevice->pNextReadByte = (uint8_t)hDevice->pDev->MRX; + hDevice->pNextReadByte++; + + if ((0u == hDevice->pDev->MCRXCNT) && (hDevice->remainingReadCount)) { + + /* if HW read counter goes to zero with remaining data to read, reprogram read count */ + if (hDevice->remainingReadCount > BITM_I2C_MRXCNT_EXTEND) { + /* use extended count flag for large remaining counts... */ + hDevice->pDev->MRXCNT = BITM_I2C_MRXCNT_EXTEND; + hDevice->remainingReadCount -= BITM_I2C_MRXCNT_EXTEND; + } else { + /* new count fits... no need for extended count */ + hDevice->pDev->MRXCNT = hDevice->remainingReadCount - 1u; + hDevice->remainingReadCount = 0u; + } + } + } +} + +/* completion interrupt handler */ +static void completeHandler(ADI_I2C_HANDLE const hDevice) { + + /* block on busy until all transmit data has both left + the fifo AND has been fully serialized to the bus. */ + while (I2C_BUSY) { + ; + } + + /* disable interrupts */ + NVIC_DisableIRQ(hDevice->pDevInfo->pioIRQn); + + /* reset controller to default user config state */ + hDevice->pDev->MCTL = (uint16_t)gConfigInfo->MasterControlRegister; +} + + +/* error interrupt handler */ +static void errorHandler(ADI_I2C_HANDLE const hDevice) { + + /* accumulate I2C bus errors */ + + if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_NACKADDR)) { + hDevice->hwErrors |= ADI_I2C_HW_ERROR_NACK_ADDR; + } + + if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_NACKDATA)) { + hDevice->hwErrors |= ADI_I2C_HW_ERROR_NACK_DATA; + } + + if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_ALOST)) { + hDevice->hwErrors |= ADI_I2C_HW_ERROR_ARBITRATION_LOST; + } + + /* if no other errors exist, note we had an unexpected error */ + if (hDevice->hwErrors == ADI_I2C_HW_ERROR_NONE) { + hDevice->hwErrors = ADI_I2C_HW_ERROR_UNEXPECTED_ERROR; + } +} + + +/**********************************************************************************\ +|*****************************I2C INTERRUPT HANDLER********************************| +\**********************************************************************************/ + + +/* PIO mode I2C interrupt handler */ +void I2C0_Master_Int_Handler(void) { + + bool bPost = false; + + /* rtos prologue */ + ISR_PROLOG() + ; + + /* recover device handle */ + ADI_I2C_HANDLE const hDevice = (ADI_I2C_HANDLE)i2c_device_info[0].hDevice; + + /* save destructive status read... */ + hDevice->hwStatus = hDevice->pDev->MSTAT; + + /* if RepeatStart request is pending, rewrite address register ASAP (and only once) to block stop bit */ + if (hDevice->bRepeatStart) { + hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress; + hDevice->bRepeatStart = false; /* just do it once on 1st interrupt */ + } + + /* forward TX interrupts to TX handler */ + if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_MTXREQ)) { + transmitHandler(hDevice); + } + + /* forward RX interrupts to RX handler */ + if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_MRXREQ)) { + receiveHandler(hDevice); + } + + /* dispatch any errors */ + if (uZero16 != (hDevice->hwStatus & ADI_I2C_STATUS_ERROR_MASK)) { + errorHandler(hDevice); + + /* post on bus error */ + bPost = true; + } + + /* transmit complete */ + if (uZero16 != (hDevice->hwStatus & BITM_I2C_MSTAT_TCOMP)) { + completeHandler(hDevice); + + /* post on completion */ + bPost = true; + } + + /* just post once */ + if (true == bPost) { + SEM_POST(hDevice); + } + + /* rtos epilogue */ + ISR_EPILOG() + ; +} + +/*! \endcond */ + + +/* @} */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_data.c new file mode 100755 index 0000000000..c48264eb24 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_data.c @@ -0,0 +1,120 @@ +/* + ***************************************************************************** + * @file: adi_i2c_data.c + * @brief: Data declaration for I2C Device Driver + ***************************************************************************** + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be coni2ccuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_I2C_DATA_C +#define ADI_I2C_DATA_C + + /*! \cond PRIVATE */ + +#include "adi_i2c_def.h" +#include "adi_i2c_config.h" + + +/* Stores the information about the specific device */ +static ADI_I2C_DEVICE_INFO i2c_device_info [ADI_I2C_NUM_INSTANCES] = +{ + /* fixed instance data for the singular I2C0 controller */ + { + I2C_MST_EVT_IRQn, /* pio interrupt number */ + (ADI_I2C_TypeDef *)pADI_I2C0, /* i2c controller pointer */ + NULL, /* pointer to user config data */ + NULL /* i2c device handle (user mem) */ + }, + + /* no other i2c instances at this time */ +}; + +/* build I2C Application configuration array */ +static ADI_I2C_CONFIG gConfigInfo[ADI_I2C_NUM_INSTANCES] = +{ + /* the one-and-only (so far) instance data for I2C, I2C0... */ + { + /**** I2C_MCTL Master Control register *** */ + ( + /* note: Master IENMTX and IENMRX (transmit and receive interrupts) are managed dynamically */ + ( ADI_I2C_CFG_MCTL_MXMITDEC << BITP_I2C_MCTL_MXMITDEC ) | + ( ADI_I2C_CFG_MCTL_IENCMP << BITP_I2C_MCTL_IENCMP ) | + ( ADI_I2C_CFG_MCTL_IENACK << BITP_I2C_MCTL_IENACK ) | + ( ADI_I2C_CFG_MCTL_IENALOST << BITP_I2C_MCTL_IENALOST ) | + ( ADI_I2C_CFG_MCTL_STRETCHSCL << BITP_I2C_MCTL_STRETCHSCL ) | + ( ADI_I2C_CFG_MCTL_LOOPBACK << BITP_I2C_MCTL_LOOPBACK ) | + ( ADI_I2C_CFG_MCTL_COMPLETE << BITP_I2C_MCTL_COMPLETE ) | + ( ADI_I2C_CFG_MCTL_MASEN << BITP_I2C_MCTL_MASEN ) + ), + + /**** I2C_DIV Clock Divider register *** */ + ( + ( ADI_I2C_CFG_DIV_HIGH << BITP_I2C_DIV_HIGH ) | + ( ADI_I2C_CFG_DIV_LOW << BITP_I2C_DIV_LOW ) + ), + + /**** I2C_SHCTL Shared Control register *** */ + ( + ( ADI_I2C_CFG_SHCTL_RST << BITP_I2C_TCTL_FILTEROFF ) + ), + + /**** I2C_TCTL Timing control register *** */ + ( + ( ADI_I2C_CFG_TCTL_FILTEROFF << BITP_I2C_SHCTL_RST ) | + ( ADI_I2C_CFG_TCTL_THDATIN << BITP_I2C_TCTL_THDATIN ) + ), + + /**** I2C_ASTRETCH Master Clock Stretch register *** */ + ( + ( ADI_I2C_CFG_ASTRETCH_MST << BITP_I2C_ASTRETCH_SCL_MST ) + ), + + /**** Target Slave configuration value (not a register) *** */ + ( + ( ADI_I2C_CFG_SLAVE_ADDRESS ) + ), + } +}; + +/*! \endcond */ + + +#endif /* ADI_I2C_DATA_C */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_def.h new file mode 100755 index 0000000000..03ba0b5bf9 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_def.h @@ -0,0 +1,129 @@ +/*! + ***************************************************************************** + @file: adi_i2c_def.h + @brief: Internal I2C device driver definitions and macros + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ +#ifndef ADI_I2C_DEF_H +#define ADI_I2C_DEF_H + +/*! \cond PRIVATE */ + +#include + +#define ADI_I2C_NUM_INSTANCES (1u) +#define ADI_I2C_STATUS_ERROR_MASK ( (1u << BITP_I2C_MSTAT_NACKADDR) \ + | (1u << BITP_I2C_MSTAT_NACKDATA) \ + | (1u << BITP_I2C_MSTAT_ALOST) ) + +/* Internal Actions */ +static void submitTransaction (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction); +static void commenceTransmit (ADI_I2C_HANDLE const hDevice); +static void commenceReceive (ADI_I2C_HANDLE const hDevice); +static ADI_I2C_RESULT i2cReset (ADI_I2C_HANDLE const hDevice); + +/* interrupt event handlers */ +static void transmitHandler (ADI_I2C_HANDLE const hDevice); +static void receiveHandler (ADI_I2C_HANDLE const hDevice); +static void completeHandler (ADI_I2C_HANDLE const hDevice); +static void errorHandler (ADI_I2C_HANDLE const hDevice); + + +/* + ***************************************************************************** + * I2C Configuration structure. + *****************************************************************************/ +typedef struct __ADI_I2C_CONFIG { + uint16_t MasterControlRegister; /* I2C_MCTL register configuration. */ + uint16_t ClockDividerRegister; /* I2C_DIV register. */ + uint16_t SharedControlRegister; /* I2C_DIV register. */ + uint16_t TimingControlRegister; /* I2C_TCTL register. */ + uint16_t ClockStretchRegister; /* I2C_ASTRETCH register. */ + uint16_t TargetSlaveAddress; /* slave address value (not a register). */ +} ADI_I2C_CONFIG; + + +/* I2C physical device instance data */ +typedef struct __ADI_I2C_DEVICE_INFO { + IRQn_Type pioIRQn; /* PIO interrupt number */ + ADI_I2C_TypeDef *pDev; /* pointer to i2c controller */ + ADI_I2C_CONFIG *pConfig; /* pointer to user config info */ + ADI_I2C_HANDLE hDevice; /* I2C handle or NULL if uninitialized */ +} ADI_I2C_DEVICE_INFO; + +/* I2C driver instance data structure */ +typedef struct __ADI_I2C_DEV_DATA_TYPE { + + /* make sure to synchronize ANY size changes with ADI_I2C_MEMORY_SIZE macro in adi_i2c.h */ + + /* device attributes */ + ADI_I2C_TypeDef *pDev; + ADI_I2C_DEVICE_INFO *pDevInfo; + + + /* driver state */ + uint16_t hwStatus; + bool bRepeatStart; + uint16_t i2cDeviceAddress; + uint16_t i2cEncodedDeviceAddress; /* encoded as 7-bit device address + r/w LSB */ + bool bSubmitCalled; + + /* prologue data */ + volatile uint8_t *pNextPrologueByte; + volatile uint16_t remainingPrologueCount; + + /* write data */ + volatile uint8_t *pNextWriteByte; + volatile uint16_t remainingWriteCount; + + /* read data */ + volatile uint8_t *pNextReadByte; + volatile uint16_t remainingReadCount; + + ADI_I2C_RESULT result; /* collector for return status */ + ADI_I2C_HW_ERRORS hwErrors; /* collector for error status */ + + SEM_VAR_DECLR /* blocking object: "Semaphore" for rtos, "nLowPowerExitFlag" for non-rtos */ + +} ADI_I2C_DEV_DATA_TYPE; + +/*! \endcond */ + +#endif /* end of ifndef ADI_I2C_DEF_H */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr.c new file mode 100755 index 0000000000..a91c53e02c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr.c @@ -0,0 +1,1904 @@ +/* + ***************************************************************************** + * @file: adi_pwr.c + * @brief: Power Management driver implementation. + *----------------------------------------------------------------------------- + * +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/*! \addtogroup Power_Driver Power Driver + * @{ + * @brief Power Management Driver + * @note The application must include drivers/pwr/adi_pwr.h to use this driver + * @note The API #adi_pwr_EnableClockSource requires the GPIO driver if + * #ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO is set to 1. In that case the + * application must include the GPIO driver sources to avoid link errors. + */ + + +#include /* for 'NULL' */ +#include +#include "adi_pwr_def.h" +#include +#include +#include +#include + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): Types which specify sign and size should be used +* We use bool which is accepted by MISRA but the toolchain does not accept it +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +* Pm057 (rule 15.2): Every non-empty case clause in a switch statement shall be terminated with a break statement. +* In some cases we have return statement instead of break. It is not valid to both return and break in MISRA 2012. +*/ +#pragma diag_suppress=Pm011,Pm073,Pm050,Pm140,Pm143,Pm057 +#endif /* __ICCARM__ */ + +/*! \cond PRIVATE */ + +/*---------------------------------------------------------------------------- + Internal Clock Variables. The external ones are defined in system.c + *---------------------------------------------------------------------------*/ +#ifdef ADI_DEBUG +/* not needed unless its debug mode */ +extern uint32_t lfClock; /* "lf_clk" coming out of LF mux */ +#endif + +extern uint32_t hfClock; /* "root_clk" output of HF mux */ +extern uint32_t gpioClock; /* external GPIO clock */ + +static ADI_CALLBACK gpfCallbackFunction; +static void *gpPowcbParam = NULL; +static uint32_t gnLowPowerIntOccFlag = 0u; + +/*! \endcond */ + +/*---------------------------------------------------------------------------- + Clock functions + *---------------------------------------------------------------------------*/ +/** + * Initialize the clock configuration register with the default values. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully initialized the power service. + */ +ADI_PWR_RESULT adi_pwr_Init (void) +{ + /* Enable internal HF oscillators */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + + pADI_CLKG0_OSC->CTL = OSCCTRL_CONFIG_VALUE; + + gpfCallbackFunction = NULL; + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + + /* Switch on the internal HF oscillator */ + pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_HFOSC_EN; + + /* wait for HF OSC to stabilize */ + while ((pADI_CLKG0_OSC->CTL & (1U << BITP_CLKG_OSC_CTL_HFOSC_OK)) == 0u) + { + } + + /* Switch over to the internal HF oscillator */ + pADI_CLKG0_CLK->CTL0 &= ~(BITM_CLKG_CLK_CTL0_CLKMUX); + + /* complete remaining reset sequence */ + pADI_CLKG0_CLK->CTL0 = CLOCK_CTL0_CONFIG_VALUE; + pADI_CLKG0_CLK->CTL1 = CLOCK_CTL1_CONFIG_VALUE; + pADI_CLKG0_CLK->CTL2 = CLOCK_CTL2_CONFIG_VALUE; + pADI_CLKG0_CLK->CTL3 = CLOCK_CTL3_CONFIG_VALUE; + /* No CLK CTL4 */ + pADI_CLKG0_CLK->CTL5 = CLOCK_CTL5_CONFIG_VALUE; + + /* + * Configure the power management registers + */ + pADI_PMG0->IEN = PWM_INTERRUPT_CONFIG; + pADI_PMG0->PWRMOD = PWM_PWRMOD_CONFIG; + pADI_PMG0->CTL1 = PWM_HPBUCK_CONTROL; + + /* disable external HF crystal oscillator */ + /* (don't disable LF crystal or the RTC will lose time */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + pADI_CLKG0_OSC->CTL &= ~BITM_CLKG_OSC_CTL_HFX_EN; + + NVIC_EnableIRQ(PMG0_VREG_OVR_IRQn); + NVIC_EnableIRQ(PMG0_BATT_RANGE_IRQn); + + NVIC_EnableIRQ(CLKG_XTAL_OSC_EVT_IRQn); + NVIC_EnableIRQ(CLKG_PLL_EVT_IRQn); + + /* compute new internal clocks based on the newly reset controller */ + SystemCoreClockUpdate(); + + return(ADI_PWR_SUCCESS); +} + + +/** + * @brief Updates the internal SystemCoreClock variable with current core + * Clock retrieved from cpu registers. + * + * @return Status + * - #ADI_PWR_SUCCESS : Updated core system core clock variables. + * + * Updates the internal SystemCoreClock variable with current core + * Clock retrieved from cpu registers. + * + * @sa adi_pwr_GetClockFrequency () + */ +ADI_PWR_RESULT adi_pwr_UpdateCoreClock (void) +{ + SystemCoreClockUpdate(); + return(ADI_PWR_SUCCESS); +} + +/** + * @brief Registers or unregister the callback function. + * + * @details Application can register or unregister the callback function which + * will be called to notify the events from the driver. + * + * @param[in] pfCallback : Callback function pointer. + * @param[in] pcbParam : Callback parameter. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully installed the callback function. + * - #ADI_PWR_NULL_POINTER [D] : Failed to install the callback function since the call back function pointer is NULL. + */ +ADI_PWR_RESULT adi_pwr_RegisterCallback( + const ADI_CALLBACK pfCallback, + void *pcbParam + ) +{ + +#ifdef ADI_DEBUG + if(pfCallback == NULL) + { + return(ADI_PWR_NULL_POINTER); + } +#endif + + gpfCallbackFunction = pfCallback; + gpPowcbParam = pcbParam; + + return ADI_PWR_SUCCESS; +} + +/** + * @brief Sets the system external clock frequency + * + * @param[in] ExtClkFreq: External clock frequency in Hz + + * @return Status + * - #ADI_PWR_SUCCESS : Successfully set the external clock as source. + * - #ADI_PWR_INVALID_CLOCK_SPEED [D]: Specified clock is out of range. + * + * @sa adi_pwr_GetClockFrequency () + */ +ADI_PWR_RESULT adi_pwr_SetExtClkFreq (const uint32_t ExtClkFreq) +{ +#ifdef ADI_DEBUG + if(ExtClkFreq > MAXIMUM_EXT_CLOCK) + { + return(ADI_PWR_INVALID_CLOCK_SPEED); + } +#endif + gpioClock = ExtClkFreq; + return(ADI_PWR_SUCCESS); +} + +/** + * @brief Sets the input clock source for PLL multiplexer. + * + * @param[in] eClockID: Clock source to the System PLL multiplexer. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully set the PLL multiplexer clock source. + * - #ADI_PWR_INVALID_CLOCK_ID [D] : Specified clock ID is invalid. + * + * @sa adi_pwr_SetLFClockMux() + */ +ADI_PWR_RESULT adi_pwr_SetPLLClockMux(const ADI_CLOCK_MUX_ID eClockID) +{ + uint32_t tmp; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* Validate the given clock ID */ + switch (eClockID) + { + case ADI_CLOCK_MUX_SPLL_HFOSC: + case ADI_CLOCK_MUX_SPLL_HFXTAL: + case ADI_CLOCK_MUX_SPLL_GPIO: + break; + /* Any other clock ID is not valid since we are configuring the SPLL clock multiplexer. + * Only valid input clock to the multiplexer is HFOSC, HFXTAL, GPIO */ + default: + return(ADI_PWR_INVALID_CLOCK_ID); + } +#endif /* ADI_DEBUG */ + + /* update the mux setting inside a critical region */ + ADI_ENTER_CRITICAL_REGION(); + tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_PLL_IPSEL); + tmp |= (( (uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_SPLL_HFOSC) << BITP_CLKG_CLK_CTL0_PLL_IPSEL); + pADI_CLKG0_CLK->CTL0 = tmp; + ADI_EXIT_CRITICAL_REGION(); + + return(ADI_PWR_SUCCESS); +} + +/** + * @brief Sets the input clock for low frequency clock multiplexer. + * + * @param[in] eClockID: Clock source to the low frequency clock multiplexer. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully LF clock multiplexer clock source. + * - #ADI_PWR_INVALID_CLOCK_ID [D] : Specified clock ID is invalid. + * + * @sa adi_pwr_SetRootClockMux() + * @sa adi_pwr_SetPLLClockMux() + */ +ADI_PWR_RESULT adi_pwr_SetLFClockMux(const ADI_CLOCK_MUX_ID eClockID) +{ + uint32_t tmp; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + switch (eClockID) + { + + case ADI_CLOCK_MUX_LFCLK_LFOSC: + case ADI_CLOCK_MUX_LFCLK_LFXTAL: + break; + /* Any other clock ID is not valid since we are configuring the Low frequency clock multiplexer. + * Only valid input clock to the multiplexer is LFOSC, LFXTAL */ + + default: + return(ADI_PWR_INVALID_CLOCK_ID); + + } +#endif /* ADI_DEBUG */ + + /* update the mux setting inside a critical region */ + ADI_ENTER_CRITICAL_REGION(); + + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + tmp = (pADI_CLKG0_OSC->CTL & ~BITM_CLKG_OSC_CTL_LFCLK_MUX); + tmp |=(((uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_LFCLK_LFOSC) << BITP_CLKG_OSC_CTL_LFCLK_MUX); + pADI_CLKG0_OSC->CTL = tmp; + + ADI_EXIT_CRITICAL_REGION(); + + return(ADI_PWR_SUCCESS); +} + +/** + * @brief Sets clock source for the Reference clock multiplexer. + * + * @param[in] eClockID: Clock source to the reference clock multiplexer. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully set the source for reference clock multiplexer. + * - #ADI_PWR_INVALID_CLOCK_ID [D] : Specified clock ID is invalid. + * + * @sa adi_pwr_SetLFClockMux() + * @sa adi_pwr_SetRootClockMux() + * @sa adi_pwr_SetPLLClockMux() + */ + +ADI_PWR_RESULT adi_pwr_SetRefClockMux(const ADI_CLOCK_MUX_ID eClockID) +{ + uint32_t tmp; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + switch (eClockID) + { + + case ADI_CLOCK_MUX_REF_HFOSC_CLK: + case ADI_CLOCK_MUX_REF_HFXTAL_26MHZ_CLK: + case ADI_CLOCK_MUX_REF_HFXTAL_16MHZ_CLK: + break; + /* Any other clock ID is not valid since we are configuring the out clock multiplexer.*/ + + default: + return(ADI_PWR_INVALID_CLOCK_ID); + } +#endif /* ADI_DEBUG */ + + /* update the mux setting inside a critical region */ + ADI_ENTER_CRITICAL_REGION(); + + tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_RCLKMUX); + tmp |=(((uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_REF_HFOSC_CLK) << BITP_CLKG_CLK_CTL0_RCLKMUX); + pADI_CLKG0_CLK->CTL0 = tmp; + + ADI_EXIT_CRITICAL_REGION(); + + return(ADI_PWR_SUCCESS); +} + +/** + * @brief Sets the source for the root clock multiplexer. + * + * @param[in] eClockID: Clock source to the root clock multiplexer. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully set the source for root clock multiplexer. + * - #ADI_PWR_INVALID_CLOCK_ID [D] : Specified clock ID is invalid. + * + * @sa adi_pwr_SetLFClockMux() + * @sa adi_pwr_SetPLLClockMux() + */ +ADI_PWR_RESULT adi_pwr_SetRootClockMux(const ADI_CLOCK_MUX_ID eClockID) +{ + uint32_t tmp; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + switch (eClockID) + { + case ADI_CLOCK_MUX_ROOT_HFOSC: + case ADI_CLOCK_MUX_ROOT_HFXTAL: + case ADI_CLOCK_MUX_ROOT_SPLL: + case ADI_CLOCK_MUX_ROOT_GPIO: + break; + /* Any other clock ID is not valid since we are configuring the root clock multiplexer. + * Only valid input clock to the multiplexer is HFOSC, HFXTAL, SPLL, GPIO */ + default: + return(ADI_PWR_INVALID_CLOCK_ID); + } +#endif /* ADI_DEBUG */ + + /* update the mux setting inside a critical region */ + ADI_ENTER_CRITICAL_REGION(); + + tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_CLKMUX); + tmp |= (((uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_ROOT_HFOSC) << BITP_CLKG_CLK_CTL0_CLKMUX); + pADI_CLKG0_CLK->CTL0 = tmp; + + ADI_EXIT_CRITICAL_REGION(); + + return(ADI_PWR_SUCCESS); +} + + +/** + * @brief Gets the system external clock frequency. + * Gets the clock frequency of the source connected to the external GPIO clock input source. + * + * @param [in] pExtClock : Pointer to write the external clock frequency. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully returning the external clock frequency. + * - #ADI_PWR_NULL_POINTER [D] : If the given pointer is pointing to NULL. + * - #ADI_PWR_FAILURE [D] : The system is not initialized yet. Call SystemInit before calling this API. + */ +ADI_PWR_RESULT adi_pwr_GetExtClkFreq (uint32_t *pExtClock) +{ +#ifdef ADI_DEBUG + /* Trap here if the app fails to set the external clock frequency. */ + if (0u == gpioClock) + { + return (ADI_PWR_FAILURE); + } + + if(pExtClock == NULL) + { + return (ADI_PWR_NULL_POINTER); + } +#endif + *pExtClock = gpioClock; + return ADI_PWR_SUCCESS; +} + + +/*! + * @brief Get the frequency of the given clock. + * Obtain individual peripheral clock frequencies + * + * @param[in] eClockId : Clock identifier + * @param[out] pClock : Pointer to a location to store the clock frequency. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully returned the queried clock. + * - #ADI_PWR_SYSTEM_NOT_INITIALIZED [D] : The system is not initialized yet. Call SystemInit before calling this API. + * + * @sa adi_PWR_SetClockDivide + * @sa SystemSetClockDivider +*/ +ADI_PWR_RESULT adi_pwr_GetClockFrequency (const ADI_CLOCK_ID eClockId, uint32_t *pClock ) +{ + uint32_t src, nDiv; + +#ifdef ADI_DEBUG + /* trap here if the app fails to call SystemInit(). */ + if ((0u == hfClock) || (0u == lfClock)) + { + return ADI_PWR_SYSTEM_NOT_INITIALIZED; + } +#endif + + /* refresh internal clock variables */ + SystemCoreClockUpdate(); + src = hfClock; + + switch (eClockId) { + + /* HCLOCK domain */ + case ADI_CLOCK_HCLK: + nDiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT; + break; + + /* PCLOCK domain */ + case ADI_CLOCK_PCLK: + nDiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_PCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_PCLKDIVCNT; + break; + + default: + return ADI_PWR_INVALID_CLOCK_ID; + } /* end switch */ + + if(nDiv == 0u) + { + nDiv = 1u; + } + + *pClock = (src/nDiv); + + return ADI_PWR_SUCCESS; +} + + +/*! + @brief Enable/disable individual peripheral clocks. + + @param[in] eClockGate Clock identifier + @param[in] bEnable Flag to indicate whether to enable/disable individual clock. + true - to enable individual clock. + false - to disable individual clock. + + @return Status + - #ADI_PWR_SUCCESS if we have successfully enabled or disabled the clock. + + @details Manage individual peripheral clock gates to enable or disable the clocks to the peripheral. +*/ +ADI_PWR_RESULT adi_pwr_EnableClock (const ADI_CLOCK_GATE eClockGate, const bool bEnable) +{ + uint32_t mask; + ADI_INT_STATUS_ALLOC(); + + mask = (uint16_t)eClockGate; + /* update the Clock Gate register in a critical region */ + ADI_ENTER_CRITICAL_REGION(); + + /* NOTE NEGATIVE LOGIC!!! */ + if (bEnable == true) { + + /* clear disable bit */ + pADI_CLKG0_CLK->CTL5 &= ~mask; + } else { + /* set disable bit */ + pADI_CLKG0_CLK->CTL5 |= mask; + } + + /* end critical region */ + ADI_EXIT_CRITICAL_REGION(); + + return ADI_PWR_SUCCESS; +} + + +/*! + @brief Sets the clock divide factor for an individual clock group. + + @param[in] eClockId Clock domain identifier. + @param[in] nDiv Clock divide value to be set (right-justified uint16_t). + + @return Status + - #ADI_PWR_SUCCESS if successfully set the given clock divide factor. + - #ADI_PWR_INVALID_CLOCK_DIVIDER [D] if the divider is out of range. + - #ADI_PWR_INVALID_CLOCK_ID [D] if the given clock is invalid. + - #ADI_PWR_INVALID_CLOCK_RATIO [D] if the given clock ratio invalid. + + @details Manage individual peripheral clock dividers. + + @sa SystemGetClockFrequency +*/ +ADI_PWR_RESULT adi_pwr_SetClockDivider (const ADI_CLOCK_ID eClockId, const uint16_t nDiv) +{ + uint32_t mask; + uint32_t value; + uint32_t tmp; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + uint32_t hdiv, pdiv; +#endif /*ADI_DEBUG*/ + + switch (eClockId) + { + case ADI_CLOCK_HCLK: +#ifdef ADI_DEBUG + /* Verify the divide factor is within the range */ + if ((nDiv > CLOCK_MAX_DIV_VALUE) || (nDiv < CLOCK_MIN_DIV_VALUE)) + { + return ADI_PWR_INVALID_CLOCK_DIVIDER; + } + + /* verify PCLK freq is <= requested HCLK */ + pdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_PCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_PCLKDIVCNT; + hdiv = nDiv; + if (hdiv > pdiv) { + return ADI_PWR_INVALID_CLOCK_SPEED; + } + + /* verify new PDIV:HDIV ratio will be integral */ + if ((pdiv % hdiv) != 0u) + { + return ADI_PWR_INVALID_CLOCK_RATIO; + } +#endif /*ADI_DEBUG*/ + + mask = BITM_CLKG_CLK_CTL1_HCLKDIVCNT; + value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_HCLKDIVCNT; + break; + + case ADI_CLOCK_PCLK: +#ifdef ADI_DEBUG + + /* Verify the divide factor is within the range */ + if ((nDiv > CLOCK_MAX_DIV_VALUE) || (nDiv < CLOCK_MIN_DIV_VALUE)) + { + return ADI_PWR_INVALID_CLOCK_DIVIDER; + } + + /* verify requested PCLK freq is <= HCLK */ + pdiv = nDiv; + hdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT; + if (hdiv > pdiv) { + return ADI_PWR_INVALID_CLOCK_SPEED; + } + + /* verify new PDIV:HDIV ratio will be integral */ + if ((pdiv % hdiv) != 0u) + { + return ADI_PWR_INVALID_CLOCK_RATIO; + } +#endif /*ADI_DEBUG*/ + mask = BITM_CLKG_CLK_CTL1_PCLKDIVCNT; + value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_PCLKDIVCNT; + break; + + case ADI_CLOCK_ACLK: +#ifdef ADI_DEBUG + /* Verify the divide factor is within the range */ + if ((nDiv > ACLK_MAX_DIV_VALUE) || (nDiv < ACLK_MIN_DIV_VALUE)) + { + return ADI_PWR_INVALID_CLOCK_DIVIDER; + } + + /* verify requested ACLK freq is <= HCLK */ + pdiv = nDiv; + hdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT; + if (hdiv > pdiv) { + return ADI_PWR_INVALID_CLOCK_SPEED; + } + + /* verify new PDIV:HDIV ratio will be integral */ + if ((pdiv % hdiv) != 0u) + { + return ADI_PWR_INVALID_CLOCK_RATIO; + } +#endif /*ADI_DEBUG*/ + + mask = BITM_CLKG_CLK_CTL1_ACLKDIVCNT; + value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_ACLKDIVCNT; + break; + + + default: + return ADI_PWR_INVALID_CLOCK_ID; + } /* end switch */ + + /* critical region */ + ADI_ENTER_CRITICAL_REGION(); + + /* read-modify-write without any interrupts */ + /* change in a tmp variable and write entire new value all at once */ + tmp = pADI_CLKG0_CLK->CTL1; + tmp &= ~mask; /* blank the field */ + tmp |= value; /* set the new value */ + pADI_CLKG0_CLK->CTL1 = tmp; /* write the new value */ + + /* end critical region */ + ADI_EXIT_CRITICAL_REGION(); + + /* refresh internal clock variables */ + SystemCoreClockUpdate(); + + return ADI_PWR_SUCCESS; +} + +/*! + * @brief To Enable/disable clock sources. + * + * @param[in] eClockSource : Clock source identifier. + * @param[in] bEnable : Enable (true) or disable (false) the clock source. + * + * @return Status + * - #ADI_PWR_SUCCESS if the clock source powers up successfully. + * - #ADI_PWR_INVALID_PARAM if the clock source is not valid. + * + * @details Enables or disables clock sources without additional checks, by writing a "1" or "0" to the enable bit. + * + */ +ADI_PWR_RESULT adi_pwr_EnableClockSource (const ADI_CLOCK_SOURCE_ID eClockSource, const bool bEnable) +{ + uint32_t val = 0u; + volatile uint32_t *pReg = NULL; + uint32_t nMask = 0u; + ADI_INT_STATUS_ALLOC(); + + /* This switch statement does not handle every value in the ADI_CLOCK_SOURCE_ID enumeration + * which results on a gcc warning. This is done intentionally: + * ADI_CLOCK_SOURCE_LFOSC is not checked because it is enabled always and it cannot be disabled + * ADI_CLOCK_SOURCE_GPIO is only checked if a specific configuration macro is defined + */ + switch(eClockSource) + { + case ADI_CLOCK_SOURCE_HFXTAL: + val = (1u << BITP_CLKG_OSC_CTL_HFX_EN); + pReg = &pADI_CLKG0_OSC->CTL; + nMask = BITM_CLKG_OSC_CTL_HFX_OK; + break; + + case ADI_CLOCK_SOURCE_LFXTAL: + val = (1u << BITP_CLKG_OSC_CTL_LFX_EN); + pReg = &pADI_CLKG0_OSC->CTL; + nMask = BITM_CLKG_OSC_CTL_LFX_OK; + break; + + case ADI_CLOCK_SOURCE_HFOSC: + val = (1u << BITP_CLKG_OSC_CTL_HFOSC_EN); + pReg = &pADI_CLKG0_OSC->CTL; + nMask = BITM_CLKG_OSC_CTL_HFOSC_OK; + break; + + case ADI_CLOCK_SOURCE_SPLL: + val = (1u << BITP_CLKG_CLK_CTL3_SPLLEN); + pReg = &pADI_CLKG0_CLK->CTL3; + nMask = BITM_CLKG_CLK_CTL3_SPLLEN; + break; + +#if (ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO == 1) + case ADI_CLOCK_SOURCE_GPIO: + if(adi_gpio_PullUpEnable(ADI_GPIO_PORT1,ADI_GPIO_PIN_10,false) != ADI_GPIO_SUCCESS) + { + return(ADI_PWR_FAILURE); + } + if(adi_gpio_InputEnable(ADI_GPIO_PORT1,ADI_GPIO_PIN_10,true) != ADI_GPIO_SUCCESS) + { + return ADI_PWR_SUCCESS; + } + break; +#endif + + default: + return(ADI_PWR_INVALID_PARAM); + + } /* end switch */ + + ADI_ENTER_CRITICAL_REGION(); + + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + if (bEnable == true) + { + *pReg |= val; + } + else + { + *pReg &= ~val; + } + + ADI_EXIT_CRITICAL_REGION(); + + if((nMask !=0u) && (bEnable == true)) + { + while(0u== (pADI_CLKG0_OSC->CTL & nMask)){} + } + + return (ADI_PWR_SUCCESS); +} + + +/*! + * @brief Return the status of a clock source. + * + * @param[in] eClockSource : Clock source identifier. + * @param[out] peStatus : Pointer to variable of type #ADI_CLOCK_SOURCE_STATUS for storing clock source status. + * + * @return Status + * - #ADI_PWR_SUCCESS if the clock source is disabled. + * - #ADI_PWR_NULL_POINTER [D] if the given pointer is pointing to NULL. + + * @details Return the status of a clock source. + * + */ +ADI_PWR_RESULT adi_pwr_GetClockStatus (const ADI_CLOCK_SOURCE_ID eClockSource, ADI_CLOCK_SOURCE_STATUS *peStatus) +{ + uint32_t val = pADI_CLKG0_OSC->CTL; + +#ifdef ADI_DEBUG + if(peStatus == NULL) + { + return ADI_PWR_NULL_POINTER; + } +#endif /* ADI_DEBUG */ + + *peStatus = ADI_CLOCK_SOURCE_DISABLED; + + switch(eClockSource) + { + case ADI_CLOCK_SOURCE_HFOSC: + if ((val & BITM_CLKG_OSC_CTL_HFOSC_EN) != 0u) + { + /* Clock source enabled, now check for stable */ + if ((val & BITM_CLKG_OSC_CTL_HFOSC_OK) != 0u) + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_STABLE; + } + else + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE; + } + } + break; + + case ADI_CLOCK_SOURCE_HFXTAL: + if ((val & BITM_CLKG_OSC_CTL_HFX_EN) != 0u) + { + /* Clock source enabled, now check for stable */ + if ((val & BITM_CLKG_OSC_CTL_HFX_OK) != 0u) + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_STABLE; + } + else + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE; + } + } + break; + + case ADI_CLOCK_SOURCE_LFXTAL: + if ((val & BITM_CLKG_OSC_CTL_LFX_EN) != 0u) + { + /* Clock source enabled, now check for stable */ + if ((val & BITM_CLKG_OSC_CTL_LFX_OK) != 0u) + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_STABLE; + } + else + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE; + } + } + break; + + case ADI_CLOCK_SOURCE_LFOSC: + /* Clock source enabled, now check for stable */ + if ((val & BITM_CLKG_OSC_CTL_LFOSC_OK) != 0u) + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_STABLE; + } + else + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE; + } + break; + + /* Since the clock through GPIO is supplied externally we cannot get + the clock status for GPIO */ + case ADI_CLOCK_SOURCE_GPIO: + default: + *peStatus = ADI_CLOCK_SOURCE_ID_NOT_VALID; + break; + + } /* end switch */ + + return ADI_PWR_SUCCESS; +} + +/*! + * @brief Enable/Disable the clock interrupt to monitor status of LFXTAL, HFXTAL and PLL. + * + * @param[in] eIrq : Specify which interrupt need to be enable/disabled. + @param[in] bEnable : Specifies to enable/disable the specified interrupt. + * + * @return Status + * - #ADI_PWR_SUCCESS Enabled the specified interrupt. + * + * @sa adi_pwr_SetVoltageRange() + */ + +ADI_PWR_RESULT adi_pwr_EnableClockInterrupt(const ADI_PWR_CLOCK_IRQ eIrq, const bool bEnable) +{ + ADI_INT_STATUS_ALLOC(); + volatile uint32_t *pReg = NULL; + uint32_t tmp; + + switch(eIrq) + { + /*! Interrupt for root clock monitor and Clock Fail */ + case ADI_PWR_ROOT_CLOCK_MON_IEN: + pReg = &pADI_CLKG0_OSC->CTL; + break; + + /*! Interrupt for LFXTAL clock monitor and Clock Fail */ + case ADI_PWR_LFXTAL_CLOCK_MON_IEN: + pReg = &pADI_CLKG0_OSC->CTL; + break; + + /*! Interrupt when LFXTAL clock becomes stable/unstable */ + case ADI_PWR_LFXTAL_STATUS_IEN: + pReg = &pADI_CLKG0_CLK->CTL0; + break; + + /*! Interrupt when HFXTAL clock becomes stable/unstable */ + case ADI_PWR_HFXTAL_STATUS_IEN: + pReg = &pADI_CLKG0_CLK->CTL0; + break; + + /*! Interrupt when PLL-LOCK/PLL-UNLOCK */ + case ADI_PWR_PLL_STATUS_IEN: + pReg = &pADI_CLKG0_CLK->CTL3; + break; + + default: + break; + } + + ADI_ENTER_CRITICAL_REGION(); + + tmp = *pReg; + + if(bEnable == true) + { + tmp |= (uint32_t)eIrq; + } + else + { + tmp &= ~((uint32_t)eIrq); + } + + /* If we have to write to oscillator control register unlock it */ + if(pReg == &pADI_CLKG0_OSC->CTL) + { + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + } + *pReg = tmp; + + ADI_EXIT_CRITICAL_REGION(); + + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Program PLL frequency. + * + * @param[in] nDivFactor PLL divider(M). + * @param[in] nMulFactor PLL Multiplier(N) + * @param[in] bDiv2 PLL DIV2 parameter. + * @param[in] bMul2 PLL DIV2 parameter. + * + * @return Status + * - #ADI_PWR_SUCCESS if the PLL has been programmed successfully. + * - #ADI_PWR_OPERATION_NOT_ALLOWED [D] if trying to program SPLL and SPLL drives the system clock. + * - #ADI_PWR_INVALID_CLOCK_ID [D] if the clock identifier does not match either PLL. + * + * @details Program PLL frequency (parameters M, N, DIV2) forSystem PLL(SPLL). + * + * SPLL = input clock * ["(N * (1+ bMul2 )" / "((1+bDiv2)*M)" ] + * where input clock can be HFOSC or HFXTAL. + */ +ADI_PWR_RESULT adi_pwr_SetPll(uint8_t nDivFactor, const uint8_t nMulFactor, const bool bDiv2, const bool bMul2) +{ + uint32_t val, cfg = 0u; + uint8_t nTempDivFactor = nDivFactor, nTempMulFactor = nMulFactor; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* Check if multiplication factor and division factor is more than 6 bits */ + if (((nMulFactor & ~0x3Fu) != 0u) || ((nDivFactor & ~0x3Fu) != 0u)) + { + return ADI_PWR_INVALID_CLOCK_DIVIDER; + } + + /* Check if the PLL is multipexed in as root clock source, parameters should not change in that case */ + if((pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_CLKMUX) == + ((uint32_t)((ADI_CLOCK_MUX_ROOT_SPLL - ADI_CLOCK_MUX_ROOT_HFOSC) << BITP_CLKG_CLK_CTL0_CLKMUX))) + { + return ADI_PWR_OPERATION_NOT_ALLOWED; + } +#endif + + if(nTempDivFactor < MINIMUM_PLL_DIVIDER) + { + nTempDivFactor = MINIMUM_PLL_DIVIDER; + } + if(nTempMulFactor < MINIMUM_PLL_MULTIPLIER) + { + nTempMulFactor = MINIMUM_PLL_MULTIPLIER; + } + + cfg = (((uint32_t)nTempDivFactor) << BITP_CLKG_CLK_CTL3_SPLLMSEL)|( ((uint32_t) nTempMulFactor) << BITP_CLKG_CLK_CTL3_SPLLNSEL); + + if(bDiv2 == true) + { + cfg |= (1u <CTL3; + val &= ~( BITM_CLKG_CLK_CTL3_SPLLMUL2 | BITM_CLKG_CLK_CTL3_SPLLMSEL | BITM_CLKG_CLK_CTL3_SPLLDIV2 | BITM_CLKG_CLK_CTL3_SPLLNSEL); + val |= cfg; + pADI_CLKG0_CLK->CTL3 = val; + + /* end critical region */ + ADI_EXIT_CRITICAL_REGION(); + + return ADI_PWR_SUCCESS; +} + + +/*! + * @brief Enable/Disable the power management interrupt. + * + * @param[in] eIrq : Specify which interrupt need to be enable/disabled. + @param[in] bEnable : Specifies to enable/disable the interrupt. + * + * @return Status + * - #ADI_PWR_SUCCESS Enabled the specified interrupt. + * - #ADI_PWR_FAILURE [D] Enabling the battery monitoring interrupt when range is set to safe range (VBAT > 2.75 ). + * + * @note : User should configure the appropriate voltage range before enabling the interrupt for battery voltage range. + * + * @sa adi_pwr_SetVoltageRange() + */ +ADI_PWR_RESULT adi_pwr_EnablePMGInterrupt(const ADI_PWR_PMG_IRQ eIrq, const bool bEnable) +{ + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + if(((pADI_PMG0->IEN & BITM_PMG_IEN_RANGEBAT) == 0u) || (eIrq != ADI_PWR_BATTERY_VOLTAGE_RANGE_IEN)) + { + return(ADI_PWR_FAILURE); + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + if(bEnable == true) + { + pADI_PMG0->IEN |= (uint32_t)eIrq; + } + else + { + pADI_PMG0->IEN &= ~(uint32_t)(eIrq); + } + ADI_EXIT_CRITICAL_REGION(); + + return(ADI_PWR_SUCCESS); +} + + + +/*! + * @brief Enable/disable LFXTAL bypass mode. + * + @param[in] bEnable : Specifies to enable/disable the LFXTAL bypass mode + *\n true: To enable LFXTAL bypass mode. + * \n false: To disable LFXTAL bypass mode. + * @return Status + * - #ADI_PWR_SUCCESS Enabled/Disabled LFXTAL bypass mode. + * - #ADI_PWR_FAILURE[D] Failed to Enable/Disable LFXTAL bypass mode. + * + */ +ADI_PWR_RESULT adi_pwr_EnableLFXTALBypass(const bool bEnable) +{ + volatile uint32_t nDelay = 0xFFFFFFu; + if(bEnable == true) + { + /* Write the oscillator key */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + /* Disable the LFXTAL */ + pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_EN); + /* Wait till status de-asserted. */ + while(nDelay != 0u) + { + if((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK) == 0u) + { + break; + } + nDelay--; + } +#ifdef ADI_DEBUG + if(nDelay == 0u) + { + return(ADI_PWR_FAILURE); + } +#endif + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + /* Enable the BYPASS mode */ + pADI_CLKG0_OSC->CTL |= (BITM_CLKG_OSC_CTL_LFX_BYP); + /* Wait till status asserted. */ + nDelay = 0xFFFFFFu; + while(nDelay != 0u) + { + if(((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK)== BITM_CLKG_OSC_CTL_LFX_OK)) + { + break; + } + nDelay--; + } +#ifdef ADI_DEBUG + if(nDelay == 0u) + { + return(ADI_PWR_FAILURE); + } +#endif + + } + else + { + /* Write the oscillator key */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + /* Disable the BYPASS mode */ + pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_BYP); + /* Wait till status de-asserted. */ + while(nDelay != 0u) + { + if((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK) == 0u) + { + break; + } + nDelay--; + } +#ifdef ADI_DEBUG + if(nDelay == 0u) + { + return(ADI_PWR_FAILURE); + } +#endif + } + + return(ADI_PWR_SUCCESS); +} + + + +/*! + * @brief Enables or disables the LFXTAL Robust mode. + * The Robust mode enables the LFXTAL oscillator to work also when an additional resistive + * load is placed between the crystal pins and GND. This feature is capable of tolerating + * the presence of impurities on the PCB board, where these impurities allow a high-resistance + * leakage path from the crystal pins to ground, which can cause problems to the circuit operation + * + * @param[in] bEnable : Flag which indicates whether to enable or disable LFXTAL Robust mode. + true - Enable Robust mode. + false - Disable Robust mode. + * @return Status + * - #ADI_PWR_SUCCESS Enabled/Disabled LFXTAL Robust mode. + * + * @sa adi_pwr_SetLFXTALRobustModeLoad() + */ +ADI_PWR_RESULT adi_pwr_EnableLFXTALRobustMode( const bool bEnable ) +{ + /* Write the oscillator key */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + + if(bEnable == true) + { + pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_LFX_ROBUST_EN; + } + else + { + pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_ROBUST_EN); + } + + return(ADI_PWR_SUCCESS); +} + +/*! + * @brief Enable/Disable the LFXTAL Fail Auto switch. + * Enables/Disable automatic Switching of the LF Mux to LF OSC on LF XTAL Failure. + * + * @param[in] bEnable : Flag which indicates whether to enable/disable LFXTAL Auto switch. + * true - Enable LFXTAL Auto switch. + * false - Disable LFXTAL Auto switch. + * @return Status + * - #ADI_PWR_SUCCESS Enabled/Disabled LFXTAL Auto switch mode. + */ +ADI_PWR_RESULT adi_pwr_EnableLFXTALFailAutoSwitch( const bool bEnable ) +{ + /* Write the oscillator key */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + + if(bEnable == true) + { + pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_LFX_AUTSW_EN; + } + else + { + pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_AUTSW_EN); + } + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Sets the LFXT Robust Mode Load. + * Selects the amount of loading tolerated when LFXTAL robust mode is enabled. + * + * @param[in] eLoad : Amount of loading tolerance required. + * @return Status + * - #ADI_PWR_SUCCESS Successfully set the load tolerance for LFXTAL Robust mode. + * + * @sa adi_pwr_EnableLFXTALRobustMode() + */ +ADI_PWR_RESULT adi_pwr_SetLFXTALRobustModeLoad( const ADI_PWR_LFXTAL_LOAD eLoad ) +{ + uint32_t tmp; + + tmp = pADI_CLKG0_OSC->CTL & ~BITM_CLKG_OSC_CTL_LFX_ROBUST_LD; + tmp |= ((uint32_t)eLoad) << BITP_CLKG_OSC_CTL_LFX_ROBUST_LD; + + /* Write the oscillator key */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + pADI_CLKG0_OSC->CTL = tmp; + + return(ADI_PWR_SUCCESS); +} + +/*! + * @brief To enable/disable auto switching of root clock to HFOSC upon detection of Root clock failure. + * This feature is valid only when the ROOT clock monitor is enabled. The root clock monitoring + * can be enabled by using the API #adi_pwr_EnableClockInterrupt. + * + * @param[in] bEnable : Flag which indicates whether to enable or disable Root clock auto switch. + * true - Enable Root clock auto switch. + false - Disable Root clock auto switch. + * @return Status + * - #ADI_PWR_SUCCESS Successfully set the load tolerance for LFXTAL Robust mode. + * + * @sa adi_pwr_EnableClockInterrupt() + */ +ADI_PWR_RESULT adi_pwr_EnableRootClockFailAutoSwitch( const bool bEnable ) +{ + /* Write the oscillator key */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + + if(bEnable == true) + { + pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_ROOT_AUTSW_EN; + } + else + { + pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_ROOT_AUTSW_EN); + } + + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Sets the HF Oscillator divide factor. + * + * Sets the divide factor for the clocks derived from the HF oscillator clock. + * + * @param[in] eDivFactor : HF Clock divide factor to be set. + * + * @return Status + * - #ADI_PWR_SUCCESS Successfully set the clock divide factor for HF Oscillator. + * + * @note When the HF Oscillator auto divide by 1 is set, the divide factor set is automatically + * changed to 1 when coming out of Flexi mode. Application should set it back to the + * required divide after coming out of Flexi mode. + * + * @sa adi_pwr_EnableHFOscAutoDivBy1() + */ +ADI_PWR_RESULT adi_pwr_SetHFOscDivFactor( const ADI_PWR_HFOSC_DIV eDivFactor ) +{ + uint32_t tmp; + + tmp = (pADI_CLKG0_CLK->CTL2 & ~BITM_CLKG_CLK_CTL2_HFOSCDIVCLKSEL); + tmp |= ((uint32_t) eDivFactor << BITP_CLKG_CLK_CTL2_HFOSCDIVCLKSEL); + pADI_CLKG0_CLK->CTL2 = tmp; + + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Enable or disable the HF oscillator automatic divide by 1 during wakeup from Flexi mode. + * + * This is used to enable/disable the fast wakeup from Flexi power mode. When the fast wakeup + * from Flexi mode is enabled, the frequency undivided 26MHz HF oscillator clock itself will + * be used during the wake up. The undivided HFOSC clock is selected automatically by setting + * the HF oscillator divide factor to 1. This updated divided by 1 clock selection will remain + * same until the new divider value is set. + * + * When disabled the HF Oscillator divide factor will remain unchanged during the wakeup. + * + * @param[in] bEnable : Flag which indicates whether HF oscillator automatic divide by 1 is enabled/disabled. + * 'true' - To enable automatic divide by 1. + * 'false' - To disable automatic divide by 1. + * + * @return Status + * - #ADI_PWR_SUCCESS Successfully enable/disabled HF Oscillator automatic divide by 1. + * + * @sa adi_pwr_SetHFOscDivFactor() + */ +ADI_PWR_RESULT adi_pwr_EnableHFOscAutoDivBy1( const bool bEnable ) +{ + if(bEnable == true) + { + pADI_CLKG0_CLK->CTL2 |= BITM_CLKG_CLK_CTL2_HFOSCAUTODIV_EN; + } + else + { + pADI_CLKG0_CLK->CTL2 &= ~(BITM_CLKG_CLK_CTL2_HFOSCAUTODIV_EN); + } + + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Set the clock output through the GPIO. + * + * @param[in] eClockOutput : Clock to be output through the GPIO pin. + * + * @return Status + * - #ADI_PWR_SUCCESS Successfully set the GPIO clock output. + */ +ADI_PWR_RESULT adi_pwr_SetGPIOClockOutput( const ADI_CLOCK_OUTPUT_ID eClockOutput ) +{ + uint32_t tmp; + + tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_CLKOUT); + tmp |= ((uint32_t)eClockOutput << BITP_CLKG_CLK_CTL0_CLKOUT); + pADI_CLKG0_CLK->CTL0 = tmp; + + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Enables or disables the HP Buck. + * + * @param[in] bEnable : Flag which indicates whether to enable or disable HPBuck + * 'true' - To enable HPBuck. + * 'false' - To disable HPBuck. + * @return Status + * - #ADI_PWR_SUCCESS Successfully enabled or disabled HPBUCK successfully. + */ +ADI_PWR_RESULT adi_pwr_EnableHPBuck(const bool bEnable) +{ + if(bEnable == true) + { + pADI_PMG0->CTL1 |= BITM_PMG_CTL1_HPBUCKEN; + } + else + { + pADI_PMG0->CTL1 &= ~(BITM_PMG_CTL1_HPBUCKEN); + } + + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Enable or disable the HPBuck Low Power mode. + * The HPBUCK Low Power mode can be selected, when the Chip is in Flexi Power mode + * and low power modules such as Timer, Beeper only are enabled. + * + * @param[in] bEnable : Flag which indicates whether to enable or disable HPBuck low power mode. + * 'true' - Enable HPBuck low power mode. + * 'false' - Disable HPBuck low power mode. + * @return Status + * - #ADI_PWR_SUCCESS Successfully enabled or disabled the HPBuck low power mode. + */ +ADI_PWR_RESULT adi_pwr_EnableHPBuckLowPowerMode( const bool bEnable ) +{ + if(bEnable == true) + { + pADI_PMG0->CTL1 |= BITM_PMG_CTL1_HPBUCK_LOWPWR_MODE; + } + else + { + pADI_PMG0->CTL1 &= ~(BITM_PMG_CTL1_HPBUCK_LOWPWR_MODE); + } + + return(ADI_PWR_SUCCESS); +} + +/*! + * @brief Set the HP Buck load mode. + * + * HP Buck load mode can be set based on the system load. + * The low load mode can be set when the system is running below 26Mhz. + * The High load mode can be set when the system is running at greater than 26Mhz. + * + * @param[in] eLoadMode : Load mode to be set. + * + * @return Status + * - #ADI_PWR_SUCCESS Successfully set the load mode. + */ +ADI_PWR_RESULT adi_pwr_SetHPBuckLoadMode( const ADI_PWR_HPBUCK_LD_MODE eLoadMode ) +{ + if(eLoadMode == ADI_PWR_HPBUCK_LD_MODE_HIGH) + { + pADI_PMG0->CTL1 |= BITM_PMG_CTL1_HPBUCK_LD_MODE; + } + else + { + pADI_PMG0->CTL1 &= ~(BITM_PMG_CTL1_HPBUCK_LD_MODE); + } + + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Function to retrieve the wakeup from shut down mode status. + * + * @param[in] peStatus : Pointer to #ADI_PWR_WAKEUP_STATUS for returning the wakeup status. + * + * @return Status + * - #ADI_PWR_SUCCESS: Successfully returned the shut down status. + */ +ADI_PWR_RESULT adi_pwr_GetWakeUpStatus(ADI_PWR_WAKEUP_STATUS *peStatus) +{ + *peStatus =(ADI_PWR_WAKEUP_STATUS) pADI_PMG0->SHDN_STAT; + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief To Monitor voltage range of battery. + * + * @param[in] eRange : Specify the voltage range for the battery. + * + * @return Status + * - #ADI_PWR_SUCCESS: Successfully programmed battery range. + * @details + * + */ +ADI_PWR_RESULT adi_pwr_SetVoltageRange(const ADI_PWR_VOLTAGE_RANGE eRange) +{ + uint32_t tmp; + + tmp = (pADI_PMG0->IEN & ~BITM_PMG_IEN_RANGEBAT); + tmp |= ((uint32_t)eRange << BITP_PMG_IEN_RANGEBAT); + pADI_PMG0->IEN = tmp; + + return(ADI_PWR_SUCCESS); +} + +/*! \cond PRIVATE */ + +/* + * Interrupt handler for PLL interrupts. + */ +void PLL_Int_Handler(void) +{ + ISR_PROLOG(); + + /* As the same status word is shared between two interrupts + Crystal_osc_Int_Handler and PLL_Int_Handler + check and clear status bits handled in this handler */ + uint32_t nStatus = (pADI_CLKG0_CLK->STAT0 & + (BITM_CLKG_CLK_STAT0_SPLLUNLK | BITM_CLKG_CLK_STAT0_SPLLLK)); + + /* If a callback is registered notify the events */ + if(gpfCallbackFunction != NULL) + { + if((nStatus & BITM_CLKG_CLK_STAT0_SPLLUNLK ) != 0u) + { + /* PLL unlock event */ + gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_PLLC_UNLOCK,(void *)0); + } + else if((nStatus & BITM_CLKG_CLK_STAT0_SPLLLK) != 0u) + { + /* PLL lock event */ + gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_PLLC_LOCK,(void *)0); + } + else + { + /* Do nothing */ + } + } + + /* Clear the status bits */ + pADI_CLKG0_CLK->STAT0 = nStatus; + + ISR_EPILOG(); +} + +/* + * Interrupt handler for oscillator interrupts. + */ +void Crystal_osc_Int_Handler(void) +{ + ISR_PROLOG(); + + /* As the same status word is shared between two interrupts + Crystal_osc_Int_Handler and PLL_Int_Handler + check and clear status bits handled in this handler */ + uint32_t nClkStatus = (pADI_CLKG0_CLK->STAT0 & + (BITM_CLKG_CLK_STAT0_HFXTALNOK | + BITM_CLKG_CLK_STAT0_HFXTALOK | + BITM_CLKG_CLK_STAT0_LFXTALOK | + BITM_CLKG_CLK_STAT0_LFXTALNOK)); + + /* Check if the interrupt was generated due to failure in Root Clock or LFXTAL */ + uint32_t nOscStatus = (pADI_CLKG0_OSC->CTL & (BITM_CLKG_OSC_CTL_LFX_FAIL_STA | + BITM_CLKG_OSC_CTL_ROOT_FAIL_STA | + BITM_CLKG_OSC_CTL_ROOT_AUTSW_STA | + BITM_CLKG_OSC_CTL_LFX_AUTSW_STA )); + + uint32_t nEvent = 0u; + + + if(gpfCallbackFunction != NULL) + { + /* Is the interrupt caused due to HFXTAL or LFXTAL status */ + if(nClkStatus != 0u) + { + if ((nClkStatus & BITM_CLKG_CLK_STAT0_HFXTALNOK) != 0u) { nEvent |= ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_NO_OK; } + else if ((nClkStatus & BITM_CLKG_CLK_STAT0_HFXTALOK) != 0u) { nEvent |= ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_OK; } + else if ((nClkStatus & BITM_CLKG_CLK_STAT0_LFXTALOK) != 0u) { nEvent |= ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_OK; } + else if ((nClkStatus & BITM_CLKG_CLK_STAT0_LFXTALNOK) != 0u) { nEvent |= ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_NO_OK; } + else { /* do nothing */ } + + if(nEvent != 0u) { gpfCallbackFunction( gpPowcbParam, nEvent, (void *)0u); } + + } + /* Or is the interrupt caused due to Root Clock or LFXTAL failure status */ + else if(nOscStatus != 0u) + { + /* Did the LFXTAL failed */ + if( (nOscStatus & BITM_CLKG_OSC_CTL_LFX_FAIL_STA) != 0u) + { + /* Notifiy LFXTAL failure */ + gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_LFXTAL_MON_FAIL, (void *)0u); + + /* Did the HW auto switched to LFOSC due to LFXTAL failure */ + if((nOscStatus & BITM_CLKG_OSC_CTL_LFX_AUTSW_STA) != 0u) + { + /* Notify about the auto switch to LFOSC */ + gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_LFXTAL_AUTO_SWITCH, (void *)0u); + } + } + /* Did the root clock failed */ + else if((nOscStatus & BITM_CLKG_OSC_CTL_ROOT_FAIL_STA) != 0u) + { + /* Indicate about the root clock failure */ + gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_ROOT_CLOCK_MON_FAIL, (void *)0u); + + /* Did the HW auto switched to HFOSC due to root clock failure */ + if((nOscStatus & BITM_CLKG_OSC_CTL_ROOT_AUTSW_STA) != 0u) + { + /* Notify about auto switch to HFOSC */ + gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_ROOT_CLOCK_FAIL_AUTO_SWITCH, (void *)0u); + } + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } + } + + /* Clear the staus bits */ + if(nClkStatus != 0u) + { + pADI_CLKG0_CLK->STAT0 = nClkStatus; + } + else if(nOscStatus != 0u) + { + /* Write the oscillator key to clear the status bits */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + + /* Clear only status bits */ + pADI_CLKG0_OSC->CTL |= nOscStatus; + } + else + { + /* Do nothing */ + } + + ISR_EPILOG(); +} + +/* + * Interrupt handler for battery voltage interrupt. + */ +void Battery_Voltage_Int_Handler(void) +{ + ISR_PROLOG(); + uint32_t nStatus = pADI_PMG0->PSM_STAT; + + if ((nStatus & BITM_PMG_PSM_STAT_VBATUNDR) != 0u) + { + if(gpfCallbackFunction != NULL) + { + gpfCallbackFunction( gpPowcbParam, (uint32_t)nStatus, (void *)0); + } + pADI_PMG0->PSM_STAT |= (BITM_PMG_PSM_STAT_VBATUNDR); + } + ISR_EPILOG(); +} + +/* + * Interrupt handler for battery voltage interrupt. + */ +void Vreg_over_Int_Handler(void) +{ + ISR_PROLOG(); + uint32_t nStatus = pADI_PMG0->PSM_STAT; + + if(gpfCallbackFunction != NULL) + { + if ((nStatus & BITM_PMG_PSM_STAT_VREGOVR) != 0u) + { + gpfCallbackFunction(gpPowcbParam, (uint32_t)ADI_PWR_EVENT_VREG_OVER_VOLTAGE, NULL); + } + if ((nStatus & BITM_PMG_PSM_STAT_VREGUNDR) != 0u) + { + gpfCallbackFunction(gpPowcbParam, (uint32_t)ADI_PWR_EVENT_VREG_UNDER_VOLTAGE, NULL); + } + } + pADI_PMG0->PSM_STAT |= (nStatus &(BITM_PMG_PSM_STAT_VREGOVR | BITM_PMG_PSM_STAT_VREGUNDR)); + ISR_EPILOG(); +} + +/*! \endcond */ +/*! + @brief Puts the processor into given low power mode. + + @param[in] PowerMode One of the ADI_PWR_POWER_MODE enum values, defining the specific + low-power modes to use. + + @param[in,out] pnInterruptOccurred + Control parameter selection low-power operation. Either a NULL pointer + for automatic hardware-based sleeping between interrupts, or a pointer + to uint32_t for software looping sleep between interrupts. + + If a pointer to uint32_t is passed in, the integer must be \b 0 on entry, + and will be set to \b 0 on exit. + + When a NULL is passed, it means the application wants the low-power + implementation to use the automatic "sleep-on-exit" hardware sleep + mode in which wakeup interrupts are dispatched and then automatically + put the processor back to sleep on exit. All interrupts execute the + same WFI instruction (no looping) under hardware control, which results + in a faster re-sleep than the software mode. + + When a non-NULL value is passed, it is interpreted as a pointer to a + shared integer application control variable allowing the wake-up + interrupts to control whether/when the control loop should re-sleep the + processor as each interrupt exits. Any interrupt that sets the variable + will cause the sleep loop to exit. Otherwise, exiting interrupts will + cause the core to re-sleep until the variable is set. Each interrupt executes + a different WFI instruction inside a software loop (slower re-sleep). + + @param[in] PriorityMask A right-justified (un shifted) wakeup interrupt priority mask, corresponding + to the programmable interrupt priority encoding scheme defined by the Cortex + NVIC controller. The \a PriorityMask value blocks interrupts with an equal + or lower priority than the specified level, such that only higher-priority + interrupts (less in numerical value) than the priority mask awake the + processor. A zero-valued \a PriorityMask disables interrupt masking. + + @return Status + - #ADI_PWR_SUCCESS If successfully put the processor into low power mode. + - #ADI_PWR_INVALID_PARAM[D] PriorityMask contains unimplemented hardware bits. + + + + Puts the processor into a low-power mode with interrupt-based wakeup(s). Applications specify the low-power + mode, a pointer to an application-defined interrupt variable, and an interrupt priority mask controlling the + interrupt priority level that may awake the processor. + + @par pnInterruptOccurred + When NULL, the processor is automatically put back to sleep as awaking interrupts exit. This mode employs + the hardware "sleep-on-exit" system control register bit: SLEEPONEXIT_BIT in conjunction with the "wait-for- + interrupt" (WFI) instruction to implement a persistent sleep mode. + + When non-Null, a software strategy is used to control sleeping. As awakening interrupts are processed, they + can increment the interrupt controlling variable and thereby cause the sleep mode to be exited. Note that all + interrupts share a common variable and any interrupt that sets the variable will cause the sleep mode to be + exited. + + Use of the \a pnInterruptOccurred parameter provides a mechanism to resolve two potential hibernation trouble + spots: 1) the inherent race between the intended wakeup interrupt and the execution of the Wait-For-Interrupt + instruction (WFI) used to sleep the processor, and 2) unrelated interrupts (of sufficient priority) + that may terminate the wait prematurely. + + In the first case of the race condition, the race is avoided by testing the \a pnInterruptOccurred variable prior + to the WFI within a common critical section. This allows the #adi_pwr_EnterLowPowerMode() implementation + to insure the intended wakeup interrupt has not occurred already and control whether to sleep the processor. + This insures the intended wakeup interrupt has not already occurred prior to the wait, thereby eliminating the + race condition otherwise present. + + In the second case of an unrelated interrupt terminating the sleep prematurely, the problem is solved by + requiring the interrupt handler(s) which is(are) intended to awake the sleeping processor to set the + application-defined \a pnInterruptOccurred variable in their respective interrupt handler(s). This insures only those + interrupts that explicitly set the variable will break the sleeping processor out of the sleep cycle. Other + (incidental) interrupts put the processor back to sleep after the interrupt because the variable would not have been set. + This is why there is a loop around the WFI instruction. + + The \a pnInterruptOccurred variable must be initialized to zero before first use, and this should be done + prior to enabling any interrupt which may set it (otherwise interrupts may be missed). If this variable is + global or static then static initialization to zero or false will be sufficient. + + The variable should only be set, from an interrupt handler, by calling adi_pwr_ExitLowPowerMode() and passing + the variable by reference. The variable should not be assigned to directly, other than for initialization. + + #adi_pwr_EnterLowPowerMode() will always clear the variable again before returning, so it does not + need to be cleared by user code on each use. Explicitly clearing the variable, outside of #adi_pwr_EnterLowPowerMode() + runs the risk of missing interrupts. + + @par PriorityMask + A zero-valued \a PriorityMask disables interrupt masking, leaving all interrupts eligible to awake the + sleeping processor. This means that zero-valued interrupts cannot be masked. A non-zero \a PriorityMask + limits interrupts that may awake the sleeping processor to those with a higher priority level (lower + numerically) than the specified \a PriorityMask value. + + Each "programmable" peripheral interrupt has an associated priority-level register (which defaults to + zero) within the Nested Vectored Interrupt Controller (NVIC). The number of interrupt priority encoding + bits is defined by constant __NVIC_PRIO_BITS and is a fixed silicon attribute configured during chip + design. The interrupt priority-level registers range in width from 3 to 8 bits. + + This processor uses 3-bit priority encoding, allowing priority levels ranging between 0 (the highest, + default programmable priority) and 7 (the lowest). For example, if the \a PriorityMask parameter is + set to 3, only interrupts with assigned priority 0, 1, and 2 may awake the processor. Since default + priority of all programmable interrupts is 0, setting up maskable interrupts requires that they be + demoted in priority (raised numerically) relative to interrupts that are intended to awake the processor. + + @note The number of priority levels is uncorrelated with the actual number of interrupts or their position + in the Interrupt Vector Table (IVT). Interrupt priorities may be programmed individually.\n\n + + @note The priority levels are actually stored in the core as a left-justified value in an 8-bit field. + The #adi_pwr_EnterLowPowerMode() API takes care of aligning the passed \a PriorityMask value to the + core register (BASEPRI).\n\n + + @note The default priority level for all interrupts is zero, which implies it is impossible to mask interrupts + with a default zero-level priority encoding. All interrupt priorities must be managed to create meaningful + interrupt masks for low-power wakeups, as described above.\n\n + + @warning Do not modify the BASEPRI register (used for masking interrupt priority) during interrupts that take + the core out of low-power mode momentarily. The BASEPRI register is saved/restored on low-power mode + entry/exit to honor user priority requests. Interrupt-level changes to BASEPRI will be clobbered on + low-power exit as the saved value is restored.\n\n + + @sa adi_pwr_ExitLowPowerMode +*/ +ADI_PWR_RESULT adi_pwr_EnterLowPowerMode ( const ADI_PWR_POWER_MODE PowerMode, + uint32_t volatile * pnInterruptOccurred, + const uint8_t PriorityMask + ) +{ + uint32_t savedPriority; + uint32_t scrSetBits = 0u; + uint32_t scrClrBits = 0u; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + + /* verify the requested priority mask bits are right-justified and don't exceed __NVIC_PRIO_BITS in width */ + if ((PriorityMask & ~((1u << __NVIC_PRIO_BITS) - 1u)) != 0u) + { + return ADI_PWR_INVALID_PARAM; + } + +#endif /* ADI_DEBUG */ + + /* pre-calculate the sleep-on-exit set/clear bits */ + if(NULL == pnInterruptOccurred) { + scrSetBits |= SCB_SCR_SLEEPONEXIT_Msk; + + /* point to private control variable when in hardware (sleep-on-exit) mode */ + pnInterruptOccurred = &gnLowPowerIntOccFlag; + } + + /* pre-calculate the deepsleep and sleep-on-exit set/clear bits */ + switch (PowerMode) { + + case ADI_PWR_MODE_ACTIVE: /* Note: this value is a "reserved" PWRMODE register code. */ + return ADI_PWR_SUCCESS; /* avoids the reserved value "1" being written to PWRMODE. */ + + case ADI_PWR_MODE_FLEXI: /* wfi without deepsleep or sleep-on-exit */ + scrClrBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT); + break; + + case ADI_PWR_MODE_HIBERNATE: /* wfi with deepsleep and sleep-on-exit per pnInterruptOccurred setting */ + scrSetBits |= BITM_NVIC_INTCON0_SLEEPDEEP; + + break; + + case ADI_PWR_MODE_SHUTDOWN: /* wfi with both deepsleep and sleep-on-exit */ + /* Note: sleep-on-exit causes WFI to never exit and wakeup is only through system reset. */ + scrSetBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT); + break; + + default: + return ADI_PWR_INVALID_POWER_MODE; + + } /* end switch */ + + /* put the power mode and system control mods, as well as the WFI loop inside a critical section */ + ADI_ENTER_CRITICAL_REGION(); + + { /* these lines must be in a success-checking loop if they are not inside critical section */ + /* Uninterruptable unlock sequence */ + pADI_PMG0->PWRKEY = ADI_PMG_KEY; + + /* Clear the previous mode and set new mode */ + pADI_PMG0->PWRMOD = (uint32_t) ( ( pADI_PMG0->PWRMOD & (uint32_t) (~BITM_PMG_PWRMOD_MODE) ) | PowerMode ); + } + + /* Update the SCR (sleepdeep and sleep-on-exit bits) */ + SCB->SCR = ((SCB->SCR | scrSetBits) & ~scrClrBits); + + /* save/restore current Base Priority Level */ + savedPriority = __get_BASEPRI(); + + /* assert caller's priority threshold (left-justified) */ + __set_BASEPRI((uint32_t)PriorityMask << (8u -__NVIC_PRIO_BITS)); + + /* if we are in the software looping mode, loop on the user's variable until set */ + while (0u == *pnInterruptOccurred) { + + __DSB(); /* bus sync to insure register writes from interrupt handlers are always complete before WFI */ + + /* NOTE: aggressive compiler optimizations can muck up critical timing here, so reduce if hangs are present */ + + /* The WFI loop MUST reside in a critical section because we need to insure that the interrupt + that is planned to take us out of WFI (via a call to adi_pwr_ExitLowPowerMode()) is not + dispatched until we get into the WFI. If that interrupt sneaks in prior to our getting to the + WFI, then we may end up waiting (potentially forever) for an interrupt that has already occurred. + */ + __WFI(); + + /* Recycle the critical section so that other (non-wakeup) interrupts are dispatched. + This allows *pnInterruptOccurred to be set from any interrupt context. + */ + ADI_EXIT_CRITICAL_REGION(); + /* nop */ + ADI_ENTER_CRITICAL_REGION(); + + } /* end while */ + + /* ...still within critical section... */ + + (*pnInterruptOccurred)--; /* decrement the completion variable on exit */ + + /* Restore previous base priority */ + __set_BASEPRI(savedPriority); + + /* clear sleep-on-exit bit to avoid sleeping on exception return to thread level */ + SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk; + + __DSB(); /* bus sync before re-enabling interrupts */ + + ADI_EXIT_CRITICAL_REGION(); + + return ADI_PWR_SUCCESS; +} + + +/*! + * Companion function to #adi_pwr_EnterLowPowerMode() that allows interrupts to \n + * break out of the "FLEXI" mode in which the processor stays in \n + * sleep while peripherals are active. \n + + @param[in,out] pnInterruptOccurred + Control parameter selection low-power operation. Either a NULL pointer \n + for hardware sleep-on-exit feature, or a pointer to uint32_t for software \n + looping sleep between interrupts. + @return Status + - #ADI_PWR_SUCCESS If successfully exited from low power mode. + + * @sa adi_pwr_EnterLowPowerMode + */ +ADI_PWR_RESULT adi_pwr_ExitLowPowerMode(uint32_t volatile * pnInterruptOccurred) +{ + ADI_INT_STATUS_ALLOC(); + + /* Manage the exit depending on pnInterruptOccurred convention... */ + /* NULL pointer means we are using the hardware sleep-on-exit feature */ + /* non-NULL pointer means we are using a software looping variable top sleep */ + + if (NULL == pnInterruptOccurred) { + + pnInterruptOccurred = &gnLowPowerIntOccFlag; /* point to private control variable in hardware mode */ + + /* clear hardware sleep-on-exit feature */ + ADI_ENTER_CRITICAL_REGION(); + + SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk; + __DSB(); /* bus sync before interrupt exit */ + + ADI_EXIT_CRITICAL_REGION(); + } + + /* set control variable (whether hardware or software based) so WFI exits in SystemEnterLowPowerMode() */ + (*pnInterruptOccurred)++; + return ADI_PWR_SUCCESS; +} + +/* +** EOF +*/ + +/*! @} */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr_def.h new file mode 100755 index 0000000000..c5f372ed34 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr_def.h @@ -0,0 +1,172 @@ +/* + ***************************************************************************** + * @file: adi_pwr_def.h + * @brief: Definitions for the system clock and power management. + *----------------------------------------------------------------------------- + * + * Copyright (c) 2016 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL + * PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef ADI_PWR_DEF_H +#define ADI_PWR_DEF_H + + /*Power control register access key */ +#define ADI_PMG_KEY (0x4859u) + + /*Osc control register access key */ +#define ADI_OSC_KEY (0xCB14u) + + /*HCLK/PCLK minimum Divider value */ +#define CLOCK_MIN_DIV_VALUE (0x1u) + + /*HCLK/PCLK maximum Divider value */ +#define CLOCK_MAX_DIV_VALUE (32u) + + /*ADC Clock minimum Divider value */ +#define ACLK_MIN_DIV_VALUE (0x1u) + + /*ADC Clock maximum Divider value */ +#define ACLK_MAX_DIV_VALUE (511u) + +/* Minimum divider for PLL */ +#define MINIMUM_PLL_DIVIDER (0x02u) + +/* Minimum multiplier for PLL */ +#define MINIMUM_PLL_MULTIPLIER (0x08u) + +/* Maximum external clock */ +#define MAXIMUM_EXT_CLOCK (26000000u) + + /* Default osc control register value */ +#define OSCCTRL_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_LF_CLOCK_MUX << BITP_CLKG_OSC_CTL_LFCLK_MUX | \ + (uint32_t) ADI_PWR_HFOSC_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFOSC_EN | \ + (uint32_t) ADI_PWR_LFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_LFX_EN | \ + (uint32_t) ADI_PWR_HFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFX_EN | \ + (uint32_t) ADI_PWR_LFXTAL_CLOCK_MON_ENABLE << BITP_CLKG_OSC_CTL_LFX_MON_EN | \ + (uint32_t) ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE << BITP_CLKG_OSC_CTL_LFX_AUTSW_EN | \ + (uint32_t) ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE << BITP_CLKG_OSC_CTL_LFX_ROBUST_EN | \ + (uint32_t) ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT << BITP_CLKG_OSC_CTL_LFX_ROBUST_LD | \ + (uint32_t) ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE << BITP_CLKG_OSC_CTL_ROOT_MON_EN | \ + (uint32_t) ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE << BITP_CLKG_OSC_CTL_ROOT_AUTSW_EN ) + + /* Default clock control register-0 value */ +#define CLOCK_CTL0_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX << BITP_CLKG_CLK_CTL0_CLKMUX | \ + (uint32_t) ADI_PWR_GPIO_CLOCK_OUT_SELECT << BITP_CLKG_CLK_CTL0_CLKOUT | \ + (uint32_t) ADI_PWR_INPUT_TO_RCLK_MUX << BITP_CLKG_CLK_CTL0_RCLKMUX | \ + (uint32_t) ADI_PWR_INPUT_TO_SPLL_MUX << BITP_CLKG_CLK_CTL0_PLL_IPSEL | \ + (uint32_t) ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_LFXTALIE | \ + (uint32_t) ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_HFXTALIE ) + + /* Default clock control register-1 value */ +#define CLOCK_CTL1_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_HCLK_DIVIDE_COUNT << BITP_CLKG_CLK_CTL1_HCLKDIVCNT | \ + (uint32_t) ADI_PWR_PCLK_DIVIDE_COUNT << BITP_CLKG_CLK_CTL1_PCLKDIVCNT | \ + (uint32_t) ADI_PWR_ACLK_DIVIDE_COUNT << BITP_CLKG_CLK_CTL1_ACLKDIVCNT ) + +/* Default clock control register-2 value */ +#define CLOCK_CTL2_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_HFOSC_AUTO_DIV_BY_1 << BITP_CLKG_CLK_CTL2_HFOSCAUTODIV_EN | \ + (uint32_t) ADI_PWR_HFOSC_DIVIDE_SELECT << BITP_CLKG_CLK_CTL2_HFOSCDIVCLKSEL ) + + /* Default clock control register-3 value */ +#define CLOCK_CTL3_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_SPLL_MUL_FACTOR << BITP_CLKG_CLK_CTL3_SPLLNSEL | \ + (uint32_t) ADI_PWR_SPLL_ENABLE_DIV2 << BITP_CLKG_CLK_CTL3_SPLLDIV2 | \ + (uint32_t) ADI_PWR_SPLL_ENABLE << BITP_CLKG_CLK_CTL3_SPLLEN | \ + (uint32_t) ADI_PWR_SPLL_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL3_SPLLIE | \ + (uint32_t) ADI_PWR_SPLL_DIV_FACTOR << BITP_CLKG_CLK_CTL3_SPLLMSEL | \ + (uint32_t) ADI_PWR_SPLL_ENABLE_MUL2 << BITP_CLKG_CLK_CTL3_SPLLMUL2 ) + + /* Default clock control register-5 value */ +#define CLOCK_CTL5_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_GPT0_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK0OFF | \ + (uint32_t) ADI_PWR_GPT1_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK1OFF | \ + (uint32_t) ADI_PWR_GPT2_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK2OFF | \ + (uint32_t) ADI_PWR_I2C_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_UCLKI2COFF | \ + (uint32_t) ADI_PWR_GPIO_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPIOCLKOFF | \ + (uint32_t) ADI_PWR_PCLK_ENABLE << BITP_CLKG_CLK_CTL5_PERCLKOFF | \ + (uint32_t) ADI_PWR_TIMER_RGB_ENABLE << BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF ) + +/* Default configuration for Power supply monitor Interrupt Enable Register */ +#define PWM_INTERRUPT_CONFIG \ + ( (uint32_t) ADI_PWR_ENABLE_VBAT_INTERRUPT << BITP_PMG_IEN_VBAT | \ + (uint32_t) ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT << BITP_PMG_IEN_VREGUNDR | \ + (uint32_t) ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT << BITP_PMG_IEN_VREGOVR | \ + (uint32_t) ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT << BITP_PMG_IEN_IENBAT | \ + (uint32_t) ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT << BITP_PMG_IEN_RANGEBAT ) + + /* Default configuration for Power Mode Register */ + #define PWM_PWRMOD_CONFIG \ + ( (uint32_t) ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING << BITP_PMG_PWRMOD_MONVBATN ) + +/* Default configuration for HP Buck Control register */ +#define PWM_HPBUCK_CONTROL \ + ( (uint32_t) ADI_PWR_HP_BUCK_ENABLE << BITP_PMG_CTL1_HPBUCKEN | \ + (uint32_t) ADI_PWR_HP_BUCK_LOAD_MODE << BITP_PMG_CTL1_HPBUCK_LD_MODE | \ + (uint32_t) ADI_PWR_HP_BUCK_LOW_POWER_MODE << BITP_PMG_CTL1_HPBUCK_LOWPWR_MODE ) + + /*Selecting HFOSC as input for generating root clock*/ +#define HFMUX_INTERNAL_OSC_VAL (0u << BITP_CLKG_CLK_CTL0_CLKMUX) + + /*Selecting HFXTAL as input for generating root clock*/ +#define HFMUX_EXTERNAL_XTAL_VAL (1u << BITP_CLKG_CLK_CTL0_CLKMUX) + + /*Selecting SPLL as input for generating root clock*/ +#define HFMUX_SYSTEM_SPLL_VAL (2u << BITP_CLKG_CLK_CTL0_CLKMUX) + + /*Selecting GPIO as input for generating root clock*/ +#define HFMUX_GPIO_VAL (3u << BITP_CLKG_CLK_CTL0_CLKMUX) + +/* Interrupt handler for the battery voltage interrupt */ +void Battery_Voltage_Int_Handler(void); +/* Interrupt handler for the VREG under/over voltage interrupt */ +void Vreg_over_Int_Handler(void); +/* Interrupt handler for PLL interrupts. */ +void PLL_Int_Handler(void); +/*Interrupt handler for oscillator interrupts.*/ +void Crystal_osc_Int_Handler(void); + +#endif /* ADI_PWR_DEF_H */ + + +/* +** EOF +*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/retarget_uart_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/retarget_uart_config.h new file mode 100755 index 0000000000..a9f0e37275 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/retarget_uart_config.h @@ -0,0 +1,27 @@ +/* +** I/O redirection support over UART, via SSL/DD. +** Copyright (C) 2017 Analog Devices, Inc. All Rights Reserved. +** +** This file is intended for use with the ARM:Compiler:IO:*:User +** components, which set up redirection of stdout and stderr. +*/ + +#ifndef RETARGET_UART_CONFIG_H +#define RETARGET_UART_CONFIG_H + +// --- <<< Use Configuration Wizard in Context Menu >>> --- + +// UART Configuration for STDOUT and STDERR + +// Configure Pinmuxing for UART. +// Enable pinmux configuration for UART on first output. +#define ADI_UART_SETUP_PINMUX 1 + +// Raise Breakpoint on exit() +// Cause a breakpoint event in exit() rather than looping forever. +#define ADI_UART_EXIT_BREAKPOINT 1 + + +// + +#endif /* RETARGET_UART_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng.c new file mode 100755 index 0000000000..75eb73a6cb --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng.c @@ -0,0 +1,796 @@ +/*! + ***************************************************************************** + * @file: adi_rng.c + * @brief: Random Number Generator Driver + *---------------------------------------------------------------------------- + * +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/*! \addtogroup RNG_Driver RNG Driver + * Random Number Generator Driver + * @{ + */ + + /*! \cond PRIVATE */ + +#include /* for 'NULL' definition */ +#include + +#include +#include +#include "adi_rng_def.h" +#include + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): Types which specify sign and size should be used +* We use bool which is accepted by MISRA but the toolchain does not accept it +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Needed for null expansion of ISR_PROLOG in no-OS case and others. +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +*/ +#pragma diag_suppress=Pm011,Pm073,Pm143,Pm050 +#endif /* __ICCARM__ */ + +#ifdef __ADUCM4x50__ +#define NUM_RNG_DEVICES (1u) +#else +#error "Unsupported processor" +#endif + +/*============== D A T A ===============*/ + +/** + * Information for managing all the RNG devices available + */ +#ifdef __ICCARM__ +#pragma diag_suppress=Pm140 +#endif + +static ADI_RNG_DEV_TYPE gRNG_Device[NUM_RNG_DEVICES] = +{ + {(ADI_RNG_TypeDef*)pADI_RNG0,NULL} /* RNG0 */ +}; +#ifdef __ICCARM__ +#pragma diag_default=Pm140 +#endif + +/* Forward prototypes */ +void RNG_Int_Handler(void); + +/** Check the validity of a handle for debug mode */ +#ifdef ADI_DEBUG +#define ADI_RNG_INVALID_HANDLE(h) (&gRNG_Device[0] != (h)) +#endif + +/*! \endcond */ + +/*! + @brief Opena a Random Number Generator Device + + @param[in] nDeviceNum Device number to be opened. + @param[in] pMemory Pointer to the memory to be used by the driver. + Size of the memory should be at least #ADI_RNG_MEMORY_SIZE bytes. + @param[in] MemorySize Size of the memory passed in pMemory parameter. + @param[out] phDevice Pointer to a location in the calling function memory space to which + the device handle will be written upon successful driver initialization. + + @return Status + - #ADI_RNG_SUCCESS RNG device driver opened successfully. + - #ADI_RNG_INVALID_PARAM [D] The memory passed to the API is either NULL or its size is not sufficient. + - #ADI_RNG_ALREADY_INITIALIZED [D] The RNG is already initialized. + - #ADI_RNG_BAD_DEVICE_NUM [D] The device number is invalid. + + Initialize and allocate a RNG device for other use. The core NVIC RNG interrupt is enabled. This API + must preceed all other RNG API calls and the handle returned must be passed to all other RNG API calls. + + @note The contents of \a ppDevice will be set to NULL upon failure.\n\n + + @note The RNG device driver will clear all pending interrupts and disable all RNG + interrupts during RNG device initialization. + + @sa adi_rng_Close(). +*/ +ADI_RNG_RESULT adi_rng_Open( + uint32_t const nDeviceNum, + void* const pMemory, + uint32_t const MemorySize, + ADI_RNG_HANDLE* const phDevice + ) +{ + ADI_RNG_DEV_TYPE *pDevice; + + /* store a bad handle in case of failure */ + *phDevice = (ADI_RNG_HANDLE) NULL; + +#ifdef ADI_DEBUG + if (nDeviceNum >= NUM_RNG_DEVICES) + { + return ADI_RNG_BAD_DEVICE_NUM; + } + + if ((NULL == pMemory) || ( MemorySize < (uint32_t) ADI_RNG_MEMORY_SIZE)) + { + return ADI_RNG_INVALID_PARAM; + } + assert (ADI_RNG_MEMORY_SIZE == sizeof(ADI_RNG_DEV_DATA_TYPE)); +#endif + + /* local pointer to instance data */ + pDevice = &gRNG_Device[nDeviceNum]; + +#ifdef ADI_DEBUG + if (NULL != pDevice->pData) + { + return ADI_RNG_ALREADY_INITIALIZED; + } +#endif + + /* Set the internal device data */ + pDevice->pData = pMemory; + + /* initialize internal device data */ + pDevice->pData->IRQn = RNG0_EVT_IRQn; + pDevice->pData->CBFunc = NULL; + + /* clear any pending interrupts. Both bits are write 1 to clear */ + pDevice->pRNG->STAT = BITM_RNG_STAT_RNRDY | BITM_RNG_STAT_STUCK; + + /* Set the RNG register based on static configuration */ + pDevice->pRNG->CTL = (uint16_t)RNG0_CFG_ONLY_8_BIT << BITP_RNG_CTL_SINGLE; + pDevice->pRNG->LEN = (RNG0_CFG_LENGTH_RELOAD << BITP_RNG_LEN_RELOAD) + | (RNG0_CFG_LENGTH_PRESCALER << BITP_RNG_LEN_PRESCALE); + + /* The interrupt handler only gets used in the case of callback mode so its + * enabling only happens in the adi_rng_RegisterCallBack API. + */ + NVIC_ClearPendingIRQ(pDevice->pData->IRQn); + + /* store handle at application handle pointer */ + *phDevice = pDevice; + + return ADI_RNG_SUCCESS; +} + + +/*! + * @brief Uninitializes and deallocates the RNG device. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * + * Uninitialize and release an allocated RNG device for other use. The core NVIC RNG interrupt is disabled. + * + * @sa adi_rng_Open(). + */ +ADI_RNG_RESULT adi_rng_Close(ADI_RNG_HANDLE hDevice) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } +#endif + + /* uninitialize */ + NVIC_DisableIRQ(pDevice->pData->IRQn); + pDevice->pData = NULL; + + return ADI_RNG_SUCCESS; +} + +/*! + * @brief Enables/Disables the RNG device. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[in] bFlag Flag to specify whether to enable or disable RNG device. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * + * @sa adi_rng_Open(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_Enable (ADI_RNG_HANDLE const hDevice, bool const bFlag) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)) { + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + if (true == bFlag) { + pDevice->pRNG->CTL |= BITM_RNG_CTL_EN; + } else { + pDevice->pRNG->CTL &= (uint16_t)~(BITM_RNG_CTL_EN); + } + ADI_EXIT_CRITICAL_REGION(); + + return ADI_RNG_SUCCESS; +} + +/*! + * @brief Enables/Disables Buffering for RNG. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[in] bFlag Flag to specify whether to enable or disable buffering for RNG device. + * When buffering is enabled, adi_rng_GetRngData returns 32-bit values. + * When buffering is disabled the API returns 8-bit values. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * + * @sa adi_rng_Open(). + * @sa adi_rng_RegisterCallback(). + * @sa adi_rng_GetRngData(). + */ +ADI_RNG_RESULT adi_rng_EnableBuffering (ADI_RNG_HANDLE const hDevice, bool const bFlag) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)) { + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + if (true == bFlag) { + pDevice->pRNG->CTL &= (uint16_t)~(BITM_RNG_CTL_SINGLE); + } else { + pDevice->pRNG->CTL |= BITM_RNG_CTL_SINGLE; + } + ADI_EXIT_CRITICAL_REGION(); + + return ADI_RNG_SUCCESS; +} + +/*! + * @brief Sets the reload and prescale value for the sample counter. + * The Sample Length will be nLenReload*2^nLenPrescaler. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[in] nLenPrescaler Prescaler value for the sample counter (0-10). + * @param[in] nLenReload Reload value for the sample counter (0-4095) + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * + * @sa adi_rng_Open(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_SetSampleLen ( + ADI_RNG_HANDLE const hDevice, + uint16_t const nLenPrescaler, + uint16_t const nLenReload + ) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } + + if ( (nLenPrescaler > 10u) + || ((0u == nLenPrescaler) && (0u == nLenReload)) + || (nLenReload > 4095u)) { + return ADI_RNG_INVALID_PARAM; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + /* Set the sample reload and prescaler value */ + pDevice->pRNG->LEN = (uint16_t)((uint16_t)(nLenReload << BITP_RNG_LEN_RELOAD) & BITM_RNG_LEN_RELOAD) + | (uint16_t)((uint16_t)(nLenPrescaler << BITP_RNG_LEN_PRESCALE) & BITM_RNG_LEN_PRESCALE); + ADI_EXIT_CRITICAL_REGION(); + + return ADI_RNG_SUCCESS; +} + + +/*! + * @brief Retrieves the current state of RNG data/CRC accumulator register. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[out] pbFlag Pointer to an application-defined boolean variable into which to write the result: + * - true = RNG data is ready to be read. + * - false = RNG data is not ready. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + - #ADI_RNG_INVALID_PARAM [D] Argument is incorrect. + * + * Retrieve the current state of RNG data/CRC accumulator register. The register holds the final entropy value + * accumulated by RNG and it should to read only when the data is ready. + * + * @sa adi_rng_Open(). + * @sa adi_rng_GetRngData(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_GetRdyStatus (ADI_RNG_HANDLE const hDevice, bool* const pbFlag) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } + + if (NULL == pbFlag) { + return ADI_RNG_INVALID_PARAM; + } +#endif + + /* Get the RNG Ready status bit */ + if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) != 0u) + { + *pbFlag = true; + } + else + { + *pbFlag = false; + } + + return ADI_RNG_SUCCESS; +} + +/*! + * @brief Retrieve whether the RNG oscillator output is stuck at a constant value + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[out] pbFlag Pointer to an application-defined boolean variable into which to write the result: + * - true = RNG oscillator is stuck at a constant value. + * - false = RNG oscillator is not stuck at a constant value. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + - #ADI_RNG_INVALID_PARAM [D] Argument is incorrect. + * + * @sa adi_rng_Open(). + * @sa adi_rng_GetRngData(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_GetStuckStatus ( + ADI_RNG_HANDLE const hDevice, + bool* const pbFlag + ) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (pDevice->pData == NULL) { + return ADI_RNG_NOT_INITIALIZED; + } + + if (NULL == pbFlag) { + return ADI_RNG_INVALID_PARAM; + } +#endif + + /* Get the stuck status bit */ + if ((pDevice->pRNG->STAT & BITM_RNG_STAT_STUCK) != 0u) + { + *pbFlag = true; + } + else + { + *pbFlag = false; + } + + return ADI_RNG_SUCCESS; +} + + +/*! + * @brief Retrieve the current value of the RNG data register. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[in] pRegData Pointer to an application-defined variable into which to write the result. + * Only lower 8-bit is valid if buffering is not enabled + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * - #ADI_RNG_INVALID_PARAM [D] pRegData is a NULL pointer. + * - #ADI_RNG_INVALID_STATE[D] Random number ready status is not set + * + * Retrieve the current value of RNG data register. If the buffering is enabled all 32-bit of value written to + * pRegData is valid else only the lower 8-bit is valid. + * + * @sa adi_rng_Open(). + * @sa adi_rng_GetRdyStatus(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_GetRngData (ADI_RNG_HANDLE const hDevice, uint32_t* const pRegData) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } + + if (NULL == pRegData) { + return ADI_RNG_INVALID_PARAM; + } + + if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) == 0u) { + return ADI_RNG_INVALID_STATE; + } +#endif + + /* Get the RNG CRC accumulator value */ + *pRegData = pDevice->pRNG->DATA; + + return ADI_RNG_SUCCESS; +} + + +/*! + * @brief Retrieve the current RNG Oscillator count. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[in] pOscCount Pointer to an application-defined variable into which to write the result. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * - #ADI_RNG_INVALID_STATE[D] Random number ready status is not set + - #ADI_RNG_INVALID_PARAM [D] Argument is incorrect. + * + * @sa adi_rng_Open(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_GetOscCount (ADI_RNG_HANDLE const hDevice, uint32_t* const pOscCount) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } + + if (NULL == pOscCount) { + return (ADI_RNG_INVALID_PARAM); + } + + if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) == 0u) { + return ADI_RNG_INVALID_STATE; + } +#endif + + /* Get the oscillator count high count */ + *pOscCount = pDevice->pRNG->OSCCNT; + + return ADI_RNG_SUCCESS; +} + +/*! + * @brief Retrieve the current RNG Oscillator difference value for the given index. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[in] nIndex Index of the difference register. + * @param[out] pOscDiff Pointer to an application-defined variable into which to + * write the oscillator difference value for the given index. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * - #ADI_RNG_INVALID_STATE[D] Random number ready status is not set + - #ADI_RNG_INVALID_PARAM [D] Argument is incorrect. + * + * @sa adi_rng_Open(). + * @sa adi_Rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_GetOscDiff ( + ADI_RNG_HANDLE const hDevice, + uint32_t const nIndex, + uint8_t* const pOscDiff + ) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } + + if ((NULL == pOscDiff) || (nIndex > 3u)) { + return( ADI_RNG_INVALID_PARAM ); + } + + if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) == 0u) { + return ADI_RNG_INVALID_STATE; + } +#endif + + /* Get the Osc Difference Register */ + *pOscDiff = (uint8_t)pDevice->pRNG->OSCDIFF[nIndex]; + + return ADI_RNG_SUCCESS; +} + +/*! + * @brief Retrieve the current RNG sample length prescale and reload value configured in the device. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[out] pLenPrescaler Pointer to an application-defined variable into which the prescaler value is written. + * @param[out] pLenReload Pointer to an application-defined variable into which the reload value for the sample counter is written. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + - #ADI_RNG_INVALID_PARAM [D] Argument is incorrect. + * + * + * @sa adi_rng_Open(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_GetSampleLen ( + ADI_RNG_HANDLE const hDevice, + uint16_t* const pLenPrescaler, + uint16_t* const pLenReload + ) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } + + if ((NULL == pLenPrescaler) || (NULL == pLenReload)) { + return ADI_RNG_INVALID_PARAM; + } +#endif + + *pLenPrescaler = (pDevice->pRNG->LEN & BITM_RNG_LEN_PRESCALE) >> BITP_RNG_LEN_PRESCALE; + *pLenReload = (pDevice->pRNG->LEN & BITM_RNG_LEN_RELOAD) >> BITP_RNG_LEN_RELOAD; + + return ADI_RNG_SUCCESS; +} + + +/************************************************************************************************* +************************************************************************************************** +***************************************** CALLBACKS ****************************************** +***************************************** AND ****************************************** +***************************************** INTERRUPT ****************************************** +************************************************************************************************** +*************************************************************************************************/ + + +/*! + @brief RNG Application callback registration API. + + @param[in] hDevice Device handle obtained from #adi_rng_Open(). + @param[in] cbFunc Application callback address; the function to call on the interrupt. + @param[in] pCBParam Application handle to be passed in the call back. + + @return Status + - #ADI_RNG_SUCCESS The callback is successfully registered. + - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + + Registers an application-defined callback \a cbFunc function address of type ADI_CALLBACK with the RNG device driver. + Callbacks are made in response to received RNG interrupts. + + The callback to the application is made in context of the originating interrupt (i.e., the RNG driver's + RNG interrupt handler that is registered in the system's interrupt vector table). Extended processing + during the callback (an extension of the RNG's interrupt handler) is discouraged so as to avoid lower-priority + interrupt blocking. Also, any register read-modify-write operations should be protected using the + ADI_ENTER_CRITICAL_REGION()/ADI_EXIT_CRITICAL_REGION() pair to prevent higher-priority interrupts from modifying + said register during the read-modify-write operation. + + @note CALLBACKS: RNG interrupt callbacks are \b disabled by default during RNG device driver + initialization (#adi_rng_Open()). The application uses the #adi_rng_RegisterCallback() + API to request an application-defined callback from the RNG device driver. The RNG device + driver clears the interrupt when the callback exits. + The application callback should avoid extended processing + during callbacks as the callback is executing context of the initiating interrupt and will + block lower-priority interrupts. If extended application-level interrupt processing is + required, the application should schedule it for the main application loop and exit the + callback as soon as possible.\n + + + @sa adi_rng_Open(). +*/ +ADI_RNG_RESULT adi_rng_RegisterCallback ( + ADI_RNG_HANDLE hDevice, + ADI_CALLBACK cbFunc, + void *pCBParam) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } +#endif + + /* save the callback info */ + pDevice->pData->CBFunc = cbFunc; + pDevice->pData->pCBParam = pCBParam; + + if (NULL != cbFunc) { + /* enable RNG interrupts in NVIC */ + NVIC_EnableIRQ(pDevice->pData->IRQn); + } else { + NVIC_DisableIRQ(pDevice->pData->IRQn); + } + + return ADI_RNG_SUCCESS; +} + +/*! \cond PRIVATE */ +/* RNG driver interrupt handler. Overrides weak default handler in startup file */ +void RNG_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_RNG_DEV_TYPE *pDevice = &gRNG_Device[0]; + register uint16_t candidate; + + /* if we have an initialized driver... */ + if (NULL != pDevice->pData) + { + /* if we have a registered callback */ + if (NULL != pDevice->pData->CBFunc) + { + ADI_INT_STATUS_ALLOC(); + + ADI_ENTER_CRITICAL_REGION(); + /* read status register without other interrupts in between */ + candidate = pDevice->pRNG->STAT; + ADI_EXIT_CRITICAL_REGION(); + + /* Only have bits in stat that are necessary */ + candidate = candidate & (BITM_RNG_STAT_STUCK | BITM_RNG_STAT_RNRDY); + + while (0u != candidate) { + uint32_t nEvent; + + if (0u != (candidate & BITM_RNG_STAT_RNRDY)) { + nEvent = ADI_RNG_EVENT_READY; + candidate &= (uint16_t)~BITM_RNG_STAT_RNRDY; + } else if (0u != (candidate & BITM_RNG_STAT_STUCK)) { + nEvent = ADI_RNG_EVENT_STUCK; + candidate &= (uint16_t)~BITM_RNG_STAT_STUCK; + } else { + break; + } + + pDevice->pData->CBFunc ( + pDevice->pData->pCBParam, + nEvent, + NULL + ); + } + + pDevice->pRNG->STAT = BITM_RNG_STAT_RNRDY | BITM_RNG_STAT_STUCK; + } + } + ISR_EPILOG(); +} +/*! \endcond */ + +/* +** EOF +*/ + +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng_def.h new file mode 100755 index 0000000000..462861d976 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng_def.h @@ -0,0 +1,69 @@ +/*! + ***************************************************************************** + * @file: adi_rng_def.h + * @brief: Random Number Generator Driver private data structures + *---------------------------------------------------------------------------- + * +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_RNG_DEF_H +#define ADI_RNG_DEF_H + + /*! \cond PRIVATE */ + + +/*! RNG device internal instance data structure */ +typedef struct __ADI_RNG_DEV_DATA_TYPE +{ + IRQn_Type IRQn; /*!< RNG interrupt number */ + ADI_CALLBACK CBFunc; /*!< Callback function */ + void *pCBParam; /*!< Callback parameter */ +} ADI_RNG_DEV_DATA_TYPE; + +/*! RNG device internal data structure */ +typedef struct __ADI_RNG_DEV_TYPE +{ + volatile ADI_RNG_TypeDef *pRNG; /*!< MMR address for this RNG */ + ADI_RNG_DEV_DATA_TYPE *pData; /*!< Pointer to instance data */ +} ADI_RNG_DEV_TYPE; + + +/*! \endcond */ +#endif /* ADI_RNG_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc.c new file mode 100755 index 0000000000..f4b91d4adb --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc.c @@ -0,0 +1,2608 @@ +/*! + ***************************************************************************** + * @file: adi_rtc.c + * @brief: Real-Time Clock Device Implementations. + * @version: $Revision: 35155 $ + * @date: $Date: 2016-07-26 13:09:22 -0400 (Tue, 26 Jul 2016) $ + *---------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +/*! \addtogroup RTC_Driver RTC Driver + * @{ + * @brief Real Time Clock (RTC) Driver + * @details The RTC driver manages all instances of the RTC peripheral. + * @note The application must include drivers/rtc/adi_rtc.h to use this driver + */ + + +/*! \cond PRIVATE */ + + +#if defined ( __ADSPGCC__ ) +#define UNUSED __attribute__ ((unused)) +#else +#define UNUSED +#endif + +#include /* for 'NULL" definition */ +#include +#include +#include + + + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): Types which specify sign and size should be used +* We use bool which is accepted by MISRA but the toolchain does not accept it +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Needed for null expansion of ADI_INSTALL_HANDLER and others. +* +* Pm109 (rule 20.12): the time handling functions of library shall not be used +* Pm150 (rule 20.2): the names of standard library macros, objects and function shall not be reused +* Needed to implement the functions here. +* +* Pm129 (rule 12.7): bitwise operations shall not be performed on signed integer types +* The rule makes an exception for valid expressions. +* +* Pm029: this bitwise operation is in a boolean context - logical operators should not be confused with bitwise operators +* The rule is suppressed as the bitwise and logical operators are being used correctly and are not being confused +* +* Pm126: if the bitwise operators ~ and << are applied to an operand of underlying type 'unsigned char' or 'unsigned short', the result shall be immediately cast to the underlying type of the operand +* The behaviour as described is correct +* +* Pm031: bitwise operations shall not be performed on signed integer types +* Device drivers often require bit banging on MMRs that are defined as signed + +*/ +#pragma diag_suppress=Pm011,Pm123,Pm073,Pm143,Pm050,Pm109,Pm150,Pm140,Pm129,Pm029,Pm126,Pm031 +#endif /* __ICCARM__ */ +/*! \endcond */ + + +#include + + +/*! \cond PRIVATE */ + + +#include "adi_rtc_data.c" + + + + +/* Forward prototypes */ +void RTC0_Int_Handler(void); +void RTC1_Int_Handler(void); + + + +#ifdef ADI_DEBUG +static ADI_RTC_RESULT ValidateHandle( ADI_RTC_DEVICE *pInDevice) +{ + /* Return code */ + ADI_RTC_RESULT nResult = ADI_RTC_INVALID_HANDLE; + uint32_t i; + for(i = 0u; i < ADI_RTC_NUM_INSTANCE; i++) + { + if(aRTCDeviceInfo[i].hDevice == pInDevice) + { + return(ADI_RTC_SUCCESS); + } + } + return (nResult); +} +#endif +/*! \endcond */ + +/*! + @brief RTC Initialization + + * @param[in] DeviceNumber The RTC device instance number to be opened. + * @param[in] pDeviceMemory The pointer to the device memory passed by application. + * @param[in] MemorySize The memory size passed by application. + * @param[out] phDevice The pointer to a location where the handle to the opened RTC device is written. + @return Status + - #ADI_RTC_SUCCESS RTC device driver initialized successfully. + - #ADI_RTC_INVALID_INSTANCE [D] The RTC instance number is invalid. + - #ADI_RTC_FAILURE General RTC initialization failure. + + The RTC controller interrupt enable state is unaltered during driver initialization. + Use the #adi_rtc_EnableInterrupts API to manage interrupting. + + @note The contents of phDevice will be set to NULL upon failure.\n\n + + @note On #ADI_RTC_SUCCESS the RTC device driver is initialized and made ready for use, + though pending interrupts may be latched. During initialization, the content of the + various RTC control, count, alarm and status registers are untouched to preserve prior + RTC initializations and operation. The core NVIC RTC interrupt is enabled.\n\n + + + @note SAFE WRITES: The "safe write" mode is enabled by default and can be changed using the macro + "ADI_RTC_CFG_ENABLE_SAFE_WRITE" defined in adi_rtc_config.h file. + + @sa adi_rtc_Enable(). + @sa adi_rtc_EnableInterrupts(). + @sa adi_rtc_SetCount(). + @sa adi_rtc_Close() +*/ +ADI_RTC_RESULT adi_rtc_Open( + uint32_t DeviceNumber, + void *pDeviceMemory, + uint32_t MemorySize, + ADI_RTC_HANDLE *phDevice + ) +{ + ADI_RTC_DEVICE *pDevice = pDeviceMemory; + + /* store a bad handle in case of failure */ + *phDevice = (ADI_RTC_HANDLE) NULL; + +#ifdef ADI_DEBUG + if ( DeviceNumber >= ADI_RTC_NUM_INSTANCE) + { + return ADI_RTC_INVALID_INSTANCE; + } + assert(ADI_RTC_MEMORY_SIZE == sizeof(ADI_RTC_DEVICE)); + if (aRTCDeviceInfo[DeviceNumber].hDevice != NULL) + { + return ADI_RTC_IN_USE; + } + if(MemorySize < ADI_RTC_MEMORY_SIZE) + { + return(ADI_RTC_FAILURE); + } +#endif + + memset(pDeviceMemory,0,MemorySize); + /* initialize device data entries */ + pDevice->pRTCRegs = aRTCDeviceInfo[DeviceNumber].pRTCRegs; + + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + pDevice->pRTCRegs->CR0 = 0u; + pDevice->pRTCRegs->CR1 = 0u; + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDSR0) + + pDevice->pRTCRegs->SR0 = ADI_RTC_SR3_IRQ_STATUS_MASK; + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCSR0) + + pDevice->pRTCRegs->CNT0 = 0u; + pDevice->pRTCRegs->CNT1 = 0u; + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCNT0) + + /* local pointer to instance data */ + aRTCDeviceInfo[DeviceNumber].hDevice = pDevice; + pDevice->pDeviceInfo = &aRTCDeviceInfo[DeviceNumber]; + + /* Use static configuration to initialize the RTC */ + rtc_init(pDevice,&aRTCConfig[DeviceNumber]); + + /* store handle at application handle pointer */ + *phDevice = pDevice; + pDevice->eIRQn = aRTCDeviceInfo[DeviceNumber].eIRQn; + /* Enable RTC interrupts in NVIC */ + NVIC_EnableIRQ((IRQn_Type)(pDevice->eIRQn)); + + return ADI_RTC_SUCCESS; /* initialized */ +} + + +/*! + * @brief Uninitialize and deallocate an RTC device. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Uninitialize and release an allocated RTC device for other use. The core NVIC RTC interrupt is disabled. + * + * @sa adi_rtc_Open(). + */ +ADI_RTC_RESULT adi_rtc_Close(ADI_RTC_HANDLE const hDevice) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* uninitialize */ + NVIC_DisableIRQ( pDevice->eIRQn); + + pDevice->pRTCRegs = NULL; + pDevice->pfCallback = NULL; + pDevice->pCBParam = NULL; + pDevice->cbWatch = 0u; + + pDevice->pDeviceInfo->hDevice = NULL; + return ADI_RTC_SUCCESS; +} + + +/************************************************************************************************* +************************************************************************************************** +**************************************** ENABLE APIS ******************************************* +************************************************************************************************** +*************************************************************************************************/ + + +/*! + * @brief Enable RTC alarm. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] bEnable boolean Flag to enable/disable alarm logic. + * - true : Enable alarm logic. + * - false : Disable alarm logic. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Enable/disable operation of RTC internal alarm logic. + * + * Alarm events and interrupt notifications are gated by enabling the alarm logic. + * RTC alarm interrupts require both RTC device and RTC alarm interrupt to be enabled + * to have been set. + * + * The alarm is relative to some future alarm value match against the RTC counter. + * + * @note The RTC device driver does not modify the alarm enable on the hardware except through use of this API. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_EnableInterrupts(). + * @sa adi_rtc_GetAlarm(). + * @sa adi_rtc_GetCount(). + * @sa adi_rtc_SetAlarm(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_EnableAlarm(ADI_RTC_HANDLE const hDevice, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear RTC alarm enable */ + if (bEnable) + { + pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_ALMEN; + } + else + { + pDevice->pRTCRegs->CR0 &= (uint16_t)(~BITM_RTC_CR0_ALMEN); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Enable MOD60 RTC alarm. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] bEnable boolean Flag for enable/disable mod60 alarm logic. + * - true : Enable mod60 alarm logic. + * - false : Disable mod60 alarm logic. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Enable/disable operation of RTC internal MOD60 alarm logic. + * + * Alarm events and interrupt notifications are gated by enabling the alarm logic. + * RTC alarm interrupts require both RTC device and RTC alarm interrupt to be enabled + * to have been set. + * + * The alarm is relative to some future alarm value match against the RTC counter. + * + * @note The RTC device driver does not modify the alarm enable on the hardware except through use of this API. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_EnableInterrupts(). + * @sa adi_rtc_GetAlarm(). + * @sa adi_rtc_GetCount(). + * @sa adi_rtc_SetAlarm(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_EnableMod60Alarm(ADI_RTC_HANDLE const hDevice, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + /* Mod-60 Alarm is present only in RTC-1 */ + if(pDevice->pRTCRegs == pADI_RTC0) + { + return(ADI_RTC_OPERATION_NOT_ALLOWED); + } + +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear RTC alarm enable */ + if (bEnable) + { + pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_MOD60ALMEN; + } + else + { + pDevice->pRTCRegs->CR0 &= (uint16_t)(~BITM_RTC_CR0_MOD60ALMEN); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Enable RTC device. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] bEnable boolean Flag for enabling/disabling the RTC device. + * - true : Enable RTC device. + * - false : Disable RTC device. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Global enable/disable of the RTC controller. Enables counting of elapsed real time and acts + * as a master enable for the RTC. + * + * @note When enabled, the RTC input clock pre-scaler and trim interval are realigned. + * + * @note The RTC device driver does not modify the device enable on the hardware except through use of this API. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_EnableAlarm(). + */ + +ADI_RTC_RESULT adi_rtc_Enable(ADI_RTC_HANDLE const hDevice, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear RTC device enable */ + if (bEnable) + { + pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_CNTEN; + } + else + { + pDevice->pRTCRegs->CR0 &=(uint16_t)(~BITM_RTC_CR0_CNTEN); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; +} + + +/* Data structures used to manage the enabling of all RTC interrupts */ +static uint16_t cr0 = 0u, cr1 = 0u, cr3oc = 0u, cr4oc = 0u, cr2ic = 0u, cr5ocs = 0u; + +static struct xxx +{ + uint16_t *cr; + uint16_t bitPositionl; +} +Interrupt_Details[ADI_RTC_NUM_INTERRUPTS] = +{ + { &cr0, BITP_RTC_CR0_ALMINTEN }, + { &cr0, BITP_RTC_CR0_MOD60ALMINTEN }, + { &cr0, BITP_RTC_CR0_ISOINTEN }, + { &cr0, BITP_RTC_CR0_WPNDERRINTEN }, + { &cr0, BITP_RTC_CR0_WSYNCINTEN }, + { &cr0, BITP_RTC_CR0_WPNDINTEN }, + { &cr1, BITP_RTC_CR1_CNTINTEN }, + { &cr1, BITP_RTC_CR1_PSINTEN }, + { &cr1, BITP_RTC_CR1_TRMINTEN }, + { &cr1, BITP_RTC_CR1_CNTROLLINTEN }, + { &cr1, BITP_RTC_CR1_CNTMOD60ROLLINTEN }, + { &cr3oc, BITP_RTC_CR3SS_SS1IRQEN }, + { &cr3oc, BITP_RTC_CR3SS_SS2IRQEN }, + { &cr3oc, BITP_RTC_CR3SS_SS2IRQEN }, + { &cr3oc, BITP_RTC_CR3SS_SS4IRQEN }, + { &cr2ic, BITP_RTC_CR2IC_IC0IRQEN }, + { &cr2ic, BITP_RTC_CR2IC_IC2IRQEN }, + { &cr2ic, BITP_RTC_CR2IC_IC3IRQEN }, + { &cr2ic, BITP_RTC_CR2IC_IC4IRQEN }, + { &cr2ic, BITP_CLKG_OSC_CTL_LFX_FAIL_STA }, + { &cr3oc, BITM_RTC_CR3SS_SS4FEIRQEN}, + { &cr3oc, BITM_RTC_CR3SS_SS3FEIRQEN}, + { &cr3oc, BITM_RTC_CR3SS_SS2FEIRQEN}, + { &cr3oc, BITM_RTC_CR3SS_SS1FEIRQEN}, + { &cr4oc, BITP_RTC_CR4SS_SS4MSKEN}, + { &cr4oc, BITP_RTC_CR4SS_SS3MSKEN}, + { &cr4oc, BITP_RTC_CR4SS_SS2MSKEN}, + { &cr4oc, BITP_RTC_CR4SS_SS1MSKEN}, + { &cr5ocs, BITP_RTC_CR5SSS_SS3SMPMTCHIRQEN}, + { &cr5ocs, BITP_RTC_CR5SSS_SS2SMPMTCHIRQEN}, + { &cr5ocs, BITP_RTC_CR5SSS_SS1SMPMTCHIRQEN} + +}; + + +/*! + * @brief Manage interrupt enable/disable in the RTC and NVIC controller. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] Interrupts Conveys which interrupts are affected. + * @param[in] bEnable Flag which controls whether to enable or disable RTC interrupt. + * - true : Enable RTC interrupts. + * - false : Disable RTC interrupts. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Enable/disable RTC interrupt as well as manage global NVIC enable/disable for the RTC. + * Input parameter \a Interrupts is a interrupt ID of type #ADI_RTC_INT_TYPE designating the + * interrupt to be enabled or disabled. The interrupt parameter may be zero, which will then simply + * manage the NVIC RTC enable and leave the individual RTC interrupt enables unchanged. + * Input parameter \a bEnable controls whether to enable or disable the designated set of interrupts. + * + * @note The RTC device driver does not modify the interrupt enables on the hardware except through use of this API. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + */ +ADI_RTC_RESULT adi_rtc_EnableInterrupts (ADI_RTC_HANDLE const hDevice, ADI_RTC_INT_TYPE Interrupts, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + if( (pDevice->pRTCRegs == pADI_RTC0) &&(((uint16_t)((ADI_RTC_MOD60ALM_INT | ADI_RTC_ISO_DONE_INT| + ADI_RTC_COUNT_INT | + ADI_RTC_TRIM_INT | ADI_RTC_COUNT_ROLLOVER_INT | + ADI_RTC_MOD60_ROLLOVER_INT + )) & (uint16_t)Interrupts) != 0u)) + { + return(ADI_RTC_INVALID_PARAM); + } + + assert(sizeof(Interrupt_Details)/sizeof(Interrupt_Details[0]) == ADI_RTC_NUM_INTERRUPTS); +#endif + + /* TODO - more sync for new registers */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDCR1MIR) + + uint8_t ndx = 0u; + cr0 = 0u; cr1 = 0u; cr3oc = 0u; cr4oc = 0u; cr2ic = 0u; cr5ocs = 0u; + + while( Interrupts ) + { + if( 0u != (Interrupts & 1u) ) + { + uint16_t *cr = Interrupt_Details[ndx].cr; + uint16_t enableBitPosition = Interrupt_Details[ndx].bitPositionl; + *cr = *cr | (1u << enableBitPosition); + } + Interrupts >>= 1; + ndx++; + } + /* set/clear interrupt enable bit(s) in control register */ + if (bEnable) + { + pDevice->pRTCRegs->CR0 |= cr0; + pDevice->pRTCRegs->CR1 |= cr1; + pDevice->pRTCRegs->CR3SS |= cr3oc; + pDevice->pRTCRegs->CR4SS |= cr4oc; + pDevice->pRTCRegs->CR2IC |= cr2ic; + pDevice->pRTCRegs->CR5SSS |= cr5ocs; + + } + else + { + pDevice->pRTCRegs->CR0 &= ~cr0; + pDevice->pRTCRegs->CR1 &= ~cr1; + pDevice->pRTCRegs->CR3SS &= ~cr3oc; + pDevice->pRTCRegs->CR4SS &= ~cr4oc; + pDevice->pRTCRegs->CR2IC &= ~cr2ic; + pDevice->pRTCRegs->CR5SSS &= ~cr5ocs; + } + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + SYNC_AFTER_WRITE(SR2,BITM_RTC_SR2_WSYNCCR1MIR) + return ADI_RTC_SUCCESS; +} + + +/*! + * @brief Enable RTC automatic clock trimming. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] bEnable Flag controlling RTC enabling trim. + * - true Enable RTC trimming. + * - false Disable RTC trimming. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Enable/disable automatic application of trim values to the main RTC clock. Allows application + * of periodic real-time RTC clock adjustments to correct for drift. Trim values are pre-calibrated + * and stored at manufacture. Trim values may be recalibrated by monitoring the RTC clock externally + * and computing/storing new trim values (see #adi_rtc_SetTrim). + * + * @note The trim interval is reset with device enable, #adi_rtc_Enable(). + * + * @note The RTC device driver does not modify the trim enable on the hardware except through use of this API. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_GetTrim(). + * @sa adi_rtc_SetTrim(). + */ +ADI_RTC_RESULT adi_rtc_EnableTrim (ADI_RTC_HANDLE const hDevice, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear trim enable bit(s) in control register */ + if (bEnable) + { + pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_TRMEN; + } + else + { + pDevice->pRTCRegs->CR0 &=(uint16_t)(~BITM_RTC_CR0_TRMEN); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Enable input capture for the specified channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eInpChannel Specify input compare channel. + * @param[in] bEnable Flag for enabling RTC input capture for specified channel. + * - true Enable input capture. + * - false Disable input capture. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + */ +ADI_RTC_RESULT adi_rtc_EnableInputCapture (ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eInpChannel, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear trim input capture enable for specified channel*/ + if (bEnable) + { + pDevice->pRTCRegs->CR2IC |=(uint16_t)eInpChannel; + } + else + { + pDevice->pRTCRegs->CR2IC &= (uint16_t)(~(uint16_t)eInpChannel); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Enable Overwrite of Unread Snapshots for all RTC Input Capture Channels. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] bEnable Flag for enabling overwriting the unread snapshot. + * - true Enable overwrite snapshot. + * - false Disable overwrite of snapshot. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + */ +ADI_RTC_RESULT adi_rtc_EnableOverwriteSnapshot (ADI_RTC_HANDLE const hDevice, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear trim input capture enable for specified channel*/ + if (bEnable) + { + pDevice->pRTCRegs->CR2IC |= BITM_RTC_CR2IC_ICOWUSEN; + } + else + { + pDevice->pRTCRegs->CR2IC &= (uint16_t)~BITM_RTC_CR2IC_ICOWUSEN; + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Set input capture polarity for the specified channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eInpChannel Specify which input capture channel. + * @param[in] bEnable Flag for selecting RTC input capture polarity. + * - false channel uses a *high-to-low* transition on its GPIO pin to signal an input capture event + * - true channel uses a *low-to-high* transition on its GPIO pin to signal an input capture event. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + */ +ADI_RTC_RESULT adi_rtc_SetInputCapturePolarity (ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eInpChannel, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint32_t nInpChannel = (uint16_t)eInpChannel; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear trim input capture enable for specified channel*/ + if (bEnable) + { + pDevice->pRTCRegs->CR2IC |= (uint16_t)(nInpChannel << BITP_RTC_CR2IC_IC0LH); + } + else + { + pDevice->pRTCRegs->CR2IC &= (uint16_t)~(nInpChannel << BITP_RTC_CR2IC_IC0LH); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC) + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Enable output for the specified Sensor Strobe Channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Specify which Sensor Strobe channel. + * @param[in] bEnable Flag for enabling output for specified Sensor Strobe channel. + * - true Enable output. + * - false Disable output. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + */ +ADI_RTC_RESULT adi_rtc_EnableSensorStrobeOutput (ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR3SS) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear Sensor Strobe enable for specified channel*/ + if (bEnable) + { + pDevice->pRTCRegs->CR3SS |=(uint16_t)eSSChannel; + } + else + { + pDevice->pRTCRegs->CR3SS &= (uint16_t)(~(uint16_t)eSSChannel); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR3SS) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Enable auto reload for given Sensor Strobe Channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Sensor Strobe Channel number. + * @param[in] bEnable Flag to enable auto reload for given Sensor Strobe Channel. + * - true Enable auto reload. + * - false Disable auto reload. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + */ +ADI_RTC_RESULT adi_rtc_EnableAutoReload(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR4SS) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear auto reload enable options */ + /* Note that channel 4 does not have this feature */ + if (bEnable) + { + switch( eSSChannel) + { + case ADI_RTC_SS_CHANNEL_1: + pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS1ARLEN; + break; + case ADI_RTC_SS_CHANNEL_2: + pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS2ARLEN; + break; + case ADI_RTC_SS_CHANNEL_3: + pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS3ARLEN; + break; + default: + return ADI_RTC_FAILURE; + } + + } + else + { + switch( eSSChannel) + { + case ADI_RTC_SS_CHANNEL_1: + pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS1ARLEN; + break; + case ADI_RTC_SS_CHANNEL_2: + pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS2ARLEN; + break; + case ADI_RTC_SS_CHANNEL_3: + pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS3ARLEN; + break; + default: + return ADI_RTC_FAILURE; + } + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR4SS) + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Set auto reload value for the given Sensor Strobe channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Sensor Strobe channel for which auto reload to be set. + * @param[in] nValue Auto reload value to be set. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * + */ +ADI_RTC_RESULT adi_rtc_SetAutoReloadValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t nValue) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + switch( eSSChannel ) + { + case ADI_RTC_SS_CHANNEL_1: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1) + pDevice->pRTCRegs->SS1 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS1) + break; + + case ADI_RTC_SS_CHANNEL_2: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2) + pDevice->pRTCRegs->SS2 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS2) + break; + + case ADI_RTC_SS_CHANNEL_3: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3) + pDevice->pRTCRegs->SS3 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS3) + break; + + case ADI_RTC_SS_CHANNEL_4: + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4) + pDevice->pRTCRegs->SS4 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS4) + break; + + default: + return ADI_RTC_FAILURE; + + } + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Enable or disable thermometer-code masking for the given Sensor Strobe Channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Sensor Strobe channel for which thermometer-code masking to be enabled or disabled. + * @param[in] bEnable Flag to enable or disable masking for the given Sensor Strobe channel. + * - true Enable masking . + * - false Disable masking. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + */ +ADI_RTC_RESULT adi_rtc_EnableSensorStrobeChannelMask(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5, BITM_RTC_SR5_WPENDCR4SS) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear auto reload enable options */ + if (bEnable) + { + pDevice->pRTCRegs->CR4SS |= (uint16_t)eSSChannel; + } + else + { + pDevice->pRTCRegs->CR4SS &= (uint16_t)~(uint16_t)eSSChannel; + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR4SS) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief To set channel mask for the given Sensor Strobe channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Sensor Strobe Channel for which the mask to be set. + * @param[in] nMask Channel Mask to be set for Sensor Strobe channel. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_CHANNEL The given channel is invalid. + */ +ADI_RTC_RESULT adi_rtc_SetSensorStrobeChannelMask(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint8_t nMask) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint16_t MaskPos = 0u; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + switch( eSSChannel ) + { + case ADI_RTC_SS_CHANNEL_1: + MaskPos = (uint16_t)BITP_RTC_SSMSK_SS1MSK; + break; + + case ADI_RTC_SS_CHANNEL_2: + MaskPos = (uint16_t)BITP_RTC_SSMSK_SS2MSK; + break; + + case ADI_RTC_SS_CHANNEL_3: + MaskPos = (uint16_t)BITP_RTC_SSMSK_SS3MSK; + break; + + case ADI_RTC_SS_CHANNEL_4: + MaskPos = (uint16_t)BITP_RTC_SSMSK_SS4MSK; + break; + + default: + return ADI_RTC_INVALID_CHANNEL; + } + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5, BITM_RTC_SR5_WPENDSSMSK) + + pDevice->pRTCRegs->SSMSK = ((uint16_t)nMask & 0xFu) << MaskPos; + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4, BITM_RTC_SR4_WSYNCSSMSK) + + return ADI_RTC_SUCCESS; +} + +/************************************************************************************************* +************************************************************************************************** +****************************************** GET APIS ****************************************** +************************************************************************************************** +*************************************************************************************************/ + + +/*! + * @brief Get current RTC alarm value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pAlarm Pointer to application memory where the alarm value is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the currently programmed 32-bit RTC alarm value and write it to the address provided by parameter \a pAlarm. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_SetAlarm(). + */ +ADI_RTC_RESULT adi_rtc_GetAlarm (ADI_RTC_HANDLE hDevice, uint32_t *pAlarm) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint32_t nAlarm; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1)) + + /* disable interrupts during paired read */ + NVIC_DisableIRQ(pDevice->eIRQn); + nAlarm =(uint32_t) pDevice->pRTCRegs->ALM1 << 16u; + nAlarm |= (uint32_t)pDevice->pRTCRegs->ALM0; + NVIC_EnableIRQ((IRQn_Type)(pDevice->eIRQn)); + + *pAlarm = nAlarm; + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Get current RTC alarm value with fractional part also. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pAlarm Pointer to application memory where the alarm value is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the currently programmed 32-bit RTC alarm value and write it to the address provided by parameter \a pAlarm. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_SetAlarm(). + */ +ADI_RTC_RESULT adi_rtc_GetAlarmEx (ADI_RTC_HANDLE hDevice, float *pAlarm) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint32_t nAlarm,nTemp; + uint16_t nPreScale; + float fFraction; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1)) + nPreScale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP; + /* disable interrupts during paired read */ + NVIC_DisableIRQ(pDevice->eIRQn); + nAlarm = (uint32_t)pDevice->pRTCRegs->ALM1 << 16u; + nAlarm |= (uint32_t)pDevice->pRTCRegs->ALM0; + NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn); + nTemp = 1lu<pRTCRegs->ALM2 /(float)(nTemp); + + *pAlarm = (float)nAlarm+fFraction; + + return ADI_RTC_SUCCESS; +} + + +/*! + * @brief Get current RTC control register value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eRegister Specify which register content need to be returned. + * + * @param[out] pControl Pointer to application memory where the control register value is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the currently programmed 16-bit RTC control register value and write it to the address provided by parameter \a pControl. + * + * @sa adi_rtc_Open(). + * @sa adi_rtcSetControl(). + */ +ADI_RTC_RESULT adi_rtc_GetControl (ADI_RTC_HANDLE hDevice, ADI_RTC_CONTROL_REGISTER eRegister ,uint32_t *pControl) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + switch(eRegister) + { + case ADI_RTC_CONTROL_REGISTER_0: + *pControl = pDevice->pRTCRegs->CR0; + break; + case ADI_RTC_CONTROL_REGISTER_1: + *pControl = pDevice->pRTCRegs->CR1; + break; + default: + return(ADI_RTC_FAILURE); + } + return ADI_RTC_SUCCESS; +} + + +/*! + * @brief Get current RTC count value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pCount Pointer to application memory where the count value is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the current 32-bit RTC count value and write it to the address provided by parameter \a pCount. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_GetCount(ADI_RTC_HANDLE const hDevice, uint32_t *pCount) +{ + uint32_t nCount; + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* Wait till previously posted write to couunt Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1)) + + /* disable interrupts during paired read */ + NVIC_DisableIRQ(pDevice->eIRQn); + nCount = (uint32_t)pDevice->pRTCRegs->CNT1 << 16u; + nCount |= pDevice->pRTCRegs->CNT0; + *pCount = nCount; + NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn); + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Get current RTC count value with fraction. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pfCount Pointer to application memory where the count(with fraction) value is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the current 32-bit RTC count value and write it to the address provided by parameter \a pCount. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_GetCountEx(ADI_RTC_HANDLE const hDevice, float *pfCount) +{ + uint32_t nCount,nTemp; + uint16_t nPrescale; + ADI_RTC_DEVICE *pDevice = hDevice; + float fFraction; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to couunt Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1)) + nPrescale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP; + /* disable interrupts during paired read */ + NVIC_DisableIRQ(pDevice->eIRQn); + nCount = (uint32_t)pDevice->pRTCRegs->CNT1 << 16u; + nCount |= pDevice->pRTCRegs->CNT0; + nTemp = (1lu<pRTCRegs->CNT2/(float)(nTemp); + NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn); + *pfCount = (float)nCount+ fFraction; + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Get current RTC count value of all registers. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pnCount Pointer to application memory where the count's 32 MSB are written. + * @param[out] pfCount Pointer to application memory where the count's 16 LSB are written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the current 32-bit RTC count integer value and fractional value in the integer format. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_GetCountRegs(ADI_RTC_HANDLE const hDevice, uint32_t *pnCount, uint32_t *pfCount) +{ + uint32_t nCount; + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to couunt Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1)) + /* disable interrupts during paired read */ + NVIC_DisableIRQ(pDevice->eIRQn); + nCount = (uint32_t)pDevice->pRTCRegs->CNT1 << 16u; + nCount |= pDevice->pRTCRegs->CNT0; + *pnCount= nCount; + *pfCount = (uint32_t)pDevice->pRTCRegs->CNT2; + NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn); + return ADI_RTC_SUCCESS; +} + + + +/*! + * @brief Get current RTC clock trim value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] peTrim Pointer to #ADI_RTC_TRIM_VALUE where the trim value is to be written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the current 16-bit RTC trim value and write it to the address provided by parameter \a pTrim. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_EnableInterrupts(). + * @sa adi_rtc_EnableTrim(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_GetWriteSyncStatus(). + * @sa adi_rtc_SetTrim(). + */ +ADI_RTC_RESULT adi_rtc_GetTrim (ADI_RTC_HANDLE hDevice, ADI_RTC_TRIM_VALUE *peTrim) +{ + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + if(peTrim == NULL) + { + return( ADI_RTC_INVALID_PARAM); + } +#endif + + /* Wait till previously posted write to couunt Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDTRM); + + *peTrim =(ADI_RTC_TRIM_VALUE)(pDevice->pRTCRegs->TRM & BITM_RTC_TRM_VALUE); + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Get Sensor Strobe value for the given Sensor Strobe channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Sensor Strobe Channel whose value to be read. + * @param[out] pValue Pointer to application memory where the Sensor Strobe value to be written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_GetSensorStrobeValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t *pValue) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + switch( eSSChannel ) + { + case ADI_RTC_SS_CHANNEL_1: + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1) + *pValue = pDevice->pRTCRegs->SS1; + break; + + case ADI_RTC_SS_CHANNEL_2: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2) + *pValue = pDevice->pRTCRegs->SS2; + break; + + case ADI_RTC_SS_CHANNEL_3: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3) + *pValue = pDevice->pRTCRegs->SS3; + break; + + case ADI_RTC_SS_CHANNEL_4: + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4) + *pValue = pDevice->pRTCRegs->SS4; + break; + + default: + return ADI_RTC_FAILURE; + } + + + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Set Sensor Strobe value for the given Sensor Strobe channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Sensor Strobe Channel. + * @param[out] nValue Sensor Strobe value to be set for the given Sensor Strobe channel . + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_SetSensorStrobeValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t nValue) +{ + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + switch( eSSChannel ) + { + case ADI_RTC_SS_CHANNEL_1: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1) + pDevice->pRTCRegs->SS1 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS1) + break; + + case ADI_RTC_SS_CHANNEL_2: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2) + pDevice->pRTCRegs->SS2 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS2) + break; + + case ADI_RTC_SS_CHANNEL_3: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3) + pDevice->pRTCRegs->SS3 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS3) + break; + + case ADI_RTC_SS_CHANNEL_4: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4) + pDevice->pRTCRegs->SS4 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS4) + break; + + default: + return ADI_RTC_FAILURE; + } + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Get input capture value for specified input channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eChannel Specify which input capture channel. + * @param[out] pValue Pointer to application memory where the input capture value to be written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * - #ADI_RTC_INVALID_CHANNEL [D] Input channel-0 is not valid for this operation since + * channel-0 can provide precise (47bit) capture value. + * + * + * + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_GetInputCaptureValue(ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eChannel, uint16_t *pValue) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + ADI_RTC_RESULT eResult= ADI_RTC_SUCCESS; + +#ifdef ADI_DEBUG + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + switch(eChannel) + { + case ADI_RTC_INPUT_CHANNEL_2: + *pValue = pDevice->pRTCRegs->IC2; + break; + case ADI_RTC_INPUT_CHANNEL_3: + *pValue = pDevice->pRTCRegs->IC3; + break; + + case ADI_RTC_INPUT_CHANNEL_4: + *pValue = pDevice->pRTCRegs->IC4; + break; + default: + eResult = ADI_RTC_INVALID_CHANNEL; + break; + } + return(eResult); +} +/*! + * @brief Get snapshot of the value of RTC . + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eChannel Specify input channel from which captured value to be obtained. + * @param[in] pFraction Pointer to application memory where the fractional part of snap shot value to be written. + * @param[out] pValue Pointer to application memory where the snap shot value of RTC to be written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * + * + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_GetSnapShot(ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eChannel, uint32_t *pValue, uint16_t *pFraction) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + ADI_RTC_RESULT eResult= ADI_RTC_SUCCESS; + uint32_t nCount = 0u; +#ifdef ADI_DEBUG + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* disable interrupts during paired read */ + NVIC_DisableIRQ(pDevice->eIRQn); + nCount = (uint32_t)pDevice->pRTCRegs->SNAP1 << 16u; + nCount |= pDevice->pRTCRegs->SNAP0; + *pFraction = pDevice->pRTCRegs->SNAP2; + *pValue = nCount; + NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn); + return(eResult); +} + + +/*! + * @brief Get current RTC posted write pending status. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pPendBits Pointer to application memory where the posted write status is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * + * \b Pending \b Writes: Register writes to internal RTC registers take time to complete because the RTC controller + * clock is running at a much slower (32kHz) rate than the core processor clock. So each RTC write register has a + * one-deep FIFO to hold write values until the RTC can effect them. This gives rise to the notion of a \a pending + * \a write state: if a write is already pending and another write from the core comes along before the first (pending) + * write has cleared to its destination register, the second write may be lost because the FIFO is full already. + * + * To avoid data loss, the user may tell the RTC device driver to enforce safe writes with the configuration switch + * ADI_RTC_CFG_ENABLE_SAFE_WRITE. Enabeling safe writes (on be default) insures write data is never lost by + * detecting and pausing on pending writes prior writing new data. The penalty in using safe writes is the stall + * overhead in execution (which is not incurred if there is nothing pending). Additionally, \a all pending writes + * may also be synchronized manually with the #adi_rtc_SynchronizeAllWrites() API, which will pause until all + * pending RTC writes have completed. + * + * The distinction between "pend" status (#adi_rtc_GetWritePendStatus()) and "sync" (#adi_rtc_GetWriteSyncStatus()) + * status is that the \a pend state is normally clear and is set only while no room remains in a register's write FIFO, + * whereas \a sync state is normally set and is clear only while the effects of the write are not yet apparent. + * + * Each write error + * source may be configured to interrupt the core by enabling the appropriate + * write error interrupt mask bit in the RTC control register (see the + * #adi_rtc_EnableInterrupts() API), at which time, the RTC interrupt handler + * will be dispatched. + * + * @sa adi_rtc_Open(). + * @sa #adi_rtc_EnableInterrupts(). + * @sa adi_rtc_GetWriteSyncStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_GetWritePendStatus (ADI_RTC_HANDLE const hDevice, ADI_RTC_WRITE_STATUS *pPendBits) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint16_t nPendBits; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* get the value */ + nPendBits = pDevice->pRTCRegs->SR1 & ADI_RTC_WRITE_STATUS_MASK; + *pPendBits = (ADI_RTC_WRITE_STATUS)nPendBits; + + return ADI_RTC_SUCCESS; +} + + +/*! + * @brief Get current RTC posted write synchronization status. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pSyncBits Pointer to application memory where the posted write status is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * + * \b Pending \b Writes: Register writes to internal RTC registers take time to complete because the RTC controller + * clock is running at a much slower (32kHz) rate than the core processor clock. So each RTC write register has a + * one-deep FIFO to hold write values until the RTC can effect them. This gives rise to the notion of a \a pending + * \a write state: if a write is already pending and another write from the core comes along before the first (pending) + * write has cleared to its destination register, the second write may be lost because the FIFO is full already. + * + * To avoid data loss, the user may tell the RTC device driver to enforce safe writes with the + * #ADI_RTC_CFG_ENABLE_SAFE_WRITE switch. Enabling safe writes (on be default) insures write data is never lost by + * detecting and pausing on pending writes prior writing new data. The penalty in using safe writes is the stall + * overhead in execution (which is not incurred if there is nothing pending). Additionally, \a all pending writes + * may also be synchronized manually with the #adi_rtc_SynchronizeAllWrites() API, which will pause until all + * pending RTC writes have completed. + * + * The distinction between "pend" status (#adi_rtc_GetWritePendStatus()) and "sync" (#adi_rtc_GetWriteSyncStatus()) + * status is that the \a pend state is normally clear is set only while no room remains in a register's write FIFO, + * whereas \a sync state is normally set and is clear only while the effects of the write are not yet apparent. + * + * Each write error source may be configured to interrupt the core by enabling + * the appropriate write error interrupt mask bit in the RTC control register + * (see the #adi_rtc_EnableInterrupts() API), at which time, the RTC interrupt + * handler will be dispatched. + * + * @sa adi_rtc_Open(). + * @sa #adi_rtc_EnableInterrupts(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtcStallOnPendingWrites(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_GetWriteSyncStatus (ADI_RTC_HANDLE const hDevice, ADI_RTC_WRITE_STATUS *pSyncBits) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint16_t nSyncBits; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to couunt Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDSR0); + + /* get the value */ + nSyncBits = pDevice->pRTCRegs->SR0 & ADI_RTC_WRITE_STATUS_MASK; + *pSyncBits = (ADI_RTC_WRITE_STATUS)nSyncBits; + + return ADI_RTC_SUCCESS; +} + + +/************************************************************************************************* +************************************************************************************************** +****************************************** SET APIS ****************************************** +************************************************************************************************** +*************************************************************************************************/ + + +/*! + * @brief Set a new RTC alarm value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] nAlarm New alarm value to set. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Writes the 32-bit RTC alarm comparator with the value provided by \a Alarm. + * + * Honours the safe write mode if set. Otherwise, it is the application's responsibility to + * synchronize any multiple writes to the same register. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_GetAlarm(). + * @sa adi_rtc_EnableAlarm(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_SetAlarm (ADI_RTC_HANDLE const hDevice, uint32_t nAlarm) +{ + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* Wait till previously posted write to Alram Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1)) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* RTC hardware insures paired write, so no need to disable interrupts */ + pDevice->pRTCRegs->ALM0 = (uint16_t)nAlarm; + pDevice->pRTCRegs->ALM1 = (uint16_t)(nAlarm >> 16); + pDevice->pRTCRegs->ALM2 = 0u; + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1)) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Set Prescale. This is power of 2 division factor for the RTC base clock. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] nPreScale Prescale value to be set. if "nPreScale" is 5, RTC base clock is + divided by 32. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_GetAlarm(). + * @sa adi_rtc_EnableAlarm(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_SetPreScale(ADI_RTC_HANDLE const hDevice, uint8_t nPreScale ) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint16_t nTemp; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + /* Pre scale is invalid for RTC0 */ + if(pDevice->pRTCRegs == pADI_RTC0) + { + return(ADI_RTC_OPERATION_NOT_ALLOWED); + } +#endif + PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDCR1MIR) + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* RTC hardware insures paired write, so no need to disable interrupts */ + /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/ + nTemp = pDevice->pRTCRegs->CR1 & (uint16_t)~BITM_RTC_CR1_PRESCALE2EXP; + nTemp |= (uint16_t)((uint16_t)nPreScale << BITP_RTC_CR1_PRESCALE2EXP); + pDevice->pRTCRegs->CR1 = nTemp; + ADI_EXIT_CRITICAL_REGION(); + + SYNC_AFTER_WRITE(SR2,BITM_RTC_SR2_WSYNCCR1MIR) + return ADI_RTC_SUCCESS; +} +/*! + * @brief Set the pre-scale. This is power of 2 division factor for the RTC base clock. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] nPeriod Periodic, modulo-60 alarm time in pre-scaled RTC time units beyond a modulo-60 boundary. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * @note This API helps the CPU to position a periodic (repeating) alarm interrupt from the RTC at any integer number of pre-scaled RTC time units from a modulo-60 boundary (roll-over event) of the value of count. + * @sa adi_rtc_Open(). + * @sa adi_rtc_GetAlarm(). + * @sa adi_rtc_EnableAlarm(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_SetMod60AlarmPeriod(ADI_RTC_HANDLE const hDevice, uint8_t nPeriod ) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint16_t nTemp; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + + /* Mod60 Alarm is valid only in RTC-1 */ + if(pDevice->pRTCRegs == pADI_RTC0) + { + return(ADI_RTC_OPERATION_NOT_ALLOWED); + } + +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* RTC hardware insures paired write, so no need to disable interrupts */ + /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/ + nTemp = pDevice->pRTCRegs->CR0 & BITM_RTC_CR0_MOD60ALM; + nTemp |= (uint16_t)((uint16_t)nPeriod << BITP_RTC_CR0_MOD60ALM); + pDevice->pRTCRegs->CR0 = nTemp; + ADI_EXIT_CRITICAL_REGION(); + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Set a new RTC alarm value with fractional value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] fAlarm New alarm value to set. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Writes the 32-bit RTC alarm comparator with the value provided by \a Alarm. + * + * Honours the safe write mode if set. Otherwise, it is the application's responsibility to + * synchronize any multiple writes to the same register. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_GetAlarm(). + * @sa adi_rtc_EnableAlarm(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_SetAlarmEx(ADI_RTC_HANDLE const hDevice, float fAlarm) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint32_t nAlarm = (uint32_t)fAlarm,nTemp; + uint16_t nPreScale; + float fFraction; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + /* Only 1Hz clocking is supported in RTC-0.So no fractional Alarm. */ + if(pDevice->pRTCRegs == pADI_RTC0) + { + return(ADI_RTC_OPERATION_NOT_ALLOWED); + } + +#endif + + /* Wait till previously posted write to Alarm Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1)) + nPreScale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP; + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* RTC hardware insures paired write, so no need to disable interrupts */ + /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/ + pDevice->pRTCRegs->ALM0 = (uint16_t)nAlarm; + pDevice->pRTCRegs->ALM1 = (uint16_t)(nAlarm >> 16); + nTemp = 1lu<pRTCRegs->ALM2 = (uint16_t)(fFraction); + ADI_EXIT_CRITICAL_REGION(); + /* Wait till write to Alarm Register to take effect */ + SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1)) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Set a new RTC control register value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eRegister Specify which register need to be initialized. + * @param[in] Control New control register value to set. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Writes the 16-bit RTC control register with the value provided by \a Control. + * + * Honours the safe write mode if set. Otherwise, it is the application's responsibility to + * synchronize any multiple writes to the same register. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_GetControlRegister(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_SetControlRegister(ADI_RTC_HANDLE const hDevice,ADI_RTC_CONTROL_REGISTER eRegister, uint32_t Control) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + switch(eRegister) + { + case ADI_RTC_CONTROL_REGISTER_0: + pDevice->pRTCRegs->CR0 = (uint16_t)Control; + break; + case ADI_RTC_CONTROL_REGISTER_1: + pDevice->pRTCRegs->CR1 = (uint16_t)Control; + break; + default: + return(ADI_RTC_FAILURE); + } + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; + +} + +/*! + * @brief Registers a Callback function with the RTC device driver. The registered call + * back function will be called when an event is detected. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param [in] pfCallback Function pointer to Callback function. Passing a NULL pointer will + * unregister the call back function. + * + * @param [in] pCBparam Call back function parameter. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * @sa adi_rtc_Open(). + */ +ADI_RTC_RESULT adi_rtc_RegisterCallback( + ADI_RTC_HANDLE const hDevice, + ADI_CALLBACK const pfCallback, + void *const pCBparam + ) + +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + +#if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1) + /* pause on pending writes to CR to avoid data loss */ + while((pDevice->pRTCRegs->SR1 & (uint32_t)ADI_RTC_WRITE_STATUS_CONTROL0)!=0u) + { + } +#endif + /* Store the address of the callback function */ + pDevice->pfCallback = pfCallback; + /* Store the call back parameter */ + pDevice->pCBParam = pCBparam; + + return ADI_RTC_SUCCESS; + +} + +/*! + * @brief Set a new RTC count value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] nCount New count value to set. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Writes the main 32-bit RTC counter with the value provided by \a Count. + * + * Honours the safe write mode if set. Otherwise, it is the application's responsibility to + * synchronize any multiple writes to the same register. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_SetCount(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_SetCount (ADI_RTC_HANDLE const hDevice, uint32_t nCount) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + +#if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1) + /* pause on pending writes to CR to avoid data loss */ + while((pDevice->pRTCRegs->SR1 & (uint32_t)(ADI_RTC_WRITE_STATUS_COUNT0 | ADI_RTC_WRITE_STATUS_COUNT1)) !=0u) + { + + } +#endif + + /* Wait till previously posted write to count Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1)) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* RTC hardware insures paired write, so no need to disable interrupts */ + pDevice->pRTCRegs->CNT0 = (uint16_t)nCount; + pDevice->pRTCRegs->CNT1 = (uint16_t)(nCount >> 16); + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to count Register to take effect */ + SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCCNT0|BITM_RTC_SR0_WSYNCCNT1)) + + return ADI_RTC_SUCCESS; +} + + +/*! + * @brief Set an RTC gateway command. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] Command Gateway command value. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Writes the 16-bit RTC gateway register with the command provided by \a Command. + * + * The gateway register is used to force the RTC to perform some urgent action. + * + * Currently, only the #ADI_RTC_GATEWAY_FLUSH command is defined, which will cancel all + * RTC register write transactions, both pending and executing. It is intended to truncate + * all core interactions in preparation for an imminent power loss when the RTC power + * isolation barrier will be activated. + * + * @sa adi_rtc_Open(). + */ +ADI_RTC_RESULT adi_rtc_SetGateway(ADI_RTC_HANDLE const hDevice, uint16_t Command) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* set the command */ + pDevice->pRTCRegs->GWY = Command; + return ADI_RTC_SUCCESS; +} + + + +/*! + * @brief Set a new RTC trim value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eInterval Specify the trimming interval and will always in the range of (2^2 to S^17 pre-scaled RTC clock ). + * @param[in] eTrimValue Specify the trimming value. + * @param[in] eOperation Specify the operation(Add or subtract) need to be performed for trimming. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] Input parameter out of range. + * + * The RTC hardware has the ability to automatically trim the clock to compensate for variations + * in oscillator tolerance . Automatic trimming is enabled with the #adi_rtc_EnableTrim() API. + * + * @note Alarms are not affected by automatic trim operations. + * + * @note The trim boundary (interval) alignment is reset when new trim values are written. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_EnableTrim(). + * @sa adi_rtc_GetTrim(). + */ +ADI_RTC_RESULT adi_rtc_SetTrim(ADI_RTC_HANDLE const hDevice, ADI_RTC_TRIM_INTERVAL eInterval, ADI_RTC_TRIM_VALUE eTrimValue, ADI_RTC_TRIM_POLARITY eOperation) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint32_t trm = (uint32_t)eInterval | (uint32_t)eTrimValue | (uint32_t)eOperation; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDTRM) + + pDevice->pRTCRegs->TRM = (uint16_t)trm; + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCTRM) + + return ADI_RTC_SUCCESS; +} + + +/************************************************************************************************* +************************************************************************************************** +************************************ SYNCHRONIZATION API ************************************* +************************************************************************************************** +*************************************************************************************************/ + + +/*! + * @brief Force synchronization of all pending writes. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Blocking call to coerce all outstanding posted RTC register writes to fully flush and synchronize. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_GetWriteSyncStatus(). +*/ +ADI_RTC_RESULT adi_rtc_SynchronizeAllWrites (ADI_RTC_HANDLE const hDevice) +{ + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + +#endif + + /* forced block until all SYNC bits are set (ignore bSafe) */ + while (ADI_RTC_WRITE_STATUS_MASK != (pDevice->pRTCRegs->SR0 & ADI_RTC_WRITE_STATUS_MASK)) + { + + } + + return ADI_RTC_SUCCESS; +} + + +/*! \cond PRIVATE */ + +/* + * @brief Initializes the device using static configuration + * + * @param[in] pDevice Pointer to RTC device . + pConfig Pointer to static configuration device structure. + * +*/ + +static void rtc_init(ADI_RTC_DEVICE *pDevice,ADI_RTC_CONFIG *pConfig) +{ + + /* FIXME - static init is even more now */ + + /* Control register -0 which controls all main stream activity of RTC0 */ + pDevice->pRTCRegs->CR0 = pConfig->CR0; + /* Control register -1 which is granularity of RTC control register */ + pDevice->pRTCRegs->CR1 = pConfig->CR1; + /*CNT0 contains the lower 16 bits of the RTC counter */ + pDevice->pRTCRegs->CNT0 = pConfig->CNT0; + /*CNT1 contains the lower 16 bits of the RTC counter */ + pDevice->pRTCRegs->CNT1 = pConfig->CNT1; + /* ALM0 contains the lower 16 bits of the Alarm register */ + pDevice->pRTCRegs->ALM0 = pConfig->ALM0; + /* ALM1 contains the upper 16 bits of the Alarm register */ + pDevice->pRTCRegs->ALM1 = pConfig->ALM1; + /* ALM1 contains the fractional part of the Alarm register */ + pDevice->pRTCRegs->ALM2 = pConfig->ALM2; + /* Set Input capture/sensor strobe registers only for RTC1 */ + if(pDevice->pRTCRegs == pADI_RTC1) + { + pDevice->pRTCRegs->CR2IC = pConfig->CR2IC; + pDevice->pRTCRegs->CR3SS = pConfig->CR3SS; + pDevice->pRTCRegs->CR4SS = pConfig->CR4SS; + pDevice->pRTCRegs->SSMSK = pConfig->SSMSK; + pDevice->pRTCRegs->SS1 = pConfig->SS1; + pDevice->pRTCRegs->CR5SSS = pConfig->CR5SSS; + pDevice->pRTCRegs->CR6SSS = pConfig->CR6SSS; + pDevice->pRTCRegs->CR7SSS = pConfig->CR7SSS; + pDevice->pRTCRegs->GPMUX0 = pConfig->GPMUX0; + pDevice->pRTCRegs->GPMUX1 = pConfig->GPMUX1; + } +} + + + +/*! @brief RTC device driver interrupt handler. Overrides weakly-bound default interrupt handler in _startup.c. */ +void RTC0_Int_Handler(void) +{ + ISR_PROLOG(); + uint16_t nIntSrc0, nIntSrc2, nIntSrc3; + uint32_t fired = 0u, enables = 0u; + ADI_RTC_DEVICE *pDevice = aRTCDeviceInfo[0].hDevice; + + /* determine qualified interrupt source(s) */ + /* need to test each interrupt source and whether it is enabled before notifying */ + /* because each source is latched regardless of whether it is enabled or not :-( */ + + /* CR0 SR0 */ + enables = (uint32_t)pDevice->pRTCRegs->CR0 & ADI_RTC_INT_ENA_MASK_CR0; + nIntSrc0 = pDevice->pRTCRegs->SR0 & ADI_RTC_INT_SOURCE_MASK_SR0; + if( nIntSrc0 && enables ) + { + if( (enables & BITM_RTC_CR0_MOD60ALMEN) && (nIntSrc0 & BITM_RTC_SR0_MOD60ALMINT)) + { + fired |= ADI_RTC_MOD60ALM_INT; + } + if( (enables & BITM_RTC_CR0_ALMINTEN) && (nIntSrc0 & BITM_RTC_SR0_ALMINT)) + { + fired |= ADI_RTC_ALARM_INT; + } + if( (enables & BITM_RTC_CR0_ISOINTEN) && (nIntSrc0 & BITM_RTC_SR0_ISOINT)) + { + fired |= ADI_RTC_ISO_DONE_INT; + } + if( (enables & BITM_RTC_CR0_WPNDINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDINT)) + { + fired |= ADI_RTC_WRITE_PEND_INT; + } + if( (enables & BITM_RTC_CR0_WSYNCINTEN) && (nIntSrc0 & BITM_RTC_SR0_WSYNCINT)) + { + fired |= ADI_RTC_WRITE_SYNC_INT; + } + if( (enables & BITM_RTC_CR0_WPNDERRINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDERRINT)) + { + fired |= ADI_RTC_WRITE_PENDERR_INT; + } + } + + /* CR1 SR2 */ + enables = (uint32_t)pDevice->pRTCRegs->CR1 & ADI_RTC_INT_ENA_MASK_CR1; + nIntSrc2 = pDevice->pRTCRegs->SR2 & ADI_RTC_INT_SOURCE_MASK_SR2; + if( nIntSrc2 && enables ) + { + if( (enables & BITM_RTC_CR1_CNTMOD60ROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTMOD60ROLLINT)) + { + fired |= ADI_RTC_MOD60_ROLLOVER_INT; + } + if( (enables & BITM_RTC_CR1_CNTROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTROLLINT)) + { + fired |= ADI_RTC_COUNT_ROLLOVER_INT; + } + if( (enables & BITM_RTC_CR1_TRMINTEN) && (nIntSrc2 & BITM_RTC_SR2_TRMINT)) + { + fired |= ADI_RTC_TRIM_INT; + } + if( (enables & BITM_RTC_CR1_PSINTEN) && (nIntSrc2 & BITM_RTC_SR2_PSINT)) + { + fired |= ADI_RTC_PSI_INT; + } + if( (enables & BITM_RTC_CR1_CNTINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTINT)) + { + fired |= ADI_RTC_COUNT_INT; + } + } + + /* CR3OC, CR2IC SR3*/ + enables = pDevice->pRTCRegs->CR3SS & (uint16_t)ADI_RTC_INT_ENA_MASK_CR3SS; + nIntSrc3 = pDevice->pRTCRegs->SR3 & ADI_RTC_SR3_IRQ_STATUS_MASK; + if( nIntSrc3 && enables ) + { + if( (enables & BITM_RTC_CR3SS_SS4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH4_INT; + } + if( (enables & BITM_RTC_CR3SS_SS3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH3_INT; + } + if( (enables & BITM_RTC_CR3SS_SS2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH2_INT; + } + if( (enables & BITM_RTC_CR3SS_SS1IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH1_INT; + } + + if( (enables & BITM_RTC_CR3SS_SS4FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4FEIRQ)) + { + fired |= ADI_RTC_RTCSS4_FE_INT; + } + if( (enables & BITM_RTC_CR3SS_SS3FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2FEIRQ)) + { + fired |= ADI_RTC_RTCSS3_FE_INT; + } + if( (enables & BITM_RTC_CR3SS_SS2FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3FEIRQ)) + { + fired |= ADI_RTC_RTCSS2_FE_INT; + } + if( (enables & BITM_RTC_CR3SS_SS1FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1FEIRQ)) + { + fired |= ADI_RTC_RTCSS1_FE_INT; + } + } + enables = pDevice->pRTCRegs->CR3SS & (uint16_t)ADI_RTC_INT_ENA_MASK_CR2IC; + if( nIntSrc3 && enables ) + { + if( (enables & BITM_RTC_CR2IC_IC4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC4IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH4_INT; + } + if( (enables & BITM_RTC_CR2IC_IC3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC3IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH3_INT; + } + if( (enables & BITM_RTC_CR2IC_IC2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC2IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH2_INT; + } + if( (enables & BITM_RTC_CR2IC_IC0IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC0IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH0_INT; + } + } + + + if (pDevice->pfCallback != NULL) { + + /* forward to the user if he is watching this interrupt */ + /* pass the "fired" value as the event. argument param is not used */ + if ( fired) + { + pDevice->pfCallback (pDevice->pCBParam, fired, NULL); + } + } + + /* Write 1 to clear the interrupts */ + pDevice->pRTCRegs->SR0 |= nIntSrc0; + pDevice->pRTCRegs->SR2 |= nIntSrc2; + pDevice->pRTCRegs->SR3 |= nIntSrc3; + ISR_EPILOG(); +} + +/*! @brief RTC device driver interrupt handler. Overrides weakly-bound default interrupt handler in _startup.c. */ +void RTC1_Int_Handler(void) +{ + ISR_PROLOG(); + uint16_t nIntSrc0, nIntSrc2, nIntSrc3; + uint32_t fired = 0u, enables = 0u; + ADI_RTC_DEVICE *pDevice = aRTCDeviceInfo[1].hDevice; + + /* determine qualified interrupt source(s) */ + /* need to test each interrupt source and whether it is enabled before notifying */ + /* because each source is latched regardless of whether it is enabled or not :-( */ + + /* CR0 SR0 */ + enables = (uint32_t)pDevice->pRTCRegs->CR0 & ADI_RTC_INT_ENA_MASK_CR0; + nIntSrc0 = pDevice->pRTCRegs->SR0 & ADI_RTC_INT_SOURCE_MASK_SR0; + if( nIntSrc0 && enables ) + { + if( (enables & BITM_RTC_CR0_MOD60ALMEN) && (nIntSrc0 & BITM_RTC_SR0_MOD60ALMINT)) + { + fired |= ADI_RTC_MOD60ALM_INT; + } + if( (enables & BITM_RTC_CR0_ALMINTEN) && (nIntSrc0 & BITM_RTC_SR0_ALMINT)) + { + fired |= ADI_RTC_ALARM_INT; + } + if( (enables & BITM_RTC_CR0_ISOINTEN) && (nIntSrc0 & BITM_RTC_SR0_ISOINT)) + { + fired |= ADI_RTC_ISO_DONE_INT; + } + if( (enables & BITM_RTC_CR0_WPNDINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDINT)) + { + fired |= ADI_RTC_WRITE_PEND_INT; + } + if( (enables & BITM_RTC_CR0_WSYNCINTEN) && (nIntSrc0 & BITM_RTC_SR0_WSYNCINT)) + { + fired |= ADI_RTC_WRITE_SYNC_INT; + } + if( (enables & BITM_RTC_CR0_WPNDERRINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDERRINT)) + { + fired |= ADI_RTC_WRITE_PENDERR_INT; + } + } + + /* CR1 SR2 */ + enables = (uint32_t)pDevice->pRTCRegs->CR1 & ADI_RTC_INT_ENA_MASK_CR1; + nIntSrc2 = pDevice->pRTCRegs->SR2 & ADI_RTC_INT_SOURCE_MASK_SR2; + if( nIntSrc2 && enables ) + { + if( (enables & BITM_RTC_CR1_CNTMOD60ROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTMOD60ROLLINT)) + { + fired |= ADI_RTC_MOD60_ROLLOVER_INT; + } + if( (enables & BITM_RTC_CR1_CNTROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTROLLINT)) + { + fired |= ADI_RTC_COUNT_ROLLOVER_INT; + } + if( (enables & BITM_RTC_CR1_TRMINTEN) && (nIntSrc2 & BITM_RTC_SR2_TRMINT)) + { + fired |= ADI_RTC_TRIM_INT; + } + if( (enables & BITM_RTC_CR1_PSINTEN) && (nIntSrc2 & BITM_RTC_SR2_PSINT)) + { + fired |= ADI_RTC_PSI_INT; + } + if( (enables & BITM_RTC_CR1_CNTINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTINT)) + { + fired |= ADI_RTC_COUNT_INT; + } + } + + /* CR3OC, CR2IC SR3*/ + enables = pDevice->pRTCRegs->CR3SS & (uint32_t)ADI_RTC_INT_ENA_MASK_CR3SS; + nIntSrc3 = pDevice->pRTCRegs->SR3 & ADI_RTC_SR3_IRQ_STATUS_MASK; + if( nIntSrc3 && enables ) + { + if( (enables & BITM_RTC_CR3SS_SS4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH4_INT; + } + if( (enables & BITM_RTC_CR3SS_SS3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH3_INT; + } + if( (enables & BITM_RTC_CR3SS_SS2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH2_INT; + } + if( (enables & BITM_RTC_CR3SS_SS1IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH1_INT; + } + + if( (enables & BITM_RTC_CR3SS_SS4FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4FEIRQ)) + { + fired |= ADI_RTC_RTCSS4_FE_INT; + } + if( (enables & BITM_RTC_CR3SS_SS3FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2FEIRQ)) + { + fired |= ADI_RTC_RTCSS3_FE_INT; + } + if( (enables & BITM_RTC_CR3SS_SS2FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3FEIRQ)) + { + fired |= ADI_RTC_RTCSS2_FE_INT; + } + if( (enables & BITM_RTC_CR3SS_SS1FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1FEIRQ)) + { + fired |= ADI_RTC_RTCSS1_FE_INT; + } + } + enables = pDevice->pRTCRegs->CR2IC & (uint32_t)ADI_RTC_INT_ENA_MASK_CR2IC; + if( nIntSrc3 && enables ) + { + if( (enables & BITM_RTC_CR2IC_IC4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC4IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH4_INT; + } + if( (enables & BITM_RTC_CR2IC_IC3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC3IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH3_INT; + } + if( (enables & BITM_RTC_CR2IC_IC2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC2IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH2_INT; + } + if( (enables & BITM_RTC_CR2IC_IC0IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC0IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH0_INT; + } + } + + if (pDevice->pfCallback != NULL) { + + /* forward to the user if he is watching this interrupt */ + /* pass the "fired" value as the event. argument param is not used */ + if ( fired) + { + pDevice->pfCallback (pDevice->pCBParam, fired, NULL); + } + } + + /* Write 1 to clear the interrupts */ + pDevice->pRTCRegs->SR0 |= nIntSrc0; + pDevice->pRTCRegs->SR2 |= nIntSrc2; + pDevice->pRTCRegs->SR3 |= nIntSrc3; + + ISR_EPILOG(); +} + +/*! \endcond */ + +/* @} */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_data.c new file mode 100755 index 0000000000..1cd5f0c773 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_data.c @@ -0,0 +1,190 @@ +/*! + ***************************************************************************** + * @file: adi_rtc_data.c + * @brief: rtc device data file + * @version: $Revision: 34933 $ + * @date: $Date: 2016-06-28 07:11:25 -0400 (Tue, 28 Jun 2016) $ + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/*! \cond PRIVATE */ +#ifndef ADI_RTC_DATA_C_ +#define ADI_RTC_DATA_C_ + +#include +#include "adi_rtc_def.h" + +static ADI_RTC_DEVICE_INFO aRTCDeviceInfo[ADI_RTC_NUM_INSTANCE] = +{ + { + (ADI_RTC_TypeDef *)pADI_RTC0,RTC0_EVT_IRQn, NULL + }, + { + (ADI_RTC_TypeDef *)pADI_RTC1,RTC1_EVT_IRQn,NULL, + } +}; + + +static ADI_RTC_CONFIG aRTCConfig[ADI_RTC_NUM_INSTANCE] = +{ + { + /* CR0 */ + RTC0_CFG_ENABLE_ALARM << BITP_RTC_CR0_ALMEN | + RTC0_CFG_ENABLE_ALARM_INTERRUPT << BITP_RTC_CR0_ALMINTEN | + RTC0_CFG_ENABLE_TRIM << BITP_RTC_CR0_TRMEN | + RTC0_CFG_ENABLE_PENDERROR_INTERRUPT << BITP_RTC_CR0_WPNDERRINTEN | + RTC0_CFG_ENABLE_WSYNC_INTERRUPT << BITP_RTC_CR0_WSYNCINTEN | + RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT << BITP_RTC_CR0_WPNDINTEN , + /* CR1 */ + 0, + /* CNT0 */ + RTC0_CFG_COUNT_VALUE_0, + /* CNT1 */ + RTC0_CFG_COUNT_VALUE_1, + /* ALM0 */ + RTC0_CFG_ALARM_VALUE_0, + /* ALM1 */ + RTC0_CFG_ALARM_VALUE_1, + /* ALM2 */ + 0, + /* TRIM */ + RTC0_CFG_POW2_TRIM_INTERVAL << BITP_RTC_TRM_IVL2EXPMIN | + RTC0_CFG_TRIM_INTERVAL << BITP_RTC_TRM_IVL | + RTC0_CFG_TRIM_OPERATION << BITP_RTC_TRM_ADD | + RTC0_CFG_TRIM_VALUE << BITP_RTC_TRM_VALUE, + 0, /* CR2IC */ + 0, /* CR3SS */ + 0, /* CR4SS */ + 0, /* SSMSK */ + 0, /* SS1 */ + 0, /* CR5SSS */ + 0, /* CR6SSS */ + 0, /* CR7SSS */ + 0, /* GPMUX0 */ + 0 /* GPMUX1 */ + + }, + /* RTC-1 */ + { + /* CR0 */ + RTC1_CFG_ENABLE_ALARM << BITP_RTC_CR0_ALMEN | + RTC1_CFG_ENABLE_ALARM_INTERRUPT << BITP_RTC_CR0_ALMINTEN | + RTC1_CFG_ENABLE_TRIM << BITP_RTC_CR0_TRMEN | + RTC1_CFG_ENABLE_MOD60_ALARM << BITP_RTC_CR0_MOD60ALMEN | + RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD << BITP_RTC_CR0_MOD60ALM | + RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT << BITP_RTC_CR0_MOD60ALMINTEN | + RTC1_CFG_ENABLE_ISO_INTERRUPT << BITP_RTC_CR0_ISOINTEN | + RTC1_CFG_ENABLE_PENDERROR_INTERRUPT << BITP_RTC_CR0_WPNDERRINTEN | + RTC1_CFG_ENABLE_WSYNC_INTERRUPT << BITP_RTC_CR0_WSYNCINTEN | + RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT << BITP_RTC_CR0_WPNDINTEN , + /* CR1 */ + RTC1_CFG_ENABLE_COUNT_INTERRUPT << BITP_RTC_CR1_CNTINTEN | + RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT << BITP_RTC_CR1_PSINTEN | + RTC1_CFG_ENABLE_TRIM_INTERRUPT << BITP_RTC_CR1_TRMINTEN | + RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT << BITP_RTC_CR1_CNTROLLINTEN | + RTC1_CFG_PRESCALE << BITP_RTC_CR1_PRESCALE2EXP | + RTC1_CFG_CNT_ROLLLOVER_INTERRUPT << BITP_RTC_CR1_CNTMOD60ROLLINTEN , + /* CNT0 */ + RTC1_CFG_COUNT_VALUE_0, + /* CNT1 */ + RTC1_CFG_COUNT_VALUE_1, + + /* ALM[123] */ + RTC1_CFG_ALARM_VALUE_0, + RTC1_CFG_ALARM_VALUE_1, + RTC1_CFG_ALARM_VALUE_2, + + /* TRIM */ + RTC1_CFG_POW2_TRIM_INTERVAL << BITP_RTC_TRM_IVL2EXPMIN | + RTC1_CFG_TRIM_INTERVAL << BITP_RTC_TRM_IVL | + RTC1_CFG_TRIM_OPERATION << BITP_RTC_TRM_ADD | + RTC1_CFG_TRIM_VALUE << BITP_RTC_TRM_VALUE, + + /* CR2IC */ + RTC1_CFG_IC0_ENABLE << BITP_RTC_CR2IC_IC0EN | + RTC1_CFG_IC2_ENABLE << BITP_RTC_CR2IC_IC2EN | + RTC1_CFG_IC3_ENABLE << BITP_RTC_CR2IC_IC3EN | + RTC1_CFG_IC4_ENABLE << BITP_RTC_CR2IC_IC4EN | + RTC1_CFG_IC0_INT_ENABLE << BITP_RTC_CR2IC_IC0IRQEN | + RTC1_CFG_IC0_INT_ENABLE << BITP_RTC_CR2IC_IC2IRQEN | + RTC1_CFG_IC0_INT_ENABLE << BITP_RTC_CR2IC_IC3IRQEN | + RTC1_CFG_IC0_INT_ENABLE << BITP_RTC_CR2IC_IC4IRQEN | + RTC1_CFG_IC0_EDGE_POLARITY << BITP_RTC_CR2IC_IC0LH | + RTC1_CFG_IC2_EDGE_POLARITY << BITP_RTC_CR2IC_IC2LH | + RTC1_CFG_IC3_EDGE_POLARITY << BITP_RTC_CR2IC_IC3LH | + RTC1_CFG_IC4_EDGE_POLARITY << BITP_RTC_CR2IC_IC4LH | + RTC1_CFG_IC_OVER_WRITE_ENABLE << BITP_RTC_CR2IC_ICOWUSEN, + + /* CR3SS */ + RTC1_CFG_SS1_ENABLE << BITP_RTC_CR3SS_SS1EN | + RTC1_CFG_SS2_ENABLE << BITP_RTC_CR3SS_SS2EN | + RTC1_CFG_SS3_ENABLE << BITP_RTC_CR3SS_SS3EN | + RTC1_CFG_SS4_ENABLE << BITP_RTC_CR3SS_SS4EN | + RTC1_CFG_SS1_INT_ENABLE << BITP_RTC_CR3SS_SS1IRQEN | + RTC1_CFG_SS2_INT_ENABLE << BITP_RTC_CR3SS_SS2IRQEN | + RTC1_CFG_SS3_INT_ENABLE << BITP_RTC_CR3SS_SS3IRQEN | + RTC1_CFG_SS4_INT_ENABLE << BITP_RTC_CR3SS_SS4IRQEN, + + /* CR4SS */ + RTC1_CFG_SS1_MASK_ENABLE << BITP_RTC_CR4SS_SS1MSKEN | + RTC1_CFG_SS2_MASK_ENABLE << BITP_RTC_CR4SS_SS2MSKEN | + RTC1_CFG_SS3_MASK_ENABLE << BITP_RTC_CR4SS_SS3MSKEN | + RTC1_CFG_SS4_MASK_ENABLE << BITP_RTC_CR4SS_SS4MSKEN | + RTC1_CFG_SS1_AUTO_RELOADING_ENABLE << BITP_RTC_CR4SS_SS1ARLEN, + + /* SSMSK */ + RTC1_CFG_SS1_MASK_VALUE, + + /* SS1 */ + RTC1_CFG_SS1_AUTO_RELOAD_VALUE, + + 0, /* CR5SSS */ /* TODO: Add the following to the static configuration macros */ + 0, /* CR6SSS */ + 0, /* CR7SSS */ + 0x4688, /* GPMUX0 */ + 0x01F5, /* GPMUX1 */ + + } + +}; + +#endif +/*! \endcond */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_def.h new file mode 100755 index 0000000000..4b5afa44ef --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_def.h @@ -0,0 +1,163 @@ +/*! + ***************************************************************************** + * @file: adi_rtc_def.h + * @brief: RTC def file + * @version: $Revision: 33205 $ + * @date: $Date: 2016-01-11 05:46:07 -0500 (Mon, 11 Jan 2016) $ + *----------------------------------------------------------------------------- + * + * Copyright (c) 2010-2016 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL + * PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef ADI_RTC_DEF_H__ +#define ADI_RTC_DEF_H__ + +/*! \cond PRIVATE */ +#define ADI_RTC_NUM_INSTANCE 2u + + + +#define ADI_RTC_INT_ENA_MASK_CR0 0XF804u + +#define ADI_RTC_INT_ENA_MASK_CR1 0X1Fu + +#define ADI_RTC_INT_ENA_MASK_CR2IC 0xF41C +#define ADI_RTC_INT_ENA_MASK_CR3SS 0x1FFE +#define ADI_RTC_INT_ENA_MASK_CR4SS 0x0E0E +#define ADI_RTC_INT_ENA_MASK_CR5SSS 0x0FFF + +#define ADI_RTC_INT_SOURCE_MASK_SR0 0x007Eu +#define ADI_RTC_INT_SOURCE_MASK_SR2 0x001Fu + +#define ADI_RTC_WRITE_STATUS_MASK 0XCF8u +#define ADI_RTC_SR2_IRQ_STATUS_MASK 0X1Fu +#define ADI_RTC_SR3_IRQ_STATUS_MASK 0X1FFFu + + + +#define ADI_RTC_TRIM_MASK (BITM_RTC_TRM_VALUE | BITM_RTC_TRM_ADD|BITM_RTC_TRM_IVL | BITM_RTC_TRM_IVL2EXPMIN ) + +#if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1) + /* pause on pending writes to CR to avoid data loss */ + +#ifdef __ICCARM__ +/* +* Pm154 (rule 19.10): in the definition of a function-like macro, each instance +* of a parameter shall be enclosed in parentheses +* Parameter use without parentheses needed for struct field name in register access macro. +*/ +#pragma diag_suppress=Pm154 +#endif /* __ICCARM__ */ + +#define PEND_BEFORE_WRITE(reg,mask) while((pDevice->pRTCRegs->reg&(mask))!=0u)\ + {\ + } + +#define SYNC_AFTER_WRITE(reg,mask) while((pDevice->pRTCRegs->reg&(mask))==0u)\ + {\ + } + +#ifdef __ICCARM__ +#pragma diag_default=Pm154 +#endif /* __ICCARM__ */ + +#else + /* pause on pending writes to CR to avoid data loss */ +#define PEND_BEFORE_WRITE(reg,mask) +#define SYNC_AFTER_WRITE(reg,mask) +#endif + +/* + * The following is used for static configuration + */ +typedef struct +{ + uint16_t CR0; /*!< CR0 16 bit control register-0 value */ + uint16_t CR1; /*!< CR1 16 bit control register-1 value */ + uint16_t CNT0; /*!< CNT0 16 bit count register value */ + uint16_t CNT1; /*!< CNT1 16 bit count register value */ + + uint16_t ALM0; /*!< ALM0 16 bit integer part of alarm value */ + uint16_t ALM1; /*!< ALM1 16 bit integer part of alarm value */ + uint16_t ALM2; /*!< ALM2 16 bit integer part of alarm value */ + uint16_t TRIM; /*!< 16 bit trim register value */ + uint16_t CR2IC; /*!< CR2IC 16 bit control (which controls the input capture ) register-2 value */ + uint16_t CR3SS; /*!< CR3SS 16 bit control ( Controls enabling sensor strobe /IRQ etc )register-3 value */ + uint16_t CR4SS; /*!< CR4SS 16 bit control ( controls Auto reload and mask for sensor strobe ) register-4 value */ + uint16_t SSMSK; /*!< OCMSK Mask register for sensor strobe channel */ + uint16_t SS1; /*!< 16 bit Auto reload value */ + + uint16_t CR5SSS; /*!< Configure Sensor Strobe Channel GPIO Sampling Register */ + uint16_t CR6SSS; /*!< Configure Sensor Strobe Channel GPIO Sampling Register */ + uint16_t CR7SSS; /*!< Configure Sensor Strobe Channel GPIO Sampling Register */ + uint16_t GPMUX0; /*!< Control register for selecting a GPIO (pin) as data to be sampled by a Sensor Strobe channel */ + uint16_t GPMUX1; /*!< Control register for selecting a GPIO (pin) as data to be sampled by a Sensor Strobe channel */ +}ADI_RTC_CONFIG; + +/* Device information structure */ +typedef struct _ADI_RTC_DEVICE_INFO +{ + volatile ADI_RTC_TypeDef *pRTCRegs; /* Base address of the SPORT registers */ + const IRQn_Type eIRQn; /* IRQn */ + ADI_RTC_HANDLE hDevice; /* RTC handle */ +}ADI_RTC_DEVICE_INFO; + +/*! RTC driver instance data */ +typedef struct _ADI_RTC_DEVICE +{ + volatile ADI_RTC_TypeDef *pRTCRegs; /* Pointer to RTC Memory Mapped Registers */ + + ADI_CALLBACK pfCallback; /* Function pointer for callback function. */ + + void *pCBParam; /* Parameter to callback function. */ + IRQn_Type eIRQn; /* IRQn */ + uint32_t cbWatch; + ADI_RTC_DEVICE_INFO *pDeviceInfo; /* Parameter to callback function. */ + +} ADI_RTC_DEVICE; + + +static void rtc_init(ADI_RTC_DEVICE *pDevice,ADI_RTC_CONFIG *pConfig); + +#ifdef ADI_DEBUG +static ADI_RTC_RESULT ValidateHandle( ADI_RTC_DEVICE *pInDevice); +#endif +/*! \endcond */ +#endif /* ADI_RTC_DEF_H__ */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map.h new file mode 100755 index 0000000000..7224c14faa --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map.h @@ -0,0 +1,71 @@ +/*! + ***************************************************************************** + @file: adi_rtos_map.h + @brief: RTOS API mapping file. + This is the main RTOS mapping header file which will include other + RTOS mapping files based on the RTOS selection. + + The purpose of RTOS mapping file is for mapping the abstracted + RTOS macros to the RTOS API calls based on the chosen RTOS. + + NOTE: This file is intended to be used by only the drivers. Not at + the application level. + + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ +#ifndef ADI_RTOS_MAP_H +#define ADI_RTOS_MAP_H + +#include + +#if (ADI_CFG_RTOS == ADI_CFG_RTOS_MICRIUM_III) + +#include "rtos_map/adi_rtos_map_ucos_iii.h" + +#elif (ADI_CFG_RTOS == ADI_CFG_RTOS_FREERTOS) + +#include "rtos_map/adi_rtos_map_freertos.h" + +#else + +#include "rtos_map/adi_rtos_map_noos.h" + +#endif /* ADI_CFG_RTOS_MICRIUM_III */ + +#endif /* ADI_RTOS_MAP_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_freertos.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_freertos.h new file mode 100755 index 0000000000..97cbcaeeb7 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_freertos.h @@ -0,0 +1,144 @@ +/*! + ***************************************************************************** + @file: adi_rtos_map_freertos.h + @brief: FreeRTOS RTOS API mapping file. + + This file maps the RTOS macros to FreeRTOS APIs + + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ + +#ifndef ADI_RTOS_MAP_FREERTOS_H +#define ADI_RTOS_MAP_FREERTOS_H + +/* If building a c file */ +#if defined(__STDC__) + +#include +#include "semphr.h" + +extern BaseType_t xHigherPriorityTaskWoken; + +/*! Macro that declares the semaphore type that the drivers use. + The macro should be used within the device data structure. + It should not be used to declare the semaphore as a global variable. */ +#define SEM_VAR_DECLR \ + StaticQueue_t hSemaphore; + +/*! Memory required for semaphore in terms bytes. This size is used to compute + the total memory required for the operation of the driver. FreeRtos does not + require semaphore memory to be passed by application. But memory is required + to store the handle. */ +#define ADI_SEM_SIZE (sizeof(StaticQueue_t)) + +/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */ + + /*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */ +#define SEM_CREATE(DEV, name, error) \ + do { \ + xSemaphoreCreateBinaryStatic(&(DEV)->hSemaphore); \ + } while (0) + +/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */ +#define SEM_DELETE(DEV, error) \ + do { \ + vSemaphoreDelete (&(DEV)->hSemaphore); \ + } while (0) + + +/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle.*/ +#define SEM_PEND(DEV, error) \ + do { \ + if(xSemaphoreTake (&(DEV)->hSemaphore, portMAX_DELAY) != pdTRUE) \ + return((error)); \ + } while (0) + +/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */ +/* Note that priority inversion is supported */ +#define SEM_POST(DEV) \ + do { \ + /* Assume that a higher priority task can be schedule in */ \ + BaseType_t xHigherPriorityTaskWoken = pdTRUE; \ + xSemaphoreGiveFromISR(&(DEV)->hSemaphore, &xHigherPriorityTaskWoken); \ + } while (0) + +/*! Defines a local variable where interrupt status register value is stored. + This macro should be used within a function in which critical section + macros ADI_ENTER_CRITICAL_REGION and ADI_EXIT_CRITICAL_REGION are + used. + + @sa ADI_ENTER_CRITICAL_REGION() + @sa ADI_EXIT_CRITICAL_REGION() + */ +#define ADI_INT_STATUS_ALLOC() + +/*! Macro to enter critical section. To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_ENTER_CRITICAL_REGION() vPortEnterCritical() + +/*! Macro to exit critical section.To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_EXIT_CRITICAL_REGION() vPortExitCritical() + +/*! Code that uCOS requires to be run in the beginning of an interrupt handler. + @sa ISR_EPILOG() +*/ +#define ISR_PROLOG() + +/*! Code that uCOS requires to be run in the end of an interrupt handler. + @sa ISR_PROLOG() +*/ +#define ISR_EPILOG() portYIELD() + +#endif /* __STDC__ */ + +#define PENDSV_HANDLER xPortPendSVHandler +#define SYSTICK_HANDLER xPortSysTickHandler +#define SVC_HANDLER vPortSVCHandler + + +#endif /* ADI_RTOS_MAP_FREERTOS_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_noos.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_noos.h new file mode 100755 index 0000000000..e508f1ccf5 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_noos.h @@ -0,0 +1,180 @@ +/*! + ***************************************************************************** + @file: adi_rtos_map_noos.h + @brief: No OS API mapping file. + + This file maps the RTOS macros to No OS APIs + + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ + +#ifndef ADI_RTOS_MAP_NOOS_H +#define ADI_RTOS_MAP_NOOS_H + +/* If building a c file */ +#if defined(__STDC__) + +#include +#include +#include +#include + +/*! Defines a local variable where interrupt status register value is stored. + This macro should be used within a function in which critical section + macros ADI_ENTER_CRITICAL_REGION and ADI_EXIT_CRITICAL_REGION are + used. + + @sa ADI_ENTER_CRITICAL_REGION() + @sa ADI_EXIT_CRITICAL_REGION() + */ +#define ADI_INT_STATUS_ALLOC() uint32_t IntStatus = 0u + +/*! Macro to enter critical section. To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_ENTER_CRITICAL_REGION() \ +do { \ + IntStatus = __get_PRIMASK(); \ + __disable_irq(); \ +} while (0) + + +/*! Macro to exit critical section.To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_EXIT_CRITICAL_REGION() \ +do { \ + __set_PRIMASK(IntStatus); \ +} while (0) + + +/*! Memory required for semaphore in terms bytes. This size is used to compute + the total memory required for the operation of the driver. */ +#define ADI_SEM_SIZE (sizeof(uint32_t)) + +/*! Code that uCOS requires to be run in the beginning of an interrupt handler. + @sa ISR_EPILOG() +*/ +#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1u) +#define ISR_PROLOG() adi_cyclecount_start(); +#else +#define ISR_PROLOG() +#endif + + +/*! Code that uCOS requires to be run in the end of an interrupt handler. + @sa ISR_PROLOG() +*/ +#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1u) +#define ISR_EPILOG() adi_cyclecount_stop(); +#else +#define ISR_EPILOG() +#endif + +#if (ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT == 1) + +/*! Macro that declares the semaphore type that the drivers use. + The macro should be used within the device data structure. + It should not be used to declare the semaphore as a global variable. */ +#define SEM_VAR_DECLR volatile uint32_t nLowPowerExitFlag; + +/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */ +#define SEM_CREATE(DEV, name, error) \ + (DEV)->nLowPowerExitFlag = 0u + +/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */ +#define SEM_DELETE(DEV, error) do { } while(0) + +/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_PEND(DEV, error) \ + do { \ + ADI_PWR_RESULT eResult; \ + eResult = adi_pwr_EnterLowPowerMode(ADI_PWR_MODE_FLEXI, &(DEV)->nLowPowerExitFlag, 0u); \ + if(eResult != ADI_PWR_SUCCESS) { return ((error)); } \ + } while(0) + + +/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_POST(DEV) \ + do { \ + adi_pwr_ExitLowPowerMode(&(DEV)->nLowPowerExitFlag); \ + } while(0) + + +#else /* ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT == 0 */ + +/*! Macro that declares the semaphore type that the drivers use. + The macro should be used within the device data structure. + It should not be used to declare the semaphore as a global variable. */ +#define SEM_VAR_DECLR volatile uint32_t nSemCount; + +/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */ +#define SEM_CREATE(DEV, name, error) \ + (DEV)->nSemCount = 0 + +/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */ +#define SEM_DELETE(DEV, error) do { } while(0) + +/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_PEND(DEV, error) \ + while ((DEV)->nSemCount == 0u) {} \ + (DEV)->nSemCount-- + +/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_POST(DEV) { \ + (DEV)->nSemCount++; \ +} + +#endif /* ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT */ + +#endif /* __STDC__ */ + +#define PENDSV_HANDLER PendSV_Handler +#define SYSTICK_HANDLER SysTick_Handler +#define SVC_HANDLER SVC_Handler + + +#endif /* ADI_RTOS_MAP_NOOS_H */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_ii.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_ii.h new file mode 100755 index 0000000000..20ee60f610 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_ii.h @@ -0,0 +1,149 @@ +/*! + ***************************************************************************** + @file: adi_rtos_map_ucos_ii.h + @brief: uCOS-III RTOS API mapping file. + + This file maps the RTOS macros to uCOS-II APIs + + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ + +#ifndef ADI_RTOS_MAP_UCOS_II_H +#define ADI_RTOS_MAP_UCOS_II_H + +/* If building a c file */ +#if defined(__STDC__) + +#include +#include +#include +#include + +/*! Macro that declares the semaphore type that the drivers use. + The macro should be used within the device data structure. + It should not be used to declare the semaphore as a global variable. */ +#define SEM_VAR_DECLR \ + OS_EVENT *hSemaphore; + +/*! Memory size required for semaphore in terms bytes. This size is used to compute + the total memory required for the operation of the driver. In case of uCOS-II + there is no requirement to provide the memory to create the semaphore, but + memory is required to store the handle */ +#define ADI_SEM_SIZE sizeof(OS_EVENT) + +/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */ +#define SEM_CREATE(DEV, name, error) \ + do { \ + ((DEV)->hSemaphore) = OSSemCreate(0u); \ + if((DEV)->hSemaphore == NULL) {return((error));} \ + } while (0) + +/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */ +#define SEM_DELETE(DEV, error) \ + do { \ + INT8U os_error; \ + OSSemDel( (DEV)->hSemaphore, OS_DEL_NO_PEND, &os_error ); \ + if(os_error != OS_ERR_NONE) {return((error));} \ + } while (0) + + +/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_PEND(DEV, error) \ + do { \ + INT8U os_error; \ + OSSemPend ((DEV)->hSemaphore, 0u, &os_error); \ + if(os_error != OS_ERR_NONE) {return((error));} \ + } while (0) + +/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_POST(DEV) \ + do { \ + OSSemPost((DEV)->hSemaphore ); \ + } while (0) + +/*! Defines a local variable where interrupt status register value is stored. + This macro should be used within a function in which critical section + macros ADI_ENTER_CRITICAL_REGION and ADI_EXIT_CRITICAL_REGION are + used. + + @sa ADI_ENTER_CRITICAL_REGION() + @sa ADI_EXIT_CRITICAL_REGION() + */ +#define ADI_INT_STATUS_ALLOC() CPU_SR_ALLOC() + +/*! Macro to enter critical section. To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_ENTER_CRITICAL_REGION() CPU_CRITICAL_ENTER() + +/*! Macro to exit critical section.To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_EXIT_CRITICAL_REGION() CPU_CRITICAL_EXIT() + +/*! Code that uCOS requires to be run in the beginning of an interrupt handler. + @sa ISR_EPILOG() +*/ +#define ISR_PROLOG() \ + do { \ + CPU_SR_ALLOC(); \ + CPU_CRITICAL_ENTER(); \ + OSIntEnter(); \ + CPU_CRITICAL_EXIT(); \ + } while (0); + +/*! Code that uCOS requires to be run in the end of an interrupt handler. + @sa ISR_PROLOG() +*/ +#define ISR_EPILOG() OSIntExit(); + +#endif /* __STDC__ */ + +#define PENDSV_HANDLER OS_CPU_PendSVHandler +#define SYSTICK_HANDLER OS_CPU_SysTickHandler +#define SVC_HANDLER SVC_Handler + + +#endif /* ADI_RTOS_MAP_UCOS_II_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_iii.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_iii.h new file mode 100755 index 0000000000..e055b7010f --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_iii.h @@ -0,0 +1,167 @@ +/*! + ***************************************************************************** + @file: adi_rtos_map_ucos_iii.h + @brief: uCOS-III RTOS API mapping file. + + This file maps the RTOS macros to uCOS-III APIs + + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ + +#ifndef ADI_RTOS_MAP_UCOS_III_H +#define ADI_RTOS_MAP_UCOS_III_H + +/* If building a c file */ +#if defined(__STDC__) + +#include +#include +#include +#include + +/*! Macro that declares the semaphore type that the drivers use. + The macro should be used within the device data structure. + It should not be used to declare the semaphore as a global variable. */ +#define SEM_VAR_DECLR \ + OS_SEM Semaphore; + +/*! Memory required for semaphore in terms bytes. This size is used to compute + the total memory required for the operation of the driver. uCOS-III requires + semaphore memory to be passed by application. But there is no memory required + to store the handle. For every semaphore related call the same memory pointer + that was used during create will be passed. */ +#define ADI_SEM_SIZE (sizeof(OS_SEM)) + +/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */ +#define SEM_CREATE(DEV, name, error) \ + do { \ + OS_ERR os_error; \ + OSSemCreate(&((DEV)->Semaphore), name ,0u, &os_error); \ + if(OS_ERR_NONE != os_error) {return((error));} \ + } while (0) + +/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */ +#define SEM_DELETE(DEV, error) \ + do { \ + OS_ERR os_error; \ + OSSemDel( &((DEV)->Semaphore), OS_OPT_DEL_NO_PEND, &os_error ); \ + if(OS_ERR_NONE != os_error) {return((error));} \ + } while (0) + + +/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle.*/ +#define SEM_PEND(DEV, error) \ + do { \ + OS_ERR os_error; \ + OSSemPend (&((DEV)->Semaphore), 0u, OS_OPT_PEND_BLOCKING , NULL, &os_error); \ + if(OS_ERR_NONE != os_error) {return((error));} \ + } while (0) + +/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_POST(DEV) \ + do { \ + OS_ERR os_error; \ + OSSemPost(&((DEV)->Semaphore), OS_OPT_POST_1, &os_error); \ + } while (0) + + +/*! Defines a local variable where interrupt status register value is stored. + This macro should be used within a function in which critical section + macros ADI_ENTER_CRITICAL_REGION and ADI_EXIT_CRITICAL_REGION are + used. + + @sa ADI_ENTER_CRITICAL_REGION() + @sa ADI_EXIT_CRITICAL_REGION() +*/ +#define ADI_INT_STATUS_ALLOC() CPU_SR_ALLOC() + +/*! Macro to enter critical section. To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_ENTER_CRITICAL_REGION() CPU_CRITICAL_ENTER() + +/*! Macro to exit critical section.To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_EXIT_CRITICAL_REGION() CPU_CRITICAL_EXIT() + + +/*! Code that uCOS requires to be run in the beginning of an interrupt handler. + @sa ISR_EPILOG() +*/ +#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1) +#define ADI_RTOS_UCOS_III_CYCLECOUNT_START adi_cyclecount_start(); +#define ADI_RTOS_UCOS_III_CYCLECOUNT_STOP adi_cyclecount_stop(); +#else +#define ADI_RTOS_UCOS_III_CYCLECOUNT_START +#define ADI_RTOS_UCOS_III_CYCLECOUNT_STOP +#endif + +#define ISR_PROLOG() \ + do { \ + CPU_SR_ALLOC(); \ + CPU_CRITICAL_ENTER(); \ + OSIntEnter(); \ + CPU_CRITICAL_EXIT(); \ + ADI_RTOS_UCOS_III_CYCLECOUNT_START \ + } while (0); + +/*! Code that uCOS requires to be run in the end of an interrupt handler. + @sa ISR_PROLOG() +*/ +#define ISR_EPILOG() \ + do { \ + ADI_RTOS_UCOS_III_CYCLECOUNT_STOP \ + OSIntExit(); \ + } while (0); \ + +#endif /* __STDC__ */ + +#define PENDSV_HANDLER OS_CPU_PendSVHandler +#define SYSTICK_HANDLER OS_CPU_SysTickHandler +#define SVC_HANDLER SVC_Handler + + +#endif /* ADI_RTOS_MAP_UCOS_III_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi.c new file mode 100755 index 0000000000..7c8c0e3022 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi.c @@ -0,0 +1,1892 @@ +/*! ***************************************************************************** + * @file: adi_spi.c + * @brief: SPI device driver global file. + * @details: This a global file which includes a specific file based on the processor family. + * This included file will be containing SPI device driver functions. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/** @addtogroup SPI_Driver SPI Driver + * @{ + * @brief Serial Peripheral Interface (SPI) Driver + * @details The SPI driver manages all instances of the SPI peripheral. + * @note The application must include drivers/spi/adi_spi.h to use this driver. + * @note This driver requires the DMA driver.The application must include the DMA driver sources to avoid link errors. + * @note Also note that the SPI will be configured by default to operate in Master mode. + * @note To configure the driver to operate in slave mode the static configuration file adi_spi_config.h must be modified. + * @note Specifically, the macro ADI_SPIx_MASTER_MODE must be set to '0' to indicate that slave mode functionality is needed. + * @note Since there are three SPI devices there are three macros, ADI_SPI0_MASTER_MODE, ADI_SPI1_MASTER_MODE and ADI_SPI2_MASTER_MODE to control the functionality of each SPI controller. + * @note Each instance of the SPI operates independently from all other instances. + * @note + * @note When operating the SPI at high bit rates the application may need to modify the IRQ interrupt mode. The API adi_spi_SetIrqmode() can be used for this. + * @note At higher bit rates the ISR could mask a TX/RX interrupt. Specifically, it is possible that while servicing a TX/RX event another TX/RX event could occur. It is + * @note possible, therefore, that when the ISR clears the interrupt status it will not only be clearing the current TX event but the next TX/RX event as well. The result + * @note could that a final TX/RX event will not be processed. One way to work around this would be to set IRQMODE such that TX/RX events will occur only after N bytes + * @note are in the FIFO. This will only work for short bursts less than the size of the FIFO. For larger transfer DMA mode, which will not have any of these issues, should be used. + * @note Finally, if interrupt mode is required at hight bit rates note that the SPI ISR has been designed with minimal cycle count as the highest priority. + * @note The ISR could certainly be modified to re-examine the FIFO before existing at the cost of additional cycles. + */ + + /*! \cond PRIVATE */ +#include +/*! \endcond */ + +#include /* for 'NULL" definition */ +#include + +#include +#include +#include +#include +#include +#include "adi_spi_config.h" +#include + + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Relying on pointer arithmetic for buffer handling. +* +* Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type +* Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors +* +* Pm151 (rule 17.4): array indexing shall only be applied to objects of array type +* Pm123 (rule 18.5): there shall be no definition of objects in a header file +* +* Pm50: (MISRA C 2004 rule 14.3) a null statement shall only occur on a line by itself, and shall not have any other text on the same line +* Some Macros, such as ISR_PROLOGUE, may not have any expansion resulting in just the terminating ';' +* +*Pm140: (MISRA C 2004 rule 11.3) a cast should not be performed between a pointer type and an integral type +* MMR addresses are defined as simple constants. Accessing the MMR requires casting to a pointer type +* +* Pm031: (MISRA C 2004 rule 12.7) bitwise operations shall not be performed on signed integer types +* MMR macros are beyond the control of the driver. +* +*/ +#pragma diag_suppress=Pm050,Pm073,Pm088,Pm123,Pm143,Pm152,Pm140,Pm031 + +#endif /* __ICCARM__ */ + +#include "adi_spi_data.c" + +/*! \cond PRIVATE */ + +/* handle checker for debug mode */ +#define ADI_SPI_VALIDATE_HANDLE(h) ((spi_device_info[0].hDevice != (h)) && (spi_device_info[1].hDevice != (h)) && (spi_device_info[2].hDevice != (h))) + +/*! \endcond */ + +/* + * Local prototypes + */ +static void common_SPI_Int_Handler (ADI_SPI_DEV_DATA_TYPE* pDD); +static void StartTransaction (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr); +static void TxDmaErrorCallback (void *pCBParam, uint32_t Event, void *pArg); +static void RxDmaErrorCallback (void *pCBParam, uint32_t Event, void *pArg); + +/* ISR forward declarations */ +/*! \cond PRIVATE */ +void SPI0_Int_Handler(void); +void SPI1_Int_Handler(void); +void SPI2_Int_Handler(void); +void DMA_SPI0_TX_Int_Handler(void); +void DMA_SPI0_RX_Int_Handler(void); +void DMA_SPI1_TX_Int_Handler(void); +void DMA_SPI1_RX_Int_Handler(void); +void DMA_SPIH_TX_Int_Handler(void); +void DMA_SPIH_RX_Int_Handler(void); +/*! \endcond */ + +/* + ////////////////////////////////////////////////////////////////////////////// + ////////////////////// API IMPLEMENTATIONS /////////////////////////////// + ////////////////////////////////////////////////////////////////////////////// +*/ + +/*! + * @brief Initialize and allocate an SPI device for use in Master Mode. + * + * @param[in] nDeviceNum Zero-based device index designating which device to initialize. + *\n + * @param [in] pDevMemory Pointer to a buffer of size ADI_SPI_MEMORY_SIZE + *\n required by the driver for the operation of specified SPI device. + * + * @param [in] nMemorySize Size of the buffer to which "pMemory" points. + * + * @param[out] phDevice The caller's device handle pointer for storing the initialized device instance data pointer. + * + * @return Status + * - #ADI_SPI_INVALID_DEVICE_NUM [D] Invalid device index. + * - #ADI_SPI_INVALID_PARAM [D] Invalid parameter. + * - #ADI_SPI_SEMAPHORE_FAILED Semaphore creation failed. + * - #ADI_SPI_DMA_REG_FAILED Failed to register DMA callbacks with common DMA service. + * - #ADI_SPI_IN_USE SPI is already open and in use. + * - #ADI_SPI_SUCCESS Call completed successfully. + * +* @note : No other SPI APIs may be called until the device open function is called. + *\n Initialize an SPI device using internal default configuration settings and allocate the + *\n device for use.The returned device handle is required to be passed to all subsequent + *\n calls to convey which device instance to operate on. + *\n The contents of phDevice will be set to NULL upon failure. Device is opened in Master mode. + *\n + * @sa adi_spi_SetMasterMode() + * @sa adi_spi_Close(). + */ +ADI_SPI_RESULT adi_spi_Open(uint32_t nDeviceNum, + void *pDevMemory, + uint32_t nMemorySize, + ADI_SPI_HANDLE* const phDevice) +{ + +#ifdef ADI_DEBUG + + if (nDeviceNum >= ADI_SPI_NUM_INSTANCES) + { + return ADI_SPI_INVALID_DEVICE_NUM; + } + + if (nMemorySize != sizeof(struct __ADI_SPI_DEV_DATA_TYPE)) + { + return ADI_SPI_INVALID_PARAM; + } + + if( spi_device_info[nDeviceNum].hDevice != NULL ) + { + return ADI_SPI_IN_USE; + } + +#endif + + ADI_SPI_HANDLE hDevice = pDevMemory; + + /* + * Link the two data structures together. + * + * ADI_SPI_DEVICE_INFO <==> ADI_SPI_HANDLE + * + * Clear the ADI_SPI_HANDLE memory. This also sets all bool + * structure members to false so we do not need to waste cycles + * setting these explicitly (e.g. hDevice->bDMA = false) + * + * Other fields, such as callback related fields, are also zeroed + * and therefore properly initialized. + */ + + spi_device_info[nDeviceNum].hDevice = (ADI_SPI_DEV_DATA_TYPE *)pDevMemory; + memset(pDevMemory,0,nMemorySize); + hDevice->pDevInfo = &spi_device_info[nDeviceNum]; + + + /* + * Although the ADI_SPI_DEVICE_INFO struct has the address of the SPI registers + * for this instance, copying it to the ADI_SPI_HANDLE struct will minimize + * the runtime footprint and cycle count when accessing the SPI registers + */ + hDevice->pSpi = spi_device_info[nDeviceNum].pSpiRegs; + + SEM_CREATE(hDevice, "SPI_SEM", ADI_SPI_SEMAPHORE_FAILED); + + /* Static Configuration */ + /* Initialize the device based on the given configuration parameters */ + ADI_SPI_CFG_TYPE const* pSPICfg = &gSPICfg[nDeviceNum]; + hDevice->pSpi->CTL = pSPICfg->SPI_CTL; + hDevice->pSpi->DIV = pSPICfg->SPI_DIV; + + /* write the device data pointer into the caller's handle */ + *phDevice = hDevice; + hDevice->pSpi->CTL |= BITM_SPI_CTL_SPIEN; + + /* Make sure the DMA controller and its SRAM based descriptors are initialized */ + adi_dma_Init(); + + /* Setup the DMA TX callback */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback((DMA_CHANn_TypeDef) hDevice->pDevInfo->dmaTxChannelNumber, TxDmaErrorCallback, (void *) hDevice)) + { + return ADI_SPI_DMA_REG_FAILED; + } + + /* Setup the DMA RX callback */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback((DMA_CHANn_TypeDef) hDevice->pDevInfo->dmaRxChannelNumber, RxDmaErrorCallback, (void *) hDevice)) + { + return ADI_SPI_DMA_REG_FAILED; + } + + return ADI_SPI_SUCCESS; +} + + +/*! + * @brief Uninitialize and deallocate an SPI device. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Uninitialize and release an allocated SPI device,and memory associated with it for other use. + * + * @sa adi_spi_Open(). + */ +ADI_SPI_RESULT adi_spi_Close (ADI_SPI_HANDLE const hDevice) +{ + + ADI_SPI_RESULT result = ADI_SPI_SUCCESS; +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + + + /* disable Interrupt */ + NVIC_DisableIRQ(hDevice->pDevInfo->eIRQn); + + + /* destroy semaphore */ + SEM_DELETE((ADI_SPI_HANDLE) hDevice,ADI_SPI_SEMAPHORE_FAILED); + + /* invalidate initialization state */ + hDevice->pDevInfo->hDevice = NULL; + return result; +} + + +/*! + * @brief Register or unregister the callback. + * + * @param [in] hDevice Device handle obtained from adi_spi_Open(). + * @param [in] pfCallback Pointer to the callback function. Can be passed as NULL to unregister the + *\n previously registered callback. + * @param [in] pCBParam Callback parameter which will be passed back to the application when the + *\n callback is called. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + */ +ADI_SPI_RESULT adi_spi_RegisterCallback (ADI_SPI_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void *const pCBParam ) +{ +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + /* Save the application provided callback and callback parameters */ + hDevice->pfCallback = pfCallback; + hDevice->pCBParam = pCBParam; + + return ADI_SPI_SUCCESS; +} + +/*! + * @brief Set the IRQ mode. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] nMode IRQ mode value to set. +* - true Set continuous transfer mode. +* - false Clear continuous transfer mode. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * These bits configure when the Tx/Rx interrupts occur in a transfer. + * For DMA Rxtransfer, these bits should be 0. + * Value values are 0-7 + * Tx interrupt occurs when (nMode+1) byte(s) has been transferred. + * Rx interrupt occurs when (nMode+1) or more bytes have been received into the FIFO. + * + * @note The application will have to carefully manage IRQMODE relative to a transaction's buffer size. + * @note Specifically, the application must ensure that the last byte causes an interrupt else the + * @note transaction will not terminate. As explained in the SPI driver overview, this functionality + * @note is typically needed when operating in interrupt mode with a high SPI bit rate (typically issues + * @note are seen at SPI clock rates of 4MHz or greater). The max clock rate will vary depending on the application. + * @note The max clock rate is a function of the SPI ISR cycle count plus any other delay that might be caused + * @note by other parts of the system. Finally, please note that while sustaining interrupt mode SPI transaction + * @note at high bit rates will work buffers that are the size of the SPI FIFO or less, transactions that are + * @note larger that the size of the FIFO may run into issues associated with masked/lost interrupts. If this + * @note does prove to be an issue for an applicatoon then the SPI ISR could be modified to examine the FIFO + * @note status on a continuous basis in the ISR (as opposed to examining the FIFO status just once at the start + * @note of the ISR). However, adding this functionality to the ISR will increase the ISR cycle count and footprint. + * + */ +ADI_SPI_RESULT adi_spi_SetIrqmode (ADI_SPI_CONST_HANDLE const hDevice, const uint8_t nMode) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + + uint16_t ien = hDevice->pSpi->IEN; + ien = ien & (uint16_t)~BITM_SPI_IEN_IRQMODE; + ien = ien | (nMode & BITM_SPI_IEN_IRQMODE); + hDevice->pSpi->IEN = ien; + + return ADI_SPI_SUCCESS; +} + + +/*! + * @brief Set the continuous transfer mode. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] bFlag Flag to manage SPI continuous transfer mode. +* - true Set continuous transfer mode. +* - false Clear continuous transfer mode. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Setting this mode causes the SPI controller to drive the Chip Select signal continuously until the transaction + * is complete. Clearing it causes Chip Select to cycle between bytes. + * + * + */ +ADI_SPI_RESULT adi_spi_SetContinuousMode (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + + if (true == bFlag) { + hDevice->pSpi->CTL |= (BITM_SPI_CTL_CON); + } else { + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CON; + } + + return ADI_SPI_SUCCESS; +} + +/*! + * @brief Set the internal loopback mode. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] bFlag Flag to manage internal SPI loopback mode. + * - true Set internal loopback mode. + * - false Clear internal loopback mode. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Set or clear the internal SPI loopback mode. Primarily used for testing. + * + */ +ADI_SPI_RESULT adi_spi_SetLoopback (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + + if (true == bFlag) { + hDevice->pSpi->CTL |= (BITM_SPI_CTL_LOOPBACK); + } else { + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_LOOPBACK; + } + + return ADI_SPI_SUCCESS; +} + +/*! + * @brief Set SPI Master-Mode operation. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] bFlag Flag to select either Master-Mode or Slave-Mode operation. + *\n - true Enable Master-Mode. Default. + *\n - false Enable Slave-Mode. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Controls SPI Master/Slave mode of operation, set for Master-Mode, clear for Slave-Mode. + * + */ +ADI_SPI_RESULT adi_spi_SetMasterMode (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + if (true == bFlag) { /* hardware default */ + hDevice->pSpi->CTL |= (ADI_SPI_MASTERCON_INITIALIZER); + } else { + hDevice->pSpi->CNT = 0u; + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_MASEN; + hDevice->pSpi->CTL |= (ADI_SPI_SLAVECON_INITIALIZER); + } + ADI_EXIT_CRITICAL_REGION(); + return ADI_SPI_SUCCESS; +} + + +/*! + * @brief Set the SPI receive FIFO overflow mode. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] bFlag Flag to manage receive FIFO overflow behaviour. + *\n - true Discard old data on receive FIFO overflow. + *\n - false Discard new data on receive FIFO overflow. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Controls what to do with excess incoming data when the receive FIFO becomes full. + * Either the new data or the old data is discarded. Set the receive FIFO overflow mode + * to replace data in the RX register (top of receive FIFO) with the incoming new data. + * Clear it to discard incoming new data and preserve old unread data. + + * + */ +ADI_SPI_RESULT adi_spi_SetReceiveOverflow (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + + if (true == bFlag) { + hDevice->pSpi->CTL |= (BITM_SPI_CTL_RXOF); + } else { + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_RXOF; + } + + return ADI_SPI_SUCCESS; +} + + +/*! + * @brief Set the SPI transmit FIFO underflow mode. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] bFlag Flag to manage transmit FIFO underflow behaviour. + *\n - true Send zeroes on transmit FIFO underflow. + *\n - false Resend last data on transmit FIFO underflow. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + *\n Controls what to transmit when lacking valid data because the transmit FIFO is empty. + *\n Either zeros or the last valid data are transmitted. Set transmit FIFO underflow mode to send zeros. + *\n Clear it to resend the last transmitted data. + * + */ +ADI_SPI_RESULT adi_spi_SetTransmitUnderflow (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } +#endif + + if (true == bFlag) { + hDevice->pSpi->CTL |= (BITM_SPI_CTL_ZEN); + } else { + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_ZEN; + } + + return ADI_SPI_SUCCESS; +} + + + + + + +/*! + * @brief Set the SPI serial clock frequency. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open() + * @param[in] Hertz Target frequency (in Hz) for SPI bitrate. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_INVALID_PARAM Specified frequency is out of range. + * - #ADI_SPI_BAD_SYS_CLOCK Unable to obtain PCLK which is needed to calculate the new bit rate. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Compute and set the internal SPI clock rate divider register to produce + *\n the desired serial clock frequency. Resulting frequency is subject to arithmetic rounding errors. + *\n Use #adi_spi_GetBitrate() to obtain the exact frequency produced, including rounding errors. + * + * @sa adi_spi_GetBitrate(). + */ +ADI_SPI_RESULT adi_spi_SetBitrate (ADI_SPI_CONST_HANDLE const hDevice, const uint32_t Hertz) +{ + uint32_t incoming_clock; + uint16_t Div; + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } +#endif + + if( adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &incoming_clock) != ADI_PWR_SUCCESS) + { + return ADI_SPI_INVALID_HANDLE; + } + + /* requested rate needs to be 2x or less than incoming clock */ + if ((2U * Hertz) > incoming_clock) + { + return ADI_SPI_BAD_SYS_CLOCK; + } + + /* compute the SPI divider value */ + Div = (uint16_t) ((incoming_clock / Hertz) >> 1U) - 1U; /* '>>1' is really a divide by 2 */ + + /* range check that computed divider fits */ + if (Div != (Div & BITM_SPI_DIV_VALUE)) + { + return ADI_SPI_INVALID_PARAM; + } + + /* store it in core */ + hDevice->pSpi->DIV = Div; + + return ADI_SPI_SUCCESS; +} + + +/*! + * @brief Get the SPI serial clock frequency. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open() + * \n + * @param[out] pnBitrate Pointer to the location where Bitrate need to be written. + * + * @return + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Get the current serial clock frequency. The returned value is exact but + *\n may not exactly match the value set with #adi_spi_SetBitrate() due to + *\n computational round-off errors resulting from fixed register size and + *\n finite-precision arithmetic. + * + * @sa adi_spi_SetBitrate(). + */ +ADI_SPI_RESULT adi_spi_GetBitrate (ADI_SPI_CONST_HANDLE const hDevice, uint32_t* const pnBitrate) +{ + uint32_t incoming_clock; + ADI_PWR_RESULT ePwrResult; + uint32_t Div; + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } +#endif + Div = hDevice->pSpi->DIV; /* assumes this is always a right-justified value */ + + ePwrResult = adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &incoming_clock); + if(ePwrResult != ADI_PWR_SUCCESS) + { + *pnBitrate= 0u; + return(ADI_SPI_FAILURE); + } + *pnBitrate= (incoming_clock / (Div + 1U)) >> 1U; /* '>>1' is divide by 2 */ + return(ADI_SPI_SUCCESS); + +} + + +/*! + * @brief Set the chip select. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] eChipSelect An enum value representing the requested Chip Select. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Sets the desired chip select to use for activating an external slave device. + * + * @note Chip select \a ADI_SPI0_CSn is reserved for SPI device 0 (SPI0) internal chip select line + * dedicated for communications with the UHF device. + * + */ +ADI_SPI_RESULT adi_spi_SetChipSelect (ADI_SPI_HANDLE const hDevice, const ADI_SPI_CHIP_SELECT eChipSelect) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } +#endif + + hDevice->ChipSelect = eChipSelect; + + return ADI_SPI_SUCCESS; +} + +/*! + * @brief Submit data buffers for SPI Master-Mode transaction in "Blocking mode".This function + *\n returns only after the data transfer is complete + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pXfr Pointer to transfer data struct #ADI_SPI_TRANSCEIVER. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_BUFFER_NOT_SUBMITTED [D] Failed to submit the buffer. + * - #ADI_SPI_INVALID_POINTER [D] Invalid data pointer detected (NULL). + * - #ADI_SPI_INVALID_PARAM [D] Invalid size parameter detected (0). + * - #ADI_SPI_SUCCESS Call completed successfully. + * + *\n + *\n Request a non-blocking mode transmit and receive of multiple data bytes + *\n over the SPI serial channel. + *\n Buffer allocations are made by the calling code (the application). + *\n + *\n The transmit buffer is sent and the receive buffer is written according + *\n to the size and increment information contained by the \a pXft transfer + *\n data structure parameter. + *\n + *\n + * @sa adi_spi_MasterSubmitBuffer(). + * @sa ADI_SPI_TRANSCEIVER + */ +ADI_SPI_RESULT adi_spi_MasterReadWrite (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr) +{ + ADI_SPI_RESULT eResult; + hDevice->bBlockingMode = true; + eResult = adi_spi_MasterSubmitBuffer(hDevice,pXfr); + hDevice->bBlockingMode = false; + if( (eResult == ADI_SPI_SUCCESS) && (hDevice->HWErrors != 0u)) + { + eResult = ADI_SPI_HW_ERROR_OCCURRED; + } + return(eResult); +} + +/*! + * @brief Submit data buffers for SPI Master-Mode transaction. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pXfr Pointer to transfer data struct. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_IN_USE [D] DMA transaction already under way. + * - #ADI_SPI_INVALID_POINTER [D] Invalid data pointer detected (NULL). + * - #ADI_SPI_INVALID_PARAM [D] Invalid size parameter detected (0). + * - #ADI_SPI_SUCCESS Call completed successfully. + * + *\n Request a blocking mode transmit and receive of multiple data bytes + *\n over the SPI serial channel. + *\n Buffer allocations are made by the calling code (the application). + *\n + *\n The transmit buffer is sent and the receive buffer is written according + *\n to the size and increment information contained by the \a pXft transfer + *\n data structure parameter. + * + * + * @sa adi_spi_MasterReadWrite(). + * @sa adi_spi_isBufferAvailable() + * @sa ADI_SPI_TRANSCEIVER + */ + +ADI_SPI_RESULT adi_spi_MasterSubmitBuffer (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr) +{ + ADI_SPI_RESULT result = ADI_SPI_SUCCESS; + volatile uint16_t nStatus; + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } + + if ((NULL == pXfr->pTransmitter) && (NULL == pXfr->pReceiver)) + { + return ADI_SPI_INVALID_POINTER; + } + + if( (pXfr->bRD_CTL == true) && (pXfr->TransmitterBytes > 16u)) + { + return ADI_SPI_INVALID_PARAM; + } + +#endif /* ADI_DEBUG */ + + /* Initialize the transaction. 'hDevice' must hold the transaction values as pXfr is owned by the application */ + hDevice->pTxBuffer = pXfr->pTransmitter; + hDevice->pRxBuffer = pXfr->pReceiver; + hDevice->TxRemaining = pXfr->TransmitterBytes; + hDevice->RxRemaining = pXfr->ReceiverBytes; + hDevice->TxIncrement = (uint8_t)pXfr->nTxIncrement; + hDevice->RxIncrement = (uint8_t)pXfr->nRxIncrement; + hDevice->bDmaMode = pXfr->bDMA; + hDevice->bRdCtlMode = pXfr->bRD_CTL; + hDevice->bTransferComplete = false; + hDevice->HWErrors = ADI_SPI_HW_ERROR_NONE; + + + /* + * + * TIM + * If set: initiate transfer with write to SPI_TX register + * If clear: initiate transfer with a read from SPI_RX register + * + * RFLUSH + * Clear this bit to ensure that incoming data is ignored + * + * TFLUSH + * Clear this not to ensure that transmitted data is not a zero (if SPI_CTL.ZEN is set) or last transmitted byte + * + */ + + + hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_TIM | BITM_SPI_CTL_RFLUSH | BITM_SPI_CTL_TFLUSH); + + /* + * If in DMA mode then make sure XFRDONE interrupt is not set. DMA mode will generate three interrupts + * TX DMA + * RX DMA + * XFRDONE + * + * There is a race condition between XFRDONE and DMA interrupts. They are on different clocks. + * + * SPI XfrDone is counted on SPI clock (SCL) edge, which is a fixed timing related to SPI bit protocol. + * But the DMA works upon system clock (HCLK) and it could finish on various timing upon SCL/HCLK ratio. + * And bus bandwidth (e.g., DMA hold off until processor frees up the bus). So SPI RX DMA done interrupt + * could be issued earlier or later than SPI XferDone interrupt. + * + */ + if( hDevice->bDmaMode==true ) { + /* The race condition has been between RX and XFRDONE. If there are no bytes to receive then */ + /* do not clear XFRDONE */ + if( hDevice->RxRemaining != 0u) { + hDevice->pSpi->IEN &= (uint16_t)~(BITM_SPI_IEN_XFRDONE); + } else { + hDevice->pSpi->IEN |= (BITM_SPI_IEN_XFRDONE); + } + + } else { + + /* In interrupt mode always enable XFRDONE */ + uint16_t activeInterrupts = BITM_SPI_IEN_XFRDONE; + /* Enable underflow on;y if sending bytes */ + if( hDevice->TxRemaining ) { + activeInterrupts |= BITM_SPI_IEN_TXUNDR; + } + /* Enable overflow only if receiving bytes */ + if( hDevice->RxRemaining ) { + activeInterrupts |= BITM_SPI_IEN_RXOVR; + } + + hDevice->pSpi->IEN |= activeInterrupts; + + /* + * In interrupt mode, when there is nothing to receive, need to initiate a transaction + * on an TX write only. Initiating on an RX read will start the transaction, but just for + * a single byte (and we're not sure why this is true) + */ + + if( hDevice->RxRemaining == 0u) { + hDevice->pSpi->CTL |= ( BITM_SPI_CTL_TIM ); + } + + } + + + /* STAT bits are cleared by writing a '1' to them. Clear any residual status*/ + nStatus = hDevice->pSpi->STAT; + hDevice->pSpi->STAT = nStatus; + + /* Make sure we are in master mode */ + hDevice->pSpi->CTL |= ( BITM_SPI_CTL_MASEN); + + /* Set ChipSelect */ + hDevice->pSpi->CS_CTL = hDevice->ChipSelect; + + StartTransaction(hDevice, pXfr); + + + /* block if required */ + if (hDevice->bBlockingMode == true) + { + SEM_PEND(hDevice,ADI_SPI_PEND_FAILED); + } + + return result; +} + +/*********************************************************************************************************/ +/* */ +/* SPI DRIVER Master Mode transaction start */ +/* */ +/*********************************************************************************************************/ + +static void StartTransaction(ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr) +{ + /* Transaction completion is determined by the number of bytes to be received */ + uint16_t nCount; + + /* Effectively flush the FIFOs before the start of the next transaction */ + hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH); + hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH); + + /* Disable any prior notion of DMA */ + hDevice->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + + + /* + * If the transaction is DMA based then set up the DMA descriptors for this transaction + */ + + uint16_t dmaFlags = 0u; + + if( hDevice->bDmaMode == true) + { + dmaFlags = BITM_SPI_DMA_EN; + + uint16_t sz = pXfr->TransmitterBytes; + if( sz ) + { + uint16_t TxChanNum = hDevice->pDevInfo->dmaTxChannelNumber; + + /* Enable the interrupt for the given DMA */ + NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaTxIrqNumber)); + + /* Disables source address decrement for TX channel */ + pADI_DMA0->SRCADDR_CLR = 1U << TxChanNum; + + /* Enable the channel */ + pADI_DMA0->EN_SET = 1U << TxChanNum; + + /* Enables SPI peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1U << TxChanNum; + + /* Set the primary as the current DMA descriptor */ + pADI_DMA0->ALT_CLR = 1U << TxChanNum; + + /* fill in the DMA RAM descriptors */ + if( (sz & 1U) != 0u ) + { + /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */ + /* The SPI_CNT register will hold the "real" transfer count */ + sz++; + } + + pPrimaryCCD[TxChanNum].DMASRCEND = (uint32_t)(pXfr->pTransmitter + (sz - 2U)); + + pPrimaryCCD[TxChanNum].DMADSTEND = (uint32_t)&hDevice->pSpi->TX; + + pPrimaryCCD[TxChanNum].DMACDC = ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) | + (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_SRC_INC) | + (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) | + ((sz/2U -1U)<< DMA_BITP_CTL_N_MINUS_1) | + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL); + + dmaFlags |= (BITM_SPI_DMA_TXEN); + } + + sz = pXfr->ReceiverBytes; + if( sz ) + { + + uint16_t RxChanNum = hDevice->pDevInfo->dmaRxChannelNumber; + NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaRxIrqNumber)); + + /* Disables destination address decrement for RX channel */ + pADI_DMA0->DSTADDR_CLR = 1U << RxChanNum; + + /* Enable the channel */ + pADI_DMA0->EN_SET = 1U << RxChanNum; + + /* Enables SPI peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1U << RxChanNum; + + /* Set the primary as the current DMA descriptor */ + pADI_DMA0->ALT_CLR = 1U << RxChanNum; + + if( (sz & 1U) != 0u ) + { + /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */ + /* The SPI_CNT register will hold the "real" transfer count */ + sz++; + } + + pPrimaryCCD[RxChanNum].DMASRCEND = (uint32_t)&hDevice->pSpi->RX; + + pPrimaryCCD[RxChanNum].DMADSTEND = (uint32_t)(pXfr->pReceiver + (sz - 2U)); + + pPrimaryCCD[RxChanNum].DMACDC = (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_DST_INC) | + (ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) | + (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) | + ((sz/2U -1U) << DMA_BITP_CTL_N_MINUS_1) | + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL); + + dmaFlags |= (BITM_SPI_DMA_RXEN ); + + } + } + + /* + * SPI CNT register + * Non Read Mode: Size of the entire transactions + * Read Mode: Size of the RX transaction + * + * RD_CTL.SZ + * Read Mode: Size of the TX transaction + */ + + hDevice->pSpi->RD_CTL = 0u; + if( hDevice->bRdCtlMode) + { + /* "Half Duplex Mode" */ + + /* The number of bytes to be transmitted */ + uint32_t nBytes = hDevice->TxRemaining - 1U; + + /* Enable RD_CTL and set the TX count for the half-duplex mode of operation */ + hDevice->pSpi->RD_CTL &= (uint16_t)~((uint16_t)(BITM_SPI_RD_CTL_TXBYTES << BITP_SPI_RD_CTL_TXBYTES)); + + hDevice->pSpi->RD_CTL |= (uint16_t)( (uint16_t)(nBytes << BITP_SPI_RD_CTL_TXBYTES) | + (uint16_t)(1 << BITP_SPI_RD_CTL_CMDEN)); + + /* RD_CTL requires continuous mode operation. */ + hDevice->pSpi->CTL |= (BITM_SPI_CTL_CON); + + /* CNT represent the number of bytes to receive */ + hDevice->pSpi->CNT = hDevice->RxRemaining; + + } + else + { + /* Full duplex mode of operation */ + if(hDevice->RxRemaining == 0u) + { + /* There is nothing to receive. Flush the RX FIFO and to ignore all incoming data */ + hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH); + } + else if(hDevice->TxRemaining == 0u) + { + /* If there is nothing to transmit then clear the TX FIFO */ + hDevice->pSpi->CTL |= (BITM_SPI_CTL_TFLUSH); + } + else + { + /* Misra compliance: All if/else chains should end with a final else clause */ + } + + /* Set CNT to MAX of RX/TX */ + + nCount = hDevice->RxRemaining > hDevice->TxRemaining ? hDevice->RxRemaining : hDevice->TxRemaining; + hDevice->pSpi->CNT = (uint16_t)nCount; + + } + + + if( hDevice->bDmaMode == false) + { + /* Make sure that the application passed in a TX Buffer */ + if( hDevice->pTxBuffer != NULL) + { + /* interrupt mode: Fill in the FIFO */ + nCount = 0u; + while((nCount < ADI_SPI_FIFO_SIZE) && (hDevice->TxRemaining != 0u)) + { + /* grab the lead byte */ + hDevice->pSpi->TX = *hDevice->pTxBuffer; + /* modify tx pointer and buffer count prior to interrupt */ + hDevice->pTxBuffer += hDevice->TxIncrement; + /* decrement the byte count */ + hDevice->TxRemaining--; + nCount++; + } + } + + } else { + + hDevice->pSpi->DMA |= dmaFlags; + } + + if((hDevice->pSpi->CTL & BITM_SPI_CTL_TIM) != BITM_SPI_CTL_TIM) + { + uint16_t byte ADI_UNUSED_ATTRIBUTE = hDevice->pSpi->RX; + } + + + NVIC_EnableIRQ(hDevice->pDevInfo->eIRQn); + + return; +} + +/*! + * @brief Block until the SPI transaction is complete. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + *\n + * @param[out] pHWErrors Pointer to hardware error return variable. + *\n + * @return Status + * - #ADI_SPI_SUCCESS Call completed successfully. + * - #ADI_SPI_SEMAPHORE_FAILED Semaphore Pend failed + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * + * @sa adi_spi_MasterSubmitBuffer(). + * @sa adi_spi_SlaveSubmitBuffer(). + */ +ADI_SPI_RESULT adi_spi_GetBuffer( + ADI_SPI_HANDLE const hDevice, + uint32_t * const pHWErrors + ) +{ +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + *pHWErrors = ADI_SPI_HW_ERROR_NONE; + return ADI_SPI_INVALID_HANDLE; + } +#endif + + SEM_PEND(hDevice,ADI_SPI_SEMAPHORE_FAILED); + *pHWErrors = hDevice->HWErrors; + return(ADI_SPI_SUCCESS); +} + +/*! + * @brief Get the SPI transaction completion status. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + *\n + * @param[out] bComplete Pointer to boolean variable that indicates + *\n - true DMA transmit sequence is complete. + *\n - false DMA transmit sequence is incomplete. + *\n + * @return Status + * - #ADI_SPI_SUCCESS Call completed successfully. + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * + * @sa adi_spi_MasterSubmitBuffer(). + * @sa adi_spi_SlaveSubmitBuffer(). + */ + +ADI_SPI_RESULT adi_spi_isBufferAvailable(ADI_SPI_CONST_HANDLE const hDevice, bool* const bComplete) +{ +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } +#endif + + *bComplete = hDevice->bTransferComplete; + return(ADI_SPI_SUCCESS); +} + +/*! + * @brief Submit data buffers for SPI Slave-Mode transaction. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pXfr Pointer to transfer data struct. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_IN_USE [D] DMA transaction already under way. + * - #ADI_SPI_INVALID_POINTER [D] Invalid data pointer detected (NULL). + * - #ADI_SPI_INVALID_PARAM [D] Invalid size parameter detected (0). + * - #ADI_SPI_SUCCESS Call completed successfully. + * + *\n Request a non-blocking transmit and receive of multiple data bytes + *\n over the SPI serial channel. Honours current blocking and DMA modes. + *\n Buffer allocations are made by the calling code (the application). + *\n + *\n The transmit buffer is sent and the receive buffer is written according + *\n to the size and increment information contained by the \a pXft transfer + *\n data structure parameter. + *\n + *\n The application must make a call to adi_spi_GetBuffer() to retrieve the buffer + *\n + *\n @note: + * + * @sa adi_spi_MasterReadWrite(). + * @sa adi_spi_EnableDmaMode(). + * @sa adi_spi_isBufferAvailable(). + * @sa adi_spi_GetBuffer(). + */ +ADI_SPI_RESULT adi_spi_SlaveSubmitBuffer (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr) +{ + volatile uint16_t ADI_UNUSED_ATTRIBUTE byte; + uint32_t nCount = 0u; + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } + if ((NULL == pXfr->pTransmitter) && (NULL == pXfr->pReceiver)) + { + return ADI_SPI_INVALID_POINTER; + } + + if ((0u == pXfr->pTransmitter) && (0u == pXfr->pReceiver) ) + { + return ADI_SPI_INVALID_PARAM; + } + /* Return error if the RX buffer is not null and count is equal to zero or vice versa.*/ + if (((pXfr->pReceiver != NULL) && (pXfr->ReceiverBytes == 0u)) || ((pXfr->pReceiver == NULL) && ((pXfr->ReceiverBytes > 0u)))) + { + return ADI_SPI_INVALID_PARAM; + } + + /* Return error if the Tx buffer is not null and count is equal to zero or vice versa.*/ + if (((pXfr->pTransmitter != NULL) && (pXfr->TransmitterBytes == 0u)) || ((pXfr->pTransmitter == NULL) && (pXfr->TransmitterBytes > 0u))) + { + return ADI_SPI_INVALID_PARAM; + } + + /* DMA count register is only 8 bits, so block size is limited to 255 */ + if ((pXfr->bDMA==true) && (pXfr->TransmitterBytes != 0u) &&(((uint32_t)pXfr->pTransmitter&0x1U) !=0u ) ) + { + return ADI_SPI_INVALID_PARAM; + } + +#endif /* ADI_DEBUG */ + + /* Effectively flush the FIFOs before the start of the next transaction */ + hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH); + hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH); + + /* Shut down any DMA enables that are still lingering from a prior transaction */ + hDevice->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + + hDevice->bTransferComplete = false; + hDevice->pTxBuffer = pXfr->pTransmitter; + hDevice->pRxBuffer = pXfr->pReceiver; + hDevice->TxRemaining = pXfr->TransmitterBytes; + hDevice->RxRemaining = pXfr->ReceiverBytes; + hDevice->TxIncrement = (uint8_t)pXfr->nTxIncrement; + hDevice->RxIncrement = (uint8_t)pXfr->nRxIncrement; + hDevice->pSpi->CNT = (uint16_t)nCount; + hDevice->bDmaMode = pXfr->bDMA; + hDevice->bRdCtlMode = pXfr->bRD_CTL; + hDevice->HWErrors = ADI_SPI_HW_ERROR_NONE; + + + /* Configure SPI. First step is to clear CTL bits that may have been set previously */ + hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_TIM | BITM_SPI_CTL_RFLUSH | BITM_SPI_CTL_TFLUSH | BITM_SPI_CTL_CON); + if( hDevice->TxRemaining == 0u ) + { + /* This will prevent TX underflow interrupts from occurring */ + hDevice->pSpi->CTL |= BITM_SPI_CTL_TFLUSH; + } + if( hDevice->RxRemaining == 0u ) + { + /* This will prevent data from entering RX. Also prevents overflow interrupts from occurring */ + hDevice->pSpi->CTL |= BITM_SPI_CTL_RFLUSH; + + /* If SPI_CTL.TIM is set, the Tx FIFO status causes the interrupt. */ + if( hDevice->bDmaMode != true) { + hDevice->pSpi->CTL |= BITM_SPI_CTL_TIM; + } + + } + + hDevice->pSpi->CNT = (uint16_t) hDevice->TxRemaining > hDevice->RxRemaining ? hDevice->TxRemaining : hDevice->RxRemaining; + + uint16_t nDMAFlags = 0u; + + if( hDevice->bDmaMode == true) + { + uint16_t sz = pXfr->TransmitterBytes; + if( sz ) + { + uint16_t TxChanNum = hDevice->pDevInfo->dmaTxChannelNumber; + + /* Enable the interrupt for the given DMA */ + NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaTxIrqNumber)); + + /* Disables source address decrement for TX channel */ + pADI_DMA0->SRCADDR_CLR = 1U << TxChanNum; + + /* Enable the channel */ + pADI_DMA0->EN_SET = 1U << TxChanNum; + + /* Enables SPI peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1U << TxChanNum; + + /* Set the primary as the current DMA descriptor */ + pADI_DMA0->ALT_CLR = 1U << TxChanNum; + + /* fill in the DMA RAM descriptors */ + if( (sz & 1U) != 0u ) + { + /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */ + /* The SPI_CNT register will hold the "real" transfer count */ + sz++; + } + + pPrimaryCCD[TxChanNum].DMASRCEND = (uint32_t)(pXfr->pTransmitter + (sz - 2U)); + + pPrimaryCCD[TxChanNum].DMADSTEND = (uint32_t)&hDevice->pSpi->TX; + + pPrimaryCCD[TxChanNum].DMACDC = ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) | + (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_SRC_INC) | + (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) | + ((sz/2U -1U)<< DMA_BITP_CTL_N_MINUS_1) | + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL); + + nDMAFlags |= (BITM_SPI_DMA_TXEN); + } + + sz = pXfr->ReceiverBytes; + if( sz ) + { + + uint16_t RxChanNum = hDevice->pDevInfo->dmaRxChannelNumber; + NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaRxIrqNumber)); + + /* Disables destination address decrement for RX channel */ + pADI_DMA0->DSTADDR_CLR = 1U << RxChanNum; + + /* Enable the channel */ + pADI_DMA0->EN_SET = 1U << RxChanNum; + + /* Enables SPI peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1U << RxChanNum; + + /* Set the primary as the current DMA descriptor */ + pADI_DMA0->ALT_CLR = 1U << RxChanNum; + + if( (sz & 1U) != 0u ) + { + /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */ + /* The SPI_CNT register will hold the "real" transfer count */ + sz++; + } + + pPrimaryCCD[RxChanNum].DMASRCEND = (uint32_t)&hDevice->pSpi->RX; + + pPrimaryCCD[RxChanNum].DMADSTEND = (uint32_t)(pXfr->pReceiver + (sz - 2U)); + + pPrimaryCCD[RxChanNum].DMACDC = (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_DST_INC) | + (ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) | + (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) | + ((sz/2U -1U) << DMA_BITP_CTL_N_MINUS_1) | + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL); + + nDMAFlags |= (BITM_SPI_DMA_RXEN ); + + } + } + + /* Make sure XFRDONE is shut down. This IEN has no affect in slave mode */ + hDevice->pSpi->IEN &= (uint16_t)~BITM_SPI_IEN_XFRDONE; + + if( hDevice->bDmaMode == false) { + /* Make sure we are not in continuous mode from a prior DMA transaction */ + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CON; + + + /* interrupt mode: Enable the UNDERFLOW and OVERFLOW interrupts */ + /* XFRDONE is invalid in slave mode */ + uint16_t activeInterrupts = 0u; + /* Enable underflow on;y if sending bytes */ + if( hDevice->TxRemaining ) { + activeInterrupts |= BITM_SPI_IEN_TXUNDR; + } + /* Enable overflow only if receiving bytes */ + if( hDevice->RxRemaining ) { + activeInterrupts |= BITM_SPI_IEN_RXOVR; + } + hDevice->pSpi->IEN |= activeInterrupts; + + /* interrupt mode: Fill in the FIFO and enable the TX by a dummy read. */ + while((nCount < ADI_SPI_FIFO_SIZE) && (hDevice->TxRemaining != 0u)) + { + /* grab the lead byte */ + hDevice->pSpi->TX = *hDevice->pTxBuffer; + /* modify tx pointer and buffer count prior to interrupt */ + hDevice->pTxBuffer += hDevice->TxIncrement; + /* decrement the byte count */ + hDevice->TxRemaining--; + nCount++; + } + } else { + + /* DMA mode. Enable the controller */ + hDevice->pSpi->DMA |= (uint16_t)(BITM_SPI_DMA_EN | nDMAFlags); + } + + if((hDevice->pSpi->CTL & BITM_SPI_CTL_TIM) != BITM_SPI_CTL_TIM) + { + byte = hDevice->pSpi->RX; + } + NVIC_EnableIRQ(hDevice->pDevInfo->eIRQn); + + if (hDevice->bBlockingMode == true) + { + SEM_PEND(hDevice,ADI_SPI_SEMAPHORE_FAILED); + } + + return ADI_SPI_SUCCESS; +} + + + +/*! + * @brief Submit data buffers for SPI Slave-Mode transaction in "Blocking mode".This function + *\n returns only after the data transfer is complete + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pXfr Pointer to transfer data struct #ADI_SPI_TRANSCEIVER. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_BUFFER_NOT_SUBMITTED [D] Failed to submit the buffer. + * - #ADI_SPI_INVALID_POINTER [D] Invalid data pointer detected (NULL). + * - #ADI_SPI_INVALID_PARAM [D] Invalid size parameter detected (0). + * - #ADI_SPI_SUCCESS Call completed successfully. + * + *\n + *\n Request a non-blocking mode transmit and receive of multiple data bytes + *\n over the SPI serial channel. + *\n Buffer allocations are made by the calling code (the application). + *\n + *\n The transmit buffer is sent and the receive buffer is written according + *\n to the size and increment information contained by the \a pXft transfer + *\n data structure parameter. + *\n + *\n + * @sa adi_spi_SlaveSubmitBuffer(). + * @sa ADI_SPI_TRANSCEIVER + */ +ADI_SPI_RESULT adi_spi_SlaveReadWrite (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr) +{ + ADI_SPI_RESULT eResult; + hDevice->bBlockingMode = true; + eResult = adi_spi_SlaveSubmitBuffer(hDevice,pXfr); + hDevice->bBlockingMode = false; + if( (eResult == ADI_SPI_SUCCESS) && (hDevice->HWErrors != 0u)) + { + eResult = ADI_SPI_HW_ERROR_OCCURRED; + } + return(eResult); +} + +/* + ***************************************************************************** + * SPI Internal Static Support Functions + *****************************************************************************/ + + + /*! \cond PRIVATE */ + + +/*----------------------------------------------------------------------------- + * + * SPI ISR + * + *----------------------------------------------------------------------------*/ + + + +static void common_SPI_Int_Handler (ADI_SPI_DEV_DATA_TYPE* pDD) +{ + + /* read status register - first thing */ + volatile uint16_t nFifoStatus = pDD->pSpi->FIFO_STAT; + uint16_t nErrorStatus = pDD->pSpi->STAT; + + uint16_t writableBytes; + uint16_t readableBytes; + + + + /* Trap overflow/underflow errors and terminate the current transaction if there is an error. */ + if( BITM_SPI_STAT_RXOVR == (BITM_SPI_STAT_RXOVR & nErrorStatus)) { + pDD->HWErrors |= (uint32_t)ADI_SPI_HW_ERROR_RX_OVERFLOW; + } else if( BITM_SPI_STAT_TXUNDR == (BITM_SPI_STAT_TXUNDR & nErrorStatus)) { + pDD->HWErrors |= (uint32_t)ADI_SPI_HW_ERROR_TX_UNDERFLOW; + } + else + { + + /* calculate number of bytes that can be written to tx fifo */ + writableBytes = ADI_SPI_FIFO_SIZE - ((BITM_SPI_FIFO_STAT_TX & nFifoStatus) >> BITP_SPI_FIFO_STAT_TX); + /* calculate number of bytes to read from rx fifo */ + readableBytes = ((BITM_SPI_FIFO_STAT_RX & nFifoStatus) >> BITP_SPI_FIFO_STAT_RX); + + /* fill tx fifo */ + while ((writableBytes != 0u) && (pDD->TxRemaining != 0u)) + { + pDD->pSpi->TX = *pDD->pTxBuffer; + pDD->pTxBuffer += pDD->TxIncrement; + pDD->TxRemaining--; + writableBytes--; + } + + /* + * Now focus on the RX FIFO but only if we are not in RD_CTL mode OR, if we + * are in RD_CTL mode, TX bytes are all transmitted + */ + + if( (pDD->bRdCtlMode==false) || (pDD->TxRemaining==0u) ) + { + /* empty rx fifo */ + while ((readableBytes != 0u) &&(pDD->RxRemaining != 0u)) + { + + *pDD->pRxBuffer = (uint8_t) pDD->pSpi->RX; + pDD->pRxBuffer += pDD->RxIncrement; + pDD->RxRemaining--; + readableBytes--; + } + } + } + + + /* Terminate the transaction and notify the caller + * 1) Master mode: If there are no more bytes to RX or TX and XFRDONE is set + * 2) Slave mode: If there are no more bytes to RX or TX (XFRDONE is invalid in slave mode) + * 3) If there was a HW error + */ + bool terminate = false; + if( (pDD->RxRemaining == 0u) && (pDD->TxRemaining == 0u)) + { + if( BITM_SPI_CTL_MASEN == (pDD->pSpi->CTL & BITM_SPI_CTL_MASEN )) + { + /* Master mode */ + if( BITM_SPI_STAT_XFRDONE == (pDD->pSpi->STAT & BITM_SPI_STAT_XFRDONE )) + { + /* Master mode XFRDONE */ + terminate = true; + } + } else { + /* Slave mode - we're all done here */ + terminate = true; + } + } + + if( terminate || (pDD->HWErrors != (uint32_t)ADI_SPI_HW_ERROR_NONE)) + { + + /* Clear possible interrupt sources: XFRDONE and underflow and overflow */ + pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR); + pDD->bTransferComplete = true; + NVIC_DisableIRQ(pDD->pDevInfo->eIRQn); + + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + + } + + /* All interrupts are cleared by a write of 1 to the status register bits (W1C) */ + pDD->pSpi->STAT = nErrorStatus; + +#if defined(ADI_CYCLECOUNT_SPI_ISR_ENABLED) && (ADI_CYCLECOUNT_SPI_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPI); +#endif + + + +} + + +/* Internal DMA Callback for receiving DMA faults from common DMA error handler. */ +static void RxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) { + + /* Recover the device handle. */ + ADI_SPI_HANDLE hDevice = (ADI_SPI_HANDLE) pCBParam; + + /* Save the DMA error. */ + switch (Event) { + case ADI_DMA_EVENT_ERR_BUS: + hDevice->HWErrors |= ADI_SPI_HW_ERROR_RX_CHAN_DMA_BUS_FAULT; + break; + case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR: + hDevice->HWErrors |= ADI_SPI_HW_ERROR_RX_CHAN_DMA_INVALID_DESCR; + break; + default: + hDevice->HWErrors |= ADI_SPI_HW_ERROR_RX_CHAN_DMA_UNKNOWN_ERROR; + break; + } +} + + +/* Internal DMA Callback for receiving DMA faults from common DMA error handler. */ +static void TxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) { + + /* Recover the device handle. */ + ADI_SPI_HANDLE hDevice = (ADI_SPI_HANDLE) pArg; + + /* Save the DMA error. */ + switch (Event) { + case ADI_DMA_EVENT_ERR_BUS: + hDevice->HWErrors |= ADI_SPI_HW_ERROR_TX_CHAN_DMA_BUS_FAULT; + break; + case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR: + hDevice->HWErrors |= ADI_SPI_HW_ERROR_TX_CHAN_DMA_INVALID_DESCR; + break; + default: + hDevice->HWErrors |= ADI_SPI_HW_ERROR_TX_CHAN_DMA_UNKNOWN_ERROR; + break; + } +} + + +/*! + * @brief SPI0 Interrupt Handler. + * + * @return void. + * + * Overrides default SPI0 interrupt handler. + */ +void SPI0_Int_Handler(void) { + ISR_PROLOG(); + common_SPI_Int_Handler(spi_device_info[0].hDevice ); + ISR_EPILOG(); +} + + +/*! + * @brief SPI1 Interrupt Handler. + * + * @return void. + * + * Overrides default SPI1 interrupt handler. + */ +void SPI1_Int_Handler(void) { + ISR_PROLOG(); + common_SPI_Int_Handler(spi_device_info[1].hDevice); + ISR_EPILOG(); +} + +/*! + * @brief SPI2 Interrupt Handler. + * + * @return void. + * + * Overrides default SPI2 interrupt handler. + */ +void SPI2_Int_Handler(void) { + ISR_PROLOG(); + common_SPI_Int_Handler(spi_device_info[2].hDevice ); + ISR_EPILOG(); +} + + +/* + ////////////////////////////////////////////////////////////////////////////// + ////////////////////////// DMA-RELATED /////////////////////////////////// + ////////////////////////////////////////////////////////////////////////////// +*/ + + +/* + * SPI DMA interrupt handlers + */ + + +#if defined(ADI_SPI0_MASTER_MODE) && (ADI_SPI0_MASTER_MODE==1u) +void DMA_SPI0_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice; + pDD->TxRemaining = 0u; + ISR_EPILOG(); +} + +/* Master mode DMA ISR */ +void DMA_SPI0_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice; + pDD->RxRemaining = 0u; + /* Disable DMA */ + pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + /* Master mode: Now allow the XFRDONE interrupt to occur. It's the SPI ISR that really ends the transaction */ + /* The slave mode is not affected by this setting */ + pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE; + ISR_EPILOG(); +} +#endif +#if defined(ADI_SPI0_MASTER_MODE) && (ADI_SPI0_MASTER_MODE==0u) +/* Slave mode DMA ISRs */ +void DMA_SPI0_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice; + pDD->TxRemaining = 0u; + if( pDD->RxRemaining == 0) + { + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + } + ISR_EPILOG(); +} +void DMA_SPI0_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice; + pDD->RxRemaining = 0u; + /* Disable DMA */ + pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR); + pDD->bTransferComplete = true; + NVIC_DisableIRQ(pDD->pDevInfo->eIRQn); + + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + ISR_EPILOG(); +} +#endif + + + + +#if defined(ADI_SPI1_MASTER_MODE) && (ADI_SPI1_MASTER_MODE==1u) +/* Master mode DMA ISR */ +void DMA_SPI1_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice; + pDD->TxRemaining = 0u; + ISR_EPILOG(); +} + +void DMA_SPI1_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice; + pDD->RxRemaining = 0u; + /* Disable DMA */ + pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + /* Master mode: Now allow the XFRDONE interrupt to occur. It's the SPI ISR that really ends the transaction */ + /* The slave mode is not affected by this setting */ + pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE; + ISR_EPILOG(); +} +#endif + + +#if defined(ADI_SPI1_MASTER_MODE) && (ADI_SPI1_MASTER_MODE==0u) +/* Slave mode DMA ISRs */ +void DMA_SPI1_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice; + pDD->TxRemaining = 0u; + if( pDD->RxRemaining == 0) + { + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + } + ISR_EPILOG(); +} + + +void DMA_SPI1_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice; + pDD->RxRemaining = 0u; + /* Disable DMA */ + pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR); + pDD->bTransferComplete = true; + NVIC_DisableIRQ(pDD->pDevInfo->eIRQn); + + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + ISR_EPILOG(); +} +#endif + + +#if defined(ADI_SPI2_MASTER_MODE) && (ADI_SPI2_MASTER_MODE==1u) +/* Master mode DMA ISR */ + +void DMA_SPIH_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice; + pDD->TxRemaining = 0u; + ISR_EPILOG(); +} + +void DMA_SPIH_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice; + pDD->RxRemaining = 0u; + /* Disable DMA */ + pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + /* Master mode: Now allow the XFRDONE interrupt to occur. It's the SPI ISR that really ends the transaction */ + /* The slave mode is not affected by this setting */ + pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE; + ISR_EPILOG(); +} +#endif +#if defined(ADI_SPI2_MASTER_MODE) && (ADI_SPI2_MASTER_MODE==0u) +/* Master mode DMA ISRs */ + +void DMA_SPIH_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice; + pDD->TxRemaining = 0u; + ISR_EPILOG(); + if( pDD->RxRemaining == 0) + { + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + } + ISR_EPILOG(); +} + +void DMA_SPIH_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice; + pDD->RxRemaining = 0u; + /* Disable DMA */ + pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR); + pDD->bTransferComplete = true; + NVIC_DisableIRQ(pDD->pDevInfo->eIRQn); + + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + ISR_EPILOG(); +} +#endif + + + + +/*! \endcond */ + + +/* @} */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_data.c new file mode 100755 index 0000000000..9d8f001a37 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_data.c @@ -0,0 +1,162 @@ +/* + ***************************************************************************** + * @file: adi_spi_data.c + * @brief: Data declaration for SPORT Device Driver + ***************************************************************************** + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef _ADI_SPI_DATA_C_ +#define _ADI_SPI_DATA_C_ + + /*! \cond PRIVATE */ + +#include "adi_spi_def.h" +#include "adi_spi_config.h" +#include + +/* Stores the information about the specific device */ +static ADI_SPI_DEVICE_INFO spi_device_info [ADI_SPI_NUM_INSTANCES]= +{ + { + DMA0_CH4_DONE_IRQn, + SPI0_TX_CHANn, + DMA0_CH5_DONE_IRQn, + SPI0_RX_CHANn, + (volatile ADI_SPI_TypeDef *)pADI_SPI0, + SPI0_EVT_IRQn, + NULL + }, + { + DMA0_CH6_DONE_IRQn, + SPI1_TX_CHANn, + DMA0_CH7_DONE_IRQn, + SPI1_RX_CHANn, + (volatile ADI_SPI_TypeDef *)pADI_SPI1, + SPI1_EVT_IRQn, + NULL + }, + + { + DMA0_CH0_DONE_IRQn, + SPI2_TX_CHANn, + DMA0_CH1_DONE_IRQn, + SPI2_RX_CHANn, + (volatile ADI_SPI_TypeDef *)pADI_SPI2, + SPI2_EVT_IRQn, + NULL + } +}; + +/* SPI Application configuration array */ +static const ADI_SPI_CFG_TYPE gSPICfg[ADI_SPI_NUM_INSTANCES] = +{ + /* Initialize SPI0 Instance configuration. */ + { + /**** SPI_CFG register configuration *** */ + (( ADI_SPI0_CFG_ENABLE << BITP_SPI_CTL_SPIEN ) | + ( ADI_SPI0_CFG_CLK_PHASE << BITP_SPI_CTL_CPHA ) | + ( ADI_SPI0_CFG_CLK_POLARITY << BITP_SPI_CTL_CPOL ) | + ( ADI_SPI0_CFG_WIRED_OR << BITP_SPI_CTL_WOM ) | + ( ADI_SPI0_CFG_LSB_MSB << BITP_SPI_CTL_LSB ) | + ( ADI_SPI0_CFG_TRANSFER_INITIATE << BITP_SPI_CTL_TIM ) | + ( ADI_SPI0_CFG_TX_UNDERFLOW << BITP_SPI_CTL_ZEN ) | + ( ADI_SPI0_CFG_RX_OVERFLOW << BITP_SPI_CTL_RXOF ) | + ( ADI_SPI0_CFG_MISO_ENABLE << BITP_SPI_CTL_OEN ) | + ( ADI_SPI0_CFG_LOOPBACK << BITP_SPI_CTL_LOOPBACK ) | + ( ADI_SPI0_CFG_CONTINUOUS << BITP_SPI_CTL_CON ) | + ( ADI_SPI0_CFG_RX_FLUSH << BITP_SPI_CTL_RFLUSH ) | + ( ADI_SPI0_CFG_TX_FLUSH << BITP_SPI_CTL_TFLUSH ) | + ( ADI_SPI0_CFG_CSERR_RESET << BITP_SPI_CTL_CSRST )), + + /**** SPI_DIV buad rate selection register *** */ + (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI0_CFG_BIT_RATE)) >>1u)-1u))\ + << BITP_SPI_DIV_VALUE ) + }, + /* Initialize SPI1 Instance configuration. */ + { + /**** SPI_CFG register configuration *** */ + (( ADI_SPI1_CFG_ENABLE << BITP_SPI_CTL_SPIEN ) | + ( ADI_SPI1_CFG_CLK_PHASE << BITP_SPI_CTL_CPHA ) | + ( ADI_SPI1_CFG_CLK_POLARITY << BITP_SPI_CTL_CPOL ) | + ( ADI_SPI1_CFG_WIRED_OR << BITP_SPI_CTL_WOM ) | + ( ADI_SPI1_CFG_LSB_MSB << BITP_SPI_CTL_LSB ) | + ( ADI_SPI1_CFG_TRANSFER_INITIATE << BITP_SPI_CTL_TIM ) | + ( ADI_SPI1_CFG_TX_UNDERFLOW << BITP_SPI_CTL_ZEN ) | + ( ADI_SPI1_CFG_RX_OVERFLOW << BITP_SPI_CTL_RXOF ) | + ( ADI_SPI1_CFG_MISO_ENABLE << BITP_SPI_CTL_OEN ) | + ( ADI_SPI1_CFG_LOOPBACK << BITP_SPI_CTL_LOOPBACK ) | + ( ADI_SPI1_CFG_CONTINUOUS << BITP_SPI_CTL_CON ) | + ( ADI_SPI1_CFG_RX_FLUSH << BITP_SPI_CTL_RFLUSH ) | + ( ADI_SPI1_CFG_TX_FLUSH << BITP_SPI_CTL_TFLUSH ) | + ( ADI_SPI1_CFG_CSERR_RESET << BITP_SPI_CTL_CSRST )), + + /**** SPI_DIV buad rate selection register *** */ + (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI1_CFG_BIT_RATE)) >>1u)-1u))\ + << BITP_SPI_DIV_VALUE ) + }, + /* Initialize SPI2 Instance configuration. */ + { + /**** SPI_CFG register configuration *** */ + (( ADI_SPI2_CFG_ENABLE << BITP_SPI_CTL_SPIEN ) | + ( ADI_SPI2_CFG_CLK_PHASE << BITP_SPI_CTL_CPHA ) | + ( ADI_SPI2_CFG_CLK_POLARITY << BITP_SPI_CTL_CPOL ) | + ( ADI_SPI2_CFG_WIRED_OR << BITP_SPI_CTL_WOM ) | + ( ADI_SPI2_CFG_LSB_MSB << BITP_SPI_CTL_LSB ) | + ( ADI_SPI2_CFG_TRANSFER_INITIATE << BITP_SPI_CTL_TIM ) | + ( ADI_SPI2_CFG_TX_UNDERFLOW << BITP_SPI_CTL_ZEN ) | + ( ADI_SPI2_CFG_RX_OVERFLOW << BITP_SPI_CTL_RXOF ) | + ( ADI_SPI2_CFG_MISO_ENABLE << BITP_SPI_CTL_OEN ) | + ( ADI_SPI2_CFG_LOOPBACK << BITP_SPI_CTL_LOOPBACK ) | + ( ADI_SPI2_CFG_CONTINUOUS << BITP_SPI_CTL_CON ) | + ( ADI_SPI2_CFG_RX_FLUSH << BITP_SPI_CTL_RFLUSH ) | + ( ADI_SPI2_CFG_TX_FLUSH << BITP_SPI_CTL_TFLUSH ) | + ( ADI_SPI2_CFG_CSERR_RESET << BITP_SPI_CTL_CSRST )), + + /**** SPI_DIV buad rate selection register *** */ + (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI2_CFG_BIT_RATE)) >>1u)-1u))\ + << BITP_SPI_DIV_VALUE ) + } +}; + +/*! \endcond */ + +#endif /* _ADI_SPI_DATA_C_ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_def.h new file mode 100755 index 0000000000..8cbbf1b8d7 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_def.h @@ -0,0 +1,148 @@ +/*! + ***************************************************************************** + * @file: adi_spi_def.h + * @brief: SPI Device Driver definition + ***************************************************************************** +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_SPI_DEF_H_ +#define ADI_SPI_DEF_H_ + + + +#include + +#define ADI_SPI_NUM_INSTANCES (3u) +#define ADI_SPI_FIFO_SIZE (8u) + + + /*! \cond PRIVATE */ + +/* + ***************************************************************************** + * SPI Bitrate Initializer. Sets a default serial clockrate for the SPI channel. + *****************************************************************************/ +/* #define ADI_SPI_BITRATE_INITIALIZER 4000000 // 4MHz default bitrate */ +#define ADI_SPI_BITRATE_INITIALIZER 250000u /* depends on processor */ + +/* + ***************************************************************************** + * SPI0/SPI1 Control Register Initializer. This macro configures default + * settings for the SPI configuration control register when operated in Master-mode. + *****************************************************************************/ +/* SPI master DMA mode control configuration */ +#define ADI_SPI_MASTERCON_INITIALIZER BITM_SPI_CTL_MASEN + +/* + ***************************************************************************** + * SPI0/SPI1 Control Register Initializer. This macro configures default + * settings for the SPI configuration control register when operated in Slave-mode. + *****************************************************************************/ + #define ADI_SPI_SLAVECON_INITIALIZER BITM_SPI_CTL_OEN \ + | BITM_SPI_CTL_ZEN \ + | BITM_SPI_CTL_SPIEN + +/* 16-bit DMA... (two-byte size and increment) */ +#define ADI_DMA_DATA_WIDTH ADI_DMA_WIDTH_2_BYTE /*!< DMA data attribute */ +#define ADI_DMA_DATA_INCREMENT ADI_DMA_INCR_HALFWORD /*!< DMA data attribute */ + + + +/*! + ***************************************************************************** + * SPI Configuration structure. + *****************************************************************************/ +typedef struct ADI_SPI_CONFIG +{ + uint16_t SPI_CTL; /*!< SPI_CTL register configuration. */ + uint16_t SPI_DIV; /*!< SPI_DIV register. */ +} ADI_SPI_CFG_TYPE; + +/*! SPI device information */ + +typedef struct __ADI_SPI_DEVICE_INFO +{ + const uint16_t dmaTxIrqNumber; /* DMA channel ID-Tx */ + const uint16_t dmaTxChannelNumber; /* Tx */ + const uint16_t dmaRxIrqNumber; /* DMA channel ID-Rx */ + const uint16_t dmaRxChannelNumber; /* DMA channel ID-Rx */ + volatile ADI_SPI_TypeDef *pSpiRegs; /* Base address of the SPI registers */ + const IRQn_Type eIRQn; /* IRQn */ + ADI_SPI_HANDLE hDevice; /* SPI handle */ +}ADI_SPI_DEVICE_INFO; + + +/*! \struct ADI_SPI_DEV_DATA_TYPE SPI Device instance data structure */ +typedef struct __ADI_SPI_DEV_DATA_TYPE +{ + + /* device attributes */ + volatile ADI_SPI_TypeDef *pSpi; /*!< track MMR device pointer */ + ADI_SPI_DEVICE_INFO *pDevInfo; + + /* Callback and Callback parameters */ + ADI_CALLBACK pfCallback; /*!< Callback address */ + void * pCBParam; /*!< Callback parameter */ + /* The last recorded SPI event */ + uint32_t HWErrors; /*!< HW transaction status */ + + uint8_t* pTxBuffer; /*!< Transmit Buffer */ + uint8_t* pRxBuffer; /*!< Receive Buffer */ + uint16_t TxRemaining; /*!< Transmit Count */ + uint16_t RxRemaining; /*!< Receive Count */ + uint8_t TxIncrement; /*!< Transmit Increment */ + uint8_t RxIncrement; /*!< Receive Increment */ + + volatile bool bTransferComplete; /*!< Transfer Complete Flag */ + + bool bDmaMode; /*!< DMA mode flag */ + bool bRdCtlMode; /* Use half duplex read control feature */ + bool bBlockingMode; /*!< blocking mode flag */ + ADI_SPI_CHIP_SELECT ChipSelect; /*!< track chip select */ + + SEM_VAR_DECLR +} ADI_SPI_DEV_DATA_TYPE; + + + +/*! \endcond */ + +#endif /* ADI_SPI_DEF_H__ */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport.c new file mode 100755 index 0000000000..5c352c2bc5 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport.c @@ -0,0 +1,1771 @@ +/*! **************************************************************************** + * @file: adi_sport.c + * @brief: SPORT (Serial Port) device driver source file. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/** @addtogroup SPORT_Driver SPORT Driver + * @{ + */ + +/*! \cond PRIVATE */ + +/*============= I N C L U D E S =============*/ + +#include +#include /* memset declaration */ + +#include +#include +#include +#include +#include "adi_sport_def.h" + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Needed for null expansion of ADI_INSTALL_HANDLER and others. +* +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Relying on pointer arithmetic for buffer handling. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +* +* Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type +* Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors + +*/ +#pragma diag_suppress=Pm026,Pm050,Pm073,Pm088,Pm123,Pm140,Pm143,Pm152,Pm153 +#endif /* __ICCARM__ */ + +/*============== D A T A ===============*/ + +#define SPORT0_A_REGS ((volatile ADI_SPORT_TypeDef*)REG_SPORT0_CTL_A) +#define SPORT0_B_REGS ((volatile ADI_SPORT_TypeDef*)REG_SPORT0_CTL_B) + +#define SPORT0_A_CFG { 0u, 0u, 0u, 0u, 0u } +#define SPORT0_B_CFG { 0u, 0u, 0u, 0u, 0u } + +#define DXS_FIFO_IS_FULL(STAT) (((STAT) & BITM_SPORT_STAT_A_DXS) == BITM_SPORT_STAT_A_DXS) +#define DXS_FIFO_IS_EMPTY(STAT) (((STAT) & BITM_SPORT_STAT_A_DXS) == 0u) + +static ADI_SPORT_DEVICE_INFO gSportDevInfo [ADI_SPORT_NUM_INSTANCES][ADI_SPORT_NUM_CHANNELS] = +{ + {/* registers configuration initial state DMA channel DMA IRQ SPORT IRQ handle */ + {SPORT0_A_REGS, SPORT0_A_CFG, ADI_SPORT_STATE_UNINITIALIZED, SPORT0A_CHANn, DMA0_CH2_DONE_IRQn, SPORT_A_EVT_IRQn, NULL}, + {SPORT0_B_REGS, SPORT0_B_CFG, ADI_SPORT_STATE_UNINITIALIZED, SPORT0B_CHANn, DMA0_CH3_DONE_IRQn, SPORT_B_EVT_IRQn, NULL}, + }, +}; + + +static const ADI_SPORT_CONFIG gSportCfg[ADI_SPORT_NUM_INSTANCES][ADI_SPORT_NUM_CHANNELS] = +{ + { /* configuration for SPORT 0 */ + /* Configuration for half-SPORT A */ + { /* SPORT_CTL register */ + ((ADI_CFG_SPORT0A_ENABLE_FSMUXSEL) << BITP_SPORT_CTL_A_FSMUXSEL) | + ((ADI_CFG_SPORT0A_ENABLE_CKMUXSEL) << BITP_SPORT_CTL_A_CKMUXSEL) | + ((ADI_CFG_SPORT0A_LSB_FIRST) << BITP_SPORT_CTL_A_LSBF) | + ((ADI_CFG_SPORT0A_SERIAL_WLEN - 1u) << BITP_SPORT_CTL_A_SLEN) | + ((ADI_CFG_SPORT0A_INTERNAL_CLK) << BITP_SPORT_CTL_A_ICLK) | + ((ADI_CFG_SPORT0A_OPERATION_MODE) << BITP_SPORT_CTL_A_OPMODE) | + ((ADI_CFG_SPORT0A_CLOCK_EDGE) << BITP_SPORT_CTL_A_CKRE) | + ((ADI_CFG_SPORT0A_FS_REQUIRED) << BITP_SPORT_CTL_A_FSR) | + ((ADI_CFG_SPORT0A_INTERNAL_FS) << BITP_SPORT_CTL_A_IFS) | + ((ADI_CFG_SPORT0A_DATA_INDEPENDENT_FS) << BITP_SPORT_CTL_A_DIFS) | + ((ADI_CFG_SPORT0A_ACTIVE_LOW_FS) << BITP_SPORT_CTL_A_LFS) | + ((ADI_CFG_SPORT0A_LATE_FS) << BITP_SPORT_CTL_A_LAFS) | + ((ADI_CFG_SPORT0A_ENABLE_PACKING) << BITP_SPORT_CTL_A_PACK) | + ((ADI_CFG_SPORT0A_FS_ERROR_OPERATION) << BITP_SPORT_CTL_A_FSERRMODE) | + ((ADI_CFG_SPORT0A_GATED_CLOCK) << BITP_SPORT_CTL_A_GCLKEN), + + /* SPORT_DIV register */ + ((ADI_CFG_SPORT0A_CLOCK_DIVISOR) << BITP_SPORT_DIV_A_CLKDIV) | + ((ADI_CFG_SPORT0A_FS_DIVISOR) << BITP_SPORT_DIV_A_FSDIV), + + /* SPORT_CONVT register */ + ((ADI_CFG_SPORT0A_CONVT_WIDTH) << BITP_SPORT_CNVT_A_WID) | + ((ADI_CFG_SPORT0A_CONVT_POLARITY) << BITP_SPORT_CNVT_A_POL) | + ((ADI_CFG_SPORT0A_CONVT_FS_DURATION) << BITP_SPORT_CNVT_A_CNVT2FS), + + /* Default DMA data size for SPORT */ + ADI_DMA_WIDTH_4_BYTE, + + /* Default DMA data increment for SPORT */ + ADI_DMA_INCR_4_BYTE + }, + + /* Configuration for half-SPORT B */ + { /* SPORT_CTL register */ + ((ADI_CFG_SPORT0B_LSB_FIRST) << BITP_SPORT_CTL_B_LSBF) | + ((ADI_CFG_SPORT0B_SERIAL_WLEN - 1u) << BITP_SPORT_CTL_B_SLEN) | + ((ADI_CFG_SPORT0B_INTERNAL_CLK) << BITP_SPORT_CTL_B_ICLK) | + ((ADI_CFG_SPORT0B_OPERATION_MODE) << BITP_SPORT_CTL_B_OPMODE) | + ((ADI_CFG_SPORT0B_CLOCK_EDGE) << BITP_SPORT_CTL_B_CKRE) | + ((ADI_CFG_SPORT0B_FS_REQUIRED) << BITP_SPORT_CTL_B_FSR) | + ((ADI_CFG_SPORT0B_INTERNAL_FS) << BITP_SPORT_CTL_B_IFS) | + ((ADI_CFG_SPORT0B_DATA_INDEPENDENT_FS) << BITP_SPORT_CTL_B_DIFS) | + ((ADI_CFG_SPORT0B_ACTIVE_LOW_FS) << BITP_SPORT_CTL_B_LFS) | + ((ADI_CFG_SPORT0B_LATE_FS) << BITP_SPORT_CTL_B_LAFS) | + ((ADI_CFG_SPORT0B_ENABLE_PACKING) << BITP_SPORT_CTL_B_PACK) | + ((ADI_CFG_SPORT0B_FS_ERROR_OPERATION) << BITP_SPORT_CTL_B_FSERRMODE) | + ((ADI_CFG_SPORT0B_GATED_CLOCK) << BITP_SPORT_CTL_B_GCLKEN), + + /* SPORT_DIV register */ + ((ADI_CFG_SPORT0B_CLOCK_DIVISOR) << BITP_SPORT_DIV_B_CLKDIV) | + ((ADI_CFG_SPORT0B_FS_DIVISOR) << BITP_SPORT_DIV_B_FSDIV), + + /* SPORT_CONVT register */ + ((ADI_CFG_SPORT0B_CONVT_WIDTH) << BITP_SPORT_CNVT_B_WID) | + ((ADI_CFG_SPORT0B_CONVT_POLARITY) << BITP_SPORT_CNVT_B_POL) | + ((ADI_CFG_SPORT0B_CONVT_FS_DURATION) << BITP_SPORT_CNVT_B_CNVT2FS), + + /* Default DMA data size for SPORT */ + ADI_DMA_WIDTH_4_BYTE, + + /* Default DMA data increment for SPORT */ + ADI_DMA_INCR_4_BYTE + } + } +}; + +/*! \endcond */ + +/*============= C O D E =============*/ + +extern void SPORT0A_Int_Handler(void); /*!< Interrupt handler for the SPORT0-A */ +extern void SPORT0B_Int_Handler(void); /*!< Interrupt handler for the SPORT0-B */ +extern void DMA_SPORT0A_Int_Handler(void); /*!< DMA handler for the SPORT0-A */ +extern void DMA_SPORT0B_Int_Handler(void); /*!< DMA handler for the SPORT0-B */ + +/*============= L O C A L F U N C T I O N S =============*/ + +/*============= P U B L I C F U N C T I O N S =============*/ + +/** + * @brief Initialization function for SPORT device. + * @details Initialization function for SPORT device. This function must be + * called before operating any SPORT device. + * + * @param [in] nDevNum SPORT Device instance to be opened. + * @param [in] eChannel Channel ID of the SPORT device (A or B) + * @param [in] eDirection Direction of the SPORT operation (i.e Rx or Tx) + * @param [in] pMemory Pointer to a 32 bit aligned buffer containing + * ADI_SPORT_MEMORY_SIZE bytes. This buffer is + * required by the SPORT driver for its operations. + * The "ADI_SPORT_MEMORY_SIZE" varies based on the + * configuration. + * @param [in] nMemSize Size of the buffer to which "pMemory" points. + * @param [out] phDevice Pointer to a location where a handle to the + * opened SPORT driver can be stored. This handle + * will be used to identity a SPORT device when + * calling SPORT management functions. + * + * @return Status + * - #ADI_SPORT_SUCCESS Successful device initialization. + * - #ADI_SPORT_DEVICE_IN_USE Device already initialized. + * - #ADI_SPORT_FAILED Failed initialize a semaphore for managing device. + * - #ADI_SPORT_INVALID_DEVICE_NUM Invalid SPORT device identifier + * - #ADI_SPORT_INVALID_NULL_POINTER Invalid pointer (callback function or device handle). + * + * @sa adi_sport_Close() + */ +ADI_SPORT_RESULT adi_sport_Open( + const uint32_t nDevNum, + const ADI_SPORT_CHANNEL eChannel, + const ADI_SPORT_DIRECTION eDirection, + void *pMemory, + const uint32_t nMemSize, + ADI_SPORT_HANDLE * const phDevice + ) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + + assert(ADI_SPORT_MEMORY_SIZE == sizeof(ADI_SPORT_DEVICE)); /* validate the memory size macro */ +#ifdef ADI_DEBUG + if (nDevNum >= ADI_SPORT_NUM_INSTANCES) + { + result = ADI_SPORT_INVALID_DEVICE_NUM; /* SPORT identifier must be within [0..ADI_SPORT_NUM_INSTANCES-1] */ + } + else if (phDevice == NULL) + { + result = ADI_SPORT_INVALID_NULL_POINTER; /* the pointer to device handle must be valid */ + } + else if (ADI_SPORT_MEMORY_SIZE != nMemSize) + { + result = ADI_SPORT_FAILED; + } + else if (ADI_SPORT_STATE_UNINITIALIZED != gSportDevInfo[nDevNum][eChannel].eState) + { + result = ADI_SPORT_DEVICE_IN_USE; /* the device instance must not be in use */ + } + else +#endif /* ADI_DEBUG */ + { + ADI_SPORT_DEVICE * pDevice = pMemory; /* Pointer to the SPORT device instance (from supplied memory) */ + ADI_SPORT_DEVICE_INFO * sportInfo = &gSportDevInfo[nDevNum][eChannel]; /* SPORT info for HSPORT A or HSPORT B */ + ADI_SPORT_CONFIG const * sportCfg = &gSportCfg[nDevNum][eChannel]; /* SPORT configuration for HSPORT A or HSPORT B */ + + assert(eChannel < ADI_SPORT_NUM_CHANNELS); + + memset(pMemory, 0, nMemSize); /* clear the device instance data before initializing it */ + + pDevice->pSportInfo = sportInfo; /* Initialize the pointer which provides the device information (HSPORT A or HSPORT B). */ + pDevice->eDirection = eDirection; /* Initialize the direction (BEFORE calling sport_Configure)*/ + pDevice->nHwError = (uint32_t) ADI_SPORT_HW_NO_ERR; + + adi_dma_Init(); /* Set up the DMA Controller. */ + sport_Init(pDevice); /* Initialize the data transmission buffers */ + sport_Configure(pDevice,sportCfg); /* Configure the SPORT */ + + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(sportInfo->eDMAChnlID, sport_DmaErrorCallback, pDevice)) + { + adi_sport_Close(pDevice); + result = ADI_SPORT_DMA_REGISTER_FAILED; + } + + if (ADI_SPORT_SUCCESS == result) + { + ADI_SPORT_DEVICE_INFO * devInfo = &gSportDevInfo[nDevNum][eChannel]; + + /* Create a "semaphore" (varies per OS) used for blocking buffer resource management. */ + if (ADI_HALF_SPORT_A == eChannel) + { + SEM_CREATE(&pDevice->sportChannel, "SPORT0_A_SEM", ADI_SPORT_FAILED); + }else{ + SEM_CREATE(&pDevice->sportChannel, "SPORT0_B_SEM", ADI_SPORT_FAILED); + } + + /* Change the state of the specified device */ + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + devInfo->eState = ADI_SPORT_STATE_INITIALIZED; + devInfo->hDevice = pDevice; + ADI_EXIT_CRITICAL_REGION(); + *phDevice = pDevice; /* Return the device handle to the application */ + } + } + + return result; +} + +/** + * @brief Closes the operation of specified SPORT device. + * + * @details Closes the operation of specified SPORT device. + * Device need to be opened again for any further use. + * + * @param [in] hDevice SPORT device handle whose operation is to be closed. + * This handle was obtained when a SPORT device is opened + * successfully. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully closed the specified device. + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * - #ADI_SPORT_FAILED [D] SPORT device internal error. + * + * @note It is user's responsibility to free/reuse the memory supplied + * during the opening of the device. + * + * @sa adi_sport_Open() + */ +ADI_SPORT_RESULT adi_sport_Close(ADI_SPORT_HANDLE const hDevice) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; /* return code */ + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice; /* Pointer to SPORT device instance */ +#ifdef ADI_DEBUG + if (ADI_SPORT_SUCCESS == (result=ValidateHandle(pDevice))) /* Validate the given handle */ +#endif /* ADI_DEBUG */ + { + ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo; + + /* Free up the device */ + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + NVIC_DisableIRQ(pSportInfo->eIRQn); /* Disable SPORT event interrupts. */ + NVIC_DisableIRQ(pSportInfo->eDMAn); /* Disable DMA SPORT interrupts. */ + pSportInfo->eState = ADI_SPORT_STATE_UNINITIALIZED; + pSportInfo->hDevice = NULL; /* Free up the device memory. */ + ADI_EXIT_CRITICAL_REGION(); + + SEM_DELETE(&pDevice->sportChannel, ADI_SPORT_FAILED); /* Delete SPORT channel semaphore. */ + + adi_dma_RegisterCallback(pSportInfo->eDMAChnlID, NULL, NULL); /* unregister the callback function in the DMA error handler */ + + pSportInfo->pSportRegs->CTL_A = 0u; + } + return result; +} + +/** + * @brief Submit the buffer for transmitting/receiving the data. This function can + * be used to submit the buffers for both transmitting and receiving. It will + * be returned after successfully submitting the buffer for transmitting data. + * User will be notified if a call back function is registered with an event code + * #ADI_SPORT_EVENT_RX_BUFFER_PROCESSED or #ADI_SPORT_EVENT_TX_BUFFER_PROCESSED" + * depending on the direction in which device is operating. + * + * @param [in] hDevice Device handle to SPORT device is obtained when a SPORT device is opened + * successfully. + * + * @param [in] pBuffer Pointer to buffer from where data need to be transmitted OR to which + * received data need to to be written. + * + * @param [in] nNumBytes Size in bytes of the data to be transmitted/received. + * @param [in] bDMA True if the buffer must be processed through DMA-driven SPORT operations. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Buffer successfully submitted to the specified SPORT. + * - #ADI_SPORT_INVALID_HANDLE Invalid SPORT device handle. + * - #ADI_SPORT_INVALID_PARAMETER Number of bytes is too large for a SPORT transfer or the buffer is mis-aligned + * - #ADI_SPORT_BUFFERS_NOT_SUBMITTED All the SPORT buffers are already being used + * + * @sa adi_sport_GetBuffer() + * + */ +ADI_SPORT_RESULT adi_sport_SubmitBuffer(ADI_SPORT_HANDLE const hDevice, + void * const pBuffer, + uint32_t const nNumBytes, + bool const bDMA + ) +{ + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice; /* pointer to SPORT device instance */ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; /* return code */ + +#ifdef ADI_DEBUG + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; /* short cut to SPORT configuration */ + + if(ADI_SPORT_SUCCESS != (result=ValidateHandle(hDevice))) /* validate the given handle */ + { + } + else if ( ((2u >= nNumBytes) && ((pDevice->pSportInfo->pSportRegs->CTL_A & BITM_SPORT_CTL_A_OPMODE) != 0u)) + || (0u != (nNumBytes & ~(BITM_SPORT_NUMTRAN_A_VALUE))) /* buffer size limited by SPORT transmission capabilities */ + ) + { + result = ADI_SPORT_INVALID_PARAMETER; + } + else +#endif /* ADI_DEBUG */ + /* Check that there is a free buffer to use for this transmit operation. pFreeBuffer + is the next buffer available, so if it is in use we can make the assumption that + there are no buffers available. The start address is set to NULL once the buffer + has finished being processed in "adi_sport_GetBuffer()". + */ + if (NULL != pDevice->sportChannel.pFreeBuffer->pStartAddress) + { + result = ADI_SPORT_BUFFERS_NOT_SUBMITTED; + } + else + { +#ifdef ADI_DEBUG + const uint32_t addr = (uint32_t) pBuffer; + + if (true == bDMA) + { + /** + * Using SPORT configuration data, let's define information such as data + * size in bytes, data number, number of data and bytes in the DMA transfer + * being prepared, last byte position for the DMA transfer + * + * It's important to keep in mind that for buffer that contain too many data + * multiple DMA transfers are needed: it's up to the application to split the + * DMA requests in requests which have an appropriate number of data. + */ + const uint32_t dataSizeInBytes = GetBytesPerSportData(pSportCfg->CTL); + const uint32_t full = nNumBytes / dataSizeInBytes; /* number of full data to transmit/receive */ + const uint32_t partial = nNumBytes % dataSizeInBytes; /* number of partial data to transmit/receive */ + const uint32_t misaligned = addr % dataSizeInBytes; /* number of data to transmit/receive */ + + if ( (full > DMA_TRANSFER_LIMIT) /* number of data to process too large for DMA */ + || (0u != partial) /* buffer size not a multiple of dataSizeInBytes */ + || (0u != misaligned) /* buffer mis-aligned */ + ) + { + result = ADI_SPORT_INVALID_PARAMETER; + } + } else { + const uint32_t misAligned = addr % 4u; + const uint32_t invalidNum = nNumBytes % 4u; + + if ( (0u != misAligned) /* mis-aligned buffer */ + || (0u != invalidNum) /* number of bytes not a multiple of 32-bit */ + ) + { + result = ADI_SPORT_INVALID_PARAMETER; /* reject the buffer submission */ + } + } + if (ADI_SPORT_SUCCESS == result) +#endif /* ADI_DEBUG */ + { + ADI_DT_CHANNEL * pSportChnl = &pDevice->sportChannel; + + pSportChnl->pFreeBuffer->pStartAddress = pBuffer; /* Set the start address of the data buffer */ + pSportChnl->pFreeBuffer->nCount = nNumBytes; /* Set the buffer size */ + pSportChnl->pFreeBuffer->nIndex = 0u; /* Initialize the buffer index to zero (1st data in buffer) */ + pSportChnl->pFreeBuffer->bDMA = bDMA; /* Set the DMA boolean value. */ + pSportChnl->pFreeBuffer->bInUse = true; /* this buffer is now being used by the SPORT */ + + /* Now that this "pFreeBuffer" is no longer free for use, update the + "pFreeBuffer" to the next buffer. "pFreeBuffer" will only be updated + during the process of submitting a buffer or a read/write operation. + */ + pSportChnl->pFreeBuffer = pSportChnl->pFreeBuffer->pNextBuffer; + + /* Set the data transfer mode in case it was #ADI_DT_MODE_NONE. This + will be set back to #ADI_DT_MODE_NONE once this transaction is complete. + Then, if a buffer is not currently active, set up the interrupts for + this transaction. Otherwise if a buffer is currently active, this will + be taken care of in the ISR. + */ + if (pSportChnl->eDataTranferMode == ADI_DT_MODE_NONE) /* if the SPORT is available for a transmission */ + { + pSportChnl->eDataTranferMode = ADI_DT_MODE_NONBLOCKING; + + /* call an appropriate function based on mode in which device is operating */ + if (true == bDMA) /* select a DMA driven or a core driven non-blocking transmission */ + { + result = sport_SubmitBufferDmaMode(pDevice, pSportChnl->pFillBuffer); + } else { + result = sport_SubmitBufferIntMode(pDevice, pSportChnl->pFillBuffer); + } + } + + if(ADI_SPORT_SUCCESS != result) /* if an error occurred...*/ + { + pSportChnl->eDataTranferMode = ADI_DT_MODE_NONE; /* SPORT is available */ + } + } + } + + return result; +} + +/* + * @brief Submit a buffer for SPORT Rx or Tx DMA driven transmission. + * + * @param [in] pDevice Pointer to SPORT device. + * + * @param [in] pBuffer Pointer to data transfer buffer information. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS buffer successfully submitted to the DMA associated with the SPORT. + * - #ADI_SPORT_BUFFERS_NOT_SUBMITTED Failed to submit the buffer to the DMA associated with the SPORT. + */ +/** Function prototype for submitting a buffer for SPORT Rx or Tx DMA driven transmission */ +static ADI_SPORT_RESULT sport_SubmitBufferDmaMode(ADI_SPORT_DEVICE * pDevice, + ADI_DT_BUFF_INFO * pBuff) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo; /* short cut to SPORT information */ + ADI_SPORT_CONFIG * pSportCfg = &pSportInfo->sportCfg; /* short cut to SPORT configuration */ + +#ifdef ADI_DEBUG + if ( (pBuff != pDevice->sportChannel.pFillBuffer) /* a submitted buffer should always be the current fill buffer */ + || (true != pBuff->bInUse) /* Processed buffers should already be marked as being used */ + || (0u != pBuff->nIndex) /* processing should start from index 0 */ + ) + { + result = ADI_SPORT_FAILED; + } + else +#endif + { + volatile ADI_SPORT_TypeDef* pSportRegs = pSportInfo->pSportRegs;/* short cut to SPORT registers */ + const uint32_t dmaChnlId = (uint32_t) pSportInfo->eDMAChnlID; /* identifier for the DMA channel to be used */ + const uint32_t dmaChnlBit = (1u << dmaChnlId); /* bit representing the DMA channel to be used */ + + /** + * Using SPORT configuration data, let's define information such as data + * size in bytes, data number, number of data and bytes in the DMA transfer + * being prepared, last byte position for the DMA transfer + * + * It's important to keep in mind that for buffer that contain too many data + * multiple DMA transfers are needed, so a buffer may have had part of its + * content already DMA-transferred: nIndex defines the position of the first + * byte in a buffer that has not been DMA-transferred yet. + */ + const uint32_t dmaIncNone = (uint32_t) ADI_DMA_INCR_NONE; + const uint32_t dmaDcc = (uint32_t) DMA_ENUM_CTL_CYCLE_CTL_BASIC; + const uint32_t bytesPerData = GetBytesPerSportData(pSportCfg->CTL); + + const uint32_t dataSizeInBytes = (1u << pSportCfg->DMA_WIDTH); /* number of bytes in each data to transmit/receive */ + uint32_t numDmaData = pBuff->nCount / dataSizeInBytes; /* number of DMA data to transmit/receive */ + const uint32_t dmaDataEnd = (pBuff->nCount - dataSizeInBytes); /* position of last <8,16,32>-bit data in the DMA transfer being setup */ + const uint32_t startAddress = (uint32_t) pBuff->pStartAddress; /* address of the first byte in the data buffer */ + const uint32_t numSportData = pBuff->nCount / bytesPerData; /* number of SPORT data to transmit/receive */ + + assert(pBuff->nCount == (numSportData * bytesPerData)); + assert(numSportData <= 0xFFFu); + assert(0u == (pBuff->nCount % dataSizeInBytes)); + assert(numDmaData <= DMA_TRANSFER_LIMIT); + assert((ADI_SPORT_DIR_RX == pDevice->eDirection) || (ADI_SPORT_DIR_TX == pDevice->eDirection)); + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); + + pSportRegs->CTL_A = 0u; /* make sure SPORT is disable */ + pADI_DMA0->SRCADDR_CLR = dmaChnlBit; /* Clear source address decrement for TX channel DMA. */ + pADI_DMA0->EN_SET = dmaChnlBit; /* Enable channel DMA. */ + pADI_DMA0->RMSK_CLR = dmaChnlBit; /* Enable SPORT peripheral to generate DMA requests. */ + pADI_DMA0->ALT_CLR = dmaChnlBit; /* Set the primary control data structure as the current DMA descriptor. */ + pADI_DMA0->PRI_SET = dmaChnlBit; + + if (ADI_SPORT_DIR_RX == pDevice->eDirection) + { + pPrimaryCCD[dmaChnlId].DMASRCEND = (uint32_t) &pSportRegs->RX_A; /* address of the last src data in the DMA transfer being setup */ + pPrimaryCCD[dmaChnlId].DMADSTEND = startAddress + dmaDataEnd; /* address of the last dst data in the DMA transfer being setup */ + pPrimaryCCD[dmaChnlId].DMACDC = + (pSportCfg->DMA_INC << ((uint32_t)DMA_BITP_CTL_DST_INC)) | /* destination address incremented by N bytes */ + (dmaIncNone << ((uint32_t)DMA_BITP_CTL_SRC_INC)); /* source address not incremented */ + } + else /* ADI_SPORT_DIR_TX */ + { + pPrimaryCCD[dmaChnlId].DMASRCEND = startAddress + dmaDataEnd; /* address of the last src data in the DMA transfer being setup */ + pPrimaryCCD[dmaChnlId].DMADSTEND = (uint32_t) &pSportRegs->TX_A; /* address of the last dst data in the DMA transfer being setup */ + pPrimaryCCD[dmaChnlId].DMACDC = + (dmaIncNone << ((uint32_t)DMA_BITP_CTL_DST_INC)) | /* destination address not incremented */ + (pSportCfg->DMA_INC << ((uint32_t)DMA_BITP_CTL_SRC_INC)); /* source address incremented by N byte */ + + /** + * Fix for data transmission when DMA is used with packed data. + */ + if (numDmaData < numSportData) + { + pPrimaryCCD[dmaChnlId].DMASRCEND = startAddress + dmaDataEnd + dataSizeInBytes; /* address of the last src data in the DMA transfer being setup */ + numDmaData++; + } + } + pPrimaryCCD[dmaChnlId].DMACDC |= + (pSportCfg->DMA_WIDTH << ((uint32_t)DMA_BITP_CTL_SRC_SIZE)) | /* source data size in bytes */ + (0u << ((uint32_t) DMA_BITP_CTL_R_POWER)) | + ((numDmaData - 1u) << ((uint32_t)DMA_BITP_CTL_N_MINUS_1)) | /* number of DMA transfers (minus 1) */ + (dmaDcc << ((uint32_t)DMA_BITP_CTL_CYCLE_CTL)); + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + pDevice->pSportInfo->eState = ADI_SPORT_STATE_DATA_FLOW_ENABLED; + pSportRegs->NUMTRAN_A = numSportData; + + /* Enable SPORT DMA request interrupt for the SPORT tx channel. */ + NVIC_ClearPendingIRQ(pSportInfo->eIRQn); + NVIC_ClearPendingIRQ(pSportInfo->eDMAn); + + uint32_t ien_a = ((uint32_t)BITM_SPORT_IEN_A_SYSDATERR) | + ((uint32_t)BITM_SPORT_IEN_A_FSERRMSK) | + ((uint32_t)BITM_SPORT_IEN_A_DERRMSK); + if (ADI_SPORT_DIR_RX == pDevice->eDirection) + { + /* Allow SPORT DMA interrupt handling to mark SPORT Rx as complete */ + NVIC_EnableIRQ(pSportInfo->eDMAn); + } + else + { + /* SPORT DMA Tx is complete when TFI is raised: enable TFI */ + ien_a |= ((uint32_t)BITM_SPORT_IEN_A_TF); + } + + NVIC_EnableIRQ(pSportInfo->eIRQn); + + pSportRegs->IEN_A = ien_a; + pSportRegs->CTL_A = pSportCfg->CTL | + ((uint32_t)BITM_SPORT_CTL_A_SPEN) | + ((uint32_t)BITM_SPORT_CTL_A_DMAEN); + ADI_EXIT_CRITICAL_REGION(); + + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); + } + return result; +} + +/** Function prototype for */ +/* + * @brief Submit a buffer for SPORT Rx or Tx core driven transmission. + * + * @details Submit a buffer for SPORT Rx or Tx core driven transmission. + * The buffer must be 32-bit aligned and contain N * 32-bit data. + * + * @param [in] pDevice Pointer to SPORT device. + * + * @param [in] pBuffer Pointer to data transfer buffer information. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully submitted the buffer for data transfer. + * + * - #ADI_SPORT_BUFFERS_NOT_SUBMITTED No free descriptor for data transfer. + * + * + */ +static ADI_SPORT_RESULT sport_SubmitBufferIntMode(ADI_SPORT_DEVICE * pDevice, ADI_DT_BUFF_INFO * pBuff) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; +#ifdef ADI_DEBUG + if ( (pBuff != pDevice->sportChannel.pFillBuffer) /* a submitted buffer should always be the current fill buffer */ + || (true != pBuff->bInUse) /* Processed buffers should already be marked as being used */ + || (0u != pBuff->nIndex) /* processing should start from index 0 */ + ) + { + result = ADI_SPORT_FAILED; + } + else +#endif /* ADI_DEBUG */ + { + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; + volatile ADI_SPORT_TypeDef * pSportRegs = pDevice->pSportInfo->pSportRegs; + uint32_t ctl = pSportCfg->CTL; + uint32_t bytesPerData = GetBytesPerSportData(ctl); + + /** + * Buffer can be too large for being processed in one submission. + * Consequently, if pBuff->nCount requires more than than 12-bit, + * multiple buffer submissions will be required by the application; + * the SPORT driver cannot process large buffers implicitly. + * The number of bytes in submitted buffers must be a multiple of 4 + * because data are processed by the SPORT driver as 32-bit data. + */ + + /* use the SPORT configuration to setup the SPORT registers */ + + pBuff->nCount /= bytesPerData; /* number of data to be transmitted */ + +#ifdef ADI_DEBUG + uint32_t pack = SPORT_GET_PACKEN(pSportCfg->CTL); + assert( ((9u > bytesPerData) && (1u == pack)) || ((17u > bytesPerData) && (2u == pack)) || (0u == pack)); +#endif + assert(pBuff->nCount <= 0xFFFu); + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + pSportRegs->CTL_A = 0u; /* make sure SPORT is disable */ + pSportRegs->NUMTRAN_A = pBuff->nCount; + pDevice->pSportInfo->eState = ADI_SPORT_STATE_DATA_FLOW_ENABLED; + + /* Enable SPORT Interrupt. */ + NVIC_ClearPendingIRQ(pDevice->pSportInfo->eIRQn); + NVIC_EnableIRQ(pDevice->pSportInfo->eIRQn); + pSportRegs->IEN_A |= ((uint32_t) ( BITM_SPORT_IEN_A_DATA + | BITM_SPORT_IEN_A_SYSDATERR + | BITM_SPORT_IEN_A_FSERRMSK + | BITM_SPORT_IEN_A_DERRMSK + | BITM_SPORT_IEN_A_TF + ) + ); + pSportRegs->CTL_A = pSportCfg->CTL | ((uint32_t)BITM_SPORT_CTL_A_SPEN); + ADI_EXIT_CRITICAL_REGION(); + } + return result; +} + +/** + * @brief This function returns the address of a processed buffer. This + * is a blocking function: it waits until a buffer has been dealt + * with. This function returns an error if a callback function is + * registered. #adi_sport_IsBufferAvailable can be used as a peek + * function to know whether a buffer is available. + * + * @param [in] hDevice Device handle to SPORT device, obtained when a SPORT + * device is openedsuccessfully. + * + * @param [out] ppBuffer Pointer to a location where the the address of the + * buffer is to be written. Contains the address of an + * "empty" buffer (i.e the content of the buffer is + * transmitted) OR "filled" buffer which contains the + * received data. + * + * @param [out] pHwError Pointer to 32-bit value reporting SPORT/DMA events + * that can occur when processing buffer ppBuffer. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully returned. ppBuffer points + * to the address of the buffer. + * + * - #ADI_SPORT_FAILED Failed to get the buffer since device + * is operating in call back mode. + * ppBuffer points NULL. + * + * - #ADI_SPORT_HW_ERROR SPORT hardware or DMA error detected + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * @sa adi_sport_SubmitBuffer() + * @sa adi_sport_IsBufferAvailable() + * + */ +ADI_SPORT_RESULT adi_sport_GetBuffer(ADI_SPORT_HANDLE const hDevice, + void ** const ppBuffer, + uint32_t * pHwError) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) hDevice; /* Pointer to SPORT device instance */ + + *ppBuffer = NULL; +#ifdef ADI_DEBUG + if (ADI_SPORT_SUCCESS != (result=ValidateHandle(pDevice))) /* Validate the given handle */ + { + } + else +#endif /* ADI_DEBUG */ + if (NULL != pDevice->pfCallback) + { + result = ADI_SPORT_FAILED; + } else { + ADI_DT_CHANNEL * pSportChnl = &pDevice->sportChannel; + + SEM_PEND(pSportChnl,ADI_SPORT_FAILED); /* wait for a submitted buffer to be processed */ + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + *pHwError = pDevice->nHwError; + pDevice->nHwError = 0u; + *ppBuffer = pSportChnl->pActiveBuffer->pStartAddress; /* return the buffer start address in *ppBuffer */ + pSportChnl->pActiveBuffer->pStartAddress = NULL; /* clear the free buffer address */ + pSportChnl->pActiveBuffer = pSportChnl->pActiveBuffer->pNextBuffer; + ADI_EXIT_CRITICAL_REGION(); + if (0u != *pHwError) + { + result = ADI_SPORT_HW_ERROR; + } + } + return result; +} + +/** + * @brief Peek function to know whether an empty/filled buffer is available. Call to this + * function is valid only if the call back function is not registered. Call to this + * function results in error if a call back function is registered. + * + * @param [in] hDevice Device handle to SPORT device obtained when a SPORT device is opened + * successfully. + * + * @param [out] pbAvailable Pointer to a boolean variable. Contains "True" if there is an + * empty/filled buffer and a call to #adi_sport_GetBuffer is ensured to be + * successful. Contains "false" if there is no empty buffer. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully retrieved the status of availability of the buffer. + * - #ADI_SPORT_INVALID_HANDLE Failed to retrieve the status of the buffer availability. + * - #ADI_SPORT_OPERATION_NOT_ALLOWED Function cannot be called (no buffer to be processed or callback function registered). + * - ADI_SPORT_PERIPHERAL_ERROR Hardware error detected + * + * @sa adi_sport_GetBuffer() + * @sa adi_sport_GetBuffer() + * + */ +ADI_SPORT_RESULT adi_sport_IsBufferAvailable(ADI_SPORT_HANDLE const hDevice, + bool * const pbAvailable) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) hDevice; /* Pointer to SPORT device instance */ + + *pbAvailable = false; +#ifdef ADI_DEBUG + if (ADI_SPORT_SUCCESS != (result=ValidateHandle(pDevice))) /* Validate the given handle */ + { + } + else +#endif /* ADI_DEBUG */ + if (NULL != pDevice->pfCallback) + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else + { + ADI_DT_BUFF_INFO * pActiveBuffer = pDevice->sportChannel.pActiveBuffer; + + if (pActiveBuffer->pStartAddress == NULL) + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else if (false == pActiveBuffer->bInUse) /* this buffer has been processed by the SPORT */ + { + *pbAvailable = true; + } + else + { + } + } + return result; +} + +/** + * @brief Register and unregister a Callback function with the SPORT device driver. + * A registered call back function will be called, if not NULL, when a buffer + * is processed OR hardware error(s) encountered. + * + * @param [in] hDevice Device handle to SPORT device is obtained when a SPORT device is opened + * successfully. + * + * @param [in] pfCallback Function pointer to Callback function. Passing a NULL pointer will + * unregister the call back function. + * + * @param [in] pCBparam Call back function parameter. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully registered specified callback function. + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * - #ADI_SPORT_OPERATION_NOT_ALLOWED [D] Operation is not allowed when data flow is enabled. + * + */ +ADI_SPORT_RESULT adi_sport_RegisterCallback(ADI_SPORT_HANDLE const hDevice, + ADI_CALLBACK const pfCallback, + void * const pCBparam) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice; /* Pointer to SPORT device instance */ +#ifdef ADI_DEBUG + /* Validate the given handle */ + if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice))) + { + } + /* Check if the data flow is already enabled */ + else if (ADI_SPORT_STATE_DATA_FLOW_ENABLED == pDevice->pSportInfo->eState) + { + /* Not allowed to register a callback if the data flow is enabled. */ + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else +#endif /* ADI_DEBUG */ + { + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + pDevice->pfCallback = pfCallback; /* Store the address of the callback function */ + pDevice->pCBParam = pCBparam; /* Store the call back parameter */ + ADI_EXIT_CRITICAL_REGION(); + } + return result; +} + +/** + * @brief Sets data format for the specified SPORT device. + * + * @details Sets data type,Big endian (MSB first) OR Little endian (LSB first) and word + * length(in bits) for the specified SPORT device.This function return error if the + * device is already enabled. + * + * @param [in] hDevice Device handle to SPORT device. + * + * @param [in] nWordLength Specify the word size of the data. Valid range is from + * 4(nWordLength = 3) to 32(nWordLength =31). + * + * @param [in] bLSBFirst Configure the specified SPORT device to operate either LSB + * first or MSB first. + * \n + * \n true : LSB first (Little endian) . + * \n + * \n false : MSB first (Big endian) + * + * @param [in] ePackMode Mode of packging need to configured. Please refer #ADI_SPORT_PACKING_MODE. + * + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully configured the device to operate in + * specified data format. + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * - #ADI_SPORT_INVALID_WORD_LENGTH [D] Invalid word size. + * + * - #ADI_SPORT_OPERATION_NOT_ALLOWED [D] Operation is not allowed when data flow is enabled. + * + */ +ADI_SPORT_RESULT adi_sport_ConfigData(ADI_SPORT_HANDLE const hDevice, + const uint8_t nWordLength, + const ADI_SPORT_PACKING_MODE ePackMode, + const bool bLSBFirst + ) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice; /* Pointer to SPORT device instance */ +#ifdef ADI_DEBUG + if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice))) + { + } + if(pDevice->pSportInfo->eState == ADI_SPORT_STATE_DATA_FLOW_ENABLED) /* Not allowed to change when data flow is enabled */ + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else +#endif /* ADI_DEBUG */ + if (nWordLength > SPORT_WORD_TRANSFER_LENGTH) + { + result = ADI_SPORT_INVALID_WORD_LENGTH; + } + else + { + ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo; /* short cut to SPORT information */ + ADI_SPORT_CONFIG * pSportCfg = &pSportInfo->sportCfg; /* short cut to SPORT configuration */ + const uint32_t bytesPerData = ((nWordLength < 9u) ? (1u) : ((nWordLength < 17u) ? (2u) : (4u))); + + const uint32_t wordPos = (uint32_t) BITP_SPORT_CTL_A_SLEN; + const uint32_t wordLen = (uint32_t) nWordLength; + const uint32_t ctlSlen = (wordLen - 1u) << wordPos; + const uint32_t packMode = (uint32_t) ePackMode; + const uint32_t ctlSlenBits = (0x1Fu << wordPos); + const uint32_t ctlDataMask = ~(BITM_SPORT_DATA_CONFIG | ctlSlenBits | BITM_SPORT_CTL_A_LSBF); + + uint32_t ctl = pDevice->pSportInfo->sportCfg.CTL; + ctl &= ctlDataMask; /* clear all the fields(i.e Set to "0" ) */ + ctl |= (packMode | ctlSlen); /* assign packing and slen information */ + if (true == bLSBFirst) + { + ctl |= BITM_SPORT_CTL_A_LSBF; /* set the the LSB first field */ + } + pDevice->pSportInfo->sportCfg.CTL = ctl; /* CTL value set - CTL_A is assigned when submitting a buffer */ + + SPORT_CHECK_CFG_CTL(pDevice->pSportInfo->sportCfg.CTL); + + switch (bytesPerData) + { + case 1u: + if (((uint32_t) ADI_SPORT_8BIT_PACKING) == packMode) + { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE; + } else { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_1_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_1_BYTE; + + assert(((uint32_t) ADI_SPORT_NO_PACKING) == packMode); + } + break; + + case 2u: + if (((uint32_t) ADI_SPORT_16BIT_PACKING) == packMode) + { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE; + } else { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_2_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_2_BYTE; + + assert(((uint32_t) ADI_SPORT_NO_PACKING) == packMode); + } + break; + + default: + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE; + assert((4u == bytesPerData) || (((uint32_t) ADI_SPORT_NO_PACKING) == packMode)); + break; + } + } + return result; +} + +/** + * @brief Configure the clock for the specified SPORT device. + * + * @details Configure the SPORT device to use the "internal/external " rising/falling clock + * edge,clock edge and for enabling the gated Clock Mode. + * + * @details fspclk = fsclk/(2*( nClockRatio + 1)) + * + * @details fspclk: frequency of SPORT clock + * + * @param [in] hDevice Device handle to SPORT device. + * + * @param [in] nClockRatio The value which determines the ratio between System clock and SPORT + * clock as explained above. + * + * + * @param [in] bUseIntlClock Boolean flag to indicate whether to use internal clock or external + * clock for data transmission. By default, device is configured to use + * the external clock. + * \n + * \n true : Device configured to use Internal clock. + * \n + * \n false : Device configured to use external clock.. + * + * @param [in] bRisingEdge Boolean flag to indicate whether to drive data and internal frame + * sync with rising edge OR falling edge of SP clock. + * \n + * \n true : Use falling edge of the clock. + * \n + * \n false : Use rising edge of the clock. + * + * @param [in] bGatedClk Boolean flag to indicate whether to enable/disable gated clock for + * the specified SPORT channel.Ignored in Multi channel mode. Clock will + * be active only when active data is getting transmitted or received + * when this mode is enabled. + * \n true : Enable gated clock mode. + * \n + * \n false : Disable gated clock mode. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully configured clock for the specified device. + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * - #ADI_SPORT_OPERATION_NOT_ALLOWED [D] Operation is not allowed when data flow is enabled. + * + */ +ADI_SPORT_RESULT adi_sport_ConfigClock(ADI_SPORT_HANDLE const hDevice, + const uint16_t nClockRatio, + const bool bUseIntlClock, + const bool bRisingEdge, + const bool bGatedClk) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice; /* Pointer to SPORT device instance */ + +#ifdef ADI_DEBUG + if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice))) + { + } + else if (ADI_SPORT_STATE_DATA_FLOW_ENABLED == pDevice->pSportInfo->eState) + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else +#endif /* ADI_DEBUG */ + { + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; + uint32_t clockRatio = (uint32_t) nClockRatio; + + uint32_t ctl = pSportCfg->CTL; + uint32_t dv = pSportCfg->DIV; + + ctl &= ~BITM_SPORT_CLOCK_CONFIG; /* clear all clock configuration fields */ + + dv &= ~BITM_SPORT_DIV_A_CLKDIV; + dv |= (clockRatio & BITM_SPORT_DIV_A_CLKDIV); /* update the clock divisior value */ + + if (true == bUseIntlClock) + { + ctl |= BITM_SPORT_CTL_A_ICLK; /* select the internal clock */ + } + if (true == bRisingEdge) + { + ctl |= BITM_SPORT_CTL_A_CKRE; /* select the rising edge of the clock */ + } + if (true == bGatedClk) + { + ctl |= BITM_SPORT_CTL_A_GCLKEN; /* Enable the Gated clock */ + } + pDevice->pSportInfo->pSportRegs->DIV_A = pSportCfg->DIV = dv; /* DIV value set */ + pSportCfg->CTL = ctl; /* CTL value set - CTL_A is assigned when submitting a buffer */ + + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); + } + return result; +} + +/** + * @brief Frame Sync(FS) configuration for the specified SPORT. + * + * @details Configure the SPORT to use internal/external frame sync,level/edge sensitive + * early/late frame sync etc. + * + * @param [in] hDevice Device handle to SPORT device. + * + * @param [in] nFsDivisor The value which decides the number of SPORT clock cycles between + * each frame count. + * + * @param [in] bFSRequired Boolean flag to indicate whether frame sync required OR not to + * the frame sync for the data transfer. + * \n + * \n true : Device requires a frame sync for its operation. + * \n + * \n false : Device does not requires a frame sync for its operation + * \n + * \n + * + * @param [in] bInternalFS Boolean flag to indicate whether to configure the specified SPORT + * device to use the internal frame sync OR external frame sync as + * below. + * \n + * \n true : Use internal frame sync. + * \n + * \n false : Use external frame sync + * \n + * \n + * + * @param [in] bDataFS Boolean flag to indicate whether to configure the specified SPORT + * device to use the data-independent frame sync OR Serial port uses + * a data-dependent frame sync. Valid only if the specified device is + * in "transmit"(TX)mode . Ignored if the device is opened in + * "receive"(RX) mode. + * \n + * \n true : Use data-independent frame sync. + * \n + * \n false : Use data-dependent frame sync. + * \n + * \n + * + * @param [in] bActiveLowFS Boolean flag to indicate whether to configure the specified SPORT + * device for active low frame sync OR active high frame sync. Call + * to this function will return error if SPORT is configured in I2S + * mode. + * \n + * \n true : Use active low frame sync. + * \n + * \n false : Use active high frame sync. + * \n + * \n + * + * @param [in] bLateFS Boolean flag to indicate whether to use the late frame sync OR + * Early frame sync. + * \n + * \n true : Use late frame sync. + * \n + * \n false : Use Early frame sync. + * \n + * \n + * +* @param [in] bFSErrorOperation Frame Sync Error Operation. This + *\n decides the way the SPORT responds when a frame sync error occurs. + * \n + * \n true : When frame Sync error occurs, discard the receive data. + * \n + * \n false : Flag the Frame Sync error and continue normal operation + * \n + * \n + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully configured the frame sync requirement. + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * - #ADI_SPORT_OPERATION_NOT_ALLOWED [D] Operation is not allowed when data flow is enabled. + * + */ +ADI_SPORT_RESULT adi_sport_ConfigFrameSync(ADI_SPORT_HANDLE const hDevice, + const uint16_t nFsDivisor, + const bool bFSRequired, + const bool bInternalFS, + const bool bDataFS, + const bool bActiveLowFS, + const bool bLateFS, + const bool bFSErrorOperation) +{ + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice; /* Pointer to SPORT device instance */ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + +#ifdef ADI_DEBUG + /* Validate the given handle */ + if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice))) + { + } + else if(pDevice->pSportInfo->eState == ADI_SPORT_STATE_DATA_FLOW_ENABLED) + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else +#endif /* ADI_DEBUG */ + { + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; + const uint32_t fsDivisor = (uint32_t) nFsDivisor; + + uint32_t ctl = pSportCfg->CTL; + uint32_t dv = pSportCfg->DIV; + + dv &= ~BITM_SPORT_DIV_A_FSDIV; /* clear all the fields of frame sync */ + dv |= (fsDivisor << BITP_SPORT_DIV_A_FSDIV); + + ctl &= ~BITM_SPORT_FS_CONFIG; /* clear all the fields of frame sync */ + + if ((ADI_SPORT_DIR_RX == pDevice->eDirection) || (true == bDataFS)) + { + ctl |= BITM_SPORT_CTL_A_DIFS; /* Set this bit when SPORT is opened in RX mode */ + } + if (true == bFSRequired) /* "Frame sync required" is reserved when device */ + { /* is operating in I2S and MC mode */ + ctl |= BITM_SPORT_CTL_A_FSR; /* Frame Sync(FS) is required */ + } + if (true == bInternalFS) + { + ctl |= BITM_SPORT_CTL_A_IFS; /* Select the internal Frame Sync(FS)*/ + } + if (true == bActiveLowFS) + { + ctl |= BITM_SPORT_CTL_A_LFS; /* Select the Active High Frame Sync(FS)*/ + } + if (true == bLateFS) + { + ctl |= BITM_SPORT_CTL_A_LAFS; /* Select the Late Frame Sync(FS)*/ + } + if (true == bFSErrorOperation) + { + ctl |= BITM_SPORT_CTL_A_FSERRMODE; /* Select the edge sensitive Frame Sync(FS)*/ + } + pDevice->pSportInfo->pSportRegs->DIV_A = pSportCfg->DIV = dv; /* DIV value set */ + pSportCfg->CTL = ctl; /* CTL value set - CTL_A is assigned when submitting a buffer */ + + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); + } + return result; +} + +/** + * @brief Configure the SPORT use the Clocks and Frame Sync of other Half-Sport + * + * @param [in] hDevice Device handle to SPORT device. + * + * @param [in] bUseOtherFS Boolean flag to indicate whether to use own Frame Sync(false) OR to + * use frame sync of other half SPORT (true). + * \n + * \n true : Use frame sync of other half SPORT device. + * \n + * \n false : Use own frame sync. + * + * @param [in] bUseOtherClk Boolean flag to indicate whether to use own clock clock(false) OR to + * use clock of other half SPORT(true). + * \n + * \n true : Use clock of other half SPORT device. + * \n + * \n false : Use own clock. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully enabled the specified SPORT to use the clk + * and FS of other half SPORT. + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * - #ADI_SPORT_OPERATION_NOT_ALLOWED [D] Operation is not allowed when data flow is enabled. + * + */ +ADI_SPORT_RESULT adi_sport_MultiplexSportSignal(ADI_SPORT_HANDLE const hDevice, + const bool bUseOtherFS, + const bool bUseOtherClk) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *)hDevice; /* Pointer to SPORT device instance */ +#ifdef ADI_DEBUG + if((result = ValidateHandle(pDevice)) != ADI_SPORT_SUCCESS) /* Validate the given handle */ + { + } + else if (pDevice->pSportInfo->eState == ADI_SPORT_STATE_DATA_FLOW_ENABLED) + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else +#endif /* ADI_DEBUG */ + { + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; + uint32_t ctl = pSportCfg->CTL; + + /* clear the muxing fields of the control register 2 */ + ctl &= (uint32_t)(~(BITM_SPORT_CTL_A_CKMUXSEL | BITM_SPORT_CTL_A_FSMUXSEL)); + if (true == bUseOtherFS) + { + ctl |= BITM_SPORT_CTL_A_FSMUXSEL; /* Use the the frame sync of other half sport*/ + } + if(bUseOtherClk == true) + { + ctl |= BITM_SPORT_CTL_A_CKMUXSEL; /* Use the the clock of other half sport*/ + } + pSportCfg->CTL = ctl; /* CTL value set - CTL_A is assigned when submitting a buffer */ + + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); + } + + return result; +} +/** + * @brief Configure the SPORT use the Clocks and Frame Sync of other Half-Sport + * + * @param [in] hDevice Device handle to SPORT device. + * + * @param [in] nFSDuration Specify the value of the number of clocks which would be programmed corresponding to the + * desired time duration from assertion of CONVT signal to Frame sync signal + * + * @param [in] nWidth Specify the value of the number of serial clocks for which CONVT signal should be active. + + * + * @param [in] bActiveLow Boolean flag to indicate the polarity of the Convt signal. + * \n + * \n true : Active low Polarity. + * \n + * \n false : Active High Polarity. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully enabled the specified SPORT to use the clk + * and FS of other half SPORT. + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * - #ADI_SPORT_OPERATION_NOT_ALLOWED [D] Operation is not allowed when data flow is enabled. + * + */ +ADI_SPORT_RESULT adi_sport_ConfigTimerMode(ADI_SPORT_HANDLE const hDevice, + const uint8_t nFSDuration, + const uint8_t nWidth, + const bool bActiveLow) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) hDevice; /* Pointer to SPORT device instance */ + +#ifdef ADI_DEBUG /* Validate the given handle */ + if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice))) + { + } + else if (ADI_SPORT_STATE_DATA_FLOW_ENABLED == pDevice->pSportInfo->eState) + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else +#endif /* ADI_DEBUG */ + { + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; + uint32_t cnvt = pSportCfg->TIM_CONVT; + + /* clear the muxing fields of the control register 2 */ + cnvt &= (uint32_t)(~(BITM_SPORT_CNVT_A_POL | BITM_SPORT_CNVT_A_WID | BITM_SPORT_CNVT_A_CNVT2FS )); + cnvt |= (((uint32_t) nFSDuration << ((uint32_t) BITP_SPORT_CNVT_A_CNVT2FS)) | ((uint32_t) nWidth)); + if(bActiveLow == true) + { + cnvt |= ((uint32_t) BITM_SPORT_CNVT_A_POL); /* Use the the clock of other half sport*/ + } + pDevice->pSportInfo->pSportRegs->CNVT_A = pSportCfg->TIM_CONVT = cnvt; + } + return result; +} + +/*! \cond PRIVATE */ + +/** + * @brief Create a circular linked list for buffer management. + * + * @details Create a circular linked list for buffer management and + * initialize the free buffer, the fill buffer and he active + * buffer with the first buffer in this circular array. + * + * @param [in] hDevice Device handle to SPORT device. + * + * @param [in] NumDesc Number of descriptorS. + * + */ +static inline void sport_Init (ADI_SPORT_DEVICE *pDevice) +{ + uint32_t i; + ADI_DT_CHANNEL *pChannel = &pDevice->sportChannel; + ADI_DT_BUFF_INFO *pBufInfo = &pChannel->BufInfo[0]; /* initialize this variable with the first array element */ + ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo; /* short cut to SPORT information */ + ADI_SPORT_CONFIG * pSportCfg = &pSportInfo->sportCfg; /* short cut to SPORT configuration */ + const uint32_t bytesPerData = GetBytesPerSportData(pSportCfg->CTL); /* number of bytes in SPORT data (1, 2, or 4) */ + const uint32_t packMode = SPORT_GET_PACKEN(pSportCfg->CTL); /* SPORT data pack mode */ + + /* Initialize the all descriptors. Make it circular. */ + for(i = 0u; i < ADI_DT_BUFNUM; i++) + { + pBufInfo[i].pStartAddress = NULL; + pBufInfo[i].nCount = 0u; + pBufInfo[i].nIndex = 0u; + pBufInfo[i].pNextBuffer = &pBufInfo[(i+1u) % ADI_DT_BUFNUM]; /* link the buffers in a circular way */ + } + pChannel->pFreeBuffer = &pChannel->BufInfo[0u]; /* the first free buffer is the first array element */ + pChannel->pActiveBuffer = &pChannel->BufInfo[0u]; /* the first active buffer is the first array element */ + pChannel->pFillBuffer = &pChannel->BufInfo[0u]; /* the first fill buffer is the first array element */ + + switch (bytesPerData) + { + case 1u: + if (SPORT_BIT_PACK_8 == packMode) + { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE; + } else { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_1_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_1_BYTE; + + assert(SPORT_BIT_PACK_NONE == packMode); + } + break; + + case 2u: + if (SPORT_BIT_PACK_16 == packMode) + { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE; + } else { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_2_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_2_BYTE; + + assert(SPORT_BIT_PACK_NONE == packMode); + } + break; + + default: + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE; + assert((4u == bytesPerData) || (SPORT_BIT_PACK_NONE == packMode)); + break; + } +} + +/* + * @brief Configure the registers with the half-SPORT + * + * @param [in] hDevice Device handle to SPORT device. + * @param [in] sportCfg SPORT configuration to be used. + * + * @return None + */ +static inline void sport_Configure (ADI_SPORT_DEVICE *pDevice, ADI_SPORT_CONFIG const * sportCfg) +{ + /* Configure the SPORT device using static configuration parameters. + * pSportInfo is mapped to one of the half-SPORT available; this is the + * half-SPORT configured. (CTL_A, DIV_A, CNVT_A and NUMTRAN_A map either + * to half-SPORT A registers or half-SPORT B registers, depending on + * sportRegs.) + */ + volatile ADI_SPORT_TypeDef * sportRegs = pDevice->pSportInfo->pSportRegs; + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; + + /* record the SPORT default configuration */ + memcpy(pSportCfg, sportCfg, sizeof(ADI_SPORT_CONFIG)); + + switch (pDevice->eDirection) /* Set the direction of operation */ + { + case ADI_SPORT_DIR_RX: + pSportCfg->CTL &= ~BITM_SPORT_CTL_A_SPTRAN; + break; + case ADI_SPORT_DIR_TX: + pSportCfg->CTL |= BITM_SPORT_CTL_A_SPTRAN; + break; + default: + assert(0); + break; + } + /* use the SPORT configuration to setup the SPORT registers */ + sportRegs->CTL_A = pSportCfg->CTL; + sportRegs->DIV_A = pSportCfg->DIV; + sportRegs->CNVT_A = pSportCfg->TIM_CONVT; + sportRegs->NUMTRAN_A = 0u; + + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); +} + +#ifdef ADI_DEBUG +static ADI_SPORT_RESULT ValidateHandle(ADI_SPORT_HANDLE const hDevice) +{ + ADI_SPORT_RESULT result = ADI_SPORT_INVALID_HANDLE; + ADI_SPORT_DEVICE * pInDevice = (ADI_SPORT_DEVICE*) hDevice; + ADI_SPORT_DEVICE_INFO *poDeviceInfo = &gSportDevInfo[0][0]; + uint32_t i; + + /* Pointer to SPORT device instance */ + for (i=0u; i<(ADI_SPORT_NUM_INSTANCES << 1u); i++) /* 2 half-devices per SPORT */ + { + if (pInDevice == poDeviceInfo->hDevice) + { + result = ADI_SPORT_SUCCESS; + break; + } + poDeviceInfo++; + } + return result; +} +#endif /* ADI_DEBUG */ + +/* mask for events to be recorded in the driver HW error */ +#define recEvt ((uint32_t) (BITM_SPORT_STAT_A_SYSDATERR | BITM_SPORT_STAT_A_FSERR | BITM_SPORT_STAT_A_DERR)) + +/* bits to be cleared by the ISR */ +#define clrEvt ((recEvt | BITM_SPORT_STAT_A_TFI)) + +static void sport_Terminate(ADI_SPORT_DEVICE * pDevice) +{ + ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo; /* get SPORT device information */ + volatile ADI_SPORT_TypeDef * pRegs = pSportInfo->pSportRegs; /* access SPORT registers */ + + ADI_DT_CHANNEL * pSportChnl = &pDevice->sportChannel; + ADI_DT_BUFF_INFO * pBuff = pSportChnl->pFillBuffer; + + pRegs->CTL_A &= ~BITM_SPORT_CTL_A_SPEN; /* disable SPORT */ + pRegs->IEN_A &= ~(BITM_SPORT_IEN_A_TF | BITM_SPORT_IEN_A_DATA); /* disable SPORT interrupts */ + pRegs->NUMTRAN_A = 0u; + +#ifdef ADI_DEBUG + { + /* ============================================= */ + /* Check the number of data transmitted/received */ + /* nIndex is incremented each time a data packed */ + /* or unpacked in received. The size in bytes of */ + /* each data depends on the SPORT configuration. */ + /* In core driven operations, nCount represents */ + /* the number of 32-bit words transmitted. */ + /* In DMA driven operations, nCount represents */ + /* the number of DMA data transmitted */ + /* ============================================= */ + const uint32_t ctl = pRegs->CTL_A; + const uint32_t bytesPerData = GetBytesPerSportData(ctl); + const uint32_t nIndex = pBuff->nIndex * (4u / bytesPerData); + assert((nIndex>=pBuff->nCount)||(true==pBuff->bDMA)); /* buffer must be fully processed */ + } +#endif + + pBuff->bInUse = false; /* mark buffer as ready */ + + NVIC_DisableIRQ(pSportInfo->eIRQn); /* suspend SPORT Interrupt */ + NVIC_DisableIRQ(pSportInfo->eDMAn); /* suspend SPORT DMA interrupt */ + + pDevice->pSportInfo->eState = ADI_SPORT_STATE_PAUSED; + + if(NULL != pDevice->pfCallback) /* Call the callback function if one is registered. */ + { + uint32_t evt = ( (ADI_SPORT_DIR_RX == pDevice->eDirection) + ? ((uint32_t) ADI_SPORT_EVENT_RX_BUFFER_PROCESSED) + : ((uint32_t) ADI_SPORT_EVENT_TX_BUFFER_PROCESSED) + ); + + pDevice->pfCallback(pDevice->pCBParam,evt,pBuff->pStartAddress); + pBuff->pStartAddress = NULL; /* No need to keep the processed buffer address */ + } + else + { + SEM_POST(pSportChnl); /* signal the buffer availability through a semaphore */ + } + pRegs->STAT_A = clrEvt; /* clear status register bits (W1C) */ + pSportChnl->eDataTranferMode = ADI_DT_MODE_NONE; /* SPORT is available */ + pBuff = pBuff->pNextBuffer; /* point to the next buffer to process */ + pSportChnl->pFillBuffer = pBuff; /* this is the new pFillBuffer */ + + if ((0u != pBuff->pStartAddress) && (true == pBuff->bInUse)) /* valid buffer not being processed yet */ + { + ADI_SPORT_RESULT result; + + pSportChnl->eDataTranferMode = ADI_DT_MODE_NONBLOCKING; + if (true == pBuff->bDMA) + { + result = sport_SubmitBufferDmaMode(pDevice, pBuff); + } + else + { + result = sport_SubmitBufferIntMode(pDevice, pBuff); + } + + if(ADI_SPORT_SUCCESS != result) /* if an error occurred...*/ + { + pSportChnl->eDataTranferMode = ADI_DT_MODE_NONE; /* SPORT is available */ + } + } +} + +/* + * @brief Common SPORT interrupt handler function called by SPORT0 A and SPORT0 B ISRs. + * + * @details Process SPORT0 A and B interrupts, recording HW errors that must be reported, + * reading/writing transmitted data, launching new SPORT transmissions if more + * buffers are to be processed, and deactivating the SPORT device if there are + * no pending requests. (Common fucntion for both core driven and DMA driven + * SPORT operations.) + * + * @param [in] pDevice Sport device pointer related to the calling ISR. + */ +static void sport_InterruptHandler(ADI_SPORT_DEVICE * pDevice) +{ + ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo; /* get SPORT device information */ + volatile ADI_SPORT_TypeDef * pRegs = pSportInfo->pSportRegs; /* access SPORT registers */ + const uint32_t sportStatus = pRegs->STAT_A; /* read SPORT status */ + const uint32_t dataRequest = (sportStatus & BITM_SPORT_STAT_A_DATA);/* set if any data to be processed by the SPORT */ + const uint32_t hwEvents = sportStatus & recEvt; /* HW events to be recorded in the driver */ + + + /* This implementation assumes an identity mapping between BITM_SPORT_STAT values + * and their equivalent event in ADI_SPORT_EVENT, e.g. ADI_SPORT_HW_ERR_FS and + * BITM_SPORT_STAT_A_FSERR share the same value. This simplifies event processing + * and reports. */ + assert(((uint32_t) ADI_SPORT_HW_ERR_RX_OVERFLOW) == BITM_SPORT_STAT_A_DERR); + assert(((uint32_t) ADI_SPORT_HW_ERR_TX_UNDERFLOW) == BITM_SPORT_STAT_A_DERR); + assert(((uint32_t) ADI_SPORT_HW_ERR_FS) == BITM_SPORT_STAT_A_FSERR); + assert(((uint32_t) ADI_SPORT_HW_ERR_SYSDATAERR) == BITM_SPORT_STAT_A_SYSDATERR); + + if (0u != hwEvents) /* any event recorded? */ + { + if (NULL != pDevice->pfCallback) /* if a callback has been registered ? */ + { + pDevice->pfCallback(pDevice->pCBParam,hwEvents,NULL); /* then call it */ + } else { + pDevice->nHwError |= hwEvents; /* else set the driver HW error */ + SEM_POST(&pDevice->sportChannel); /* and signal this through a semaphore */ + } + } + + if (0u != dataRequest) /* Tx FIFO is not full or Rx FIFO is not empty */ + { + ADI_DT_BUFF_INFO * pBuff = pDevice->sportChannel.pFillBuffer; + uint32_t * pNextWord = (uint32_t*) pBuff->pStartAddress; + + if ((NULL != pNextWord) && (pBuff->nIndex < pBuff->nCount)) /* This buffer has not been fully processed yet */ + { + if (ADI_SPORT_DIR_RX == pDevice->eDirection) + { + pNextWord[pBuff->nIndex++] = pRegs->RX_A; /* Read the data received in RX and increment the index */ + while (!DXS_FIFO_IS_EMPTY(pRegs->STAT_A)) /* and if there are more data available in the FIFO */ + { + pNextWord[pBuff->nIndex++] = pRegs->RX_A; /* Read remaining data received in RX and increment the index */ + } + } + else + { + pRegs->TX_A = pNextWord[pBuff->nIndex++]; /* Write the data to be sent into TX and increment the index */ + while ( (pBuff->nIndex < pBuff->nCount) /* and if there are more data to be sent */ + && (!DXS_FIFO_IS_FULL(pRegs->STAT_A)) /* and there is still room in the FIFO */ + ) + { + pRegs->TX_A = pNextWord[pBuff->nIndex++]; /* then write more data to be sent into TX and increment the index */ + } + } + } + } + + /* ========================================================== */ + /* Common to core driven operations and DMA driven operations */ + /* ========================================================== */ + if (0u != (pRegs->STAT_A & BITM_SPORT_STAT_A_TFI)) /* If a SPORT Tx/Rx request has finished */ + { + sport_Terminate(pDevice); + } + +#if defined(ADI_CYCLECOUNT_SPORT_ISR_ENABLED) && (ADI_CYCLECOUNT_SPORT_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPORT); +#endif +} + +/** Interrupt handler for SPORT0 A */ +void SPORT0A_Int_Handler(void) +{ + ISR_PROLOG(); + sport_InterruptHandler(gSportDevInfo[0][ADI_HALF_SPORT_A].hDevice); + ISR_EPILOG(); +} + +/** Interrupt handler for SPORT0 B */ +void SPORT0B_Int_Handler(void) +{ + ISR_PROLOG(); + sport_InterruptHandler(gSportDevInfo[0][ADI_HALF_SPORT_B].hDevice); + ISR_EPILOG(); +} + +void DMA_SPORT0A_Int_Handler(void) +{ + ISR_PROLOG(); + /** + * if SPORT is in Rx mode, then the DMA interrupt is the signal for + * end of transmission: buffer is ready. (In Tx mode, the signal is + * the TFI event and SPORT DMA interrup is not enabled). + */ + sport_Terminate(gSportDevInfo[0][ADI_HALF_SPORT_A].hDevice); +#if defined(ADI_CYCLECOUNT_SPORT_ISR_ENABLED) && (ADI_CYCLECOUNT_SPORT_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPORT); +#endif + ISR_EPILOG(); +} + +void DMA_SPORT0B_Int_Handler(void) +{ + ISR_PROLOG(); + /** + * if SPORT is in Rx mode, then the DMA interrupt is the signal for + * end of transmission: buffer is ready. (In Tx mode, the signal is + * the TFI event and SPORT DMA interrup is not enabled). + */ + sport_Terminate(gSportDevInfo[0][ADI_HALF_SPORT_B].hDevice); +#if defined(ADI_CYCLECOUNT_SPORT_ISR_ENABLED) && (ADI_CYCLECOUNT_SPORT_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPORT); +#endif + ISR_EPILOG(); +} + +static void sport_DmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) +{ + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) pCBParam; /* Recover the device handle. */ + ADI_DT_BUFF_INFO * pFillBuffer = pDevice->sportChannel.pFillBuffer; + ADI_DT_BUFF_INFO * pNextBuffer = pFillBuffer->pNextBuffer; + uint32_t nEvent = 0u; + + if (ADI_DMA_EVENT_ERR_BUS == Event) + { + nEvent = (uint32_t) ADI_SPORT_DMA_ERR_BUS; /* SPORT DMA bus error detected */ + } else { + assert(ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR == Event); + nEvent = (uint32_t) ADI_SPORT_DMA_ERR_INVALID_DESCRIPTOR; /* SPORT DMA invalid descriptor error detected */ + } + + pDevice->nHwError |= nEvent; + sport_InterruptHandler(pDevice); + + while ( (NULL != pNextBuffer->pStartAddress) + && (true == pNextBuffer->bInUse) + && (true == pNextBuffer->bDMA) + ) /* another buffer is pending for a DMA driven request */ + { + pDevice->nHwError |= nEvent; + pNextBuffer->bInUse = false; + sport_InterruptHandler(pDevice); + pNextBuffer = pNextBuffer->pNextBuffer; + } +} + +static inline uint32_t GetBytesPerSportData(const uint32_t ctlVal) +{ + const uint32_t wlen = SPORT_GET_WLEN(ctlVal); + const uint32_t bytesPerData = ((wlen < 9u) ? (1u) : ((wlen < 17u) ? (2u) : (4u))); + return bytesPerData; +} + +/*! \endcond */ + +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport_def.h new file mode 100755 index 0000000000..7244562e9a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport_def.h @@ -0,0 +1,193 @@ +/*! ***************************************************************************** + * @file: adi_sport_def.h + * @brief: UART Device Driver definition for processor + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +/*! \cond PRIVATE */ +#ifndef ADI_SPORT_DEF_H +#define ADI_SPORT_DEF_H + +#include + +#if defined(ADI_CFG_SPORT0A_SERIAL_WLEN) +#if (ADI_CFG_SPORT0A_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0A_SERIAL_WLEN > 32u) +#error "Invalid word length : it must be between 4 and 32" +#endif +#else +#error "ADI_CFG_SPORT0A_SERIAL_WLEN undefined!!! " +#endif + +#if defined(ADI_CFG_SPORT0B_SERIAL_WLEN) +#if (ADI_CFG_SPORT0B_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0B_SERIAL_WLEN > 32u) +#error "Invalid word length : it must be between 4 and 32" +#endif +#else +#error "ADI_CFG_SPORT0B_SERIAL_WLEN undefined!!! " +#endif + +#define ADI_SPORT_NUM_INSTANCES (1u) /*!< Number of SPORT devices available */ +#define ADI_SPORT_NUM_CHANNELS (2u) /*!< Number of SPORT channel for each SPORT devcie */ + +#define BITM_SPORT_DATA_CONFIG ( BITM_SPORT_CTL_A_LSBF \ + | BITM_SPORT_CTL_A_PACK) + +#define BITM_SPORT_CLOCK_CONFIG ( BITM_SPORT_CTL_A_ICLK \ + | BITM_SPORT_CTL_A_CKRE \ + | BITM_SPORT_CTL_A_GCLKEN) + +#define BITM_SPORT_FS_CONFIG ( BITM_SPORT_CTL_A_FSR \ + | BITM_SPORT_CTL_A_IFS \ + | BITM_SPORT_CTL_A_DIFS \ + | BITM_SPORT_CTL_A_LFS \ + | BITM_SPORT_CTL_A_LAFS \ + | BITM_SPORT_CTL_A_FSERRMODE) + +#define SPORT_BYTE_TRANSFER_LENGTH (8u) +#define SPORT_HALFWORD_TRANSFER_LENGTH (16u) +#define SPORT_WORD_TRANSFER_LENGTH (32u) + +#define SPORT_GET_WLEN(ctlVal) ((((ctlVal) & (uint32_t) BITM_SPORT_CTL_A_SLEN) >> ((uint32_t) BITP_SPORT_CTL_A_SLEN)) + 1u) +#define SPORT_GET_PACKEN(ctlVal) ((ctlVal) & (uint32_t) BITM_SPORT_CTL_A_PACK) >> ((uint32_t) BITP_SPORT_CTL_A_PACK) + +#define SPORT_CHECK_CFG_CTL(CFG) assert(0u == ((CFG) & (((uint32_t)BITM_SPORT_CTL_A_SPEN) | ((uint32_t)BITM_SPORT_CTL_A_DMAEN)))) + + +#define SPORT_BIT_PACK_NONE (((uint32_t) ADI_SPORT_NO_PACKING) >> ((uint32_t) BITP_SPORT_CTL_A_PACK)) +#define SPORT_BIT_PACK_8 (((uint32_t) ADI_SPORT_8BIT_PACKING) >> ((uint32_t) BITP_SPORT_CTL_A_PACK)) +#define SPORT_BIT_PACK_16 (((uint32_t) ADI_SPORT_16BIT_PACKING) >> ((uint32_t) BITP_SPORT_CTL_A_PACK)) + +/*! + ***************************************************************************** + * \struct ADI_SPORT_STATE + * Enumeration of different SPORT states. + *****************************************************************************/ +typedef enum +{ + ADI_SPORT_STATE_UNINITIALIZED = 0, /*!< SPORT is not yet initialized */ + ADI_SPORT_STATE_INITIALIZED, /*!< SPORT is initialized */ + ADI_SPORT_STATE_DATA_FLOW_ENABLED, /*!< SPORT Tx or Rx data flow is enabled (SPORT peripheral cannot be re-configured) */ + ADI_SPORT_STATE_DATA_FLOW_DISABLED, /*!< SPORT Tx or Rx data flow is disabled (SPORT peripheral can be re-configured) */ + ADI_SPORT_STATE_PAUSED +} ADI_SPORT_STATE; + +/*! + ***************************************************************************** + * \struct ADI_SPORT_CONFIG + * Structure for initializing the static config. + *****************************************************************************/ + +typedef struct _ADI_SPORT_CONFIG +{ + uint32_t CTL; /*!< SPORT_CTL register. */ + uint32_t DIV; /*!< SPORT_DIV register. */ + uint32_t TIM_CONVT; /*!< TIM_CONVT Register. */ + uint32_t DMA_WIDTH; /*!< DMA_WIDTH */ + uint32_t DMA_INC; /*!< DMA_INC */ +} ADI_SPORT_CONFIG; + +/*! + ***************************************************************************** + * \struct ADI_SPORT_DEVICE_INFO + * SPORT device information. + *****************************************************************************/ +typedef struct _ADI_SPORT_DEVICE_INFO +{ + volatile ADI_SPORT_TypeDef* pSportRegs; /*!< Base address of the SPORT registers */ + ADI_SPORT_CONFIG sportCfg; /*!< SPORT configuration data */ + ADI_SPORT_STATE eState; /*!< To indicate the state of the device */ + const DMA_CHANn_TypeDef eDMAChnlID; /*!< DMA channel ID */ + const IRQn_Type eDMAn; /*!< DMA channel IRQ identifier */ + const IRQn_Type eIRQn; /*!< SPORT IRQ identifier */ + ADI_SPORT_HANDLE hDevice; /*!< SPORT handle */ +} ADI_SPORT_DEVICE_INFO; + +/****************************************************************************** + * SPORT Device internal API function prototypes + *****************************************************************************/ + +#define NUM_SPORT_BUFFER (2u) + +/** SPORT driver instance data */ +typedef struct _ADI_SPORT_DEVICE +{ + ADI_SPORT_DEVICE_INFO * pSportInfo; /*!< pointer to the structure which stores the information about the SPORT instances.*/ + ADI_SPORT_DIRECTION eDirection; /*!< Direction in which the SPORT is opened */ + ADI_CALLBACK pfCallback; /*!< Function pointer for callback function. */ + void * pCBParam; /*!< Parameter to callback function. */ + ADI_DT_CHANNEL sportChannel; /*!< SPORT channel to manage transmitted data buffers */ + volatile uint32_t nHwError; /*!< variable to store the hardware status */ +} ADI_SPORT_DEVICE; + +/** Initialize a SPORT device */ +static inline void sport_Init (ADI_SPORT_DEVICE * pDevice); + +/** Configure a SPORT device */ +static inline void sport_Configure (ADI_SPORT_DEVICE *pDevice, ADI_SPORT_CONFIG const * sportCfg); + +/** Function prototype for submitting a buffer for SPORT Rx or Tx DMA driven transmission */ +static ADI_SPORT_RESULT sport_SubmitBufferDmaMode(ADI_SPORT_DEVICE * pDevice, ADI_DT_BUFF_INFO * pBuff); + +/** Function prototype for submitting a buffer for SPORT Rx or Tx core driven transmission */ +static ADI_SPORT_RESULT sport_SubmitBufferIntMode(ADI_SPORT_DEVICE * pDevice, ADI_DT_BUFF_INFO * pBuff); + +/** Fucntion prototype for completing a SPORT transmission (Rx or Tx) */ +static void sport_Terminate(ADI_SPORT_DEVICE * pDevice); + +/** Interrupt Handlers */ + +/** SPORT interrupt handler */ +static void sport_InterruptHandler(ADI_SPORT_DEVICE * pDevice); + +static inline void sport_DmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg); + +static inline uint32_t GetBytesPerSportData(const uint32_t ctlVal); + +/* + * Handle Validation function +*/ +#ifdef ADI_DEBUG +static ADI_SPORT_RESULT ValidateHandle(ADI_SPORT_HANDLE const hDevice); +#endif /* ADI_DEBUG */ + +#endif /* end of ifndef ADI_SPORT_DEF_H */ +/*! \endcond */ + + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050.h new file mode 100755 index 0000000000..d2a7a908a4 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050.h @@ -0,0 +1,5339 @@ +/* ================================================================================ + + Project : ADuCM4050 + File : ADuCM4050.h + Description : Register Definitions + + Date : Feb 7, 2017 + + Copyright (c) 2014-2017 Analog Devices, Inc. All Rights Reserved. + This software is proprietary and confidential to Analog Devices, Inc. and + its licensors. + + This file was auto-generated. Do not make local changes to this file. + + ================================================================================ */ + +#ifndef _DEF_ADUCM4050_H +#define _DEF_ADUCM4050_H + +#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include +#endif /* _LANGUAGE_C */ + + +#if defined (_MISRA_RULES) +#pragma diag(push) +#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit") +#pragma diag(suppress:misra_rule_19_7:"ADI header allows function-like macros") +#pragma diag(suppress:misra_rule_19_13:"ADI headers can use the # and ## preprocessor operators") +#endif /* _MISRA_RULES */ + +/* _ADI_MSK_3 might be defined in wrapper includes - otherwise provide a default */ +#if !defined(_ADI_MSK_3) +/* do not add casts to literal constants in assembly code */ +#if defined(_LANGUAGE_ASM) || defined(__ASSEMBLER__) +/* Use unsuffixed literals for BITM macros */ +#define _ADI_MSK_3( mask, smask, type ) (mask) +#else +/* Use casted suffixed literals for BITM macros */ +#define _ADI_MSK_3( mask, smask, type ) ((type)(smask)) +#endif +#endif + +#ifndef __ADI_GENERATED_DEF_HEADERS__ +#define __ADI_GENERATED_DEF_HEADERS__ 1 +#endif + +#define __ADI_HAS_ADC__ 1 +#define __ADI_HAS_BEEP__ 1 +#define __ADI_HAS_BUSM__ 1 +#define __ADI_HAS_CLKG_OSC__ 1 +#define __ADI_HAS_CLKG__ 1 +#define __ADI_HAS_CLKG_CLK__ 1 +#define __ADI_HAS_CRC__ 1 +#define __ADI_HAS_CRYPT__ 1 +#define __ADI_HAS_DMA__ 1 +#define __ADI_HAS_XINT__ 1 +#define __ADI_HAS_FLCC__ 1 +#define __ADI_HAS_FLCC_CACHE__ 1 +#define __ADI_HAS_FLCC_DFT__ 1 +#define __ADI_HAS_FLCC_TEST__ 1 +#define __ADI_HAS_GPIO__ 1 +#define __ADI_HAS_TMR__ 1 +#define __ADI_HAS_I2C__ 1 +#define __ADI_HAS_NVIC__ 1 +#define __ADI_HAS_PMG__ 1 +#define __ADI_HAS_PMG_TST__ 1 +#define __ADI_HAS_PTI__ 1 +#define __ADI_HAS_RNG__ 1 +#define __ADI_HAS_RTC__ 1 +#define __ADI_HAS_SPI__ 1 +#define __ADI_HAS_SPORT__ 1 +#define __ADI_HAS_SYS__ 1 +#define __ADI_HAS_TMR_RGB__ 1 +#define __ADI_HAS_UART__ 1 +#define __ADI_HAS_WDT__ 1 + +/* ============================================================================================================================ + General Purpose Timer + ============================================================================================================================ */ + +/* ============================================================================================================================ + TMR0 + ============================================================================================================================ */ +#define REG_TMR0_LOAD 0x40000000 /* TMR0 16-bit Load Value */ +#define REG_TMR0_CURCNT 0x40000004 /* TMR0 16-bit Timer Value */ +#define REG_TMR0_CTL 0x40000008 /* TMR0 Control */ +#define REG_TMR0_CLRINT 0x4000000C /* TMR0 Clear Interrupt */ +#define REG_TMR0_CAPTURE 0x40000010 /* TMR0 Capture */ +#define REG_TMR0_ALOAD 0x40000014 /* TMR0 16-bit Load Value, Asynchronous */ +#define REG_TMR0_ACURCNT 0x40000018 /* TMR0 16-bit Timer Value, Asynchronous */ +#define REG_TMR0_STAT 0x4000001C /* TMR0 Status */ +#define REG_TMR0_PWMCTL 0x40000020 /* TMR0 PWM Control Register */ +#define REG_TMR0_PWMMATCH 0x40000024 /* TMR0 PWM Match Value */ +#define REG_TMR0_EVENTSELECT 0x40000028 /* TMR0 Timer Event Selection Register */ + +/* ============================================================================================================================ + TMR1 + ============================================================================================================================ */ +#define REG_TMR1_LOAD 0x40000400 /* TMR1 16-bit Load Value */ +#define REG_TMR1_CURCNT 0x40000404 /* TMR1 16-bit Timer Value */ +#define REG_TMR1_CTL 0x40000408 /* TMR1 Control */ +#define REG_TMR1_CLRINT 0x4000040C /* TMR1 Clear Interrupt */ +#define REG_TMR1_CAPTURE 0x40000410 /* TMR1 Capture */ +#define REG_TMR1_ALOAD 0x40000414 /* TMR1 16-bit Load Value, Asynchronous */ +#define REG_TMR1_ACURCNT 0x40000418 /* TMR1 16-bit Timer Value, Asynchronous */ +#define REG_TMR1_STAT 0x4000041C /* TMR1 Status */ +#define REG_TMR1_PWMCTL 0x40000420 /* TMR1 PWM Control Register */ +#define REG_TMR1_PWMMATCH 0x40000424 /* TMR1 PWM Match Value */ +#define REG_TMR1_EVENTSELECT 0x40000428 /* TMR1 Timer Event Selection Register */ + +/* ============================================================================================================================ + TMR2 + ============================================================================================================================ */ +#define REG_TMR2_LOAD 0x40000800 /* TMR2 16-bit Load Value */ +#define REG_TMR2_CURCNT 0x40000804 /* TMR2 16-bit Timer Value */ +#define REG_TMR2_CTL 0x40000808 /* TMR2 Control */ +#define REG_TMR2_CLRINT 0x4000080C /* TMR2 Clear Interrupt */ +#define REG_TMR2_CAPTURE 0x40000810 /* TMR2 Capture */ +#define REG_TMR2_ALOAD 0x40000814 /* TMR2 16-bit Load Value, Asynchronous */ +#define REG_TMR2_ACURCNT 0x40000818 /* TMR2 16-bit Timer Value, Asynchronous */ +#define REG_TMR2_STAT 0x4000081C /* TMR2 Status */ +#define REG_TMR2_PWMCTL 0x40000820 /* TMR2 PWM Control Register */ +#define REG_TMR2_PWMMATCH 0x40000824 /* TMR2 PWM Match Value */ +#define REG_TMR2_EVENTSELECT 0x40000828 /* TMR2 Timer Event Selection Register */ + +/* ============================================================================================================================ + TMR Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_LOAD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_LOAD_VALUE 0 /* Load Value */ +#define BITM_TMR_LOAD_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Load Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_CURCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_CURCNT_VALUE 0 /* Current Count */ +#define BITM_TMR_CURCNT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Current Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_CTL_SYNCBYP 15 /* Synchronization Bypass */ +#define BITP_TMR_CTL_RSTEN 14 /* Counter and Prescale Reset Enable */ +#define BITP_TMR_CTL_EVTEN 13 /* Event Select */ +#define BITP_TMR_CTL_RLD 7 /* Reload Control */ +#define BITP_TMR_CTL_CLK 5 /* Clock Select */ +#define BITP_TMR_CTL_EN 4 /* Timer Enable */ +#define BITP_TMR_CTL_MODE 3 /* Timer Mode */ +#define BITP_TMR_CTL_UP 2 /* Count up */ +#define BITP_TMR_CTL_PRE 0 /* Prescaler */ +#define BITM_TMR_CTL_SYNCBYP (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Synchronization Bypass */ +#define BITM_TMR_CTL_RSTEN (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Counter and Prescale Reset Enable */ +#define BITM_TMR_CTL_EVTEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Event Select */ +#define BITM_TMR_CTL_RLD (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Reload Control */ +#define BITM_TMR_CTL_CLK (_ADI_MSK_3(0x00000060,0x00000060U, uint16_t )) /* Clock Select */ +#define BITM_TMR_CTL_EN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Timer Enable */ +#define BITM_TMR_CTL_MODE (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Timer Mode */ +#define BITM_TMR_CTL_UP (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Count up */ +#define BITM_TMR_CTL_PRE (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Prescaler */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_CLRINT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_CLRINT_EVTCAPT 1 /* Clear Captured Event Interrupt */ +#define BITP_TMR_CLRINT_TIMEOUT 0 /* Clear Timeout Interrupt */ +#define BITM_TMR_CLRINT_EVTCAPT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Clear Captured Event Interrupt */ +#define BITM_TMR_CLRINT_TIMEOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Clear Timeout Interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_CAPTURE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_CAPTURE_VALUE 0 /* 16-bit Captured Value */ +#define BITM_TMR_CAPTURE_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* 16-bit Captured Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_ALOAD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_ALOAD_VALUE 0 /* Load Value, Asynchronous */ +#define BITM_TMR_ALOAD_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Load Value, Asynchronous */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_ACURCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_ACURCNT_VALUE 0 /* Counter Value */ +#define BITM_TMR_ACURCNT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Counter Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_STAT_CNTRST 8 /* Counter Reset Occurring */ +#define BITP_TMR_STAT_PDOK 7 /* Clear Interrupt Register Synchronization */ +#define BITP_TMR_STAT_BUSY 6 /* Timer Busy */ +#define BITP_TMR_STAT_CAPTURE 1 /* Capture Event Pending */ +#define BITP_TMR_STAT_TIMEOUT 0 /* Timeout Event Occurred */ +#define BITM_TMR_STAT_CNTRST (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Counter Reset Occurring */ +#define BITM_TMR_STAT_PDOK (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Clear Interrupt Register Synchronization */ +#define BITM_TMR_STAT_BUSY (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Timer Busy */ +#define BITM_TMR_STAT_CAPTURE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Capture Event Pending */ +#define BITM_TMR_STAT_TIMEOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Timeout Event Occurred */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_PWMCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_PWMCTL_IDLESTATE 1 /* PWM Idle State */ +#define BITP_TMR_PWMCTL_MATCH 0 /* PWM Match Enabled */ +#define BITM_TMR_PWMCTL_IDLESTATE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* PWM Idle State */ +#define BITM_TMR_PWMCTL_MATCH (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* PWM Match Enabled */ +#define ENUM_TMR_PWMCTL_IDLE_LOW (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* IDLESTATE: PWM idles low */ +#define ENUM_TMR_PWMCTL_IDLE_HIGH (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* IDLESTATE: PWM idles high */ +#define ENUM_TMR_PWMCTL_PWM_TOGGLE (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* MATCH: PWM in toggle mode */ +#define ENUM_TMR_PWMCTL_PWM_MATCH (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* MATCH: PWM in match mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_PWMMATCH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_PWMMATCH_VALUE 0 /* PWM Match Value */ +#define BITM_TMR_PWMMATCH_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* PWM Match Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_EVENTSELECT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_EVENTSELECT_EVTRANGE 0 /* Event Select Range */ +#define BITM_TMR_EVENTSELECT_EVTRANGE (_ADI_MSK_3(0x0000003F,0x0000003FU, uint16_t )) /* Event Select Range */ + + +/* ============================================================================================================================ + Timer_RGB with 3 PWM outputs + ============================================================================================================================ */ + +/* ============================================================================================================================ + TMR_RGB + ============================================================================================================================ */ +#define REG_TMR_RGB_LOAD 0x40000C00 /* TMR_RGB 16-bit load value */ +#define REG_TMR_RGB_CURCNT 0x40000C04 /* TMR_RGB 16-bit timer value */ +#define REG_TMR_RGB_CTL 0x40000C08 /* TMR_RGB Control */ +#define REG_TMR_RGB_CLRINT 0x40000C0C /* TMR_RGB Clear interrupt */ +#define REG_TMR_RGB_CAPTURE 0x40000C10 /* TMR_RGB Capture */ +#define REG_TMR_RGB_ALOAD 0x40000C14 /* TMR_RGB 16-bit load value, asynchronous */ +#define REG_TMR_RGB_ACURCNT 0x40000C18 /* TMR_RGB 16-bit timer value, asynchronous */ +#define REG_TMR_RGB_STAT 0x40000C1C /* TMR_RGB Status */ +#define REG_TMR_RGB_PWM0CTL 0x40000C20 /* TMR_RGB PWM0 Control Register */ +#define REG_TMR_RGB_PWM0MATCH 0x40000C24 /* TMR_RGB PWM0 Match Value */ +#define REG_TMR_RGB_EVENTSELECT 0x40000C28 /* TMR_RGB Timer Event selection Register */ +#define REG_TMR_RGB_PWM1CTL 0x40000C2C /* TMR_RGB PWM1 Control Register */ +#define REG_TMR_RGB_PWM1MATCH 0x40000C30 /* TMR_RGB PWM1 Match Value */ +#define REG_TMR_RGB_PWM2CTL 0x40000C34 /* TMR_RGB PWM2 Control Register */ +#define REG_TMR_RGB_PWM2MATCH 0x40000C38 /* TMR_RGB PWM2 Match Value */ + +/* ============================================================================================================================ + TMR_RGB Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_LOAD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_LOAD_VALUE 0 /* Load value */ +#define BITM_TMR_RGB_LOAD_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Load value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_CURCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_CURCNT_VALUE 0 /* Current count */ +#define BITM_TMR_RGB_CURCNT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Current count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_CTL_SYNCBYP 15 /* Synchronization bypass */ +#define BITP_TMR_RGB_CTL_RSTEN 14 /* Counter and prescale reset enable */ +#define BITP_TMR_RGB_CTL_EVTEN 13 /* Event select */ +#define BITP_TMR_RGB_CTL_RLD 7 /* Reload control */ +#define BITP_TMR_RGB_CTL_CLK 5 /* Clock select */ +#define BITP_TMR_RGB_CTL_EN 4 /* Timer enable */ +#define BITP_TMR_RGB_CTL_MODE 3 /* Timer mode */ +#define BITP_TMR_RGB_CTL_UP 2 /* Count up */ +#define BITP_TMR_RGB_CTL_PRE 0 /* Prescaler */ +#define BITM_TMR_RGB_CTL_SYNCBYP (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Synchronization bypass */ +#define BITM_TMR_RGB_CTL_RSTEN (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Counter and prescale reset enable */ +#define BITM_TMR_RGB_CTL_EVTEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Event select */ +#define BITM_TMR_RGB_CTL_RLD (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Reload control */ +#define BITM_TMR_RGB_CTL_CLK (_ADI_MSK_3(0x00000060,0x00000060U, uint16_t )) /* Clock select */ +#define BITM_TMR_RGB_CTL_EN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Timer enable */ +#define BITM_TMR_RGB_CTL_MODE (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Timer mode */ +#define BITM_TMR_RGB_CTL_UP (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Count up */ +#define BITM_TMR_RGB_CTL_PRE (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Prescaler */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_CLRINT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_CLRINT_EVTCAPT 1 /* Clear captured event interrupt */ +#define BITP_TMR_RGB_CLRINT_TIMEOUT 0 /* Clear timeout interrupt */ +#define BITM_TMR_RGB_CLRINT_EVTCAPT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Clear captured event interrupt */ +#define BITM_TMR_RGB_CLRINT_TIMEOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Clear timeout interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_CAPTURE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_CAPTURE_VALUE 0 /* 16-bit captured value */ +#define BITM_TMR_RGB_CAPTURE_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* 16-bit captured value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_ALOAD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_ALOAD_VALUE 0 /* Load value, asynchronous */ +#define BITM_TMR_RGB_ALOAD_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Load value, asynchronous */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_ACURCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_ACURCNT_VALUE 0 /* Counter value */ +#define BITM_TMR_RGB_ACURCNT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Counter value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_STAT_CNTRST 8 /* Counter reset occurring */ +#define BITP_TMR_RGB_STAT_PDOK 7 /* Clear Interrupt Register synchronization */ +#define BITP_TMR_RGB_STAT_BUSY 6 /* Timer Busy */ +#define BITP_TMR_RGB_STAT_CAPTURE 1 /* Capture event pending */ +#define BITP_TMR_RGB_STAT_TIMEOUT 0 /* Timeout event occurred */ +#define BITM_TMR_RGB_STAT_CNTRST (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Counter reset occurring */ +#define BITM_TMR_RGB_STAT_PDOK (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Clear Interrupt Register synchronization */ +#define BITM_TMR_RGB_STAT_BUSY (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Timer Busy */ +#define BITM_TMR_RGB_STAT_CAPTURE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Capture event pending */ +#define BITM_TMR_RGB_STAT_TIMEOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Timeout event occurred */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_PWM0CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_PWM0CTL_IDLESTATE 1 /* PWM Idle State */ +#define BITP_TMR_RGB_PWM0CTL_MATCH 0 /* PWM Match enabled */ +#define BITM_TMR_RGB_PWM0CTL_IDLESTATE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* PWM Idle State */ +#define BITM_TMR_RGB_PWM0CTL_MATCH (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* PWM Match enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_PWM0MATCH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_PWM0MATCH_VALUE 0 /* PWM Match Value */ +#define BITM_TMR_RGB_PWM0MATCH_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* PWM Match Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_EVENTSELECT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_EVENTSELECT_EVTRANGE 0 /* Event select range */ +#define BITM_TMR_RGB_EVENTSELECT_EVTRANGE (_ADI_MSK_3(0x0000003F,0x0000003FU, uint16_t )) /* Event select range */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_PWM1CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_PWM1CTL_IDLESTATE 1 /* PWM Idle State */ +#define BITP_TMR_RGB_PWM1CTL_MATCH 0 /* PWM Match enabled */ +#define BITM_TMR_RGB_PWM1CTL_IDLESTATE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* PWM Idle State */ +#define BITM_TMR_RGB_PWM1CTL_MATCH (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* PWM Match enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_PWM1MATCH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_PWM1MATCH_VALUE 0 /* PWM Match Value */ +#define BITM_TMR_RGB_PWM1MATCH_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* PWM Match Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_PWM2CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_PWM2CTL_IDLESTATE 1 /* PWM Idle State */ +#define BITP_TMR_RGB_PWM2CTL_MATCH 0 /* PWM Match enabled */ +#define BITM_TMR_RGB_PWM2CTL_IDLESTATE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* PWM Idle State */ +#define BITM_TMR_RGB_PWM2CTL_MATCH (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* PWM Match enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_PWM2MATCH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_PWM2MATCH_VALUE 0 /* PWM Match Value */ +#define BITM_TMR_RGB_PWM2MATCH_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* PWM Match Value */ + + +/* ============================================================================================================================ + Real-Time Clock + ============================================================================================================================ */ + +/* ============================================================================================================================ + RTC0 + ============================================================================================================================ */ +#define REG_RTC0_CR0 0x40001000 /* RTC0 RTC Control 0 */ +#define REG_RTC0_SR0 0x40001004 /* RTC0 RTC Status 0 */ +#define REG_RTC0_SR1 0x40001008 /* RTC0 RTC Status 1 */ +#define REG_RTC0_CNT0 0x4000100C /* RTC0 RTC Count 0 */ +#define REG_RTC0_CNT1 0x40001010 /* RTC0 RTC Count 1 */ +#define REG_RTC0_ALM0 0x40001014 /* RTC0 RTC Alarm 0 */ +#define REG_RTC0_ALM1 0x40001018 /* RTC0 RTC Alarm 1 */ +#define REG_RTC0_TRM 0x4000101C /* RTC0 RTC Trim */ +#define REG_RTC0_GWY 0x40001020 /* RTC0 RTC Gateway */ +#define REG_RTC0_CR1 0x40001028 /* RTC0 RTC Control 1 */ +#define REG_RTC0_SR2 0x4000102C /* RTC0 RTC Status 2 */ +#define REG_RTC0_SNAP0 0x40001030 /* RTC0 RTC Snapshot 0 */ +#define REG_RTC0_SNAP1 0x40001034 /* RTC0 RTC Snapshot 1 */ +#define REG_RTC0_SNAP2 0x40001038 /* RTC0 RTC Snapshot 2 */ +#define REG_RTC0_MOD 0x4000103C /* RTC0 RTC Modulo */ +#define REG_RTC0_CNT2 0x40001040 /* RTC0 RTC Count 2 */ +#define REG_RTC0_ALM2 0x40001044 /* RTC0 RTC Alarm 2 */ +#define REG_RTC0_SR3 0x40001048 /* RTC0 RTC Status 3 */ +#define REG_RTC0_CR2IC 0x4000104C /* RTC0 RTC Control 2 for Configuring Input Capture Channels */ +#define REG_RTC0_CR3SS 0x40001050 /* RTC0 RTC Control 3 for Configuring SensorStrobe Channel */ +#define REG_RTC0_CR4SS 0x40001054 /* RTC0 RTC Control 4 for Configuring SensorStrobe Channel */ +#define REG_RTC0_SSMSK 0x40001058 /* RTC0 RTC Mask for SensorStrobe Channel */ +#define REG_RTC0_IC2 0x40001064 /* RTC0 RTC Input Capture Channel 2 */ +#define REG_RTC0_IC3 0x40001068 /* RTC0 RTC Input Capture Channel 3 */ +#define REG_RTC0_IC4 0x4000106C /* RTC0 RTC Input Capture Channel 4 */ +#define REG_RTC0_SS1 0x40001070 /* RTC0 RTC SensorStrobe Channel 1 */ +#define REG_RTC0_SS2 0x40001074 /* RTC0 RTC SensorStrobe Channel 2 */ +#define REG_RTC0_SS3 0x40001078 /* RTC0 RTC SensorStrobe Channel 3 */ +#define REG_RTC0_SS4 0x4000107C /* RTC0 RTC SensorStrobe Channel 4 */ +#define REG_RTC0_SR4 0x40001080 /* RTC0 RTC Status 4 */ +#define REG_RTC0_SR5 0x40001084 /* RTC0 RTC Status 5 */ +#define REG_RTC0_SR6 0x40001088 /* RTC0 RTC Status 6 */ +#define REG_RTC0_SS1TGT 0x4000108C /* RTC0 RTC SensorStrobe Channel 1 Target */ +#define REG_RTC0_FRZCNT 0x40001090 /* RTC0 RTC Freeze Count */ +#define REG_RTC0_SS2TGT 0x40001094 /* RTC0 RTC SensorStrobe Channel 2 Target */ +#define REG_RTC0_SS3TGT 0x40001098 /* RTC0 RTC SensorStrobe Channel 3 Target */ +#define REG_RTC0_SS1LOWDUR 0x400010A0 /* RTC0 RTC Auto-Reload Low Duration for SensorStrobe Channel 1 */ +#define REG_RTC0_SS2LOWDUR 0x400010A4 /* RTC0 RTC Auto-Reload Low Duration for SensorStrobe Channel 2 */ +#define REG_RTC0_SS3LOWDUR 0x400010A8 /* RTC0 RTC Auto-Reload Low Duration for SensorStrobe Channel 3 */ +#define REG_RTC0_SS1HIGHDUR 0x400010B0 /* RTC0 RTC Auto-Reload High Duration for SensorStrobe Channel 1 */ +#define REG_RTC0_SS2HIGHDUR 0x400010B4 /* RTC0 RTC Auto-Reload High Duration for SensorStrobe Channel 2 */ +#define REG_RTC0_SS3HIGHDUR 0x400010B8 /* RTC0 RTC Auto-Reload High Duration for SensorStrobe Channel 3 */ +#define REG_RTC0_SSMSKOT 0x400010C0 /* RTC0 RTC Masks for SensorStrobe Channels on Time Control */ +#define REG_RTC0_CR5SSS 0x400010C4 /* RTC0 RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling */ +#define REG_RTC0_CR6SSS 0x400010C8 /* RTC0 RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge */ +#define REG_RTC0_CR7SSS 0x400010CC /* RTC0 RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity */ +#define REG_RTC0_SR7 0x400010D0 /* RTC0 RTC Status 7 */ +#define REG_RTC0_SR8 0x400010D4 /* RTC0 RTC Status 8 */ +#define REG_RTC0_SR9 0x400010D8 /* RTC0 RTC Status 9 */ +#define REG_RTC0_GPMUX0 0x400010E0 /* RTC0 RTC GPIO Pin Mux Control Register 0 */ +#define REG_RTC0_GPMUX1 0x400010E4 /* RTC0 RTC GPIO Pin Mux Control Register 1 */ + +/* ============================================================================================================================ + RTC1 + ============================================================================================================================ */ +#define REG_RTC1_CR0 0x40001400 /* RTC1 RTC Control 0 */ +#define REG_RTC1_SR0 0x40001404 /* RTC1 RTC Status 0 */ +#define REG_RTC1_SR1 0x40001408 /* RTC1 RTC Status 1 */ +#define REG_RTC1_CNT0 0x4000140C /* RTC1 RTC Count 0 */ +#define REG_RTC1_CNT1 0x40001410 /* RTC1 RTC Count 1 */ +#define REG_RTC1_ALM0 0x40001414 /* RTC1 RTC Alarm 0 */ +#define REG_RTC1_ALM1 0x40001418 /* RTC1 RTC Alarm 1 */ +#define REG_RTC1_TRM 0x4000141C /* RTC1 RTC Trim */ +#define REG_RTC1_GWY 0x40001420 /* RTC1 RTC Gateway */ +#define REG_RTC1_CR1 0x40001428 /* RTC1 RTC Control 1 */ +#define REG_RTC1_SR2 0x4000142C /* RTC1 RTC Status 2 */ +#define REG_RTC1_SNAP0 0x40001430 /* RTC1 RTC Snapshot 0 */ +#define REG_RTC1_SNAP1 0x40001434 /* RTC1 RTC Snapshot 1 */ +#define REG_RTC1_SNAP2 0x40001438 /* RTC1 RTC Snapshot 2 */ +#define REG_RTC1_MOD 0x4000143C /* RTC1 RTC Modulo */ +#define REG_RTC1_CNT2 0x40001440 /* RTC1 RTC Count 2 */ +#define REG_RTC1_ALM2 0x40001444 /* RTC1 RTC Alarm 2 */ +#define REG_RTC1_SR3 0x40001448 /* RTC1 RTC Status 3 */ +#define REG_RTC1_CR2IC 0x4000144C /* RTC1 RTC Control 2 for Configuring Input Capture Channels */ +#define REG_RTC1_CR3SS 0x40001450 /* RTC1 RTC Control 3 for Configuring SensorStrobe Channel */ +#define REG_RTC1_CR4SS 0x40001454 /* RTC1 RTC Control 4 for Configuring SensorStrobe Channel */ +#define REG_RTC1_SSMSK 0x40001458 /* RTC1 RTC Mask for SensorStrobe Channel */ +#define REG_RTC1_IC2 0x40001464 /* RTC1 RTC Input Capture Channel 2 */ +#define REG_RTC1_IC3 0x40001468 /* RTC1 RTC Input Capture Channel 3 */ +#define REG_RTC1_IC4 0x4000146C /* RTC1 RTC Input Capture Channel 4 */ +#define REG_RTC1_SS1 0x40001470 /* RTC1 RTC SensorStrobe Channel 1 */ +#define REG_RTC1_SS2 0x40001474 /* RTC1 RTC SensorStrobe Channel 2 */ +#define REG_RTC1_SS3 0x40001478 /* RTC1 RTC SensorStrobe Channel 3 */ +#define REG_RTC1_SS4 0x4000147C /* RTC1 RTC SensorStrobe Channel 4 */ +#define REG_RTC1_SR4 0x40001480 /* RTC1 RTC Status 4 */ +#define REG_RTC1_SR5 0x40001484 /* RTC1 RTC Status 5 */ +#define REG_RTC1_SR6 0x40001488 /* RTC1 RTC Status 6 */ +#define REG_RTC1_SS1TGT 0x4000148C /* RTC1 RTC SensorStrobe Channel 1 Target */ +#define REG_RTC1_FRZCNT 0x40001490 /* RTC1 RTC Freeze Count */ +#define REG_RTC1_SS2TGT 0x40001494 /* RTC1 RTC SensorStrobe Channel 2 Target */ +#define REG_RTC1_SS3TGT 0x40001498 /* RTC1 RTC SensorStrobe Channel 3 Target */ +#define REG_RTC1_SS1LOWDUR 0x400014A0 /* RTC1 RTC Auto-Reload Low Duration for SensorStrobe Channel 1 */ +#define REG_RTC1_SS2LOWDUR 0x400014A4 /* RTC1 RTC Auto-Reload Low Duration for SensorStrobe Channel 2 */ +#define REG_RTC1_SS3LOWDUR 0x400014A8 /* RTC1 RTC Auto-Reload Low Duration for SensorStrobe Channel 3 */ +#define REG_RTC1_SS1HIGHDUR 0x400014B0 /* RTC1 RTC Auto-Reload High Duration for SensorStrobe Channel 1 */ +#define REG_RTC1_SS2HIGHDUR 0x400014B4 /* RTC1 RTC Auto-Reload High Duration for SensorStrobe Channel 2 */ +#define REG_RTC1_SS3HIGHDUR 0x400014B8 /* RTC1 RTC Auto-Reload High Duration for SensorStrobe Channel 3 */ +#define REG_RTC1_SSMSKOT 0x400014C0 /* RTC1 RTC Masks for SensorStrobe Channels on Time Control */ +#define REG_RTC1_CR5SSS 0x400014C4 /* RTC1 RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling */ +#define REG_RTC1_CR6SSS 0x400014C8 /* RTC1 RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge */ +#define REG_RTC1_CR7SSS 0x400014CC /* RTC1 RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity */ +#define REG_RTC1_SR7 0x400014D0 /* RTC1 RTC Status 7 */ +#define REG_RTC1_SR8 0x400014D4 /* RTC1 RTC Status 8 */ +#define REG_RTC1_SR9 0x400014D8 /* RTC1 RTC Status 9 */ +#define REG_RTC1_GPMUX0 0x400014E0 /* RTC1 RTC GPIO Pin Mux Control Register 0 */ +#define REG_RTC1_GPMUX1 0x400014E4 /* RTC1 RTC GPIO Pin Mux Control Register 1 */ + +/* ============================================================================================================================ + RTC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR0_WPNDINTEN 15 /* Enable Write Pending Sourced Interrupts to the CPU */ +#define BITP_RTC_CR0_WSYNCINTEN 14 /* Enable Write Synchronization Sourced Interrupts to the CPU */ +#define BITP_RTC_CR0_WPNDERRINTEN 13 /* Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs */ +#define BITP_RTC_CR0_ISOINTEN 12 /* Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated */ +#define BITP_RTC_CR0_MOD60ALMINTEN 11 /* Enable Periodic Modulo-60 RTC Alarm Sourced Interrupts to the CPU */ +#define BITP_RTC_CR0_MOD60ALM 5 /* Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary */ +#define BITP_RTC_CR0_MOD60ALMEN 4 /* Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary */ +#define BITP_RTC_CR0_TRMEN 3 /* Enable RTC Digital Trimming */ +#define BITP_RTC_CR0_ALMINTEN 2 /* Enable ALMINT Sourced Alarm Interrupts to the CPU */ +#define BITP_RTC_CR0_ALMEN 1 /* Enable the RTC Alarm (Absolute) Operation */ +#define BITP_RTC_CR0_CNTEN 0 /* Global Enable for the RTC */ +#define BITM_RTC_CR0_WPNDINTEN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable Write Pending Sourced Interrupts to the CPU */ +#define BITM_RTC_CR0_WSYNCINTEN (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Enable Write Synchronization Sourced Interrupts to the CPU */ +#define BITM_RTC_CR0_WPNDERRINTEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs */ +#define BITM_RTC_CR0_ISOINTEN (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated */ +#define BITM_RTC_CR0_MOD60ALMINTEN (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Enable Periodic Modulo-60 RTC Alarm Sourced Interrupts to the CPU */ +#define BITM_RTC_CR0_MOD60ALM (_ADI_MSK_3(0x000007E0,0x000007E0U, uint16_t )) /* Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary */ +#define BITM_RTC_CR0_MOD60ALMEN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary */ +#define BITM_RTC_CR0_TRMEN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Enable RTC Digital Trimming */ +#define BITM_RTC_CR0_ALMINTEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable ALMINT Sourced Alarm Interrupts to the CPU */ +#define BITM_RTC_CR0_ALMEN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enable the RTC Alarm (Absolute) Operation */ +#define BITM_RTC_CR0_CNTEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Global Enable for the RTC */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR0_ISOENB 14 /* Visibility of 32kHz Sourced Registers */ +#define BITP_RTC_SR0_WSYNCTRM 13 /* Synchronisation Status of Posted Writes to TRM */ +#define BITP_RTC_SR0_WSYNCALM1 12 /* Synchronisation Status of Posted Writes to ALM1 */ +#define BITP_RTC_SR0_WSYNCALM0 11 /* Synchronisation Status of Posted Writes to ALM0 */ +#define BITP_RTC_SR0_WSYNCCNT1 10 /* Synchronisation Status of Posted Writes to CNT1 */ +#define BITP_RTC_SR0_WSYNCCNT0 9 /* Synchronisation Status of Posted Writes to CNT0 */ +#define BITP_RTC_SR0_WSYNCSR0 8 /* Synchronisation Status of Posted Writes to SR0 */ +#define BITP_RTC_SR0_WSYNCCR0 7 /* Synchronisation Status of Posted Writes to CR0 */ +#define BITP_RTC_SR0_WPNDINT 6 /* Write Pending Interrupt */ +#define BITP_RTC_SR0_WSYNCINT 5 /* Write Synchronisation Interrupt */ +#define BITP_RTC_SR0_WPNDERRINT 4 /* Write Pending Error Interrupt Source */ +#define BITP_RTC_SR0_ISOINT 3 /* RTC Power-Domain Isolation Interrupt Source */ +#define BITP_RTC_SR0_MOD60ALMINT 2 /* Modulo-60 RTC Alarm Interrupt Source */ +#define BITP_RTC_SR0_ALMINT 1 /* Alarm Interrupt Source */ +#define BITM_RTC_SR0_ISOENB (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Visibility of 32kHz Sourced Registers */ +#define BITM_RTC_SR0_WSYNCTRM (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Synchronisation Status of Posted Writes to TRM */ +#define BITM_RTC_SR0_WSYNCALM1 (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Synchronisation Status of Posted Writes to ALM1 */ +#define BITM_RTC_SR0_WSYNCALM0 (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Synchronisation Status of Posted Writes to ALM0 */ +#define BITM_RTC_SR0_WSYNCCNT1 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Synchronisation Status of Posted Writes to CNT1 */ +#define BITM_RTC_SR0_WSYNCCNT0 (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Synchronisation Status of Posted Writes to CNT0 */ +#define BITM_RTC_SR0_WSYNCSR0 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Synchronisation Status of Posted Writes to SR0 */ +#define BITM_RTC_SR0_WSYNCCR0 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Synchronisation Status of Posted Writes to CR0 */ +#define BITM_RTC_SR0_WPNDINT (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Write Pending Interrupt */ +#define BITM_RTC_SR0_WSYNCINT (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Write Synchronisation Interrupt */ +#define BITM_RTC_SR0_WPNDERRINT (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Write Pending Error Interrupt Source */ +#define BITM_RTC_SR0_ISOINT (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* RTC Power-Domain Isolation Interrupt Source */ +#define BITM_RTC_SR0_MOD60ALMINT (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Modulo-60 RTC Alarm Interrupt Source */ +#define BITM_RTC_SR0_ALMINT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Alarm Interrupt Source */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR1_WPNDTRM 13 /* Pending Status of Posted Writes to TRM */ +#define BITP_RTC_SR1_WPNDALM1 12 /* Pending Status of Posted Writes to ALM1 */ +#define BITP_RTC_SR1_WPNDALM0 11 /* Pending Status of Posted Writes to ALM0 */ +#define BITP_RTC_SR1_WPNDCNT1 10 /* Pending Status of Posted Writes to CNT1 */ +#define BITP_RTC_SR1_WPNDCNT0 9 /* Pending Status of Posted Writes to CNT0 */ +#define BITP_RTC_SR1_WPNDSR0 8 /* Pending Status of Posted Clearances of Interrupt Sources in SR0 */ +#define BITP_RTC_SR1_WPNDCR0 7 /* Pending Status of Posted Writes to CR0 */ +#define BITM_RTC_SR1_WPNDTRM (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Pending Status of Posted Writes to TRM */ +#define BITM_RTC_SR1_WPNDALM1 (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Pending Status of Posted Writes to ALM1 */ +#define BITM_RTC_SR1_WPNDALM0 (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Pending Status of Posted Writes to ALM0 */ +#define BITM_RTC_SR1_WPNDCNT1 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Pending Status of Posted Writes to CNT1 */ +#define BITM_RTC_SR1_WPNDCNT0 (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Pending Status of Posted Writes to CNT0 */ +#define BITM_RTC_SR1_WPNDSR0 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Pending Status of Posted Clearances of Interrupt Sources in SR0 */ +#define BITM_RTC_SR1_WPNDCR0 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Pending Status of Posted Writes to CR0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CNT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CNT0_VALUE 0 /* Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */ +#define BITM_RTC_CNT0_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CNT1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CNT1_VALUE 0 /* Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */ +#define BITM_RTC_CNT1_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_ALM0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_ALM0_VALUE 0 /* Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time */ +#define BITM_RTC_ALM0_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_ALM1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_ALM1_VALUE 0 /* Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time */ +#define BITM_RTC_ALM1_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_TRM Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_TRM_IVL2EXPMIN 6 /* Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select */ +#define BITP_RTC_TRM_IVL 4 /* Trim Interval in Prescaled RTC Time Units */ +#define BITP_RTC_TRM_ADD 3 /* Trim Polarity */ +#define BITP_RTC_TRM_VALUE 0 /* Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL */ +#define BITM_RTC_TRM_IVL2EXPMIN (_ADI_MSK_3(0x000003C0,0x000003C0U, uint16_t )) /* Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select */ +#define BITM_RTC_TRM_IVL (_ADI_MSK_3(0x00000030,0x00000030U, uint16_t )) /* Trim Interval in Prescaled RTC Time Units */ +#define BITM_RTC_TRM_ADD (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Trim Polarity */ +#define BITM_RTC_TRM_VALUE (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t )) /* Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_GWY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_GWY_SWKEY 0 /* Software-keyed Command Issued by the CPU */ +#define BITM_RTC_GWY_SWKEY (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Software-keyed Command Issued by the CPU */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR1_PRESCALE2EXP 5 /* Prescale Power of 2 Division Factor for the RTC Base Clock */ +#define BITP_RTC_CR1_CNTMOD60ROLLINTEN 4 /* Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source, in SR2:RTCCNTMOD60ROLLINT */ +#define BITP_RTC_CR1_CNTROLLINTEN 3 /* Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT */ +#define BITP_RTC_CR1_TRMINTEN 2 /* Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT */ +#define BITP_RTC_CR1_PSINTEN 1 /* Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT */ +#define BITP_RTC_CR1_CNTINTEN 0 /* Enable for the RTC Count Interrupt Source */ +#define BITM_RTC_CR1_PRESCALE2EXP (_ADI_MSK_3(0x000001E0,0x000001E0U, uint16_t )) /* Prescale Power of 2 Division Factor for the RTC Base Clock */ +#define BITM_RTC_CR1_CNTMOD60ROLLINTEN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source, in SR2:RTCCNTMOD60ROLLINT */ +#define BITM_RTC_CR1_CNTROLLINTEN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT */ +#define BITM_RTC_CR1_TRMINTEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT */ +#define BITM_RTC_CR1_PSINTEN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT */ +#define BITM_RTC_CR1_CNTINTEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Enable for the RTC Count Interrupt Source */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR2_WSYNCALM2MIR 15 /* Synchronization Status of Posted Writes to ALM2 */ +#define BITP_RTC_SR2_WSYNCCR1MIR 14 /* Synchronization Status of Posted Writes to CR1 */ +#define BITP_RTC_SR2_WPNDALM2MIR 13 /* Pending Status of Posted Writes to ALM2 */ +#define BITP_RTC_SR2_WPNDCR1MIR 12 /* Pending Status of Posted Writes to CR1 */ +#define BITP_RTC_SR2_TRMBDYMIR 7 /* Mirror of MOD:RTCTRMBDY */ +#define BITP_RTC_SR2_CNTMOD60ROLL 6 /* RTC Count Modulo-60 Roll-Over */ +#define BITP_RTC_SR2_CNTROLL 5 /* RTC Count Roll-Over */ +#define BITP_RTC_SR2_CNTMOD60ROLLINT 4 /* RTC Modulo-60 Count Roll-Over Interrupt Source */ +#define BITP_RTC_SR2_CNTROLLINT 3 /* RTC Count Roll-Over Interrupt Source */ +#define BITP_RTC_SR2_TRMINT 2 /* RTC Trim Interrupt Source */ +#define BITP_RTC_SR2_PSINT 1 /* RTC Prescaled, Modulo-1 Boundary Interrupt Source */ +#define BITP_RTC_SR2_CNTINT 0 /* RTC Count Interrupt Source */ +#define BITM_RTC_SR2_WSYNCALM2MIR (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Synchronization Status of Posted Writes to ALM2 */ +#define BITM_RTC_SR2_WSYNCCR1MIR (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Synchronization Status of Posted Writes to CR1 */ +#define BITM_RTC_SR2_WPNDALM2MIR (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Pending Status of Posted Writes to ALM2 */ +#define BITM_RTC_SR2_WPNDCR1MIR (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Pending Status of Posted Writes to CR1 */ +#define BITM_RTC_SR2_TRMBDYMIR (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Mirror of MOD:RTCTRMBDY */ +#define BITM_RTC_SR2_CNTMOD60ROLL (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* RTC Count Modulo-60 Roll-Over */ +#define BITM_RTC_SR2_CNTROLL (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* RTC Count Roll-Over */ +#define BITM_RTC_SR2_CNTMOD60ROLLINT (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* RTC Modulo-60 Count Roll-Over Interrupt Source */ +#define BITM_RTC_SR2_CNTROLLINT (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* RTC Count Roll-Over Interrupt Source */ +#define BITM_RTC_SR2_TRMINT (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* RTC Trim Interrupt Source */ +#define BITM_RTC_SR2_PSINT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* RTC Prescaled, Modulo-1 Boundary Interrupt Source */ +#define BITM_RTC_SR2_CNTINT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* RTC Count Interrupt Source */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SNAP0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SNAP0_VALUE 0 /* Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of CNT0 */ +#define BITM_RTC_SNAP0_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of CNT0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SNAP1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SNAP1_VALUE 0 /* Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT1 */ +#define BITM_RTC_SNAP1_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SNAP2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SNAP2_VALUE 0 /* Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT2 */ +#define BITM_RTC_SNAP2_VALUE (_ADI_MSK_3(0x00007FFF,0x00007FFFU, uint16_t )) /* Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_MOD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_MOD_CNT0_4TOZERO 11 /* Mirror of CNT0[4:0] */ +#define BITP_RTC_MOD_TRMBDY 10 /* Trim Boundary Indicator */ +#define BITP_RTC_MOD_INCR 6 /* Most Recent Increment Value Added to the RTC Count in CNT1 and CNT0 */ +#define BITP_RTC_MOD_CNTMOD60 0 /* Modulo-60 Value of the RTC Count: CNT1 and CNT0 */ +#define BITM_RTC_MOD_CNT0_4TOZERO (_ADI_MSK_3(0x0000F800,0x0000F800U, uint16_t )) /* Mirror of CNT0[4:0] */ +#define BITM_RTC_MOD_TRMBDY (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Trim Boundary Indicator */ +#define BITM_RTC_MOD_INCR (_ADI_MSK_3(0x000003C0,0x000003C0U, uint16_t )) /* Most Recent Increment Value Added to the RTC Count in CNT1 and CNT0 */ +#define BITM_RTC_MOD_CNTMOD60 (_ADI_MSK_3(0x0000003F,0x0000003FU, uint16_t )) /* Modulo-60 Value of the RTC Count: CNT1 and CNT0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CNT2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CNT2_VALUE 0 /* Fractional Bits of the RTC Real-Time Count */ +#define BITM_RTC_CNT2_VALUE (_ADI_MSK_3(0x00007FFF,0x00007FFFU, uint16_t )) /* Fractional Bits of the RTC Real-Time Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_ALM2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_ALM2_VALUE 0 /* Fractional Bits of the Alarm Target Time */ +#define BITM_RTC_ALM2_VALUE (_ADI_MSK_3(0x00007FFF,0x00007FFFU, uint16_t )) /* Fractional Bits of the Alarm Target Time */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR3_ALMINTMIR 13 /* Read-only Mirror of the SR0:ALMINT Interrupt Source */ +#define BITP_RTC_SR3_SS4IRQ 12 /* Sticky Interrupt Source for the SensorStrobe Channel 4 */ +#define BITP_RTC_SR3_SS3IRQ 11 /* Sticky Interrupt Source for the SensorStrobe Channel 3 */ +#define BITP_RTC_SR3_SS2IRQ 10 /* Sticky Interrupt Source for the SensorStrobe Channel 2 */ +#define BITP_RTC_SR3_SS1IRQ 9 /* Sticky Interrupt Source for SensorStrobe Channel 1 */ +#define BITP_RTC_SR3_SS4FEIRQ 8 /* Sticky Interrupt Source for the SensorStrobe Channel 4 Falling Edge */ +#define BITP_RTC_SR3_SS3FEIRQ 7 /* Sticky Interrupt Source for the SensorStrobe Channel 3 Falling Edge */ +#define BITP_RTC_SR3_SS2FEIRQ 6 /* Sticky Interrupt Source for the SensorStrobe Channel 2 Falling Edge */ +#define BITP_RTC_SR3_SS1FEIRQ 5 /* Sticky Interrupt Source for the SensorStrobe Channel 1 Falling Edge */ +#define BITP_RTC_SR3_IC4IRQ 4 /* Sticky Interrupt Source for the RTC Input Capture Channel 4 */ +#define BITP_RTC_SR3_IC3IRQ 3 /* Sticky Interrupt Source for the RTC Input Capture Channel 3 */ +#define BITP_RTC_SR3_IC2IRQ 2 /* Sticky Interrupt Source for the RTC Input Capture Channel 2 */ +#define BITP_RTC_SR3_IC0IRQ 0 /* Sticky Interrupt Source for the RTC Input Capture Channel 0 */ +#define BITM_RTC_SR3_ALMINTMIR (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Read-only Mirror of the SR0:ALMINT Interrupt Source */ +#define BITM_RTC_SR3_SS4IRQ (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Sticky Interrupt Source for the SensorStrobe Channel 4 */ +#define BITM_RTC_SR3_SS3IRQ (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Sticky Interrupt Source for the SensorStrobe Channel 3 */ +#define BITM_RTC_SR3_SS2IRQ (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Sticky Interrupt Source for the SensorStrobe Channel 2 */ +#define BITM_RTC_SR3_SS1IRQ (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Sticky Interrupt Source for SensorStrobe Channel 1 */ +#define BITM_RTC_SR3_SS4FEIRQ (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Sticky Interrupt Source for the SensorStrobe Channel 4 Falling Edge */ +#define BITM_RTC_SR3_SS3FEIRQ (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Sticky Interrupt Source for the SensorStrobe Channel 3 Falling Edge */ +#define BITM_RTC_SR3_SS2FEIRQ (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Sticky Interrupt Source for the SensorStrobe Channel 2 Falling Edge */ +#define BITM_RTC_SR3_SS1FEIRQ (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Sticky Interrupt Source for the SensorStrobe Channel 1 Falling Edge */ +#define BITM_RTC_SR3_IC4IRQ (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Sticky Interrupt Source for the RTC Input Capture Channel 4 */ +#define BITM_RTC_SR3_IC3IRQ (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Sticky Interrupt Source for the RTC Input Capture Channel 3 */ +#define BITM_RTC_SR3_IC2IRQ (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Sticky Interrupt Source for the RTC Input Capture Channel 2 */ +#define BITM_RTC_SR3_IC0IRQ (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Sticky Interrupt Source for the RTC Input Capture Channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR2IC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR2IC_ICOWUSEN 15 /* Enable Overwrite of Unread Snapshots for All Input Capture Channels */ +#define BITP_RTC_CR2IC_IC4IRQEN 14 /* Interrupt Enable for the RTC Input Capture Channel 4 */ +#define BITP_RTC_CR2IC_IC3IRQEN 13 /* Interrupt Enable for the RTC Input Capture Channel 3 */ +#define BITP_RTC_CR2IC_IC2IRQEN 12 /* Interrupt Enable for the RTC Input Capture Channel 2 */ +#define BITP_RTC_CR2IC_IC0IRQEN 10 /* Interrupt Enable for the RTC Input Capture Channel 0 */ +#define BITP_RTC_CR2IC_IC4LH 9 /* Polarity of the Active-going Capture Edge for the Input Capture Channel 4 */ +#define BITP_RTC_CR2IC_IC3LH 8 /* Polarity of the Active-going Capture Edge for the Input Capture Channel 3 */ +#define BITP_RTC_CR2IC_IC2LH 7 /* Polarity of the Active-going Capture Edge for the Input Capture Channel 2 */ +#define BITP_RTC_CR2IC_IC0LH 5 /* Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0 */ +#define BITP_RTC_CR2IC_IC4EN 4 /* Enable for the RTC Input Capture Channel 4 */ +#define BITP_RTC_CR2IC_IC3EN 3 /* Enable for the RTC Input Capture Channel 3 */ +#define BITP_RTC_CR2IC_IC2EN 2 /* Enable for the RTC Input Capture Channel 2 */ +#define BITP_RTC_CR2IC_IC0EN 0 /* Enable for the RTC Input Capture Channel 0 */ +#define BITM_RTC_CR2IC_ICOWUSEN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable Overwrite of Unread Snapshots for All Input Capture Channels */ +#define BITM_RTC_CR2IC_IC4IRQEN (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Interrupt Enable for the RTC Input Capture Channel 4 */ +#define BITM_RTC_CR2IC_IC3IRQEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Interrupt Enable for the RTC Input Capture Channel 3 */ +#define BITM_RTC_CR2IC_IC2IRQEN (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Interrupt Enable for the RTC Input Capture Channel 2 */ +#define BITM_RTC_CR2IC_IC0IRQEN (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Interrupt Enable for the RTC Input Capture Channel 0 */ +#define BITM_RTC_CR2IC_IC4LH (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Polarity of the Active-going Capture Edge for the Input Capture Channel 4 */ +#define BITM_RTC_CR2IC_IC3LH (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Polarity of the Active-going Capture Edge for the Input Capture Channel 3 */ +#define BITM_RTC_CR2IC_IC2LH (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Polarity of the Active-going Capture Edge for the Input Capture Channel 2 */ +#define BITM_RTC_CR2IC_IC0LH (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0 */ +#define BITM_RTC_CR2IC_IC4EN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Enable for the RTC Input Capture Channel 4 */ +#define BITM_RTC_CR2IC_IC3EN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Enable for the RTC Input Capture Channel 3 */ +#define BITM_RTC_CR2IC_IC2EN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable for the RTC Input Capture Channel 2 */ +#define BITM_RTC_CR2IC_IC0EN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Enable for the RTC Input Capture Channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR3SS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR3SS_SS4IRQEN 12 /* Posedge EdgeInterrupt Enable for the SensorStrobe Channel 4 */ +#define BITP_RTC_CR3SS_SS3IRQEN 11 /* Posedge EdgeInterrupt Enable for the SensorStrobe Channel 3 */ +#define BITP_RTC_CR3SS_SS2IRQEN 10 /* Posedge EdgeInterrupt Enable for the SensorStrobe Channel 2 */ +#define BITP_RTC_CR3SS_SS1IRQEN 9 /* Interrupt Enable for SensorStrobe Channel 1 */ +#define BITP_RTC_CR3SS_SS4FEIRQEN 8 /* Falling Edge Interrupt Enable for the SensorStrobe Channel 4 */ +#define BITP_RTC_CR3SS_SS3FEIRQEN 7 /* Falling Edge Interrupt Enable for the SensorStrobe Channel 3 */ +#define BITP_RTC_CR3SS_SS2FEIRQEN 6 /* Falling Edge Interrupt Enable for the SensorStrobe Channel 2 */ +#define BITP_RTC_CR3SS_SS1FEIRQEN 5 /* Falling Edge Interrupt Enable for the SensorStrobe Channel 1 */ +#define BITP_RTC_CR3SS_SS4EN 4 /* Enable for the SensorStrobe Channel 4 */ +#define BITP_RTC_CR3SS_SS3EN 3 /* Enable for the SensorStrobe Channel 3 */ +#define BITP_RTC_CR3SS_SS2EN 2 /* Enable for the SensorStrobe Channel 2 */ +#define BITP_RTC_CR3SS_SS1EN 1 /* Enable for SensorStrobe Channel 1 */ +#define BITM_RTC_CR3SS_SS4IRQEN (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Posedge EdgeInterrupt Enable for the SensorStrobe Channel 4 */ +#define BITM_RTC_CR3SS_SS3IRQEN (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Posedge EdgeInterrupt Enable for the SensorStrobe Channel 3 */ +#define BITM_RTC_CR3SS_SS2IRQEN (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Posedge EdgeInterrupt Enable for the SensorStrobe Channel 2 */ +#define BITM_RTC_CR3SS_SS1IRQEN (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Interrupt Enable for SensorStrobe Channel 1 */ +#define BITM_RTC_CR3SS_SS4FEIRQEN (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Falling Edge Interrupt Enable for the SensorStrobe Channel 4 */ +#define BITM_RTC_CR3SS_SS3FEIRQEN (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Falling Edge Interrupt Enable for the SensorStrobe Channel 3 */ +#define BITM_RTC_CR3SS_SS2FEIRQEN (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Falling Edge Interrupt Enable for the SensorStrobe Channel 2 */ +#define BITM_RTC_CR3SS_SS1FEIRQEN (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Falling Edge Interrupt Enable for the SensorStrobe Channel 1 */ +#define BITM_RTC_CR3SS_SS4EN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Enable for the SensorStrobe Channel 4 */ +#define BITM_RTC_CR3SS_SS3EN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Enable for the SensorStrobe Channel 3 */ +#define BITM_RTC_CR3SS_SS2EN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable for the SensorStrobe Channel 2 */ +#define BITM_RTC_CR3SS_SS1EN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enable for SensorStrobe Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR4SS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR4SS_SS3ARLEN 11 /* Enable for Fine Control on SensorStrobe Channel 3 Period and Duty Cycle */ +#define BITP_RTC_CR4SS_SS2ARLEN 10 /* Enable for Fine Control on SensorStrobe Channel 2 Period and Duty Cycle */ +#define BITP_RTC_CR4SS_SS1ARLEN 9 /* Enable for Fine Control on SensorStrobe Channel 1 Period and Duty Cycle */ +#define BITP_RTC_CR4SS_SS4POL 8 /* SensorStrobe Channel 4 Polarity Control */ +#define BITP_RTC_CR4SS_SS3POL 7 /* SensorStrobe Channel 3 Polarity Control */ +#define BITP_RTC_CR4SS_SS2POL 6 /* SensorStrobe Channel 2 Polarity Control */ +#define BITP_RTC_CR4SS_SS1POL 5 /* SensorSTrobe Channel 1 Polarity Control */ +#define BITP_RTC_CR4SS_SS4MSKEN 4 /* Enable for Thermometer-Code Masking of the SensorStrobe Channel 4 */ +#define BITP_RTC_CR4SS_SS3MSKEN 3 /* Enable for Thermometer-Code Masking of the SensorStrobe Channel 3 */ +#define BITP_RTC_CR4SS_SS2MSKEN 2 /* Enable for Thermometer-Code Masking of the SensorStrobe Channel 2 */ +#define BITP_RTC_CR4SS_SS1MSKEN 1 /* Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 */ +#define BITM_RTC_CR4SS_SS3ARLEN (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Enable for Fine Control on SensorStrobe Channel 3 Period and Duty Cycle */ +#define BITM_RTC_CR4SS_SS2ARLEN (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Enable for Fine Control on SensorStrobe Channel 2 Period and Duty Cycle */ +#define BITM_RTC_CR4SS_SS1ARLEN (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Enable for Fine Control on SensorStrobe Channel 1 Period and Duty Cycle */ +#define BITM_RTC_CR4SS_SS4POL (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* SensorStrobe Channel 4 Polarity Control */ +#define BITM_RTC_CR4SS_SS3POL (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* SensorStrobe Channel 3 Polarity Control */ +#define BITM_RTC_CR4SS_SS2POL (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* SensorStrobe Channel 2 Polarity Control */ +#define BITM_RTC_CR4SS_SS1POL (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* SensorSTrobe Channel 1 Polarity Control */ +#define BITM_RTC_CR4SS_SS4MSKEN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Enable for Thermometer-Code Masking of the SensorStrobe Channel 4 */ +#define BITM_RTC_CR4SS_SS3MSKEN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Enable for Thermometer-Code Masking of the SensorStrobe Channel 3 */ +#define BITM_RTC_CR4SS_SS2MSKEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable for Thermometer-Code Masking of the SensorStrobe Channel 2 */ +#define BITM_RTC_CR4SS_SS1MSKEN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 */ +#define ENUM_RTC_CR4SS_NO_MSK (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS1MSKEN: Do not apply a mask to SensorStrobe Channel 1 Register */ +#define ENUM_RTC_CR4SS_THERM_MSK (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* SS1MSKEN: Apply thermometer decoded mask */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SSMSK Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SSMSK_SS4MSK 12 /* SensorStrobe Channel 4 Period Control */ +#define BITP_RTC_SSMSK_SS3MSK 8 /* SensorStrobe Channel 3 Period Control */ +#define BITP_RTC_SSMSK_SS2MSK 4 /* SensorStrobe Channel 2 Period Control */ +#define BITP_RTC_SSMSK_SS1MSK 0 /* Concatenation of Thermometer-Encoded Masks for the 16-bit SensorStrobe Channels */ +#define BITM_RTC_SSMSK_SS4MSK (_ADI_MSK_3(0x0000F000,0x0000F000U, uint16_t )) /* SensorStrobe Channel 4 Period Control */ +#define BITM_RTC_SSMSK_SS3MSK (_ADI_MSK_3(0x00000F00,0x00000F00U, uint16_t )) /* SensorStrobe Channel 3 Period Control */ +#define BITM_RTC_SSMSK_SS2MSK (_ADI_MSK_3(0x000000F0,0x000000F0U, uint16_t )) /* SensorStrobe Channel 2 Period Control */ +#define BITM_RTC_SSMSK_SS1MSK (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t )) /* Concatenation of Thermometer-Encoded Masks for the 16-bit SensorStrobe Channels */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_IC2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_IC2_IC2 0 /* RTC Input Capture Channel 2 */ +#define BITM_RTC_IC2_IC2 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* RTC Input Capture Channel 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_IC3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_IC3_IC3 0 /* RTC Input Capture Channel 3 */ +#define BITM_RTC_IC3_IC3 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* RTC Input Capture Channel 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_IC4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_IC4_IC4 0 /* RTC Input Capture Channel 4 */ +#define BITM_RTC_IC4_IC4 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* RTC Input Capture Channel 4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS1_SS1 0 /* SensorStrobe Channel 1 */ +#define BITM_RTC_SS1_SS1 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* SensorStrobe Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS2_SS2 0 /* SensorStrobe Channel 2 */ +#define BITM_RTC_SS2_SS2 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* SensorStrobe Channel 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS3_SS3 0 /* SensorStrobe Channel 3 */ +#define BITM_RTC_SS3_SS3 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* SensorStrobe Channel 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS4_SS4 0 /* SensorStrobe Channel 4 */ +#define BITM_RTC_SS4_SS4 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* SensorStrobe Channel 4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR4_WSYNCSSMSKOT 15 /* Synchronization Status of Posted Reads Writes to Mask for SensorStrobe Channels on Time Control Register */ +#define BITP_RTC_SR4_RSYNCIC4 14 /* Synchronization Status of Posted Reads of RTC Input Channel 4 */ +#define BITP_RTC_SR4_RSYNCIC3 13 /* Synchronization Status of Posted Reads of RTC Input Channel 3 */ +#define BITP_RTC_SR4_RSYNCIC2 12 /* Synchronization Status of Posted Reads of RTC Input Channel 2 */ +#define BITP_RTC_SR4_RSYNCIC0 10 /* Synchronization Status of Posted Reads of RTC Input Channel 0 */ +#define BITP_RTC_SR4_WSYNCSS4 9 /* Synchronization Status of Posted Writes to SensorStrobe Channel 4 */ +#define BITP_RTC_SR4_WSYNCSS3 8 /* Synchronization Status of Posted Writes to SensorStrobe Channel 3 */ +#define BITP_RTC_SR4_WSYNCSS2 7 /* Synchronization Status of Posted Writes to SensorStrobe Channel 2 */ +#define BITP_RTC_SR4_WSYNCSS1 6 /* Synchronization Status of Posted Writes to SensorStrobe Channel 1 */ +#define BITP_RTC_SR4_WSYNCSSMSK 4 /* Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register */ +#define BITP_RTC_SR4_WSYNCCR4SS 3 /* Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR4_WSYNCCR3SS 2 /* Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR4_WSYNCCR2IC 1 /* Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */ +#define BITP_RTC_SR4_WSYNCSR3 0 /* Synchronisation Status of Posted Writes to SR3 */ +#define BITM_RTC_SR4_WSYNCSSMSKOT (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Synchronization Status of Posted Reads Writes to Mask for SensorStrobe Channels on Time Control Register */ +#define BITM_RTC_SR4_RSYNCIC4 (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Synchronization Status of Posted Reads of RTC Input Channel 4 */ +#define BITM_RTC_SR4_RSYNCIC3 (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Synchronization Status of Posted Reads of RTC Input Channel 3 */ +#define BITM_RTC_SR4_RSYNCIC2 (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Synchronization Status of Posted Reads of RTC Input Channel 2 */ +#define BITM_RTC_SR4_RSYNCIC0 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Synchronization Status of Posted Reads of RTC Input Channel 0 */ +#define BITM_RTC_SR4_WSYNCSS4 (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Synchronization Status of Posted Writes to SensorStrobe Channel 4 */ +#define BITM_RTC_SR4_WSYNCSS3 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Synchronization Status of Posted Writes to SensorStrobe Channel 3 */ +#define BITM_RTC_SR4_WSYNCSS2 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Synchronization Status of Posted Writes to SensorStrobe Channel 2 */ +#define BITM_RTC_SR4_WSYNCSS1 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Synchronization Status of Posted Writes to SensorStrobe Channel 1 */ +#define BITM_RTC_SR4_WSYNCSSMSK (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register */ +#define BITM_RTC_SR4_WSYNCCR4SS (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR4_WSYNCCR3SS (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR4_WSYNCCR2IC (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */ +#define BITM_RTC_SR4_WSYNCSR3 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Synchronisation Status of Posted Writes to SR3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR5_WPENDSSMSKOT 15 /* Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */ +#define BITP_RTC_SR5_RPENDIC4 14 /* Pending Status of Posted Reads of IC4 */ +#define BITP_RTC_SR5_RPENDIC3 13 /* Pending Status of Posted Reads of IC3 */ +#define BITP_RTC_SR5_RPENDIC2 12 /* Pending Status of Posted Reads of IC2 */ +#define BITP_RTC_SR5_RPENDIC0 10 /* Pending Status of Posted Reads of Input Capture Channel 0 */ +#define BITP_RTC_SR5_WPENDSS4 9 /* Pending Status of Posted Writes to SensorStrobe Channel 4 */ +#define BITP_RTC_SR5_WPENDSS3 8 /* Pending Status of Posted Writes to SensorStrobe Channel 3 */ +#define BITP_RTC_SR5_WPENDSS2 7 /* Pending Status of Posted Writes to SensorStrobe Channel 2 */ +#define BITP_RTC_SR5_WPENDSS1 6 /* Pending Status of Posted Writes to SensorStrobe Channel 1 */ +#define BITP_RTC_SR5_WPENDSSMSK 4 /* Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */ +#define BITP_RTC_SR5_WPENDCR4SS 3 /* Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR5_WPENDCR3SS 2 /* Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR5_WPENDCR2IC 1 /* Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */ +#define BITP_RTC_SR5_WPENDSR3 0 /* Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register */ +#define BITM_RTC_SR5_WPENDSSMSKOT (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */ +#define BITM_RTC_SR5_RPENDIC4 (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Pending Status of Posted Reads of IC4 */ +#define BITM_RTC_SR5_RPENDIC3 (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Pending Status of Posted Reads of IC3 */ +#define BITM_RTC_SR5_RPENDIC2 (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Pending Status of Posted Reads of IC2 */ +#define BITM_RTC_SR5_RPENDIC0 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Pending Status of Posted Reads of Input Capture Channel 0 */ +#define BITM_RTC_SR5_WPENDSS4 (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Pending Status of Posted Writes to SensorStrobe Channel 4 */ +#define BITM_RTC_SR5_WPENDSS3 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Pending Status of Posted Writes to SensorStrobe Channel 3 */ +#define BITM_RTC_SR5_WPENDSS2 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Pending Status of Posted Writes to SensorStrobe Channel 2 */ +#define BITM_RTC_SR5_WPENDSS1 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Pending Status of Posted Writes to SensorStrobe Channel 1 */ +#define BITM_RTC_SR5_WPENDSSMSK (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */ +#define BITM_RTC_SR5_WPENDCR4SS (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR5_WPENDCR3SS (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR5_WPENDCR2IC (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */ +#define BITM_RTC_SR5_WPENDSR3 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR6 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR6_FRZCNTPTR 9 /* Pointer for the Triple-Read Sequence of FRZCNT */ +#define BITP_RTC_SR6_IC0SNAP 8 /* Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture Channel RTC Input Capture Channel 0 */ +#define BITP_RTC_SR6_IC4UNR 4 /* Sticky Unread Status of the Input Capture Channel 4 */ +#define BITP_RTC_SR6_IC3UNR 3 /* Sticky Unread Status of the Input Capture Channel 3 */ +#define BITP_RTC_SR6_IC2UNR 2 /* Sticky Unread Status of the Input Capture Channel 2 */ +#define BITP_RTC_SR6_IC0UNR 0 /* Sticky Unread Status of the Input Capture Channel 0 */ +#define BITM_RTC_SR6_FRZCNTPTR (_ADI_MSK_3(0x00000600,0x00000600U, uint16_t )) /* Pointer for the Triple-Read Sequence of FRZCNT */ +#define BITM_RTC_SR6_IC0SNAP (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture Channel RTC Input Capture Channel 0 */ +#define BITM_RTC_SR6_IC4UNR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Sticky Unread Status of the Input Capture Channel 4 */ +#define BITM_RTC_SR6_IC3UNR (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Sticky Unread Status of the Input Capture Channel 3 */ +#define BITM_RTC_SR6_IC2UNR (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Sticky Unread Status of the Input Capture Channel 2 */ +#define BITM_RTC_SR6_IC0UNR (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Sticky Unread Status of the Input Capture Channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS1TGT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS1TGT_SS1TGT 0 /* Current Target Value for the SensorStrobe Channel 1 */ +#define BITM_RTC_SS1TGT_SS1TGT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Current Target Value for the SensorStrobe Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_FRZCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_FRZCNT_FRZCNT 0 /* RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count */ +#define BITM_RTC_FRZCNT_FRZCNT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS2TGT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS2TGT_SS2TGT 0 /* Current, Cumulative Target Time for SensorStrobe Channel 2, Taking Account of Any Auto-reloading */ +#define BITM_RTC_SS2TGT_SS2TGT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Current, Cumulative Target Time for SensorStrobe Channel 2, Taking Account of Any Auto-reloading */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS3TGT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS3TGT_SS3TGT 0 /* Current, Cumulative Target Time for SensorStrobe Channel 3, Taking Account of Any Auto-reloading */ +#define BITM_RTC_SS3TGT_SS3TGT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Current, Cumulative Target Time for SensorStrobe Channel 3, Taking Account of Any Auto-reloading */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS1LOWDUR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS1LOWDUR_SS1LOWDUR 0 /* Low Duration for SensorStrobe Channel 1. */ +#define BITM_RTC_SS1LOWDUR_SS1LOWDUR (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Low Duration for SensorStrobe Channel 1. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS2LOWDUR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS2LOWDUR_SS2LOWDUR 0 /* Low Duration for SensorStrobe Channel 2. */ +#define BITM_RTC_SS2LOWDUR_SS2LOWDUR (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Low Duration for SensorStrobe Channel 2. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS3LOWDUR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS3LOWDUR_SS3LOWDUR 0 /* Low Duration for SensorStrobe Channel 3. */ +#define BITM_RTC_SS3LOWDUR_SS3LOWDUR (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Low Duration for SensorStrobe Channel 3. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS1HIGHDUR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS1HIGHDUR_SS1HIGHDUR 0 /* High Duration for SensorStrobe Channel 1. */ +#define BITM_RTC_SS1HIGHDUR_SS1HIGHDUR (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* High Duration for SensorStrobe Channel 1. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS2HIGHDUR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS2HIGHDUR_SS2HIGHDUR 0 /* High Duration for SensorStrobe Channel 2. */ +#define BITM_RTC_SS2HIGHDUR_SS2HIGHDUR (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* High Duration for SensorStrobe Channel 2. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS3HIGHDUR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS3HIGHDUR_SS3HIGHDUR 0 /* High Duration for SensorStrobe Channel 3. */ +#define BITM_RTC_SS3HIGHDUR_SS3HIGHDUR (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* High Duration for SensorStrobe Channel 3. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SSMSKOT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SSMSKOT_SS4MSKOT 12 /* SensorStrobe Channel 4 on Time Control */ +#define BITP_RTC_SSMSKOT_SS3MSKOT 8 /* SensorStrobe Channel 3 on Time Control */ +#define BITP_RTC_SSMSKOT_SS2MSKOT 4 /* SensorStrobe Channel 2 on Time Control */ +#define BITP_RTC_SSMSKOT_SS1MSKOT 0 /* Concatenation of Thermometer-encoded Masks for the 16-bit SensorStrobe Channels */ +#define BITM_RTC_SSMSKOT_SS4MSKOT (_ADI_MSK_3(0x0000F000,0x0000F000U, uint16_t )) /* SensorStrobe Channel 4 on Time Control */ +#define BITM_RTC_SSMSKOT_SS3MSKOT (_ADI_MSK_3(0x00000F00,0x00000F00U, uint16_t )) /* SensorStrobe Channel 3 on Time Control */ +#define BITM_RTC_SSMSKOT_SS2MSKOT (_ADI_MSK_3(0x000000F0,0x000000F0U, uint16_t )) /* SensorStrobe Channel 2 on Time Control */ +#define BITM_RTC_SSMSKOT_SS1MSKOT (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t )) /* Concatenation of Thermometer-encoded Masks for the 16-bit SensorStrobe Channels */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR5SSS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR5SSS_SS3SMPMTCHIRQEN 11 /* Sample Activity Interrupt Enable for SensorStrobe Channel 3 */ +#define BITP_RTC_CR5SSS_SS3SMPEN 8 /* GPIO Input Sample Enable for SensorStrobe Channel 3 */ +#define BITP_RTC_CR5SSS_SS2SMPMTCHIRQEN 7 /* Sample Activity Interrupt Enable for SensorStrobe Channel 2 */ +#define BITP_RTC_CR5SSS_SS2SMPEN 4 /* GPIO Input Sample Enable for SensorStrobe Channel 2 */ +#define BITP_RTC_CR5SSS_SS1SMPMTCHIRQEN 3 /* Sample Activity Interrupt Enable for SensorStrobe Channel 1 */ +#define BITP_RTC_CR5SSS_SS1SMPEN 0 /* GPIO Input Sample Enable for SensorStrobe Channel 1 */ +#define BITM_RTC_CR5SSS_SS3SMPMTCHIRQEN (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Sample Activity Interrupt Enable for SensorStrobe Channel 3 */ +#define BITM_RTC_CR5SSS_SS3SMPEN (_ADI_MSK_3(0x00000700,0x00000700U, uint16_t )) /* GPIO Input Sample Enable for SensorStrobe Channel 3 */ +#define BITM_RTC_CR5SSS_SS2SMPMTCHIRQEN (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Sample Activity Interrupt Enable for SensorStrobe Channel 2 */ +#define BITM_RTC_CR5SSS_SS2SMPEN (_ADI_MSK_3(0x00000070,0x00000070U, uint16_t )) /* GPIO Input Sample Enable for SensorStrobe Channel 2 */ +#define BITM_RTC_CR5SSS_SS1SMPMTCHIRQEN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Sample Activity Interrupt Enable for SensorStrobe Channel 1 */ +#define BITM_RTC_CR5SSS_SS1SMPEN (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t )) /* GPIO Input Sample Enable for SensorStrobe Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR6SSS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR6SSS_SS3SMPONRE 10 /* GPIO Sample Around Rising Edge of SensorStrobe Channel 3 */ +#define BITP_RTC_CR6SSS_SS3SMPONFE 8 /* GPIO Sample Around Falling Edge of SensorStrobe Channel 3 */ +#define BITP_RTC_CR6SSS_SS2SMPONRE 6 /* GPIO Sample Around Rising Edge of SensorStrobe Channel 2 */ +#define BITP_RTC_CR6SSS_SS2SMPONFE 4 /* GPIO Sample Around Falling Edge of SensorStrobe Channel 2 */ +#define BITP_RTC_CR6SSS_SS1SMPONRE 2 /* GPIO Sample Around Rising Edge of SensorStrobe Channel 1 */ +#define BITP_RTC_CR6SSS_SS1SMPONFE 0 /* GPIO Sample Around Falling Edge of SensorStrobe Channel 1 */ +#define BITM_RTC_CR6SSS_SS3SMPONRE (_ADI_MSK_3(0x00000C00,0x00000C00U, uint16_t )) /* GPIO Sample Around Rising Edge of SensorStrobe Channel 3 */ +#define BITM_RTC_CR6SSS_SS3SMPONFE (_ADI_MSK_3(0x00000300,0x00000300U, uint16_t )) /* GPIO Sample Around Falling Edge of SensorStrobe Channel 3 */ +#define BITM_RTC_CR6SSS_SS2SMPONRE (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t )) /* GPIO Sample Around Rising Edge of SensorStrobe Channel 2 */ +#define BITM_RTC_CR6SSS_SS2SMPONFE (_ADI_MSK_3(0x00000030,0x00000030U, uint16_t )) /* GPIO Sample Around Falling Edge of SensorStrobe Channel 2 */ +#define BITM_RTC_CR6SSS_SS1SMPONRE (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t )) /* GPIO Sample Around Rising Edge of SensorStrobe Channel 1 */ +#define BITM_RTC_CR6SSS_SS1SMPONFE (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* GPIO Sample Around Falling Edge of SensorStrobe Channel 1 */ +#define ENUM_RTC_CR6SSS_SS3NORES (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS3SMPONRE: No sampling of input around rising edge */ +#define ENUM_RTC_CR6SSS_SS3BRES (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* SS3SMPONRE: Input sampled one clock cycle before rising edge of the SensorStrobe channel 3 */ +#define ENUM_RTC_CR6SSS_SS3RES (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* SS3SMPONRE: Input sampled at rising edge of the SensorStrobe channel 3 */ +#define ENUM_RTC_CR6SSS_SS3ARES (_ADI_MSK_3(0x00000C00,0x00000C00U, uint16_t )) /* SS3SMPONRE: Input sampled one clock cycle after rising edge of the SensorStrobe channel 3 */ +#define ENUM_RTC_CR6SSS_SS3NOFES (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS3SMPONFE: No sampling of input around falling edge */ +#define ENUM_RTC_CR6SSS_SS3BFES (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* SS3SMPONFE: Input sampled one clock cycle before falling edge of the SensorStrobe channel 3 */ +#define ENUM_RTC_CR6SSS_SS3FES (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* SS3SMPONFE: Input sampled at falling edge of the SensorStrobe channel 3 */ +#define ENUM_RTC_CR6SSS_SS3AFES (_ADI_MSK_3(0x00000300,0x00000300U, uint16_t )) /* SS3SMPONFE: Input sampled one clock cycle after falling edge of the SensorStrobe channel 3 */ +#define ENUM_RTC_CR6SSS_SS2NORES (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS2SMPONRE: No sampling of input around rising edge */ +#define ENUM_RTC_CR6SSS_SS2BRES (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* SS2SMPONRE: Input sampled one clock cycle before rising edge of the SensorStrobe channel 2 */ +#define ENUM_RTC_CR6SSS_SS2RES (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* SS2SMPONRE: Input sampled at rising edge of the SensorStrobe channel 2 */ +#define ENUM_RTC_CR6SSS_SS2ARES (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t )) /* SS2SMPONRE: Input sampled one clock cycle after rising edge of the SensorStrobe channel 2 */ +#define ENUM_RTC_CR6SSS_SS2NOFES (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS2SMPONFE: No sampling of input around falling edge */ +#define ENUM_RTC_CR6SSS_SS2BFES (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* SS2SMPONFE: Input sampled one clock cycle before falling edge of the SensorStrobe channel 2 */ +#define ENUM_RTC_CR6SSS_SS2FES (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* SS2SMPONFE: Input sampled at falling edge of the SensorStrobe channel 2 */ +#define ENUM_RTC_CR6SSS_SS2AFES (_ADI_MSK_3(0x00000030,0x00000030U, uint16_t )) /* SS2SMPONFE: Input sampled one clock cycle after falling edge of the SensorStrobe channel 2 */ +#define ENUM_RTC_CR6SSS_SS1NORES (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS1SMPONRE: No sampling of input around rising edge */ +#define ENUM_RTC_CR6SSS_SS1BRES (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* SS1SMPONRE: Input sampled one clock cycle before rising edge of the SensorStrobe channel 1 */ +#define ENUM_RTC_CR6SSS_SS1RES (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* SS1SMPONRE: Input sampled at rising edge of the SensorStrobe channel 1 */ +#define ENUM_RTC_CR6SSS_SS1ARES (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t )) /* SS1SMPONRE: Input sampled one clock cycle after rising edge of the SensorStrobe channel 1 */ +#define ENUM_RTC_CR6SSS_SS1NOFES (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS1SMPONFE: No sampling of input around falling edge */ +#define ENUM_RTC_CR6SSS_SS1BFES (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* SS1SMPONFE: Input sampled one clock cycle before falling edge of the SensorStrobe channel 1 */ +#define ENUM_RTC_CR6SSS_SS1FES (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* SS1SMPONFE: Input sampled at falling edge of the SensorStrobe channel 1 */ +#define ENUM_RTC_CR6SSS_SS1AFES (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* SS1SMPONFE: Input sampled one clock cycle after falling edge of the SensorStrobe channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR7SSS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR7SSS_SS3SMPPTRN 13 /* Sample Activity Selection for SensorStrobe Channel 3 */ +#define BITP_RTC_CR7SSS_SS3SMPEXP 10 /* Expected GPIO Sample for SensorStrobe Channel 3 */ +#define BITP_RTC_CR7SSS_SS2SMPPTRN 8 /* Sample Activity Selection for SensorStrobe Channel 2 */ +#define BITP_RTC_CR7SSS_SS2SMPEXP 5 /* Expected GPIO Sample for SensorStrobe Channel 2 */ +#define BITP_RTC_CR7SSS_SS1SMPPTRN 3 /* Sample Activity Selection for SensorStrobe Channel 1 */ +#define BITP_RTC_CR7SSS_SS1SMPEXP 0 /* Expected GPIO Sample for SensorStrobe Channel 1 */ +#define BITM_RTC_CR7SSS_SS3SMPPTRN (_ADI_MSK_3(0x00006000,0x00006000U, uint16_t )) /* Sample Activity Selection for SensorStrobe Channel 3 */ +#define BITM_RTC_CR7SSS_SS3SMPEXP (_ADI_MSK_3(0x00001C00,0x00001C00U, uint16_t )) /* Expected GPIO Sample for SensorStrobe Channel 3 */ +#define BITM_RTC_CR7SSS_SS2SMPPTRN (_ADI_MSK_3(0x00000300,0x00000300U, uint16_t )) /* Sample Activity Selection for SensorStrobe Channel 2 */ +#define BITM_RTC_CR7SSS_SS2SMPEXP (_ADI_MSK_3(0x000000E0,0x000000E0U, uint16_t )) /* Expected GPIO Sample for SensorStrobe Channel 2 */ +#define BITM_RTC_CR7SSS_SS1SMPPTRN (_ADI_MSK_3(0x00000018,0x00000018U, uint16_t )) /* Sample Activity Selection for SensorStrobe Channel 1 */ +#define BITM_RTC_CR7SSS_SS1SMPEXP (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t )) /* Expected GPIO Sample for SensorStrobe Channel 1 */ +#define ENUM_RTC_CR7SSS_SS3SMPCHNG (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS3SMPPTRN: Current GPIO sample is not same as previous sample */ +#define ENUM_RTC_CR7SSS_SS3SMPSAME (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* SS3SMPPTRN: Current GPIO sample is same as previous sample */ +#define ENUM_RTC_CR7SSS_SS3SMPMTCH (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* SS3SMPPTRN: Current GPIO sample is same as expected sample */ +#define ENUM_RTC_CR7SSS_SS3SMPNOMTCH (_ADI_MSK_3(0x00006000,0x00006000U, uint16_t )) /* SS3SMPPTRN: Current GPIO sample is not same as expected sample */ +#define ENUM_RTC_CR7SSS_SS2SMPCHNG (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS2SMPPTRN: Current GPIO sample is not same as previous sample */ +#define ENUM_RTC_CR7SSS_SS2SMPSAME (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* SS2SMPPTRN: Current GPIO sample is same as previous sample */ +#define ENUM_RTC_CR7SSS_SS2SMPMTCH (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* SS2SMPPTRN: Current GPIO sample is same as expected sample */ +#define ENUM_RTC_CR7SSS_SS2SMPNOMTCH (_ADI_MSK_3(0x00000300,0x00000300U, uint16_t )) /* SS2SMPPTRN: Current GPIO sample is not same as expected sample */ +#define ENUM_RTC_CR7SSS_SS1SMPCHNG (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS1SMPPTRN: Current GPIO sample is not same as previous sample */ +#define ENUM_RTC_CR7SSS_SS1SMPSAME (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* SS1SMPPTRN: Current GPIO sample is same as previous sample */ +#define ENUM_RTC_CR7SSS_SS1SMPMTCH (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* SS1SMPPTRN: Current GPIO sample is same as expected sample */ +#define ENUM_RTC_CR7SSS_SS1SMPNOMTCH (_ADI_MSK_3(0x00000018,0x00000018U, uint16_t )) /* SS1SMPPTRN: Current GPIO sample is not same as expected sample */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR7 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR7_SS4OUT 15 /* Output Value for SensorStrobe Channel 4 */ +#define BITP_RTC_SR7_SS3OUT 14 /* Output Value for SensorStrobe Channel 3 */ +#define BITP_RTC_SR7_SS2OUT 13 /* Output Value for SensorStrobe Channel 2 */ +#define BITP_RTC_SR7_SS1OUT 12 /* Output Value for SensorStrobe Channel 1 */ +#define BITP_RTC_SR7_SS3SMPMTCHIRQ 11 /* Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 3 */ +#define BITP_RTC_SR7_SS3SMP 8 /* Latest GPIO Sample for SensorStrobe Channel 3 */ +#define BITP_RTC_SR7_SS2SMPMTCHIRQ 7 /* Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 2 */ +#define BITP_RTC_SR7_SS2SMP 4 /* Latest GPIO Sample for SensorStrobe Channel 2 */ +#define BITP_RTC_SR7_SS1SMPMTCHIRQ 3 /* Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 1 */ +#define BITP_RTC_SR7_SS1SMP 0 /* Latest GPIO Sample for SensorStrobe Channel 1 */ +#define BITM_RTC_SR7_SS4OUT (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Output Value for SensorStrobe Channel 4 */ +#define BITM_RTC_SR7_SS3OUT (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Output Value for SensorStrobe Channel 3 */ +#define BITM_RTC_SR7_SS2OUT (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Output Value for SensorStrobe Channel 2 */ +#define BITM_RTC_SR7_SS1OUT (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Output Value for SensorStrobe Channel 1 */ +#define BITM_RTC_SR7_SS3SMPMTCHIRQ (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 3 */ +#define BITM_RTC_SR7_SS3SMP (_ADI_MSK_3(0x00000700,0x00000700U, uint16_t )) /* Latest GPIO Sample for SensorStrobe Channel 3 */ +#define BITM_RTC_SR7_SS2SMPMTCHIRQ (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 2 */ +#define BITM_RTC_SR7_SS2SMP (_ADI_MSK_3(0x00000070,0x00000070U, uint16_t )) /* Latest GPIO Sample for SensorStrobe Channel 2 */ +#define BITM_RTC_SR7_SS1SMPMTCHIRQ (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 1 */ +#define BITM_RTC_SR7_SS1SMP (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t )) /* Latest GPIO Sample for SensorStrobe Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR8 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR8_WSYNCGPMUX1 13 /* Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 1 */ +#define BITP_RTC_SR8_WSYNCGPMUX0 12 /* Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 0 */ +#define BITP_RTC_SR8_WSYNCSR7 11 /* Synchronisation Status of Posted Writes to Status 7 Register */ +#define BITP_RTC_SR8_WSYNCCR7SSS 10 /* Synchronisation Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR8_WSYNCCR6SSS 9 /* Synchronisation Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR8_WSYNCCR5SSS 8 /* Synchronisation Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR8_WSYNCSS3HIGHDUR 6 /* Synchronisation Status of Posted Writes to SensorStrobe Channel 3 High Duration Register */ +#define BITP_RTC_SR8_WSYNCSS2HIGHDUR 5 /* Synchronisation Status of Posted Writes to SensorStrobe Channel 2 High Duration Register */ +#define BITP_RTC_SR8_WSYNCSS1HIGHDUR 4 /* Synchronisation Status of Posted Writes to SensorStrobe Channel 1 High Duration Register */ +#define BITP_RTC_SR8_WSYNCSS3LOWDUR 2 /* Synchronisation Status of Posted Writes to SensorStrobe Channel 3 Low Duration Register */ +#define BITP_RTC_SR8_WSYNCSS2LOWDUR 1 /* Synchronisation Status of Posted Writes to SensorStrobe Channel 2 Low Duration Register */ +#define BITP_RTC_SR8_WSYNCSS1LOWDUR 0 /* Synchronisation Status of Posted Writes to SensorStrobe Channel 1 Low Duration Register */ +#define BITM_RTC_SR8_WSYNCGPMUX1 (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 1 */ +#define BITM_RTC_SR8_WSYNCGPMUX0 (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 0 */ +#define BITM_RTC_SR8_WSYNCSR7 (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Synchronisation Status of Posted Writes to Status 7 Register */ +#define BITM_RTC_SR8_WSYNCCR7SSS (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Synchronisation Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR8_WSYNCCR6SSS (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Synchronisation Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR8_WSYNCCR5SSS (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Synchronisation Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR8_WSYNCSS3HIGHDUR (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Synchronisation Status of Posted Writes to SensorStrobe Channel 3 High Duration Register */ +#define BITM_RTC_SR8_WSYNCSS2HIGHDUR (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Synchronisation Status of Posted Writes to SensorStrobe Channel 2 High Duration Register */ +#define BITM_RTC_SR8_WSYNCSS1HIGHDUR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Synchronisation Status of Posted Writes to SensorStrobe Channel 1 High Duration Register */ +#define BITM_RTC_SR8_WSYNCSS3LOWDUR (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Synchronisation Status of Posted Writes to SensorStrobe Channel 3 Low Duration Register */ +#define BITM_RTC_SR8_WSYNCSS2LOWDUR (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Synchronisation Status of Posted Writes to SensorStrobe Channel 2 Low Duration Register */ +#define BITM_RTC_SR8_WSYNCSS1LOWDUR (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Synchronisation Status of Posted Writes to SensorStrobe Channel 1 Low Duration Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR9 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR9_WPENDGPMUX1 13 /* Pending Status of Posted Writes to GPMUX1 */ +#define BITP_RTC_SR9_WPENDGPMUX0 12 /* Pending Status of Posted Writes to GPMUX0 */ +#define BITP_RTC_SR9_WPENDSR7 11 /* Pending Status of Posted Writes to SR7 */ +#define BITP_RTC_SR9_WPENDCR7SSS 10 /* Pending Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR9_WPENDCR6SSS 9 /* Pending Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR9_WPENDCR5SSS 8 /* Pending Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR9_WPENDSS3HIGHDUR 6 /* Pending Status of Posted Writes to SensortStrobe Channel 3 High Duration Register */ +#define BITP_RTC_SR9_WPENDSS2HIGHDUR 5 /* Pending Status of Posted Writes to SensortStrobe Channel 2 High Duration Register */ +#define BITP_RTC_SR9_WPENDSS1HIGHDUR 4 /* Pending Status of Posted Writes to SensortStrobe Channel 1 High Duration Register */ +#define BITP_RTC_SR9_WPENDSS3LOWDUR 2 /* Pending Status of Posted Writes to SensortStrobe Channel 3 Low Duration Register */ +#define BITP_RTC_SR9_WPENDSS2LOWDUR 1 /* Pending Status of Posted Writes to SensortStrobe Channel 2 Low Duration Register */ +#define BITP_RTC_SR9_WPENDSS1LOWDUR 0 /* Pending Status of Posted Writes to SensortStrobe Channel 1 Low Duration Register */ +#define BITM_RTC_SR9_WPENDGPMUX1 (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Pending Status of Posted Writes to GPMUX1 */ +#define BITM_RTC_SR9_WPENDGPMUX0 (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Pending Status of Posted Writes to GPMUX0 */ +#define BITM_RTC_SR9_WPENDSR7 (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Pending Status of Posted Writes to SR7 */ +#define BITM_RTC_SR9_WPENDCR7SSS (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Pending Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR9_WPENDCR6SSS (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Pending Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR9_WPENDCR5SSS (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Pending Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR9_WPENDSS3HIGHDUR (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Pending Status of Posted Writes to SensortStrobe Channel 3 High Duration Register */ +#define BITM_RTC_SR9_WPENDSS2HIGHDUR (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Pending Status of Posted Writes to SensortStrobe Channel 2 High Duration Register */ +#define BITM_RTC_SR9_WPENDSS1HIGHDUR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Pending Status of Posted Writes to SensortStrobe Channel 1 High Duration Register */ +#define BITM_RTC_SR9_WPENDSS3LOWDUR (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Pending Status of Posted Writes to SensortStrobe Channel 3 Low Duration Register */ +#define BITM_RTC_SR9_WPENDSS2LOWDUR (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Pending Status of Posted Writes to SensortStrobe Channel 2 Low Duration Register */ +#define BITM_RTC_SR9_WPENDSS1LOWDUR (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Pending Status of Posted Writes to SensortStrobe Channel 1 Low Duration Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_GPMUX0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_GPMUX0_SS2GPIN1SEL 12 /* GPIO Mux Selection for SensorStrobe Channel 2 Input 1 */ +#define BITP_RTC_GPMUX0_SS2GPIN0SEL 9 /* GPIO Mux Selection for SensorStrobe Channel 2 Input 0 */ +#define BITP_RTC_GPMUX0_SS1GPIN2SEL 6 /* GPIO Mux Selection for SensorStrobe Channel 1 Input 2 */ +#define BITP_RTC_GPMUX0_SS1GPIN1SEL 3 /* GPIO Mux Selection for SensorStrobe Channel 1 Input 1 */ +#define BITP_RTC_GPMUX0_SS1GPIN0SEL 0 /* GPIO Mux Selection for SensorStrobe Channel 1 Input0 */ +#define BITM_RTC_GPMUX0_SS2GPIN1SEL (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t )) /* GPIO Mux Selection for SensorStrobe Channel 2 Input 1 */ +#define BITM_RTC_GPMUX0_SS2GPIN0SEL (_ADI_MSK_3(0x00000E00,0x00000E00U, uint16_t )) /* GPIO Mux Selection for SensorStrobe Channel 2 Input 0 */ +#define BITM_RTC_GPMUX0_SS1GPIN2SEL (_ADI_MSK_3(0x000001C0,0x000001C0U, uint16_t )) /* GPIO Mux Selection for SensorStrobe Channel 1 Input 2 */ +#define BITM_RTC_GPMUX0_SS1GPIN1SEL (_ADI_MSK_3(0x00000038,0x00000038U, uint16_t )) /* GPIO Mux Selection for SensorStrobe Channel 1 Input 1 */ +#define BITM_RTC_GPMUX0_SS1GPIN0SEL (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t )) /* GPIO Mux Selection for SensorStrobe Channel 1 Input0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_GPMUX1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_GPMUX1_SS3DIFFOUT 15 /* Differential SensorStrobe Out Option for SensorStrobe Channel 3 */ +#define BITP_RTC_GPMUX1_SS1DIFFOUT 14 /* Differential SensorStrobe Out Option for SensorStrobe Channel 1 */ +#define BITP_RTC_GPMUX1_SS3GPIN2SEL 9 /* GPIO Mux Selection for SensorStrobe Channel 3 Input 2 */ +#define BITP_RTC_GPMUX1_SS3GPIN1SEL 6 /* GPIO Mux Selection for SensorStrobe Channel 3 Input 1 */ +#define BITP_RTC_GPMUX1_SS3GPIN0SEL 3 /* GPIO Mux Selection for SensorStrobe Channel 3 Input 0 */ +#define BITP_RTC_GPMUX1_SS2GPIN2SEL 0 /* GPIO Mux Selection for SensorStrobe Channel 2 Input 2 */ +#define BITM_RTC_GPMUX1_SS3DIFFOUT (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Differential SensorStrobe Out Option for SensorStrobe Channel 3 */ +#define BITM_RTC_GPMUX1_SS1DIFFOUT (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Differential SensorStrobe Out Option for SensorStrobe Channel 1 */ +#define BITM_RTC_GPMUX1_SS3GPIN2SEL (_ADI_MSK_3(0x00000E00,0x00000E00U, uint16_t )) /* GPIO Mux Selection for SensorStrobe Channel 3 Input 2 */ +#define BITM_RTC_GPMUX1_SS3GPIN1SEL (_ADI_MSK_3(0x000001C0,0x000001C0U, uint16_t )) /* GPIO Mux Selection for SensorStrobe Channel 3 Input 1 */ +#define BITM_RTC_GPMUX1_SS3GPIN0SEL (_ADI_MSK_3(0x00000038,0x00000038U, uint16_t )) /* GPIO Mux Selection for SensorStrobe Channel 3 Input 0 */ +#define BITM_RTC_GPMUX1_SS2GPIN2SEL (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t )) /* GPIO Mux Selection for SensorStrobe Channel 2 Input 2 */ + + +/* ============================================================================================================================ + System Identification and Debug Enable + ============================================================================================================================ */ + +/* ============================================================================================================================ + SYS + ============================================================================================================================ */ +#define REG_SYS_ADIID 0x40002020 /* SYS ADI Identification */ +#define REG_SYS_CHIPID 0x40002024 /* SYS Chip Identifier */ +#define REG_SYS_SWDEN 0x40002040 /* SYS Serial Wire Debug Enable */ + +/* ============================================================================================================================ + SYS Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + SYS_ADIID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SYS_ADIID_VALUE 0 /* Reads a fixed value of 0x4144 to indicate to debuggers that they are connected to an Analog Devices implemented Cortex based part */ +#define BITM_SYS_ADIID_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Reads a fixed value of 0x4144 to indicate to debuggers that they are connected to an Analog Devices implemented Cortex based part */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SYS_CHIPID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SYS_CHIPID_PARTID 4 /* Part identifier */ +#define BITP_SYS_CHIPID_REV 0 /* Silicon revision */ +#define BITM_SYS_CHIPID_PARTID (_ADI_MSK_3(0x0000FFF0,0x0000FFF0U, uint16_t )) /* Part identifier */ +#define BITM_SYS_CHIPID_REV (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t )) /* Silicon revision */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SYS_SWDEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SYS_SWDEN_VALUE 0 /* To enable SWD interface */ +#define BITM_SYS_SWDEN_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* To enable SWD interface */ + + +/* ============================================================================================================================ + Watchdog Timer + ============================================================================================================================ */ + +/* ============================================================================================================================ + WDT0 + ============================================================================================================================ */ +#define REG_WDT0_LOAD 0x40002C00 /* WDT0 Load Value */ +#define REG_WDT0_CCNT 0x40002C04 /* WDT0 Current Count Value */ +#define REG_WDT0_CTL 0x40002C08 /* WDT0 Control */ +#define REG_WDT0_RESTART 0x40002C0C /* WDT0 Clear Interrupt */ +#define REG_WDT0_STAT 0x40002C18 /* WDT0 Status */ + +/* ============================================================================================================================ + WDT Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + WDT_LOAD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WDT_LOAD_VALUE 0 /* Load Value */ +#define BITM_WDT_LOAD_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Load Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WDT_CCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WDT_CCNT_VALUE 0 /* Current Count Value */ +#define BITM_WDT_CCNT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Current Count Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WDT_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WDT_CTL_SPARE 7 /* Unused Spare Bit */ +#define BITP_WDT_CTL_MODE 6 /* Timer Mode */ +#define BITP_WDT_CTL_EN 5 /* Timer Enable */ +#define BITP_WDT_CTL_PRE 2 /* Prescaler */ +#define BITP_WDT_CTL_IRQ 1 /* Timer Interrupt */ +#define BITM_WDT_CTL_SPARE (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Unused Spare Bit */ +#define BITM_WDT_CTL_MODE (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Timer Mode */ +#define BITM_WDT_CTL_EN (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Timer Enable */ +#define BITM_WDT_CTL_PRE (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t )) /* Prescaler */ +#define BITM_WDT_CTL_IRQ (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Timer Interrupt */ +#define ENUM_WDT_CTL_FREE_RUN (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* MODE: Free running mode */ +#define ENUM_WDT_CTL_PERIODIC (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* MODE: Periodic mode */ +#define ENUM_WDT_CTL_WDT_DIS (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* EN: WDT not enabled */ +#define ENUM_WDT_CTL_WDT_EN (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* EN: WDT enabled */ +#define ENUM_WDT_CTL_DIV1 (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* PRE: Source clock/1 */ +#define ENUM_WDT_CTL_DIV16 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* PRE: Source clock/16 */ +#define ENUM_WDT_CTL_DIV256 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* PRE: Source clock/256 (default) */ +#define ENUM_WDT_CTL_RST (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* IRQ: WDT asserts reset when timed out */ +#define ENUM_WDT_CTL_INT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* IRQ: WDT generates interrupt when timed out */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WDT_RESTART Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WDT_RESTART_CLRWORD 0 /* Clear Watchdog */ +#define BITM_WDT_RESTART_CLRWORD (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Clear Watchdog */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WDT_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WDT_STAT_RSTCTL 5 /* Reset Control Register Written and Locked */ +#define BITP_WDT_STAT_LOCKED 4 /* Lock Status Bit */ +#define BITP_WDT_STAT_COUNTING 3 /* Control Register Write Sync in Progress */ +#define BITP_WDT_STAT_LOADING 2 /* Load Register Write Sync in Progress */ +#define BITP_WDT_STAT_CLRIRQ 1 /* Clear Interrupt Register Write Sync in Progress */ +#define BITP_WDT_STAT_IRQ 0 /* WDT Interrupt */ +#define BITM_WDT_STAT_RSTCTL (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Reset Control Register Written and Locked */ +#define BITM_WDT_STAT_LOCKED (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Lock Status Bit */ +#define BITM_WDT_STAT_COUNTING (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Control Register Write Sync in Progress */ +#define BITM_WDT_STAT_LOADING (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Load Register Write Sync in Progress */ +#define BITM_WDT_STAT_CLRIRQ (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Clear Interrupt Register Write Sync in Progress */ +#define BITM_WDT_STAT_IRQ (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* WDT Interrupt */ + + +/* ============================================================================================================================ + I2C Master/Slave + ============================================================================================================================ */ + +/* ============================================================================================================================ + I2C0 + ============================================================================================================================ */ +#define REG_I2C0_MCTL 0x40003000 /* I2C0 Master Control */ +#define REG_I2C0_MSTAT 0x40003004 /* I2C0 Master Status */ +#define REG_I2C0_MRX 0x40003008 /* I2C0 Master Receive Data */ +#define REG_I2C0_MTX 0x4000300C /* I2C0 Master Transmit Data */ +#define REG_I2C0_MRXCNT 0x40003010 /* I2C0 Master Receive Data Count */ +#define REG_I2C0_MCRXCNT 0x40003014 /* I2C0 Master Current Receive Data Count */ +#define REG_I2C0_ADDR1 0x40003018 /* I2C0 Master Address Byte 1 */ +#define REG_I2C0_ADDR2 0x4000301C /* I2C0 Master Address Byte 2 */ +#define REG_I2C0_BYT 0x40003020 /* I2C0 Start Byte */ +#define REG_I2C0_DIV 0x40003024 /* I2C0 Serial Clock Period Divisor */ +#define REG_I2C0_SCTL 0x40003028 /* I2C0 Slave Control */ +#define REG_I2C0_SSTAT 0x4000302C /* I2C0 Slave I2C Status/Error/IRQ */ +#define REG_I2C0_SRX 0x40003030 /* I2C0 Slave Receive */ +#define REG_I2C0_STX 0x40003034 /* I2C0 Slave Transmit */ +#define REG_I2C0_ALT 0x40003038 /* I2C0 Hardware General Call ID */ +#define REG_I2C0_ID0 0x4000303C /* I2C0 First Slave Address Device ID */ +#define REG_I2C0_ID1 0x40003040 /* I2C0 Second Slave Address Device ID */ +#define REG_I2C0_ID2 0x40003044 /* I2C0 Third Slave Address Device ID */ +#define REG_I2C0_ID3 0x40003048 /* I2C0 Fourth Slave Address Device ID */ +#define REG_I2C0_STAT 0x4000304C /* I2C0 Master and Slave FIFO Status */ +#define REG_I2C0_SHCTL 0x40003050 /* I2C0 Shared Control */ +#define REG_I2C0_TCTL 0x40003054 /* I2C0 Timing Control Register */ +#define REG_I2C0_ASTRETCH_SCL 0x40003058 /* I2C0 Automatic Stretch SCL */ + +/* ============================================================================================================================ + I2C Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_MCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_MCTL_STOPBUSCLR 13 /* Prestop Bus Clear */ +#define BITP_I2C_MCTL_BUSCLR 12 /* Bus-Clear Enable */ +#define BITP_I2C_MCTL_MTXDMA 11 /* Enable Master Tx DMA Request */ +#define BITP_I2C_MCTL_MRXDMA 10 /* Enable Master Rx DMA Request */ +#define BITP_I2C_MCTL_MXMITDEC 9 /* Decrement Master Tx FIFO Status When a Byte Txed */ +#define BITP_I2C_MCTL_IENCMP 8 /* Transaction Completed (or Stop Detected) Interrupt Enable */ +#define BITP_I2C_MCTL_IENACK 7 /* ACK Not Received Interrupt Enable */ +#define BITP_I2C_MCTL_IENALOST 6 /* Arbitration Lost Interrupt Enable */ +#define BITP_I2C_MCTL_IENMTX 5 /* Transmit Request Interrupt Enable */ +#define BITP_I2C_MCTL_IENMRX 4 /* Receive Request Interrupt Enable */ +#define BITP_I2C_MCTL_STRETCHSCL 3 /* Stretch SCL Enable */ +#define BITP_I2C_MCTL_LOOPBACK 2 /* Internal Loopback Enable */ +#define BITP_I2C_MCTL_COMPLETE 1 /* Start Back-off Disable */ +#define BITP_I2C_MCTL_MASEN 0 /* Master Enable */ +#define BITM_I2C_MCTL_STOPBUSCLR (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Prestop Bus Clear */ +#define BITM_I2C_MCTL_BUSCLR (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Bus-Clear Enable */ +#define BITM_I2C_MCTL_MTXDMA (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Enable Master Tx DMA Request */ +#define BITM_I2C_MCTL_MRXDMA (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Enable Master Rx DMA Request */ +#define BITM_I2C_MCTL_MXMITDEC (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Decrement Master Tx FIFO Status When a Byte Txed */ +#define BITM_I2C_MCTL_IENCMP (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Transaction Completed (or Stop Detected) Interrupt Enable */ +#define BITM_I2C_MCTL_IENACK (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* ACK Not Received Interrupt Enable */ +#define BITM_I2C_MCTL_IENALOST (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Arbitration Lost Interrupt Enable */ +#define BITM_I2C_MCTL_IENMTX (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Transmit Request Interrupt Enable */ +#define BITM_I2C_MCTL_IENMRX (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Receive Request Interrupt Enable */ +#define BITM_I2C_MCTL_STRETCHSCL (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Stretch SCL Enable */ +#define BITM_I2C_MCTL_LOOPBACK (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Internal Loopback Enable */ +#define BITM_I2C_MCTL_COMPLETE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Start Back-off Disable */ +#define BITM_I2C_MCTL_MASEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Master Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_MSTAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_MSTAT_SCLFILT 14 /* State of SCL Line */ +#define BITP_I2C_MSTAT_SDAFILT 13 /* State of SDA Line */ +#define BITP_I2C_MSTAT_MTXUNDR 12 /* Master Transmit Underflow */ +#define BITP_I2C_MSTAT_MSTOP 11 /* STOP Driven by This I2C Master */ +#define BITP_I2C_MSTAT_LINEBUSY 10 /* Line is Busy */ +#define BITP_I2C_MSTAT_MRXOVR 9 /* Master Receive FIFO Overflow */ +#define BITP_I2C_MSTAT_TCOMP 8 /* Transaction Complete or Stop Detected */ +#define BITP_I2C_MSTAT_NACKDATA 7 /* ACK Not Received in Response to Data Write */ +#define BITP_I2C_MSTAT_MBUSY 6 /* Master Busy */ +#define BITP_I2C_MSTAT_ALOST 5 /* Arbitration Lost */ +#define BITP_I2C_MSTAT_NACKADDR 4 /* ACK Not Received in Response to an Address */ +#define BITP_I2C_MSTAT_MRXREQ 3 /* Master Receive Request */ +#define BITP_I2C_MSTAT_MTXREQ 2 /* Master Transmit Request/Clear Master Transmit Interrupt */ +#define BITP_I2C_MSTAT_MTXF 0 /* Master Transmit FIFO Status */ +#define BITM_I2C_MSTAT_SCLFILT (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* State of SCL Line */ +#define BITM_I2C_MSTAT_SDAFILT (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* State of SDA Line */ +#define BITM_I2C_MSTAT_MTXUNDR (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Master Transmit Underflow */ +#define BITM_I2C_MSTAT_MSTOP (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* STOP Driven by This I2C Master */ +#define BITM_I2C_MSTAT_LINEBUSY (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Line is Busy */ +#define BITM_I2C_MSTAT_MRXOVR (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Master Receive FIFO Overflow */ +#define BITM_I2C_MSTAT_TCOMP (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Transaction Complete or Stop Detected */ +#define BITM_I2C_MSTAT_NACKDATA (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* ACK Not Received in Response to Data Write */ +#define BITM_I2C_MSTAT_MBUSY (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Master Busy */ +#define BITM_I2C_MSTAT_ALOST (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Arbitration Lost */ +#define BITM_I2C_MSTAT_NACKADDR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* ACK Not Received in Response to an Address */ +#define BITM_I2C_MSTAT_MRXREQ (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Master Receive Request */ +#define BITM_I2C_MSTAT_MTXREQ (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Master Transmit Request/Clear Master Transmit Interrupt */ +#define BITM_I2C_MSTAT_MTXF (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Master Transmit FIFO Status */ +#define ENUM_I2C_MSTAT_FIFO_EMPTY (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* MTXF: FIFO Empty. */ +#define ENUM_I2C_MSTAT_FIFO_1BYTE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* MTXF: 1 byte in FIFO. */ +#define ENUM_I2C_MSTAT_FIFO_FULL (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* MTXF: FIFO Full. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_MRX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_MRX_VALUE 0 /* Master Receive Register */ +#define BITM_I2C_MRX_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Master Receive Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_MTX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_MTX_VALUE 0 /* Master Transmit Register */ +#define BITM_I2C_MTX_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Master Transmit Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_MRXCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_MRXCNT_EXTEND 8 /* Extended Read */ +#define BITP_I2C_MRXCNT_VALUE 0 /* Receive Count */ +#define BITM_I2C_MRXCNT_EXTEND (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Extended Read */ +#define BITM_I2C_MRXCNT_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Receive Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_MCRXCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_MCRXCNT_VALUE 0 /* Current Receive Count */ +#define BITM_I2C_MCRXCNT_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Current Receive Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ADDR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ADDR1_VALUE 0 /* Address Byte 1 */ +#define BITM_I2C_ADDR1_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Address Byte 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ADDR2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ADDR2_VALUE 0 /* Address Byte 2 */ +#define BITM_I2C_ADDR2_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Address Byte 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_BYT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_BYT_SBYTE 0 /* Start Byte */ +#define BITM_I2C_BYT_SBYTE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Start Byte */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_DIV Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_DIV_HIGH 8 /* Serial Clock High Time */ +#define BITP_I2C_DIV_LOW 0 /* Serial Clock Low Time */ +#define BITM_I2C_DIV_HIGH (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t )) /* Serial Clock High Time */ +#define BITM_I2C_DIV_LOW (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Serial Clock Low Time */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_SCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_SCTL_STXDMA 14 /* Enable Slave Tx DMA Request */ +#define BITP_I2C_SCTL_SRXDMA 13 /* Enable Slave Rx DMA Request */ +#define BITP_I2C_SCTL_IENREPST 12 /* Repeated Start Interrupt Enable */ +#define BITP_I2C_SCTL_STXDEC 11 /* Decrement Slave Tx FIFO Status When a Byte is Txed */ +#define BITP_I2C_SCTL_IENSTX 10 /* Slave Transmit Request Interrupt Enable */ +#define BITP_I2C_SCTL_IENSRX 9 /* Slave Receive Request Interrupt Enable */ +#define BITP_I2C_SCTL_IENSTOP 8 /* Stop Condition Detected Interrupt Enable */ +#define BITP_I2C_SCTL_NACK 7 /* NACK Next Communication */ +#define BITP_I2C_SCTL_EARLYTXR 5 /* Early Transmit Request Mode */ +#define BITP_I2C_SCTL_GCSBCLR 4 /* General Call Status Bit Clear */ +#define BITP_I2C_SCTL_HGCEN 3 /* Hardware General Call Enable */ +#define BITP_I2C_SCTL_GCEN 2 /* General Call Enable */ +#define BITP_I2C_SCTL_ADR10EN 1 /* Enabled 10-bit Addressing */ +#define BITP_I2C_SCTL_SLVEN 0 /* Slave Enable */ +#define BITM_I2C_SCTL_STXDMA (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Enable Slave Tx DMA Request */ +#define BITM_I2C_SCTL_SRXDMA (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Enable Slave Rx DMA Request */ +#define BITM_I2C_SCTL_IENREPST (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Repeated Start Interrupt Enable */ +#define BITM_I2C_SCTL_STXDEC (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Decrement Slave Tx FIFO Status When a Byte is Txed */ +#define BITM_I2C_SCTL_IENSTX (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Slave Transmit Request Interrupt Enable */ +#define BITM_I2C_SCTL_IENSRX (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Slave Receive Request Interrupt Enable */ +#define BITM_I2C_SCTL_IENSTOP (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Stop Condition Detected Interrupt Enable */ +#define BITM_I2C_SCTL_NACK (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* NACK Next Communication */ +#define BITM_I2C_SCTL_EARLYTXR (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Early Transmit Request Mode */ +#define BITM_I2C_SCTL_GCSBCLR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* General Call Status Bit Clear */ +#define BITM_I2C_SCTL_HGCEN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Hardware General Call Enable */ +#define BITM_I2C_SCTL_GCEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* General Call Enable */ +#define BITM_I2C_SCTL_ADR10EN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enabled 10-bit Addressing */ +#define BITM_I2C_SCTL_SLVEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Slave Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_SSTAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_SSTAT_START 14 /* Start and Matching Address */ +#define BITP_I2C_SSTAT_REPSTART 13 /* Repeated Start and Matching Address */ +#define BITP_I2C_SSTAT_IDMAT 11 /* Device ID Matched */ +#define BITP_I2C_SSTAT_STOP 10 /* Stop After Start and Matching Address */ +#define BITP_I2C_SSTAT_GCID 8 /* General ID */ +#define BITP_I2C_SSTAT_GCINT 7 /* General Call Interrupt */ +#define BITP_I2C_SSTAT_SBUSY 6 /* Slave Busy */ +#define BITP_I2C_SSTAT_NOACK 5 /* ACK Not Generated by the Slave */ +#define BITP_I2C_SSTAT_SRXOVR 4 /* Slave Receive FIFO Overflow */ +#define BITP_I2C_SSTAT_SRXREQ 3 /* Slave Receive Request */ +#define BITP_I2C_SSTAT_STXREQ 2 /* Slave Transmit Request/Slave Transmit Interrupt */ +#define BITP_I2C_SSTAT_STXUNDR 1 /* Slave Transmit FIFO Underflow */ +#define BITP_I2C_SSTAT_STXFSEREQ 0 /* Slave Tx FIFO Status or Early Request */ +#define BITM_I2C_SSTAT_START (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Start and Matching Address */ +#define BITM_I2C_SSTAT_REPSTART (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Repeated Start and Matching Address */ +#define BITM_I2C_SSTAT_IDMAT (_ADI_MSK_3(0x00001800,0x00001800U, uint16_t )) /* Device ID Matched */ +#define BITM_I2C_SSTAT_STOP (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Stop After Start and Matching Address */ +#define BITM_I2C_SSTAT_GCID (_ADI_MSK_3(0x00000300,0x00000300U, uint16_t )) /* General ID */ +#define BITM_I2C_SSTAT_GCINT (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* General Call Interrupt */ +#define BITM_I2C_SSTAT_SBUSY (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Slave Busy */ +#define BITM_I2C_SSTAT_NOACK (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* ACK Not Generated by the Slave */ +#define BITM_I2C_SSTAT_SRXOVR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Slave Receive FIFO Overflow */ +#define BITM_I2C_SSTAT_SRXREQ (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Slave Receive Request */ +#define BITM_I2C_SSTAT_STXREQ (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Slave Transmit Request/Slave Transmit Interrupt */ +#define BITM_I2C_SSTAT_STXUNDR (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Slave Transmit FIFO Underflow */ +#define BITM_I2C_SSTAT_STXFSEREQ (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Slave Tx FIFO Status or Early Request */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_SRX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_SRX_VALUE 0 /* Slave Receive Register */ +#define BITM_I2C_SRX_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Receive Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_STX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_STX_VALUE 0 /* Slave Transmit Register */ +#define BITM_I2C_STX_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Transmit Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ALT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ALT_ID 0 /* Slave Alt */ +#define BITM_I2C_ALT_ID (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Alt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ID0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ID0_VALUE 0 /* Slave Device ID 0 */ +#define BITM_I2C_ID0_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Device ID 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ID1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ID1_VALUE 0 /* Slave Device ID 1 */ +#define BITM_I2C_ID1_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Device ID 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ID2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ID2_VALUE 0 /* Slave Device ID 2 */ +#define BITM_I2C_ID2_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Device ID 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ID3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ID3_VALUE 0 /* Slave Device ID 3 */ +#define BITM_I2C_ID3_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Device ID 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_STAT_MFLUSH 9 /* Flush the Master Transmit FIFO */ +#define BITP_I2C_STAT_SFLUSH 8 /* Flush the Slave Transmit FIFO */ +#define BITP_I2C_STAT_MRXF 6 /* Master Receive FIFO Status */ +#define BITP_I2C_STAT_MTXF 4 /* Master Transmit FIFO Status */ +#define BITP_I2C_STAT_SRXF 2 /* Slave Receive FIFO Status */ +#define BITP_I2C_STAT_STXF 0 /* Slave Transmit FIFO Status */ +#define BITM_I2C_STAT_MFLUSH (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Flush the Master Transmit FIFO */ +#define BITM_I2C_STAT_SFLUSH (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Flush the Slave Transmit FIFO */ +#define BITM_I2C_STAT_MRXF (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t )) /* Master Receive FIFO Status */ +#define BITM_I2C_STAT_MTXF (_ADI_MSK_3(0x00000030,0x00000030U, uint16_t )) /* Master Transmit FIFO Status */ +#define BITM_I2C_STAT_SRXF (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t )) /* Slave Receive FIFO Status */ +#define BITM_I2C_STAT_STXF (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Slave Transmit FIFO Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_SHCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_SHCTL_RST 0 /* Reset START STOP Detect Circuit */ +#define BITM_I2C_SHCTL_RST (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Reset START STOP Detect Circuit */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_TCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_TCTL_FILTEROFF 8 /* Input Filter Control */ +#define BITP_I2C_TCTL_THDATIN 0 /* Data in Hold Start */ +#define BITM_I2C_TCTL_FILTEROFF (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Input Filter Control */ +#define BITM_I2C_TCTL_THDATIN (_ADI_MSK_3(0x0000001F,0x0000001FU, uint16_t )) /* Data in Hold Start */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ASTRETCH_SCL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ASTRETCH_SCL_SLVTMO 9 /* Slave Automatic Stretch Timeout */ +#define BITP_I2C_ASTRETCH_SCL_MSTTMO 8 /* Master Automatic Stretch Timeout */ +#define BITP_I2C_ASTRETCH_SCL_SLV 4 /* Slave Automatic Stretch Mode */ +#define BITP_I2C_ASTRETCH_SCL_MST 0 /* Master Automatic Stretch Mode */ +#define BITM_I2C_ASTRETCH_SCL_SLVTMO (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Slave Automatic Stretch Timeout */ +#define BITM_I2C_ASTRETCH_SCL_MSTTMO (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Master Automatic Stretch Timeout */ +#define BITM_I2C_ASTRETCH_SCL_SLV (_ADI_MSK_3(0x000000F0,0x000000F0U, uint16_t )) /* Slave Automatic Stretch Mode */ +#define BITM_I2C_ASTRETCH_SCL_MST (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t )) /* Master Automatic Stretch Mode */ + + +/* ============================================================================================================================ + Serial Peripheral Interface + ============================================================================================================================ */ + +/* ============================================================================================================================ + SPI0 + ============================================================================================================================ */ +#define REG_SPI0_STAT 0x40004000 /* SPI0 Status */ +#define REG_SPI0_RX 0x40004004 /* SPI0 Receive */ +#define REG_SPI0_TX 0x40004008 /* SPI0 Transmit */ +#define REG_SPI0_DIV 0x4000400C /* SPI0 SPI Baud Rate Selection */ +#define REG_SPI0_CTL 0x40004010 /* SPI0 SPI Configuration */ +#define REG_SPI0_IEN 0x40004014 /* SPI0 SPI Interrupts Enable */ +#define REG_SPI0_CNT 0x40004018 /* SPI0 Transfer Byte Count */ +#define REG_SPI0_DMA 0x4000401C /* SPI0 SPI DMA Enable */ +#define REG_SPI0_FIFO_STAT 0x40004020 /* SPI0 FIFO Status */ +#define REG_SPI0_RD_CTL 0x40004024 /* SPI0 Read Control */ +#define REG_SPI0_FLOW_CTL 0x40004028 /* SPI0 Flow Control */ +#define REG_SPI0_WAIT_TMR 0x4000402C /* SPI0 Wait Timer for Flow Control */ +#define REG_SPI0_CS_CTL 0x40004030 /* SPI0 Chip Select Control for Multi-slave Connections */ +#define REG_SPI0_CS_OVERRIDE 0x40004034 /* SPI0 Chip Select Override */ + +/* ============================================================================================================================ + SPI1 + ============================================================================================================================ */ +#define REG_SPI1_STAT 0x40004400 /* SPI1 Status */ +#define REG_SPI1_RX 0x40004404 /* SPI1 Receive */ +#define REG_SPI1_TX 0x40004408 /* SPI1 Transmit */ +#define REG_SPI1_DIV 0x4000440C /* SPI1 SPI Baud Rate Selection */ +#define REG_SPI1_CTL 0x40004410 /* SPI1 SPI Configuration */ +#define REG_SPI1_IEN 0x40004414 /* SPI1 SPI Interrupts Enable */ +#define REG_SPI1_CNT 0x40004418 /* SPI1 Transfer Byte Count */ +#define REG_SPI1_DMA 0x4000441C /* SPI1 SPI DMA Enable */ +#define REG_SPI1_FIFO_STAT 0x40004420 /* SPI1 FIFO Status */ +#define REG_SPI1_RD_CTL 0x40004424 /* SPI1 Read Control */ +#define REG_SPI1_FLOW_CTL 0x40004428 /* SPI1 Flow Control */ +#define REG_SPI1_WAIT_TMR 0x4000442C /* SPI1 Wait Timer for Flow Control */ +#define REG_SPI1_CS_CTL 0x40004430 /* SPI1 Chip Select Control for Multi-slave Connections */ +#define REG_SPI1_CS_OVERRIDE 0x40004434 /* SPI1 Chip Select Override */ + +/* ============================================================================================================================ + SPI2 + ============================================================================================================================ */ +#define REG_SPI2_STAT 0x40024000 /* SPI2 Status */ +#define REG_SPI2_RX 0x40024004 /* SPI2 Receive */ +#define REG_SPI2_TX 0x40024008 /* SPI2 Transmit */ +#define REG_SPI2_DIV 0x4002400C /* SPI2 SPI Baud Rate Selection */ +#define REG_SPI2_CTL 0x40024010 /* SPI2 SPI Configuration */ +#define REG_SPI2_IEN 0x40024014 /* SPI2 SPI Interrupts Enable */ +#define REG_SPI2_CNT 0x40024018 /* SPI2 Transfer Byte Count */ +#define REG_SPI2_DMA 0x4002401C /* SPI2 SPI DMA Enable */ +#define REG_SPI2_FIFO_STAT 0x40024020 /* SPI2 FIFO Status */ +#define REG_SPI2_RD_CTL 0x40024024 /* SPI2 Read Control */ +#define REG_SPI2_FLOW_CTL 0x40024028 /* SPI2 Flow Control */ +#define REG_SPI2_WAIT_TMR 0x4002402C /* SPI2 Wait Timer for Flow Control */ +#define REG_SPI2_CS_CTL 0x40024030 /* SPI2 Chip Select Control for Multi-slave Connections */ +#define REG_SPI2_CS_OVERRIDE 0x40024034 /* SPI2 Chip Select Override */ + +/* ============================================================================================================================ + SPI Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_STAT_RDY 15 /* Detected an Edge on Ready Indicator for Flow Control */ +#define BITP_SPI_STAT_CSFALL 14 /* Detected a Falling Edge on CS, in Slave CON Mode */ +#define BITP_SPI_STAT_CSRISE 13 /* Detected a Rising Edge on CS, in Slave CON Mode */ +#define BITP_SPI_STAT_CSERR 12 /* Detected a CS Error Condition in Slave Mode */ +#define BITP_SPI_STAT_CS 11 /* CS Status */ +#define BITP_SPI_STAT_RXOVR 7 /* SPI Rx FIFO Overflow */ +#define BITP_SPI_STAT_RXIRQ 6 /* SPI Rx IRQ */ +#define BITP_SPI_STAT_TXIRQ 5 /* SPI Tx IRQ */ +#define BITP_SPI_STAT_TXUNDR 4 /* SPI Tx FIFO Underflow */ +#define BITP_SPI_STAT_TXDONE 3 /* SPI Tx Done in Read Command Mode */ +#define BITP_SPI_STAT_TXEMPTY 2 /* SPI Tx FIFO Empty Interrupt */ +#define BITP_SPI_STAT_XFRDONE 1 /* SPI Transfer Completion */ +#define BITP_SPI_STAT_IRQ 0 /* SPI Interrupt Status */ +#define BITM_SPI_STAT_RDY (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Detected an Edge on Ready Indicator for Flow Control */ +#define BITM_SPI_STAT_CSFALL (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Detected a Falling Edge on CS, in Slave CON Mode */ +#define BITM_SPI_STAT_CSRISE (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Detected a Rising Edge on CS, in Slave CON Mode */ +#define BITM_SPI_STAT_CSERR (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Detected a CS Error Condition in Slave Mode */ +#define BITM_SPI_STAT_CS (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* CS Status */ +#define BITM_SPI_STAT_RXOVR (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* SPI Rx FIFO Overflow */ +#define BITM_SPI_STAT_RXIRQ (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* SPI Rx IRQ */ +#define BITM_SPI_STAT_TXIRQ (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* SPI Tx IRQ */ +#define BITM_SPI_STAT_TXUNDR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* SPI Tx FIFO Underflow */ +#define BITM_SPI_STAT_TXDONE (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* SPI Tx Done in Read Command Mode */ +#define BITM_SPI_STAT_TXEMPTY (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* SPI Tx FIFO Empty Interrupt */ +#define BITM_SPI_STAT_XFRDONE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* SPI Transfer Completion */ +#define BITM_SPI_STAT_IRQ (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* SPI Interrupt Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_RX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_RX_BYTE2 8 /* 8-bit Receive Buffer, Used Only in DMA Modes */ +#define BITP_SPI_RX_BYTE1 0 /* 8-bit Receive Buffer */ +#define BITM_SPI_RX_BYTE2 (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t )) /* 8-bit Receive Buffer, Used Only in DMA Modes */ +#define BITM_SPI_RX_BYTE1 (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* 8-bit Receive Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_TX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_TX_BYTE2 8 /* 8-bit Transmit Buffer, Used Only in DMA Modes */ +#define BITP_SPI_TX_BYTE1 0 /* 8-bit Transmit Buffer */ +#define BITM_SPI_TX_BYTE2 (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t )) /* 8-bit Transmit Buffer, Used Only in DMA Modes */ +#define BITM_SPI_TX_BYTE1 (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* 8-bit Transmit Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_DIV Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_DIV_VALUE 0 /* SPI Clock Divider */ +#define BITM_SPI_DIV_VALUE (_ADI_MSK_3(0x0000003F,0x0000003FU, uint16_t )) /* SPI Clock Divider */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_CTL_CSRST 14 /* Reset Mode for CS Error Bit */ +#define BITP_SPI_CTL_TFLUSH 13 /* SPI Tx FIFO Flush Enable */ +#define BITP_SPI_CTL_RFLUSH 12 /* SPI Rx FIFO Flush Enable */ +#define BITP_SPI_CTL_CON 11 /* Continuous Transfer Enable */ +#define BITP_SPI_CTL_LOOPBACK 10 /* Loopback Enable */ +#define BITP_SPI_CTL_OEN 9 /* Slave MISO Output Enable */ +#define BITP_SPI_CTL_RXOF 8 /* Rx Overflow Overwrite Enable */ +#define BITP_SPI_CTL_ZEN 7 /* Transmit Zeros Enable */ +#define BITP_SPI_CTL_TIM 6 /* SPI Transfer and Interrupt Mode */ +#define BITP_SPI_CTL_LSB 5 /* LSB First Transfer Enable */ +#define BITP_SPI_CTL_WOM 4 /* SPI Wired-OR Mode */ +#define BITP_SPI_CTL_CPOL 3 /* Serial Clock Polarity */ +#define BITP_SPI_CTL_CPHA 2 /* Serial Clock Phase Mode */ +#define BITP_SPI_CTL_MASEN 1 /* Master Mode Enable */ +#define BITP_SPI_CTL_SPIEN 0 /* SPI Enable */ +#define BITM_SPI_CTL_CSRST (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Reset Mode for CS Error Bit */ +#define BITM_SPI_CTL_TFLUSH (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* SPI Tx FIFO Flush Enable */ +#define BITM_SPI_CTL_RFLUSH (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* SPI Rx FIFO Flush Enable */ +#define BITM_SPI_CTL_CON (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Continuous Transfer Enable */ +#define BITM_SPI_CTL_LOOPBACK (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Loopback Enable */ +#define BITM_SPI_CTL_OEN (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Slave MISO Output Enable */ +#define BITM_SPI_CTL_RXOF (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Rx Overflow Overwrite Enable */ +#define BITM_SPI_CTL_ZEN (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Transmit Zeros Enable */ +#define BITM_SPI_CTL_TIM (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* SPI Transfer and Interrupt Mode */ +#define BITM_SPI_CTL_LSB (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* LSB First Transfer Enable */ +#define BITM_SPI_CTL_WOM (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* SPI Wired-OR Mode */ +#define BITM_SPI_CTL_CPOL (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Serial Clock Polarity */ +#define BITM_SPI_CTL_CPHA (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Serial Clock Phase Mode */ +#define BITM_SPI_CTL_MASEN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Master Mode Enable */ +#define BITM_SPI_CTL_SPIEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* SPI Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_IEN_TXEMPTY 14 /* Tx FIFO Empty Interrupt Enable */ +#define BITP_SPI_IEN_XFRDONE 13 /* SPI Transfer Completion Interrupt Enable */ +#define BITP_SPI_IEN_TXDONE 12 /* SPI Transmit Done Interrupt Enable */ +#define BITP_SPI_IEN_RDY 11 /* Ready Signal Edge Interrupt Enable */ +#define BITP_SPI_IEN_RXOVR 10 /* Rx Overflow Interrupt Enable */ +#define BITP_SPI_IEN_TXUNDR 9 /* Tx Underflow Interrupt Enable */ +#define BITP_SPI_IEN_CS 8 /* Enable Interrupt on Every CS Edge in Slave CON Mode */ +#define BITP_SPI_IEN_IRQMODE 0 /* SPI IRQ Mode Bits */ +#define BITM_SPI_IEN_TXEMPTY (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Tx FIFO Empty Interrupt Enable */ +#define BITM_SPI_IEN_XFRDONE (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* SPI Transfer Completion Interrupt Enable */ +#define BITM_SPI_IEN_TXDONE (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* SPI Transmit Done Interrupt Enable */ +#define BITM_SPI_IEN_RDY (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Ready Signal Edge Interrupt Enable */ +#define BITM_SPI_IEN_RXOVR (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Rx Overflow Interrupt Enable */ +#define BITM_SPI_IEN_TXUNDR (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Tx Underflow Interrupt Enable */ +#define BITM_SPI_IEN_CS (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Enable Interrupt on Every CS Edge in Slave CON Mode */ +#define BITM_SPI_IEN_IRQMODE (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t )) /* SPI IRQ Mode Bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_CNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_CNT_FRAMECONT 15 /* Continue Frame */ +#define BITP_SPI_CNT_VALUE 0 /* Transfer Byte Count */ +#define BITM_SPI_CNT_FRAMECONT (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Continue Frame */ +#define BITM_SPI_CNT_VALUE (_ADI_MSK_3(0x00003FFF,0x00003FFFU, uint16_t )) /* Transfer Byte Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_DMA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_DMA_RXEN 2 /* Enable Receive DMA Request */ +#define BITP_SPI_DMA_TXEN 1 /* Enable Transmit DMA Request */ +#define BITP_SPI_DMA_EN 0 /* Enable DMA for Data Transfer */ +#define BITM_SPI_DMA_RXEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable Receive DMA Request */ +#define BITM_SPI_DMA_TXEN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enable Transmit DMA Request */ +#define BITM_SPI_DMA_EN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Enable DMA for Data Transfer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_FIFO_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_FIFO_STAT_RX 8 /* SPI Rx FIFO Dtatus */ +#define BITP_SPI_FIFO_STAT_TX 0 /* SPI Tx FIFO Status */ +#define BITM_SPI_FIFO_STAT_RX (_ADI_MSK_3(0x00000F00,0x00000F00U, uint16_t )) /* SPI Rx FIFO Dtatus */ +#define BITM_SPI_FIFO_STAT_TX (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t )) /* SPI Tx FIFO Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_RD_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_RD_CTL_THREEPIN 8 /* Three Pin SPI Mode */ +#define BITP_SPI_RD_CTL_TXBYTES 2 /* Transmit Byte Count - 1 (Read Command) */ +#define BITP_SPI_RD_CTL_OVERLAP 1 /* Tx/Rx Overlap Mode */ +#define BITP_SPI_RD_CTL_CMDEN 0 /* Read Command Enable */ +#define BITM_SPI_RD_CTL_THREEPIN (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Three Pin SPI Mode */ +#define BITM_SPI_RD_CTL_TXBYTES (_ADI_MSK_3(0x0000003C,0x0000003CU, uint16_t )) /* Transmit Byte Count - 1 (Read Command) */ +#define BITM_SPI_RD_CTL_OVERLAP (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Tx/Rx Overlap Mode */ +#define BITM_SPI_RD_CTL_CMDEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Read Command Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_FLOW_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_FLOW_CTL_RDBURSTSZ 6 /* Read Data Burst Size - 1 */ +#define BITP_SPI_FLOW_CTL_RDYPOL 4 /* Polarity of RDY/MISO Line */ +#define BITP_SPI_FLOW_CTL_MODE 0 /* Flow Control Mode */ +#define BITM_SPI_FLOW_CTL_RDBURSTSZ (_ADI_MSK_3(0x0000FFC0,0x0000FFC0U, uint16_t )) /* Read Data Burst Size - 1 */ +#define BITM_SPI_FLOW_CTL_RDYPOL (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Polarity of RDY/MISO Line */ +#define BITM_SPI_FLOW_CTL_MODE (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Flow Control Mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_WAIT_TMR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_WAIT_TMR_VALUE 0 /* Wait Timer */ +#define BITM_SPI_WAIT_TMR_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Wait Timer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_CS_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_CS_CTL_SEL 0 /* Chip Select Control */ +#define BITM_SPI_CS_CTL_SEL (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t )) /* Chip Select Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_CS_OVERRIDE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_CS_OVERRIDE_CTL 0 /* CS Override Control */ +#define BITM_SPI_CS_OVERRIDE_CTL (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* CS Override Control */ + + +/* ============================================================================================================================ + + ============================================================================================================================ */ + +/* ============================================================================================================================ + UART0 + ============================================================================================================================ */ +#define REG_UART0_RX 0x40005000 /* UART0 Receive Buffer Register */ +#define REG_UART0_TX 0x40005000 /* UART0 Transmit Holding Register */ +#define REG_UART0_IEN 0x40005004 /* UART0 Interrupt Enable */ +#define REG_UART0_IIR 0x40005008 /* UART0 Interrupt ID */ +#define REG_UART0_LCR 0x4000500C /* UART0 Line Control */ +#define REG_UART0_MCR 0x40005010 /* UART0 Modem Control */ +#define REG_UART0_LSR 0x40005014 /* UART0 Line Status */ +#define REG_UART0_MSR 0x40005018 /* UART0 Modem Status */ +#define REG_UART0_SCR 0x4000501C /* UART0 Scratch Buffer */ +#define REG_UART0_FCR 0x40005020 /* UART0 FIFO Control */ +#define REG_UART0_FBR 0x40005024 /* UART0 Fractional Baud Rate */ +#define REG_UART0_DIV 0x40005028 /* UART0 Baud Rate Divider */ +#define REG_UART0_LCR2 0x4000502C /* UART0 Second Line Control */ +#define REG_UART0_CTL 0x40005030 /* UART0 UART Control Register */ +#define REG_UART0_RFC 0x40005034 /* UART0 RX FIFO Byte Count */ +#define REG_UART0_TFC 0x40005038 /* UART0 TX FIFO Byte Count */ +#define REG_UART0_RSC 0x4000503C /* UART0 RS485 Half-duplex Control */ +#define REG_UART0_ACR 0x40005040 /* UART0 Auto Baud Control */ +#define REG_UART0_ASRL 0x40005044 /* UART0 Auto Baud Status (Low) */ +#define REG_UART0_ASRH 0x40005048 /* UART0 Auto Baud Status (High) */ + +/* ============================================================================================================================ + UART1 + ============================================================================================================================ */ +#define REG_UART1_RX 0x40005400 /* UART1 Receive Buffer Register */ +#define REG_UART1_TX 0x40005400 /* UART1 Transmit Holding Register */ +#define REG_UART1_IEN 0x40005404 /* UART1 Interrupt Enable */ +#define REG_UART1_IIR 0x40005408 /* UART1 Interrupt ID */ +#define REG_UART1_LCR 0x4000540C /* UART1 Line Control */ +#define REG_UART1_MCR 0x40005410 /* UART1 Modem Control */ +#define REG_UART1_LSR 0x40005414 /* UART1 Line Status */ +#define REG_UART1_MSR 0x40005418 /* UART1 Modem Status */ +#define REG_UART1_SCR 0x4000541C /* UART1 Scratch Buffer */ +#define REG_UART1_FCR 0x40005420 /* UART1 FIFO Control */ +#define REG_UART1_FBR 0x40005424 /* UART1 Fractional Baud Rate */ +#define REG_UART1_DIV 0x40005428 /* UART1 Baud Rate Divider */ +#define REG_UART1_LCR2 0x4000542C /* UART1 Second Line Control */ +#define REG_UART1_CTL 0x40005430 /* UART1 UART Control Register */ +#define REG_UART1_RFC 0x40005434 /* UART1 RX FIFO Byte Count */ +#define REG_UART1_TFC 0x40005438 /* UART1 TX FIFO Byte Count */ +#define REG_UART1_RSC 0x4000543C /* UART1 RS485 Half-duplex Control */ +#define REG_UART1_ACR 0x40005440 /* UART1 Auto Baud Control */ +#define REG_UART1_ASRL 0x40005444 /* UART1 Auto Baud Status (Low) */ +#define REG_UART1_ASRH 0x40005448 /* UART1 Auto Baud Status (High) */ + +/* ============================================================================================================================ + UART Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + UART_RX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_RX_RBR 0 /* Receive Buffer Register */ +#define BITM_UART_RX_RBR (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Receive Buffer Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_TX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_TX_THR 0 /* Transmit Holding Register */ +#define BITM_UART_TX_THR (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Transmit Holding Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_IEN_EDMAR 5 /* DMA Requests in Receive Mode */ +#define BITP_UART_IEN_EDMAT 4 /* DMA Requests in Transmit Mode */ +#define BITP_UART_IEN_EDSSI 3 /* Modem Status Interrupt */ +#define BITP_UART_IEN_ELSI 2 /* Rx Status Interrupt */ +#define BITP_UART_IEN_ETBEI 1 /* Transmit Buffer Empty Interrupt */ +#define BITP_UART_IEN_ERBFI 0 /* Receive Buffer Full Interrupt */ +#define BITM_UART_IEN_EDMAR (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* DMA Requests in Receive Mode */ +#define BITM_UART_IEN_EDMAT (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* DMA Requests in Transmit Mode */ +#define BITM_UART_IEN_EDSSI (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Modem Status Interrupt */ +#define BITM_UART_IEN_ELSI (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Rx Status Interrupt */ +#define BITM_UART_IEN_ETBEI (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Transmit Buffer Empty Interrupt */ +#define BITM_UART_IEN_ERBFI (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Receive Buffer Full Interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_IIR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_IIR_FEND 6 /* FIFO Enabled */ +#define BITP_UART_IIR_STAT 1 /* Interrupt Status */ +#define BITP_UART_IIR_NIRQ 0 /* Interrupt Flag */ +#define BITM_UART_IIR_FEND (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t )) /* FIFO Enabled */ +#define BITM_UART_IIR_STAT (_ADI_MSK_3(0x0000000E,0x0000000EU, uint16_t )) /* Interrupt Status */ +#define BITM_UART_IIR_NIRQ (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Interrupt Flag */ +#define ENUM_UART_IIR_STAT_EDSSI (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* STAT: Modem status interrupt (Read MSR register to clear) */ +#define ENUM_UART_IIR_STAT_ETBEI (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* STAT: Transmit buffer empty interrupt (Write to Tx register or read IIR register to clear) */ +#define ENUM_UART_IIR_STAT_ERBFI (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* STAT: Receive buffer full interrupt (Read Rx register to clear) */ +#define ENUM_UART_IIR_STAT_RLSI (_ADI_MSK_3(0x00000006,0x00000006U, uint16_t )) /* STAT: Receive line status interrupt (Read LSR register to clear) */ +#define ENUM_UART_IIR_STAT_RFTOI (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t )) /* STAT: Receive FIFO time-out interrupt (Read Rx register to clear) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_LCR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_LCR_BRK 6 /* Set Break */ +#define BITP_UART_LCR_SP 5 /* Stick Parity */ +#define BITP_UART_LCR_EPS 4 /* Parity Select */ +#define BITP_UART_LCR_PEN 3 /* Parity Enable */ +#define BITP_UART_LCR_STOP 2 /* Stop Bit */ +#define BITP_UART_LCR_WLS 0 /* Word Length Select */ +#define BITM_UART_LCR_BRK (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Set Break */ +#define BITM_UART_LCR_SP (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Stick Parity */ +#define BITM_UART_LCR_EPS (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Parity Select */ +#define BITM_UART_LCR_PEN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Parity Enable */ +#define BITM_UART_LCR_STOP (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Stop Bit */ +#define BITM_UART_LCR_WLS (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Word Length Select */ +#define ENUM_UART_LCR_PAR_NOTFORCED (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SP: Parity will not be forced based on Parity Select and Parity Enable bits. */ +#define ENUM_UART_LCR_PAR_FORCED (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* SP: Parity forced based on Parity Select and Parity Enable bits. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_MCR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_MCR_LOOPBACK 4 /* Loopback Mode */ +#define BITP_UART_MCR_OUT2 3 /* Output 2 */ +#define BITP_UART_MCR_OUT1 2 /* Output 1 */ +#define BITP_UART_MCR_RTS 1 /* Request to Send */ +#define BITP_UART_MCR_DTR 0 /* Data Terminal Ready */ +#define BITM_UART_MCR_LOOPBACK (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Loopback Mode */ +#define BITM_UART_MCR_OUT2 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Output 2 */ +#define BITM_UART_MCR_OUT1 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Output 1 */ +#define BITM_UART_MCR_RTS (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Request to Send */ +#define BITM_UART_MCR_DTR (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Data Terminal Ready */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_LSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_LSR_FIFOERR 7 /* Rx FIFO Parity Error/Frame Error/Break Indication */ +#define BITP_UART_LSR_TEMT 6 /* Transmit and Shift Register Empty Status */ +#define BITP_UART_LSR_THRE 5 /* Transmit Register Empty */ +#define BITP_UART_LSR_BI 4 /* Break Indicator */ +#define BITP_UART_LSR_FE 3 /* Framing Error */ +#define BITP_UART_LSR_PE 2 /* Parity Error */ +#define BITP_UART_LSR_OE 1 /* Overrun Error */ +#define BITP_UART_LSR_DR 0 /* Data Ready */ +#define BITM_UART_LSR_FIFOERR (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Rx FIFO Parity Error/Frame Error/Break Indication */ +#define BITM_UART_LSR_TEMT (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Transmit and Shift Register Empty Status */ +#define BITM_UART_LSR_THRE (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Transmit Register Empty */ +#define BITM_UART_LSR_BI (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Break Indicator */ +#define BITM_UART_LSR_FE (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Framing Error */ +#define BITM_UART_LSR_PE (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Parity Error */ +#define BITM_UART_LSR_OE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Overrun Error */ +#define BITM_UART_LSR_DR (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Data Ready */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_MSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_MSR_DCD 7 /* Data Carrier Detect */ +#define BITP_UART_MSR_RI 6 /* Ring Indicator */ +#define BITP_UART_MSR_DSR 5 /* Data Set Ready */ +#define BITP_UART_MSR_CTS 4 /* Clear to Send */ +#define BITP_UART_MSR_DDCD 3 /* Delta DCD */ +#define BITP_UART_MSR_TERI 2 /* Trailing Edge RI */ +#define BITP_UART_MSR_DDSR 1 /* Delta DSR */ +#define BITP_UART_MSR_DCTS 0 /* Delta CTS */ +#define BITM_UART_MSR_DCD (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Data Carrier Detect */ +#define BITM_UART_MSR_RI (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Ring Indicator */ +#define BITM_UART_MSR_DSR (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Data Set Ready */ +#define BITM_UART_MSR_CTS (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Clear to Send */ +#define BITM_UART_MSR_DDCD (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Delta DCD */ +#define BITM_UART_MSR_TERI (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Trailing Edge RI */ +#define BITM_UART_MSR_DDSR (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Delta DSR */ +#define BITM_UART_MSR_DCTS (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Delta CTS */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_SCR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_SCR_SCR 0 /* Scratch */ +#define BITM_UART_SCR_SCR (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Scratch */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_FCR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_FCR_RFTRIG 6 /* Rx FIFO Trigger Level */ +#define BITP_UART_FCR_FDMAMD 3 /* FIFO DMA Mode */ +#define BITP_UART_FCR_TFCLR 2 /* Clear Tx FIFO */ +#define BITP_UART_FCR_RFCLR 1 /* Clear Rx FIFO */ +#define BITP_UART_FCR_FIFOEN 0 /* FIFO Enable as to Work in 16550 Mode */ +#define BITM_UART_FCR_RFTRIG (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t )) /* Rx FIFO Trigger Level */ +#define BITM_UART_FCR_FDMAMD (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* FIFO DMA Mode */ +#define BITM_UART_FCR_TFCLR (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Clear Tx FIFO */ +#define BITM_UART_FCR_RFCLR (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Clear Rx FIFO */ +#define BITM_UART_FCR_FIFOEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* FIFO Enable as to Work in 16550 Mode */ +#define ENUM_UART_FCR_MODE0 (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* FDMAMD: In DMA mode 0, RX DMA request will be asserted whenever there's data in RBR or RX FIFO and de-assert whenever RBR or RX FIFO is empty; TX DMA request will be asserted whenever THR or TX FIFO is empty and de-assert whenever data written to. */ +#define ENUM_UART_FCR_MODE1 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* FDMAMD: in DMA mode 1, RX DMA request will be asserted whenever RX FIFO trig level or time out reached and de-assert thereafter when RX FIFO is empty; TX DMA request will be asserted whenever TX FIFO is empty and de-assert thereafter when TX FIFO is completely filled up full. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_FBR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_FBR_FBEN 15 /* Fractional Baud Rate Generator Enable */ +#define BITP_UART_FBR_DIVM 11 /* Fractional Baud Rate M Divide Bits 1 to 3 */ +#define BITP_UART_FBR_DIVN 0 /* Fractional Baud Rate N Divide Bits 0 to 2047 */ +#define BITM_UART_FBR_FBEN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Fractional Baud Rate Generator Enable */ +#define BITM_UART_FBR_DIVM (_ADI_MSK_3(0x00001800,0x00001800U, uint16_t )) /* Fractional Baud Rate M Divide Bits 1 to 3 */ +#define BITM_UART_FBR_DIVN (_ADI_MSK_3(0x000007FF,0x000007FFU, uint16_t )) /* Fractional Baud Rate N Divide Bits 0 to 2047 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_DIV Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_DIV_DIV 0 /* Baud Rate Divider */ +#define BITM_UART_DIV_DIV (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Baud Rate Divider */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_LCR2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_LCR2_OSR 0 /* Over Sample Rate */ +#define BITM_UART_LCR2_OSR (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Over Sample Rate */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_CTL_REV 8 /* UART Revision ID */ +#define BITP_UART_CTL_RXINV 4 /* Invert Receiver Line */ +#define BITP_UART_CTL_FORCECLK 1 /* Force UCLK on */ +#define BITM_UART_CTL_REV (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t )) /* UART Revision ID */ +#define BITM_UART_CTL_RXINV (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Invert Receiver Line */ +#define BITM_UART_CTL_FORCECLK (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Force UCLK on */ +#define ENUM_UART_CTL_NOTINV_RX (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* RXINV: Don't invert receiver line (idling high). */ +#define ENUM_UART_CTL_INV_RX (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* RXINV: Invert receiver line (idling low). */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_RFC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_RFC_RFC 0 /* Current Rx FIFO Data Bytes */ +#define BITM_UART_RFC_RFC (_ADI_MSK_3(0x0000001F,0x0000001FU, uint16_t )) /* Current Rx FIFO Data Bytes */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_TFC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_TFC_TFC 0 /* Current Tx FIFO Data Bytes */ +#define BITM_UART_TFC_TFC (_ADI_MSK_3(0x0000001F,0x0000001FU, uint16_t )) /* Current Tx FIFO Data Bytes */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_RSC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_RSC_DISTX 3 /* Hold off Tx When Receiving */ +#define BITP_UART_RSC_DISRX 2 /* Disable Rx When Transmitting */ +#define BITP_UART_RSC_OENSP 1 /* SOUT_EN De-assert Before Full Stop Bit(s) */ +#define BITP_UART_RSC_OENP 0 /* SOUT_EN Polarity */ +#define BITM_UART_RSC_DISTX (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Hold off Tx When Receiving */ +#define BITM_UART_RSC_DISRX (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Disable Rx When Transmitting */ +#define BITM_UART_RSC_OENSP (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* SOUT_EN De-assert Before Full Stop Bit(s) */ +#define BITM_UART_RSC_OENP (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* SOUT_EN Polarity */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_ACR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_ACR_EEC 8 /* Ending Edge Count */ +#define BITP_UART_ACR_SEC 4 /* Starting Edge Count */ +#define BITP_UART_ACR_TOIEN 2 /* Enable Time-out Interrupt */ +#define BITP_UART_ACR_DNIEN 1 /* Enable Done Interrupt */ +#define BITP_UART_ACR_ABE 0 /* Auto Baud Enable */ +#define BITM_UART_ACR_EEC (_ADI_MSK_3(0x00000F00,0x00000F00U, uint16_t )) /* Ending Edge Count */ +#define BITM_UART_ACR_SEC (_ADI_MSK_3(0x00000070,0x00000070U, uint16_t )) /* Starting Edge Count */ +#define BITM_UART_ACR_TOIEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable Time-out Interrupt */ +#define BITM_UART_ACR_DNIEN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enable Done Interrupt */ +#define BITM_UART_ACR_ABE (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Auto Baud Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_ASRL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_ASRL_CNT 4 /* Auto Baud Counter Value */ +#define BITP_UART_ASRL_NEETO 3 /* Timed Out Due to No Valid Ending Edge Found */ +#define BITP_UART_ASRL_NSETO 2 /* Timed Out Due to No Valid Start Edge Found */ +#define BITP_UART_ASRL_BRKTO 1 /* Timed Out Due to Long Time Break Condition */ +#define BITP_UART_ASRL_DONE 0 /* Auto Baud Done Successfully */ +#define BITM_UART_ASRL_CNT (_ADI_MSK_3(0x0000FFF0,0x0000FFF0U, uint16_t )) /* Auto Baud Counter Value */ +#define BITM_UART_ASRL_NEETO (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Timed Out Due to No Valid Ending Edge Found */ +#define BITM_UART_ASRL_NSETO (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Timed Out Due to No Valid Start Edge Found */ +#define BITM_UART_ASRL_BRKTO (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Timed Out Due to Long Time Break Condition */ +#define BITM_UART_ASRL_DONE (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Auto Baud Done Successfully */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_ASRH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_ASRH_CNT 0 /* Auto Baud Counter Value */ +#define BITM_UART_ASRH_CNT (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Auto Baud Counter Value */ + + +/* ============================================================================================================================ + Beeper Driver + ============================================================================================================================ */ + +/* ============================================================================================================================ + BEEP0 + ============================================================================================================================ */ +#define REG_BEEP0_CFG 0x40005C00 /* BEEP0 Beeper Configuration */ +#define REG_BEEP0_STAT 0x40005C04 /* BEEP0 Beeper Status */ +#define REG_BEEP0_TONEA 0x40005C08 /* BEEP0 Tone A Data */ +#define REG_BEEP0_TONEB 0x40005C0C /* BEEP0 Tone B Data */ + +/* ============================================================================================================================ + BEEP Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + BEEP_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BEEP_CFG_SEQATENDIRQ 15 /* Sequence End IRQ */ +#define BITP_BEEP_CFG_SEQNEARENDIRQ 14 /* Sequence 1 Cycle from End IRQ */ +#define BITP_BEEP_CFG_BENDIRQ 13 /* Tone B End IRQ */ +#define BITP_BEEP_CFG_BSTARTIRQ 12 /* Tone B Start IRQ */ +#define BITP_BEEP_CFG_AENDIRQ 11 /* Tone A End IRQ */ +#define BITP_BEEP_CFG_ASTARTIRQ 10 /* Tone A Start IRQ */ +#define BITP_BEEP_CFG_EN 8 /* Beeper Enable */ +#define BITP_BEEP_CFG_SEQREPEAT 0 /* Beeper Sequence Repeat Value */ +#define BITM_BEEP_CFG_SEQATENDIRQ (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Sequence End IRQ */ +#define BITM_BEEP_CFG_SEQNEARENDIRQ (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Sequence 1 Cycle from End IRQ */ +#define BITM_BEEP_CFG_BENDIRQ (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Tone B End IRQ */ +#define BITM_BEEP_CFG_BSTARTIRQ (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Tone B Start IRQ */ +#define BITM_BEEP_CFG_AENDIRQ (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Tone A End IRQ */ +#define BITM_BEEP_CFG_ASTARTIRQ (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Tone A Start IRQ */ +#define BITM_BEEP_CFG_EN (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Beeper Enable */ +#define BITM_BEEP_CFG_SEQREPEAT (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Beeper Sequence Repeat Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BEEP_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BEEP_STAT_SEQENDED 15 /* Sequencer Has Ended */ +#define BITP_BEEP_STAT_SEQNEAREND 14 /* Sequencer Last Tone-pair Has Started */ +#define BITP_BEEP_STAT_BENDED 13 /* Tone B Has Ended */ +#define BITP_BEEP_STAT_BSTARTED 12 /* Tone B Has Started */ +#define BITP_BEEP_STAT_AENDED 11 /* Tone A Has Ended */ +#define BITP_BEEP_STAT_ASTARTED 10 /* Tone A Has Started */ +#define BITP_BEEP_STAT_BUSY 8 /* Beeper is Busy */ +#define BITP_BEEP_STAT_SEQREMAIN 0 /* Remaining Tone-pair Iterations to Play in Sequence Mode */ +#define BITM_BEEP_STAT_SEQENDED (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Sequencer Has Ended */ +#define BITM_BEEP_STAT_SEQNEAREND (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Sequencer Last Tone-pair Has Started */ +#define BITM_BEEP_STAT_BENDED (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Tone B Has Ended */ +#define BITM_BEEP_STAT_BSTARTED (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Tone B Has Started */ +#define BITM_BEEP_STAT_AENDED (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Tone A Has Ended */ +#define BITM_BEEP_STAT_ASTARTED (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Tone A Has Started */ +#define BITM_BEEP_STAT_BUSY (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Beeper is Busy */ +#define BITM_BEEP_STAT_SEQREMAIN (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Remaining Tone-pair Iterations to Play in Sequence Mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BEEP_TONEA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BEEP_TONEA_DIS 15 /* Output Disable */ +#define BITP_BEEP_TONEA_FREQ 8 /* Tone Frequency */ +#define BITP_BEEP_TONEA_DUR 0 /* Tone Duration */ +#define BITM_BEEP_TONEA_DIS (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Output Disable */ +#define BITM_BEEP_TONEA_FREQ (_ADI_MSK_3(0x00007F00,0x00007F00U, uint16_t )) /* Tone Frequency */ +#define BITM_BEEP_TONEA_DUR (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Tone Duration */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BEEP_TONEB Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BEEP_TONEB_DIS 15 /* Output Disable */ +#define BITP_BEEP_TONEB_FREQ 8 /* Tone Frequency */ +#define BITP_BEEP_TONEB_DUR 0 /* Tone Duration */ +#define BITM_BEEP_TONEB_DIS (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Output Disable */ +#define BITM_BEEP_TONEB_FREQ (_ADI_MSK_3(0x00007F00,0x00007F00U, uint16_t )) /* Tone Frequency */ +#define BITM_BEEP_TONEB_DUR (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Tone Duration */ + + +/* ============================================================================================================================ + + ============================================================================================================================ */ + +/* ============================================================================================================================ + ADC0 + ============================================================================================================================ */ +#define REG_ADC0_CFG 0x40007000 /* ADC0 ADC Configuration */ +#define REG_ADC0_PWRUP 0x40007004 /* ADC0 ADC Power-up Time */ +#define REG_ADC0_CAL_WORD 0x40007008 /* ADC0 Calibration Word */ +#define REG_ADC0_CNV_CFG 0x4000700C /* ADC0 ADC Conversion Configuration */ +#define REG_ADC0_CNV_TIME 0x40007010 /* ADC0 ADC Conversion Time */ +#define REG_ADC0_AVG_CFG 0x40007014 /* ADC0 Averaging Configuration */ +#define REG_ADC0_IRQ_EN 0x40007020 /* ADC0 Interrupt Enable */ +#define REG_ADC0_STAT 0x40007024 /* ADC0 ADC Status */ +#define REG_ADC0_OVF 0x40007028 /* ADC0 Overflow of Output Registers */ +#define REG_ADC0_ALERT 0x4000702C /* ADC0 Alert Indication */ +#define REG_ADC0_CH0_OUT 0x40007030 /* ADC0 Conversion Result Channel 0 */ +#define REG_ADC0_CH1_OUT 0x40007034 /* ADC0 Conversion Result Channel 1 */ +#define REG_ADC0_CH2_OUT 0x40007038 /* ADC0 Conversion Result Channel 2 */ +#define REG_ADC0_CH3_OUT 0x4000703C /* ADC0 Conversion Result Channel 3 */ +#define REG_ADC0_CH4_OUT 0x40007040 /* ADC0 Conversion Result Channel 4 */ +#define REG_ADC0_CH5_OUT 0x40007044 /* ADC0 Conversion Result Channel 5 */ +#define REG_ADC0_CH6_OUT 0x40007048 /* ADC0 Conversion Result Channel 6 */ +#define REG_ADC0_CH7_OUT 0x4000704C /* ADC0 Conversion Result Channel 7 */ +#define REG_ADC0_BAT_OUT 0x40007050 /* ADC0 Battery Monitoring Result */ +#define REG_ADC0_TMP_OUT 0x40007054 /* ADC0 Temperature Result */ +#define REG_ADC0_TMP2_OUT 0x40007058 /* ADC0 Temperature Result 2 */ +#define REG_ADC0_DMA_OUT 0x4000705C /* ADC0 DMA Output Register */ +#define REG_ADC0_LIM0_LO 0x40007060 /* ADC0 Channel 0 Low Limit */ +#define REG_ADC0_LIM0_HI 0x40007064 /* ADC0 Channel 0 High Limit */ +#define REG_ADC0_HYS0 0x40007068 /* ADC0 Channel 0 Hysteresis */ +#define REG_ADC0_LIM1_LO 0x40007070 /* ADC0 Channel 1 Low Limit */ +#define REG_ADC0_LIM1_HI 0x40007074 /* ADC0 Channel 1 High Limit */ +#define REG_ADC0_HYS1 0x40007078 /* ADC0 Channel 1 Hysteresis */ +#define REG_ADC0_LIM2_LO 0x40007080 /* ADC0 Channel 2 Low Limit */ +#define REG_ADC0_LIM2_HI 0x40007084 /* ADC0 Channel 2 High Limit */ +#define REG_ADC0_HYS2 0x40007088 /* ADC0 Channel 2 Hysteresis */ +#define REG_ADC0_LIM3_LO 0x40007090 /* ADC0 Channel 3 Low Limit */ +#define REG_ADC0_LIM3_HI 0x40007094 /* ADC0 Channel 3 High Limit */ +#define REG_ADC0_HYS3 0x40007098 /* ADC0 Channel 3 Hysteresis */ +#define REG_ADC0_CFG1 0x400070C0 /* ADC0 Reference Buffer Low Power Mode */ + +/* ============================================================================================================================ + ADC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CFG_VREFVBAT_DEL 10 /* Set to 1 after minimum delay of 700 us from VREFBAT field being set to 1 */ +#define BITP_ADC_CFG_FAST_DISCH 9 /* For fast switchover of Vref from 2.5 V to 1.25 V */ +#define BITP_ADC_CFG_TMPEN 8 /* To power up temperature sensor */ +#define BITP_ADC_CFG_SINKEN 7 /* To enable additional 50 uA sink current capability @1.25 V, 100 uA current capability @2.5 V */ +#define BITP_ADC_CFG_RST 6 /* Resets internal buffers and registers when high */ +#define BITP_ADC_CFG_STARTCAL 5 /* To start a new offset calibration cycle */ +#define BITP_ADC_CFG_EN 4 /* To enable ADC subsystem */ +#define BITP_ADC_CFG_VREFVBAT 3 /* VRef VBAT */ +#define BITP_ADC_CFG_REFBUFEN 2 /* To enable internal reference buffer */ +#define BITP_ADC_CFG_VREFSEL 1 /* To select Vref as 1.25 V or 2.5 V */ +#define BITP_ADC_CFG_PWRUP 0 /* Powering up ADC */ +#define BITM_ADC_CFG_VREFVBAT_DEL (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Set to 1 after minimum delay of 700 us from VREFBAT field being set to 1 */ +#define BITM_ADC_CFG_FAST_DISCH (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* For fast switchover of Vref from 2.5 V to 1.25 V */ +#define BITM_ADC_CFG_TMPEN (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* To power up temperature sensor */ +#define BITM_ADC_CFG_SINKEN (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* To enable additional 50 uA sink current capability @1.25 V, 100 uA current capability @2.5 V */ +#define BITM_ADC_CFG_RST (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Resets internal buffers and registers when high */ +#define BITM_ADC_CFG_STARTCAL (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* To start a new offset calibration cycle */ +#define BITM_ADC_CFG_EN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* To enable ADC subsystem */ +#define BITM_ADC_CFG_VREFVBAT (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* VRef VBAT */ +#define BITM_ADC_CFG_REFBUFEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* To enable internal reference buffer */ +#define BITM_ADC_CFG_VREFSEL (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* To select Vref as 1.25 V or 2.5 V */ +#define BITM_ADC_CFG_PWRUP (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Powering up ADC */ +#define ENUM_ADC_CFG_EXT_REF (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* REFBUFEN: External reference is used */ +#define ENUM_ADC_CFG_BUF_REF (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* REFBUFEN: Reference buffer is enabled */ +#define ENUM_ADC_CFG_V_2P5 (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* VREFSEL: Vref = 2.5 V */ +#define ENUM_ADC_CFG_V_1P25 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* VREFSEL: Vref = 1.25 V */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_PWRUP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_PWRUP_WAIT 0 /* Program this count to generate 20us wait time with respect to the PCLK frequency */ +#define BITM_ADC_PWRUP_WAIT (_ADI_MSK_3(0x000007FF,0x000007FFU, uint16_t )) /* Program this count to generate 20us wait time with respect to the PCLK frequency */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CAL_WORD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CAL_WORD_VALUE 0 /* Offset calibration word */ +#define BITM_ADC_CAL_WORD_VALUE (_ADI_MSK_3(0x0000007F,0x0000007FU, uint16_t )) /* Offset calibration word */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CNV_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CNV_CFG_MULTI 15 /* Set to start multiple conversions */ +#define BITP_ADC_CNV_CFG_SINGLE 14 /* Set to start single conversion */ +#define BITP_ADC_CNV_CFG_DMAEN 13 /* To enable DMA channel */ +#define BITP_ADC_CNV_CFG_AUTOMODE 12 /* To enable auto mode */ +#define BITP_ADC_CNV_CFG_TMP2 10 /* To select temperature measurement 2 */ +#define BITP_ADC_CNV_CFG_TMP 9 /* To select temperature measurement 1 */ +#define BITP_ADC_CNV_CFG_BAT 8 /* To enable battery monitoring */ +#define BITP_ADC_CNV_CFG_SEL 0 /* To select channel(s) to convert */ +#define BITM_ADC_CNV_CFG_MULTI (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Set to start multiple conversions */ +#define BITM_ADC_CNV_CFG_SINGLE (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Set to start single conversion */ +#define BITM_ADC_CNV_CFG_DMAEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* To enable DMA channel */ +#define BITM_ADC_CNV_CFG_AUTOMODE (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* To enable auto mode */ +#define BITM_ADC_CNV_CFG_TMP2 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* To select temperature measurement 2 */ +#define BITM_ADC_CNV_CFG_TMP (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* To select temperature measurement 1 */ +#define BITM_ADC_CNV_CFG_BAT (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* To enable battery monitoring */ +#define BITM_ADC_CNV_CFG_SEL (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* To select channel(s) to convert */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CNV_TIME Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CNV_TIME_DLY 8 /* Delay between two consecutive conversions in terms of number of ACLK cycles */ +#define BITP_ADC_CNV_TIME_SAMPTIME 0 /* Number of clock cycles (ACLK) required for sampling */ +#define BITM_ADC_CNV_TIME_DLY (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t )) /* Delay between two consecutive conversions in terms of number of ACLK cycles */ +#define BITM_ADC_CNV_TIME_SAMPTIME (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Number of clock cycles (ACLK) required for sampling */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_AVG_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_AVG_CFG_EN 15 /* To enable averaging on Channels enabled in enable register */ +#define BITP_ADC_AVG_CFG_OS 14 /* Enable oversampling */ +#define BITP_ADC_AVG_CFG_FACTOR 0 /* Program averaging factor for averaging enabled channels (1-256) */ +#define BITM_ADC_AVG_CFG_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable averaging on Channels enabled in enable register */ +#define BITM_ADC_AVG_CFG_OS (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Enable oversampling */ +#define BITM_ADC_AVG_CFG_FACTOR (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Program averaging factor for averaging enabled channels (1-256) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_IRQ_EN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_IRQ_EN_RDY 13 /* Set to enable interrupt when ADC is ready to convert */ +#define BITP_ADC_IRQ_EN_ALERT 12 /* Set to enable interrupt on crossing lower or higher limit */ +#define BITP_ADC_IRQ_EN_OVF 11 /* Set to enable interrupt in case of overflow */ +#define BITP_ADC_IRQ_EN_CALDONE 10 /* Set it to enable interrupt for calibration done */ +#define BITP_ADC_IRQ_EN_CNVDONE 0 /* Set it to enable interrupt after conversion is done */ +#define BITM_ADC_IRQ_EN_RDY (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Set to enable interrupt when ADC is ready to convert */ +#define BITM_ADC_IRQ_EN_ALERT (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Set to enable interrupt on crossing lower or higher limit */ +#define BITM_ADC_IRQ_EN_OVF (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Set to enable interrupt in case of overflow */ +#define BITM_ADC_IRQ_EN_CALDONE (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Set it to enable interrupt for calibration done */ +#define BITM_ADC_IRQ_EN_CNVDONE (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Set it to enable interrupt after conversion is done */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_STAT_RDY 15 /* Indicates ADC is ready to start converting, when using external reference buffer */ +#define BITP_ADC_STAT_CALDONE 14 /* Indicates calibration is done */ +#define BITP_ADC_STAT_TMP2DONE 10 /* Indicates conversion is done for temperature sensing 2 */ +#define BITP_ADC_STAT_TMPDONE 9 /* Indicates conversion is done for temperature sensing */ +#define BITP_ADC_STAT_BATDONE 8 /* Indicates conversion done for battery monitoring */ +#define BITP_ADC_STAT_DONE7 7 /* Indicates conversion done on Channel 7 */ +#define BITP_ADC_STAT_DONE6 6 /* Indicates conversion done on Channel 6 */ +#define BITP_ADC_STAT_DONE5 5 /* Indicates conversion done on Channel 5 */ +#define BITP_ADC_STAT_DONE4 4 /* Indicates conversion done on Channel 4 */ +#define BITP_ADC_STAT_DONE3 3 /* Indicates conversion done on Channel 3 */ +#define BITP_ADC_STAT_DONE2 2 /* Indicates conversion done on Channel 2 */ +#define BITP_ADC_STAT_DONE1 1 /* Indicates conversion done on Channel 1 */ +#define BITP_ADC_STAT_DONE0 0 /* Indicates conversion done on Channel 0 */ +#define BITM_ADC_STAT_RDY (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Indicates ADC is ready to start converting, when using external reference buffer */ +#define BITM_ADC_STAT_CALDONE (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Indicates calibration is done */ +#define BITM_ADC_STAT_TMP2DONE (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Indicates conversion is done for temperature sensing 2 */ +#define BITM_ADC_STAT_TMPDONE (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Indicates conversion is done for temperature sensing */ +#define BITM_ADC_STAT_BATDONE (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Indicates conversion done for battery monitoring */ +#define BITM_ADC_STAT_DONE7 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Indicates conversion done on Channel 7 */ +#define BITM_ADC_STAT_DONE6 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Indicates conversion done on Channel 6 */ +#define BITM_ADC_STAT_DONE5 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Indicates conversion done on Channel 5 */ +#define BITM_ADC_STAT_DONE4 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Indicates conversion done on Channel 4 */ +#define BITM_ADC_STAT_DONE3 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Indicates conversion done on Channel 3 */ +#define BITM_ADC_STAT_DONE2 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Indicates conversion done on Channel 2 */ +#define BITM_ADC_STAT_DONE1 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Indicates conversion done on Channel 1 */ +#define BITM_ADC_STAT_DONE0 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Indicates conversion done on Channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_OVF Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_OVF_TMP2 10 /* Indicates overflow in temperature 2 output register */ +#define BITP_ADC_OVF_TMP 9 /* Indicates overflow in temperature output register */ +#define BITP_ADC_OVF_BAT 8 /* Indicates overflow in battery monitoring output register */ +#define BITP_ADC_OVF_CH7 7 /* Indicates overflow in channel 7 output register */ +#define BITP_ADC_OVF_CH6 6 /* Indicates overflow in channel 6 output register */ +#define BITP_ADC_OVF_CH5 5 /* Indicates overflow in channel 5 output register */ +#define BITP_ADC_OVF_CH4 4 /* Indicates overflow in channel 4 output register */ +#define BITP_ADC_OVF_CH3 3 /* Indicates overflow in channel 3 output register */ +#define BITP_ADC_OVF_CH2 2 /* Indicates overflow in channel 2 output register */ +#define BITP_ADC_OVF_CH1 1 /* Indicates overflow in channel 1 output register */ +#define BITP_ADC_OVF_CH0 0 /* Indicates overflow in channel 0 output register */ +#define BITM_ADC_OVF_TMP2 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Indicates overflow in temperature 2 output register */ +#define BITM_ADC_OVF_TMP (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Indicates overflow in temperature output register */ +#define BITM_ADC_OVF_BAT (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Indicates overflow in battery monitoring output register */ +#define BITM_ADC_OVF_CH7 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Indicates overflow in channel 7 output register */ +#define BITM_ADC_OVF_CH6 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Indicates overflow in channel 6 output register */ +#define BITM_ADC_OVF_CH5 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Indicates overflow in channel 5 output register */ +#define BITM_ADC_OVF_CH4 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Indicates overflow in channel 4 output register */ +#define BITM_ADC_OVF_CH3 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Indicates overflow in channel 3 output register */ +#define BITM_ADC_OVF_CH2 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Indicates overflow in channel 2 output register */ +#define BITM_ADC_OVF_CH1 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Indicates overflow in channel 1 output register */ +#define BITM_ADC_OVF_CH0 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Indicates overflow in channel 0 output register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_ALERT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_ALERT_LO3 7 /* Channel 3 Low alert status */ +#define BITP_ADC_ALERT_HI3 6 /* Channel 3 High alert status */ +#define BITP_ADC_ALERT_LO2 5 /* Channel 2 Low alert status */ +#define BITP_ADC_ALERT_HI2 4 /* Channel 2 High alert status */ +#define BITP_ADC_ALERT_LO1 3 /* Channel 1 Low alert status */ +#define BITP_ADC_ALERT_HI1 2 /* Channel 1 High alert status */ +#define BITP_ADC_ALERT_LO0 1 /* Channel 0 Low alert status */ +#define BITP_ADC_ALERT_HI0 0 /* Channel 0 High alert status */ +#define BITM_ADC_ALERT_LO3 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Channel 3 Low alert status */ +#define BITM_ADC_ALERT_HI3 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Channel 3 High alert status */ +#define BITM_ADC_ALERT_LO2 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Channel 2 Low alert status */ +#define BITM_ADC_ALERT_HI2 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Channel 2 High alert status */ +#define BITM_ADC_ALERT_LO1 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Channel 1 Low alert status */ +#define BITM_ADC_ALERT_HI1 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Channel 1 High alert status */ +#define BITM_ADC_ALERT_LO0 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Channel 0 Low alert status */ +#define BITM_ADC_ALERT_HI0 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Channel 0 High alert status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH0_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH0_OUT_RESULT 0 /* Conversion result of channel 0 is stored here */ +#define BITM_ADC_CH0_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of channel 0 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH1_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH1_OUT_RESULT 0 /* Conversion result of channel 1 is stored here */ +#define BITM_ADC_CH1_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of channel 1 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH2_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH2_OUT_RESULT 0 /* Conversion result of channel 2 is stored here */ +#define BITM_ADC_CH2_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of channel 2 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH3_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH3_OUT_RESULT 0 /* Conversion result of channel 3 is stored here */ +#define BITM_ADC_CH3_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of channel 3 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH4_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH4_OUT_RESULT 0 /* Conversion result of channel 4 is stored here */ +#define BITM_ADC_CH4_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of channel 4 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH5_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH5_OUT_RESULT 0 /* Conversion result of channel 5 is stored here */ +#define BITM_ADC_CH5_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of channel 5 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH6_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH6_OUT_RESULT 0 /* Conversion result of channel 6 is stored here */ +#define BITM_ADC_CH6_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of channel 6 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH7_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH7_OUT_RESULT 0 /* Conversion result of channel 7 is stored here */ +#define BITM_ADC_CH7_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of channel 7 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_BAT_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_BAT_OUT_RESULT 0 /* Conversion result of battery monitoring is stored here */ +#define BITM_ADC_BAT_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of battery monitoring is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_TMP_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_TMP_OUT_RESULT 0 /* Conversion result of Temperature measurement 1 is stored here */ +#define BITM_ADC_TMP_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of Temperature measurement 1 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_TMP2_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_TMP2_OUT_RESULT 0 /* Conversion result of Temperature measurement 2 is stored here */ +#define BITM_ADC_TMP2_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of Temperature measurement 2 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_DMA_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_DMA_OUT_RESULT 0 /* Register to store conversion result for DMA */ +#define BITM_ADC_DMA_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Register to store conversion result for DMA */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM0_LO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM0_LO_EN 15 /* To enable low limit comparison on Channel 0 */ +#define BITP_ADC_LIM0_LO_VALUE 0 /* Low limit value for channel 0 */ +#define BITM_ADC_LIM0_LO_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable low limit comparison on Channel 0 */ +#define BITM_ADC_LIM0_LO_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* Low limit value for channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM0_HI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM0_HI_EN 15 /* To enable high limit comparison on Channel 0 */ +#define BITP_ADC_LIM0_HI_VALUE 0 /* High limit value for channel 0 */ +#define BITM_ADC_LIM0_HI_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable high limit comparison on Channel 0 */ +#define BITM_ADC_LIM0_HI_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* High limit value for channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_HYS0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_HYS0_EN 15 /* To enable hysteresis for comparison on Channel 0 */ +#define BITP_ADC_HYS0_MONCYC 12 /* Program number of conversion cycles to monitor channel 0 before raising alert */ +#define BITP_ADC_HYS0_VALUE 0 /* Hysteresis value for Channel 0 */ +#define BITM_ADC_HYS0_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable hysteresis for comparison on Channel 0 */ +#define BITM_ADC_HYS0_MONCYC (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t )) /* Program number of conversion cycles to monitor channel 0 before raising alert */ +#define BITM_ADC_HYS0_VALUE (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t )) /* Hysteresis value for Channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM1_LO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM1_LO_EN 15 /* To enable low limit comparison on Channel 1 */ +#define BITP_ADC_LIM1_LO_VALUE 0 /* Low limit value for channel 1 */ +#define BITM_ADC_LIM1_LO_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable low limit comparison on Channel 1 */ +#define BITM_ADC_LIM1_LO_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* Low limit value for channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM1_HI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM1_HI_EN 15 /* To enable high limit comparison on Channel 1 */ +#define BITP_ADC_LIM1_HI_VALUE 0 /* High limit value for channel 1 */ +#define BITM_ADC_LIM1_HI_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable high limit comparison on Channel 1 */ +#define BITM_ADC_LIM1_HI_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* High limit value for channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_HYS1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_HYS1_EN 15 /* To enable hysteresis for comparison on Channel 1 */ +#define BITP_ADC_HYS1_MONCYC 12 /* Program number of conversion cycles to monitor channel 1 before raising alert */ +#define BITP_ADC_HYS1_VALUE 0 /* Hysteresis value for Channel 1 */ +#define BITM_ADC_HYS1_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable hysteresis for comparison on Channel 1 */ +#define BITM_ADC_HYS1_MONCYC (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t )) /* Program number of conversion cycles to monitor channel 1 before raising alert */ +#define BITM_ADC_HYS1_VALUE (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t )) /* Hysteresis value for Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM2_LO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM2_LO_EN 15 /* To enable low limit comparison on Channel 2 */ +#define BITP_ADC_LIM2_LO_VALUE 0 /* Low limit value for channel 2 */ +#define BITM_ADC_LIM2_LO_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable low limit comparison on Channel 2 */ +#define BITM_ADC_LIM2_LO_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* Low limit value for channel 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM2_HI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM2_HI_EN 15 /* To enable high limit comparison on Channel 2 */ +#define BITP_ADC_LIM2_HI_VALUE 0 /* High limit value for channel 2 */ +#define BITM_ADC_LIM2_HI_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable high limit comparison on Channel 2 */ +#define BITM_ADC_LIM2_HI_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* High limit value for channel 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_HYS2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_HYS2_EN 15 /* To enable hysteresis for comparison on Channel 2 */ +#define BITP_ADC_HYS2_MONCYC 12 /* Program number of conversion cycles to monitor channel 2 before raising alert */ +#define BITP_ADC_HYS2_VALUE 0 /* Hysteresis value for Channel 2 */ +#define BITM_ADC_HYS2_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable hysteresis for comparison on Channel 2 */ +#define BITM_ADC_HYS2_MONCYC (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t )) /* Program number of conversion cycles to monitor channel 2 before raising alert */ +#define BITM_ADC_HYS2_VALUE (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t )) /* Hysteresis value for Channel 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM3_LO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM3_LO_EN 15 /* To enable low limit comparison on Channel 3 */ +#define BITP_ADC_LIM3_LO_VALUE 0 /* Low limit value for channel 3 */ +#define BITM_ADC_LIM3_LO_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable low limit comparison on Channel 3 */ +#define BITM_ADC_LIM3_LO_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* Low limit value for channel 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM3_HI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM3_HI_EN 15 /* To enable high limit comparison on Channel 3 */ +#define BITP_ADC_LIM3_HI_VALUE 0 /* High limit value for channel 3 */ +#define BITM_ADC_LIM3_HI_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable high limit comparison on Channel 3 */ +#define BITM_ADC_LIM3_HI_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* High limit value for channel 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_HYS3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_HYS3_EN 15 /* To enable hysteresis for comparison on Channel 3 */ +#define BITP_ADC_HYS3_MONCYC 12 /* Program number of conversion cycles to monitor channel 3 before raising alert */ +#define BITP_ADC_HYS3_VALUE 0 /* Hysteresis value for Channel 3 */ +#define BITM_ADC_HYS3_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable hysteresis for comparison on Channel 3 */ +#define BITM_ADC_HYS3_MONCYC (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t )) /* Program number of conversion cycles to monitor channel 3 before raising alert */ +#define BITM_ADC_HYS3_VALUE (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t )) /* Hysteresis value for Channel 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CFG1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CFG1_RBUFLP 0 /* Enable low power mode for reference buffer */ +#define BITM_ADC_CFG1_RBUFLP (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Enable low power mode for reference buffer */ + + +/* ============================================================================================================================ + DMA + ============================================================================================================================ */ + +/* ============================================================================================================================ + DMA0 + ============================================================================================================================ */ +#define REG_DMA0_STAT 0x40010000 /* DMA0 DMA Status */ +#define REG_DMA0_CFG 0x40010004 /* DMA0 DMA Configuration */ +#define REG_DMA0_PDBPTR 0x40010008 /* DMA0 DMA Channel Primary Control Database Pointer */ +#define REG_DMA0_ADBPTR 0x4001000C /* DMA0 DMA Channel Alternate Control Database Pointer */ +#define REG_DMA0_SWREQ 0x40010014 /* DMA0 DMA Channel Software Request */ +#define REG_DMA0_RMSK_SET 0x40010020 /* DMA0 DMA Channel Request Mask Set */ +#define REG_DMA0_RMSK_CLR 0x40010024 /* DMA0 DMA Channel Request Mask Clear */ +#define REG_DMA0_EN_SET 0x40010028 /* DMA0 DMA Channel Enable Set */ +#define REG_DMA0_EN_CLR 0x4001002C /* DMA0 DMA Channel Enable Clear */ +#define REG_DMA0_ALT_SET 0x40010030 /* DMA0 DMA Channel Primary Alternate Set */ +#define REG_DMA0_ALT_CLR 0x40010034 /* DMA0 DMA Channel Primary Alternate Clear */ +#define REG_DMA0_PRI_SET 0x40010038 /* DMA0 DMA Channel Priority Set */ +#define REG_DMA0_PRI_CLR 0x4001003C /* DMA0 DMA Channel Priority Clear */ +#define REG_DMA0_ERRCHNL_CLR 0x40010048 /* DMA0 DMA per Channel Error Clear */ +#define REG_DMA0_ERR_CLR 0x4001004C /* DMA0 DMA Bus Error Clear */ +#define REG_DMA0_INVALIDDESC_CLR 0x40010050 /* DMA0 DMA per Channel Invalid Descriptor Clear */ +#define REG_DMA0_BS_SET 0x40010800 /* DMA0 DMA Channel Bytes Swap Enable Set */ +#define REG_DMA0_BS_CLR 0x40010804 /* DMA0 DMA Channel Bytes Swap Enable Clear */ +#define REG_DMA0_SRCADDR_SET 0x40010810 /* DMA0 DMA Channel Source Address Decrement Enable Set */ +#define REG_DMA0_SRCADDR_CLR 0x40010814 /* DMA0 DMA Channel Source Address Decrement Enable Clear */ +#define REG_DMA0_DSTADDR_SET 0x40010818 /* DMA0 DMA Channel Destination Address Decrement Enable Set */ +#define REG_DMA0_DSTADDR_CLR 0x4001081C /* DMA0 DMA Channel Destination Address Decrement Enable Clear */ +#define REG_DMA0_REVID 0x40010FE0 /* DMA0 DMA Controller Revision ID */ + +/* ============================================================================================================================ + DMA Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_STAT_CHANM1 16 /* Number of Available DMA Channels Minus 1 */ +#define BITP_DMA_STAT_MEN 0 /* Enable Status of the Controller */ +#define BITM_DMA_STAT_CHANM1 (_ADI_MSK_3(0x001F0000,0x001F0000UL, uint32_t )) /* Number of Available DMA Channels Minus 1 */ +#define BITM_DMA_STAT_MEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable Status of the Controller */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_CFG_MEN 0 /* Controller Enable */ +#define BITM_DMA_CFG_MEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Controller Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_PDBPTR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_PDBPTR_ADDR 0 /* Pointer to the Base Address of the Primary Data Structure */ +#define BITM_DMA_PDBPTR_ADDR (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Pointer to the Base Address of the Primary Data Structure */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_ADBPTR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_ADBPTR_ADDR 0 /* Base Address of the Alternate Data Structure */ +#define BITM_DMA_ADBPTR_ADDR (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Base Address of the Alternate Data Structure */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_SWREQ Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_SWREQ_CHAN 0 /* Generate Software Request */ +#define BITM_DMA_SWREQ_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Generate Software Request */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_RMSK_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_RMSK_SET_CHAN 0 /* Mask Requests from DMA Channels */ +#define BITM_DMA_RMSK_SET_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Mask Requests from DMA Channels */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_RMSK_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_RMSK_CLR_CHAN 0 /* Clear Request Mask Set Bits */ +#define BITM_DMA_RMSK_CLR_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Clear Request Mask Set Bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_EN_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_EN_SET_CHAN 0 /* Enable DMA Channels */ +#define BITM_DMA_EN_SET_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Enable DMA Channels */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_EN_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_EN_CLR_CHAN 0 /* Disable DMA Channels */ +#define BITM_DMA_EN_CLR_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Disable DMA Channels */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_ALT_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_ALT_SET_CHAN 0 /* Control Structure Status / Select Alternate Structure */ +#define BITM_DMA_ALT_SET_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Control Structure Status / Select Alternate Structure */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_ALT_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_ALT_CLR_CHAN 0 /* Select Primary Data Structure */ +#define BITM_DMA_ALT_CLR_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Select Primary Data Structure */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_PRI_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_PRI_SET_CHAN 0 /* Configure Channel for High Priority */ +#define BITM_DMA_PRI_SET_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Configure Channel for High Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_PRI_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_PRI_CLR_CHPRICLR 0 /* Configure Channel for Default Priority Level */ +#define BITM_DMA_PRI_CLR_CHPRICLR (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Configure Channel for Default Priority Level */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_ERRCHNL_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_ERRCHNL_CLR_CHAN 0 /* Per Channel Bus Error Status/Clear */ +#define BITM_DMA_ERRCHNL_CLR_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Per Channel Bus Error Status/Clear */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_ERR_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_ERR_CLR_CHAN 0 /* Bus Error Status */ +#define BITM_DMA_ERR_CLR_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Bus Error Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_INVALIDDESC_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_INVALIDDESC_CLR_CHAN 0 /* Per Channel Invalid Descriptor Status/Clear */ +#define BITM_DMA_INVALIDDESC_CLR_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Per Channel Invalid Descriptor Status/Clear */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_BS_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_BS_SET_CHAN 0 /* Byte Swap Status */ +#define BITM_DMA_BS_SET_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Byte Swap Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_BS_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_BS_CLR_CHAN 0 /* Disable Byte Swap */ +#define BITM_DMA_BS_CLR_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Disable Byte Swap */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_SRCADDR_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_SRCADDR_SET_CHAN 0 /* Source Address Decrement Status */ +#define BITM_DMA_SRCADDR_SET_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Source Address Decrement Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_SRCADDR_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_SRCADDR_CLR_CHAN 0 /* Disable Source Address Decrement */ +#define BITM_DMA_SRCADDR_CLR_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Disable Source Address Decrement */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_DSTADDR_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_DSTADDR_SET_CHAN 0 /* Destination Address Decrement Status */ +#define BITM_DMA_DSTADDR_SET_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Destination Address Decrement Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_DSTADDR_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_DSTADDR_CLR_CHAN 0 /* Disable Destination Address Decrement */ +#define BITM_DMA_DSTADDR_CLR_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Disable Destination Address Decrement */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_REVID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_REVID_VALUE 0 /* DMA Controller Revision ID */ +#define BITM_DMA_REVID_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFUL, uint32_t )) /* DMA Controller Revision ID */ + + +/* ============================================================================================================================ + Flash Controller + ============================================================================================================================ */ + +/* ============================================================================================================================ + FLCC0 + ============================================================================================================================ */ +#define REG_FLCC0_STAT 0x40018000 /* FLCC0 Status */ +#define REG_FLCC0_IEN 0x40018004 /* FLCC0 Interrupt Enable */ +#define REG_FLCC0_CMD 0x40018008 /* FLCC0 Command */ +#define REG_FLCC0_KH_ADDR 0x4001800C /* FLCC0 Write Address */ +#define REG_FLCC0_KH_DATA0 0x40018010 /* FLCC0 Write Lower Data */ +#define REG_FLCC0_KH_DATA1 0x40018014 /* FLCC0 Write Upper Data */ +#define REG_FLCC0_PAGE_ADDR0 0x40018018 /* FLCC0 Lower Page Address */ +#define REG_FLCC0_PAGE_ADDR1 0x4001801C /* FLCC0 Upper Page Address */ +#define REG_FLCC0_KEY 0x40018020 /* FLCC0 Key */ +#define REG_FLCC0_WR_ABORT_ADDR 0x40018024 /* FLCC0 Write Abort Address */ +#define REG_FLCC0_WRPROT 0x40018028 /* FLCC0 Write Protection */ +#define REG_FLCC0_SIGNATURE 0x4001802C /* FLCC0 Signature */ +#define REG_FLCC0_UCFG 0x40018030 /* FLCC0 User Configuration */ +#define REG_FLCC0_TIME_PARAM0 0x40018034 /* FLCC0 Time Parameter 0 */ +#define REG_FLCC0_TIME_PARAM1 0x40018038 /* FLCC0 Time Parameter 1 */ +#define REG_FLCC0_ABORT_EN_LO 0x4001803C /* FLCC0 IRQ Abort Enable (Lower Bits) */ +#define REG_FLCC0_ABORT_EN_HI 0x40018040 /* FLCC0 IRQ Abort Enable (Upper Bits) */ +#define REG_FLCC0_ECC_CFG 0x40018044 /* FLCC0 ECC Configuration */ +#define REG_FLCC0_ECC_ADDR 0x40018048 /* FLCC0 ECC Status (Address) */ +#define REG_FLCC0_POR_SEC 0x40018050 /* FLCC0 Flash Security */ +#define REG_FLCC0_VOL_CFG 0x40018054 /* FLCC0 Volatile Flash Configuration */ + +/* ============================================================================================================================ + FLCC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_STAT_ACCESS_MODE 31 /* Access Mode */ +#define BITP_FLCC_STAT_CACHESRAMPERR 29 /* SRAM parity errors in Cache Controller */ +#define BITP_FLCC_STAT_ECCDCODE 27 /* DCode AHB Bus Error ECC status */ +#define BITP_FLCC_STAT_ECCICODE 25 /* ICode AHB Bus Error ECC status */ +#define BITP_FLCC_STAT_ECCERRCNT 17 /* ECC correction counter */ +#define BITP_FLCC_STAT_ECCINFOSIGN 15 /* ECC status of flash initialization */ +#define BITP_FLCC_STAT_INIT 14 /* Flash controller initialization in progress */ +#define BITP_FLCC_STAT_SIGNERR 13 /* Signature check failure during initialization */ +#define BITP_FLCC_STAT_OVERLAP 11 /* Overlapping Command */ +#define BITP_FLCC_STAT_ECCRDERR 9 /* ECC IRQ cause */ +#define BITP_FLCC_STAT_ECCERRCMD 7 /* ECC errors detected during user issued SIGN command */ +#define BITP_FLCC_STAT_SLEEPING 6 /* Flash array is in low power (sleep) mode */ +#define BITP_FLCC_STAT_CMDFAIL 4 /* Provides information on command failures */ +#define BITP_FLCC_STAT_WRALCOMP 3 /* Write almost complete */ +#define BITP_FLCC_STAT_CMDCOMP 2 /* Command complete */ +#define BITP_FLCC_STAT_WRCLOSE 1 /* WRITE registers are closed */ +#define BITP_FLCC_STAT_CMDBUSY 0 /* Command busy */ +#define BITM_FLCC_STAT_ACCESS_MODE (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t )) /* Access Mode */ +#define BITM_FLCC_STAT_CACHESRAMPERR (_ADI_MSK_3(0x20000000,0x20000000UL, uint32_t )) /* SRAM parity errors in Cache Controller */ +#define BITM_FLCC_STAT_ECCDCODE (_ADI_MSK_3(0x18000000,0x18000000UL, uint32_t )) /* DCode AHB Bus Error ECC status */ +#define BITM_FLCC_STAT_ECCICODE (_ADI_MSK_3(0x06000000,0x06000000UL, uint32_t )) /* ICode AHB Bus Error ECC status */ +#define BITM_FLCC_STAT_ECCERRCNT (_ADI_MSK_3(0x000E0000,0x000E0000UL, uint32_t )) /* ECC correction counter */ +#define BITM_FLCC_STAT_ECCINFOSIGN (_ADI_MSK_3(0x00018000,0x00018000UL, uint32_t )) /* ECC status of flash initialization */ +#define BITM_FLCC_STAT_INIT (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Flash controller initialization in progress */ +#define BITM_FLCC_STAT_SIGNERR (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* Signature check failure during initialization */ +#define BITM_FLCC_STAT_OVERLAP (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* Overlapping Command */ +#define BITM_FLCC_STAT_ECCRDERR (_ADI_MSK_3(0x00000600,0x00000600UL, uint32_t )) /* ECC IRQ cause */ +#define BITM_FLCC_STAT_ECCERRCMD (_ADI_MSK_3(0x00000180,0x00000180UL, uint32_t )) /* ECC errors detected during user issued SIGN command */ +#define BITM_FLCC_STAT_SLEEPING (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* Flash array is in low power (sleep) mode */ +#define BITM_FLCC_STAT_CMDFAIL (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* Provides information on command failures */ +#define BITM_FLCC_STAT_WRALCOMP (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Write almost complete */ +#define BITM_FLCC_STAT_CMDCOMP (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Command complete */ +#define BITM_FLCC_STAT_WRCLOSE (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* WRITE registers are closed */ +#define BITM_FLCC_STAT_CMDBUSY (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Command busy */ +#define ENUM_FLCC_STAT_DIRECT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* ACCESS_MODE: Flash controller is currently in Direct Access mode; user access to all registers is enabled */ +#define ENUM_FLCC_STAT_INDIRECT (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t )) /* ACCESS_MODE: Flash Controller is currently in Indirect Access mode; user access to registers is limited to read-only access of the status register. Full register access will be restored when the Cryptographic module releases control of the flash controller (crypto completes the ongoing operation within the protected key storage region) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_IEN_ECC_ERROR 6 /* Control whether to generate bus errors, interrupts, or neither in response to 2-bit ECC Error events */ +#define BITP_FLCC_IEN_ECC_CORRECT 4 /* Control whether to generate bus errors, interrupts, or neither in response to 1-bit ECC Correction events */ +#define BITP_FLCC_IEN_CMDFAIL 2 /* Command fail interrupt enable */ +#define BITP_FLCC_IEN_WRALCMPLT 1 /* Write almost complete interrupt enable */ +#define BITP_FLCC_IEN_CMDCMPLT 0 /* Command complete interrupt enable */ +#define BITM_FLCC_IEN_ECC_ERROR (_ADI_MSK_3(0x000000C0,0x000000C0UL, uint32_t )) /* Control whether to generate bus errors, interrupts, or neither in response to 2-bit ECC Error events */ +#define BITM_FLCC_IEN_ECC_CORRECT (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* Control whether to generate bus errors, interrupts, or neither in response to 1-bit ECC Correction events */ +#define BITM_FLCC_IEN_CMDFAIL (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Command fail interrupt enable */ +#define BITM_FLCC_IEN_WRALCMPLT (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Write almost complete interrupt enable */ +#define BITM_FLCC_IEN_CMDCMPLT (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Command complete interrupt enable */ +#define ENUM_FLCC_IEN_NONE_ERR (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* ECC_ERROR: Do not generate a response to ECC events */ +#define ENUM_FLCC_IEN_BUS_ERR_ERR (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* ECC_ERROR: Generate Bus Errors in response to ECC events */ +#define ENUM_FLCC_IEN_IRQ_ERR (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* ECC_ERROR: Generate IRQs in response to ECC events */ +#define ENUM_FLCC_IEN_NONE_COR (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* ECC_CORRECT: Do not generate a response to ECC events */ +#define ENUM_FLCC_IEN_BUS_ERR_COR (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* ECC_CORRECT: Generate Bus Errors in response to ECC events */ +#define ENUM_FLCC_IEN_IRQ_COR (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* ECC_CORRECT: Generate IRQs in response to ECC events */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_CMD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_CMD_VALUE 0 /* Commands */ +#define BITM_FLCC_CMD_VALUE (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t )) /* Commands */ +#define ENUM_FLCC_CMD_IDLE (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* VALUE: IDLE */ +#define ENUM_FLCC_CMD_ABORT (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* VALUE: ABORT */ +#define ENUM_FLCC_CMD_SLEEP (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* VALUE: Requests flash to enter Sleep mode */ +#define ENUM_FLCC_CMD_SIGN (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* VALUE: SIGN */ +#define ENUM_FLCC_CMD_WRITE (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* VALUE: WRITE */ +#define ENUM_FLCC_CMD_BLANK_CHECK (_ADI_MSK_3(0x00000005,0x00000005UL, uint32_t )) /* VALUE: Checks all of User Space; fails if any bits in user space are cleared */ +#define ENUM_FLCC_CMD_ERASEPAGE (_ADI_MSK_3(0x00000006,0x00000006UL, uint32_t )) /* VALUE: ERASEPAGE */ +#define ENUM_FLCC_CMD_MASSERASE (_ADI_MSK_3(0x00000007,0x00000007UL, uint32_t )) /* VALUE: MASSERASE */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_KH_ADDR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_KH_ADDR_VALUE 3 /* Address to be written on a WRITE command */ +#define BITM_FLCC_KH_ADDR_VALUE (_ADI_MSK_3(0x000FFFF8,0x000FFFF8UL, uint32_t )) /* Address to be written on a WRITE command */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_KH_DATA0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_KH_DATA0_VALUE 0 /* Lower half of 64-bit dual word data to be written on a Write command */ +#define BITM_FLCC_KH_DATA0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Lower half of 64-bit dual word data to be written on a Write command */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_KH_DATA1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_KH_DATA1_VALUE 0 /* Upper half of 64-bit dual word data to be written on a Write command */ +#define BITM_FLCC_KH_DATA1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Upper half of 64-bit dual word data to be written on a Write command */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_PAGE_ADDR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_PAGE_ADDR0_VALUE 10 /* Lower address bits of the page address */ +#define BITM_FLCC_PAGE_ADDR0_VALUE (_ADI_MSK_3(0x000FFC00,0x000FFC00UL, uint32_t )) /* Lower address bits of the page address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_PAGE_ADDR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_PAGE_ADDR1_VALUE 10 /* Upper address bits of the page address */ +#define BITM_FLCC_PAGE_ADDR1_VALUE (_ADI_MSK_3(0x000FFC00,0x000FFC00UL, uint32_t )) /* Upper address bits of the page address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_KEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_KEY_VALUE 0 /* Key register */ +#define BITM_FLCC_KEY_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key register */ +#define ENUM_FLCC_KEY_USERKEY (_ADI_MSK_3(0x676C7565,0x676C7565UL, uint32_t )) /* VALUE: USERKEY */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_WR_ABORT_ADDR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_WR_ABORT_ADDR_VALUE 0 /* Address of recently aborted write command */ +#define BITM_FLCC_WR_ABORT_ADDR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Address of recently aborted write command */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_WRPROT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_WRPROT_WORD 0 /* Clear bits to write protect related groups of user space pages */ +#define BITM_FLCC_WRPROT_WORD (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Clear bits to write protect related groups of user space pages */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_SIGNATURE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_SIGNATURE_VALUE 0 /* Read signature */ +#define BITM_FLCC_SIGNATURE_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Read signature */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_UCFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_UCFG_AUTOINCEN 1 /* Auto Address Increment for Key Hole Access */ +#define BITP_FLCC_UCFG_KHDMAEN 0 /* Key hole DMA enable */ +#define BITM_FLCC_UCFG_AUTOINCEN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Auto Address Increment for Key Hole Access */ +#define BITM_FLCC_UCFG_KHDMAEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Key hole DMA enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_TIME_PARAM0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_TIME_PARAM0_TNVH1 28 /* NVSTR Hold time during Mass Erase */ +#define BITP_FLCC_TIME_PARAM0_TERASE 24 /* Erase Time */ +#define BITP_FLCC_TIME_PARAM0_TRCV 20 /* Recovery time */ +#define BITP_FLCC_TIME_PARAM0_TNVH 16 /* NVSTR Hold time */ +#define BITP_FLCC_TIME_PARAM0_TPROG 12 /* Program time */ +#define BITP_FLCC_TIME_PARAM0_TPGS 8 /* NVSTR to Program setup time */ +#define BITP_FLCC_TIME_PARAM0_TNVS 4 /* PROG/ERASE to NVSTR setup time */ +#define BITP_FLCC_TIME_PARAM0_DIVREFCLK 0 /* Divide Reference Clock (by 2) */ +#define BITM_FLCC_TIME_PARAM0_TNVH1 (_ADI_MSK_3(0xF0000000,0xF0000000UL, uint32_t )) /* NVSTR Hold time during Mass Erase */ +#define BITM_FLCC_TIME_PARAM0_TERASE (_ADI_MSK_3(0x0F000000,0x0F000000UL, uint32_t )) /* Erase Time */ +#define BITM_FLCC_TIME_PARAM0_TRCV (_ADI_MSK_3(0x00F00000,0x00F00000UL, uint32_t )) /* Recovery time */ +#define BITM_FLCC_TIME_PARAM0_TNVH (_ADI_MSK_3(0x000F0000,0x000F0000UL, uint32_t )) /* NVSTR Hold time */ +#define BITM_FLCC_TIME_PARAM0_TPROG (_ADI_MSK_3(0x0000F000,0x0000F000UL, uint32_t )) /* Program time */ +#define BITM_FLCC_TIME_PARAM0_TPGS (_ADI_MSK_3(0x00000F00,0x00000F00UL, uint32_t )) /* NVSTR to Program setup time */ +#define BITM_FLCC_TIME_PARAM0_TNVS (_ADI_MSK_3(0x000000F0,0x000000F0UL, uint32_t )) /* PROG/ERASE to NVSTR setup time */ +#define BITM_FLCC_TIME_PARAM0_DIVREFCLK (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Divide Reference Clock (by 2) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_TIME_PARAM1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_TIME_PARAM1_CURWAITSTATES 8 /* Current wait states [2:0] */ +#define BITP_FLCC_TIME_PARAM1_WAITSTATES 4 /* Number of wait states to access flash */ +#define BITP_FLCC_TIME_PARAM1_TWK 0 /* Wake up time */ +#define BITM_FLCC_TIME_PARAM1_CURWAITSTATES (_ADI_MSK_3(0x00000700,0x00000700UL, uint32_t )) /* Current wait states [2:0] */ +#define BITM_FLCC_TIME_PARAM1_WAITSTATES (_ADI_MSK_3(0x00000070,0x00000070UL, uint32_t )) /* Number of wait states to access flash */ +#define BITM_FLCC_TIME_PARAM1_TWK (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t )) /* Wake up time */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_ABORT_EN_LO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_ABORT_EN_LO_VALUE 0 /* Sys IRQ Abort Enable */ +#define BITM_FLCC_ABORT_EN_LO_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Sys IRQ Abort Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_ABORT_EN_HI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_ABORT_EN_HI_VALUE 0 /* Sys IRQ Abort Enable */ +#define BITM_FLCC_ABORT_EN_HI_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Sys IRQ Abort Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_ECC_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_ECC_CFG_PTR 8 /* ECC start page pointer */ +#define BITP_FLCC_ECC_CFG_INFOEN 1 /* Info space ECC Enable bit */ +#define BITP_FLCC_ECC_CFG_EN 0 /* ECC Enable */ +#define BITM_FLCC_ECC_CFG_PTR (_ADI_MSK_3(0xFFFFFF00,0xFFFFFF00UL, uint32_t )) /* ECC start page pointer */ +#define BITM_FLCC_ECC_CFG_INFOEN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Info space ECC Enable bit */ +#define BITM_FLCC_ECC_CFG_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* ECC Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_ECC_ADDR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_ECC_ADDR_VALUE 0 /* This register has the address for which ECC error is detected */ +#define BITM_FLCC_ECC_ADDR_VALUE (_ADI_MSK_3(0x000FFFFF,0x000FFFFFUL, uint32_t )) /* This register has the address for which ECC error is detected */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_POR_SEC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_POR_SEC_SECURE 0 /* Set this bit to prevent read or write access to User Space (sticky when set) */ +#define BITM_FLCC_POR_SEC_SECURE (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Set this bit to prevent read or write access to User Space (sticky when set) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_VOL_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_VOL_CFG_INFO_REMAP 0 /* Alias the info space to the base address of user space */ +#define BITM_FLCC_VOL_CFG_INFO_REMAP (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Alias the info space to the base address of user space */ + + +/* ============================================================================================================================ + Cache Controller + ============================================================================================================================ */ + +/* ============================================================================================================================ + FLCC0_CACHE + ============================================================================================================================ */ +#define REG_FLCC0_CACHE_STAT 0x40018058 /* FLCC0_CACHE Cache Status Register */ +#define REG_FLCC0_CACHE_SETUP 0x4001805C /* FLCC0_CACHE Cache Setup Register */ +#define REG_FLCC0_CACHE_KEY 0x40018060 /* FLCC0_CACHE Cache Key Register */ + +/* ============================================================================================================================ + FLCC_CACHE Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_CACHE_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_CACHE_STAT_ICEN 0 /* If this bit is set, I-Cache is enabled */ +#define BITM_FLCC_CACHE_STAT_ICEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* If this bit is set, I-Cache is enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_CACHE_SETUP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_CACHE_SETUP_LCKIC 1 /* If this bit is set, I-Cache contents are locked */ +#define BITP_FLCC_CACHE_SETUP_ICEN 0 /* If this bit set, I-Cache is enabled for AHB accesses */ +#define BITM_FLCC_CACHE_SETUP_LCKIC (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* If this bit is set, I-Cache contents are locked */ +#define BITM_FLCC_CACHE_SETUP_ICEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* If this bit set, I-Cache is enabled for AHB accesses */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_CACHE_KEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_CACHE_KEY_VALUE 0 /* Cache Key */ +#define BITM_FLCC_CACHE_KEY_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Cache Key */ + + +/* ============================================================================================================================ + + ============================================================================================================================ */ + +/* ============================================================================================================================ + GPIO0 + ============================================================================================================================ */ +#define REG_GPIO0_CFG 0x40020000 /* GPIO0 Port Configuration */ +#define REG_GPIO0_OEN 0x40020004 /* GPIO0 Port Output Enable */ +#define REG_GPIO0_PE 0x40020008 /* GPIO0 Port Output Pull-up/Pull-down Enable */ +#define REG_GPIO0_IEN 0x4002000C /* GPIO0 Port Input Path Enable */ +#define REG_GPIO0_IN 0x40020010 /* GPIO0 Port Registered Data Input */ +#define REG_GPIO0_OUT 0x40020014 /* GPIO0 Port Data Output */ +#define REG_GPIO0_SET 0x40020018 /* GPIO0 Port Data Out Set */ +#define REG_GPIO0_CLR 0x4002001C /* GPIO0 Port Data Out Clear */ +#define REG_GPIO0_TGL 0x40020020 /* GPIO0 Port Pin Toggle */ +#define REG_GPIO0_POL 0x40020024 /* GPIO0 Port Interrupt Polarity */ +#define REG_GPIO0_IENA 0x40020028 /* GPIO0 Port Interrupt A Enable */ +#define REG_GPIO0_IENB 0x4002002C /* GPIO0 Port Interrupt B Enable */ +#define REG_GPIO0_INT 0x40020030 /* GPIO0 Port Interrupt Status */ +#define REG_GPIO0_DS 0x40020034 /* GPIO0 Port Drive Strength Select */ + +/* ============================================================================================================================ + GPIO1 + ============================================================================================================================ */ +#define REG_GPIO1_CFG 0x40020040 /* GPIO1 Port Configuration */ +#define REG_GPIO1_OEN 0x40020044 /* GPIO1 Port Output Enable */ +#define REG_GPIO1_PE 0x40020048 /* GPIO1 Port Output Pull-up/Pull-down Enable */ +#define REG_GPIO1_IEN 0x4002004C /* GPIO1 Port Input Path Enable */ +#define REG_GPIO1_IN 0x40020050 /* GPIO1 Port Registered Data Input */ +#define REG_GPIO1_OUT 0x40020054 /* GPIO1 Port Data Output */ +#define REG_GPIO1_SET 0x40020058 /* GPIO1 Port Data Out Set */ +#define REG_GPIO1_CLR 0x4002005C /* GPIO1 Port Data Out Clear */ +#define REG_GPIO1_TGL 0x40020060 /* GPIO1 Port Pin Toggle */ +#define REG_GPIO1_POL 0x40020064 /* GPIO1 Port Interrupt Polarity */ +#define REG_GPIO1_IENA 0x40020068 /* GPIO1 Port Interrupt A Enable */ +#define REG_GPIO1_IENB 0x4002006C /* GPIO1 Port Interrupt B Enable */ +#define REG_GPIO1_INT 0x40020070 /* GPIO1 Port Interrupt Status */ +#define REG_GPIO1_DS 0x40020074 /* GPIO1 Port Drive Strength Select */ + +/* ============================================================================================================================ + GPIO2 + ============================================================================================================================ */ +#define REG_GPIO2_CFG 0x40020080 /* GPIO2 Port Configuration */ +#define REG_GPIO2_OEN 0x40020084 /* GPIO2 Port Output Enable */ +#define REG_GPIO2_PE 0x40020088 /* GPIO2 Port Output Pull-up/Pull-down Enable */ +#define REG_GPIO2_IEN 0x4002008C /* GPIO2 Port Input Path Enable */ +#define REG_GPIO2_IN 0x40020090 /* GPIO2 Port Registered Data Input */ +#define REG_GPIO2_OUT 0x40020094 /* GPIO2 Port Data Output */ +#define REG_GPIO2_SET 0x40020098 /* GPIO2 Port Data Out Set */ +#define REG_GPIO2_CLR 0x4002009C /* GPIO2 Port Data Out Clear */ +#define REG_GPIO2_TGL 0x400200A0 /* GPIO2 Port Pin Toggle */ +#define REG_GPIO2_POL 0x400200A4 /* GPIO2 Port Interrupt Polarity */ +#define REG_GPIO2_IENA 0x400200A8 /* GPIO2 Port Interrupt A Enable */ +#define REG_GPIO2_IENB 0x400200AC /* GPIO2 Port Interrupt B Enable */ +#define REG_GPIO2_INT 0x400200B0 /* GPIO2 Port Interrupt Status */ +#define REG_GPIO2_DS 0x400200B4 /* GPIO2 Port Drive Strength Select */ + +/* ============================================================================================================================ + GPIO3 + ============================================================================================================================ */ +#define REG_GPIO3_CFG 0x400200C0 /* GPIO3 Port Configuration */ +#define REG_GPIO3_OEN 0x400200C4 /* GPIO3 Port Output Enable */ +#define REG_GPIO3_PE 0x400200C8 /* GPIO3 Port Output Pull-up/Pull-down Enable */ +#define REG_GPIO3_IEN 0x400200CC /* GPIO3 Port Input Path Enable */ +#define REG_GPIO3_IN 0x400200D0 /* GPIO3 Port Registered Data Input */ +#define REG_GPIO3_OUT 0x400200D4 /* GPIO3 Port Data Output */ +#define REG_GPIO3_SET 0x400200D8 /* GPIO3 Port Data Out Set */ +#define REG_GPIO3_CLR 0x400200DC /* GPIO3 Port Data Out Clear */ +#define REG_GPIO3_TGL 0x400200E0 /* GPIO3 Port Pin Toggle */ +#define REG_GPIO3_POL 0x400200E4 /* GPIO3 Port Interrupt Polarity */ +#define REG_GPIO3_IENA 0x400200E8 /* GPIO3 Port Interrupt A Enable */ +#define REG_GPIO3_IENB 0x400200EC /* GPIO3 Port Interrupt B Enable */ +#define REG_GPIO3_INT 0x400200F0 /* GPIO3 Port Interrupt Status */ +#define REG_GPIO3_DS 0x400200F4 /* GPIO3 Port Drive Strength Select */ + +/* ============================================================================================================================ + GPIO Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_CFG_PIN15 30 /* Pin 15 configuration bits */ +#define BITP_GPIO_CFG_PIN14 28 /* Pin 14 configuration bits */ +#define BITP_GPIO_CFG_PIN13 26 /* Pin 13 configuration bits */ +#define BITP_GPIO_CFG_PIN12 24 /* Pin 12 configuration bits */ +#define BITP_GPIO_CFG_PIN11 22 /* Pin 11 configuration bits */ +#define BITP_GPIO_CFG_PIN10 20 /* Pin 10 configuration bits */ +#define BITP_GPIO_CFG_PIN09 18 /* Pin 9 configuration bits */ +#define BITP_GPIO_CFG_PIN08 16 /* Pin 8 configuration bits */ +#define BITP_GPIO_CFG_PIN07 14 /* Pin 7 configuration bits */ +#define BITP_GPIO_CFG_PIN06 12 /* Pin 6 configuration bits */ +#define BITP_GPIO_CFG_PIN05 10 /* Pin 5 configuration bits */ +#define BITP_GPIO_CFG_PIN04 8 /* Pin 4 configuration bits */ +#define BITP_GPIO_CFG_PIN03 6 /* Pin 3 configuration bits */ +#define BITP_GPIO_CFG_PIN02 4 /* Pin 2 configuration bits */ +#define BITP_GPIO_CFG_PIN01 2 /* Pin 1 configuration bits */ +#define BITP_GPIO_CFG_PIN00 0 /* Pin 0 configuration bits */ +#define BITM_GPIO_CFG_PIN15 (_ADI_MSK_3(0xC0000000,0xC0000000UL, uint32_t )) /* Pin 15 configuration bits */ +#define BITM_GPIO_CFG_PIN14 (_ADI_MSK_3(0x30000000,0x30000000UL, uint32_t )) /* Pin 14 configuration bits */ +#define BITM_GPIO_CFG_PIN13 (_ADI_MSK_3(0x0C000000,0x0C000000UL, uint32_t )) /* Pin 13 configuration bits */ +#define BITM_GPIO_CFG_PIN12 (_ADI_MSK_3(0x03000000,0x03000000UL, uint32_t )) /* Pin 12 configuration bits */ +#define BITM_GPIO_CFG_PIN11 (_ADI_MSK_3(0x00C00000,0x00C00000UL, uint32_t )) /* Pin 11 configuration bits */ +#define BITM_GPIO_CFG_PIN10 (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t )) /* Pin 10 configuration bits */ +#define BITM_GPIO_CFG_PIN09 (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* Pin 9 configuration bits */ +#define BITM_GPIO_CFG_PIN08 (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t )) /* Pin 8 configuration bits */ +#define BITM_GPIO_CFG_PIN07 (_ADI_MSK_3(0x0000C000,0x0000C000UL, uint32_t )) /* Pin 7 configuration bits */ +#define BITM_GPIO_CFG_PIN06 (_ADI_MSK_3(0x00003000,0x00003000UL, uint32_t )) /* Pin 6 configuration bits */ +#define BITM_GPIO_CFG_PIN05 (_ADI_MSK_3(0x00000C00,0x00000C00UL, uint32_t )) /* Pin 5 configuration bits */ +#define BITM_GPIO_CFG_PIN04 (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* Pin 4 configuration bits */ +#define BITM_GPIO_CFG_PIN03 (_ADI_MSK_3(0x000000C0,0x000000C0UL, uint32_t )) /* Pin 3 configuration bits */ +#define BITM_GPIO_CFG_PIN02 (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* Pin 2 configuration bits */ +#define BITM_GPIO_CFG_PIN01 (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t )) /* Pin 1 configuration bits */ +#define BITM_GPIO_CFG_PIN00 (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* Pin 0 configuration bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_OEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_OEN_VALUE 0 /* Pin Output Drive enable */ +#define BITM_GPIO_OEN_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Pin Output Drive enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_PE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_PE_VALUE 0 /* Pin Pull enable */ +#define BITM_GPIO_PE_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Pin Pull enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_IEN_VALUE 0 /* Input path enable */ +#define BITM_GPIO_IEN_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Input path enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_IN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_IN_VALUE 0 /* Registered data input */ +#define BITM_GPIO_IN_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Registered data input */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_OUT_VALUE 0 /* Data out */ +#define BITM_GPIO_OUT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Data out */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_SET_VALUE 0 /* Set the output HIGH for the pin */ +#define BITM_GPIO_SET_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Set the output HIGH for the pin */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_CLR_VALUE 0 /* Set the output low for the port pin */ +#define BITM_GPIO_CLR_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Set the output low for the port pin */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_TGL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_TGL_VALUE 0 /* Toggle the output of the port pin */ +#define BITM_GPIO_TGL_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Toggle the output of the port pin */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_POL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_POL_VALUE 0 /* Interrupt polarity */ +#define BITM_GPIO_POL_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Interrupt polarity */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_IENA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_IENA_VALUE 0 /* Interrupt A enable */ +#define BITM_GPIO_IENA_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Interrupt A enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_IENB Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_IENB_VALUE 0 /* Interrupt B enable */ +#define BITM_GPIO_IENB_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Interrupt B enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_INT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_INT_VALUE 0 /* Interrupt Status */ +#define BITM_GPIO_INT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Interrupt Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_DS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_DS_VALUE 0 /* Drive strength select */ +#define BITM_GPIO_DS_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Drive strength select */ + + +/* ============================================================================================================================ + Serial Port + ============================================================================================================================ */ + +/* ============================================================================================================================ + SPORT0 + ============================================================================================================================ */ +#define REG_SPORT0_CTL_A 0x40038000 /* SPORT0 Half SPORT 'A' Control Register */ +#define REG_SPORT0_DIV_A 0x40038004 /* SPORT0 Half SPORT 'A' Divisor Register */ +#define REG_SPORT0_IEN_A 0x40038008 /* SPORT0 Half SPORT A's Interrupt Enable register */ +#define REG_SPORT0_STAT_A 0x4003800C /* SPORT0 Half SPORT 'A' Status register */ +#define REG_SPORT0_NUMTRAN_A 0x40038010 /* SPORT0 Half SPORT A Number of transfers register */ +#define REG_SPORT0_CNVT_A 0x40038014 /* SPORT0 Half SPORT 'A' CNV width */ +#define REG_SPORT0_TX_A 0x40038020 /* SPORT0 Half SPORT 'A' Tx Buffer Register */ +#define REG_SPORT0_RX_A 0x40038028 /* SPORT0 Half SPORT 'A' Rx Buffer Register */ +#define REG_SPORT0_CTL_B 0x40038040 /* SPORT0 Half SPORT 'B' Control Register */ +#define REG_SPORT0_DIV_B 0x40038044 /* SPORT0 Half SPORT 'B' Divisor Register */ +#define REG_SPORT0_IEN_B 0x40038048 /* SPORT0 Half SPORT B's Interrupt Enable register */ +#define REG_SPORT0_STAT_B 0x4003804C /* SPORT0 Half SPORT 'B' Status register */ +#define REG_SPORT0_NUMTRAN_B 0x40038050 /* SPORT0 Half SPORT B Number of transfers register */ +#define REG_SPORT0_CNVT_B 0x40038054 /* SPORT0 Half SPORT 'B' CNV width register */ +#define REG_SPORT0_TX_B 0x40038060 /* SPORT0 Half SPORT 'B' Tx Buffer Register */ +#define REG_SPORT0_RX_B 0x40038068 /* SPORT0 Half SPORT 'B' Rx Buffer Register */ + +/* ============================================================================================================================ + SPORT Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_CTL_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_CTL_A_DMAEN 26 /* DMA Enable */ +#define BITP_SPORT_CTL_A_SPTRAN 25 /* Serial Port Transfer Direction */ +#define BITP_SPORT_CTL_A_GCLKEN 21 /* Gated Clock Enable */ +#define BITP_SPORT_CTL_A_FSERRMODE 20 /* Frame Sync Error Operation */ +#define BITP_SPORT_CTL_A_PACK 18 /* Packing Enable */ +#define BITP_SPORT_CTL_A_LAFS 17 /* Late Frame Sync */ +#define BITP_SPORT_CTL_A_LFS 16 /* Active-Low Frame Sync */ +#define BITP_SPORT_CTL_A_DIFS 15 /* Data-Independent Frame Sync */ +#define BITP_SPORT_CTL_A_IFS 14 /* Internal Frame Sync */ +#define BITP_SPORT_CTL_A_FSR 13 /* Frame Sync Required */ +#define BITP_SPORT_CTL_A_CKRE 12 /* Clock Rising Edge */ +#define BITP_SPORT_CTL_A_OPMODE 11 /* Operation mode */ +#define BITP_SPORT_CTL_A_ICLK 10 /* Internal Clock */ +#define BITP_SPORT_CTL_A_SLEN 4 /* Serial Word Length */ +#define BITP_SPORT_CTL_A_LSBF 3 /* Least-Significant Bit First */ +#define BITP_SPORT_CTL_A_CKMUXSEL 2 /* Clock Multiplexer Select */ +#define BITP_SPORT_CTL_A_FSMUXSEL 1 /* Frame Sync Multiplexer Select */ +#define BITP_SPORT_CTL_A_SPEN 0 /* Serial Port Enable */ +#define BITM_SPORT_CTL_A_DMAEN (_ADI_MSK_3(0x04000000,0x04000000UL, uint32_t )) /* DMA Enable */ +#define BITM_SPORT_CTL_A_SPTRAN (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t )) /* Serial Port Transfer Direction */ +#define BITM_SPORT_CTL_A_GCLKEN (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t )) /* Gated Clock Enable */ +#define BITM_SPORT_CTL_A_FSERRMODE (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t )) /* Frame Sync Error Operation */ +#define BITM_SPORT_CTL_A_PACK (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* Packing Enable */ +#define BITM_SPORT_CTL_A_LAFS (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t )) /* Late Frame Sync */ +#define BITM_SPORT_CTL_A_LFS (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* Active-Low Frame Sync */ +#define BITM_SPORT_CTL_A_DIFS (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* Data-Independent Frame Sync */ +#define BITM_SPORT_CTL_A_IFS (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Internal Frame Sync */ +#define BITM_SPORT_CTL_A_FSR (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* Frame Sync Required */ +#define BITM_SPORT_CTL_A_CKRE (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* Clock Rising Edge */ +#define BITM_SPORT_CTL_A_OPMODE (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* Operation mode */ +#define BITM_SPORT_CTL_A_ICLK (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* Internal Clock */ +#define BITM_SPORT_CTL_A_SLEN (_ADI_MSK_3(0x000001F0,0x000001F0UL, uint32_t )) /* Serial Word Length */ +#define BITM_SPORT_CTL_A_LSBF (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Least-Significant Bit First */ +#define BITM_SPORT_CTL_A_CKMUXSEL (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Clock Multiplexer Select */ +#define BITM_SPORT_CTL_A_FSMUXSEL (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Frame Sync Multiplexer Select */ +#define BITM_SPORT_CTL_A_SPEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Serial Port Enable */ +#define ENUM_SPORT_CTL_A_CTL_RX (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* SPTRAN: Receive */ +#define ENUM_SPORT_CTL_A_CTL_TX (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t )) /* SPTRAN: Transmit */ +#define ENUM_SPORT_CTL_A_CTL_GCLK_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* GCLKEN: Disable */ +#define ENUM_SPORT_CTL_A_CTL_GCLK_EN (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t )) /* GCLKEN: Enable */ +#define ENUM_SPORT_CTL_A_CTL_PACK_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* PACK: Disable */ +#define ENUM_SPORT_CTL_A_CTL_PACK_8BIT (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t )) /* PACK: 8-bit packing enable */ +#define ENUM_SPORT_CTL_A_CTL_PACK_16BIT (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t )) /* PACK: 16-bit packing enable */ +#define ENUM_SPORT_CTL_A_CTL_EARLY_FS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* LAFS: Early frame sync */ +#define ENUM_SPORT_CTL_A_CTL_LATE_FS (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t )) /* LAFS: Late frame sync */ +#define ENUM_SPORT_CTL_A_CTL_FS_LO (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* LFS: Active high frame sync */ +#define ENUM_SPORT_CTL_A_CTL_FS_HI (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* LFS: Active low frame sync */ +#define ENUM_SPORT_CTL_A_CTL_DATA_DEP_FS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* DIFS: Data-dependent frame sync */ +#define ENUM_SPORT_CTL_A_CTL_DATA_INDP_FS (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* DIFS: Data-independent frame sync */ +#define ENUM_SPORT_CTL_A_CTL_EXTERNAL_FS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* IFS: External frame sync */ +#define ENUM_SPORT_CTL_A_CTL_INTERNAL_FS (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* IFS: Internal frame sync */ +#define ENUM_SPORT_CTL_A_CTL_FS_NOT_REQ (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* FSR: No frame sync required */ +#define ENUM_SPORT_CTL_A_CTL_FS_REQ (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* FSR: Frame sync required */ +#define ENUM_SPORT_CTL_A_CTL_CLK_FALL_EDGE (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* CKRE: Clock falling edge */ +#define ENUM_SPORT_CTL_A_CTL_CLK_RISE_EDGE (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* CKRE: Clock rising edge */ +#define ENUM_SPORT_CTL_A_CTL_SERIAL (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* OPMODE: DSP standard */ +#define ENUM_SPORT_CTL_A_CTL_TIMER_EN_MODE (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* OPMODE: Timer_enable mode */ +#define ENUM_SPORT_CTL_A_CTL_EXTERNAL_CLK (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* ICLK: External clock */ +#define ENUM_SPORT_CTL_A_CTL_INTERNAL_CLK (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* ICLK: Internal clock */ +#define ENUM_SPORT_CTL_A_CTL_MSB_FIRST (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* LSBF: MSB first sent/received */ +#define ENUM_SPORT_CTL_A_CTL_LSB_FIRST (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* LSBF: LSB first sent/received */ +#define ENUM_SPORT_CTL_A_CTL_CLK_MUX_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* CKMUXSEL: Disable serial clock multiplexing */ +#define ENUM_SPORT_CTL_A_CTL_CLK_MUX_EN (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* CKMUXSEL: Enable serial clock multiplexing */ +#define ENUM_SPORT_CTL_A_CTL_FS_MUX_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* FSMUXSEL: Disable frame sync multiplexing */ +#define ENUM_SPORT_CTL_A_CTL_FS_MUX_EN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* FSMUXSEL: Enable frame sync multiplexing */ +#define ENUM_SPORT_CTL_A_CTL_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* SPEN: Disable */ +#define ENUM_SPORT_CTL_A_CTL_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* SPEN: Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_DIV_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_DIV_A_FSDIV 16 /* Frame Sync Divisor */ +#define BITP_SPORT_DIV_A_CLKDIV 0 /* Clock Divisor */ +#define BITM_SPORT_DIV_A_FSDIV (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t )) /* Frame Sync Divisor */ +#define BITM_SPORT_DIV_A_CLKDIV (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t )) /* Clock Divisor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_IEN_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_IEN_A_SYSDATERR 4 /* Data error for system writes or reads */ +#define BITP_SPORT_IEN_A_DATA 3 /* Data request interrupt to the core */ +#define BITP_SPORT_IEN_A_FSERRMSK 2 /* Frame Sync Error (Interrupt) Mask */ +#define BITP_SPORT_IEN_A_DERRMSK 1 /* Data Error (Interrupt) Mask */ +#define BITP_SPORT_IEN_A_TF 0 /* Transfer Finish Interrupt Enable */ +#define BITM_SPORT_IEN_A_SYSDATERR (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Data error for system writes or reads */ +#define BITM_SPORT_IEN_A_DATA (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Data request interrupt to the core */ +#define BITM_SPORT_IEN_A_FSERRMSK (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Frame Sync Error (Interrupt) Mask */ +#define BITM_SPORT_IEN_A_DERRMSK (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Data Error (Interrupt) Mask */ +#define BITM_SPORT_IEN_A_TF (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Transfer Finish Interrupt Enable */ +#define ENUM_SPORT_IEN_A_CTL_TXFIN_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* TF: Transfer finish Interrupt is disabled */ +#define ENUM_SPORT_IEN_A_CTL_TXFIN_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* TF: Transfer Finish Interrupt is Enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_STAT_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_STAT_A_DXS 8 /* Data Transfer Buffer Status */ +#define BITP_SPORT_STAT_A_SYSDATERR 4 /* System Data Error Status */ +#define BITP_SPORT_STAT_A_DATA 3 /* Data Buffer status */ +#define BITP_SPORT_STAT_A_FSERR 2 /* Frame Sync Error Status */ +#define BITP_SPORT_STAT_A_DERR 1 /* Data Error Status */ +#define BITP_SPORT_STAT_A_TFI 0 /* Transmit Finish Interrupt Status */ +#define BITM_SPORT_STAT_A_DXS (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* Data Transfer Buffer Status */ +#define BITM_SPORT_STAT_A_SYSDATERR (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* System Data Error Status */ +#define BITM_SPORT_STAT_A_DATA (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Data Buffer status */ +#define BITM_SPORT_STAT_A_FSERR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Frame Sync Error Status */ +#define BITM_SPORT_STAT_A_DERR (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Data Error Status */ +#define BITM_SPORT_STAT_A_TFI (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Transmit Finish Interrupt Status */ +#define ENUM_SPORT_STAT_A_CTL_EMPTY (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* DXS: Empty */ +#define ENUM_SPORT_STAT_A_CTL_PART_FULL (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* DXS: Partially full */ +#define ENUM_SPORT_STAT_A_CTL_FULL (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* DXS: Full */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_NUMTRAN_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_NUMTRAN_A_VALUE 0 /* Number of transfers (Half SPORT A) */ +#define BITM_SPORT_NUMTRAN_A_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFUL, uint32_t )) /* Number of transfers (Half SPORT A) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_CNVT_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_CNVT_A_CNVT2FS 16 /* CNV to FS duration: Half SPORT A */ +#define BITP_SPORT_CNVT_A_POL 8 /* Polarity of the CNV signal */ +#define BITP_SPORT_CNVT_A_WID 0 /* CNV signal width: Half SPORT A */ +#define BITM_SPORT_CNVT_A_CNVT2FS (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t )) /* CNV to FS duration: Half SPORT A */ +#define BITM_SPORT_CNVT_A_POL (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* Polarity of the CNV signal */ +#define BITM_SPORT_CNVT_A_WID (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t )) /* CNV signal width: Half SPORT A */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_TX_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_TX_A_VALUE 0 /* Transmit Buffer */ +#define BITM_SPORT_TX_A_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Transmit Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_RX_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_RX_A_VALUE 0 /* Receive Buffer */ +#define BITM_SPORT_RX_A_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Receive Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_CTL_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_CTL_B_DMAEN 26 /* DMA Enable */ +#define BITP_SPORT_CTL_B_SPTRAN 25 /* Serial Port Transfer Direction */ +#define BITP_SPORT_CTL_B_GCLKEN 21 /* Gated Clock Enable */ +#define BITP_SPORT_CTL_B_FSERRMODE 20 /* Frame Sync Error Operation */ +#define BITP_SPORT_CTL_B_PACK 18 /* Packing Enable */ +#define BITP_SPORT_CTL_B_LAFS 17 /* Late Frame Sync */ +#define BITP_SPORT_CTL_B_LFS 16 /* Active-Low Frame Sync */ +#define BITP_SPORT_CTL_B_DIFS 15 /* Data-Independent Frame Sync */ +#define BITP_SPORT_CTL_B_IFS 14 /* Internal Frame Sync */ +#define BITP_SPORT_CTL_B_FSR 13 /* Frame Sync Required */ +#define BITP_SPORT_CTL_B_CKRE 12 /* Clock Rising Edge */ +#define BITP_SPORT_CTL_B_OPMODE 11 /* Operation mode */ +#define BITP_SPORT_CTL_B_ICLK 10 /* Internal Clock */ +#define BITP_SPORT_CTL_B_SLEN 4 /* Serial Word Length */ +#define BITP_SPORT_CTL_B_LSBF 3 /* Least-Significant Bit First */ +#define BITP_SPORT_CTL_B_SPEN 0 /* Serial Port Enable */ +#define BITM_SPORT_CTL_B_DMAEN (_ADI_MSK_3(0x04000000,0x04000000UL, uint32_t )) /* DMA Enable */ +#define BITM_SPORT_CTL_B_SPTRAN (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t )) /* Serial Port Transfer Direction */ +#define BITM_SPORT_CTL_B_GCLKEN (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t )) /* Gated Clock Enable */ +#define BITM_SPORT_CTL_B_FSERRMODE (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t )) /* Frame Sync Error Operation */ +#define BITM_SPORT_CTL_B_PACK (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* Packing Enable */ +#define BITM_SPORT_CTL_B_LAFS (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t )) /* Late Frame Sync */ +#define BITM_SPORT_CTL_B_LFS (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* Active-Low Frame Sync */ +#define BITM_SPORT_CTL_B_DIFS (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* Data-Independent Frame Sync */ +#define BITM_SPORT_CTL_B_IFS (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Internal Frame Sync */ +#define BITM_SPORT_CTL_B_FSR (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* Frame Sync Required */ +#define BITM_SPORT_CTL_B_CKRE (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* Clock Rising Edge */ +#define BITM_SPORT_CTL_B_OPMODE (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* Operation mode */ +#define BITM_SPORT_CTL_B_ICLK (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* Internal Clock */ +#define BITM_SPORT_CTL_B_SLEN (_ADI_MSK_3(0x000001F0,0x000001F0UL, uint32_t )) /* Serial Word Length */ +#define BITM_SPORT_CTL_B_LSBF (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Least-Significant Bit First */ +#define BITM_SPORT_CTL_B_SPEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Serial Port Enable */ +#define ENUM_SPORT_CTL_B_CTL_PACK_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* PACK: Disable */ +#define ENUM_SPORT_CTL_B_CTL_PACK_8BIT (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t )) /* PACK: 8-bit packing enable */ +#define ENUM_SPORT_CTL_B_CTL_PACK_16BIT (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t )) /* PACK: 16-bit packing enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_DIV_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_DIV_B_FSDIV 16 /* Frame Sync Divisor */ +#define BITP_SPORT_DIV_B_CLKDIV 0 /* Clock Divisor */ +#define BITM_SPORT_DIV_B_FSDIV (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t )) /* Frame Sync Divisor */ +#define BITM_SPORT_DIV_B_CLKDIV (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t )) /* Clock Divisor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_IEN_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_IEN_B_SYSDATERR 4 /* Data error for system writes or reads */ +#define BITP_SPORT_IEN_B_DATA 3 /* Data request interrupt to the core */ +#define BITP_SPORT_IEN_B_FSERRMSK 2 /* Frame Sync Error (Interrupt) Mask */ +#define BITP_SPORT_IEN_B_DERRMSK 1 /* Data Error (Interrupt) Mask */ +#define BITP_SPORT_IEN_B_TF 0 /* Transmit Finish Interrupt Enable */ +#define BITM_SPORT_IEN_B_SYSDATERR (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Data error for system writes or reads */ +#define BITM_SPORT_IEN_B_DATA (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Data request interrupt to the core */ +#define BITM_SPORT_IEN_B_FSERRMSK (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Frame Sync Error (Interrupt) Mask */ +#define BITM_SPORT_IEN_B_DERRMSK (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Data Error (Interrupt) Mask */ +#define BITM_SPORT_IEN_B_TF (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Transmit Finish Interrupt Enable */ +#define ENUM_SPORT_IEN_B_CTL_TXFIN_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* TF: Transfer Finish Interrupt is disabled */ +#define ENUM_SPORT_IEN_B_CTL_TXFIN_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* TF: Transfer Finish Interrupt is Enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_STAT_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_STAT_B_DXS 8 /* Data Transfer Buffer Status */ +#define BITP_SPORT_STAT_B_SYSDATERR 4 /* System Data Error Status */ +#define BITP_SPORT_STAT_B_DATA 3 /* Data Buffer status */ +#define BITP_SPORT_STAT_B_FSERR 2 /* Frame Sync Error Status */ +#define BITP_SPORT_STAT_B_DERR 1 /* Data Error Status */ +#define BITP_SPORT_STAT_B_TFI 0 /* Transmit Finish Interrupt Status */ +#define BITM_SPORT_STAT_B_DXS (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* Data Transfer Buffer Status */ +#define BITM_SPORT_STAT_B_SYSDATERR (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* System Data Error Status */ +#define BITM_SPORT_STAT_B_DATA (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Data Buffer status */ +#define BITM_SPORT_STAT_B_FSERR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Frame Sync Error Status */ +#define BITM_SPORT_STAT_B_DERR (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Data Error Status */ +#define BITM_SPORT_STAT_B_TFI (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Transmit Finish Interrupt Status */ +#define ENUM_SPORT_STAT_B_CTL_EMPTY (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* DXS: Empty */ +#define ENUM_SPORT_STAT_B_CTL_PART_FULL (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* DXS: Partially full */ +#define ENUM_SPORT_STAT_B_CTL_FULL (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* DXS: Full */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_NUMTRAN_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_NUMTRAN_B_VALUE 0 /* Number of transfers (Half SPORT A) */ +#define BITM_SPORT_NUMTRAN_B_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFUL, uint32_t )) /* Number of transfers (Half SPORT A) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_CNVT_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_CNVT_B_CNVT2FS 16 /* CNV to FS duration: Half SPORT B */ +#define BITP_SPORT_CNVT_B_POL 8 /* Polarity of the CNV signal */ +#define BITP_SPORT_CNVT_B_WID 0 /* CNV signal width: Half SPORT B */ +#define BITM_SPORT_CNVT_B_CNVT2FS (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t )) /* CNV to FS duration: Half SPORT B */ +#define BITM_SPORT_CNVT_B_POL (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* Polarity of the CNV signal */ +#define BITM_SPORT_CNVT_B_WID (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t )) /* CNV signal width: Half SPORT B */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_TX_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_TX_B_VALUE 0 /* Transmit Buffer */ +#define BITM_SPORT_TX_B_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Transmit Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_RX_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_RX_B_VALUE 0 /* Receive Buffer */ +#define BITM_SPORT_RX_B_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Receive Buffer */ + + +/* ============================================================================================================================ + CRC Accelerator + ============================================================================================================================ */ + +/* ============================================================================================================================ + CRC0 + ============================================================================================================================ */ +#define REG_CRC0_CTL 0x40040000 /* CRC0 CRC Control */ +#define REG_CRC0_IPDATA 0x40040004 /* CRC0 Input Data Word */ +#define REG_CRC0_RESULT 0x40040008 /* CRC0 CRC Result */ +#define REG_CRC0_POLY 0x4004000C /* CRC0 Programmable CRC Polynomial */ +#define REG_CRC0_IPBITS0 0x40040010 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS1 0x40040011 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS2 0x40040012 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS3 0x40040013 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS4 0x40040014 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS5 0x40040015 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS6 0x40040016 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS7 0x40040017 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITSn(i) (REG_CRC0_IPBITS0 + ((i) * 1)) +#define REG_CRC0_IPBITSn_COUNT 8 +#define REG_CRC0_IPBYTE 0x40040010 /* CRC0 Input Data Byte */ + +/* ============================================================================================================================ + CRC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + CRC_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRC_CTL_REVID 28 /* Revision ID */ +#define BITP_CRC_CTL_W16SWP 4 /* Word16 Swap */ +#define BITP_CRC_CTL_BYTMIRR 3 /* Byte Mirroring */ +#define BITP_CRC_CTL_BITMIRR 2 /* Bit Mirroring */ +#define BITP_CRC_CTL_LSBFIRST 1 /* LSB First Calculation Order */ +#define BITP_CRC_CTL_EN 0 /* CRC Peripheral Enable */ +#define BITM_CRC_CTL_REVID (_ADI_MSK_3(0xF0000000,0xF0000000UL, uint32_t )) /* Revision ID */ +#define BITM_CRC_CTL_W16SWP (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Word16 Swap */ +#define BITM_CRC_CTL_BYTMIRR (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Byte Mirroring */ +#define BITM_CRC_CTL_BITMIRR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Bit Mirroring */ +#define BITM_CRC_CTL_LSBFIRST (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* LSB First Calculation Order */ +#define BITM_CRC_CTL_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* CRC Peripheral Enable */ +#define ENUM_CRC_CTL_W16SP_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* W16SWP: Word16 Swap disabled */ +#define ENUM_CRC_CTL_W16SP_EN (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* W16SWP: Word16 Swap enabled */ +#define ENUM_CRC_CTL_BYTEMIR_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BYTMIRR: Byte Mirroring is disabled */ +#define ENUM_CRC_CTL_BYTEMIR_EN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* BYTMIRR: Byte Mirroring is enabled */ +#define ENUM_CRC_CTL_BITMIRR_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BITMIRR: Bit Mirroring is disabled */ +#define ENUM_CRC_CTL_BITMIRR_EN (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* BITMIRR: Bit Mirroring is enabled */ +#define ENUM_CRC_CTL_MSB_FIRST (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* LSBFIRST: MSB First CRC calculation is done */ +#define ENUM_CRC_CTL_LSB_FIRST (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* LSBFIRST: LSB First CRC calculation is done */ +#define ENUM_CRC_CTL_CRC_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* EN: CRC peripheral is disabled */ +#define ENUM_CRC_CTL_CRC_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* EN: CRC peripheral is enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRC_IPDATA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRC_IPDATA_VALUE 0 /* Data Input */ +#define BITM_CRC_IPDATA_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Data Input */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRC_RESULT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRC_RESULT_VALUE 0 /* CRC Residue */ +#define BITM_CRC_RESULT_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* CRC Residue */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRC_POLY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRC_POLY_VALUE 0 /* CRC Reduction Polynomial */ +#define BITM_CRC_POLY_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* CRC Reduction Polynomial */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRC_IPBITS[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRC_IPBITS_DATA_BITS 0 /* Input Data Bits */ +#define BITM_CRC_IPBITS_DATA_BITS (_ADI_MSK_3(0x000000FF,0x000000FFU, uint8_t )) /* Input Data Bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRC_IPBYTE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRC_IPBYTE_DATA_BYTE 0 /* Input Data Byte */ +#define BITM_CRC_IPBYTE_DATA_BYTE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint8_t )) /* Input Data Byte */ + + +/* ============================================================================================================================ + Random Number Generator + ============================================================================================================================ */ + +/* ============================================================================================================================ + RNG0 + ============================================================================================================================ */ +#define REG_RNG0_CTL 0x40040400 /* RNG0 RNG Control Register */ +#define REG_RNG0_LEN 0x40040404 /* RNG0 RNG Sample Length Register */ +#define REG_RNG0_STAT 0x40040408 /* RNG0 RNG Status Register */ +#define REG_RNG0_DATA 0x4004040C /* RNG0 RNG Data Register */ +#define REG_RNG0_OSCCNT 0x40040410 /* RNG0 Oscillator Count */ +#define REG_RNG0_OSCDIFF0 0x40040414 /* RNG0 Oscillator Difference */ +#define REG_RNG0_OSCDIFF1 0x40040415 /* RNG0 Oscillator Difference */ +#define REG_RNG0_OSCDIFF2 0x40040416 /* RNG0 Oscillator Difference */ +#define REG_RNG0_OSCDIFF3 0x40040417 /* RNG0 Oscillator Difference */ +#define REG_RNG0_OSCDIFFn(i) (REG_RNG0_OSCDIFF0 + ((i) * 1)) +#define REG_RNG0_OSCDIFFn_COUNT 4 + +/* ============================================================================================================================ + RNG Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + RNG_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RNG_CTL_SINGLE 3 /* Generate a Single Number */ +#define BITP_RNG_CTL_EN 0 /* RNG Enable */ +#define BITM_RNG_CTL_SINGLE (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Generate a Single Number */ +#define BITM_RNG_CTL_EN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* RNG Enable */ +#define ENUM_RNG_CTL_WORD (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SINGLE: Buffer Word */ +#define ENUM_RNG_CTL_SINGLE (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* SINGLE: Single Byte */ +#define ENUM_RNG_CTL_DISABLE (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* EN: Disable the RNG */ +#define ENUM_RNG_CTL_ENABLE (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* EN: Enable the RNG */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RNG_LEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RNG_LEN_PRESCALE 12 /* Prescaler for the Sample Counter */ +#define BITP_RNG_LEN_RELOAD 0 /* Reload Value for the Sample Counter */ +#define BITM_RNG_LEN_PRESCALE (_ADI_MSK_3(0x0000F000,0x0000F000U, uint16_t )) /* Prescaler for the Sample Counter */ +#define BITM_RNG_LEN_RELOAD (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* Reload Value for the Sample Counter */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RNG_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RNG_STAT_STUCK 1 /* Sampled Data Stuck High or Low */ +#define BITP_RNG_STAT_RNRDY 0 /* Random Number Ready */ +#define BITM_RNG_STAT_STUCK (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Sampled Data Stuck High or Low */ +#define BITM_RNG_STAT_RNRDY (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Random Number Ready */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RNG_DATA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RNG_DATA_BUFF 8 /* Buffer for RNG Data */ +#define BITP_RNG_DATA_VALUE 0 /* Value of the CRC Accumulator */ +#define BITM_RNG_DATA_BUFF (_ADI_MSK_3(0xFFFFFF00,0xFFFFFF00UL, uint32_t )) /* Buffer for RNG Data */ +#define BITM_RNG_DATA_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFUL, uint32_t )) /* Value of the CRC Accumulator */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RNG_OSCCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RNG_OSCCNT_VALUE 0 /* Oscillator Count */ +#define BITM_RNG_OSCCNT_VALUE (_ADI_MSK_3(0x0FFFFFFF,0x0FFFFFFFUL, uint32_t )) /* Oscillator Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RNG_OSCDIFF[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RNG_OSCDIFF_DELTA 0 /* Oscillator Count Difference */ +#define BITM_RNG_OSCDIFF_DELTA (_ADI_MSK_3(0x000000FF,0x000000FF, int8_t )) /* Oscillator Count Difference */ + + +/* ============================================================================================================================ + Register Map for the Crypto Block + ============================================================================================================================ */ + +/* ============================================================================================================================ + CRYPT0 + ============================================================================================================================ */ +#define REG_CRYPT0_CFG 0x40044000 /* CRYPT0 Configuration Register */ +#define REG_CRYPT0_DATALEN 0x40044004 /* CRYPT0 Payload Data Length */ +#define REG_CRYPT0_PREFIXLEN 0x40044008 /* CRYPT0 Authentication Data Length */ +#define REG_CRYPT0_INTEN 0x4004400C /* CRYPT0 Interrupt Enable Register */ +#define REG_CRYPT0_STAT 0x40044010 /* CRYPT0 Status Register */ +#define REG_CRYPT0_INBUF 0x40044014 /* CRYPT0 Input Buffer */ +#define REG_CRYPT0_OUTBUF 0x40044018 /* CRYPT0 Output Buffer */ +#define REG_CRYPT0_NONCE0 0x4004401C /* CRYPT0 Nonce Bits [31:0] */ +#define REG_CRYPT0_NONCE1 0x40044020 /* CRYPT0 Nonce Bits [63:32] */ +#define REG_CRYPT0_NONCE2 0x40044024 /* CRYPT0 Nonce Bits [95:64] */ +#define REG_CRYPT0_NONCE3 0x40044028 /* CRYPT0 Nonce Bits [127:96] */ +#define REG_CRYPT0_AESKEY0 0x4004402C /* CRYPT0 AES Key Bits [31:0] */ +#define REG_CRYPT0_AESKEY1 0x40044030 /* CRYPT0 AES Key Bits [63:32] */ +#define REG_CRYPT0_AESKEY2 0x40044034 /* CRYPT0 AES Key Bits [95:64] */ +#define REG_CRYPT0_AESKEY3 0x40044038 /* CRYPT0 AES Key Bits [127:96] */ +#define REG_CRYPT0_AESKEY4 0x4004403C /* CRYPT0 AES Key Bits [159:128] */ +#define REG_CRYPT0_AESKEY5 0x40044040 /* CRYPT0 AES Key Bits [191:160] */ +#define REG_CRYPT0_AESKEY6 0x40044044 /* CRYPT0 AES Key Bits [223:192] */ +#define REG_CRYPT0_AESKEY7 0x40044048 /* CRYPT0 AES Key Bits [255:224] */ +#define REG_CRYPT0_CNTRINIT 0x4004404C /* CRYPT0 Counter Initialization Vector */ +#define REG_CRYPT0_SHAH0 0x40044050 /* CRYPT0 SHA Bits [31:0] */ +#define REG_CRYPT0_SHAH1 0x40044054 /* CRYPT0 SHA Bits [63:32] */ +#define REG_CRYPT0_SHAH2 0x40044058 /* CRYPT0 SHA Bits [95:64] */ +#define REG_CRYPT0_SHAH3 0x4004405C /* CRYPT0 SHA Bits [127:96] */ +#define REG_CRYPT0_SHAH4 0x40044060 /* CRYPT0 SHA Bits [159:128] */ +#define REG_CRYPT0_SHAH5 0x40044064 /* CRYPT0 SHA Bits [191:160] */ +#define REG_CRYPT0_SHAH6 0x40044068 /* CRYPT0 SHA Bits [223:192] */ +#define REG_CRYPT0_SHAH7 0x4004406C /* CRYPT0 SHA Bits [255:224] */ +#define REG_CRYPT0_SHA_LAST_WORD 0x40044070 /* CRYPT0 SHA Last Word and Valid Bits Information */ +#define REG_CRYPT0_CCM_NUM_VALID_BYTES 0x40044074 /* CRYPT0 NUM_VALID_BYTES */ +#define REG_CRYPT0_PRKSTORCFG 0x40044078 /* CRYPT0 PRKSTOR Configuration */ +#define REG_CRYPT0_KUW0 0x40044080 /* CRYPT0 Key Wrap Unwrap Register 0 */ +#define REG_CRYPT0_KUW1 0x40044084 /* CRYPT0 Key Wrap Unwrap Register 1 */ +#define REG_CRYPT0_KUW2 0x40044088 /* CRYPT0 Key Wrap Unwrap Register 2 */ +#define REG_CRYPT0_KUW3 0x4004408C /* CRYPT0 Key Wrap Unwrap Register 3 */ +#define REG_CRYPT0_KUW4 0x40044090 /* CRYPT0 Key Wrap Unwrap Register 4 */ +#define REG_CRYPT0_KUW5 0x40044094 /* CRYPT0 Key Wrap Unwrap Register 5 */ +#define REG_CRYPT0_KUW6 0x40044098 /* CRYPT0 Key Wrap Unwrap Register 6 */ +#define REG_CRYPT0_KUW7 0x4004409C /* CRYPT0 Key Wrap Unwrap Register 7 */ +#define REG_CRYPT0_KUW8 0x400440A0 /* CRYPT0 Key Wrap Unwrap Register 8 */ +#define REG_CRYPT0_KUW9 0x400440A4 /* CRYPT0 Key Wrap Unwrap Register 9 */ +#define REG_CRYPT0_KUW10 0x400440A8 /* CRYPT0 Key Wrap Unwrap Register 10 */ +#define REG_CRYPT0_KUW11 0x400440AC /* CRYPT0 Key Wrap Unwrap Register 11 */ +#define REG_CRYPT0_KUW12 0x400440B0 /* CRYPT0 Key Wrap Unwrap Register 12 */ +#define REG_CRYPT0_KUW13 0x400440B4 /* CRYPT0 Key Wrap Unwrap Register 13 */ +#define REG_CRYPT0_KUW14 0x400440B8 /* CRYPT0 Key Wrap Unwrap Register 14 */ +#define REG_CRYPT0_KUW15 0x400440BC /* CRYPT0 Key Wrap Unwrap Register 15 */ +#define REG_CRYPT0_KUWVALSTR1 0x400440C0 /* CRYPT0 Key Wrap Unwrap Validation String [63:32] */ +#define REG_CRYPT0_KUWVALSTR2 0x400440C4 /* CRYPT0 Key Wrap Unwrap Validation String [31:0] */ + +/* ============================================================================================================================ + CRYPT Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_CFG_REVID 28 /* Rev ID for Crypto */ +#define BITP_CRYPT_CFG_SHAINIT 26 /* Restarts SHA Computation */ +#define BITP_CRYPT_CFG_SHA256EN 25 /* Enable SHA-256 Operation */ +#define BITP_CRYPT_CFG_HMACEN 21 /* HMAC Enable */ +#define BITP_CRYPT_CFG_CMACEN 20 /* Enable CMAC Mode Operation */ +#define BITP_CRYPT_CFG_CCMEN 19 /* Enable CCM/CCM* Mode Operation */ +#define BITP_CRYPT_CFG_CBCEN 18 /* Enable CBC Mode Operation */ +#define BITP_CRYPT_CFG_CTREN 17 /* Enable CTR Mode Operation */ +#define BITP_CRYPT_CFG_ECBEN 16 /* Enable ECB Mode Operation */ +#define BITP_CRYPT_CFG_PRKSTOREN 15 /* Enable PRKSTOR Commands */ +#define BITP_CRYPT_CFG_KEY_BYTESWAP 14 /* Use Key Unwrap Before HMAC */ +#define BITP_CRYPT_CFG_SHA_BYTESWAP 13 /* Enable Key Wrap */ +#define BITP_CRYPT_CFG_AES_BYTESWAP 12 /* Byteswap for AES Input */ +#define BITP_CRYPT_CFG_KUWKEYLEN 10 /* Key Length Key Wrap Unwrap */ +#define BITP_CRYPT_CFG_AESKEYLEN 8 /* Select Key Length for AES Cipher */ +#define BITP_CRYPT_CFG_OUTFLUSH 5 /* Output Buffer Flush */ +#define BITP_CRYPT_CFG_INFLUSH 4 /* Input Buffer Flush */ +#define BITP_CRYPT_CFG_OUTDMAEN 3 /* Enable DMA Channel Request for Output Buffer */ +#define BITP_CRYPT_CFG_INDMAEN 2 /* Enable DMA Channel Request for Input Buffer */ +#define BITP_CRYPT_CFG_ENCR 1 /* Encrypt or Decrypt */ +#define BITP_CRYPT_CFG_BLKEN 0 /* Enable Bit for Crypto Block */ +#define BITM_CRYPT_CFG_REVID (_ADI_MSK_3(0xF0000000,0xF0000000UL, uint32_t )) /* Rev ID for Crypto */ +#define BITM_CRYPT_CFG_SHAINIT (_ADI_MSK_3(0x04000000,0x04000000UL, uint32_t )) /* Restarts SHA Computation */ +#define BITM_CRYPT_CFG_SHA256EN (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t )) /* Enable SHA-256 Operation */ +#define BITM_CRYPT_CFG_HMACEN (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t )) /* HMAC Enable */ +#define BITM_CRYPT_CFG_CMACEN (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t )) /* Enable CMAC Mode Operation */ +#define BITM_CRYPT_CFG_CCMEN (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t )) /* Enable CCM/CCM* Mode Operation */ +#define BITM_CRYPT_CFG_CBCEN (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t )) /* Enable CBC Mode Operation */ +#define BITM_CRYPT_CFG_CTREN (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t )) /* Enable CTR Mode Operation */ +#define BITM_CRYPT_CFG_ECBEN (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* Enable ECB Mode Operation */ +#define BITM_CRYPT_CFG_PRKSTOREN (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* Enable PRKSTOR Commands */ +#define BITM_CRYPT_CFG_KEY_BYTESWAP (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Use Key Unwrap Before HMAC */ +#define BITM_CRYPT_CFG_SHA_BYTESWAP (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* Enable Key Wrap */ +#define BITM_CRYPT_CFG_AES_BYTESWAP (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* Byteswap for AES Input */ +#define BITM_CRYPT_CFG_KUWKEYLEN (_ADI_MSK_3(0x00000C00,0x00000C00UL, uint32_t )) /* Key Length Key Wrap Unwrap */ +#define BITM_CRYPT_CFG_AESKEYLEN (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* Select Key Length for AES Cipher */ +#define BITM_CRYPT_CFG_OUTFLUSH (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* Output Buffer Flush */ +#define BITM_CRYPT_CFG_INFLUSH (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Input Buffer Flush */ +#define BITM_CRYPT_CFG_OUTDMAEN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Enable DMA Channel Request for Output Buffer */ +#define BITM_CRYPT_CFG_INDMAEN (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Enable DMA Channel Request for Input Buffer */ +#define BITM_CRYPT_CFG_ENCR (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Encrypt or Decrypt */ +#define BITM_CRYPT_CFG_BLKEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable Bit for Crypto Block */ +#define ENUM_CRYPT_CFG_LEN128 (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* KUWKeyLen: The key size of KUW key is 128 bits */ +#define ENUM_CRYPT_CFG_LEN256 (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* KUWKeyLen: The key size of KUW key is 256 bits */ +#define ENUM_CRYPT_CFG_LEN512 (_ADI_MSK_3(0x00000C00,0x00000C00UL, uint32_t )) /* KUWKeyLen: The key size of KUW key is 512 bits */ +#define ENUM_CRYPT_CFG_AESKEYLEN128 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* AESKEYLEN: Uses 128-bit long key */ +#define ENUM_CRYPT_CFG_AESKEYLEN256 (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* AESKEYLEN: Uses 256-bit long key */ +#define ENUM_CRYPT_CFG_DMA_DISABLE_OUTBUF (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* OUTDMAEN: Disable DMA Requesting for Output Buffer */ +#define ENUM_CRYPT_CFG_DMA_ENABLE_OUTBUF (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* OUTDMAEN: Enable DMA Requesting for Output Buffer */ +#define ENUM_CRYPT_CFG_DMA_DISABLE_INBUF (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* INDMAEN: Disable DMA Requesting for Input Buffer */ +#define ENUM_CRYPT_CFG_DMA_ENABLE_INBUF (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* INDMAEN: Enable DMA Requesting for Input Buffer */ +#define ENUM_CRYPT_CFG_ENABLE (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BLKEN: Enable Crypto Block */ +#define ENUM_CRYPT_CFG_DISABLE (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* BLKEN: Disable Crypto Block */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_DATALEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_DATALEN_VALUE 0 /* Length of Payload Data */ +#define BITM_CRYPT_DATALEN_VALUE (_ADI_MSK_3(0x000FFFFF,0x000FFFFFUL, uint32_t )) /* Length of Payload Data */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_PREFIXLEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_PREFIXLEN_VALUE 0 /* Length of Associated Data */ +#define BITM_CRYPT_PREFIXLEN_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t )) /* Length of Associated Data */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_INTEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_INTEN_PRKSTRCMDONEEN 8 /* PRKSTOR CMD DONE INTEN */ +#define BITP_CRYPT_INTEN_HMACMSGRDYEN 7 /* Status Bit for HMAC Message Input Ready */ +#define BITP_CRYPT_INTEN_HMACDONEEN 6 /* Interrupt Enable for HMAC Done */ +#define BITP_CRYPT_INTEN_SHADONEN 5 /* Enable SHA_Done Interrupt */ +#define BITP_CRYPT_INTEN_INOVREN 2 /* Enable Input Overflow Interrupt */ +#define BITP_CRYPT_INTEN_OUTRDYEN 1 /* Enables the Output Ready Interrupt */ +#define BITP_CRYPT_INTEN_INRDYEN 0 /* Enable Input Ready Interrupt */ +#define BITM_CRYPT_INTEN_PRKSTRCMDONEEN (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* PRKSTOR CMD DONE INTEN */ +#define BITM_CRYPT_INTEN_HMACMSGRDYEN (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* Status Bit for HMAC Message Input Ready */ +#define BITM_CRYPT_INTEN_HMACDONEEN (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* Interrupt Enable for HMAC Done */ +#define BITM_CRYPT_INTEN_SHADONEN (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* Enable SHA_Done Interrupt */ +#define BITM_CRYPT_INTEN_INOVREN (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Enable Input Overflow Interrupt */ +#define BITM_CRYPT_INTEN_OUTRDYEN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Enables the Output Ready Interrupt */ +#define BITM_CRYPT_INTEN_INRDYEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable Input Ready Interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_STAT_PRKSTOR_BUSY 31 /* Indicates PrKSTOR is Busy */ +#define BITP_CRYPT_STAT_CMD_ISSUED 27 /* Last Command Issued to PrKStor; */ +#define BITP_CRYPT_STAT_PRKSTOR_RET_STATUS 25 /* ECC Errors in the PRKSTOR_RETRIEVE Command */ +#define BITP_CRYPT_STAT_PRKSTOR_CMD_FAIL 24 /* Indicates Last Command Issued Failed */ +#define BITP_CRYPT_STAT_PRKSTOR_CMD_DONE 23 /* Indicates Command Done for PrKStor */ +#define BITP_CRYPT_STAT_HMACMSGRDY 15 /* Status Bit Indicates HMAC is Message Ready */ +#define BITP_CRYPT_STAT_HMACDONE 14 /* Status Bit Indicates HMAC Done */ +#define BITP_CRYPT_STAT_HMACBUSY 13 /* Status Bit Indicates HMAC Busy */ +#define BITP_CRYPT_STAT_OUTWORDS 10 /* Number of Words in the Output Buffer */ +#define BITP_CRYPT_STAT_INWORDS 7 /* Number of Words in the Input Buffer */ +#define BITP_CRYPT_STAT_SHABUSY 6 /* SHA Busy. in Computation */ +#define BITP_CRYPT_STAT_SHADONE 5 /* SHA Computation Complete */ +#define BITP_CRYPT_STAT_INOVR 2 /* Overflow in the Input Buffer */ +#define BITP_CRYPT_STAT_OUTRDY 1 /* Output Data Ready */ +#define BITP_CRYPT_STAT_INRDY 0 /* Input Buffer Status */ +#define BITM_CRYPT_STAT_PRKSTOR_BUSY (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t )) /* Indicates PrKSTOR is Busy */ +#define BITM_CRYPT_STAT_CMD_ISSUED (_ADI_MSK_3(0x78000000,0x78000000UL, uint32_t )) /* Last Command Issued to PrKStor; */ +#define BITM_CRYPT_STAT_PRKSTOR_RET_STATUS (_ADI_MSK_3(0x06000000,0x06000000UL, uint32_t )) /* ECC Errors in the PRKSTOR_RETRIEVE Command */ +#define BITM_CRYPT_STAT_PRKSTOR_CMD_FAIL (_ADI_MSK_3(0x01000000,0x01000000UL, uint32_t )) /* Indicates Last Command Issued Failed */ +#define BITM_CRYPT_STAT_PRKSTOR_CMD_DONE (_ADI_MSK_3(0x00800000,0x00800000UL, uint32_t )) /* Indicates Command Done for PrKStor */ +#define BITM_CRYPT_STAT_HMACMSGRDY (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* Status Bit Indicates HMAC is Message Ready */ +#define BITM_CRYPT_STAT_HMACDONE (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Status Bit Indicates HMAC Done */ +#define BITM_CRYPT_STAT_HMACBUSY (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* Status Bit Indicates HMAC Busy */ +#define BITM_CRYPT_STAT_OUTWORDS (_ADI_MSK_3(0x00001C00,0x00001C00UL, uint32_t )) /* Number of Words in the Output Buffer */ +#define BITM_CRYPT_STAT_INWORDS (_ADI_MSK_3(0x00000380,0x00000380UL, uint32_t )) /* Number of Words in the Input Buffer */ +#define BITM_CRYPT_STAT_SHABUSY (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* SHA Busy. in Computation */ +#define BITM_CRYPT_STAT_SHADONE (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* SHA Computation Complete */ +#define BITM_CRYPT_STAT_INOVR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Overflow in the Input Buffer */ +#define BITM_CRYPT_STAT_OUTRDY (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Output Data Ready */ +#define BITM_CRYPT_STAT_INRDY (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Input Buffer Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_INBUF Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_INBUF_VALUE 0 /* Input Buffer */ +#define BITM_CRYPT_INBUF_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Input Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_OUTBUF Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_OUTBUF_VALUE 0 /* Output Buffer */ +#define BITM_CRYPT_OUTBUF_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Output Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_NONCE0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_NONCE0_VALUE 0 /* Word 0: Nonce Bits [31:0] */ +#define BITM_CRYPT_NONCE0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 0: Nonce Bits [31:0] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_NONCE1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_NONCE1_VALUE 0 /* Word 1: Nonce Bits [63:32] */ +#define BITM_CRYPT_NONCE1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 1: Nonce Bits [63:32] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_NONCE2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_NONCE2_VALUE 0 /* Word 2: Nonce Bits [95:64] */ +#define BITM_CRYPT_NONCE2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 2: Nonce Bits [95:64] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_NONCE3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_NONCE3_VALUE 0 /* Word 3: Nonce Bits [127:96] */ +#define BITM_CRYPT_NONCE3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 3: Nonce Bits [127:96] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY0_VALUE 0 /* Key: Bytes [3:0] */ +#define BITM_CRYPT_AESKEY0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [3:0] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY1_VALUE 0 /* Key: Bytes [7:4] */ +#define BITM_CRYPT_AESKEY1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [7:4] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY2_VALUE 0 /* Key: Bytes [11:8] */ +#define BITM_CRYPT_AESKEY2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [11:8] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY3_VALUE 0 /* Key: Bytes [15:12] */ +#define BITM_CRYPT_AESKEY3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [15:12] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY4_VALUE 0 /* Key: Bytes [19:16] */ +#define BITM_CRYPT_AESKEY4_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [19:16] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY5_VALUE 0 /* Key: Bytes [23:20] */ +#define BITM_CRYPT_AESKEY5_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [23:20] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY6 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY6_VALUE 0 /* Key: Bytes [27:24] */ +#define BITM_CRYPT_AESKEY6_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [27:24] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY7 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY7_VALUE 0 /* Key: Bytes [31:28] */ +#define BITM_CRYPT_AESKEY7_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [31:28] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_CNTRINIT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_CNTRINIT_VALUE 0 /* Counter Initialization Value */ +#define BITM_CRYPT_CNTRINIT_VALUE (_ADI_MSK_3(0x000FFFFF,0x000FFFFFUL, uint32_t )) /* Counter Initialization Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH0_SHAHASH0 0 /* Word 0: SHA Hash */ +#define BITM_CRYPT_SHAH0_SHAHASH0 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 0: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH1_SHAHASH1 0 /* Word 1: SHA Hash */ +#define BITM_CRYPT_SHAH1_SHAHASH1 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 1: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH2_SHAHASH2 0 /* Word 2: SHA Hash */ +#define BITM_CRYPT_SHAH2_SHAHASH2 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 2: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH3_SHAHASH3 0 /* Word 3: SHA Hash */ +#define BITM_CRYPT_SHAH3_SHAHASH3 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 3: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH4_SHAHASH4 0 /* Word 4: SHA Hash */ +#define BITM_CRYPT_SHAH4_SHAHASH4 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 4: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH5_SHAHASH5 0 /* Word 5: SHA Hash */ +#define BITM_CRYPT_SHAH5_SHAHASH5 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 5: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH6 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH6_SHAHASH6 0 /* Word 6: SHA Hash */ +#define BITM_CRYPT_SHAH6_SHAHASH6 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 6: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH7 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH7_SHAHASH7 0 /* Word 7: SHA Hash */ +#define BITM_CRYPT_SHAH7_SHAHASH7 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 7: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHA_LAST_WORD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHA_LAST_WORD_O_BITS_VALID 1 /* Bits Valid in SHA Last Word Input */ +#define BITP_CRYPT_SHA_LAST_WORD_O_LAST_WORD 0 /* Last SHA Input Word */ +#define BITM_CRYPT_SHA_LAST_WORD_O_BITS_VALID (_ADI_MSK_3(0x0000003E,0x0000003EUL, uint32_t )) /* Bits Valid in SHA Last Word Input */ +#define BITM_CRYPT_SHA_LAST_WORD_O_LAST_WORD (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Last SHA Input Word */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_CCM_NUM_VALID_BYTES Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_CCM_NUM_VALID_BYTES_NUM_VALID_BYTES 0 /* Number of Valid Bytes in CCM Last Data */ +#define BITM_CRYPT_CCM_NUM_VALID_BYTES_NUM_VALID_BYTES (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t )) /* Number of Valid Bytes in CCM Last Data */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_PRKSTORCFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_PRKSTORCFG_CMD 7 /* Command Input for PRKSTOR */ +#define BITP_CRYPT_PRKSTORCFG_KEY_INDEX 0 /* Index of Key in PRKSTOR */ +#define BITM_CRYPT_PRKSTORCFG_CMD (_ADI_MSK_3(0x00000780,0x00000780UL, uint32_t )) /* Command Input for PRKSTOR */ +#define BITM_CRYPT_PRKSTORCFG_KEY_INDEX (_ADI_MSK_3(0x0000007F,0x0000007FUL, uint32_t )) /* Index of Key in PRKSTOR */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW0_KUW0 0 /* KUW [31:0] */ +#define BITM_CRYPT_KUW0_KUW0 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [31:0] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW1_KUW1 0 /* KUW [63:32] */ +#define BITM_CRYPT_KUW1_KUW1 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [63:32] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW2_KUW2 0 /* KUW [95:64] */ +#define BITM_CRYPT_KUW2_KUW2 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [95:64] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW3_KUW3 0 /* KUW [127:96] */ +#define BITM_CRYPT_KUW3_KUW3 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [127:96] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW4_KUW4 0 /* KUW [159:128] */ +#define BITM_CRYPT_KUW4_KUW4 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [159:128] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW5_KUW5 0 /* KUW [191:160] */ +#define BITM_CRYPT_KUW5_KUW5 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [191:160] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW6 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW6_KUW6 0 /* KUW [223:192] */ +#define BITM_CRYPT_KUW6_KUW6 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [223:192] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW7 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW7_KUW7 0 /* KUW [255:224] */ +#define BITM_CRYPT_KUW7_KUW7 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [255:224] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW8 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW8_KUW8 0 /* KUW [287:256] */ +#define BITM_CRYPT_KUW8_KUW8 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [287:256] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW9 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW9_KUW9 0 /* KUW [319:288] */ +#define BITM_CRYPT_KUW9_KUW9 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [319:288] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW10 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW10_KUW10 0 /* KUW [351:320] */ +#define BITM_CRYPT_KUW10_KUW10 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [351:320] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW11 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW11_KUW11 0 /* KUW [383:352] */ +#define BITM_CRYPT_KUW11_KUW11 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [383:352] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW12 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW12_KUW12 0 /* KUW [415:384] */ +#define BITM_CRYPT_KUW12_KUW12 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [415:384] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW13 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW13_KUW13 0 /* KUW [447:416] */ +#define BITM_CRYPT_KUW13_KUW13 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [447:416] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW14 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW14_KUW14 0 /* KUW [479:448] */ +#define BITM_CRYPT_KUW14_KUW14 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [479:448] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW15 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW15_KUW15 0 /* KUW [511:480] */ +#define BITM_CRYPT_KUW15_KUW15 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [511:480] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUWVALSTR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUWVALSTR1_INITALVALUE0 0 /* Initial Value */ +#define BITM_CRYPT_KUWVALSTR1_INITALVALUE0 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Initial Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUWVALSTR2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUWVALSTR2_INITIALVALUE1 0 /* Initial Value */ +#define BITM_CRYPT_KUWVALSTR2_INITIALVALUE1 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Initial Value */ + + +/* ============================================================================================================================ + Power Management Registers + ============================================================================================================================ */ + +/* ============================================================================================================================ + PMG0 + ============================================================================================================================ */ +#define REG_PMG0_IEN 0x4004C000 /* PMG0 Power Supply Monitor Interrupt Enable */ +#define REG_PMG0_PSM_STAT 0x4004C004 /* PMG0 Power Supply Monitor Status */ +#define REG_PMG0_PWRMOD 0x4004C008 /* PMG0 Power Mode Register */ +#define REG_PMG0_PWRKEY 0x4004C00C /* PMG0 Key Protection for PWRMOD and SRAMRET */ +#define REG_PMG0_SHDN_STAT 0x4004C010 /* PMG0 Shutdown Status Register */ +#define REG_PMG0_SRAMRET 0x4004C014 /* PMG0 Control for Retention SRAM in Hibernate Mode */ +#define REG_PMG0_TRIM 0x4004C038 /* PMG0 Trimming Bits */ +#define REG_PMG0_RST_STAT 0x4004C040 /* PMG0 Reset Status */ +#define REG_PMG0_CTL1 0x4004C044 /* PMG0 HPBUCK Control */ + +/* ============================================================================================================================ + PMG Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_IEN_IENBAT 10 /* Interrupt enable for VBAT range */ +#define BITP_PMG_IEN_RANGEBAT 8 /* Battery Monitor Range */ +#define BITP_PMG_IEN_VREGOVR 2 /* Enable Interrupt when VREG over-voltage (above 1.32 V) */ +#define BITP_PMG_IEN_VREGUNDR 1 /* Enable Interrupt when VREG under-voltage (below 1 V) */ +#define BITP_PMG_IEN_VBAT 0 /* Enable Interrupt for VBAT */ +#define BITM_PMG_IEN_IENBAT (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* Interrupt enable for VBAT range */ +#define BITM_PMG_IEN_RANGEBAT (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* Battery Monitor Range */ +#define BITM_PMG_IEN_VREGOVR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Enable Interrupt when VREG over-voltage (above 1.32 V) */ +#define BITM_PMG_IEN_VREGUNDR (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Enable Interrupt when VREG under-voltage (below 1 V) */ +#define BITM_PMG_IEN_VBAT (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable Interrupt for VBAT */ +#define ENUM_PMG_IEN_REGION1 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* RANGEBAT: Configure to generate interrupt if VBAT in Region1 */ +#define ENUM_PMG_IEN_REGION2 (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* RANGEBAT: Configure to generate interrupt if VBAT in Region2 */ +#define ENUM_PMG_IEN_REGION3 (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* RANGEBAT: Configure to generate interrupt if VBAT in Region3 */ +#define ENUM_PMG_IEN_NA (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* RANGEBAT: NA */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_PSM_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_PSM_STAT_RORANGE3 15 /* VBAT range3 */ +#define BITP_PMG_PSM_STAT_RORANGE2 14 /* VBAT range2 */ +#define BITP_PMG_PSM_STAT_RORANGE1 13 /* VBAT range1 */ +#define BITP_PMG_PSM_STAT_RANGE3 10 /* VBAT range3 */ +#define BITP_PMG_PSM_STAT_RANGE2 9 /* VBAT range2 */ +#define BITP_PMG_PSM_STAT_RANGE1 8 /* VBAT range1 */ +#define BITP_PMG_PSM_STAT_WICENACK 7 /* WIC Enable Acknowledge from Cortex */ +#define BITP_PMG_PSM_STAT_VREGOVR 2 /* Status bit for alarm indicating Over Voltage for VREG */ +#define BITP_PMG_PSM_STAT_VREGUNDR 1 /* Status bit for Alarm indicating VREG is below 1 V */ +#define BITP_PMG_PSM_STAT_VBATUNDR 0 /* Status bit indicating an Alarm that battery is below 1.8 V */ +#define BITM_PMG_PSM_STAT_RORANGE3 (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* VBAT range3 */ +#define BITM_PMG_PSM_STAT_RORANGE2 (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* VBAT range2 */ +#define BITM_PMG_PSM_STAT_RORANGE1 (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* VBAT range1 */ +#define BITM_PMG_PSM_STAT_RANGE3 (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* VBAT range3 */ +#define BITM_PMG_PSM_STAT_RANGE2 (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* VBAT range2 */ +#define BITM_PMG_PSM_STAT_RANGE1 (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* VBAT range1 */ +#define BITM_PMG_PSM_STAT_WICENACK (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* WIC Enable Acknowledge from Cortex */ +#define BITM_PMG_PSM_STAT_VREGOVR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Status bit for alarm indicating Over Voltage for VREG */ +#define BITM_PMG_PSM_STAT_VREGUNDR (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Status bit for Alarm indicating VREG is below 1 V */ +#define BITM_PMG_PSM_STAT_VBATUNDR (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Status bit indicating an Alarm that battery is below 1.8 V */ +#define ENUM_PMG_PSM_STAT_BATSTAT1 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* RORANGE1: VBAT NOT in the range specified */ +#define ENUM_PMG_PSM_STAT_BATSTAT0 (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* RORANGE1: VBAT in the range specified */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_PWRMOD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_PWRMOD_MONVBATN 3 /* Monitor VBAT during Hibernate Mode. Monitors VBAT by default */ +#define BITP_PMG_PWRMOD_MODE 0 /* Power Mode Bits */ +#define BITM_PMG_PWRMOD_MONVBATN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Monitor VBAT during Hibernate Mode. Monitors VBAT by default */ +#define BITM_PMG_PWRMOD_MODE (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* Power Mode Bits */ +#define ENUM_PMG_PWRMOD_FLEXI (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* MODE: Flexi Mode */ +#define ENUM_PMG_PWRMOD_HIBERNATE (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* MODE: Hibernate Mode */ +#define ENUM_PMG_PWRMOD_SHUTDOWN (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* MODE: Shutdown Mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_PWRKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_PWRKEY_VALUE 0 /* Power Control Key */ +#define BITM_PMG_PWRKEY_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t )) /* Power Control Key */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_SHDN_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_SHDN_STAT_RTC 3 /* Interrupt from RTC */ +#define BITP_PMG_SHDN_STAT_EXTINT2 2 /* Interrupt from External Interrupt 2 */ +#define BITP_PMG_SHDN_STAT_EXTINT1 1 /* Interrupt from External Interrupt 1 */ +#define BITP_PMG_SHDN_STAT_EXTINT0 0 /* Interrupt from External Interrupt 0 */ +#define BITM_PMG_SHDN_STAT_RTC (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Interrupt from RTC */ +#define BITM_PMG_SHDN_STAT_EXTINT2 (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Interrupt from External Interrupt 2 */ +#define BITM_PMG_SHDN_STAT_EXTINT1 (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Interrupt from External Interrupt 1 */ +#define BITM_PMG_SHDN_STAT_EXTINT0 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Interrupt from External Interrupt 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_SRAMRET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_SRAMRET_HIBERNATE_SRAM_LOAD_MODE 23 /* Hibernate mode SRAM load mode control */ +#define BITP_PMG_SRAMRET_RET4 9 /* Enable retention bank 6 and bank 7 (32 KB) */ +#define BITP_PMG_SRAMRET_RET3 8 /* Enable retention bank 5 (32 KB) */ +#define BITP_PMG_SRAMRET_RET2 1 /* Enable retention bank 3 and bank 4 (32 KB) */ +#define BITP_PMG_SRAMRET_RET1 0 /* Enable retention bank 1 (12 KB) */ +#define BITM_PMG_SRAMRET_HIBERNATE_SRAM_LOAD_MODE (_ADI_MSK_3(0x00800000,0x00800000UL, uint32_t )) /* Hibernate mode SRAM load mode control */ +#define BITM_PMG_SRAMRET_RET4 (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* Enable retention bank 6 and bank 7 (32 KB) */ +#define BITM_PMG_SRAMRET_RET3 (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* Enable retention bank 5 (32 KB) */ +#define BITM_PMG_SRAMRET_RET2 (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Enable retention bank 3 and bank 4 (32 KB) */ +#define BITM_PMG_SRAMRET_RET1 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable retention bank 1 (12 KB) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TRIM Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TRIM_HIBERNATE_LOAD_MODE 29 /* Hibernate mode load mode control */ +#define BITM_PMG_TRIM_HIBERNATE_LOAD_MODE (_ADI_MSK_3(0xE0000000,0xE0000000UL, uint32_t )) /* Hibernate mode load mode control */ +#define ENUM_PMG_TRIM_HIGH_LOAD (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* hibernate_load_mode: High hibernate load */ +#define ENUM_PMG_TRIM_LOW_LOAD (_ADI_MSK_3(0xE0000000,0xE0000000UL, uint32_t )) /* hibernate_load_mode: Low hibernate load */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_RST_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_RST_STAT_PORSRC 4 /* Power on reset Source */ +#define BITP_PMG_RST_STAT_SWRST 3 /* Software reset */ +#define BITP_PMG_RST_STAT_WDRST 2 /* Watchdog timeout */ +#define BITP_PMG_RST_STAT_EXTRST 1 /* External reset */ +#define BITP_PMG_RST_STAT_POR 0 /* Power-on reset */ +#define BITM_PMG_RST_STAT_PORSRC (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* Power on reset Source */ +#define BITM_PMG_RST_STAT_SWRST (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Software reset */ +#define BITM_PMG_RST_STAT_WDRST (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Watchdog timeout */ +#define BITM_PMG_RST_STAT_EXTRST (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* External reset */ +#define BITM_PMG_RST_STAT_POR (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Power-on reset */ +#define ENUM_PMG_RST_STAT_FAILSAFE_HV (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* PORSRC: POR triggered because VBAT drops below Fail Safe */ +#define ENUM_PMG_RST_STAT_RST_VBAT (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* PORSRC: POR trigger because VBAT supply (VBAT < 1.7 V) */ +#define ENUM_PMG_RST_STAT_RST_VREG (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* PORSRC: POR triggered because VDD supply (VDD < 1.08 V) */ +#define ENUM_PMG_RST_STAT_FAILSAFE_LV (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* PORSRC: POR triggered because VREG drops below Fail Safe */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_CTL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_CTL1_HPBUCK_LOWPWR_MODE 2 /* HP Buck low power mode */ +#define BITP_PMG_CTL1_HPBUCK_LD_MODE 1 /* HP Buck load mode */ +#define BITP_PMG_CTL1_HPBUCKEN 0 /* Enable HP Buck */ +#define BITM_PMG_CTL1_HPBUCK_LOWPWR_MODE (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* HP Buck low power mode */ +#define BITM_PMG_CTL1_HPBUCK_LD_MODE (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* HP Buck load mode */ +#define BITM_PMG_CTL1_HPBUCKEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable HP Buck */ +#define ENUM_PMG_CTL1_LOWPWRDISABLE (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* HPBUCK_LOWPWR_MODE: HPBUCK Low power mode is disabled */ +#define ENUM_PMG_CTL1_LOWPWRENABLE (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* HPBUCK_LOWPWR_MODE: HPBUCK Low power mode is enabled */ +#define ENUM_PMG_CTL1_HPBUCKLOWLOAD (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* HPBUCK_LD_MODE: HPBUCK Low load mode is enabled */ +#define ENUM_PMG_CTL1_HPBUCKHIGHLOAD (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* HPBUCK_LD_MODE: HPBUCK High load mode is enabled */ + + +/* ============================================================================================================================ + External interrupt configuration + ============================================================================================================================ */ + +/* ============================================================================================================================ + XINT0 + ============================================================================================================================ */ +#define REG_XINT0_CFG0 0x4004C080 /* XINT0 External Interrupt configuration */ +#define REG_XINT0_EXT_STAT 0x4004C084 /* XINT0 External Wakeup Interrupt Status register */ +#define REG_XINT0_CLR 0x4004C090 /* XINT0 External Interrupt clear */ +#define REG_XINT0_NMICLR 0x4004C094 /* XINT0 Non-maskable interrupt clear */ + +/* ============================================================================================================================ + XINT Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + XINT_CFG0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_XINT_CFG0_UART_RX_MDE 21 /* External Interrupt using UART_RX wakeup Mode registers */ +#define BITP_XINT_CFG0_UART_RX_EN 20 /* External Interrupt using SIP_UPDATE enable bit */ +#define BITP_XINT_CFG0_IRQ3EN 15 /* External Interrupt 3 enable bit */ +#define BITP_XINT_CFG0_IRQ3MDE 12 /* External Interrupt 3 Mode registers */ +#define BITP_XINT_CFG0_IRQ2EN 11 /* External Interrupt 2 Enable bit */ +#define BITP_XINT_CFG0_IRQ2MDE 8 /* External Interrupt 2 Mode registers */ +#define BITP_XINT_CFG0_IRQ1EN 7 /* External Interrupt 1 Enable bit */ +#define BITP_XINT_CFG0_IRQ1MDE 4 /* External Interrupt 1 Mode registers */ +#define BITP_XINT_CFG0_IRQ0EN 3 /* External Interrupt 0 Enable bit */ +#define BITP_XINT_CFG0_IRQ0MDE 0 /* External Interrupt 0 Mode registers */ +#define BITM_XINT_CFG0_UART_RX_MDE (_ADI_MSK_3(0x00E00000,0x00E00000UL, uint32_t )) /* External Interrupt using UART_RX wakeup Mode registers */ +#define BITM_XINT_CFG0_UART_RX_EN (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t )) /* External Interrupt using SIP_UPDATE enable bit */ +#define BITM_XINT_CFG0_IRQ3EN (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* External Interrupt 3 enable bit */ +#define BITM_XINT_CFG0_IRQ3MDE (_ADI_MSK_3(0x00007000,0x00007000UL, uint32_t )) /* External Interrupt 3 Mode registers */ +#define BITM_XINT_CFG0_IRQ2EN (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* External Interrupt 2 Enable bit */ +#define BITM_XINT_CFG0_IRQ2MDE (_ADI_MSK_3(0x00000700,0x00000700UL, uint32_t )) /* External Interrupt 2 Mode registers */ +#define BITM_XINT_CFG0_IRQ1EN (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* External Interrupt 1 Enable bit */ +#define BITM_XINT_CFG0_IRQ1MDE (_ADI_MSK_3(0x00000070,0x00000070UL, uint32_t )) /* External Interrupt 1 Mode registers */ +#define BITM_XINT_CFG0_IRQ0EN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* External Interrupt 0 Enable bit */ +#define BITM_XINT_CFG0_IRQ0MDE (_ADI_MSK_3(0x00000007,0x00000007UL, uint32_t )) /* External Interrupt 0 Mode registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + XINT_EXT_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_XINT_EXT_STAT_STAT_UART_RXWKUP 5 /* Interrupt status bit for UART RX WAKEUP interrupt */ +#define BITP_XINT_EXT_STAT_STAT_EXTINT3 3 /* Interrupt status bit for External Interrupt 3 */ +#define BITP_XINT_EXT_STAT_STAT_EXTINT2 2 /* Interrupt status bit for External Interrupt 2 */ +#define BITP_XINT_EXT_STAT_STAT_EXTINT1 1 /* Interrupt status bit for External Interrupt 1 */ +#define BITP_XINT_EXT_STAT_STAT_EXTINT0 0 /* Interrupt status bit for External Interrupt 0 */ +#define BITM_XINT_EXT_STAT_STAT_UART_RXWKUP (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* Interrupt status bit for UART RX WAKEUP interrupt */ +#define BITM_XINT_EXT_STAT_STAT_EXTINT3 (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Interrupt status bit for External Interrupt 3 */ +#define BITM_XINT_EXT_STAT_STAT_EXTINT2 (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Interrupt status bit for External Interrupt 2 */ +#define BITM_XINT_EXT_STAT_STAT_EXTINT1 (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Interrupt status bit for External Interrupt 1 */ +#define BITM_XINT_EXT_STAT_STAT_EXTINT0 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Interrupt status bit for External Interrupt 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + XINT_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_XINT_CLR_UART_RX_CLR 5 /* External interrupt Clear for UART_RX WAKEUP interrupt */ +#define BITP_XINT_CLR_IRQ3 3 /* External interrupt 3 */ +#define BITP_XINT_CLR_IRQ2 2 /* External interrupt 2 */ +#define BITP_XINT_CLR_IRQ1 1 /* External interrupt 1 */ +#define BITP_XINT_CLR_IRQ0 0 /* External interrupt 0 */ +#define BITM_XINT_CLR_UART_RX_CLR (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* External interrupt Clear for UART_RX WAKEUP interrupt */ +#define BITM_XINT_CLR_IRQ3 (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* External interrupt 3 */ +#define BITM_XINT_CLR_IRQ2 (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* External interrupt 2 */ +#define BITM_XINT_CLR_IRQ1 (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* External interrupt 1 */ +#define BITM_XINT_CLR_IRQ0 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* External interrupt 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + XINT_NMICLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_XINT_NMICLR_CLR 0 /* NMI clear */ +#define BITM_XINT_NMICLR_CLR (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* NMI clear */ + + +/* ============================================================================================================================ + Clocking registers + ============================================================================================================================ */ + +/* ============================================================================================================================ + CLKG0_OSC + ============================================================================================================================ */ +#define REG_CLKG0_OSC_KEY 0x4004C10C /* CLKG0_OSC Key Protection for OSCCTRL */ +#define REG_CLKG0_OSC_CTL 0x4004C110 /* CLKG0_OSC Oscillator Control */ + +/* ============================================================================================================================ + CLKG_OSC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_OSC_KEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_OSC_KEY_VALUE 0 /* Oscillator key */ +#define BITM_CLKG_OSC_KEY_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t )) /* Oscillator key */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_OSC_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_OSC_CTL_LFX_FAIL_STA 31 /* LF XTAL (crystal clock) Not Stable */ +#define BITP_CLKG_OSC_CTL_ROOT_FAIL_STA 30 /* Root clock (crystal clock) Not Stable */ +#define BITP_CLKG_OSC_CTL_ROOT_AUTSW_STA 22 /* Status of automatic switching of the Root clock to HFOSC upon detection of Root clock failure */ +#define BITP_CLKG_OSC_CTL_ROOT_AUTSW_EN 21 /* Enables automatic Switching of the Root clock to HFOSC on Root clock Failure */ +#define BITP_CLKG_OSC_CTL_ROOT_MON_EN 20 /* ROOT clock monitor and Clock FAIL interrupt enable */ +#define BITP_CLKG_OSC_CTL_LFX_ROBUST_LD 15 /* LFXTAL Robust Mode Load select */ +#define BITP_CLKG_OSC_CTL_LFX_ROBUST_EN 14 /* LFXTAL Mode select */ +#define BITP_CLKG_OSC_CTL_LFX_AUTSW_STA 13 /* Status of automatic switching of the LF Mux to LFOSC upon detection of LFXTAL failure */ +#define BITP_CLKG_OSC_CTL_LFX_AUTSW_EN 12 /* Enables automatic Switching of the LF Mux to LFOSC on LFXTAL Failure */ +#define BITP_CLKG_OSC_CTL_HFX_OK 11 /* Status of HFXTAL oscillator */ +#define BITP_CLKG_OSC_CTL_LFX_OK 10 /* Status of LFXTAL oscillator */ +#define BITP_CLKG_OSC_CTL_HFOSC_OK 9 /* Status of HFOSC oscillator */ +#define BITP_CLKG_OSC_CTL_LFOSC_OK 8 /* Status of LFOSC oscillator */ +#define BITP_CLKG_OSC_CTL_LFX_MON_EN 5 /* LFXTAL clock monitor and Clock FAIL interrupt enable */ +#define BITP_CLKG_OSC_CTL_LFX_BYP 4 /* Low frequency crystal oscillator Bypass */ +#define BITP_CLKG_OSC_CTL_HFX_EN 3 /* High frequency crystal oscillator enable */ +#define BITP_CLKG_OSC_CTL_LFX_EN 2 /* Low frequency crystal oscillator enable */ +#define BITP_CLKG_OSC_CTL_HFOSC_EN 1 /* High frequency internal oscillator enable */ +#define BITP_CLKG_OSC_CTL_LFCLK_MUX 0 /* 32 kHz clock select mux */ +#define BITM_CLKG_OSC_CTL_LFX_FAIL_STA (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t )) /* LF XTAL (crystal clock) Not Stable */ +#define BITM_CLKG_OSC_CTL_ROOT_FAIL_STA (_ADI_MSK_3(0x40000000,0x40000000UL, uint32_t )) /* Root clock (crystal clock) Not Stable */ +#define BITM_CLKG_OSC_CTL_ROOT_AUTSW_STA (_ADI_MSK_3(0x00400000,0x00400000UL, uint32_t )) /* Status of automatic switching of the Root clock to HFOSC upon detection of Root clock failure */ +#define BITM_CLKG_OSC_CTL_ROOT_AUTSW_EN (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t )) /* Enables automatic Switching of the Root clock to HFOSC on Root clock Failure */ +#define BITM_CLKG_OSC_CTL_ROOT_MON_EN (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t )) /* ROOT clock monitor and Clock FAIL interrupt enable */ +#define BITM_CLKG_OSC_CTL_LFX_ROBUST_LD (_ADI_MSK_3(0x00018000,0x00018000UL, uint32_t )) /* LFXTAL Robust Mode Load select */ +#define BITM_CLKG_OSC_CTL_LFX_ROBUST_EN (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* LFXTAL Mode select */ +#define BITM_CLKG_OSC_CTL_LFX_AUTSW_STA (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* Status of automatic switching of the LF Mux to LFOSC upon detection of LFXTAL failure */ +#define BITM_CLKG_OSC_CTL_LFX_AUTSW_EN (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* Enables automatic Switching of the LF Mux to LFOSC on LFXTAL Failure */ +#define BITM_CLKG_OSC_CTL_HFX_OK (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* Status of HFXTAL oscillator */ +#define BITM_CLKG_OSC_CTL_LFX_OK (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* Status of LFXTAL oscillator */ +#define BITM_CLKG_OSC_CTL_HFOSC_OK (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* Status of HFOSC oscillator */ +#define BITM_CLKG_OSC_CTL_LFOSC_OK (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* Status of LFOSC oscillator */ +#define BITM_CLKG_OSC_CTL_LFX_MON_EN (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* LFXTAL clock monitor and Clock FAIL interrupt enable */ +#define BITM_CLKG_OSC_CTL_LFX_BYP (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Low frequency crystal oscillator Bypass */ +#define BITM_CLKG_OSC_CTL_HFX_EN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* High frequency crystal oscillator enable */ +#define BITM_CLKG_OSC_CTL_LFX_EN (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Low frequency crystal oscillator enable */ +#define BITM_CLKG_OSC_CTL_HFOSC_EN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* High frequency internal oscillator enable */ +#define BITM_CLKG_OSC_CTL_LFCLK_MUX (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* 32 kHz clock select mux */ + + +/* ============================================================================================================================ + Power Management Registers + ============================================================================================================================ */ + +/* ============================================================================================================================ + PMG0_TST + ============================================================================================================================ */ +#define REG_PMG0_TST_SRAM_CTL 0x4004C260 /* PMG0_TST Control for SRAM Parity and Instruction SRAM */ +#define REG_PMG0_TST_SRAM_INITSTAT 0x4004C264 /* PMG0_TST Initialization Status Register */ +#define REG_PMG0_TST_CLR_LATCH_GPIOS 0x4004C268 /* PMG0_TST Clear GPIO After Shutdown Mode */ +#define REG_PMG0_TST_SCRPAD_IMG 0x4004C26C /* PMG0_TST Scratch Pad Image */ +#define REG_PMG0_TST_SCRPAD_3V_RD 0x4004C270 /* PMG0_TST Scratch Pad Saved in Battery Domain */ +#define REG_PMG0_TST_FAST_SHT_WAKEUP 0x4004C274 /* PMG0_TST Fast Shutdown Wake-up Enable */ + +/* ============================================================================================================================ + PMG_TST Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TST_SRAM_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TST_SRAM_CTL_INSTREN 31 /* Enables 32 KB instruction SRAM */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK7 23 /* Enable parity check */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK6 22 /* Enable parity check */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK5 21 /* Enable parity check */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK4 20 /* Enable parity check */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK3 19 /* Enable parity check */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK2 18 /* Enable parity check */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK1 17 /* Enable parity check */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK0 16 /* Enable parity check */ +#define BITP_PMG_TST_SRAM_CTL_ABTINIT 15 /* Abort current initialization. Self-cleared */ +#define BITP_PMG_TST_SRAM_CTL_AUTOINIT 14 /* Automatic initialization on wake up from hibernate mode */ +#define BITP_PMG_TST_SRAM_CTL_STARTINIT 13 /* Write one to trigger initialization. Self-cleared */ +#define BITP_PMG_TST_SRAM_CTL_BNK7EN 7 /* Enable initialization */ +#define BITP_PMG_TST_SRAM_CTL_BNK2EN 2 /* Enable initialization */ +#define BITP_PMG_TST_SRAM_CTL_BNK1EN 1 /* Enable initialization */ +#define BITM_PMG_TST_SRAM_CTL_INSTREN (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t )) /* Enables 32 KB instruction SRAM */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK7 (_ADI_MSK_3(0x00800000,0x00800000UL, uint32_t )) /* Enable parity check */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK6 (_ADI_MSK_3(0x00400000,0x00400000UL, uint32_t )) /* Enable parity check */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK5 (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t )) /* Enable parity check */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK4 (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t )) /* Enable parity check */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK3 (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t )) /* Enable parity check */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK2 (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t )) /* Enable parity check */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK1 (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t )) /* Enable parity check */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK0 (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* Enable parity check */ +#define BITM_PMG_TST_SRAM_CTL_ABTINIT (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* Abort current initialization. Self-cleared */ +#define BITM_PMG_TST_SRAM_CTL_AUTOINIT (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Automatic initialization on wake up from hibernate mode */ +#define BITM_PMG_TST_SRAM_CTL_STARTINIT (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* Write one to trigger initialization. Self-cleared */ +#define BITM_PMG_TST_SRAM_CTL_BNK7EN (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* Enable initialization */ +#define BITM_PMG_TST_SRAM_CTL_BNK2EN (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Enable initialization */ +#define BITM_PMG_TST_SRAM_CTL_BNK1EN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Enable initialization */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TST_SRAM_INITSTAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK7DONE 7 /* Bank 7 initialization status */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK6DONE 6 /* Bank 6 initialization status */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK5DONE 5 /* Bank 5 initialization status */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK4DONE 4 /* Bank 4 initialization status */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK3DONE 3 /* Bank 3 initialization status */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK2DONE 2 /* Bank 2 initialization status */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK1DONE 1 /* Bank 1 initialization status */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK0DONE 0 /* Bank 0 initialization status */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK7DONE (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* Bank 7 initialization status */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK6DONE (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* Bank 6 initialization status */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK5DONE (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* Bank 5 initialization status */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK4DONE (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Bank 4 initialization status */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK3DONE (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Bank 3 initialization status */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK2DONE (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Bank 2 initialization status */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK1DONE (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Bank 1 initialization status */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK0DONE (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Bank 0 initialization status */ +#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK7_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BNK7DONE: Bank 7 not initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_BANK7_INIT (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* BNK7DONE: Bank 7 initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK6_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BNK6DONE: Bank 6 not initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_BANK6_INIT (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* BNK6DONE: Bank 6 initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK5_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BNK5DONE: Bank 5 not initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_BANK5_INIT (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* BNK5DONE: Bank 5 initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK4_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BNK4DONE: Bank 4 not initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_BANK4_INIT (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* BNK4DONE: Bank 4 initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK3_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BNK3DONE: Bank 3 not initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_BANK3_INIT (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* BNK3DONE: Bank 3 initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK2_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BNK2DONE: Bank 2 not initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_BANK2_INIT (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* BNK2DONE: Bank 2 initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK1_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BNK1DONE: Bank 1 not initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_BANK1_INIT (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* BNK1DONE: Bank 1 initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK0_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BNK0DONE: Bank 0 not initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_BANK0_INIT (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* BNK0DONE: Bank 0 initialized */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TST_CLR_LATCH_GPIOS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TST_CLR_LATCH_GPIOS_VALUE 0 /* Writing 0x58FA creates a pulse to clear the latches for the GPIOs */ +#define BITM_PMG_TST_CLR_LATCH_GPIOS_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Writing 0x58FA creates a pulse to clear the latches for the GPIOs */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TST_SCRPAD_IMG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TST_SCRPAD_IMG_DATA 0 /* Value written to this register is saved in 3 V when going to shutdown */ +#define BITM_PMG_TST_SCRPAD_IMG_DATA (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Value written to this register is saved in 3 V when going to shutdown */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TST_SCRPAD_3V_RD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TST_SCRPAD_3V_RD_DATA 0 /* Reading the scratch pad stored in shutdown mode */ +#define BITM_PMG_TST_SCRPAD_3V_RD_DATA (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Reading the scratch pad stored in shutdown mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TST_FAST_SHT_WAKEUP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TST_FAST_SHT_WAKEUP_FAST_SHT_WAKEUP 0 /* Enables fast shutdown wake-up */ +#define BITM_PMG_TST_FAST_SHT_WAKEUP_FAST_SHT_WAKEUP (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enables fast shutdown wake-up */ + + +/* ============================================================================================================================ + Clocking registers + ============================================================================================================================ */ + +/* ============================================================================================================================ + CLKG0_CLK + ============================================================================================================================ */ +#define REG_CLKG0_CLK_CTL0 0x4004C300 /* CLKG0_CLK Misc Clock Settings */ +#define REG_CLKG0_CLK_CTL1 0x4004C304 /* CLKG0_CLK Clock Dividers */ +#define REG_CLKG0_CLK_CTL2 0x4004C308 /* CLKG0_CLK HF Oscillator Divided Clock Select */ +#define REG_CLKG0_CLK_CTL3 0x4004C30C /* CLKG0_CLK System PLL */ +#define REG_CLKG0_CLK_CTL5 0x4004C314 /* CLKG0_CLK User Clock Gating Control */ +#define REG_CLKG0_CLK_STAT0 0x4004C318 /* CLKG0_CLK Clocking Status */ + +/* ============================================================================================================================ + CLKG_CLK Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_CLK_CTL0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_CLK_CTL0_HFXTALIE 15 /* High frequency crystal interrupt enable */ +#define BITP_CLKG_CLK_CTL0_LFXTALIE 14 /* Low frequency crystal interrupt enable */ +#define BITP_CLKG_CLK_CTL0_PLL_IPSEL 11 /* SPLL source select mux */ +#define BITP_CLKG_CLK_CTL0_RCLKMUX 8 /* Flash reference clock and HPBUCK clock source mux */ +#define BITP_CLKG_CLK_CTL0_CLKOUT 3 /* GPIO clock out select */ +#define BITP_CLKG_CLK_CTL0_CLKMUX 0 /* Clock mux select */ +#define BITM_CLKG_CLK_CTL0_HFXTALIE (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* High frequency crystal interrupt enable */ +#define BITM_CLKG_CLK_CTL0_LFXTALIE (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Low frequency crystal interrupt enable */ +#define BITM_CLKG_CLK_CTL0_PLL_IPSEL (_ADI_MSK_3(0x00001800,0x00001800UL, uint32_t )) /* SPLL source select mux */ +#define BITM_CLKG_CLK_CTL0_RCLKMUX (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* Flash reference clock and HPBUCK clock source mux */ +#define BITM_CLKG_CLK_CTL0_CLKOUT (_ADI_MSK_3(0x00000078,0x00000078UL, uint32_t )) /* GPIO clock out select */ +#define BITM_CLKG_CLK_CTL0_CLKMUX (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* Clock mux select */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_CLK_CTL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_CLK_CTL1_ACLKDIVCNT 16 /* ACLK Divide Count */ +#define BITP_CLKG_CLK_CTL1_PCLKDIVCNT 8 /* PCLK divide count */ +#define BITP_CLKG_CLK_CTL1_HCLKDIVCNT 0 /* HCLK divide count */ +#define BITM_CLKG_CLK_CTL1_ACLKDIVCNT (_ADI_MSK_3(0x01FF0000,0x01FF0000UL, uint32_t )) /* ACLK Divide Count */ +#define BITM_CLKG_CLK_CTL1_PCLKDIVCNT (_ADI_MSK_3(0x00003F00,0x00003F00UL, uint32_t )) /* PCLK divide count */ +#define BITM_CLKG_CLK_CTL1_HCLKDIVCNT (_ADI_MSK_3(0x0000003F,0x0000003FUL, uint32_t )) /* HCLK divide count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_CLK_CTL2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_CLK_CTL2_HFOSCDIVCLKSEL 1 /* HF Oscillator divided clock select */ +#define BITP_CLKG_CLK_CTL2_HFOSCAUTODIV_EN 0 /* HF Oscillator auto divide by one clock selection during wakeup from Flexi power mode */ +#define BITM_CLKG_CLK_CTL2_HFOSCDIVCLKSEL (_ADI_MSK_3(0x0000000E,0x0000000EUL, uint32_t )) /* HF Oscillator divided clock select */ +#define BITM_CLKG_CLK_CTL2_HFOSCAUTODIV_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* HF Oscillator auto divide by one clock selection during wakeup from Flexi power mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_CLK_CTL3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_CLK_CTL3_SPLLMUL2 16 /* System PLL multiply by 2 */ +#define BITP_CLKG_CLK_CTL3_SPLLMSEL 11 /* System PLL M Divider */ +#define BITP_CLKG_CLK_CTL3_SPLLIE 10 /* System PLL interrupt enable */ +#define BITP_CLKG_CLK_CTL3_SPLLEN 9 /* System PLL enable */ +#define BITP_CLKG_CLK_CTL3_SPLLDIV2 8 /* System PLL division by 2 */ +#define BITP_CLKG_CLK_CTL3_SPLLNSEL 0 /* System PLL N multiplier */ +#define BITM_CLKG_CLK_CTL3_SPLLMUL2 (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* System PLL multiply by 2 */ +#define BITM_CLKG_CLK_CTL3_SPLLMSEL (_ADI_MSK_3(0x00007800,0x00007800UL, uint32_t )) /* System PLL M Divider */ +#define BITM_CLKG_CLK_CTL3_SPLLIE (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* System PLL interrupt enable */ +#define BITM_CLKG_CLK_CTL3_SPLLEN (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* System PLL enable */ +#define BITM_CLKG_CLK_CTL3_SPLLDIV2 (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* System PLL division by 2 */ +#define BITM_CLKG_CLK_CTL3_SPLLNSEL (_ADI_MSK_3(0x0000001F,0x0000001FUL, uint32_t )) /* System PLL N multiplier */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_CLK_CTL5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF 6 /* Timer RGB user control */ +#define BITP_CLKG_CLK_CTL5_PERCLKOFF 5 /* This bit is used to disable all clocks connected to all peripherals */ +#define BITP_CLKG_CLK_CTL5_GPIOCLKOFF 4 /* GPIO clock control */ +#define BITP_CLKG_CLK_CTL5_UCLKI2COFF 3 /* I2C clock user control */ +#define BITP_CLKG_CLK_CTL5_GPTCLK2OFF 2 /* GP Timer 2 user control */ +#define BITP_CLKG_CLK_CTL5_GPTCLK1OFF 1 /* GP Timer 1 user control */ +#define BITP_CLKG_CLK_CTL5_GPTCLK0OFF 0 /* GP Timer 0 user control */ +#define BITM_CLKG_CLK_CTL5_TMRRGBCLKOFF (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* Timer RGB user control */ +#define BITM_CLKG_CLK_CTL5_PERCLKOFF (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* This bit is used to disable all clocks connected to all peripherals */ +#define BITM_CLKG_CLK_CTL5_GPIOCLKOFF (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* GPIO clock control */ +#define BITM_CLKG_CLK_CTL5_UCLKI2COFF (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* I2C clock user control */ +#define BITM_CLKG_CLK_CTL5_GPTCLK2OFF (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* GP Timer 2 user control */ +#define BITM_CLKG_CLK_CTL5_GPTCLK1OFF (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* GP Timer 1 user control */ +#define BITM_CLKG_CLK_CTL5_GPTCLK0OFF (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* GP Timer 0 user control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_CLK_STAT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_CLK_STAT0_HFXTALNOK 14 /* HF crystal not stable */ +#define BITP_CLKG_CLK_STAT0_HFXTALOK 13 /* HF crystal stable */ +#define BITP_CLKG_CLK_STAT0_HFXTAL 12 /* HF crystal status */ +#define BITP_CLKG_CLK_STAT0_LFXTALNOK 10 /* LF crystal not stable */ +#define BITP_CLKG_CLK_STAT0_LFXTALOK 9 /* LF crystal stable */ +#define BITP_CLKG_CLK_STAT0_LFXTAL 8 /* LF crystal status */ +#define BITP_CLKG_CLK_STAT0_SPLLUNLK 2 /* System PLL unlock */ +#define BITP_CLKG_CLK_STAT0_SPLLLK 1 /* System PLL lock */ +#define BITP_CLKG_CLK_STAT0_SPLL 0 /* System PLL status */ +#define BITM_CLKG_CLK_STAT0_HFXTALNOK (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* HF crystal not stable */ +#define BITM_CLKG_CLK_STAT0_HFXTALOK (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* HF crystal stable */ +#define BITM_CLKG_CLK_STAT0_HFXTAL (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* HF crystal status */ +#define BITM_CLKG_CLK_STAT0_LFXTALNOK (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* LF crystal not stable */ +#define BITM_CLKG_CLK_STAT0_LFXTALOK (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* LF crystal stable */ +#define BITM_CLKG_CLK_STAT0_LFXTAL (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* LF crystal status */ +#define BITM_CLKG_CLK_STAT0_SPLLUNLK (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* System PLL unlock */ +#define BITM_CLKG_CLK_STAT0_SPLLLK (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* System PLL lock */ +#define BITM_CLKG_CLK_STAT0_SPLL (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* System PLL status */ + + +/* ============================================================================================================================ + Bus matrix + ============================================================================================================================ */ + +/* ============================================================================================================================ + BUSM0 + ============================================================================================================================ */ +#define REG_BUSM0_ARBIT0 0x4004C800 /* BUSM0 Arbitration Priority Configuration for FLASH and SRAM0 */ +#define REG_BUSM0_ARBIT1 0x4004C804 /* BUSM0 Arbitration Priority Configuration for SRAM1 and SIP */ +#define REG_BUSM0_ARBIT2 0x4004C808 /* BUSM0 Arbitration Priority Configuration for APB32 and APB16 */ +#define REG_BUSM0_ARBIT3 0x4004C80C /* BUSM0 Arbitration Priority Configuration for APB16 priority for core and for DMA1 */ +#define REG_BUSM0_ARBIT4 0x4004C814 /* BUSM0 Arbitration Priority Configuration for SRAM1 and SIP */ + +/* ============================================================================================================================ + BUSM Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + BUSM_ARBIT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BUSM_ARBIT0_SRAM0_DMA0 20 /* SRAM0 priority for DMA0 */ +#define BITP_BUSM_ARBIT0_SRAM0_SBUS 18 /* SRAM0 priority for SBUS */ +#define BITP_BUSM_ARBIT0_SRAM0_DCODE 16 /* SRAM0 priority for Dcode */ +#define BITP_BUSM_ARBIT0_FLSH_DMA0 4 /* Flash priority for DMA0 */ +#define BITP_BUSM_ARBIT0_FLSH_SBUS 2 /* Flash priority for SBUS */ +#define BITP_BUSM_ARBIT0_FLSH_DCODE 0 /* Flash priority for DCODE */ +#define BITM_BUSM_ARBIT0_SRAM0_DMA0 (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t )) /* SRAM0 priority for DMA0 */ +#define BITM_BUSM_ARBIT0_SRAM0_SBUS (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* SRAM0 priority for SBUS */ +#define BITM_BUSM_ARBIT0_SRAM0_DCODE (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t )) /* SRAM0 priority for Dcode */ +#define BITM_BUSM_ARBIT0_FLSH_DMA0 (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* Flash priority for DMA0 */ +#define BITM_BUSM_ARBIT0_FLSH_SBUS (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t )) /* Flash priority for SBUS */ +#define BITM_BUSM_ARBIT0_FLSH_DCODE (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* Flash priority for DCODE */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BUSM_ARBIT1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BUSM_ARBIT1_SIP_DMA0 20 /* SIP priority for DMA0 */ +#define BITP_BUSM_ARBIT1_SIP_SBUS 18 /* SIP priority for SBUS */ +#define BITP_BUSM_ARBIT1_SIP_DCODE 16 /* SIP priority for DCODE */ +#define BITP_BUSM_ARBIT1_SRAM1_DMA0 4 /* SRAM1 priority for DMA0 */ +#define BITP_BUSM_ARBIT1_SRAM1_SBUS 2 /* SRAM1 priority for SBUS */ +#define BITP_BUSM_ARBIT1_SRAM1_DCODE 0 /* SRAM1 priority for Dcode */ +#define BITM_BUSM_ARBIT1_SIP_DMA0 (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t )) /* SIP priority for DMA0 */ +#define BITM_BUSM_ARBIT1_SIP_SBUS (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* SIP priority for SBUS */ +#define BITM_BUSM_ARBIT1_SIP_DCODE (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t )) /* SIP priority for DCODE */ +#define BITM_BUSM_ARBIT1_SRAM1_DMA0 (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* SRAM1 priority for DMA0 */ +#define BITM_BUSM_ARBIT1_SRAM1_SBUS (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t )) /* SRAM1 priority for SBUS */ +#define BITM_BUSM_ARBIT1_SRAM1_DCODE (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* SRAM1 priority for Dcode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BUSM_ARBIT2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BUSM_ARBIT2_APB16_DMA0 20 /* APB16 priority for DMA0 */ +#define BITP_BUSM_ARBIT2_APB16_SBUS 18 /* APB16 priority for SBUS */ +#define BITP_BUSM_ARBIT2_APB16_DCODE 16 /* APB16 priority for DCODE */ +#define BITP_BUSM_ARBIT2_APB32_DMA0 4 /* APB32 priority for DMA0 */ +#define BITP_BUSM_ARBIT2_APB32_SBUS 2 /* APB32 priority for SBUS */ +#define BITP_BUSM_ARBIT2_APB32_DCODE 0 /* APB32 priority for DCODE */ +#define BITM_BUSM_ARBIT2_APB16_DMA0 (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t )) /* APB16 priority for DMA0 */ +#define BITM_BUSM_ARBIT2_APB16_SBUS (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* APB16 priority for SBUS */ +#define BITM_BUSM_ARBIT2_APB16_DCODE (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t )) /* APB16 priority for DCODE */ +#define BITM_BUSM_ARBIT2_APB32_DMA0 (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* APB32 priority for DMA0 */ +#define BITM_BUSM_ARBIT2_APB32_SBUS (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t )) /* APB32 priority for SBUS */ +#define BITM_BUSM_ARBIT2_APB32_DCODE (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* APB32 priority for DCODE */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BUSM_ARBIT3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BUSM_ARBIT3_APB16_4DMA_DMA1 17 /* APB16 for dma priority for DMA1 */ +#define BITP_BUSM_ARBIT3_APB16_4DMA_CORE 16 /* APB16 for dma priority for CORE */ +#define BITP_BUSM_ARBIT3_APB16_DMA1 1 /* APB16 priority for DMA1 */ +#define BITP_BUSM_ARBIT3_APB16_CORE 0 /* APB16 priority for CORE */ +#define BITM_BUSM_ARBIT3_APB16_4DMA_DMA1 (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t )) /* APB16 for dma priority for DMA1 */ +#define BITM_BUSM_ARBIT3_APB16_4DMA_CORE (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* APB16 for dma priority for CORE */ +#define BITM_BUSM_ARBIT3_APB16_DMA1 (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* APB16 priority for DMA1 */ +#define BITM_BUSM_ARBIT3_APB16_CORE (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* APB16 priority for CORE */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BUSM_ARBIT4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BUSM_ARBIT4_SRAM2_DMA0 4 /* SRAM2 priority for DMA0 */ +#define BITP_BUSM_ARBIT4_SRAM2_SBUS 2 /* SRAM2 priority for SBUS */ +#define BITP_BUSM_ARBIT4_SRAM2_DCODE 0 /* SRAM2 priority for Dcode */ +#define BITM_BUSM_ARBIT4_SRAM2_DMA0 (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* SRAM2 priority for DMA0 */ +#define BITM_BUSM_ARBIT4_SRAM2_SBUS (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t )) /* SRAM2 priority for SBUS */ +#define BITM_BUSM_ARBIT4_SRAM2_DCODE (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* SRAM2 priority for Dcode */ + + +/* ============================================================================================================================ + Parallel Test Interface + ============================================================================================================================ */ + +/* ============================================================================================================================ + PTI0 + ============================================================================================================================ */ +#define REG_PTI0_RST_ISR_STARTADDR 0x4004CD00 /* PTI0 Reset ISR Start Address */ +#define REG_PTI0_RST_STACK_PTR 0x4004CD04 /* PTI0 Reset Stack Pointer */ +#define REG_PTI0_CTL 0x4004CD08 /* PTI0 Parallel Test Interface Control Register */ + +/* ============================================================================================================================ + PTI Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + PTI_RST_ISR_STARTADDR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PTI_RST_ISR_STARTADDR_VALUE 0 +#define BITM_PTI_RST_ISR_STARTADDR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) + +/* ------------------------------------------------------------------------------------------------------------------------- + PTI_RST_STACK_PTR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PTI_RST_STACK_PTR_VALUE 0 +#define BITM_PTI_RST_STACK_PTR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) + +/* ------------------------------------------------------------------------------------------------------------------------- + PTI_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PTI_CTL_EN 0 +#define BITM_PTI_CTL_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) + + +/* ============================================================================================================================ + Cortex-M3 Interrupt Controller + ============================================================================================================================ */ + +/* ============================================================================================================================ + NVIC0 + ============================================================================================================================ */ +#define REG_NVIC0_INTNUM 0xE000E004 /* NVIC0 Interrupt Control Type */ +#define REG_NVIC0_STKSTA 0xE000E010 /* NVIC0 Systick Control and Status */ +#define REG_NVIC0_STKLD 0xE000E014 /* NVIC0 Systick Reload Value */ +#define REG_NVIC0_STKVAL 0xE000E018 /* NVIC0 Systick Current Value */ +#define REG_NVIC0_STKCAL 0xE000E01C /* NVIC0 Systick Calibration Value */ +#define REG_NVIC0_INTSETE0 0xE000E100 /* NVIC0 IRQ0..31 Set_Enable */ +#define REG_NVIC0_INTSETE1 0xE000E104 /* NVIC0 IRQ32..63 Set_Enable */ +#define REG_NVIC0_INTCLRE0 0xE000E180 /* NVIC0 IRQ0..31 Clear_Enable */ +#define REG_NVIC0_INTCLRE1 0xE000E184 /* NVIC0 IRQ32..63 Clear_Enable */ +#define REG_NVIC0_INTSETP0 0xE000E200 /* NVIC0 IRQ0..31 Set_Pending */ +#define REG_NVIC0_INTSETP1 0xE000E204 /* NVIC0 IRQ32..63 Set_Pending */ +#define REG_NVIC0_INTCLRP0 0xE000E280 /* NVIC0 IRQ0..31 Clear_Pending */ +#define REG_NVIC0_INTCLRP1 0xE000E284 /* NVIC0 IRQ32..63 Clear_Pending */ +#define REG_NVIC0_INTACT0 0xE000E300 /* NVIC0 IRQ0..31 Active Bit */ +#define REG_NVIC0_INTACT1 0xE000E304 /* NVIC0 IRQ32..63 Active Bit */ +#define REG_NVIC0_INTPRI0 0xE000E400 /* NVIC0 IRQ0..3 Priority */ +#define REG_NVIC0_INTPRI1 0xE000E404 /* NVIC0 IRQ4..7 Priority */ +#define REG_NVIC0_INTPRI2 0xE000E408 /* NVIC0 IRQ8..11 Priority */ +#define REG_NVIC0_INTPRI3 0xE000E40C /* NVIC0 IRQ12..15 Priority */ +#define REG_NVIC0_INTPRI4 0xE000E410 /* NVIC0 IRQ16..19 Priority */ +#define REG_NVIC0_INTPRI5 0xE000E414 /* NVIC0 IRQ20..23 Priority */ +#define REG_NVIC0_INTPRI6 0xE000E418 /* NVIC0 IRQ24..27 Priority */ +#define REG_NVIC0_INTPRI7 0xE000E41C /* NVIC0 IRQ28..31 Priority */ +#define REG_NVIC0_INTPRI8 0xE000E420 /* NVIC0 IRQ32..35 Priority */ +#define REG_NVIC0_INTPRI9 0xE000E424 /* NVIC0 IRQ36..39 Priority */ +#define REG_NVIC0_INTPRI10 0xE000E428 /* NVIC0 IRQ40..43 Priority */ +#define REG_NVIC0_INTCPID 0xE000ED00 /* NVIC0 CPUID Base */ +#define REG_NVIC0_INTSTA 0xE000ED04 /* NVIC0 Interrupt Control State */ +#define REG_NVIC0_INTVEC 0xE000ED08 /* NVIC0 Vector Table Offset */ +#define REG_NVIC0_INTAIRC 0xE000ED0C /* NVIC0 Application Interrupt/Reset Control */ +#define REG_NVIC0_INTCON0 0xE000ED10 /* NVIC0 System Control */ +#define REG_NVIC0_INTCON1 0xE000ED14 /* NVIC0 Configuration Control */ +#define REG_NVIC0_INTSHPRIO0 0xE000ED18 /* NVIC0 System Handlers 4-7 Priority */ +#define REG_NVIC0_INTSHPRIO1 0xE000ED1C /* NVIC0 System Handlers 8-11 Priority */ +#define REG_NVIC0_INTSHPRIO3 0xE000ED20 /* NVIC0 System Handlers 12-15 Priority */ +#define REG_NVIC0_INTSHCSR 0xE000ED24 /* NVIC0 System Handler Control and State */ +#define REG_NVIC0_INTCFSR 0xE000ED28 /* NVIC0 Configurable Fault Status */ +#define REG_NVIC0_INTHFSR 0xE000ED2C /* NVIC0 Hard Fault Status */ +#define REG_NVIC0_INTDFSR 0xE000ED30 /* NVIC0 Debug Fault Status */ +#define REG_NVIC0_INTMMAR 0xE000ED34 /* NVIC0 Mem Manage Address */ +#define REG_NVIC0_INTBFAR 0xE000ED38 /* NVIC0 Bus Fault Address */ +#define REG_NVIC0_INTAFSR 0xE000ED3C /* NVIC0 Auxiliary Fault Status */ +#define REG_NVIC0_INTPFR0 0xE000ED40 /* NVIC0 Processor Feature Register 0 */ +#define REG_NVIC0_INTPFR1 0xE000ED44 /* NVIC0 Processor Feature Register 1 */ +#define REG_NVIC0_INTDFR0 0xE000ED48 /* NVIC0 Debug Feature Register 0 */ +#define REG_NVIC0_INTAFR0 0xE000ED4C /* NVIC0 Auxiliary Feature Register 0 */ +#define REG_NVIC0_INTMMFR0 0xE000ED50 /* NVIC0 Memory Model Feature Register 0 */ +#define REG_NVIC0_INTMMFR1 0xE000ED54 /* NVIC0 Memory Model Feature Register 1 */ +#define REG_NVIC0_INTMMFR2 0xE000ED58 /* NVIC0 Memory Model Feature Register 2 */ +#define REG_NVIC0_INTMMFR3 0xE000ED5C /* NVIC0 Memory Model Feature Register 3 */ +#define REG_NVIC0_INTISAR0 0xE000ED60 /* NVIC0 ISA Feature Register 0 */ +#define REG_NVIC0_INTISAR1 0xE000ED64 /* NVIC0 ISA Feature Register 1 */ +#define REG_NVIC0_INTISAR2 0xE000ED68 /* NVIC0 ISA Feature Register 2 */ +#define REG_NVIC0_INTISAR3 0xE000ED6C /* NVIC0 ISA Feature Register 3 */ +#define REG_NVIC0_INTISAR4 0xE000ED70 /* NVIC0 ISA Feature Register 4 */ +#define REG_NVIC0_INTTRGI 0xE000EF00 /* NVIC0 Software Trigger Interrupt Register */ +#define REG_NVIC0_INTPID4 0xE000EFD0 /* NVIC0 Peripheral Identification Register 4 */ +#define REG_NVIC0_INTPID5 0xE000EFD4 /* NVIC0 Peripheral Identification Register 5 */ +#define REG_NVIC0_INTPID6 0xE000EFD8 /* NVIC0 Peripheral Identification Register 6 */ +#define REG_NVIC0_INTPID7 0xE000EFDC /* NVIC0 Peripheral Identification Register 7 */ +#define REG_NVIC0_INTPID0 0xE000EFE0 /* NVIC0 Peripheral Identification Bits7:0 */ +#define REG_NVIC0_INTPID1 0xE000EFE4 /* NVIC0 Peripheral Identification Bits15:8 */ +#define REG_NVIC0_INTPID2 0xE000EFE8 /* NVIC0 Peripheral Identification Bits16:23 */ +#define REG_NVIC0_INTPID3 0xE000EFEC /* NVIC0 Peripheral Identification Bits24:31 */ +#define REG_NVIC0_INTCID0 0xE000EFF0 /* NVIC0 Component Identification Bits7:0 */ +#define REG_NVIC0_INTCID1 0xE000EFF4 /* NVIC0 Component Identification Bits15:8 */ +#define REG_NVIC0_INTCID2 0xE000EFF8 /* NVIC0 Component Identification Bits16:23 */ +#define REG_NVIC0_INTCID3 0xE000EFFC /* NVIC0 Component Identification Bits24:31 */ + +/* ============================================================================================================================ + NVIC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTNUM Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTNUM_VALUE 0 /* Interrupt Control Type */ +#define BITM_NVIC_INTNUM_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Interrupt Control Type */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_STKSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_STKSTA_VALUE 0 /* Systick Control and Status */ +#define BITM_NVIC_STKSTA_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Systick Control and Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_STKLD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_STKLD_VALUE 0 /* Systick Reload Value */ +#define BITM_NVIC_STKLD_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Systick Reload Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_STKVAL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_STKVAL_VALUE 0 /* Systick Current Value */ +#define BITM_NVIC_STKVAL_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Systick Current Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_STKCAL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_STKCAL_VALUE 0 /* Systick Calibration Value */ +#define BITM_NVIC_STKCAL_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Systick Calibration Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSETE0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSETE0_VALUE 0 /* IRQ0..31 Set_Enable */ +#define BITM_NVIC_INTSETE0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ0..31 Set_Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSETE1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSETE1_VALUE 0 /* IRQ32..63 Set_Enable */ +#define BITM_NVIC_INTSETE1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ32..63 Set_Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCLRE0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCLRE0_VALUE 0 /* IRQ0..31 Clear_Enable */ +#define BITM_NVIC_INTCLRE0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ0..31 Clear_Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCLRE1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCLRE1_VALUE 0 /* IRQ32..63 Clear_Enable */ +#define BITM_NVIC_INTCLRE1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ32..63 Clear_Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSETP0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSETP0_VALUE 0 /* IRQ0..31 Set_Pending */ +#define BITM_NVIC_INTSETP0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ0..31 Set_Pending */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSETP1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSETP1_VALUE 0 /* IRQ32..63 Set_Pending */ +#define BITM_NVIC_INTSETP1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ32..63 Set_Pending */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCLRP0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCLRP0_VALUE 0 /* IRQ0..31 Clear_Pending */ +#define BITM_NVIC_INTCLRP0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ0..31 Clear_Pending */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCLRP1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCLRP1_VALUE 0 /* IRQ32..63 Clear_Pending */ +#define BITM_NVIC_INTCLRP1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ32..63 Clear_Pending */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTACT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTACT0_VALUE 0 /* IRQ0..31 Active Bit */ +#define BITM_NVIC_INTACT0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ0..31 Active Bit */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTACT1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTACT1_VALUE 0 /* IRQ32..63 Active Bit */ +#define BITM_NVIC_INTACT1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ32..63 Active Bit */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI0_VALUE 0 /* IRQ0..3 Priority */ +#define BITM_NVIC_INTPRI0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ0..3 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI1_VALUE 0 /* IRQ4..7 Priority */ +#define BITM_NVIC_INTPRI1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ4..7 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI2_VALUE 0 /* IRQ8..11 Priority */ +#define BITM_NVIC_INTPRI2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ8..11 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI3_VALUE 0 /* IRQ12..15 Priority */ +#define BITM_NVIC_INTPRI3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ12..15 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI4_VALUE 0 /* IRQ16..19 Priority */ +#define BITM_NVIC_INTPRI4_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ16..19 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI5_VALUE 0 /* IRQ20..23 Priority */ +#define BITM_NVIC_INTPRI5_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ20..23 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI6 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI6_VALUE 0 /* IRQ24..27 Priority */ +#define BITM_NVIC_INTPRI6_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ24..27 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI7 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI7_VALUE 0 /* IRQ28..31 Priority */ +#define BITM_NVIC_INTPRI7_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ28..31 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI8 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI8_VALUE 0 /* IRQ32..35 Priority */ +#define BITM_NVIC_INTPRI8_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ32..35 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI9 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI9_VALUE 0 /* IRQ36..39 Priority */ +#define BITM_NVIC_INTPRI9_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ36..39 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI10 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI10_VALUE 0 /* IRQ40..43 Priority */ +#define BITM_NVIC_INTPRI10_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ40..43 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCPID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCPID_VALUE 0 /* CPUID Base */ +#define BITM_NVIC_INTCPID_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* CPUID Base */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSTA_VALUE 0 /* Interrupt Control State */ +#define BITM_NVIC_INTSTA_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Interrupt Control State */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTVEC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTVEC_VALUE 0 /* Vector Table Offset */ +#define BITM_NVIC_INTVEC_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Vector Table Offset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTAIRC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTAIRC_VALUE 0 /* Application Interrupt/Reset Control */ +#define BITM_NVIC_INTAIRC_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Application Interrupt/Reset Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCON0_SLEEPDEEP 2 /* deep sleep flag for HIBERNATE mode */ +#define BITP_NVIC_INTCON0_SLEEPONEXIT 1 /* Sleeps the core on exit from an ISR */ +#define BITM_NVIC_INTCON0_SLEEPDEEP (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* deep sleep flag for HIBERNATE mode */ +#define BITM_NVIC_INTCON0_SLEEPONEXIT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Sleeps the core on exit from an ISR */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCON1_VALUE 0 /* Configuration Control */ +#define BITM_NVIC_INTCON1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Configuration Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSHPRIO0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSHPRIO0_VALUE 0 /* System Handlers 4-7 Priority */ +#define BITM_NVIC_INTSHPRIO0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* System Handlers 4-7 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSHPRIO1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSHPRIO1_VALUE 0 /* System Handlers 8-11 Priority */ +#define BITM_NVIC_INTSHPRIO1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* System Handlers 8-11 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSHPRIO3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSHPRIO3_VALUE 0 /* System Handlers 12-15 Priority */ +#define BITM_NVIC_INTSHPRIO3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* System Handlers 12-15 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSHCSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSHCSR_VALUE 0 /* System Handler Control and State */ +#define BITM_NVIC_INTSHCSR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* System Handler Control and State */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCFSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCFSR_VALUE 0 /* Configurable Fault Status */ +#define BITM_NVIC_INTCFSR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Configurable Fault Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTHFSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTHFSR_VALUE 0 /* Hard Fault Status */ +#define BITM_NVIC_INTHFSR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Hard Fault Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTDFSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTDFSR_VALUE 0 /* Debug Fault Status */ +#define BITM_NVIC_INTDFSR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Debug Fault Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTMMAR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTMMAR_VALUE 0 /* Mem Manage Address */ +#define BITM_NVIC_INTMMAR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Mem Manage Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTBFAR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTBFAR_VALUE 0 /* Bus Fault Address */ +#define BITM_NVIC_INTBFAR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Bus Fault Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTAFSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTAFSR_VALUE 0 /* Auxiliary Fault Status */ +#define BITM_NVIC_INTAFSR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Auxiliary Fault Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPFR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPFR0_VALUE 0 /* Processor Feature Register 0 */ +#define BITM_NVIC_INTPFR0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Processor Feature Register 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPFR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPFR1_VALUE 0 /* Processor Feature Register 1 */ +#define BITM_NVIC_INTPFR1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Processor Feature Register 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTDFR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTDFR0_VALUE 0 /* Debug Feature Register 0 */ +#define BITM_NVIC_INTDFR0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Debug Feature Register 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTAFR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTAFR0_VALUE 0 /* Auxiliary Feature Register 0 */ +#define BITM_NVIC_INTAFR0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Auxiliary Feature Register 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTMMFR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTMMFR0_VALUE 0 /* Memory Model Feature Register 0 */ +#define BITM_NVIC_INTMMFR0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Memory Model Feature Register 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTMMFR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTMMFR1_VALUE 0 /* Memory Model Feature Register 1 */ +#define BITM_NVIC_INTMMFR1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Memory Model Feature Register 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTMMFR2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTMMFR2_VALUE 0 /* Memory Model Feature Register 2 */ +#define BITM_NVIC_INTMMFR2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Memory Model Feature Register 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTMMFR3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTMMFR3_VALUE 0 /* Memory Model Feature Register 3 */ +#define BITM_NVIC_INTMMFR3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Memory Model Feature Register 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTISAR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTISAR0_VALUE 0 /* ISA Feature Register 0 */ +#define BITM_NVIC_INTISAR0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* ISA Feature Register 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTISAR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTISAR1_VALUE 0 /* ISA Feature Register 1 */ +#define BITM_NVIC_INTISAR1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* ISA Feature Register 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTISAR2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTISAR2_VALUE 0 /* ISA Feature Register 2 */ +#define BITM_NVIC_INTISAR2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* ISA Feature Register 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTISAR3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTISAR3_VALUE 0 /* ISA Feature Register 3 */ +#define BITM_NVIC_INTISAR3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* ISA Feature Register 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTISAR4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTISAR4_VALUE 0 /* ISA Feature Register 4 */ +#define BITM_NVIC_INTISAR4_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* ISA Feature Register 4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTTRGI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTTRGI_VALUE 0 /* Software Trigger Interrupt Register */ +#define BITM_NVIC_INTTRGI_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Software Trigger Interrupt Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID4_VALUE 0 /* Peripheral Identification Register 4 */ +#define BITM_NVIC_INTPID4_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Register 4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID5_VALUE 0 /* Peripheral Identification Register 5 */ +#define BITM_NVIC_INTPID5_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Register 5 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID6 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID6_VALUE 0 /* Peripheral Identification Register 6 */ +#define BITM_NVIC_INTPID6_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Register 6 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID7 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID7_VALUE 0 /* Peripheral Identification Register 7 */ +#define BITM_NVIC_INTPID7_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Register 7 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID0_VALUE 0 /* Peripheral Identification Bits7:0 */ +#define BITM_NVIC_INTPID0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Bits7:0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID1_VALUE 0 /* Peripheral Identification Bits15:8 */ +#define BITM_NVIC_INTPID1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Bits15:8 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID2_VALUE 0 /* Peripheral Identification Bits16:23 */ +#define BITM_NVIC_INTPID2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Bits16:23 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID3_VALUE 0 /* Peripheral Identification Bits24:31 */ +#define BITM_NVIC_INTPID3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Bits24:31 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCID0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCID0_VALUE 0 /* Component Identification Bits7:0 */ +#define BITM_NVIC_INTCID0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Component Identification Bits7:0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCID1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCID1_VALUE 0 /* Component Identification Bits15:8 */ +#define BITM_NVIC_INTCID1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Component Identification Bits15:8 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCID2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCID2_VALUE 0 /* Component Identification Bits16:23 */ +#define BITM_NVIC_INTCID2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Component Identification Bits16:23 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCID3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCID3_VALUE 0 /* Component Identification Bits24:31 */ +#define BITM_NVIC_INTCID3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Component Identification Bits24:31 */ + +/* ==================================================================================================== + * Interrupt Definitions + * ==================================================================================================== */ +#define INTR_RESET (-15) /* Cortex-M4 Reset */ +#define INTR_NonMaskableInt (-14) /* Cortex-M4 Non-maskable Interrupt */ +#define INTR_HardFault (-13) /* Cortex-M4 Hardware Fault */ +#define INTR_MemoryManagement (-12) /* Cortex-M4 Memory Management Interrupt */ +#define INTR_BusFault (-11) /* Cortex-M4 Bus Fault */ +#define INTR_UsageFault (-10) /* Cortex-M4 Usage Fault */ +#define INTR_SVCall ( -5) /* Cortex-M4 SVCall Interrupt */ +#define INTR_DebugMonitor ( -4) /* Cortex-M4 Debug Monitor */ +#define INTR_PendSV ( -2) /* Cortex-M4 PendSV Interrupt */ +#define INTR_SysTick ( -1) /* Cortex-M4 SysTick Interrupt */ +#define INTR_RTC1_EVT 0 /* Event */ +#define INTR_XINT_EVT0 1 /* External Wakeup Interrupt n */ +#define INTR_XINT_EVT1 2 /* External Wakeup Interrupt n */ +#define INTR_XINT_EVT2 3 /* External Wakeup Interrupt n */ +#define INTR_XINT_EVT3 4 /* External Wakeup Interrupt n */ +#define INTR_WDT_EXP 5 /* Expiration */ +#define INTR_PMG0_VREG_OVR 6 /* Voltage Regulator (VREG) Overvoltage */ +#define INTR_PMG0_BATT_RANGE 7 /* Battery Voltage (VBAT) Out of Range */ +#define INTR_RTC0_EVT 8 /* Event */ +#define INTR_SYS_GPIO_INTA 9 /* GPIO Interrupt A */ +#define INTR_SYS_GPIO_INTB 10 /* GPIO Interrupt B */ +#define INTR_TMR0_EVT 11 /* Event */ +#define INTR_TMR1_EVT 12 /* Event */ +#define INTR_FLCC_EVT 13 /* Event */ +#define INTR_UART0_EVT 14 /* UART0 Event */ +#define INTR_SPI0_EVT 15 /* Event */ +#define INTR_SPI2_EVT 16 /* Event */ +#define INTR_I2C_SLV_EVT 17 /* Slave Event */ +#define INTR_I2C_MST_EVT 18 /* Master Event */ +#define INTR_DMA_CHAN_ERR 19 /* Channel Error */ +#define INTR_DMA0_CH0_DONE 20 /* Channel 0 Done */ +#define INTR_DMA0_CH1_DONE 21 /* Channel 1 Done */ +#define INTR_DMA0_CH2_DONE 22 /* Channel 2 Done */ +#define INTR_DMA0_CH3_DONE 23 /* Channel 3 Done */ +#define INTR_DMA0_CH4_DONE 24 /* Channel 4 Done */ +#define INTR_DMA0_CH5_DONE 25 /* Channel 5 Done */ +#define INTR_DMA0_CH6_DONE 26 /* Channel 6 Done */ +#define INTR_DMA0_CH7_DONE 27 /* Channel 7 Done */ +#define INTR_DMA0_CH8_DONE 28 /* Channel 8 Done */ +#define INTR_DMA0_CH9_DONE 29 /* Channel 9 Done */ +#define INTR_DMA0_CH10_DONE 30 /* Channel 10 Done */ +#define INTR_DMA0_CH11_DONE 31 /* Channel 11 Done */ +#define INTR_DMA0_CH12_DONE 32 /* Channel 12 Done */ +#define INTR_DMA0_CH13_DONE 33 /* Channel 13 Done */ +#define INTR_DMA0_CH14_DONE 34 /* Channel 14 Done */ +#define INTR_DMA0_CH15_DONE 35 /* Channel 15 Done */ +#define INTR_SPORT_A_EVT 36 /* Channel A Event */ +#define INTR_SPORT_B_EVT 37 /* Channel B Event */ +#define INTR_CRYPT_EVT 38 /* Event */ +#define INTR_DMA0_CH24_DONE 39 /* Channel 24 Done */ +#define INTR_TMR2_EVT 40 /* Event */ +#define INTR_CLKG_XTAL_OSC_EVT 41 /* Crystal Oscillator Event */ +#define INTR_SPI1_EVT 42 /* Event */ +#define INTR_CLKG_PLL_EVT 43 /* PLL Event */ +#define INTR_RNG0_EVT 44 /* Event */ +#define INTR_BEEP_EVT 45 /* Event */ +#define INTR_ADC0_EVT 46 /* Event */ +#define INTR_DMA0_CH16_DONE 56 /* Channel 16 Done */ +#define INTR_DMA0_CH17_DONE 57 /* Channel 17 Done */ +#define INTR_DMA0_CH18_DONE 58 /* Channel 18 Done */ +#define INTR_DMA0_CH19_DONE 59 /* Channel 19 Done */ +#define INTR_DMA0_CH20_DONE 60 /* Channel 20 Done */ +#define INTR_DMA0_CH21_DONE 61 /* Channel 21 Done */ +#define INTR_DMA0_CH22_DONE 62 /* Channel 22 Done */ +#define INTR_DMA0_CH23_DONE 63 /* Channel 23 Done */ +#define INTR_UART1_EVT 66 /* Event */ +#define INTR_DMA0_CH25_DONE 67 /* Channel 25 Done */ +#define INTR_DMA0_CH26_DONE 68 /* Channel 26 Done */ +#define INTR_TMR_RGB_EVT 69 /* Event */ +#define INTR_CLKG_ROOTCLK_ERR 71 /* Root Clock Error */ + + +#if defined (_MISRA_RULES) +#pragma diag(pop) +#endif /* _MISRA_RULES */ + +#endif /* end ifndef _DEF_ADUCM4050_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_cdef.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_cdef.h new file mode 100755 index 0000000000..067c0386a3 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_cdef.h @@ -0,0 +1,788 @@ +/* ================================================================================ + + Project : ADuCM4050 + File : ADuCM4050_cdef.h + Description : C MMR Pointer Definitions + + Date : Feb 7, 2017 + + Copyright (c) 2014-2017 Analog Devices, Inc. All Rights Reserved. + This software is proprietary and confidential to Analog Devices, Inc. and + its licensors. + + This file was auto-generated. Do not make local changes to this file. + + ================================================================================ */ + +#ifndef _ADUCM4050_CDEF_H +#define _ADUCM4050_CDEF_H + +#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include +#endif /* _LANGUAGE_C */ + +/* pickup register bitfield and bit masks */ +#include "adi_ADuCM4050.h" + + +#ifndef __IO +#ifdef __cplusplus +#define __I volatile /* read-only */ +#define __C +#else +#define __I volatile /* read-only */ +#define __C const +#endif +#define __O volatile /* write-only */ +#define __IO volatile /* read-write */ +#endif +#if defined (_MISRA_RULES) +#pragma diag(push) +#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit") +#pragma diag(suppress:misra_rule_19_7:"ADI header allows function-like macros") +#pragma diag(suppress:misra_rule_19_13:"ADI headers can use the # and ## preprocessor operators") +#endif /* _MISRA_RULES */ + + +/* ================================================================================= + * General Purpose Timer (TMR0) + * ================================================================================= */ +#define pREG_TMR0_LOAD ((__IO uint16_t *) REG_TMR0_LOAD) /* 16-bit Load Value */ +#define pREG_TMR0_CURCNT ((__I __C uint16_t *) REG_TMR0_CURCNT) /* 16-bit Timer Value */ +#define pREG_TMR0_CTL ((__IO uint16_t *) REG_TMR0_CTL) /* Control */ +#define pREG_TMR0_CLRINT ((__O uint16_t *) REG_TMR0_CLRINT) /* Clear Interrupt */ +#define pREG_TMR0_CAPTURE ((__I __C uint16_t *) REG_TMR0_CAPTURE) /* Capture */ +#define pREG_TMR0_ALOAD ((__IO uint16_t *) REG_TMR0_ALOAD) /* 16-bit Load Value, Asynchronous */ +#define pREG_TMR0_ACURCNT ((__I __C uint16_t *) REG_TMR0_ACURCNT) /* 16-bit Timer Value, Asynchronous */ +#define pREG_TMR0_STAT ((__I __C uint16_t *) REG_TMR0_STAT) /* Status */ +#define pREG_TMR0_PWMCTL ((__IO uint16_t *) REG_TMR0_PWMCTL) /* PWM Control Register */ +#define pREG_TMR0_PWMMATCH ((__IO uint16_t *) REG_TMR0_PWMMATCH) /* PWM Match Value */ +#define pREG_TMR0_EVENTSELECT ((__IO uint16_t *) REG_TMR0_EVENTSELECT) /* Timer Event Selection Register */ + +/* ================================================================================= + * General Purpose Timer (TMR1) + * ================================================================================= */ +#define pREG_TMR1_LOAD ((__IO uint16_t *) REG_TMR1_LOAD) /* 16-bit Load Value */ +#define pREG_TMR1_CURCNT ((__I __C uint16_t *) REG_TMR1_CURCNT) /* 16-bit Timer Value */ +#define pREG_TMR1_CTL ((__IO uint16_t *) REG_TMR1_CTL) /* Control */ +#define pREG_TMR1_CLRINT ((__O uint16_t *) REG_TMR1_CLRINT) /* Clear Interrupt */ +#define pREG_TMR1_CAPTURE ((__I __C uint16_t *) REG_TMR1_CAPTURE) /* Capture */ +#define pREG_TMR1_ALOAD ((__IO uint16_t *) REG_TMR1_ALOAD) /* 16-bit Load Value, Asynchronous */ +#define pREG_TMR1_ACURCNT ((__I __C uint16_t *) REG_TMR1_ACURCNT) /* 16-bit Timer Value, Asynchronous */ +#define pREG_TMR1_STAT ((__I __C uint16_t *) REG_TMR1_STAT) /* Status */ +#define pREG_TMR1_PWMCTL ((__IO uint16_t *) REG_TMR1_PWMCTL) /* PWM Control Register */ +#define pREG_TMR1_PWMMATCH ((__IO uint16_t *) REG_TMR1_PWMMATCH) /* PWM Match Value */ +#define pREG_TMR1_EVENTSELECT ((__IO uint16_t *) REG_TMR1_EVENTSELECT) /* Timer Event Selection Register */ + +/* ================================================================================= + * General Purpose Timer (TMR2) + * ================================================================================= */ +#define pREG_TMR2_LOAD ((__IO uint16_t *) REG_TMR2_LOAD) /* 16-bit Load Value */ +#define pREG_TMR2_CURCNT ((__I __C uint16_t *) REG_TMR2_CURCNT) /* 16-bit Timer Value */ +#define pREG_TMR2_CTL ((__IO uint16_t *) REG_TMR2_CTL) /* Control */ +#define pREG_TMR2_CLRINT ((__O uint16_t *) REG_TMR2_CLRINT) /* Clear Interrupt */ +#define pREG_TMR2_CAPTURE ((__I __C uint16_t *) REG_TMR2_CAPTURE) /* Capture */ +#define pREG_TMR2_ALOAD ((__IO uint16_t *) REG_TMR2_ALOAD) /* 16-bit Load Value, Asynchronous */ +#define pREG_TMR2_ACURCNT ((__I __C uint16_t *) REG_TMR2_ACURCNT) /* 16-bit Timer Value, Asynchronous */ +#define pREG_TMR2_STAT ((__I __C uint16_t *) REG_TMR2_STAT) /* Status */ +#define pREG_TMR2_PWMCTL ((__IO uint16_t *) REG_TMR2_PWMCTL) /* PWM Control Register */ +#define pREG_TMR2_PWMMATCH ((__IO uint16_t *) REG_TMR2_PWMMATCH) /* PWM Match Value */ +#define pREG_TMR2_EVENTSELECT ((__IO uint16_t *) REG_TMR2_EVENTSELECT) /* Timer Event Selection Register */ + +/* ================================================================================= + * Timer_RGB with 3 PWM outputs (TMR_RGB) + * ================================================================================= */ +#define pREG_TMR_RGB_LOAD ((__IO uint16_t *) REG_TMR_RGB_LOAD) /* 16-bit load value */ +#define pREG_TMR_RGB_CURCNT ((__I __C uint16_t *) REG_TMR_RGB_CURCNT) /* 16-bit timer value */ +#define pREG_TMR_RGB_CTL ((__IO uint16_t *) REG_TMR_RGB_CTL) /* Control */ +#define pREG_TMR_RGB_CLRINT ((__O uint16_t *) REG_TMR_RGB_CLRINT) /* Clear interrupt */ +#define pREG_TMR_RGB_CAPTURE ((__I __C uint16_t *) REG_TMR_RGB_CAPTURE) /* Capture */ +#define pREG_TMR_RGB_ALOAD ((__IO uint16_t *) REG_TMR_RGB_ALOAD) /* 16-bit load value, asynchronous */ +#define pREG_TMR_RGB_ACURCNT ((__I __C uint16_t *) REG_TMR_RGB_ACURCNT) /* 16-bit timer value, asynchronous */ +#define pREG_TMR_RGB_STAT ((__I __C uint16_t *) REG_TMR_RGB_STAT) /* Status */ +#define pREG_TMR_RGB_PWM0CTL ((__IO uint16_t *) REG_TMR_RGB_PWM0CTL) /* PWM0 Control Register */ +#define pREG_TMR_RGB_PWM0MATCH ((__IO uint16_t *) REG_TMR_RGB_PWM0MATCH) /* PWM0 Match Value */ +#define pREG_TMR_RGB_EVENTSELECT ((__IO uint16_t *) REG_TMR_RGB_EVENTSELECT) /* Timer Event selection Register */ +#define pREG_TMR_RGB_PWM1CTL ((__IO uint16_t *) REG_TMR_RGB_PWM1CTL) /* PWM1 Control Register */ +#define pREG_TMR_RGB_PWM1MATCH ((__IO uint16_t *) REG_TMR_RGB_PWM1MATCH) /* PWM1 Match Value */ +#define pREG_TMR_RGB_PWM2CTL ((__IO uint16_t *) REG_TMR_RGB_PWM2CTL) /* PWM2 Control Register */ +#define pREG_TMR_RGB_PWM2MATCH ((__IO uint16_t *) REG_TMR_RGB_PWM2MATCH) /* PWM2 Match Value */ + +/* ================================================================================= + * Real-Time Clock (RTC0) + * ================================================================================= */ +#define pREG_RTC0_CR0 ((__IO uint16_t *) REG_RTC0_CR0) /* RTC Control 0 */ +#define pREG_RTC0_SR0 ((__IO uint16_t *) REG_RTC0_SR0) /* RTC Status 0 */ +#define pREG_RTC0_SR1 ((__I __C uint16_t *) REG_RTC0_SR1) /* RTC Status 1 */ +#define pREG_RTC0_CNT0 ((__IO uint16_t *) REG_RTC0_CNT0) /* RTC Count 0 */ +#define pREG_RTC0_CNT1 ((__IO uint16_t *) REG_RTC0_CNT1) /* RTC Count 1 */ +#define pREG_RTC0_ALM0 ((__IO uint16_t *) REG_RTC0_ALM0) /* RTC Alarm 0 */ +#define pREG_RTC0_ALM1 ((__IO uint16_t *) REG_RTC0_ALM1) /* RTC Alarm 1 */ +#define pREG_RTC0_TRM ((__IO uint16_t *) REG_RTC0_TRM) /* RTC Trim */ +#define pREG_RTC0_GWY ((__O uint16_t *) REG_RTC0_GWY) /* RTC Gateway */ +#define pREG_RTC0_CR1 ((__IO uint16_t *) REG_RTC0_CR1) /* RTC Control 1 */ +#define pREG_RTC0_SR2 ((__IO uint16_t *) REG_RTC0_SR2) /* RTC Status 2 */ +#define pREG_RTC0_SNAP0 ((__I __C uint16_t *) REG_RTC0_SNAP0) /* RTC Snapshot 0 */ +#define pREG_RTC0_SNAP1 ((__I __C uint16_t *) REG_RTC0_SNAP1) /* RTC Snapshot 1 */ +#define pREG_RTC0_SNAP2 ((__I __C uint16_t *) REG_RTC0_SNAP2) /* RTC Snapshot 2 */ +#define pREG_RTC0_MOD ((__I __C uint16_t *) REG_RTC0_MOD) /* RTC Modulo */ +#define pREG_RTC0_CNT2 ((__I __C uint16_t *) REG_RTC0_CNT2) /* RTC Count 2 */ +#define pREG_RTC0_ALM2 ((__IO uint16_t *) REG_RTC0_ALM2) /* RTC Alarm 2 */ +#define pREG_RTC0_SR3 ((__IO uint16_t *) REG_RTC0_SR3) /* RTC Status 3 */ +#define pREG_RTC0_CR2IC ((__IO uint16_t *) REG_RTC0_CR2IC) /* RTC Control 2 for Configuring Input Capture Channels */ +#define pREG_RTC0_CR3SS ((__IO uint16_t *) REG_RTC0_CR3SS) /* RTC Control 3 for Configuring SensorStrobe Channel */ +#define pREG_RTC0_CR4SS ((__IO uint16_t *) REG_RTC0_CR4SS) /* RTC Control 4 for Configuring SensorStrobe Channel */ +#define pREG_RTC0_SSMSK ((__IO uint16_t *) REG_RTC0_SSMSK) /* RTC Mask for SensorStrobe Channel */ +#define pREG_RTC0_IC2 ((__I __C uint16_t *) REG_RTC0_IC2) /* RTC Input Capture Channel 2 */ +#define pREG_RTC0_IC3 ((__I __C uint16_t *) REG_RTC0_IC3) /* RTC Input Capture Channel 3 */ +#define pREG_RTC0_IC4 ((__I __C uint16_t *) REG_RTC0_IC4) /* RTC Input Capture Channel 4 */ +#define pREG_RTC0_SS1 ((__IO uint16_t *) REG_RTC0_SS1) /* RTC SensorStrobe Channel 1 */ +#define pREG_RTC0_SS2 ((__IO uint16_t *) REG_RTC0_SS2) /* RTC SensorStrobe Channel 2 */ +#define pREG_RTC0_SS3 ((__IO uint16_t *) REG_RTC0_SS3) /* RTC SensorStrobe Channel 3 */ +#define pREG_RTC0_SS4 ((__IO uint16_t *) REG_RTC0_SS4) /* RTC SensorStrobe Channel 4 */ +#define pREG_RTC0_SR4 ((__I __C uint16_t *) REG_RTC0_SR4) /* RTC Status 4 */ +#define pREG_RTC0_SR5 ((__I __C uint16_t *) REG_RTC0_SR5) /* RTC Status 5 */ +#define pREG_RTC0_SR6 ((__I __C uint16_t *) REG_RTC0_SR6) /* RTC Status 6 */ +#define pREG_RTC0_SS1TGT ((__I __C uint16_t *) REG_RTC0_SS1TGT) /* RTC SensorStrobe Channel 1 Target */ +#define pREG_RTC0_FRZCNT ((__I __C uint16_t *) REG_RTC0_FRZCNT) /* RTC Freeze Count */ +#define pREG_RTC0_SS2TGT ((__I __C uint16_t *) REG_RTC0_SS2TGT) /* RTC SensorStrobe Channel 2 Target */ +#define pREG_RTC0_SS3TGT ((__I __C uint16_t *) REG_RTC0_SS3TGT) /* RTC SensorStrobe Channel 3 Target */ +#define pREG_RTC0_SS1LOWDUR ((__IO uint16_t *) REG_RTC0_SS1LOWDUR) /* RTC Auto-Reload Low Duration for SensorStrobe Channel 1 */ +#define pREG_RTC0_SS2LOWDUR ((__IO uint16_t *) REG_RTC0_SS2LOWDUR) /* RTC Auto-Reload Low Duration for SensorStrobe Channel 2 */ +#define pREG_RTC0_SS3LOWDUR ((__IO uint16_t *) REG_RTC0_SS3LOWDUR) /* RTC Auto-Reload Low Duration for SensorStrobe Channel 3 */ +#define pREG_RTC0_SS1HIGHDUR ((__IO uint16_t *) REG_RTC0_SS1HIGHDUR) /* RTC Auto-Reload High Duration for SensorStrobe Channel 1 */ +#define pREG_RTC0_SS2HIGHDUR ((__IO uint16_t *) REG_RTC0_SS2HIGHDUR) /* RTC Auto-Reload High Duration for SensorStrobe Channel 2 */ +#define pREG_RTC0_SS3HIGHDUR ((__IO uint16_t *) REG_RTC0_SS3HIGHDUR) /* RTC Auto-Reload High Duration for SensorStrobe Channel 3 */ +#define pREG_RTC0_SSMSKOT ((__IO uint16_t *) REG_RTC0_SSMSKOT) /* RTC Masks for SensorStrobe Channels on Time Control */ +#define pREG_RTC0_CR5SSS ((__IO uint16_t *) REG_RTC0_CR5SSS) /* RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling */ +#define pREG_RTC0_CR6SSS ((__IO uint16_t *) REG_RTC0_CR6SSS) /* RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge */ +#define pREG_RTC0_CR7SSS ((__IO uint16_t *) REG_RTC0_CR7SSS) /* RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity */ +#define pREG_RTC0_SR7 ((__IO uint16_t *) REG_RTC0_SR7) /* RTC Status 7 */ +#define pREG_RTC0_SR8 ((__I __C uint16_t *) REG_RTC0_SR8) /* RTC Status 8 */ +#define pREG_RTC0_SR9 ((__I __C uint16_t *) REG_RTC0_SR9) /* RTC Status 9 */ +#define pREG_RTC0_GPMUX0 ((__IO uint16_t *) REG_RTC0_GPMUX0) /* RTC GPIO Pin Mux Control Register 0 */ +#define pREG_RTC0_GPMUX1 ((__IO uint16_t *) REG_RTC0_GPMUX1) /* RTC GPIO Pin Mux Control Register 1 */ + +/* ================================================================================= + * Real-Time Clock (RTC1) + * ================================================================================= */ +#define pREG_RTC1_CR0 ((__IO uint16_t *) REG_RTC1_CR0) /* RTC Control 0 */ +#define pREG_RTC1_SR0 ((__IO uint16_t *) REG_RTC1_SR0) /* RTC Status 0 */ +#define pREG_RTC1_SR1 ((__I __C uint16_t *) REG_RTC1_SR1) /* RTC Status 1 */ +#define pREG_RTC1_CNT0 ((__IO uint16_t *) REG_RTC1_CNT0) /* RTC Count 0 */ +#define pREG_RTC1_CNT1 ((__IO uint16_t *) REG_RTC1_CNT1) /* RTC Count 1 */ +#define pREG_RTC1_ALM0 ((__IO uint16_t *) REG_RTC1_ALM0) /* RTC Alarm 0 */ +#define pREG_RTC1_ALM1 ((__IO uint16_t *) REG_RTC1_ALM1) /* RTC Alarm 1 */ +#define pREG_RTC1_TRM ((__IO uint16_t *) REG_RTC1_TRM) /* RTC Trim */ +#define pREG_RTC1_GWY ((__O uint16_t *) REG_RTC1_GWY) /* RTC Gateway */ +#define pREG_RTC1_CR1 ((__IO uint16_t *) REG_RTC1_CR1) /* RTC Control 1 */ +#define pREG_RTC1_SR2 ((__IO uint16_t *) REG_RTC1_SR2) /* RTC Status 2 */ +#define pREG_RTC1_SNAP0 ((__I __C uint16_t *) REG_RTC1_SNAP0) /* RTC Snapshot 0 */ +#define pREG_RTC1_SNAP1 ((__I __C uint16_t *) REG_RTC1_SNAP1) /* RTC Snapshot 1 */ +#define pREG_RTC1_SNAP2 ((__I __C uint16_t *) REG_RTC1_SNAP2) /* RTC Snapshot 2 */ +#define pREG_RTC1_MOD ((__I __C uint16_t *) REG_RTC1_MOD) /* RTC Modulo */ +#define pREG_RTC1_CNT2 ((__I __C uint16_t *) REG_RTC1_CNT2) /* RTC Count 2 */ +#define pREG_RTC1_ALM2 ((__IO uint16_t *) REG_RTC1_ALM2) /* RTC Alarm 2 */ +#define pREG_RTC1_SR3 ((__IO uint16_t *) REG_RTC1_SR3) /* RTC Status 3 */ +#define pREG_RTC1_CR2IC ((__IO uint16_t *) REG_RTC1_CR2IC) /* RTC Control 2 for Configuring Input Capture Channels */ +#define pREG_RTC1_CR3SS ((__IO uint16_t *) REG_RTC1_CR3SS) /* RTC Control 3 for Configuring SensorStrobe Channel */ +#define pREG_RTC1_CR4SS ((__IO uint16_t *) REG_RTC1_CR4SS) /* RTC Control 4 for Configuring SensorStrobe Channel */ +#define pREG_RTC1_SSMSK ((__IO uint16_t *) REG_RTC1_SSMSK) /* RTC Mask for SensorStrobe Channel */ +#define pREG_RTC1_IC2 ((__I __C uint16_t *) REG_RTC1_IC2) /* RTC Input Capture Channel 2 */ +#define pREG_RTC1_IC3 ((__I __C uint16_t *) REG_RTC1_IC3) /* RTC Input Capture Channel 3 */ +#define pREG_RTC1_IC4 ((__I __C uint16_t *) REG_RTC1_IC4) /* RTC Input Capture Channel 4 */ +#define pREG_RTC1_SS1 ((__IO uint16_t *) REG_RTC1_SS1) /* RTC SensorStrobe Channel 1 */ +#define pREG_RTC1_SS2 ((__IO uint16_t *) REG_RTC1_SS2) /* RTC SensorStrobe Channel 2 */ +#define pREG_RTC1_SS3 ((__IO uint16_t *) REG_RTC1_SS3) /* RTC SensorStrobe Channel 3 */ +#define pREG_RTC1_SS4 ((__IO uint16_t *) REG_RTC1_SS4) /* RTC SensorStrobe Channel 4 */ +#define pREG_RTC1_SR4 ((__I __C uint16_t *) REG_RTC1_SR4) /* RTC Status 4 */ +#define pREG_RTC1_SR5 ((__I __C uint16_t *) REG_RTC1_SR5) /* RTC Status 5 */ +#define pREG_RTC1_SR6 ((__I __C uint16_t *) REG_RTC1_SR6) /* RTC Status 6 */ +#define pREG_RTC1_SS1TGT ((__I __C uint16_t *) REG_RTC1_SS1TGT) /* RTC SensorStrobe Channel 1 Target */ +#define pREG_RTC1_FRZCNT ((__I __C uint16_t *) REG_RTC1_FRZCNT) /* RTC Freeze Count */ +#define pREG_RTC1_SS2TGT ((__I __C uint16_t *) REG_RTC1_SS2TGT) /* RTC SensorStrobe Channel 2 Target */ +#define pREG_RTC1_SS3TGT ((__I __C uint16_t *) REG_RTC1_SS3TGT) /* RTC SensorStrobe Channel 3 Target */ +#define pREG_RTC1_SS1LOWDUR ((__IO uint16_t *) REG_RTC1_SS1LOWDUR) /* RTC Auto-Reload Low Duration for SensorStrobe Channel 1 */ +#define pREG_RTC1_SS2LOWDUR ((__IO uint16_t *) REG_RTC1_SS2LOWDUR) /* RTC Auto-Reload Low Duration for SensorStrobe Channel 2 */ +#define pREG_RTC1_SS3LOWDUR ((__IO uint16_t *) REG_RTC1_SS3LOWDUR) /* RTC Auto-Reload Low Duration for SensorStrobe Channel 3 */ +#define pREG_RTC1_SS1HIGHDUR ((__IO uint16_t *) REG_RTC1_SS1HIGHDUR) /* RTC Auto-Reload High Duration for SensorStrobe Channel 1 */ +#define pREG_RTC1_SS2HIGHDUR ((__IO uint16_t *) REG_RTC1_SS2HIGHDUR) /* RTC Auto-Reload High Duration for SensorStrobe Channel 2 */ +#define pREG_RTC1_SS3HIGHDUR ((__IO uint16_t *) REG_RTC1_SS3HIGHDUR) /* RTC Auto-Reload High Duration for SensorStrobe Channel 3 */ +#define pREG_RTC1_SSMSKOT ((__IO uint16_t *) REG_RTC1_SSMSKOT) /* RTC Masks for SensorStrobe Channels on Time Control */ +#define pREG_RTC1_CR5SSS ((__IO uint16_t *) REG_RTC1_CR5SSS) /* RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling */ +#define pREG_RTC1_CR6SSS ((__IO uint16_t *) REG_RTC1_CR6SSS) /* RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge */ +#define pREG_RTC1_CR7SSS ((__IO uint16_t *) REG_RTC1_CR7SSS) /* RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity */ +#define pREG_RTC1_SR7 ((__IO uint16_t *) REG_RTC1_SR7) /* RTC Status 7 */ +#define pREG_RTC1_SR8 ((__I __C uint16_t *) REG_RTC1_SR8) /* RTC Status 8 */ +#define pREG_RTC1_SR9 ((__I __C uint16_t *) REG_RTC1_SR9) /* RTC Status 9 */ +#define pREG_RTC1_GPMUX0 ((__IO uint16_t *) REG_RTC1_GPMUX0) /* RTC GPIO Pin Mux Control Register 0 */ +#define pREG_RTC1_GPMUX1 ((__IO uint16_t *) REG_RTC1_GPMUX1) /* RTC GPIO Pin Mux Control Register 1 */ + +/* ================================================================================= + * System Identification and Debug Enable (SYS) + * ================================================================================= */ +#define pREG_SYS_ADIID ((__I __C uint16_t *) REG_SYS_ADIID) /* ADI Identification */ +#define pREG_SYS_CHIPID ((__I __C uint16_t *) REG_SYS_CHIPID) /* Chip Identifier */ +#define pREG_SYS_SWDEN ((__O uint16_t *) REG_SYS_SWDEN) /* Serial Wire Debug Enable */ + +/* ================================================================================= + * Watchdog Timer (WDT0) + * ================================================================================= */ +#define pREG_WDT0_LOAD ((__IO uint16_t *) REG_WDT0_LOAD) /* Load Value */ +#define pREG_WDT0_CCNT ((__I __C uint16_t *) REG_WDT0_CCNT) /* Current Count Value */ +#define pREG_WDT0_CTL ((__IO uint16_t *) REG_WDT0_CTL) /* Control */ +#define pREG_WDT0_RESTART ((__O uint16_t *) REG_WDT0_RESTART) /* Clear Interrupt */ +#define pREG_WDT0_STAT ((__I __C uint16_t *) REG_WDT0_STAT) /* Status */ + +/* ================================================================================= + * I2C Master/Slave (I2C0) + * ================================================================================= */ +#define pREG_I2C0_MCTL ((__IO uint16_t *) REG_I2C0_MCTL) /* Master Control */ +#define pREG_I2C0_MSTAT ((__IO uint16_t *) REG_I2C0_MSTAT) /* Master Status */ +#define pREG_I2C0_MRX ((__I __C uint16_t *) REG_I2C0_MRX) /* Master Receive Data */ +#define pREG_I2C0_MTX ((__IO uint16_t *) REG_I2C0_MTX) /* Master Transmit Data */ +#define pREG_I2C0_MRXCNT ((__IO uint16_t *) REG_I2C0_MRXCNT) /* Master Receive Data Count */ +#define pREG_I2C0_MCRXCNT ((__I __C uint16_t *) REG_I2C0_MCRXCNT) /* Master Current Receive Data Count */ +#define pREG_I2C0_ADDR1 ((__IO uint16_t *) REG_I2C0_ADDR1) /* Master Address Byte 1 */ +#define pREG_I2C0_ADDR2 ((__IO uint16_t *) REG_I2C0_ADDR2) /* Master Address Byte 2 */ +#define pREG_I2C0_BYT ((__IO uint16_t *) REG_I2C0_BYT) /* Start Byte */ +#define pREG_I2C0_DIV ((__IO uint16_t *) REG_I2C0_DIV) /* Serial Clock Period Divisor */ +#define pREG_I2C0_SCTL ((__IO uint16_t *) REG_I2C0_SCTL) /* Slave Control */ +#define pREG_I2C0_SSTAT ((__IO uint16_t *) REG_I2C0_SSTAT) /* Slave I2C Status/Error/IRQ */ +#define pREG_I2C0_SRX ((__I __C uint16_t *) REG_I2C0_SRX) /* Slave Receive */ +#define pREG_I2C0_STX ((__IO uint16_t *) REG_I2C0_STX) /* Slave Transmit */ +#define pREG_I2C0_ALT ((__IO uint16_t *) REG_I2C0_ALT) /* Hardware General Call ID */ +#define pREG_I2C0_ID0 ((__IO uint16_t *) REG_I2C0_ID0) /* First Slave Address Device ID */ +#define pREG_I2C0_ID1 ((__IO uint16_t *) REG_I2C0_ID1) /* Second Slave Address Device ID */ +#define pREG_I2C0_ID2 ((__IO uint16_t *) REG_I2C0_ID2) /* Third Slave Address Device ID */ +#define pREG_I2C0_ID3 ((__IO uint16_t *) REG_I2C0_ID3) /* Fourth Slave Address Device ID */ +#define pREG_I2C0_STAT ((__IO uint16_t *) REG_I2C0_STAT) /* Master and Slave FIFO Status */ +#define pREG_I2C0_SHCTL ((__O uint16_t *) REG_I2C0_SHCTL) /* Shared Control */ +#define pREG_I2C0_TCTL ((__IO uint16_t *) REG_I2C0_TCTL) /* Timing Control Register */ +#define pREG_I2C0_ASTRETCH_SCL ((__IO uint16_t *) REG_I2C0_ASTRETCH_SCL) /* Automatic Stretch SCL */ + +/* ================================================================================= + * Serial Peripheral Interface (SPI0) + * ================================================================================= */ +#define pREG_SPI0_STAT ((__IO uint16_t *) REG_SPI0_STAT) /* Status */ +#define pREG_SPI0_RX ((__I __C uint16_t *) REG_SPI0_RX) /* Receive */ +#define pREG_SPI0_TX ((__O uint16_t *) REG_SPI0_TX) /* Transmit */ +#define pREG_SPI0_DIV ((__IO uint16_t *) REG_SPI0_DIV) /* SPI Baud Rate Selection */ +#define pREG_SPI0_CTL ((__IO uint16_t *) REG_SPI0_CTL) /* SPI Configuration */ +#define pREG_SPI0_IEN ((__IO uint16_t *) REG_SPI0_IEN) /* SPI Interrupts Enable */ +#define pREG_SPI0_CNT ((__IO uint16_t *) REG_SPI0_CNT) /* Transfer Byte Count */ +#define pREG_SPI0_DMA ((__IO uint16_t *) REG_SPI0_DMA) /* SPI DMA Enable */ +#define pREG_SPI0_FIFO_STAT ((__I __C uint16_t *) REG_SPI0_FIFO_STAT) /* FIFO Status */ +#define pREG_SPI0_RD_CTL ((__IO uint16_t *) REG_SPI0_RD_CTL) /* Read Control */ +#define pREG_SPI0_FLOW_CTL ((__IO uint16_t *) REG_SPI0_FLOW_CTL) /* Flow Control */ +#define pREG_SPI0_WAIT_TMR ((__IO uint16_t *) REG_SPI0_WAIT_TMR) /* Wait Timer for Flow Control */ +#define pREG_SPI0_CS_CTL ((__IO uint16_t *) REG_SPI0_CS_CTL) /* Chip Select Control for Multi-slave Connections */ +#define pREG_SPI0_CS_OVERRIDE ((__IO uint16_t *) REG_SPI0_CS_OVERRIDE) /* Chip Select Override */ + +/* ================================================================================= + * Serial Peripheral Interface (SPI1) + * ================================================================================= */ +#define pREG_SPI1_STAT ((__IO uint16_t *) REG_SPI1_STAT) /* Status */ +#define pREG_SPI1_RX ((__I __C uint16_t *) REG_SPI1_RX) /* Receive */ +#define pREG_SPI1_TX ((__O uint16_t *) REG_SPI1_TX) /* Transmit */ +#define pREG_SPI1_DIV ((__IO uint16_t *) REG_SPI1_DIV) /* SPI Baud Rate Selection */ +#define pREG_SPI1_CTL ((__IO uint16_t *) REG_SPI1_CTL) /* SPI Configuration */ +#define pREG_SPI1_IEN ((__IO uint16_t *) REG_SPI1_IEN) /* SPI Interrupts Enable */ +#define pREG_SPI1_CNT ((__IO uint16_t *) REG_SPI1_CNT) /* Transfer Byte Count */ +#define pREG_SPI1_DMA ((__IO uint16_t *) REG_SPI1_DMA) /* SPI DMA Enable */ +#define pREG_SPI1_FIFO_STAT ((__I __C uint16_t *) REG_SPI1_FIFO_STAT) /* FIFO Status */ +#define pREG_SPI1_RD_CTL ((__IO uint16_t *) REG_SPI1_RD_CTL) /* Read Control */ +#define pREG_SPI1_FLOW_CTL ((__IO uint16_t *) REG_SPI1_FLOW_CTL) /* Flow Control */ +#define pREG_SPI1_WAIT_TMR ((__IO uint16_t *) REG_SPI1_WAIT_TMR) /* Wait Timer for Flow Control */ +#define pREG_SPI1_CS_CTL ((__IO uint16_t *) REG_SPI1_CS_CTL) /* Chip Select Control for Multi-slave Connections */ +#define pREG_SPI1_CS_OVERRIDE ((__IO uint16_t *) REG_SPI1_CS_OVERRIDE) /* Chip Select Override */ + +/* ================================================================================= + * Serial Peripheral Interface (SPI2) + * ================================================================================= */ +#define pREG_SPI2_STAT ((__IO uint16_t *) REG_SPI2_STAT) /* Status */ +#define pREG_SPI2_RX ((__I __C uint16_t *) REG_SPI2_RX) /* Receive */ +#define pREG_SPI2_TX ((__O uint16_t *) REG_SPI2_TX) /* Transmit */ +#define pREG_SPI2_DIV ((__IO uint16_t *) REG_SPI2_DIV) /* SPI Baud Rate Selection */ +#define pREG_SPI2_CTL ((__IO uint16_t *) REG_SPI2_CTL) /* SPI Configuration */ +#define pREG_SPI2_IEN ((__IO uint16_t *) REG_SPI2_IEN) /* SPI Interrupts Enable */ +#define pREG_SPI2_CNT ((__IO uint16_t *) REG_SPI2_CNT) /* Transfer Byte Count */ +#define pREG_SPI2_DMA ((__IO uint16_t *) REG_SPI2_DMA) /* SPI DMA Enable */ +#define pREG_SPI2_FIFO_STAT ((__I __C uint16_t *) REG_SPI2_FIFO_STAT) /* FIFO Status */ +#define pREG_SPI2_RD_CTL ((__IO uint16_t *) REG_SPI2_RD_CTL) /* Read Control */ +#define pREG_SPI2_FLOW_CTL ((__IO uint16_t *) REG_SPI2_FLOW_CTL) /* Flow Control */ +#define pREG_SPI2_WAIT_TMR ((__IO uint16_t *) REG_SPI2_WAIT_TMR) /* Wait Timer for Flow Control */ +#define pREG_SPI2_CS_CTL ((__IO uint16_t *) REG_SPI2_CS_CTL) /* Chip Select Control for Multi-slave Connections */ +#define pREG_SPI2_CS_OVERRIDE ((__IO uint16_t *) REG_SPI2_CS_OVERRIDE) /* Chip Select Override */ + +/* ================================================================================= + * (UART0) + * ================================================================================= */ +#define pREG_UART0_TX ((__O uint16_t *) REG_UART0_TX) /* Transmit Holding Register */ +#define pREG_UART0_RX ((__I __C uint16_t *) REG_UART0_RX) /* Receive Buffer Register */ +#define pREG_UART0_IEN ((__IO uint16_t *) REG_UART0_IEN) /* Interrupt Enable */ +#define pREG_UART0_IIR ((__I __C uint16_t *) REG_UART0_IIR) /* Interrupt ID */ +#define pREG_UART0_LCR ((__IO uint16_t *) REG_UART0_LCR) /* Line Control */ +#define pREG_UART0_MCR ((__IO uint16_t *) REG_UART0_MCR) /* Modem Control */ +#define pREG_UART0_LSR ((__I __C uint16_t *) REG_UART0_LSR) /* Line Status */ +#define pREG_UART0_MSR ((__I __C uint16_t *) REG_UART0_MSR) /* Modem Status */ +#define pREG_UART0_SCR ((__IO uint16_t *) REG_UART0_SCR) /* Scratch Buffer */ +#define pREG_UART0_FCR ((__IO uint16_t *) REG_UART0_FCR) /* FIFO Control */ +#define pREG_UART0_FBR ((__IO uint16_t *) REG_UART0_FBR) /* Fractional Baud Rate */ +#define pREG_UART0_DIV ((__IO uint16_t *) REG_UART0_DIV) /* Baud Rate Divider */ +#define pREG_UART0_LCR2 ((__IO uint16_t *) REG_UART0_LCR2) /* Second Line Control */ +#define pREG_UART0_CTL ((__IO uint16_t *) REG_UART0_CTL) /* UART Control Register */ +#define pREG_UART0_RFC ((__I __C uint16_t *) REG_UART0_RFC) /* RX FIFO Byte Count */ +#define pREG_UART0_TFC ((__I __C uint16_t *) REG_UART0_TFC) /* TX FIFO Byte Count */ +#define pREG_UART0_RSC ((__IO uint16_t *) REG_UART0_RSC) /* RS485 Half-duplex Control */ +#define pREG_UART0_ACR ((__IO uint16_t *) REG_UART0_ACR) /* Auto Baud Control */ +#define pREG_UART0_ASRL ((__I __C uint16_t *) REG_UART0_ASRL) /* Auto Baud Status (Low) */ +#define pREG_UART0_ASRH ((__I __C uint16_t *) REG_UART0_ASRH) /* Auto Baud Status (High) */ + +/* ================================================================================= + * (UART1) + * ================================================================================= */ +#define pREG_UART1_RX ((__I __C uint16_t *) REG_UART1_RX) /* Receive Buffer Register */ +#define pREG_UART1_TX ((__O uint16_t *) REG_UART1_TX) /* Transmit Holding Register */ +#define pREG_UART1_IEN ((__IO uint16_t *) REG_UART1_IEN) /* Interrupt Enable */ +#define pREG_UART1_IIR ((__I __C uint16_t *) REG_UART1_IIR) /* Interrupt ID */ +#define pREG_UART1_LCR ((__IO uint16_t *) REG_UART1_LCR) /* Line Control */ +#define pREG_UART1_MCR ((__IO uint16_t *) REG_UART1_MCR) /* Modem Control */ +#define pREG_UART1_LSR ((__I __C uint16_t *) REG_UART1_LSR) /* Line Status */ +#define pREG_UART1_MSR ((__I __C uint16_t *) REG_UART1_MSR) /* Modem Status */ +#define pREG_UART1_SCR ((__IO uint16_t *) REG_UART1_SCR) /* Scratch Buffer */ +#define pREG_UART1_FCR ((__IO uint16_t *) REG_UART1_FCR) /* FIFO Control */ +#define pREG_UART1_FBR ((__IO uint16_t *) REG_UART1_FBR) /* Fractional Baud Rate */ +#define pREG_UART1_DIV ((__IO uint16_t *) REG_UART1_DIV) /* Baud Rate Divider */ +#define pREG_UART1_LCR2 ((__IO uint16_t *) REG_UART1_LCR2) /* Second Line Control */ +#define pREG_UART1_CTL ((__IO uint16_t *) REG_UART1_CTL) /* UART Control Register */ +#define pREG_UART1_RFC ((__I __C uint16_t *) REG_UART1_RFC) /* RX FIFO Byte Count */ +#define pREG_UART1_TFC ((__I __C uint16_t *) REG_UART1_TFC) /* TX FIFO Byte Count */ +#define pREG_UART1_RSC ((__IO uint16_t *) REG_UART1_RSC) /* RS485 Half-duplex Control */ +#define pREG_UART1_ACR ((__IO uint16_t *) REG_UART1_ACR) /* Auto Baud Control */ +#define pREG_UART1_ASRL ((__I __C uint16_t *) REG_UART1_ASRL) /* Auto Baud Status (Low) */ +#define pREG_UART1_ASRH ((__I __C uint16_t *) REG_UART1_ASRH) /* Auto Baud Status (High) */ + +/* ================================================================================= + * Beeper Driver (BEEP0) + * ================================================================================= */ +#define pREG_BEEP0_CFG ((__IO uint16_t *) REG_BEEP0_CFG) /* Beeper Configuration */ +#define pREG_BEEP0_STAT ((__IO uint16_t *) REG_BEEP0_STAT) /* Beeper Status */ +#define pREG_BEEP0_TONEA ((__IO uint16_t *) REG_BEEP0_TONEA) /* Tone A Data */ +#define pREG_BEEP0_TONEB ((__IO uint16_t *) REG_BEEP0_TONEB) /* Tone B Data */ + +/* ================================================================================= + * (ADC0) + * ================================================================================= */ +#define pREG_ADC0_CFG ((__IO uint16_t *) REG_ADC0_CFG) /* ADC Configuration */ +#define pREG_ADC0_PWRUP ((__IO uint16_t *) REG_ADC0_PWRUP) /* ADC Power-up Time */ +#define pREG_ADC0_CAL_WORD ((__IO uint16_t *) REG_ADC0_CAL_WORD) /* Calibration Word */ +#define pREG_ADC0_CNV_CFG ((__IO uint16_t *) REG_ADC0_CNV_CFG) /* ADC Conversion Configuration */ +#define pREG_ADC0_CNV_TIME ((__IO uint16_t *) REG_ADC0_CNV_TIME) /* ADC Conversion Time */ +#define pREG_ADC0_AVG_CFG ((__IO uint16_t *) REG_ADC0_AVG_CFG) /* Averaging Configuration */ +#define pREG_ADC0_IRQ_EN ((__IO uint16_t *) REG_ADC0_IRQ_EN) /* Interrupt Enable */ +#define pREG_ADC0_STAT ((__IO uint16_t *) REG_ADC0_STAT) /* ADC Status */ +#define pREG_ADC0_OVF ((__IO uint16_t *) REG_ADC0_OVF) /* Overflow of Output Registers */ +#define pREG_ADC0_ALERT ((__IO uint16_t *) REG_ADC0_ALERT) /* Alert Indication */ +#define pREG_ADC0_CH0_OUT ((__I __C uint16_t *) REG_ADC0_CH0_OUT) /* Conversion Result Channel 0 */ +#define pREG_ADC0_CH1_OUT ((__I __C uint16_t *) REG_ADC0_CH1_OUT) /* Conversion Result Channel 1 */ +#define pREG_ADC0_CH2_OUT ((__I __C uint16_t *) REG_ADC0_CH2_OUT) /* Conversion Result Channel 2 */ +#define pREG_ADC0_CH3_OUT ((__I __C uint16_t *) REG_ADC0_CH3_OUT) /* Conversion Result Channel 3 */ +#define pREG_ADC0_CH4_OUT ((__I __C uint16_t *) REG_ADC0_CH4_OUT) /* Conversion Result Channel 4 */ +#define pREG_ADC0_CH5_OUT ((__I __C uint16_t *) REG_ADC0_CH5_OUT) /* Conversion Result Channel 5 */ +#define pREG_ADC0_CH6_OUT ((__I __C uint16_t *) REG_ADC0_CH6_OUT) /* Conversion Result Channel 6 */ +#define pREG_ADC0_CH7_OUT ((__I __C uint16_t *) REG_ADC0_CH7_OUT) /* Conversion Result Channel 7 */ +#define pREG_ADC0_BAT_OUT ((__I __C uint16_t *) REG_ADC0_BAT_OUT) /* Battery Monitoring Result */ +#define pREG_ADC0_TMP_OUT ((__I __C uint16_t *) REG_ADC0_TMP_OUT) /* Temperature Result */ +#define pREG_ADC0_TMP2_OUT ((__I __C uint16_t *) REG_ADC0_TMP2_OUT) /* Temperature Result 2 */ +#define pREG_ADC0_DMA_OUT ((__I __C uint16_t *) REG_ADC0_DMA_OUT) /* DMA Output Register */ +#define pREG_ADC0_LIM0_LO ((__IO uint16_t *) REG_ADC0_LIM0_LO) /* Channel 0 Low Limit */ +#define pREG_ADC0_LIM0_HI ((__IO uint16_t *) REG_ADC0_LIM0_HI) /* Channel 0 High Limit */ +#define pREG_ADC0_HYS0 ((__IO uint16_t *) REG_ADC0_HYS0) /* Channel 0 Hysteresis */ +#define pREG_ADC0_LIM1_LO ((__IO uint16_t *) REG_ADC0_LIM1_LO) /* Channel 1 Low Limit */ +#define pREG_ADC0_LIM1_HI ((__IO uint16_t *) REG_ADC0_LIM1_HI) /* Channel 1 High Limit */ +#define pREG_ADC0_HYS1 ((__IO uint16_t *) REG_ADC0_HYS1) /* Channel 1 Hysteresis */ +#define pREG_ADC0_LIM2_LO ((__IO uint16_t *) REG_ADC0_LIM2_LO) /* Channel 2 Low Limit */ +#define pREG_ADC0_LIM2_HI ((__IO uint16_t *) REG_ADC0_LIM2_HI) /* Channel 2 High Limit */ +#define pREG_ADC0_HYS2 ((__IO uint16_t *) REG_ADC0_HYS2) /* Channel 2 Hysteresis */ +#define pREG_ADC0_LIM3_LO ((__IO uint16_t *) REG_ADC0_LIM3_LO) /* Channel 3 Low Limit */ +#define pREG_ADC0_LIM3_HI ((__IO uint16_t *) REG_ADC0_LIM3_HI) /* Channel 3 High Limit */ +#define pREG_ADC0_HYS3 ((__IO uint16_t *) REG_ADC0_HYS3) /* Channel 3 Hysteresis */ +#define pREG_ADC0_CFG1 ((__IO uint16_t *) REG_ADC0_CFG1) /* Reference Buffer Low Power Mode */ + +/* ================================================================================= + * DMA (DMA0) + * ================================================================================= */ +#define pREG_DMA0_STAT ((__I __C uint32_t *) REG_DMA0_STAT) /* DMA Status */ +#define pREG_DMA0_CFG ((__O uint32_t *) REG_DMA0_CFG) /* DMA Configuration */ +#define pREG_DMA0_PDBPTR ((__IO uint32_t *) REG_DMA0_PDBPTR) /* DMA Channel Primary Control Database Pointer */ +#define pREG_DMA0_ADBPTR ((__I __C uint32_t *) REG_DMA0_ADBPTR) /* DMA Channel Alternate Control Database Pointer */ +#define pREG_DMA0_SWREQ ((__O uint32_t *) REG_DMA0_SWREQ) /* DMA Channel Software Request */ +#define pREG_DMA0_RMSK_SET ((__IO uint32_t *) REG_DMA0_RMSK_SET) /* DMA Channel Request Mask Set */ +#define pREG_DMA0_RMSK_CLR ((__O uint32_t *) REG_DMA0_RMSK_CLR) /* DMA Channel Request Mask Clear */ +#define pREG_DMA0_EN_SET ((__IO uint32_t *) REG_DMA0_EN_SET) /* DMA Channel Enable Set */ +#define pREG_DMA0_EN_CLR ((__O uint32_t *) REG_DMA0_EN_CLR) /* DMA Channel Enable Clear */ +#define pREG_DMA0_ALT_SET ((__IO uint32_t *) REG_DMA0_ALT_SET) /* DMA Channel Primary Alternate Set */ +#define pREG_DMA0_ALT_CLR ((__O uint32_t *) REG_DMA0_ALT_CLR) /* DMA Channel Primary Alternate Clear */ +#define pREG_DMA0_PRI_SET ((__O uint32_t *) REG_DMA0_PRI_SET) /* DMA Channel Priority Set */ +#define pREG_DMA0_PRI_CLR ((__O uint32_t *) REG_DMA0_PRI_CLR) /* DMA Channel Priority Clear */ +#define pREG_DMA0_ERRCHNL_CLR ((__IO uint32_t *) REG_DMA0_ERRCHNL_CLR) /* DMA per Channel Error Clear */ +#define pREG_DMA0_ERR_CLR ((__IO uint32_t *) REG_DMA0_ERR_CLR) /* DMA Bus Error Clear */ +#define pREG_DMA0_INVALIDDESC_CLR ((__IO uint32_t *) REG_DMA0_INVALIDDESC_CLR) /* DMA per Channel Invalid Descriptor Clear */ +#define pREG_DMA0_BS_SET ((__IO uint32_t *) REG_DMA0_BS_SET) /* DMA Channel Bytes Swap Enable Set */ +#define pREG_DMA0_BS_CLR ((__O uint32_t *) REG_DMA0_BS_CLR) /* DMA Channel Bytes Swap Enable Clear */ +#define pREG_DMA0_SRCADDR_SET ((__IO uint32_t *) REG_DMA0_SRCADDR_SET) /* DMA Channel Source Address Decrement Enable Set */ +#define pREG_DMA0_SRCADDR_CLR ((__O uint32_t *) REG_DMA0_SRCADDR_CLR) /* DMA Channel Source Address Decrement Enable Clear */ +#define pREG_DMA0_DSTADDR_SET ((__IO uint32_t *) REG_DMA0_DSTADDR_SET) /* DMA Channel Destination Address Decrement Enable Set */ +#define pREG_DMA0_DSTADDR_CLR ((__O uint32_t *) REG_DMA0_DSTADDR_CLR) /* DMA Channel Destination Address Decrement Enable Clear */ +#define pREG_DMA0_REVID ((__I __C uint32_t *) REG_DMA0_REVID) /* DMA Controller Revision ID */ + +/* ================================================================================= + * Flash Controller (FLCC0) + * ================================================================================= */ +#define pREG_FLCC0_STAT ((__IO uint32_t *) REG_FLCC0_STAT) /* Status */ +#define pREG_FLCC0_IEN ((__IO uint32_t *) REG_FLCC0_IEN) /* Interrupt Enable */ +#define pREG_FLCC0_CMD ((__IO uint32_t *) REG_FLCC0_CMD) /* Command */ +#define pREG_FLCC0_KH_ADDR ((__IO uint32_t *) REG_FLCC0_KH_ADDR) /* Write Address */ +#define pREG_FLCC0_KH_DATA0 ((__IO uint32_t *) REG_FLCC0_KH_DATA0) /* Write Lower Data */ +#define pREG_FLCC0_KH_DATA1 ((__IO uint32_t *) REG_FLCC0_KH_DATA1) /* Write Upper Data */ +#define pREG_FLCC0_PAGE_ADDR0 ((__IO uint32_t *) REG_FLCC0_PAGE_ADDR0) /* Lower Page Address */ +#define pREG_FLCC0_PAGE_ADDR1 ((__IO uint32_t *) REG_FLCC0_PAGE_ADDR1) /* Upper Page Address */ +#define pREG_FLCC0_KEY ((__O uint32_t *) REG_FLCC0_KEY) /* Key */ +#define pREG_FLCC0_WR_ABORT_ADDR ((__I __C uint32_t *) REG_FLCC0_WR_ABORT_ADDR) /* Write Abort Address */ +#define pREG_FLCC0_WRPROT ((__IO uint32_t *) REG_FLCC0_WRPROT) /* Write Protection */ +#define pREG_FLCC0_SIGNATURE ((__I __C uint32_t *) REG_FLCC0_SIGNATURE) /* Signature */ +#define pREG_FLCC0_UCFG ((__IO uint32_t *) REG_FLCC0_UCFG) /* User Configuration */ +#define pREG_FLCC0_TIME_PARAM0 ((__IO uint32_t *) REG_FLCC0_TIME_PARAM0) /* Time Parameter 0 */ +#define pREG_FLCC0_TIME_PARAM1 ((__IO uint32_t *) REG_FLCC0_TIME_PARAM1) /* Time Parameter 1 */ +#define pREG_FLCC0_ABORT_EN_LO ((__IO uint32_t *) REG_FLCC0_ABORT_EN_LO) /* IRQ Abort Enable (Lower Bits) */ +#define pREG_FLCC0_ABORT_EN_HI ((__IO uint32_t *) REG_FLCC0_ABORT_EN_HI) /* IRQ Abort Enable (Upper Bits) */ +#define pREG_FLCC0_ECC_CFG ((__IO uint32_t *) REG_FLCC0_ECC_CFG) /* ECC Configuration */ +#define pREG_FLCC0_ECC_ADDR ((__I __C uint32_t *) REG_FLCC0_ECC_ADDR) /* ECC Status (Address) */ +#define pREG_FLCC0_POR_SEC ((__IO uint32_t *) REG_FLCC0_POR_SEC) /* Flash Security */ +#define pREG_FLCC0_VOL_CFG ((__IO uint32_t *) REG_FLCC0_VOL_CFG) /* Volatile Flash Configuration */ + +/* ================================================================================= + * Cache Controller (FLCC0_CACHE) + * ================================================================================= */ +#define pREG_FLCC0_CACHE_STAT ((__I __C uint32_t *) REG_FLCC0_CACHE_STAT) /* Cache Status Register */ +#define pREG_FLCC0_CACHE_SETUP ((__IO uint32_t *) REG_FLCC0_CACHE_SETUP) /* Cache Setup Register */ +#define pREG_FLCC0_CACHE_KEY ((__O uint32_t *) REG_FLCC0_CACHE_KEY) /* Cache Key Register */ + +/* ================================================================================= + * (GPIO0) + * ================================================================================= */ +#define pREG_GPIO0_CFG ((__IO uint32_t *) REG_GPIO0_CFG) /* Port Configuration */ +#define pREG_GPIO0_OEN ((__IO uint16_t *) REG_GPIO0_OEN) /* Port Output Enable */ +#define pREG_GPIO0_PE ((__IO uint16_t *) REG_GPIO0_PE) /* Port Output Pull-up/Pull-down Enable */ +#define pREG_GPIO0_IEN ((__IO uint16_t *) REG_GPIO0_IEN) /* Port Input Path Enable */ +#define pREG_GPIO0_IN ((__I __C uint16_t *) REG_GPIO0_IN) /* Port Registered Data Input */ +#define pREG_GPIO0_OUT ((__IO uint16_t *) REG_GPIO0_OUT) /* Port Data Output */ +#define pREG_GPIO0_SET ((__O uint16_t *) REG_GPIO0_SET) /* Port Data Out Set */ +#define pREG_GPIO0_CLR ((__O uint16_t *) REG_GPIO0_CLR) /* Port Data Out Clear */ +#define pREG_GPIO0_TGL ((__O uint16_t *) REG_GPIO0_TGL) /* Port Pin Toggle */ +#define pREG_GPIO0_POL ((__IO uint16_t *) REG_GPIO0_POL) /* Port Interrupt Polarity */ +#define pREG_GPIO0_IENA ((__IO uint16_t *) REG_GPIO0_IENA) /* Port Interrupt A Enable */ +#define pREG_GPIO0_IENB ((__IO uint16_t *) REG_GPIO0_IENB) /* Port Interrupt B Enable */ +#define pREG_GPIO0_INT ((__IO uint16_t *) REG_GPIO0_INT) /* Port Interrupt Status */ +#define pREG_GPIO0_DS ((__IO uint16_t *) REG_GPIO0_DS) /* Port Drive Strength Select */ + +/* ================================================================================= + * (GPIO1) + * ================================================================================= */ +#define pREG_GPIO1_CFG ((__IO uint32_t *) REG_GPIO1_CFG) /* Port Configuration */ +#define pREG_GPIO1_OEN ((__IO uint16_t *) REG_GPIO1_OEN) /* Port Output Enable */ +#define pREG_GPIO1_PE ((__IO uint16_t *) REG_GPIO1_PE) /* Port Output Pull-up/Pull-down Enable */ +#define pREG_GPIO1_IEN ((__IO uint16_t *) REG_GPIO1_IEN) /* Port Input Path Enable */ +#define pREG_GPIO1_IN ((__I __C uint16_t *) REG_GPIO1_IN) /* Port Registered Data Input */ +#define pREG_GPIO1_OUT ((__IO uint16_t *) REG_GPIO1_OUT) /* Port Data Output */ +#define pREG_GPIO1_SET ((__O uint16_t *) REG_GPIO1_SET) /* Port Data Out Set */ +#define pREG_GPIO1_CLR ((__O uint16_t *) REG_GPIO1_CLR) /* Port Data Out Clear */ +#define pREG_GPIO1_TGL ((__O uint16_t *) REG_GPIO1_TGL) /* Port Pin Toggle */ +#define pREG_GPIO1_POL ((__IO uint16_t *) REG_GPIO1_POL) /* Port Interrupt Polarity */ +#define pREG_GPIO1_IENA ((__IO uint16_t *) REG_GPIO1_IENA) /* Port Interrupt A Enable */ +#define pREG_GPIO1_IENB ((__IO uint16_t *) REG_GPIO1_IENB) /* Port Interrupt B Enable */ +#define pREG_GPIO1_INT ((__IO uint16_t *) REG_GPIO1_INT) /* Port Interrupt Status */ +#define pREG_GPIO1_DS ((__IO uint16_t *) REG_GPIO1_DS) /* Port Drive Strength Select */ + +/* ================================================================================= + * (GPIO2) + * ================================================================================= */ +#define pREG_GPIO2_CFG ((__IO uint32_t *) REG_GPIO2_CFG) /* Port Configuration */ +#define pREG_GPIO2_OEN ((__IO uint16_t *) REG_GPIO2_OEN) /* Port Output Enable */ +#define pREG_GPIO2_PE ((__IO uint16_t *) REG_GPIO2_PE) /* Port Output Pull-up/Pull-down Enable */ +#define pREG_GPIO2_IEN ((__IO uint16_t *) REG_GPIO2_IEN) /* Port Input Path Enable */ +#define pREG_GPIO2_IN ((__I __C uint16_t *) REG_GPIO2_IN) /* Port Registered Data Input */ +#define pREG_GPIO2_OUT ((__IO uint16_t *) REG_GPIO2_OUT) /* Port Data Output */ +#define pREG_GPIO2_SET ((__O uint16_t *) REG_GPIO2_SET) /* Port Data Out Set */ +#define pREG_GPIO2_CLR ((__O uint16_t *) REG_GPIO2_CLR) /* Port Data Out Clear */ +#define pREG_GPIO2_TGL ((__O uint16_t *) REG_GPIO2_TGL) /* Port Pin Toggle */ +#define pREG_GPIO2_POL ((__IO uint16_t *) REG_GPIO2_POL) /* Port Interrupt Polarity */ +#define pREG_GPIO2_IENA ((__IO uint16_t *) REG_GPIO2_IENA) /* Port Interrupt A Enable */ +#define pREG_GPIO2_IENB ((__IO uint16_t *) REG_GPIO2_IENB) /* Port Interrupt B Enable */ +#define pREG_GPIO2_INT ((__IO uint16_t *) REG_GPIO2_INT) /* Port Interrupt Status */ +#define pREG_GPIO2_DS ((__IO uint16_t *) REG_GPIO2_DS) /* Port Drive Strength Select */ + +/* ================================================================================= + * (GPIO3) + * ================================================================================= */ +#define pREG_GPIO3_CFG ((__IO uint32_t *) REG_GPIO3_CFG) /* Port Configuration */ +#define pREG_GPIO3_OEN ((__IO uint16_t *) REG_GPIO3_OEN) /* Port Output Enable */ +#define pREG_GPIO3_PE ((__IO uint16_t *) REG_GPIO3_PE) /* Port Output Pull-up/Pull-down Enable */ +#define pREG_GPIO3_IEN ((__IO uint16_t *) REG_GPIO3_IEN) /* Port Input Path Enable */ +#define pREG_GPIO3_IN ((__I __C uint16_t *) REG_GPIO3_IN) /* Port Registered Data Input */ +#define pREG_GPIO3_OUT ((__IO uint16_t *) REG_GPIO3_OUT) /* Port Data Output */ +#define pREG_GPIO3_SET ((__O uint16_t *) REG_GPIO3_SET) /* Port Data Out Set */ +#define pREG_GPIO3_CLR ((__O uint16_t *) REG_GPIO3_CLR) /* Port Data Out Clear */ +#define pREG_GPIO3_TGL ((__O uint16_t *) REG_GPIO3_TGL) /* Port Pin Toggle */ +#define pREG_GPIO3_POL ((__IO uint16_t *) REG_GPIO3_POL) /* Port Interrupt Polarity */ +#define pREG_GPIO3_IENA ((__IO uint16_t *) REG_GPIO3_IENA) /* Port Interrupt A Enable */ +#define pREG_GPIO3_IENB ((__IO uint16_t *) REG_GPIO3_IENB) /* Port Interrupt B Enable */ +#define pREG_GPIO3_INT ((__IO uint16_t *) REG_GPIO3_INT) /* Port Interrupt Status */ +#define pREG_GPIO3_DS ((__IO uint16_t *) REG_GPIO3_DS) /* Port Drive Strength Select */ + +/* ================================================================================= + * Serial Port (SPORT0) + * ================================================================================= */ +#define pREG_SPORT0_CTL_A ((__IO uint32_t *) REG_SPORT0_CTL_A) /* Half SPORT 'A' Control Register */ +#define pREG_SPORT0_DIV_A ((__IO uint32_t *) REG_SPORT0_DIV_A) /* Half SPORT 'A' Divisor Register */ +#define pREG_SPORT0_IEN_A ((__IO uint32_t *) REG_SPORT0_IEN_A) /* Half SPORT A's Interrupt Enable register */ +#define pREG_SPORT0_STAT_A ((__IO uint32_t *) REG_SPORT0_STAT_A) /* Half SPORT 'A' Status register */ +#define pREG_SPORT0_NUMTRAN_A ((__IO uint32_t *) REG_SPORT0_NUMTRAN_A) /* Half SPORT A Number of transfers register */ +#define pREG_SPORT0_CNVT_A ((__IO uint32_t *) REG_SPORT0_CNVT_A) /* Half SPORT 'A' CNV width */ +#define pREG_SPORT0_TX_A ((__O uint32_t *) REG_SPORT0_TX_A) /* Half SPORT 'A' Tx Buffer Register */ +#define pREG_SPORT0_RX_A ((__I __C uint32_t *) REG_SPORT0_RX_A) /* Half SPORT 'A' Rx Buffer Register */ +#define pREG_SPORT0_CTL_B ((__IO uint32_t *) REG_SPORT0_CTL_B) /* Half SPORT 'B' Control Register */ +#define pREG_SPORT0_DIV_B ((__IO uint32_t *) REG_SPORT0_DIV_B) /* Half SPORT 'B' Divisor Register */ +#define pREG_SPORT0_IEN_B ((__IO uint32_t *) REG_SPORT0_IEN_B) /* Half SPORT B's Interrupt Enable register */ +#define pREG_SPORT0_STAT_B ((__IO uint32_t *) REG_SPORT0_STAT_B) /* Half SPORT 'B' Status register */ +#define pREG_SPORT0_NUMTRAN_B ((__IO uint32_t *) REG_SPORT0_NUMTRAN_B) /* Half SPORT B Number of transfers register */ +#define pREG_SPORT0_CNVT_B ((__IO uint32_t *) REG_SPORT0_CNVT_B) /* Half SPORT 'B' CNV width register */ +#define pREG_SPORT0_TX_B ((__O uint32_t *) REG_SPORT0_TX_B) /* Half SPORT 'B' Tx Buffer Register */ +#define pREG_SPORT0_RX_B ((__I __C uint32_t *) REG_SPORT0_RX_B) /* Half SPORT 'B' Rx Buffer Register */ + +/* ================================================================================= + * CRC Accelerator (CRC0) + * ================================================================================= */ +#define pREG_CRC0_CTL ((__IO uint32_t *) REG_CRC0_CTL) /* CRC Control */ +#define pREG_CRC0_IPDATA ((__O uint32_t *) REG_CRC0_IPDATA) /* Input Data Word */ +#define pREG_CRC0_RESULT ((__IO uint32_t *) REG_CRC0_RESULT) /* CRC Result */ +#define pREG_CRC0_POLY ((__IO uint32_t *) REG_CRC0_POLY) /* Programmable CRC Polynomial */ +#define pREG_CRC0_IPBYTE ((__O uint8_t *) REG_CRC0_IPBYTE) /* Input Data Byte */ +#define pREG_CRC0_IPBITS0 ((__O uint8_t *) REG_CRC0_IPBITS0) /* Input Data Bits */ +#define pREG_CRC0_IPBITS1 ((__O uint8_t *) REG_CRC0_IPBITS1) /* Input Data Bits */ +#define pREG_CRC0_IPBITS2 ((__O uint8_t *) REG_CRC0_IPBITS2) /* Input Data Bits */ +#define pREG_CRC0_IPBITS3 ((__O uint8_t *) REG_CRC0_IPBITS3) /* Input Data Bits */ +#define pREG_CRC0_IPBITS4 ((__O uint8_t *) REG_CRC0_IPBITS4) /* Input Data Bits */ +#define pREG_CRC0_IPBITS5 ((__O uint8_t *) REG_CRC0_IPBITS5) /* Input Data Bits */ +#define pREG_CRC0_IPBITS6 ((__O uint8_t *) REG_CRC0_IPBITS6) /* Input Data Bits */ +#define pREG_CRC0_IPBITS7 ((__O uint8_t *) REG_CRC0_IPBITS7) /* Input Data Bits */ + +/* ================================================================================= + * Random Number Generator (RNG0) + * ================================================================================= */ +#define pREG_RNG0_CTL ((__IO uint16_t *) REG_RNG0_CTL) /* RNG Control Register */ +#define pREG_RNG0_LEN ((__IO uint16_t *) REG_RNG0_LEN) /* RNG Sample Length Register */ +#define pREG_RNG0_STAT ((__IO uint16_t *) REG_RNG0_STAT) /* RNG Status Register */ +#define pREG_RNG0_DATA ((__I __C uint32_t *) REG_RNG0_DATA) /* RNG Data Register */ +#define pREG_RNG0_OSCCNT ((__I __C uint32_t *) REG_RNG0_OSCCNT) /* Oscillator Count */ +#define pREG_RNG0_OSCDIFF0 ((__I __C int8_t *) REG_RNG0_OSCDIFF0) /* Oscillator Difference */ +#define pREG_RNG0_OSCDIFF1 ((__I __C int8_t *) REG_RNG0_OSCDIFF1) /* Oscillator Difference */ +#define pREG_RNG0_OSCDIFF2 ((__I __C int8_t *) REG_RNG0_OSCDIFF2) /* Oscillator Difference */ +#define pREG_RNG0_OSCDIFF3 ((__I __C int8_t *) REG_RNG0_OSCDIFF3) /* Oscillator Difference */ + +/* ================================================================================= + * Register Map for the Crypto Block (CRYPT0) + * ================================================================================= */ +#define pREG_CRYPT0_CFG ((__IO uint32_t *) REG_CRYPT0_CFG) /* Configuration Register */ +#define pREG_CRYPT0_DATALEN ((__IO uint32_t *) REG_CRYPT0_DATALEN) /* Payload Data Length */ +#define pREG_CRYPT0_PREFIXLEN ((__IO uint32_t *) REG_CRYPT0_PREFIXLEN) /* Authentication Data Length */ +#define pREG_CRYPT0_INTEN ((__IO uint32_t *) REG_CRYPT0_INTEN) /* Interrupt Enable Register */ +#define pREG_CRYPT0_STAT ((__IO uint32_t *) REG_CRYPT0_STAT) /* Status Register */ +#define pREG_CRYPT0_INBUF ((__O uint32_t *) REG_CRYPT0_INBUF) /* Input Buffer */ +#define pREG_CRYPT0_OUTBUF ((__I __C uint32_t *) REG_CRYPT0_OUTBUF) /* Output Buffer */ +#define pREG_CRYPT0_NONCE0 ((__IO uint32_t *) REG_CRYPT0_NONCE0) /* Nonce Bits [31:0] */ +#define pREG_CRYPT0_NONCE1 ((__IO uint32_t *) REG_CRYPT0_NONCE1) /* Nonce Bits [63:32] */ +#define pREG_CRYPT0_NONCE2 ((__IO uint32_t *) REG_CRYPT0_NONCE2) /* Nonce Bits [95:64] */ +#define pREG_CRYPT0_NONCE3 ((__IO uint32_t *) REG_CRYPT0_NONCE3) /* Nonce Bits [127:96] */ +#define pREG_CRYPT0_AESKEY0 ((__O uint32_t *) REG_CRYPT0_AESKEY0) /* AES Key Bits [31:0] */ +#define pREG_CRYPT0_AESKEY1 ((__O uint32_t *) REG_CRYPT0_AESKEY1) /* AES Key Bits [63:32] */ +#define pREG_CRYPT0_AESKEY2 ((__O uint32_t *) REG_CRYPT0_AESKEY2) /* AES Key Bits [95:64] */ +#define pREG_CRYPT0_AESKEY3 ((__O uint32_t *) REG_CRYPT0_AESKEY3) /* AES Key Bits [127:96] */ +#define pREG_CRYPT0_AESKEY4 ((__O uint32_t *) REG_CRYPT0_AESKEY4) /* AES Key Bits [159:128] */ +#define pREG_CRYPT0_AESKEY5 ((__O uint32_t *) REG_CRYPT0_AESKEY5) /* AES Key Bits [191:160] */ +#define pREG_CRYPT0_AESKEY6 ((__O uint32_t *) REG_CRYPT0_AESKEY6) /* AES Key Bits [223:192] */ +#define pREG_CRYPT0_AESKEY7 ((__O uint32_t *) REG_CRYPT0_AESKEY7) /* AES Key Bits [255:224] */ +#define pREG_CRYPT0_CNTRINIT ((__IO uint32_t *) REG_CRYPT0_CNTRINIT) /* Counter Initialization Vector */ +#define pREG_CRYPT0_SHAH0 ((__IO uint32_t *) REG_CRYPT0_SHAH0) /* SHA Bits [31:0] */ +#define pREG_CRYPT0_SHAH1 ((__IO uint32_t *) REG_CRYPT0_SHAH1) /* SHA Bits [63:32] */ +#define pREG_CRYPT0_SHAH2 ((__IO uint32_t *) REG_CRYPT0_SHAH2) /* SHA Bits [95:64] */ +#define pREG_CRYPT0_SHAH3 ((__IO uint32_t *) REG_CRYPT0_SHAH3) /* SHA Bits [127:96] */ +#define pREG_CRYPT0_SHAH4 ((__IO uint32_t *) REG_CRYPT0_SHAH4) /* SHA Bits [159:128] */ +#define pREG_CRYPT0_SHAH5 ((__IO uint32_t *) REG_CRYPT0_SHAH5) /* SHA Bits [191:160] */ +#define pREG_CRYPT0_SHAH6 ((__IO uint32_t *) REG_CRYPT0_SHAH6) /* SHA Bits [223:192] */ +#define pREG_CRYPT0_SHAH7 ((__IO uint32_t *) REG_CRYPT0_SHAH7) /* SHA Bits [255:224] */ +#define pREG_CRYPT0_SHA_LAST_WORD ((__IO uint32_t *) REG_CRYPT0_SHA_LAST_WORD) /* SHA Last Word and Valid Bits Information */ +#define pREG_CRYPT0_CCM_NUM_VALID_BYTES ((__IO uint32_t *) REG_CRYPT0_CCM_NUM_VALID_BYTES) /* NUM_VALID_BYTES */ +#define pREG_CRYPT0_PRKSTORCFG ((__IO uint32_t *) REG_CRYPT0_PRKSTORCFG) /* PRKSTOR Configuration */ +#define pREG_CRYPT0_KUW0 ((__O uint32_t *) REG_CRYPT0_KUW0) /* Key Wrap Unwrap Register 0 */ +#define pREG_CRYPT0_KUW1 ((__O uint32_t *) REG_CRYPT0_KUW1) /* Key Wrap Unwrap Register 1 */ +#define pREG_CRYPT0_KUW2 ((__O uint32_t *) REG_CRYPT0_KUW2) /* Key Wrap Unwrap Register 2 */ +#define pREG_CRYPT0_KUW3 ((__O uint32_t *) REG_CRYPT0_KUW3) /* Key Wrap Unwrap Register 3 */ +#define pREG_CRYPT0_KUW4 ((__O uint32_t *) REG_CRYPT0_KUW4) /* Key Wrap Unwrap Register 4 */ +#define pREG_CRYPT0_KUW5 ((__O uint32_t *) REG_CRYPT0_KUW5) /* Key Wrap Unwrap Register 5 */ +#define pREG_CRYPT0_KUW6 ((__O uint32_t *) REG_CRYPT0_KUW6) /* Key Wrap Unwrap Register 6 */ +#define pREG_CRYPT0_KUW7 ((__O uint32_t *) REG_CRYPT0_KUW7) /* Key Wrap Unwrap Register 7 */ +#define pREG_CRYPT0_KUW8 ((__O uint32_t *) REG_CRYPT0_KUW8) /* Key Wrap Unwrap Register 8 */ +#define pREG_CRYPT0_KUW9 ((__O uint32_t *) REG_CRYPT0_KUW9) /* Key Wrap Unwrap Register 9 */ +#define pREG_CRYPT0_KUW10 ((__O uint32_t *) REG_CRYPT0_KUW10) /* Key Wrap Unwrap Register 10 */ +#define pREG_CRYPT0_KUW11 ((__O uint32_t *) REG_CRYPT0_KUW11) /* Key Wrap Unwrap Register 11 */ +#define pREG_CRYPT0_KUW12 ((__O uint32_t *) REG_CRYPT0_KUW12) /* Key Wrap Unwrap Register 12 */ +#define pREG_CRYPT0_KUW13 ((__O uint32_t *) REG_CRYPT0_KUW13) /* Key Wrap Unwrap Register 13 */ +#define pREG_CRYPT0_KUW14 ((__O uint32_t *) REG_CRYPT0_KUW14) /* Key Wrap Unwrap Register 14 */ +#define pREG_CRYPT0_KUW15 ((__O uint32_t *) REG_CRYPT0_KUW15) /* Key Wrap Unwrap Register 15 */ +#define pREG_CRYPT0_KUWVALSTR1 ((__O uint32_t *) REG_CRYPT0_KUWVALSTR1) /* Key Wrap Unwrap Validation String [63:32] */ +#define pREG_CRYPT0_KUWVALSTR2 ((__O uint32_t *) REG_CRYPT0_KUWVALSTR2) /* Key Wrap Unwrap Validation String [31:0] */ + +/* ================================================================================= + * Power Management (PMG0) + * ================================================================================= */ +#define pREG_PMG0_IEN ((__IO uint32_t *) REG_PMG0_IEN) /* Power Supply Monitor Interrupt Enable */ +#define pREG_PMG0_PSM_STAT ((__IO uint32_t *) REG_PMG0_PSM_STAT) /* Power Supply Monitor Status */ +#define pREG_PMG0_PWRMOD ((__IO uint32_t *) REG_PMG0_PWRMOD) /* Power Mode Register */ +#define pREG_PMG0_PWRKEY ((__O uint32_t *) REG_PMG0_PWRKEY) /* Key Protection for PWRMOD and SRAMRET */ +#define pREG_PMG0_SHDN_STAT ((__I __C uint32_t *) REG_PMG0_SHDN_STAT) /* Shutdown Status Register */ +#define pREG_PMG0_SRAMRET ((__IO uint32_t *) REG_PMG0_SRAMRET) /* Control for Retention SRAM in Hibernate Mode */ +#define pREG_PMG0_TRIM ((__IO uint32_t *) REG_PMG0_TRIM) /* Trimming Bits */ +#define pREG_PMG0_RST_STAT ((__IO uint32_t *) REG_PMG0_RST_STAT) /* Reset Status */ +#define pREG_PMG0_CTL1 ((__IO uint32_t *) REG_PMG0_CTL1) /* HPBUCK Control */ + +/* ================================================================================= + * External interrupt configuration (XINT0) + * ================================================================================= */ +#define pREG_XINT0_CFG0 ((__IO uint32_t *) REG_XINT0_CFG0) /* External Interrupt configuration */ +#define pREG_XINT0_EXT_STAT ((__I __C uint32_t *) REG_XINT0_EXT_STAT) /* External Wakeup Interrupt Status register */ +#define pREG_XINT0_CLR ((__IO uint32_t *) REG_XINT0_CLR) /* External Interrupt clear */ +#define pREG_XINT0_NMICLR ((__IO uint32_t *) REG_XINT0_NMICLR) /* Non-maskable interrupt clear */ + +/* ================================================================================= + * Clocking (CLKG0_OSC) + * ================================================================================= */ +#define pREG_CLKG0_OSC_KEY ((__O uint32_t *) REG_CLKG0_OSC_KEY) /* Key Protection for OSCCTRL */ +#define pREG_CLKG0_OSC_CTL ((__IO uint32_t *) REG_CLKG0_OSC_CTL) /* Oscillator Control */ + +/* ================================================================================= + * Power Management (PMG0_TST) + * ================================================================================= */ +#define pREG_PMG0_TST_SRAM_CTL ((__IO uint32_t *) REG_PMG0_TST_SRAM_CTL) /* Control for SRAM Parity and Instruction SRAM */ +#define pREG_PMG0_TST_SRAM_INITSTAT ((__I __C uint32_t *) REG_PMG0_TST_SRAM_INITSTAT) /* Initialization Status Register */ +#define pREG_PMG0_TST_CLR_LATCH_GPIOS ((__O uint16_t *) REG_PMG0_TST_CLR_LATCH_GPIOS) /* Clear GPIO After Shutdown Mode */ +#define pREG_PMG0_TST_SCRPAD_IMG ((__IO uint32_t *) REG_PMG0_TST_SCRPAD_IMG) /* Scratch Pad Image */ +#define pREG_PMG0_TST_SCRPAD_3V_RD ((__I __C uint32_t *) REG_PMG0_TST_SCRPAD_3V_RD) /* Scratch Pad Saved in Battery Domain */ +#define pREG_PMG0_TST_FAST_SHT_WAKEUP ((__IO uint32_t *) REG_PMG0_TST_FAST_SHT_WAKEUP) /* Fast Shutdown Wake-up Enable */ + +/* ================================================================================= + * Clocking (CLKG0_CLK) + * ================================================================================= */ +#define pREG_CLKG0_CLK_CTL0 ((__IO uint32_t *) REG_CLKG0_CLK_CTL0) /* Misc Clock Settings */ +#define pREG_CLKG0_CLK_CTL1 ((__IO uint32_t *) REG_CLKG0_CLK_CTL1) /* Clock Dividers */ +#define pREG_CLKG0_CLK_CTL2 ((__IO uint32_t *) REG_CLKG0_CLK_CTL2) /* HF Oscillator Divided Clock Select */ +#define pREG_CLKG0_CLK_CTL3 ((__IO uint32_t *) REG_CLKG0_CLK_CTL3) /* System PLL */ +#define pREG_CLKG0_CLK_CTL5 ((__IO uint32_t *) REG_CLKG0_CLK_CTL5) /* User Clock Gating Control */ +#define pREG_CLKG0_CLK_STAT0 ((__IO uint32_t *) REG_CLKG0_CLK_STAT0) /* Clocking Status */ + +/* ================================================================================= + * Bus matrix (BUSM0) + * ================================================================================= */ +#define pREG_BUSM0_ARBIT0 ((__IO uint32_t *) REG_BUSM0_ARBIT0) /* Arbitration Priority Configuration for FLASH and SRAM0 */ +#define pREG_BUSM0_ARBIT1 ((__IO uint32_t *) REG_BUSM0_ARBIT1) /* Arbitration Priority Configuration for SRAM1 and SIP */ +#define pREG_BUSM0_ARBIT2 ((__IO uint32_t *) REG_BUSM0_ARBIT2) /* Arbitration Priority Configuration for APB32 and APB16 */ +#define pREG_BUSM0_ARBIT3 ((__IO uint32_t *) REG_BUSM0_ARBIT3) /* Arbitration Priority Configuration for APB16 priority for core and for DMA1 */ +#define pREG_BUSM0_ARBIT4 ((__IO uint32_t *) REG_BUSM0_ARBIT4) /* Arbitration Priority Configuration for SRAM1 and SIP */ + +/* ================================================================================= + * Parallel Test Interface (PTI0) + * ================================================================================= */ +#define pREG_PTI0_RST_ISR_STARTADDR ((__IO uint32_t *) REG_PTI0_RST_ISR_STARTADDR) /* Reset ISR Start Address */ +#define pREG_PTI0_RST_STACK_PTR ((__IO uint32_t *) REG_PTI0_RST_STACK_PTR) /* Reset Stack Pointer */ +#define pREG_PTI0_CTL ((__IO uint32_t *) REG_PTI0_CTL) /* Parallel Test Interface Control Register */ + +/* ================================================================================= + * Cortex-M3 Interrupt Controller (NVIC0) + * ================================================================================= */ +#define pREG_NVIC0_INTNUM ((__IO uint32_t *) REG_NVIC0_INTNUM) /* Interrupt Control Type */ +#define pREG_NVIC0_STKSTA ((__IO uint32_t *) REG_NVIC0_STKSTA) /* Systick Control and Status */ +#define pREG_NVIC0_STKLD ((__IO uint32_t *) REG_NVIC0_STKLD) /* Systick Reload Value */ +#define pREG_NVIC0_STKVAL ((__IO uint32_t *) REG_NVIC0_STKVAL) /* Systick Current Value */ +#define pREG_NVIC0_STKCAL ((__IO uint32_t *) REG_NVIC0_STKCAL) /* Systick Calibration Value */ +#define pREG_NVIC0_INTSETE0 ((__IO uint32_t *) REG_NVIC0_INTSETE0) /* IRQ0..31 Set_Enable */ +#define pREG_NVIC0_INTSETE1 ((__IO uint32_t *) REG_NVIC0_INTSETE1) /* IRQ32..63 Set_Enable */ +#define pREG_NVIC0_INTCLRE0 ((__IO uint32_t *) REG_NVIC0_INTCLRE0) /* IRQ0..31 Clear_Enable */ +#define pREG_NVIC0_INTCLRE1 ((__IO uint32_t *) REG_NVIC0_INTCLRE1) /* IRQ32..63 Clear_Enable */ +#define pREG_NVIC0_INTSETP0 ((__IO uint32_t *) REG_NVIC0_INTSETP0) /* IRQ0..31 Set_Pending */ +#define pREG_NVIC0_INTSETP1 ((__IO uint32_t *) REG_NVIC0_INTSETP1) /* IRQ32..63 Set_Pending */ +#define pREG_NVIC0_INTCLRP0 ((__IO uint32_t *) REG_NVIC0_INTCLRP0) /* IRQ0..31 Clear_Pending */ +#define pREG_NVIC0_INTCLRP1 ((__IO uint32_t *) REG_NVIC0_INTCLRP1) /* IRQ32..63 Clear_Pending */ +#define pREG_NVIC0_INTACT0 ((__IO uint32_t *) REG_NVIC0_INTACT0) /* IRQ0..31 Active Bit */ +#define pREG_NVIC0_INTACT1 ((__IO uint32_t *) REG_NVIC0_INTACT1) /* IRQ32..63 Active Bit */ +#define pREG_NVIC0_INTPRI0 ((__IO uint32_t *) REG_NVIC0_INTPRI0) /* IRQ0..3 Priority */ +#define pREG_NVIC0_INTPRI1 ((__IO uint32_t *) REG_NVIC0_INTPRI1) /* IRQ4..7 Priority */ +#define pREG_NVIC0_INTPRI2 ((__IO uint32_t *) REG_NVIC0_INTPRI2) /* IRQ8..11 Priority */ +#define pREG_NVIC0_INTPRI3 ((__IO uint32_t *) REG_NVIC0_INTPRI3) /* IRQ12..15 Priority */ +#define pREG_NVIC0_INTPRI4 ((__IO uint32_t *) REG_NVIC0_INTPRI4) /* IRQ16..19 Priority */ +#define pREG_NVIC0_INTPRI5 ((__IO uint32_t *) REG_NVIC0_INTPRI5) /* IRQ20..23 Priority */ +#define pREG_NVIC0_INTPRI6 ((__IO uint32_t *) REG_NVIC0_INTPRI6) /* IRQ24..27 Priority */ +#define pREG_NVIC0_INTPRI7 ((__IO uint32_t *) REG_NVIC0_INTPRI7) /* IRQ28..31 Priority */ +#define pREG_NVIC0_INTPRI8 ((__IO uint32_t *) REG_NVIC0_INTPRI8) /* IRQ32..35 Priority */ +#define pREG_NVIC0_INTPRI9 ((__IO uint32_t *) REG_NVIC0_INTPRI9) /* IRQ36..39 Priority */ +#define pREG_NVIC0_INTPRI10 ((__IO uint32_t *) REG_NVIC0_INTPRI10) /* IRQ40..43 Priority */ +#define pREG_NVIC0_INTCPID ((__IO uint32_t *) REG_NVIC0_INTCPID) /* CPUID Base */ +#define pREG_NVIC0_INTSTA ((__IO uint32_t *) REG_NVIC0_INTSTA) /* Interrupt Control State */ +#define pREG_NVIC0_INTVEC ((__IO uint32_t *) REG_NVIC0_INTVEC) /* Vector Table Offset */ +#define pREG_NVIC0_INTAIRC ((__IO uint32_t *) REG_NVIC0_INTAIRC) /* Application Interrupt/Reset Control */ +#define pREG_NVIC0_INTCON0 ((__IO uint16_t *) REG_NVIC0_INTCON0) /* System Control */ +#define pREG_NVIC0_INTCON1 ((__IO uint32_t *) REG_NVIC0_INTCON1) /* Configuration Control */ +#define pREG_NVIC0_INTSHPRIO0 ((__IO uint32_t *) REG_NVIC0_INTSHPRIO0) /* System Handlers 4-7 Priority */ +#define pREG_NVIC0_INTSHPRIO1 ((__IO uint32_t *) REG_NVIC0_INTSHPRIO1) /* System Handlers 8-11 Priority */ +#define pREG_NVIC0_INTSHPRIO3 ((__IO uint32_t *) REG_NVIC0_INTSHPRIO3) /* System Handlers 12-15 Priority */ +#define pREG_NVIC0_INTSHCSR ((__IO uint32_t *) REG_NVIC0_INTSHCSR) /* System Handler Control and State */ +#define pREG_NVIC0_INTCFSR ((__IO uint32_t *) REG_NVIC0_INTCFSR) /* Configurable Fault Status */ +#define pREG_NVIC0_INTHFSR ((__IO uint32_t *) REG_NVIC0_INTHFSR) /* Hard Fault Status */ +#define pREG_NVIC0_INTDFSR ((__IO uint32_t *) REG_NVIC0_INTDFSR) /* Debug Fault Status */ +#define pREG_NVIC0_INTMMAR ((__IO uint32_t *) REG_NVIC0_INTMMAR) /* Mem Manage Address */ +#define pREG_NVIC0_INTBFAR ((__IO uint32_t *) REG_NVIC0_INTBFAR) /* Bus Fault Address */ +#define pREG_NVIC0_INTAFSR ((__IO uint32_t *) REG_NVIC0_INTAFSR) /* Auxiliary Fault Status */ +#define pREG_NVIC0_INTPFR0 ((__IO uint32_t *) REG_NVIC0_INTPFR0) /* Processor Feature Register 0 */ +#define pREG_NVIC0_INTPFR1 ((__IO uint32_t *) REG_NVIC0_INTPFR1) /* Processor Feature Register 1 */ +#define pREG_NVIC0_INTDFR0 ((__IO uint32_t *) REG_NVIC0_INTDFR0) /* Debug Feature Register 0 */ +#define pREG_NVIC0_INTAFR0 ((__IO uint32_t *) REG_NVIC0_INTAFR0) /* Auxiliary Feature Register 0 */ +#define pREG_NVIC0_INTMMFR0 ((__IO uint32_t *) REG_NVIC0_INTMMFR0) /* Memory Model Feature Register 0 */ +#define pREG_NVIC0_INTMMFR1 ((__IO uint32_t *) REG_NVIC0_INTMMFR1) /* Memory Model Feature Register 1 */ +#define pREG_NVIC0_INTMMFR2 ((__IO uint32_t *) REG_NVIC0_INTMMFR2) /* Memory Model Feature Register 2 */ +#define pREG_NVIC0_INTMMFR3 ((__IO uint32_t *) REG_NVIC0_INTMMFR3) /* Memory Model Feature Register 3 */ +#define pREG_NVIC0_INTISAR0 ((__IO uint32_t *) REG_NVIC0_INTISAR0) /* ISA Feature Register 0 */ +#define pREG_NVIC0_INTISAR1 ((__IO uint32_t *) REG_NVIC0_INTISAR1) /* ISA Feature Register 1 */ +#define pREG_NVIC0_INTISAR2 ((__IO uint32_t *) REG_NVIC0_INTISAR2) /* ISA Feature Register 2 */ +#define pREG_NVIC0_INTISAR3 ((__IO uint32_t *) REG_NVIC0_INTISAR3) /* ISA Feature Register 3 */ +#define pREG_NVIC0_INTISAR4 ((__IO uint32_t *) REG_NVIC0_INTISAR4) /* ISA Feature Register 4 */ +#define pREG_NVIC0_INTTRGI ((__IO uint32_t *) REG_NVIC0_INTTRGI) /* Software Trigger Interrupt Register */ +#define pREG_NVIC0_INTPID4 ((__IO uint32_t *) REG_NVIC0_INTPID4) /* Peripheral Identification Register 4 */ +#define pREG_NVIC0_INTPID5 ((__IO uint32_t *) REG_NVIC0_INTPID5) /* Peripheral Identification Register 5 */ +#define pREG_NVIC0_INTPID6 ((__IO uint32_t *) REG_NVIC0_INTPID6) /* Peripheral Identification Register 6 */ +#define pREG_NVIC0_INTPID7 ((__IO uint32_t *) REG_NVIC0_INTPID7) /* Peripheral Identification Register 7 */ +#define pREG_NVIC0_INTPID0 ((__IO uint32_t *) REG_NVIC0_INTPID0) /* Peripheral Identification Bits7:0 */ +#define pREG_NVIC0_INTPID1 ((__IO uint32_t *) REG_NVIC0_INTPID1) /* Peripheral Identification Bits15:8 */ +#define pREG_NVIC0_INTPID2 ((__IO uint32_t *) REG_NVIC0_INTPID2) /* Peripheral Identification Bits16:23 */ +#define pREG_NVIC0_INTPID3 ((__IO uint32_t *) REG_NVIC0_INTPID3) /* Peripheral Identification Bits24:31 */ +#define pREG_NVIC0_INTCID0 ((__IO uint32_t *) REG_NVIC0_INTCID0) /* Component Identification Bits7:0 */ +#define pREG_NVIC0_INTCID1 ((__IO uint32_t *) REG_NVIC0_INTCID1) /* Component Identification Bits15:8 */ +#define pREG_NVIC0_INTCID2 ((__IO uint32_t *) REG_NVIC0_INTCID2) /* Component Identification Bits16:23 */ +#define pREG_NVIC0_INTCID3 ((__IO uint32_t *) REG_NVIC0_INTCID3) /* Component Identification Bits24:31 */ + +#if defined (_MISRA_RULES) +#pragma diag(pop) +#endif /* _MISRA_RULES */ + + +#endif + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_device.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_device.h new file mode 100755 index 0000000000..858848297b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_device.h @@ -0,0 +1,1338 @@ +/* ================================================================================ + + Project : ADuCM4050 + File : ADuCM4050_device.h + Description : C Register Definitions + + Date : Feb 7, 2017 + + Copyright (c) 2014-2017 Analog Devices, Inc. All Rights Reserved. + This software is proprietary and confidential to Analog Devices, Inc. and + its licensors. + + This file was auto-generated. Do not make local changes to this file. + + ================================================================================ */ + +#ifndef _ADUCM4050_DEVICE_H +#define _ADUCM4050_DEVICE_H + +/* pickup integer types */ +#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include +#endif /* _LANGUAGE_C */ + +/* pickup register bitfield and bit masks */ +#include "adi_ADuCM4050_typedefs.h" + +#if defined ( __CC_ARM ) +#pragma push +#pragma anon_unions +#endif + + +#ifndef __IO +#ifdef __cplusplus +#define __I volatile /* read-only */ +#define __C +#else +#define __I volatile /* read-only */ +#define __C const +#endif +#define __O volatile /* write-only */ +#define __IO volatile /* read-write */ +#endif + +#if defined (_MISRA_RULES) +/* + anonymous unions violate ISO 9899:1990 and therefore MISRA Rule 1.1. + Use of unions violates MISRA Rule 18.4. + Anonymous unions are required for this implementation. + Re-use of identifiers violates MISRA Rule 5.7. + Field names are repeated for the ADuCM4050 register map. +*/ +#pragma diag(push) +#pragma diag(suppress:misra_rule_1_1:"Allow anonymous unions") +#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit") +#pragma diag(suppress:misra_rule_5_3:"Header will re-use typedef identifiers") +#pragma diag(suppress:misra_rule_5_6:"Header will re-use identifiers in the same scope") +#pragma diag(suppress:misra_rule_5_7:"Header will re-use identifiers") +#pragma diag(suppress:misra_rule_18_4:"Allow the use of a union") +#endif /* _MISRA_RULES */ + +/** @defgroup TMR General Purpose Timer (TMR) Module + * General Purpose Timer + * @{ + */ + +/*! ========================================================================== + * \struct ADI_TMR_TypeDef + * \brief General Purpose Timer + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_TypeDef__ +typedef struct _ADI_TMR_TypeDef +{ + __IO uint16_t LOAD; /*!< 16-bit Load Value */ + __I __C uint8_t RESERVED0[2]; + __I __C uint16_t CURCNT; /*!< 16-bit Timer Value */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t CTL; /*!< Control */ + __I __C uint8_t RESERVED2[2]; + __O uint16_t CLRINT; /*!< Clear Interrupt */ + __I __C uint8_t RESERVED3[2]; + __I __C uint16_t CAPTURE; /*!< Capture */ + __I __C uint8_t RESERVED4[2]; + __IO uint16_t ALOAD; /*!< 16-bit Load Value, Asynchronous */ + __I __C uint8_t RESERVED5[2]; + __I __C uint16_t ACURCNT; /*!< 16-bit Timer Value, Asynchronous */ + __I __C uint8_t RESERVED6[2]; + __I __C uint16_t STAT; /*!< Status */ + __I __C uint8_t RESERVED7[2]; + __IO uint16_t PWMCTL; /*!< PWM Control Register */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t PWMMATCH; /*!< PWM Match Value */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t EVENTSELECT; /*!< Timer Event Selection Register */ +} ADI_TMR_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_TypeDef__ */ + +/*!@}*/ + +/** @defgroup TMR_RGB Timer_RGB with 3 PWM outputs (TMR_RGB) Module + * Timer_RGB with 3 PWM outputs + * @{ + */ + +/*! ========================================================================== + * \struct ADI_TMR_RGB_TypeDef + * \brief Timer_RGB with 3 PWM outputs + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_TypeDef__ +typedef struct _ADI_TMR_RGB_TypeDef +{ + __IO uint16_t LOAD; /*!< 16-bit load value */ + __I __C uint8_t RESERVED0[2]; + __I __C uint16_t CURCNT; /*!< 16-bit timer value */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t CTL; /*!< Control */ + __I __C uint8_t RESERVED2[2]; + __O uint16_t CLRINT; /*!< Clear interrupt */ + __I __C uint8_t RESERVED3[2]; + __I __C uint16_t CAPTURE; /*!< Capture */ + __I __C uint8_t RESERVED4[2]; + __IO uint16_t ALOAD; /*!< 16-bit load value, asynchronous */ + __I __C uint8_t RESERVED5[2]; + __I __C uint16_t ACURCNT; /*!< 16-bit timer value, asynchronous */ + __I __C uint8_t RESERVED6[2]; + __I __C uint16_t STAT; /*!< Status */ + __I __C uint8_t RESERVED7[2]; + __IO uint16_t PWM0CTL; /*!< PWM0 Control Register */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t PWM0MATCH; /*!< PWM0 Match Value */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t EVENTSELECT; /*!< Timer Event selection Register */ + __I __C uint8_t RESERVED10[2]; + __IO uint16_t PWM1CTL; /*!< PWM1 Control Register */ + __I __C uint8_t RESERVED11[2]; + __IO uint16_t PWM1MATCH; /*!< PWM1 Match Value */ + __I __C uint8_t RESERVED12[2]; + __IO uint16_t PWM2CTL; /*!< PWM2 Control Register */ + __I __C uint8_t RESERVED13[2]; + __IO uint16_t PWM2MATCH; /*!< PWM2 Match Value */ +} ADI_TMR_RGB_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_TypeDef__ */ + +/*!@}*/ + +/** @defgroup RTC Real-Time Clock (RTC) Module + * Real-Time Clock + * @{ + */ + +/*! ========================================================================== + * \struct ADI_RTC_TypeDef + * \brief Real-Time Clock + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_TypeDef__ +typedef struct _ADI_RTC_TypeDef +{ + __IO uint16_t CR0; /*!< RTC Control 0 */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t SR0; /*!< RTC Status 0 */ + __I __C uint8_t RESERVED1[2]; + __I __C uint16_t SR1; /*!< RTC Status 1 */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t CNT0; /*!< RTC Count 0 */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t CNT1; /*!< RTC Count 1 */ + __I __C uint8_t RESERVED4[2]; + __IO uint16_t ALM0; /*!< RTC Alarm 0 */ + __I __C uint8_t RESERVED5[2]; + __IO uint16_t ALM1; /*!< RTC Alarm 1 */ + __I __C uint8_t RESERVED6[2]; + __IO uint16_t TRM; /*!< RTC Trim */ + __I __C uint8_t RESERVED7[2]; + __O uint16_t GWY; /*!< RTC Gateway */ + __I __C uint8_t RESERVED8[6]; + __IO uint16_t CR1; /*!< RTC Control 1 */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t SR2; /*!< RTC Status 2 */ + __I __C uint8_t RESERVED10[2]; + __I __C uint16_t SNAP0; /*!< RTC Snapshot 0 */ + __I __C uint8_t RESERVED11[2]; + __I __C uint16_t SNAP1; /*!< RTC Snapshot 1 */ + __I __C uint8_t RESERVED12[2]; + __I __C uint16_t SNAP2; /*!< RTC Snapshot 2 */ + __I __C uint8_t RESERVED13[2]; + __I __C uint16_t MOD; /*!< RTC Modulo */ + __I __C uint8_t RESERVED14[2]; + __I __C uint16_t CNT2; /*!< RTC Count 2 */ + __I __C uint8_t RESERVED15[2]; + __IO uint16_t ALM2; /*!< RTC Alarm 2 */ + __I __C uint8_t RESERVED16[2]; + __IO uint16_t SR3; /*!< RTC Status 3 */ + __I __C uint8_t RESERVED17[2]; + __IO uint16_t CR2IC; /*!< RTC Control 2 for Configuring Input Capture Channels */ + __I __C uint8_t RESERVED18[2]; + __IO uint16_t CR3SS; /*!< RTC Control 3 for Configuring SensorStrobe Channel */ + __I __C uint8_t RESERVED19[2]; + __IO uint16_t CR4SS; /*!< RTC Control 4 for Configuring SensorStrobe Channel */ + __I __C uint8_t RESERVED20[2]; + __IO uint16_t SSMSK; /*!< RTC Mask for SensorStrobe Channel */ + __I __C uint8_t RESERVED21[10]; + __I __C uint16_t IC2; /*!< RTC Input Capture Channel 2 */ + __I __C uint8_t RESERVED22[2]; + __I __C uint16_t IC3; /*!< RTC Input Capture Channel 3 */ + __I __C uint8_t RESERVED23[2]; + __I __C uint16_t IC4; /*!< RTC Input Capture Channel 4 */ + __I __C uint8_t RESERVED24[2]; + __IO uint16_t SS1; /*!< RTC SensorStrobe Channel 1 */ + __I __C uint8_t RESERVED25[2]; + __IO uint16_t SS2; /*!< RTC SensorStrobe Channel 2 */ + __I __C uint8_t RESERVED26[2]; + __IO uint16_t SS3; /*!< RTC SensorStrobe Channel 3 */ + __I __C uint8_t RESERVED27[2]; + __IO uint16_t SS4; /*!< RTC SensorStrobe Channel 4 */ + __I __C uint8_t RESERVED28[2]; + __I __C uint16_t SR4; /*!< RTC Status 4 */ + __I __C uint8_t RESERVED29[2]; + __I __C uint16_t SR5; /*!< RTC Status 5 */ + __I __C uint8_t RESERVED30[2]; + __I __C uint16_t SR6; /*!< RTC Status 6 */ + __I __C uint8_t RESERVED31[2]; + __I __C uint16_t SS1TGT; /*!< RTC SensorStrobe Channel 1 Target */ + __I __C uint8_t RESERVED32[2]; + __I __C uint16_t FRZCNT; /*!< RTC Freeze Count */ + __I __C uint8_t RESERVED33[2]; + __I __C uint16_t SS2TGT; /*!< RTC SensorStrobe Channel 2 Target */ + __I __C uint8_t RESERVED34[2]; + __I __C uint16_t SS3TGT; /*!< RTC SensorStrobe Channel 3 Target */ + __I __C uint8_t RESERVED35[6]; + __IO uint16_t SS1LOWDUR; /*!< RTC Auto-Reload Low Duration for SensorStrobe Channel 1 */ + __I __C uint8_t RESERVED36[2]; + __IO uint16_t SS2LOWDUR; /*!< RTC Auto-Reload Low Duration for SensorStrobe Channel 2 */ + __I __C uint8_t RESERVED37[2]; + __IO uint16_t SS3LOWDUR; /*!< RTC Auto-Reload Low Duration for SensorStrobe Channel 3 */ + __I __C uint8_t RESERVED38[6]; + __IO uint16_t SS1HIGHDUR; /*!< RTC Auto-Reload High Duration for SensorStrobe Channel 1 */ + __I __C uint8_t RESERVED39[2]; + __IO uint16_t SS2HIGHDUR; /*!< RTC Auto-Reload High Duration for SensorStrobe Channel 2 */ + __I __C uint8_t RESERVED40[2]; + __IO uint16_t SS3HIGHDUR; /*!< RTC Auto-Reload High Duration for SensorStrobe Channel 3 */ + __I __C uint8_t RESERVED41[6]; + __IO uint16_t SSMSKOT; /*!< RTC Masks for SensorStrobe Channels on Time Control */ + __I __C uint8_t RESERVED42[2]; + __IO uint16_t CR5SSS; /*!< RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling */ + __I __C uint8_t RESERVED43[2]; + __IO uint16_t CR6SSS; /*!< RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge */ + __I __C uint8_t RESERVED44[2]; + __IO uint16_t CR7SSS; /*!< RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity */ + __I __C uint8_t RESERVED45[2]; + __IO uint16_t SR7; /*!< RTC Status 7 */ + __I __C uint8_t RESERVED46[2]; + __I __C uint16_t SR8; /*!< RTC Status 8 */ + __I __C uint8_t RESERVED47[2]; + __I __C uint16_t SR9; /*!< RTC Status 9 */ + __I __C uint8_t RESERVED48[6]; + __IO uint16_t GPMUX0; /*!< RTC GPIO Pin Mux Control Register 0 */ + __I __C uint8_t RESERVED49[2]; + __IO uint16_t GPMUX1; /*!< RTC GPIO Pin Mux Control Register 1 */ +} ADI_RTC_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_TypeDef__ */ + +/*!@}*/ + +/** @defgroup SYS System Identification and Debug Enable (SYS) Module + * System Identification and Debug Enable + * @{ + */ + +/*! ========================================================================== + * \struct ADI_SYS_TypeDef + * \brief System Identification and Debug Enable + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_TypeDef__ +typedef struct _ADI_SYS_TypeDef +{ + __I __C uint8_t RESERVED0[32]; + __I __C uint16_t ADIID; /*!< ADI Identification */ + __I __C uint8_t RESERVED1[2]; + __I __C uint16_t CHIPID; /*!< Chip Identifier */ + __I __C uint8_t RESERVED2[26]; + __O uint16_t SWDEN; /*!< Serial Wire Debug Enable */ +} ADI_SYS_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_TypeDef__ */ + +/*!@}*/ + +/** @defgroup WDT Watchdog Timer (WDT) Module + * Watchdog Timer + * @{ + */ + +/*! ========================================================================== + * \struct ADI_WDT_TypeDef + * \brief Watchdog Timer + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_TypeDef__ +typedef struct _ADI_WDT_TypeDef +{ + __IO uint16_t LOAD; /*!< Load Value */ + __I __C uint8_t RESERVED0[2]; + __I __C uint16_t CCNT; /*!< Current Count Value */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t CTL; /*!< Control */ + __I __C uint8_t RESERVED2[2]; + __O uint16_t RESTART; /*!< Clear Interrupt */ + __I __C uint8_t RESERVED3[10]; + __I __C uint16_t STAT; /*!< Status */ +} ADI_WDT_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_TypeDef__ */ + +/*!@}*/ + +/** @defgroup I2C I2C Master/Slave (I2C) Module + * I2C Master/Slave + * @{ + */ + +/*! ========================================================================== + * \struct ADI_I2C_TypeDef + * \brief I2C Master/Slave + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_TypeDef__ +typedef struct _ADI_I2C_TypeDef +{ + __IO uint16_t MCTL; /*!< Master Control */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t MSTAT; /*!< Master Status */ + __I __C uint8_t RESERVED1[2]; + __I __C uint16_t MRX; /*!< Master Receive Data */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t MTX; /*!< Master Transmit Data */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t MRXCNT; /*!< Master Receive Data Count */ + __I __C uint8_t RESERVED4[2]; + __I __C uint16_t MCRXCNT; /*!< Master Current Receive Data Count */ + __I __C uint8_t RESERVED5[2]; + __IO uint16_t ADDR1; /*!< Master Address Byte 1 */ + __I __C uint8_t RESERVED6[2]; + __IO uint16_t ADDR2; /*!< Master Address Byte 2 */ + __I __C uint8_t RESERVED7[2]; + __IO uint16_t BYT; /*!< Start Byte */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t DIV; /*!< Serial Clock Period Divisor */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t SCTL; /*!< Slave Control */ + __I __C uint8_t RESERVED10[2]; + __IO uint16_t SSTAT; /*!< Slave I2C Status/Error/IRQ */ + __I __C uint8_t RESERVED11[2]; + __I __C uint16_t SRX; /*!< Slave Receive */ + __I __C uint8_t RESERVED12[2]; + __IO uint16_t STX; /*!< Slave Transmit */ + __I __C uint8_t RESERVED13[2]; + __IO uint16_t ALT; /*!< Hardware General Call ID */ + __I __C uint8_t RESERVED14[2]; + __IO uint16_t ID0; /*!< First Slave Address Device ID */ + __I __C uint8_t RESERVED15[2]; + __IO uint16_t ID1; /*!< Second Slave Address Device ID */ + __I __C uint8_t RESERVED16[2]; + __IO uint16_t ID2; /*!< Third Slave Address Device ID */ + __I __C uint8_t RESERVED17[2]; + __IO uint16_t ID3; /*!< Fourth Slave Address Device ID */ + __I __C uint8_t RESERVED18[2]; + __IO uint16_t STAT; /*!< Master and Slave FIFO Status */ + __I __C uint8_t RESERVED19[2]; + __O uint16_t SHCTL; /*!< Shared Control */ + __I __C uint8_t RESERVED20[2]; + __IO uint16_t TCTL; /*!< Timing Control Register */ + __I __C uint8_t RESERVED21[2]; + __IO uint16_t ASTRETCH_SCL; /*!< Automatic Stretch SCL */ +} ADI_I2C_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_TypeDef__ */ + +/*!@}*/ + +/** @defgroup SPI Serial Peripheral Interface (SPI) Module + * Serial Peripheral Interface + * @{ + */ + +/*! ========================================================================== + * \struct ADI_SPI_TypeDef + * \brief Serial Peripheral Interface + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_TypeDef__ +typedef struct _ADI_SPI_TypeDef +{ + __IO uint16_t STAT; /*!< Status */ + __I __C uint8_t RESERVED0[2]; + __I __C uint16_t RX; /*!< Receive */ + __I __C uint8_t RESERVED1[2]; + __O uint16_t TX; /*!< Transmit */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t DIV; /*!< SPI Baud Rate Selection */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t CTL; /*!< SPI Configuration */ + __I __C uint8_t RESERVED4[2]; + __IO uint16_t IEN; /*!< SPI Interrupts Enable */ + __I __C uint8_t RESERVED5[2]; + __IO uint16_t CNT; /*!< Transfer Byte Count */ + __I __C uint8_t RESERVED6[2]; + __IO uint16_t DMA; /*!< SPI DMA Enable */ + __I __C uint8_t RESERVED7[2]; + __I __C uint16_t FIFO_STAT; /*!< FIFO Status */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t RD_CTL; /*!< Read Control */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t FLOW_CTL; /*!< Flow Control */ + __I __C uint8_t RESERVED10[2]; + __IO uint16_t WAIT_TMR; /*!< Wait Timer for Flow Control */ + __I __C uint8_t RESERVED11[2]; + __IO uint16_t CS_CTL; /*!< Chip Select Control for Multi-slave Connections */ + __I __C uint8_t RESERVED12[2]; + __IO uint16_t CS_OVERRIDE; /*!< Chip Select Override */ + __I __C uint8_t RESERVED13[4]; +} ADI_SPI_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_TypeDef__ */ + +/*!@}*/ + +/** @defgroup UART (UART) Module + * + * @{ + */ + +/*! ========================================================================== + * \struct ADI_UART_TypeDef + * \brief + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_TypeDef__ +typedef struct _ADI_UART_TypeDef +{ + union { + __I __C uint16_t RX; /*!< Receive Buffer Register */ + __O uint16_t TX; /*!< Transmit Holding Register */ + }; + __I __C uint8_t RESERVED0[2]; + __IO uint16_t IEN; /*!< Interrupt Enable */ + __I __C uint8_t RESERVED1[2]; + __I __C uint16_t IIR; /*!< Interrupt ID */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t LCR; /*!< Line Control */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t MCR; /*!< Modem Control */ + __I __C uint8_t RESERVED4[2]; + __I __C uint16_t LSR; /*!< Line Status */ + __I __C uint8_t RESERVED5[2]; + __I __C uint16_t MSR; /*!< Modem Status */ + __I __C uint8_t RESERVED6[2]; + __IO uint16_t SCR; /*!< Scratch Buffer */ + __I __C uint8_t RESERVED7[2]; + __IO uint16_t FCR; /*!< FIFO Control */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t FBR; /*!< Fractional Baud Rate */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t DIV; /*!< Baud Rate Divider */ + __I __C uint8_t RESERVED10[2]; + __IO uint16_t LCR2; /*!< Second Line Control */ + __I __C uint8_t RESERVED11[2]; + __IO uint16_t CTL; /*!< UART Control Register */ + __I __C uint8_t RESERVED12[2]; + __I __C uint16_t RFC; /*!< RX FIFO Byte Count */ + __I __C uint8_t RESERVED13[2]; + __I __C uint16_t TFC; /*!< TX FIFO Byte Count */ + __I __C uint8_t RESERVED14[2]; + __IO uint16_t RSC; /*!< RS485 Half-duplex Control */ + __I __C uint8_t RESERVED15[2]; + __IO uint16_t ACR; /*!< Auto Baud Control */ + __I __C uint8_t RESERVED16[2]; + __I __C uint16_t ASRL; /*!< Auto Baud Status (Low) */ + __I __C uint8_t RESERVED17[2]; + __I __C uint16_t ASRH; /*!< Auto Baud Status (High) */ +} ADI_UART_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_TypeDef__ */ + +/*!@}*/ + +/** @defgroup BEEP Beeper Driver (BEEP) Module + * Beeper Driver + * @{ + */ + +/*! ========================================================================== + * \struct ADI_BEEP_TypeDef + * \brief Beeper Driver + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_TypeDef__ +typedef struct _ADI_BEEP_TypeDef +{ + __IO uint16_t CFG; /*!< Beeper Configuration */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t STAT; /*!< Beeper Status */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t TONEA; /*!< Tone A Data */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t TONEB; /*!< Tone B Data */ +} ADI_BEEP_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_TypeDef__ */ + +/*!@}*/ + +/** @defgroup ADC (ADC) Module + * + * @{ + */ + +/*! ========================================================================== + * \struct ADI_ADC_TypeDef + * \brief + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_TypeDef__ +typedef struct _ADI_ADC_TypeDef +{ + __IO uint16_t CFG; /*!< ADC Configuration */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t PWRUP; /*!< ADC Power-up Time */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t CAL_WORD; /*!< Calibration Word */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t CNV_CFG; /*!< ADC Conversion Configuration */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t CNV_TIME; /*!< ADC Conversion Time */ + __I __C uint8_t RESERVED4[2]; + __IO uint16_t AVG_CFG; /*!< Averaging Configuration */ + __I __C uint8_t RESERVED5[10]; + __IO uint16_t IRQ_EN; /*!< Interrupt Enable */ + __I __C uint8_t RESERVED6[2]; + __IO uint16_t STAT; /*!< ADC Status */ + __I __C uint8_t RESERVED7[2]; + __IO uint16_t OVF; /*!< Overflow of Output Registers */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t ALERT; /*!< Alert Indication */ + __I __C uint8_t RESERVED9[2]; + __I __C uint16_t CH0_OUT; /*!< Conversion Result Channel 0 */ + __I __C uint8_t RESERVED10[2]; + __I __C uint16_t CH1_OUT; /*!< Conversion Result Channel 1 */ + __I __C uint8_t RESERVED11[2]; + __I __C uint16_t CH2_OUT; /*!< Conversion Result Channel 2 */ + __I __C uint8_t RESERVED12[2]; + __I __C uint16_t CH3_OUT; /*!< Conversion Result Channel 3 */ + __I __C uint8_t RESERVED13[2]; + __I __C uint16_t CH4_OUT; /*!< Conversion Result Channel 4 */ + __I __C uint8_t RESERVED14[2]; + __I __C uint16_t CH5_OUT; /*!< Conversion Result Channel 5 */ + __I __C uint8_t RESERVED15[2]; + __I __C uint16_t CH6_OUT; /*!< Conversion Result Channel 6 */ + __I __C uint8_t RESERVED16[2]; + __I __C uint16_t CH7_OUT; /*!< Conversion Result Channel 7 */ + __I __C uint8_t RESERVED17[2]; + __I __C uint16_t BAT_OUT; /*!< Battery Monitoring Result */ + __I __C uint8_t RESERVED18[2]; + __I __C uint16_t TMP_OUT; /*!< Temperature Result */ + __I __C uint8_t RESERVED19[2]; + __I __C uint16_t TMP2_OUT; /*!< Temperature Result 2 */ + __I __C uint8_t RESERVED20[2]; + __I __C uint16_t DMA_OUT; /*!< DMA Output Register */ + __I __C uint8_t RESERVED21[2]; + __IO uint16_t LIM0_LO; /*!< Channel 0 Low Limit */ + __I __C uint8_t RESERVED22[2]; + __IO uint16_t LIM0_HI; /*!< Channel 0 High Limit */ + __I __C uint8_t RESERVED23[2]; + __IO uint16_t HYS0; /*!< Channel 0 Hysteresis */ + __I __C uint8_t RESERVED24[6]; + __IO uint16_t LIM1_LO; /*!< Channel 1 Low Limit */ + __I __C uint8_t RESERVED25[2]; + __IO uint16_t LIM1_HI; /*!< Channel 1 High Limit */ + __I __C uint8_t RESERVED26[2]; + __IO uint16_t HYS1; /*!< Channel 1 Hysteresis */ + __I __C uint8_t RESERVED27[6]; + __IO uint16_t LIM2_LO; /*!< Channel 2 Low Limit */ + __I __C uint8_t RESERVED28[2]; + __IO uint16_t LIM2_HI; /*!< Channel 2 High Limit */ + __I __C uint8_t RESERVED29[2]; + __IO uint16_t HYS2; /*!< Channel 2 Hysteresis */ + __I __C uint8_t RESERVED30[6]; + __IO uint16_t LIM3_LO; /*!< Channel 3 Low Limit */ + __I __C uint8_t RESERVED31[2]; + __IO uint16_t LIM3_HI; /*!< Channel 3 High Limit */ + __I __C uint8_t RESERVED32[2]; + __IO uint16_t HYS3; /*!< Channel 3 Hysteresis */ + __I __C uint8_t RESERVED33[38]; + __IO uint16_t CFG1; /*!< Reference Buffer Low Power Mode */ + __I __C uint8_t RESERVED34[576]; +} ADI_ADC_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_TypeDef__ */ + +/*!@}*/ + +/** @defgroup DMA DMA (DMA) Module + * DMA + * @{ + */ + +/*! ========================================================================== + * \struct ADI_DMA_TypeDef + * \brief DMA + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_TypeDef__ +typedef struct _ADI_DMA_TypeDef +{ + __I __C uint32_t STAT; /*!< DMA Status */ + __O uint32_t CFG; /*!< DMA Configuration */ + __IO uint32_t PDBPTR; /*!< DMA Channel Primary Control Database Pointer */ + __I __C uint32_t ADBPTR; /*!< DMA Channel Alternate Control Database Pointer */ + __I __C uint8_t RESERVED0[4]; + __O uint32_t SWREQ; /*!< DMA Channel Software Request */ + __I __C uint8_t RESERVED1[8]; + __IO uint32_t RMSK_SET; /*!< DMA Channel Request Mask Set */ + __O uint32_t RMSK_CLR; /*!< DMA Channel Request Mask Clear */ + __IO uint32_t EN_SET; /*!< DMA Channel Enable Set */ + __O uint32_t EN_CLR; /*!< DMA Channel Enable Clear */ + __IO uint32_t ALT_SET; /*!< DMA Channel Primary Alternate Set */ + __O uint32_t ALT_CLR; /*!< DMA Channel Primary Alternate Clear */ + __O uint32_t PRI_SET; /*!< DMA Channel Priority Set */ + __O uint32_t PRI_CLR; /*!< DMA Channel Priority Clear */ + __I __C uint8_t RESERVED2[8]; + __IO uint32_t ERRCHNL_CLR; /*!< DMA per Channel Error Clear */ + __IO uint32_t ERR_CLR; /*!< DMA Bus Error Clear */ + __IO uint32_t INVALIDDESC_CLR; /*!< DMA per Channel Invalid Descriptor Clear */ + __I __C uint8_t RESERVED3[1964]; + __IO uint32_t BS_SET; /*!< DMA Channel Bytes Swap Enable Set */ + __O uint32_t BS_CLR; /*!< DMA Channel Bytes Swap Enable Clear */ + __I __C uint8_t RESERVED4[8]; + __IO uint32_t SRCADDR_SET; /*!< DMA Channel Source Address Decrement Enable Set */ + __O uint32_t SRCADDR_CLR; /*!< DMA Channel Source Address Decrement Enable Clear */ + __IO uint32_t DSTADDR_SET; /*!< DMA Channel Destination Address Decrement Enable Set */ + __O uint32_t DSTADDR_CLR; /*!< DMA Channel Destination Address Decrement Enable Clear */ + __I __C uint8_t RESERVED5[1984]; + __I __C uint32_t REVID; /*!< DMA Controller Revision ID */ +} ADI_DMA_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_TypeDef__ */ + +/*!@}*/ + +/** @defgroup FLCC Flash Controller (FLCC) Module + * Flash Controller + * @{ + */ + +/*! ========================================================================== + * \struct ADI_FLCC_TypeDef + * \brief Flash Controller + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_TypeDef__ +typedef struct _ADI_FLCC_TypeDef +{ + __IO uint32_t STAT; /*!< Status */ + __IO uint32_t IEN; /*!< Interrupt Enable */ + __IO uint32_t CMD; /*!< Command */ + __IO uint32_t KH_ADDR; /*!< Write Address */ + __IO uint32_t KH_DATA0; /*!< Write Lower Data */ + __IO uint32_t KH_DATA1; /*!< Write Upper Data */ + __IO uint32_t PAGE_ADDR0; /*!< Lower Page Address */ + __IO uint32_t PAGE_ADDR1; /*!< Upper Page Address */ + __O uint32_t KEY; /*!< Key */ + __I __C uint32_t WR_ABORT_ADDR; /*!< Write Abort Address */ + __IO uint32_t WRPROT; /*!< Write Protection */ + __I __C uint32_t SIGNATURE; /*!< Signature */ + __IO uint32_t UCFG; /*!< User Configuration */ + __IO uint32_t TIME_PARAM0; /*!< Time Parameter 0 */ + __IO uint32_t TIME_PARAM1; /*!< Time Parameter 1 */ + __IO uint32_t ABORT_EN_LO; /*!< IRQ Abort Enable (Lower Bits) */ + __IO uint32_t ABORT_EN_HI; /*!< IRQ Abort Enable (Upper Bits) */ + __IO uint32_t ECC_CFG; /*!< ECC Configuration */ + __I __C uint32_t ECC_ADDR; /*!< ECC Status (Address) */ + __I __C uint8_t RESERVED0[4]; + __IO uint32_t POR_SEC; /*!< Flash Security */ + __IO uint32_t VOL_CFG; /*!< Volatile Flash Configuration */ +} ADI_FLCC_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_TypeDef__ */ + +/*!@}*/ + +/** @defgroup FLCC_CACHE Cache Controller (FLCC_CACHE) Module + * Cache Controller + * @{ + */ + +/*! ========================================================================== + * \struct ADI_FLCC_CACHE_TypeDef + * \brief Cache Controller + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_TypeDef__ +typedef struct _ADI_FLCC_CACHE_TypeDef +{ + __I __C uint32_t STAT; /*!< Cache Status Register */ + __IO uint32_t SETUP; /*!< Cache Setup Register */ + __O uint32_t KEY; /*!< Cache Key Register */ + __I __C uint8_t RESERVED0[40]; +} ADI_FLCC_CACHE_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_TypeDef__ */ + +/*!@}*/ + +/** @defgroup GPIO (GPIO) Module + * + * @{ + */ + +/*! ========================================================================== + * \struct ADI_GPIO_TypeDef + * \brief + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_TypeDef__ +typedef struct _ADI_GPIO_TypeDef +{ + __IO uint32_t CFG; /*!< Port Configuration */ + __IO uint16_t OEN; /*!< Port Output Enable */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t PE; /*!< Port Output Pull-up/Pull-down Enable */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t IEN; /*!< Port Input Path Enable */ + __I __C uint8_t RESERVED2[2]; + __I __C uint16_t IN; /*!< Port Registered Data Input */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t OUT; /*!< Port Data Output */ + __I __C uint8_t RESERVED4[2]; + __O uint16_t SET; /*!< Port Data Out Set */ + __I __C uint8_t RESERVED5[2]; + __O uint16_t CLR; /*!< Port Data Out Clear */ + __I __C uint8_t RESERVED6[2]; + __O uint16_t TGL; /*!< Port Pin Toggle */ + __I __C uint8_t RESERVED7[2]; + __IO uint16_t POL; /*!< Port Interrupt Polarity */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t IENA; /*!< Port Interrupt A Enable */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t IENB; /*!< Port Interrupt B Enable */ + __I __C uint8_t RESERVED10[2]; + __IO uint16_t INT; /*!< Port Interrupt Status */ + __I __C uint8_t RESERVED11[2]; + __IO uint16_t DS; /*!< Port Drive Strength Select */ +} ADI_GPIO_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_TypeDef__ */ + +/*!@}*/ + +/** @defgroup SPORT Serial Port (SPORT) Module + * Serial Port + * @{ + */ + +/*! ========================================================================== + * \struct ADI_SPORT_TypeDef + * \brief Serial Port + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_TypeDef__ +typedef struct _ADI_SPORT_TypeDef +{ + __IO uint32_t CTL_A; /*!< Half SPORT 'A' Control Register */ + __IO uint32_t DIV_A; /*!< Half SPORT 'A' Divisor Register */ + __IO uint32_t IEN_A; /*!< Half SPORT A's Interrupt Enable register */ + __IO uint32_t STAT_A; /*!< Half SPORT 'A' Status register */ + __IO uint32_t NUMTRAN_A; /*!< Half SPORT A Number of transfers register */ + __IO uint32_t CNVT_A; /*!< Half SPORT 'A' CNV width */ + __I __C uint8_t RESERVED0[8]; + __O uint32_t TX_A; /*!< Half SPORT 'A' Tx Buffer Register */ + __I __C uint8_t RESERVED1[4]; + __I __C uint32_t RX_A; /*!< Half SPORT 'A' Rx Buffer Register */ + __I __C uint8_t RESERVED2[20]; + __IO uint32_t CTL_B; /*!< Half SPORT 'B' Control Register */ + __IO uint32_t DIV_B; /*!< Half SPORT 'B' Divisor Register */ + __IO uint32_t IEN_B; /*!< Half SPORT B's Interrupt Enable register */ + __IO uint32_t STAT_B; /*!< Half SPORT 'B' Status register */ + __IO uint32_t NUMTRAN_B; /*!< Half SPORT B Number of transfers register */ + __IO uint32_t CNVT_B; /*!< Half SPORT 'B' CNV width register */ + __I __C uint8_t RESERVED3[8]; + __O uint32_t TX_B; /*!< Half SPORT 'B' Tx Buffer Register */ + __I __C uint8_t RESERVED4[4]; + __I __C uint32_t RX_B; /*!< Half SPORT 'B' Rx Buffer Register */ + __I __C uint8_t RESERVED5[16]; +} ADI_SPORT_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_TypeDef__ */ + +/*!@}*/ + +/** @defgroup CRC CRC Accelerator (CRC) Module + * CRC Accelerator + * @{ + */ + +/*! ========================================================================== + * \struct ADI_CRC_TypeDef + * \brief CRC Accelerator + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_TypeDef__ +typedef struct _ADI_CRC_TypeDef +{ + __IO uint32_t CTL; /*!< CRC Control */ + __O uint32_t IPDATA; /*!< Input Data Word */ + __IO uint32_t RESULT; /*!< CRC Result */ + __IO uint32_t POLY; /*!< Programmable CRC Polynomial */ + union { + __O uint8_t IPBITS[8]; /*!< Input Data Bits */ + __O uint8_t IPBYTE; /*!< Input Data Byte */ + }; +} ADI_CRC_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_TypeDef__ */ + +/*!@}*/ + +/** @defgroup RNG Random Number Generator (RNG) Module + * Random Number Generator + * @{ + */ + +/*! ========================================================================== + * \struct ADI_RNG_TypeDef + * \brief Random Number Generator + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_TypeDef__ +typedef struct _ADI_RNG_TypeDef +{ + __IO uint16_t CTL; /*!< RNG Control Register */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t LEN; /*!< RNG Sample Length Register */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t STAT; /*!< RNG Status Register */ + __I __C uint8_t RESERVED2[2]; + __I __C uint32_t DATA; /*!< RNG Data Register */ + __I __C uint32_t OSCCNT; /*!< Oscillator Count */ + __I __C int8_t OSCDIFF[4]; /*!< Oscillator Difference */ +} ADI_RNG_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_TypeDef__ */ + +/*!@}*/ + +/** @defgroup CRYPT Register Map for the Crypto Block (CRYPT) Module + * Register Map for the Crypto Block + * @{ + */ + +/*! ========================================================================== + * \struct ADI_CRYPT_TypeDef + * \brief Register Map for the Crypto Block + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_TypeDef__ +typedef struct _ADI_CRYPT_TypeDef +{ + __IO uint32_t CFG; /*!< Configuration Register */ + __IO uint32_t DATALEN; /*!< Payload Data Length */ + __IO uint32_t PREFIXLEN; /*!< Authentication Data Length */ + __IO uint32_t INTEN; /*!< Interrupt Enable Register */ + __IO uint32_t STAT; /*!< Status Register */ + __O uint32_t INBUF; /*!< Input Buffer */ + __I __C uint32_t OUTBUF; /*!< Output Buffer */ + __IO uint32_t NONCE0; /*!< Nonce Bits [31:0] */ + __IO uint32_t NONCE1; /*!< Nonce Bits [63:32] */ + __IO uint32_t NONCE2; /*!< Nonce Bits [95:64] */ + __IO uint32_t NONCE3; /*!< Nonce Bits [127:96] */ + __O uint32_t AESKEY0; /*!< AES Key Bits [31:0] */ + __O uint32_t AESKEY1; /*!< AES Key Bits [63:32] */ + __O uint32_t AESKEY2; /*!< AES Key Bits [95:64] */ + __O uint32_t AESKEY3; /*!< AES Key Bits [127:96] */ + __O uint32_t AESKEY4; /*!< AES Key Bits [159:128] */ + __O uint32_t AESKEY5; /*!< AES Key Bits [191:160] */ + __O uint32_t AESKEY6; /*!< AES Key Bits [223:192] */ + __O uint32_t AESKEY7; /*!< AES Key Bits [255:224] */ + __IO uint32_t CNTRINIT; /*!< Counter Initialization Vector */ + __IO uint32_t SHAH0; /*!< SHA Bits [31:0] */ + __IO uint32_t SHAH1; /*!< SHA Bits [63:32] */ + __IO uint32_t SHAH2; /*!< SHA Bits [95:64] */ + __IO uint32_t SHAH3; /*!< SHA Bits [127:96] */ + __IO uint32_t SHAH4; /*!< SHA Bits [159:128] */ + __IO uint32_t SHAH5; /*!< SHA Bits [191:160] */ + __IO uint32_t SHAH6; /*!< SHA Bits [223:192] */ + __IO uint32_t SHAH7; /*!< SHA Bits [255:224] */ + __IO uint32_t SHA_LAST_WORD; /*!< SHA Last Word and Valid Bits Information */ + __IO uint32_t CCM_NUM_VALID_BYTES; /*!< NUM_VALID_BYTES */ + __IO uint32_t PRKSTORCFG; /*!< PRKSTOR Configuration */ + __I __C uint8_t RESERVED0[4]; + __O uint32_t KUW0; /*!< Key Wrap Unwrap Register 0 */ + __O uint32_t KUW1; /*!< Key Wrap Unwrap Register 1 */ + __O uint32_t KUW2; /*!< Key Wrap Unwrap Register 2 */ + __O uint32_t KUW3; /*!< Key Wrap Unwrap Register 3 */ + __O uint32_t KUW4; /*!< Key Wrap Unwrap Register 4 */ + __O uint32_t KUW5; /*!< Key Wrap Unwrap Register 5 */ + __O uint32_t KUW6; /*!< Key Wrap Unwrap Register 6 */ + __O uint32_t KUW7; /*!< Key Wrap Unwrap Register 7 */ + __O uint32_t KUW8; /*!< Key Wrap Unwrap Register 8 */ + __O uint32_t KUW9; /*!< Key Wrap Unwrap Register 9 */ + __O uint32_t KUW10; /*!< Key Wrap Unwrap Register 10 */ + __O uint32_t KUW11; /*!< Key Wrap Unwrap Register 11 */ + __O uint32_t KUW12; /*!< Key Wrap Unwrap Register 12 */ + __O uint32_t KUW13; /*!< Key Wrap Unwrap Register 13 */ + __O uint32_t KUW14; /*!< Key Wrap Unwrap Register 14 */ + __O uint32_t KUW15; /*!< Key Wrap Unwrap Register 15 */ + __O uint32_t KUWVALSTR1; /*!< Key Wrap Unwrap Validation String [63:32] */ + __O uint32_t KUWVALSTR2; /*!< Key Wrap Unwrap Validation String [31:0] */ +} ADI_CRYPT_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_TypeDef__ */ + +/*!@}*/ + +/** @defgroup PMG Power Management (PMG) Module + * Power Management + * @{ + */ + +/*! ========================================================================== + * \struct ADI_PMG_TypeDef + * \brief Power Management + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TypeDef__ +typedef struct _ADI_PMG_TypeDef +{ + __IO uint32_t IEN; /*!< Power Supply Monitor Interrupt Enable */ + __IO uint32_t PSM_STAT; /*!< Power Supply Monitor Status */ + __IO uint32_t PWRMOD; /*!< Power Mode Register */ + __O uint32_t PWRKEY; /*!< Key Protection for PWRMOD and SRAMRET */ + __I __C uint32_t SHDN_STAT; /*!< Shutdown Status Register */ + __IO uint32_t SRAMRET; /*!< Control for Retention SRAM in Hibernate Mode */ + __I __C uint8_t RESERVED0[32]; + __IO uint32_t TRIM; /*!< Trimming Bits */ + __I __C uint8_t RESERVED1[4]; + __IO uint32_t RST_STAT; /*!< Reset Status */ + __IO uint32_t CTL1; /*!< HPBUCK Control */ + __I __C uint8_t RESERVED2[20]; +} ADI_PMG_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TypeDef__ */ + +/*!@}*/ + +/** @defgroup XINT External interrupt configuration (XINT) Module + * External interrupt configuration + * @{ + */ + +/*! ========================================================================== + * \struct ADI_XINT_TypeDef + * \brief External interrupt configuration + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_TypeDef__ +typedef struct _ADI_XINT_TypeDef +{ + __IO uint32_t CFG0; /*!< External Interrupt configuration */ + __I __C uint32_t EXT_STAT; /*!< External Wakeup Interrupt Status register */ + __I __C uint8_t RESERVED0[8]; + __IO uint32_t CLR; /*!< External Interrupt clear */ + __IO uint32_t NMICLR; /*!< Non-maskable interrupt clear */ +} ADI_XINT_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_TypeDef__ */ + +/*!@}*/ + +/** @defgroup CLKG_OSC Clocking (CLKG_OSC) Module + * Clocking + * @{ + */ + +/*! ========================================================================== + * \struct ADI_CLKG_OSC_TypeDef + * \brief Clocking + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_TypeDef__ +typedef struct _ADI_CLKG_OSC_TypeDef +{ + __I __C uint8_t RESERVED0[12]; + __O uint32_t KEY; /*!< Key Protection for OSCCTRL */ + __IO uint32_t CTL; /*!< Oscillator Control */ + __I __C uint8_t RESERVED1[8]; +} ADI_CLKG_OSC_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_TypeDef__ */ + +/*!@}*/ + +/** @defgroup PMG_TST Power Management (PMG_TST) Module + * Power Management + * @{ + */ + +/*! ========================================================================== + * \struct ADI_PMG_TST_TypeDef + * \brief Power Management + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_TypeDef__ +typedef struct _ADI_PMG_TST_TypeDef +{ + __I __C uint8_t RESERVED0[96]; + __IO uint32_t SRAM_CTL; /*!< Control for SRAM Parity and Instruction SRAM */ + __I __C uint32_t SRAM_INITSTAT; /*!< Initialization Status Register */ + __O uint16_t CLR_LATCH_GPIOS; /*!< Clear GPIO After Shutdown Mode */ + __I __C uint8_t RESERVED1[2]; + __IO uint32_t SCRPAD_IMG; /*!< Scratch Pad Image */ + __I __C uint32_t SCRPAD_3V_RD; /*!< Scratch Pad Saved in Battery Domain */ + __IO uint32_t FAST_SHT_WAKEUP; /*!< Fast Shutdown Wake-up Enable */ +} ADI_PMG_TST_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_TypeDef__ */ + +/*!@}*/ + +/** @defgroup CLKG_CLK Clocking (CLKG_CLK) Module + * Clocking + * @{ + */ + +/*! ========================================================================== + * \struct ADI_CLKG_CLK_TypeDef + * \brief Clocking + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_TypeDef__ +typedef struct _ADI_CLKG_CLK_TypeDef +{ + __IO uint32_t CTL0; /*!< Misc Clock Settings */ + __IO uint32_t CTL1; /*!< Clock Dividers */ + __IO uint32_t CTL2; /*!< HF Oscillator Divided Clock Select */ + __IO uint32_t CTL3; /*!< System PLL */ + __I __C uint8_t RESERVED0[4]; + __IO uint32_t CTL5; /*!< User Clock Gating Control */ + __IO uint32_t STAT0; /*!< Clocking Status */ + __I __C uint8_t RESERVED1[20]; +} ADI_CLKG_CLK_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_TypeDef__ */ + +/*!@}*/ + +/** @defgroup BUSM Bus matrix (BUSM) Module + * Bus matrix + * @{ + */ + +/*! ========================================================================== + * \struct ADI_BUSM_TypeDef + * \brief Bus matrix + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_TypeDef__ +typedef struct _ADI_BUSM_TypeDef +{ + __IO uint32_t ARBIT0; /*!< Arbitration Priority Configuration for FLASH and SRAM0 */ + __IO uint32_t ARBIT1; /*!< Arbitration Priority Configuration for SRAM1 and SIP */ + __IO uint32_t ARBIT2; /*!< Arbitration Priority Configuration for APB32 and APB16 */ + __IO uint32_t ARBIT3; /*!< Arbitration Priority Configuration for APB16 priority for core and for DMA1 */ + __I __C uint8_t RESERVED0[4]; + __IO uint32_t ARBIT4; /*!< Arbitration Priority Configuration for SRAM1 and SIP */ +} ADI_BUSM_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_TypeDef__ */ + +/*!@}*/ + +/** @defgroup PTI Parallel Test Interface (PTI) Module + * Parallel Test Interface + * @{ + */ + +/*! ========================================================================== + * \struct ADI_PTI_TypeDef + * \brief Parallel Test Interface + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_TypeDef__ +typedef struct _ADI_PTI_TypeDef +{ + __IO uint32_t RST_ISR_STARTADDR; /*!< Reset ISR Start Address */ + __IO uint32_t RST_STACK_PTR; /*!< Reset Stack Pointer */ + __IO uint32_t CTL; /*!< Parallel Test Interface Control Register */ +} ADI_PTI_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_TypeDef__ */ + +/*!@}*/ + +/** @defgroup NVIC Cortex-M3 Interrupt Controller (NVIC) Module + * Cortex-M3 Interrupt Controller + * @{ + */ + +/*! ========================================================================== + * \struct ADI_NVIC_TypeDef + * \brief Cortex-M3 Interrupt Controller + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_TypeDef__ +typedef struct _ADI_NVIC_TypeDef +{ + __I __C uint8_t RESERVED0[4]; + __IO uint32_t INTNUM; /*!< Interrupt Control Type */ + __I __C uint8_t RESERVED1[8]; + __IO uint32_t STKSTA; /*!< Systick Control and Status */ + __IO uint32_t STKLD; /*!< Systick Reload Value */ + __IO uint32_t STKVAL; /*!< Systick Current Value */ + __IO uint32_t STKCAL; /*!< Systick Calibration Value */ + __I __C uint8_t RESERVED2[224]; + __IO uint32_t INTSETE0; /*!< IRQ0..31 Set_Enable */ + __IO uint32_t INTSETE1; /*!< IRQ32..63 Set_Enable */ + __I __C uint8_t RESERVED3[120]; + __IO uint32_t INTCLRE0; /*!< IRQ0..31 Clear_Enable */ + __IO uint32_t INTCLRE1; /*!< IRQ32..63 Clear_Enable */ + __I __C uint8_t RESERVED4[120]; + __IO uint32_t INTSETP0; /*!< IRQ0..31 Set_Pending */ + __IO uint32_t INTSETP1; /*!< IRQ32..63 Set_Pending */ + __I __C uint8_t RESERVED5[120]; + __IO uint32_t INTCLRP0; /*!< IRQ0..31 Clear_Pending */ + __IO uint32_t INTCLRP1; /*!< IRQ32..63 Clear_Pending */ + __I __C uint8_t RESERVED6[120]; + __IO uint32_t INTACT0; /*!< IRQ0..31 Active Bit */ + __IO uint32_t INTACT1; /*!< IRQ32..63 Active Bit */ + __I __C uint8_t RESERVED7[248]; + __IO uint32_t INTPRI0; /*!< IRQ0..3 Priority */ + __IO uint32_t INTPRI1; /*!< IRQ4..7 Priority */ + __IO uint32_t INTPRI2; /*!< IRQ8..11 Priority */ + __IO uint32_t INTPRI3; /*!< IRQ12..15 Priority */ + __IO uint32_t INTPRI4; /*!< IRQ16..19 Priority */ + __IO uint32_t INTPRI5; /*!< IRQ20..23 Priority */ + __IO uint32_t INTPRI6; /*!< IRQ24..27 Priority */ + __IO uint32_t INTPRI7; /*!< IRQ28..31 Priority */ + __IO uint32_t INTPRI8; /*!< IRQ32..35 Priority */ + __IO uint32_t INTPRI9; /*!< IRQ36..39 Priority */ + __IO uint32_t INTPRI10; /*!< IRQ40..43 Priority */ + __I __C uint8_t RESERVED8[2260]; + __IO uint32_t INTCPID; /*!< CPUID Base */ + __IO uint32_t INTSTA; /*!< Interrupt Control State */ + __IO uint32_t INTVEC; /*!< Vector Table Offset */ + __IO uint32_t INTAIRC; /*!< Application Interrupt/Reset Control */ + __IO uint16_t INTCON0; /*!< System Control */ + __I __C uint8_t RESERVED9[2]; + __IO uint32_t INTCON1; /*!< Configuration Control */ + __IO uint32_t INTSHPRIO0; /*!< System Handlers 4-7 Priority */ + __IO uint32_t INTSHPRIO1; /*!< System Handlers 8-11 Priority */ + __IO uint32_t INTSHPRIO3; /*!< System Handlers 12-15 Priority */ + __IO uint32_t INTSHCSR; /*!< System Handler Control and State */ + __IO uint32_t INTCFSR; /*!< Configurable Fault Status */ + __IO uint32_t INTHFSR; /*!< Hard Fault Status */ + __IO uint32_t INTDFSR; /*!< Debug Fault Status */ + __IO uint32_t INTMMAR; /*!< Mem Manage Address */ + __IO uint32_t INTBFAR; /*!< Bus Fault Address */ + __IO uint32_t INTAFSR; /*!< Auxiliary Fault Status */ + __IO uint32_t INTPFR0; /*!< Processor Feature Register 0 */ + __IO uint32_t INTPFR1; /*!< Processor Feature Register 1 */ + __IO uint32_t INTDFR0; /*!< Debug Feature Register 0 */ + __IO uint32_t INTAFR0; /*!< Auxiliary Feature Register 0 */ + __IO uint32_t INTMMFR0; /*!< Memory Model Feature Register 0 */ + __IO uint32_t INTMMFR1; /*!< Memory Model Feature Register 1 */ + __IO uint32_t INTMMFR2; /*!< Memory Model Feature Register 2 */ + __IO uint32_t INTMMFR3; /*!< Memory Model Feature Register 3 */ + __IO uint32_t INTISAR0; /*!< ISA Feature Register 0 */ + __IO uint32_t INTISAR1; /*!< ISA Feature Register 1 */ + __IO uint32_t INTISAR2; /*!< ISA Feature Register 2 */ + __IO uint32_t INTISAR3; /*!< ISA Feature Register 3 */ + __IO uint32_t INTISAR4; /*!< ISA Feature Register 4 */ + __I __C uint8_t RESERVED10[396]; + __IO uint32_t INTTRGI; /*!< Software Trigger Interrupt Register */ + __I __C uint8_t RESERVED11[204]; + __IO uint32_t INTPID4; /*!< Peripheral Identification Register 4 */ + __IO uint32_t INTPID5; /*!< Peripheral Identification Register 5 */ + __IO uint32_t INTPID6; /*!< Peripheral Identification Register 6 */ + __IO uint32_t INTPID7; /*!< Peripheral Identification Register 7 */ + __IO uint32_t INTPID0; /*!< Peripheral Identification Bits7:0 */ + __IO uint32_t INTPID1; /*!< Peripheral Identification Bits15:8 */ + __IO uint32_t INTPID2; /*!< Peripheral Identification Bits16:23 */ + __IO uint32_t INTPID3; /*!< Peripheral Identification Bits24:31 */ + __IO uint32_t INTCID0; /*!< Component Identification Bits7:0 */ + __IO uint32_t INTCID1; /*!< Component Identification Bits15:8 */ + __IO uint32_t INTCID2; /*!< Component Identification Bits16:23 */ + __IO uint32_t INTCID3; /*!< Component Identification Bits24:31 */ +} ADI_NVIC_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_TypeDef__ */ + +/*!@}*/ + +/* ****************************************************************************** + * Peripheral Memory Map Declarations + * *****************************************************************************/ +/*! @defgroup PMEMMAPDEC Peripheral Memory Map Declarations + * \addtogroup PMEMMAPDEC + * @{ */ +#define ADI_TMR0_BASE 0x40000000 /*!< Base address of TMR0 */ +#define ADI_TMR1_BASE 0x40000400 /*!< Base address of TMR1 */ +#define ADI_TMR2_BASE 0x40000800 /*!< Base address of TMR2 */ +#define ADI_TMR_RGB_BASE 0x40000c00 /*!< Base address of TMR_RGB */ +#define ADI_RTC0_BASE 0x40001000 /*!< Base address of RTC0 */ +#define ADI_RTC1_BASE 0x40001400 /*!< Base address of RTC1 */ +#define ADI_SYS_BASE 0x40002000 /*!< Base address of SYS */ +#define ADI_WDT0_BASE 0x40002c00 /*!< Base address of WDT0 */ +#define ADI_I2C0_BASE 0x40003000 /*!< Base address of I2C0 */ +#define ADI_SPI0_BASE 0x40004000 /*!< Base address of SPI0 */ +#define ADI_SPI1_BASE 0x40004400 /*!< Base address of SPI1 */ +#define ADI_SPI2_BASE 0x40024000 /*!< Base address of SPI2 */ +#define ADI_UART0_BASE 0x40005000 /*!< Base address of UART0 */ +#define ADI_UART1_BASE 0x40005400 /*!< Base address of UART1 */ +#define ADI_BEEP0_BASE 0x40005c00 /*!< Base address of BEEP0 */ +#define ADI_ADC0_BASE 0x40007000 /*!< Base address of ADC0 */ +#define ADI_DMA0_BASE 0x40010000 /*!< Base address of DMA0 */ +#define ADI_FLCC0_BASE 0x40018000 /*!< Base address of FLCC0 */ +#define ADI_FLCC0_CACHE_BASE 0x40018058 /*!< Base address of FLCC0_CACHE */ +#define ADI_GPIO0_BASE 0x40020000 /*!< Base address of GPIO0 */ +#define ADI_GPIO1_BASE 0x40020040 /*!< Base address of GPIO1 */ +#define ADI_GPIO2_BASE 0x40020080 /*!< Base address of GPIO2 */ +#define ADI_GPIO3_BASE 0x400200c0 /*!< Base address of GPIO3 */ +#define ADI_SPORT0_BASE 0x40038000 /*!< Base address of SPORT0 */ +#define ADI_CRC0_BASE 0x40040000 /*!< Base address of CRC0 */ +#define ADI_RNG0_BASE 0x40040400 /*!< Base address of RNG0 */ +#define ADI_CRYPT0_BASE 0x40044000 /*!< Base address of CRYPT0 */ +#define ADI_PMG0_BASE 0x4004c000 /*!< Base address of PMG0 */ +#define ADI_XINT0_BASE 0x4004c080 /*!< Base address of XINT0 */ +#define ADI_CLKG0_OSC_BASE 0x4004c100 /*!< Base address of CLKG0_OSC */ +#define ADI_PMG0_TST_BASE 0x4004c200 /*!< Base address of PMG0_TST */ +#define ADI_CLKG0_CLK_BASE 0x4004c300 /*!< Base address of CLKG0_CLK */ +#define ADI_BUSM0_BASE 0x4004c800 /*!< Base address of BUSM0 */ +#define ADI_PTI0_BASE 0x4004cd00 /*!< Base address of PTI0 */ +#define ADI_NVIC0_BASE 0xe000e000 /*!< Base address of NVIC0 */ + +/*! @} */ + +/* ****************************************************************************** + * Peripheral Pointer Declarations + * *****************************************************************************/ +/*! @Defgroup Pptrdec Peripheral Pointer Declarations + * \Addtogroup Pptrdec + * @{ */ +#define pADI_TMR0 ((ADI_TMR_TypeDef *) ADI_TMR0_BASE ) /*!< Pointer to General Purpose Timer (TMR0) */ +#define pADI_TMR1 ((ADI_TMR_TypeDef *) ADI_TMR1_BASE ) /*!< Pointer to General Purpose Timer (TMR1) */ +#define pADI_TMR2 ((ADI_TMR_TypeDef *) ADI_TMR2_BASE ) /*!< Pointer to General Purpose Timer (TMR2) */ +#define pADI_TMR_RGB ((ADI_TMR_RGB_TypeDef *) ADI_TMR_RGB_BASE ) /*!< Pointer to Timer_RGB with 3 PWM outputs (TMR_RGB) */ +#define pADI_RTC0 ((ADI_RTC_TypeDef *) ADI_RTC0_BASE ) /*!< Pointer to Real-Time Clock (RTC0) */ +#define pADI_RTC1 ((ADI_RTC_TypeDef *) ADI_RTC1_BASE ) /*!< Pointer to Real-Time Clock (RTC1) */ +#define pADI_SYS ((ADI_SYS_TypeDef *) ADI_SYS_BASE ) /*!< Pointer to System Identification and Debug Enable (SYS) */ +#define pADI_WDT0 ((ADI_WDT_TypeDef *) ADI_WDT0_BASE ) /*!< Pointer to Watchdog Timer (WDT0) */ +#define pADI_I2C0 ((ADI_I2C_TypeDef *) ADI_I2C0_BASE ) /*!< Pointer to I2C Master/Slave (I2C0) */ +#define pADI_SPI0 ((ADI_SPI_TypeDef *) ADI_SPI0_BASE ) /*!< Pointer to Serial Peripheral Interface (SPI0) */ +#define pADI_SPI1 ((ADI_SPI_TypeDef *) ADI_SPI1_BASE ) /*!< Pointer to Serial Peripheral Interface (SPI1) */ +#define pADI_SPI2 ((ADI_SPI_TypeDef *) ADI_SPI2_BASE ) /*!< Pointer to Serial Peripheral Interface (SPI2) */ +#define pADI_UART0 ((ADI_UART_TypeDef *) ADI_UART0_BASE ) /*!< Pointer to (UART0) */ +#define pADI_UART1 ((ADI_UART_TypeDef *) ADI_UART1_BASE ) /*!< Pointer to (UART1) */ +#define pADI_BEEP0 ((ADI_BEEP_TypeDef *) ADI_BEEP0_BASE ) /*!< Pointer to Beeper Driver (BEEP0) */ +#define pADI_ADC0 ((ADI_ADC_TypeDef *) ADI_ADC0_BASE ) /*!< Pointer to (ADC0) */ +#define pADI_DMA0 ((ADI_DMA_TypeDef *) ADI_DMA0_BASE ) /*!< Pointer to DMA (DMA0) */ +#define pADI_FLCC0 ((ADI_FLCC_TypeDef *) ADI_FLCC0_BASE ) /*!< Pointer to Flash Controller (FLCC0) */ +#define pADI_FLCC0_CACHE ((ADI_FLCC_CACHE_TypeDef *) ADI_FLCC0_CACHE_BASE) /*!< Pointer to Cache Controller (FLCC0_CACHE) */ +#define pADI_GPIO0 ((ADI_GPIO_TypeDef *) ADI_GPIO0_BASE ) /*!< Pointer to (GPIO0) */ +#define pADI_GPIO1 ((ADI_GPIO_TypeDef *) ADI_GPIO1_BASE ) /*!< Pointer to (GPIO1) */ +#define pADI_GPIO2 ((ADI_GPIO_TypeDef *) ADI_GPIO2_BASE ) /*!< Pointer to (GPIO2) */ +#define pADI_GPIO3 ((ADI_GPIO_TypeDef *) ADI_GPIO3_BASE ) /*!< Pointer to (GPIO3) */ +#define pADI_SPORT0 ((ADI_SPORT_TypeDef *) ADI_SPORT0_BASE ) /*!< Pointer to Serial Port (SPORT0) */ +#define pADI_CRC0 ((ADI_CRC_TypeDef *) ADI_CRC0_BASE ) /*!< Pointer to CRC Accelerator (CRC0) */ +#define pADI_RNG0 ((ADI_RNG_TypeDef *) ADI_RNG0_BASE ) /*!< Pointer to Random Number Generator (RNG0) */ +#define pADI_CRYPT0 ((ADI_CRYPT_TypeDef *) ADI_CRYPT0_BASE ) /*!< Pointer to Register Map for the Crypto Block (CRYPT0) */ +#define pADI_PMG0 ((ADI_PMG_TypeDef *) ADI_PMG0_BASE ) /*!< Pointer to Power Management (PMG0) */ +#define pADI_XINT0 ((ADI_XINT_TypeDef *) ADI_XINT0_BASE ) /*!< Pointer to External interrupt configuration (XINT0) */ +#define pADI_CLKG0_OSC ((ADI_CLKG_OSC_TypeDef *) ADI_CLKG0_OSC_BASE ) /*!< Pointer to Clocking (CLKG0_OSC) */ +#define pADI_PMG0_TST ((ADI_PMG_TST_TypeDef *) ADI_PMG0_TST_BASE ) /*!< Pointer to Power Management (PMG0_TST) */ +#define pADI_CLKG0_CLK ((ADI_CLKG_CLK_TypeDef *) ADI_CLKG0_CLK_BASE ) /*!< Pointer to Clocking (CLKG0_CLK) */ +#define pADI_BUSM0 ((ADI_BUSM_TypeDef *) ADI_BUSM0_BASE ) /*!< Pointer to Bus matrix (BUSM0) */ +#define pADI_PTI0 ((ADI_PTI_TypeDef *) ADI_PTI0_BASE ) /*!< Pointer to Parallel Test Interface (PTI0) */ +#define pADI_NVIC0 ((ADI_NVIC_TypeDef *) ADI_NVIC0_BASE ) /*!< Pointer to Cortex-M3 Interrupt Controller (NVIC0) */ + +/*! @} */ + + +/* ========================================================================= + *! \enum IRQn_Type + *! \brief Interrupt Number Assignments + * ========================================================================= */ +#ifndef __ADI_NO_DECL_ENUM_IRQn_Type__ + +typedef enum +{ + RESET_IRQn = -15, /*!< Cortex-M4 Reset */ + NonMaskableInt_IRQn = -14, /*!< Cortex-M4 Non-maskable Interrupt */ + HardFault_IRQn = -13, /*!< Cortex-M4 Hardware Fault */ + MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault */ + UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault */ + SVCall_IRQn = -5, /*!< Cortex-M4 SVCall Interrupt */ + DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor */ + PendSV_IRQn = -2, /*!< Cortex-M4 PendSV Interrupt */ + SysTick_IRQn = -1, /*!< Cortex-M4 SysTick Interrupt */ + RTC1_EVT_IRQn = 0, /*!< Event */ + XINT_EVT0_IRQn = 1, /*!< External Wakeup Interrupt n */ + XINT_EVT1_IRQn = 2, /*!< External Wakeup Interrupt n */ + XINT_EVT2_IRQn = 3, /*!< External Wakeup Interrupt n */ + XINT_EVT3_IRQn = 4, /*!< External Wakeup Interrupt n */ + WDT_EXP_IRQn = 5, /*!< Expiration */ + PMG0_VREG_OVR_IRQn = 6, /*!< Voltage Regulator (VREG) Overvoltage */ + PMG0_BATT_RANGE_IRQn = 7, /*!< Battery Voltage (VBAT) Out of Range */ + RTC0_EVT_IRQn = 8, /*!< Event */ + SYS_GPIO_INTA_IRQn = 9, /*!< GPIO Interrupt A */ + SYS_GPIO_INTB_IRQn = 10, /*!< GPIO Interrupt B */ + TMR0_EVT_IRQn = 11, /*!< Event */ + TMR1_EVT_IRQn = 12, /*!< Event */ + FLCC_EVT_IRQn = 13, /*!< Event */ + UART0_EVT_IRQn = 14, /*!< UART0 Event */ + SPI0_EVT_IRQn = 15, /*!< Event */ + SPI2_EVT_IRQn = 16, /*!< Event */ + I2C_SLV_EVT_IRQn = 17, /*!< Slave Event */ + I2C_MST_EVT_IRQn = 18, /*!< Master Event */ + DMA_CHAN_ERR_IRQn = 19, /*!< Channel Error */ + DMA0_CH0_DONE_IRQn = 20, /*!< Channel 0 Done */ + DMA0_CH1_DONE_IRQn = 21, /*!< Channel 1 Done */ + DMA0_CH2_DONE_IRQn = 22, /*!< Channel 2 Done */ + DMA0_CH3_DONE_IRQn = 23, /*!< Channel 3 Done */ + DMA0_CH4_DONE_IRQn = 24, /*!< Channel 4 Done */ + DMA0_CH5_DONE_IRQn = 25, /*!< Channel 5 Done */ + DMA0_CH6_DONE_IRQn = 26, /*!< Channel 6 Done */ + DMA0_CH7_DONE_IRQn = 27, /*!< Channel 7 Done */ + DMA0_CH8_DONE_IRQn = 28, /*!< Channel 8 Done */ + DMA0_CH9_DONE_IRQn = 29, /*!< Channel 9 Done */ + DMA0_CH10_DONE_IRQn = 30, /*!< Channel 10 Done */ + DMA0_CH11_DONE_IRQn = 31, /*!< Channel 11 Done */ + DMA0_CH12_DONE_IRQn = 32, /*!< Channel 12 Done */ + DMA0_CH13_DONE_IRQn = 33, /*!< Channel 13 Done */ + DMA0_CH14_DONE_IRQn = 34, /*!< Channel 14 Done */ + DMA0_CH15_DONE_IRQn = 35, /*!< Channel 15 Done */ + SPORT_A_EVT_IRQn = 36, /*!< Channel A Event */ + SPORT_B_EVT_IRQn = 37, /*!< Channel B Event */ + CRYPT_EVT_IRQn = 38, /*!< Event */ + DMA0_CH24_DONE_IRQn = 39, /*!< Channel 24 Done */ + TMR2_EVT_IRQn = 40, /*!< Event */ + CLKG_XTAL_OSC_EVT_IRQn = 41, /*!< Crystal Oscillator Event */ + SPI1_EVT_IRQn = 42, /*!< Event */ + CLKG_PLL_EVT_IRQn = 43, /*!< PLL Event */ + RNG0_EVT_IRQn = 44, /*!< Event */ + BEEP_EVT_IRQn = 45, /*!< Event */ + ADC0_EVT_IRQn = 46, /*!< Event */ + DMA0_CH16_DONE_IRQn = 56, /*!< Channel 16 Done */ + DMA0_CH17_DONE_IRQn = 57, /*!< Channel 17 Done */ + DMA0_CH18_DONE_IRQn = 58, /*!< Channel 18 Done */ + DMA0_CH19_DONE_IRQn = 59, /*!< Channel 19 Done */ + DMA0_CH20_DONE_IRQn = 60, /*!< Channel 20 Done */ + DMA0_CH21_DONE_IRQn = 61, /*!< Channel 21 Done */ + DMA0_CH22_DONE_IRQn = 62, /*!< Channel 22 Done */ + DMA0_CH23_DONE_IRQn = 63, /*!< Channel 23 Done */ + UART1_EVT_IRQn = 66, /*!< Event */ + DMA0_CH25_DONE_IRQn = 67, /*!< Channel 25 Done */ + DMA0_CH26_DONE_IRQn = 68, /*!< Channel 26 Done */ + TMR_RGB_EVT_IRQn = 69, /*!< Event */ + CLKG_ROOTCLK_ERR_IRQn = 71, /*!< Root Clock Error */ +} IRQn_Type; /* typedef name for fixed interrupt numbers */ +#endif /* !__ADI_NO_DECL_ENUM_IRQn_Type__ */ + + + +#if defined (_MISRA_RULES) +#pragma diag(pop) +#endif /* _MISRA_RULES */ + + +#if defined (__CC_ARM) +#pragma pop +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_typedefs.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_typedefs.h new file mode 100755 index 0000000000..356eea0165 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_typedefs.h @@ -0,0 +1,11252 @@ +/* ================================================================================ + + Project : ADuCM4050 + File : ADuCM4050_typedefs.h + Description : C Register Structures + + Date : Feb 7, 2017 + + Copyright (c) 2014-2017 Analog Devices, Inc. All Rights Reserved. + This software is proprietary and confidential to Analog Devices, Inc. and + its licensors. + + This file was auto-generated. Do not make local changes to this file. + + ================================================================================ */ + +#ifndef _ADUCM4050_TYPEDEFS_H +#define _ADUCM4050_TYPEDEFS_H + +/* pickup integer types */ +#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include +#endif /* _LANGUAGE_C */ + +#if defined ( __CC_ARM ) +#pragma push +#pragma anon_unions +#endif + + +#if defined (_MISRA_RULES) +/* + anonymous unions violate ISO 9899:1990 and therefore MISRA Rule 1.1. + Use of unions violates MISRA Rule 18.4. + Anonymous unions are required for this implementation. + Re-use of identifiers violates MISRA Rule 5.7. + Field names are repeated for the ADuCM4050 register map. +*/ +#pragma diag(push) +#pragma diag(suppress:misra_rule_1_1:"Allow anonymous unions") +#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit") +#pragma diag(suppress:misra_rule_5_3:"Header will re-use typedef identifiers") +#pragma diag(suppress:misra_rule_5_6:"Header will re-use identifiers in the same scope") +#pragma diag(suppress:misra_rule_5_7:"Header will re-use identifiers") +#pragma diag(suppress:misra_rule_18_4:"Allow the use of a union") +#endif /* _MISRA_RULES */ + +/** @defgroup LOAD 16-bit Load Value (LOAD) Register + * 16-bit Load Value (LOAD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_LOAD_Struct + *! \brief 16-bit Load Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_LOAD_t__ +typedef struct _ADI_TMR_LOAD_t { + union { + struct { + unsigned int VALUE : 16; /**< Load Value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_LOAD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_LOAD_t__ */ + +/*@}*/ + +/** @defgroup CURCNT 16-bit Timer Value (CURCNT) Register + * 16-bit Timer Value (CURCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_CURCNT_Struct + *! \brief 16-bit Timer Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CURCNT_t__ +typedef struct _ADI_TMR_CURCNT_t { + union { + struct { + unsigned int VALUE : 16; /**< Current Count */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_CURCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CURCNT_t__ */ + +/*@}*/ + +/** @defgroup CTL Control (CTL) Register + * Control (CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_CTL_Struct + *! \brief Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CTL_t__ +typedef struct _ADI_TMR_CTL_t { + union { + struct { + unsigned int PRE : 2; /**< Prescaler */ + unsigned int UP : 1; /**< Count up */ + unsigned int MODE : 1; /**< Timer Mode */ + unsigned int EN : 1; /**< Timer Enable */ + unsigned int CLK : 2; /**< Clock Select */ + unsigned int RLD : 1; /**< Reload Control */ + unsigned int reserved8 : 5; + unsigned int EVTEN : 1; /**< Event Select */ + unsigned int RSTEN : 1; /**< Counter and Prescale Reset Enable */ + unsigned int SYNCBYP : 1; /**< Synchronization Bypass */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CTL_t__ */ + +/*@}*/ + +/** @defgroup CLRINT Clear Interrupt (CLRINT) Register + * Clear Interrupt (CLRINT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_CLRINT_Struct + *! \brief Clear Interrupt Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CLRINT_t__ +typedef struct _ADI_TMR_CLRINT_t { + union { + struct { + unsigned int TIMEOUT : 1; /**< Clear Timeout Interrupt */ + unsigned int EVTCAPT : 1; /**< Clear Captured Event Interrupt */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_TMR_CLRINT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CLRINT_t__ */ + +/*@}*/ + +/** @defgroup CAPTURE Capture (CAPTURE) Register + * Capture (CAPTURE) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_CAPTURE_Struct + *! \brief Capture Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CAPTURE_t__ +typedef struct _ADI_TMR_CAPTURE_t { + union { + struct { + unsigned int VALUE : 16; /**< 16-bit Captured Value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_CAPTURE_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CAPTURE_t__ */ + +/*@}*/ + +/** @defgroup ALOAD 16-bit Load Value, Asynchronous (ALOAD) Register + * 16-bit Load Value, Asynchronous (ALOAD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_ALOAD_Struct + *! \brief 16-bit Load Value, Asynchronous Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_ALOAD_t__ +typedef struct _ADI_TMR_ALOAD_t { + union { + struct { + unsigned int VALUE : 16; /**< Load Value, Asynchronous */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_ALOAD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_ALOAD_t__ */ + +/*@}*/ + +/** @defgroup ACURCNT 16-bit Timer Value, Asynchronous (ACURCNT) Register + * 16-bit Timer Value, Asynchronous (ACURCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_ACURCNT_Struct + *! \brief 16-bit Timer Value, Asynchronous Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_ACURCNT_t__ +typedef struct _ADI_TMR_ACURCNT_t { + union { + struct { + unsigned int VALUE : 16; /**< Counter Value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_ACURCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_ACURCNT_t__ */ + +/*@}*/ + +/** @defgroup STAT Status (STAT) Register + * Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_STAT_Struct + *! \brief Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_STAT_t__ +typedef struct _ADI_TMR_STAT_t { + union { + struct { + unsigned int TIMEOUT : 1; /**< Timeout Event Occurred */ + unsigned int CAPTURE : 1; /**< Capture Event Pending */ + unsigned int reserved2 : 4; + unsigned int BUSY : 1; /**< Timer Busy */ + unsigned int PDOK : 1; /**< Clear Interrupt Register Synchronization */ + unsigned int CNTRST : 1; /**< Counter Reset Occurring */ + unsigned int reserved9 : 7; + }; + uint16_t VALUE16; + }; +} ADI_TMR_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_STAT_t__ */ + +/*@}*/ + +/** @defgroup PWMCTL PWM Control Register (PWMCTL) Register + * PWM Control Register (PWMCTL) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_TMR_PWMCTL_MATCH + *! \brief PWM Match Enabled (MATCH) Enumerations + * ========================================================================= */ +typedef enum +{ + TMR_PWMCTL_PWM_TOGGLE = 0, /**< PWM in toggle mode */ + TMR_PWMCTL_PWM_MATCH = 1 /**< PWM in match mode */ +} ADI_TMR_PWMCTL_MATCH; + + +/* ========================================================================= + *! \enum ADI_TMR_PWMCTL_IDLESTATE + *! \brief PWM Idle State (IDLESTATE) Enumerations + * ========================================================================= */ +typedef enum +{ + TMR_PWMCTL_IDLE_LOW = 0, /**< PWM idles low */ + TMR_PWMCTL_IDLE_HIGH = 1 /**< PWM idles high */ +} ADI_TMR_PWMCTL_IDLESTATE; + + +/* ========================================================================== + *! \struct ADI_TMR_PWMCTL_Struct + *! \brief PWM Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_PWMCTL_t__ +typedef struct _ADI_TMR_PWMCTL_t { + union { + struct { + unsigned int MATCH : 1; /**< PWM Match Enabled */ + unsigned int IDLESTATE : 1; /**< PWM Idle State */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_TMR_PWMCTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_PWMCTL_t__ */ + +/*@}*/ + +/** @defgroup PWMMATCH PWM Match Value (PWMMATCH) Register + * PWM Match Value (PWMMATCH) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_PWMMATCH_Struct + *! \brief PWM Match Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_PWMMATCH_t__ +typedef struct _ADI_TMR_PWMMATCH_t { + union { + struct { + unsigned int VALUE : 16; /**< PWM Match Value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_PWMMATCH_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_PWMMATCH_t__ */ + +/*@}*/ + +/** @defgroup EVENTSELECT Timer Event Selection Register (EVENTSELECT) Register + * Timer Event Selection Register (EVENTSELECT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_EVENTSELECT_Struct + *! \brief Timer Event Selection Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_EVENTSELECT_t__ +typedef struct _ADI_TMR_EVENTSELECT_t { + union { + struct { + unsigned int EVTRANGE : 6; /**< Event Select Range */ + unsigned int reserved6 : 10; + }; + uint16_t VALUE16; + }; +} ADI_TMR_EVENTSELECT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_EVENTSELECT_t__ */ + +/*@}*/ + +/** @defgroup LOAD 16-bit load value (LOAD) Register + * 16-bit load value (LOAD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_LOAD_Struct + *! \brief 16-bit load value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_LOAD_t__ +typedef struct _ADI_TMR_RGB_LOAD_t { + union { + struct { + unsigned int VALUE : 16; /**< Load value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_LOAD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_LOAD_t__ */ + +/*@}*/ + +/** @defgroup CURCNT 16-bit timer value (CURCNT) Register + * 16-bit timer value (CURCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_CURCNT_Struct + *! \brief 16-bit timer value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CURCNT_t__ +typedef struct _ADI_TMR_RGB_CURCNT_t { + union { + struct { + unsigned int VALUE : 16; /**< Current count */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_CURCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CURCNT_t__ */ + +/*@}*/ + +/** @defgroup CTL Control (CTL) Register + * Control (CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_CTL_Struct + *! \brief Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CTL_t__ +typedef struct _ADI_TMR_RGB_CTL_t { + union { + struct { + unsigned int PRE : 2; /**< Prescaler */ + unsigned int UP : 1; /**< Count up */ + unsigned int MODE : 1; /**< Timer mode */ + unsigned int EN : 1; /**< Timer enable */ + unsigned int CLK : 2; /**< Clock select */ + unsigned int RLD : 1; /**< Reload control */ + unsigned int reserved8 : 5; + unsigned int EVTEN : 1; /**< Event select */ + unsigned int RSTEN : 1; /**< Counter and prescale reset enable */ + unsigned int SYNCBYP : 1; /**< Synchronization bypass */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CTL_t__ */ + +/*@}*/ + +/** @defgroup CLRINT Clear interrupt (CLRINT) Register + * Clear interrupt (CLRINT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_CLRINT_Struct + *! \brief Clear interrupt Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CLRINT_t__ +typedef struct _ADI_TMR_RGB_CLRINT_t { + union { + struct { + unsigned int TIMEOUT : 1; /**< Clear timeout interrupt */ + unsigned int EVTCAPT : 1; /**< Clear captured event interrupt */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_CLRINT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CLRINT_t__ */ + +/*@}*/ + +/** @defgroup CAPTURE Capture (CAPTURE) Register + * Capture (CAPTURE) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_CAPTURE_Struct + *! \brief Capture Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CAPTURE_t__ +typedef struct _ADI_TMR_RGB_CAPTURE_t { + union { + struct { + unsigned int VALUE : 16; /**< 16-bit captured value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_CAPTURE_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CAPTURE_t__ */ + +/*@}*/ + +/** @defgroup ALOAD 16-bit load value, asynchronous (ALOAD) Register + * 16-bit load value, asynchronous (ALOAD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_ALOAD_Struct + *! \brief 16-bit load value, asynchronous Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_ALOAD_t__ +typedef struct _ADI_TMR_RGB_ALOAD_t { + union { + struct { + unsigned int VALUE : 16; /**< Load value, asynchronous */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_ALOAD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_ALOAD_t__ */ + +/*@}*/ + +/** @defgroup ACURCNT 16-bit timer value, asynchronous (ACURCNT) Register + * 16-bit timer value, asynchronous (ACURCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_ACURCNT_Struct + *! \brief 16-bit timer value, asynchronous Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_ACURCNT_t__ +typedef struct _ADI_TMR_RGB_ACURCNT_t { + union { + struct { + unsigned int VALUE : 16; /**< Counter value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_ACURCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_ACURCNT_t__ */ + +/*@}*/ + +/** @defgroup STAT Status (STAT) Register + * Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_STAT_Struct + *! \brief Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_STAT_t__ +typedef struct _ADI_TMR_RGB_STAT_t { + union { + struct { + unsigned int TIMEOUT : 1; /**< Timeout event occurred */ + unsigned int CAPTURE : 1; /**< Capture event pending */ + unsigned int reserved2 : 4; + unsigned int BUSY : 1; /**< Timer Busy */ + unsigned int PDOK : 1; /**< Clear Interrupt Register synchronization */ + unsigned int CNTRST : 1; /**< Counter reset occurring */ + unsigned int reserved9 : 7; + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_STAT_t__ */ + +/*@}*/ + +/** @defgroup PWM0CTL PWM0 Control Register (PWM0CTL) Register + * PWM0 Control Register (PWM0CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_PWM0CTL_Struct + *! \brief PWM0 Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM0CTL_t__ +typedef struct _ADI_TMR_RGB_PWM0CTL_t { + union { + struct { + unsigned int MATCH : 1; /**< PWM Match enabled */ + unsigned int IDLESTATE : 1; /**< PWM Idle State */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_PWM0CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM0CTL_t__ */ + +/*@}*/ + +/** @defgroup PWM0MATCH PWM0 Match Value (PWM0MATCH) Register + * PWM0 Match Value (PWM0MATCH) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_PWM0MATCH_Struct + *! \brief PWM0 Match Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM0MATCH_t__ +typedef struct _ADI_TMR_RGB_PWM0MATCH_t { + union { + struct { + unsigned int VALUE : 16; /**< PWM Match Value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_PWM0MATCH_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM0MATCH_t__ */ + +/*@}*/ + +/** @defgroup EVENTSELECT Timer Event selection Register (EVENTSELECT) Register + * Timer Event selection Register (EVENTSELECT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_EVENTSELECT_Struct + *! \brief Timer Event selection Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_EVENTSELECT_t__ +typedef struct _ADI_TMR_RGB_EVENTSELECT_t { + union { + struct { + unsigned int EVTRANGE : 6; /**< Event select range */ + unsigned int reserved6 : 10; + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_EVENTSELECT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_EVENTSELECT_t__ */ + +/*@}*/ + +/** @defgroup PWM1CTL PWM1 Control Register (PWM1CTL) Register + * PWM1 Control Register (PWM1CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_PWM1CTL_Struct + *! \brief PWM1 Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM1CTL_t__ +typedef struct _ADI_TMR_RGB_PWM1CTL_t { + union { + struct { + unsigned int MATCH : 1; /**< PWM Match enabled */ + unsigned int IDLESTATE : 1; /**< PWM Idle State */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_PWM1CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM1CTL_t__ */ + +/*@}*/ + +/** @defgroup PWM1MATCH PWM1 Match Value (PWM1MATCH) Register + * PWM1 Match Value (PWM1MATCH) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_PWM1MATCH_Struct + *! \brief PWM1 Match Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM1MATCH_t__ +typedef struct _ADI_TMR_RGB_PWM1MATCH_t { + union { + struct { + unsigned int VALUE : 16; /**< PWM Match Value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_PWM1MATCH_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM1MATCH_t__ */ + +/*@}*/ + +/** @defgroup PWM2CTL PWM2 Control Register (PWM2CTL) Register + * PWM2 Control Register (PWM2CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_PWM2CTL_Struct + *! \brief PWM2 Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM2CTL_t__ +typedef struct _ADI_TMR_RGB_PWM2CTL_t { + union { + struct { + unsigned int MATCH : 1; /**< PWM Match enabled */ + unsigned int IDLESTATE : 1; /**< PWM Idle State */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_PWM2CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM2CTL_t__ */ + +/*@}*/ + +/** @defgroup PWM2MATCH PWM2 Match Value (PWM2MATCH) Register + * PWM2 Match Value (PWM2MATCH) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_PWM2MATCH_Struct + *! \brief PWM2 Match Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM2MATCH_t__ +typedef struct _ADI_TMR_RGB_PWM2MATCH_t { + union { + struct { + unsigned int VALUE : 16; /**< PWM Match Value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_PWM2MATCH_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM2MATCH_t__ */ + +/*@}*/ + +/** @defgroup CR0 RTC Control 0 (CR0) Register + * RTC Control 0 (CR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CR0_Struct + *! \brief RTC Control 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR0_t__ +typedef struct _ADI_RTC_CR0_t { + union { + struct { + unsigned int CNTEN : 1; /**< Global Enable for the RTC */ + unsigned int ALMEN : 1; /**< Enable the RTC Alarm (Absolute) Operation */ + unsigned int ALMINTEN : 1; /**< Enable ALMINT Sourced Alarm Interrupts to the CPU */ + unsigned int TRMEN : 1; /**< Enable RTC Digital Trimming */ + unsigned int MOD60ALMEN : 1; /**< Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary */ + unsigned int MOD60ALM : 6; /**< Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary */ + unsigned int MOD60ALMINTEN : 1; /**< Enable Periodic Modulo-60 RTC Alarm Sourced Interrupts to the CPU */ + unsigned int ISOINTEN : 1; /**< Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated */ + unsigned int WPNDERRINTEN : 1; /**< Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs */ + unsigned int WSYNCINTEN : 1; /**< Enable Write Synchronization Sourced Interrupts to the CPU */ + unsigned int WPNDINTEN : 1; /**< Enable Write Pending Sourced Interrupts to the CPU */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR0_t__ */ + +/*@}*/ + +/** @defgroup SR0 RTC Status 0 (SR0) Register + * RTC Status 0 (SR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR0_Struct + *! \brief RTC Status 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR0_t__ +typedef struct _ADI_RTC_SR0_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int ALMINT : 1; /**< Alarm Interrupt Source */ + unsigned int MOD60ALMINT : 1; /**< Modulo-60 RTC Alarm Interrupt Source */ + unsigned int ISOINT : 1; /**< RTC Power-Domain Isolation Interrupt Source */ + unsigned int WPNDERRINT : 1; /**< Write Pending Error Interrupt Source */ + unsigned int WSYNCINT : 1; /**< Write Synchronisation Interrupt */ + unsigned int WPNDINT : 1; /**< Write Pending Interrupt */ + unsigned int WSYNCCR0 : 1; /**< Synchronisation Status of Posted Writes to CR0 */ + unsigned int WSYNCSR0 : 1; /**< Synchronisation Status of Posted Writes to SR0 */ + unsigned int WSYNCCNT0 : 1; /**< Synchronisation Status of Posted Writes to CNT0 */ + unsigned int WSYNCCNT1 : 1; /**< Synchronisation Status of Posted Writes to CNT1 */ + unsigned int WSYNCALM0 : 1; /**< Synchronisation Status of Posted Writes to ALM0 */ + unsigned int WSYNCALM1 : 1; /**< Synchronisation Status of Posted Writes to ALM1 */ + unsigned int WSYNCTRM : 1; /**< Synchronisation Status of Posted Writes to TRM */ + unsigned int ISOENB : 1; /**< Visibility of 32kHz Sourced Registers */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR0_t__ */ + +/*@}*/ + +/** @defgroup SR1 RTC Status 1 (SR1) Register + * RTC Status 1 (SR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR1_Struct + *! \brief RTC Status 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR1_t__ +typedef struct _ADI_RTC_SR1_t { + union { + struct { + unsigned int reserved0 : 7; + unsigned int WPNDCR0 : 1; /**< Pending Status of Posted Writes to CR0 */ + unsigned int WPNDSR0 : 1; /**< Pending Status of Posted Clearances of Interrupt Sources in SR0 */ + unsigned int WPNDCNT0 : 1; /**< Pending Status of Posted Writes to CNT0 */ + unsigned int WPNDCNT1 : 1; /**< Pending Status of Posted Writes to CNT1 */ + unsigned int WPNDALM0 : 1; /**< Pending Status of Posted Writes to ALM0 */ + unsigned int WPNDALM1 : 1; /**< Pending Status of Posted Writes to ALM1 */ + unsigned int WPNDTRM : 1; /**< Pending Status of Posted Writes to TRM */ + unsigned int reserved14 : 2; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR1_t__ */ + +/*@}*/ + +/** @defgroup CNT0 RTC Count 0 (CNT0) Register + * RTC Count 0 (CNT0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CNT0_Struct + *! \brief RTC Count 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CNT0_t__ +typedef struct _ADI_RTC_CNT0_t { + union { + struct { + unsigned int VALUE : 16; /**< Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_CNT0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CNT0_t__ */ + +/*@}*/ + +/** @defgroup CNT1 RTC Count 1 (CNT1) Register + * RTC Count 1 (CNT1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CNT1_Struct + *! \brief RTC Count 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CNT1_t__ +typedef struct _ADI_RTC_CNT1_t { + union { + struct { + unsigned int VALUE : 16; /**< Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_CNT1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CNT1_t__ */ + +/*@}*/ + +/** @defgroup ALM0 RTC Alarm 0 (ALM0) Register + * RTC Alarm 0 (ALM0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_ALM0_Struct + *! \brief RTC Alarm 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_ALM0_t__ +typedef struct _ADI_RTC_ALM0_t { + union { + struct { + unsigned int VALUE : 16; /**< Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_ALM0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_ALM0_t__ */ + +/*@}*/ + +/** @defgroup ALM1 RTC Alarm 1 (ALM1) Register + * RTC Alarm 1 (ALM1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_ALM1_Struct + *! \brief RTC Alarm 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_ALM1_t__ +typedef struct _ADI_RTC_ALM1_t { + union { + struct { + unsigned int VALUE : 16; /**< Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_ALM1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_ALM1_t__ */ + +/*@}*/ + +/** @defgroup TRM RTC Trim (TRM) Register + * RTC Trim (TRM) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_TRM_Struct + *! \brief RTC Trim Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_TRM_t__ +typedef struct _ADI_RTC_TRM_t { + union { + struct { + unsigned int VALUE : 3; /**< Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL */ + unsigned int ADD : 1; /**< Trim Polarity */ + unsigned int IVL : 2; /**< Trim Interval in Prescaled RTC Time Units */ + unsigned int IVL2EXPMIN : 4; /**< Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select */ + unsigned int reserved10 : 6; + }; + uint16_t VALUE16; + }; +} ADI_RTC_TRM_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_TRM_t__ */ + +/*@}*/ + +/** @defgroup GWY RTC Gateway (GWY) Register + * RTC Gateway (GWY) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_GWY_Struct + *! \brief RTC Gateway Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_GWY_t__ +typedef struct _ADI_RTC_GWY_t { + union { + struct { + unsigned int SWKEY : 16; /**< Software-keyed Command Issued by the CPU */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_GWY_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_GWY_t__ */ + +/*@}*/ + +/** @defgroup CR1 RTC Control 1 (CR1) Register + * RTC Control 1 (CR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CR1_Struct + *! \brief RTC Control 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR1_t__ +typedef struct _ADI_RTC_CR1_t { + union { + struct { + unsigned int CNTINTEN : 1; /**< Enable for the RTC Count Interrupt Source */ + unsigned int PSINTEN : 1; /**< Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT */ + unsigned int TRMINTEN : 1; /**< Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT */ + unsigned int CNTROLLINTEN : 1; /**< Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT */ + unsigned int CNTMOD60ROLLINTEN : 1; /**< Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source, in SR2:RTCCNTMOD60ROLLINT */ + unsigned int PRESCALE2EXP : 4; /**< Prescale Power of 2 Division Factor for the RTC Base Clock */ + unsigned int reserved9 : 7; + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR1_t__ */ + +/*@}*/ + +/** @defgroup SR2 RTC Status 2 (SR2) Register + * RTC Status 2 (SR2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR2_Struct + *! \brief RTC Status 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR2_t__ +typedef struct _ADI_RTC_SR2_t { + union { + struct { + unsigned int CNTINT : 1; /**< RTC Count Interrupt Source */ + unsigned int PSINT : 1; /**< RTC Prescaled, Modulo-1 Boundary Interrupt Source */ + unsigned int TRMINT : 1; /**< RTC Trim Interrupt Source */ + unsigned int CNTROLLINT : 1; /**< RTC Count Roll-Over Interrupt Source */ + unsigned int CNTMOD60ROLLINT : 1; /**< RTC Modulo-60 Count Roll-Over Interrupt Source */ + unsigned int CNTROLL : 1; /**< RTC Count Roll-Over */ + unsigned int CNTMOD60ROLL : 1; /**< RTC Count Modulo-60 Roll-Over */ + unsigned int TRMBDYMIR : 1; /**< Mirror of MOD:RTCTRMBDY */ + unsigned int reserved8 : 4; + unsigned int WPNDCR1MIR : 1; /**< Pending Status of Posted Writes to CR1 */ + unsigned int WPNDALM2MIR : 1; /**< Pending Status of Posted Writes to ALM2 */ + unsigned int WSYNCCR1MIR : 1; /**< Synchronization Status of Posted Writes to CR1 */ + unsigned int WSYNCALM2MIR : 1; /**< Synchronization Status of Posted Writes to ALM2 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR2_t__ */ + +/*@}*/ + +/** @defgroup SNAP0 RTC Snapshot 0 (SNAP0) Register + * RTC Snapshot 0 (SNAP0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SNAP0_Struct + *! \brief RTC Snapshot 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SNAP0_t__ +typedef struct _ADI_RTC_SNAP0_t { + union { + struct { + unsigned int VALUE : 16; /**< Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of CNT0 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SNAP0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SNAP0_t__ */ + +/*@}*/ + +/** @defgroup SNAP1 RTC Snapshot 1 (SNAP1) Register + * RTC Snapshot 1 (SNAP1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SNAP1_Struct + *! \brief RTC Snapshot 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SNAP1_t__ +typedef struct _ADI_RTC_SNAP1_t { + union { + struct { + unsigned int VALUE : 16; /**< Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT1 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SNAP1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SNAP1_t__ */ + +/*@}*/ + +/** @defgroup SNAP2 RTC Snapshot 2 (SNAP2) Register + * RTC Snapshot 2 (SNAP2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SNAP2_Struct + *! \brief RTC Snapshot 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SNAP2_t__ +typedef struct _ADI_RTC_SNAP2_t { + union { + struct { + unsigned int VALUE : 15; /**< Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT2 */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SNAP2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SNAP2_t__ */ + +/*@}*/ + +/** @defgroup MOD RTC Modulo (MOD) Register + * RTC Modulo (MOD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_MOD_Struct + *! \brief RTC Modulo Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_MOD_t__ +typedef struct _ADI_RTC_MOD_t { + union { + struct { + unsigned int CNTMOD60 : 6; /**< Modulo-60 Value of the RTC Count: CNT1 and CNT0 */ + unsigned int INCR : 4; /**< Most Recent Increment Value Added to the RTC Count in CNT1 and CNT0 */ + unsigned int TRMBDY : 1; /**< Trim Boundary Indicator */ + unsigned int CNT0_4TOZERO : 5; /**< Mirror of CNT0[4:0] */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_MOD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_MOD_t__ */ + +/*@}*/ + +/** @defgroup CNT2 RTC Count 2 (CNT2) Register + * RTC Count 2 (CNT2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CNT2_Struct + *! \brief RTC Count 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CNT2_t__ +typedef struct _ADI_RTC_CNT2_t { + union { + struct { + unsigned int VALUE : 15; /**< Fractional Bits of the RTC Real-Time Count */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_RTC_CNT2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CNT2_t__ */ + +/*@}*/ + +/** @defgroup ALM2 RTC Alarm 2 (ALM2) Register + * RTC Alarm 2 (ALM2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_ALM2_Struct + *! \brief RTC Alarm 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_ALM2_t__ +typedef struct _ADI_RTC_ALM2_t { + union { + struct { + unsigned int VALUE : 15; /**< Fractional Bits of the Alarm Target Time */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_RTC_ALM2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_ALM2_t__ */ + +/*@}*/ + +/** @defgroup SR3 RTC Status 3 (SR3) Register + * RTC Status 3 (SR3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR3_Struct + *! \brief RTC Status 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR3_t__ +typedef struct _ADI_RTC_SR3_t { + union { + struct { + unsigned int IC0IRQ : 1; /**< Sticky Interrupt Source for the RTC Input Capture Channel 0 */ + unsigned int reserved1 : 1; + unsigned int IC2IRQ : 1; /**< Sticky Interrupt Source for the RTC Input Capture Channel 2 */ + unsigned int IC3IRQ : 1; /**< Sticky Interrupt Source for the RTC Input Capture Channel 3 */ + unsigned int IC4IRQ : 1; /**< Sticky Interrupt Source for the RTC Input Capture Channel 4 */ + unsigned int SS1FEIRQ : 1; /**< Sticky Interrupt Source for the SensorStrobe Channel 1 Falling Edge */ + unsigned int SS2FEIRQ : 1; /**< Sticky Interrupt Source for the SensorStrobe Channel 2 Falling Edge */ + unsigned int SS3FEIRQ : 1; /**< Sticky Interrupt Source for the SensorStrobe Channel 3 Falling Edge */ + unsigned int SS4FEIRQ : 1; /**< Sticky Interrupt Source for the SensorStrobe Channel 4 Falling Edge */ + unsigned int SS1IRQ : 1; /**< Sticky Interrupt Source for SensorStrobe Channel 1 */ + unsigned int SS2IRQ : 1; /**< Sticky Interrupt Source for the SensorStrobe Channel 2 */ + unsigned int SS3IRQ : 1; /**< Sticky Interrupt Source for the SensorStrobe Channel 3 */ + unsigned int SS4IRQ : 1; /**< Sticky Interrupt Source for the SensorStrobe Channel 4 */ + unsigned int ALMINTMIR : 1; /**< Read-only Mirror of the SR0:ALMINT Interrupt Source */ + unsigned int reserved14 : 2; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR3_t__ */ + +/*@}*/ + +/** @defgroup CR2IC RTC Control 2 for Configuring Input Capture Channels (CR2IC) Register + * RTC Control 2 for Configuring Input Capture Channels (CR2IC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CR2IC_Struct + *! \brief RTC Control 2 for Configuring Input Capture Channels Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR2IC_t__ +typedef struct _ADI_RTC_CR2IC_t { + union { + struct { + unsigned int IC0EN : 1; /**< Enable for the RTC Input Capture Channel 0 */ + unsigned int reserved1 : 1; + unsigned int IC2EN : 1; /**< Enable for the RTC Input Capture Channel 2 */ + unsigned int IC3EN : 1; /**< Enable for the RTC Input Capture Channel 3 */ + unsigned int IC4EN : 1; /**< Enable for the RTC Input Capture Channel 4 */ + unsigned int IC0LH : 1; /**< Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0 */ + unsigned int reserved6 : 1; + unsigned int IC2LH : 1; /**< Polarity of the Active-going Capture Edge for the Input Capture Channel 2 */ + unsigned int IC3LH : 1; /**< Polarity of the Active-going Capture Edge for the Input Capture Channel 3 */ + unsigned int IC4LH : 1; /**< Polarity of the Active-going Capture Edge for the Input Capture Channel 4 */ + unsigned int IC0IRQEN : 1; /**< Interrupt Enable for the RTC Input Capture Channel 0 */ + unsigned int reserved11 : 1; + unsigned int IC2IRQEN : 1; /**< Interrupt Enable for the RTC Input Capture Channel 2 */ + unsigned int IC3IRQEN : 1; /**< Interrupt Enable for the RTC Input Capture Channel 3 */ + unsigned int IC4IRQEN : 1; /**< Interrupt Enable for the RTC Input Capture Channel 4 */ + unsigned int ICOWUSEN : 1; /**< Enable Overwrite of Unread Snapshots for All Input Capture Channels */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR2IC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR2IC_t__ */ + +/*@}*/ + +/** @defgroup CR3SS RTC Control 3 for Configuring SensorStrobe Channel (CR3SS) Register + * RTC Control 3 for Configuring SensorStrobe Channel (CR3SS) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CR3SS_Struct + *! \brief RTC Control 3 for Configuring SensorStrobe Channel Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR3SS_t__ +typedef struct _ADI_RTC_CR3SS_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int SS1EN : 1; /**< Enable for SensorStrobe Channel 1 */ + unsigned int SS2EN : 1; /**< Enable for the SensorStrobe Channel 2 */ + unsigned int SS3EN : 1; /**< Enable for the SensorStrobe Channel 3 */ + unsigned int SS4EN : 1; /**< Enable for the SensorStrobe Channel 4 */ + unsigned int SS1FEIRQEN : 1; /**< Falling Edge Interrupt Enable for the SensorStrobe Channel 1 */ + unsigned int SS2FEIRQEN : 1; /**< Falling Edge Interrupt Enable for the SensorStrobe Channel 2 */ + unsigned int SS3FEIRQEN : 1; /**< Falling Edge Interrupt Enable for the SensorStrobe Channel 3 */ + unsigned int SS4FEIRQEN : 1; /**< Falling Edge Interrupt Enable for the SensorStrobe Channel 4 */ + unsigned int SS1IRQEN : 1; /**< Interrupt Enable for SensorStrobe Channel 1 */ + unsigned int SS2IRQEN : 1; /**< Posedge EdgeInterrupt Enable for the SensorStrobe Channel 2 */ + unsigned int SS3IRQEN : 1; /**< Posedge EdgeInterrupt Enable for the SensorStrobe Channel 3 */ + unsigned int SS4IRQEN : 1; /**< Posedge EdgeInterrupt Enable for the SensorStrobe Channel 4 */ + unsigned int reserved13 : 3; + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR3SS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR3SS_t__ */ + +/*@}*/ + +/** @defgroup CR4SS RTC Control 4 for Configuring SensorStrobe Channel (CR4SS) Register + * RTC Control 4 for Configuring SensorStrobe Channel (CR4SS) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_RTC_CR4SS_SS1MSKEN + *! \brief Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 (SS1MSKEN) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR4SS_NO_MSK = 0, /**< Do not apply a mask to SensorStrobe Channel 1 Register */ + RTC_CR4SS_THERM_MSK = 1 /**< Apply thermometer decoded mask */ +} ADI_RTC_CR4SS_SS1MSKEN; + + +/* ========================================================================== + *! \struct ADI_RTC_CR4SS_Struct + *! \brief RTC Control 4 for Configuring SensorStrobe Channel Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR4SS_t__ +typedef struct _ADI_RTC_CR4SS_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int SS1MSKEN : 1; /**< Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 */ + unsigned int SS2MSKEN : 1; /**< Enable for Thermometer-Code Masking of the SensorStrobe Channel 2 */ + unsigned int SS3MSKEN : 1; /**< Enable for Thermometer-Code Masking of the SensorStrobe Channel 3 */ + unsigned int SS4MSKEN : 1; /**< Enable for Thermometer-Code Masking of the SensorStrobe Channel 4 */ + unsigned int SS1POL : 1; /**< SensorSTrobe Channel 1 Polarity Control */ + unsigned int SS2POL : 1; /**< SensorStrobe Channel 2 Polarity Control */ + unsigned int SS3POL : 1; /**< SensorStrobe Channel 3 Polarity Control */ + unsigned int SS4POL : 1; /**< SensorStrobe Channel 4 Polarity Control */ + unsigned int SS1ARLEN : 1; /**< Enable for Fine Control on SensorStrobe Channel 1 Period and Duty Cycle */ + unsigned int SS2ARLEN : 1; /**< Enable for Fine Control on SensorStrobe Channel 2 Period and Duty Cycle */ + unsigned int SS3ARLEN : 1; /**< Enable for Fine Control on SensorStrobe Channel 3 Period and Duty Cycle */ + unsigned int reserved12 : 4; + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR4SS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR4SS_t__ */ + +/*@}*/ + +/** @defgroup SSMSK RTC Mask for SensorStrobe Channel (SSMSK) Register + * RTC Mask for SensorStrobe Channel (SSMSK) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SSMSK_Struct + *! \brief RTC Mask for SensorStrobe Channel Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SSMSK_t__ +typedef struct _ADI_RTC_SSMSK_t { + union { + struct { + unsigned int SS1MSK : 4; /**< Concatenation of Thermometer-Encoded Masks for the 16-bit SensorStrobe Channels */ + unsigned int SS2MSK : 4; /**< SensorStrobe Channel 2 Period Control */ + unsigned int SS3MSK : 4; /**< SensorStrobe Channel 3 Period Control */ + unsigned int SS4MSK : 4; /**< SensorStrobe Channel 4 Period Control */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SSMSK_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SSMSK_t__ */ + +/*@}*/ + +/** @defgroup IC2 RTC Input Capture Channel 2 (IC2) Register + * RTC Input Capture Channel 2 (IC2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_IC2_Struct + *! \brief RTC Input Capture Channel 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_IC2_t__ +typedef struct _ADI_RTC_IC2_t { + union { + struct { + unsigned int IC2 : 16; /**< RTC Input Capture Channel 2 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_IC2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_IC2_t__ */ + +/*@}*/ + +/** @defgroup IC3 RTC Input Capture Channel 3 (IC3) Register + * RTC Input Capture Channel 3 (IC3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_IC3_Struct + *! \brief RTC Input Capture Channel 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_IC3_t__ +typedef struct _ADI_RTC_IC3_t { + union { + struct { + unsigned int IC3 : 16; /**< RTC Input Capture Channel 3 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_IC3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_IC3_t__ */ + +/*@}*/ + +/** @defgroup IC4 RTC Input Capture Channel 4 (IC4) Register + * RTC Input Capture Channel 4 (IC4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_IC4_Struct + *! \brief RTC Input Capture Channel 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_IC4_t__ +typedef struct _ADI_RTC_IC4_t { + union { + struct { + unsigned int IC4 : 16; /**< RTC Input Capture Channel 4 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_IC4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_IC4_t__ */ + +/*@}*/ + +/** @defgroup SS1 RTC SensorStrobe Channel 1 (SS1) Register + * RTC SensorStrobe Channel 1 (SS1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS1_Struct + *! \brief RTC SensorStrobe Channel 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS1_t__ +typedef struct _ADI_RTC_SS1_t { + union { + struct { + unsigned int SS1 : 16; /**< SensorStrobe Channel 1 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS1_t__ */ + +/*@}*/ + +/** @defgroup SS2 RTC SensorStrobe Channel 2 (SS2) Register + * RTC SensorStrobe Channel 2 (SS2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS2_Struct + *! \brief RTC SensorStrobe Channel 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS2_t__ +typedef struct _ADI_RTC_SS2_t { + union { + struct { + unsigned int SS2 : 16; /**< SensorStrobe Channel 2 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS2_t__ */ + +/*@}*/ + +/** @defgroup SS3 RTC SensorStrobe Channel 3 (SS3) Register + * RTC SensorStrobe Channel 3 (SS3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS3_Struct + *! \brief RTC SensorStrobe Channel 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS3_t__ +typedef struct _ADI_RTC_SS3_t { + union { + struct { + unsigned int SS3 : 16; /**< SensorStrobe Channel 3 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS3_t__ */ + +/*@}*/ + +/** @defgroup SS4 RTC SensorStrobe Channel 4 (SS4) Register + * RTC SensorStrobe Channel 4 (SS4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS4_Struct + *! \brief RTC SensorStrobe Channel 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS4_t__ +typedef struct _ADI_RTC_SS4_t { + union { + struct { + unsigned int SS4 : 16; /**< SensorStrobe Channel 4 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS4_t__ */ + +/*@}*/ + +/** @defgroup SR4 RTC Status 4 (SR4) Register + * RTC Status 4 (SR4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR4_Struct + *! \brief RTC Status 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR4_t__ +typedef struct _ADI_RTC_SR4_t { + union { + struct { + unsigned int WSYNCSR3 : 1; /**< Synchronisation Status of Posted Writes to SR3 */ + unsigned int WSYNCCR2IC : 1; /**< Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */ + unsigned int WSYNCCR3SS : 1; /**< Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */ + unsigned int WSYNCCR4SS : 1; /**< Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */ + unsigned int WSYNCSSMSK : 1; /**< Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register */ + unsigned int reserved5 : 1; + unsigned int WSYNCSS1 : 1; /**< Synchronization Status of Posted Writes to SensorStrobe Channel 1 */ + unsigned int WSYNCSS2 : 1; /**< Synchronization Status of Posted Writes to SensorStrobe Channel 2 */ + unsigned int WSYNCSS3 : 1; /**< Synchronization Status of Posted Writes to SensorStrobe Channel 3 */ + unsigned int WSYNCSS4 : 1; /**< Synchronization Status of Posted Writes to SensorStrobe Channel 4 */ + unsigned int RSYNCIC0 : 1; /**< Synchronization Status of Posted Reads of RTC Input Channel 0 */ + unsigned int reserved11 : 1; + unsigned int RSYNCIC2 : 1; /**< Synchronization Status of Posted Reads of RTC Input Channel 2 */ + unsigned int RSYNCIC3 : 1; /**< Synchronization Status of Posted Reads of RTC Input Channel 3 */ + unsigned int RSYNCIC4 : 1; /**< Synchronization Status of Posted Reads of RTC Input Channel 4 */ + unsigned int WSYNCSSMSKOT : 1; /**< Synchronization Status of Posted Reads Writes to Mask for SensorStrobe Channels on Time Control Register */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR4_t__ */ + +/*@}*/ + +/** @defgroup SR5 RTC Status 5 (SR5) Register + * RTC Status 5 (SR5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR5_Struct + *! \brief RTC Status 5 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR5_t__ +typedef struct _ADI_RTC_SR5_t { + union { + struct { + unsigned int WPENDSR3 : 1; /**< Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register */ + unsigned int WPENDCR2IC : 1; /**< Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */ + unsigned int WPENDCR3SS : 1; /**< Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */ + unsigned int WPENDCR4SS : 1; /**< Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */ + unsigned int WPENDSSMSK : 1; /**< Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */ + unsigned int reserved5 : 1; + unsigned int WPENDSS1 : 1; /**< Pending Status of Posted Writes to SensorStrobe Channel 1 */ + unsigned int WPENDSS2 : 1; /**< Pending Status of Posted Writes to SensorStrobe Channel 2 */ + unsigned int WPENDSS3 : 1; /**< Pending Status of Posted Writes to SensorStrobe Channel 3 */ + unsigned int WPENDSS4 : 1; /**< Pending Status of Posted Writes to SensorStrobe Channel 4 */ + unsigned int RPENDIC0 : 1; /**< Pending Status of Posted Reads of Input Capture Channel 0 */ + unsigned int reserved11 : 1; + unsigned int RPENDIC2 : 1; /**< Pending Status of Posted Reads of IC2 */ + unsigned int RPENDIC3 : 1; /**< Pending Status of Posted Reads of IC3 */ + unsigned int RPENDIC4 : 1; /**< Pending Status of Posted Reads of IC4 */ + unsigned int WPENDSSMSKOT : 1; /**< Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR5_t__ */ + +/*@}*/ + +/** @defgroup SR6 RTC Status 6 (SR6) Register + * RTC Status 6 (SR6) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR6_Struct + *! \brief RTC Status 6 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR6_t__ +typedef struct _ADI_RTC_SR6_t { + union { + struct { + unsigned int IC0UNR : 1; /**< Sticky Unread Status of the Input Capture Channel 0 */ + unsigned int reserved1 : 1; + unsigned int IC2UNR : 1; /**< Sticky Unread Status of the Input Capture Channel 2 */ + unsigned int IC3UNR : 1; /**< Sticky Unread Status of the Input Capture Channel 3 */ + unsigned int IC4UNR : 1; /**< Sticky Unread Status of the Input Capture Channel 4 */ + unsigned int reserved5 : 3; + unsigned int IC0SNAP : 1; /**< Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture Channel RTC Input Capture Channel 0 */ + unsigned int FRZCNTPTR : 2; /**< Pointer for the Triple-Read Sequence of FRZCNT */ + unsigned int reserved11 : 5; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR6_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR6_t__ */ + +/*@}*/ + +/** @defgroup SS1TGT RTC SensorStrobe Channel 1 Target (SS1TGT) Register + * RTC SensorStrobe Channel 1 Target (SS1TGT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS1TGT_Struct + *! \brief RTC SensorStrobe Channel 1 Target Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS1TGT_t__ +typedef struct _ADI_RTC_SS1TGT_t { + union { + struct { + unsigned int SS1TGT : 16; /**< Current Target Value for the SensorStrobe Channel 1 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS1TGT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS1TGT_t__ */ + +/*@}*/ + +/** @defgroup FRZCNT RTC Freeze Count (FRZCNT) Register + * RTC Freeze Count (FRZCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_FRZCNT_Struct + *! \brief RTC Freeze Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_FRZCNT_t__ +typedef struct _ADI_RTC_FRZCNT_t { + union { + struct { + unsigned int FRZCNT : 16; /**< RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_FRZCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_FRZCNT_t__ */ + +/*@}*/ + +/** @defgroup SS2TGT RTC SensorStrobe Channel 2 Target (SS2TGT) Register + * RTC SensorStrobe Channel 2 Target (SS2TGT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS2TGT_Struct + *! \brief RTC SensorStrobe Channel 2 Target Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS2TGT_t__ +typedef struct _ADI_RTC_SS2TGT_t { + union { + struct { + unsigned int SS2TGT : 16; /**< Current, Cumulative Target Time for SensorStrobe Channel 2, Taking Account of Any Auto-reloading */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS2TGT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS2TGT_t__ */ + +/*@}*/ + +/** @defgroup SS3TGT RTC SensorStrobe Channel 3 Target (SS3TGT) Register + * RTC SensorStrobe Channel 3 Target (SS3TGT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS3TGT_Struct + *! \brief RTC SensorStrobe Channel 3 Target Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS3TGT_t__ +typedef struct _ADI_RTC_SS3TGT_t { + union { + struct { + unsigned int SS3TGT : 16; /**< Current, Cumulative Target Time for SensorStrobe Channel 3, Taking Account of Any Auto-reloading */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS3TGT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS3TGT_t__ */ + +/*@}*/ + +/** @defgroup SS1LOWDUR RTC Auto-Reload Low Duration for SensorStrobe Channel 1 (SS1LOWDUR) Register + * RTC Auto-Reload Low Duration for SensorStrobe Channel 1 (SS1LOWDUR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS1LOWDUR_Struct + *! \brief RTC Auto-Reload Low Duration for SensorStrobe Channel 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS1LOWDUR_t__ +typedef struct _ADI_RTC_SS1LOWDUR_t { + union { + struct { + unsigned int SS1LOWDUR : 16; /**< Low Duration for SensorStrobe Channel 1. */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS1LOWDUR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS1LOWDUR_t__ */ + +/*@}*/ + +/** @defgroup SS2LOWDUR RTC Auto-Reload Low Duration for SensorStrobe Channel 2 (SS2LOWDUR) Register + * RTC Auto-Reload Low Duration for SensorStrobe Channel 2 (SS2LOWDUR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS2LOWDUR_Struct + *! \brief RTC Auto-Reload Low Duration for SensorStrobe Channel 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS2LOWDUR_t__ +typedef struct _ADI_RTC_SS2LOWDUR_t { + union { + struct { + unsigned int SS2LOWDUR : 16; /**< Low Duration for SensorStrobe Channel 2. */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS2LOWDUR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS2LOWDUR_t__ */ + +/*@}*/ + +/** @defgroup SS3LOWDUR RTC Auto-Reload Low Duration for SensorStrobe Channel 3 (SS3LOWDUR) Register + * RTC Auto-Reload Low Duration for SensorStrobe Channel 3 (SS3LOWDUR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS3LOWDUR_Struct + *! \brief RTC Auto-Reload Low Duration for SensorStrobe Channel 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS3LOWDUR_t__ +typedef struct _ADI_RTC_SS3LOWDUR_t { + union { + struct { + unsigned int SS3LOWDUR : 16; /**< Low Duration for SensorStrobe Channel 3. */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS3LOWDUR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS3LOWDUR_t__ */ + +/*@}*/ + +/** @defgroup SS1HIGHDUR RTC Auto-Reload High Duration for SensorStrobe Channel 1 (SS1HIGHDUR) Register + * RTC Auto-Reload High Duration for SensorStrobe Channel 1 (SS1HIGHDUR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS1HIGHDUR_Struct + *! \brief RTC Auto-Reload High Duration for SensorStrobe Channel 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS1HIGHDUR_t__ +typedef struct _ADI_RTC_SS1HIGHDUR_t { + union { + struct { + unsigned int SS1HIGHDUR : 16; /**< High Duration for SensorStrobe Channel 1. */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS1HIGHDUR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS1HIGHDUR_t__ */ + +/*@}*/ + +/** @defgroup SS2HIGHDUR RTC Auto-Reload High Duration for SensorStrobe Channel 2 (SS2HIGHDUR) Register + * RTC Auto-Reload High Duration for SensorStrobe Channel 2 (SS2HIGHDUR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS2HIGHDUR_Struct + *! \brief RTC Auto-Reload High Duration for SensorStrobe Channel 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS2HIGHDUR_t__ +typedef struct _ADI_RTC_SS2HIGHDUR_t { + union { + struct { + unsigned int SS2HIGHDUR : 16; /**< High Duration for SensorStrobe Channel 2. */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS2HIGHDUR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS2HIGHDUR_t__ */ + +/*@}*/ + +/** @defgroup SS3HIGHDUR RTC Auto-Reload High Duration for SensorStrobe Channel 3 (SS3HIGHDUR) Register + * RTC Auto-Reload High Duration for SensorStrobe Channel 3 (SS3HIGHDUR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS3HIGHDUR_Struct + *! \brief RTC Auto-Reload High Duration for SensorStrobe Channel 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS3HIGHDUR_t__ +typedef struct _ADI_RTC_SS3HIGHDUR_t { + union { + struct { + unsigned int SS3HIGHDUR : 16; /**< High Duration for SensorStrobe Channel 3. */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS3HIGHDUR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS3HIGHDUR_t__ */ + +/*@}*/ + +/** @defgroup SSMSKOT RTC Masks for SensorStrobe Channels on Time Control (SSMSKOT) Register + * RTC Masks for SensorStrobe Channels on Time Control (SSMSKOT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SSMSKOT_Struct + *! \brief RTC Masks for SensorStrobe Channels on Time Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SSMSKOT_t__ +typedef struct _ADI_RTC_SSMSKOT_t { + union { + struct { + unsigned int SS1MSKOT : 4; /**< Concatenation of Thermometer-encoded Masks for the 16-bit SensorStrobe Channels */ + unsigned int SS2MSKOT : 4; /**< SensorStrobe Channel 2 on Time Control */ + unsigned int SS3MSKOT : 4; /**< SensorStrobe Channel 3 on Time Control */ + unsigned int SS4MSKOT : 4; /**< SensorStrobe Channel 4 on Time Control */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SSMSKOT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SSMSKOT_t__ */ + +/*@}*/ + +/** @defgroup CR5SSS RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling (CR5SSS) Register + * RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling (CR5SSS) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CR5SSS_Struct + *! \brief RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR5SSS_t__ +typedef struct _ADI_RTC_CR5SSS_t { + union { + struct { + unsigned int SS1SMPEN : 3; /**< GPIO Input Sample Enable for SensorStrobe Channel 1 */ + unsigned int SS1SMPMTCHIRQEN : 1; /**< Sample Activity Interrupt Enable for SensorStrobe Channel 1 */ + unsigned int SS2SMPEN : 3; /**< GPIO Input Sample Enable for SensorStrobe Channel 2 */ + unsigned int SS2SMPMTCHIRQEN : 1; /**< Sample Activity Interrupt Enable for SensorStrobe Channel 2 */ + unsigned int SS3SMPEN : 3; /**< GPIO Input Sample Enable for SensorStrobe Channel 3 */ + unsigned int SS3SMPMTCHIRQEN : 1; /**< Sample Activity Interrupt Enable for SensorStrobe Channel 3 */ + unsigned int reserved12 : 4; + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR5SSS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR5SSS_t__ */ + +/*@}*/ + +/** @defgroup CR6SSS RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge (CR6SSS) Register + * RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge (CR6SSS) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_RTC_CR6SSS_SS1SMPONFE + *! \brief GPIO Sample Around Falling Edge of SensorStrobe Channel 1 (SS1SMPONFE) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR6SSS_SS1NOFES = 0, /**< No sampling of input around falling edge */ + RTC_CR6SSS_SS1BFES = 1, /**< Input sampled one clock cycle before falling edge of the SensorStrobe channel 1 */ + RTC_CR6SSS_SS1FES = 2, /**< Input sampled at falling edge of the SensorStrobe channel 1 */ + RTC_CR6SSS_SS1AFES = 3 /**< Input sampled one clock cycle after falling edge of the SensorStrobe channel 1 */ +} ADI_RTC_CR6SSS_SS1SMPONFE; + + +/* ========================================================================= + *! \enum ADI_RTC_CR6SSS_SS1SMPONRE + *! \brief GPIO Sample Around Rising Edge of SensorStrobe Channel 1 (SS1SMPONRE) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR6SSS_SS1NORES = 0, /**< No sampling of input around rising edge */ + RTC_CR6SSS_SS1BRES = 1, /**< Input sampled one clock cycle before rising edge of the SensorStrobe channel 1 */ + RTC_CR6SSS_SS1RES = 2, /**< Input sampled at rising edge of the SensorStrobe channel 1 */ + RTC_CR6SSS_SS1ARES = 3 /**< Input sampled one clock cycle after rising edge of the SensorStrobe channel 1 */ +} ADI_RTC_CR6SSS_SS1SMPONRE; + + +/* ========================================================================= + *! \enum ADI_RTC_CR6SSS_SS2SMPONFE + *! \brief GPIO Sample Around Falling Edge of SensorStrobe Channel 2 (SS2SMPONFE) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR6SSS_SS2NOFES = 0, /**< No sampling of input around falling edge */ + RTC_CR6SSS_SS2BFES = 1, /**< Input sampled one clock cycle before falling edge of the SensorStrobe channel 2 */ + RTC_CR6SSS_SS2FES = 2, /**< Input sampled at falling edge of the SensorStrobe channel 2 */ + RTC_CR6SSS_SS2AFES = 3 /**< Input sampled one clock cycle after falling edge of the SensorStrobe channel 2 */ +} ADI_RTC_CR6SSS_SS2SMPONFE; + + +/* ========================================================================= + *! \enum ADI_RTC_CR6SSS_SS2SMPONRE + *! \brief GPIO Sample Around Rising Edge of SensorStrobe Channel 2 (SS2SMPONRE) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR6SSS_SS2NORES = 0, /**< No sampling of input around rising edge */ + RTC_CR6SSS_SS2BRES = 1, /**< Input sampled one clock cycle before rising edge of the SensorStrobe channel 2 */ + RTC_CR6SSS_SS2RES = 2, /**< Input sampled at rising edge of the SensorStrobe channel 2 */ + RTC_CR6SSS_SS2ARES = 3 /**< Input sampled one clock cycle after rising edge of the SensorStrobe channel 2 */ +} ADI_RTC_CR6SSS_SS2SMPONRE; + + +/* ========================================================================= + *! \enum ADI_RTC_CR6SSS_SS3SMPONFE + *! \brief GPIO Sample Around Falling Edge of SensorStrobe Channel 3 (SS3SMPONFE) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR6SSS_SS3NOFES = 0, /**< No sampling of input around falling edge */ + RTC_CR6SSS_SS3BFES = 1, /**< Input sampled one clock cycle before falling edge of the SensorStrobe channel 3 */ + RTC_CR6SSS_SS3FES = 2, /**< Input sampled at falling edge of the SensorStrobe channel 3 */ + RTC_CR6SSS_SS3AFES = 3 /**< Input sampled one clock cycle after falling edge of the SensorStrobe channel 3 */ +} ADI_RTC_CR6SSS_SS3SMPONFE; + + +/* ========================================================================= + *! \enum ADI_RTC_CR6SSS_SS3SMPONRE + *! \brief GPIO Sample Around Rising Edge of SensorStrobe Channel 3 (SS3SMPONRE) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR6SSS_SS3NORES = 0, /**< No sampling of input around rising edge */ + RTC_CR6SSS_SS3BRES = 1, /**< Input sampled one clock cycle before rising edge of the SensorStrobe channel 3 */ + RTC_CR6SSS_SS3RES = 2, /**< Input sampled at rising edge of the SensorStrobe channel 3 */ + RTC_CR6SSS_SS3ARES = 3 /**< Input sampled one clock cycle after rising edge of the SensorStrobe channel 3 */ +} ADI_RTC_CR6SSS_SS3SMPONRE; + + +/* ========================================================================== + *! \struct ADI_RTC_CR6SSS_Struct + *! \brief RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR6SSS_t__ +typedef struct _ADI_RTC_CR6SSS_t { + union { + struct { + unsigned int SS1SMPONFE : 2; /**< GPIO Sample Around Falling Edge of SensorStrobe Channel 1 */ + unsigned int SS1SMPONRE : 2; /**< GPIO Sample Around Rising Edge of SensorStrobe Channel 1 */ + unsigned int SS2SMPONFE : 2; /**< GPIO Sample Around Falling Edge of SensorStrobe Channel 2 */ + unsigned int SS2SMPONRE : 2; /**< GPIO Sample Around Rising Edge of SensorStrobe Channel 2 */ + unsigned int SS3SMPONFE : 2; /**< GPIO Sample Around Falling Edge of SensorStrobe Channel 3 */ + unsigned int SS3SMPONRE : 2; /**< GPIO Sample Around Rising Edge of SensorStrobe Channel 3 */ + unsigned int reserved12 : 4; + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR6SSS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR6SSS_t__ */ + +/*@}*/ + +/** @defgroup CR7SSS RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity (CR7SSS) Register + * RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity (CR7SSS) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_RTC_CR7SSS_SS1SMPPTRN + *! \brief Sample Activity Selection for SensorStrobe Channel 1 (SS1SMPPTRN) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR7SSS_SS1SMPCHNG = 0, /**< Current GPIO sample is not same as previous sample */ + RTC_CR7SSS_SS1SMPSAME = 1, /**< Current GPIO sample is same as previous sample */ + RTC_CR7SSS_SS1SMPMTCH = 2, /**< Current GPIO sample is same as expected sample */ + RTC_CR7SSS_SS1SMPNOMTCH = 3 /**< Current GPIO sample is not same as expected sample */ +} ADI_RTC_CR7SSS_SS1SMPPTRN; + + +/* ========================================================================= + *! \enum ADI_RTC_CR7SSS_SS2SMPPTRN + *! \brief Sample Activity Selection for SensorStrobe Channel 2 (SS2SMPPTRN) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR7SSS_SS2SMPCHNG = 0, /**< Current GPIO sample is not same as previous sample */ + RTC_CR7SSS_SS2SMPSAME = 1, /**< Current GPIO sample is same as previous sample */ + RTC_CR7SSS_SS2SMPMTCH = 2, /**< Current GPIO sample is same as expected sample */ + RTC_CR7SSS_SS2SMPNOMTCH = 3 /**< Current GPIO sample is not same as expected sample */ +} ADI_RTC_CR7SSS_SS2SMPPTRN; + + +/* ========================================================================= + *! \enum ADI_RTC_CR7SSS_SS3SMPPTRN + *! \brief Sample Activity Selection for SensorStrobe Channel 3 (SS3SMPPTRN) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR7SSS_SS3SMPCHNG = 0, /**< Current GPIO sample is not same as previous sample */ + RTC_CR7SSS_SS3SMPSAME = 1, /**< Current GPIO sample is same as previous sample */ + RTC_CR7SSS_SS3SMPMTCH = 2, /**< Current GPIO sample is same as expected sample */ + RTC_CR7SSS_SS3SMPNOMTCH = 3 /**< Current GPIO sample is not same as expected sample */ +} ADI_RTC_CR7SSS_SS3SMPPTRN; + + +/* ========================================================================== + *! \struct ADI_RTC_CR7SSS_Struct + *! \brief RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR7SSS_t__ +typedef struct _ADI_RTC_CR7SSS_t { + union { + struct { + unsigned int SS1SMPEXP : 3; /**< Expected GPIO Sample for SensorStrobe Channel 1 */ + unsigned int SS1SMPPTRN : 2; /**< Sample Activity Selection for SensorStrobe Channel 1 */ + unsigned int SS2SMPEXP : 3; /**< Expected GPIO Sample for SensorStrobe Channel 2 */ + unsigned int SS2SMPPTRN : 2; /**< Sample Activity Selection for SensorStrobe Channel 2 */ + unsigned int SS3SMPEXP : 3; /**< Expected GPIO Sample for SensorStrobe Channel 3 */ + unsigned int SS3SMPPTRN : 2; /**< Sample Activity Selection for SensorStrobe Channel 3 */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR7SSS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR7SSS_t__ */ + +/*@}*/ + +/** @defgroup SR7 RTC Status 7 (SR7) Register + * RTC Status 7 (SR7) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR7_Struct + *! \brief RTC Status 7 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR7_t__ +typedef struct _ADI_RTC_SR7_t { + union { + struct { + unsigned int SS1SMP : 3; /**< Latest GPIO Sample for SensorStrobe Channel 1 */ + unsigned int SS1SMPMTCHIRQ : 1; /**< Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 1 */ + unsigned int SS2SMP : 3; /**< Latest GPIO Sample for SensorStrobe Channel 2 */ + unsigned int SS2SMPMTCHIRQ : 1; /**< Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 2 */ + unsigned int SS3SMP : 3; /**< Latest GPIO Sample for SensorStrobe Channel 3 */ + unsigned int SS3SMPMTCHIRQ : 1; /**< Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 3 */ + unsigned int SS1OUT : 1; /**< Output Value for SensorStrobe Channel 1 */ + unsigned int SS2OUT : 1; /**< Output Value for SensorStrobe Channel 2 */ + unsigned int SS3OUT : 1; /**< Output Value for SensorStrobe Channel 3 */ + unsigned int SS4OUT : 1; /**< Output Value for SensorStrobe Channel 4 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR7_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR7_t__ */ + +/*@}*/ + +/** @defgroup SR8 RTC Status 8 (SR8) Register + * RTC Status 8 (SR8) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR8_Struct + *! \brief RTC Status 8 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR8_t__ +typedef struct _ADI_RTC_SR8_t { + union { + struct { + unsigned int WSYNCSS1LOWDUR : 1; /**< Synchronisation Status of Posted Writes to SensorStrobe Channel 1 Low Duration Register */ + unsigned int WSYNCSS2LOWDUR : 1; /**< Synchronisation Status of Posted Writes to SensorStrobe Channel 2 Low Duration Register */ + unsigned int WSYNCSS3LOWDUR : 1; /**< Synchronisation Status of Posted Writes to SensorStrobe Channel 3 Low Duration Register */ + unsigned int reserved3 : 1; + unsigned int WSYNCSS1HIGHDUR : 1; /**< Synchronisation Status of Posted Writes to SensorStrobe Channel 1 High Duration Register */ + unsigned int WSYNCSS2HIGHDUR : 1; /**< Synchronisation Status of Posted Writes to SensorStrobe Channel 2 High Duration Register */ + unsigned int WSYNCSS3HIGHDUR : 1; /**< Synchronisation Status of Posted Writes to SensorStrobe Channel 3 High Duration Register */ + unsigned int reserved7 : 1; + unsigned int WSYNCCR5SSS : 1; /**< Synchronisation Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register */ + unsigned int WSYNCCR6SSS : 1; /**< Synchronisation Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register */ + unsigned int WSYNCCR7SSS : 1; /**< Synchronisation Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register */ + unsigned int WSYNCSR7 : 1; /**< Synchronisation Status of Posted Writes to Status 7 Register */ + unsigned int WSYNCGPMUX0 : 1; /**< Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 0 */ + unsigned int WSYNCGPMUX1 : 1; /**< Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 1 */ + unsigned int reserved14 : 2; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR8_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR8_t__ */ + +/*@}*/ + +/** @defgroup SR9 RTC Status 9 (SR9) Register + * RTC Status 9 (SR9) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR9_Struct + *! \brief RTC Status 9 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR9_t__ +typedef struct _ADI_RTC_SR9_t { + union { + struct { + unsigned int WPENDSS1LOWDUR : 1; /**< Pending Status of Posted Writes to SensortStrobe Channel 1 Low Duration Register */ + unsigned int WPENDSS2LOWDUR : 1; /**< Pending Status of Posted Writes to SensortStrobe Channel 2 Low Duration Register */ + unsigned int WPENDSS3LOWDUR : 1; /**< Pending Status of Posted Writes to SensortStrobe Channel 3 Low Duration Register */ + unsigned int reserved3 : 1; + unsigned int WPENDSS1HIGHDUR : 1; /**< Pending Status of Posted Writes to SensortStrobe Channel 1 High Duration Register */ + unsigned int WPENDSS2HIGHDUR : 1; /**< Pending Status of Posted Writes to SensortStrobe Channel 2 High Duration Register */ + unsigned int WPENDSS3HIGHDUR : 1; /**< Pending Status of Posted Writes to SensortStrobe Channel 3 High Duration Register */ + unsigned int reserved7 : 1; + unsigned int WPENDCR5SSS : 1; /**< Pending Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register */ + unsigned int WPENDCR6SSS : 1; /**< Pending Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register */ + unsigned int WPENDCR7SSS : 1; /**< Pending Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register */ + unsigned int WPENDSR7 : 1; /**< Pending Status of Posted Writes to SR7 */ + unsigned int WPENDGPMUX0 : 1; /**< Pending Status of Posted Writes to GPMUX0 */ + unsigned int WPENDGPMUX1 : 1; /**< Pending Status of Posted Writes to GPMUX1 */ + unsigned int reserved14 : 2; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR9_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR9_t__ */ + +/*@}*/ + +/** @defgroup GPMUX0 RTC GPIO Pin Mux Control Register 0 (GPMUX0) Register + * RTC GPIO Pin Mux Control Register 0 (GPMUX0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_GPMUX0_Struct + *! \brief RTC GPIO Pin Mux Control Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_GPMUX0_t__ +typedef struct _ADI_RTC_GPMUX0_t { + union { + struct { + unsigned int SS1GPIN0SEL : 3; /**< GPIO Mux Selection for SensorStrobe Channel 1 Input0 */ + unsigned int SS1GPIN1SEL : 3; /**< GPIO Mux Selection for SensorStrobe Channel 1 Input 1 */ + unsigned int SS1GPIN2SEL : 3; /**< GPIO Mux Selection for SensorStrobe Channel 1 Input 2 */ + unsigned int SS2GPIN0SEL : 3; /**< GPIO Mux Selection for SensorStrobe Channel 2 Input 0 */ + unsigned int SS2GPIN1SEL : 3; /**< GPIO Mux Selection for SensorStrobe Channel 2 Input 1 */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_RTC_GPMUX0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_GPMUX0_t__ */ + +/*@}*/ + +/** @defgroup GPMUX1 RTC GPIO Pin Mux Control Register 1 (GPMUX1) Register + * RTC GPIO Pin Mux Control Register 1 (GPMUX1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_GPMUX1_Struct + *! \brief RTC GPIO Pin Mux Control Register 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_GPMUX1_t__ +typedef struct _ADI_RTC_GPMUX1_t { + union { + struct { + unsigned int SS2GPIN2SEL : 3; /**< GPIO Mux Selection for SensorStrobe Channel 2 Input 2 */ + unsigned int SS3GPIN0SEL : 3; /**< GPIO Mux Selection for SensorStrobe Channel 3 Input 0 */ + unsigned int SS3GPIN1SEL : 3; /**< GPIO Mux Selection for SensorStrobe Channel 3 Input 1 */ + unsigned int SS3GPIN2SEL : 3; /**< GPIO Mux Selection for SensorStrobe Channel 3 Input 2 */ + unsigned int reserved12 : 2; + unsigned int SS1DIFFOUT : 1; /**< Differential SensorStrobe Out Option for SensorStrobe Channel 1 */ + unsigned int SS3DIFFOUT : 1; /**< Differential SensorStrobe Out Option for SensorStrobe Channel 3 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_GPMUX1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_GPMUX1_t__ */ + +/*@}*/ + +/** @defgroup ADIID ADI Identification (ADIID) Register + * ADI Identification (ADIID) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SYS_ADIID_Struct + *! \brief ADI Identification Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_ADIID_t__ +typedef struct _ADI_SYS_ADIID_t { + union { + struct { + unsigned int VALUE : 16; /**< Reads a fixed value of 0x4144 to indicate to debuggers that they are connected to an Analog Devices implemented Cortex based part */ + }; + uint16_t VALUE16; + }; +} ADI_SYS_ADIID_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_ADIID_t__ */ + +/*@}*/ + +/** @defgroup CHIPID Chip Identifier (CHIPID) Register + * Chip Identifier (CHIPID) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SYS_CHIPID_Struct + *! \brief Chip Identifier Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_CHIPID_t__ +typedef struct _ADI_SYS_CHIPID_t { + union { + struct { + unsigned int REV : 4; /**< Silicon revision */ + unsigned int PARTID : 12; /**< Part identifier */ + }; + uint16_t VALUE16; + }; +} ADI_SYS_CHIPID_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_CHIPID_t__ */ + +/*@}*/ + +/** @defgroup SWDEN Serial Wire Debug Enable (SWDEN) Register + * Serial Wire Debug Enable (SWDEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SYS_SWDEN_Struct + *! \brief Serial Wire Debug Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_SWDEN_t__ +typedef struct _ADI_SYS_SWDEN_t { + union { + struct { + unsigned int VALUE : 16; /**< To enable SWD interface */ + }; + uint16_t VALUE16; + }; +} ADI_SYS_SWDEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_SWDEN_t__ */ + +/*@}*/ + +/** @defgroup LOAD Load Value (LOAD) Register + * Load Value (LOAD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_WDT_LOAD_Struct + *! \brief Load Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_LOAD_t__ +typedef struct _ADI_WDT_LOAD_t { + union { + struct { + unsigned int VALUE : 16; /**< Load Value */ + }; + uint16_t VALUE16; + }; +} ADI_WDT_LOAD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_LOAD_t__ */ + +/*@}*/ + +/** @defgroup CCNT Current Count Value (CCNT) Register + * Current Count Value (CCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_WDT_CCNT_Struct + *! \brief Current Count Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_CCNT_t__ +typedef struct _ADI_WDT_CCNT_t { + union { + struct { + unsigned int VALUE : 16; /**< Current Count Value */ + }; + uint16_t VALUE16; + }; +} ADI_WDT_CCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_CCNT_t__ */ + +/*@}*/ + +/** @defgroup CTL Control (CTL) Register + * Control (CTL) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_WDT_CTL_IRQ + *! \brief Timer Interrupt (IRQ) Enumerations + * ========================================================================= */ +typedef enum +{ + WDT_CTL_RST = 0, /**< WDT asserts reset when timed out */ + WDT_CTL_INT = 1 /**< WDT generates interrupt when timed out */ +} ADI_WDT_CTL_IRQ; + + +/* ========================================================================= + *! \enum ADI_WDT_CTL_PRE + *! \brief Prescaler (PRE) Enumerations + * ========================================================================= */ +typedef enum +{ + WDT_CTL_DIV1 = 0, /**< Source clock/1 */ + WDT_CTL_DIV16 = 1, /**< Source clock/16 */ + WDT_CTL_DIV256 = 2 /**< Source clock/256 (default) */ +} ADI_WDT_CTL_PRE; + + +/* ========================================================================= + *! \enum ADI_WDT_CTL_EN + *! \brief Timer Enable (EN) Enumerations + * ========================================================================= */ +typedef enum +{ + WDT_CTL_WDT_DIS = 0, /**< WDT not enabled */ + WDT_CTL_WDT_EN = 1 /**< WDT enabled */ +} ADI_WDT_CTL_EN; + + +/* ========================================================================= + *! \enum ADI_WDT_CTL_MODE + *! \brief Timer Mode (MODE) Enumerations + * ========================================================================= */ +typedef enum +{ + WDT_CTL_FREE_RUN = 0, /**< Free running mode */ + WDT_CTL_PERIODIC = 1 /**< Periodic mode */ +} ADI_WDT_CTL_MODE; + + +/* ========================================================================== + *! \struct ADI_WDT_CTL_Struct + *! \brief Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_CTL_t__ +typedef struct _ADI_WDT_CTL_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int IRQ : 1; /**< Timer Interrupt */ + unsigned int PRE : 2; /**< Prescaler */ + unsigned int reserved4 : 1; + unsigned int EN : 1; /**< Timer Enable */ + unsigned int MODE : 1; /**< Timer Mode */ + unsigned int SPARE : 1; /**< Unused Spare Bit */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_WDT_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_CTL_t__ */ + +/*@}*/ + +/** @defgroup RESTART Clear Interrupt (RESTART) Register + * Clear Interrupt (RESTART) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_WDT_RESTART_Struct + *! \brief Clear Interrupt Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_RESTART_t__ +typedef struct _ADI_WDT_RESTART_t { + union { + struct { + unsigned int CLRWORD : 16; /**< Clear Watchdog */ + }; + uint16_t VALUE16; + }; +} ADI_WDT_RESTART_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_RESTART_t__ */ + +/*@}*/ + +/** @defgroup STAT Status (STAT) Register + * Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_WDT_STAT_Struct + *! \brief Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_STAT_t__ +typedef struct _ADI_WDT_STAT_t { + union { + struct { + unsigned int IRQ : 1; /**< WDT Interrupt */ + unsigned int CLRIRQ : 1; /**< Clear Interrupt Register Write Sync in Progress */ + unsigned int LOADING : 1; /**< Load Register Write Sync in Progress */ + unsigned int COUNTING : 1; /**< Control Register Write Sync in Progress */ + unsigned int LOCKED : 1; /**< Lock Status Bit */ + unsigned int RSTCTL : 1; /**< Reset Control Register Written and Locked */ + unsigned int reserved6 : 10; + }; + uint16_t VALUE16; + }; +} ADI_WDT_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_STAT_t__ */ + +/*@}*/ + +/** @defgroup MCTL Master Control (MCTL) Register + * Master Control (MCTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_MCTL_Struct + *! \brief Master Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MCTL_t__ +typedef struct _ADI_I2C_MCTL_t { + union { + struct { + unsigned int MASEN : 1; /**< Master Enable */ + unsigned int COMPLETE : 1; /**< Start Back-off Disable */ + unsigned int LOOPBACK : 1; /**< Internal Loopback Enable */ + unsigned int STRETCHSCL : 1; /**< Stretch SCL Enable */ + unsigned int IENMRX : 1; /**< Receive Request Interrupt Enable */ + unsigned int IENMTX : 1; /**< Transmit Request Interrupt Enable */ + unsigned int IENALOST : 1; /**< Arbitration Lost Interrupt Enable */ + unsigned int IENACK : 1; /**< ACK Not Received Interrupt Enable */ + unsigned int IENCMP : 1; /**< Transaction Completed (or Stop Detected) Interrupt Enable */ + unsigned int MXMITDEC : 1; /**< Decrement Master Tx FIFO Status When a Byte Txed */ + unsigned int MRXDMA : 1; /**< Enable Master Rx DMA Request */ + unsigned int MTXDMA : 1; /**< Enable Master Tx DMA Request */ + unsigned int BUSCLR : 1; /**< Bus-Clear Enable */ + unsigned int STOPBUSCLR : 1; /**< Prestop Bus Clear */ + unsigned int reserved14 : 2; + }; + uint16_t VALUE16; + }; +} ADI_I2C_MCTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MCTL_t__ */ + +/*@}*/ + +/** @defgroup MSTAT Master Status (MSTAT) Register + * Master Status (MSTAT) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_I2C_MSTAT_MTXF + *! \brief Master Transmit FIFO Status (MTXF) Enumerations + * ========================================================================= */ +typedef enum +{ + I2C_MSTAT_FIFO_EMPTY = 0, /**< FIFO Empty. */ + I2C_MSTAT_FIFO_1BYTE = 2, /**< 1 byte in FIFO. */ + I2C_MSTAT_FIFO_FULL = 3 /**< FIFO Full. */ +} ADI_I2C_MSTAT_MTXF; + + +/* ========================================================================== + *! \struct ADI_I2C_MSTAT_Struct + *! \brief Master Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MSTAT_t__ +typedef struct _ADI_I2C_MSTAT_t { + union { + struct { + unsigned int MTXF : 2; /**< Master Transmit FIFO Status */ + unsigned int MTXREQ : 1; /**< Master Transmit Request/Clear Master Transmit Interrupt */ + unsigned int MRXREQ : 1; /**< Master Receive Request */ + unsigned int NACKADDR : 1; /**< ACK Not Received in Response to an Address */ + unsigned int ALOST : 1; /**< Arbitration Lost */ + unsigned int MBUSY : 1; /**< Master Busy */ + unsigned int NACKDATA : 1; /**< ACK Not Received in Response to Data Write */ + unsigned int TCOMP : 1; /**< Transaction Complete or Stop Detected */ + unsigned int MRXOVR : 1; /**< Master Receive FIFO Overflow */ + unsigned int LINEBUSY : 1; /**< Line is Busy */ + unsigned int MSTOP : 1; /**< STOP Driven by This I2C Master */ + unsigned int MTXUNDR : 1; /**< Master Transmit Underflow */ + unsigned int SDAFILT : 1; /**< State of SDA Line */ + unsigned int SCLFILT : 1; /**< State of SCL Line */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_I2C_MSTAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MSTAT_t__ */ + +/*@}*/ + +/** @defgroup MRX Master Receive Data (MRX) Register + * Master Receive Data (MRX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_MRX_Struct + *! \brief Master Receive Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MRX_t__ +typedef struct _ADI_I2C_MRX_t { + union { + struct { + unsigned int VALUE : 8; /**< Master Receive Register */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_MRX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MRX_t__ */ + +/*@}*/ + +/** @defgroup MTX Master Transmit Data (MTX) Register + * Master Transmit Data (MTX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_MTX_Struct + *! \brief Master Transmit Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MTX_t__ +typedef struct _ADI_I2C_MTX_t { + union { + struct { + unsigned int VALUE : 8; /**< Master Transmit Register */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_MTX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MTX_t__ */ + +/*@}*/ + +/** @defgroup MRXCNT Master Receive Data Count (MRXCNT) Register + * Master Receive Data Count (MRXCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_MRXCNT_Struct + *! \brief Master Receive Data Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MRXCNT_t__ +typedef struct _ADI_I2C_MRXCNT_t { + union { + struct { + unsigned int VALUE : 8; /**< Receive Count */ + unsigned int EXTEND : 1; /**< Extended Read */ + unsigned int reserved9 : 7; + }; + uint16_t VALUE16; + }; +} ADI_I2C_MRXCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MRXCNT_t__ */ + +/*@}*/ + +/** @defgroup MCRXCNT Master Current Receive Data Count (MCRXCNT) Register + * Master Current Receive Data Count (MCRXCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_MCRXCNT_Struct + *! \brief Master Current Receive Data Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MCRXCNT_t__ +typedef struct _ADI_I2C_MCRXCNT_t { + union { + struct { + unsigned int VALUE : 8; /**< Current Receive Count */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_MCRXCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MCRXCNT_t__ */ + +/*@}*/ + +/** @defgroup ADDR1 Master Address Byte 1 (ADDR1) Register + * Master Address Byte 1 (ADDR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ADDR1_Struct + *! \brief Master Address Byte 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ADDR1_t__ +typedef struct _ADI_I2C_ADDR1_t { + union { + struct { + unsigned int VALUE : 8; /**< Address Byte 1 */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ADDR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ADDR1_t__ */ + +/*@}*/ + +/** @defgroup ADDR2 Master Address Byte 2 (ADDR2) Register + * Master Address Byte 2 (ADDR2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ADDR2_Struct + *! \brief Master Address Byte 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ADDR2_t__ +typedef struct _ADI_I2C_ADDR2_t { + union { + struct { + unsigned int VALUE : 8; /**< Address Byte 2 */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ADDR2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ADDR2_t__ */ + +/*@}*/ + +/** @defgroup BYT Start Byte (BYT) Register + * Start Byte (BYT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_BYT_Struct + *! \brief Start Byte Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_BYT_t__ +typedef struct _ADI_I2C_BYT_t { + union { + struct { + unsigned int SBYTE : 8; /**< Start Byte */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_BYT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_BYT_t__ */ + +/*@}*/ + +/** @defgroup DIV Serial Clock Period Divisor (DIV) Register + * Serial Clock Period Divisor (DIV) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_DIV_Struct + *! \brief Serial Clock Period Divisor Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_DIV_t__ +typedef struct _ADI_I2C_DIV_t { + union { + struct { + unsigned int LOW : 8; /**< Serial Clock Low Time */ + unsigned int HIGH : 8; /**< Serial Clock High Time */ + }; + uint16_t VALUE16; + }; +} ADI_I2C_DIV_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_DIV_t__ */ + +/*@}*/ + +/** @defgroup SCTL Slave Control (SCTL) Register + * Slave Control (SCTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_SCTL_Struct + *! \brief Slave Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SCTL_t__ +typedef struct _ADI_I2C_SCTL_t { + union { + struct { + unsigned int SLVEN : 1; /**< Slave Enable */ + unsigned int ADR10EN : 1; /**< Enabled 10-bit Addressing */ + unsigned int GCEN : 1; /**< General Call Enable */ + unsigned int HGCEN : 1; /**< Hardware General Call Enable */ + unsigned int GCSBCLR : 1; /**< General Call Status Bit Clear */ + unsigned int EARLYTXR : 1; /**< Early Transmit Request Mode */ + unsigned int reserved6 : 1; + unsigned int NACK : 1; /**< NACK Next Communication */ + unsigned int IENSTOP : 1; /**< Stop Condition Detected Interrupt Enable */ + unsigned int IENSRX : 1; /**< Slave Receive Request Interrupt Enable */ + unsigned int IENSTX : 1; /**< Slave Transmit Request Interrupt Enable */ + unsigned int STXDEC : 1; /**< Decrement Slave Tx FIFO Status When a Byte is Txed */ + unsigned int IENREPST : 1; /**< Repeated Start Interrupt Enable */ + unsigned int SRXDMA : 1; /**< Enable Slave Rx DMA Request */ + unsigned int STXDMA : 1; /**< Enable Slave Tx DMA Request */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_I2C_SCTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SCTL_t__ */ + +/*@}*/ + +/** @defgroup SSTAT Slave I2C Status/Error/IRQ (SSTAT) Register + * Slave I2C Status/Error/IRQ (SSTAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_SSTAT_Struct + *! \brief Slave I2C Status/Error/IRQ Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SSTAT_t__ +typedef struct _ADI_I2C_SSTAT_t { + union { + struct { + unsigned int STXFSEREQ : 1; /**< Slave Tx FIFO Status or Early Request */ + unsigned int STXUNDR : 1; /**< Slave Transmit FIFO Underflow */ + unsigned int STXREQ : 1; /**< Slave Transmit Request/Slave Transmit Interrupt */ + unsigned int SRXREQ : 1; /**< Slave Receive Request */ + unsigned int SRXOVR : 1; /**< Slave Receive FIFO Overflow */ + unsigned int NOACK : 1; /**< ACK Not Generated by the Slave */ + unsigned int SBUSY : 1; /**< Slave Busy */ + unsigned int GCINT : 1; /**< General Call Interrupt */ + unsigned int GCID : 2; /**< General ID */ + unsigned int STOP : 1; /**< Stop After Start and Matching Address */ + unsigned int IDMAT : 2; /**< Device ID Matched */ + unsigned int REPSTART : 1; /**< Repeated Start and Matching Address */ + unsigned int START : 1; /**< Start and Matching Address */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_I2C_SSTAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SSTAT_t__ */ + +/*@}*/ + +/** @defgroup SRX Slave Receive (SRX) Register + * Slave Receive (SRX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_SRX_Struct + *! \brief Slave Receive Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SRX_t__ +typedef struct _ADI_I2C_SRX_t { + union { + struct { + unsigned int VALUE : 8; /**< Slave Receive Register */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_SRX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SRX_t__ */ + +/*@}*/ + +/** @defgroup STX Slave Transmit (STX) Register + * Slave Transmit (STX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_STX_Struct + *! \brief Slave Transmit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_STX_t__ +typedef struct _ADI_I2C_STX_t { + union { + struct { + unsigned int VALUE : 8; /**< Slave Transmit Register */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_STX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_STX_t__ */ + +/*@}*/ + +/** @defgroup ALT Hardware General Call ID (ALT) Register + * Hardware General Call ID (ALT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ALT_Struct + *! \brief Hardware General Call ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ALT_t__ +typedef struct _ADI_I2C_ALT_t { + union { + struct { + unsigned int ID : 8; /**< Slave Alt */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ALT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ALT_t__ */ + +/*@}*/ + +/** @defgroup ID0 First Slave Address Device ID (ID0) Register + * First Slave Address Device ID (ID0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ID0_Struct + *! \brief First Slave Address Device ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID0_t__ +typedef struct _ADI_I2C_ID0_t { + union { + struct { + unsigned int VALUE : 8; /**< Slave Device ID 0 */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ID0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID0_t__ */ + +/*@}*/ + +/** @defgroup ID1 Second Slave Address Device ID (ID1) Register + * Second Slave Address Device ID (ID1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ID1_Struct + *! \brief Second Slave Address Device ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID1_t__ +typedef struct _ADI_I2C_ID1_t { + union { + struct { + unsigned int VALUE : 8; /**< Slave Device ID 1 */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ID1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID1_t__ */ + +/*@}*/ + +/** @defgroup ID2 Third Slave Address Device ID (ID2) Register + * Third Slave Address Device ID (ID2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ID2_Struct + *! \brief Third Slave Address Device ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID2_t__ +typedef struct _ADI_I2C_ID2_t { + union { + struct { + unsigned int VALUE : 8; /**< Slave Device ID 2 */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ID2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID2_t__ */ + +/*@}*/ + +/** @defgroup ID3 Fourth Slave Address Device ID (ID3) Register + * Fourth Slave Address Device ID (ID3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ID3_Struct + *! \brief Fourth Slave Address Device ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID3_t__ +typedef struct _ADI_I2C_ID3_t { + union { + struct { + unsigned int VALUE : 8; /**< Slave Device ID 3 */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ID3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID3_t__ */ + +/*@}*/ + +/** @defgroup STAT Master and Slave FIFO Status (STAT) Register + * Master and Slave FIFO Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_STAT_Struct + *! \brief Master and Slave FIFO Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_STAT_t__ +typedef struct _ADI_I2C_STAT_t { + union { + struct { + unsigned int STXF : 2; /**< Slave Transmit FIFO Status */ + unsigned int SRXF : 2; /**< Slave Receive FIFO Status */ + unsigned int MTXF : 2; /**< Master Transmit FIFO Status */ + unsigned int MRXF : 2; /**< Master Receive FIFO Status */ + unsigned int SFLUSH : 1; /**< Flush the Slave Transmit FIFO */ + unsigned int MFLUSH : 1; /**< Flush the Master Transmit FIFO */ + unsigned int reserved10 : 6; + }; + uint16_t VALUE16; + }; +} ADI_I2C_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_STAT_t__ */ + +/*@}*/ + +/** @defgroup SHCTL Shared Control (SHCTL) Register + * Shared Control (SHCTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_SHCTL_Struct + *! \brief Shared Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SHCTL_t__ +typedef struct _ADI_I2C_SHCTL_t { + union { + struct { + unsigned int RST : 1; /**< Reset START STOP Detect Circuit */ + unsigned int reserved1 : 15; + }; + uint16_t VALUE16; + }; +} ADI_I2C_SHCTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SHCTL_t__ */ + +/*@}*/ + +/** @defgroup TCTL Timing Control Register (TCTL) Register + * Timing Control Register (TCTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_TCTL_Struct + *! \brief Timing Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_TCTL_t__ +typedef struct _ADI_I2C_TCTL_t { + union { + struct { + unsigned int THDATIN : 5; /**< Data in Hold Start */ + unsigned int reserved5 : 3; + unsigned int FILTEROFF : 1; /**< Input Filter Control */ + unsigned int reserved9 : 7; + }; + uint16_t VALUE16; + }; +} ADI_I2C_TCTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_TCTL_t__ */ + +/*@}*/ + +/** @defgroup ASTRETCH_SCL Automatic Stretch SCL (ASTRETCH_SCL) Register + * Automatic Stretch SCL (ASTRETCH_SCL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ASTRETCH_SCL_Struct + *! \brief Automatic Stretch SCL Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ASTRETCH_SCL_t__ +typedef struct _ADI_I2C_ASTRETCH_SCL_t { + union { + struct { + unsigned int MST : 4; /**< Master Automatic Stretch Mode */ + unsigned int SLV : 4; /**< Slave Automatic Stretch Mode */ + unsigned int MSTTMO : 1; /**< Master Automatic Stretch Timeout */ + unsigned int SLVTMO : 1; /**< Slave Automatic Stretch Timeout */ + unsigned int reserved10 : 6; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ASTRETCH_SCL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ASTRETCH_SCL_t__ */ + +/*@}*/ + +/** @defgroup STAT Status (STAT) Register + * Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_STAT_Struct + *! \brief Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_STAT_t__ +typedef struct _ADI_SPI_STAT_t { + union { + struct { + unsigned int IRQ : 1; /**< SPI Interrupt Status */ + unsigned int XFRDONE : 1; /**< SPI Transfer Completion */ + unsigned int TXEMPTY : 1; /**< SPI Tx FIFO Empty Interrupt */ + unsigned int TXDONE : 1; /**< SPI Tx Done in Read Command Mode */ + unsigned int TXUNDR : 1; /**< SPI Tx FIFO Underflow */ + unsigned int TXIRQ : 1; /**< SPI Tx IRQ */ + unsigned int RXIRQ : 1; /**< SPI Rx IRQ */ + unsigned int RXOVR : 1; /**< SPI Rx FIFO Overflow */ + unsigned int reserved8 : 3; + unsigned int CS : 1; /**< CS Status */ + unsigned int CSERR : 1; /**< Detected a CS Error Condition in Slave Mode */ + unsigned int CSRISE : 1; /**< Detected a Rising Edge on CS, in Slave CON Mode */ + unsigned int CSFALL : 1; /**< Detected a Falling Edge on CS, in Slave CON Mode */ + unsigned int RDY : 1; /**< Detected an Edge on Ready Indicator for Flow Control */ + }; + uint16_t VALUE16; + }; +} ADI_SPI_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_STAT_t__ */ + +/*@}*/ + +/** @defgroup RX Receive (RX) Register + * Receive (RX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_RX_Struct + *! \brief Receive Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_RX_t__ +typedef struct _ADI_SPI_RX_t { + union { + struct { + unsigned int BYTE1 : 8; /**< 8-bit Receive Buffer */ + unsigned int BYTE2 : 8; /**< 8-bit Receive Buffer, Used Only in DMA Modes */ + }; + uint16_t VALUE16; + }; +} ADI_SPI_RX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_RX_t__ */ + +/*@}*/ + +/** @defgroup TX Transmit (TX) Register + * Transmit (TX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_TX_Struct + *! \brief Transmit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_TX_t__ +typedef struct _ADI_SPI_TX_t { + union { + struct { + unsigned int BYTE1 : 8; /**< 8-bit Transmit Buffer */ + unsigned int BYTE2 : 8; /**< 8-bit Transmit Buffer, Used Only in DMA Modes */ + }; + uint16_t VALUE16; + }; +} ADI_SPI_TX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_TX_t__ */ + +/*@}*/ + +/** @defgroup DIV SPI Baud Rate Selection (DIV) Register + * SPI Baud Rate Selection (DIV) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_DIV_Struct + *! \brief SPI Baud Rate Selection Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_DIV_t__ +typedef struct _ADI_SPI_DIV_t { + union { + struct { + unsigned int VALUE : 6; /**< SPI Clock Divider */ + unsigned int reserved6 : 10; + }; + uint16_t VALUE16; + }; +} ADI_SPI_DIV_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_DIV_t__ */ + +/*@}*/ + +/** @defgroup CTL SPI Configuration (CTL) Register + * SPI Configuration (CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_CTL_Struct + *! \brief SPI Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CTL_t__ +typedef struct _ADI_SPI_CTL_t { + union { + struct { + unsigned int SPIEN : 1; /**< SPI Enable */ + unsigned int MASEN : 1; /**< Master Mode Enable */ + unsigned int CPHA : 1; /**< Serial Clock Phase Mode */ + unsigned int CPOL : 1; /**< Serial Clock Polarity */ + unsigned int WOM : 1; /**< SPI Wired-OR Mode */ + unsigned int LSB : 1; /**< LSB First Transfer Enable */ + unsigned int TIM : 1; /**< SPI Transfer and Interrupt Mode */ + unsigned int ZEN : 1; /**< Transmit Zeros Enable */ + unsigned int RXOF : 1; /**< Rx Overflow Overwrite Enable */ + unsigned int OEN : 1; /**< Slave MISO Output Enable */ + unsigned int LOOPBACK : 1; /**< Loopback Enable */ + unsigned int CON : 1; /**< Continuous Transfer Enable */ + unsigned int RFLUSH : 1; /**< SPI Rx FIFO Flush Enable */ + unsigned int TFLUSH : 1; /**< SPI Tx FIFO Flush Enable */ + unsigned int CSRST : 1; /**< Reset Mode for CS Error Bit */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_SPI_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CTL_t__ */ + +/*@}*/ + +/** @defgroup IEN SPI Interrupts Enable (IEN) Register + * SPI Interrupts Enable (IEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_IEN_Struct + *! \brief SPI Interrupts Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_IEN_t__ +typedef struct _ADI_SPI_IEN_t { + union { + struct { + unsigned int IRQMODE : 3; /**< SPI IRQ Mode Bits */ + unsigned int reserved3 : 5; + unsigned int CS : 1; /**< Enable Interrupt on Every CS Edge in Slave CON Mode */ + unsigned int TXUNDR : 1; /**< Tx Underflow Interrupt Enable */ + unsigned int RXOVR : 1; /**< Rx Overflow Interrupt Enable */ + unsigned int RDY : 1; /**< Ready Signal Edge Interrupt Enable */ + unsigned int TXDONE : 1; /**< SPI Transmit Done Interrupt Enable */ + unsigned int XFRDONE : 1; /**< SPI Transfer Completion Interrupt Enable */ + unsigned int TXEMPTY : 1; /**< Tx FIFO Empty Interrupt Enable */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_SPI_IEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_IEN_t__ */ + +/*@}*/ + +/** @defgroup CNT Transfer Byte Count (CNT) Register + * Transfer Byte Count (CNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_CNT_Struct + *! \brief Transfer Byte Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CNT_t__ +typedef struct _ADI_SPI_CNT_t { + union { + struct { + unsigned int VALUE : 14; /**< Transfer Byte Count */ + unsigned int reserved14 : 1; + unsigned int FRAMECONT : 1; /**< Continue Frame */ + }; + uint16_t VALUE16; + }; +} ADI_SPI_CNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CNT_t__ */ + +/*@}*/ + +/** @defgroup DMA SPI DMA Enable (DMA) Register + * SPI DMA Enable (DMA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_DMA_Struct + *! \brief SPI DMA Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_DMA_t__ +typedef struct _ADI_SPI_DMA_t { + union { + struct { + unsigned int EN : 1; /**< Enable DMA for Data Transfer */ + unsigned int TXEN : 1; /**< Enable Transmit DMA Request */ + unsigned int RXEN : 1; /**< Enable Receive DMA Request */ + unsigned int reserved3 : 13; + }; + uint16_t VALUE16; + }; +} ADI_SPI_DMA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_DMA_t__ */ + +/*@}*/ + +/** @defgroup FIFO_STAT FIFO Status (FIFO_STAT) Register + * FIFO Status (FIFO_STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_FIFO_STAT_Struct + *! \brief FIFO Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_FIFO_STAT_t__ +typedef struct _ADI_SPI_FIFO_STAT_t { + union { + struct { + unsigned int TX : 4; /**< SPI Tx FIFO Status */ + unsigned int reserved4 : 4; + unsigned int RX : 4; /**< SPI Rx FIFO Dtatus */ + unsigned int reserved12 : 4; + }; + uint16_t VALUE16; + }; +} ADI_SPI_FIFO_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_FIFO_STAT_t__ */ + +/*@}*/ + +/** @defgroup RD_CTL Read Control (RD_CTL) Register + * Read Control (RD_CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_RD_CTL_Struct + *! \brief Read Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_RD_CTL_t__ +typedef struct _ADI_SPI_RD_CTL_t { + union { + struct { + unsigned int CMDEN : 1; /**< Read Command Enable */ + unsigned int OVERLAP : 1; /**< Tx/Rx Overlap Mode */ + unsigned int TXBYTES : 4; /**< Transmit Byte Count - 1 (Read Command) */ + unsigned int reserved6 : 2; + unsigned int THREEPIN : 1; /**< Three Pin SPI Mode */ + unsigned int reserved9 : 7; + }; + uint16_t VALUE16; + }; +} ADI_SPI_RD_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_RD_CTL_t__ */ + +/*@}*/ + +/** @defgroup FLOW_CTL Flow Control (FLOW_CTL) Register + * Flow Control (FLOW_CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_FLOW_CTL_Struct + *! \brief Flow Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_FLOW_CTL_t__ +typedef struct _ADI_SPI_FLOW_CTL_t { + union { + struct { + unsigned int MODE : 2; /**< Flow Control Mode */ + unsigned int reserved2 : 2; + unsigned int RDYPOL : 1; /**< Polarity of RDY/MISO Line */ + unsigned int reserved5 : 1; + unsigned int RDBURSTSZ : 10; /**< Read Data Burst Size - 1 */ + }; + uint16_t VALUE16; + }; +} ADI_SPI_FLOW_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_FLOW_CTL_t__ */ + +/*@}*/ + +/** @defgroup WAIT_TMR Wait Timer for Flow Control (WAIT_TMR) Register + * Wait Timer for Flow Control (WAIT_TMR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_WAIT_TMR_Struct + *! \brief Wait Timer for Flow Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_WAIT_TMR_t__ +typedef struct _ADI_SPI_WAIT_TMR_t { + union { + struct { + unsigned int VALUE : 16; /**< Wait Timer */ + }; + uint16_t VALUE16; + }; +} ADI_SPI_WAIT_TMR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_WAIT_TMR_t__ */ + +/*@}*/ + +/** @defgroup CS_CTL Chip Select Control for Multi-slave Connections (CS_CTL) Register + * Chip Select Control for Multi-slave Connections (CS_CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_CS_CTL_Struct + *! \brief Chip Select Control for Multi-slave Connections Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CS_CTL_t__ +typedef struct _ADI_SPI_CS_CTL_t { + union { + struct { + unsigned int SEL : 4; /**< Chip Select Control */ + unsigned int reserved4 : 12; + }; + uint16_t VALUE16; + }; +} ADI_SPI_CS_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CS_CTL_t__ */ + +/*@}*/ + +/** @defgroup CS_OVERRIDE Chip Select Override (CS_OVERRIDE) Register + * Chip Select Override (CS_OVERRIDE) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_CS_OVERRIDE_Struct + *! \brief Chip Select Override Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CS_OVERRIDE_t__ +typedef struct _ADI_SPI_CS_OVERRIDE_t { + union { + struct { + unsigned int CTL : 2; /**< CS Override Control */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_SPI_CS_OVERRIDE_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CS_OVERRIDE_t__ */ + +/*@}*/ + +/** @defgroup RX Receive Buffer Register (RX) Register + * Receive Buffer Register (RX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_RX_Struct + *! \brief Receive Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_RX_t__ +typedef struct _ADI_UART_RX_t { + union { + struct { + unsigned int RBR : 8; /**< Receive Buffer Register */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_RX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_RX_t__ */ + +/*@}*/ + +/** @defgroup TX Transmit Holding Register (TX) Register + * Transmit Holding Register (TX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_TX_Struct + *! \brief Transmit Holding Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_TX_t__ +typedef struct _ADI_UART_TX_t { + union { + struct { + unsigned int THR : 8; /**< Transmit Holding Register */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_TX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_TX_t__ */ + +/*@}*/ + +/** @defgroup IEN Interrupt Enable (IEN) Register + * Interrupt Enable (IEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_IEN_Struct + *! \brief Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_IEN_t__ +typedef struct _ADI_UART_IEN_t { + union { + struct { + unsigned int ERBFI : 1; /**< Receive Buffer Full Interrupt */ + unsigned int ETBEI : 1; /**< Transmit Buffer Empty Interrupt */ + unsigned int ELSI : 1; /**< Rx Status Interrupt */ + unsigned int EDSSI : 1; /**< Modem Status Interrupt */ + unsigned int EDMAT : 1; /**< DMA Requests in Transmit Mode */ + unsigned int EDMAR : 1; /**< DMA Requests in Receive Mode */ + unsigned int reserved6 : 10; + }; + uint16_t VALUE16; + }; +} ADI_UART_IEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_IEN_t__ */ + +/*@}*/ + +/** @defgroup IIR Interrupt ID (IIR) Register + * Interrupt ID (IIR) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_UART_IIR_STAT + *! \brief Interrupt Status (STAT) Enumerations + * ========================================================================= */ +typedef enum +{ + UART_IIR_STAT_EDSSI = 0, /**< Modem status interrupt (Read MSR register to clear) */ + UART_IIR_STAT_ETBEI = 1, /**< Transmit buffer empty interrupt (Write to Tx register or read IIR register to clear) */ + UART_IIR_STAT_ERBFI = 2, /**< Receive buffer full interrupt (Read Rx register to clear) */ + UART_IIR_STAT_RLSI = 3, /**< Receive line status interrupt (Read LSR register to clear) */ + UART_IIR_STAT_RFTOI = 6 /**< Receive FIFO time-out interrupt (Read Rx register to clear) */ +} ADI_UART_IIR_STAT; + + +/* ========================================================================== + *! \struct ADI_UART_IIR_Struct + *! \brief Interrupt ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_IIR_t__ +typedef struct _ADI_UART_IIR_t { + union { + struct { + unsigned int NIRQ : 1; /**< Interrupt Flag */ + unsigned int STAT : 3; /**< Interrupt Status */ + unsigned int reserved4 : 2; + unsigned int FEND : 2; /**< FIFO Enabled */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_IIR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_IIR_t__ */ + +/*@}*/ + +/** @defgroup LCR Line Control (LCR) Register + * Line Control (LCR) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_UART_LCR_SP + *! \brief Stick Parity (SP) Enumerations + * ========================================================================= */ +typedef enum +{ + UART_LCR_PAR_NOTFORCED = 0, /**< Parity will not be forced based on Parity Select and Parity Enable bits. */ + UART_LCR_PAR_FORCED = 1 /**< Parity forced based on Parity Select and Parity Enable bits. */ +} ADI_UART_LCR_SP; + + +/* ========================================================================== + *! \struct ADI_UART_LCR_Struct + *! \brief Line Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_LCR_t__ +typedef struct _ADI_UART_LCR_t { + union { + struct { + unsigned int WLS : 2; /**< Word Length Select */ + unsigned int STOP : 1; /**< Stop Bit */ + unsigned int PEN : 1; /**< Parity Enable */ + unsigned int EPS : 1; /**< Parity Select */ + unsigned int SP : 1; /**< Stick Parity */ + unsigned int BRK : 1; /**< Set Break */ + unsigned int reserved7 : 9; + }; + uint16_t VALUE16; + }; +} ADI_UART_LCR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_LCR_t__ */ + +/*@}*/ + +/** @defgroup MCR Modem Control (MCR) Register + * Modem Control (MCR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_MCR_Struct + *! \brief Modem Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_MCR_t__ +typedef struct _ADI_UART_MCR_t { + union { + struct { + unsigned int DTR : 1; /**< Data Terminal Ready */ + unsigned int RTS : 1; /**< Request to Send */ + unsigned int OUT1 : 1; /**< Output 1 */ + unsigned int OUT2 : 1; /**< Output 2 */ + unsigned int LOOPBACK : 1; /**< Loopback Mode */ + unsigned int reserved5 : 11; + }; + uint16_t VALUE16; + }; +} ADI_UART_MCR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_MCR_t__ */ + +/*@}*/ + +/** @defgroup LSR Line Status (LSR) Register + * Line Status (LSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_LSR_Struct + *! \brief Line Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_LSR_t__ +typedef struct _ADI_UART_LSR_t { + union { + struct { + unsigned int DR : 1; /**< Data Ready */ + unsigned int OE : 1; /**< Overrun Error */ + unsigned int PE : 1; /**< Parity Error */ + unsigned int FE : 1; /**< Framing Error */ + unsigned int BI : 1; /**< Break Indicator */ + unsigned int THRE : 1; /**< Transmit Register Empty */ + unsigned int TEMT : 1; /**< Transmit and Shift Register Empty Status */ + unsigned int FIFOERR : 1; /**< Rx FIFO Parity Error/Frame Error/Break Indication */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_LSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_LSR_t__ */ + +/*@}*/ + +/** @defgroup MSR Modem Status (MSR) Register + * Modem Status (MSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_MSR_Struct + *! \brief Modem Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_MSR_t__ +typedef struct _ADI_UART_MSR_t { + union { + struct { + unsigned int DCTS : 1; /**< Delta CTS */ + unsigned int DDSR : 1; /**< Delta DSR */ + unsigned int TERI : 1; /**< Trailing Edge RI */ + unsigned int DDCD : 1; /**< Delta DCD */ + unsigned int CTS : 1; /**< Clear to Send */ + unsigned int DSR : 1; /**< Data Set Ready */ + unsigned int RI : 1; /**< Ring Indicator */ + unsigned int DCD : 1; /**< Data Carrier Detect */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_MSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_MSR_t__ */ + +/*@}*/ + +/** @defgroup SCR Scratch Buffer (SCR) Register + * Scratch Buffer (SCR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_SCR_Struct + *! \brief Scratch Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_SCR_t__ +typedef struct _ADI_UART_SCR_t { + union { + struct { + unsigned int SCR : 8; /**< Scratch */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_SCR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_SCR_t__ */ + +/*@}*/ + +/** @defgroup FCR FIFO Control (FCR) Register + * FIFO Control (FCR) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_UART_FCR_FDMAMD + *! \brief FIFO DMA Mode (FDMAMD) Enumerations + * ========================================================================= */ +typedef enum +{ + UART_FCR_MODE0 = 0, /**< In DMA mode 0, RX DMA request will be asserted whenever there's data in RBR or RX FIFO and de-assert whenever RBR or RX FIFO is empty; TX DMA request will be asserted whenever THR or TX FIFO is empty and de-assert whenever data written to. */ + UART_FCR_MODE1 = 1 /**< in DMA mode 1, RX DMA request will be asserted whenever RX FIFO trig level or time out reached and de-assert thereafter when RX FIFO is empty; TX DMA request will be asserted whenever TX FIFO is empty and de-assert thereafter when TX FIFO is completely filled up full. */ +} ADI_UART_FCR_FDMAMD; + + +/* ========================================================================== + *! \struct ADI_UART_FCR_Struct + *! \brief FIFO Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_FCR_t__ +typedef struct _ADI_UART_FCR_t { + union { + struct { + unsigned int FIFOEN : 1; /**< FIFO Enable as to Work in 16550 Mode */ + unsigned int RFCLR : 1; /**< Clear Rx FIFO */ + unsigned int TFCLR : 1; /**< Clear Tx FIFO */ + unsigned int FDMAMD : 1; /**< FIFO DMA Mode */ + unsigned int reserved4 : 2; + unsigned int RFTRIG : 2; /**< Rx FIFO Trigger Level */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_FCR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_FCR_t__ */ + +/*@}*/ + +/** @defgroup FBR Fractional Baud Rate (FBR) Register + * Fractional Baud Rate (FBR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_FBR_Struct + *! \brief Fractional Baud Rate Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_FBR_t__ +typedef struct _ADI_UART_FBR_t { + union { + struct { + unsigned int DIVN : 11; /**< Fractional Baud Rate N Divide Bits 0 to 2047 */ + unsigned int DIVM : 2; /**< Fractional Baud Rate M Divide Bits 1 to 3 */ + unsigned int reserved13 : 2; + unsigned int FBEN : 1; /**< Fractional Baud Rate Generator Enable */ + }; + uint16_t VALUE16; + }; +} ADI_UART_FBR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_FBR_t__ */ + +/*@}*/ + +/** @defgroup DIV Baud Rate Divider (DIV) Register + * Baud Rate Divider (DIV) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_DIV_Struct + *! \brief Baud Rate Divider Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_DIV_t__ +typedef struct _ADI_UART_DIV_t { + union { + struct { + unsigned int DIV : 16; /**< Baud Rate Divider */ + }; + uint16_t VALUE16; + }; +} ADI_UART_DIV_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_DIV_t__ */ + +/*@}*/ + +/** @defgroup LCR2 Second Line Control (LCR2) Register + * Second Line Control (LCR2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_LCR2_Struct + *! \brief Second Line Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_LCR2_t__ +typedef struct _ADI_UART_LCR2_t { + union { + struct { + unsigned int OSR : 2; /**< Over Sample Rate */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_UART_LCR2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_LCR2_t__ */ + +/*@}*/ + +/** @defgroup CTL UART Control Register (CTL) Register + * UART Control Register (CTL) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_UART_CTL_RXINV + *! \brief Invert Receiver Line (RXINV) Enumerations + * ========================================================================= */ +typedef enum +{ + UART_CTL_NOTINV_RX = 0, /**< Don't invert receiver line (idling high). */ + UART_CTL_INV_RX = 1 /**< Invert receiver line (idling low). */ +} ADI_UART_CTL_RXINV; + + +/* ========================================================================== + *! \struct ADI_UART_CTL_Struct + *! \brief UART Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_CTL_t__ +typedef struct _ADI_UART_CTL_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int FORCECLK : 1; /**< Force UCLK on */ + unsigned int reserved2 : 2; + unsigned int RXINV : 1; /**< Invert Receiver Line */ + unsigned int reserved5 : 3; + unsigned int REV : 8; /**< UART Revision ID */ + }; + uint16_t VALUE16; + }; +} ADI_UART_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_CTL_t__ */ + +/*@}*/ + +/** @defgroup RFC RX FIFO Byte Count (RFC) Register + * RX FIFO Byte Count (RFC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_RFC_Struct + *! \brief RX FIFO Byte Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_RFC_t__ +typedef struct _ADI_UART_RFC_t { + union { + struct { + unsigned int RFC : 5; /**< Current Rx FIFO Data Bytes */ + unsigned int reserved5 : 11; + }; + uint16_t VALUE16; + }; +} ADI_UART_RFC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_RFC_t__ */ + +/*@}*/ + +/** @defgroup TFC TX FIFO Byte Count (TFC) Register + * TX FIFO Byte Count (TFC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_TFC_Struct + *! \brief TX FIFO Byte Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_TFC_t__ +typedef struct _ADI_UART_TFC_t { + union { + struct { + unsigned int TFC : 5; /**< Current Tx FIFO Data Bytes */ + unsigned int reserved5 : 11; + }; + uint16_t VALUE16; + }; +} ADI_UART_TFC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_TFC_t__ */ + +/*@}*/ + +/** @defgroup RSC RS485 Half-duplex Control (RSC) Register + * RS485 Half-duplex Control (RSC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_RSC_Struct + *! \brief RS485 Half-duplex Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_RSC_t__ +typedef struct _ADI_UART_RSC_t { + union { + struct { + unsigned int OENP : 1; /**< SOUT_EN Polarity */ + unsigned int OENSP : 1; /**< SOUT_EN De-assert Before Full Stop Bit(s) */ + unsigned int DISRX : 1; /**< Disable Rx When Transmitting */ + unsigned int DISTX : 1; /**< Hold off Tx When Receiving */ + unsigned int reserved4 : 12; + }; + uint16_t VALUE16; + }; +} ADI_UART_RSC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_RSC_t__ */ + +/*@}*/ + +/** @defgroup ACR Auto Baud Control (ACR) Register + * Auto Baud Control (ACR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_ACR_Struct + *! \brief Auto Baud Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_ACR_t__ +typedef struct _ADI_UART_ACR_t { + union { + struct { + unsigned int ABE : 1; /**< Auto Baud Enable */ + unsigned int DNIEN : 1; /**< Enable Done Interrupt */ + unsigned int TOIEN : 1; /**< Enable Time-out Interrupt */ + unsigned int reserved3 : 1; + unsigned int SEC : 3; /**< Starting Edge Count */ + unsigned int reserved7 : 1; + unsigned int EEC : 4; /**< Ending Edge Count */ + unsigned int reserved12 : 4; + }; + uint16_t VALUE16; + }; +} ADI_UART_ACR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_ACR_t__ */ + +/*@}*/ + +/** @defgroup ASRL Auto Baud Status (Low) (ASRL) Register + * Auto Baud Status (Low) (ASRL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_ASRL_Struct + *! \brief Auto Baud Status (Low) Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_ASRL_t__ +typedef struct _ADI_UART_ASRL_t { + union { + struct { + unsigned int DONE : 1; /**< Auto Baud Done Successfully */ + unsigned int BRKTO : 1; /**< Timed Out Due to Long Time Break Condition */ + unsigned int NSETO : 1; /**< Timed Out Due to No Valid Start Edge Found */ + unsigned int NEETO : 1; /**< Timed Out Due to No Valid Ending Edge Found */ + unsigned int CNT : 12; /**< CNT[11:0] Auto Baud Counter Value */ + }; + uint16_t VALUE16; + }; +} ADI_UART_ASRL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_ASRL_t__ */ + +/*@}*/ + +/** @defgroup ASRH Auto Baud Status (High) (ASRH) Register + * Auto Baud Status (High) (ASRH) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_ASRH_Struct + *! \brief Auto Baud Status (High) Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_ASRH_t__ +typedef struct _ADI_UART_ASRH_t { + union { + struct { + unsigned int CNT : 8; /**< CNT[19:12] Auto Baud Counter Value */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_ASRH_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_ASRH_t__ */ + +/*@}*/ + +/** @defgroup CFG Beeper Configuration (CFG) Register + * Beeper Configuration (CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BEEP_CFG_Struct + *! \brief Beeper Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_CFG_t__ +typedef struct _ADI_BEEP_CFG_t { + union { + struct { + unsigned int SEQREPEAT : 8; /**< Beeper Sequence Repeat Value */ + unsigned int EN : 1; /**< Beeper Enable */ + unsigned int reserved9 : 1; + unsigned int ASTARTIRQ : 1; /**< Tone A Start IRQ */ + unsigned int AENDIRQ : 1; /**< Tone A End IRQ */ + unsigned int BSTARTIRQ : 1; /**< Tone B Start IRQ */ + unsigned int BENDIRQ : 1; /**< Tone B End IRQ */ + unsigned int SEQNEARENDIRQ : 1; /**< Sequence 1 Cycle from End IRQ */ + unsigned int SEQATENDIRQ : 1; /**< Sequence End IRQ */ + }; + uint16_t VALUE16; + }; +} ADI_BEEP_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_CFG_t__ */ + +/*@}*/ + +/** @defgroup STAT Beeper Status (STAT) Register + * Beeper Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BEEP_STAT_Struct + *! \brief Beeper Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_STAT_t__ +typedef struct _ADI_BEEP_STAT_t { + union { + struct { + unsigned int SEQREMAIN : 8; /**< Remaining Tone-pair Iterations to Play in Sequence Mode */ + unsigned int BUSY : 1; /**< Beeper is Busy */ + unsigned int reserved9 : 1; + unsigned int ASTARTED : 1; /**< Tone A Has Started */ + unsigned int AENDED : 1; /**< Tone A Has Ended */ + unsigned int BSTARTED : 1; /**< Tone B Has Started */ + unsigned int BENDED : 1; /**< Tone B Has Ended */ + unsigned int SEQNEAREND : 1; /**< Sequencer Last Tone-pair Has Started */ + unsigned int SEQENDED : 1; /**< Sequencer Has Ended */ + }; + uint16_t VALUE16; + }; +} ADI_BEEP_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_STAT_t__ */ + +/*@}*/ + +/** @defgroup TONEA Tone A Data (TONEA) Register + * Tone A Data (TONEA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BEEP_TONEA_Struct + *! \brief Tone A Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_TONEA_t__ +typedef struct _ADI_BEEP_TONEA_t { + union { + struct { + unsigned int DUR : 8; /**< Tone Duration */ + unsigned int FREQ : 7; /**< Tone Frequency */ + unsigned int DIS : 1; /**< Output Disable */ + }; + uint16_t VALUE16; + }; +} ADI_BEEP_TONEA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_TONEA_t__ */ + +/*@}*/ + +/** @defgroup TONEB Tone B Data (TONEB) Register + * Tone B Data (TONEB) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BEEP_TONEB_Struct + *! \brief Tone B Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_TONEB_t__ +typedef struct _ADI_BEEP_TONEB_t { + union { + struct { + unsigned int DUR : 8; /**< Tone Duration */ + unsigned int FREQ : 7; /**< Tone Frequency */ + unsigned int DIS : 1; /**< Output Disable */ + }; + uint16_t VALUE16; + }; +} ADI_BEEP_TONEB_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_TONEB_t__ */ + +/*@}*/ + +/** @defgroup CFG ADC Configuration (CFG) Register + * ADC Configuration (CFG) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_ADC_CFG_VREFSEL + *! \brief To select Vref as 1.25 V or 2.5 V (VREFSEL) Enumerations + * ========================================================================= */ +typedef enum +{ + ADC_CFG_V_2P5 = 0, /**< Vref = 2.5 V */ + ADC_CFG_V_1P25 = 1 /**< Vref = 1.25 V */ +} ADI_ADC_CFG_VREFSEL; + + +/* ========================================================================= + *! \enum ADI_ADC_CFG_REFBUFEN + *! \brief To enable internal reference buffer (REFBUFEN) Enumerations + * ========================================================================= */ +typedef enum +{ + ADC_CFG_EXT_REF = 0, /**< External reference is used */ + ADC_CFG_BUF_REF = 1 /**< Reference buffer is enabled */ +} ADI_ADC_CFG_REFBUFEN; + + +/* ========================================================================== + *! \struct ADI_ADC_CFG_Struct + *! \brief ADC Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CFG_t__ +typedef struct _ADI_ADC_CFG_t { + union { + struct { + unsigned int PWRUP : 1; /**< Powering up ADC */ + unsigned int VREFSEL : 1; /**< To select Vref as 1.25 V or 2.5 V */ + unsigned int REFBUFEN : 1; /**< To enable internal reference buffer */ + unsigned int VREFVBAT : 1; /**< VRef VBAT */ + unsigned int EN : 1; /**< To enable ADC subsystem */ + unsigned int STARTCAL : 1; /**< To start a new offset calibration cycle */ + unsigned int RST : 1; /**< Resets internal buffers and registers when high */ + unsigned int SINKEN : 1; /**< To enable additional 50 uA sink current capability @1.25 V, 100 uA current capability @2.5 V */ + unsigned int TMPEN : 1; /**< To power up temperature sensor */ + unsigned int FAST_DISCH : 1; /**< For fast switchover of Vref from 2.5 V to 1.25 V */ + unsigned int VREFVBAT_DEL : 1; /**< Set to 1 after minimum delay of 700 us from VREFBAT field being set to 1 */ + unsigned int reserved11 : 5; + }; + uint16_t VALUE16; + }; +} ADI_ADC_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CFG_t__ */ + +/*@}*/ + +/** @defgroup PWRUP ADC Power-up Time (PWRUP) Register + * ADC Power-up Time (PWRUP) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_PWRUP_Struct + *! \brief ADC Power-up Time Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_PWRUP_t__ +typedef struct _ADI_ADC_PWRUP_t { + union { + struct { + unsigned int WAIT : 11; /**< Program this count to generate 20us wait time with respect to the PCLK frequency */ + unsigned int reserved11 : 5; + }; + uint16_t VALUE16; + }; +} ADI_ADC_PWRUP_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_PWRUP_t__ */ + +/*@}*/ + +/** @defgroup CAL_WORD Calibration Word (CAL_WORD) Register + * Calibration Word (CAL_WORD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CAL_WORD_Struct + *! \brief Calibration Word Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CAL_WORD_t__ +typedef struct _ADI_ADC_CAL_WORD_t { + union { + struct { + unsigned int VALUE : 7; /**< Offset calibration word */ + unsigned int reserved7 : 9; + }; + uint16_t VALUE16; + }; +} ADI_ADC_CAL_WORD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CAL_WORD_t__ */ + +/*@}*/ + +/** @defgroup CNV_CFG ADC Conversion Configuration (CNV_CFG) Register + * ADC Conversion Configuration (CNV_CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CNV_CFG_Struct + *! \brief ADC Conversion Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CNV_CFG_t__ +typedef struct _ADI_ADC_CNV_CFG_t { + union { + struct { + unsigned int SEL : 8; /**< To select channel(s) to convert */ + unsigned int BAT : 1; /**< To enable battery monitoring */ + unsigned int TMP : 1; /**< To select temperature measurement 1 */ + unsigned int TMP2 : 1; /**< To select temperature measurement 2 */ + unsigned int reserved11 : 1; + unsigned int AUTOMODE : 1; /**< To enable auto mode */ + unsigned int DMAEN : 1; /**< To enable DMA channel */ + unsigned int SINGLE : 1; /**< Set to start single conversion */ + unsigned int MULTI : 1; /**< Set to start multiple conversions */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CNV_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CNV_CFG_t__ */ + +/*@}*/ + +/** @defgroup CNV_TIME ADC Conversion Time (CNV_TIME) Register + * ADC Conversion Time (CNV_TIME) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CNV_TIME_Struct + *! \brief ADC Conversion Time Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CNV_TIME_t__ +typedef struct _ADI_ADC_CNV_TIME_t { + union { + struct { + unsigned int SAMPTIME : 8; /**< Number of clock cycles (ACLK) required for sampling */ + unsigned int DLY : 8; /**< Delay between two consecutive conversions in terms of number of ACLK cycles */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CNV_TIME_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CNV_TIME_t__ */ + +/*@}*/ + +/** @defgroup AVG_CFG Averaging Configuration (AVG_CFG) Register + * Averaging Configuration (AVG_CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_AVG_CFG_Struct + *! \brief Averaging Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_AVG_CFG_t__ +typedef struct _ADI_ADC_AVG_CFG_t { + union { + struct { + unsigned int FACTOR : 8; /**< Program averaging factor for averaging enabled channels (1-256) */ + unsigned int reserved8 : 6; + unsigned int OS : 1; /**< Enable oversampling */ + unsigned int EN : 1; /**< To enable averaging on Channels enabled in enable register */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_AVG_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_AVG_CFG_t__ */ + +/*@}*/ + +/** @defgroup IRQ_EN Interrupt Enable (IRQ_EN) Register + * Interrupt Enable (IRQ_EN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_IRQ_EN_Struct + *! \brief Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_IRQ_EN_t__ +typedef struct _ADI_ADC_IRQ_EN_t { + union { + struct { + unsigned int CNVDONE : 1; /**< Set it to enable interrupt after conversion is done */ + unsigned int reserved1 : 9; + unsigned int CALDONE : 1; /**< Set it to enable interrupt for calibration done */ + unsigned int OVF : 1; /**< Set to enable interrupt in case of overflow */ + unsigned int ALERT : 1; /**< Set to enable interrupt on crossing lower or higher limit */ + unsigned int RDY : 1; /**< Set to enable interrupt when ADC is ready to convert */ + unsigned int reserved14 : 2; + }; + uint16_t VALUE16; + }; +} ADI_ADC_IRQ_EN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_IRQ_EN_t__ */ + +/*@}*/ + +/** @defgroup STAT ADC Status (STAT) Register + * ADC Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_STAT_Struct + *! \brief ADC Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_STAT_t__ +typedef struct _ADI_ADC_STAT_t { + union { + struct { + unsigned int DONE0 : 1; /**< Indicates conversion done on Channel 0 */ + unsigned int DONE1 : 1; /**< Indicates conversion done on Channel 1 */ + unsigned int DONE2 : 1; /**< Indicates conversion done on Channel 2 */ + unsigned int DONE3 : 1; /**< Indicates conversion done on Channel 3 */ + unsigned int DONE4 : 1; /**< Indicates conversion done on Channel 4 */ + unsigned int DONE5 : 1; /**< Indicates conversion done on Channel 5 */ + unsigned int DONE6 : 1; /**< Indicates conversion done on Channel 6 */ + unsigned int DONE7 : 1; /**< Indicates conversion done on Channel 7 */ + unsigned int BATDONE : 1; /**< Indicates conversion done for battery monitoring */ + unsigned int TMPDONE : 1; /**< Indicates conversion is done for temperature sensing */ + unsigned int TMP2DONE : 1; /**< Indicates conversion is done for temperature sensing 2 */ + unsigned int reserved11 : 3; + unsigned int CALDONE : 1; /**< Indicates calibration is done */ + unsigned int RDY : 1; /**< Indicates ADC is ready to start converting, when using external reference buffer */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_STAT_t__ */ + +/*@}*/ + +/** @defgroup OVF Overflow of Output Registers (OVF) Register + * Overflow of Output Registers (OVF) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_OVF_Struct + *! \brief Overflow of Output Registers Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_OVF_t__ +typedef struct _ADI_ADC_OVF_t { + union { + struct { + unsigned int CH0 : 1; /**< Indicates overflow in channel 0 output register */ + unsigned int CH1 : 1; /**< Indicates overflow in channel 1 output register */ + unsigned int CH2 : 1; /**< Indicates overflow in channel 2 output register */ + unsigned int CH3 : 1; /**< Indicates overflow in channel 3 output register */ + unsigned int CH4 : 1; /**< Indicates overflow in channel 4 output register */ + unsigned int CH5 : 1; /**< Indicates overflow in channel 5 output register */ + unsigned int CH6 : 1; /**< Indicates overflow in channel 6 output register */ + unsigned int CH7 : 1; /**< Indicates overflow in channel 7 output register */ + unsigned int BAT : 1; /**< Indicates overflow in battery monitoring output register */ + unsigned int TMP : 1; /**< Indicates overflow in temperature output register */ + unsigned int TMP2 : 1; /**< Indicates overflow in temperature 2 output register */ + unsigned int reserved11 : 5; + }; + uint16_t VALUE16; + }; +} ADI_ADC_OVF_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_OVF_t__ */ + +/*@}*/ + +/** @defgroup ALERT Alert Indication (ALERT) Register + * Alert Indication (ALERT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_ALERT_Struct + *! \brief Alert Indication Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_ALERT_t__ +typedef struct _ADI_ADC_ALERT_t { + union { + struct { + unsigned int HI0 : 1; /**< Channel 0 High alert status */ + unsigned int LO0 : 1; /**< Channel 0 Low alert status */ + unsigned int HI1 : 1; /**< Channel 1 High alert status */ + unsigned int LO1 : 1; /**< Channel 1 Low alert status */ + unsigned int HI2 : 1; /**< Channel 2 High alert status */ + unsigned int LO2 : 1; /**< Channel 2 Low alert status */ + unsigned int HI3 : 1; /**< Channel 3 High alert status */ + unsigned int LO3 : 1; /**< Channel 3 Low alert status */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_ADC_ALERT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_ALERT_t__ */ + +/*@}*/ + +/** @defgroup CH0_OUT Conversion Result Channel 0 (CH0_OUT) Register + * Conversion Result Channel 0 (CH0_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH0_OUT_Struct + *! \brief Conversion Result Channel 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH0_OUT_t__ +typedef struct _ADI_ADC_CH0_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of channel 0 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH0_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH0_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH1_OUT Conversion Result Channel 1 (CH1_OUT) Register + * Conversion Result Channel 1 (CH1_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH1_OUT_Struct + *! \brief Conversion Result Channel 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH1_OUT_t__ +typedef struct _ADI_ADC_CH1_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of channel 1 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH1_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH1_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH2_OUT Conversion Result Channel 2 (CH2_OUT) Register + * Conversion Result Channel 2 (CH2_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH2_OUT_Struct + *! \brief Conversion Result Channel 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH2_OUT_t__ +typedef struct _ADI_ADC_CH2_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of channel 2 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH2_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH2_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH3_OUT Conversion Result Channel 3 (CH3_OUT) Register + * Conversion Result Channel 3 (CH3_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH3_OUT_Struct + *! \brief Conversion Result Channel 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH3_OUT_t__ +typedef struct _ADI_ADC_CH3_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of channel 3 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH3_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH3_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH4_OUT Conversion Result Channel 4 (CH4_OUT) Register + * Conversion Result Channel 4 (CH4_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH4_OUT_Struct + *! \brief Conversion Result Channel 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH4_OUT_t__ +typedef struct _ADI_ADC_CH4_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of channel 4 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH4_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH4_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH5_OUT Conversion Result Channel 5 (CH5_OUT) Register + * Conversion Result Channel 5 (CH5_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH5_OUT_Struct + *! \brief Conversion Result Channel 5 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH5_OUT_t__ +typedef struct _ADI_ADC_CH5_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of channel 5 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH5_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH5_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH6_OUT Conversion Result Channel 6 (CH6_OUT) Register + * Conversion Result Channel 6 (CH6_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH6_OUT_Struct + *! \brief Conversion Result Channel 6 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH6_OUT_t__ +typedef struct _ADI_ADC_CH6_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of channel 6 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH6_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH6_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH7_OUT Conversion Result Channel 7 (CH7_OUT) Register + * Conversion Result Channel 7 (CH7_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH7_OUT_Struct + *! \brief Conversion Result Channel 7 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH7_OUT_t__ +typedef struct _ADI_ADC_CH7_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of channel 7 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH7_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH7_OUT_t__ */ + +/*@}*/ + +/** @defgroup BAT_OUT Battery Monitoring Result (BAT_OUT) Register + * Battery Monitoring Result (BAT_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_BAT_OUT_Struct + *! \brief Battery Monitoring Result Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_BAT_OUT_t__ +typedef struct _ADI_ADC_BAT_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of battery monitoring is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_BAT_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_BAT_OUT_t__ */ + +/*@}*/ + +/** @defgroup TMP_OUT Temperature Result (TMP_OUT) Register + * Temperature Result (TMP_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_TMP_OUT_Struct + *! \brief Temperature Result Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_TMP_OUT_t__ +typedef struct _ADI_ADC_TMP_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of Temperature measurement 1 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_TMP_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_TMP_OUT_t__ */ + +/*@}*/ + +/** @defgroup TMP2_OUT Temperature Result 2 (TMP2_OUT) Register + * Temperature Result 2 (TMP2_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_TMP2_OUT_Struct + *! \brief Temperature Result 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_TMP2_OUT_t__ +typedef struct _ADI_ADC_TMP2_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of Temperature measurement 2 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_TMP2_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_TMP2_OUT_t__ */ + +/*@}*/ + +/** @defgroup DMA_OUT DMA Output Register (DMA_OUT) Register + * DMA Output Register (DMA_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_DMA_OUT_Struct + *! \brief DMA Output Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_DMA_OUT_t__ +typedef struct _ADI_ADC_DMA_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Register to store conversion result for DMA */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_DMA_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_DMA_OUT_t__ */ + +/*@}*/ + +/** @defgroup LIM0_LO Channel 0 Low Limit (LIM0_LO) Register + * Channel 0 Low Limit (LIM0_LO) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM0_LO_Struct + *! \brief Channel 0 Low Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_LO_t__ +typedef struct _ADI_ADC_LIM0_LO_t { + union { + struct { + unsigned int VALUE : 12; /**< Low limit value for channel 0 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< To enable low limit comparison on Channel 0 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM0_LO_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_LO_t__ */ + +/*@}*/ + +/** @defgroup LIM0_HI Channel 0 High Limit (LIM0_HI) Register + * Channel 0 High Limit (LIM0_HI) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM0_HI_Struct + *! \brief Channel 0 High Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_HI_t__ +typedef struct _ADI_ADC_LIM0_HI_t { + union { + struct { + unsigned int VALUE : 12; /**< High limit value for channel 0 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< To enable high limit comparison on Channel 0 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM0_HI_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_HI_t__ */ + +/*@}*/ + +/** @defgroup HYS0 Channel 0 Hysteresis (HYS0) Register + * Channel 0 Hysteresis (HYS0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_HYS0_Struct + *! \brief Channel 0 Hysteresis Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS0_t__ +typedef struct _ADI_ADC_HYS0_t { + union { + struct { + unsigned int VALUE : 9; /**< Hysteresis value for Channel 0 */ + unsigned int reserved9 : 3; + unsigned int MONCYC : 3; /**< Program number of conversion cycles to monitor channel 0 before raising alert */ + unsigned int EN : 1; /**< To enable hysteresis for comparison on Channel 0 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_HYS0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS0_t__ */ + +/*@}*/ + +/** @defgroup LIM1_LO Channel 1 Low Limit (LIM1_LO) Register + * Channel 1 Low Limit (LIM1_LO) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM1_LO_Struct + *! \brief Channel 1 Low Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_LO_t__ +typedef struct _ADI_ADC_LIM1_LO_t { + union { + struct { + unsigned int VALUE : 12; /**< Low limit value for channel 1 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< To enable low limit comparison on Channel 1 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM1_LO_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_LO_t__ */ + +/*@}*/ + +/** @defgroup LIM1_HI Channel 1 High Limit (LIM1_HI) Register + * Channel 1 High Limit (LIM1_HI) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM1_HI_Struct + *! \brief Channel 1 High Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_HI_t__ +typedef struct _ADI_ADC_LIM1_HI_t { + union { + struct { + unsigned int VALUE : 12; /**< High limit value for channel 1 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< To enable high limit comparison on Channel 1 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM1_HI_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_HI_t__ */ + +/*@}*/ + +/** @defgroup HYS1 Channel 1 Hysteresis (HYS1) Register + * Channel 1 Hysteresis (HYS1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_HYS1_Struct + *! \brief Channel 1 Hysteresis Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS1_t__ +typedef struct _ADI_ADC_HYS1_t { + union { + struct { + unsigned int VALUE : 9; /**< Hysteresis value for Channel 1 */ + unsigned int reserved9 : 3; + unsigned int MONCYC : 3; /**< Program number of conversion cycles to monitor channel 1 before raising alert */ + unsigned int EN : 1; /**< To enable hysteresis for comparison on Channel 1 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_HYS1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS1_t__ */ + +/*@}*/ + +/** @defgroup LIM2_LO Channel 2 Low Limit (LIM2_LO) Register + * Channel 2 Low Limit (LIM2_LO) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM2_LO_Struct + *! \brief Channel 2 Low Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_LO_t__ +typedef struct _ADI_ADC_LIM2_LO_t { + union { + struct { + unsigned int VALUE : 12; /**< Low limit value for channel 2 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< To enable low limit comparison on Channel 2 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM2_LO_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_LO_t__ */ + +/*@}*/ + +/** @defgroup LIM2_HI Channel 2 High Limit (LIM2_HI) Register + * Channel 2 High Limit (LIM2_HI) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM2_HI_Struct + *! \brief Channel 2 High Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_HI_t__ +typedef struct _ADI_ADC_LIM2_HI_t { + union { + struct { + unsigned int VALUE : 12; /**< High limit value for channel 2 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< To enable high limit comparison on Channel 2 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM2_HI_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_HI_t__ */ + +/*@}*/ + +/** @defgroup HYS2 Channel 2 Hysteresis (HYS2) Register + * Channel 2 Hysteresis (HYS2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_HYS2_Struct + *! \brief Channel 2 Hysteresis Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS2_t__ +typedef struct _ADI_ADC_HYS2_t { + union { + struct { + unsigned int VALUE : 9; /**< Hysteresis value for Channel 2 */ + unsigned int reserved9 : 3; + unsigned int MONCYC : 3; /**< Program number of conversion cycles to monitor channel 2 before raising alert */ + unsigned int EN : 1; /**< To enable hysteresis for comparison on Channel 2 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_HYS2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS2_t__ */ + +/*@}*/ + +/** @defgroup LIM3_LO Channel 3 Low Limit (LIM3_LO) Register + * Channel 3 Low Limit (LIM3_LO) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM3_LO_Struct + *! \brief Channel 3 Low Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_LO_t__ +typedef struct _ADI_ADC_LIM3_LO_t { + union { + struct { + unsigned int VALUE : 12; /**< Low limit value for channel 3 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< To enable low limit comparison on Channel 3 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM3_LO_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_LO_t__ */ + +/*@}*/ + +/** @defgroup LIM3_HI Channel 3 High Limit (LIM3_HI) Register + * Channel 3 High Limit (LIM3_HI) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM3_HI_Struct + *! \brief Channel 3 High Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_HI_t__ +typedef struct _ADI_ADC_LIM3_HI_t { + union { + struct { + unsigned int VALUE : 12; /**< High limit value for channel 3 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< To enable high limit comparison on Channel 3 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM3_HI_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_HI_t__ */ + +/*@}*/ + +/** @defgroup HYS3 Channel 3 Hysteresis (HYS3) Register + * Channel 3 Hysteresis (HYS3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_HYS3_Struct + *! \brief Channel 3 Hysteresis Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS3_t__ +typedef struct _ADI_ADC_HYS3_t { + union { + struct { + unsigned int VALUE : 9; /**< Hysteresis value for Channel 3 */ + unsigned int reserved9 : 3; + unsigned int MONCYC : 3; /**< Program number of conversion cycles to monitor channel 3 before raising alert */ + unsigned int EN : 1; /**< To enable hysteresis for comparison on Channel 3 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_HYS3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS3_t__ */ + +/*@}*/ + +/** @defgroup CFG1 Reference Buffer Low Power Mode (CFG1) Register + * Reference Buffer Low Power Mode (CFG1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CFG1_Struct + *! \brief Reference Buffer Low Power Mode Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CFG1_t__ +typedef struct _ADI_ADC_CFG1_t { + union { + struct { + unsigned int RBUFLP : 1; /**< Enable low power mode for reference buffer */ + unsigned int reserved1 : 15; + }; + uint16_t VALUE16; + }; +} ADI_ADC_CFG1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CFG1_t__ */ + +/*@}*/ + +/** @defgroup STAT DMA Status (STAT) Register + * DMA Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_STAT_Struct + *! \brief DMA Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_STAT_t__ +typedef struct _ADI_DMA_STAT_t { + union { + struct { + unsigned int MEN : 1; /**< Enable Status of the Controller */ + unsigned int reserved1 : 15; + unsigned int CHANM1 : 5; /**< Number of Available DMA Channels Minus 1 */ + unsigned int reserved21 : 11; + }; + uint32_t VALUE32; + }; +} ADI_DMA_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_STAT_t__ */ + +/*@}*/ + +/** @defgroup CFG DMA Configuration (CFG) Register + * DMA Configuration (CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_CFG_Struct + *! \brief DMA Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_CFG_t__ +typedef struct _ADI_DMA_CFG_t { + union { + struct { + unsigned int MEN : 1; /**< Controller Enable */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_DMA_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_CFG_t__ */ + +/*@}*/ + +/** @defgroup PDBPTR DMA Channel Primary Control Database Pointer (PDBPTR) Register + * DMA Channel Primary Control Database Pointer (PDBPTR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_PDBPTR_Struct + *! \brief DMA Channel Primary Control Database Pointer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_PDBPTR_t__ +typedef struct _ADI_DMA_PDBPTR_t { + union { + struct { + unsigned int ADDR : 32; /**< Pointer to the Base Address of the Primary Data Structure */ + }; + uint32_t VALUE32; + }; +} ADI_DMA_PDBPTR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_PDBPTR_t__ */ + +/*@}*/ + +/** @defgroup ADBPTR DMA Channel Alternate Control Database Pointer (ADBPTR) Register + * DMA Channel Alternate Control Database Pointer (ADBPTR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_ADBPTR_Struct + *! \brief DMA Channel Alternate Control Database Pointer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ADBPTR_t__ +typedef struct _ADI_DMA_ADBPTR_t { + union { + struct { + unsigned int ADDR : 32; /**< Base Address of the Alternate Data Structure */ + }; + uint32_t VALUE32; + }; +} ADI_DMA_ADBPTR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ADBPTR_t__ */ + +/*@}*/ + +/** @defgroup SWREQ DMA Channel Software Request (SWREQ) Register + * DMA Channel Software Request (SWREQ) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_SWREQ_Struct + *! \brief DMA Channel Software Request Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_SWREQ_t__ +typedef struct _ADI_DMA_SWREQ_t { + union { + struct { + unsigned int CHAN : 27; /**< Generate Software Request */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_SWREQ_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_SWREQ_t__ */ + +/*@}*/ + +/** @defgroup RMSK_SET DMA Channel Request Mask Set (RMSK_SET) Register + * DMA Channel Request Mask Set (RMSK_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_RMSK_SET_Struct + *! \brief DMA Channel Request Mask Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_SET_t__ +typedef struct _ADI_DMA_RMSK_SET_t { + union { + struct { + unsigned int CHAN : 27; /**< Mask Requests from DMA Channels */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_RMSK_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_SET_t__ */ + +/*@}*/ + +/** @defgroup RMSK_CLR DMA Channel Request Mask Clear (RMSK_CLR) Register + * DMA Channel Request Mask Clear (RMSK_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_RMSK_CLR_Struct + *! \brief DMA Channel Request Mask Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_CLR_t__ +typedef struct _ADI_DMA_RMSK_CLR_t { + union { + struct { + unsigned int CHAN : 27; /**< Clear Request Mask Set Bits */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_RMSK_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_CLR_t__ */ + +/*@}*/ + +/** @defgroup EN_SET DMA Channel Enable Set (EN_SET) Register + * DMA Channel Enable Set (EN_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_EN_SET_Struct + *! \brief DMA Channel Enable Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_EN_SET_t__ +typedef struct _ADI_DMA_EN_SET_t { + union { + struct { + unsigned int CHAN : 27; /**< Enable DMA Channels */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_EN_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_EN_SET_t__ */ + +/*@}*/ + +/** @defgroup EN_CLR DMA Channel Enable Clear (EN_CLR) Register + * DMA Channel Enable Clear (EN_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_EN_CLR_Struct + *! \brief DMA Channel Enable Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_EN_CLR_t__ +typedef struct _ADI_DMA_EN_CLR_t { + union { + struct { + unsigned int CHAN : 27; /**< Disable DMA Channels */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_EN_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_EN_CLR_t__ */ + +/*@}*/ + +/** @defgroup ALT_SET DMA Channel Primary Alternate Set (ALT_SET) Register + * DMA Channel Primary Alternate Set (ALT_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_ALT_SET_Struct + *! \brief DMA Channel Primary Alternate Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ALT_SET_t__ +typedef struct _ADI_DMA_ALT_SET_t { + union { + struct { + unsigned int CHAN : 27; /**< Control Structure Status / Select Alternate Structure */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_ALT_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ALT_SET_t__ */ + +/*@}*/ + +/** @defgroup ALT_CLR DMA Channel Primary Alternate Clear (ALT_CLR) Register + * DMA Channel Primary Alternate Clear (ALT_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_ALT_CLR_Struct + *! \brief DMA Channel Primary Alternate Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ALT_CLR_t__ +typedef struct _ADI_DMA_ALT_CLR_t { + union { + struct { + unsigned int CHAN : 27; /**< Select Primary Data Structure */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_ALT_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ALT_CLR_t__ */ + +/*@}*/ + +/** @defgroup PRI_SET DMA Channel Priority Set (PRI_SET) Register + * DMA Channel Priority Set (PRI_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_PRI_SET_Struct + *! \brief DMA Channel Priority Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_PRI_SET_t__ +typedef struct _ADI_DMA_PRI_SET_t { + union { + struct { + unsigned int CHAN : 27; /**< Configure Channel for High Priority */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_PRI_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_PRI_SET_t__ */ + +/*@}*/ + +/** @defgroup PRI_CLR DMA Channel Priority Clear (PRI_CLR) Register + * DMA Channel Priority Clear (PRI_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_PRI_CLR_Struct + *! \brief DMA Channel Priority Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_PRI_CLR_t__ +typedef struct _ADI_DMA_PRI_CLR_t { + union { + struct { + unsigned int CHPRICLR : 27; /**< Configure Channel for Default Priority Level */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_PRI_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_PRI_CLR_t__ */ + +/*@}*/ + +/** @defgroup ERRCHNL_CLR DMA per Channel Error Clear (ERRCHNL_CLR) Register + * DMA per Channel Error Clear (ERRCHNL_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_ERRCHNL_CLR_Struct + *! \brief DMA per Channel Error Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ERRCHNL_CLR_t__ +typedef struct _ADI_DMA_ERRCHNL_CLR_t { + union { + struct { + unsigned int CHAN : 27; /**< Per Channel Bus Error Status/Clear */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_ERRCHNL_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ERRCHNL_CLR_t__ */ + +/*@}*/ + +/** @defgroup ERR_CLR DMA Bus Error Clear (ERR_CLR) Register + * DMA Bus Error Clear (ERR_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_ERR_CLR_Struct + *! \brief DMA Bus Error Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ERR_CLR_t__ +typedef struct _ADI_DMA_ERR_CLR_t { + union { + struct { + unsigned int CHAN : 27; /**< Bus Error Status */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_ERR_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ERR_CLR_t__ */ + +/*@}*/ + +/** @defgroup INVALIDDESC_CLR DMA per Channel Invalid Descriptor Clear (INVALIDDESC_CLR) Register + * DMA per Channel Invalid Descriptor Clear (INVALIDDESC_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_INVALIDDESC_CLR_Struct + *! \brief DMA per Channel Invalid Descriptor Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_INVALIDDESC_CLR_t__ +typedef struct _ADI_DMA_INVALIDDESC_CLR_t { + union { + struct { + unsigned int CHAN : 27; /**< Per Channel Invalid Descriptor Status/Clear */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_INVALIDDESC_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_INVALIDDESC_CLR_t__ */ + +/*@}*/ + +/** @defgroup BS_SET DMA Channel Bytes Swap Enable Set (BS_SET) Register + * DMA Channel Bytes Swap Enable Set (BS_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_BS_SET_Struct + *! \brief DMA Channel Bytes Swap Enable Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_BS_SET_t__ +typedef struct _ADI_DMA_BS_SET_t { + union { + struct { + unsigned int CHAN : 27; /**< Byte Swap Status */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_BS_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_BS_SET_t__ */ + +/*@}*/ + +/** @defgroup BS_CLR DMA Channel Bytes Swap Enable Clear (BS_CLR) Register + * DMA Channel Bytes Swap Enable Clear (BS_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_BS_CLR_Struct + *! \brief DMA Channel Bytes Swap Enable Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_BS_CLR_t__ +typedef struct _ADI_DMA_BS_CLR_t { + union { + struct { + unsigned int CHAN : 27; /**< Disable Byte Swap */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_BS_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_BS_CLR_t__ */ + +/*@}*/ + +/** @defgroup SRCADDR_SET DMA Channel Source Address Decrement Enable Set (SRCADDR_SET) Register + * DMA Channel Source Address Decrement Enable Set (SRCADDR_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_SRCADDR_SET_Struct + *! \brief DMA Channel Source Address Decrement Enable Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_SET_t__ +typedef struct _ADI_DMA_SRCADDR_SET_t { + union { + struct { + unsigned int CHAN : 27; /**< Source Address Decrement Status */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_SRCADDR_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_SET_t__ */ + +/*@}*/ + +/** @defgroup SRCADDR_CLR DMA Channel Source Address Decrement Enable Clear (SRCADDR_CLR) Register + * DMA Channel Source Address Decrement Enable Clear (SRCADDR_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_SRCADDR_CLR_Struct + *! \brief DMA Channel Source Address Decrement Enable Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_CLR_t__ +typedef struct _ADI_DMA_SRCADDR_CLR_t { + union { + struct { + unsigned int CHAN : 27; /**< Disable Source Address Decrement */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_SRCADDR_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_CLR_t__ */ + +/*@}*/ + +/** @defgroup DSTADDR_SET DMA Channel Destination Address Decrement Enable Set (DSTADDR_SET) Register + * DMA Channel Destination Address Decrement Enable Set (DSTADDR_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_DSTADDR_SET_Struct + *! \brief DMA Channel Destination Address Decrement Enable Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_SET_t__ +typedef struct _ADI_DMA_DSTADDR_SET_t { + union { + struct { + unsigned int CHAN : 27; /**< Destination Address Decrement Status */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_DSTADDR_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_SET_t__ */ + +/*@}*/ + +/** @defgroup DSTADDR_CLR DMA Channel Destination Address Decrement Enable Clear (DSTADDR_CLR) Register + * DMA Channel Destination Address Decrement Enable Clear (DSTADDR_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_DSTADDR_CLR_Struct + *! \brief DMA Channel Destination Address Decrement Enable Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_CLR_t__ +typedef struct _ADI_DMA_DSTADDR_CLR_t { + union { + struct { + unsigned int CHAN : 27; /**< Disable Destination Address Decrement */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_DSTADDR_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_CLR_t__ */ + +/*@}*/ + +/** @defgroup REVID DMA Controller Revision ID (REVID) Register + * DMA Controller Revision ID (REVID) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_REVID_Struct + *! \brief DMA Controller Revision ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_REVID_t__ +typedef struct _ADI_DMA_REVID_t { + union { + struct { + unsigned int VALUE : 8; /**< DMA Controller Revision ID */ + unsigned int reserved8 : 24; + }; + uint32_t VALUE32; + }; +} ADI_DMA_REVID_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_REVID_t__ */ + +/*@}*/ + +/** @defgroup STAT Status (STAT) Register + * Status (STAT) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_FLCC_STAT_ACCESS_MODE + *! \brief Access Mode (ACCESS_MODE) Enumerations + * ========================================================================= */ +typedef enum +{ + FLCC_STAT_DIRECT = 0, /**< Flash controller is currently in Direct Access mode; user access to all registers is enabled */ + FLCC_STAT_INDIRECT = 1 /**< Flash Controller is currently in Indirect Access mode; user access to registers is limited to read-only access of the status register. Full register access will be restored when the Cryptographic module releases control of the flash controller (crypto completes the ongoing operation within the protected key storage region) */ +} ADI_FLCC_STAT_ACCESS_MODE; + + +/* ========================================================================== + *! \struct ADI_FLCC_STAT_Struct + *! \brief Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_STAT_t__ +typedef struct _ADI_FLCC_STAT_t { + union { + struct { + unsigned int CMDBUSY : 1; /**< Command busy */ + unsigned int WRCLOSE : 1; /**< WRITE registers are closed */ + unsigned int CMDCOMP : 1; /**< Command complete */ + unsigned int WRALCOMP : 1; /**< Write almost complete */ + unsigned int CMDFAIL : 2; /**< Provides information on command failures */ + unsigned int SLEEPING : 1; /**< Flash array is in low power (sleep) mode */ + unsigned int ECCERRCMD : 2; /**< ECC errors detected during user issued SIGN command */ + unsigned int ECCRDERR : 2; /**< ECC IRQ cause */ + unsigned int OVERLAP : 1; /**< Overlapping Command */ + unsigned int reserved12 : 1; + unsigned int SIGNERR : 1; /**< Signature check failure during initialization */ + unsigned int INIT : 1; /**< Flash controller initialization in progress */ + unsigned int ECCINFOSIGN : 2; /**< ECC status of flash initialization */ + unsigned int ECCERRCNT : 3; /**< ECC correction counter */ + unsigned int reserved20 : 5; + unsigned int ECCICODE : 2; /**< ICode AHB Bus Error ECC status */ + unsigned int ECCDCODE : 2; /**< DCode AHB Bus Error ECC status */ + unsigned int CACHESRAMPERR : 1; /**< SRAM parity errors in Cache Controller */ + unsigned int reserved30 : 1; + unsigned int ACCESS_MODE : 1; /**< Access Mode */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_STAT_t__ */ + +/*@}*/ + +/** @defgroup IEN Interrupt Enable (IEN) Register + * Interrupt Enable (IEN) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_FLCC_IEN_ECC_CORRECT + *! \brief Control whether to generate bus errors, interrupts, or neither in response to 1-bit ECC Correction events (ECC_CORRECT) Enumerations + * ========================================================================= */ +typedef enum +{ + FLCC_IEN_NONE_COR = 0, /**< Do not generate a response to ECC events */ + FLCC_IEN_BUS_ERR_COR = 1, /**< Generate Bus Errors in response to ECC events */ + FLCC_IEN_IRQ_COR = 2 /**< Generate IRQs in response to ECC events */ +} ADI_FLCC_IEN_ECC_CORRECT; + + +/* ========================================================================= + *! \enum ADI_FLCC_IEN_ECC_ERROR + *! \brief Control whether to generate bus errors, interrupts, or neither in response to 2-bit ECC Error events (ECC_ERROR) Enumerations + * ========================================================================= */ +typedef enum +{ + FLCC_IEN_NONE_ERR = 0, /**< Do not generate a response to ECC events */ + FLCC_IEN_BUS_ERR_ERR = 1, /**< Generate Bus Errors in response to ECC events */ + FLCC_IEN_IRQ_ERR = 2 /**< Generate IRQs in response to ECC events */ +} ADI_FLCC_IEN_ECC_ERROR; + + +/* ========================================================================== + *! \struct ADI_FLCC_IEN_Struct + *! \brief Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_IEN_t__ +typedef struct _ADI_FLCC_IEN_t { + union { + struct { + unsigned int CMDCMPLT : 1; /**< Command complete interrupt enable */ + unsigned int WRALCMPLT : 1; /**< Write almost complete interrupt enable */ + unsigned int CMDFAIL : 1; /**< Command fail interrupt enable */ + unsigned int reserved3 : 1; + unsigned int ECC_CORRECT : 2; /**< Control whether to generate bus errors, interrupts, or neither in response to 1-bit ECC Correction events */ + unsigned int ECC_ERROR : 2; /**< Control whether to generate bus errors, interrupts, or neither in response to 2-bit ECC Error events */ + unsigned int reserved8 : 24; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_IEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_IEN_t__ */ + +/*@}*/ + +/** @defgroup CMD Command (CMD) Register + * Command (CMD) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_FLCC_CMD_VALUE + *! \brief Commands (VALUE) Enumerations + * ========================================================================= */ +typedef enum +{ + FLCC_CMD_IDLE = 0, /**< IDLE */ + FLCC_CMD_ABORT = 1, /**< ABORT */ + FLCC_CMD_SLEEP = 2, /**< Requests flash to enter Sleep mode */ + FLCC_CMD_SIGN = 3, /**< SIGN */ + FLCC_CMD_WRITE = 4, /**< WRITE */ + FLCC_CMD_BLANK_CHECK = 5, /**< Checks all of User Space; fails if any bits in user space are cleared */ + FLCC_CMD_ERASEPAGE = 6, /**< ERASEPAGE */ + FLCC_CMD_MASSERASE = 7 /**< MASSERASE */ +} ADI_FLCC_CMD_VALUE; + + +/* ========================================================================== + *! \struct ADI_FLCC_CMD_Struct + *! \brief Command Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CMD_t__ +typedef struct _ADI_FLCC_CMD_t { + union { + struct { + unsigned int VALUE : 4; /**< Commands */ + unsigned int reserved4 : 28; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_CMD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CMD_t__ */ + +/*@}*/ + +/** @defgroup KH_ADDR Write Address (KH_ADDR) Register + * Write Address (KH_ADDR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_KH_ADDR_Struct + *! \brief Write Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KH_ADDR_t__ +typedef struct _ADI_FLCC_KH_ADDR_t { + union { + struct { + unsigned int reserved0 : 3; + unsigned int VALUE : 17; /**< Address to be written on a WRITE command */ + unsigned int reserved20 : 12; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_KH_ADDR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KH_ADDR_t__ */ + +/*@}*/ + +/** @defgroup KH_DATA0 Write Lower Data (KH_DATA0) Register + * Write Lower Data (KH_DATA0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_KH_DATA0_Struct + *! \brief Write Lower Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA0_t__ +typedef struct _ADI_FLCC_KH_DATA0_t { + union { + struct { + unsigned int VALUE : 32; /**< Lower half of 64-bit dual word data to be written on a Write command */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_KH_DATA0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA0_t__ */ + +/*@}*/ + +/** @defgroup KH_DATA1 Write Upper Data (KH_DATA1) Register + * Write Upper Data (KH_DATA1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_KH_DATA1_Struct + *! \brief Write Upper Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA1_t__ +typedef struct _ADI_FLCC_KH_DATA1_t { + union { + struct { + unsigned int VALUE : 32; /**< Upper half of 64-bit dual word data to be written on a Write command */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_KH_DATA1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA1_t__ */ + +/*@}*/ + +/** @defgroup PAGE_ADDR0 Lower Page Address (PAGE_ADDR0) Register + * Lower Page Address (PAGE_ADDR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_PAGE_ADDR0_Struct + *! \brief Lower Page Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR0_t__ +typedef struct _ADI_FLCC_PAGE_ADDR0_t { + union { + struct { + unsigned int reserved0 : 10; + unsigned int VALUE : 10; /**< Lower address bits of the page address */ + unsigned int reserved20 : 12; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_PAGE_ADDR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR0_t__ */ + +/*@}*/ + +/** @defgroup PAGE_ADDR1 Upper Page Address (PAGE_ADDR1) Register + * Upper Page Address (PAGE_ADDR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_PAGE_ADDR1_Struct + *! \brief Upper Page Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR1_t__ +typedef struct _ADI_FLCC_PAGE_ADDR1_t { + union { + struct { + unsigned int reserved0 : 10; + unsigned int VALUE : 10; /**< Upper address bits of the page address */ + unsigned int reserved20 : 12; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_PAGE_ADDR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR1_t__ */ + +/*@}*/ + +/** @defgroup KEY Key (KEY) Register + * Key (KEY) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_FLCC_KEY_VALUE + *! \brief Key register (VALUE) Enumerations + * ========================================================================= */ +typedef enum +{ + FLCC_KEY_USERKEY = 1735161189 /**< USERKEY */ +} ADI_FLCC_KEY_VALUE; + + +/* ========================================================================== + *! \struct ADI_FLCC_KEY_Struct + *! \brief Key Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KEY_t__ +typedef struct _ADI_FLCC_KEY_t { + union { + struct { + unsigned int VALUE : 32; /**< Key register */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_KEY_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KEY_t__ */ + +/*@}*/ + +/** @defgroup WR_ABORT_ADDR Write Abort Address (WR_ABORT_ADDR) Register + * Write Abort Address (WR_ABORT_ADDR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_WR_ABORT_ADDR_Struct + *! \brief Write Abort Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_WR_ABORT_ADDR_t__ +typedef struct _ADI_FLCC_WR_ABORT_ADDR_t { + union { + struct { + unsigned int VALUE : 32; /**< Address of recently aborted write command */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_WR_ABORT_ADDR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_WR_ABORT_ADDR_t__ */ + +/*@}*/ + +/** @defgroup WRPROT Write Protection (WRPROT) Register + * Write Protection (WRPROT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_WRPROT_Struct + *! \brief Write Protection Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_WRPROT_t__ +typedef struct _ADI_FLCC_WRPROT_t { + union { + struct { + unsigned int WORD : 32; /**< Clear bits to write protect related groups of user space pages */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_WRPROT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_WRPROT_t__ */ + +/*@}*/ + +/** @defgroup SIGNATURE Signature (SIGNATURE) Register + * Signature (SIGNATURE) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_SIGNATURE_Struct + *! \brief Signature Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_SIGNATURE_t__ +typedef struct _ADI_FLCC_SIGNATURE_t { + union { + struct { + unsigned int VALUE : 32; /**< Read signature */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_SIGNATURE_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_SIGNATURE_t__ */ + +/*@}*/ + +/** @defgroup UCFG User Configuration (UCFG) Register + * User Configuration (UCFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_UCFG_Struct + *! \brief User Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_UCFG_t__ +typedef struct _ADI_FLCC_UCFG_t { + union { + struct { + unsigned int KHDMAEN : 1; /**< Key hole DMA enable */ + unsigned int AUTOINCEN : 1; /**< Auto Address Increment for Key Hole Access */ + unsigned int reserved2 : 30; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_UCFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_UCFG_t__ */ + +/*@}*/ + +/** @defgroup TIME_PARAM0 Time Parameter 0 (TIME_PARAM0) Register + * Time Parameter 0 (TIME_PARAM0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_TIME_PARAM0_Struct + *! \brief Time Parameter 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM0_t__ +typedef struct _ADI_FLCC_TIME_PARAM0_t { + union { + struct { + unsigned int DIVREFCLK : 1; /**< Divide Reference Clock (by 2) */ + unsigned int reserved1 : 3; + unsigned int TNVS : 4; /**< PROG/ERASE to NVSTR setup time */ + unsigned int TPGS : 4; /**< NVSTR to Program setup time */ + unsigned int TPROG : 4; /**< Program time */ + unsigned int TNVH : 4; /**< NVSTR Hold time */ + unsigned int TRCV : 4; /**< Recovery time */ + unsigned int TERASE : 4; /**< Erase Time */ + unsigned int TNVH1 : 4; /**< NVSTR Hold time during Mass Erase */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_TIME_PARAM0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM0_t__ */ + +/*@}*/ + +/** @defgroup TIME_PARAM1 Time Parameter 1 (TIME_PARAM1) Register + * Time Parameter 1 (TIME_PARAM1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_TIME_PARAM1_Struct + *! \brief Time Parameter 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM1_t__ +typedef struct _ADI_FLCC_TIME_PARAM1_t { + union { + struct { + unsigned int TWK : 4; /**< Wake up time */ + unsigned int WAITSTATES : 3; /**< Number of wait states to access flash */ + unsigned int reserved7 : 1; + unsigned int CURWAITSTATES : 3; /**< Current wait states [2:0] */ + unsigned int reserved11 : 21; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_TIME_PARAM1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM1_t__ */ + +/*@}*/ + +/** @defgroup ABORT_EN_LO IRQ Abort Enable (Lower Bits) (ABORT_EN_LO) Register + * IRQ Abort Enable (Lower Bits) (ABORT_EN_LO) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_ABORT_EN_LO_Struct + *! \brief IRQ Abort Enable (Lower Bits) Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_LO_t__ +typedef struct _ADI_FLCC_ABORT_EN_LO_t { + union { + struct { + unsigned int VALUE : 32; /**< VALUE[31:0] Sys IRQ Abort Enable */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_ABORT_EN_LO_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_LO_t__ */ + +/*@}*/ + +/** @defgroup ABORT_EN_HI IRQ Abort Enable (Upper Bits) (ABORT_EN_HI) Register + * IRQ Abort Enable (Upper Bits) (ABORT_EN_HI) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_ABORT_EN_HI_Struct + *! \brief IRQ Abort Enable (Upper Bits) Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_HI_t__ +typedef struct _ADI_FLCC_ABORT_EN_HI_t { + union { + struct { + unsigned int VALUE : 32; /**< VALUE[63:32] Sys IRQ Abort Enable */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_ABORT_EN_HI_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_HI_t__ */ + +/*@}*/ + +/** @defgroup ECC_CFG ECC Configuration (ECC_CFG) Register + * ECC Configuration (ECC_CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_ECC_CFG_Struct + *! \brief ECC Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_CFG_t__ +typedef struct _ADI_FLCC_ECC_CFG_t { + union { + struct { + unsigned int EN : 1; /**< ECC Enable */ + unsigned int INFOEN : 1; /**< Info space ECC Enable bit */ + unsigned int reserved2 : 6; + unsigned int PTR : 24; /**< ECC start page pointer */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_ECC_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_CFG_t__ */ + +/*@}*/ + +/** @defgroup ECC_ADDR ECC Status (Address) (ECC_ADDR) Register + * ECC Status (Address) (ECC_ADDR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_ECC_ADDR_Struct + *! \brief ECC Status (Address) Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_ADDR_t__ +typedef struct _ADI_FLCC_ECC_ADDR_t { + union { + struct { + unsigned int VALUE : 20; /**< This register has the address for which ECC error is detected */ + unsigned int reserved20 : 12; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_ECC_ADDR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_ADDR_t__ */ + +/*@}*/ + +/** @defgroup POR_SEC Flash Security (POR_SEC) Register + * Flash Security (POR_SEC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_POR_SEC_Struct + *! \brief Flash Security Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_POR_SEC_t__ +typedef struct _ADI_FLCC_POR_SEC_t { + union { + struct { + unsigned int SECURE : 1; /**< Set this bit to prevent read or write access to User Space (sticky when set) */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_POR_SEC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_POR_SEC_t__ */ + +/*@}*/ + +/** @defgroup VOL_CFG Volatile Flash Configuration (VOL_CFG) Register + * Volatile Flash Configuration (VOL_CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_VOL_CFG_Struct + *! \brief Volatile Flash Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_VOL_CFG_t__ +typedef struct _ADI_FLCC_VOL_CFG_t { + union { + struct { + unsigned int INFO_REMAP : 1; /**< Alias the info space to the base address of user space */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_VOL_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_VOL_CFG_t__ */ + +/*@}*/ + +/** @defgroup STAT Cache Status Register (STAT) Register + * Cache Status Register (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_CACHE_STAT_Struct + *! \brief Cache Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_STAT_t__ +typedef struct _ADI_FLCC_CACHE_STAT_t { + union { + struct { + unsigned int ICEN : 1; /**< If this bit is set, I-Cache is enabled */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_CACHE_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_STAT_t__ */ + +/*@}*/ + +/** @defgroup SETUP Cache Setup Register (SETUP) Register + * Cache Setup Register (SETUP) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_CACHE_SETUP_Struct + *! \brief Cache Setup Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_SETUP_t__ +typedef struct _ADI_FLCC_CACHE_SETUP_t { + union { + struct { + unsigned int ICEN : 1; /**< If this bit set, I-Cache is enabled for AHB accesses */ + unsigned int LCKIC : 1; /**< If this bit is set, I-Cache contents are locked */ + unsigned int reserved2 : 30; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_CACHE_SETUP_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_SETUP_t__ */ + +/*@}*/ + +/** @defgroup KEY Cache Key Register (KEY) Register + * Cache Key Register (KEY) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_CACHE_KEY_Struct + *! \brief Cache Key Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_KEY_t__ +typedef struct _ADI_FLCC_CACHE_KEY_t { + union { + struct { + unsigned int VALUE : 32; /**< Cache Key */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_CACHE_KEY_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_KEY_t__ */ + +/*@}*/ + +/** @defgroup CFG Port Configuration (CFG) Register + * Port Configuration (CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_CFG_Struct + *! \brief Port Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_CFG_t__ +typedef struct _ADI_GPIO_CFG_t { + union { + struct { + unsigned int PIN00 : 2; /**< Pin 0 configuration bits */ + unsigned int PIN01 : 2; /**< Pin 1 configuration bits */ + unsigned int PIN02 : 2; /**< Pin 2 configuration bits */ + unsigned int PIN03 : 2; /**< Pin 3 configuration bits */ + unsigned int PIN04 : 2; /**< Pin 4 configuration bits */ + unsigned int PIN05 : 2; /**< Pin 5 configuration bits */ + unsigned int PIN06 : 2; /**< Pin 6 configuration bits */ + unsigned int PIN07 : 2; /**< Pin 7 configuration bits */ + unsigned int PIN08 : 2; /**< Pin 8 configuration bits */ + unsigned int PIN09 : 2; /**< Pin 9 configuration bits */ + unsigned int PIN10 : 2; /**< Pin 10 configuration bits */ + unsigned int PIN11 : 2; /**< Pin 11 configuration bits */ + unsigned int PIN12 : 2; /**< Pin 12 configuration bits */ + unsigned int PIN13 : 2; /**< Pin 13 configuration bits */ + unsigned int PIN14 : 2; /**< Pin 14 configuration bits */ + unsigned int PIN15 : 2; /**< Pin 15 configuration bits */ + }; + uint32_t VALUE32; + }; +} ADI_GPIO_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_CFG_t__ */ + +/*@}*/ + +/** @defgroup OEN Port Output Enable (OEN) Register + * Port Output Enable (OEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_OEN_Struct + *! \brief Port Output Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_OEN_t__ +typedef struct _ADI_GPIO_OEN_t { + union { + struct { + unsigned int VALUE : 16; /**< Pin Output Drive enable */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_OEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_OEN_t__ */ + +/*@}*/ + +/** @defgroup PE Port Output Pull-up/Pull-down Enable (PE) Register + * Port Output Pull-up/Pull-down Enable (PE) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_PE_Struct + *! \brief Port Output Pull-up/Pull-down Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_PE_t__ +typedef struct _ADI_GPIO_PE_t { + union { + struct { + unsigned int VALUE : 16; /**< Pin Pull enable */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_PE_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_PE_t__ */ + +/*@}*/ + +/** @defgroup IEN Port Input Path Enable (IEN) Register + * Port Input Path Enable (IEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_IEN_Struct + *! \brief Port Input Path Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IEN_t__ +typedef struct _ADI_GPIO_IEN_t { + union { + struct { + unsigned int VALUE : 16; /**< Input path enable */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_IEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IEN_t__ */ + +/*@}*/ + +/** @defgroup IN Port Registered Data Input (IN) Register + * Port Registered Data Input (IN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_IN_Struct + *! \brief Port Registered Data Input Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IN_t__ +typedef struct _ADI_GPIO_IN_t { + union { + struct { + unsigned int VALUE : 16; /**< Registered data input */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_IN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IN_t__ */ + +/*@}*/ + +/** @defgroup OUT Port Data Output (OUT) Register + * Port Data Output (OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_OUT_Struct + *! \brief Port Data Output Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_OUT_t__ +typedef struct _ADI_GPIO_OUT_t { + union { + struct { + unsigned int VALUE : 16; /**< Data out */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_OUT_t__ */ + +/*@}*/ + +/** @defgroup SET Port Data Out Set (SET) Register + * Port Data Out Set (SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_SET_Struct + *! \brief Port Data Out Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_SET_t__ +typedef struct _ADI_GPIO_SET_t { + union { + struct { + unsigned int VALUE : 16; /**< Set the output HIGH for the pin */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_SET_t__ */ + +/*@}*/ + +/** @defgroup CLR Port Data Out Clear (CLR) Register + * Port Data Out Clear (CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_CLR_Struct + *! \brief Port Data Out Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_CLR_t__ +typedef struct _ADI_GPIO_CLR_t { + union { + struct { + unsigned int VALUE : 16; /**< Set the output low for the port pin */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_CLR_t__ */ + +/*@}*/ + +/** @defgroup TGL Port Pin Toggle (TGL) Register + * Port Pin Toggle (TGL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_TGL_Struct + *! \brief Port Pin Toggle Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_TGL_t__ +typedef struct _ADI_GPIO_TGL_t { + union { + struct { + unsigned int VALUE : 16; /**< Toggle the output of the port pin */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_TGL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_TGL_t__ */ + +/*@}*/ + +/** @defgroup POL Port Interrupt Polarity (POL) Register + * Port Interrupt Polarity (POL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_POL_Struct + *! \brief Port Interrupt Polarity Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_POL_t__ +typedef struct _ADI_GPIO_POL_t { + union { + struct { + unsigned int VALUE : 16; /**< Interrupt polarity */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_POL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_POL_t__ */ + +/*@}*/ + +/** @defgroup IENA Port Interrupt A Enable (IENA) Register + * Port Interrupt A Enable (IENA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_IENA_Struct + *! \brief Port Interrupt A Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IENA_t__ +typedef struct _ADI_GPIO_IENA_t { + union { + struct { + unsigned int VALUE : 16; /**< Interrupt A enable */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_IENA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IENA_t__ */ + +/*@}*/ + +/** @defgroup IENB Port Interrupt B Enable (IENB) Register + * Port Interrupt B Enable (IENB) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_IENB_Struct + *! \brief Port Interrupt B Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IENB_t__ +typedef struct _ADI_GPIO_IENB_t { + union { + struct { + unsigned int VALUE : 16; /**< Interrupt B enable */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_IENB_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IENB_t__ */ + +/*@}*/ + +/** @defgroup INT Port Interrupt Status (INT) Register + * Port Interrupt Status (INT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_INT_Struct + *! \brief Port Interrupt Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_INT_t__ +typedef struct _ADI_GPIO_INT_t { + union { + struct { + unsigned int VALUE : 16; /**< Interrupt Status */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_INT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_INT_t__ */ + +/*@}*/ + +/** @defgroup DS Port Drive Strength Select (DS) Register + * Port Drive Strength Select (DS) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_DS_Struct + *! \brief Port Drive Strength Select Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_DS_t__ +typedef struct _ADI_GPIO_DS_t { + union { + struct { + unsigned int VALUE : 16; /**< Drive strength select */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_DS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_DS_t__ */ + +/*@}*/ + +/** @defgroup CTL_A Half SPORT 'A' Control Register (CTL_A) Register + * Half SPORT 'A' Control Register (CTL_A) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_SPEN + *! \brief Serial Port Enable (SPEN) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_DIS = 0, /**< Disable */ + SPORT_CTL_A_CTL_EN = 1 /**< Enable */ +} ADI_SPORT_CTL_A_SPEN; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_FSMUXSEL + *! \brief Frame Sync Multiplexer Select (FSMUXSEL) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_FS_MUX_DIS = 0, /**< Disable frame sync multiplexing */ + SPORT_CTL_A_CTL_FS_MUX_EN = 1 /**< Enable frame sync multiplexing */ +} ADI_SPORT_CTL_A_FSMUXSEL; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_CKMUXSEL + *! \brief Clock Multiplexer Select (CKMUXSEL) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_CLK_MUX_DIS = 0, /**< Disable serial clock multiplexing */ + SPORT_CTL_A_CTL_CLK_MUX_EN = 1 /**< Enable serial clock multiplexing */ +} ADI_SPORT_CTL_A_CKMUXSEL; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_LSBF + *! \brief Least-Significant Bit First (LSBF) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_MSB_FIRST = 0, /**< MSB first sent/received */ + SPORT_CTL_A_CTL_LSB_FIRST = 1 /**< LSB first sent/received */ +} ADI_SPORT_CTL_A_LSBF; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_ICLK + *! \brief Internal Clock (ICLK) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_EXTERNAL_CLK = 0, /**< External clock */ + SPORT_CTL_A_CTL_INTERNAL_CLK = 1 /**< Internal clock */ +} ADI_SPORT_CTL_A_ICLK; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_OPMODE + *! \brief Operation mode (OPMODE) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_SERIAL = 0, /**< DSP standard */ + SPORT_CTL_A_CTL_TIMER_EN_MODE = 1 /**< Timer_enable mode */ +} ADI_SPORT_CTL_A_OPMODE; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_CKRE + *! \brief Clock Rising Edge (CKRE) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_CLK_FALL_EDGE = 0, /**< Clock falling edge */ + SPORT_CTL_A_CTL_CLK_RISE_EDGE = 1 /**< Clock rising edge */ +} ADI_SPORT_CTL_A_CKRE; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_FSR + *! \brief Frame Sync Required (FSR) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_FS_NOT_REQ = 0, /**< No frame sync required */ + SPORT_CTL_A_CTL_FS_REQ = 1 /**< Frame sync required */ +} ADI_SPORT_CTL_A_FSR; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_IFS + *! \brief Internal Frame Sync (IFS) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_EXTERNAL_FS = 0, /**< External frame sync */ + SPORT_CTL_A_CTL_INTERNAL_FS = 1 /**< Internal frame sync */ +} ADI_SPORT_CTL_A_IFS; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_DIFS + *! \brief Data-Independent Frame Sync (DIFS) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_DATA_DEP_FS = 0, /**< Data-dependent frame sync */ + SPORT_CTL_A_CTL_DATA_INDP_FS = 1 /**< Data-independent frame sync */ +} ADI_SPORT_CTL_A_DIFS; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_LFS + *! \brief Active-Low Frame Sync (LFS) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_FS_LO = 0, /**< Active high frame sync */ + SPORT_CTL_A_CTL_FS_HI = 1 /**< Active low frame sync */ +} ADI_SPORT_CTL_A_LFS; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_LAFS + *! \brief Late Frame Sync (LAFS) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_EARLY_FS = 0, /**< Early frame sync */ + SPORT_CTL_A_CTL_LATE_FS = 1 /**< Late frame sync */ +} ADI_SPORT_CTL_A_LAFS; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_PACK + *! \brief Packing Enable (PACK) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_PACK_DIS = 0, /**< Disable */ + SPORT_CTL_A_CTL_PACK_8BIT = 1, /**< 8-bit packing enable */ + SPORT_CTL_A_CTL_PACK_16BIT = 2 /**< 16-bit packing enable */ +} ADI_SPORT_CTL_A_PACK; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_GCLKEN + *! \brief Gated Clock Enable (GCLKEN) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_GCLK_DIS = 0, /**< Disable */ + SPORT_CTL_A_CTL_GCLK_EN = 1 /**< Enable */ +} ADI_SPORT_CTL_A_GCLKEN; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_SPTRAN + *! \brief Serial Port Transfer Direction (SPTRAN) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_RX = 0, /**< Receive */ + SPORT_CTL_A_CTL_TX = 1 /**< Transmit */ +} ADI_SPORT_CTL_A_SPTRAN; + + +/* ========================================================================== + *! \struct ADI_SPORT_CTL_A_Struct + *! \brief Half SPORT 'A' Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_A_t__ +typedef struct _ADI_SPORT_CTL_A_t { + union { + struct { + unsigned int SPEN : 1; /**< Serial Port Enable */ + unsigned int FSMUXSEL : 1; /**< Frame Sync Multiplexer Select */ + unsigned int CKMUXSEL : 1; /**< Clock Multiplexer Select */ + unsigned int LSBF : 1; /**< Least-Significant Bit First */ + unsigned int SLEN : 5; /**< Serial Word Length */ + unsigned int reserved9 : 1; + unsigned int ICLK : 1; /**< Internal Clock */ + unsigned int OPMODE : 1; /**< Operation mode */ + unsigned int CKRE : 1; /**< Clock Rising Edge */ + unsigned int FSR : 1; /**< Frame Sync Required */ + unsigned int IFS : 1; /**< Internal Frame Sync */ + unsigned int DIFS : 1; /**< Data-Independent Frame Sync */ + unsigned int LFS : 1; /**< Active-Low Frame Sync */ + unsigned int LAFS : 1; /**< Late Frame Sync */ + unsigned int PACK : 2; /**< Packing Enable */ + unsigned int FSERRMODE : 1; /**< Frame Sync Error Operation */ + unsigned int GCLKEN : 1; /**< Gated Clock Enable */ + unsigned int reserved22 : 3; + unsigned int SPTRAN : 1; /**< Serial Port Transfer Direction */ + unsigned int DMAEN : 1; /**< DMA Enable */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_CTL_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_A_t__ */ + +/*@}*/ + +/** @defgroup DIV_A Half SPORT 'A' Divisor Register (DIV_A) Register + * Half SPORT 'A' Divisor Register (DIV_A) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_DIV_A_Struct + *! \brief Half SPORT 'A' Divisor Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_A_t__ +typedef struct _ADI_SPORT_DIV_A_t { + union { + struct { + unsigned int CLKDIV : 16; /**< Clock Divisor */ + unsigned int FSDIV : 8; /**< Frame Sync Divisor */ + unsigned int reserved24 : 8; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_DIV_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_A_t__ */ + +/*@}*/ + +/** @defgroup IEN_A Half SPORT A's Interrupt Enable register (IEN_A) Register + * Half SPORT A's Interrupt Enable register (IEN_A) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_SPORT_IEN_A_TF + *! \brief Transfer Finish Interrupt Enable (TF) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_IEN_A_CTL_TXFIN_DIS = 0, /**< Transfer finish Interrupt is disabled */ + SPORT_IEN_A_CTL_TXFIN_EN = 1 /**< Transfer Finish Interrupt is Enabled */ +} ADI_SPORT_IEN_A_TF; + + +/* ========================================================================== + *! \struct ADI_SPORT_IEN_A_Struct + *! \brief Half SPORT A's Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_A_t__ +typedef struct _ADI_SPORT_IEN_A_t { + union { + struct { + unsigned int TF : 1; /**< Transfer Finish Interrupt Enable */ + unsigned int DERRMSK : 1; /**< Data Error (Interrupt) Mask */ + unsigned int FSERRMSK : 1; /**< Frame Sync Error (Interrupt) Mask */ + unsigned int DATA : 1; /**< Data request interrupt to the core */ + unsigned int SYSDATERR : 1; /**< Data error for system writes or reads */ + unsigned int reserved5 : 27; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_IEN_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_A_t__ */ + +/*@}*/ + +/** @defgroup STAT_A Half SPORT 'A' Status register (STAT_A) Register + * Half SPORT 'A' Status register (STAT_A) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_SPORT_STAT_A_DXS + *! \brief Data Transfer Buffer Status (DXS) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_STAT_A_CTL_EMPTY = 0, /**< Empty */ + SPORT_STAT_A_CTL_PART_FULL = 2, /**< Partially full */ + SPORT_STAT_A_CTL_FULL = 3 /**< Full */ +} ADI_SPORT_STAT_A_DXS; + + +/* ========================================================================== + *! \struct ADI_SPORT_STAT_A_Struct + *! \brief Half SPORT 'A' Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_A_t__ +typedef struct _ADI_SPORT_STAT_A_t { + union { + struct { + unsigned int TFI : 1; /**< Transmit Finish Interrupt Status */ + unsigned int DERR : 1; /**< Data Error Status */ + unsigned int FSERR : 1; /**< Frame Sync Error Status */ + unsigned int DATA : 1; /**< Data Buffer status */ + unsigned int SYSDATERR : 1; /**< System Data Error Status */ + unsigned int reserved5 : 3; + unsigned int DXS : 2; /**< Data Transfer Buffer Status */ + unsigned int reserved10 : 22; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_STAT_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_A_t__ */ + +/*@}*/ + +/** @defgroup NUMTRAN_A Half SPORT A Number of transfers register (NUMTRAN_A) Register + * Half SPORT A Number of transfers register (NUMTRAN_A) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_NUMTRAN_A_Struct + *! \brief Half SPORT A Number of transfers Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_A_t__ +typedef struct _ADI_SPORT_NUMTRAN_A_t { + union { + struct { + unsigned int VALUE : 12; /**< Number of transfers (Half SPORT A) */ + unsigned int reserved12 : 20; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_NUMTRAN_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_A_t__ */ + +/*@}*/ + +/** @defgroup CNVT_A Half SPORT 'A' CNV width (CNVT_A) Register + * Half SPORT 'A' CNV width (CNVT_A) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_CNVT_A_Struct + *! \brief Half SPORT 'A' CNV width Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_A_t__ +typedef struct _ADI_SPORT_CNVT_A_t { + union { + struct { + unsigned int WID : 4; /**< CNV signal width: Half SPORT A */ + unsigned int reserved4 : 4; + unsigned int POL : 1; /**< Polarity of the CNV signal */ + unsigned int reserved9 : 7; + unsigned int CNVT2FS : 8; /**< CNV to FS duration: Half SPORT A */ + unsigned int reserved24 : 8; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_CNVT_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_A_t__ */ + +/*@}*/ + +/** @defgroup TX_A Half SPORT 'A' Tx Buffer Register (TX_A) Register + * Half SPORT 'A' Tx Buffer Register (TX_A) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_TX_A_Struct + *! \brief Half SPORT 'A' Tx Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_TX_A_t__ +typedef struct _ADI_SPORT_TX_A_t { + union { + struct { + unsigned int VALUE : 32; /**< Transmit Buffer */ + }; + uint32_t VALUE32; + }; +} ADI_SPORT_TX_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_TX_A_t__ */ + +/*@}*/ + +/** @defgroup RX_A Half SPORT 'A' Rx Buffer Register (RX_A) Register + * Half SPORT 'A' Rx Buffer Register (RX_A) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_RX_A_Struct + *! \brief Half SPORT 'A' Rx Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_RX_A_t__ +typedef struct _ADI_SPORT_RX_A_t { + union { + struct { + unsigned int VALUE : 32; /**< Receive Buffer */ + }; + uint32_t VALUE32; + }; +} ADI_SPORT_RX_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_RX_A_t__ */ + +/*@}*/ + +/** @defgroup CTL_B Half SPORT 'B' Control Register (CTL_B) Register + * Half SPORT 'B' Control Register (CTL_B) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_B_PACK + *! \brief Packing Enable (PACK) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_B_CTL_PACK_DIS = 0, /**< Disable */ + SPORT_CTL_B_CTL_PACK_8BIT = 1, /**< 8-bit packing enable */ + SPORT_CTL_B_CTL_PACK_16BIT = 2 /**< 16-bit packing enable */ +} ADI_SPORT_CTL_B_PACK; + + +/* ========================================================================== + *! \struct ADI_SPORT_CTL_B_Struct + *! \brief Half SPORT 'B' Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_B_t__ +typedef struct _ADI_SPORT_CTL_B_t { + union { + struct { + unsigned int SPEN : 1; /**< Serial Port Enable */ + unsigned int reserved1 : 2; + unsigned int LSBF : 1; /**< Least-Significant Bit First */ + unsigned int SLEN : 5; /**< Serial Word Length */ + unsigned int reserved9 : 1; + unsigned int ICLK : 1; /**< Internal Clock */ + unsigned int OPMODE : 1; /**< Operation mode */ + unsigned int CKRE : 1; /**< Clock Rising Edge */ + unsigned int FSR : 1; /**< Frame Sync Required */ + unsigned int IFS : 1; /**< Internal Frame Sync */ + unsigned int DIFS : 1; /**< Data-Independent Frame Sync */ + unsigned int LFS : 1; /**< Active-Low Frame Sync */ + unsigned int LAFS : 1; /**< Late Frame Sync */ + unsigned int PACK : 2; /**< Packing Enable */ + unsigned int FSERRMODE : 1; /**< Frame Sync Error Operation */ + unsigned int GCLKEN : 1; /**< Gated Clock Enable */ + unsigned int reserved22 : 3; + unsigned int SPTRAN : 1; /**< Serial Port Transfer Direction */ + unsigned int DMAEN : 1; /**< DMA Enable */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_CTL_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_B_t__ */ + +/*@}*/ + +/** @defgroup DIV_B Half SPORT 'B' Divisor Register (DIV_B) Register + * Half SPORT 'B' Divisor Register (DIV_B) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_DIV_B_Struct + *! \brief Half SPORT 'B' Divisor Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_B_t__ +typedef struct _ADI_SPORT_DIV_B_t { + union { + struct { + unsigned int CLKDIV : 16; /**< Clock Divisor */ + unsigned int FSDIV : 8; /**< Frame Sync Divisor */ + unsigned int reserved24 : 8; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_DIV_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_B_t__ */ + +/*@}*/ + +/** @defgroup IEN_B Half SPORT B's Interrupt Enable register (IEN_B) Register + * Half SPORT B's Interrupt Enable register (IEN_B) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_SPORT_IEN_B_TF + *! \brief Transmit Finish Interrupt Enable (TF) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_IEN_B_CTL_TXFIN_DIS = 0, /**< Transfer Finish Interrupt is disabled */ + SPORT_IEN_B_CTL_TXFIN_EN = 1 /**< Transfer Finish Interrupt is Enabled */ +} ADI_SPORT_IEN_B_TF; + + +/* ========================================================================== + *! \struct ADI_SPORT_IEN_B_Struct + *! \brief Half SPORT B's Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_B_t__ +typedef struct _ADI_SPORT_IEN_B_t { + union { + struct { + unsigned int TF : 1; /**< Transmit Finish Interrupt Enable */ + unsigned int DERRMSK : 1; /**< Data Error (Interrupt) Mask */ + unsigned int FSERRMSK : 1; /**< Frame Sync Error (Interrupt) Mask */ + unsigned int DATA : 1; /**< Data request interrupt to the core */ + unsigned int SYSDATERR : 1; /**< Data error for system writes or reads */ + unsigned int reserved5 : 27; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_IEN_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_B_t__ */ + +/*@}*/ + +/** @defgroup STAT_B Half SPORT 'B' Status register (STAT_B) Register + * Half SPORT 'B' Status register (STAT_B) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_SPORT_STAT_B_DXS + *! \brief Data Transfer Buffer Status (DXS) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_STAT_B_CTL_EMPTY = 0, /**< Empty */ + SPORT_STAT_B_CTL_PART_FULL = 2, /**< Partially full */ + SPORT_STAT_B_CTL_FULL = 3 /**< Full */ +} ADI_SPORT_STAT_B_DXS; + + +/* ========================================================================== + *! \struct ADI_SPORT_STAT_B_Struct + *! \brief Half SPORT 'B' Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_B_t__ +typedef struct _ADI_SPORT_STAT_B_t { + union { + struct { + unsigned int TFI : 1; /**< Transmit Finish Interrupt Status */ + unsigned int DERR : 1; /**< Data Error Status */ + unsigned int FSERR : 1; /**< Frame Sync Error Status */ + unsigned int DATA : 1; /**< Data Buffer status */ + unsigned int SYSDATERR : 1; /**< System Data Error Status */ + unsigned int reserved5 : 3; + unsigned int DXS : 2; /**< Data Transfer Buffer Status */ + unsigned int reserved10 : 22; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_STAT_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_B_t__ */ + +/*@}*/ + +/** @defgroup NUMTRAN_B Half SPORT B Number of transfers register (NUMTRAN_B) Register + * Half SPORT B Number of transfers register (NUMTRAN_B) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_NUMTRAN_B_Struct + *! \brief Half SPORT B Number of transfers Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_B_t__ +typedef struct _ADI_SPORT_NUMTRAN_B_t { + union { + struct { + unsigned int VALUE : 12; /**< Number of transfers (Half SPORT A) */ + unsigned int reserved12 : 20; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_NUMTRAN_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_B_t__ */ + +/*@}*/ + +/** @defgroup CNVT_B Half SPORT 'B' CNV width register (CNVT_B) Register + * Half SPORT 'B' CNV width register (CNVT_B) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_CNVT_B_Struct + *! \brief Half SPORT 'B' CNV width Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_B_t__ +typedef struct _ADI_SPORT_CNVT_B_t { + union { + struct { + unsigned int WID : 4; /**< CNV signal width: Half SPORT B */ + unsigned int reserved4 : 4; + unsigned int POL : 1; /**< Polarity of the CNV signal */ + unsigned int reserved9 : 7; + unsigned int CNVT2FS : 8; /**< CNV to FS duration: Half SPORT B */ + unsigned int reserved24 : 8; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_CNVT_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_B_t__ */ + +/*@}*/ + +/** @defgroup TX_B Half SPORT 'B' Tx Buffer Register (TX_B) Register + * Half SPORT 'B' Tx Buffer Register (TX_B) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_TX_B_Struct + *! \brief Half SPORT 'B' Tx Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_TX_B_t__ +typedef struct _ADI_SPORT_TX_B_t { + union { + struct { + unsigned int VALUE : 32; /**< Transmit Buffer */ + }; + uint32_t VALUE32; + }; +} ADI_SPORT_TX_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_TX_B_t__ */ + +/*@}*/ + +/** @defgroup RX_B Half SPORT 'B' Rx Buffer Register (RX_B) Register + * Half SPORT 'B' Rx Buffer Register (RX_B) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_RX_B_Struct + *! \brief Half SPORT 'B' Rx Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_RX_B_t__ +typedef struct _ADI_SPORT_RX_B_t { + union { + struct { + unsigned int VALUE : 32; /**< Receive Buffer */ + }; + uint32_t VALUE32; + }; +} ADI_SPORT_RX_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_RX_B_t__ */ + +/*@}*/ + +/** @defgroup CTL CRC Control (CTL) Register + * CRC Control (CTL) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_CRC_CTL_EN + *! \brief CRC Peripheral Enable (EN) Enumerations + * ========================================================================= */ +typedef enum +{ + CRC_CTL_CRC_DIS = 0, /**< CRC peripheral is disabled */ + CRC_CTL_CRC_EN = 1 /**< CRC peripheral is enabled */ +} ADI_CRC_CTL_EN; + + +/* ========================================================================= + *! \enum ADI_CRC_CTL_LSBFIRST + *! \brief LSB First Calculation Order (LSBFIRST) Enumerations + * ========================================================================= */ +typedef enum +{ + CRC_CTL_MSB_FIRST = 0, /**< MSB First CRC calculation is done */ + CRC_CTL_LSB_FIRST = 1 /**< LSB First CRC calculation is done */ +} ADI_CRC_CTL_LSBFIRST; + + +/* ========================================================================= + *! \enum ADI_CRC_CTL_BITMIRR + *! \brief Bit Mirroring (BITMIRR) Enumerations + * ========================================================================= */ +typedef enum +{ + CRC_CTL_BITMIRR_DIS = 0, /**< Bit Mirroring is disabled */ + CRC_CTL_BITMIRR_EN = 1 /**< Bit Mirroring is enabled */ +} ADI_CRC_CTL_BITMIRR; + + +/* ========================================================================= + *! \enum ADI_CRC_CTL_BYTMIRR + *! \brief Byte Mirroring (BYTMIRR) Enumerations + * ========================================================================= */ +typedef enum +{ + CRC_CTL_BYTEMIR_DIS = 0, /**< Byte Mirroring is disabled */ + CRC_CTL_BYTEMIR_EN = 1 /**< Byte Mirroring is enabled */ +} ADI_CRC_CTL_BYTMIRR; + + +/* ========================================================================= + *! \enum ADI_CRC_CTL_W16SWP + *! \brief Word16 Swap (W16SWP) Enumerations + * ========================================================================= */ +typedef enum +{ + CRC_CTL_W16SP_DIS = 0, /**< Word16 Swap disabled */ + CRC_CTL_W16SP_EN = 1 /**< Word16 Swap enabled */ +} ADI_CRC_CTL_W16SWP; + + +/* ========================================================================== + *! \struct ADI_CRC_CTL_Struct + *! \brief CRC Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_CTL_t__ +typedef struct _ADI_CRC_CTL_t { + union { + struct { + unsigned int EN : 1; /**< CRC Peripheral Enable */ + unsigned int LSBFIRST : 1; /**< LSB First Calculation Order */ + unsigned int BITMIRR : 1; /**< Bit Mirroring */ + unsigned int BYTMIRR : 1; /**< Byte Mirroring */ + unsigned int W16SWP : 1; /**< Word16 Swap */ + unsigned int reserved5 : 23; + unsigned int RevID : 4; /**< Revision ID */ + }; + uint32_t VALUE32; + }; +} ADI_CRC_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_CTL_t__ */ + +/*@}*/ + +/** @defgroup IPDATA Input Data Word (IPDATA) Register + * Input Data Word (IPDATA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRC_IPDATA_Struct + *! \brief Input Data Word Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_IPDATA_t__ +typedef struct _ADI_CRC_IPDATA_t { + union { + struct { + unsigned int VALUE : 32; /**< Data Input */ + }; + uint32_t VALUE32; + }; +} ADI_CRC_IPDATA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_IPDATA_t__ */ + +/*@}*/ + +/** @defgroup RESULT CRC Result (RESULT) Register + * CRC Result (RESULT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRC_RESULT_Struct + *! \brief CRC Result Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_RESULT_t__ +typedef struct _ADI_CRC_RESULT_t { + union { + struct { + unsigned int VALUE : 32; /**< CRC Residue */ + }; + uint32_t VALUE32; + }; +} ADI_CRC_RESULT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_RESULT_t__ */ + +/*@}*/ + +/** @defgroup POLY Programmable CRC Polynomial (POLY) Register + * Programmable CRC Polynomial (POLY) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRC_POLY_Struct + *! \brief Programmable CRC Polynomial Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_POLY_t__ +typedef struct _ADI_CRC_POLY_t { + union { + struct { + unsigned int VALUE : 32; /**< CRC Reduction Polynomial */ + }; + uint32_t VALUE32; + }; +} ADI_CRC_POLY_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_POLY_t__ */ + +/*@}*/ + +/** @defgroup IPBITS Input Data Bits (IPBITS) Register + * Input Data Bits (IPBITS) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRC_IPBITS_Struct + *! \brief Input Data Bits Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_IPBITS_t__ +typedef struct _ADI_CRC_IPBITS_t { + union { + struct { + unsigned int DATA_BITS : 8; /**< Input Data Bits */ + }; + uint8_t VALUE8; + }; +} ADI_CRC_IPBITS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_IPBITS_t__ */ + +/*@}*/ + +/** @defgroup IPBYTE Input Data Byte (IPBYTE) Register + * Input Data Byte (IPBYTE) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRC_IPBYTE_Struct + *! \brief Input Data Byte Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_IPBYTE_t__ +typedef struct _ADI_CRC_IPBYTE_t { + union { + struct { + unsigned int DATA_BYTE : 8; /**< Input Data Byte */ + }; + uint8_t VALUE8; + }; +} ADI_CRC_IPBYTE_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_IPBYTE_t__ */ + +/*@}*/ + +/** @defgroup CTL RNG Control Register (CTL) Register + * RNG Control Register (CTL) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_RNG_CTL_EN + *! \brief RNG Enable (EN) Enumerations + * ========================================================================= */ +typedef enum +{ + RNG_CTL_DISABLE = 0, /**< Disable the RNG */ + RNG_CTL_ENABLE = 1 /**< Enable the RNG */ +} ADI_RNG_CTL_EN; + + +/* ========================================================================= + *! \enum ADI_RNG_CTL_SINGLE + *! \brief Generate a Single Number (SINGLE) Enumerations + * ========================================================================= */ +typedef enum +{ + RNG_CTL_WORD = 0, /**< Buffer Word */ + RNG_CTL_SINGLE = 1 /**< Single Byte */ +} ADI_RNG_CTL_SINGLE; + + +/* ========================================================================== + *! \struct ADI_RNG_CTL_Struct + *! \brief RNG Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_CTL_t__ +typedef struct _ADI_RNG_CTL_t { + union { + struct { + unsigned int EN : 1; /**< RNG Enable */ + unsigned int reserved1 : 2; + unsigned int SINGLE : 1; /**< Generate a Single Number */ + unsigned int reserved4 : 12; + }; + uint16_t VALUE16; + }; +} ADI_RNG_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_CTL_t__ */ + +/*@}*/ + +/** @defgroup LEN RNG Sample Length Register (LEN) Register + * RNG Sample Length Register (LEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RNG_LEN_Struct + *! \brief RNG Sample Length Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_LEN_t__ +typedef struct _ADI_RNG_LEN_t { + union { + struct { + unsigned int RELOAD : 12; /**< Reload Value for the Sample Counter */ + unsigned int PRESCALE : 4; /**< Prescaler for the Sample Counter */ + }; + uint16_t VALUE16; + }; +} ADI_RNG_LEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_LEN_t__ */ + +/*@}*/ + +/** @defgroup STAT RNG Status Register (STAT) Register + * RNG Status Register (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RNG_STAT_Struct + *! \brief RNG Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_STAT_t__ +typedef struct _ADI_RNG_STAT_t { + union { + struct { + unsigned int RNRDY : 1; /**< Random Number Ready */ + unsigned int STUCK : 1; /**< Sampled Data Stuck High or Low */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_RNG_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_STAT_t__ */ + +/*@}*/ + +/** @defgroup DATA RNG Data Register (DATA) Register + * RNG Data Register (DATA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RNG_DATA_Struct + *! \brief RNG Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_DATA_t__ +typedef struct _ADI_RNG_DATA_t { + union { + struct { + unsigned int VALUE : 8; /**< Value of the CRC Accumulator */ + unsigned int BUFF : 24; /**< Buffer for RNG Data */ + }; + uint32_t VALUE32; + }; +} ADI_RNG_DATA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_DATA_t__ */ + +/*@}*/ + +/** @defgroup OSCCNT Oscillator Count (OSCCNT) Register + * Oscillator Count (OSCCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RNG_OSCCNT_Struct + *! \brief Oscillator Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_OSCCNT_t__ +typedef struct _ADI_RNG_OSCCNT_t { + union { + struct { + unsigned int VALUE : 28; /**< Oscillator Count */ + unsigned int reserved28 : 4; + }; + uint32_t VALUE32; + }; +} ADI_RNG_OSCCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_OSCCNT_t__ */ + +/*@}*/ + +/** @defgroup OSCDIFF Oscillator Difference (OSCDIFF) Register + * Oscillator Difference (OSCDIFF) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RNG_OSCDIFF_Struct + *! \brief Oscillator Difference Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_OSCDIFF_t__ +typedef struct _ADI_RNG_OSCDIFF_t { + union { + struct { + signed int DELTA : 8; /**< Oscillator Count Difference */ + }; + int8_t VALUE8; + }; +} ADI_RNG_OSCDIFF_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_OSCDIFF_t__ */ + +/*@}*/ + +/** @defgroup CFG Configuration Register (CFG) Register + * Configuration Register (CFG) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_CRYPT_CFG_BLKEN + *! \brief Enable Bit for Crypto Block (BLKEN) Enumerations + * ========================================================================= */ +typedef enum +{ + CRYPT_CFG_ENABLE = 0, /**< Enable Crypto Block */ + CRYPT_CFG_DISABLE = 1 /**< Disable Crypto Block */ +} ADI_CRYPT_CFG_BLKEN; + + +/* ========================================================================= + *! \enum ADI_CRYPT_CFG_INDMAEN + *! \brief Enable DMA Channel Request for Input Buffer (INDMAEN) Enumerations + * ========================================================================= */ +typedef enum +{ + CRYPT_CFG_DMA_DISABLE_INBUF = 0, /**< Disable DMA Requesting for Input Buffer */ + CRYPT_CFG_DMA_ENABLE_INBUF = 1 /**< Enable DMA Requesting for Input Buffer */ +} ADI_CRYPT_CFG_INDMAEN; + + +/* ========================================================================= + *! \enum ADI_CRYPT_CFG_OUTDMAEN + *! \brief Enable DMA Channel Request for Output Buffer (OUTDMAEN) Enumerations + * ========================================================================= */ +typedef enum +{ + CRYPT_CFG_DMA_DISABLE_OUTBUF = 0, /**< Disable DMA Requesting for Output Buffer */ + CRYPT_CFG_DMA_ENABLE_OUTBUF = 1 /**< Enable DMA Requesting for Output Buffer */ +} ADI_CRYPT_CFG_OUTDMAEN; + + +/* ========================================================================= + *! \enum ADI_CRYPT_CFG_AESKEYLEN + *! \brief Select Key Length for AES Cipher (AESKEYLEN) Enumerations + * ========================================================================= */ +typedef enum +{ + CRYPT_CFG_AESKEYLEN128 = 0, /**< Uses 128-bit long key */ + CRYPT_CFG_AESKEYLEN256 = 2 /**< Uses 256-bit long key */ +} ADI_CRYPT_CFG_AESKEYLEN; + + +/* ========================================================================= + *! \enum ADI_CRYPT_CFG_KUWKeyLen + *! \brief Key Length Key Wrap Unwrap (KUWKeyLen) Enumerations + * ========================================================================= */ +typedef enum +{ + CRYPT_CFG_LEN128 = 1, /**< The key size of KUW key is 128 bits */ + CRYPT_CFG_LEN256 = 2, /**< The key size of KUW key is 256 bits */ + CRYPT_CFG_LEN512 = 3 /**< The key size of KUW key is 512 bits */ +} ADI_CRYPT_CFG_KUWKeyLen; + + +/* ========================================================================== + *! \struct ADI_CRYPT_CFG_Struct + *! \brief Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_CFG_t__ +typedef struct _ADI_CRYPT_CFG_t { + union { + struct { + unsigned int BLKEN : 1; /**< Enable Bit for Crypto Block */ + unsigned int ENCR : 1; /**< Encrypt or Decrypt */ + unsigned int INDMAEN : 1; /**< Enable DMA Channel Request for Input Buffer */ + unsigned int OUTDMAEN : 1; /**< Enable DMA Channel Request for Output Buffer */ + unsigned int INFLUSH : 1; /**< Input Buffer Flush */ + unsigned int OUTFLUSH : 1; /**< Output Buffer Flush */ + unsigned int reserved6 : 2; + unsigned int AESKEYLEN : 2; /**< Select Key Length for AES Cipher */ + unsigned int KUWKeyLen : 2; /**< Key Length Key Wrap Unwrap */ + unsigned int AES_BYTESWAP : 1; /**< Byteswap for AES Input */ + unsigned int SHA_BYTESWAP : 1; /**< Enable Key Wrap */ + unsigned int KEY_BYTESWAP : 1; /**< Use Key Unwrap Before HMAC */ + unsigned int PRKSTOREN : 1; /**< Enable PRKSTOR Commands */ + unsigned int ECBEN : 1; /**< Enable ECB Mode Operation */ + unsigned int CTREN : 1; /**< Enable CTR Mode Operation */ + unsigned int CBCEN : 1; /**< Enable CBC Mode Operation */ + unsigned int CCMEN : 1; /**< Enable CCM/CCM* Mode Operation */ + unsigned int CMACEN : 1; /**< Enable CMAC Mode Operation */ + unsigned int HMACEN : 1; /**< HMAC Enable */ + unsigned int reserved22 : 3; + unsigned int SHA256EN : 1; /**< Enable SHA-256 Operation */ + unsigned int SHAINIT : 1; /**< Restarts SHA Computation */ + unsigned int reserved27 : 1; + unsigned int RevID : 4; /**< Rev ID for Crypto */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_CFG_t__ */ + +/*@}*/ + +/** @defgroup DATALEN Payload Data Length (DATALEN) Register + * Payload Data Length (DATALEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_DATALEN_Struct + *! \brief Payload Data Length Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_DATALEN_t__ +typedef struct _ADI_CRYPT_DATALEN_t { + union { + struct { + unsigned int VALUE : 20; /**< Length of Payload Data */ + unsigned int reserved20 : 12; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_DATALEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_DATALEN_t__ */ + +/*@}*/ + +/** @defgroup PREFIXLEN Authentication Data Length (PREFIXLEN) Register + * Authentication Data Length (PREFIXLEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_PREFIXLEN_Struct + *! \brief Authentication Data Length Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_PREFIXLEN_t__ +typedef struct _ADI_CRYPT_PREFIXLEN_t { + union { + struct { + unsigned int VALUE : 16; /**< Length of Associated Data */ + unsigned int reserved16 : 16; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_PREFIXLEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_PREFIXLEN_t__ */ + +/*@}*/ + +/** @defgroup INTEN Interrupt Enable Register (INTEN) Register + * Interrupt Enable Register (INTEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_INTEN_Struct + *! \brief Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_INTEN_t__ +typedef struct _ADI_CRYPT_INTEN_t { + union { + struct { + unsigned int INRDYEN : 1; /**< Enable Input Ready Interrupt */ + unsigned int OUTRDYEN : 1; /**< Enables the Output Ready Interrupt */ + unsigned int INOVREN : 1; /**< Enable Input Overflow Interrupt */ + unsigned int reserved3 : 2; + unsigned int SHADONEN : 1; /**< Enable SHA_Done Interrupt */ + unsigned int HMACDONEEN : 1; /**< Interrupt Enable for HMAC Done */ + unsigned int HMACMSGRDYEN : 1; /**< Status Bit for HMAC Message Input Ready */ + unsigned int PRKSTRCMDONEEN : 1; /**< PRKSTOR CMD DONE INTEN */ + unsigned int reserved9 : 23; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_INTEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_INTEN_t__ */ + +/*@}*/ + +/** @defgroup STAT Status Register (STAT) Register + * Status Register (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_STAT_Struct + *! \brief Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_STAT_t__ +typedef struct _ADI_CRYPT_STAT_t { + union { + struct { + unsigned int INRDY : 1; /**< Input Buffer Status */ + unsigned int OUTRDY : 1; /**< Output Data Ready */ + unsigned int INOVR : 1; /**< Overflow in the Input Buffer */ + unsigned int reserved3 : 2; + unsigned int SHADONE : 1; /**< SHA Computation Complete */ + unsigned int SHABUSY : 1; /**< SHA Busy. in Computation */ + unsigned int INWORDS : 3; /**< Number of Words in the Input Buffer */ + unsigned int OUTWORDS : 3; /**< Number of Words in the Output Buffer */ + unsigned int HMACBUSY : 1; /**< Status Bit Indicates HMAC Busy */ + unsigned int HMACDONE : 1; /**< Status Bit Indicates HMAC Done */ + unsigned int HMACMSGRDY : 1; /**< Status Bit Indicates HMAC is Message Ready */ + unsigned int reserved16 : 7; + unsigned int PRKSTOR_CMD_DONE : 1; /**< Indicates Command Done for PrKStor */ + unsigned int PRKSTOR_CMD_FAIL : 1; /**< Indicates Last Command Issued Failed */ + unsigned int PRKSTOR_RET_STATUS : 2; /**< ECC Errors in the PRKSTOR_RETRIEVE Command */ + unsigned int CMD_ISSUED : 4; /**< Last Command Issued to PrKStor; */ + unsigned int PRKSTOR_BUSY : 1; /**< Indicates PrKSTOR is Busy */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_STAT_t__ */ + +/*@}*/ + +/** @defgroup INBUF Input Buffer (INBUF) Register + * Input Buffer (INBUF) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_INBUF_Struct + *! \brief Input Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_INBUF_t__ +typedef struct _ADI_CRYPT_INBUF_t { + union { + struct { + unsigned int VALUE : 32; /**< Input Buffer */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_INBUF_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_INBUF_t__ */ + +/*@}*/ + +/** @defgroup OUTBUF Output Buffer (OUTBUF) Register + * Output Buffer (OUTBUF) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_OUTBUF_Struct + *! \brief Output Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_OUTBUF_t__ +typedef struct _ADI_CRYPT_OUTBUF_t { + union { + struct { + unsigned int VALUE : 32; /**< Output Buffer */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_OUTBUF_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_OUTBUF_t__ */ + +/*@}*/ + +/** @defgroup NONCE0 Nonce Bits [31:0] (NONCE0) Register + * Nonce Bits [31:0] (NONCE0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_NONCE0_Struct + *! \brief Nonce Bits [31:0] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE0_t__ +typedef struct _ADI_CRYPT_NONCE0_t { + union { + struct { + unsigned int VALUE : 32; /**< Word 0: Nonce Bits [31:0] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_NONCE0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE0_t__ */ + +/*@}*/ + +/** @defgroup NONCE1 Nonce Bits [63:32] (NONCE1) Register + * Nonce Bits [63:32] (NONCE1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_NONCE1_Struct + *! \brief Nonce Bits [63:32] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE1_t__ +typedef struct _ADI_CRYPT_NONCE1_t { + union { + struct { + unsigned int VALUE : 32; /**< Word 1: Nonce Bits [63:32] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_NONCE1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE1_t__ */ + +/*@}*/ + +/** @defgroup NONCE2 Nonce Bits [95:64] (NONCE2) Register + * Nonce Bits [95:64] (NONCE2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_NONCE2_Struct + *! \brief Nonce Bits [95:64] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE2_t__ +typedef struct _ADI_CRYPT_NONCE2_t { + union { + struct { + unsigned int VALUE : 32; /**< Word 2: Nonce Bits [95:64] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_NONCE2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE2_t__ */ + +/*@}*/ + +/** @defgroup NONCE3 Nonce Bits [127:96] (NONCE3) Register + * Nonce Bits [127:96] (NONCE3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_NONCE3_Struct + *! \brief Nonce Bits [127:96] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE3_t__ +typedef struct _ADI_CRYPT_NONCE3_t { + union { + struct { + unsigned int VALUE : 32; /**< Word 3: Nonce Bits [127:96] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_NONCE3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE3_t__ */ + +/*@}*/ + +/** @defgroup AESKEY0 AES Key Bits [31:0] (AESKEY0) Register + * AES Key Bits [31:0] (AESKEY0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY0_Struct + *! \brief AES Key Bits [31:0] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY0_t__ +typedef struct _ADI_CRYPT_AESKEY0_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [3:0] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY0_t__ */ + +/*@}*/ + +/** @defgroup AESKEY1 AES Key Bits [63:32] (AESKEY1) Register + * AES Key Bits [63:32] (AESKEY1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY1_Struct + *! \brief AES Key Bits [63:32] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY1_t__ +typedef struct _ADI_CRYPT_AESKEY1_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [7:4] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY1_t__ */ + +/*@}*/ + +/** @defgroup AESKEY2 AES Key Bits [95:64] (AESKEY2) Register + * AES Key Bits [95:64] (AESKEY2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY2_Struct + *! \brief AES Key Bits [95:64] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY2_t__ +typedef struct _ADI_CRYPT_AESKEY2_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [11:8] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY2_t__ */ + +/*@}*/ + +/** @defgroup AESKEY3 AES Key Bits [127:96] (AESKEY3) Register + * AES Key Bits [127:96] (AESKEY3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY3_Struct + *! \brief AES Key Bits [127:96] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY3_t__ +typedef struct _ADI_CRYPT_AESKEY3_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [15:12] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY3_t__ */ + +/*@}*/ + +/** @defgroup AESKEY4 AES Key Bits [159:128] (AESKEY4) Register + * AES Key Bits [159:128] (AESKEY4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY4_Struct + *! \brief AES Key Bits [159:128] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY4_t__ +typedef struct _ADI_CRYPT_AESKEY4_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [19:16] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY4_t__ */ + +/*@}*/ + +/** @defgroup AESKEY5 AES Key Bits [191:160] (AESKEY5) Register + * AES Key Bits [191:160] (AESKEY5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY5_Struct + *! \brief AES Key Bits [191:160] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY5_t__ +typedef struct _ADI_CRYPT_AESKEY5_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [23:20] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY5_t__ */ + +/*@}*/ + +/** @defgroup AESKEY6 AES Key Bits [223:192] (AESKEY6) Register + * AES Key Bits [223:192] (AESKEY6) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY6_Struct + *! \brief AES Key Bits [223:192] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY6_t__ +typedef struct _ADI_CRYPT_AESKEY6_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [27:24] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY6_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY6_t__ */ + +/*@}*/ + +/** @defgroup AESKEY7 AES Key Bits [255:224] (AESKEY7) Register + * AES Key Bits [255:224] (AESKEY7) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY7_Struct + *! \brief AES Key Bits [255:224] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY7_t__ +typedef struct _ADI_CRYPT_AESKEY7_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [31:28] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY7_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY7_t__ */ + +/*@}*/ + +/** @defgroup CNTRINIT Counter Initialization Vector (CNTRINIT) Register + * Counter Initialization Vector (CNTRINIT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_CNTRINIT_Struct + *! \brief Counter Initialization Vector Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_CNTRINIT_t__ +typedef struct _ADI_CRYPT_CNTRINIT_t { + union { + struct { + unsigned int VALUE : 20; /**< Counter Initialization Value */ + unsigned int reserved20 : 12; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_CNTRINIT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_CNTRINIT_t__ */ + +/*@}*/ + +/** @defgroup SHAH0 SHA Bits [31:0] (SHAH0) Register + * SHA Bits [31:0] (SHAH0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH0_Struct + *! \brief SHA Bits [31:0] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH0_t__ +typedef struct _ADI_CRYPT_SHAH0_t { + union { + struct { + unsigned int SHAHASH0 : 32; /**< Word 0: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH0_t__ */ + +/*@}*/ + +/** @defgroup SHAH1 SHA Bits [63:32] (SHAH1) Register + * SHA Bits [63:32] (SHAH1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH1_Struct + *! \brief SHA Bits [63:32] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH1_t__ +typedef struct _ADI_CRYPT_SHAH1_t { + union { + struct { + unsigned int SHAHASH1 : 32; /**< Word 1: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH1_t__ */ + +/*@}*/ + +/** @defgroup SHAH2 SHA Bits [95:64] (SHAH2) Register + * SHA Bits [95:64] (SHAH2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH2_Struct + *! \brief SHA Bits [95:64] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH2_t__ +typedef struct _ADI_CRYPT_SHAH2_t { + union { + struct { + unsigned int SHAHASH2 : 32; /**< Word 2: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH2_t__ */ + +/*@}*/ + +/** @defgroup SHAH3 SHA Bits [127:96] (SHAH3) Register + * SHA Bits [127:96] (SHAH3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH3_Struct + *! \brief SHA Bits [127:96] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH3_t__ +typedef struct _ADI_CRYPT_SHAH3_t { + union { + struct { + unsigned int SHAHASH3 : 32; /**< Word 3: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH3_t__ */ + +/*@}*/ + +/** @defgroup SHAH4 SHA Bits [159:128] (SHAH4) Register + * SHA Bits [159:128] (SHAH4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH4_Struct + *! \brief SHA Bits [159:128] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH4_t__ +typedef struct _ADI_CRYPT_SHAH4_t { + union { + struct { + unsigned int SHAHASH4 : 32; /**< Word 4: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH4_t__ */ + +/*@}*/ + +/** @defgroup SHAH5 SHA Bits [191:160] (SHAH5) Register + * SHA Bits [191:160] (SHAH5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH5_Struct + *! \brief SHA Bits [191:160] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH5_t__ +typedef struct _ADI_CRYPT_SHAH5_t { + union { + struct { + unsigned int SHAHASH5 : 32; /**< Word 5: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH5_t__ */ + +/*@}*/ + +/** @defgroup SHAH6 SHA Bits [223:192] (SHAH6) Register + * SHA Bits [223:192] (SHAH6) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH6_Struct + *! \brief SHA Bits [223:192] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH6_t__ +typedef struct _ADI_CRYPT_SHAH6_t { + union { + struct { + unsigned int SHAHASH6 : 32; /**< Word 6: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH6_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH6_t__ */ + +/*@}*/ + +/** @defgroup SHAH7 SHA Bits [255:224] (SHAH7) Register + * SHA Bits [255:224] (SHAH7) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH7_Struct + *! \brief SHA Bits [255:224] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH7_t__ +typedef struct _ADI_CRYPT_SHAH7_t { + union { + struct { + unsigned int SHAHASH7 : 32; /**< Word 7: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH7_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH7_t__ */ + +/*@}*/ + +/** @defgroup SHA_LAST_WORD SHA Last Word and Valid Bits Information (SHA_LAST_WORD) Register + * SHA Last Word and Valid Bits Information (SHA_LAST_WORD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHA_LAST_WORD_Struct + *! \brief SHA Last Word and Valid Bits Information Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHA_LAST_WORD_t__ +typedef struct _ADI_CRYPT_SHA_LAST_WORD_t { + union { + struct { + unsigned int O_Last_Word : 1; /**< Last SHA Input Word */ + unsigned int O_Bits_Valid : 5; /**< Bits Valid in SHA Last Word Input */ + unsigned int reserved6 : 26; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHA_LAST_WORD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHA_LAST_WORD_t__ */ + +/*@}*/ + +/** @defgroup CCM_NUM_VALID_BYTES NUM_VALID_BYTES (CCM_NUM_VALID_BYTES) Register + * NUM_VALID_BYTES (CCM_NUM_VALID_BYTES) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_CCM_NUM_VALID_BYTES_Struct + *! \brief NUM_VALID_BYTES Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_CCM_NUM_VALID_BYTES_t__ +typedef struct _ADI_CRYPT_CCM_NUM_VALID_BYTES_t { + union { + struct { + unsigned int NUM_VALID_BYTES : 4; /**< Number of Valid Bytes in CCM Last Data */ + unsigned int reserved4 : 28; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_CCM_NUM_VALID_BYTES_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_CCM_NUM_VALID_BYTES_t__ */ + +/*@}*/ + +/** @defgroup PRKSTORCFG PRKSTOR Configuration (PRKSTORCFG) Register + * PRKSTOR Configuration (PRKSTORCFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_PRKSTORCFG_Struct + *! \brief PRKSTOR Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_PRKSTORCFG_t__ +typedef struct _ADI_CRYPT_PRKSTORCFG_t { + union { + struct { + unsigned int KEY_INDEX : 7; /**< Index of Key in PRKSTOR */ + unsigned int CMD : 4; /**< Command Input for PRKSTOR */ + unsigned int reserved11 : 21; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_PRKSTORCFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_PRKSTORCFG_t__ */ + +/*@}*/ + +/** @defgroup KUW0 Key Wrap Unwrap Register 0 (KUW0) Register + * Key Wrap Unwrap Register 0 (KUW0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW0_Struct + *! \brief Key Wrap Unwrap Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW0_t__ +typedef struct _ADI_CRYPT_KUW0_t { + union { + struct { + unsigned int KUW0 : 32; /**< KUW [31:0] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW0_t__ */ + +/*@}*/ + +/** @defgroup KUW1 Key Wrap Unwrap Register 1 (KUW1) Register + * Key Wrap Unwrap Register 1 (KUW1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW1_Struct + *! \brief Key Wrap Unwrap Register 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW1_t__ +typedef struct _ADI_CRYPT_KUW1_t { + union { + struct { + unsigned int KUW1 : 32; /**< KUW [63:32] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW1_t__ */ + +/*@}*/ + +/** @defgroup KUW2 Key Wrap Unwrap Register 2 (KUW2) Register + * Key Wrap Unwrap Register 2 (KUW2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW2_Struct + *! \brief Key Wrap Unwrap Register 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW2_t__ +typedef struct _ADI_CRYPT_KUW2_t { + union { + struct { + unsigned int KUW2 : 32; /**< KUW [95:64] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW2_t__ */ + +/*@}*/ + +/** @defgroup KUW3 Key Wrap Unwrap Register 3 (KUW3) Register + * Key Wrap Unwrap Register 3 (KUW3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW3_Struct + *! \brief Key Wrap Unwrap Register 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW3_t__ +typedef struct _ADI_CRYPT_KUW3_t { + union { + struct { + unsigned int KUW3 : 32; /**< KUW [127:96] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW3_t__ */ + +/*@}*/ + +/** @defgroup KUW4 Key Wrap Unwrap Register 4 (KUW4) Register + * Key Wrap Unwrap Register 4 (KUW4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW4_Struct + *! \brief Key Wrap Unwrap Register 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW4_t__ +typedef struct _ADI_CRYPT_KUW4_t { + union { + struct { + unsigned int KUW4 : 32; /**< KUW [159:128] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW4_t__ */ + +/*@}*/ + +/** @defgroup KUW5 Key Wrap Unwrap Register 5 (KUW5) Register + * Key Wrap Unwrap Register 5 (KUW5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW5_Struct + *! \brief Key Wrap Unwrap Register 5 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW5_t__ +typedef struct _ADI_CRYPT_KUW5_t { + union { + struct { + unsigned int KUW5 : 32; /**< KUW [191:160] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW5_t__ */ + +/*@}*/ + +/** @defgroup KUW6 Key Wrap Unwrap Register 6 (KUW6) Register + * Key Wrap Unwrap Register 6 (KUW6) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW6_Struct + *! \brief Key Wrap Unwrap Register 6 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW6_t__ +typedef struct _ADI_CRYPT_KUW6_t { + union { + struct { + unsigned int KUW6 : 32; /**< KUW [223:192] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW6_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW6_t__ */ + +/*@}*/ + +/** @defgroup KUW7 Key Wrap Unwrap Register 7 (KUW7) Register + * Key Wrap Unwrap Register 7 (KUW7) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW7_Struct + *! \brief Key Wrap Unwrap Register 7 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW7_t__ +typedef struct _ADI_CRYPT_KUW7_t { + union { + struct { + unsigned int KUW7 : 32; /**< KUW [255:224] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW7_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW7_t__ */ + +/*@}*/ + +/** @defgroup KUW8 Key Wrap Unwrap Register 8 (KUW8) Register + * Key Wrap Unwrap Register 8 (KUW8) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW8_Struct + *! \brief Key Wrap Unwrap Register 8 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW8_t__ +typedef struct _ADI_CRYPT_KUW8_t { + union { + struct { + unsigned int KUW8 : 32; /**< KUW [287:256] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW8_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW8_t__ */ + +/*@}*/ + +/** @defgroup KUW9 Key Wrap Unwrap Register 9 (KUW9) Register + * Key Wrap Unwrap Register 9 (KUW9) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW9_Struct + *! \brief Key Wrap Unwrap Register 9 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW9_t__ +typedef struct _ADI_CRYPT_KUW9_t { + union { + struct { + unsigned int KUW9 : 32; /**< KUW [319:288] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW9_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW9_t__ */ + +/*@}*/ + +/** @defgroup KUW10 Key Wrap Unwrap Register 10 (KUW10) Register + * Key Wrap Unwrap Register 10 (KUW10) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW10_Struct + *! \brief Key Wrap Unwrap Register 10 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW10_t__ +typedef struct _ADI_CRYPT_KUW10_t { + union { + struct { + unsigned int KUW10 : 32; /**< KUW [351:320] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW10_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW10_t__ */ + +/*@}*/ + +/** @defgroup KUW11 Key Wrap Unwrap Register 11 (KUW11) Register + * Key Wrap Unwrap Register 11 (KUW11) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW11_Struct + *! \brief Key Wrap Unwrap Register 11 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW11_t__ +typedef struct _ADI_CRYPT_KUW11_t { + union { + struct { + unsigned int KUW11 : 32; /**< KUW [383:352] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW11_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW11_t__ */ + +/*@}*/ + +/** @defgroup KUW12 Key Wrap Unwrap Register 12 (KUW12) Register + * Key Wrap Unwrap Register 12 (KUW12) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW12_Struct + *! \brief Key Wrap Unwrap Register 12 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW12_t__ +typedef struct _ADI_CRYPT_KUW12_t { + union { + struct { + unsigned int KUW12 : 32; /**< KUW [415:384] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW12_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW12_t__ */ + +/*@}*/ + +/** @defgroup KUW13 Key Wrap Unwrap Register 13 (KUW13) Register + * Key Wrap Unwrap Register 13 (KUW13) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW13_Struct + *! \brief Key Wrap Unwrap Register 13 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW13_t__ +typedef struct _ADI_CRYPT_KUW13_t { + union { + struct { + unsigned int KUW13 : 32; /**< KUW [447:416] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW13_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW13_t__ */ + +/*@}*/ + +/** @defgroup KUW14 Key Wrap Unwrap Register 14 (KUW14) Register + * Key Wrap Unwrap Register 14 (KUW14) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW14_Struct + *! \brief Key Wrap Unwrap Register 14 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW14_t__ +typedef struct _ADI_CRYPT_KUW14_t { + union { + struct { + unsigned int KUW14 : 32; /**< KUW [479:448] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW14_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW14_t__ */ + +/*@}*/ + +/** @defgroup KUW15 Key Wrap Unwrap Register 15 (KUW15) Register + * Key Wrap Unwrap Register 15 (KUW15) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW15_Struct + *! \brief Key Wrap Unwrap Register 15 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW15_t__ +typedef struct _ADI_CRYPT_KUW15_t { + union { + struct { + unsigned int KUW15 : 32; /**< KUW [511:480] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW15_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW15_t__ */ + +/*@}*/ + +/** @defgroup KUWValStr1 Key Wrap Unwrap Validation String [63:32] (KUWValStr1) Register + * Key Wrap Unwrap Validation String [63:32] (KUWValStr1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUWValStr1_Struct + *! \brief Key Wrap Unwrap Validation String [63:32] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUWValStr1_t__ +typedef struct _ADI_CRYPT_KUWValStr1_t { + union { + struct { + unsigned int InitalValue0 : 32; /**< Initial Value */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUWValStr1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUWValStr1_t__ */ + +/*@}*/ + +/** @defgroup KUWValStr2 Key Wrap Unwrap Validation String [31:0] (KUWValStr2) Register + * Key Wrap Unwrap Validation String [31:0] (KUWValStr2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUWValStr2_Struct + *! \brief Key Wrap Unwrap Validation String [31:0] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUWValStr2_t__ +typedef struct _ADI_CRYPT_KUWValStr2_t { + union { + struct { + unsigned int InitialValue1 : 32; /**< Initial Value */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUWValStr2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUWValStr2_t__ */ + +/*@}*/ + +/** @defgroup IEN Power Supply Monitor Interrupt Enable (IEN) Register + * Power Supply Monitor Interrupt Enable (IEN) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_PMG_IEN_RANGEBAT + *! \brief Battery Monitor Range (RANGEBAT) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_IEN_REGION1 = 0, /**< Configure to generate interrupt if VBAT in Region1 */ + PMG_IEN_REGION2 = 1, /**< Configure to generate interrupt if VBAT in Region2 */ + PMG_IEN_REGION3 = 2, /**< Configure to generate interrupt if VBAT in Region3 */ + PMG_IEN_NA = 3 /**< NA */ +} ADI_PMG_IEN_RANGEBAT; + + +/* ========================================================================== + *! \struct ADI_PMG_IEN_Struct + *! \brief Power Supply Monitor Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_IEN_t__ +typedef struct _ADI_PMG_IEN_t { + union { + struct { + unsigned int VBAT : 1; /**< Enable Interrupt for VBAT */ + unsigned int VREGUNDR : 1; /**< Enable Interrupt when VREG under-voltage (below 1 V) */ + unsigned int VREGOVR : 1; /**< Enable Interrupt when VREG over-voltage (above 1.32 V) */ + unsigned int reserved3 : 5; + unsigned int RANGEBAT : 2; /**< Battery Monitor Range */ + unsigned int IENBAT : 1; /**< Interrupt enable for VBAT range */ + unsigned int reserved11 : 21; + }; + uint32_t VALUE32; + }; +} ADI_PMG_IEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_IEN_t__ */ + +/*@}*/ + +/** @defgroup PSM_STAT Power Supply Monitor Status (PSM_STAT) Register + * Power Supply Monitor Status (PSM_STAT) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_PMG_PSM_STAT_RORANGE1 + *! \brief VBAT range1 (RORANGE1) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_PSM_STAT_BATSTAT1 = 0, /**< VBAT NOT in the range specified */ + PMG_PSM_STAT_BATSTAT0 = 1 /**< VBAT in the range specified */ +} ADI_PMG_PSM_STAT_RORANGE1; + + +/* ========================================================================== + *! \struct ADI_PMG_PSM_STAT_Struct + *! \brief Power Supply Monitor Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_PSM_STAT_t__ +typedef struct _ADI_PMG_PSM_STAT_t { + union { + struct { + unsigned int VBATUNDR : 1; /**< Status bit indicating an Alarm that battery is below 1.8 V */ + unsigned int VREGUNDR : 1; /**< Status bit for Alarm indicating VREG is below 1 V */ + unsigned int VREGOVR : 1; /**< Status bit for alarm indicating Over Voltage for VREG */ + unsigned int reserved3 : 4; + unsigned int WICENACK : 1; /**< WIC Enable Acknowledge from Cortex */ + unsigned int RANGE1 : 1; /**< VBAT range1 */ + unsigned int RANGE2 : 1; /**< VBAT range2 */ + unsigned int RANGE3 : 1; /**< VBAT range3 */ + unsigned int reserved11 : 2; + unsigned int RORANGE1 : 1; /**< VBAT range1 */ + unsigned int RORANGE2 : 1; /**< VBAT range2 */ + unsigned int RORANGE3 : 1; /**< VBAT range3 */ + unsigned int reserved16 : 16; + }; + uint32_t VALUE32; + }; +} ADI_PMG_PSM_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_PSM_STAT_t__ */ + +/*@}*/ + +/** @defgroup PWRMOD Power Mode Register (PWRMOD) Register + * Power Mode Register (PWRMOD) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_PMG_PWRMOD_MODE + *! \brief Power Mode Bits (MODE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_PWRMOD_FLEXI = 0, /**< Flexi Mode */ + PMG_PWRMOD_HIBERNATE = 2, /**< Hibernate Mode */ + PMG_PWRMOD_SHUTDOWN = 3 /**< Shutdown Mode */ +} ADI_PMG_PWRMOD_MODE; + + +/* ========================================================================== + *! \struct ADI_PMG_PWRMOD_Struct + *! \brief Power Mode Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_PWRMOD_t__ +typedef struct _ADI_PMG_PWRMOD_t { + union { + struct { + unsigned int MODE : 2; /**< Power Mode Bits */ + unsigned int reserved2 : 1; + unsigned int MONVBATN : 1; /**< Monitor VBAT during Hibernate Mode. Monitors VBAT by default */ + unsigned int reserved4 : 28; + }; + uint32_t VALUE32; + }; +} ADI_PMG_PWRMOD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_PWRMOD_t__ */ + +/*@}*/ + +/** @defgroup PWRKEY Key Protection for PWRMOD and SRAMRET (PWRKEY) Register + * Key Protection for PWRMOD and SRAMRET (PWRKEY) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_PWRKEY_Struct + *! \brief Key Protection for PWRMOD and SRAMRET Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_PWRKEY_t__ +typedef struct _ADI_PMG_PWRKEY_t { + union { + struct { + unsigned int VALUE : 16; /**< Power Control Key */ + unsigned int reserved16 : 16; + }; + uint32_t VALUE32; + }; +} ADI_PMG_PWRKEY_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_PWRKEY_t__ */ + +/*@}*/ + +/** @defgroup SHDN_STAT Shutdown Status Register (SHDN_STAT) Register + * Shutdown Status Register (SHDN_STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_SHDN_STAT_Struct + *! \brief Shutdown Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_SHDN_STAT_t__ +typedef struct _ADI_PMG_SHDN_STAT_t { + union { + struct { + unsigned int EXTINT0 : 1; /**< Interrupt from External Interrupt 0 */ + unsigned int EXTINT1 : 1; /**< Interrupt from External Interrupt 1 */ + unsigned int EXTINT2 : 1; /**< Interrupt from External Interrupt 2 */ + unsigned int RTC : 1; /**< Interrupt from RTC */ + unsigned int reserved4 : 28; + }; + uint32_t VALUE32; + }; +} ADI_PMG_SHDN_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_SHDN_STAT_t__ */ + +/*@}*/ + +/** @defgroup SRAMRET Control for Retention SRAM in Hibernate Mode (SRAMRET) Register + * Control for Retention SRAM in Hibernate Mode (SRAMRET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_SRAMRET_Struct + *! \brief Control for Retention SRAM in Hibernate Mode Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_SRAMRET_t__ +typedef struct _ADI_PMG_SRAMRET_t { + union { + struct { + unsigned int RET1 : 1; /**< Enable retention bank 1 (12 KB) */ + unsigned int RET2 : 1; /**< Enable retention bank 3 and bank 4 (32 KB) */ + unsigned int reserved2 : 6; + unsigned int RET3 : 1; /**< Enable retention bank 5 (32 KB) */ + unsigned int RET4 : 1; /**< Enable retention bank 6 and bank 7 (32 KB) */ + unsigned int reserved10 : 13; + unsigned int HIBERNATE_SRAM_LOAD_MODE : 1; /**< Hibernate mode SRAM load mode control */ + unsigned int reserved24 : 8; + }; + uint32_t VALUE32; + }; +} ADI_PMG_SRAMRET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_SRAMRET_t__ */ + +/*@}*/ + +/** @defgroup TRIM Trimming Bits (TRIM) Register + * Trimming Bits (TRIM) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_PMG_TRIM_hibernate_load_mode + *! \brief Hibernate mode load mode control (hibernate_load_mode) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_TRIM_HIGH_LOAD = 0, /**< High hibernate load */ + PMG_TRIM_LOW_LOAD = 7 /**< Low hibernate load */ +} ADI_PMG_TRIM_hibernate_load_mode; + + +/* ========================================================================== + *! \struct ADI_PMG_TRIM_Struct + *! \brief Trimming Bits Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TRIM_t__ +typedef struct _ADI_PMG_TRIM_t { + union { + struct { + unsigned int reserved0 : 29; + unsigned int hibernate_load_mode : 3; /**< Hibernate mode load mode control */ + }; + uint32_t VALUE32; + }; +} ADI_PMG_TRIM_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TRIM_t__ */ + +/*@}*/ + +/** @defgroup RST_STAT Reset Status (RST_STAT) Register + * Reset Status (RST_STAT) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_PMG_RST_STAT_PORSRC + *! \brief Power on reset Source (PORSRC) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_RST_STAT_FAILSAFE_HV = 0, /**< POR triggered because VBAT drops below Fail Safe */ + PMG_RST_STAT_RST_VBAT = 1, /**< POR trigger because VBAT supply (VBAT < 1.7 V) */ + PMG_RST_STAT_RST_VREG = 2, /**< POR triggered because VDD supply (VDD < 1.08 V) */ + PMG_RST_STAT_FAILSAFE_LV = 3 /**< POR triggered because VREG drops below Fail Safe */ +} ADI_PMG_RST_STAT_PORSRC; + + +/* ========================================================================== + *! \struct ADI_PMG_RST_STAT_Struct + *! \brief Reset Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_RST_STAT_t__ +typedef struct _ADI_PMG_RST_STAT_t { + union { + struct { + unsigned int POR : 1; /**< Power-on reset */ + unsigned int EXTRST : 1; /**< External reset */ + unsigned int WDRST : 1; /**< Watchdog timeout */ + unsigned int SWRST : 1; /**< Software reset */ + unsigned int PORSRC : 2; /**< Power on reset Source */ + unsigned int reserved6 : 26; + }; + uint32_t VALUE32; + }; +} ADI_PMG_RST_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_RST_STAT_t__ */ + +/*@}*/ + +/** @defgroup CTL1 HPBUCK Control (CTL1) Register + * HPBUCK Control (CTL1) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_PMG_CTL1_HPBUCK_LD_MODE + *! \brief HP Buck load mode (HPBUCK_LD_MODE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_CTL1_HPBUCKLOWLOAD = 0, /**< HPBUCK Low load mode is enabled */ + PMG_CTL1_HPBUCKHIGHLOAD = 1 /**< HPBUCK High load mode is enabled */ +} ADI_PMG_CTL1_HPBUCK_LD_MODE; + + +/* ========================================================================= + *! \enum ADI_PMG_CTL1_HPBUCK_LOWPWR_MODE + *! \brief HP Buck low power mode (HPBUCK_LOWPWR_MODE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_CTL1_LOWPWRDISABLE = 0, /**< HPBUCK Low power mode is disabled */ + PMG_CTL1_LOWPWRENABLE = 1 /**< HPBUCK Low power mode is enabled */ +} ADI_PMG_CTL1_HPBUCK_LOWPWR_MODE; + + +/* ========================================================================== + *! \struct ADI_PMG_CTL1_Struct + *! \brief HPBUCK Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_CTL1_t__ +typedef struct _ADI_PMG_CTL1_t { + union { + struct { + unsigned int HPBUCKEN : 1; /**< Enable HP Buck */ + unsigned int HPBUCK_LD_MODE : 1; /**< HP Buck load mode */ + unsigned int HPBUCK_LOWPWR_MODE : 1; /**< HP Buck low power mode */ + unsigned int reserved3 : 29; + }; + uint32_t VALUE32; + }; +} ADI_PMG_CTL1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_CTL1_t__ */ + +/*@}*/ + +/** @defgroup CFG0 External Interrupt configuration (CFG0) Register + * External Interrupt configuration (CFG0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_XINT_CFG0_Struct + *! \brief External Interrupt configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_CFG0_t__ +typedef struct _ADI_XINT_CFG0_t { + union { + struct { + unsigned int IRQ0MDE : 3; /**< External Interrupt 0 Mode registers */ + unsigned int IRQ0EN : 1; /**< External Interrupt 0 Enable bit */ + unsigned int IRQ1MDE : 3; /**< External Interrupt 1 Mode registers */ + unsigned int IRQ1EN : 1; /**< External Interrupt 1 Enable bit */ + unsigned int IRQ2MDE : 3; /**< External Interrupt 2 Mode registers */ + unsigned int IRQ2EN : 1; /**< External Interrupt 2 Enable bit */ + unsigned int IRQ3MDE : 3; /**< External Interrupt 3 Mode registers */ + unsigned int IRQ3EN : 1; /**< External Interrupt 3 enable bit */ + unsigned int reserved16 : 4; + unsigned int UART_RX_EN : 1; /**< External Interrupt using SIP_UPDATE enable bit */ + unsigned int UART_RX_MDE : 3; /**< External Interrupt using UART_RX wakeup Mode registers */ + unsigned int reserved24 : 8; + }; + uint32_t VALUE32; + }; +} ADI_XINT_CFG0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_CFG0_t__ */ + +/*@}*/ + +/** @defgroup EXT_STAT External Wakeup Interrupt Status register (EXT_STAT) Register + * External Wakeup Interrupt Status register (EXT_STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_XINT_EXT_STAT_Struct + *! \brief External Wakeup Interrupt Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_EXT_STAT_t__ +typedef struct _ADI_XINT_EXT_STAT_t { + union { + struct { + unsigned int STAT_EXTINT0 : 1; /**< Interrupt status bit for External Interrupt 0 */ + unsigned int STAT_EXTINT1 : 1; /**< Interrupt status bit for External Interrupt 1 */ + unsigned int STAT_EXTINT2 : 1; /**< Interrupt status bit for External Interrupt 2 */ + unsigned int STAT_EXTINT3 : 1; /**< Interrupt status bit for External Interrupt 3 */ + unsigned int reserved4 : 1; + unsigned int STAT_UART_RXWKUP : 1; /**< Interrupt status bit for UART RX WAKEUP interrupt */ + unsigned int reserved6 : 26; + }; + uint32_t VALUE32; + }; +} ADI_XINT_EXT_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_EXT_STAT_t__ */ + +/*@}*/ + +/** @defgroup CLR External Interrupt clear (CLR) Register + * External Interrupt clear (CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_XINT_CLR_Struct + *! \brief External Interrupt clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_CLR_t__ +typedef struct _ADI_XINT_CLR_t { + union { + struct { + unsigned int IRQ0 : 1; /**< External interrupt 0 */ + unsigned int IRQ1 : 1; /**< External interrupt 1 */ + unsigned int IRQ2 : 1; /**< External interrupt 2 */ + unsigned int IRQ3 : 1; /**< External interrupt 3 */ + unsigned int reserved4 : 1; + unsigned int UART_RX_CLR : 1; /**< External interrupt Clear for UART_RX WAKEUP interrupt */ + unsigned int reserved6 : 26; + }; + uint32_t VALUE32; + }; +} ADI_XINT_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_CLR_t__ */ + +/*@}*/ + +/** @defgroup NMICLR Non-maskable interrupt clear (NMICLR) Register + * Non-maskable interrupt clear (NMICLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_XINT_NMICLR_Struct + *! \brief Non-maskable interrupt clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_NMICLR_t__ +typedef struct _ADI_XINT_NMICLR_t { + union { + struct { + unsigned int CLR : 1; /**< NMI clear */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_XINT_NMICLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_NMICLR_t__ */ + +/*@}*/ + +/** @defgroup KEY Key Protection for OSCCTRL (KEY) Register + * Key Protection for OSCCTRL (KEY) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_OSC_KEY_Struct + *! \brief Key Protection for OSCCTRL Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_KEY_t__ +typedef struct _ADI_CLKG_OSC_KEY_t { + union { + struct { + unsigned int VALUE : 16; /**< Oscillator key */ + unsigned int reserved16 : 16; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_OSC_KEY_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_KEY_t__ */ + +/*@}*/ + +/** @defgroup CTL Oscillator Control (CTL) Register + * Oscillator Control (CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_OSC_CTL_Struct + *! \brief Oscillator Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_CTL_t__ +typedef struct _ADI_CLKG_OSC_CTL_t { + union { + struct { + unsigned int LFCLK_MUX : 1; /**< 32 kHz clock select mux */ + unsigned int HFOSC_EN : 1; /**< High frequency internal oscillator enable */ + unsigned int LFX_EN : 1; /**< Low frequency crystal oscillator enable */ + unsigned int HFX_EN : 1; /**< High frequency crystal oscillator enable */ + unsigned int LFX_BYP : 1; /**< Low frequency crystal oscillator Bypass */ + unsigned int LFX_MON_EN : 1; /**< LFXTAL clock monitor and Clock FAIL interrupt enable */ + unsigned int reserved6 : 2; + unsigned int LFOSC_OK : 1; /**< Status of LFOSC oscillator */ + unsigned int HFOSC_OK : 1; /**< Status of HFOSC oscillator */ + unsigned int LFX_OK : 1; /**< Status of LFXTAL oscillator */ + unsigned int HFX_OK : 1; /**< Status of HFXTAL oscillator */ + unsigned int LFX_AUTSW_EN : 1; /**< Enables automatic Switching of the LF Mux to LFOSC on LFXTAL Failure */ + unsigned int LFX_AUTSW_STA : 1; /**< Status of automatic switching of the LF Mux to LFOSC upon detection of LFXTAL failure */ + unsigned int LFX_ROBUST_EN : 1; /**< LFXTAL Mode select */ + unsigned int LFX_ROBUST_LD : 2; /**< LFXTAL Robust Mode Load select */ + unsigned int reserved17 : 3; + unsigned int ROOT_MON_EN : 1; /**< ROOT clock monitor and Clock FAIL interrupt enable */ + unsigned int ROOT_AUTSW_EN : 1; /**< Enables automatic Switching of the Root clock to HFOSC on Root clock Failure */ + unsigned int ROOT_AUTSW_STA : 1; /**< Status of automatic switching of the Root clock to HFOSC upon detection of Root clock failure */ + unsigned int reserved23 : 7; + unsigned int ROOT_FAIL_STA : 1; /**< Root clock (crystal clock) Not Stable */ + unsigned int LFX_FAIL_STA : 1; /**< LF XTAL (crystal clock) Not Stable */ + }; + uint32_t VALUE32; + }; +} ADI_CLKG_OSC_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_CTL_t__ */ + +/*@}*/ + +/** @defgroup SRAM_CTL Control for SRAM Parity and Instruction SRAM (SRAM_CTL) Register + * Control for SRAM Parity and Instruction SRAM (SRAM_CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_TST_SRAM_CTL_Struct + *! \brief Control for SRAM Parity and Instruction SRAM Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_CTL_t__ +typedef struct _ADI_PMG_TST_SRAM_CTL_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int BNK1EN : 1; /**< Enable initialization */ + unsigned int BNK2EN : 1; /**< Enable initialization */ + unsigned int reserved3 : 4; + unsigned int BNK7EN : 1; /**< Enable initialization */ + unsigned int reserved8 : 5; + unsigned int STARTINIT : 1; /**< Write one to trigger initialization. Self-cleared */ + unsigned int AUTOINIT : 1; /**< Automatic initialization on wake up from hibernate mode */ + unsigned int ABTINIT : 1; /**< Abort current initialization. Self-cleared */ + unsigned int PENBNK0 : 1; /**< Enable parity check */ + unsigned int PENBNK1 : 1; /**< Enable parity check */ + unsigned int PENBNK2 : 1; /**< Enable parity check */ + unsigned int PENBNK3 : 1; /**< Enable parity check */ + unsigned int PENBNK4 : 1; /**< Enable parity check */ + unsigned int PENBNK5 : 1; /**< Enable parity check */ + unsigned int PENBNK6 : 1; /**< Enable parity check */ + unsigned int PENBNK7 : 1; /**< Enable parity check */ + unsigned int reserved24 : 7; + unsigned int INSTREN : 1; /**< Enables 32 KB instruction SRAM */ + }; + uint32_t VALUE32; + }; +} ADI_PMG_TST_SRAM_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_CTL_t__ */ + +/*@}*/ + +/** @defgroup SRAM_INITSTAT Initialization Status Register (SRAM_INITSTAT) Register + * Initialization Status Register (SRAM_INITSTAT) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_PMG_TST_SRAM_INITSTAT_BNK0DONE + *! \brief Bank 0 initialization status (BNK0DONE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_TST_SRAM_INITSTAT_NO_BANK0_INIT = 0, /**< Bank 0 not initialized */ + PMG_TST_SRAM_INITSTAT_BANK0_INIT = 1 /**< Bank 0 initialized */ +} ADI_PMG_TST_SRAM_INITSTAT_BNK0DONE; + + +/* ========================================================================= + *! \enum ADI_PMG_TST_SRAM_INITSTAT_BNK1DONE + *! \brief Bank 1 initialization status (BNK1DONE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_TST_SRAM_INITSTAT_NO_BANK1_INIT = 0, /**< Bank 1 not initialized */ + PMG_TST_SRAM_INITSTAT_BANK1_INIT = 1 /**< Bank 1 initialized */ +} ADI_PMG_TST_SRAM_INITSTAT_BNK1DONE; + + +/* ========================================================================= + *! \enum ADI_PMG_TST_SRAM_INITSTAT_BNK2DONE + *! \brief Bank 2 initialization status (BNK2DONE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_TST_SRAM_INITSTAT_NO_BANK2_INIT = 0, /**< Bank 2 not initialized */ + PMG_TST_SRAM_INITSTAT_BANK2_INIT = 1 /**< Bank 2 initialized */ +} ADI_PMG_TST_SRAM_INITSTAT_BNK2DONE; + + +/* ========================================================================= + *! \enum ADI_PMG_TST_SRAM_INITSTAT_BNK3DONE + *! \brief Bank 3 initialization status (BNK3DONE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_TST_SRAM_INITSTAT_NO_BANK3_INIT = 0, /**< Bank 3 not initialized */ + PMG_TST_SRAM_INITSTAT_BANK3_INIT = 1 /**< Bank 3 initialized */ +} ADI_PMG_TST_SRAM_INITSTAT_BNK3DONE; + + +/* ========================================================================= + *! \enum ADI_PMG_TST_SRAM_INITSTAT_BNK4DONE + *! \brief Bank 4 initialization status (BNK4DONE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_TST_SRAM_INITSTAT_NO_BANK4_INIT = 0, /**< Bank 4 not initialized */ + PMG_TST_SRAM_INITSTAT_BANK4_INIT = 1 /**< Bank 4 initialized */ +} ADI_PMG_TST_SRAM_INITSTAT_BNK4DONE; + + +/* ========================================================================= + *! \enum ADI_PMG_TST_SRAM_INITSTAT_BNK5DONE + *! \brief Bank 5 initialization status (BNK5DONE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_TST_SRAM_INITSTAT_NO_BANK5_INIT = 0, /**< Bank 5 not initialized */ + PMG_TST_SRAM_INITSTAT_BANK5_INIT = 1 /**< Bank 5 initialized */ +} ADI_PMG_TST_SRAM_INITSTAT_BNK5DONE; + + +/* ========================================================================= + *! \enum ADI_PMG_TST_SRAM_INITSTAT_BNK6DONE + *! \brief Bank 6 initialization status (BNK6DONE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_TST_SRAM_INITSTAT_NO_BANK6_INIT = 0, /**< Bank 6 not initialized */ + PMG_TST_SRAM_INITSTAT_BANK6_INIT = 1 /**< Bank 6 initialized */ +} ADI_PMG_TST_SRAM_INITSTAT_BNK6DONE; + + +/* ========================================================================= + *! \enum ADI_PMG_TST_SRAM_INITSTAT_BNK7DONE + *! \brief Bank 7 initialization status (BNK7DONE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_TST_SRAM_INITSTAT_NO_BANK7_INIT = 0, /**< Bank 7 not initialized */ + PMG_TST_SRAM_INITSTAT_BANK7_INIT = 1 /**< Bank 7 initialized */ +} ADI_PMG_TST_SRAM_INITSTAT_BNK7DONE; + + +/* ========================================================================== + *! \struct ADI_PMG_TST_SRAM_INITSTAT_Struct + *! \brief Initialization Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_INITSTAT_t__ +typedef struct _ADI_PMG_TST_SRAM_INITSTAT_t { + union { + struct { + unsigned int BNK0DONE : 1; /**< Bank 0 initialization status */ + unsigned int BNK1DONE : 1; /**< Bank 1 initialization status */ + unsigned int BNK2DONE : 1; /**< Bank 2 initialization status */ + unsigned int BNK3DONE : 1; /**< Bank 3 initialization status */ + unsigned int BNK4DONE : 1; /**< Bank 4 initialization status */ + unsigned int BNK5DONE : 1; /**< Bank 5 initialization status */ + unsigned int BNK6DONE : 1; /**< Bank 6 initialization status */ + unsigned int BNK7DONE : 1; /**< Bank 7 initialization status */ + unsigned int reserved8 : 24; + }; + uint32_t VALUE32; + }; +} ADI_PMG_TST_SRAM_INITSTAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_INITSTAT_t__ */ + +/*@}*/ + +/** @defgroup CLR_LATCH_GPIOS Clear GPIO After Shutdown Mode (CLR_LATCH_GPIOS) Register + * Clear GPIO After Shutdown Mode (CLR_LATCH_GPIOS) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_TST_CLR_LATCH_GPIOS_Struct + *! \brief Clear GPIO After Shutdown Mode Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_CLR_LATCH_GPIOS_t__ +typedef struct _ADI_PMG_TST_CLR_LATCH_GPIOS_t { + union { + struct { + unsigned int VALUE : 16; /**< Writing 0x58FA creates a pulse to clear the latches for the GPIOs */ + }; + uint16_t VALUE16; + }; +} ADI_PMG_TST_CLR_LATCH_GPIOS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_CLR_LATCH_GPIOS_t__ */ + +/*@}*/ + +/** @defgroup SCRPAD_IMG Scratch Pad Image (SCRPAD_IMG) Register + * Scratch Pad Image (SCRPAD_IMG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_TST_SCRPAD_IMG_Struct + *! \brief Scratch Pad Image Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_IMG_t__ +typedef struct _ADI_PMG_TST_SCRPAD_IMG_t { + union { + struct { + unsigned int DATA : 32; /**< Value written to this register is saved in 3 V when going to shutdown */ + }; + uint32_t VALUE32; + }; +} ADI_PMG_TST_SCRPAD_IMG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_IMG_t__ */ + +/*@}*/ + +/** @defgroup SCRPAD_3V_RD Scratch Pad Saved in Battery Domain (SCRPAD_3V_RD) Register + * Scratch Pad Saved in Battery Domain (SCRPAD_3V_RD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_TST_SCRPAD_3V_RD_Struct + *! \brief Scratch Pad Saved in Battery Domain Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_3V_RD_t__ +typedef struct _ADI_PMG_TST_SCRPAD_3V_RD_t { + union { + struct { + unsigned int DATA : 32; /**< Reading the scratch pad stored in shutdown mode */ + }; + uint32_t VALUE32; + }; +} ADI_PMG_TST_SCRPAD_3V_RD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_3V_RD_t__ */ + +/*@}*/ + +/** @defgroup FAST_SHT_WAKEUP Fast Shutdown Wake-up Enable (FAST_SHT_WAKEUP) Register + * Fast Shutdown Wake-up Enable (FAST_SHT_WAKEUP) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_TST_FAST_SHT_WAKEUP_Struct + *! \brief Fast Shutdown Wake-up Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_FAST_SHT_WAKEUP_t__ +typedef struct _ADI_PMG_TST_FAST_SHT_WAKEUP_t { + union { + struct { + unsigned int FAST_SHT_WAKEUP : 1; /**< Enables fast shutdown wake-up */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_PMG_TST_FAST_SHT_WAKEUP_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_FAST_SHT_WAKEUP_t__ */ + +/*@}*/ + +/** @defgroup CTL0 Misc Clock Settings (CTL0) Register + * Misc Clock Settings (CTL0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_CLK_CTL0_Struct + *! \brief Misc Clock Settings Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL0_t__ +typedef struct _ADI_CLKG_CLK_CTL0_t { + union { + struct { + unsigned int CLKMUX : 2; /**< Clock mux select */ + unsigned int reserved2 : 1; + unsigned int CLKOUT : 4; /**< GPIO clock out select */ + unsigned int reserved7 : 1; + unsigned int RCLKMUX : 2; /**< Flash reference clock and HPBUCK clock source mux */ + unsigned int reserved10 : 1; + unsigned int PLL_IPSEL : 2; /**< SPLL source select mux */ + unsigned int reserved13 : 1; + unsigned int LFXTALIE : 1; /**< Low frequency crystal interrupt enable */ + unsigned int HFXTALIE : 1; /**< High frequency crystal interrupt enable */ + unsigned int reserved16 : 16; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_CLK_CTL0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL0_t__ */ + +/*@}*/ + +/** @defgroup CTL1 Clock Dividers (CTL1) Register + * Clock Dividers (CTL1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_CLK_CTL1_Struct + *! \brief Clock Dividers Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL1_t__ +typedef struct _ADI_CLKG_CLK_CTL1_t { + union { + struct { + unsigned int HCLKDIVCNT : 6; /**< HCLK divide count */ + unsigned int reserved6 : 2; + unsigned int PCLKDIVCNT : 6; /**< PCLK divide count */ + unsigned int reserved14 : 2; + unsigned int ACLKDIVCNT : 9; /**< ACLK Divide Count */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_CLK_CTL1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL1_t__ */ + +/*@}*/ + +/** @defgroup CTL2 HF Oscillator Divided Clock Select (CTL2) Register + * HF Oscillator Divided Clock Select (CTL2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_CLK_CTL2_Struct + *! \brief HF Oscillator Divided Clock Select Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL2_t__ +typedef struct _ADI_CLKG_CLK_CTL2_t { + union { + struct { + unsigned int HFOSCAUTODIV_EN : 1; /**< HF Oscillator auto divide by one clock selection during wakeup from Flexi power mode */ + unsigned int HFOSCDIVCLKSEL : 3; /**< HF Oscillator divided clock select */ + unsigned int reserved4 : 28; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_CLK_CTL2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL2_t__ */ + +/*@}*/ + +/** @defgroup CTL3 System PLL (CTL3) Register + * System PLL (CTL3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_CLK_CTL3_Struct + *! \brief System PLL Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL3_t__ +typedef struct _ADI_CLKG_CLK_CTL3_t { + union { + struct { + unsigned int SPLLNSEL : 5; /**< System PLL N multiplier */ + unsigned int reserved5 : 3; + unsigned int SPLLDIV2 : 1; /**< System PLL division by 2 */ + unsigned int SPLLEN : 1; /**< System PLL enable */ + unsigned int SPLLIE : 1; /**< System PLL interrupt enable */ + unsigned int SPLLMSEL : 4; /**< System PLL M Divider */ + unsigned int reserved15 : 1; + unsigned int SPLLMUL2 : 1; /**< System PLL multiply by 2 */ + unsigned int reserved17 : 15; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_CLK_CTL3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL3_t__ */ + +/*@}*/ + +/** @defgroup CTL5 User Clock Gating Control (CTL5) Register + * User Clock Gating Control (CTL5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_CLK_CTL5_Struct + *! \brief User Clock Gating Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL5_t__ +typedef struct _ADI_CLKG_CLK_CTL5_t { + union { + struct { + unsigned int GPTCLK0OFF : 1; /**< GP Timer 0 user control */ + unsigned int GPTCLK1OFF : 1; /**< GP Timer 1 user control */ + unsigned int GPTCLK2OFF : 1; /**< GP Timer 2 user control */ + unsigned int UCLKI2COFF : 1; /**< I2C clock user control */ + unsigned int GPIOCLKOFF : 1; /**< GPIO clock control */ + unsigned int PERCLKOFF : 1; /**< This bit is used to disable all clocks connected to all peripherals */ + unsigned int TMRRGBCLKOFF : 1; /**< Timer RGB user control */ + unsigned int reserved7 : 25; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_CLK_CTL5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL5_t__ */ + +/*@}*/ + +/** @defgroup STAT0 Clocking Status (STAT0) Register + * Clocking Status (STAT0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_CLK_STAT0_Struct + *! \brief Clocking Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_STAT0_t__ +typedef struct _ADI_CLKG_CLK_STAT0_t { + union { + struct { + unsigned int SPLL : 1; /**< System PLL status */ + unsigned int SPLLLK : 1; /**< System PLL lock */ + unsigned int SPLLUNLK : 1; /**< System PLL unlock */ + unsigned int reserved3 : 5; + unsigned int LFXTAL : 1; /**< LF crystal status */ + unsigned int LFXTALOK : 1; /**< LF crystal stable */ + unsigned int LFXTALNOK : 1; /**< LF crystal not stable */ + unsigned int reserved11 : 1; + unsigned int HFXTAL : 1; /**< HF crystal status */ + unsigned int HFXTALOK : 1; /**< HF crystal stable */ + unsigned int HFXTALNOK : 1; /**< HF crystal not stable */ + unsigned int reserved15 : 17; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_CLK_STAT0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_STAT0_t__ */ + +/*@}*/ + +/** @defgroup ARBIT0 Arbitration Priority Configuration for FLASH and SRAM0 (ARBIT0) Register + * Arbitration Priority Configuration for FLASH and SRAM0 (ARBIT0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BUSM_ARBIT0_Struct + *! \brief Arbitration Priority Configuration for FLASH and SRAM0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT0_t__ +typedef struct _ADI_BUSM_ARBIT0_t { + union { + struct { + unsigned int FLSH_DCODE : 2; /**< Flash priority for DCODE */ + unsigned int FLSH_SBUS : 2; /**< Flash priority for SBUS */ + unsigned int FLSH_DMA0 : 2; /**< Flash priority for DMA0 */ + unsigned int reserved6 : 10; + unsigned int SRAM0_DCODE : 2; /**< SRAM0 priority for Dcode */ + unsigned int SRAM0_SBUS : 2; /**< SRAM0 priority for SBUS */ + unsigned int SRAM0_DMA0 : 2; /**< SRAM0 priority for DMA0 */ + unsigned int reserved22 : 10; + }; + uint32_t VALUE32; + }; +} ADI_BUSM_ARBIT0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT0_t__ */ + +/*@}*/ + +/** @defgroup ARBIT1 Arbitration Priority Configuration for SRAM1 and SIP (ARBIT1) Register + * Arbitration Priority Configuration for SRAM1 and SIP (ARBIT1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BUSM_ARBIT1_Struct + *! \brief Arbitration Priority Configuration for SRAM1 and SIP Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT1_t__ +typedef struct _ADI_BUSM_ARBIT1_t { + union { + struct { + unsigned int SRAM1_DCODE : 2; /**< SRAM1 priority for Dcode */ + unsigned int SRAM1_SBUS : 2; /**< SRAM1 priority for SBUS */ + unsigned int SRAM1_DMA0 : 2; /**< SRAM1 priority for DMA0 */ + unsigned int reserved6 : 10; + unsigned int SIP_DCODE : 2; /**< SIP priority for DCODE */ + unsigned int SIP_SBUS : 2; /**< SIP priority for SBUS */ + unsigned int SIP_DMA0 : 2; /**< SIP priority for DMA0 */ + unsigned int reserved22 : 10; + }; + uint32_t VALUE32; + }; +} ADI_BUSM_ARBIT1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT1_t__ */ + +/*@}*/ + +/** @defgroup ARBIT2 Arbitration Priority Configuration for APB32 and APB16 (ARBIT2) Register + * Arbitration Priority Configuration for APB32 and APB16 (ARBIT2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BUSM_ARBIT2_Struct + *! \brief Arbitration Priority Configuration for APB32 and APB16 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT2_t__ +typedef struct _ADI_BUSM_ARBIT2_t { + union { + struct { + unsigned int APB32_DCODE : 2; /**< APB32 priority for DCODE */ + unsigned int APB32_SBUS : 2; /**< APB32 priority for SBUS */ + unsigned int APB32_DMA0 : 2; /**< APB32 priority for DMA0 */ + unsigned int reserved6 : 10; + unsigned int APB16_DCODE : 2; /**< APB16 priority for DCODE */ + unsigned int APB16_SBUS : 2; /**< APB16 priority for SBUS */ + unsigned int APB16_DMA0 : 2; /**< APB16 priority for DMA0 */ + unsigned int reserved22 : 10; + }; + uint32_t VALUE32; + }; +} ADI_BUSM_ARBIT2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT2_t__ */ + +/*@}*/ + +/** @defgroup ARBIT3 Arbitration Priority Configuration for APB16 priority for core and for DMA1 (ARBIT3) Register + * Arbitration Priority Configuration for APB16 priority for core and for DMA1 (ARBIT3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BUSM_ARBIT3_Struct + *! \brief Arbitration Priority Configuration for APB16 priority for core and for DMA1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT3_t__ +typedef struct _ADI_BUSM_ARBIT3_t { + union { + struct { + unsigned int APB16_CORE : 1; /**< APB16 priority for CORE */ + unsigned int APB16_DMA1 : 1; /**< APB16 priority for DMA1 */ + unsigned int reserved2 : 14; + unsigned int APB16_4DMA_CORE : 1; /**< APB16 for dma priority for CORE */ + unsigned int APB16_4DMA_DMA1 : 1; /**< APB16 for dma priority for DMA1 */ + unsigned int reserved18 : 14; + }; + uint32_t VALUE32; + }; +} ADI_BUSM_ARBIT3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT3_t__ */ + +/*@}*/ + +/** @defgroup ARBIT4 Arbitration Priority Configuration for SRAM1 and SIP (ARBIT4) Register + * Arbitration Priority Configuration for SRAM1 and SIP (ARBIT4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BUSM_ARBIT4_Struct + *! \brief Arbitration Priority Configuration for SRAM1 and SIP Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT4_t__ +typedef struct _ADI_BUSM_ARBIT4_t { + union { + struct { + unsigned int SRAM2_DCODE : 2; /**< SRAM2 priority for Dcode */ + unsigned int SRAM2_SBUS : 2; /**< SRAM2 priority for SBUS */ + unsigned int SRAM2_DMA0 : 2; /**< SRAM2 priority for DMA0 */ + unsigned int reserved6 : 26; + }; + uint32_t VALUE32; + }; +} ADI_BUSM_ARBIT4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT4_t__ */ + +/*@}*/ + +/** @defgroup RST_ISR_STARTADDR Reset ISR Start Address (RST_ISR_STARTADDR) Register + * Reset ISR Start Address (RST_ISR_STARTADDR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PTI_RST_ISR_STARTADDR_Struct + *! \brief Reset ISR Start Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_RST_ISR_STARTADDR_t__ +typedef struct _ADI_PTI_RST_ISR_STARTADDR_t { + union { + struct { + unsigned int VALUE : 32; + }; + uint32_t VALUE32; + }; +} ADI_PTI_RST_ISR_STARTADDR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_RST_ISR_STARTADDR_t__ */ + +/*@}*/ + +/** @defgroup RST_STACK_PTR Reset Stack Pointer (RST_STACK_PTR) Register + * Reset Stack Pointer (RST_STACK_PTR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PTI_RST_STACK_PTR_Struct + *! \brief Reset Stack Pointer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_RST_STACK_PTR_t__ +typedef struct _ADI_PTI_RST_STACK_PTR_t { + union { + struct { + unsigned int VALUE : 32; + }; + uint32_t VALUE32; + }; +} ADI_PTI_RST_STACK_PTR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_RST_STACK_PTR_t__ */ + +/*@}*/ + +/** @defgroup CTL Parallel Test Interface Control Register (CTL) Register + * Parallel Test Interface Control Register (CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PTI_CTL_Struct + *! \brief Parallel Test Interface Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_CTL_t__ +typedef struct _ADI_PTI_CTL_t { + union { + struct { + unsigned int EN : 1; + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_PTI_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_CTL_t__ */ + +/*@}*/ + +/** @defgroup INTNUM Interrupt Control Type (INTNUM) Register + * Interrupt Control Type (INTNUM) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTNUM_Struct + *! \brief Interrupt Control Type Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTNUM_t__ +typedef struct _ADI_NVIC_INTNUM_t { + union { + struct { + unsigned int VALUE : 32; /**< Interrupt Control Type */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTNUM_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTNUM_t__ */ + +/*@}*/ + +/** @defgroup STKSTA Systick Control and Status (STKSTA) Register + * Systick Control and Status (STKSTA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_STKSTA_Struct + *! \brief Systick Control and Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKSTA_t__ +typedef struct _ADI_NVIC_STKSTA_t { + union { + struct { + unsigned int VALUE : 32; /**< Systick Control and Status */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_STKSTA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKSTA_t__ */ + +/*@}*/ + +/** @defgroup STKLD Systick Reload Value (STKLD) Register + * Systick Reload Value (STKLD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_STKLD_Struct + *! \brief Systick Reload Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKLD_t__ +typedef struct _ADI_NVIC_STKLD_t { + union { + struct { + unsigned int VALUE : 32; /**< Systick Reload Value */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_STKLD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKLD_t__ */ + +/*@}*/ + +/** @defgroup STKVAL Systick Current Value (STKVAL) Register + * Systick Current Value (STKVAL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_STKVAL_Struct + *! \brief Systick Current Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKVAL_t__ +typedef struct _ADI_NVIC_STKVAL_t { + union { + struct { + unsigned int VALUE : 32; /**< Systick Current Value */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_STKVAL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKVAL_t__ */ + +/*@}*/ + +/** @defgroup STKCAL Systick Calibration Value (STKCAL) Register + * Systick Calibration Value (STKCAL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_STKCAL_Struct + *! \brief Systick Calibration Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKCAL_t__ +typedef struct _ADI_NVIC_STKCAL_t { + union { + struct { + unsigned int VALUE : 32; /**< Systick Calibration Value */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_STKCAL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKCAL_t__ */ + +/*@}*/ + +/** @defgroup INTSETE0 IRQ0..31 Set_Enable (INTSETE0) Register + * IRQ0..31 Set_Enable (INTSETE0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSETE0_Struct + *! \brief IRQ0..31 Set_Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE0_t__ +typedef struct _ADI_NVIC_INTSETE0_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ0..31 Set_Enable */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSETE0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE0_t__ */ + +/*@}*/ + +/** @defgroup INTSETE1 IRQ32..63 Set_Enable (INTSETE1) Register + * IRQ32..63 Set_Enable (INTSETE1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSETE1_Struct + *! \brief IRQ32..63 Set_Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE1_t__ +typedef struct _ADI_NVIC_INTSETE1_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ32..63 Set_Enable */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSETE1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE1_t__ */ + +/*@}*/ + +/** @defgroup INTCLRE0 IRQ0..31 Clear_Enable (INTCLRE0) Register + * IRQ0..31 Clear_Enable (INTCLRE0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCLRE0_Struct + *! \brief IRQ0..31 Clear_Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE0_t__ +typedef struct _ADI_NVIC_INTCLRE0_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ0..31 Clear_Enable */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCLRE0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE0_t__ */ + +/*@}*/ + +/** @defgroup INTCLRE1 IRQ32..63 Clear_Enable (INTCLRE1) Register + * IRQ32..63 Clear_Enable (INTCLRE1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCLRE1_Struct + *! \brief IRQ32..63 Clear_Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE1_t__ +typedef struct _ADI_NVIC_INTCLRE1_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ32..63 Clear_Enable */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCLRE1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE1_t__ */ + +/*@}*/ + +/** @defgroup INTSETP0 IRQ0..31 Set_Pending (INTSETP0) Register + * IRQ0..31 Set_Pending (INTSETP0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSETP0_Struct + *! \brief IRQ0..31 Set_Pending Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP0_t__ +typedef struct _ADI_NVIC_INTSETP0_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ0..31 Set_Pending */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSETP0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP0_t__ */ + +/*@}*/ + +/** @defgroup INTSETP1 IRQ32..63 Set_Pending (INTSETP1) Register + * IRQ32..63 Set_Pending (INTSETP1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSETP1_Struct + *! \brief IRQ32..63 Set_Pending Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP1_t__ +typedef struct _ADI_NVIC_INTSETP1_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ32..63 Set_Pending */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSETP1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP1_t__ */ + +/*@}*/ + +/** @defgroup INTCLRP0 IRQ0..31 Clear_Pending (INTCLRP0) Register + * IRQ0..31 Clear_Pending (INTCLRP0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCLRP0_Struct + *! \brief IRQ0..31 Clear_Pending Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP0_t__ +typedef struct _ADI_NVIC_INTCLRP0_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ0..31 Clear_Pending */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCLRP0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP0_t__ */ + +/*@}*/ + +/** @defgroup INTCLRP1 IRQ32..63 Clear_Pending (INTCLRP1) Register + * IRQ32..63 Clear_Pending (INTCLRP1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCLRP1_Struct + *! \brief IRQ32..63 Clear_Pending Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP1_t__ +typedef struct _ADI_NVIC_INTCLRP1_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ32..63 Clear_Pending */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCLRP1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP1_t__ */ + +/*@}*/ + +/** @defgroup INTACT0 IRQ0..31 Active Bit (INTACT0) Register + * IRQ0..31 Active Bit (INTACT0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTACT0_Struct + *! \brief IRQ0..31 Active Bit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT0_t__ +typedef struct _ADI_NVIC_INTACT0_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ0..31 Active Bit */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTACT0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT0_t__ */ + +/*@}*/ + +/** @defgroup INTACT1 IRQ32..63 Active Bit (INTACT1) Register + * IRQ32..63 Active Bit (INTACT1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTACT1_Struct + *! \brief IRQ32..63 Active Bit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT1_t__ +typedef struct _ADI_NVIC_INTACT1_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ32..63 Active Bit */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTACT1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT1_t__ */ + +/*@}*/ + +/** @defgroup INTPRI0 IRQ0..3 Priority (INTPRI0) Register + * IRQ0..3 Priority (INTPRI0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI0_Struct + *! \brief IRQ0..3 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI0_t__ +typedef struct _ADI_NVIC_INTPRI0_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ0..3 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI0_t__ */ + +/*@}*/ + +/** @defgroup INTPRI1 IRQ4..7 Priority (INTPRI1) Register + * IRQ4..7 Priority (INTPRI1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI1_Struct + *! \brief IRQ4..7 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI1_t__ +typedef struct _ADI_NVIC_INTPRI1_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ4..7 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI1_t__ */ + +/*@}*/ + +/** @defgroup INTPRI2 IRQ8..11 Priority (INTPRI2) Register + * IRQ8..11 Priority (INTPRI2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI2_Struct + *! \brief IRQ8..11 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI2_t__ +typedef struct _ADI_NVIC_INTPRI2_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ8..11 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI2_t__ */ + +/*@}*/ + +/** @defgroup INTPRI3 IRQ12..15 Priority (INTPRI3) Register + * IRQ12..15 Priority (INTPRI3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI3_Struct + *! \brief IRQ12..15 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI3_t__ +typedef struct _ADI_NVIC_INTPRI3_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ12..15 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI3_t__ */ + +/*@}*/ + +/** @defgroup INTPRI4 IRQ16..19 Priority (INTPRI4) Register + * IRQ16..19 Priority (INTPRI4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI4_Struct + *! \brief IRQ16..19 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI4_t__ +typedef struct _ADI_NVIC_INTPRI4_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ16..19 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI4_t__ */ + +/*@}*/ + +/** @defgroup INTPRI5 IRQ20..23 Priority (INTPRI5) Register + * IRQ20..23 Priority (INTPRI5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI5_Struct + *! \brief IRQ20..23 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI5_t__ +typedef struct _ADI_NVIC_INTPRI5_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ20..23 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI5_t__ */ + +/*@}*/ + +/** @defgroup INTPRI6 IRQ24..27 Priority (INTPRI6) Register + * IRQ24..27 Priority (INTPRI6) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI6_Struct + *! \brief IRQ24..27 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI6_t__ +typedef struct _ADI_NVIC_INTPRI6_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ24..27 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI6_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI6_t__ */ + +/*@}*/ + +/** @defgroup INTPRI7 IRQ28..31 Priority (INTPRI7) Register + * IRQ28..31 Priority (INTPRI7) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI7_Struct + *! \brief IRQ28..31 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI7_t__ +typedef struct _ADI_NVIC_INTPRI7_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ28..31 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI7_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI7_t__ */ + +/*@}*/ + +/** @defgroup INTPRI8 IRQ32..35 Priority (INTPRI8) Register + * IRQ32..35 Priority (INTPRI8) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI8_Struct + *! \brief IRQ32..35 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI8_t__ +typedef struct _ADI_NVIC_INTPRI8_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ32..35 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI8_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI8_t__ */ + +/*@}*/ + +/** @defgroup INTPRI9 IRQ36..39 Priority (INTPRI9) Register + * IRQ36..39 Priority (INTPRI9) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI9_Struct + *! \brief IRQ36..39 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI9_t__ +typedef struct _ADI_NVIC_INTPRI9_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ36..39 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI9_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI9_t__ */ + +/*@}*/ + +/** @defgroup INTPRI10 IRQ40..43 Priority (INTPRI10) Register + * IRQ40..43 Priority (INTPRI10) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI10_Struct + *! \brief IRQ40..43 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI10_t__ +typedef struct _ADI_NVIC_INTPRI10_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ40..43 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI10_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI10_t__ */ + +/*@}*/ + +/** @defgroup INTCPID CPUID Base (INTCPID) Register + * CPUID Base (INTCPID) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCPID_Struct + *! \brief CPUID Base Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCPID_t__ +typedef struct _ADI_NVIC_INTCPID_t { + union { + struct { + unsigned int VALUE : 32; /**< CPUID Base */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCPID_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCPID_t__ */ + +/*@}*/ + +/** @defgroup INTSTA Interrupt Control State (INTSTA) Register + * Interrupt Control State (INTSTA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSTA_Struct + *! \brief Interrupt Control State Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSTA_t__ +typedef struct _ADI_NVIC_INTSTA_t { + union { + struct { + unsigned int VALUE : 32; /**< Interrupt Control State */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSTA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSTA_t__ */ + +/*@}*/ + +/** @defgroup INTVEC Vector Table Offset (INTVEC) Register + * Vector Table Offset (INTVEC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTVEC_Struct + *! \brief Vector Table Offset Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTVEC_t__ +typedef struct _ADI_NVIC_INTVEC_t { + union { + struct { + unsigned int VALUE : 32; /**< Vector Table Offset */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTVEC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTVEC_t__ */ + +/*@}*/ + +/** @defgroup INTAIRC Application Interrupt/Reset Control (INTAIRC) Register + * Application Interrupt/Reset Control (INTAIRC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTAIRC_Struct + *! \brief Application Interrupt/Reset Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTAIRC_t__ +typedef struct _ADI_NVIC_INTAIRC_t { + union { + struct { + unsigned int VALUE : 32; /**< Application Interrupt/Reset Control */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTAIRC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTAIRC_t__ */ + +/*@}*/ + +/** @defgroup INTCON0 System Control (INTCON0) Register + * System Control (INTCON0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCON0_Struct + *! \brief System Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON0_t__ +typedef struct _ADI_NVIC_INTCON0_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int SLEEPONEXIT : 1; /**< Sleeps the core on exit from an ISR */ + unsigned int SLEEPDEEP : 1; /**< deep sleep flag for HIBERNATE mode */ + unsigned int reserved3 : 13; + }; + uint16_t VALUE16; + }; +} ADI_NVIC_INTCON0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON0_t__ */ + +/*@}*/ + +/** @defgroup INTCON1 Configuration Control (INTCON1) Register + * Configuration Control (INTCON1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCON1_Struct + *! \brief Configuration Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON1_t__ +typedef struct _ADI_NVIC_INTCON1_t { + union { + struct { + unsigned int VALUE : 32; /**< Configuration Control */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCON1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON1_t__ */ + +/*@}*/ + +/** @defgroup INTSHPRIO0 System Handlers 4-7 Priority (INTSHPRIO0) Register + * System Handlers 4-7 Priority (INTSHPRIO0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSHPRIO0_Struct + *! \brief System Handlers 4-7 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO0_t__ +typedef struct _ADI_NVIC_INTSHPRIO0_t { + union { + struct { + unsigned int VALUE : 32; /**< System Handlers 4-7 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSHPRIO0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO0_t__ */ + +/*@}*/ + +/** @defgroup INTSHPRIO1 System Handlers 8-11 Priority (INTSHPRIO1) Register + * System Handlers 8-11 Priority (INTSHPRIO1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSHPRIO1_Struct + *! \brief System Handlers 8-11 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO1_t__ +typedef struct _ADI_NVIC_INTSHPRIO1_t { + union { + struct { + unsigned int VALUE : 32; /**< System Handlers 8-11 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSHPRIO1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO1_t__ */ + +/*@}*/ + +/** @defgroup INTSHPRIO3 System Handlers 12-15 Priority (INTSHPRIO3) Register + * System Handlers 12-15 Priority (INTSHPRIO3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSHPRIO3_Struct + *! \brief System Handlers 12-15 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO3_t__ +typedef struct _ADI_NVIC_INTSHPRIO3_t { + union { + struct { + unsigned int VALUE : 32; /**< System Handlers 12-15 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSHPRIO3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO3_t__ */ + +/*@}*/ + +/** @defgroup INTSHCSR System Handler Control and State (INTSHCSR) Register + * System Handler Control and State (INTSHCSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSHCSR_Struct + *! \brief System Handler Control and State Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHCSR_t__ +typedef struct _ADI_NVIC_INTSHCSR_t { + union { + struct { + unsigned int VALUE : 32; /**< System Handler Control and State */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSHCSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHCSR_t__ */ + +/*@}*/ + +/** @defgroup INTCFSR Configurable Fault Status (INTCFSR) Register + * Configurable Fault Status (INTCFSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCFSR_Struct + *! \brief Configurable Fault Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCFSR_t__ +typedef struct _ADI_NVIC_INTCFSR_t { + union { + struct { + unsigned int VALUE : 32; /**< Configurable Fault Status */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCFSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCFSR_t__ */ + +/*@}*/ + +/** @defgroup INTHFSR Hard Fault Status (INTHFSR) Register + * Hard Fault Status (INTHFSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTHFSR_Struct + *! \brief Hard Fault Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTHFSR_t__ +typedef struct _ADI_NVIC_INTHFSR_t { + union { + struct { + unsigned int VALUE : 32; /**< Hard Fault Status */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTHFSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTHFSR_t__ */ + +/*@}*/ + +/** @defgroup INTDFSR Debug Fault Status (INTDFSR) Register + * Debug Fault Status (INTDFSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTDFSR_Struct + *! \brief Debug Fault Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFSR_t__ +typedef struct _ADI_NVIC_INTDFSR_t { + union { + struct { + unsigned int VALUE : 32; /**< Debug Fault Status */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTDFSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFSR_t__ */ + +/*@}*/ + +/** @defgroup INTMMAR Mem Manage Address (INTMMAR) Register + * Mem Manage Address (INTMMAR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTMMAR_Struct + *! \brief Mem Manage Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMAR_t__ +typedef struct _ADI_NVIC_INTMMAR_t { + union { + struct { + unsigned int VALUE : 32; /**< Mem Manage Address */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTMMAR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMAR_t__ */ + +/*@}*/ + +/** @defgroup INTBFAR Bus Fault Address (INTBFAR) Register + * Bus Fault Address (INTBFAR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTBFAR_Struct + *! \brief Bus Fault Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTBFAR_t__ +typedef struct _ADI_NVIC_INTBFAR_t { + union { + struct { + unsigned int VALUE : 32; /**< Bus Fault Address */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTBFAR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTBFAR_t__ */ + +/*@}*/ + +/** @defgroup INTAFSR Auxiliary Fault Status (INTAFSR) Register + * Auxiliary Fault Status (INTAFSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTAFSR_Struct + *! \brief Auxiliary Fault Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFSR_t__ +typedef struct _ADI_NVIC_INTAFSR_t { + union { + struct { + unsigned int VALUE : 32; /**< Auxiliary Fault Status */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTAFSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFSR_t__ */ + +/*@}*/ + +/** @defgroup INTPFR0 Processor Feature Register 0 (INTPFR0) Register + * Processor Feature Register 0 (INTPFR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPFR0_Struct + *! \brief Processor Feature Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR0_t__ +typedef struct _ADI_NVIC_INTPFR0_t { + union { + struct { + unsigned int VALUE : 32; /**< Processor Feature Register 0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPFR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR0_t__ */ + +/*@}*/ + +/** @defgroup INTPFR1 Processor Feature Register 1 (INTPFR1) Register + * Processor Feature Register 1 (INTPFR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPFR1_Struct + *! \brief Processor Feature Register 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR1_t__ +typedef struct _ADI_NVIC_INTPFR1_t { + union { + struct { + unsigned int VALUE : 32; /**< Processor Feature Register 1 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPFR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR1_t__ */ + +/*@}*/ + +/** @defgroup INTDFR0 Debug Feature Register 0 (INTDFR0) Register + * Debug Feature Register 0 (INTDFR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTDFR0_Struct + *! \brief Debug Feature Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFR0_t__ +typedef struct _ADI_NVIC_INTDFR0_t { + union { + struct { + unsigned int VALUE : 32; /**< Debug Feature Register 0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTDFR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFR0_t__ */ + +/*@}*/ + +/** @defgroup INTAFR0 Auxiliary Feature Register 0 (INTAFR0) Register + * Auxiliary Feature Register 0 (INTAFR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTAFR0_Struct + *! \brief Auxiliary Feature Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFR0_t__ +typedef struct _ADI_NVIC_INTAFR0_t { + union { + struct { + unsigned int VALUE : 32; /**< Auxiliary Feature Register 0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTAFR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFR0_t__ */ + +/*@}*/ + +/** @defgroup INTMMFR0 Memory Model Feature Register 0 (INTMMFR0) Register + * Memory Model Feature Register 0 (INTMMFR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTMMFR0_Struct + *! \brief Memory Model Feature Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR0_t__ +typedef struct _ADI_NVIC_INTMMFR0_t { + union { + struct { + unsigned int VALUE : 32; /**< Memory Model Feature Register 0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTMMFR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR0_t__ */ + +/*@}*/ + +/** @defgroup INTMMFR1 Memory Model Feature Register 1 (INTMMFR1) Register + * Memory Model Feature Register 1 (INTMMFR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTMMFR1_Struct + *! \brief Memory Model Feature Register 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR1_t__ +typedef struct _ADI_NVIC_INTMMFR1_t { + union { + struct { + unsigned int VALUE : 32; /**< Memory Model Feature Register 1 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTMMFR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR1_t__ */ + +/*@}*/ + +/** @defgroup INTMMFR2 Memory Model Feature Register 2 (INTMMFR2) Register + * Memory Model Feature Register 2 (INTMMFR2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTMMFR2_Struct + *! \brief Memory Model Feature Register 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR2_t__ +typedef struct _ADI_NVIC_INTMMFR2_t { + union { + struct { + unsigned int VALUE : 32; /**< Memory Model Feature Register 2 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTMMFR2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR2_t__ */ + +/*@}*/ + +/** @defgroup INTMMFR3 Memory Model Feature Register 3 (INTMMFR3) Register + * Memory Model Feature Register 3 (INTMMFR3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTMMFR3_Struct + *! \brief Memory Model Feature Register 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR3_t__ +typedef struct _ADI_NVIC_INTMMFR3_t { + union { + struct { + unsigned int VALUE : 32; /**< Memory Model Feature Register 3 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTMMFR3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR3_t__ */ + +/*@}*/ + +/** @defgroup INTISAR0 ISA Feature Register 0 (INTISAR0) Register + * ISA Feature Register 0 (INTISAR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTISAR0_Struct + *! \brief ISA Feature Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR0_t__ +typedef struct _ADI_NVIC_INTISAR0_t { + union { + struct { + unsigned int VALUE : 32; /**< ISA Feature Register 0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTISAR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR0_t__ */ + +/*@}*/ + +/** @defgroup INTISAR1 ISA Feature Register 1 (INTISAR1) Register + * ISA Feature Register 1 (INTISAR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTISAR1_Struct + *! \brief ISA Feature Register 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR1_t__ +typedef struct _ADI_NVIC_INTISAR1_t { + union { + struct { + unsigned int VALUE : 32; /**< ISA Feature Register 1 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTISAR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR1_t__ */ + +/*@}*/ + +/** @defgroup INTISAR2 ISA Feature Register 2 (INTISAR2) Register + * ISA Feature Register 2 (INTISAR2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTISAR2_Struct + *! \brief ISA Feature Register 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR2_t__ +typedef struct _ADI_NVIC_INTISAR2_t { + union { + struct { + unsigned int VALUE : 32; /**< ISA Feature Register 2 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTISAR2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR2_t__ */ + +/*@}*/ + +/** @defgroup INTISAR3 ISA Feature Register 3 (INTISAR3) Register + * ISA Feature Register 3 (INTISAR3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTISAR3_Struct + *! \brief ISA Feature Register 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR3_t__ +typedef struct _ADI_NVIC_INTISAR3_t { + union { + struct { + unsigned int VALUE : 32; /**< ISA Feature Register 3 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTISAR3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR3_t__ */ + +/*@}*/ + +/** @defgroup INTISAR4 ISA Feature Register 4 (INTISAR4) Register + * ISA Feature Register 4 (INTISAR4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTISAR4_Struct + *! \brief ISA Feature Register 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR4_t__ +typedef struct _ADI_NVIC_INTISAR4_t { + union { + struct { + unsigned int VALUE : 32; /**< ISA Feature Register 4 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTISAR4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR4_t__ */ + +/*@}*/ + +/** @defgroup INTTRGI Software Trigger Interrupt Register (INTTRGI) Register + * Software Trigger Interrupt Register (INTTRGI) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTTRGI_Struct + *! \brief Software Trigger Interrupt Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTTRGI_t__ +typedef struct _ADI_NVIC_INTTRGI_t { + union { + struct { + unsigned int VALUE : 32; /**< Software Trigger Interrupt Register */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTTRGI_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTTRGI_t__ */ + +/*@}*/ + +/** @defgroup INTPID4 Peripheral Identification Register 4 (INTPID4) Register + * Peripheral Identification Register 4 (INTPID4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID4_Struct + *! \brief Peripheral Identification Register 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID4_t__ +typedef struct _ADI_NVIC_INTPID4_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Register 4 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID4_t__ */ + +/*@}*/ + +/** @defgroup INTPID5 Peripheral Identification Register 5 (INTPID5) Register + * Peripheral Identification Register 5 (INTPID5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID5_Struct + *! \brief Peripheral Identification Register 5 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID5_t__ +typedef struct _ADI_NVIC_INTPID5_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Register 5 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID5_t__ */ + +/*@}*/ + +/** @defgroup INTPID6 Peripheral Identification Register 6 (INTPID6) Register + * Peripheral Identification Register 6 (INTPID6) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID6_Struct + *! \brief Peripheral Identification Register 6 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID6_t__ +typedef struct _ADI_NVIC_INTPID6_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Register 6 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID6_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID6_t__ */ + +/*@}*/ + +/** @defgroup INTPID7 Peripheral Identification Register 7 (INTPID7) Register + * Peripheral Identification Register 7 (INTPID7) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID7_Struct + *! \brief Peripheral Identification Register 7 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID7_t__ +typedef struct _ADI_NVIC_INTPID7_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Register 7 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID7_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID7_t__ */ + +/*@}*/ + +/** @defgroup INTPID0 Peripheral Identification Bits7:0 (INTPID0) Register + * Peripheral Identification Bits7:0 (INTPID0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID0_Struct + *! \brief Peripheral Identification Bits7:0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID0_t__ +typedef struct _ADI_NVIC_INTPID0_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Bits7:0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID0_t__ */ + +/*@}*/ + +/** @defgroup INTPID1 Peripheral Identification Bits15:8 (INTPID1) Register + * Peripheral Identification Bits15:8 (INTPID1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID1_Struct + *! \brief Peripheral Identification Bits15:8 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID1_t__ +typedef struct _ADI_NVIC_INTPID1_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Bits15:8 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID1_t__ */ + +/*@}*/ + +/** @defgroup INTPID2 Peripheral Identification Bits16:23 (INTPID2) Register + * Peripheral Identification Bits16:23 (INTPID2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID2_Struct + *! \brief Peripheral Identification Bits16:23 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID2_t__ +typedef struct _ADI_NVIC_INTPID2_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Bits16:23 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID2_t__ */ + +/*@}*/ + +/** @defgroup INTPID3 Peripheral Identification Bits24:31 (INTPID3) Register + * Peripheral Identification Bits24:31 (INTPID3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID3_Struct + *! \brief Peripheral Identification Bits24:31 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID3_t__ +typedef struct _ADI_NVIC_INTPID3_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Bits24:31 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID3_t__ */ + +/*@}*/ + +/** @defgroup INTCID0 Component Identification Bits7:0 (INTCID0) Register + * Component Identification Bits7:0 (INTCID0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCID0_Struct + *! \brief Component Identification Bits7:0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID0_t__ +typedef struct _ADI_NVIC_INTCID0_t { + union { + struct { + unsigned int VALUE : 32; /**< Component Identification Bits7:0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCID0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID0_t__ */ + +/*@}*/ + +/** @defgroup INTCID1 Component Identification Bits15:8 (INTCID1) Register + * Component Identification Bits15:8 (INTCID1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCID1_Struct + *! \brief Component Identification Bits15:8 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID1_t__ +typedef struct _ADI_NVIC_INTCID1_t { + union { + struct { + unsigned int VALUE : 32; /**< Component Identification Bits15:8 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCID1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID1_t__ */ + +/*@}*/ + +/** @defgroup INTCID2 Component Identification Bits16:23 (INTCID2) Register + * Component Identification Bits16:23 (INTCID2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCID2_Struct + *! \brief Component Identification Bits16:23 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID2_t__ +typedef struct _ADI_NVIC_INTCID2_t { + union { + struct { + unsigned int VALUE : 32; /**< Component Identification Bits16:23 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCID2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID2_t__ */ + +/*@}*/ + +/** @defgroup INTCID3 Component Identification Bits24:31 (INTCID3) Register + * Component Identification Bits24:31 (INTCID3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCID3_Struct + *! \brief Component Identification Bits24:31 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID3_t__ +typedef struct _ADI_NVIC_INTCID3_t { + union { + struct { + unsigned int VALUE : 32; /**< Component Identification Bits24:31 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCID3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID3_t__ */ + +/*@}*/ + + +#if defined (_MISRA_RULES) +#pragma diag(pop) +#endif /* _MISRA_RULES */ + + +#if defined (__CC_ARM) +#pragma pop +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_cio_macros.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_cio_macros.h new file mode 100755 index 0000000000..45f235b44b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_cio_macros.h @@ -0,0 +1,50 @@ +/* +** adi_cio_macros.h +** +** Copyright (C) 2016 Analog Devices, Inc. All Rights Reserved. +** +*/ + +#ifndef _ADI_CIO_MACROS_H +#define _ADI_CIO_MACROS_H + +/* + * Macro definitions in adi_ADuCM4*50_cdef.h and the struct definitions + * in adi_ADuCM4*50_device.h use macros "__I __C", "__O" and "__IO" to + * represent read-only, write-only and read/write register attributes. + * + * The core_cm4.h include file will define macros __I, __O and __IO as below + * but it does not define __C. + * + * The __C macro is defined to nothing here. The __C macro is intended for + * the proprietary compilers in CCES to avoid MISRA Rule 19.4 errors regarding + * permitted macro expansions. The iccarm.exe MISRA checking does not fault + * the combined "volatile const" __I macro so __C is not required. + * + * Each of the macro defines is guarded by a #ifndef check to allow them + * to be redefined if required. + * + * Workaround for 01-00-0757 / 01-00-0759 + */ + +#ifndef __I + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif +#endif + +#ifndef __O + #define __O volatile /*!< Defines 'write only' permissions */ +#endif + +#ifndef __IO + #define __IO volatile /*!< Defines 'read / write' permissions */ +#endif + +#ifndef __C + #define __C /*nothing*/ +#endif + +#endif /* _ADI_CIO_MACROS_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/platform.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/platform.h new file mode 100755 index 0000000000..c21be7b293 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/platform.h @@ -0,0 +1,56 @@ +/*! + ***************************************************************************** + * @file: platform.h + * @brief: Include appropriate architecture definitions. + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef __ADI_SYS_PLATFORM_H__ +#define __ADI_SYS_PLATFORM_H__ + +/* Include the ADI cdef header for the selected target. */ + +#if defined(__ADUCM4050__) +#include +#else +#error not configured for this target. +#endif + +#endif /* __ADI_SYS_PLATFORM_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/system_ADuCM4050.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/system_ADuCM4050.h new file mode 100755 index 0000000000..5bde78d691 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/system_ADuCM4050.h @@ -0,0 +1,159 @@ +/*! + ***************************************************************************** + * @file: system_ADuCM4050.h + * @brief: CMSIS Cortex-M4 Device Peripheral Access Layer Header File + * for ADuCM4050 + * @version V3.10 + * @date 23. November 2012 + * + * @note Modified September 21 2016 Analog Devices +******************************************************************************/ +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef SYSTEM_ADUCM4050_H +#define SYSTEM_ADUCM4050_H + +#include /* for 'NULL' */ +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +#if defined (__ICCARM__) +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): Types which specify sign and size should be used +* We use bool which is accepted by MISRA but the toolchain does not accept it +* +*/ +#pragma diag_suppress=Pm011 + +#endif + +/*! \addtogroup SYS_Driver System Interfaces + * @{ + * System global interfaces and CMSIS required variables + */ + +/*! System API function return codes */ +typedef enum +{ + ADI_SYS_SUCCESS = 0, /*!< No error detected. */ + ADI_SYS_FAILURE, /*!< The API call failed. */ +} ADI_SYS_RESULT; + + +/*! \cond PRIVATE */ +/* System clock constant */ +#define __HFOSC 26000000u + +/* System clock constant (may also be 16000000) */ +#define __HFXTAL 26000000u + + /*System clock constant (same whether internal osc or external xtal) */ +#define __LFCLK 32768u + + /*Selecting HFOSC as input for generating root clock*/ +#define HFMUX_INTERNAL_OSC_VAL (0u << BITP_CLKG_CLK_CTL0_CLKMUX) + + /*Selecting HFXTAL as input for generating root clock*/ +#define HFMUX_EXTERNAL_XTAL_VAL (1u << BITP_CLKG_CLK_CTL0_CLKMUX) + + /*Selecting SPLL as input for generating root clock*/ +#define HFMUX_SYSTEM_SPLL_VAL (2u << BITP_CLKG_CLK_CTL0_CLKMUX) + + /*Selecting GPIO as input for generating root clock*/ +#define HFMUX_GPIO_VAL (3u << BITP_CLKG_CLK_CTL0_CLKMUX) + +/*! Cache controller key */ +#define CACHE_CONTROLLER_KEY 0xF123F456u +/*! Power key */ +#define PWRKEY_VALUE_KEY 0x4859u + +/** + * Security options + */ +typedef struct { + const uint32_t ReadProtectKeyHash[4]; + const uint32_t CrcOfReadProtectKeyHash; + const uint32_t LastCRCPage; + const uint32_t InCircuitWriteProtectCode; + const uint32_t FlashBlockWriteProtect; + +} ADI_ADUCM4X50_SECURITY_OPTIONS; + +/*! \endcond*/ + +/** + * SRAM banks + */ +typedef uint32_t ADI_SRAM_BANK; + +/*! SRAM_BANK_0 */ +#define ADI_SRAM_BANK_0 (1u << 0) +/*! SRAM_BANK_1 */ +#define ADI_SRAM_BANK_1 (1u << 1) +/*! SRAM_BANK_2 */ +#define ADI_SRAM_BANK_2 (1u << 2) +/*! SRAM_BANK_3 */ +#define ADI_SRAM_BANK_3 (1u << 3) +/*! SRAM_BANK_4 */ +#define ADI_SRAM_BANK_4 (1u << 4) +/*! SRAM_BANK_5 */ +#define ADI_SRAM_BANK_5 (1u << 5) +/*! SRAM_BANK_6 */ +#define ADI_SRAM_BANK_6 (1u << 6) +/*! SRAM_BANK_7 */ +#define ADI_SRAM_BANK_7 (1u << 7) + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +void adi_system_EnableCache(bool bEnable); +ADI_SYS_RESULT adi_system_EnableRetention(ADI_SRAM_BANK eBank, bool bEnable); +void adi_system_EnableISRAM(bool bEnable); + +#if defined (__ICCARM__) +#pragma diag_default=Pm011 +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_ADUCM4050_H */ + +/*@}*/ +/* +** EOF +*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c new file mode 100755 index 0000000000..b7153b79a8 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c @@ -0,0 +1,611 @@ +/*! ***************************************************************************** + * @file adi_tmr.c + * @brief GP and RGB timer device driver implementation + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): the basic types of char, int, short, long, float, and double should not be used +* Necessary for stdbool. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* Static configuration data file is included. +* +* Pm140 (Rule 11.4): a cast should not be performed between a pointer type and an integral type +* This violation appears when deferencing the pointer to the register typedef. No way around this. +* +* Pm141 (Rule 11.4): a cast should not be performed between a pointer to object type and a different pointer to object type +* The pointer casting is necessary to allow the GP and RGB timers to abstracted into one driver. This has been approved by the PO. +*/ +#pragma diag_suppress=Pm011,Pm073,Pm123,Pm140,Pm141,Pm143 +#endif /* __ICCARM__ */ + + +/** @addtogroup TMR_Driver Timer Driver + * @{ + * @brief General Purpose and RGB Timer Driver + * @details The timer driver controls the timer period, event capture, and + * pulse width modulation (PWM) features of the General Purpose (GP) Timers and + * the RGB Timer. + * @note The application must include drivers/tmr/adi_tmr.h to use this driver + */ + +#include +#include +#include +#include + +/* Static configuration data */ +#if ADI_TIMER_ENABLE_STATIC_CONFIG_SUPPORT == 1u +#include "adi_tmr_data.c" +#endif + + +/* In adi_tmr_ConfigPwm, the bit positions for just PWM0 are used for PWM1 and PWM2 to simplify the code. Check here to make sure this is safe. */ +#if BITP_TMR_RGB_PWM0CTL_IDLESTATE != BITP_TMR_RGB_PWM1CTL_IDLESTATE +#error "Bit positions for PWM0 and PWM1 do not match. Fix adi_tmr_ConfigPwm." +#endif +#if BITP_TMR_RGB_PWM0CTL_IDLESTATE != BITP_TMR_RGB_PWM2CTL_IDLESTATE +#error "Bit positions for PWM0 and PWM2 do not match. Fix adi_tmr_ConfigPwm." +#endif +#if BITP_TMR_RGB_PWM0CTL_MATCH != BITP_TMR_RGB_PWM1CTL_MATCH +#error "Bit positions for PWM0 and PWM1 do not match. Fix adi_tmr_ConfigPwm." +#endif +#if BITP_TMR_RGB_PWM0CTL_MATCH != BITP_TMR_RGB_PWM2CTL_MATCH +#error "Bit positions for PWM0 and PWM2 do not match. Fix adi_tmr_ConfigPwm." +#endif + +/*! Number of events that can be captured */ +#define ADI_TMR_NUM_EVENTS (40u) + +/*! \cond PRIVATE */ + +/* Since the RGB typedef is a superset of the GP typedef, treat the GP timers as RGB timers and restrict top register access */ +static ADI_TMR_RGB_TypeDef * adi_tmr_registers[ADI_TMR_DEVICE_NUM] = {(ADI_TMR_RGB_TypeDef *) pADI_TMR0, (ADI_TMR_RGB_TypeDef *) pADI_TMR1, (ADI_TMR_RGB_TypeDef *) pADI_TMR2, pADI_TMR_RGB}; + +/* Interrupt enums */ +static const IRQn_Type adi_tmr_interrupt[ADI_TMR_DEVICE_NUM] = {TMR0_EVT_IRQn, TMR1_EVT_IRQn, TMR2_EVT_IRQn, TMR_RGB_EVT_IRQn}; + +/* Private data that the driver needs to retain between function calls */ +static ADI_CALLBACK adi_tmr_callbacks[ADI_TMR_DEVICE_NUM]; +static void * adi_tmr_parameters[ADI_TMR_DEVICE_NUM]; + +static ADI_TMR_RESULT WaitForStatusBit (ADI_TMR_DEVICE const eDevice, uint16_t nBusyBit); +static void CommonIntHandler (ADI_TMR_DEVICE const eDevice); + void GP_Tmr0_Int_Handler(void); + void GP_Tmr1_Int_Handler(void); + void GP_Tmr2_Int_Handler(void); + void RGB_Tmr_Int_Handler(void); + +/*! \endcond */ + + +/********************************************************************************* + API IMPLEMENTATIONS +*********************************************************************************/ + + +/*! + * @brief Initialize GP or RGB Timer + * + * @details Setup callback function, device interrupt, and perform static configuration (if applicable). + * + * @note This function can only be called when the timer is disabled. This function should be called + * before any other functions are called. + * + * @param [in] eDevice : Device number + * + * @param [in] pfCallback : Callback function + * + * @param [in] pCBParam : Callback function parameter + * + * @param [in] bEnableInt : True to enable the device interrupt, false to disable it + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_OPERATION_NOT_ALLOWED [D] Timer is currently running + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_Init(ADI_TMR_DEVICE const eDevice, ADI_CALLBACK const pfCallback, void * const pCBParam, bool bEnableInt) { +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(The timer is already running) */ + if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) { + return ADI_TMR_OPERATION_NOT_ALLOWED; + } /* ENDIF */ +#endif + /* Setup the callback function */ + adi_tmr_callbacks [eDevice] = pfCallback; + adi_tmr_parameters[eDevice] = pCBParam; + + /* IF(Enable interrupt) */ + if (bEnableInt == true) { + NVIC_EnableIRQ(adi_tmr_interrupt[eDevice]); + /* ELSE(Disable interrupt) */ + } else { + NVIC_DisableIRQ(adi_tmr_interrupt[eDevice]); + } /* ENDIF */ + + /* Static configuration */ +#if ADI_TIMER_ENABLE_STATIC_CONFIG_SUPPORT == 1u + adi_tmr_registers[eDevice]->CTL = aTimerCtlConfig [eDevice]; + adi_tmr_registers[eDevice]->LOAD = aTimerLoadConfig [eDevice]; + adi_tmr_registers[eDevice]->ALOAD = aTimerALoadConfig [eDevice]; + adi_tmr_registers[eDevice]->EVENTSELECT = aTimerEventConfig [eDevice]; + adi_tmr_registers[eDevice]->PWM0CTL = aTimerPwmCtlConfig [eDevice]; + adi_tmr_registers[eDevice]->PWM0MATCH = aTimerPwmMatchConfig[eDevice]; + + /* IF(Initializing the RGB timer, there are 2 other PWM outputs to configure) */ + if (eDevice == ADI_TMR_DEVICE_RGB) { + /* The array is bumped by 1 to get to the 5th entry in the static config array, which contains RGB PWM1 */ + adi_tmr_registers[eDevice]->PWM1CTL = aTimerPwmCtlConfig [eDevice+1u]; + adi_tmr_registers[eDevice]->PWM1MATCH = aTimerPwmMatchConfig[eDevice+1u]; + /* The array is bumped by 2 to get to the 6th entry in the static config array, which contains RGB PWM2 */ + adi_tmr_registers[eDevice]->PWM2CTL = aTimerPwmCtlConfig [eDevice+2u]; + adi_tmr_registers[eDevice]->PWM2MATCH = aTimerPwmMatchConfig[eDevice+2u]; + } /* ENDIF */ +#endif + + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Configure GP or RGB Timer + * + * @details Configure the basic hardware timer parameters. + * + * @note This function can only be called when the timer is disabled. + * + * @param [in] eDevice : Device number + * + * @param [in] timerConfig : Timer configuration structure, filled by user prior to function call + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_BAD_RELOAD_CONFIGURATION [D] bPeriodic is false and bReloading is true + * - #ADI_TMR_OPERATION_NOT_ALLOWED [D] Timer is currently running + * - #ADI_TMR_DEVICE_BUSY Timer is busy processing a previous control register write + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_ConfigTimer(ADI_TMR_DEVICE const eDevice, ADI_TMR_CONFIG timerConfig) { + uint16_t nTemp; +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(Bad configuration, cannot enable reloading while in free running mode) */ + if ((timerConfig.bPeriodic == false) && (timerConfig.bReloading == true)) { + return ADI_TMR_BAD_RELOAD_CONFIGURATION; + } /* ENDIF */ + /* IF(The timer is already running) */ + if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) { + return ADI_TMR_OPERATION_NOT_ALLOWED; + } /* ENDIF */ +#endif + /* Set the load registers */ + adi_tmr_registers[eDevice]->LOAD = timerConfig.nLoad; + adi_tmr_registers[eDevice]->ALOAD = timerConfig.nAsyncLoad; + + /* IF(Busy bit does not clear after waiting) */ + if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_BUSY)) { + return ADI_TMR_DEVICE_BUSY; + } /* ENDIF */ + + /* Read the control register and clear everything aside to the event capture bits, which are the only fields not set in this function */ + nTemp = adi_tmr_registers[eDevice]->CTL; + nTemp &= (uint16_t) (BITM_TMR_RGB_CTL_EVTEN | BITM_TMR_RGB_CTL_RSTEN); + + /* Setup the prescaler and the clock source */ + nTemp |= (uint16_t)(((uint16_t) timerConfig.ePrescaler ) << BITP_TMR_RGB_CTL_PRE); + nTemp |= (uint16_t)(((uint16_t) timerConfig.eClockSource) << BITP_TMR_RGB_CTL_CLK); + + /* IF(Periodic mode) */ + if (timerConfig.bPeriodic == true) { + nTemp |= (1u << BITP_TMR_RGB_CTL_MODE); + } /* ENDIF */ + + /* IF(Counting up) */ + if (timerConfig.bCountingUp == true) { + nTemp |= (1u << BITP_TMR_RGB_CTL_UP); + } /* ENDIF */ + + /* IF(Reloading is enabled) */ + if (timerConfig.bReloading == true) { + nTemp |= (1u << BITP_TMR_RGB_CTL_RLD); + } /* ENDIF */ + + /* IF(Sync bypass is enabled) */ + if (timerConfig.bSyncBypass == true) { + nTemp |= (1u << BITP_TMR_RGB_CTL_SYNCBYP); + } /* ENDIF */ + + /* Update the control register with the new configuration */ + adi_tmr_registers[eDevice]->CTL = nTemp; + + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Setup GP or RGB Timer Event Capture + * + * @details The timer can be configured to capture the timer value when a specific event occurs. The + * list of events can be found in the hardware reference manual. The callback function specified + * in #adi_tmr_Init will be supplied #ADI_TMR_EVENT_CAPTURE to indicate the event occured. The + * user can then read the captured value by calling #adi_tmr_GetCaptureCount. + * + * @note This function can only be called when the timer is disabled. + * + * @param [in] eDevice : Device number + * + * @param [in] eventConfig : Event configuration structure, filled by user prior to function call + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_BAD_EVENT_ID [D] Event ID was not out of the valid range [0,#ADI_TMR_NUM_EVENTS] + * - #ADI_TMR_OPERATION_NOT_ALLOWED [D] Timer is currently running + * - #ADI_TMR_DEVICE_BUSY Timer is busy processing a previous control register write + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_ConfigEvent(ADI_TMR_DEVICE const eDevice, ADI_TMR_EVENT_CONFIG eventConfig) { +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(Bad event input parameter) */ + if (eventConfig.nEventID >= ADI_TMR_NUM_EVENTS) { + return ADI_TMR_BAD_EVENT_ID; + } /* ENDIF */ + /* IF(The timer is already running) */ + if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) { + return ADI_TMR_OPERATION_NOT_ALLOWED; + } /* ENDIF */ +#endif + /* Set the event number */ + adi_tmr_registers[eDevice]->EVENTSELECT = (uint16_t) eventConfig.nEventID; + + /* IF(Busy bit does not clear after waiting) */ + if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_BUSY)) { + return ADI_TMR_DEVICE_BUSY; + } /* ENDIF */ + + /* Clear the event enable bit and keep the other bits */ + adi_tmr_registers[eDevice]->CTL &= (uint16_t) ~(BITM_TMR_RGB_CTL_EVTEN | BITM_TMR_RGB_CTL_RSTEN); + + /* IF(Turning event capture on) */ + if (eventConfig.bEnable == true) { + adi_tmr_registers[eDevice]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EVTEN; + } /* ENDIF */ + + /* IF(Enabling reset on event capture) */ + if (eventConfig.bPrescaleReset == true) { + adi_tmr_registers[eDevice]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_RSTEN; + } /* ENDIF */ + + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Setup GP or RGB Timer Pulse Width Modulation + * + * @details The timer can be configured to generate a pulse width modulation output signal. + * The period of this signal is simply determined by the period of timer. The duty + * cycle will be 50% in toggle mode, or can be configured by the user for a different + * value using the match value. The pulse will toggle when the timer count matches + * the match value. The user can also specify the polarity of the signal by choosing + * if the signal idles low or high. GPIO muxing will be required to use the PWM output. + * + * @note This function can only be called when the timer is disabled. + * + * @param [in] eDevice : Device number + * + * @param [in] pwmConfig : PWM configuration structure, filled by user prior to function call + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_OPERATION_NOT_ALLOWED [D] Timer is currently running + * - #ADI_TMR_BAD_PWM_NUM [D] Invalid eOutput parameter supplied + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_ConfigPwm(ADI_TMR_DEVICE const eDevice, ADI_TMR_PWM_CONFIG pwmConfig) { + uint16_t nControl = 0u; +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(The timer is already running) */ + if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) { + return ADI_TMR_OPERATION_NOT_ALLOWED; + } /* ENDIF */ + /* IF(Bad PWM output and device combo OR bad PWM output) */ + if (((eDevice != ADI_TMR_DEVICE_RGB) && (pwmConfig.eOutput != ADI_TMR_PWM_OUTPUT_0)) || (pwmConfig.eOutput >= ADI_TMR_PWM_OUTPUT_NUM)) { + return ADI_TMR_BAD_PWM_NUM; + } /* ENDIF */ +#endif + /* IF(Idle high is set) */ + if (pwmConfig.bIdleHigh == true) { + nControl = (1u << ((uint16_t) BITP_TMR_RGB_PWM0CTL_IDLESTATE)); + } /* ENDIF */ + + /* IF(Match mode is enabled) */ + if (pwmConfig.bMatch == true) { + nControl |= (1u << ((uint16_t) BITP_TMR_RGB_PWM0CTL_MATCH)); + } /* ENDIF */ + + /* IF(PWM output 0) */ + if (pwmConfig.eOutput == ADI_TMR_PWM_OUTPUT_0) { + adi_tmr_registers[eDevice]->PWM0CTL = nControl; + adi_tmr_registers[eDevice]->PWM0MATCH = pwmConfig.nMatchValue; + /* IF(PWM output 1) */ + } else if (pwmConfig.eOutput == ADI_TMR_PWM_OUTPUT_1) { + adi_tmr_registers[eDevice]->PWM1CTL = nControl; + adi_tmr_registers[eDevice]->PWM1MATCH = pwmConfig.nMatchValue; + /* ELSE(PWM output 2) */ + } else { + adi_tmr_registers[eDevice]->PWM2CTL = nControl; + adi_tmr_registers[eDevice]->PWM2MATCH = pwmConfig.nMatchValue; + } /* ENDIF */ + + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Enable or Disable the GP or RGB Timer + * + * @details Start or stop the timer. + * + * @param [in] eDevice : Device number + * + * @param [in] bEnable : True to enable, false to disable + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_DEVICE_BUSY Timer is busy processing a previous control register write + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_Enable(ADI_TMR_DEVICE const eDevice, bool bEnable) { +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ +#endif + /* IF(Busy bit does not clear after waiting) */ + if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_BUSY)) { + return ADI_TMR_DEVICE_BUSY; + } /* ENDIF */ + + /* Clear the enable bit and keep the other bits */ + adi_tmr_registers[eDevice]->CTL &= (uint16_t) ~BITM_TMR_RGB_CTL_EN; + + /* IF(Turning the timer on) */ + if (bEnable == true) { + adi_tmr_registers[eDevice]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EN; + } /* ENDIF */ + + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Get GP or RGB Timer Current Count + * + * @details Read the timer. + * + * @param [in] eDevice : Device number + * + * @param [out] pCount : Pointer to the result. + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_NULL_POINTER [D] Invalid pCount parameter supplied + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_GetCurrentCount(ADI_TMR_DEVICE const eDevice, uint16_t *pCount) { +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(Null pointer) */ + if (pCount == NULL) { + return ADI_TMR_NULL_POINTER; + } /* ENDIF */ +#endif + *pCount = adi_tmr_registers[eDevice]->CURCNT; + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Get GP or RGB Timer Captured Count + * + * @details Read the captured timer value. This should be called after the callback function + * is called with #ADI_TMR_EVENT_CAPTURE in the Event field. + * + * @param [in] eDevice : Device number + * + * @param [out] pCount : Pointer to the result. + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_NULL_POINTER [D] Invalid pCount parameter supplied + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_GetCaptureCount(ADI_TMR_DEVICE const eDevice, uint16_t *pCount) { +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(Null pointer) */ + if (pCount == NULL) { + return ADI_TMR_NULL_POINTER; + } /* ENDIF */ +#endif + *pCount = adi_tmr_registers[eDevice]->CAPTURE; + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Reload GP or RGB Timer + * + * @details Only relevent in peridic mode and when bReloading was set to + * true when configuring the timer. Calling this function will + * reload (i.e. reset) the timer to the LOAD value. + * + * @param [in] eDevice : Device number + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_RELOAD_DISABLED [D] Reloading not enabled for this timer + * - #ADI_TMR_DEVICE_BUSY Reload did not take effect in time + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_Reload(ADI_TMR_DEVICE const eDevice) { +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(Reloading has not been enabled) */ + if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_RLD) != BITM_TMR_RGB_CTL_RLD) { + return ADI_TMR_RELOAD_DISABLED; + } /* ENDIF */ +#endif + /* Clear the timeout bit to cause a reload to happen */ + adi_tmr_registers[eDevice]->CLRINT = BITM_TMR_RGB_CLRINT_TIMEOUT; + /* IF(The clear interrupt does not take effect in a reasonable amount of time) */ + if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_PDOK)) { + return ADI_TMR_DEVICE_BUSY; + } /* ENDIF */ + return ADI_TMR_SUCCESS; +} + + +/********************************************************************************* + PRIVATE FUNCTIONS +*********************************************************************************/ + + /*! \cond PRIVATE */ + +static ADI_TMR_RESULT WaitForStatusBit(ADI_TMR_DEVICE const eDevice, uint16_t nBusyBit) { + /* FOR(Number of arbitrary iterations) */ + for (uint16_t i = 0u; i < 1000u; i++) { + /* IF(Busy bit is low) */ + if ((adi_tmr_registers[(eDevice)]->STAT & nBusyBit) == ((uint16_t) 0u)) { + return ADI_TMR_SUCCESS; + } /* ENDIF */ + } /* ENDFOR */ + return ADI_TMR_DEVICE_BUSY; +} + +static void CommonIntHandler(ADI_TMR_DEVICE const eDevice) { + /* Read status register */ + uint16_t IntStatus = adi_tmr_registers[eDevice]->STAT; + /* IF(Callback function has been set) */ + if(adi_tmr_callbacks[eDevice] != NULL) { + /* IF(Timeout interrupt occurred) */ + if((IntStatus & ((uint16_t) BITM_TMR_RGB_STAT_TIMEOUT)) != ((uint16_t) 0u)) { + adi_tmr_callbacks[eDevice](adi_tmr_parameters[eDevice], ADI_TMR_EVENT_TIMEOUT, NULL); + } /* ENDIF */ + /* IF(Event capture interrupt occurred) */ + if((IntStatus & ((uint16_t) BITM_TMR_RGB_STAT_CAPTURE)) != ((uint16_t) 0u)) { + adi_tmr_callbacks[eDevice](adi_tmr_parameters[eDevice], ADI_TMR_EVENT_CAPTURE, NULL); + } /* ENDIF */ + } /* ENDIF */ + /* Clear pending interrupt */ + adi_tmr_registers[eDevice]->CLRINT = (BITM_TMR_RGB_CLRINT_EVTCAPT | BITM_TMR_RGB_CLRINT_TIMEOUT); +} + +void GP_Tmr0_Int_Handler(void) { + ISR_PROLOG() + CommonIntHandler(ADI_TMR_DEVICE_GP0); + ISR_EPILOG() +} + +void GP_Tmr1_Int_Handler(void) { + ISR_PROLOG() + CommonIntHandler(ADI_TMR_DEVICE_GP1); + ISR_EPILOG() +} + +void GP_Tmr2_Int_Handler(void) { + ISR_PROLOG() + CommonIntHandler(ADI_TMR_DEVICE_GP2); + ISR_EPILOG() +} + +void RGB_Tmr_Int_Handler(void) { + ISR_PROLOG() + CommonIntHandler(ADI_TMR_DEVICE_RGB); + ISR_EPILOG() +} + +/*! \endcond */ + +/*! @} */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr_data.c new file mode 100755 index 0000000000..7cf4a8295e --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr_data.c @@ -0,0 +1,155 @@ +/*! ***************************************************************************** + * @file adi_tmr_data.c + * @brief GP and RGB timer static configuration data + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifndef ADI_TMR_DATA +#define ADI_TMR_DATA + + +#include +#include +#include + + +/* CTL register static configuration */ +static uint16_t aTimerCtlConfig[] = +{ + (TMR0_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) | + (TMR0_CFG_MODE << BITP_TMR_RGB_CTL_MODE) | + (TMR0_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | + (TMR0_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) | + (TMR0_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) | + (TMR0_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) | + (TMR0_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) | + (TMR0_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN), + + (TMR1_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) | + (TMR1_CFG_MODE << BITP_TMR_RGB_CTL_MODE) | + (TMR1_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | + (TMR1_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) | + (TMR1_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) | + (TMR1_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) | + (TMR1_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) | + (TMR1_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN), + + (TMR2_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) | + (TMR2_CFG_MODE << BITP_TMR_RGB_CTL_MODE) | + (TMR2_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | + (TMR2_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) | + (TMR2_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) | + (TMR2_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) | + (TMR2_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) | + (TMR2_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN), + + (TMR3_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) | + (TMR3_CFG_MODE << BITP_TMR_RGB_CTL_MODE) | + (TMR3_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | + (TMR3_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) | + (TMR3_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) | + (TMR3_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) | + (TMR3_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) | + (TMR3_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN), +}; + +/* LOAD register static configuration */ +static uint16_t aTimerLoadConfig[] = +{ + TMR0_CFG_LOAD_VALUE, + TMR1_CFG_LOAD_VALUE, + TMR2_CFG_LOAD_VALUE, + TMR3_CFG_LOAD_VALUE, +}; + +/* Asynchronous LOAD static configuraton */ +static uint16_t aTimerALoadConfig[] = +{ + TMR0_CFG_ASYNC_LOAD_VALUE, + TMR1_CFG_ASYNC_LOAD_VALUE, + TMR2_CFG_ASYNC_LOAD_VALUE, + TMR3_CFG_ASYNC_LOAD_VALUE, +}; + +/* EVENTSELECT static configuration */ +static uint16_t aTimerEventConfig[] = +{ + TMR0_CFG_EVENT_CAPTURE, + TMR1_CFG_EVENT_CAPTURE, + TMR2_CFG_EVENT_CAPTURE, + TMR3_CFG_EVENT_CAPTURE, +}; + +/* PWM CTL static configuration */ +static uint16_t aTimerPwmCtlConfig[] = +{ + (TMR0_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) | + (TMR0_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH), + + (TMR1_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) | + (TMR1_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH), + + (TMR2_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) | + (TMR2_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH), + + (TMR3_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) | + (TMR3_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH), + + (TMR3_CFG_PWM1_IDLE_STATE << BITP_TMR_RGB_PWM1CTL_IDLESTATE) | + (TMR3_CFG_PWM1_MATCH_VALUE << BITP_TMR_RGB_PWM1CTL_MATCH), + + (TMR3_CFG_PWM2_IDLE_STATE << BITP_TMR_RGB_PWM2CTL_IDLESTATE) | + (TMR3_CFG_PWM2_MATCH_VALUE << BITP_TMR_RGB_PWM2CTL_MATCH), +}; + +/* PWM MATCH static configuration */ +static uint16_t aTimerPwmMatchConfig[] = { + TMR0_CFG_PWM0_MATCH_VALUE, + TMR1_CFG_PWM0_MATCH_VALUE, + TMR2_CFG_PWM0_MATCH_VALUE, + TMR3_CFG_PWM0_MATCH_VALUE, + TMR3_CFG_PWM1_MATCH_VALUE, + TMR3_CFG_PWM2_MATCH_VALUE +}; + + +#endif /* ADI_TMR_DATA */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c new file mode 100755 index 0000000000..d1f72d6048 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c @@ -0,0 +1,2779 @@ +/*! ***************************************************************************** + * @file: adi_uart.c + * @brief: uart device driver implementation + * @details: This file contains the UART device driver functions + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/** @addtogroup UART_Driver + * @{ + * @brief UART Driver + * @note The application must include drivers/uart/adi_uart.h to use this + * driver + * @note This driver requires the DMA driver.The application must + * include the DMA driver sources to avoid link errors. + */ + +/*! \cond PRIVATE */ +#include +#include +#include "adi_uart_def.h" +#include + + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm50: (MISRA C 2004 rule 14.3): a null statement shall only occur on a line by itself, +* and shall not have any other text on the same line +* Some Macros, such as ISR_PROLOGUE, may not have any expansion +* resulting in just the terminating ';'. +* +* Pm073 (rule 14.7): A function should have a single point of exit. +* Pm143 (rule 14.7): A function should have a single point of exit at the end of the function. +* Multiple returns are used for error handling. +* +* Pm088 (rule 17.4): Pointer arithmetic should not be used. +* Relying on pointer arithmetic for buffer handling. +* +* Pm123 (rule 18.5): There shall be no definition of objects in a header file. +* +* Pm140 (rule 11.3): A cast should not be performed between a pointer type and an integral type. +* MMR addresses are defined as simple constants. Accessing the MMR requires casting to a pointer type. +* +* Pm152 (rule 17.4): Array indexing shall only be applied to objects defined as an array type. +* Relying on pointer arithmetic for buffer handling and +* Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors. +* +* Pm008: Code should not be commented out. + This code was commented out to show what the autobaud equations would look like if there were floating point precision. + Ideally this would be the case but for the sake of footprint size we will leave it at single point precision. +*/ +#pragma diag_suppress=Pm050,Pm073,Pm088,Pm123,Pm140,Pm143,Pm152,Pm008 +#endif /* __ICCARM__ */ + + + + +/********************************************************** + * UART Data + **********************************************************/ +static ADI_UART_DEVICE_INFO uart_device_info[ ] = +{ + { + UART0_TX_CHANn, /*!< DMA channel number for UART0 Tx. */ + UART0_RX_CHANn, /*!< DMA channel number for UART0 Rx. */ + DMA0_CH8_DONE_IRQn, /*!< DMA channel IRQ for UART0 Tx. */ + DMA0_CH9_DONE_IRQn, /*!< DMA channel IRQ for UART0 Rx. */ + (IRQn_Type)INTR_UART0_EVT, /*!< UART0 interrupt ID. */ + pADI_UART0, /*!< Start address of UART0. */ + NULL /*!< Device Handle for UART0. */ + }, + { + UART1_TX_CHANn, /*!< DMA channel number for UART1 Tx. */ + UART1_RX_CHANn, /*!< DMA channel number for UART1 Rx. */ + DMA0_CH25_DONE_IRQn, /*!< DMA channel IRQ for UART1 Tx. */ + DMA0_CH26_DONE_IRQn, /*!< DMA channel IRQ for UART1 Rx. */ + (IRQn_Type)INTR_UART1_EVT, /*!< UART1 interrupt ID. */ + pADI_UART1, /*!< Start address of UART1. */ + NULL /*!< Device Handle for UART1. */ + }, +}; + +static const ADI_UART_CONFIG gUARTCfg[ ] = +{ + { + /* Line control register. */ + ((ADI_UART0_CFG_WORD_LENGTH << BITP_UART_LCR_WLS) | + (ADI_UART0_CFG_STOP_BIT << BITP_UART_LCR_STOP) | + (ADI_UART0_CFG_ENABLE_PARITY << BITP_UART_LCR_PEN) | + (ADI_UART0_CFG_PARITY_SELECTION << BITP_UART_LCR_EPS) | + (ADI_UART0_CFG_ENABLE_STICKY_PARITY << BITP_UART_LCR_SP)), + + /* Div-C in baudrate divider register. */ + ADI_UART0_CFG_DIVC, + + /* Div-M and Div-N in fractional baudrate Register. */ + (((uint32_t)ADI_UART0_CFG_DIVN << BITP_UART_FBR_DIVN) | + ((uint32_t)ADI_UART0_CFG_DIVM << BITP_UART_FBR_DIVM) | + ((uint32_t)BITM_UART_FBR_FBEN)), + + /* Over sample rate in second line control register. */ + ADI_UART0_CFG_OSR, + + /* FIFO control register. */ + ((ADI_UART0_CFG_ENABLE_FIFO << BITP_UART_FCR_FIFOEN)| + (ADI_UART0_CFG_TRIG_LEVEL << BITP_UART_FCR_RFTRIG)), + + /* Half duplex control register. */ + ((ADI_UART0_CFG_SOUT_POLARITY << BITP_UART_RSC_OENP) | + (ADI_UART0_CFG_DEASSERTION << BITP_UART_RSC_OENSP) | + (ADI_UART0_CFG_DISABLE_RX << BITP_UART_RSC_DISRX) | + (ADI_UART0_CFG_HOLD_TX << BITP_UART_RSC_DISTX)), + + /* Interrupt enable register. */ + ((ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT << BITP_UART_IEN_EDSSI) | + (ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT << BITP_UART_IEN_ELSI)) + + }, + + { + /* Line control register. */ + ((ADI_UART1_CFG_WORD_LENGTH << BITP_UART_LCR_WLS) | + (ADI_UART1_CFG_STOP_BIT << BITP_UART_LCR_STOP) | + (ADI_UART1_CFG_ENABLE_PARITY << BITP_UART_LCR_PEN) | + (ADI_UART1_CFG_PARITY_SELECTION << BITP_UART_LCR_EPS) | + (ADI_UART1_CFG_ENABLE_STICKY_PARITY << BITP_UART_LCR_SP)), + + /* Div-C in Baudrate divider register. */ + ADI_UART1_CFG_DIVC, + + /* Div-M and Div-N in fractional baudrate Register. */ + (((uint32_t)ADI_UART1_CFG_DIVN << BITP_UART_FBR_DIVN) | + ((uint32_t)ADI_UART1_CFG_DIVM << BITP_UART_FBR_DIVM) | + ((uint32_t)BITM_UART_FBR_FBEN)), + + /* Over sample rate in second line control register. */ + ADI_UART1_CFG_OSR, + + /* FIFO control register. */ + ((ADI_UART1_CFG_ENABLE_FIFO << BITP_UART_FCR_FIFOEN)| + (ADI_UART1_CFG_TRIG_LEVEL << BITP_UART_FCR_RFTRIG)), + + /* Half duplex control register. */ + ((ADI_UART1_CFG_SOUT_POLARITY << BITP_UART_RSC_OENP) | + (ADI_UART1_CFG_DEASSERTION << BITP_UART_RSC_OENSP) | + (ADI_UART1_CFG_DISABLE_RX << BITP_UART_RSC_DISRX) | + (ADI_UART1_CFG_HOLD_TX << BITP_UART_RSC_DISTX)), + + /* Interrupt enable register. */ + ((ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT << BITP_UART_IEN_EDSSI) | + (ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT << BITP_UART_IEN_ELSI)) + } +}; + +/*! \endcond */ + +/*! Number of UART devices available on the chip. */ +#define ADI_UART_NUM_DEVICES (sizeof(uart_device_info)/sizeof(ADI_UART_DEVICE_INFO)) + +/* Override "weak" default binding in startup.c */ +/*! \cond PRIVATE */ +extern void UART0_Int_Handler(void); +extern void UART1_Int_Handler(void); +extern void DMA_UART0_TX_Int_Handler(void); +extern void DMA_UART0_RX_Int_Handler(void); +extern void DMA_UART1_TX_Int_Handler(void); +extern void DMA_UART1_RX_Int_Handler(void); + +/* Internal DMA Callback for receiving DMA faults from common DMA error handler. */ +static void RxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg); +static void RxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) { + + /* Recover the device handle. */ + ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)pCBParam; + ADI_UART_BUFF_INFO * pNextBuff = hDevice->pChannelRx->pFillBuffer->pNextBuffer; + uint32_t nEvent = 0u; + + /* Save the DMA error. */ + switch (Event) { + case ADI_DMA_EVENT_ERR_BUS: + nEvent |= (uint32_t)ADI_UART_HW_ERR_RX_CHAN_DMA_BUS_FAULT; + break; + case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR: + nEvent |= (uint32_t)ADI_UART_HW_ERR_RX_CHAN_DMA_INVALID_DESCR; + break; + default: + nEvent |= (uint32_t)ADI_UART_HW_ERR_RX_CHAN_DMA_UNKNOWN_ERROR; + break; + } + + if((pNextBuff->pStartAddress != NULL) && (pNextBuff->bDMA == true)) + { + hDevice->nHwError |= nEvent; + pNextBuff->bInUse = false; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED); + + } + hDevice->nHwError |= nEvent; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED); +} + +static void TxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg); +static void TxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) { + + /* Recover the device handle. */ + ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)pCBParam; + ADI_UART_BUFF_INFO * pNextBuff = hDevice->pChannelTx->pFillBuffer->pNextBuffer; + uint32_t nEvent = 0u; + + /* Save the DMA error. */ + switch (Event) { + case ADI_DMA_EVENT_ERR_BUS: + nEvent |= (uint32_t)ADI_UART_HW_ERR_TX_CHAN_DMA_BUS_FAULT; + break; + case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR: + nEvent |= (uint32_t)ADI_UART_HW_ERR_TX_CHAN_DMA_INVALID_DESCR; + break; + default: + nEvent |= (uint32_t)ADI_UART_HW_ERR_TX_CHAN_DMA_UNKNOWN_ERROR; + break; + } + if((pNextBuff->pStartAddress != NULL) && (pNextBuff->bDMA == true)) + { + hDevice->nHwError |= nEvent; + pNextBuff->bInUse = false; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED); + + } + + hDevice->nHwError |= nEvent; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED); +} +/*! \endcond */ + +/********************************************************** + * General UART APIs + **********************************************************/ + +/*! + * @brief Initialization function for the UART device. + * @details Opens the specified UART device. This function must be called before operating any UART device. + * + * + * @param [in] nDeviceNum UART device instance to be opened. + * @param [in] eDirection Direction of the UART operation. (i.e Rx or Tx) + * @param [in] pMemory Pointer to a 32 bit aligned buffer the size of #ADI_UART_UNIDIR_MEMORY_SIZE + * or #ADI_UART_BIDIR_MEMORY_SIZE. + * @param [in] nMemSize Size of the buffer to which "pMemory" points. This will vary based on + * direction of operation for this device instance. (i.e Rx and Tx, Rx, Tx) + * + * @param [out] phDevice The caller's device handle pointer for storing the initialized device instance data pointer. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully initialized UART device. + * - #ADI_UART_SEMAPHORE_FAILED Failed to create semaphore. + * - #ADI_UART_INVALID_DEVICE_NUM [D] Device instance is invalid. + * - #ADI_UART_INSUFFICIENT_MEMORY [D] Supplied memory is insufficient for the operation of specified UART device. + * - #ADI_UART_DEVICE_IN_USE [D] Device is already open. + * + * @sa adi_uart_Close() + * + * @note: Memory supplied by the API will be used by the driver for managing the UART device. This memory can be reused once + * device is closed. + * + */ +ADI_UART_RESULT adi_uart_Open( + uint32_t const nDeviceNum, + ADI_UART_DIRECTION const eDirection, + void *pMemory, + uint32_t const nMemSize, + ADI_UART_HANDLE *const phDevice + ) +{ +#ifdef ADI_DEBUG + /* Check if the given device number is within the range of UART + * devices present in the processor. There are two devices present here + * so this can be a 0 or 1. + */ + if(nDeviceNum >= ADI_UART_NUM_DEVICES) + { + return(ADI_UART_INVALID_DEVICE_NUM); + } + + /* Verify the device is not already open. */ + if(uart_device_info[nDeviceNum].hDevice != NULL) + { + return(ADI_UART_DEVICE_IN_USE); + } + + /* Make sure there is enough memory for the device instance to operate in a single direction. */ + if(eDirection != ADI_UART_DIR_BIDIRECTION) + { + if(nMemSize < (uint32_t)ADI_UART_UNIDIR_MEMORY_SIZE) + { + return(ADI_UART_INSUFFICIENT_MEMORY); + } + assert(nMemSize == (sizeof(ADI_UART_DEVICE) + sizeof(ADI_UART_DATA_CHANNEL))); + } + + /* Make sure there is enough memory for the device instance to operate in both directions. */ + else + { + if(nMemSize < (uint32_t)ADI_UART_BIDIR_MEMORY_SIZE) + { + return(ADI_UART_INSUFFICIENT_MEMORY); + } + assert(nMemSize == (sizeof(ADI_UART_DEVICE) + (sizeof(ADI_UART_DATA_CHANNEL)*2u))); + } +#endif /* ADI_DEBUG */ + + /* Initialize the device handle to NULL in case of a failure. */ + *phDevice = NULL; + + /* Link the ADI_UART_HANDLE to the ADI_UART_DEVICE structure. */ + ADI_UART_HANDLE hDevice = pMemory; + + /* Zero the device handle memory so we do not have to explicitely initialize + the structure members to 0. + */ + memset(pMemory, 0, nMemSize); + + + /* Set the device information. */ + hDevice->pUartInfo = &uart_device_info[nDeviceNum]; + + /* Set the base of the UART register address. We do this to minimize + the cycle count when accessing the UART registers. + */ + hDevice->pUARTRegs = uart_device_info[nDeviceNum].pUartRegs; + + /* Store the direction that this device will operate in. */ + hDevice->eDirection = eDirection; + + /* Increment the device handle with the size of the UART device structure + so we can set the channel data next without overwriting + the #ADI_UART_DEVICE data. + */ + pMemory = ((uint8_t *)pMemory +(sizeof(ADI_UART_DEVICE))); + + /* Set up the DMA Controller. */ + adi_dma_Init(); + + /* Initialize the TX-channel. */ + if(ADI_UART_DIR_RECEIVE != eDirection) + { + hDevice->pChannelTx = (ADI_UART_DATA_CHANNEL *)pMemory; + + /* Initialize the data transfer mode. */ + hDevice->pChannelTx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE; + + /* Initialize Tx buffer pointers. */ + hDevice->pChannelTx->pFreeBuffer = &hDevice->pChannelTx->PingPong[0]; + hDevice->pChannelTx->pActiveBuffer = &hDevice->pChannelTx->PingPong[0]; + hDevice->pChannelTx->pFillBuffer = &hDevice->pChannelTx->PingPong[0]; + + + /* Create a "semaphore" (varies per OS) used for blocking buffer resource management. */ + SEM_CREATE(hDevice->pChannelTx, "UART_TX_SEM", ADI_UART_SEMAPHORE_FAILED); + + /* Set submit buffer function pointer. */ + hDevice->pChannelTx->pfSubmitBuffer = &uart_submittxbuffer; + + hDevice->pChannelTx->PingPong[0].pNextBuffer = &hDevice->pChannelTx->PingPong[1]; + hDevice->pChannelTx->PingPong[1].pNextBuffer = &hDevice->pChannelTx->PingPong[0]; + + /*Register DMA Callback. */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pUartInfo->dmaTxChannelNum, TxDmaErrorCallback, (void*)hDevice)) + { + adi_uart_Close(hDevice); + return ADI_UART_ERR_DMA_REGISTER; + } + + /* Increment the device handle the size of #ADI_UART_DATA_CHANNEL + structure in case there is another channel to configure. + */ + pMemory = ((uint8_t *)pMemory + sizeof(ADI_UART_DATA_CHANNEL)); + } + /* Initialize the RX-channel. */ + if(ADI_UART_DIR_TRANSMIT != eDirection) + { + hDevice->pChannelRx = (ADI_UART_DATA_CHANNEL *)pMemory; + + /* Initialize the data transfer mode. */ + hDevice->pChannelRx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE; + + /* Initialize Rx buffer pointers. */ + hDevice->pChannelRx->pFreeBuffer = &hDevice->pChannelRx->PingPong[0]; + hDevice->pChannelRx->pActiveBuffer = &hDevice->pChannelRx->PingPong[0]; + hDevice->pChannelRx->pFillBuffer = &hDevice->pChannelRx->PingPong[0]; + + /* Create a "semaphore" (varies per OS) used for blocking buffer resource management. */ + SEM_CREATE(hDevice->pChannelRx, "UART_RX_SEM", ADI_UART_SEMAPHORE_FAILED); + + /* Set submit buffer function pointer. */ + hDevice->pChannelRx->pfSubmitBuffer = &uart_submitrxbuffer; + + hDevice->pChannelRx->PingPong[0].pNextBuffer = &hDevice->pChannelRx->PingPong[1]; + hDevice->pChannelRx->PingPong[1].pNextBuffer = &hDevice->pChannelRx->PingPong[0]; + + /*Register DMA Callback. */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pUartInfo->dmaRxChannelNum, RxDmaErrorCallback, (void*)hDevice)) + { + adi_uart_Close(hDevice); + return ADI_UART_ERR_DMA_REGISTER; + } + } + + /* Initialize the device with the static config values.*/ + uart_init(hDevice, nDeviceNum); + + /* Write the device data pointer to the application's handle. */ + *phDevice = hDevice; + + /* Store the device handle. */ + uart_device_info[nDeviceNum].hDevice = hDevice; + + + /* Enable UART Interrupt. */ + NVIC_ClearPendingIRQ(hDevice->pUartInfo->eIRQn); + NVIC_EnableIRQ(hDevice->pUartInfo->eIRQn); + + /* Enable the interrupt for the DMA. */ + NVIC_EnableIRQ(hDevice->pUartInfo->eDMATx); + NVIC_EnableIRQ(hDevice->pUartInfo->eDMARx); + + /* Return SUCCESS */ + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Uninitialize the memory for the specified UART instance. + * + * @param [in] hDevice UART device handle whose operation is to be closed. This handle was obtained when the UART + * device instance was opened successfully. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully closed the UART device instance. + * - #ADI_UART_SEMAPHORE_FAILED Failed to delete the semaphore. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_DEVICE_IN_USE [D] Specified UART device is in the process of a transaction or autobaud has not completed. + * + * @details Closes the operation of specified UART device. Device needs to be opened again for any further use. + * + * @sa adi_uart_Open() + * + * @note: It is the user's responsibility to free/reuse the memory supplied during the opening of the device. + */ +ADI_UART_RESULT adi_uart_Close( + ADI_UART_HANDLE const hDevice + ) +{ +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Make sure there are no active buffers on any active channel, autobaud is not in progress and the + Tx shift register is completely empty. This can be an issue if you submitted a nonblocking transmit + because you will receive interrupt before the hardware has fully finished the transaction. The start + address of the active buffer will remain in use until the buffer has been completely processed. + Therefore if the start address is NULL it means it has not been submitted for a transaction. + */ + if(((hDevice->pUARTRegs->LSR & BITM_UART_LSR_TEMT) != BITM_UART_LSR_TEMT) || + ((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pFillBuffer->pStartAddress != NULL)) || + ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pFillBuffer->pStartAddress != NULL)) || + (hDevice->bAutobaudInProgress == true)) + { + return(ADI_UART_DEVICE_IN_USE); + } +#endif /* ADI_DEBUG */ + + /* Disable UART status interrupts. */ + hDevice->pUARTRegs->IEN = 0x00U; + + /* Disable DMA UART interrupts. */ + NVIC_DisableIRQ(hDevice->pUartInfo->eDMARx); + NVIC_DisableIRQ(hDevice->pUartInfo->eDMATx); + + /* Disable UART event interrupt. */ + NVIC_DisableIRQ(hDevice->pUartInfo->eIRQn); + + /* Delete Tx-Channel semaphore. */ + if(hDevice->eDirection != ADI_UART_DIR_RECEIVE) + { + SEM_DELETE(hDevice->pChannelTx, ADI_UART_SEMAPHORE_FAILED); + } + + /* Delete Rx-Channel semaphore. */ + if(hDevice->eDirection != ADI_UART_DIR_TRANSMIT) + { + SEM_DELETE(hDevice->pChannelRx, ADI_UART_SEMAPHORE_FAILED); + } + + /* Free up the device memory. */ + hDevice->pUartInfo->hDevice = NULL; + + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Submit a "filled" buffer for transmitting data in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * This function sets up the apropriate interrupts associated with the transaction and marks + * the buffer as submitted. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pBuffer Pointer to data supplied by the API that is to be transmitted. + * @param [in] nBufSize Size of the buffer to be transmitted(in bytes). Must be smaller than 1024 bytes for DMA transfers. + * @param [in] bDMA Submit the buffer using the DMA flag. + + * + * @return Status + * - #ADI_UART_SUCCESS Successfully submitted the buffer for transmission. + * - #ADI_UART_FAILED [D] Generic failure. In this case the size of the data buffer we are trying + * to submit is NULL. + * - #ADI_UART_INVALID_DATA_TRANSFER_MODE [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. This + * operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Device direction is set up as #ADI_UART_DIR_RECEIVE, so we can not complete + * a transmit operation. The required directions are #ADI_UART_DIR_TRANSMIT or + * #ADI_UART_DIR_BIDIRECTION. + * - #ADI_UART_INVALID_POINTER [D] Pointer to the buffer being submitted is NULL. + * - #ADI_UART_DEVICE_IN_USE [D] Autobaud in progress. + * - #ADI_UART_INVALID_DATA_SIZE [D] DMA transfers must be smaller than 1025 bytes. + * + * @sa adi_uart_IsTxBufferAvailable() + * @sa adi_uart_GetTxBuffer() + * @sa adi_uart_SubmitRxBuffer() + * + * @note: Only one transfer mode (DMA vs. PIO) can be used at once. For example, if you submit a buffer in PIO mode + * and then right away another using the DMA, this transaction will be denied. + * + */ +ADI_UART_RESULT adi_uart_SubmitTxBuffer( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA + ) +{ + +#ifdef ADI_DEBUG + /* Validate the device handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate the pointer to the buffer memory. */ + if(pBuffer == NULL) + { + return(ADI_UART_INVALID_POINTER); + } + + /* Validate the buffer size. */ + if(nBufSize == 0U) + { + return(ADI_UART_FAILED); + } + + /* Autobaud in progress. */ + if(hDevice->bAutobaudInProgress == true) + { + return(ADI_UART_DEVICE_IN_USE); + } + + /* Make sure we are transmitting. */ + if(ADI_UART_DIR_RECEIVE == hDevice->eDirection) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Check the data transfer mode (only allowed in nonblocking mode). */ + if(hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING) + { + return(ADI_UART_INVALID_DATA_TRANSFER_MODE); + } + + /* Check that there is a free buffer to use for this transmit operation. pFreeBuffer + is the next buffer available, so if it is in use we can make the assumption that + there are no buffers available. The start address is set to NULL once the buffer + has finished being processed in "adi_uart_GetBuffer()" or "adi_uart_PendForBuffer()". + */ + if(hDevice->pChannelTx->pFreeBuffer->pStartAddress != NULL) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Make sure the DMA transfer size is not too large. */ + if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT)) + { + return(ADI_UART_INVALID_DATA_SIZE); + } + +#endif /* ADI_DEBUG */ + + /* Set the start address of the data buffer we are going to submit. */ + hDevice->pChannelTx->pFreeBuffer->pStartAddress = pBuffer; + + /* Set the buffer size to the size of the data buffer passed down from the API. */ + hDevice->pChannelTx->pFreeBuffer->nCount = nBufSize; + + /* Initialize the buffer index to zero because we will start shifting out + the Tx data from the first position of the buffer. + */ + hDevice->pChannelTx->pFreeBuffer->nIndex = 0U; + + /* Mark the buffer as in use so no other transactions can use it until this one is complete. */ + hDevice->pChannelTx->pFreeBuffer->bInUse = true; + + /* Mark the DMA as in use. */ + hDevice->pChannelTx->pFreeBuffer->bDMA = bDMA; + + /* Now that this "pFreeBuffer" is no longer free for use, update the + "pFreeBuffer" to the other PingPong buffer. Because there are only two + buffers in the PingPong structure, this will be the opposite of the one + we just submitted. "pFreeBuffer" will only be updated during the process of + submitting a buffer or a read/write operation. + */ + hDevice->pChannelTx->pFreeBuffer = hDevice->pChannelTx->pFreeBuffer->pNextBuffer; + + /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE. + This will be set back to #ADI_UART_DATA_TRANSFER_MODE_NONE once this + transaction is complete. Then, if a buffer is not currently active, set up the + interrupts for this transaction. Otherwise if a buffer is currently active, + this will be taken care of in the ISR. + */ + if (hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONE) + { + hDevice->pChannelTx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING; + hDevice->pChannelTx->pfSubmitBuffer(hDevice, hDevice->pChannelTx->pFillBuffer); + } + + return(ADI_UART_SUCCESS); + } + +/*! \cond PRIVATE */ + +/* + * @brief This is an internal helper function for adi_uart_SubmitTxBuffer(). It sets up the Tx channel DMA + or device interrupts for the Tx channel to transmit data. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pBuffer Pointer to buffer from where data will be transmitted. + * @param [in] nBufSize Size of the buffer containing the data to be transmitted(in bytes). + * @param [in] bDMA Submit the buffer using the DMA. +*/ +static void uart_submittxbuffer( + ADI_UART_CONST_HANDLE const hDevice, + ADI_UART_BUFF_INFO *const pBuffer + ) +{ + /* If this transmission is using DMA... */ + if (pBuffer->bDMA) + { + /* Enable clear source address decrement for TX channel DMA. */ + pADI_DMA0->SRCADDR_CLR = 1u << (uint32_t)hDevice->pUartInfo->dmaTxChannelNum; + + /* Enable Tx channel DMA. */ + pADI_DMA0->EN_SET = 1u << hDevice->pUartInfo->dmaTxChannelNum; + + /* Enable UART peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1u << hDevice->pUartInfo->dmaTxChannelNum; + + /* Set the primary control data structure as the current DMA descriptor. */ + pADI_DMA0->ALT_CLR = 1u << hDevice->pUartInfo->dmaTxChannelNum; + + /* Fill in the DMA RAM descriptors */ + pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMASRCEND = ((uint32_t)pBuffer->pStartAddress + (uint32_t)(pBuffer->nCount - 1u)); + + pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMADSTEND = (uint32_t)&hDevice->pUARTRegs->TX; + + pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMACDC = ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) | + ((uint32_t)ADI_DMA_INCR_1_BYTE << DMA_BITP_CTL_SRC_INC) | + (ADI_DMA_WIDTH_1_BYTE << DMA_BITP_CTL_SRC_SIZE) | + (0u << DMA_BITP_CTL_R_POWER) | + ((pBuffer->nCount - 1u) << DMA_BITP_CTL_N_MINUS_1) | + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL); + /* Enable UART DMA request interrupt for the Tx channel. */ + hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_EDMAT); + } + else + /* If this transmission is using UART interrupts.. */ + { + /* Enable buffer empty interrupts. */ + hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ETBEI); + } +} + +/*! \endcond */ + +/*! + * @brief Submit an empty buffer for receiving the data in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * This will set up the Rx channel for notification on incoming data using either the DMA + * or UART interrupts, as well as mark the buffer as submitted. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pBuffer Pointer to buffer from that will be filled by the driver when data has been received. + * @param [in] nBufSize Size of the buffer(in bytes). Must be smaller than 1024 bytes for DMA transfers. + * @param [in] bDMA Submit the buffer using DMA flag. + + * + * @return Status + * - #ADI_UART_SUCCESS Successfully submitted the buffer for receiving data. + * - #ADI_UART_FAILED [D] Generic failure. In this case the size of the data buffer we are trying + * to submit is NULL. + * - #ADI_UART_INVALID_DATA_TRANSFER_MODE [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. This + * operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Device direction is set up as #ADI_UART_DIR_TRANSMIT, so we can not complete + * a receive operation. The required directions are #ADI_UART_DIR_RECEIVE or + * #ADI_UART_DIR_BIDIRECTION. + * - #ADI_UART_INVALID_POINTER [D] Pointer to the buffer being submitted is NULL. + * - #ADI_UART_DEVICE_IN_USE [D] Autobaud in progress. + * - #ADI_UART_INVALID_DATA_SIZE [D] DMA transfers must be smaller than 1025 bytes. + * + * @sa adi_uart_IsRxBufferAvailable() + * @sa adi_uart_GetRxBuffer() + * @sa adi_uart_SubmitTxBuffer() + * + * @note: Only one transfer mode (DMA vs. PIO) can be used at once. For example, if you submit a buffer in PIO mode + * and then right away another using the DMA, this transaction will be denied. +*/ +ADI_UART_RESULT adi_uart_SubmitRxBuffer( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA + ) +{ + +#ifdef ADI_DEBUG + /* Validate the device handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate the pointer to the buffer memory. */ + if(pBuffer == NULL) + { + return(ADI_UART_INVALID_POINTER); + } + + /* Validate the buffer size. */ + if(nBufSize == 0U ) + { + return(ADI_UART_FAILED); + } + + /* Autobaud in progress. */ + if(hDevice->bAutobaudInProgress == true) + { + return(ADI_UART_DEVICE_IN_USE); + } + + /* Make sure the UART device is configured to operate in the receive direction. */ + if(ADI_UART_DIR_TRANSMIT == hDevice->eDirection) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Check for the data transfer mode(only allowed in nonblocking mode). */ + if(hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING) + { + return(ADI_UART_INVALID_DATA_TRANSFER_MODE); + } + + /* Check that there is a free buffer to use for this operation. pFreeBuffer + is the next buffer available, so if it is in use we can make the assumption that + there are no buffers available. If the start address is not set to NULL, then we + can conclude the buffer has not finished being processed because this gets set in + adi_uart_pend_for_buffer() and adi_uart_get_buffer(). + */ + if(hDevice->pChannelRx->pFreeBuffer->pStartAddress != NULL) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Make sure the DMA transfer size is not too large. */ + if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT)) + { + return(ADI_UART_INVALID_DATA_SIZE); + } + +#endif /* ADI_DEBUG */ + + /* Set the start address of the buffer you are going to submit. */ + hDevice->pChannelRx->pFreeBuffer->pStartAddress = pBuffer; + + /* Set the size of the buffer. */ + hDevice->pChannelRx->pFreeBuffer->nCount = nBufSize; + + /* Initialize the buffer index to 0, because as we receive data it will be put into + the buffer starting at the first position. + */ + hDevice->pChannelRx->pFreeBuffer->nIndex = 0U; + + /* Mark the buffer as in use. */ + hDevice->pChannelRx->pFreeBuffer->bInUse = true; + + /* Mark the DMA as in use. */ + hDevice->pChannelRx->pFreeBuffer->bDMA = bDMA; + + /* Now that this "pFreeBuffer" is no longer free for use, update the + "pFreeBuffer" to the other PingPong buffer. Because there are only two + buffers in the PingPong structure, this will be the opposite of the one + we just submitted. "pFreeBuffer" will only be updated during the process of + submitting a buffer or a read/write operation. + */ + hDevice->pChannelRx->pFreeBuffer = hDevice->pChannelRx->pFreeBuffer->pNextBuffer; + + + /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE. + This will be set back to #ADI_UART_DATA_TRANSFER_MODE_NONE once this + transaction is complete. Then, if a buffer is not currently active, set up the + interrupts for this transaction. Otherwise if a buffer is currently active, + this will be taken care of in the ISR. + */ + if (hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONE) + { + hDevice->pChannelRx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING; + hDevice->pChannelRx->pfSubmitBuffer(hDevice, hDevice->pChannelRx->pFillBuffer); + } + + return(ADI_UART_SUCCESS); +} + +/*! \cond PRIVATE */ + +/* + * @brief This is an internal helper function for adi_uart_SubmitRxBuffer(). It sets up the DMA + * or device receive interrupts for the Rx channel to receive data. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pBuffer Pointer to the empty receive buffer. + * @param [in] nBufSize Size of the receive buffer(in bytes). + * @param [in] bDMA Submit the buffer using the DMA. +*/ +static void uart_submitrxbuffer( + ADI_UART_CONST_HANDLE const hDevice, + ADI_UART_BUFF_INFO *const pBuffer + ) +{ + + + /* If this transaction is using the DMA.. */ + if (pBuffer->bDMA) + { + /* Enable source address decrement for RX DMA channel. */ + pADI_DMA0->DSTADDR_CLR = 1u << (uint32_t)hDevice->pUartInfo->dmaRxChannelNum; + + /* Enable Rx DMA channel. */ + pADI_DMA0->EN_SET = 1u << hDevice->pUartInfo->dmaRxChannelNum; + + /* Enable UART peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1u << hDevice->pUartInfo->dmaRxChannelNum; + + /* Set the primary data structure as the current DMA descriptor. */ + pADI_DMA0->ALT_CLR = 1u << hDevice->pUartInfo->dmaRxChannelNum; + + /* Fill in the DMA RAM descriptors. */ + pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMASRCEND = (uint32_t)&hDevice->pUARTRegs->RX; + + pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMADSTEND = ((uint32_t)pBuffer->pStartAddress + (uint32_t)(pBuffer->nCount - 1u)); + + pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMACDC = (uint32_t)(ADI_DMA_INCR_1_BYTE << DMA_BITP_CTL_DST_INC) | + (uint32_t)(ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) | + (ADI_DMA_WIDTH_1_BYTE << DMA_BITP_CTL_SRC_SIZE) | + (0u << DMA_BITP_CTL_R_POWER) | + ((pBuffer->nCount - 1u) << DMA_BITP_CTL_N_MINUS_1) | + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL); + /* Enable UART receive DMA requests. */ + hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_EDMAR); + } + /* If this transaction is using UART interrupts.. */ + else + { + /* Enable buffer full interrupt. */ + hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ERBFI); + } +} + +/*! \endcond */ + +/*! + * @brief Transfer buffer ownership from the device back to the API if the data + * transmit has completed. Otherwise it will block until completion. + * This allows a nonblocking call to become blocking. + * This function is only called in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] ppBuffer Contains the address of the buffer passed down from the API + * for transmitting data. + * @param [out] pHwError Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status. + * If there is no hardware event, this will be 0. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully returned buffer to the API. + * - #ADI_UART_HW_ERROR_DETECTED Hardware error(s) detected. "pHwError" can be checked for the specific error code(s). + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_BUFFER_NOT_SUBMITTED [D] The buffer has not been submitted to the driver. + * + * @sa adi_uart_IsTxBufferAvailable() + * @sa adi_uart_SubmitTxBuffer() + * + * @note: If the transaction has already completed, this will return immediately rather than block. + */ +ADI_UART_RESULT adi_uart_GetTxBuffer( + ADI_UART_HANDLE const hDevice, + void **const ppBuffer, + uint32_t *pHwError + ) + +{ + +#ifdef ADI_DEBUG + /* Validate the device handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate that this buffer has actually been submitted. */ + if(hDevice->pChannelTx->pActiveBuffer->pStartAddress == NULL) + { + return(ADI_UART_BUFFER_NOT_SUBMITTED); + } + + /* This function is allowed to be called when the channel is operating in NONBLOCKING mode. */ + if(hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } +#endif /* ADI_DEBUG */ + + /* Blocking call to get the submitted buffer */ + return(uart_getbuffer(hDevice, hDevice->pChannelTx, ppBuffer, pHwError)); +} + + + +/*! + * @brief Transfer buffer ownership from the device back to the API if the data + * receive has completed. Otherwise it will block until completion. + * This allows a nonblocking call to become blocking. + * This function is only called in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] ppBuffer Contains the address of the buffer passed down from the API + * for receiving data. + * @param [out] pHwError Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status. + * If there is no hardware event, this will be 0. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully returned buffer to the API. + * - #ADI_UART_HW_ERROR_DETECTED Hardware error(s) detected. "pHwError" can be checked for the specific error code(s). + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_BUFFER_NOT_SUBMITTED [D] The buffer has not been submitted to the driver. + * + * @sa adi_uart_IsRxBufferAvailable() + * @sa adi_uart_SubmitRxBuffer() + * + * @note: If the transaction has already completed, this will return immediately rather than block. +*/ +ADI_UART_RESULT adi_uart_GetRxBuffer( + ADI_UART_HANDLE const hDevice, + void **const ppBuffer, + uint32_t *pHwError + ) + +{ + +#ifdef ADI_DEBUG + /* Validate the device handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate that this buffer has actually been submitted. */ + if(hDevice->pChannelRx->pActiveBuffer->pStartAddress == NULL) + { + return(ADI_UART_BUFFER_NOT_SUBMITTED); + } + + /* This function is only allowed to be called when the channel is operating in NONBLOCKING mode. */ + if(hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } +#endif /* ADI_DEBUG */ + + /* Blocking call to get the full Rx Buffer */ + return(uart_getbuffer(hDevice, hDevice->pChannelRx, ppBuffer, pHwError)); +} + +/*! \cond PRIVATE */ + +/* + * @brief This is an internal helper function for adi_uart_GetRxBuffer() and adi_uart_GetTxBuffer(). + * It blocks until until the completion of the data transaction. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pChannel Pointer to UART channel data structure. + * @param [out] ppBuffer Contains the address of the buffer passed down from the API. + * @param [out] pHwError Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status. + * If there is no hardware event, this will be 0. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully got buffer. + * - #ADI_UART_HW_ERROR_DETECTED Hardware error(s) detected. "pHwError" can be checked for the specific error code(s). + * +*/ +static ADI_UART_RESULT uart_getbuffer( + ADI_UART_HANDLE hDevice, + ADI_UART_DATA_CHANNEL *pChannel, + void **ppBuffer, + uint32_t *pHwError + ) +{ + /* Set ppBuffer to NULL in case there is an error. */ + *ppBuffer = NULL; + + /* Wait until the peripheral has finished processing the buffer. */ + SEM_PEND(pChannel,ADI_UART_FAILED); + + /* Save the address of the buffer that has just been processed, so it can be + returned back to the API. + */ + *ppBuffer = pChannel->pActiveBuffer->pStartAddress; + + /* Reinitialize the start address to NULL so this buffer can be used for a new transaction. */ + pChannel->pActiveBuffer->pStartAddress = NULL; + + /* Now that the desired data has either been transmitted or received, this buffer is no longer + in use. We can update "pActiveBuffer" to point to the next buffer that will become or is already + active. + */ + pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer; + + /* Set the data transfer mode to none so that the next transfer can be either in blocking or in nonblocking mode. + This will only be done if there are no other active buffers in flight to avoid disrupting an active transfer. + */ + if(pChannel->pActiveBuffer->pStartAddress == NULL) + { + pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE; + } + + /* If there are hardware errors and no callback, then return failure. */ + if(hDevice->nHwError != 0u) + { + /* Save the hardware error detected. This will be passed back to the API. */ + *pHwError = hDevice->nHwError; + + /* Clear any hardware errors detected. */ + hDevice->nHwError = 0u; + + return(ADI_UART_HW_ERROR_DETECTED); + } + else + { + return(ADI_UART_SUCCESS); + } +} + +/*! \endcond */ + + +/*! + * @brief Submit the buffer for transmitting the data in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * Call to this function will not return until the entire buffer is transmitted. + * Returns error if this function is called when device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * i.e Function "adi_uart_SubmitTxBuffer()" is called and the transfer is not yet complete. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pBuffer Pointer to data supplied by the API that is to be transmitted. + * @param [in] nBufSize Size of the buffer(in bytes). Must be smaller than 1024 bytes for DMA transfers. + * @param [in] bDMA Submit the buffer using the DMA flag. + * @param [out] pHwError Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status. + * If there is no hardware event, this will be 0. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully transmitted the data from the submitted buffer. + * - #ADI_UART_HW_ERROR_DETECTED Hardware error(s) detected. "pHwError" can be checked for the specific error code(s). + * - #ADI_UART_FAILED [D] Generic failure. In this case the size of the data buffer we are trying + * to submit is NULL. + * - #ADI_UART_INVALID_DATA_TRANSFER_MODE [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. This + * operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Device direction is set up as #ADI_UART_DIR_RECEIVE, so we can not complete + * a transmit operation. The required directions are #ADI_UART_DIR_TRANSMIT or + * #ADI_UART_DIR_BIDIRECTION. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_INVALID_POINTER [D] The pointer to the buffer being submitted is a NULL. + * - #ADI_UART_DEVICE_IN_USE [D] Autobaud in progress. + * - #ADI_UART_INVALID_DATA_SIZE [D] DMA transfers must be smaller than 1025 bytes. + * + * @sa adi_uart_Read() + * @sa adi_uart_SubmitTxBuffer() + * + * @note: This function is a blocking function which means that the function returns only after the completion of + * buffer transmission. +*/ +ADI_UART_RESULT adi_uart_Write( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA, + uint32_t *pHwError + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate the pointer to the buffer memory. */ + if(pBuffer == NULL) + { + return(ADI_UART_INVALID_POINTER); + } + + /* Validate the buffer size. */ + if(nBufSize == 0U ) + { + return(ADI_UART_FAILED); + } + + /* Autobaud in progress. */ + if(hDevice->bAutobaudInProgress == true) + { + return(ADI_UART_DEVICE_IN_USE); + } + + /* Make sure we are transmitting. */ + if(ADI_UART_DIR_RECEIVE == hDevice->eDirection) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Check for the data transfer mode (only allowed in blocking mode). */ + if(hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING) + { + return(ADI_UART_INVALID_DATA_TRANSFER_MODE); + } + + /* Check that there is a free buffer to use for this transmit operation. "pFreeBuffer" + is the next buffer available, so if it is in use we can make the assumption that + there are no buffers available. The start address is set to NULL once the buffer + has been processed. + */ + if(hDevice->pChannelTx->pFreeBuffer->pStartAddress != NULL) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Make sure the DMA transfer size is not too large. */ + if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT)) + { + return(ADI_UART_INVALID_DATA_SIZE); + } + +#endif /* ADI_DEBUG */ + + /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE. */ + hDevice->pChannelTx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_BLOCKING; + + /* Set the start address of the data buffer we are going to submit. */ + hDevice->pChannelTx->pFreeBuffer->pStartAddress = pBuffer; + + /* Set the buffer size to the size of the data buffer passed down from the API. */ + hDevice->pChannelTx->pFreeBuffer->nCount = nBufSize; + + /* Initialize the buffer index to zero because we will start shifting out + the Tx data from the first position of the buffer. + */ + hDevice->pChannelTx->pFreeBuffer->nIndex = 0U; + + /* Mark the buffer as in use so no other transactions can use it until this one is complete. */ + hDevice->pChannelTx->pFreeBuffer->bInUse = true; + + /* Mark the DMA as in use. */ + hDevice->pChannelTx->pFreeBuffer->bDMA = bDMA; + + /* Now that this "pFreeBuffer" is no longer free for use, update the + "pFreeBuffer" to the other PingPong buffer. Because there are only two + buffers in the PingPong structure, this will be the opposite of the one + we just submitted. "pFreeBuffer" will only be updated during the process of + submitting a buffer or a read/write operation. + */ + hDevice->pChannelTx->pFreeBuffer = hDevice->pChannelTx->pFreeBuffer->pNextBuffer; + + hDevice->pChannelTx->pfSubmitBuffer(hDevice, hDevice->pChannelTx->pFillBuffer); + + /* Block for the active buffer to complete. */ + return(uart_PendForBuffer(hDevice, hDevice->pChannelTx, pHwError)); +} + +/*! + * @brief Submit the buffer for reading the data in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. Call to this function will not + * return until the entire buffer is filled up. Returns error if this function is called when + * device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. i.e The function "adi_uart_SubmitRxBuffer()" is called + * when the transfer is not yet complete. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pBuffer Pointer to buffer from that will be filled by the driver when data has been received. + * @param [in] nBufSize Size of the buffer(in bytes). Must be smaller than 1024 bytes for DMA transfers. + * @param [in] bDMA Submit the buffer using DMA flag. + * @param [out] pHwError Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status. + * If there is no hardware event, this will be 0. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully submitted the buffer for receiving data. + * - #ADI_UART_HW_ERROR_DETECTED Hardware error(s) detected. "pHwError" can be checked for the specific error code(s). + * - #ADI_UART_FAILED [D] Generic failure. In this case the size of the data buffer we are trying + * to submit is NULL. + * - #ADI_UART_INVALID_DATA_TRANSFER_MODE [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. This + * operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Device direction is set up as #ADI_UART_DIR_TRANSMIT, so we can not complete + * a receive operation. The required directions are #ADI_UART_DIR_RECEIVE or + * #ADI_UART_DIR_BIDIRECTION. + * - #ADI_UART_INVALID_POINTER [D] Pointer to the buffer being submitted is NULL. + * - #ADI_UART_DEVICE_IN_USE [D] Autobaud in progress. + * - #ADI_UART_INVALID_DATA_SIZE [D] DMA transfers must be smaller than 1025 bytes. + * + * @sa adi_uart_Write() + * @sa adi_uart_SubmitTxBuffer() + * + * @note: This function is a blocking function which means that the function returns only after the completion of + * data receive. +*/ +ADI_UART_RESULT adi_uart_Read( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA, + uint32_t *pHwError + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate the pointer to the buffer memory. */ + if(pBuffer == NULL) + { + return(ADI_UART_INVALID_POINTER); + } + + /* Validate the buffer size. */ + if(nBufSize == 0U ) + { + return(ADI_UART_FAILED); + } + + /* Autobaud in progress. */ + if(hDevice->bAutobaudInProgress == true) + { + return(ADI_UART_DEVICE_IN_USE); + } + + /* Make sure the UART device is configured to operate in the receive direction. */ + if(ADI_UART_DIR_TRANSMIT == hDevice->eDirection) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Check for the data transfer mode(only allowed in blocking mode).*/ + if(hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING) + { + return(ADI_UART_INVALID_DATA_TRANSFER_MODE); + } + + /* Check that there is a free buffer to use for this receive operation. "pFreeBuffer" + is the next buffer available, so if it is in use we can make the assumption that + there are no buffers available. The start address gets set to NULL once the buffer + processing has completed. + */ + if(hDevice->pChannelRx->pFreeBuffer->pStartAddress != NULL) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Make sure the DMA transfer size is not too large. */ + if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT)) + { + return(ADI_UART_INVALID_DATA_SIZE); + } + +#endif /* ADI_DEBUG */ + + /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE. + This will be set back to #ADI_UART_DATA_TRANSFER_MODE_NONE once this + transaction is complete. + */ + hDevice->pChannelRx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_BLOCKING; + + /* Set the start address of the buffer you are going to submit. */ + hDevice->pChannelRx->pFreeBuffer->pStartAddress = pBuffer; + + /* Set the size of the buffer. */ + hDevice->pChannelRx->pFreeBuffer->nCount = nBufSize; + + /* Initialize the buffer index to 0, because as we receive data it will be put into + the buffer starting at the first position. + */ + hDevice->pChannelRx->pFreeBuffer->nIndex = 0U; + + /* Mark the buffer as in use. */ + hDevice->pChannelRx->pFreeBuffer->bInUse = true; + + /* Mark the DMA as in use. */ + hDevice->pChannelRx->pFreeBuffer->bDMA = bDMA; + + + /* Now that this "pFreeBuffer" is no longer free for use, update the + "pFreeBuffer" to the other PingPong buffer. Because there are only two + buffers in the PingPong structure, this will be the opposite of the one + we just submitted. "pFreeBuffer" will only be updated during the process of + submitting a buffer or a read/write operation. + */ + hDevice->pChannelRx->pFreeBuffer = hDevice->pChannelRx->pFreeBuffer->pNextBuffer; + + hDevice->pChannelRx->pfSubmitBuffer(hDevice, hDevice->pChannelRx->pFillBuffer); + + /* Block for the active buffer to complete. */ + return(uart_PendForBuffer(hDevice, hDevice->pChannelRx, pHwError)); +} + +/*! \cond PRIVATE */ + +/* + * @brief Pends for data transaction to complete. Buffer gets returned to API. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pChannel Pointer to UART channel data structure. + * @param [out] pBuffer Address of buffer on which data transfer being carried out. + * @param [out] pHwError Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status. + * If there is no hardware event, this will be 0. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully got buffer. + * - #ADI_UART_HW_ERROR_DETECTED Hardware error(s) detected. "pHwError" can be checked for the specific error code(s). + * +*/ +static ADI_UART_RESULT uart_PendForBuffer( + ADI_UART_HANDLE const hDevice, + ADI_UART_DATA_CHANNEL *pChannel, + uint32_t *pHwError + ) +{ + + /* Wait until the peripheral has finished processing the buffer. */ + SEM_PEND(pChannel,ADI_UART_FAILED); + + /* Reinitialize the start address to NULL so this buffer can be used for a new transaction. */ + pChannel->pActiveBuffer->pStartAddress = NULL; + + /* Now that the desired data has either been transmitted or received, this buffer is no longer + in use. We can update "pActiveBuffer" to point to the next buffer that will become or is already + active. This will only be updated in places where transactions are completed, + such as uart_PendForBuffer() and uart_GetBuffer(). + */ + pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer; + + /* Set the data transfer mode to none so that the next transfer can be either in blocking or in nonblocking mode. + Only if there are no active buffers. + */ + if(pChannel->pActiveBuffer->pStartAddress == NULL) + { + pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE; + } + + /* If there are hardware errors and no callback, then return failure. */ + if(hDevice->nHwError != 0u) + { + /* Save the hardware error detected. This will be passed back to the API. */ + *pHwError = hDevice->nHwError; + + /* Clear any hardware errors detected. */ + hDevice->nHwError = 0u; + + return(ADI_UART_HW_ERROR_DETECTED); + } + else + { + return(ADI_UART_SUCCESS); + } + +} +/*! \endcond */ + + +/*! + * @brief Peek function to know if an empty buffer is avilable. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [out] pbAvailable Pointer to a boolean variable. Contains "true" if there is an empty buffer + * and a call to "adi_uart_GetTxBuffer" is ensured to be successful. Contains + * "false" if there is no empty buffer. + * @return Status + * - #ADI_UART_SUCCESS Successfully retrieved the status of availability of the buffer. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * + * @sa adi_uart_GetTxBuffer() + * @sa adi_uart_IsRxBufferAvailable + * + */ + +ADI_UART_RESULT adi_uart_IsTxBufferAvailable( + ADI_UART_HANDLE const hDevice, + bool *const pbAvailable + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* This function is only allowed to be called when the channel is operating in NONBLOCKING mode. */ + if(hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } +#endif /* ADI_DEBUG */ + + /* Initialize to "false" in case of an error. */ + *pbAvailable = false; + + /* Make sure the buffer has not already been processed. This would mean that there are + currently no active buffers. This is only updated in adi_uart_GetBuffer(), which is + called once a transaction has completed. + */ + if (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL) + { + /* If the buffer has reached the interrupt handler, "bInUse" will be + updated so we know that the buffer has become available. + */ + if (hDevice->pChannelTx->pActiveBuffer->bInUse == false) + { + *pbAvailable = true; + } + } + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Peek function to know if a filled buffer is available. + * + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [out] pbAvailable Pointer to a boolean variable. Contains "true" if there is an empty buffer + * and a call to "adi_uart_GetTxBuffer" is ensured to be successful. Contains + * "false" if there is no empty buffer. + * @return Status + * - #ADI_UART_SUCCESS Successfully retrieved the status of availability of the buffer. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * + * @sa adi_uart_GetRxBuffer() + * + */ +ADI_UART_RESULT adi_uart_IsRxBufferAvailable( + ADI_UART_HANDLE const hDevice, + bool *const pbAvailable + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* This function is only allowed to be called when the channel is operating in NONBLOCKING mode. */ + if(hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } +#endif /* ADI_DEBUG */ + + /* Initialize to "false" in case of an error. */ + *pbAvailable = false; + + /* Make sure the buffer has not already been processed. This would mean that there are + currently no active buffers. This is only updated in adi_uart_GetBuffer(), which is + called once a transaction has completed. + */ + if(hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL) + { + /* If the buffer has reached the interrupt handler, "bInUse" will be + updated so we know that the buffer has become available. + */ + if (hDevice->pChannelRx->pActiveBuffer->bInUse == false) + { + *pbAvailable = true; + } + } + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Function to let the API know if all the data had been drained from the Tx shift registers. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [out] pbComplete Pointer to a boolean variable. Contains "true" if there is no data left in the + * device to transmit and device can be disabled without data loss. Contains "false" + * if the data transmission is not complete. + * @return Status + * - #ADI_UART_SUCCESS Successfully retrieved the status of data transmission. + * - #ADI_UART_INVALID_HANDLE [D] Specified handle is invalid. + * + * @note adi_uart_getTxBuffer() or the callback may indicate that a transmit transaction is complete when the + * device is using the DMA. This is because the interrupt will trigger once the transmit holding register is empty. + However, there may still be a some data in the shift register. If the transmit channel needs + * to be closed then the application must poll the transmit channel to see if all data has indeed been transmitted before + * shutting down the channel. Otherwise data will be lost. + * + */ + +ADI_UART_RESULT adi_uart_IsTxComplete( + ADI_UART_HANDLE const hDevice, + bool *const pbComplete + ) +{ +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + /* Initialize to false. */ + *pbComplete = false; + + /* If the register is empty, set the return variable to "true". + This register is empty, when the value becomes a 1. + */ + if((hDevice->pUARTRegs->LSR & BITM_UART_LSR_TEMT) == BITM_UART_LSR_TEMT) + { + *pbComplete = true; + } + return(ADI_UART_SUCCESS); +} + + +/*! + * @brief Registering a callback function. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pfCallback Function pointer to callback. Passing a NULL pointer will unregister + * the callback function. + * @param [in] pCBParam Callback function parameter. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully registered callback function. + * - #ADI_UART_DEVICE_IN_USE [D] This operation is not allowed when a data transfer is in progress. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * + * +*/ +ADI_UART_RESULT adi_uart_RegisterCallback( + ADI_UART_HANDLE const hDevice, + const ADI_CALLBACK pfCallback, + void *const pCBParam + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Make sure there are no active buffers on any active channel and autobaud is not in progress. */ + if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) || + ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)) || + (hDevice->bAutobaudInProgress == true)) + { + return(ADI_UART_DEVICE_IN_USE); + } +#endif /* ADI_DEBUG */ + + /* Set the device callback. */ + hDevice->pfCallback = pfCallback; + + /* Set the callback parameter. */ + hDevice->pCBParam = pCBParam; + + return(ADI_UART_SUCCESS); +} + + +/*! + * @brief Configuration of UART data. + * + * @details Sets the configuration parameters for the specified UART device such as wordlength, whether to + * enable/disable the parity, and the number of stop bits. This function returns an error if the + * device has active data or autobaud is in progress. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] eParity Specify the type of parity check for the UART device. + * @param [in] eStopBits Specify the stop-bits for the UART device. + * @param [in] eWordLength Specify the word size of the data for the UART device. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully set the data configuration. + * - #ADI_UART_DEVICE_IN_USE [D] This operation is not allowed when a data transfer or autobaud is in progress. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * +*/ +ADI_UART_RESULT adi_uart_SetConfiguration( + ADI_UART_HANDLE const hDevice, + ADI_UART_PARITY const eParity, + ADI_UART_STOPBITS const eStopBits, + ADI_UART_WORDLEN const eWordLength + ) +{ +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Make sure there are no active buffers on any active channel and autobaud is not in progress. */ + if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) || + ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)) || + (hDevice->bAutobaudInProgress == true)) + { + return(ADI_UART_DEVICE_IN_USE); + } +#endif /* ADI_DEBUG */ + + /* Clear all the fields. */ + uint16_t nDataCfg = hDevice->pUARTRegs->LCR & (uint16_t)(~(BITM_UART_LCR_WLS |BITM_UART_LCR_STOP |BITM_UART_LCR_PEN)); + + /* Construct the configuration word. */ + nDataCfg |= (uint16_t)(((uint16_t)((uint16_t)eWordLength |(uint16_t)eStopBits) |(uint16_t)eParity)); + + /* Write to the register */ + hDevice->pUARTRegs->LCR = nDataCfg; + + /* Return Success */ + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Set baudrate by configuring the fractional dividors. + * + * @details Baudrate is calculated as per below equation. + * + * Baudrate = (UARTCLK / (nDivM + nDivN/2048)*pow(2,nOSR+2)* nDivC)). + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] nDivC Specify the "nDivC" in the above equation. + * @param [in] nDivM Specify the "nDivM" in the above equation. + * @param [in] nDivN Specify the "nDivN" in the above equation. + * @param [in] nOSR Specify the "nOSR" " in the above equation. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully set the baudrate for the device. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_DEVICE_IN_USE [D] Device is in use + * - #ADI_UART_INVALID_PARAMETER [D] Input for baud rate values are out of range. + * + * @sa adi_uart_GetBaudRate() + * @sa adi_uart_EnableAutobaud(); + * + * @note It is expected that initialization of the power management + * driver is done before calling this function. + * + */ +ADI_UART_RESULT adi_uart_ConfigBaudRate( + ADI_UART_HANDLE const hDevice, + uint16_t const nDivC, + uint8_t const nDivM, + uint16_t const nDivN, + uint8_t const nOSR + ) +{ +#ifdef ADI_DEBUG + /* Validate the given handle */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Make sure there are no active buffers on any active channel. */ + if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) || + ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL))) + { + return(ADI_UART_DEVICE_IN_USE); + } + + /* Check if the given baudrate is valid */ + if( (nDivM < 1u) || (nDivM > 3u)|| (nDivN > 2047u ) || (nOSR > 3u)) + { + return ADI_UART_INVALID_PARAMETER; + } + +#endif /* ADI_DEBUG */ + + /* Write back the register contents for baudrate detection in the hardware. */ + hDevice->pUARTRegs->DIV = nDivC; + hDevice->pUARTRegs->FBR = (uint16_t)((uint16_t)nDivN | (uint16_t)((uint16_t)nDivM <pUARTRegs->LCR2 = nOSR; + + return(ADI_UART_SUCCESS); +} + + +/*! + * @brief Get the baudrate of the UART device instance. This is used in the scenario when a callback has not been initialized. + * This allows the the API to know if autobaud is complete. If this returns a baudrate other than 0, + * it indicates that the autobaud completed, otherwise autobaud is still in progress. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [out] pnBaudRate Pointer to a location where baudrate is to be written. + * @param [out] pAutobaudError Pointer to an integer that will hold the value of any baudrate error(s), that correlates with + * #ADI_UART_AUTOBAUD_ERRORS. This will be 0 if there are no errors. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully retrieved the baudrate. + * - #ADI_UART_AUTOBAUD_ERROR_DETECTED There has been an autobaud error. The API can get the specific error(s) + * by checking "pAutobaudError". + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_INVALID_POINTER [D] The pointer to baudrate or autobaud error is NULL. + + * +*/ +ADI_UART_RESULT adi_uart_GetBaudRate( + ADI_UART_HANDLE const hDevice, + uint32_t *pnBaudRate, + uint32_t *pAutobaudError + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate pointers. */ + if(pnBaudRate == NULL) + { + return(ADI_UART_INVALID_POINTER); + } + +#endif /* ADI_DEBUG */ + + /* If an error occured during autobaud this value will be set to a + non-zero value. The specific error can be found by checking against + #ADI_UART_EVENT. + */ + if(hDevice->nAutobaudError != 0u) + { + /* Save the autobaud error to pass back to the API.*/ + *pAutobaudError = hDevice->nAutobaudError; + + /* Clear the autobaud errors found. */ + hDevice->nAutobaudError = 0u; + + return(ADI_UART_AUTOBAUD_ERROR_DETECTED); + } + + /* Return the baudrate. If this is 0, then autobaud has not completed. */ + *pnBaudRate = hDevice->nBaudRate; + + return(ADI_UART_SUCCESS); +} + + +/*! + * @brief Enable/Disable UART autobaud detection as well as configures the device for autobaud detection. + * + * @details The baud rate is detected using the hardware support. + * After the baud rate is detected the interrupt handler is notified of the completion. + * When a callback is not registered with UART driver, the API adi_uart_GetBaudRate() + * can be used to know if autobaud is complete. Autobaud needs to be disabled in order to + * clear the internal counter and to close the device. + * + * @param [in] hDevice Handle to UART device whose autobaud detection to be enabled/disabled. + * @param [in] bEnable Boolean flag to indicate whether to enable or disable the autobaud. + * @param [in] bAutobaudCallbackMode Use a callback to report autobaud errors or type #ADI_UART_AUTOBAUD_ERRORS. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully enabled/disabled Autobaud detection. + * - #ADI_UART_DEVICE_IN_USE [D] Trying to enable/disable Autobaud when + * dataflow is enabled or autobaud is in progress. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * + * @sa adi_uart_GetBaudRate() + * + * @note: For autobaud we assume the key character being used is a carrige return (0xD), so the start edge count is + * hardcoded to the second edge (first edge after start edge) and the last edge count is set to the fouth edge. + * This will give us a total bit count of 8 bits that we will time in order to figure out the baud rate (bits/second). + */ +ADI_UART_RESULT adi_uart_EnableAutobaud( + ADI_UART_HANDLE const hDevice, + bool const bEnable, + bool const bAutobaudCallbackMode + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Make sure there are no active buffers on any active channel and autobaud is not in progress. */ + if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) || + ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL))) + { + return(ADI_UART_DEVICE_IN_USE); + } + +#endif /* ADI_DEBUG */ + + if(bEnable) + { + /* Enable Autobaud, timeout interrupt and done interrupt in the autobaud control register. + Set the starting edge trigger to the second edge. Set the ending edge count to + the fourth edge, for the carrige return key character (0xD). + */ + hDevice->pUARTRegs->ACR |=(BITM_UART_ACR_ABE | BITM_UART_ACR_DNIEN | BITM_UART_ACR_TOIEN |(1u << 4u) | (3u << 8u)); + + /* Initialize device baudrate to 0. This will be set once autobaud is complete. */ + hDevice->nBaudRate = 0u; + + /* Change the state to indicate autobaud is in progress. */ + hDevice->bAutobaudInProgress = true; + + /* Set the callback mode for autobaud based on the user input. */ + hDevice->bAutobaudCallbackMode = bAutobaudCallbackMode; + } + else + { + /* Change the state to indicate autobaud is not in progress. */ + hDevice->bAutobaudInProgress = false; + + /* Disable Autobaud, timeout interrupt and done interrupt in the autobaud control register. */ + hDevice->pUARTRegs->ACR |= (uint16_t)(~(uint32_t)BITM_UART_ACR_ABE | ~(uint32_t)BITM_UART_ACR_DNIEN | ~(uint32_t)BITM_UART_ACR_TOIEN); + + /* Initialize device baudrate to 0. */ + hDevice->nBaudRate = 0u; + } + + return ADI_UART_SUCCESS; +} + +/*! + * @brief Forces the UART to send out a break signal. + * + * @details Sets the UART Tx pin to a logic-low/high (depending upon the + * Tx polarity) asynchronously. The UART keeps transmitting break + * until it is disabled to send the break. + * + * @param [in] hDevice Handle to the UART whose Tx is forced to + * send a break. + * @param [in] bEnable Flag which indicates whether to enable or + * disable transmitting the break. + * + * @return Status + * + * - #ADI_UART_SUCCESS If successfully enabled or disabled sending break. + * - #ADI_UART_INVALID_HANDLE [D] If the given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_ForceTxBreak( + ADI_UART_HANDLE const hDevice, + bool const bEnable + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + if(bEnable == true) + { + /* Set the force break bit. */ + hDevice->pUARTRegs->LCR |= BITM_UART_LCR_BRK; + } + else + { + /* Clear the force break bit. */ + hDevice->pUARTRegs->LCR &= (uint16_t)~(BITM_UART_LCR_BRK); + } + + return ADI_UART_SUCCESS; +} + +/*! + * @brief Enable/Disable the loopback for the specified UART device. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] bEnable Boolean flag to indicate whether to enable or disable the loopback mode. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully enable/disable the loopback. + * - #ADI_UART_INVALID_HANDLE Invalid UART device handle. + * +*/ +ADI_UART_RESULT adi_uart_EnableLoopBack( + ADI_UART_HANDLE const hDevice, + bool const bEnable + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + if(true == bEnable) + { + /* Enable loopback. */ + hDevice->pUARTRegs->MCR |= (BITM_UART_MCR_LOOPBACK); + } + else + { + /* Disable loopback. */ + hDevice->pUARTRegs->MCR &= (uint16_t)~(BITM_UART_MCR_LOOPBACK); + } + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Sets the RX FIFO trigger level. This will be the amount of data in the FIFO + * that will trigger an interrupt. + * + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] eTriglevel Trigger level to be set in terms of number of bytes. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully set the trigger level. + * - #ADI_UART_INVALID_HANDLE [D] The given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_SetRxFifoTriggerLevel( + ADI_UART_CONST_HANDLE const hDevice, + ADI_UART_TRIG_LEVEL const eTriglevel + ) +{ +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + /* Clear existing FIFO trigger level. */ + hDevice->pUARTRegs->FCR &= (uint16_t)~BITM_UART_FCR_RFTRIG; + + /* Set the FIFO trigger level. */ + hDevice->pUARTRegs->FCR |= (uint16_t)eTriglevel; + + return(ADI_UART_SUCCESS); +} +/*! + * @brief Enables internal FIFO as to work in 16550 mode. This helps to minimize system overhead + * and maximize system efficiency. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] bEnable Boolean flag to indicate whether to enable or disable FIFO. + * + * @return Status + * - #ADI_UART_SUCCESS If successfully enabled FIFO for UART device. + * - #ADI_UART_INVALID_HANDLE [D] The given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_EnableFifo( + ADI_UART_HANDLE const hDevice, + bool const bEnable + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + if(bEnable == true) + { + /* Enable TX/RX FIFO. */ + hDevice->pUARTRegs->FCR |= BITM_UART_FCR_FIFOEN; + hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ERBFI); + + hDevice->bRxFifoEn = true; + + } + else + { + /* Disable TX/RX FIFO. */ + hDevice->pUARTRegs->FCR &= (uint16_t)~(BITM_UART_FCR_FIFOEN); + + hDevice->bRxFifoEn = false; + } + + return ADI_UART_SUCCESS; +} + +/*! + * @brief To flush the TX FIFO. + * + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * + * + * @return Status + * - #ADI_UART_SUCCESS Successfully flushed TX Fifo. + * - #ADI_UART_INVALID_HANDLE [D] The given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_FlushTxFifo( + ADI_UART_CONST_HANDLE const hDevice + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + /* Flush the Tx FIFO. */ + hDevice->pUARTRegs->FCR |= BITM_UART_FCR_TFCLR; + + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Flush the RX FIFO. + * + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * + * + * @return Status + * - #ADI_UART_SUCCESS Successfully flushed RX Fifo. + * - #ADI_UART_INVALID_HANDLE [D] The given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_FlushRxFifo( + ADI_UART_CONST_HANDLE const hDevice + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + /* Flush RX FIFO. */ + hDevice->pUARTRegs->FCR |= BITM_UART_FCR_RFCLR; + + return ADI_UART_SUCCESS; +} + +/*! + * @brief Flush the Rx channel and disable interrupts. This will stop any buffers in flight and + * clear out any data that was in the RX holding register as well as the Rx fifo. Once this is done, + * in order to turn back on Rx interrupts, a new transaction will need to be started (adi_uart_Read() + * or adi_uart_SubmitRxBuffer()). + * + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * + * @return Status + * - #ADI_UART_SUCCESS Successfully flushed the Rx channel. + * - #ADI_UART_INVALID_HANDLE [D] The given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_FlushRxChannel( + ADI_UART_CONST_HANDLE const hDevice + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + /* Disable receive interrupts in PIO mode as well as DMA mode. */ + hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ERBFI | BITM_UART_IEN_EDMAR); + + /* Clear any data in the Rx Fifo. */ + hDevice->pUARTRegs->FCR |= BITM_UART_FCR_RFCLR; + + /* Reset the buffers to 0. */ + memset(hDevice->pChannelRx->PingPong,0, sizeof (hDevice->pChannelRx->PingPong)); + + hDevice->pChannelRx->PingPong[0].pNextBuffer = &hDevice->pChannelRx->PingPong[1]; + hDevice->pChannelRx->PingPong[1].pNextBuffer = &hDevice->pChannelRx->PingPong[0]; + + /* Reset the buffer pointers. */ + hDevice->pChannelRx->pActiveBuffer = &hDevice->pChannelRx->PingPong[0]; + hDevice->pChannelRx->pFreeBuffer = &hDevice->pChannelRx->PingPong[0]; + hDevice->pChannelRx->pFillBuffer = &hDevice->pChannelRx->PingPong[0]; + + /* Dummy read to flush the RX register. */ + hDevice->pUARTRegs->RX; + + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Flush the Tx channel and disable interrupts.This will stop any buffers in flight and + * clear out any data that was in the TX holding register. Any data in the TX shift register + * will still finish transmitting. + * + * + * @param [in] hDevice Device handle to UART device obtained when an UART device is opened successfully. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully flushed the Tx channel. + * - #ADI_UART_INVALID_HANDLE [D] The given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_FlushTxChannel(ADI_UART_CONST_HANDLE const hDevice) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + /* Disable transmit interrupts in PIO mode as well as DMA mode. */ + hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ETBEI | BITM_UART_IEN_EDMAT); + + /* Clear any data in the Rx Fifo. */ + hDevice->pUARTRegs->FCR |= BITM_UART_FCR_TFCLR; + + /* Reset the buffers to 0. */ + memset(hDevice->pChannelTx->PingPong,0, sizeof (hDevice->pChannelTx->PingPong)); + + hDevice->pChannelTx->PingPong[0].pNextBuffer = &hDevice->pChannelTx->PingPong[1]; + hDevice->pChannelTx->PingPong[1].pNextBuffer = &hDevice->pChannelTx->PingPong[0]; + + /* Reset the buffer pointers. */ + hDevice->pChannelTx->pActiveBuffer = &hDevice->pChannelTx->PingPong[0]; + hDevice->pChannelTx->pFreeBuffer = &hDevice->pChannelTx->PingPong[0]; + hDevice->pChannelTx->pFillBuffer = &hDevice->pChannelTx->PingPong[0]; + + return(ADI_UART_SUCCESS); +} + + +/*! \cond PRIVATE */ + +void UART0_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)uart_device_info[0].hDevice; + Common_Uart_Interrupt_Handler(hDevice); +#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_UART); +#endif + ISR_EPILOG(); + return; +} + +void UART1_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)uart_device_info[1].hDevice; + Common_Uart_Interrupt_Handler(hDevice); +#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_UART); +#endif + ISR_EPILOG(); + return; +} + +static void Common_Uart_Interrupt_Handler(ADI_UART_HANDLE hDevice) +{ + switch(hDevice->pUARTRegs->IIR & BITM_UART_IIR_STAT ) + { + /* Tx buffer empty interrupt. This means that the data has successfully left the holding register and is + now in transmit shift register or has completed its transfer. + */ + case ENUM_UART_IIR_STAT_ETBEI: + uart_TxDataHandler(hDevice); + break; + + /* Rx buffer FIFO timeout interrupt. This means that we have data in the RX FIFO + but there is not enough data to trigger an interrupt so we will process this data here. + */ + case ENUM_UART_IIR_STAT_RFTOI: + uart_RxDataHandler(hDevice); + break; + + /* Rx buffer full interrupt. This means that the RX buffer has finished receiving data. */ + case ENUM_UART_IIR_STAT_ERBFI: + uart_RxDataHandler(hDevice); + break; + + /* Line status interrupt. */ + case ENUM_UART_IIR_STAT_RLSI: + { + /* Initialze the line status event to 0. */ + uint32_t nEvent = 0u; + + /* Get the interrupts status. */ + uint16_t nStatus = hDevice->pUARTRegs->LSR; + + /* If a break signal is detected.. */ + if((BITM_UART_LSR_BI & nStatus) == BITM_UART_LSR_BI) + { + /* Dummy read to flush the RX register. We do this because + we do not actaully want to do anything with this data as it + is only a break indicator. */ + hDevice->pUARTRegs->RX; + + /* Set the event to a break interrupt. */ + nEvent = (uint32_t)ADI_UART_BREAK_INTERRUPT; + } + + /* Ignore the framing error if the break is asserted. + We do this because a break can trigger a false framing error. + */ + else if((BITM_UART_LSR_FE & nStatus) == BITM_UART_LSR_FE) + { + /* Set the event to show a framing error has been detected. */ + nEvent |= (uint32_t)ADI_UART_HW_ERR_FRAMING; + } + else + { + /* Do nothing. This is required for MISRA. */ + } + + if((BITM_UART_LSR_PE & nStatus) == BITM_UART_LSR_PE) + { + /* Set the event to show a parity error has been detected. */ + nEvent |= (uint32_t)ADI_UART_HW_ERR_PARITY; + } + if((BITM_UART_LSR_OE & nStatus) == BITM_UART_LSR_OE) + { + /* Set the event to show a hardware overrun error has been detected, meaning receive data has + been overwritten. + */ + nEvent |= (uint32_t)ADI_UART_HW_ERR_OVERRUN; + } + + /* If there was an event and autobaud is not in progress, notify the API. */ + if((nEvent != 0u) && (hDevice->bAutobaudInProgress == false)) + { + /* Set the UART device hw error bit field. This will allow us to return the + specific failure to the application once we return from this ISR. + */ + hDevice->nHwError |= nEvent; + uart_ManageProcessedBuffer(hDevice, hDevice->pChannelRx, ADI_UART_EVENT_HW_ERROR_DETECTED); + } + break; + } + + /* If there was a modem status interrupt. For our purposes, we will only check if this is related to autobaud. */ + case ENUM_UART_IIR_STAT_EDSSI: + { +#if (ADI_UART_CFG_ENABLE_AUTOBAUD == 1) + /* Initialize the autobaud event to 0. */ + uint32_t nEvent = 0u; + + /* Get the autobaud interrupt status but not the counter value. */ + uint16_t nStatus = hDevice->pUARTRegs->ASRL & 0xFu; + + /* Read the autobaud control register to see if autobaud was enabled. */ + uint16_t acr = (hDevice->pUARTRegs->ACR & BITM_UART_ACR_ABE); + + /* If there is an autobaud event and autobaud is enabled */ + if((nStatus != 0u) && (acr != 0u)) + { + uint32_t nClock; + uint32_t nCount; + + /*Get the clock frequency. */ + if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK,&nClock) != ADI_PWR_SUCCESS) + { + nClock = 0u; + } + + /* Get the autobaud counter bits 12-19. */ + nCount = (uint32_t)hDevice->pUARTRegs->ASRH << 12u; + + /* Get the autobaud counter bits 0-11. */ + nCount |= (uint32_t)hDevice->pUARTRegs->ASRL >> 4u; + + /* if the autobaud event was that the autobaud is done.. */ + if((nStatus & BITM_UART_ASRL_DONE) == BITM_UART_ASRL_DONE) + { + /* If the fractional baud generator is enabled, calculate the fractional portional of the baudrate. + It seems that in order to get a correct baudrate reading, we need the fractional divider enabled. + */ + if ((hDevice->pUARTRegs->FBR & 0x8000u) == 0x8000u) + { + uint8_t nOSR = 0u; + uint32_t nDivN; + uint32_t nDivNSubtractor = 2048u; + + /* DIVC is always 1, unless the oversample rate is 32. */ + uint16_t nDivC = 1u; + + /* If the oversample rate is 4.. */ + if(nCount < (8u << 3u)) + { + nDivN = ((nCount << 9u) / 8u) - nDivNSubtractor; + } + + /* If the oversample rate is 8.. */ + else if(nCount < (8u << 4u)) + { + nDivN = ((nCount << 8u) / 8u) - nDivNSubtractor; + nOSR = 1u; + } + + /* If the oversample rate is 16.. */ + else if(nCount < (8u << 5u)) + { + nDivN = ((nCount << 7u) / 8u) - nDivNSubtractor; + nOSR = 2u; + } + + /* If the oversample rate is 32.. */ + else + { + nDivC = (uint16_t) (nCount / 32u / 8u); + nDivN = ((nCount << 6u) / (8u * nDivC)) - nDivNSubtractor; + nOSR = 3u; + } + + /* Write back the register contents for baudrate detection in the hardware. */ + adi_uart_ConfigBaudRate(hDevice, nDivC, 1u, (uint16_t)nDivN, nOSR); + + /* For more precise calculations we would use floating point math here. Integer precision will do for now. + This avoids bringing in extra libraries for floating point math. */ + + /* Baudrate = (UARTCLK / (nDivM + nDivN / 2048) * pow(2, nOSR + 2) * nDivC) + nOSR = (1u << (nOSR + 2u)); Seperate this out of the equation for misra compliance + hDevice->nBaudRate = ((float)nClock / (((float)1 + (float)nDivN / (float)2048) * (float)nOSR * (float)nDivC)); + */ + + /* In order to avoid bringing in the extra floating point libraries, we will use the non fractional baudrate for the API. */ + hDevice->nBaudRate = ((nClock * 8u) / nCount); + } + else + { + /* No Fractional divider: Baudrate (bits/second) = (UARTCLK (cycles/second) * counted bits (bits)) / nCount (cycles)*/ + hDevice->nBaudRate = ((nClock * 8u) / nCount); + } + + /* If there is a callback, notify the API that autobaud is complete. + If there is not a callback, the baudrate will be set to a non zero value so the user can call "Get_BaudRate" + to know that autobaud has completed. + */ + if((hDevice->pfCallback != NULL) && (hDevice->bAutobaudCallbackMode == true)) + { + hDevice->pfCallback(hDevice->pCBParam, ADI_UART_EVENT_AUTOBAUD_COMPLETE, (void*)hDevice->nBaudRate); + } + } + else + { + if((nStatus & BITM_UART_ASRL_BRKTO) == BITM_UART_ASRL_BRKTO) + { + /* Autobaud timed out due to break error. */ + nEvent |= (uint32_t)ADI_UART_AUTOBAUD_TIMEOUT_LONGBREAK; + } + if((nStatus & BITM_UART_ASRL_NSETO) == BITM_UART_ASRL_NSETO) + { + /* Autobaud timed out due to no valid start edge found. */ + nEvent |= (uint32_t)ADI_UART_AUTOBAUD_TIMEOUT_NO_START_EDGE; + } + if((nStatus & BITM_UART_ASRL_NEETO) == BITM_UART_ASRL_NEETO) + { + /* Autobaud timed out due to no valid end edge found. */ + nEvent |= (uint32_t)ADI_UART_AUTOBAUD_TIMEOUT_NO_END_EDGE; + } + /* If there is an event callback.. */ + if((hDevice->pfCallback != NULL) && (hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING)) + { + /* Notify application of errors through callback. */ + hDevice->pfCallback(hDevice->pCBParam, ADI_UART_EVENT_AUTOBAUD_ERROR_DETECTED, (void*)nEvent); + } + else + { + /* Notify application of errors through autobaud return value. */ + hDevice->nAutobaudError = nEvent; + } + + } + + /* Dummy read to flush the RX register to clear the key character that was sent while configuring autobaud. */ + hDevice->pUARTRegs->RX; + } +#endif + /* Clear auto baud enable and interrupt registers. We disable autobaud here because it is required in order to clear the counter. */ + hDevice->pUARTRegs->ACR &=(uint16_t)~( BITM_UART_ACR_ABE | + BITM_UART_ACR_DNIEN | + BITM_UART_ACR_TOIEN ); + + hDevice->bAutobaudInProgress = false; + break; + } + default: + break; + } + return; +} + + +/* DMA interrupt handlers */ +void DMA_UART0_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[0].hDevice; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED); +#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_TX); +#endif + ISR_EPILOG(); +} + +void DMA_UART0_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[0].hDevice; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED); +#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_RX); +#endif + ISR_EPILOG(); +} + +void DMA_UART1_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[1].hDevice; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED); +#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_TX); +#endif + ISR_EPILOG(); +} + +void DMA_UART1_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[1].hDevice; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED); +#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_RX); +#endif + ISR_EPILOG(); +} + + +/* + * @brief UART interrupt handler for receiving the data in interrupt mode. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * +*/ +static void uart_RxDataHandler(ADI_UART_HANDLE hDevice) +{ + volatile uint8_t *pNextData; + + /* If there is an active buffer.. */ + if((hDevice->pChannelRx->pFillBuffer->pStartAddress != NULL) && (hDevice->pChannelRx->pFillBuffer->bInUse == true)) + { + /* Get the address of the buffer we are filling. */ + pNextData = (uint8_t *)hDevice->pChannelRx->pFillBuffer->pStartAddress; + + /* Read data from the RX holding register into the buffer at the indexed location. */ + pNextData[hDevice->pChannelRx->pFillBuffer->nIndex] = (uint8_t) hDevice->pUARTRegs->RX; + + /* Increment the buffer index so we don't overwrite this data in the buffer. */ + hDevice->pChannelRx->pFillBuffer->nIndex++; + + /* If all of the data has been processed, manage the processed data buffer. Otherwise we will + leave everything as is and continue to receive interrupts for the incoming data, until this + buffer has been filled. + */ + if(hDevice->pChannelRx->pFillBuffer->nIndex == hDevice->pChannelRx->pFillBuffer->nCount) + { + uart_ManageProcessedBuffer(hDevice, hDevice->pChannelRx, ADI_UART_EVENT_RX_BUFFER_PROCESSED); + } + } + /* If we do not have a buffer submitted.. */ + else + { + /* Ask the API for a buffer so we can process this data before having an overflow. + if there is no callback, the API will not be able to submit a buffer in time. + */ + if (hDevice->pfCallback != NULL) + { + hDevice->pfCallback(hDevice->pCBParam, (uint32_t)ADI_UART_EVENT_NO_RX_BUFFER_EVENT, NULL); + } + + /* This check here is in case in the callback the application submitted a buffer. If they did + not then we need to clear the RX register in order to clear this interrupt. + */ + if((hDevice->pChannelRx->pFillBuffer->pStartAddress == NULL) && (hDevice->pChannelRx->pFillBuffer->bInUse == false)) + { + hDevice->pUARTRegs->RX; + } + } + + return; +} + +/* + * @brief UART interrupt handler transmitting the data in interrupt mode. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * +*/ +static void uart_TxDataHandler(ADI_UART_HANDLE hDevice) +{ + volatile uint8_t *pNextData; + + /* If there is an active buffer.. */ + if((hDevice->pChannelTx->pFillBuffer->pStartAddress != NULL) && (hDevice->pChannelTx->pFillBuffer->bInUse == true)) + { + /* Get the start address of the buffer we are transmitting data from. */ + pNextData = (uint8_t *)hDevice->pChannelTx->pFillBuffer->pStartAddress; + + /* Write data to the TX holding register. This will be shifted out at the baud rate by the shift register. */ + hDevice->pUARTRegs->TX = (uint16_t)pNextData[hDevice->pChannelTx->pFillBuffer->nIndex]; + + /* Increment the buffer index. */ + hDevice->pChannelTx->pFillBuffer->nIndex++; + + + /* If all of the characters have been transmitted, manage the data buffer. Otherwise we will leave everything + as is and continue to transmit this data until everything is out of the buffer. */ + if(hDevice->pChannelTx->pFillBuffer->nIndex >= hDevice->pChannelTx->pFillBuffer->nCount) + { + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED); + } + } + return; +} + + +/* + * @brief Function for managing the processed buffer. This gets called after the receive buffer has been filled + * and when the transmit buffer has been emptied. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pChannel Channel handler for the Tx or Rx. + * @param [in] eEvent Indicate the event ID to be passed to registered callback function, if one has been registered. + * +*/ + +static void uart_ManageProcessedBuffer(ADI_UART_HANDLE hDevice,ADI_UART_DATA_CHANNEL *pChannel, ADI_UART_EVENT eEvent) +{ + + + /* Now that this transaction has completed, this buffer is no longer in use. */ + pChannel->pFillBuffer->bInUse = false; + + pChannel->pFillBuffer = pChannel->pFillBuffer->pNextBuffer; + + if(eEvent == ADI_UART_EVENT_TX_BUFFER_PROCESSED) + { + /* Disable Tx buffer interrupts. */ + hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ETBEI | BITM_UART_IEN_EDMAT); + } + else + { + /* Disable Rx buffer interrupts for the DMA. We do not disable receive buffer full interrupts to allow + the use of the RX FIFO. + */ + hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_EDMAR); + + if (hDevice->bRxFifoEn != true) + { + /* Disable Rx buffer interrupts for PIO mode if the FIFO is not enabled. + */ + hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ERBFI); + } + + } + + /* If there is a callback registered, notify the API that a buffer has been processed. Clean up the buffer. */ + if((hDevice->pfCallback != NULL) && (pChannel->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING)) + { + uint32_t nEvent = hDevice->nHwError; + hDevice->nHwError = 0u; + + uint32_t *pBuffer = pChannel->pActiveBuffer->pStartAddress; + + /* Reinitialize the start address to NULL so this buffer can be used for a new transaction. */ + pChannel->pActiveBuffer->pStartAddress = NULL; + + /* Now that the desired data has either been transmitted or received, this buffer is no longer + in use. We can update "pActiveBuffer" to point to the next buffer that will become or is already + active. + */ + pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer; + + /* Set the data transfer mode to none so that the next transfer can be either in blocking or in nonblocking mode. + This will only be done if there are no other active buffers in flight to avoid disrupting an active transfer. + */ + if(pChannel->pActiveBuffer->pStartAddress == NULL) + { + pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE; + } + if(nEvent != 0u) + { + hDevice->pfCallback(hDevice->pCBParam, ADI_UART_EVENT_HW_ERROR_DETECTED,(void*)nEvent); + + } + else + { + hDevice->pfCallback(hDevice->pCBParam, (uint32_t)eEvent, (void*)pBuffer); + } + + } + else + { + /* Post to the blocking function. If we are in blocking mode, this will allow the buffer to be returned to the API. + If we are in nonblocking mode, this will allow adi_uart_GetBuffer() to return immediately so the API can have + control over the buffer again. + */ + SEM_POST(pChannel); + } + + /* If there is another buffer active. The buffer we want to check is "pFillBuffer" because that is the next one that would + be processed. So if it has been submitted, now would be the time to set up the interrupts based on its requirements. + */ + if(pChannel->pFillBuffer->bInUse == true) + { + pChannel->pfSubmitBuffer(hDevice, pChannel->pFillBuffer); + } +} + + +/* + * @brief Initialize the UART instance to the default values specified in "adi_uart_config.h". + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] nDeviceNum UART device number +*/ + +static void uart_init(ADI_UART_CONST_HANDLE const hDevice, uint32_t const nDeviceNum) +{ + + ADI_UART_CONFIG const* pUARTCfg = &gUARTCfg[nDeviceNum]; + + /* Line Control Register. */ + hDevice->pUARTRegs->LCR = pUARTCfg->LCR; + + /* Div-C in Baudrate divider register. */ + hDevice->pUARTRegs->DIV = pUARTCfg->DIV; + + /* Div-M and Div-N in Fractional Baudrate register. */ + hDevice->pUARTRegs->FBR = pUARTCfg->FBR; + + /* Second line control register. */ + hDevice->pUARTRegs->LCR2 = pUARTCfg->LCR2; + + /* FIFO control register. */ + hDevice->pUARTRegs->FCR = pUARTCfg->FCR; + + /* Half Duplex Control Register. */ + hDevice->pUARTRegs->RSC = pUARTCfg->RSC; + + /* Interrupt enable register. */ + hDevice->pUARTRegs->IEN = pUARTCfg->IEN; +} + +#ifdef ADI_DEBUG +/* + * @brief Validate the device handle. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * + * @return Status + * - #ADI_UART_SUCCESS Specified handle is valid. + * - #ADI_UART_INVALID_HANDLE Specified handle is invalid. + * +*/ + +static ADI_UART_RESULT ValidateHandle(ADI_UART_CONST_HANDLE hDevice) +{ + uint32_t i; + + + for(i = 0U; i < ADI_UART_NUM_DEVICES; i++) + { + + if((hDevice == uart_device_info[i].hDevice) && (hDevice != NULL)) + { + return(ADI_UART_SUCCESS); + } + } + return(ADI_UART_INVALID_HANDLE); +} +#endif /* ADI_DEBUG */ +/*! \endcond */ +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart_def.h new file mode 100755 index 0000000000..0762d9d13b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart_def.h @@ -0,0 +1,214 @@ +/*! ***************************************************************************** + * @file: adi_uart_def.h + * @brief: UART Device Driver definition for processor + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +/*! \cond PRIVATE */ +#ifndef DEF_UART_DEF_H +#define DEF_UART_DEF_H + + +/*! + ***************************************************************************** + * \struct ADI_UART_BUFF_INFO + * Structure for managing the submitted buffers. + *****************************************************************************/ + +typedef struct UART_BUFF_INFO +{ + void *pStartAddress; /*!< Address of buffer passed down to the UART driver. */ + uint32_t nCount; /*!< Size of buffer in bytes. */ + uint32_t nIndex; /*!< Buffer index. */ + bool bInUse; /*!< Buffer in use flag. */ + bool bDMA; /*!< Transaction is using the DMA flag. */ + struct UART_BUFF_INFO *pNextBuffer; /*!< Pointer to the next buffer in the list. */ + + +}ADI_UART_BUFF_INFO; + + +/*! Function pointer typedef for the function which submit the buffer */ +typedef void (*UART_BUFFER_SUBMIT) (ADI_UART_CONST_HANDLE const hDevice, + ADI_UART_BUFF_INFO *const pBuffer + ); + + +/*! + ***************************************************************************** + * \struct ADI_UART_DATA_CHANNEL + * Structure to manage the data transfer for a given channel. + * One instance of this structure will be created for managing the + * data transfer in each direction. + *****************************************************************************/ + +typedef struct _ADI_UART_DATA_CHANNEL +{ + ADI_UART_BUFF_INFO PingPong[2]; /*!< Ping Pong Buffers. */ + ADI_UART_BUFF_INFO *pFreeBuffer; /*!< Pointer to free buffer (next buffer to submit). */ + ADI_UART_BUFF_INFO *pFillBuffer; /*!< Pointer to the next buffer to be filled. This is needed for + the case where two buffers are "submitted" before a "get" is + called. */ + ADI_UART_BUFF_INFO *pActiveBuffer; /*!< Pointer to active buffer (next buffer waiting for completion).*/ + ADI_UART_TRANSFER_MODE eDataTranferMode; /*!< Data transfer mode. */ + UART_BUFFER_SUBMIT pfSubmitBuffer; /*!< Pointer to a function used for submitting a buffer. */ + SEM_VAR_DECLR + +}ADI_UART_DATA_CHANNEL; + + +/*! + ***************************************************************************** + * \struct ADI_UART_DEVICE_INFO + * Structure for storing basic device information. + *****************************************************************************/ + +typedef struct _ADI_UART_DEVICE_INFO +{ + DMA_CHANn_TypeDef dmaTxChannelNum; /*!< DMA channel ID-Tx. */ + DMA_CHANn_TypeDef dmaRxChannelNum; /*!< DMA channel ID-Rx. */ + IRQn_Type eDMATx; /*!< DMA channel IRQ-Tx. */ + IRQn_Type eDMARx; /*!< DMA channel IRQ-Rx. */ + IRQn_Type eIRQn; /*!< UART interrupt ID. */ + ADI_UART_TypeDef *pUartRegs; /*!< Base address of the UART registers. */ + ADI_UART_HANDLE hDevice; /*!< Handle for the device instance. */ + +}ADI_UART_DEVICE_INFO; + + +/*! + ***************************************************************************** + * \struct ADI_UART_DEVICE + * Structure for managing the UART device. + *****************************************************************************/ + +typedef struct _ADI_UART_DEVICE +{ + ADI_UART_DIRECTION eDirection; /*!< UART operation direction. */ + ADI_UART_DEVICE_INFO *pUartInfo; /*!< Access to device information about the uart instance. */ + volatile ADI_UART_TypeDef *pUARTRegs; /*!< Access to UART Memory Mapped Registers. */ + ADI_CALLBACK pfCallback; /*!< Callback function. */ + void *pCBParam; /*!< Parameter for callback function. */ + bool bAutobaudInProgress; /*!< Autobaud in progress flag. */ + volatile uint32_t nHwError; /*!< Line status error(s). */ + volatile uint32_t nAutobaudError; /*!< Autobaud error(s). */ + ADI_UART_DATA_CHANNEL *pChannelTx; /*!< Tx channel. */ + ADI_UART_DATA_CHANNEL *pChannelRx; /*!< Rx channel. */ + volatile uint32_t nBaudRate; /*!< Baudrate. */ + bool bAutobaudCallbackMode;/*!< Autobaud detection is using callback mode flag. */ + bool bRxFifoEn; /*!< Rx FIFO enabled. Rx buffer full interrupts will remain enabled. */ + +} ADI_UART_DEVICE; + + +/*! + ***************************************************************************** + * \struct ADI_UART_CONFIG + * Structure for initializing the static config. + *****************************************************************************/ + +typedef struct _ADI_UART_CONFIG +{ + uint16_t LCR; /*!< UART_COMLCR Register. */ + + uint16_t DIV; /*!< UART_COMDIV Register. */ + + uint16_t FBR; /*!< UART_COMFBR Register. */ + + uint16_t LCR2; /*!< UART_COMLCR2 Register.*/ + + uint16_t FCR; /*!< UART_COMFCR Register. */ + + uint16_t RSC; /*!< UART_COMRSC Register. */ + + uint16_t IEN; /*!< UART_COMIEN Register .*/ + +} ADI_UART_CONFIG; + + +/****************************************************************************** + * UART Device internal API function prototypes + *****************************************************************************/ + +/* + * UART device initialization helper function. +*/ +static void uart_init(ADI_UART_CONST_HANDLE const hDevice, uint32_t const nDeviceNum); + + +/* + * Data transfer helper functions. +*/ +static void uart_submittxbuffer(ADI_UART_CONST_HANDLE const hDevice, ADI_UART_BUFF_INFO *const pBuffer); + +static void uart_submitrxbuffer(ADI_UART_CONST_HANDLE const hDevice, ADI_UART_BUFF_INFO *const pBuffer); + + +/* + * Data management helper functions. +*/ +static ADI_UART_RESULT uart_getbuffer(ADI_UART_HANDLE hDevice, ADI_UART_DATA_CHANNEL *pChannel, void **ppBuffer, uint32_t *pHwError); + +static ADI_UART_RESULT uart_PendForBuffer(ADI_UART_HANDLE const hDevice , ADI_UART_DATA_CHANNEL *pChannel, uint32_t *pHwError); + +static void uart_ManageProcessedBuffer(ADI_UART_HANDLE hDevice, ADI_UART_DATA_CHANNEL *pChannel, ADI_UART_EVENT eEvent); + +static void uart_TxDataHandler(ADI_UART_HANDLE hDevice); + +static void uart_RxDataHandler(ADI_UART_HANDLE hDevice); + + +/* + * Interrupt Handler. +*/ +static void Common_Uart_Interrupt_Handler(ADI_UART_HANDLE hDevice); + + +/* + * Handle Validation function +*/ +#ifdef ADI_DEBUG +static ADI_UART_RESULT ValidateHandle(ADI_UART_CONST_HANDLE hDevice); +#endif /* ADI_DEBUG */ + +#endif /* end of ifndef DEF_UART_DEF_H */ +/*! \endcond */ + + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/wdt/adi_wdt.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/wdt/adi_wdt.c new file mode 100755 index 0000000000..b2f34894a2 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/wdt/adi_wdt.c @@ -0,0 +1,225 @@ +/*! ***************************************************************************** + * @file adi_wdt.c + * @brief WDT device driver implementation + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* +* Pm011 (rule 6.3): the basic types of char, int, short, long, float, and double should not be used +* Necessary for stdbool. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm140 (Rule 11.4): a cast should not be performed between a pointer type and an integral type +* This violation appears when deferencing the pointer to the register typedef. No way around this. +*/ +#pragma diag_suppress=Pm011,Pm073,Pm140,Pm143 +#endif /* __ICCARM__ */ + + +/** @addtogroup WDT_Driver WDT Driver + * @{ + * @brief Watchdog Timer (WDT) Driver + * @details The watchdog timer driver allows the user to enable the timer with + * the static configuration parameters, reset the timer, and read the timer + * count. No interface is provided for setting the timer parameters are + * runtime since the WDT may only be configured once for the program lifetime. + * The timer is disabled by default by the ADuCM4x50 boot kernel. + * @note The application must include drivers/wdt/adi_wdt.h to use this driver + */ + +#include +#include +#include +#include +#include + +/*! \cond PRIVATE */ + +/*! Bus synchronization bits that must go low before writing to the CTL or RESET registers */ +#define ADI_WDT_SYNC_BITS ((0x1u << BITP_WDT_STAT_COUNTING) | (0x1u << BITP_WDT_STAT_LOADING) | (0x1u << BITP_WDT_STAT_CLRIRQ)) + +/*! Value that is written to the reset register to kick the dog */ +#define ADI_WDT_CLR_VALUE (0xCCCCu) + +/*! Store the callback locally if we are using interrupt mode */ +#if (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u) +static ADI_CALLBACK gAppCallback; +#endif + +/*! \endcond */ + +/********************************************************************************* + API IMPLEMENTATIONS +*********************************************************************************/ + + +/*! + * @brief WDT Enable + * + * @details Enables/disables the WDT with the paramters supplied in adi_wdt_config.h + * + * @param [in] bEnable : True to turn WDT on, false to turn it off + * + * @param [in] pfCallback : If interrupt mode is enabled, specify application callback function, + * otherwise simply pass NULL for the argument. + * + * @return ADI_WDT_RESULT + * - #ADI_WDT_FAILURE_LOCKED WDT has already been initialized + * - #ADI_WDT_SUCCESS Function call completed successfully + */ +ADI_WDT_RESULT adi_wdt_Enable(bool const bEnable, ADI_CALLBACK const pfCallback) { + /* IF(Device is enabled, application can't modify it) */ + if ((pADI_WDT0->STAT & ((uint16_t) BITM_WDT_STAT_LOCKED)) != ((uint16_t) 0x0u)) { + return ADI_WDT_FAILURE_LOCKED; + } /* ENDIF */ + + /* Setup interrupts if we are in interrupt mode */ +#if (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u) + gAppCallback = pfCallback; + /* IF(We are enabling the WDT) */ + if (bEnable == true) { + NVIC_EnableIRQ (WDT_EXP_IRQn); + /* ELSE (We are disabling the WDT, this might not be necessary, depends on startup config) */ + } else { + NVIC_DisableIRQ(WDT_EXP_IRQn); + } /* ENDIF */ +#endif + + /* WHILE(Bus sync is underway) */ + while((pADI_WDT0->STAT & ADI_WDT_SYNC_BITS) != 0u) { + ; + } /* ENDWHILE */ + + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + + pADI_WDT0->LOAD = ADI_WDT_LOAD_VALUE; + + /* IF(Turning the WDT on) */ + if (bEnable == true) { + pADI_WDT0->CTL = (ADI_WDT_CONTROL_TIMER_MODE << BITP_WDT_CTL_MODE) | + (0x1u << BITP_WDT_CTL_EN ) | + (ADI_WDT_CONTROL_CLOCK_PRESCALER << BITP_WDT_CTL_PRE ) | + (ADI_WDT_CONTROL_TIMEOUT_MODE << BITP_WDT_CTL_IRQ ) | + (ADI_WDT_CONTROL_POWER_MODE << 0u ); + /* ELSE(Turning the WDT off) */ + } else { + pADI_WDT0->CTL = (ADI_WDT_CONTROL_TIMER_MODE << BITP_WDT_CTL_MODE) | + (0x0u << BITP_WDT_CTL_EN ) | + (ADI_WDT_CONTROL_CLOCK_PRESCALER << BITP_WDT_CTL_PRE ) | + (ADI_WDT_CONTROL_TIMEOUT_MODE << BITP_WDT_CTL_IRQ ) | + (ADI_WDT_CONTROL_POWER_MODE << 0u ); + } /* ENDIF */ + + ADI_EXIT_CRITICAL_REGION(); + + return ADI_WDT_SUCCESS; +} + +/*! + * @brief WDT Reset + * + * @details Resets the WDT + * + * @return None + */ +void adi_wdt_Kick(void) { + /* WHILE(Bus sync is underway) */ + while((pADI_WDT0->STAT & ADI_WDT_SYNC_BITS) != 0u) { + ; + } /* ENDWHILE */ + + /* Kick the dog! */ + pADI_WDT0->RESTART = ADI_WDT_CLR_VALUE; +} + +/*! + * @brief WDT Read Count + * + * @details Read the current WDT count + * + * @param [out] pCurCount : Pointer to memory to read the count into + * + * @return None + */ +void adi_wdt_GetCount(uint16_t * const pCurCount) { + /* Read the count */ + *pCurCount = pADI_WDT0->CCNT; +} + +/*! \cond PRIVATE */ + +/*! + * @brief WDT0 Interrupt Handler + * + * @details Kicks the dog and calls the user supplied callback function + * + * @return None + * + * @note Do not need to explicitly clear the interrupt status, + * kicking the dog performs this action. + */ +#if (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u) +extern void WDog_Tmr_Int_Handler(void); +void WDog_Tmr_Int_Handler(void) { + ISR_PROLOG() + /* Kick the dog */ + adi_wdt_Kick(); + /* IF(Application supplied a callback) */ + if(gAppCallback != NULL) { + /* Call the callback */ + gAppCallback(NULL, 0x0u, NULL); + } /* ENDIF */ + ISR_EPILOG() +} +#endif /* (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u) */ + +/*! \endcond */ + +/*! @} */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint.c new file mode 100755 index 0000000000..53e763cb70 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint.c @@ -0,0 +1,413 @@ +/****************************************************************************** + @file: adi_xint.c + @brief: External Interrupt device driver implementation. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ +/*****************************************************************************/ + +#include +#include +#include +#include +#include +#include "adi_xint_def.h" + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +* Pm140 (rule 10.3): illegal explicit conversion from underlying MISRA type unsigned int to enum +* The typecast is used for efficiency of the code. +* Pm140 (rule 17.4): array indexing shall only be applied to objects defined as an array +* Array indexing is required on the pointer. The memory for gpCallbackTable is passed from application +*/ +#pragma diag_suppress=Pm073,Pm143,Pm140,Pm136,Pm152 +#endif /* __ICCARM__ */ + +static inline void XIntCommonInterruptHandler (const ADI_XINT_EVENT eEvent); +void Ext_Int0_Handler(void); +void Ext_Int1_Handler(void); +void Ext_Int2_Handler(void); +void Ext_Int3_Handler(void); + + + +/*========== D A T A ==========*/ + +static ADI_XINT_CALLBACK_INFO *gpCallbackTable; + +/*! \endcond */ + +/*! \addtogroup XINT_Driver External Interrupt Driver + * @{ + * @brief External Interrupt (XINT) Driver + * @note The application must include drivers/xint/adi_xint.h to use this driver + */ + +/*! + @brief Initializes the External Interrupt Driver. + + @details This function does the external interrupt driver initialization. This function should be called + before calling any of the XINT driver APIs. + + @param[in] pMemory Pointer to the memory to be used by the driver. + Size of the memory should be at equal to #ADI_XINT_MEMORY_SIZE bytes. + @param[in] MemorySize Size of the memory passed in pMemory parameter. + + @return Status + - ADI_XINT_SUCCESS If successfully initialized XINT driver. + - ADI_XINT_NULL_PARAMETER [D] If the given pointer to the driver memory is pointing to NULL. + - ADI_XINT_INVALID_MEMORY_SIZE [D] If the given memory size is not sufficient to operate the driver. + + @sa adi_xint_UnInit +*/ +ADI_XINT_RESULT adi_xint_Init(void* const pMemory, + uint32_t const MemorySize +) +{ + +#ifdef ADI_DEBUG + /* Verify the given memory pointer */ + if(NULL == pMemory) + { + return ADI_XINT_NULL_PARAMETER; + } + /* Check if the memory size is sufficient to operate the driver */ + if(MemorySize < ADI_XINT_MEMORY_SIZE) + { + return ADI_XINT_INVALID_MEMORY_SIZE; + } + assert(MemorySize == (sizeof(ADI_XINT_CALLBACK_INFO) * ADI_XINT_EVENT_MAX)); +#endif + + /* Only initialize on 1st init call, i.e., preserve callbacks on multiple inits */ + if (gpCallbackTable == NULL) + { + /* Clear the memory passed by the application */ + memset(pMemory, 0, MemorySize); + + gpCallbackTable = (ADI_XINT_CALLBACK_INFO *)pMemory; + } + return (ADI_XINT_SUCCESS); +} + + +/*! + @brief Un-initialize the external interrupt driver. + + @details Terminates the XINT functions, leaving everything unchanged. + + @return Status + - #ADI_XINT_SUCCESS If successfully uninitialized XINT driver. + - #ADI_XINT_NOT_INITIALIZED [D] If XINT driver not yet initialized. + + @sa adi_xint_Init +*/ +ADI_XINT_RESULT adi_xint_UnInit(void) +{ + +#ifdef ADI_DEBUG + /* IF (not initialized) */ + if (NULL == gpCallbackTable) + { + /* return error if not initialized */ + return (ADI_XINT_NOT_INITIALIZED); + } +#endif + + /* Clear the callback pointer */ + gpCallbackTable = NULL; + + return (ADI_XINT_SUCCESS); +} + + + +/*! + @brief Enable an External Interrupt + + @details Enables and sets the triggering mode for the given external interrupt. + Applications may register a callback using the #adi_xint_RegisterCallback + API to get a notification when the interrupt occurs. + + To get the external interrupt working application has to enable the input + (using the GPIO driver API \a adi_gpio_InputEnable) for the corresponding GPIO + pin. Please refer the GPIO chapter pin-muxing section of the Hardware Reference + Manual to see the GPIO pin that is mapped to the required external interrupt. + + @param[in] eEvent Event which needs to be enabled. + @param[in] eMode Interrupt trigger mode for the external interrupt. + + @return Status + - #ADI_XINT_SUCCESS If successfully enabled the external interrupt. + - #ADI_XINT_NOT_INITIALIZED [D] If external interrupt driver not yet initialized. + + @sa adi_xint_DisableIRQ + @sa adi_xint_RegisterCallback +*/ +ADI_XINT_RESULT adi_xint_EnableIRQ(const ADI_XINT_EVENT eEvent, const ADI_XINT_IRQ_MODE eMode) +{ + uint32_t Mask; /* mask to manipulate the register */ + uint32_t Pattern; /* bit pattern that will be written into the register */ + uint32_t CfgReg; /* interrupt config register value */ + IRQn_Type XintIrq; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == gpCallbackTable) + { + return (ADI_XINT_NOT_INITIALIZED); + } +#endif + + /* create the mask we'll use to clear the relevant bits in the config register */ + Mask = (BITM_XINT_CFG0_IRQ0MDE | BITM_XINT_CFG0_IRQ0EN) << (ADI_XINT_CFG_BITS * (uint32_t)eEvent); + + /* The Pattern has to be created differently for UART RX wakeup and other events as the + mode and enable bits are flipped in case of UART RX */ + + /* Based on the event figure out the interrupt it is mapped to */ + if(eEvent == ADI_XINT_EVENT_UART_RX) + { + /* create the bit pattern we're going to write into the configuration register */ + Pattern = (BITM_XINT_CFG0_UART_RX_EN | ((uint32_t)eMode << BITP_XINT_CFG0_UART_RX_MDE)); + + XintIrq = XINT_EVT3_IRQn; + } + else + { + /* create the bit pattern we're going to write into the configuration register */ + Pattern = (BITM_XINT_CFG0_IRQ0EN | eMode) << (ADI_XINT_CFG_BITS * (uint32_t)eEvent); + + XintIrq = (IRQn_Type)((uint32_t)XINT_EVT0_IRQn + (uint32_t)eEvent); + } + + + ADI_ENTER_CRITICAL_REGION(); + + /* read/modify/write the appropriate bits in the register */ + CfgReg = pADI_XINT0->CFG0; + CfgReg &= ~Mask; + CfgReg |= Pattern; + pADI_XINT0->CFG0 = CfgReg; + + ADI_EXIT_CRITICAL_REGION(); + + /* enable the interrupt */ + NVIC_EnableIRQ(XintIrq); + + return (ADI_XINT_SUCCESS); +} + + +/*! + @brief Disable an External Interrupt + + @details Disables an external interrupt + + @param[in] eEvent External Interrupt event that should be disabled. + + @return Status + - #ADI_XINT_SUCCESS If successfully disabled the external interrupt. + - #ADI_XINT_NOT_INITIALIZED [D] If external interrupt driver is not yet initialized. + + @sa adi_xint_EnableIRQ + @sa adi_xint_RegisterCallback +*/ +ADI_XINT_RESULT adi_xint_DisableIRQ(const ADI_XINT_EVENT eEvent) +{ + uint32_t Mask; /* mask to manipulate the register */ + uint32_t CfgReg; /* interrupt config register value */ + IRQn_Type XintIrq; /* External interrupt IRQ the event is mapped to */ + + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == gpCallbackTable) + { + return (ADI_XINT_NOT_INITIALIZED); + } +#endif + + /* Based on the event figure out the interrupt it is mapped to */ + if(eEvent == ADI_XINT_EVENT_UART_RX) + { + XintIrq = XINT_EVT3_IRQn; + } + else + { + XintIrq = (IRQn_Type)((uint32_t)XINT_EVT0_IRQn + (uint32_t)eEvent); + } + + /* disable the interrupt */ + NVIC_DisableIRQ(XintIrq); + + /* create the mask we'll use to clear the relevant bits in the config register */ + Mask = (BITM_XINT_CFG0_IRQ0MDE | BITM_XINT_CFG0_IRQ0EN) << (ADI_XINT_CFG_BITS * (uint32_t)eEvent); + + ADI_ENTER_CRITICAL_REGION(); + /* read/modify/write the appropriate bits in the register */ + CfgReg = pADI_XINT0->CFG0; + CfgReg &= ~Mask; + pADI_XINT0->CFG0 = CfgReg; + ADI_EXIT_CRITICAL_REGION(); + + return (ADI_XINT_SUCCESS); +} + + +/*! + @brief Register or unregister an application callback function for external pin interrupts. + + @details Applications may register a callback function that will be called when an + external interrupt occurs. In addition to registering the interrupt, + the application should call the #adi_xint_EnableIRQ API to enable the + external pin interrupt. + + The driver dispatches calls to registered callback functions when the + properly configured pin(s) latches an external interrupt input on the XINT + pin(s). The callback is dispatched with the following parameters, respectively: + + - application-provided callback parameter (\a pCBParam), + - the interrupt ID (#ADI_XINT_EVENT) that initiated the interrupt, + - NULL. + + @param[in] eEvent The interrupt for which the callback is being registered. + @param[in] pfCallback Pointer to the callback function. This can be passed as NULL to + unregister the callback. + @param[in] pCBParam Callback parameter which will be passed back to the application + when the callback is called.. + + @return Status + - #ADI_XINT_SUCCESS If successfully registered the callback. + - #ADI_XINT_NOT_INITIALIZED [D] If external interrupt driver is not yet initialized. + + @sa adi_xint_EnableIRQ + @sa adi_xint_DisableIRQ +*/ +ADI_XINT_RESULT adi_xint_RegisterCallback (const ADI_XINT_EVENT eEvent, ADI_CALLBACK const pfCallback, void *const pCBParam ) +{ + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == gpCallbackTable) + { + return (ADI_XINT_NOT_INITIALIZED); + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + gpCallbackTable[eEvent].pfCallback = pfCallback; + gpCallbackTable[eEvent].pCBParam = pCBParam; + ADI_EXIT_CRITICAL_REGION(); + + /* return the status */ + return (ADI_XINT_SUCCESS); +} + +/*@}*/ + +/*! \cond PRIVATE */ +/* All of the following is excluded from the doxygen output... */ + +/* Common external interrupt handler */ +static inline void XIntCommonInterruptHandler(const ADI_XINT_EVENT eEvent) +{ + /* Clear the IRQ */ + pADI_XINT0->CLR = (1u << (uint32_t)eEvent); + + /* params list is: application-registered cbParam, Event ID, and NULL */ + if(gpCallbackTable[eEvent].pfCallback != NULL) + { + gpCallbackTable[eEvent].pfCallback (gpCallbackTable[eEvent].pCBParam, (uint32_t) eEvent, NULL); + } +} + +/* strongly-bound interrupt handlers to override the default weak bindings */ +void Ext_Int0_Handler(void) +{ + ISR_PROLOG() + XIntCommonInterruptHandler(ADI_XINT_EVENT_INT0); + ISR_EPILOG() +} + +void Ext_Int1_Handler(void) +{ + ISR_PROLOG() + XIntCommonInterruptHandler(ADI_XINT_EVENT_INT1); + ISR_EPILOG() +} + +void Ext_Int2_Handler(void) +{ + ISR_PROLOG() + XIntCommonInterruptHandler(ADI_XINT_EVENT_INT2); + ISR_EPILOG() + +} + +void Ext_Int3_Handler(void) +{ + ISR_PROLOG() + if((pADI_XINT0->EXT_STAT & BITM_XINT_EXT_STAT_STAT_UART_RXWKUP)==BITM_XINT_EXT_STAT_STAT_UART_RXWKUP) + { + XIntCommonInterruptHandler(ADI_XINT_EVENT_UART_RX); + } + else + { + XIntCommonInterruptHandler(ADI_XINT_EVENT_INT3); + } + ISR_EPILOG() +} + +/*! \endcond */ + +/* +** EOF +*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint_def.h new file mode 100755 index 0000000000..205602215c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint_def.h @@ -0,0 +1,61 @@ +/*! + ***************************************************************************** + * @file: adi_xint_def.h + * @brief: External Interrupt Driver definition + ***************************************************************************** +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_XINT_DEF_H +#define ADI_XINT_DEF_H +/*! \cond PRIVATE */ + +/* General macros */ +#define ADI_XINT_CFG_BITS (4u) /*!< number of bits for each external interrupt configuration */ + +/*! Structure to hold callback function and parameter */ +typedef struct _ADI_XINT_CALLBACK_INFO +{ + ADI_CALLBACK pfCallback; /*!< Callback function pointer */ + void *pCBParam; /*!< Callback parameter */ +} ADI_XINT_CALLBACK_INFO; + + +/*! \endcond */ +#endif /* ADI_XINT_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/mbed_rtx.h b/targets/TARGET_Analog_Devices/mbed_rtx.h new file mode 100755 index 0000000000..b4e0ffd011 --- /dev/null +++ b/targets/TARGET_Analog_Devices/mbed_rtx.h @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_MBED_RTX_H +#define MBED_MBED_RTX_H + +#if defined(TARGET_EV_COG_AD3029LZ) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20004000UL) +#endif +#ifndef OS_TASKCNT +#define OS_TASKCNT 6 +#endif +#ifndef OS_MAINSTKSIZE +#define OS_MAINSTKSIZE 112 +#endif +#ifndef OS_CLOCK +#define OS_CLOCK 26000000 +#endif +#ifndef MBED_CONF_APP_THREAD_STACK_SIZE +#define MBED_CONF_APP_THREAD_STACK_SIZE 1024 +#endif + +#elif defined(TARGET_EV_COG_AD4050LZ) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20048000UL) +#endif +#ifndef OS_TASKCNT +#define OS_TASKCNT 6 +#endif +#ifndef OS_MAINSTKSIZE +#define OS_MAINSTKSIZE 112 +#endif +#ifndef OS_CLOCK +#define OS_CLOCK 26000000 +#endif +#ifndef MBED_CONF_APP_THREAD_STACK_SIZE +#define MBED_CONF_APP_THREAD_STACK_SIZE 1024 +#endif + +#endif + +#endif // MBED_MBED_RTX_H diff --git a/targets/targets.json b/targets/targets.json index ccfcd28528..49c9993fe9 100755 --- a/targets/targets.json +++ b/targets/targets.json @@ -109,8 +109,8 @@ "extra_labels": ["NXP", "LPC11UXX"], "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], "supported_toolchains": ["ARM", "uARM", "GCC_ARM"], - "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"], - "default_lib": "small", + "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"], + "default_lib": "small", "device_name": "LPC11U34FBD48/311" }, "MICRONFCBOARD": { @@ -620,6 +620,17 @@ "device_name": "MK64FN1M0xxx12", "bootloader_supported": true }, + "EV_COG_AD4050LZ": { + "inherits": ["Target"], + "core": "Cortex-M4", + "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], + "macros": ["__ADUCM4050__", "EV_COG_AD4050LZ"], + "extra_labels": ["Analog_Devices", "ADUCM4X50", "ADUCM4050", "EV_COG_AD4050LZ", "FLASH_CMSIS_ALGO"], + "device_has": ["SERIAL", "STDIO_MESSAGES", "TRNG", "SLEEP", "INTERRUPTIN", "LOWPOWERTIMER", "RTC", "SPI", "I2C", "FLASH", "ANALOGIN"], + "device_name": "ADuCM4050", + "detect_code": ["0603"], + "release_versions": ["5"] + }, "MTS_GAMBIT": { "inherits": ["Target"], "core": "Cortex-M4F", @@ -2880,7 +2891,7 @@ } } }, - "EFR32MG12P332F1024GL125": { + "EFR32MG12P332F1024GL125": { "inherits": ["EFM32"], "extra_labels_add": ["EFR32MG12", "1024K", "SL_RAIL", "SL_CRYPTO"], "core": "Cortex-M4F", @@ -2890,7 +2901,7 @@ "public": false, "bootloader_supported": true }, - "TB_SENSE_12": { + "TB_SENSE_12": { "inherits": ["EFR32MG12P332F1024GL125"], "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG", "FLASH"], "forced_reset_timeout": 5, From b1b4cfb5dc99af5f87be93e97d8991efd8b5da92 Mon Sep 17 00:00:00 2001 From: Dave Wu Date: Mon, 2 Oct 2017 14:28:25 +1100 Subject: [PATCH 30/80] Fixed issues raised in the feedback from ARM for the ADuCM4050 platform. --- .../device/startup_ADuCM4050.c | 12 --------- .../TARGET_ADUCM4050/api/analogin_api.c | 26 ++++++++----------- .../TARGET_ADUCM4050/api/us_ticker.c | 12 ++++----- targets/TARGET_Analog_Devices/mbed_rtx.h | 26 +------------------ 4 files changed, 18 insertions(+), 58 deletions(-) diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c index b48cc0f83c..f88ee01be8 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c @@ -65,18 +65,6 @@ const uint32_t SECTION_PLACE(blank_checksum[],".checksum") = BLANKX60,BLANKX600 }; -/*---------------------------------------------------------------------------- - A relocated IVT is requested. Provision for IVT relocation - to RAM during startup. This allows for dynamic interrupt - vector patching required by RTOS. Places the relocated IVT - at the start of RAM. We need (72 + 15 + 1)*4 = 352 bytes, - which address 0x20000000. -*----------------------------------------------------------------------------*/ -#ifdef __ICCARM__ -void (*__Relocated___Vectors[NVIC_NUM_VECTORS])(void) @(NVIC_RAM_VECTOR_ADDRESS); -#else -void (*__Relocated___Vectors[NVIC_NUM_VECTORS])(void) __attribute__((at(NVIC_RAM_VECTOR_ADDRESS))); -#endif /* __ICCARM__ */ /*---------------------------------------------------------------------------- External function Declaration diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c index d007006439..b9ef021c19 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c @@ -47,10 +47,6 @@ #include "pinmap.h" #include "PeripheralPins.h" -/** Analogin hal structure. analogin_s is declared in the target's hal - */ -typedef struct analogin_s analogin_t; - #ifdef __cplusplus extern "C" { #endif @@ -99,21 +95,21 @@ void analogin_init(analogin_t *obj, PinName pin) obj->UserBuffer.nChannels = channel; /* Open the ADC device */ - adi_adc_Open(ADC_DEV_NUM, DeviceMemory, sizeof(DeviceMemory),&hDevice); + adi_adc_Open(ADC_DEV_NUM, DeviceMemory, sizeof(DeviceMemory), &hDevice); obj->hDevice = hDevice; /* Power up ADC */ adi_adc_PowerUp (hDevice, true); /* Set ADC reference */ - adi_adc_SetVrefSource (hDevice, ADI_ADC_VREF_SRC_INT_2_50_V); + adi_adc_SetVrefSource(hDevice, ADI_ADC_VREF_SRC_INT_2_50_V); /* Enable ADC sub system */ - adi_adc_EnableADCSubSystem (hDevice, true); + adi_adc_EnableADCSubSystem(hDevice, true); /* Wait untilthe ADC is ready for sampling */ while(bReady == false) { - adi_adc_IsReady (hDevice, &bReady); + adi_adc_IsReady(hDevice, &bReady); } /* Start calibration */ @@ -121,14 +117,14 @@ void analogin_init(analogin_t *obj, PinName pin) /* Wait until calibration is done */ while (!bCalibrationDone) { - adi_adc_IsCalibrationDone (hDevice, &bCalibrationDone); + adi_adc_IsCalibrationDone(hDevice, &bCalibrationDone); } /* Set the delay time */ - adi_adc_SetDelayTime ( hDevice, obj->DelayCycles); + adi_adc_SetDelayTime(hDevice, obj->DelayCycles); /* Set the acquisition time. (Application need to change it based on the impedence) */ - adi_adc_SetAcquisitionTime ( hDevice, obj->SampleCycles); + adi_adc_SetAcquisitionTime(hDevice, obj->SampleCycles); } @@ -155,15 +151,15 @@ uint16_t analogin_read_u16(analogin_t *obj) ADI_ADC_BUFFER *pAdcBuffer; /* Submit the buffer to the driver */ - adi_adc_SubmitBuffer (hDevice, &obj->UserBuffer); + adi_adc_SubmitBuffer(hDevice, &obj->UserBuffer); /* Enable the ADC */ - adi_adc_Enable (hDevice, true); + adi_adc_Enable(hDevice, true); - adi_adc_GetBuffer (hDevice, &pAdcBuffer); + adi_adc_GetBuffer(hDevice, &pAdcBuffer); MBED_ASSERT(pAdcBuffer == &obj->UserBuffer); - return( (uint16_t) ( ((uint16_t *)pAdcBuffer->pDataBuffer)[(pAdcBuffer->nNumConversionPasses) - 1]) ); + return( (uint16_t)( ((uint16_t *)pAdcBuffer->pDataBuffer)[(pAdcBuffer->nNumConversionPasses) - 1]) ); } /* Retrieve te active channel correspondoing to the input pin */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/us_ticker.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/us_ticker.c index f782e4745a..29c53a4716 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/us_ticker.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/us_ticker.c @@ -171,23 +171,23 @@ static void calc_event_counts(uint32_t timestamp) uint64_t aa; calc_time = get_current_time(); - offset = timestamp - calc_time; // offset in useconds + offset = timestamp - calc_time; // offset in useconds - if (offset > 0xf0000000u) // if offset is a really big number, assume that timer has already expired (i.e. negative) + if (offset > 0xf0000000u) // if offset is a really big number, assume that timer has already expired (i.e. negative) offset = 0u; - if (offset > 10u) { // it takes 10us to user timer routine after interrupt. Offset timer to account for that. + if (offset > 10u) { // it takes 10us to user timer routine after interrupt. Offset timer to account for that. offset -= 10u; } else offset = 0u; aa = (uint64_t) offset; - aa *= 26u; // convert from 1MHz to 26MHz clock. todo scale for other clock freqs + aa *= 26u; // convert from 1MHz to 26MHz clock. todo scale for other clock freqs blocks = aa >> 7; - blocks++; // round + blocks++; // round - largecnt = blocks>>1; // communicate to event_timer() routine + largecnt = blocks>>1; // communicate to event_timer() routine } static void event_timer() diff --git a/targets/TARGET_Analog_Devices/mbed_rtx.h b/targets/TARGET_Analog_Devices/mbed_rtx.h index b4e0ffd011..16ab23b8ba 100755 --- a/targets/TARGET_Analog_Devices/mbed_rtx.h +++ b/targets/TARGET_Analog_Devices/mbed_rtx.h @@ -17,35 +17,11 @@ #ifndef MBED_MBED_RTX_H #define MBED_MBED_RTX_H -#if defined(TARGET_EV_COG_AD3029LZ) - -#ifndef INITIAL_SP -#define INITIAL_SP (0x20004000UL) -#endif -#ifndef OS_TASKCNT -#define OS_TASKCNT 6 -#endif -#ifndef OS_MAINSTKSIZE -#define OS_MAINSTKSIZE 112 -#endif -#ifndef OS_CLOCK -#define OS_CLOCK 26000000 -#endif -#ifndef MBED_CONF_APP_THREAD_STACK_SIZE -#define MBED_CONF_APP_THREAD_STACK_SIZE 1024 -#endif - -#elif defined(TARGET_EV_COG_AD4050LZ) +#if defined(TARGET_EV_COG_AD4050LZ) #ifndef INITIAL_SP #define INITIAL_SP (0x20048000UL) #endif -#ifndef OS_TASKCNT -#define OS_TASKCNT 6 -#endif -#ifndef OS_MAINSTKSIZE -#define OS_MAINSTKSIZE 112 -#endif #ifndef OS_CLOCK #define OS_CLOCK 26000000 #endif From f5b6cda0ba01153324f9892e3a9a82de38c46236 Mon Sep 17 00:00:00 2001 From: Dave Wu Date: Mon, 2 Oct 2017 14:36:03 +1100 Subject: [PATCH 31/80] Fixed a merge error for LPC11U34_421. --- targets/targets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 49c9993fe9..1f4543f020 100755 --- a/targets/targets.json +++ b/targets/targets.json @@ -109,7 +109,7 @@ "extra_labels": ["NXP", "LPC11UXX"], "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], "supported_toolchains": ["ARM", "uARM", "GCC_ARM"], - "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"], + "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"], "default_lib": "small", "device_name": "LPC11U34FBD48/311" }, From af8b5d916fe65ca19873f40ecfaf042b1b29986d Mon Sep 17 00:00:00 2001 From: Dave Wu Date: Mon, 2 Oct 2017 15:34:19 +1100 Subject: [PATCH 32/80] - Added definiton for i2c_reset; - Removed unneeded code from i2c and serial modules. --- .../TARGET_ADUCM4050/api/i2c_api.c | 38 ++++--------------- .../TARGET_ADUCM4050/api/serial_api.c | 38 ------------------- 2 files changed, 8 insertions(+), 68 deletions(-) diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c index 7a883ff245..afa0312f47 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c @@ -191,7 +191,14 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) void i2c_reset(i2c_t *obj) { - return; + ADI_I2C_RESULT I2C_Return; + ADI_I2C_HANDLE I2C_Handle = *obj->pI2C_Handle; + + I2C_Return = adi_i2c_Reset(I2C_Handle); + if (I2C_Return) { + obj->error = I2C_EVENT_ERROR; + return; + } } @@ -206,33 +213,4 @@ int i2c_byte_write(i2c_t *obj, int data) return 0; } - - -#if DEVICE_I2CSLAVE -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - -} - -int i2c_slave_receive(i2c_t *obj) -{ - -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - return length; -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - return length; -} - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - -} -#endif // #if DEVICE_I2CSLAVE - #endif // #if DEVICE_I2C diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c index 8764be8803..0a118c0cca 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c @@ -302,44 +302,6 @@ void serial_break_clear(serial_t *obj) adi_uart_ForceTxBreak(hDevice[obj->index], false); } -#if DEVICE_SERIAL_ASYNCH -uint8_t serial_tx_active(serial_t *obj) -{ - return 0; -} - -uint8_t serial_rx_active(serial_t *obj) -{ - return 0; -} - -int serial_irq_handler_asynch(serial_t *obj) -{ - return 0; -} - - - -int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) -{ - return 0; -} - -void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) -{ - -} - -void serial_tx_abort_asynch(serial_t *obj) -{ - -} - -void serial_rx_abort_asynch(serial_t *obj) -{ - -} -#endif void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { From aa6872523e3ad206db25b38e08f40ccc444ec7ff Mon Sep 17 00:00:00 2001 From: Dave Wu Date: Tue, 3 Oct 2017 14:21:37 +1100 Subject: [PATCH 33/80] - Fixed an issue where the TRNG device is read even when it is not ready; - Added a configuration call in trng_init to make sure the TRNG buffering mode is disabled, so only 8-bit bytes are returned; - Moved the TRNG device handle into the trng_t structure; - Fixed some formatting errors in the adc driver. --- .../TARGET_ADUCM4050/api/analogin_api.c | 6 +-- .../TARGET_ADUCM4050/api/objects.h | 4 +- .../TARGET_ADUCM4050/api/trng_api.c | 42 ++++++++++++------- 3 files changed, 33 insertions(+), 19 deletions(-) diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c index b9ef021c19..06413a81d6 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c @@ -99,7 +99,7 @@ void analogin_init(analogin_t *obj, PinName pin) obj->hDevice = hDevice; /* Power up ADC */ - adi_adc_PowerUp (hDevice, true); + adi_adc_PowerUp(hDevice, true); /* Set ADC reference */ adi_adc_SetVrefSource(hDevice, ADI_ADC_VREF_SRC_INT_2_50_V); @@ -113,7 +113,7 @@ void analogin_init(analogin_t *obj, PinName pin) } /* Start calibration */ - adi_adc_StartCalibration (hDevice); + adi_adc_StartCalibration(hDevice); /* Wait until calibration is done */ while (!bCalibrationDone) { @@ -198,7 +198,7 @@ static uint32_t adi_pin2channel(PinName pin) break; } - return((uint32_t) activech); + return ((uint32_t)activech); } diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h index 7b316f5c32..aeecf36d00 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h @@ -44,8 +44,8 @@ #include "cmsis.h" #include "PeripheralNames.h" #include "PinNames.h" -//#include "target_config.h" #include "gpio_object.h" +#include "adi_rng.h" #include "adi_i2c.h" #include "adi_spi.h" @@ -69,7 +69,7 @@ struct serial_s { }; struct trng_s { - uint8_t dummy; + ADI_RNG_HANDLE RNGhDevice; }; #define BUILD_I2C_MI_DYNAMIC diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c index 4012775454..8106f44e59 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c @@ -52,44 +52,58 @@ #define TRNG_CNT_VAL 4095 #define TRNG_PRESCALER 2 -static ADI_RNG_HANDLE RNGhDevice; /* Memory to handle CRC Device */ -static uint32_t RngDevMem[(ADI_RNG_MEMORY_SIZE + 3)/4]; /* Data buffers for Random numbers */ +/* Data buffers for Random numbers */ +static uint32_t RngDevMem[(ADI_RNG_MEMORY_SIZE + 3)/4]; void trng_init(trng_t *obj) { - (void)obj; + ADI_RNG_HANDLE RNGhDevice; + + // Open the device adi_rng_Open(0,RngDevMem,sizeof(RngDevMem),&RNGhDevice); // Set sample length for the H/W RN accumulator adi_rng_SetSampleLen(RNGhDevice, TRNG_PRESCALER, TRNG_CNT_VAL); - // Enable the RNG + // Disable buffering - single byte generation only + adi_rng_EnableBuffering(RNGhDevice, false); + + // Enable the TRNG adi_rng_Enable(RNGhDevice, true); + + // Save device handle + obj->RNGhDevice = RNGhDevice; } void trng_free(trng_t *obj) { - (void)obj; + ADI_RNG_HANDLE RNGhDevice = obj->RNGhDevice; + adi_rng_Enable(RNGhDevice, false); adi_rng_Close(RNGhDevice); } int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) { - (void)obj; + ADI_RNG_HANDLE RNGhDevice = obj->RNGhDevice; bool bRNGRdy; uint32_t nRandomNum, i; - for (i = 0; i < length; ) { - // wait for the RNG ready to give a random number - adi_rng_GetRdyStatus(RNGhDevice, &bRNGRdy); - if (bRNGRdy) { - // read the random number - adi_rng_GetRngData(RNGhDevice, &nRandomNum); - output[i++] = (uint8_t) nRandomNum; - } + for (i = 0; i < length; i++) { + // Loop until the device has data to be read + do { + adi_rng_GetRdyStatus(RNGhDevice, &bRNGRdy); + } while (!bRNGRdy); + + // Read the RNG + adi_rng_GetRngData(RNGhDevice, &nRandomNum); + + // Save the output + output[i] = (uint8_t)nRandomNum; } + *output_length = length; + return 0; } From 78d8379a82457f4df76ba5dc586a84e3e9ffafe4 Mon Sep 17 00:00:00 2001 From: Dave Wu Date: Tue, 3 Oct 2017 15:00:42 +1100 Subject: [PATCH 34/80] Removed undefined spi slave related functions. --- .../TARGET_ADUCM4050/api/spi_api.c | 35 ------------------- 1 file changed, 35 deletions(-) diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c index a17dea1ab6..b788e5b2ad 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c @@ -287,41 +287,6 @@ int spi_master_write(spi_t *obj, int value) } -/** Check if a value is available to read - * - * @param[in] obj The SPI peripheral to check - * @return non-zero if a value is available - */ -int spi_slave_receive(spi_t *obj) -{ - return 0; -} - - -/** Get a received value out of the SPI receive buffer in slave mode - * - * Blocks until a value is available - * @param[in] obj The SPI peripheral to read - * @return The value received - */ -int spi_slave_read(spi_t *obj) -{ - return 0; -} - - -/** Write a value to the SPI peripheral in slave mode - * - * Blocks until the SPI peripheral can be written to - * @param[in] obj The SPI peripheral to write - * @param[in] value The value to write - */ -void spi_slave_write(spi_t *obj, int value) -{ - return; -} - - /** Write a block out in master mode and receive a value * * The total number of bytes sent and recieved will be the maximum of From 1a0470f86969dc1f6cf2f8d8bf5b20548539442d Mon Sep 17 00:00:00 2001 From: Dave Wu Date: Tue, 3 Oct 2017 17:32:10 +1100 Subject: [PATCH 35/80] Removed the custom app thread stack size. --- targets/TARGET_Analog_Devices/mbed_rtx.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/targets/TARGET_Analog_Devices/mbed_rtx.h b/targets/TARGET_Analog_Devices/mbed_rtx.h index 16ab23b8ba..199b04fde8 100755 --- a/targets/TARGET_Analog_Devices/mbed_rtx.h +++ b/targets/TARGET_Analog_Devices/mbed_rtx.h @@ -25,9 +25,6 @@ #ifndef OS_CLOCK #define OS_CLOCK 26000000 #endif -#ifndef MBED_CONF_APP_THREAD_STACK_SIZE -#define MBED_CONF_APP_THREAD_STACK_SIZE 1024 -#endif #endif From 477c728b612e13ba39aae28d63324b70f9b34bb0 Mon Sep 17 00:00:00 2001 From: Dave Wu Date: Mon, 9 Oct 2017 17:13:58 +1100 Subject: [PATCH 36/80] - Added error checking for trng_get_bytes function; - Added curly brackets to single line conditions in gpio_qpi.c and gpio_irq_api.c; - Changed rx and tx buffers in serial module as local variables; - Minor i2c & spi updates for github pull request; - Added function definition for spi_master_block_write. --- .../TARGET_ADUCM4050/api/gpio_api.c | 11 ++++--- .../TARGET_ADUCM4050/api/gpio_irq_api.c | 31 ++++++++++++------- .../TARGET_ADUCM4050/api/i2c_api.c | 12 ++++--- .../TARGET_ADUCM4050/api/serial_api.c | 8 ++--- .../TARGET_ADUCM4050/api/spi_api.c | 23 +++++++++++++- .../TARGET_ADUCM4050/api/trng_api.c | 16 ++++++++-- 6 files changed, 74 insertions(+), 27 deletions(-) diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c index c338d84275..81d4be52cb 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c @@ -71,13 +71,15 @@ void gpio_init(gpio_t *obj, PinName pin) { obj->pin = pin; - if (pin == (PinName)NC) + if (pin == (PinName)NC) { return; + } // Initialize the GPIO driver. This function // initializes the GPIO driver only once globally. - if (!gpio_initialized) + if (!gpio_initialized) { adi_gpio_Init(gpioMemory, ADI_GPIO_MEMORY_SIZE); + } pin_function(pin, MUX_FUNC_0); } @@ -134,11 +136,12 @@ int gpio_read(gpio_t *obj) uint16_t Data; // check whether the pin is configured as input or output - if ((gpio_oen[port] >> pin_num) & 1) + if ((gpio_oen[port] >> pin_num) & 1) { Data = gpio_output_val[port] & (1 << pin_num); - else + } else { // otherwise call GetData adi_gpio_GetData((ADI_GPIO_PORT)port, (1 << pin_num), &Data); + } return ((((uint32_t)Data) >> pin_num) & 1); } diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c index ae5b8234c3..3cf237218b 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c @@ -183,8 +183,9 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 uint32_t pin_num = pin & 0xFF; // check for valid pin and ID - if ((pin == NC) || (id == 0)) + if ((pin == NC) || (id == 0)) { return -1; + } // make sure gpio driver has been initialized if (!gpio_initialized) { @@ -193,8 +194,9 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 } // save the handler - if (handler) + if (handler) { irq_handler = handler; + } // disable the interrupt for the given pin disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num); @@ -242,16 +244,18 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; uint32_t pin_num = obj->pinname & 0xFF; - if (event == IRQ_NONE) + if (event == IRQ_NONE) { return; + } // read the current polarity register adi_gpio_GetGroupInterruptPolarity((ADI_GPIO_PORT)port, 1 << pin_num, &int_polarity_reg); - if (event == IRQ_RISE) + if (event == IRQ_RISE) { int_polarity_reg |= (1 << pin_num); - else + } else { int_polarity_reg &= ~(1 << pin_num); + } // set the polarity register adi_gpio_SetGroupInterruptPolarity((ADI_GPIO_PORT)port, int_polarity_reg); @@ -259,10 +263,11 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) channel_ids[port][pin_num].event = event; // enable interrupt for this pin if enable flag is set - if (enable) + if (enable) { gpio_irq_enable(obj); - else + } else { gpio_irq_disable(obj); + } } /** Enable GPIO IRQ @@ -275,8 +280,9 @@ void gpio_irq_enable(gpio_irq_t *obj) uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; uint32_t pin_num = obj->pinname & 0xFF; - if (channel_ids[port][pin_num].event == IRQ_NONE) + if (channel_ids[port][pin_num].event == IRQ_NONE) { return; + } // Group all RISE interrupts in INTA and FALL interrupts in INTB if (channel_ids[port][pin_num].event == IRQ_RISE) { @@ -302,14 +308,17 @@ void gpio_irq_disable(gpio_irq_t *obj) uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; uint32_t pin_num = obj->pinname & 0xFF; - if (channel_ids[port][pin_num].event == IRQ_NONE) + if (channel_ids[port][pin_num].event == IRQ_NONE) { return; + } // Group all RISE interrupts in INTA and FALL interrupts in INTB - if (channel_ids[port][pin_num].event == IRQ_RISE) + if (channel_ids[port][pin_num].event == IRQ_RISE) { disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num); - else if (channel_ids[port][pin_num].event == IRQ_FALL) + } + else if (channel_ids[port][pin_num].event == IRQ_FALL) { disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num); + } channel_ids[port][pin_num].int_enable = 0; } diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c index afa0312f47..f25d80c910 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c @@ -110,13 +110,15 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) int i2c_start(i2c_t *obj) { - return 0; + /* The Hardware does not support this feature. */ + return -1; } int i2c_stop(i2c_t *obj) { - return 0; + /* The Hardware does not support this feature. */ + return -1; } @@ -204,13 +206,15 @@ void i2c_reset(i2c_t *obj) int i2c_byte_read(i2c_t *obj, int last) { - return 0; + /* The Hardware does not support this feature. */ + return -1; } int i2c_byte_write(i2c_t *obj, int data) { - return 0; + /* The Hardware does not support this feature. */ + return -1; } #endif // #if DEVICE_I2C diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c index 0a118c0cca..c6af733fad 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c @@ -53,16 +53,16 @@ #include "PeripheralPins.h" #include "drivers/uart/adi_uart.h" #define ADI_UART_MEMORY_SIZE (ADI_UART_BIDIR_MEMORY_SIZE) -#define ADI_UART_NUM_DEVICES 2 +#define ADI_UART_NUM_DEVICES 2 -static ADI_UART_HANDLE hDevice[ADI_UART_NUM_DEVICES]; +static ADI_UART_HANDLE hDevice[ADI_UART_NUM_DEVICES]; static uint32_t UartDeviceMem[ADI_UART_NUM_DEVICES][(ADI_UART_MEMORY_SIZE + 3)/4]; static uint32_t serial_irq_ids[ADI_UART_NUM_DEVICES] = {0}; static uart_irq_handler irq_handler = NULL; int stdio_uart_inited = 0; serial_t stdio_uart; -int rxbuffer[2]; -int txbuffer[2]; +static int rxbuffer[2]; +static int txbuffer[2]; static void uart_callback(void *pCBParam, uint32_t Event, void *pArg) { diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c index b788e5b2ad..76015a4b2d 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c @@ -305,7 +305,28 @@ int spi_master_write(spi_t *obj, int value) */ int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) { - return 0; + ADI_SPI_TRANSCEIVER transceive; + ADI_SPI_HANDLE SPI_Handle; + ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; + + transceive.pReceiver = rx_buffer; + transceive.ReceiverBytes = rx_length; /* link transceive data size to the remaining count */ + transceive.nRxIncrement = 1; /* auto increment buffer */ + transceive.pTransmitter = tx_buffer; /* initialize data attributes */ + transceive.TransmitterBytes = tx_length; /* link transceive data size to the remaining count */ + transceive.nTxIncrement = 1; /* auto increment buffer */ + + transceive.bDMA = false; + transceive.bRD_CTL = false; + SPI_Handle = *obj->pSPI_Handle; + SPI_Return = adi_spi_MasterReadWrite(SPI_Handle, &transceive); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return -1; + } + else { + return((int)tx_length); + } } #endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c index 8106f44e59..de9d710697 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c @@ -88,18 +88,28 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l ADI_RNG_HANDLE RNGhDevice = obj->RNGhDevice; bool bRNGRdy; uint32_t nRandomNum, i; + ADI_RNG_RESULT result; for (i = 0; i < length; i++) { // Loop until the device has data to be read do { - adi_rng_GetRdyStatus(RNGhDevice, &bRNGRdy); + result = adi_rng_GetRdyStatus(RNGhDevice, &bRNGRdy); + if (result != ADI_RNG_SUCCESS) + { + return -1; + } } while (!bRNGRdy); // Read the RNG - adi_rng_GetRngData(RNGhDevice, &nRandomNum); + result = adi_rng_GetRngData(RNGhDevice, &nRandomNum); + + if (result != ADI_RNG_SUCCESS) + { + return -1; + } // Save the output - output[i] = (uint8_t)nRandomNum; + output[i] = (uint8_t)(nRandomNum & 0xFF); } *output_length = length; From 46eae9f86254441146d6aac90905ee4e74b13c1d Mon Sep 17 00:00:00 2001 From: Dave Wu Date: Mon, 9 Oct 2017 17:28:46 +1100 Subject: [PATCH 37/80] Added curly brackets for the single line if else statement. --- .../TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.c index c323b51ca5..b6ea83f1ed 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.c @@ -189,10 +189,11 @@ void set_clock_gating(peripheral_clk_t eClk, int enable) } // if enable, set the bit otherwise clear the bit - if (enable) + if (enable) { pADI_CLKG0_CLK->CTL5 |= flag; - else + } else { pADI_CLKG0_CLK->CTL5 &= (~flag); + } } From a85563bcc51d6a72165651e350af8a114c7f43e6 Mon Sep 17 00:00:00 2001 From: Dave Wu Date: Wed, 11 Oct 2017 15:06:49 +1100 Subject: [PATCH 38/80] - Cleaned up some formatting issues; - Fixed a build error in spi_master_block_write; - Some clean up in serai_api. --- .../TARGET_ADUCM4050/api/cmsis.h | 1 + .../TARGET_ADUCM4050/api/lp_ticker_api.c | 12 +-- .../TARGET_ADUCM4050/api/objects.h | 2 +- .../TARGET_ADUCM4050/api/serial_api.c | 85 +++---------------- .../TARGET_ADUCM4050/api/spi_api.c | 23 +++-- 5 files changed, 30 insertions(+), 93 deletions(-) diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis.h index 2d2850cc2e..b0439b1db0 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis.h +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis.h @@ -43,4 +43,5 @@ #define __C #include "adi_processor.h" #include "cmsis_nvic.h" +#undef __C #endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/lp_ticker_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/lp_ticker_api.c index 5d46471c4a..addb198aa6 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/lp_ticker_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/lp_ticker_api.c @@ -120,7 +120,7 @@ static int set_rtc_alarm_interrupt(ADI_RTC_HANDLE const hDevice, uint32_t nAlarm * Local RTC 1 ISR callback function. * */ -static void rtc1_Callback (void *pCBParam, uint32_t nEvent, void *EventArg) +static void rtc1_Callback(void *pCBParam, uint32_t nEvent, void *EventArg) { /* process RTC interrupts (cleared by driver) */ if (ADI_RTC_ALARM_INT & nEvent) { @@ -129,16 +129,6 @@ static void rtc1_Callback (void *pCBParam, uint32_t nEvent, void *EventArg) } -/** Get low power ticker's data - * - * @return The low power ticker data - */ -/* -const ticker_data_t* get_lp_ticker_data() -{ -}*/ - - /* HAL lp ticker */ /** Initialize the low power ticker diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h index aeecf36d00..495faf8c67 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h @@ -85,7 +85,7 @@ struct i2c_s { #define BUILD_SPI_MI_DYNAMIC struct spi_s { - uint32_t instance; + uint32_t instance; uint32_t error; ADI_SPI_HANDLE *pSPI_Handle; #if defined(BUILD_SPI_MI_DYNAMIC) diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c index c6af733fad..fabe28d035 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c @@ -135,24 +135,26 @@ void serial_baud(serial_t *obj, int baudrate) void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { - int convertedparity = ADI_UART_NO_PARITY; - int convertedstopbits = ADI_UART_ONE_STOPBIT; + ADI_UART_PARITY convertedparity = ADI_UART_NO_PARITY; + ADI_UART_STOPBITS convertedstopbits = ADI_UART_ONE_STOPBIT; - if (stop_bits) + if (stop_bits) { convertedstopbits = ADI_UART_ONE_AND_HALF_TWO_STOPBITS; + } - if (parity == ParityOdd) + if (parity == ParityOdd) { convertedparity = ADI_UART_ODD_PARITY; - else if (parity == ParityEven) + } else if (parity == ParityEven) { convertedparity = ADI_UART_EVEN_PARITY; - else if (parity == ParityForced1) + } else if (parity == ParityForced1) { convertedparity = ADI_UART_ODD_PARITY_STICKY; - else if (parity == ParityForced0) + } else if (parity == ParityForced0) { convertedparity = ADI_UART_EVEN_PARITY_STICKY; + } - adi_uart_SetConfiguration(hDevice[obj->index], convertedparity, convertedstopbits, (data_bits - 5)); + adi_uart_SetConfiguration(hDevice[obj->index], convertedparity, convertedstopbits, + (ADI_UART_WORDLEN)(data_bits - 5)); } -#ifndef ADI_UART_TRANSFER_MODE void serial_init(serial_t *obj, PinName tx, PinName rx) { @@ -212,71 +214,6 @@ void serial_putc(serial_t *obj, int c) return; } -#else - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); - uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); - - obj->index = pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT((int)obj->index != NC); - - adi_uart_Open(obj->index, ADI_UART_DIR_BIDIRECTION, UartDeviceMem[obj->index], ADI_UART_MEMORY_SIZE, &hDevice[obj->index]); - - serial_baud(obj, 9600); - serial_format(obj, 8, ParityNone, 1); - - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - - if (rx != NC) { - pin_mode(rx, PullUp); - } - - if (obj->index == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } - - // set maximum FIFO depth - adi_uart_SetRxFifoTriggerLevel(hDevice[obj->index], ADI_UART_RX_FIFO_TRIG_LEVEL_14BYTE); - - // enable FIFO - adi_uart_EnableFifo(hDevice[obj->index], true); -} - -int serial_getc(serial_t *obj) -{ - int c; - uint32_t hwErr; - - adi_uart_Read(hDevice[obj->index], (void *) &c, 1, false, &hwErr); - return (c); -} - -void serial_putc(serial_t *obj, int c) -{ - uint32_t hwErr; - - adi_uart_Write(hDevice[obj->index], &c, 1, false, &hwErr); - return; -} - -int serial_readable(serial_t *obj) -{ - return 0; -} - -int serial_writable(serial_t *obj) -{ - return 0; -} -#endif void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { MBED_ASSERT(obj); diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c index 76015a4b2d..a52406889b 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c @@ -213,15 +213,24 @@ void spi_free(spi_t *obj) * 2 | 1 0 * 3 | 1 1 * @endcode + + bool phase; + true : trailing-edge + false : leading-edge + + bool polarity; + true : CPOL=1 (idle high) polarity + false : CPOL=0 (idle-low) polarity */ void spi_format(spi_t *obj, int bits, int mode, int slave) { ADI_SPI_HANDLE SPI_Handle; ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; - bool_t master; + bool master; master = !((bool_t)slave); SPI_Handle = *obj->pSPI_Handle; + SPI_Return = adi_spi_SetMasterMode(SPI_Handle, master); if (SPI_Return) { obj->error = SPI_EVENT_ERROR; @@ -309,12 +318,12 @@ int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, cha ADI_SPI_HANDLE SPI_Handle; ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; - transceive.pReceiver = rx_buffer; - transceive.ReceiverBytes = rx_length; /* link transceive data size to the remaining count */ - transceive.nRxIncrement = 1; /* auto increment buffer */ - transceive.pTransmitter = tx_buffer; /* initialize data attributes */ - transceive.TransmitterBytes = tx_length; /* link transceive data size to the remaining count */ - transceive.nTxIncrement = 1; /* auto increment buffer */ + transceive.pReceiver = (uint8_t*)rx_buffer; + transceive.ReceiverBytes = rx_length; /* link transceive data size to the remaining count */ + transceive.nRxIncrement = 1; /* auto increment buffer */ + transceive.pTransmitter = (uint8_t*)tx_buffer; /* initialize data attributes */ + transceive.TransmitterBytes = tx_length; /* link transceive data size to the remaining count */ + transceive.nTxIncrement = 1; /* auto increment buffer */ transceive.bDMA = false; transceive.bRD_CTL = false; From c4220ece9b34a601c30c90dba9e1b26186a85cd6 Mon Sep 17 00:00:00 2001 From: Dave Wu Date: Thu, 12 Oct 2017 12:46:54 +1100 Subject: [PATCH 39/80] Added default delay and sample times for the ADC during initialization. --- .../TARGET_ADUCM4050/api/analogin_api.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c index 06413a81d6..baa96a694e 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c @@ -94,6 +94,22 @@ void analogin_init(analogin_t *obj, PinName pin) MBED_ASSERT(channel != 0xFFFFFFFF); obj->UserBuffer.nChannels = channel; + /* Set ACLK to CCLK/16 */ + adi_pwr_SetClockDivider(ADI_CLOCK_ACLK,16); + + /* Set default values for conversion and delay cycles. This sets up a sampling rate of + 16kHz. The sampling frequency is worked out from the following: + + if delay time > 0: + Fs = ACLK / [((14 + sampling time) * oversample factor) + (delay time + 2)] + if delay time = 0: + Fs = ACLK / ((14 + sampling time) * oversample factor) + + The sampling (or acquisition) and delay times are in number of ACLK clock cycles. + */ + obj->DelayCycles = 0; + obj->SampleCycles = 88; + /* Open the ADC device */ adi_adc_Open(ADC_DEV_NUM, DeviceMemory, sizeof(DeviceMemory), &hDevice); obj->hDevice = hDevice; From 41c6084a1ebda43d7384e572e203469e64ae0117 Mon Sep 17 00:00:00 2001 From: "dave.wu@analog.com" Date: Mon, 30 Oct 2017 02:16:55 +0100 Subject: [PATCH 40/80] - Added code to clear temporary variable on the stack before exiting the trng_get_bytes; - Removed lp ticker as it does not satisfy the requirements of the lp timer. --- .../TARGET_ADUCM4050/api/lp_ticker_api.c | 259 ------------------ .../TARGET_ADUCM4050/api/trng_api.c | 3 + targets/targets.json | 2 +- 3 files changed, 4 insertions(+), 260 deletions(-) delete mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/lp_ticker_api.c diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/lp_ticker_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/lp_ticker_api.c deleted file mode 100755 index addb198aa6..0000000000 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/lp_ticker_api.c +++ /dev/null @@ -1,259 +0,0 @@ -/******************************************************************************* - * Copyright (c) 2010-2017 Analog Devices, Inc. - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - Modified versions of the software must be conspicuously marked as such. - * - This software is licensed solely and exclusively for use with processors - * manufactured by or for Analog Devices, Inc. - * - This software may not be combined or merged with other code in any manner - * that would cause the software to become subject to terms and conditions - * which differ from those listed here. - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - The use of this software may or may not infringe the patent rights of one - * or more patent holders. This license does not release you from the - * requirement that you obtain separate licenses from these patent holders - * to use this software. - * - * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- - * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF - * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************/ - -#include -#include "lp_ticker_api.h" -#include -#include -#include "adi_rtc_def.h" - - -#ifdef DEVICE_LOWPOWERTIMER - -// define base LF clock frequncy in Hz -#define LFCLK_FREQUENCY_HZ 32768 -// RTC prescaler for the LF clock -#define RTC_PRESCALER 0 - -/* time for each tick of the LF clock in us */ -#define TIME_US_PER_TICK ((float)1000000/(float)(LFCLK_FREQUENCY_HZ>>RTC_PRESCALER)) - -// The number of RTC clock ticks it takes to set & enable the alarm -#define TICKS_TO_ENABLE_ALARM 10 - -// Mask to limit the value of the RTC value to 27 bits so the converted time in us fits -// in 32-bits -#define MAX_TICK_MASK ((1 << 27) - 1) - -static unsigned char rtc1_memory[ADI_RTC_MEMORY_SIZE]; -static ADI_RTC_HANDLE hRTC1_Device; - - -/** - * \defgroup hal_LpTicker Low Power Ticker Functions - * @{ - */ -/** - * Local stream-lined alarm setting function. - * - */ -static int set_rtc_alarm_interrupt(ADI_RTC_HANDLE const hDevice, uint32_t nAlarm) -{ - ADI_RTC_DEVICE *pDevice = hDevice; - uint16_t cr0; - ADI_INT_STATUS_ALLOC(); - - // Section to enable interrupts - // The interrupt used is ADI_RTC_ALARM_INT - // Set the Alarm interrupt enable and Alarm enable bits in cr0 - cr0 = BITM_RTC_CR0_ALMEN | (1u << BITP_RTC_CR0_ALMINTEN); - - // Set the alarm value - /* Wait till previously posted write to Alram Register to complete */ - PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1)) - - ADI_ENTER_CRITICAL_REGION(); - /* Program the alarm count registers. */ - pDevice->pRTCRegs->ALM0 = (uint16_t)nAlarm; - pDevice->pRTCRegs->ALM1 = (uint16_t)(nAlarm >> 16); - pDevice->pRTCRegs->ALM2 = 0u; - ADI_EXIT_CRITICAL_REGION(); - - /* Wait till write to Control Register to take effect */ - SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1)) - - // Enable alarm - /* Wait till previously posted write to Control Register to complete */ - PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDALM1|BITM_RTC_SR1_WPNDALM0) - - ADI_ENTER_CRITICAL_REGION(); - /* set RTC alarm and interrupt enable */ - pDevice->pRTCRegs->CR0 |= cr0; - ADI_EXIT_CRITICAL_REGION(); - - /* Wait till write to Control Register to take effect */ - SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) - - return ADI_RTC_SUCCESS; -} - - - -/** - * Local RTC 1 ISR callback function. - * - */ -static void rtc1_Callback(void *pCBParam, uint32_t nEvent, void *EventArg) -{ - /* process RTC interrupts (cleared by driver) */ - if (ADI_RTC_ALARM_INT & nEvent) { - lp_ticker_irq_handler(); - } -} - - -/* HAL lp ticker */ - -/** Initialize the low power ticker - * - */ -void lp_ticker_init() -{ - // open the rtc device - adi_rtc_Open(1, rtc1_memory, ADI_RTC_MEMORY_SIZE, &hRTC1_Device); - - // set the prescaler value - adi_rtc_SetPreScale(hRTC1_Device, RTC_PRESCALER); - - // register call back for events - adi_rtc_RegisterCallback(hRTC1_Device, rtc1_Callback, hRTC1_Device); - - // reset the RTC counter - adi_rtc_SetCount(hRTC1_Device, 0); - - // set the trim value - adi_rtc_SetTrim(hRTC1_Device, ADI_RTC_TRIM_INTERVAL_14, ADI_RTC_TRIM_1, ADI_RTC_TRIM_SUB); - - adi_rtc_EnableTrim(hRTC1_Device, true); - - // enable the RTC - adi_rtc_Enable(hRTC1_Device, true); -} - -/** Read the current counter - * - * @return The current timer's counter value in microseconds - */ -uint32_t lp_ticker_read() -{ - uint32_t count; - float t; - - // get current count - adi_rtc_GetCount(hRTC1_Device, &count); - - // Throw away top 5 bits to avoid overflow and convert ticks to us - count &= MAX_TICK_MASK; - t = (float)count * TIME_US_PER_TICK; - - return (uint32_t)t; -} - -/** Set interrupt for specified timestamp - * - * @param timestamp The time in microseconds to be set - */ -void lp_ticker_set_interrupt(timestamp_t timestamp) -{ - uint32_t rtcCount, trunc_rtcCount, set_tick, tick_delta, alarm_tick; - - // compute the tick value based on the given alarm time - set_tick = (uint32_t)((float)(timestamp) / TIME_US_PER_TICK); - - // get current count - adi_rtc_GetCount(hRTC1_Device, &rtcCount); - - // compute the number of ticks required for the alarm - trunc_rtcCount = rtcCount & MAX_TICK_MASK; - - // if set_tick is less than the current RTC count, the counter has - // missed the desired time, so set tick_delta to 0 - if (set_tick >= trunc_rtcCount) { - tick_delta = set_tick - trunc_rtcCount; - } else { - tick_delta = 0; - } - - // compute the absolute RTC alarm count required - alarm_tick = rtcCount + tick_delta; - - // check if the desired alarm duration is less than TICKS_TO_ENABLE_ALARM, - // if so just wait it out rather than setting the alarm - if (tick_delta <= TICKS_TO_ENABLE_ALARM) { - // otherwise if the alarm time is less than the current RTC count + the time - // it takes to enable the alarm, just wait until the desired number of counts - // has expired rather than using the interrupt, then call the user ISR directly. - do { - adi_rtc_GetCount(hRTC1_Device, &rtcCount); - } while (rtcCount < alarm_tick); - - rtc1_Callback(NULL, ADI_RTC_ALARM_INT, NULL); - return; - } - - // set the alarm otherwise - set_rtc_alarm_interrupt(hRTC1_Device, alarm_tick); -} - -/** Disable low power ticker interrupt - * - */ -void lp_ticker_disable_interrupt() -{ - adi_rtc_EnableInterrupts(hRTC1_Device, ADI_RTC_ALARM_INT, false); -} - -/** Clear the low power ticker interrupt - * - */ -void lp_ticker_clear_interrupt() -{ - ADI_RTC_DEVICE *pDevice = hRTC1_Device; - - NVIC_ClearPendingIRQ(pDevice->eIRQn); - - return; -} - - -/** Set pending interrupt that should be fired right away. - * - * The ticker should be initialized prior calling this function. - */ -void lp_ticker_fire_interrupt(void) -{ - ADI_RTC_DEVICE *pDevice = hRTC1_Device; - - NVIC_SetPendingIRQ(pDevice->eIRQn); -} - - -#endif -/**@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c index de9d710697..64fe535f84 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c @@ -110,6 +110,9 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l // Save the output output[i] = (uint8_t)(nRandomNum & 0xFF); + + // Clear the nRandomNum variable for security purposes + nRandomNum = 0; } *output_length = length; diff --git a/targets/targets.json b/targets/targets.json index 1f4543f020..9284911b83 100755 --- a/targets/targets.json +++ b/targets/targets.json @@ -626,7 +626,7 @@ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], "macros": ["__ADUCM4050__", "EV_COG_AD4050LZ"], "extra_labels": ["Analog_Devices", "ADUCM4X50", "ADUCM4050", "EV_COG_AD4050LZ", "FLASH_CMSIS_ALGO"], - "device_has": ["SERIAL", "STDIO_MESSAGES", "TRNG", "SLEEP", "INTERRUPTIN", "LOWPOWERTIMER", "RTC", "SPI", "I2C", "FLASH", "ANALOGIN"], + "device_has": ["SERIAL", "STDIO_MESSAGES", "TRNG", "SLEEP", "INTERRUPTIN", "RTC", "SPI", "I2C", "FLASH", "ANALOGIN"], "device_name": "ADuCM4050", "detect_code": ["0603"], "release_versions": ["5"] From f53e037f1f737c467c4d43d718292d70b95a6444 Mon Sep 17 00:00:00 2001 From: Dave Wu Date: Thu, 2 Nov 2017 15:50:55 +1100 Subject: [PATCH 41/80] Added a check for the STUCK bit before reading the RNG data register to ensure there are no hardware faults. --- .../TARGET_ADUCM4050/api/trng_api.c | 34 +++++++++++++------ 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c index 64fe535f84..cfab85645d 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c @@ -43,6 +43,7 @@ #include #include #include +#include "adi_rng_def.h" #include "cmsis.h" #include "trng_api.h" @@ -86,37 +87,48 @@ void trng_free(trng_t *obj) int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) { ADI_RNG_HANDLE RNGhDevice = obj->RNGhDevice; - bool bRNGRdy; - uint32_t nRandomNum, i; + bool bRNGRdy, bStuck; + uint32_t i; + volatile uint32_t nRandomNum; ADI_RNG_RESULT result; + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)RNGhDevice; for (i = 0; i < length; i++) { // Loop until the device has data to be read do { result = adi_rng_GetRdyStatus(RNGhDevice, &bRNGRdy); - if (result != ADI_RNG_SUCCESS) - { + if (result != ADI_RNG_SUCCESS) { return -1; } } while (!bRNGRdy); - // Read the RNG - result = adi_rng_GetRngData(RNGhDevice, &nRandomNum); + // Check the STUCK bit to make sure the oscillator output isn't stuck + result = adi_rng_GetStuckStatus(RNGhDevice, &bStuck); - if (result != ADI_RNG_SUCCESS) - { + // If the stuck bit is set, this means there may be a problem with RNG hardware, + // exit with an error + if ( (result != ADI_RNG_SUCCESS) || ((result == ADI_RNG_SUCCESS) && (bStuck)) ) { + // Clear the STUCK bit by writing a 1 to it + pDevice->pRNG->STAT |= BITM_RNG_STAT_STUCK; + return -1; + } + + // Read the RNG + result = adi_rng_GetRngData(RNGhDevice, (uint32_t*)(&nRandomNum)); + + if (result != ADI_RNG_SUCCESS) { return -1; } // Save the output output[i] = (uint8_t)(nRandomNum & 0xFF); - - // Clear the nRandomNum variable for security purposes - nRandomNum = 0; } *output_length = length; + // Clear nRandomNum on the stack before exiting + nRandomNum = 0; + return 0; } From 5408dae639543098dd1795d07102b9978e70debe Mon Sep 17 00:00:00 2001 From: Dave Wu Date: Thu, 9 Nov 2017 14:17:15 +1100 Subject: [PATCH 42/80] - Removed .mbedignore due to an issue with the eclipse exporter not picking up the ignored files; - Added #includes in BSP data C files so they can be built on their own without mbedignore; --- .../TARGET_ADUCM4050/.mbedignore | 28 ------------------- .../TARGET_ADUCM4050/bsp/adc/adi_adc_data.c | 1 + .../bsp/flash/adi_flash_data.c | 2 +- .../TARGET_ADUCM4050/bsp/i2c/adi_i2c_data.c | 2 +- .../TARGET_ADUCM4050/bsp/rtc/adi_rtc_data.c | 14 ++++++---- .../TARGET_ADUCM4050/bsp/rtc/adi_rtc_def.h | 26 +++++++++-------- .../TARGET_ADUCM4050/bsp/spi/adi_spi_data.c | 9 +++--- .../TARGET_ADUCM4050/bsp/tmr/adi_tmr_data.c | 23 ++++++++------- 8 files changed, 41 insertions(+), 64 deletions(-) delete mode 100755 targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/.mbedignore diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/.mbedignore b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/.mbedignore deleted file mode 100755 index 94a9f73e3f..0000000000 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/.mbedignore +++ /dev/null @@ -1,28 +0,0 @@ -bsp/adc/adi_adc_data.c -bsp/adc/adi_adc_data_v1.c -bsp/adc/adi_adc_v1.c -bsp/beep/adi_beep_v1.c -bsp/crc/adi_crc_data.c -bsp/crc/adi_crc_v1.c -bsp/crypto/adi_crypto_v1.c -bsp/dma/adi_dma_pl230_v2.c -bsp/flash/adi_flash_data.c -bsp/flash/adi_flash_v1.c -bsp/gpio/adi_gpio_v1.c -bsp/i2c/adi_i2c_data.c -bsp/i2c/adi_i2c_v1.c -bsp/pwr/adi_pwr_v1.c -bsp/rtc/adi_rtc_data.c -bsp/rtc/adi_rtc_data_v1.c -bsp/rtc/adi_rtc_v1.c -bsp/sport/adi_sport_data_v1.c -bsp/sport/adi_sport_v1.c -bsp/uart/adi_uart_data_v1.c -bsp/uart/adi_uart_v1.c -bsp/spi/adi_spi_data.c -bsp/spi/adi_spi_data_v1.c -bsp/spi/adi_spi_v1.c -bsp/tmr/adi_tmr_data.c -bsp/tmr/adi_tmr_data_v1.c -bsp/tmr/adi_tmr_v1.c -bsp/wdt/adi_wdt_v1.c diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_data.c index 9ebc296297..169378ea0f 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_data.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_data.c @@ -3,6 +3,7 @@ #include #include +#include #include "adi_adc_def.h" /*! \cond PRIVATE */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_data.c index 88fe50cf05..d5b6027573 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_data.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_data.c @@ -50,10 +50,10 @@ POSSIBILITY OF SUCH DAMAGE. /*! \cond PRIVATE */ +#include #include "adi_flash_def.h" #include "adi_flash_config.h" - /* Stores the information about the specific device */ static ADI_FEE_DEVICE_INFO fee_device_info [ADI_FEE_NUM_INSTANCES] = { diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_data.c index c48264eb24..6d7a63801c 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_data.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_data.c @@ -49,10 +49,10 @@ POSSIBILITY OF SUCH DAMAGE. /*! \cond PRIVATE */ +#include #include "adi_i2c_def.h" #include "adi_i2c_config.h" - /* Stores the information about the specific device */ static ADI_I2C_DEVICE_INFO i2c_device_info [ADI_I2C_NUM_INSTANCES] = { diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_data.c index 1cd5f0c773..624b8d3030 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_data.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_data.c @@ -50,8 +50,10 @@ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define ADI_RTC_DATA_C_ #include +#include #include "adi_rtc_def.h" + static ADI_RTC_DEVICE_INFO aRTCDeviceInfo[ADI_RTC_NUM_INSTANCE] = { { @@ -100,7 +102,7 @@ static ADI_RTC_CONFIG aRTCConfig[ADI_RTC_NUM_INSTANCE] = 0, /* CR7SSS */ 0, /* GPMUX0 */ 0 /* GPMUX1 */ - + }, /* RTC-1 */ { @@ -137,7 +139,7 @@ static ADI_RTC_CONFIG aRTCConfig[ADI_RTC_NUM_INSTANCE] = RTC1_CFG_TRIM_INTERVAL << BITP_RTC_TRM_IVL | RTC1_CFG_TRIM_OPERATION << BITP_RTC_TRM_ADD | RTC1_CFG_TRIM_VALUE << BITP_RTC_TRM_VALUE, - + /* CR2IC */ RTC1_CFG_IC0_ENABLE << BITP_RTC_CR2IC_IC0EN | RTC1_CFG_IC2_ENABLE << BITP_RTC_CR2IC_IC2EN | @@ -152,7 +154,7 @@ static ADI_RTC_CONFIG aRTCConfig[ADI_RTC_NUM_INSTANCE] = RTC1_CFG_IC3_EDGE_POLARITY << BITP_RTC_CR2IC_IC3LH | RTC1_CFG_IC4_EDGE_POLARITY << BITP_RTC_CR2IC_IC4LH | RTC1_CFG_IC_OVER_WRITE_ENABLE << BITP_RTC_CR2IC_ICOWUSEN, - + /* CR3SS */ RTC1_CFG_SS1_ENABLE << BITP_RTC_CR3SS_SS1EN | RTC1_CFG_SS2_ENABLE << BITP_RTC_CR3SS_SS2EN | @@ -172,16 +174,16 @@ static ADI_RTC_CONFIG aRTCConfig[ADI_RTC_NUM_INSTANCE] = /* SSMSK */ RTC1_CFG_SS1_MASK_VALUE, - + /* SS1 */ RTC1_CFG_SS1_AUTO_RELOAD_VALUE, - + 0, /* CR5SSS */ /* TODO: Add the following to the static configuration macros */ 0, /* CR6SSS */ 0, /* CR7SSS */ 0x4688, /* GPMUX0 */ 0x01F5, /* GPMUX1 */ - + } }; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_def.h index 4b5afa44ef..a6fca0e37b 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_def.h +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_def.h @@ -1,7 +1,7 @@ /*! ***************************************************************************** * @file: adi_rtc_def.h - * @brief: RTC def file + * @brief: RTC def file * @version: $Revision: 33205 $ * @date: $Date: 2016-01-11 05:46:07 -0500 (Mon, 11 Jan 2016) $ *----------------------------------------------------------------------------- @@ -46,10 +46,12 @@ *****************************************************************************/ #ifndef ADI_RTC_DEF_H__ -#define ADI_RTC_DEF_H__ +#define ADI_RTC_DEF_H__ + +#include /*! \cond PRIVATE */ -#define ADI_RTC_NUM_INSTANCE 2u +#define ADI_RTC_NUM_INSTANCE 2u @@ -100,23 +102,23 @@ #else /* pause on pending writes to CR to avoid data loss */ #define PEND_BEFORE_WRITE(reg,mask) -#define SYNC_AFTER_WRITE(reg,mask) +#define SYNC_AFTER_WRITE(reg,mask) #endif -/* +/* * The following is used for static configuration */ typedef struct { - uint16_t CR0; /*!< CR0 16 bit control register-0 value */ + uint16_t CR0; /*!< CR0 16 bit control register-0 value */ uint16_t CR1; /*!< CR1 16 bit control register-1 value */ uint16_t CNT0; /*!< CNT0 16 bit count register value */ uint16_t CNT1; /*!< CNT1 16 bit count register value */ - + uint16_t ALM0; /*!< ALM0 16 bit integer part of alarm value */ uint16_t ALM1; /*!< ALM1 16 bit integer part of alarm value */ uint16_t ALM2; /*!< ALM2 16 bit integer part of alarm value */ - uint16_t TRIM; /*!< 16 bit trim register value */ + uint16_t TRIM; /*!< 16 bit trim register value */ uint16_t CR2IC; /*!< CR2IC 16 bit control (which controls the input capture ) register-2 value */ uint16_t CR3SS; /*!< CR3SS 16 bit control ( Controls enabling sensor strobe /IRQ etc )register-3 value */ uint16_t CR4SS; /*!< CR4SS 16 bit control ( controls Auto reload and mask for sensor strobe ) register-4 value */ @@ -134,7 +136,7 @@ typedef struct typedef struct _ADI_RTC_DEVICE_INFO { volatile ADI_RTC_TypeDef *pRTCRegs; /* Base address of the SPORT registers */ - const IRQn_Type eIRQn; /* IRQn */ + const IRQn_Type eIRQn; /* IRQn */ ADI_RTC_HANDLE hDevice; /* RTC handle */ }ADI_RTC_DEVICE_INFO; @@ -146,10 +148,10 @@ typedef struct _ADI_RTC_DEVICE ADI_CALLBACK pfCallback; /* Function pointer for callback function. */ void *pCBParam; /* Parameter to callback function. */ - IRQn_Type eIRQn; /* IRQn */ + IRQn_Type eIRQn; /* IRQn */ uint32_t cbWatch; ADI_RTC_DEVICE_INFO *pDeviceInfo; /* Parameter to callback function. */ - + } ADI_RTC_DEVICE; @@ -158,6 +160,6 @@ static void rtc_init(ADI_RTC_DEVICE *pDevice,ADI_RTC_CONFIG *pConfig); #ifdef ADI_DEBUG static ADI_RTC_RESULT ValidateHandle( ADI_RTC_DEVICE *pInDevice); #endif -/*! \endcond */ +/*! \endcond */ #endif /* ADI_RTC_DEF_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_data.c index 9d8f001a37..ecbcb00b62 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_data.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_data.c @@ -1,7 +1,7 @@ /* ***************************************************************************** * @file: adi_spi_data.c - * @brief: Data declaration for SPORT Device Driver + * @brief: Data declaration for SPORT Device Driver ***************************************************************************** Copyright (c) 2016 Analog Devices, Inc. @@ -49,6 +49,7 @@ POSSIBILITY OF SUCH DAMAGE. /*! \cond PRIVATE */ +#include #include "adi_spi_def.h" #include "adi_spi_config.h" #include @@ -109,7 +110,7 @@ static const ADI_SPI_CFG_TYPE gSPICfg[ADI_SPI_NUM_INSTANCES] = /**** SPI_DIV buad rate selection register *** */ (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI0_CFG_BIT_RATE)) >>1u)-1u))\ - << BITP_SPI_DIV_VALUE ) + << BITP_SPI_DIV_VALUE ) }, /* Initialize SPI1 Instance configuration. */ { @@ -131,7 +132,7 @@ static const ADI_SPI_CFG_TYPE gSPICfg[ADI_SPI_NUM_INSTANCES] = /**** SPI_DIV buad rate selection register *** */ (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI1_CFG_BIT_RATE)) >>1u)-1u))\ - << BITP_SPI_DIV_VALUE ) + << BITP_SPI_DIV_VALUE ) }, /* Initialize SPI2 Instance configuration. */ { @@ -153,7 +154,7 @@ static const ADI_SPI_CFG_TYPE gSPICfg[ADI_SPI_NUM_INSTANCES] = /**** SPI_DIV buad rate selection register *** */ (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI2_CFG_BIT_RATE)) >>1u)-1u))\ - << BITP_SPI_DIV_VALUE ) + << BITP_SPI_DIV_VALUE ) } }; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr_data.c index 7cf4a8295e..31b2dbe8fc 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr_data.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr_data.c @@ -46,18 +46,17 @@ POSSIBILITY OF SUCH DAMAGE. #ifndef ADI_TMR_DATA #define ADI_TMR_DATA - +#include #include #include #include - /* CTL register static configuration */ -static uint16_t aTimerCtlConfig[] = +static uint16_t aTimerCtlConfig[] = { (TMR0_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) | (TMR0_CFG_MODE << BITP_TMR_RGB_CTL_MODE) | - (TMR0_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | + (TMR0_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | (TMR0_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) | (TMR0_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) | (TMR0_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) | @@ -66,7 +65,7 @@ static uint16_t aTimerCtlConfig[] = (TMR1_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) | (TMR1_CFG_MODE << BITP_TMR_RGB_CTL_MODE) | - (TMR1_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | + (TMR1_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | (TMR1_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) | (TMR1_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) | (TMR1_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) | @@ -75,7 +74,7 @@ static uint16_t aTimerCtlConfig[] = (TMR2_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) | (TMR2_CFG_MODE << BITP_TMR_RGB_CTL_MODE) | - (TMR2_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | + (TMR2_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | (TMR2_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) | (TMR2_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) | (TMR2_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) | @@ -84,16 +83,16 @@ static uint16_t aTimerCtlConfig[] = (TMR3_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) | (TMR3_CFG_MODE << BITP_TMR_RGB_CTL_MODE) | - (TMR3_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | + (TMR3_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | (TMR3_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) | (TMR3_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) | (TMR3_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) | (TMR3_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) | - (TMR3_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN), + (TMR3_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN), }; /* LOAD register static configuration */ -static uint16_t aTimerLoadConfig[] = +static uint16_t aTimerLoadConfig[] = { TMR0_CFG_LOAD_VALUE, TMR1_CFG_LOAD_VALUE, @@ -102,7 +101,7 @@ static uint16_t aTimerLoadConfig[] = }; /* Asynchronous LOAD static configuraton */ -static uint16_t aTimerALoadConfig[] = +static uint16_t aTimerALoadConfig[] = { TMR0_CFG_ASYNC_LOAD_VALUE, TMR1_CFG_ASYNC_LOAD_VALUE, @@ -135,10 +134,10 @@ static uint16_t aTimerPwmCtlConfig[] = (TMR3_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH), (TMR3_CFG_PWM1_IDLE_STATE << BITP_TMR_RGB_PWM1CTL_IDLESTATE) | - (TMR3_CFG_PWM1_MATCH_VALUE << BITP_TMR_RGB_PWM1CTL_MATCH), + (TMR3_CFG_PWM1_MATCH_VALUE << BITP_TMR_RGB_PWM1CTL_MATCH), (TMR3_CFG_PWM2_IDLE_STATE << BITP_TMR_RGB_PWM2CTL_IDLESTATE) | - (TMR3_CFG_PWM2_MATCH_VALUE << BITP_TMR_RGB_PWM2CTL_MATCH), + (TMR3_CFG_PWM2_MATCH_VALUE << BITP_TMR_RGB_PWM2CTL_MATCH), }; /* PWM MATCH static configuration */ From de51bcaac8ba703ec6de747f08dfa6042eb16633 Mon Sep 17 00:00:00 2001 From: johnny Date: Sun, 1 Oct 2017 17:29:01 -0400 Subject: [PATCH 43/80] Add support for RedBear's BLE Nano 2 Cribbed from https://github.com/redbear/mbed-os/commit/4bf42f2e205e81ffb50a013b16c0366607bf8146 I'm not sure if if there are any copyright issues here with what is effectively a set of config files. A few folks have been bugging me (and the redbear folks) for these changes, so I wanted them somewhere centralized. --- .../TARGET_RBLAB_BLENANO2/PinNames.h | 194 ++++++++++++++++++ .../TARGET_RBLAB_BLENANO2/device.h | 23 +++ targets/targets.json | 9 + 3 files changed, 226 insertions(+) create mode 100644 targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/PinNames.h create mode 100644 targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/device.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/PinNames.h new file mode 100644 index 0000000000..0798e678c1 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/PinNames.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2016 Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA + * integrated circuit in a product or a software update for such product, must reproduce + * the above copyright notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be + * used to endorse or promote products derived from this software without specific prior + * written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary or object form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 3 + +typedef enum { + p0 = 0, + p1 = 1, + p2 = 2, + p3 = 3, + p4 = 4, + p5 = 5, + p6 = 6, + p7 = 7, + p8 = 8, + p9 = 9, + p10 = 10, + p11 = 11, + p12 = 12, + p13 = 13, + p14 = 14, + p15 = 15, + p16 = 16, + p17 = 17, + p18 = 18, + p19 = 19, + p20 = 20, + p21 = 21, + p22 = 22, + p23 = 23, + p24 = 24, + p25 = 25, + p26 = 26, + p27 = 27, + p28 = 28, + p29 = 29, + p30 = 30, + p31 = 31, + + P0_0 = p0, + P0_1 = p1, + P0_2 = p2, + P0_3 = p3, + P0_4 = p4, + P0_5 = p5, + P0_6 = p6, + P0_7 = p7, + + P0_8 = p8, + P0_9 = p9, + P0_10 = p10, + P0_11 = p11, + P0_12 = p12, + P0_13 = p13, + P0_14 = p14, + P0_15 = p15, + + P0_16 = p16, + P0_17 = p17, + P0_18 = p18, + P0_19 = p19, + P0_20 = p20, + P0_21 = p21, + P0_22 = p22, + P0_23 = p23, + + P0_24 = p24, + P0_25 = p25, + P0_26 = p26, + P0_27 = p27, + P0_28 = p28, + P0_29 = p29, + P0_30 = p30, + + LED1 = p11, + LED2 = p11, + LED3 = p11, + LED4 = p11, + + RX_PIN_NUMBER = p30, + TX_PIN_NUMBER = p29, + CTS_PIN_NUMBER = p28, + RTS_PIN_NUMBER = p2, + + // mBed interface Pins + USBTX = TX_PIN_NUMBER, + USBRX = RX_PIN_NUMBER, + + SPI_PSELMOSI0 = p6, + SPI_PSELMISO0 = p7, + SPI_PSELSS0 = p3, + SPI_PSELSCK0 = p8, + + SPI_PSELMOSI1 = p29, + SPI_PSELMISO1 = p30, + SPI_PSELSS1 = p28, + SPI_PSELSCK1 = p2, + + SPIS_PSELMOSI = p29, + SPIS_PSELMISO = p30, + SPIS_PSELSS = p28, + SPIS_PSELSCK = p2, + + I2C_SDA0 = p28, + I2C_SCL0 = p2, + + D0 = p30, + D1 = p29, + D2 = p28, + D3 = p2, + + D4 = p3, + D5 = p6, + D6 = p7, + D7 = p8, + D8 = p21, + + D9 = p4, + D10 = p5, + + D13 = p11, + + A0 = p28, + A1 = p29, + A2 = p30, + A3 = p2, + A4 = p4, + A5 = p5, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 3, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/device.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/device.h new file mode 100644 index 0000000000..493844b801 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/device.h @@ -0,0 +1,23 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#include "objects.h" + +#endif diff --git a/targets/targets.json b/targets/targets.json index 9284911b83..0a8549f009 100755 --- a/targets/targets.json +++ b/targets/targets.json @@ -2083,6 +2083,15 @@ "extra_labels_add": ["RBLAB_BLENANO"], "macros_add": ["TARGET_RBLAB_BLENANO"] }, + "RBLAB_BLENANO2": { + "supported_form_factors": ["ARDUINO"], + "inherits": ["MCU_NRF52"], + "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"], + "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], + "release_versions": ["2", "5"], + "overrides": {"uart_hwfc": 0}, + "device_name": "nRF52832_xxAA" + }, "NRF51822_Y5_MBUG": { "inherits": ["MCU_NRF51_16K"] }, From 44fc3313d1f41c73bb14ad697fcc82846f42139c Mon Sep 17 00:00:00 2001 From: Tony Wu Date: Thu, 26 Oct 2017 06:33:30 +0800 Subject: [PATCH 44/80] rtl8195am - fix us_ticker interrupt handling TIMER2_7_IRQ is shared among several timer sources, including us_ticker. Raising TIMER2_7_IRQ pending bit will trigger the timer interrupt, but the timer interrupt handler will not know which timer source this interrupt is for. This patch sets timer load value to one tick and force us_ticker to fire almost "immediately". TIMER2_7_IRQ is handled through a common interrupt handler, and is automatically cleared. Therefore, there is no need to clear IRQ. The underlying timer HAL treats load value as micro-seconds and does conversion internally. Therefore, simply pass micro-seconds to timer HAL without converting to tick first. Signed-off-by: Tony Wu --- .../TARGET_Realtek/TARGET_AMEBA/us_ticker.c | 23 +++++++------------ 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c b/targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c index 3c0b22faf9..f51f2f4e1c 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c @@ -19,7 +19,6 @@ #include "us_ticker_api.h" #include "PeripheralNames.h" -#define TICK_READ_FROM_CPU 0 // 1: read tick from CPU, 0: read tick from G-Timer #define SYS_TIM_ID 1 // the G-Timer ID for System #define APP_TIM_ID 2 // the G-Timer ID for Application @@ -33,8 +32,6 @@ * * Define the following macros to convert between TICK and US. */ -#define MS_TO_TICK(x) (uint64_t)(((x)*327) / 10) -#define US_TO_TICK(x) (uint64_t)(((x)*32) / 1000) #define TICK_TO_US(x) (uint64_t)(((x)/2) * 61 + ((x)%2) * TIMER_TICK_US) static int us_ticker_inited = 0; @@ -73,8 +70,6 @@ void us_ticker_init(void) TimerAdapter.TimerMode = USER_DEFINED; HalTimerOp.HalTimerInit((void *) &TimerAdapter); - - DBG_TIMER_INFO("%s: Timer_Id=%d\n", __FUNCTION__, APP_TIM_ID); } uint32_t us_ticker_read(void) @@ -95,27 +90,26 @@ uint32_t us_ticker_read(void) void us_ticker_set_interrupt(timestamp_t timestamp) { uint32_t time_cur; - uint32_t time_cnt; - HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId); time_cur = us_ticker_read(); if (timestamp > time_cur + TIMER_TICK_US) { - time_cnt = timestamp - time_cur; + TimerAdapter.TimerLoadValueUs = timestamp - time_cur; } else { - HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, 0xffffffff); - HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId); - us_ticker_fire_interrupt(); - return; + TimerAdapter.TimerLoadValueUs = TIMER_TICK_US; } - TimerAdapter.TimerLoadValueUs = MAX(MS_TO_TICK(time_cnt/1000) + US_TO_TICK(time_cnt%1000), 1); + HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId); HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, TimerAdapter.TimerLoadValueUs); HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId); } void us_ticker_fire_interrupt(void) { - NVIC_SetPendingIRQ(TIMER2_7_IRQ); + TimerAdapter.TimerLoadValueUs = TIMER_TICK_US; + + HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId); + HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, TimerAdapter.TimerLoadValueUs); + HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId); } void us_ticker_disable_interrupt(void) @@ -125,5 +119,4 @@ void us_ticker_disable_interrupt(void) void us_ticker_clear_interrupt(void) { - HalTimerOp.HalTimerIrqClear((u32)TimerAdapter.TimerId); } From d56959acf5c03aafbffc96ab01ac612560943e2c Mon Sep 17 00:00:00 2001 From: Yuguo Zou Date: Tue, 7 Nov 2017 17:02:42 +0800 Subject: [PATCH 45/80] Update HAL code to resolve ticker lockup issue --- .../lib_peripheral_mbed_gcc.a | Bin 648326 -> 665930 bytes .../TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a | Bin 6151596 -> 6553208 bytes .../TARGET_RTL8195A/device/rtl8195a_timer.h | 5 +++++ .../sdk/soc/realtek/8195a/fwlib/hal_timer.h | 7 ++++--- .../TARGET_Realtek/TARGET_AMEBA/us_ticker.c | 7 +++---- 5 files changed, 12 insertions(+), 7 deletions(-) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a index 352cdf86f647bcbbea5d640e052051ad396c09d1..5760bf2a0735be10b96020f5e6058366fddfa6e0 100644 GIT binary patch delta 247509 zcmce933wGn)^_#X`YxU3UJ{afLx8XdVUabgGC;@z!Gy#l2r7CBNq|U5LKb9kxQdRu zj(ByVGpOje;y$>bqT{}cqN0NPJ}x8bjQjS#Z}quJ{J!shp8x;;|M~Jf>9@|Qs#B*< zojP6Jx4Y}KCr3Q>Lf-k={t4s9=Z~K-J%8(v^27?Ij{blDH~I}%|E>Q7EADjtkN&%6 zU7%9`iBzH+H{7gT|8xI||H;OF)0X?9zbW@c2_EGC{x;?QZ~lAwA5i*#YEXIpZ~hbi zH--OS%f3EKdH%zH;y*I}yR>)lQ|iC*pHSZWX8q^?e;ud1|0Dm2|GFXHC7YH0zvnUK z>;3Ag zbeo&Od&;!w)21XVkIwW?$e%EEO7hnsBU~AScjgW4bS2IWDCJT7^BBjQN*ULJx=u5C z4lctt$WY2X11#5osXQ9~YrFuL_f>#A5i5XWer5>CzLe-Ri9MW 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