mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #11682 from mprse/fpga_tests_CI_targets
Make FPGA tests to pass on CI targets (SPI, analogIn, PWM)pull/11836/head
Martin Kojtal
GitHub
commit
33e392e9d9
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@ -190,26 +190,26 @@ Case cases[] = {
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Case("PWM - period: 10 ms, fill: 90%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 90, PERIOD_PULSEWIDTH_MS> >),
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Case("PWM - period: 10 ms, fill: 90%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<10, 90, PERIOD_PULSEWIDTH_US> >),
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Case("PWM - period: 50 ms, fill: 10%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 10, PERIOD_WRITE> >),
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Case("PWM - period: 50 ms, fill: 10%, api: period_ms/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 10, PERIOD_MS_WRITE> >),
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Case("PWM - period: 50 ms, fill: 10%, api: period_us/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 10, PERIOD_US_WRITE> >),
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Case("PWM - period: 50 ms, fill: 10%, api: period/pulse_width", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 10, PERIOD_PULSEWIDTH> >),
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Case("PWM - period: 50 ms, fill: 10%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 10, PERIOD_PULSEWIDTH_MS> >),
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Case("PWM - period: 50 ms, fill: 10%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 10, PERIOD_PULSEWIDTH_US> >),
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Case("PWM - period: 30 ms, fill: 10%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<30, 10, PERIOD_WRITE> >),
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Case("PWM - period: 30 ms, fill: 10%, api: period_ms/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<30, 10, PERIOD_MS_WRITE> >),
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Case("PWM - period: 30 ms, fill: 10%, api: period_us/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<30, 10, PERIOD_US_WRITE> >),
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Case("PWM - period: 30 ms, fill: 10%, api: period/pulse_width", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<30, 10, PERIOD_PULSEWIDTH> >),
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Case("PWM - period: 30 ms, fill: 10%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<30, 10, PERIOD_PULSEWIDTH_MS> >),
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Case("PWM - period: 30 ms, fill: 10%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<30, 10, PERIOD_PULSEWIDTH_US> >),
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Case("PWM - period: 50 ms, fill: 50%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 50, PERIOD_WRITE> >),
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Case("PWM - period: 50 ms, fill: 50%, api: period_ms/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 50, PERIOD_MS_WRITE> >),
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Case("PWM - period: 50 ms, fill: 50%, api: period_us/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 50, PERIOD_US_WRITE> >),
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Case("PWM - period: 50 ms, fill: 50%, api: period/pulse_width", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 50, PERIOD_PULSEWIDTH> >),
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Case("PWM - period: 50 ms, fill: 50%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 50, PERIOD_PULSEWIDTH_MS> >),
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Case("PWM - period: 50 ms, fill: 50%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 50, PERIOD_PULSEWIDTH_US> >),
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Case("PWM - period: 30 ms, fill: 50%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<30, 50, PERIOD_WRITE> >),
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Case("PWM - period: 30 ms, fill: 50%, api: period_ms/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<30, 50, PERIOD_MS_WRITE> >),
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Case("PWM - period: 30 ms, fill: 50%, api: period_us/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<30, 50, PERIOD_US_WRITE> >),
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Case("PWM - period: 30 ms, fill: 50%, api: period/pulse_width", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<30, 50, PERIOD_PULSEWIDTH> >),
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Case("PWM - period: 30 ms, fill: 50%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<30, 50, PERIOD_PULSEWIDTH_MS> >),
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Case("PWM - period: 30 ms, fill: 50%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<30, 50, PERIOD_PULSEWIDTH_US> >),
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Case("PWM - period: 50 ms, fill: 90%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 90, PERIOD_WRITE> >),
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Case("PWM - period: 50 ms, fill: 90%, api: period_ms/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 90, PERIOD_MS_WRITE> >),
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Case("PWM - period: 50 ms, fill: 90%, api: period_us/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 90, PERIOD_US_WRITE> >),
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Case("PWM - period: 50 ms, fill: 90%, api: period/pulse_width", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 90, PERIOD_PULSEWIDTH> >),
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Case("PWM - period: 50 ms, fill: 90%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 90, PERIOD_PULSEWIDTH_MS> >),
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Case("PWM - period: 50 ms, fill: 90%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<50, 90, PERIOD_PULSEWIDTH_US> >)
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Case("PWM - period: 30 ms, fill: 90%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<30, 90, PERIOD_WRITE> >),
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Case("PWM - period: 30 ms, fill: 90%, api: period_ms/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<30, 90, PERIOD_MS_WRITE> >),
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Case("PWM - period: 30 ms, fill: 90%, api: period_us/write", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<30, 90, PERIOD_US_WRITE> >),
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Case("PWM - period: 30 ms, fill: 90%, api: period/pulse_width", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<30, 90, PERIOD_PULSEWIDTH> >),
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Case("PWM - period: 30 ms, fill: 90%, api: period/pulse_width_ms", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<30, 90, PERIOD_PULSEWIDTH_MS> >),
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Case("PWM - period: 30 ms, fill: 90%, api: period/pulse_width_us", one_peripheral<PWMPort, DefaultFormFactor, fpga_pwm_period_fill_test<30, 90, PERIOD_PULSEWIDTH_US> >)
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};
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utest::v1::status_t greentea_test_setup(const size_t number_of_cases)
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@ -44,6 +44,10 @@ typedef enum {
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#define FREQ_500_KHZ 500000
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#define FREQ_1_MHZ 1000000
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#define FREQ_2_MHZ 2000000
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#define FREQ_MIN ((uint32_t)0)
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#define FREQ_MAX ((uint32_t)-1)
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#define TEST_CAPABILITY_BIT(MASK, CAP) ((1 << CAP) & (MASK))
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const int TRANSFER_COUNT = 300;
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SPIMasterTester tester(DefaultFormFactor::pins(), DefaultFormFactor::restricted_pins());
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@ -62,6 +66,36 @@ void spi_async_handler()
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}
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#endif
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/* Auxiliary function to check platform capabilities against test case. */
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static bool check_capabilities(const spi_capabilities_t *capabilities, SPITester::SpiMode spi_mode, uint32_t sym_size, transfer_type_t transfer_type, uint32_t frequency)
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{
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// Symbol size
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if (!TEST_CAPABILITY_BIT(capabilities->word_length, (sym_size - 1))) {
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utest_printf("\n<Specified symbol size is not supported on this platform> skipped ");
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return false;
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}
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// SPI clock mode
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if (!TEST_CAPABILITY_BIT(capabilities->clk_modes, spi_mode)) {
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utest_printf("\n<Specified spi clock mode is not supported on this platform> skipped");
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return false;
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}
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// Frequency
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if (frequency != FREQ_MAX && frequency != FREQ_MIN && frequency < capabilities->minimum_frequency && frequency > capabilities->maximum_frequency) {
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utest_printf("\n<Specified frequency is not supported on this platform> skipped ");
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return false;
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}
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// Async mode
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if (transfer_type == TRANSFER_SPI_MASTER_TRANSFER_ASYNC && capabilities->async_mode == false) {
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utest_printf("\n<Async mode is not supported on this platform> skipped ");
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return false;
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}
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return true;
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}
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void fpga_spi_test_init_free(PinName mosi, PinName miso, PinName sclk, PinName ssel)
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{
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spi_init(&spi, mosi, miso, sclk, ssel);
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@ -72,6 +106,15 @@ void fpga_spi_test_init_free(PinName mosi, PinName miso, PinName sclk, PinName s
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void fpga_spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel, SPITester::SpiMode spi_mode, uint32_t sym_size, transfer_type_t transfer_type, uint32_t frequency)
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{
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spi_capabilities_t capabilities;
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spi_get_capabilities(ssel, false, &capabilities);
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if (check_capabilities(&capabilities, spi_mode, sym_size, transfer_type, frequency) == false) {
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return;
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}
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uint32_t sym_mask = ((1 << sym_size) - 1);
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// Remap pins for test
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@ -178,14 +221,10 @@ Case cases[] = {
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Case("SPI - mode testing (MODE_1)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode1, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
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Case("SPI - mode testing (MODE_2)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode2, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
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Case("SPI - mode testing (MODE_3)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode3, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
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Case("SPI - symbol size testing (16)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 16, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
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Case("SPI - frequency testing (500 kHz)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_500_KHZ> >),
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Case("SPI - frequency testing (2 MHz)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_2_MHZ> >),
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Case("SPI - block write", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_BLOCK_WRITE_SYNC, FREQ_1_MHZ> >),
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#if DEVICE_SPI_ASYNCH
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Case("SPI - async mode", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_TRANSFER_ASYNC, FREQ_1_MHZ> >)
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#endif
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@ -17,6 +17,7 @@
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#include "analogin_api.h"
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#include "i2c_api.h"
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#include "spi_api.h"
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#include "gpio_api.h"
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#include "mbed_toolchain.h"
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@ -41,3 +42,52 @@ MBED_WEAK void analogin_free(analogin_t *obj)
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// Do nothing
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}
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#endif
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#if DEVICE_SPI
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// Default SPI capabilities. If specific target has different capabilities this function needs to be re-implemented.
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MBED_WEAK void spi_get_capabilities(PinName ssel, bool slave, spi_capabilities_t *cap)
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{
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if (slave) {
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cap->minimum_frequency = 200000; // 200 kHz
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cap->maximum_frequency = 2000000; // 2 MHz
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cap->word_length = 0x00008080; // 8 and 16 bit symbols
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cap->support_slave_mode = false; // to be determined later based on ssel
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cap->hw_cs_handle = false; // irrelevant in slave mode
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cap->slave_delay_between_symbols_ns = 2500; // 2.5 us
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cap->clk_modes = 0x0f; // all clock modes
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#if DEVICE_SPI_ASYNCH
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cap->async_mode = true;
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#else
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cap->async_mode = false;
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#endif
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} else {
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cap->minimum_frequency = 200000; // 200 kHz
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cap->maximum_frequency = 2000000; // 2 MHz
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cap->word_length = 0x00008080; // 8 and 16 bit symbols
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cap->support_slave_mode = false; // to be determined later based on ssel
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cap->hw_cs_handle = false; // to be determined later based on ssel
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cap->slave_delay_between_symbols_ns = 0; // irrelevant in master mode
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cap->clk_modes = 0x0f; // all clock modes
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#if DEVICE_SPI_ASYNCH
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cap->async_mode = true;
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#else
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cap->async_mode = false;
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#endif
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}
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// check if given ssel pin is in the cs pinmap
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const PinMap *cs_pins = spi_master_cs_pinmap();
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PinName pin = NC;
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while (cs_pins->pin != NC) {
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if (cs_pins->pin == ssel) {
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#if DEVICE_SPISLAVE
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cap->support_slave_mode = true;
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#endif
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cap->hw_cs_handle = true;
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break;
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}
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cs_pins++;
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}
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}
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#endif
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@ -53,6 +53,28 @@ typedef struct spi_s spi_t;
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#endif
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/**
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* Describes the capabilities of a SPI peripherals
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*/
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typedef struct {
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/** Minimum frequency supported must be set by target device and it will be assessed during
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* testing.
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*/
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uint32_t minimum_frequency;
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/** Maximum frequency supported must be set by target device and it will be assessed during
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* testing.
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*/
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uint32_t maximum_frequency;
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/** Each bit represents the corresponding word length. lsb => 1bit, msb => 32bit. */
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uint32_t word_length;
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uint16_t slave_delay_between_symbols_ns; /**< specifies required number of ns between transmission of successive symbols in slave mode. */
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uint8_t clk_modes; /**< specifies supported modes from spi_mode_t. Each bit represents the corresponding mode. */
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bool support_slave_mode; /**< If true, the device can handle SPI slave mode using hardware management on the specified ssel pin. */
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bool hw_cs_handle; /**< If true, in SPI master mode Chip Select can be handled by hardware. */
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bool async_mode; /**< If true, in async mode is supported. */
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} spi_capabilities_t;
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#ifdef __cplusplus
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extern "C" {
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#endif
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@ -63,6 +85,11 @@ extern "C" {
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* # Defined behavior
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* * ::spi_init initializes the spi_t control structure
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* * ::spi_init configures the pins used by SPI
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* * ::spi_get_capabilities() fills the given `spi_capabilities_t` instance
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* * ::spi_get_capabilities() should consider the `ssel` pin when evaluation the `support_slave_mode` and `hw_cs_handle` capability
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* * ::spi_get_capabilities(): if the given `ssel` pin cannot be managed by hardware, `support_slave_mode` and `hw_cs_handle` should be false
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* * At least a symbol width of 8bit must be supported
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* * The supported frequency range must include the range [0.2..2] MHz
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* * ::spi_free returns the pins owned by the SPI object to their reset state
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* * ::spi_format sets the number of bits per frame
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* * ::spi_format configures clock polarity and phase
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@ -125,6 +152,11 @@ extern "C" {
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SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName mclk);
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#endif
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/**
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* Fills the given spi_capabilities_t structure with the capabilities of the given peripheral.
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*/
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void spi_get_capabilities(PinName ssel, bool slave, spi_capabilities_t *cap);
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/** Initialize the SPI peripheral
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*
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* Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
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@ -297,7 +297,7 @@ void pwmout_pulsewidth(pwmout_t *obj, float pulse)
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DEBUG_PRINTF("pwmout_pulsewidt: %f\r\n", pulse);
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/* Cap pulsewidth to period before setting it. */
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if ((pulse * 1000000) > (float) (obj->pulse & ~SEQ_POLARITY_BIT)) {
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if ((pulse * 1000000) > (float) obj->period) {
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obj->pulse &= SEQ_POLARITY_BIT;
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obj->pulse |= obj->period;
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pwmout_pulsewidth_us(obj, obj->pulse);
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@ -354,4 +354,3 @@ const PinMap *pwmout_pinmap()
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}
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#endif // DEVICE_PWMOUT
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@ -128,6 +128,51 @@ static void spi_configure_driver_instance(spi_t *obj)
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}
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}
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void spi_get_capabilities(PinName ssel, bool slave, spi_capabilities_t *cap)
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{
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if (slave) {
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cap->minimum_frequency = 200000; // 200 kHz
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cap->maximum_frequency = 2000000; // 2 MHz
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cap->word_length = 0x00000080; // 8 bit symbols
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cap->support_slave_mode = false; // to be determined later based on ssel
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cap->hw_cs_handle = false; // irrelevant in slave mode
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cap->slave_delay_between_symbols_ns = 2500; // 2.5 us
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cap->clk_modes = 0x0f; // all clock modes
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#if DEVICE_SPI_ASYNCH
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cap->async_mode = true;
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#else
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cap->async_mode = false;
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#endif
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} else {
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cap->minimum_frequency = 200000; // 200 kHz
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cap->maximum_frequency = 2000000; // 2 MHz
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cap->word_length = 0x00000080; // 8 bit symbols
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cap->support_slave_mode = false; // to be determined later based on ssel
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cap->hw_cs_handle = false; // to be determined later based on ssel
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cap->slave_delay_between_symbols_ns = 0; // irrelevant in master mode
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cap->clk_modes = 0x0f; // all clock modes
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#if DEVICE_SPI_ASYNCH
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cap->async_mode = true;
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#else
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cap->async_mode = false;
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#endif
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}
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// check if given ssel pin is in the cs pinmap
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const PinMap *cs_pins = spi_master_cs_pinmap();
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PinName pin = NC;
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while (cs_pins->pin != NC) {
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if (cs_pins->pin == ssel) {
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#if DEVICE_SPISLAVE
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cap->support_slave_mode = true;
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#endif
|
||||
cap->hw_cs_handle = true;
|
||||
break;
|
||||
}
|
||||
cs_pins++;
|
||||
}
|
||||
}
|
||||
|
||||
/** Initialize the SPI peripheral
|
||||
*
|
||||
* Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
|
||||
|
|
@ -247,13 +292,13 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
|
|||
nrf_spi_mode_t new_mode = NRF_SPI_MODE_0;
|
||||
|
||||
/* Convert Mbed HAL mode to Nordic mode. */
|
||||
if(mode == 0) {
|
||||
if (mode == 0) {
|
||||
new_mode = NRF_SPI_MODE_0;
|
||||
} else if(mode == 1) {
|
||||
} else if (mode == 1) {
|
||||
new_mode = NRF_SPI_MODE_1;
|
||||
} else if(mode == 2) {
|
||||
} else if (mode == 2) {
|
||||
new_mode = NRF_SPI_MODE_2;
|
||||
} else if(mode == 3) {
|
||||
} else if (mode == 3) {
|
||||
new_mode = NRF_SPI_MODE_3;
|
||||
}
|
||||
|
||||
|
|
@ -351,8 +396,9 @@ int spi_master_write(spi_t *obj, int value)
|
|||
desc.rx_length = 1;
|
||||
ret = nrfx_spi_xfer(&nordic_nrf5_spi_instance[instance], &desc, 0);
|
||||
|
||||
if (ret != NRFX_SUCCESS)
|
||||
if (ret != NRFX_SUCCESS) {
|
||||
DEBUG_PRINTF("%d error returned from nrf_spi_xfer\n\r");
|
||||
}
|
||||
|
||||
/* Manually set chip select pin if defined. */
|
||||
if (spi_inst->cs != NC) {
|
||||
|
|
@ -421,7 +467,7 @@ int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, cha
|
|||
int tx_actual_length = (tx_length > 255) ? 255 : tx_length;
|
||||
|
||||
/* Set tx buffer pointer. Set to NULL if no data is going to be transmitted. */
|
||||
const uint8_t * tx_actual_buffer = (tx_actual_length > 0) ?
|
||||
const uint8_t *tx_actual_buffer = (tx_actual_length > 0) ?
|
||||
(const uint8_t *)(tx_buffer + tx_offset) :
|
||||
NULL;
|
||||
|
||||
|
|
@ -429,7 +475,7 @@ int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, cha
|
|||
int rx_actual_length = (rx_length > 255) ? 255 : rx_length;
|
||||
|
||||
/* Set rx buffer pointer. Set to NULL if no data is going to be received. */
|
||||
uint8_t * rx_actual_buffer = (rx_actual_length > 0) ?
|
||||
uint8_t *rx_actual_buffer = (rx_actual_length > 0) ?
|
||||
(uint8_t *)(rx_buffer + rx_offset) :
|
||||
NULL;
|
||||
|
||||
|
|
@ -721,7 +767,7 @@ void spi_master_transfer(spi_t *obj,
|
|||
struct buffer_s *buffer_pointer;
|
||||
|
||||
buffer_pointer = &obj->tx_buff;
|
||||
buffer_pointer->buffer = (void*) tx;
|
||||
buffer_pointer->buffer = (void *) tx;
|
||||
buffer_pointer->length = tx_length;
|
||||
buffer_pointer->pos = 0;
|
||||
buffer_pointer->width = 8;
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ MBED_WEAK const PinMap PinMap_ADC[] = {
|
|||
// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to STDIO_UART_TX
|
||||
// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // Connected to STDIO_UART_RX
|
||||
{PA_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1
|
||||
{PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 // Connected to LD2 [Green Led]
|
||||
// {PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 // Connected to LD2 [Green Led]
|
||||
{PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3
|
||||
{PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4
|
||||
{PB_0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ MBED_WEAK const PinMap PinMap_ADC[] = {
|
|||
// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to STDIO_UART_TX
|
||||
// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to STDIO_UART_RX
|
||||
{PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
|
||||
{PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to LD2 [Green Led]
|
||||
// {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to LD2 [Green Led]
|
||||
{PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
|
||||
{PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
|
||||
{PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ MBED_WEAK const PinMap PinMap_ADC[] = {
|
|||
// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 // Connected to STDIO_UART_TX
|
||||
// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3 // Connected to STDIO_UART_RX
|
||||
{PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4
|
||||
{PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5 // Connected to LD2 [Green Led]
|
||||
// {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5 // Connected to LD2 [Green Led]
|
||||
{PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC_IN6
|
||||
{PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC_IN7
|
||||
{PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8
|
||||
|
|
|
|||
Loading…
Reference in New Issue