STM32F407 : correct ARM scatter file

Alignment with STM32Cube_FW_F4_V1.18.0 done

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/STM32F407.sct

@@ -1,17 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08000000 0x00100000  {    ; load region size_region
-  ER_IROM1 0x08000000 0x00100000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  RW_IRAM1 0x10000000 0x00010000  {  ; CCM
-  }
-  RW_IRAM2 0x20000188 0x0001FE78 {
-   .ANY (+RW +ZI)
-  }
-}
-

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/STM32F407xx.sct

@@ -0,0 +1,18 @@
+; *****************************************
+; *** Scatter-Loading Description File  ***
+; *****************************************
+
+LR_IROM1 0x08000000 0x00100000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000188 0x0001FE78 {
+   .ANY (+RW +ZI)
+  }
+  RW_IRAM2 0x10000000 0x00010000  {  ; CCM
+   .ANY (CCMRAM)
+  }
+}
+

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/startup_STM32F407xx.S

@@ -1,23 +1,41 @@
-;/*****************************************************************************
+;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-; * @file:    startup_STM32F40x.s
+;* File Name          : startup_stm32f407xx.s
-; * @purpose: CMSIS Cortex-M4 Core Device Startup File
+;* Author             : MCD Application Team
-; *           for the ST STM32F40x Device Series
+;* Description        : STM32F407xx devices vector table for MDK-ARM_MICRO toolchain. 
-; * @version: V1.20
+;*                      This module performs:
-; * @date:    16. January 2012
+;*                      - Set the initial SP
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*                      - Set the initial PC == Reset_Handler
-; *
+;*                      - Set the vector table entries with the exceptions ISR address
-; * Copyright (C) 2012 ARM Limited. All rights reserved.
+;*                      - Branches to __main in the C library (which eventually
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M4
+;*                        calls main()).
-; * processor based microcontrollers.  This file can be freely distributed
+;*                      After Reset the CortexM4 processor is in Thread mode,
-; * within development tools that are supporting such ARM based processors.
+;*                      priority is Privileged, and the Stack is set to Main.
-; *
+;* <<< Use Configuration Wizard in Context Menu >>>   
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+;*******************************************************************************
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; 
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+;* Redistribution and use in source and binary forms, with or without modification,
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+;* are permitted provided that the following conditions are met:
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+;*   1. Redistributions of source code must retain the above copyright notice,
-; *
+;*      this list of conditions and the following disclaimer.
-; *****************************************************************************/
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*******************************************************************************
 
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
@@ -56,6 +74,8 @@ __heap_limit    EQU (__initial_sp - Stack_Size)
 
                 AREA    RESET, DATA, READONLY
                 EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
 
 __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     Reset_Handler             ; Reset Handler
@@ -122,7 +142,7 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 
                 DCD     TIM8_CC_IRQHandler            ; TIM8 Capture Compare 
                 DCD     DMA1_Stream7_IRQHandler       ; DMA1 Stream7 
-                DCD     FSMC_IRQHandler               ; FSMC 
+                DCD     FMC_IRQHandler                ; FMC 
                 DCD     SDIO_IRQHandler               ; SDIO 
                 DCD     TIM5_IRQHandler               ; TIM5 
                 DCD     SPI3_IRQHandler               ; SPI3 
@@ -153,10 +173,12 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     OTG_HS_WKUP_IRQHandler        ; USB OTG HS Wakeup through EXTI 
                 DCD     OTG_HS_IRQHandler             ; USB OTG HS 
                 DCD     DCMI_IRQHandler               ; DCMI 
-                DCD     CRYP_IRQHandler               ; CRYP crypto 
+                DCD     0                             ; Reserved 
                 DCD     HASH_RNG_IRQHandler           ; Hash and Rng 
                 DCD     FPU_IRQHandler                ; FPU 
+__Vectors_End
 
+__Vectors_Size  EQU  __Vectors_End - __Vectors
 
                 AREA    |.text|, CODE, READONLY
 
@@ -268,7 +290,7 @@ Default_Handler PROC
                 EXPORT  TIM8_TRG_COM_TIM14_IRQHandler   [WEAK]
                 EXPORT  TIM8_CC_IRQHandler              [WEAK]
                 EXPORT  DMA1_Stream7_IRQHandler         [WEAK]
-                EXPORT  FSMC_IRQHandler                 [WEAK]
+                EXPORT  FMC_IRQHandler                  [WEAK]
                 EXPORT  SDIO_IRQHandler                 [WEAK]
                 EXPORT  TIM5_IRQHandler                 [WEAK]
                 EXPORT  SPI3_IRQHandler                 [WEAK]
@@ -299,7 +321,6 @@ Default_Handler PROC
                 EXPORT  OTG_HS_WKUP_IRQHandler          [WEAK]
                 EXPORT  OTG_HS_IRQHandler               [WEAK]
                 EXPORT  DCMI_IRQHandler                 [WEAK]
-                EXPORT  CRYP_IRQHandler                 [WEAK]
                 EXPORT  HASH_RNG_IRQHandler             [WEAK]
                 EXPORT  FPU_IRQHandler                  [WEAK]
 
@@ -351,7 +372,7 @@ TIM8_UP_TIM13_IRQHandler
 TIM8_TRG_COM_TIM14_IRQHandler
 TIM8_CC_IRQHandler
 DMA1_Stream7_IRQHandler
-FSMC_IRQHandler
+FMC_IRQHandler
 SDIO_IRQHandler
 TIM5_IRQHandler
 SPI3_IRQHandler
@@ -382,7 +403,6 @@ OTG_HS_EP1_IN_IRQHandler
 OTG_HS_WKUP_IRQHandler
 OTG_HS_IRQHandler
 DCMI_IRQHandler
-CRYP_IRQHandler
 HASH_RNG_IRQHandler
 FPU_IRQHandler
  

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/STM32F407.sct

@@ -1,17 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08000000 0x00100000  {    ; load region size_region
-  ER_IROM1 0x08000000 0x00100000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  RW_IRAM1 0x10000000 0x00010000  {  ; CCM
-  }
-  RW_IRAM2 0x20000188 0x0001FE78 {
-   .ANY (+RW +ZI)
-  }
-}
-

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/STM32F407xx.sct

@@ -0,0 +1,18 @@
+; *****************************************
+; *** Scatter-Loading Description File  ***
+; *****************************************
+
+LR_IROM1 0x08000000 0x00100000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000188 0x0001FE78 {
+   .ANY (+RW +ZI)
+  }
+  RW_IRAM2 0x10000000 0x00010000  {  ; CCM
+   .ANY (CCMRAM)
+  }
+}
+

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/startup_STM32F407xx.S

@@ -1,23 +1,41 @@
-;/*****************************************************************************
+;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-; * @file:    startup_STM32F40x.s
+;* File Name          : startup_stm32f407xx.s
-; * @purpose: CMSIS Cortex-M4 Core Device Startup File
+;* Author             : MCD Application Team
-; *           for the ST STM32F40x Device Series
+;* Description        : STM32F407xx devices vector table for MDK-ARM_STD toolchain. 
-; * @version: V1.20
+;*                      This module performs:
-; * @date:    16. January 2012
+;*                      - Set the initial SP
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*                      - Set the initial PC == Reset_Handler
-; *
+;*                      - Set the vector table entries with the exceptions ISR address
-; * Copyright (C) 2012 ARM Limited. All rights reserved.
+;*                      - Branches to __main in the C library (which eventually
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M4
+;*                        calls main()).
-; * processor based microcontrollers.  This file can be freely distributed
+;*                      After Reset the CortexM4 processor is in Thread mode,
-; * within development tools that are supporting such ARM based processors.
+;*                      priority is Privileged, and the Stack is set to Main.
-; *
+;* <<< Use Configuration Wizard in Context Menu >>>   
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+;*******************************************************************************
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; 
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+;* Redistribution and use in source and binary forms, with or without modification,
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+;* are permitted provided that the following conditions are met:
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+;*   1. Redistributions of source code must retain the above copyright notice,
-; *
+;*      this list of conditions and the following disclaimer.
-; *****************************************************************************/
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*******************************************************************************
 
 
 
@@ -30,6 +48,8 @@ __initial_sp        EQU     0x20020000  ; Top of RAM
 
                 AREA    RESET, DATA, READONLY
                 EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
 
 __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     Reset_Handler             ; Reset Handler
@@ -96,7 +116,7 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 
                 DCD     TIM8_CC_IRQHandler            ; TIM8 Capture Compare 
                 DCD     DMA1_Stream7_IRQHandler       ; DMA1 Stream7 
-                DCD     FSMC_IRQHandler               ; FSMC 
+                DCD     FMC_IRQHandler                ; FMC 
                 DCD     SDIO_IRQHandler               ; SDIO 
                 DCD     TIM5_IRQHandler               ; TIM5 
                 DCD     SPI3_IRQHandler               ; SPI3 
@@ -127,10 +147,12 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     OTG_HS_WKUP_IRQHandler        ; USB OTG HS Wakeup through EXTI 
                 DCD     OTG_HS_IRQHandler             ; USB OTG HS 
                 DCD     DCMI_IRQHandler               ; DCMI 
-                DCD     CRYP_IRQHandler               ; CRYP crypto 
+                DCD     0                             ; Reserved 
                 DCD     HASH_RNG_IRQHandler           ; Hash and Rng 
                 DCD     FPU_IRQHandler                ; FPU 
+__Vectors_End
 
+__Vectors_Size  EQU  __Vectors_End - __Vectors
 
                 AREA    |.text|, CODE, READONLY
 
@@ -242,7 +264,7 @@ Default_Handler PROC
                 EXPORT  TIM8_TRG_COM_TIM14_IRQHandler   [WEAK]
                 EXPORT  TIM8_CC_IRQHandler              [WEAK]
                 EXPORT  DMA1_Stream7_IRQHandler         [WEAK]
-                EXPORT  FSMC_IRQHandler                 [WEAK]
+                EXPORT  FMC_IRQHandler                  [WEAK]
                 EXPORT  SDIO_IRQHandler                 [WEAK]
                 EXPORT  TIM5_IRQHandler                 [WEAK]
                 EXPORT  SPI3_IRQHandler                 [WEAK]
@@ -273,7 +295,6 @@ Default_Handler PROC
                 EXPORT  OTG_HS_WKUP_IRQHandler          [WEAK]
                 EXPORT  OTG_HS_IRQHandler               [WEAK]
                 EXPORT  DCMI_IRQHandler                 [WEAK]
-                EXPORT  CRYP_IRQHandler                 [WEAK]
                 EXPORT  HASH_RNG_IRQHandler             [WEAK]
                 EXPORT  FPU_IRQHandler                  [WEAK]
 
@@ -325,7 +346,7 @@ TIM8_UP_TIM13_IRQHandler
 TIM8_TRG_COM_TIM14_IRQHandler
 TIM8_CC_IRQHandler
 DMA1_Stream7_IRQHandler
-FSMC_IRQHandler
+FMC_IRQHandler
 SDIO_IRQHandler
 TIM5_IRQHandler
 SPI3_IRQHandler
@@ -356,7 +377,6 @@ OTG_HS_EP1_IN_IRQHandler
 OTG_HS_WKUP_IRQHandler
 OTG_HS_IRQHandler
 DCMI_IRQHandler
-CRYP_IRQHandler
 HASH_RNG_IRQHandler
 FPU_IRQHandler