mirror of https://github.com/ARMmbed/mbed-os.git
Merge remote-tracking branch 'upstream/master'
Conflicts: workspace_tools/targets.pypull/594/head
Takayuki Kurosawa
commit
33a843cf93
|
|
@ -73,6 +73,7 @@ STMicroelectronics:
|
|||
* STM32F3-Discovery (Cortex-M4F)
|
||||
* STM32F4-Discovery (Cortex-M4F)
|
||||
* STM32F429-Discovery (Cortex-M4F)
|
||||
* STM32L0-Discovery (Cortex-M0+)
|
||||
* [Arch Max](https://developer.mbed.org/platforms/Seeed-Arch-Max/) (Cortex-M4F)
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
#ifndef MBED_H
|
||||
#define MBED_H
|
||||
|
||||
#define MBED_LIBRARY_VERSION 90
|
||||
#define MBED_LIBRARY_VERSION 91
|
||||
|
||||
#include "platform.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ void us_ticker_irq_handler(void) {
|
|||
return;
|
||||
}
|
||||
|
||||
if ((int64_t)(head->timestamp - us_ticker_read()) <= 0) {
|
||||
if ((int)(head->timestamp - us_ticker_read()) <= 0) {
|
||||
// This event was in the past:
|
||||
// point to the following one and execute its handler
|
||||
ticker_event_t *p = head;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,49 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0001ffff;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x1fffe000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x800;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_RAM2_start__ = 0x20000000;
|
||||
define symbol __region_RAM2_end__ = 0x20001fff;
|
||||
|
||||
define symbol __FlashConfig_start__ = 0x00000400;
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||||
define symbol __FlashConfig_end__ = 0x0000040f;
|
||||
|
||||
define symbol __region_FlexNVM_start__ = 0x10000000;
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||||
define symbol __region_FlexNVM_end__ = 0x10007fff;
|
||||
|
||||
define symbol __region_FlexRAM_start__ = 0x14000000;
|
||||
define symbol __region_FlexRAM_end__ = 0x140007ff;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__] | mem:[from __region_FlexNVM_start__ to __region_FlexNVM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
|
||||
define region FlexRAM_region = mem:[from __region_FlexRAM_start__ to __region_FlexRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in FlashConfig_region {section FlashConfig};
|
||||
|
||||
place in ROM_region { readonly };
|
||||
|
||||
place in RAM_region { readwrite, block CSTACK, block HEAP };
|
||||
|
||||
place in FlexRAM_region { section .flex_ram };
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||||
|
|
@ -0,0 +1,271 @@
|
|||
/**************************************************
|
||||
*
|
||||
* Copyright 2010 IAR Systems. All rights reserved.
|
||||
*
|
||||
* $Revision: 16 $
|
||||
*
|
||||
**************************************************/
|
||||
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:ROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
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||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
; External Interrupts
|
||||
DCD DMA0_IRQHandler ; 0: DMA Channel 0 transfer complete
|
||||
DCD DMA1_IRQHandler ; 1: DMA Channel 1 transfer complete
|
||||
DCD DMA2_IRQHandler ; 2: DMA Channel 2 transfer complete
|
||||
DCD DMA3_IRQHandler ; 3: DMA Channel 3 transfer complete
|
||||
DCD DMA_ERR_IRQHandler ; 4: DMA Error Interrupt Channels 0-15
|
||||
DCD 0 ; 5: Reserved
|
||||
DCD FLASH_CC_IRQHandler ; 6: Flash memory command complete
|
||||
DCD FLASH_RC_IRQHandler ; 7: Flash memory read collision
|
||||
DCD VLD_IRQHandler ; 8: Low Voltage Detect, Low Voltage Warning
|
||||
DCD LLWU_IRQHandler ; 9: Low Leakage Wakeup
|
||||
DCD WDOG_IRQHandler ;10: WDOG interrupt
|
||||
DCD I2C0_IRQHandler ;11: I2C0 interrupt
|
||||
DCD SPI0_IRQHandler ;12: SPI 0 interrupt
|
||||
DCD I2S0_IRQHandler ;13: I2S 0 interrupt
|
||||
DCD I2S1_IRQHandler ;14: I2S 1 interrupt
|
||||
DCD UART0_LON_IRQHandler ;15: UART 0 LON intertrupt
|
||||
DCD UART0_IRQHandler ;16: UART 0 intertrupt
|
||||
DCD UART0_ERR_IRQHandler ;17: UART 0 error intertrupt
|
||||
DCD UART1_IRQHandler ;18: UART 1 intertrupt
|
||||
DCD UART1_ERR_IRQHandler ;19: UART 1 error intertrupt
|
||||
DCD UART2_IRQHandler ;20: UART 2 intertrupt
|
||||
DCD UART2_ERR_IRQHandler ;21: UART 2 error intertrupt
|
||||
DCD ADC0_IRQHandler ;22: ADC 0 interrupt
|
||||
DCD CMP0_IRQHandler ;23: CMP 0 High-speed comparator interrupt
|
||||
DCD CMP1_IRQHandler ;24: CMP 1 interrupt
|
||||
DCD FTM0_IRQHandler ;25: FTM 0 interrupt
|
||||
DCD FTM1_IRQHandler ;26: FTM 1 interrupt
|
||||
DCD CMT_IRQHandler ;27: CMT intrrupt
|
||||
DCD RTC_ALRM_IRQHandler ;28: RTC Alarm interrupt
|
||||
DCD RTC_SEC_IRQHandler ;29: RTC Sec interrupt
|
||||
DCD PIT0_IRQHandler ;30: PIT 0 interrupt
|
||||
DCD PIT1_IRQHandler ;31: PIT 1 interrupt
|
||||
DCD PIT2_IRQHandler ;32: PIT 2 interrupt
|
||||
DCD PIT3_IRQHandler ;33: PIT 3 interrupt
|
||||
DCD PDB_IRQHandler ;34: PDB interrupt
|
||||
DCD USB_OTG_IRQHandler ;35: USB OTG interrupt
|
||||
DCD USB_CD_IRQHandler ;36: USB Charger Detect interrupt
|
||||
DCD TSI_IRQHandler ;37: TSI interrupt
|
||||
DCD MCG_IRQHandler ;38: MCG interrupt
|
||||
DCD LPT_IRQHandler ;39: LPT interrupt
|
||||
DCD PORTA_IRQHandler ;40: PORT A interrupt
|
||||
DCD PORTB_IRQHandler ;41: PORT B interrupt
|
||||
DCD PORTC_IRQHandler ;42: PORT C interrupt
|
||||
DCD PORTD_IRQHandler ;43: PORT D interrupt
|
||||
DCD PORTE_IRQHandler ;44: PORT E interrupt
|
||||
DCD SW_IRQHandler ;45: Software initiated interrupt
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;Flash Configuration
|
||||
;;16-byte flash configuration field that stores default protection settings (loaded on reset)
|
||||
;;and security information that allows the MCU to restrict acces to the FTFL module.
|
||||
|
||||
BackDoorK0 EQU 0xFF
|
||||
BackDoorK1 EQU 0xFF
|
||||
BackDoorK2 EQU 0xFF
|
||||
BackDoorK3 EQU 0xFF
|
||||
BackDoorK4 EQU 0xFF
|
||||
BackDoorK5 EQU 0xFF
|
||||
BackDoorK6 EQU 0xFF
|
||||
BackDoorK7 EQU 0xFF
|
||||
|
||||
nFPROT0 EQU 0x00
|
||||
FPROT0 EQU nFPROT0^0xFF
|
||||
|
||||
nFPROT1 EQU 0x00
|
||||
FPROT1 EQU nFPROT1^0xFF
|
||||
|
||||
nFPROT2 EQU 0x00
|
||||
FPROT2 EQU nFPROT2^0xFF
|
||||
|
||||
nFPROT3 EQU 0x00
|
||||
FPROT3 EQU nFPROT3^0xFF
|
||||
|
||||
nFEPROT EQU 0x00
|
||||
FEPROT EQU nFEPROT^0xFF
|
||||
|
||||
nFDPROT EQU 0x00
|
||||
FDPROT EQU nFDPROT^0xFF
|
||||
|
||||
FOPT EQU 0xFF
|
||||
|
||||
FSEC EQU 0xFE
|
||||
SECTION FlashConfig:CONST:REORDER:ROOT(2)
|
||||
Config:
|
||||
DATA
|
||||
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
|
||||
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
|
||||
DCB FPROT0, FPROT1, FPROT2, FPROT3
|
||||
DCB FSEC, FOPT, FEPROT, FDPROT
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
PUBWEAK HardFault_Handler
|
||||
PUBWEAK MemManage_Handler
|
||||
PUBWEAK BusFault_Handler
|
||||
PUBWEAK UsageFault_Handler
|
||||
PUBWEAK SVC_Handler
|
||||
PUBWEAK DebugMon_Handler
|
||||
PUBWEAK PendSV_Handler
|
||||
PUBWEAK SysTick_Handler
|
||||
PUBWEAK DMA0_IRQHandler
|
||||
PUBWEAK DMA1_IRQHandler
|
||||
PUBWEAK DMA2_IRQHandler
|
||||
PUBWEAK DMA3_IRQHandler
|
||||
PUBWEAK DMA_ERR_IRQHandler
|
||||
PUBWEAK FLASH_CC_IRQHandler
|
||||
PUBWEAK FLASH_RC_IRQHandler
|
||||
PUBWEAK VLD_IRQHandler
|
||||
PUBWEAK LLWU_IRQHandler
|
||||
PUBWEAK WDOG_IRQHandler
|
||||
PUBWEAK I2C0_IRQHandler
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
PUBWEAK I2S0_IRQHandler
|
||||
PUBWEAK I2S1_IRQHandler
|
||||
PUBWEAK UART0_LON_IRQHandler
|
||||
PUBWEAK UART0_IRQHandler
|
||||
PUBWEAK UART0_ERR_IRQHandler
|
||||
PUBWEAK UART1_IRQHandler
|
||||
PUBWEAK UART1_ERR_IRQHandler
|
||||
PUBWEAK UART2_IRQHandler
|
||||
PUBWEAK UART2_ERR_IRQHandler
|
||||
PUBWEAK ADC0_IRQHandler
|
||||
PUBWEAK CMP0_IRQHandler
|
||||
PUBWEAK CMP1_IRQHandler
|
||||
PUBWEAK FTM0_IRQHandler
|
||||
PUBWEAK FTM1_IRQHandler
|
||||
PUBWEAK CMT_IRQHandler
|
||||
PUBWEAK RTC_ALRM_IRQHandler
|
||||
PUBWEAK RTC_SEC_IRQHandler
|
||||
PUBWEAK PIT0_IRQHandler
|
||||
PUBWEAK PIT1_IRQHandler
|
||||
PUBWEAK PIT2_IRQHandler
|
||||
PUBWEAK PIT3_IRQHandler
|
||||
PUBWEAK PDB_IRQHandler
|
||||
PUBWEAK USB_OTG_IRQHandler
|
||||
PUBWEAK USB_CD_IRQHandler
|
||||
PUBWEAK TSI_IRQHandler
|
||||
PUBWEAK MCG_IRQHandler
|
||||
PUBWEAK LPT_IRQHandler
|
||||
PUBWEAK PORTA_IRQHandler
|
||||
PUBWEAK PORTB_IRQHandler
|
||||
PUBWEAK PORTC_IRQHandler
|
||||
PUBWEAK PORTD_IRQHandler
|
||||
PUBWEAK PORTE_IRQHandler
|
||||
PUBWEAK SW_IRQHandler
|
||||
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
THUMB
|
||||
NMI_Handler
|
||||
HardFault_Handler
|
||||
MemManage_Handler
|
||||
BusFault_Handler
|
||||
UsageFault_Handler
|
||||
SVC_Handler
|
||||
DebugMon_Handler
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
DMA0_IRQHandler
|
||||
DMA1_IRQHandler
|
||||
DMA2_IRQHandler
|
||||
DMA3_IRQHandler
|
||||
DMA_ERR_IRQHandler
|
||||
FLASH_CC_IRQHandler
|
||||
FLASH_RC_IRQHandler
|
||||
VLD_IRQHandler
|
||||
LLWU_IRQHandler
|
||||
WDOG_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
I2S0_IRQHandler
|
||||
I2S1_IRQHandler
|
||||
UART0_LON_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART0_ERR_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART1_ERR_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART2_ERR_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
CMP0_IRQHandler
|
||||
CMP1_IRQHandler
|
||||
FTM0_IRQHandler
|
||||
FTM1_IRQHandler
|
||||
CMT_IRQHandler
|
||||
RTC_ALRM_IRQHandler
|
||||
RTC_SEC_IRQHandler
|
||||
PIT0_IRQHandler
|
||||
PIT1_IRQHandler
|
||||
PIT2_IRQHandler
|
||||
PIT3_IRQHandler
|
||||
PDB_IRQHandler
|
||||
USB_OTG_IRQHandler
|
||||
USB_CD_IRQHandler
|
||||
TSI_IRQHandler
|
||||
MCG_IRQHandler
|
||||
LPT_IRQHandler
|
||||
PORTA_IRQHandler
|
||||
PORTB_IRQHandler
|
||||
PORTC_IRQHandler
|
||||
PORTD_IRQHandler
|
||||
PORTE_IRQHandler
|
||||
SW_IRQHandler
|
||||
Default_Handler
|
||||
|
||||
B Default_Handler
|
||||
END
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0007ffff;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x1fff8000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x2000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x4000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_RAM2_start__ = 0x20000000;
|
||||
define symbol __region_RAM2_end__ = 0x20007fff;
|
||||
|
||||
define symbol __FlashConfig_start__ = 0x00000400;
|
||||
define symbol __FlashConfig_end__ = 0x0000040f;
|
||||
|
||||
define symbol __region_FlexNVM_start__ = 0x10000000;
|
||||
define symbol __region_FlexNVM_end__ = 0x1001ffff;
|
||||
|
||||
define symbol __region_FlexRAM_start__ = 0x14000000;
|
||||
define symbol __region_FlexRAM_end__ = 0x14000fff;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__] | mem:[from __region_FlexNVM_start__ to __region_FlexNVM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
|
||||
define region FlexRAM_region = mem:[from __region_FlexRAM_start__ to __region_FlexRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in FlashConfig_region {section FlashConfig};
|
||||
|
||||
place in ROM_region { readonly };
|
||||
|
||||
place in RAM_region { readwrite, block CSTACK, block HEAP };
|
||||
|
||||
place in FlexRAM_region { section .flex_ram };
|
||||
|
|
@ -0,0 +1,535 @@
|
|||
/**************************************************
|
||||
*
|
||||
* Copyright 2012 IAR Systems. All rights reserved.
|
||||
*
|
||||
* $Revision: 16 $
|
||||
*
|
||||
**************************************************/
|
||||
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:ROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
; External Interrupts
|
||||
DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
|
||||
DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
|
||||
DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
|
||||
DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
|
||||
DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
|
||||
DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
|
||||
DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
|
||||
DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
|
||||
DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
|
||||
DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
|
||||
DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
|
||||
DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
|
||||
DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
|
||||
DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
|
||||
DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
|
||||
DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
|
||||
DCD DMA_Error_IRQHandler ; DMA Error Interrupt
|
||||
DCD MCM_IRQHandler ; Normal Interrupt
|
||||
DCD FTFE_IRQHandler ; FTFE Command complete interrupt
|
||||
DCD Read_Collision_IRQHandler ; Read Collision Interrupt
|
||||
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
|
||||
DCD LLW_IRQHandler ; Low Leakage Wakeup
|
||||
DCD Watchdog_IRQHandler ; WDOG Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C0_IRQHandler ; I2C0 interrupt
|
||||
DCD I2C1_IRQHandler ; I2C1 interrupt
|
||||
DCD SPI0_IRQHandler ; SPI0 Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
|
||||
DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
|
||||
DCD UART0_LON_IRQHandler ; UART0 LON interrupt
|
||||
DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
|
||||
DCD UART0_ERR_IRQHandler ; UART0 Error interrupt
|
||||
DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
|
||||
DCD UART1_ERR_IRQHandler ; UART1 Error interrupt
|
||||
DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
|
||||
DCD UART2_ERR_IRQHandler ; UART2 Error interrupt
|
||||
DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
|
||||
DCD UART3_ERR_IRQHandler ; UART3 Error interrupt
|
||||
DCD ADC0_IRQHandler ; ADC0 interrupt
|
||||
DCD CMP0_IRQHandler ; CMP0 interrupt
|
||||
DCD CMP1_IRQHandler ; CMP1 interrupt
|
||||
DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
|
||||
DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
|
||||
DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
|
||||
DCD CMT_IRQHandler ; CMT interrupt
|
||||
DCD RTC_IRQHandler ; RTC interrupt
|
||||
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
|
||||
DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
|
||||
DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
|
||||
DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
|
||||
DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
|
||||
DCD PDB0_IRQHandler ; PDB0 Interrupt
|
||||
DCD USB0_IRQHandler ; USB0 interrupt
|
||||
DCD USBDCD_IRQHandler ; USBDCD Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD DAC0_IRQHandler ; DAC0 interrupt
|
||||
DCD MCG_IRQHandler ; MCG Interrupt
|
||||
DCD LPTimer_IRQHandler ; LPTimer interrupt
|
||||
DCD PORTA_IRQHandler ; Port A interrupt
|
||||
DCD PORTB_IRQHandler ; Port B interrupt
|
||||
DCD PORTC_IRQHandler ; Port C interrupt
|
||||
DCD PORTD_IRQHandler ; Port D interrupt
|
||||
DCD PORTE_IRQHandler ; Port E interrupt
|
||||
DCD SWI_IRQHandler ; Software interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
|
||||
DCD UART4_ERR_IRQHandler ; UART4 Error interrupt
|
||||
DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
|
||||
DCD UART5_ERR_IRQHandler ; UART5 Error interrupt
|
||||
DCD CMP2_IRQHandler ; CMP2 interrupt
|
||||
DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt
|
||||
DCD DAC1_IRQHandler ; DAC1 interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 interrupt
|
||||
DCD I2C2_IRQHandler ; I2C2 interrupt
|
||||
DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
|
||||
DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
|
||||
DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
|
||||
DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
|
||||
DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
|
||||
DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
|
||||
DCD SDHC_IRQHandler ; SDHC interrupt
|
||||
DCD Default_Handler ; 98
|
||||
DCD Default_Handler ; 99
|
||||
DCD Default_Handler ; 100
|
||||
DCD Default_Handler ; 101
|
||||
DCD Default_Handler ; 102
|
||||
DCD Default_Handler ; 103
|
||||
DCD Default_Handler ; 104
|
||||
DCD Default_Handler ; 105
|
||||
DCD Default_Handler ; 106
|
||||
DCD Default_Handler ; 107
|
||||
DCD Default_Handler ; 108
|
||||
DCD Default_Handler ; 109
|
||||
DCD Default_Handler ; 110
|
||||
DCD Default_Handler ; 111
|
||||
DCD Default_Handler ; 112
|
||||
DCD Default_Handler ; 113
|
||||
DCD Default_Handler ; 114
|
||||
DCD Default_Handler ; 115
|
||||
DCD Default_Handler ; 116
|
||||
DCD Default_Handler ; 117
|
||||
DCD Default_Handler ; 118
|
||||
DCD Default_Handler ; 119
|
||||
DCD Default_Handler ; 120
|
||||
DCD Default_Handler ; 121
|
||||
DCD Default_Handler ; 122
|
||||
DCD Default_Handler ; 123
|
||||
DCD Default_Handler ; 124
|
||||
DCD Default_Handler ; 125
|
||||
DCD Default_Handler ; 126
|
||||
DCD Default_Handler ; 127
|
||||
DCD Default_Handler ; 128
|
||||
DCD Default_Handler ; 129
|
||||
DCD Default_Handler ; 130
|
||||
DCD Default_Handler ; 131
|
||||
DCD Default_Handler ; 132
|
||||
DCD Default_Handler ; 133
|
||||
DCD Default_Handler ; 134
|
||||
DCD Default_Handler ; 135
|
||||
DCD Default_Handler ; 136
|
||||
DCD Default_Handler ; 137
|
||||
DCD Default_Handler ; 138
|
||||
DCD Default_Handler ; 139
|
||||
DCD Default_Handler ; 140
|
||||
DCD Default_Handler ; 141
|
||||
DCD Default_Handler ; 142
|
||||
DCD Default_Handler ; 143
|
||||
DCD Default_Handler ; 144
|
||||
DCD Default_Handler ; 145
|
||||
DCD Default_Handler ; 146
|
||||
DCD Default_Handler ; 147
|
||||
DCD Default_Handler ; 148
|
||||
DCD Default_Handler ; 149
|
||||
DCD Default_Handler ; 150
|
||||
DCD Default_Handler ; 151
|
||||
DCD Default_Handler ; 152
|
||||
DCD Default_Handler ; 153
|
||||
DCD Default_Handler ; 154
|
||||
DCD Default_Handler ; 155
|
||||
DCD Default_Handler ; 156
|
||||
DCD Default_Handler ; 157
|
||||
DCD Default_Handler ; 158
|
||||
DCD Default_Handler ; 159
|
||||
DCD Default_Handler ; 160
|
||||
DCD Default_Handler ; 161
|
||||
DCD Default_Handler ; 162
|
||||
DCD Default_Handler ; 163
|
||||
DCD Default_Handler ; 164
|
||||
DCD Default_Handler ; 165
|
||||
DCD Default_Handler ; 166
|
||||
DCD Default_Handler ; 167
|
||||
DCD Default_Handler ; 168
|
||||
DCD Default_Handler ; 169
|
||||
DCD Default_Handler ; 170
|
||||
DCD Default_Handler ; 171
|
||||
DCD Default_Handler ; 172
|
||||
DCD Default_Handler ; 173
|
||||
DCD Default_Handler ; 174
|
||||
DCD Default_Handler ; 175
|
||||
DCD Default_Handler ; 176
|
||||
DCD Default_Handler ; 177
|
||||
DCD Default_Handler ; 178
|
||||
DCD Default_Handler ; 179
|
||||
DCD Default_Handler ; 180
|
||||
DCD Default_Handler ; 181
|
||||
DCD Default_Handler ; 182
|
||||
DCD Default_Handler ; 183
|
||||
DCD Default_Handler ; 184
|
||||
DCD Default_Handler ; 185
|
||||
DCD Default_Handler ; 186
|
||||
DCD Default_Handler ; 187
|
||||
DCD Default_Handler ; 188
|
||||
DCD Default_Handler ; 189
|
||||
DCD Default_Handler ; 190
|
||||
DCD Default_Handler ; 191
|
||||
DCD Default_Handler ; 192
|
||||
DCD Default_Handler ; 193
|
||||
DCD Default_Handler ; 194
|
||||
DCD Default_Handler ; 195
|
||||
DCD Default_Handler ; 196
|
||||
DCD Default_Handler ; 197
|
||||
DCD Default_Handler ; 198
|
||||
DCD Default_Handler ; 199
|
||||
DCD Default_Handler ; 200
|
||||
DCD Default_Handler ; 201
|
||||
DCD Default_Handler ; 202
|
||||
DCD Default_Handler ; 203
|
||||
DCD Default_Handler ; 204
|
||||
DCD Default_Handler ; 205
|
||||
DCD Default_Handler ; 206
|
||||
DCD Default_Handler ; 207
|
||||
DCD Default_Handler ; 208
|
||||
DCD Default_Handler ; 209
|
||||
DCD Default_Handler ; 210
|
||||
DCD Default_Handler ; 211
|
||||
DCD Default_Handler ; 212
|
||||
DCD Default_Handler ; 213
|
||||
DCD Default_Handler ; 214
|
||||
DCD Default_Handler ; 215
|
||||
DCD Default_Handler ; 216
|
||||
DCD Default_Handler ; 217
|
||||
DCD Default_Handler ; 218
|
||||
DCD Default_Handler ; 219
|
||||
DCD Default_Handler ; 220
|
||||
DCD Default_Handler ; 221
|
||||
DCD Default_Handler ; 222
|
||||
DCD Default_Handler ; 223
|
||||
DCD Default_Handler ; 224
|
||||
DCD Default_Handler ; 225
|
||||
DCD Default_Handler ; 226
|
||||
DCD Default_Handler ; 227
|
||||
DCD Default_Handler ; 228
|
||||
DCD Default_Handler ; 229
|
||||
DCD Default_Handler ; 230
|
||||
DCD Default_Handler ; 231
|
||||
DCD Default_Handler ; 232
|
||||
DCD Default_Handler ; 233
|
||||
DCD Default_Handler ; 234
|
||||
DCD Default_Handler ; 235
|
||||
DCD Default_Handler ; 236
|
||||
DCD Default_Handler ; 237
|
||||
DCD Default_Handler ; 238
|
||||
DCD Default_Handler ; 239
|
||||
DCD Default_Handler ; 240
|
||||
DCD Default_Handler ; 241
|
||||
DCD Default_Handler ; 242
|
||||
DCD Default_Handler ; 243
|
||||
DCD Default_Handler ; 244
|
||||
DCD Default_Handler ; 245
|
||||
DCD Default_Handler ; 246
|
||||
DCD Default_Handler ; 247
|
||||
DCD Default_Handler ; 248
|
||||
DCD Default_Handler ; 249
|
||||
DCD Default_Handler ; 250
|
||||
DCD Default_Handler ; 251
|
||||
DCD Default_Handler ; 252
|
||||
DCD Default_Handler ; 253
|
||||
DCD Default_Handler ; 254
|
||||
DCD Default_Handler ; 255
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;Flash Configuration
|
||||
;;16-byte flash configuration field that stores default protection settings (loaded on reset)
|
||||
;;and security information that allows the MCU to restrict acces to the FTFL module.
|
||||
|
||||
BackDoorK0 EQU 0xFF
|
||||
BackDoorK1 EQU 0xFF
|
||||
BackDoorK2 EQU 0xFF
|
||||
BackDoorK3 EQU 0xFF
|
||||
BackDoorK4 EQU 0xFF
|
||||
BackDoorK5 EQU 0xFF
|
||||
BackDoorK6 EQU 0xFF
|
||||
BackDoorK7 EQU 0xFF
|
||||
|
||||
nFPROT0 EQU 0x00
|
||||
FPROT0 EQU nFPROT0^0xFF
|
||||
|
||||
nFPROT1 EQU 0x00
|
||||
FPROT1 EQU nFPROT1^0xFF
|
||||
|
||||
nFPROT2 EQU 0x00
|
||||
FPROT2 EQU nFPROT2^0xFF
|
||||
|
||||
nFPROT3 EQU 0x00
|
||||
FPROT3 EQU nFPROT3^0xFF
|
||||
|
||||
nFEPROT EQU 0x00
|
||||
FEPROT EQU nFEPROT^0xFF
|
||||
|
||||
nFDPROT EQU 0x00
|
||||
FDPROT EQU nFDPROT^0xFF
|
||||
|
||||
FOPT EQU 0xFF
|
||||
|
||||
FSEC EQU 0xFE
|
||||
SECTION FlashConfig:CONST:REORDER:ROOT(2)
|
||||
Config:
|
||||
DATA
|
||||
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
|
||||
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
|
||||
DCB FPROT0, FPROT1, FPROT2, FPROT3
|
||||
DCB FSEC, FOPT, FEPROT, FDPROT
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
PUBWEAK HardFault_Handler
|
||||
PUBWEAK MemManage_Handler
|
||||
PUBWEAK BusFault_Handler
|
||||
PUBWEAK UsageFault_Handler
|
||||
PUBWEAK SVC_Handler
|
||||
PUBWEAK DebugMon_Handler
|
||||
PUBWEAK PendSV_Handler
|
||||
PUBWEAK SysTick_Handler
|
||||
PUBWEAK DMA0_IRQHandler
|
||||
PUBWEAK DMA1_IRQHandler
|
||||
PUBWEAK DMA2_IRQHandler
|
||||
PUBWEAK DMA3_IRQHandler
|
||||
PUBWEAK DMA4_IRQHandler
|
||||
PUBWEAK DMA5_IRQHandler
|
||||
PUBWEAK DMA6_IRQHandler
|
||||
PUBWEAK DMA7_IRQHandler
|
||||
PUBWEAK DMA8_IRQHandler
|
||||
PUBWEAK DMA9_IRQHandler
|
||||
PUBWEAK DMA10_IRQHandler
|
||||
PUBWEAK DMA11_IRQHandler
|
||||
PUBWEAK DMA12_IRQHandler
|
||||
PUBWEAK DMA13_IRQHandler
|
||||
PUBWEAK DMA14_IRQHandler
|
||||
PUBWEAK DMA15_IRQHandler
|
||||
PUBWEAK DMA_Error_IRQHandler
|
||||
PUBWEAK MCM_IRQHandler
|
||||
PUBWEAK FTFE_IRQHandler
|
||||
PUBWEAK Read_Collision_IRQHandler
|
||||
PUBWEAK LVD_LVW_IRQHandler
|
||||
PUBWEAK LLW_IRQHandler
|
||||
PUBWEAK Watchdog_IRQHandler
|
||||
PUBWEAK I2C0_IRQHandler
|
||||
PUBWEAK I2C1_IRQHandler
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
PUBWEAK I2S0_Tx_IRQHandler
|
||||
PUBWEAK I2S0_Rx_IRQHandler
|
||||
PUBWEAK UART0_LON_IRQHandler
|
||||
PUBWEAK UART0_RX_TX_IRQHandler
|
||||
PUBWEAK UART0_ERR_IRQHandler
|
||||
PUBWEAK UART1_RX_TX_IRQHandler
|
||||
PUBWEAK UART1_ERR_IRQHandler
|
||||
PUBWEAK UART2_RX_TX_IRQHandler
|
||||
PUBWEAK UART2_ERR_IRQHandler
|
||||
PUBWEAK UART3_RX_TX_IRQHandler
|
||||
PUBWEAK UART3_ERR_IRQHandler
|
||||
PUBWEAK ADC0_IRQHandler
|
||||
PUBWEAK CMP0_IRQHandler
|
||||
PUBWEAK CMP1_IRQHandler
|
||||
PUBWEAK FTM0_IRQHandler
|
||||
PUBWEAK FTM1_IRQHandler
|
||||
PUBWEAK FTM2_IRQHandler
|
||||
PUBWEAK CMT_IRQHandler
|
||||
PUBWEAK RTC_IRQHandler
|
||||
PUBWEAK RTC_Seconds_IRQHandler
|
||||
PUBWEAK PIT0_IRQHandler
|
||||
PUBWEAK PIT1_IRQHandler
|
||||
PUBWEAK PIT2_IRQHandler
|
||||
PUBWEAK PIT3_IRQHandler
|
||||
PUBWEAK PDB0_IRQHandler
|
||||
PUBWEAK USB0_IRQHandler
|
||||
PUBWEAK USBDCD_IRQHandler
|
||||
PUBWEAK DAC0_IRQHandler
|
||||
PUBWEAK MCG_IRQHandler
|
||||
PUBWEAK LPTimer_IRQHandler
|
||||
PUBWEAK PORTA_IRQHandler
|
||||
PUBWEAK PORTB_IRQHandler
|
||||
PUBWEAK PORTC_IRQHandler
|
||||
PUBWEAK PORTD_IRQHandler
|
||||
PUBWEAK PORTE_IRQHandler
|
||||
PUBWEAK SWI_IRQHandler
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
PUBWEAK UART4_RX_TX_IRQHandler
|
||||
PUBWEAK UART4_ERR_IRQHandler
|
||||
PUBWEAK UART5_RX_TX_IRQHandler
|
||||
PUBWEAK UART5_ERR_IRQHandler
|
||||
PUBWEAK CMP2_IRQHandler
|
||||
PUBWEAK FTM3_IRQHandler
|
||||
PUBWEAK DAC1_IRQHandler
|
||||
PUBWEAK ADC1_IRQHandler
|
||||
PUBWEAK I2C2_IRQHandler
|
||||
PUBWEAK CAN0_ORed_Message_buffer_IRQHandler
|
||||
PUBWEAK CAN0_Bus_Off_IRQHandler
|
||||
PUBWEAK CAN0_Error_IRQHandler
|
||||
PUBWEAK CAN0_Tx_Warning_IRQHandler
|
||||
PUBWEAK CAN0_Rx_Warning_IRQHandler
|
||||
PUBWEAK CAN0_Wake_Up_IRQHandler
|
||||
PUBWEAK SDHC_IRQHandler
|
||||
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
THUMB
|
||||
NMI_Handler
|
||||
HardFault_Handler
|
||||
MemManage_Handler
|
||||
BusFault_Handler
|
||||
UsageFault_Handler
|
||||
SVC_Handler
|
||||
DebugMon_Handler
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
DMA0_IRQHandler
|
||||
DMA1_IRQHandler
|
||||
DMA2_IRQHandler
|
||||
DMA3_IRQHandler
|
||||
DMA4_IRQHandler
|
||||
DMA5_IRQHandler
|
||||
DMA6_IRQHandler
|
||||
DMA7_IRQHandler
|
||||
DMA8_IRQHandler
|
||||
DMA9_IRQHandler
|
||||
DMA10_IRQHandler
|
||||
DMA11_IRQHandler
|
||||
DMA12_IRQHandler
|
||||
DMA13_IRQHandler
|
||||
DMA14_IRQHandler
|
||||
DMA15_IRQHandler
|
||||
DMA_Error_IRQHandler
|
||||
MCM_IRQHandler
|
||||
FTFE_IRQHandler
|
||||
Read_Collision_IRQHandler
|
||||
LVD_LVW_IRQHandler
|
||||
LLW_IRQHandler
|
||||
Watchdog_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
I2S0_Tx_IRQHandler
|
||||
I2S0_Rx_IRQHandler
|
||||
UART0_LON_IRQHandler
|
||||
UART0_RX_TX_IRQHandler
|
||||
UART0_ERR_IRQHandler
|
||||
UART1_RX_TX_IRQHandler
|
||||
UART1_ERR_IRQHandler
|
||||
UART2_RX_TX_IRQHandler
|
||||
UART2_ERR_IRQHandler
|
||||
UART3_RX_TX_IRQHandler
|
||||
UART3_ERR_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
CMP0_IRQHandler
|
||||
CMP1_IRQHandler
|
||||
FTM0_IRQHandler
|
||||
FTM1_IRQHandler
|
||||
FTM2_IRQHandler
|
||||
CMT_IRQHandler
|
||||
RTC_IRQHandler
|
||||
RTC_Seconds_IRQHandler
|
||||
PIT0_IRQHandler
|
||||
PIT1_IRQHandler
|
||||
PIT2_IRQHandler
|
||||
PIT3_IRQHandler
|
||||
PDB0_IRQHandler
|
||||
USB0_IRQHandler
|
||||
USBDCD_IRQHandler
|
||||
DAC0_IRQHandler
|
||||
MCG_IRQHandler
|
||||
LPTimer_IRQHandler
|
||||
PORTA_IRQHandler
|
||||
PORTB_IRQHandler
|
||||
PORTC_IRQHandler
|
||||
PORTD_IRQHandler
|
||||
PORTE_IRQHandler
|
||||
SWI_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
UART4_RX_TX_IRQHandler
|
||||
UART4_ERR_IRQHandler
|
||||
UART5_RX_TX_IRQHandler
|
||||
UART5_ERR_IRQHandler
|
||||
CMP2_IRQHandler
|
||||
FTM3_IRQHandler
|
||||
DAC1_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
I2C2_IRQHandler
|
||||
CAN0_ORed_Message_buffer_IRQHandler
|
||||
CAN0_Bus_Off_IRQHandler
|
||||
CAN0_Error_IRQHandler
|
||||
CAN0_Tx_Warning_IRQHandler
|
||||
CAN0_Rx_Warning_IRQHandler
|
||||
CAN0_Wake_Up_IRQHandler
|
||||
SDHC_IRQHandler
|
||||
Default_Handler
|
||||
|
||||
B Default_Handler
|
||||
END
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x00007fff;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x1ffffc00;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x200;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_RAM2_start__ = 0x20000000;
|
||||
define symbol __region_RAM2_end__ = 0x20000bff;
|
||||
|
||||
define symbol __FlashConfig_start__ = 0x00000400;
|
||||
define symbol __FlashConfig_end__ = 0x0000040f;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in FlashConfig_region {section FlashConfig};
|
||||
|
||||
place in ROM_region { readonly };
|
||||
|
||||
place in RAM_region { readwrite, block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,199 @@
|
|||
/**************************************************
|
||||
*
|
||||
* Copyright 2012 IAR Systems. All rights reserved.
|
||||
*
|
||||
* $Revision: 16 $
|
||||
*
|
||||
**************************************************/
|
||||
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:ROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
; External Interrupts
|
||||
DCD DMA0_IRQHandler ; 0: DMA Channel 0 transfer complete intertrupt
|
||||
DCD DMA1_IRQHandler ; 1: DMA Channel 1 transfer complete intertrupt
|
||||
DCD DMA2_IRQHandler ; 2: DMA Channel 2 transfer complete intertrupt
|
||||
DCD DMA3_IRQHandler ; 3: DMA Channel 3 transfer complete intertrupt
|
||||
DCD 0 ; 4: Reserved
|
||||
DCD FTFA_IRQHandler ; 5: FTFA
|
||||
DCD LVD_LVW_IRQHandler ; 6: Low-voltage detect, low-voltage warning
|
||||
DCD LLW_IRQHandler ; 7: Low Leakage Wakeup
|
||||
DCD I2C0_IRQHandler ; 8: IIC 0 interrupt
|
||||
DCD 0 ; 9: Reserved
|
||||
DCD SPI0_IRQHandler ;10: SPI0 intertrupt
|
||||
DCD 0 ;11: Reserved
|
||||
DCD UART0_IRQHandler ;12: UART 0 status and error intertrupt
|
||||
DCD 0 ;13: Reserved
|
||||
DCD 0 ;14: Reserved
|
||||
DCD ADC0_IRQHandler ;15: ADC 0 interrupt
|
||||
DCD CMP0_IRQHandler ;16: CMP 0 interrupt
|
||||
DCD TPM0_IRQHandler ;17: TPM 0 interrupt
|
||||
DCD TPM1_IRQHandler ;18: TPM 1 interrupt
|
||||
DCD 0 ;19: Reserved
|
||||
DCD RTC_IRQHandler ;20: RTC interrupt
|
||||
DCD RTC_Seconds_IRQHandler ;21: RTC Seconds interrupt
|
||||
DCD PIT_IRQHandler ;22: PIT Single interrupt vector for all channels
|
||||
DCD 0 ;23: Reserved
|
||||
DCD 0 ;24: Reserved
|
||||
DCD DAC0_IRQHandler ;25: UART 0 status intertrupt
|
||||
DCD TSI0_IRQHandler ;26: TSI 0 interrupt
|
||||
DCD MCG_IRQHandler ;27: MCG intertrupt
|
||||
DCD LPTimer_IRQHandler ;28: LPTimer interrupt
|
||||
DCD 0 ;29: Reserved
|
||||
DCD PORTA_IRQHandler ;30: PORT A interrupt
|
||||
DCD PORTB_IRQHandler ;31: PORT B interrupt
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;Flash Configuration
|
||||
;;16-byte flash configuration field that stores default protection settings (loaded on reset)
|
||||
;;and security information that allows the MCU to restrict acces to the FTFL module.
|
||||
|
||||
BackDoorK0 EQU 0xFF
|
||||
BackDoorK1 EQU 0xFF
|
||||
BackDoorK2 EQU 0xFF
|
||||
BackDoorK3 EQU 0xFF
|
||||
BackDoorK4 EQU 0xFF
|
||||
BackDoorK5 EQU 0xFF
|
||||
BackDoorK6 EQU 0xFF
|
||||
BackDoorK7 EQU 0xFF
|
||||
|
||||
nFPROT0 EQU 0x00
|
||||
FPROT0 EQU nFPROT0^0xFF
|
||||
|
||||
nFPROT1 EQU 0x00
|
||||
FPROT1 EQU nFPROT1^0xFF
|
||||
|
||||
nFPROT2 EQU 0x00
|
||||
FPROT2 EQU nFPROT2^0xFF
|
||||
|
||||
nFPROT3 EQU 0x00
|
||||
FPROT3 EQU nFPROT3^0xFF
|
||||
|
||||
FOPT EQU 0xFF
|
||||
|
||||
FSEC EQU 0xFE
|
||||
SECTION FlashConfig:CONST:REORDER:ROOT(2)
|
||||
Config:
|
||||
DATA
|
||||
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
|
||||
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
|
||||
DCB FPROT0, FPROT1, FPROT2, FPROT3
|
||||
DCB FSEC, FOPT, 0xFF, 0xFF
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
PUBWEAK HardFault_Handler
|
||||
PUBWEAK SVC_Handler
|
||||
PUBWEAK PendSV_Handler
|
||||
PUBWEAK SysTick_Handler
|
||||
PUBWEAK DMA0_IRQHandler
|
||||
PUBWEAK DMA1_IRQHandler
|
||||
PUBWEAK DMA2_IRQHandler
|
||||
PUBWEAK DMA3_IRQHandler
|
||||
PUBWEAK FTFA_IRQHandler
|
||||
PUBWEAK LVD_LVW_IRQHandler
|
||||
PUBWEAK LLW_IRQHandler
|
||||
PUBWEAK I2C0_IRQHandler
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
PUBWEAK UART0_IRQHandler
|
||||
PUBWEAK ADC0_IRQHandler
|
||||
PUBWEAK CMP0_IRQHandler
|
||||
PUBWEAK TPM0_IRQHandler
|
||||
PUBWEAK TPM1_IRQHandler
|
||||
PUBWEAK RTC_IRQHandler
|
||||
PUBWEAK RTC_Seconds_IRQHandler
|
||||
PUBWEAK PIT_IRQHandler
|
||||
PUBWEAK DAC0_IRQHandler
|
||||
PUBWEAK TSI0_IRQHandler
|
||||
PUBWEAK MCG_IRQHandler
|
||||
PUBWEAK LPTimer_IRQHandler
|
||||
PUBWEAK PORTA_IRQHandler
|
||||
PUBWEAK PORTB_IRQHandler
|
||||
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
THUMB
|
||||
NMI_Handler
|
||||
HardFault_Handler
|
||||
SVC_Handler
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
DMA0_IRQHandler
|
||||
DMA1_IRQHandler
|
||||
DMA2_IRQHandler
|
||||
DMA3_IRQHandler
|
||||
FTFA_IRQHandler
|
||||
LVD_LVW_IRQHandler
|
||||
LLW_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
UART0_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
CMP0_IRQHandler
|
||||
TPM0_IRQHandler
|
||||
TPM1_IRQHandler
|
||||
RTC_IRQHandler
|
||||
RTC_Seconds_IRQHandler
|
||||
PIT_IRQHandler
|
||||
DAC0_IRQHandler
|
||||
TSI0_IRQHandler
|
||||
MCG_IRQHandler
|
||||
LPTimer_IRQHandler
|
||||
PORTA_IRQHandler
|
||||
PORTB_IRQHandler
|
||||
Default_Handler
|
||||
|
||||
B Default_Handler
|
||||
END
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0001ffff;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x1ffff000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x800;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_RAM2_start__ = 0x20000000;
|
||||
define symbol __region_RAM2_end__ = 0x20002fff;
|
||||
|
||||
define symbol __FlashConfig_start__ = 0x00000400;
|
||||
define symbol __FlashConfig_end__ = 0x0000040f;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in FlashConfig_region {section FlashConfig};
|
||||
|
||||
place in ROM_region { readonly };
|
||||
|
||||
place in RAM_region { readwrite, block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
/**************************************************
|
||||
*
|
||||
* Copyright 2012 IAR Systems. All rights reserved.
|
||||
*
|
||||
* $Revision: 16 $
|
||||
*
|
||||
**************************************************/
|
||||
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:ROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
; External Interrupts
|
||||
DCD DMA0_IRQHandler ; 0: DMA Channel 0 transfer complete intertrupt
|
||||
DCD DMA1_IRQHandler ; 1: DMA Channel 1 transfer complete intertrupt
|
||||
DCD DMA2_IRQHandler ; 2: DMA Channel 2 transfer complete intertrupt
|
||||
DCD DMA3_IRQHandler ; 3: DMA Channel 3 transfer complete intertrupt
|
||||
DCD 0 ; 4: Reserved DMA Channel 5 transfer complete intertrupt
|
||||
DCD FTFA_IRQHandler ; 5: FTFA
|
||||
DCD LVD_LVW_IRQHandler ; 6: Low-voltage detect, low-voltage warning
|
||||
DCD LLW_IRQHandler ; 7: Low Leakage Wakeup
|
||||
DCD I2C0_IRQHandler ; 8: IIC 0 interrupt
|
||||
DCD I2C1_IRQHandler ; 9: IIC 1 intertrupt
|
||||
DCD SPI0_IRQHandler ;10: SPI0 intertrupt
|
||||
DCD SPI1_IRQHandler ;11: SPI1 intertrupt
|
||||
DCD UART0_IRQHandler ;12: UART 0 status and error intertrupt
|
||||
DCD UART1_IRQHandler ;13: UART 1 status and error intertrupt
|
||||
DCD UART2_IRQHandler ;14: UART 2 status and error intertrupt
|
||||
DCD ADC0_IRQHandler ;15: ADC 0 interrupt
|
||||
DCD CMP0_IRQHandler ;16: CMP 0 interrupt
|
||||
DCD TPM0_IRQHandler ;17: TPM 0 interrupt
|
||||
DCD TPM1_IRQHandler ;18: TPM 1 interrupt
|
||||
DCD TPM2_IRQHandler ;19: TPM 2 interrupt
|
||||
DCD RTC_IRQHandler ;20: RTC Alarm interrupt
|
||||
DCD RTC_Seconds_IRQHandler ;21: RTC Seconds interrupt
|
||||
DCD PIT_IRQHandler ;22: PIT Single interrupt vector for all channels
|
||||
DCD 0 ;23: Reserved
|
||||
DCD USB0_IRQHandler ;24: USB OTG intertrupt
|
||||
DCD DAC0_IRQHandler ;25: UART 0 status intertrupt
|
||||
DCD TSI0_IRQHandler ;26: TSI 0 interrupt
|
||||
DCD MCG_IRQHandler ;27: MCG intertrupt
|
||||
DCD LPTimer_IRQHandler ;28: LPTMR0 intertrupt
|
||||
DCD 0 ;29: Reserved
|
||||
DCD PORTA_IRQHandler ;30: PORT A interrupt
|
||||
DCD PORTD_IRQHandler ;31: PORT D interrupt
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;Flash Configuration
|
||||
;;16-byte flash configuration field that stores default protection settings (loaded on reset)
|
||||
;;and security information that allows the MCU to restrict acces to the FTFL module.
|
||||
|
||||
BackDoorK0 EQU 0xFF
|
||||
BackDoorK1 EQU 0xFF
|
||||
BackDoorK2 EQU 0xFF
|
||||
BackDoorK3 EQU 0xFF
|
||||
BackDoorK4 EQU 0xFF
|
||||
BackDoorK5 EQU 0xFF
|
||||
BackDoorK6 EQU 0xFF
|
||||
BackDoorK7 EQU 0xFF
|
||||
|
||||
nFPROT0 EQU 0x00
|
||||
FPROT0 EQU nFPROT0^0xFF
|
||||
|
||||
nFPROT1 EQU 0x00
|
||||
FPROT1 EQU nFPROT1^0xFF
|
||||
|
||||
nFPROT2 EQU 0x00
|
||||
FPROT2 EQU nFPROT2^0xFF
|
||||
|
||||
nFPROT3 EQU 0x00
|
||||
FPROT3 EQU nFPROT3^0xFF
|
||||
|
||||
FOPT EQU 0xFF
|
||||
|
||||
FSEC EQU 0xFE
|
||||
SECTION FlashConfig:CONST:REORDER:ROOT(2)
|
||||
Config:
|
||||
DATA
|
||||
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
|
||||
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
|
||||
DCB FPROT0, FPROT1, FPROT2, FPROT3
|
||||
DCB FSEC, FOPT, 0xFF, 0xFF
|
||||
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
PUBWEAK HardFault_Handler
|
||||
PUBWEAK SVC_Handler
|
||||
PUBWEAK PendSV_Handler
|
||||
PUBWEAK SysTick_Handler
|
||||
PUBWEAK DMA0_IRQHandler
|
||||
PUBWEAK DMA1_IRQHandler
|
||||
PUBWEAK DMA2_IRQHandler
|
||||
PUBWEAK DMA3_IRQHandler
|
||||
PUBWEAK FTFA_IRQHandler
|
||||
PUBWEAK LVD_LVW_IRQHandler
|
||||
PUBWEAK LLW_IRQHandler
|
||||
PUBWEAK I2C0_IRQHandler
|
||||
PUBWEAK I2C1_IRQHandler
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
PUBWEAK UART0_IRQHandler
|
||||
PUBWEAK UART1_IRQHandler
|
||||
PUBWEAK UART2_IRQHandler
|
||||
PUBWEAK ADC0_IRQHandler
|
||||
PUBWEAK CMP0_IRQHandler
|
||||
PUBWEAK TPM0_IRQHandler
|
||||
PUBWEAK TPM1_IRQHandler
|
||||
PUBWEAK TPM2_IRQHandler
|
||||
PUBWEAK RTC_IRQHandler
|
||||
PUBWEAK RTC_Seconds_IRQHandler
|
||||
PUBWEAK PIT_IRQHandler
|
||||
PUBWEAK USB0_IRQHandler
|
||||
PUBWEAK DAC0_IRQHandler
|
||||
PUBWEAK TSI0_IRQHandler
|
||||
PUBWEAK MCG_IRQHandler
|
||||
PUBWEAK LPTimer_IRQHandler
|
||||
PUBWEAK PORTA_IRQHandler
|
||||
PUBWEAK PORTD_IRQHandler
|
||||
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
THUMB
|
||||
NMI_Handler
|
||||
HardFault_Handler
|
||||
SVC_Handler
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
DMA0_IRQHandler
|
||||
DMA1_IRQHandler
|
||||
DMA2_IRQHandler
|
||||
DMA3_IRQHandler
|
||||
FTFA_IRQHandler
|
||||
LVD_LVW_IRQHandler
|
||||
LLW_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
CMP0_IRQHandler
|
||||
TPM0_IRQHandler
|
||||
TPM1_IRQHandler
|
||||
TPM2_IRQHandler
|
||||
RTC_IRQHandler
|
||||
RTC_Seconds_IRQHandler
|
||||
PIT_IRQHandler
|
||||
USB0_IRQHandler
|
||||
DAC0_IRQHandler
|
||||
TSI0_IRQHandler
|
||||
MCG_IRQHandler
|
||||
LPTimer_IRQHandler
|
||||
PORTA_IRQHandler
|
||||
PORTD_IRQHandler
|
||||
Default_Handler
|
||||
|
||||
B Default_Handler
|
||||
END
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0002ffff;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x1fffe000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x800;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x1000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_RAM2_start__ = 0x20000000;
|
||||
define symbol __region_RAM2_end__ = 0x20005fff;
|
||||
|
||||
define symbol __FlashConfig_start__ = 0x00000400;
|
||||
define symbol __FlashConfig_end__ = 0x0000040f;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in FlashConfig_region {section FlashConfig};
|
||||
|
||||
place in ROM_region { readonly };
|
||||
|
||||
place in RAM_region { readwrite, block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
/**************************************************
|
||||
*
|
||||
* Copyright 2010 IAR Systems. All rights reserved.
|
||||
*
|
||||
* $Revision: 16 $
|
||||
*
|
||||
**************************************************/
|
||||
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:ROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
; External Interrupts
|
||||
DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
|
||||
DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
|
||||
DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
|
||||
DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
|
||||
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
|
||||
DCD LLW_IRQHandler ; Low Leakage Wakeup
|
||||
DCD I2C0_IRQHandler ; I2C0 interrupt
|
||||
DCD I2C1_IRQHandler ; I2C0 interrupt 25
|
||||
DCD SPI0_IRQHandler ; SPI0 interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 interrupt
|
||||
DCD UART0_IRQHandler ; UART0 status/error interrupt
|
||||
DCD UART1_IRQHandler ; UART1 status/error interrupt
|
||||
DCD UART2_IRQHandler ; UART2 status/error interrupt
|
||||
DCD ADC0_IRQHandler ; ADC0 interrupt
|
||||
DCD CMP0_IRQHandler ; CMP0 interrupt
|
||||
DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
|
||||
DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
|
||||
DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
|
||||
DCD RTC_IRQHandler ; RTC interrupt
|
||||
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
|
||||
DCD PIT_IRQHandler ; PIT timer interrupt
|
||||
DCD I2S0_IRQHandler ; I2S0 transmit interrupt
|
||||
DCD USB0_IRQHandler ; USB0 interrupt
|
||||
DCD DAC0_IRQHandler ; DAC0 interrupt
|
||||
DCD TSI0_IRQHandler ; TSI0 interrupt
|
||||
DCD MCG_IRQHandler ; MCG interrupt
|
||||
DCD LPTimer_IRQHandler ; LPTimer interrupt
|
||||
DCD LCD_IRQHandler ; Segment LCD Interrupt
|
||||
DCD PORTA_IRQHandler ; Port A interrupt
|
||||
DCD PORTD_IRQHandler ; Port D interrupt
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;Flash Configuration
|
||||
;;16-byte flash configuration field that stores default protection settings (loaded on reset)
|
||||
;;and security information that allows the MCU to restrict acces to the FTFL module.
|
||||
|
||||
BackDoorK0 EQU 0xFF
|
||||
BackDoorK1 EQU 0xFF
|
||||
BackDoorK2 EQU 0xFF
|
||||
BackDoorK3 EQU 0xFF
|
||||
BackDoorK4 EQU 0xFF
|
||||
BackDoorK5 EQU 0xFF
|
||||
BackDoorK6 EQU 0xFF
|
||||
BackDoorK7 EQU 0xFF
|
||||
|
||||
nFPROT0 EQU 0x00
|
||||
FPROT0 EQU nFPROT0^0xFF
|
||||
|
||||
nFPROT1 EQU 0x00
|
||||
FPROT1 EQU nFPROT1^0xFF
|
||||
|
||||
nFPROT2 EQU 0x00
|
||||
FPROT2 EQU nFPROT2^0xFF
|
||||
|
||||
nFPROT3 EQU 0x00
|
||||
FPROT3 EQU nFPROT3^0xFF
|
||||
|
||||
FOPT EQU 0xFF
|
||||
|
||||
FSEC EQU 0xFE
|
||||
SECTION FlashConfig:CONST:REORDER:ROOT(2)
|
||||
Config:
|
||||
DATA
|
||||
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
|
||||
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
|
||||
DCB FPROT0, FPROT1, FPROT2, FPROT3
|
||||
DCB FSEC, FOPT, 0xFF, 0xFF
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
PUBWEAK HardFault_Handler
|
||||
PUBWEAK SVC_Handler
|
||||
PUBWEAK PendSV_Handler
|
||||
PUBWEAK SysTick_Handler
|
||||
PUBWEAK DMA0_IRQHandler
|
||||
PUBWEAK DMA1_IRQHandler
|
||||
PUBWEAK DMA2_IRQHandler
|
||||
PUBWEAK DMA3_IRQHandler
|
||||
PUBWEAK Reserved20_IRQHandler
|
||||
PUBWEAK FTFA_IRQHandler
|
||||
PUBWEAK LVD_LVW_IRQHandler
|
||||
PUBWEAK LLW_IRQHandler
|
||||
PUBWEAK I2C0_IRQHandler
|
||||
PUBWEAK I2C1_IRQHandler
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
PUBWEAK UART0_IRQHandler
|
||||
PUBWEAK UART1_IRQHandler
|
||||
PUBWEAK UART2_IRQHandler
|
||||
PUBWEAK ADC0_IRQHandler
|
||||
PUBWEAK CMP0_IRQHandler
|
||||
PUBWEAK TPM0_IRQHandler
|
||||
PUBWEAK TPM1_IRQHandler
|
||||
PUBWEAK TPM2_IRQHandler
|
||||
PUBWEAK RTC_IRQHandler
|
||||
PUBWEAK RTC_Seconds_IRQHandler
|
||||
PUBWEAK PIT_IRQHandler
|
||||
PUBWEAK I2S0_IRQHandler
|
||||
PUBWEAK USB0_IRQHandler
|
||||
PUBWEAK DAC0_IRQHandler
|
||||
PUBWEAK TSI0_IRQHandler
|
||||
PUBWEAK MCG_IRQHandler
|
||||
PUBWEAK LPTimer_IRQHandler
|
||||
PUBWEAK LCD_IRQHandler
|
||||
PUBWEAK PORTA_IRQHandler
|
||||
PUBWEAK PORTD_IRQHandler
|
||||
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
THUMB
|
||||
NMI_Handler
|
||||
HardFault_Handler
|
||||
SVC_Handler
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
DMA0_IRQHandler
|
||||
DMA1_IRQHandler
|
||||
DMA2_IRQHandler
|
||||
DMA3_IRQHandler
|
||||
Reserved20_IRQHandler
|
||||
FTFA_IRQHandler
|
||||
LVD_LVW_IRQHandler
|
||||
LLW_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
CMP0_IRQHandler
|
||||
TPM0_IRQHandler
|
||||
TPM1_IRQHandler
|
||||
TPM2_IRQHandler
|
||||
RTC_IRQHandler
|
||||
RTC_Seconds_IRQHandler
|
||||
PIT_IRQHandler
|
||||
I2S0_IRQHandler
|
||||
USB0_IRQHandler
|
||||
DAC0_IRQHandler
|
||||
TSI0_IRQHandler
|
||||
MCG_IRQHandler
|
||||
LPTimer_IRQHandler
|
||||
LCD_IRQHandler
|
||||
PORTA_IRQHandler
|
||||
PORTD_IRQHandler
|
||||
Default_Handler
|
||||
|
||||
B Default_Handler
|
||||
END
|
||||
|
|
@ -402,9 +402,9 @@ FEPROT EQU nFEPROT:EOR:0xFF
|
|||
; <0=> Low-power boot
|
||||
; <1=> normal boot
|
||||
; <o.1> EZPORT_DIS
|
||||
; <0=> EzPort operation is enabled
|
||||
; <1=> EzPort operation is disabled
|
||||
FOPT EQU 0xFF
|
||||
; <0=> EzPort operation is disabled
|
||||
; <1=> EzPort operation is enabled
|
||||
FOPT EQU 0xFD
|
||||
; </h>
|
||||
; <h> Flash security byte (FSEC)
|
||||
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
|
||||
|
|
|
|||
|
|
@ -364,6 +364,6 @@ kinetis_flash_config:
|
|||
.long 0xffffffff
|
||||
.long 0xffffffff
|
||||
.long 0xffffffff
|
||||
.long 0xfffffffe
|
||||
.long 0xfffffdfe
|
||||
|
||||
.end
|
||||
|
|
|
|||
|
|
@ -0,0 +1,46 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x000fffff;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x1fff0000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x2000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x4000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_RAM2_start__ = 0x20000000;
|
||||
define symbol __region_RAM2_end__ = 0x2002ffff;
|
||||
|
||||
define symbol __FlashConfig_start__ = 0x00000400;
|
||||
define symbol __FlashConfig_end__ = 0x0000040f;
|
||||
|
||||
define symbol __region_FlexRAM_start__ = 0x14000000;
|
||||
define symbol __region_FlexRAM_end__ = 0x14000fff;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
|
||||
define region FlexRAM_region = mem:[from __region_FlexRAM_start__ to __region_FlexRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in FlashConfig_region {section FlashConfig};
|
||||
|
||||
place in ROM_region { readonly };
|
||||
|
||||
place in RAM_region { readwrite, block CSTACK, block HEAP };
|
||||
|
||||
place in FlexRAM_region { section .flex_ram };
|
||||
|
|
@ -0,0 +1,547 @@
|
|||
/**************************************************
|
||||
*
|
||||
* Copyright 2010 IAR Systems. All rights reserved.
|
||||
*
|
||||
* $Revision: 16 $
|
||||
*
|
||||
**************************************************/
|
||||
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:ROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
; External Interrupts
|
||||
DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
|
||||
DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
|
||||
DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
|
||||
DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
|
||||
DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
|
||||
DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
|
||||
DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
|
||||
DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
|
||||
DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
|
||||
DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
|
||||
DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
|
||||
DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
|
||||
DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
|
||||
DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
|
||||
DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
|
||||
DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
|
||||
DCD DMA_Error_IRQHandler ; DMA Error Interrupt
|
||||
DCD MCM_IRQHandler ; Normal Interrupt
|
||||
DCD FTFE_IRQHandler ; FTFE Command complete interrupt
|
||||
DCD Read_Collision_IRQHandler ; Read Collision Interrupt
|
||||
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
|
||||
DCD LLW_IRQHandler ; Low Leakage Wakeup
|
||||
DCD Watchdog_IRQHandler ; WDOG Interrupt
|
||||
DCD RNG_IRQHandler ; RNG Interrupt
|
||||
DCD I2C0_IRQHandler ; I2C0 interrupt
|
||||
DCD I2C1_IRQHandler ; I2C1 interrupt
|
||||
DCD SPI0_IRQHandler ; SPI0 Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
|
||||
DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
|
||||
DCD UART0_LON_IRQHandler ; UART0 LON interrupt
|
||||
DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
|
||||
DCD UART0_ERR_IRQHandler ; UART0 Error interrupt
|
||||
DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
|
||||
DCD UART1_ERR_IRQHandler ; UART1 Error interrupt
|
||||
DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
|
||||
DCD UART2_ERR_IRQHandler ; UART2 Error interrupt
|
||||
DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
|
||||
DCD UART3_ERR_IRQHandler ; UART3 Error interrupt
|
||||
DCD ADC0_IRQHandler ; ADC0 interrupt
|
||||
DCD CMP0_IRQHandler ; CMP0 interrupt
|
||||
DCD CMP1_IRQHandler ; CMP1 interrupt
|
||||
DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
|
||||
DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
|
||||
DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
|
||||
DCD CMT_IRQHandler ; CMT interrupt
|
||||
DCD RTC_IRQHandler ; RTC interrupt
|
||||
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
|
||||
DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
|
||||
DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
|
||||
DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
|
||||
DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
|
||||
DCD PDB0_IRQHandler ; PDB0 Interrupt
|
||||
DCD USB0_IRQHandler ; USB0 interrupt
|
||||
DCD USBDCD_IRQHandler ; USBDCD Interrupt
|
||||
DCD Reserved71_IRQHandler ; Reserved interrupt 71
|
||||
DCD DAC0_IRQHandler ; DAC0 interrupt
|
||||
DCD MCG_IRQHandler ; MCG Interrupt
|
||||
DCD LPTimer_IRQHandler ; LPTimer interrupt
|
||||
DCD PORTA_IRQHandler ; Port A interrupt
|
||||
DCD PORTB_IRQHandler ; Port B interrupt
|
||||
DCD PORTC_IRQHandler ; Port C interrupt
|
||||
DCD PORTD_IRQHandler ; Port D interrupt
|
||||
DCD PORTE_IRQHandler ; Port E interrupt
|
||||
DCD SWI_IRQHandler ; Software interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
|
||||
DCD UART4_ERR_IRQHandler ; UART4 Error interrupt
|
||||
DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
|
||||
DCD UART5_ERR_IRQHandler ; UART5 Error interrupt
|
||||
DCD CMP2_IRQHandler ; CMP2 interrupt
|
||||
DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt
|
||||
DCD DAC1_IRQHandler ; DAC1 interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 interrupt
|
||||
DCD I2C2_IRQHandler ; I2C2 interrupt
|
||||
DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
|
||||
DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
|
||||
DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
|
||||
DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
|
||||
DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
|
||||
DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
|
||||
DCD SDHC_IRQHandler ; SDHC interrupt
|
||||
DCD ENET_1588_Timer_IRQHandler ; Ethernet MAC IEEE 1588 Timer Interrupt
|
||||
DCD ENET_Transmit_IRQHandler ; Ethernet MAC Transmit Interrupt
|
||||
DCD ENET_Receive_IRQHandler ; Ethernet MAC Receive Interrupt
|
||||
DCD ENET_Error_IRQHandler ; Ethernet MAC Error and miscelaneous Interrupt
|
||||
DCD Default_Handler ; 102
|
||||
DCD Default_Handler ; 103
|
||||
DCD Default_Handler ; 104
|
||||
DCD Default_Handler ; 105
|
||||
DCD Default_Handler ; 106
|
||||
DCD Default_Handler ; 107
|
||||
DCD Default_Handler ; 108
|
||||
DCD Default_Handler ; 109
|
||||
DCD Default_Handler ; 110
|
||||
DCD Default_Handler ; 111
|
||||
DCD Default_Handler ; 112
|
||||
DCD Default_Handler ; 113
|
||||
DCD Default_Handler ; 114
|
||||
DCD Default_Handler ; 115
|
||||
DCD Default_Handler ; 116
|
||||
DCD Default_Handler ; 117
|
||||
DCD Default_Handler ; 118
|
||||
DCD Default_Handler ; 119
|
||||
DCD Default_Handler ; 120
|
||||
DCD Default_Handler ; 121
|
||||
DCD Default_Handler ; 122
|
||||
DCD Default_Handler ; 123
|
||||
DCD Default_Handler ; 124
|
||||
DCD Default_Handler ; 125
|
||||
DCD Default_Handler ; 126
|
||||
DCD Default_Handler ; 127
|
||||
DCD Default_Handler ; 128
|
||||
DCD Default_Handler ; 129
|
||||
DCD Default_Handler ; 130
|
||||
DCD Default_Handler ; 131
|
||||
DCD Default_Handler ; 132
|
||||
DCD Default_Handler ; 133
|
||||
DCD Default_Handler ; 134
|
||||
DCD Default_Handler ; 135
|
||||
DCD Default_Handler ; 136
|
||||
DCD Default_Handler ; 137
|
||||
DCD Default_Handler ; 138
|
||||
DCD Default_Handler ; 139
|
||||
DCD Default_Handler ; 140
|
||||
DCD Default_Handler ; 141
|
||||
DCD Default_Handler ; 142
|
||||
DCD Default_Handler ; 143
|
||||
DCD Default_Handler ; 144
|
||||
DCD Default_Handler ; 145
|
||||
DCD Default_Handler ; 146
|
||||
DCD Default_Handler ; 147
|
||||
DCD Default_Handler ; 148
|
||||
DCD Default_Handler ; 149
|
||||
DCD Default_Handler ; 150
|
||||
DCD Default_Handler ; 151
|
||||
DCD Default_Handler ; 152
|
||||
DCD Default_Handler ; 153
|
||||
DCD Default_Handler ; 154
|
||||
DCD Default_Handler ; 155
|
||||
DCD Default_Handler ; 156
|
||||
DCD Default_Handler ; 157
|
||||
DCD Default_Handler ; 158
|
||||
DCD Default_Handler ; 159
|
||||
DCD Default_Handler ; 160
|
||||
DCD Default_Handler ; 161
|
||||
DCD Default_Handler ; 162
|
||||
DCD Default_Handler ; 163
|
||||
DCD Default_Handler ; 164
|
||||
DCD Default_Handler ; 165
|
||||
DCD Default_Handler ; 166
|
||||
DCD Default_Handler ; 167
|
||||
DCD Default_Handler ; 168
|
||||
DCD Default_Handler ; 169
|
||||
DCD Default_Handler ; 170
|
||||
DCD Default_Handler ; 171
|
||||
DCD Default_Handler ; 172
|
||||
DCD Default_Handler ; 173
|
||||
DCD Default_Handler ; 174
|
||||
DCD Default_Handler ; 175
|
||||
DCD Default_Handler ; 176
|
||||
DCD Default_Handler ; 177
|
||||
DCD Default_Handler ; 178
|
||||
DCD Default_Handler ; 179
|
||||
DCD Default_Handler ; 180
|
||||
DCD Default_Handler ; 181
|
||||
DCD Default_Handler ; 182
|
||||
DCD Default_Handler ; 183
|
||||
DCD Default_Handler ; 184
|
||||
DCD Default_Handler ; 185
|
||||
DCD Default_Handler ; 186
|
||||
DCD Default_Handler ; 187
|
||||
DCD Default_Handler ; 188
|
||||
DCD Default_Handler ; 189
|
||||
DCD Default_Handler ; 190
|
||||
DCD Default_Handler ; 191
|
||||
DCD Default_Handler ; 192
|
||||
DCD Default_Handler ; 193
|
||||
DCD Default_Handler ; 194
|
||||
DCD Default_Handler ; 195
|
||||
DCD Default_Handler ; 196
|
||||
DCD Default_Handler ; 197
|
||||
DCD Default_Handler ; 198
|
||||
DCD Default_Handler ; 199
|
||||
DCD Default_Handler ; 200
|
||||
DCD Default_Handler ; 201
|
||||
DCD Default_Handler ; 202
|
||||
DCD Default_Handler ; 203
|
||||
DCD Default_Handler ; 204
|
||||
DCD Default_Handler ; 205
|
||||
DCD Default_Handler ; 206
|
||||
DCD Default_Handler ; 207
|
||||
DCD Default_Handler ; 208
|
||||
DCD Default_Handler ; 209
|
||||
DCD Default_Handler ; 210
|
||||
DCD Default_Handler ; 211
|
||||
DCD Default_Handler ; 212
|
||||
DCD Default_Handler ; 213
|
||||
DCD Default_Handler ; 214
|
||||
DCD Default_Handler ; 215
|
||||
DCD Default_Handler ; 216
|
||||
DCD Default_Handler ; 217
|
||||
DCD Default_Handler ; 218
|
||||
DCD Default_Handler ; 219
|
||||
DCD Default_Handler ; 220
|
||||
DCD Default_Handler ; 221
|
||||
DCD Default_Handler ; 222
|
||||
DCD Default_Handler ; 223
|
||||
DCD Default_Handler ; 224
|
||||
DCD Default_Handler ; 225
|
||||
DCD Default_Handler ; 226
|
||||
DCD Default_Handler ; 227
|
||||
DCD Default_Handler ; 228
|
||||
DCD Default_Handler ; 229
|
||||
DCD Default_Handler ; 230
|
||||
DCD Default_Handler ; 231
|
||||
DCD Default_Handler ; 232
|
||||
DCD Default_Handler ; 233
|
||||
DCD Default_Handler ; 234
|
||||
DCD Default_Handler ; 235
|
||||
DCD Default_Handler ; 236
|
||||
DCD Default_Handler ; 237
|
||||
DCD Default_Handler ; 238
|
||||
DCD Default_Handler ; 239
|
||||
DCD Default_Handler ; 240
|
||||
DCD Default_Handler ; 241
|
||||
DCD Default_Handler ; 242
|
||||
DCD Default_Handler ; 243
|
||||
DCD Default_Handler ; 244
|
||||
DCD Default_Handler ; 245
|
||||
DCD Default_Handler ; 246
|
||||
DCD Default_Handler ; 247
|
||||
DCD Default_Handler ; 248
|
||||
DCD Default_Handler ; 249
|
||||
DCD Default_Handler ; 250
|
||||
DCD Default_Handler ; 251
|
||||
DCD Default_Handler ; 252
|
||||
DCD Default_Handler ; 253
|
||||
DCD Default_Handler ; 254
|
||||
DCD Default_Handler ; 255
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;Flash Configuration
|
||||
;;16-byte flash configuration field that stores default protection settings (loaded on reset)
|
||||
;;and security information that allows the MCU to restrict acces to the FTFL module.
|
||||
|
||||
BackDoorK0 EQU 0xFF
|
||||
BackDoorK1 EQU 0xFF
|
||||
BackDoorK2 EQU 0xFF
|
||||
BackDoorK3 EQU 0xFF
|
||||
BackDoorK4 EQU 0xFF
|
||||
BackDoorK5 EQU 0xFF
|
||||
BackDoorK6 EQU 0xFF
|
||||
BackDoorK7 EQU 0xFF
|
||||
|
||||
nFPROT0 EQU 0x00
|
||||
FPROT0 EQU nFPROT0^0xFF
|
||||
|
||||
nFPROT1 EQU 0x00
|
||||
FPROT1 EQU nFPROT1^0xFF
|
||||
|
||||
nFPROT2 EQU 0x00
|
||||
FPROT2 EQU nFPROT2^0xFF
|
||||
|
||||
nFPROT3 EQU 0x00
|
||||
FPROT3 EQU nFPROT3^0xFF
|
||||
|
||||
nFEPROT EQU 0x00
|
||||
FEPROT EQU nFEPROT^0xFF
|
||||
|
||||
nFDPROT EQU 0x00
|
||||
FDPROT EQU nFDPROT^0xFF
|
||||
|
||||
FOPT EQU 0xFD
|
||||
|
||||
FSEC EQU 0xFE
|
||||
SECTION FlashConfig:CONST:REORDER:ROOT(2)
|
||||
Config:
|
||||
DATA
|
||||
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
|
||||
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
|
||||
DCB FPROT0, FPROT1, FPROT2, FPROT3
|
||||
DCB FSEC, FOPT, FEPROT, FDPROT
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
PUBWEAK HardFault_Handler
|
||||
PUBWEAK MemManage_Handler
|
||||
PUBWEAK BusFault_Handler
|
||||
PUBWEAK UsageFault_Handler
|
||||
PUBWEAK SVC_Handler
|
||||
PUBWEAK DebugMon_Handler
|
||||
PUBWEAK PendSV_Handler
|
||||
PUBWEAK SysTick_Handler
|
||||
PUBWEAK DMA0_IRQHandler
|
||||
PUBWEAK DMA1_IRQHandler
|
||||
PUBWEAK DMA2_IRQHandler
|
||||
PUBWEAK DMA3_IRQHandler
|
||||
PUBWEAK DMA4_IRQHandler
|
||||
PUBWEAK DMA5_IRQHandler
|
||||
PUBWEAK DMA6_IRQHandler
|
||||
PUBWEAK DMA7_IRQHandler
|
||||
PUBWEAK DMA8_IRQHandler
|
||||
PUBWEAK DMA9_IRQHandler
|
||||
PUBWEAK DMA10_IRQHandler
|
||||
PUBWEAK DMA11_IRQHandler
|
||||
PUBWEAK DMA12_IRQHandler
|
||||
PUBWEAK DMA13_IRQHandler
|
||||
PUBWEAK DMA14_IRQHandler
|
||||
PUBWEAK DMA15_IRQHandler
|
||||
PUBWEAK DMA_Error_IRQHandler
|
||||
PUBWEAK MCM_IRQHandler
|
||||
PUBWEAK FTFE_IRQHandler
|
||||
PUBWEAK Read_Collision_IRQHandler
|
||||
PUBWEAK LVD_LVW_IRQHandler
|
||||
PUBWEAK LLW_IRQHandler
|
||||
PUBWEAK Watchdog_IRQHandler
|
||||
PUBWEAK RNG_IRQHandler
|
||||
PUBWEAK I2C0_IRQHandler
|
||||
PUBWEAK I2C1_IRQHandler
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
PUBWEAK I2S0_Tx_IRQHandler
|
||||
PUBWEAK I2S0_Rx_IRQHandler
|
||||
PUBWEAK UART0_LON_IRQHandler
|
||||
PUBWEAK UART0_RX_TX_IRQHandler
|
||||
PUBWEAK UART0_ERR_IRQHandler
|
||||
PUBWEAK UART1_RX_TX_IRQHandler
|
||||
PUBWEAK UART1_ERR_IRQHandler
|
||||
PUBWEAK UART2_RX_TX_IRQHandler
|
||||
PUBWEAK UART2_ERR_IRQHandler
|
||||
PUBWEAK UART3_RX_TX_IRQHandler
|
||||
PUBWEAK UART3_ERR_IRQHandler
|
||||
PUBWEAK ADC0_IRQHandler
|
||||
PUBWEAK CMP0_IRQHandler
|
||||
PUBWEAK CMP1_IRQHandler
|
||||
PUBWEAK FTM0_IRQHandler
|
||||
PUBWEAK FTM1_IRQHandler
|
||||
PUBWEAK FTM2_IRQHandler
|
||||
PUBWEAK CMT_IRQHandler
|
||||
PUBWEAK RTC_IRQHandler
|
||||
PUBWEAK RTC_Seconds_IRQHandler
|
||||
PUBWEAK PIT0_IRQHandler
|
||||
PUBWEAK PIT1_IRQHandler
|
||||
PUBWEAK PIT2_IRQHandler
|
||||
PUBWEAK PIT3_IRQHandler
|
||||
PUBWEAK PDB0_IRQHandler
|
||||
PUBWEAK USB0_IRQHandler
|
||||
PUBWEAK USBDCD_IRQHandler
|
||||
PUBWEAK Reserved71_IRQHandler
|
||||
PUBWEAK DAC0_IRQHandler
|
||||
PUBWEAK MCG_IRQHandler
|
||||
PUBWEAK LPTimer_IRQHandler
|
||||
PUBWEAK PORTA_IRQHandler
|
||||
PUBWEAK PORTB_IRQHandler
|
||||
PUBWEAK PORTC_IRQHandler
|
||||
PUBWEAK PORTD_IRQHandler
|
||||
PUBWEAK PORTE_IRQHandler
|
||||
PUBWEAK SWI_IRQHandler
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
PUBWEAK UART4_RX_TX_IRQHandler
|
||||
PUBWEAK UART4_ERR_IRQHandler
|
||||
PUBWEAK UART5_RX_TX_IRQHandler
|
||||
PUBWEAK UART5_ERR_IRQHandler
|
||||
PUBWEAK CMP2_IRQHandler
|
||||
PUBWEAK FTM3_IRQHandler
|
||||
PUBWEAK DAC1_IRQHandler
|
||||
PUBWEAK ADC1_IRQHandler
|
||||
PUBWEAK I2C2_IRQHandler
|
||||
PUBWEAK CAN0_ORed_Message_buffer_IRQHandler
|
||||
PUBWEAK CAN0_Bus_Off_IRQHandler
|
||||
PUBWEAK CAN0_Error_IRQHandler
|
||||
PUBWEAK CAN0_Tx_Warning_IRQHandler
|
||||
PUBWEAK CAN0_Rx_Warning_IRQHandler
|
||||
PUBWEAK CAN0_Wake_Up_IRQHandler
|
||||
PUBWEAK SDHC_IRQHandler
|
||||
PUBWEAK ENET_1588_Timer_IRQHandler
|
||||
PUBWEAK ENET_Transmit_IRQHandler
|
||||
PUBWEAK ENET_Receive_IRQHandler
|
||||
PUBWEAK ENET_Error_IRQHandler
|
||||
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
THUMB
|
||||
NMI_Handler
|
||||
HardFault_Handler
|
||||
MemManage_Handler
|
||||
BusFault_Handler
|
||||
UsageFault_Handler
|
||||
SVC_Handler
|
||||
DebugMon_Handler
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
DMA0_IRQHandler
|
||||
DMA1_IRQHandler
|
||||
DMA2_IRQHandler
|
||||
DMA3_IRQHandler
|
||||
DMA4_IRQHandler
|
||||
DMA5_IRQHandler
|
||||
DMA6_IRQHandler
|
||||
DMA7_IRQHandler
|
||||
DMA8_IRQHandler
|
||||
DMA9_IRQHandler
|
||||
DMA10_IRQHandler
|
||||
DMA11_IRQHandler
|
||||
DMA12_IRQHandler
|
||||
DMA13_IRQHandler
|
||||
DMA14_IRQHandler
|
||||
DMA15_IRQHandler
|
||||
DMA_Error_IRQHandler
|
||||
MCM_IRQHandler
|
||||
FTFE_IRQHandler
|
||||
Read_Collision_IRQHandler
|
||||
LVD_LVW_IRQHandler
|
||||
LLW_IRQHandler
|
||||
Watchdog_IRQHandler
|
||||
RNG_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
I2S0_Tx_IRQHandler
|
||||
I2S0_Rx_IRQHandler
|
||||
UART0_LON_IRQHandler
|
||||
UART0_RX_TX_IRQHandler
|
||||
UART0_ERR_IRQHandler
|
||||
UART1_RX_TX_IRQHandler
|
||||
UART1_ERR_IRQHandler
|
||||
UART2_RX_TX_IRQHandler
|
||||
UART2_ERR_IRQHandler
|
||||
UART3_RX_TX_IRQHandler
|
||||
UART3_ERR_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
CMP0_IRQHandler
|
||||
CMP1_IRQHandler
|
||||
FTM0_IRQHandler
|
||||
FTM1_IRQHandler
|
||||
FTM2_IRQHandler
|
||||
CMT_IRQHandler
|
||||
RTC_IRQHandler
|
||||
RTC_Seconds_IRQHandler
|
||||
PIT0_IRQHandler
|
||||
PIT1_IRQHandler
|
||||
PIT2_IRQHandler
|
||||
PIT3_IRQHandler
|
||||
PDB0_IRQHandler
|
||||
USB0_IRQHandler
|
||||
USBDCD_IRQHandler
|
||||
Reserved71_IRQHandler
|
||||
DAC0_IRQHandler
|
||||
MCG_IRQHandler
|
||||
LPTimer_IRQHandler
|
||||
PORTA_IRQHandler
|
||||
PORTB_IRQHandler
|
||||
PORTC_IRQHandler
|
||||
PORTD_IRQHandler
|
||||
PORTE_IRQHandler
|
||||
SWI_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
UART4_RX_TX_IRQHandler
|
||||
UART4_ERR_IRQHandler
|
||||
UART5_RX_TX_IRQHandler
|
||||
UART5_ERR_IRQHandler
|
||||
CMP2_IRQHandler
|
||||
FTM3_IRQHandler
|
||||
DAC1_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
I2C2_IRQHandler
|
||||
CAN0_ORed_Message_buffer_IRQHandler
|
||||
CAN0_Bus_Off_IRQHandler
|
||||
CAN0_Error_IRQHandler
|
||||
CAN0_Tx_Warning_IRQHandler
|
||||
CAN0_Rx_Warning_IRQHandler
|
||||
CAN0_Wake_Up_IRQHandler
|
||||
SDHC_IRQHandler
|
||||
ENET_1588_Timer_IRQHandler
|
||||
ENET_Transmit_IRQHandler
|
||||
ENET_Receive_IRQHandler
|
||||
ENET_Error_IRQHandler
|
||||
Default_Handler
|
||||
|
||||
B Default_Handler
|
||||
END
|
||||
|
|
@ -25,7 +25,7 @@ Stack_Size EQU 0x00000400
|
|||
EXPORT __initial_sp
|
||||
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
|
||||
__initial_sp EQU 0x10001800 ; Top of RAM from LPC11U
|
||||
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@
|
|||
; *
|
||||
; *****************************************************************************/
|
||||
|
||||
__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
|
||||
__initial_sp EQU 0x10001800 ; Top of RAM from LPC11U
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,407 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_conf_template.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief HAL configuration template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32f4xx_hal_conf.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_HAL_CONF_H
|
||||
#define __STM32F4xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
#define HAL_ADC_MODULE_ENABLED
|
||||
#define HAL_CAN_MODULE_ENABLED
|
||||
#define HAL_CRC_MODULE_ENABLED
|
||||
#define HAL_CRYP_MODULE_ENABLED
|
||||
#define HAL_DAC_MODULE_ENABLED
|
||||
#define HAL_DCMI_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_DMA2D_MODULE_ENABLED
|
||||
#define HAL_ETH_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_NAND_MODULE_ENABLED
|
||||
#define HAL_NOR_MODULE_ENABLED
|
||||
#define HAL_PCCARD_MODULE_ENABLED
|
||||
#define HAL_SRAM_MODULE_ENABLED
|
||||
#define HAL_SDRAM_MODULE_ENABLED
|
||||
#define HAL_HASH_MODULE_ENABLED
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
#define HAL_I2S_MODULE_ENABLED
|
||||
#define HAL_IWDG_MODULE_ENABLED
|
||||
#define HAL_LTDC_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_RNG_MODULE_ENABLED
|
||||
#define HAL_RTC_MODULE_ENABLED
|
||||
#define HAL_SAI_MODULE_ENABLED
|
||||
#define HAL_SD_MODULE_ENABLED
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
#define HAL_USART_MODULE_ENABLED
|
||||
#define HAL_IRDA_MODULE_ENABLED
|
||||
#define HAL_SMARTCARD_MODULE_ENABLED
|
||||
#define HAL_WWDG_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
#define HAL_PCD_MODULE_ENABLED
|
||||
#define HAL_HCD_MODULE_ENABLED
|
||||
|
||||
|
||||
/* ########################## HSE/HSI Values adaptation ##################### */
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE ((uint32_t)40000)
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature. */
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
/**
|
||||
* @brief External clock source for I2S peripheral
|
||||
* This value is used by the I2S HAL module to compute the I2S clock source
|
||||
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||
*/
|
||||
#if !defined (EXTERNAL_CLOCK_VALUE)
|
||||
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0
|
||||
#define PREFETCH_ENABLE 1
|
||||
#define INSTRUCTION_CACHE_ENABLE 1
|
||||
#define DATA_CACHE_ENABLE 1
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
||||
/* ################## Ethernet peripheral configuration ##################### */
|
||||
|
||||
/* Section 1 : Ethernet peripheral configuration */
|
||||
|
||||
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
|
||||
#define MAC_ADDR0 2
|
||||
#define MAC_ADDR1 0
|
||||
#define MAC_ADDR2 0
|
||||
#define MAC_ADDR3 0
|
||||
#define MAC_ADDR4 0
|
||||
#define MAC_ADDR5 0
|
||||
|
||||
/* Definition of the Ethernet driver buffers size and count */
|
||||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
|
||||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
|
||||
#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||
#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||
|
||||
/* Section 2: PHY configuration section */
|
||||
|
||||
/* DP83848 PHY Address*/
|
||||
#define DP83848_PHY_ADDRESS 0x01
|
||||
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
|
||||
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
|
||||
/* PHY Configuration delay */
|
||||
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
|
||||
|
||||
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
|
||||
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
|
||||
|
||||
/* Section 3: Common PHY Registers */
|
||||
|
||||
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
|
||||
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
|
||||
|
||||
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
|
||||
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
|
||||
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
|
||||
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
|
||||
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
|
||||
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
|
||||
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
|
||||
|
||||
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
|
||||
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
|
||||
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
|
||||
|
||||
/* Section 4: Extended PHY Registers */
|
||||
|
||||
#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
|
||||
#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
|
||||
#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
|
||||
|
||||
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
|
||||
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
|
||||
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
|
||||
|
||||
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
|
||||
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
|
||||
|
||||
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
|
||||
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CAN_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_can.h"
|
||||
#endif /* HAL_CAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA2D_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_dma2d.h"
|
||||
#endif /* HAL_DMA2D_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_dac.h"
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DCMI_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_dcmi.h"
|
||||
#endif /* HAL_DCMI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ETH_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_eth.h"
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCCARD_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_pccard.h"
|
||||
#endif /* HAL_PCCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_sdram.h"
|
||||
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HASH_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_hash.h"
|
||||
#endif /* HAL_HASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LTDC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_ltdc.h"
|
||||
#endif /* HAL_LTDC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_rng.h"
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SAI_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_sai.h"
|
||||
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_HAL_CONF_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,339 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_crc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief CRC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The CRC HAL driver can be used as follows:
|
||||
|
||||
(#) Enable CRC AHB clock using __CRC_CLK_ENABLE();
|
||||
|
||||
(#) Use HAL_CRC_Accumulate() function to compute the CRC value of
|
||||
a 32-bit data buffer using combination of the previous CRC value
|
||||
and the new one.
|
||||
|
||||
(#) Use HAL_CRC_Calculate() function to compute the CRC Value of
|
||||
a new 32-bit data buffer. This function resets the CRC computation
|
||||
unit before starting the computation to avoid getting wrong CRC values.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC
|
||||
* @brief CRC HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the CRC according to the specified parameters
|
||||
in the CRC_InitTypeDef and create the associated handle
|
||||
(+) DeInitialize the CRC peripheral
|
||||
(+) Initialize the CRC MSP
|
||||
(+) DeInitialize CRC MSP
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the CRC according to the specified
|
||||
* parameters in the CRC_InitTypeDef and creates the associated handle.
|
||||
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||
* the configuration information for CRC
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Check the CRC handle allocation */
|
||||
if(hcrc == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
||||
|
||||
if(hcrc->State == HAL_CRC_STATE_RESET)
|
||||
{
|
||||
/* Init the low level hardware */
|
||||
HAL_CRC_MspInit(hcrc);
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the CRC peripheral.
|
||||
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||
* the configuration information for CRC
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Check the CRC handle allocation */
|
||||
if(hcrc == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_CRC_MspDeInit(hcrc);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hcrc);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the CRC MSP.
|
||||
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||
* the configuration information for CRC
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_CRC_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the CRC MSP.
|
||||
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||
* the configuration information for CRC
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_CRC_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Group2 Peripheral Control functions
|
||||
* @brief management functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Compute the 32-bit CRC value of 32-bit data buffer,
|
||||
using combination of the previous CRC value and the new one.
|
||||
(+) Compute the 32-bit CRC value of 32-bit data buffer,
|
||||
independently of the previous CRC value.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of 32-bit data buffer using combination
|
||||
* of the previous CRC value and the new one.
|
||||
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||
* the configuration information for CRC
|
||||
* @param pBuffer: pointer to the buffer containing the data to be computed
|
||||
* @param BufferLength: length of the buffer to be computed
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hcrc);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* Enter Data to the CRC calculator */
|
||||
for(index = 0; index < BufferLength; index++)
|
||||
{
|
||||
hcrc->Instance->DR = pBuffer[index];
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hcrc);
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return hcrc->Instance->DR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of 32-bit data buffer independently
|
||||
* of the previous CRC value.
|
||||
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||
* the configuration information for CRC
|
||||
* @param pBuffer: Pointer to the buffer containing the data to be computed
|
||||
* @param BufferLength: Length of the buffer to be computed
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hcrc);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* Reset CRC Calculation Unit */
|
||||
__HAL_CRC_DR_RESET(hcrc);
|
||||
|
||||
/* Enter Data to the CRC calculator */
|
||||
for(index = 0; index < BufferLength; index++)
|
||||
{
|
||||
hcrc->Instance->DR = pBuffer[index];
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hcrc);
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return hcrc->Instance->DR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral State functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the peripheral
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the CRC state.
|
||||
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||
* the configuration information for CRC
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
return hcrc->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,940 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_dac.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief DAC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Digital to Analog Converter (DAC) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State and Errors functions
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### DAC Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
*** DAC Channels ***
|
||||
====================
|
||||
[..]
|
||||
The device integrates two 12-bit Digital Analog Converters that can
|
||||
be used independently or simultaneously (dual mode):
|
||||
(#) DAC channel1 with DAC_OUT1 (PA4) as output
|
||||
(#) DAC channel2 with DAC_OUT2 (PA5) as output
|
||||
|
||||
*** DAC Triggers ***
|
||||
====================
|
||||
[..]
|
||||
Digital to Analog conversion can be non-triggered using DAC_Trigger_None
|
||||
and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
|
||||
[..]
|
||||
Digital to Analog conversion can be triggered by:
|
||||
(#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
|
||||
The used pin (GPIOx_Pin9) must be configured in input mode.
|
||||
|
||||
(#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
|
||||
(DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
|
||||
|
||||
(#) Software using DAC_Trigger_Software
|
||||
|
||||
*** DAC Buffer mode feature ***
|
||||
===============================
|
||||
[..]
|
||||
Each DAC channel integrates an output buffer that can be used to
|
||||
reduce the output impedance, and to drive external loads directly
|
||||
without having to add an external operational amplifier.
|
||||
To enable, the output buffer use
|
||||
sConfig.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
||||
[..]
|
||||
(@) Refer to the device datasheet for more details about output
|
||||
impedance value with and without output buffer.
|
||||
|
||||
*** DAC wave generation feature ***
|
||||
===================================
|
||||
[..]
|
||||
Both DAC channels can be used to generate
|
||||
(#) Noise wave
|
||||
(#) Triangle wave
|
||||
|
||||
*** DAC data format ***
|
||||
=======================
|
||||
[..]
|
||||
The DAC data format can be:
|
||||
(#) 8-bit right alignment using DAC_ALIGN_8B_R
|
||||
(#) 12-bit left alignment using DAC_ALIGN_12B_L
|
||||
(#) 12-bit right alignment using DAC_ALIGN_12B_R
|
||||
|
||||
*** DAC data value to voltage correspondence ***
|
||||
================================================
|
||||
[..]
|
||||
The analog output voltage on each DAC channel pin is determined
|
||||
by the following equation:
|
||||
DAC_OUTx = VREF+ * DOR / 4095
|
||||
with DOR is the Data Output Register
|
||||
VEF+ is the input voltage reference (refer to the device datasheet)
|
||||
e.g. To set DAC_OUT1 to 0.7V, use
|
||||
Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
|
||||
|
||||
*** DMA requests ***
|
||||
=====================
|
||||
[..]
|
||||
A DMA1 request can be generated when an external trigger (but not
|
||||
a software trigger) occurs if DMA1 requests are enabled using
|
||||
HAL_DAC_Start_DMA()
|
||||
[..]
|
||||
DMA1 requests are mapped as following:
|
||||
(#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be
|
||||
already configured
|
||||
(#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be
|
||||
already configured
|
||||
|
||||
-@- For Dual mode and specific signal (Triangle and noise) generation please
|
||||
refer to Extension Features Driver description
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) DAC APB clock must be enabled to get write access to DAC
|
||||
registers using HAL_DAC_Init()
|
||||
(+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
|
||||
(+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
|
||||
(+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
|
||||
|
||||
*** Polling mode IO operation ***
|
||||
=================================
|
||||
[..]
|
||||
(+) Start the DAC peripheral using HAL_DAC_Start()
|
||||
(+) To read the DAC last data output value value, use the HAL_DAC_GetValue() function.
|
||||
(+) Stop the DAC peripheral using HAL_DAC_Stop()
|
||||
|
||||
*** DMA mode IO operation ***
|
||||
==============================
|
||||
[..]
|
||||
(+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
|
||||
of data to be transferred at each end of conversion
|
||||
(+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
|
||||
function is executed and user can add his own code by customization of function pointer
|
||||
HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
|
||||
(+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
|
||||
add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
|
||||
(+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
|
||||
|
||||
*** DAC HAL driver macros list ***
|
||||
=============================================
|
||||
[..]
|
||||
Below the list of most used macros in DAC HAL driver.
|
||||
|
||||
(+) __HAL_DAC_ENABLE : Enable the DAC peripheral
|
||||
(+) __HAL_DAC_DISABLE : Disable the DAC peripheral
|
||||
(+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
|
||||
(+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
|
||||
|
||||
[..]
|
||||
(@) You can refer to the DAC HAL driver header file for more useful macros
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC
|
||||
* @brief DAC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
|
||||
static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize and configure the DAC.
|
||||
(+) De-initialize the DAC.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the DAC peripheral according to the specified parameters
|
||||
* in the DAC_InitStruct.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Check DAC handle */
|
||||
if(hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
|
||||
|
||||
if(hdac->State == HAL_DAC_STATE_RESET)
|
||||
{
|
||||
/* Init the low level hardware */
|
||||
HAL_DAC_MspInit(hdac);
|
||||
}
|
||||
|
||||
/* Initialize the DAC state*/
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Set DAC error code to none */
|
||||
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
|
||||
|
||||
/* Initialize the DAC state*/
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DAC peripheral registers to their default reset values.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Check DAC handle */
|
||||
if(hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_DAC_MspDeInit(hdac);
|
||||
|
||||
/* Set DAC error code to none */
|
||||
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DAC MSP.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the DAC MSP.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### IO operation functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Start conversion.
|
||||
(+) Stop conversion.
|
||||
(+) Start conversion and enable DMA transfer.
|
||||
(+) Stop conversion and disable DMA transfer.
|
||||
(+) Get result of conversion.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables DAC and starts conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
|
||||
{
|
||||
uint32_t tmp1 = 0, tmp2 = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Enable the Peripharal */
|
||||
__HAL_DAC_ENABLE(hdac, Channel);
|
||||
|
||||
if(Channel == DAC_CHANNEL_1)
|
||||
{
|
||||
tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
|
||||
tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
|
||||
/* Check if software trigger enabled */
|
||||
if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1))
|
||||
{
|
||||
/* Enable the selected DAC software conversion */
|
||||
hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
|
||||
tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;
|
||||
/* Check if software trigger enabled */
|
||||
if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
|
||||
{
|
||||
/* Enable the selected DAC software conversion*/
|
||||
hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;
|
||||
}
|
||||
}
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables DAC and stop conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_DAC_DISABLE(hdac, Channel);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables DAC and starts conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @param pData: The destination peripheral Buffer address.
|
||||
* @param Length: The length of data to be transferred from memory to DAC peripheral
|
||||
* @param Alignment: Specifies the data alignment for DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
|
||||
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
|
||||
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
assert_param(IS_DAC_ALIGN(Alignment));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
if(Channel == DAC_CHANNEL_1)
|
||||
{
|
||||
/* Set the DMA transfer complete callback for channel1 */
|
||||
hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
|
||||
|
||||
/* Set the DMA half transfer complete callback for channel1 */
|
||||
hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
|
||||
|
||||
/* Set the DMA error callback for channel1 */
|
||||
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
|
||||
|
||||
/* Enable the selected DAC channel1 DMA request */
|
||||
hdac->Instance->CR |= DAC_CR_DMAEN1;
|
||||
|
||||
/* Case of use of channel 1 */
|
||||
switch(Alignment)
|
||||
{
|
||||
case DAC_ALIGN_12B_R:
|
||||
/* Get DHR12R1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
|
||||
break;
|
||||
case DAC_ALIGN_12B_L:
|
||||
/* Get DHR12L1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
|
||||
break;
|
||||
case DAC_ALIGN_8B_R:
|
||||
/* Get DHR8R1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the DMA transfer complete callback for channel2 */
|
||||
hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
|
||||
|
||||
/* Set the DMA half transfer complete callback for channel2 */
|
||||
hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
|
||||
|
||||
/* Set the DMA error callback for channel2 */
|
||||
hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
|
||||
|
||||
/* Enable the selected DAC channel2 DMA request */
|
||||
hdac->Instance->CR |= DAC_CR_DMAEN2;
|
||||
|
||||
/* Case of use of channel 2 */
|
||||
switch(Alignment)
|
||||
{
|
||||
case DAC_ALIGN_12B_R:
|
||||
/* Get DHR12R2 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
|
||||
break;
|
||||
case DAC_ALIGN_12B_L:
|
||||
/* Get DHR12L2 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
|
||||
break;
|
||||
case DAC_ALIGN_8B_R:
|
||||
/* Get DHR8R2 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable the DMA Stream */
|
||||
if(Channel == DAC_CHANNEL_1)
|
||||
{
|
||||
/* Enable the DAC DMA underrun interrupt */
|
||||
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
|
||||
|
||||
/* Enable the DMA Stream */
|
||||
HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enable the DAC DMA underrun interrupt */
|
||||
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
|
||||
|
||||
/* Enable the DMA Stream */
|
||||
HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
|
||||
}
|
||||
|
||||
/* Enable the Peripharal */
|
||||
__HAL_DAC_ENABLE(hdac, Channel);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables DAC and stop conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
||||
/* Disable the selected DAC channel DMA request */
|
||||
hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
|
||||
|
||||
/* Disable the Peripharal */
|
||||
__HAL_DAC_DISABLE(hdac, Channel);
|
||||
|
||||
/* Disable the DMA Channel */
|
||||
/* Channel1 is used */
|
||||
if(Channel == DAC_CHANNEL_1)
|
||||
{
|
||||
status = HAL_DMA_Abort(hdac->DMA_Handle1);
|
||||
}
|
||||
else /* Channel2 is used for */
|
||||
{
|
||||
status = HAL_DMA_Abort(hdac->DMA_Handle2);
|
||||
}
|
||||
|
||||
/* Check if DMA Channel effectively disabled */
|
||||
if(status == HAL_ERROR)
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
hdac->State = HAL_DAC_STATE_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
if(Channel == DAC_CHANNEL_1)
|
||||
{
|
||||
return hdac->Instance->DOR1;
|
||||
}
|
||||
else
|
||||
{
|
||||
return hdac->Instance->DOR2;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handles DAC interrupt request
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Check Overrun flag */
|
||||
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
|
||||
{
|
||||
/* Change DAC state to error state */
|
||||
hdac->State = HAL_DAC_STATE_ERROR;
|
||||
|
||||
/* Set DAC error code to chanel1 DMA underrun error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
|
||||
|
||||
/* Clear the underrun flag */
|
||||
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
|
||||
|
||||
/* Disable the selected DAC channel1 DMA request */
|
||||
hdac->Instance->CR &= ~DAC_CR_DMAEN1;
|
||||
|
||||
/* Error callback */
|
||||
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Change DAC state to error state */
|
||||
hdac->State = HAL_DAC_STATE_ERROR;
|
||||
|
||||
/* Set DAC error code to channel2 DMA underrun error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
|
||||
|
||||
/* Clear the underrun flag */
|
||||
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
|
||||
|
||||
/* Disable the selected DAC channel1 DMA request */
|
||||
hdac->Instance->CR &= ~DAC_CR_DMAEN2;
|
||||
|
||||
/* Error callback */
|
||||
HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Conversion complete callback in non blocking mode for Channel1
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ConvCpltCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Conversion half DMA transfer callback in non blocking mode for Channel1
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Error DAC callback for Channel1.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA underrun DAC callback for channel1.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group3 Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure channels.
|
||||
(+) Set the specified data holding register value for DAC channel.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param sConfig: DAC configuration structure.
|
||||
* @param Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
|
||||
{
|
||||
uint32_t tmpreg1 = 0, tmpreg2 = 0;
|
||||
|
||||
/* Check the DAC parameters */
|
||||
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
|
||||
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Get the DAC CR value */
|
||||
tmpreg1 = DAC->CR;
|
||||
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
|
||||
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
|
||||
/* Configure for the selected DAC channel: buffer output, trigger */
|
||||
/* Set TSELx and TENx bits according to DAC_Trigger value */
|
||||
/* Set BOFFx bit according to DAC_OutputBuffer value */
|
||||
tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
|
||||
/* Calculate CR register value depending on DAC_Channel */
|
||||
tmpreg1 |= tmpreg2 << Channel;
|
||||
/* Write to DAC CR */
|
||||
DAC->CR = tmpreg1;
|
||||
/* Disable wave generation */
|
||||
DAC->CR &= ~(DAC_CR_WAVE1 << Channel);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @param Alignment: Specifies the data alignment.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
|
||||
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
|
||||
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
|
||||
* @param Data: Data to be loaded in the selected data holding register.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
assert_param(IS_DAC_ALIGN(Alignment));
|
||||
assert_param(IS_DAC_DATA(Data));
|
||||
|
||||
tmp = (uint32_t)hdac->Instance;
|
||||
if(Channel == DAC_CHANNEL_1)
|
||||
{
|
||||
tmp += __HAL_DHR12R1_ALIGNEMENT(Alignment);
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp += __HAL_DHR12R2_ALIGNEMENT(Alignment);
|
||||
}
|
||||
|
||||
/* Set the DAC channel1 selected data holding register */
|
||||
*(__IO uint32_t *) tmp = Data;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group4 Peripheral State and Errors functions
|
||||
* @brief Peripheral State and Errors functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral State and Errors functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides functions allowing to
|
||||
(+) Check the DAC state.
|
||||
(+) Check the DAC Errors.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief return the DAC state
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Return DAC state */
|
||||
return hdac->State;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Return the DAC error code
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval DAC Error Code
|
||||
*/
|
||||
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
return hdac->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA conversion complete callback.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA module.
|
||||
* @retval None
|
||||
*/
|
||||
static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
HAL_DAC_ConvCpltCallbackCh1(hdac);
|
||||
|
||||
hdac->State= HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA half transfer complete callback.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA module.
|
||||
* @retval None
|
||||
*/
|
||||
static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
/* Conversion complete callback */
|
||||
HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA error callback
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA module.
|
||||
* @retval None
|
||||
*/
|
||||
static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
/* Set DAC error code to DMA error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
|
||||
|
||||
HAL_DAC_ErrorCallbackCh1(hdac);
|
||||
|
||||
hdac->State= HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,818 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_dcmi.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief DCMI HAL module driver
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Digital Camera Interface (DCMI) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State and Error functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The sequence below describes how to use this driver to capture image
|
||||
from a camera module connected to the DCMI Interface.
|
||||
This sequence does not take into account the configuration of the
|
||||
camera module, which should be made before to configure and enable
|
||||
the DCMI to capture images.
|
||||
|
||||
(#) Program the required configuration through following parameters:
|
||||
horizontal and vertical polarity, pixel clock polarity, Capture Rate,
|
||||
Synchronization Mode, code of the frame delimiter and data width
|
||||
using HAL_DCMI_Init() function.
|
||||
|
||||
(#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
|
||||
register to the destination memory buffer.
|
||||
|
||||
(#) Program the required configuration through following parameters:
|
||||
DCMI mode, destination memory Buffer address and the data length
|
||||
and enable capture using HAL_DCMI_Start_DMA() function.
|
||||
|
||||
(#) Optionally, configure and Enable the CROP feature to select a rectangular
|
||||
window from the received image using HAL_DCMI_ConfigCrop()
|
||||
and HAL_DCMI_EnableCROP() functions
|
||||
|
||||
(#) The capture can be stopped using HAL_DCMI_Stop() function.
|
||||
|
||||
(#) To control DCMI state you can use the function HAL_DCMI_GetState().
|
||||
|
||||
*** DCMI HAL driver macros list ***
|
||||
=============================================
|
||||
[..]
|
||||
Below the list of most used macros in DCMI HAL driver.
|
||||
|
||||
(+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
|
||||
(+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
|
||||
(+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
|
||||
(+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
|
||||
(+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
|
||||
(+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
|
||||
(+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.
|
||||
|
||||
[..]
|
||||
(@) You can refer to the DCMI HAL driver header file for more useful macros
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup DCMI
|
||||
* @brief DCMI HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DCMI_MODULE_ENABLED
|
||||
|
||||
#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* 1s */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma);
|
||||
static void DCMI_DMAError(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DCMI_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize and configure the DCMI
|
||||
(+) De-initialize the DCMI
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the DCMI according to the specified
|
||||
* parameters in the DCMI_InitTypeDef and create the associated handle.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
/* Check the DCMI peripheral state */
|
||||
if(hdcmi == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check function parameters */
|
||||
assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
|
||||
assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
|
||||
assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
|
||||
assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
|
||||
assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
|
||||
assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
|
||||
assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
|
||||
assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
|
||||
|
||||
if(hdcmi->State == HAL_DCMI_STATE_RESET)
|
||||
{
|
||||
/* Init the low level hardware */
|
||||
HAL_DCMI_MspInit(hdcmi);
|
||||
}
|
||||
|
||||
/* Change the DCMI state */
|
||||
hdcmi->State = HAL_DCMI_STATE_BUSY;
|
||||
|
||||
/* Configures the HS, VS, DE and PC polarity */
|
||||
hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |
|
||||
DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |
|
||||
DCMI_CR_ESS);
|
||||
hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \
|
||||
hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity | \
|
||||
hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \
|
||||
hdcmi->Init.JPEGMode);
|
||||
|
||||
if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
|
||||
{
|
||||
DCMI->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |
|
||||
((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8)|
|
||||
((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16) |
|
||||
((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24));
|
||||
}
|
||||
|
||||
/* Enable the Line interrupt */
|
||||
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE);
|
||||
|
||||
/* Enable the VSYNC interrupt */
|
||||
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_VSYNC);
|
||||
|
||||
/* Enable the Frame capture complete interrupt */
|
||||
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
|
||||
|
||||
/* Enable the Synchronization error interrupt */
|
||||
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_ERR);
|
||||
|
||||
/* Enable the Overflow interrupt */
|
||||
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_OVF);
|
||||
|
||||
/* Enable DCMI by setting DCMIEN bit */
|
||||
__HAL_DCMI_ENABLE(hdcmi);
|
||||
|
||||
/* Update error code */
|
||||
hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
|
||||
|
||||
/* Initialize the DCMI state*/
|
||||
hdcmi->State = HAL_DCMI_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DCMI peripheral registers to their default reset
|
||||
* values.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
/* DeInit the low level hardware */
|
||||
HAL_DCMI_MspDeInit(hdcmi);
|
||||
|
||||
/* Update error code */
|
||||
hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
|
||||
|
||||
/* Initialize the DCMI state*/
|
||||
hdcmi->State = HAL_DCMI_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DCMI MSP.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DCMI_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the DCMI MSP.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DCMI_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup DCMI_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure destination address and data length and
|
||||
Enables DCMI DMA request and enables DCMI capture
|
||||
(+) Stop the DCMI capture.
|
||||
(+) Handles DCMI interrupt request.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables DCMI DMA request and enables DCMI capture
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @param DCMI_Mode: DCMI capture mode snapshot or continuous grab.
|
||||
* @param pData: The destination memory Buffer address (LCD Frame buffer).
|
||||
* @param Length: The length of capture to be transferred.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
|
||||
{
|
||||
/* Initialise the second memory address */
|
||||
uint32_t SecondMemAddress = 0;
|
||||
|
||||
/* Check function parameters */
|
||||
assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hdcmi);
|
||||
|
||||
/* Lock the DCMI peripheral state */
|
||||
hdcmi->State = HAL_DCMI_STATE_BUSY;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
|
||||
|
||||
/* Configure the DCMI Mode */
|
||||
hdcmi->Instance->CR &= ~(DCMI_CR_CM);
|
||||
hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);
|
||||
|
||||
/* Set the DMA memory0 conversion complete callback */
|
||||
hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAConvCplt;
|
||||
|
||||
/* Set the DMA error callback */
|
||||
hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
|
||||
|
||||
if(Length <= 0xFFFF)
|
||||
{
|
||||
/* Enable the DMA Stream */
|
||||
HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);
|
||||
}
|
||||
else /* DCMI_DOUBLE_BUFFER Mode */
|
||||
{
|
||||
/* Set the DMA memory1 conversion complete callback */
|
||||
hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAConvCplt;
|
||||
|
||||
/* Initialise transfer parameters */
|
||||
hdcmi->XferCount = 1;
|
||||
hdcmi->XferSize = Length;
|
||||
hdcmi->pBuffPtr = pData;
|
||||
|
||||
/* Get the number of buffer */
|
||||
while(hdcmi->XferSize > 0xFFFF)
|
||||
{
|
||||
hdcmi->XferSize = (hdcmi->XferSize/2);
|
||||
hdcmi->XferCount = hdcmi->XferCount*2;
|
||||
}
|
||||
|
||||
/* Update DCMI counter and transfer number*/
|
||||
hdcmi->XferCount = (hdcmi->XferCount - 2);
|
||||
hdcmi->XferTransferNumber = hdcmi->XferCount;
|
||||
|
||||
/* Update second memory address */
|
||||
SecondMemAddress = (uint32_t)(pData + (4*hdcmi->XferSize));
|
||||
|
||||
/* Start DMA multi buffer transfer */
|
||||
HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);
|
||||
}
|
||||
|
||||
/* Enable Capture */
|
||||
DCMI->CR |= DCMI_CR_CAPTURE;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable DCMI DMA request and Disable DCMI capture
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
|
||||
/* Lock the DCMI peripheral state */
|
||||
hdcmi->State = HAL_DCMI_STATE_BUSY;
|
||||
|
||||
__HAL_DCMI_DISABLE(hdcmi);
|
||||
|
||||
/* Disable Capture */
|
||||
DCMI->CR &= ~(DCMI_CR_CAPTURE);
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Check if the DCMI capture effectively disabled */
|
||||
while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DCMI_STOP)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
/* Update error code */
|
||||
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
|
||||
|
||||
/* Change DCMI state */
|
||||
hdcmi->State = HAL_DCMI_STATE_TIMEOUT;
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable the DMA */
|
||||
HAL_DMA_Abort(hdcmi->DMA_Handle);
|
||||
|
||||
/* Update error code */
|
||||
hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;
|
||||
|
||||
/* Change DCMI state */
|
||||
hdcmi->State = HAL_DCMI_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handles DCMI interrupt request.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for the DCMI.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
/* Synchronization error interrupt management *******************************/
|
||||
if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_ERRRI) != RESET)
|
||||
{
|
||||
if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_ERR) != RESET)
|
||||
{
|
||||
/* Disable the Synchronization error interrupt */
|
||||
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_ERR);
|
||||
|
||||
/* Clear the Synchronization error flag */
|
||||
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
|
||||
|
||||
/* Update error code */
|
||||
hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
|
||||
|
||||
/* Change DCMI state */
|
||||
hdcmi->State = HAL_DCMI_STATE_ERROR;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
/* Abort the DMA Transfer */
|
||||
HAL_DMA_Abort(hdcmi->DMA_Handle);
|
||||
|
||||
/* Synchronization error Callback */
|
||||
HAL_DCMI_ErrorCallback(hdcmi);
|
||||
}
|
||||
}
|
||||
/* Overflow interrupt management ********************************************/
|
||||
if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_OVFRI) != RESET)
|
||||
{
|
||||
if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_OVF) != RESET)
|
||||
{
|
||||
/* Disable the Overflow interrupt */
|
||||
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_OVF);
|
||||
|
||||
/* Clear the Overflow flag */
|
||||
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVFRI);
|
||||
|
||||
/* Update error code */
|
||||
hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVF;
|
||||
|
||||
/* Change DCMI state */
|
||||
hdcmi->State = HAL_DCMI_STATE_ERROR;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
/* Abort the DMA Transfer */
|
||||
HAL_DMA_Abort(hdcmi->DMA_Handle);
|
||||
|
||||
/* Overflow Callback */
|
||||
HAL_DCMI_ErrorCallback(hdcmi);
|
||||
}
|
||||
}
|
||||
/* Line Interrupt management ************************************************/
|
||||
if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_LINERI) != RESET)
|
||||
{
|
||||
if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_LINE) != RESET)
|
||||
{
|
||||
/* Clear the Line interrupt flag */
|
||||
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
/* Line interrupt Callback */
|
||||
HAL_DCMI_LineEventCallback(hdcmi);
|
||||
}
|
||||
}
|
||||
/* VSYNC interrupt management ***********************************************/
|
||||
if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_VSYNCRI) != RESET)
|
||||
{
|
||||
if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_VSYNC) != RESET)
|
||||
{
|
||||
/* Disable the VSYNC interrupt */
|
||||
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_VSYNC);
|
||||
|
||||
/* Clear the VSYNC flag */
|
||||
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
/* VSYNC Callback */
|
||||
HAL_DCMI_VsyncEventCallback(hdcmi);
|
||||
}
|
||||
}
|
||||
/* End of Frame interrupt management ****************************************/
|
||||
if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET)
|
||||
{
|
||||
if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_FRAME) != RESET)
|
||||
{
|
||||
/* Disable the End of Frame interrupt */
|
||||
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
|
||||
|
||||
/* Clear the End of Frame flag */
|
||||
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
/* End of Frame Callback */
|
||||
HAL_DCMI_FrameEventCallback(hdcmi);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Error DCMI callback.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DCMI_ErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Line Event callback.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DCMI_LineEventCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief VSYNC Event callback.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DCMI_VsyncEventCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Frame Event callback.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DCMI_FrameEventCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Group3 Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure the CROP feature.
|
||||
(+) Enable/Disable the CROP feature.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure the DCMI CROP coordinate.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @param YSize: DCMI Line number
|
||||
* @param XSize: DCMI Pixel per line
|
||||
* @param X0: DCMI window X offset
|
||||
* @param Y0: DCMI window Y offset
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hdcmi);
|
||||
|
||||
/* Lock the DCMI peripheral state */
|
||||
hdcmi->State = HAL_DCMI_STATE_BUSY;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DCMI_WINDOW_COORDINATE(X0));
|
||||
assert_param(IS_DCMI_WINDOW_COORDINATE(Y0));
|
||||
assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
|
||||
assert_param(IS_DCMI_WINDOW_HEIGHT(YSize));
|
||||
|
||||
/* Configure CROP */
|
||||
DCMI->CWSIZER = (XSize | (YSize << 16));
|
||||
DCMI->CWSTRTR = (X0 | (Y0 << 16));
|
||||
|
||||
/* Initialize the DCMI state*/
|
||||
hdcmi->State = HAL_DCMI_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Crop feature.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hdcmi);
|
||||
|
||||
/* Lock the DCMI peripheral state */
|
||||
hdcmi->State = HAL_DCMI_STATE_BUSY;
|
||||
|
||||
/* Disable DCMI Crop feature */
|
||||
DCMI->CR &= ~(uint32_t)DCMI_CR_CROP;
|
||||
|
||||
/* Change the DCMI state*/
|
||||
hdcmi->State = HAL_DCMI_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Crop feature.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hdcmi);
|
||||
|
||||
/* Lock the DCMI peripheral state */
|
||||
hdcmi->State = HAL_DCMI_STATE_BUSY;
|
||||
|
||||
/* Enable DCMI Crop feature */
|
||||
DCMI->CR |= (uint32_t)DCMI_CR_CROP;
|
||||
|
||||
/* Change the DCMI state*/
|
||||
hdcmi->State = HAL_DCMI_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Group4 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State and Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides functions allowing to
|
||||
(+) Check the DCMI state.
|
||||
(+) Get the specific DCMI error flag.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the DCMI state
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
return hdcmi->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the DCMI error code
|
||||
* @param hdcmi : pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval DCMI Error Code
|
||||
*/
|
||||
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
return hdcmi->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA conversion complete callback.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA module.
|
||||
* @retval None
|
||||
*/
|
||||
static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
hdcmi->State= HAL_DCMI_STATE_READY;
|
||||
|
||||
if(hdcmi->XferCount != 0)
|
||||
{
|
||||
/* Update memory 0 address location */
|
||||
tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT);
|
||||
if(((hdcmi->XferCount % 2) == 0) && (tmp != 0))
|
||||
{
|
||||
tmp = hdcmi->DMA_Handle->Instance->M0AR;
|
||||
HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY0);
|
||||
hdcmi->XferCount--;
|
||||
}
|
||||
/* Update memory 1 address location */
|
||||
else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
|
||||
{
|
||||
tmp = hdcmi->DMA_Handle->Instance->M1AR;
|
||||
HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY1);
|
||||
hdcmi->XferCount--;
|
||||
}
|
||||
}
|
||||
/* Update memory 0 address location */
|
||||
else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0)
|
||||
{
|
||||
hdcmi->DMA_Handle->Instance->M0AR = hdcmi->pBuffPtr;
|
||||
}
|
||||
/* Update memory 1 address location */
|
||||
else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
|
||||
{
|
||||
tmp = hdcmi->pBuffPtr;
|
||||
hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4*hdcmi->XferSize));
|
||||
hdcmi->XferCount = hdcmi->XferTransferNumber;
|
||||
}
|
||||
|
||||
if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
/* FRAME Callback */
|
||||
HAL_DCMI_FrameEventCallback(hdcmi);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA error callback
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA module.
|
||||
* @retval None
|
||||
*/
|
||||
static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
hdcmi->State= HAL_DCMI_STATE_READY;
|
||||
HAL_DCMI_ErrorCallback(hdcmi);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
#endif /* HAL_DCMI_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,198 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_HAL_DEF
|
||||
#define __STM32F4xx_HAL_DEF
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_OK = 0x00,
|
||||
HAL_ERROR = 0x01,
|
||||
HAL_BUSY = 0x02,
|
||||
HAL_TIMEOUT = 0x03
|
||||
} HAL_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_UNLOCKED = 0x00,
|
||||
HAL_LOCKED = 0x01
|
||||
} HAL_LockTypeDef;
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifndef NULL
|
||||
#define NULL (void *) 0
|
||||
#endif
|
||||
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFF
|
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
|
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
|
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__: specifies the Peripheral Handle.
|
||||
* @note This macro can be used for the following purpose:
|
||||
* - When the Handle is declared as local variable; before passing it as parameter
|
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||
* to set to 0 the Handle's "State" field.
|
||||
* Otherwise, "State" field may have any random value and the first time the function
|
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
|
||||
* (i.e. HAL_PPP_MspInit() will not be executed).
|
||||
* - When there is a need to reconfigure the low level hardware: instead of calling
|
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
|
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
|
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
|
||||
|
||||
#if (USE_RTOS == 1)
|
||||
/* Reserved for future use */
|
||||
#error “USE_RTOS should be 0 in the current HAL release”
|
||||
#else
|
||||
#define __HAL_LOCK(__HANDLE__) \
|
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0)
|
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((__packed__))
|
||||
#endif /* __packed */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||
#if defined (__GNUC__) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#else
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#if defined (__CC_ARM) /* ARM Compiler */
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __CC_ARM */
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/**
|
||||
* @brief __RAM_FUNC definition
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
/* ARM Compiler
|
||||
------------
|
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM.
|
||||
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
|
||||
dialog.
|
||||
*/
|
||||
#define __RAM_FUNC HAL_StatusTypeDef
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
*/
|
||||
#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
/* GNU Compiler
|
||||
------------
|
||||
RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".RamFunc")))".
|
||||
*/
|
||||
#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ___STM32F4xx_HAL_DEF */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,910 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_dma.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief DMA HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Direct Memory Access (DMA) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
* + Peripheral State and errors functions
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable and configure the peripheral to be connected to the DMA Stream
|
||||
(except for internal SRAM/FLASH memories: no initialization is
|
||||
necessary) please refer to Reference manual for connection between peripherals
|
||||
and DMA requests .
|
||||
|
||||
(#) For a given Stream, program the required configuration through the following parameters:
|
||||
Transfer Direction, Source and Destination data formats,
|
||||
Circular, Normal or peripheral flow control mode, Stream Priority level,
|
||||
Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
|
||||
Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
|
||||
|
||||
*** Polling mode IO operation ***
|
||||
=================================
|
||||
[..]
|
||||
(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
|
||||
address and destination address and the Length of data to be transferred
|
||||
(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
|
||||
case a fixed Timeout can be configured by User depending from his application.
|
||||
|
||||
*** Interrupt mode IO operation ***
|
||||
===================================
|
||||
[..]
|
||||
(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
|
||||
(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
|
||||
(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
|
||||
Source address and destination address and the Length of data to be transferred. In this
|
||||
case the DMA interrupt is configured
|
||||
(+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
|
||||
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
|
||||
add his own function by customization of function pointer XferCpltCallback and
|
||||
XferErrorCallback (i.e a member of DMA handle structure).
|
||||
[..]
|
||||
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
|
||||
detection.
|
||||
|
||||
(#) Use HAL_DMA_Abort() function to abort the current transfer
|
||||
|
||||
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
|
||||
|
||||
-@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
|
||||
possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
|
||||
Half-Word data size for the peripheral to access its data register and set Word data size
|
||||
for the Memory to gain in access time. Each two half words will be packed and written in
|
||||
a single access to a Word in the Memory).
|
||||
|
||||
-@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
|
||||
and Destination. In this case the Peripheral Data Size will be applied to both Source
|
||||
and Destination.
|
||||
|
||||
*** DMA HAL driver macros list ***
|
||||
=============================================
|
||||
[..]
|
||||
Below the list of most used macros in DMA HAL driver.
|
||||
|
||||
(+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
|
||||
(+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
|
||||
(+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
|
||||
(+) __HAL_DMA_GET_FLAG: Get the DMA Stream pending flags.
|
||||
(+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Stream pending flags.
|
||||
(+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
|
||||
(+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
|
||||
(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
|
||||
|
||||
[..]
|
||||
(@) You can refer to the DMA HAL driver header file for more useful macros
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA
|
||||
* @brief DMA HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to initialize the DMA Stream source
|
||||
and destination addresses, incrementation and data sizes, transfer direction,
|
||||
circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
|
||||
[..]
|
||||
The HAL_DMA_Init() function follows the DMA configuration procedures as described in
|
||||
reference manual.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the DMA according to the specified
|
||||
* parameters in the DMA_InitTypeDef and create the associated handle.
|
||||
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
/* Check the DMA peripheral state */
|
||||
if(hdma == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
|
||||
assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
|
||||
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
|
||||
assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
|
||||
assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
|
||||
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
|
||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
|
||||
assert_param(IS_DMA_MODE(hdma->Init.Mode));
|
||||
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
|
||||
assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
|
||||
/* Check the memory burst, peripheral burst and FIFO threshold parameters only
|
||||
when FIFO mode is enabled */
|
||||
if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
|
||||
{
|
||||
assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
|
||||
assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
|
||||
assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
|
||||
}
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Get the CR register value */
|
||||
tmp = hdma->Instance->CR;
|
||||
|
||||
/* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and CT bits */
|
||||
tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
|
||||
DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
|
||||
DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
|
||||
DMA_SxCR_DIR | DMA_SxCR_CT ));
|
||||
|
||||
/* Prepare the DMA Stream configuration */
|
||||
tmp |= hdma->Init.Channel | hdma->Init.Direction |
|
||||
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
||||
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
||||
hdma->Init.Mode | hdma->Init.Priority;
|
||||
|
||||
/* the Memory burst and peripheral burst are not used when the FIFO is disabled */
|
||||
if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
|
||||
{
|
||||
/* Get memory burst and peripheral burst */
|
||||
tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
|
||||
}
|
||||
|
||||
/* Write to DMA Stream CR register */
|
||||
hdma->Instance->CR = tmp;
|
||||
|
||||
/* Get the FCR register value */
|
||||
tmp = hdma->Instance->FCR;
|
||||
|
||||
/* Clear Direct mode and FIFO threshold bits */
|
||||
tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
|
||||
|
||||
/* Prepare the DMA Stream FIFO configuration */
|
||||
tmp |= hdma->Init.FIFOMode;
|
||||
|
||||
/* the FIFO threshold is not used when the FIFO mode is disabled */
|
||||
if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
|
||||
{
|
||||
/* Get the FIFO threshold */
|
||||
tmp |= hdma->Init.FIFOThreshold;
|
||||
}
|
||||
|
||||
/* Write to DMA Stream FCR */
|
||||
hdma->Instance->FCR = tmp;
|
||||
|
||||
/* Initialise the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Initialize the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the DMA peripheral
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Check the DMA peripheral state */
|
||||
if(hdma == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the DMA peripheral state */
|
||||
if(hdma->State == HAL_DMA_STATE_BUSY)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Disable the selected DMA Streamx */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Reset DMA Streamx control register */
|
||||
hdma->Instance->CR = 0;
|
||||
|
||||
/* Reset DMA Streamx number of data to transfer register */
|
||||
hdma->Instance->NDTR = 0;
|
||||
|
||||
/* Reset DMA Streamx peripheral address register */
|
||||
hdma->Instance->PAR = 0;
|
||||
|
||||
/* Reset DMA Streamx memory 0 address register */
|
||||
hdma->Instance->M0AR = 0;
|
||||
|
||||
/* Reset DMA Streamx memory 1 address register */
|
||||
hdma->Instance->M1AR = 0;
|
||||
|
||||
/* Reset DMA Streamx FIFO control register */
|
||||
hdma->Instance->FCR = (uint32_t)0x00000021;
|
||||
|
||||
/* Clear all flags */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
|
||||
|
||||
/* Initialise the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Initialize the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group2 I/O operation functions
|
||||
* @brief I/O operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure the source, destination address and data length and Start DMA transfer
|
||||
(+) Configure the source, destination address and data length and
|
||||
Start DMA transfer with interrupt
|
||||
(+) Abort DMA transfer
|
||||
(+) Poll for transfer complete
|
||||
(+) Handle DMA interrupt request
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Starts the DMA Transfer.
|
||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param SrcAddress: The source memory Buffer address
|
||||
* @param DstAddress: The destination memory Buffer address
|
||||
* @param DataLength: The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Disable the peripheral */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_DMA_ENABLE(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start the DMA Transfer with interrupt enabled.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param SrcAddress: The source memory Buffer address
|
||||
* @param DstAddress: The destination memory Buffer address
|
||||
* @param DataLength: The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Disable the peripheral */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Enable the transfer complete interrupt */
|
||||
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
|
||||
|
||||
/* Enable the Half transfer complete interrupt */
|
||||
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
|
||||
|
||||
/* Enable the transfer Error interrupt */
|
||||
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
|
||||
|
||||
/* Enable the FIFO Error interrupt */
|
||||
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE);
|
||||
|
||||
/* Enable the direct mode Error interrupt */
|
||||
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_DMA_ENABLE(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Aborts the DMA Transfer.
|
||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
*
|
||||
* @note After disabling a DMA Stream, a check for wait until the DMA Stream is
|
||||
* effectively disabled is added. If a Stream is disabled
|
||||
* while a data transfer is ongoing, the current data will be transferred
|
||||
* and the Stream will be effectively disabled only after the transfer of
|
||||
* this single data is finished.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
|
||||
/* Disable the stream */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Check if the DMA Stream is effectively disabled */
|
||||
while((hdma->Instance->CR & DMA_SxCR_EN) != 0)
|
||||
{
|
||||
/* Check for the Timeout */
|
||||
if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
|
||||
{
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_TIMEOUT;
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Change the DMA state*/
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Polling for transfer complete.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param CompleteLevel: Specifies the DMA level complete.
|
||||
* @param Timeout: Timeout duration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
|
||||
{
|
||||
uint32_t temp, tmp, tmp1, tmp2;
|
||||
uint32_t tickstart = 0;
|
||||
|
||||
/* Get the level transfer complete flag */
|
||||
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
|
||||
{
|
||||
/* Transfer Complete flag */
|
||||
temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Half Transfer Complete flag */
|
||||
temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
|
||||
}
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
|
||||
{
|
||||
tmp = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
|
||||
tmp1 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
|
||||
tmp2 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
|
||||
if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET))
|
||||
{
|
||||
if(tmp != RESET)
|
||||
{
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_TE;
|
||||
|
||||
/* Clear the transfer error flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
|
||||
}
|
||||
if(tmp1 != RESET)
|
||||
{
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_FE;
|
||||
|
||||
/* Clear the FIFO error flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
|
||||
}
|
||||
if(tmp2 != RESET)
|
||||
{
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_DME;
|
||||
|
||||
/* Clear the Direct Mode error flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
|
||||
}
|
||||
/* Change the DMA state */
|
||||
hdma->State= HAL_DMA_STATE_ERROR;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check for the Timeout */
|
||||
if(Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
|
||||
{
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_TIMEOUT;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
|
||||
{
|
||||
/* Multi_Buffering mode enabled */
|
||||
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
|
||||
{
|
||||
/* Clear the half transfer complete flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
|
||||
/* Clear the transfer complete flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
|
||||
|
||||
/* Current memory buffer used is Memory 0 */
|
||||
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_READY_MEM0;
|
||||
}
|
||||
/* Current memory buffer used is Memory 1 */
|
||||
else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_READY_MEM1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the half transfer complete flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
|
||||
/* Clear the transfer complete flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
|
||||
|
||||
/* The selected Streamx EN bit is cleared (DMA is disabled and all transfers
|
||||
are complete) */
|
||||
hdma->State = HAL_DMA_STATE_READY_MEM0;
|
||||
}
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Multi_Buffering mode enabled */
|
||||
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
|
||||
{
|
||||
/* Clear the half transfer complete flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
|
||||
|
||||
/* Current memory buffer used is Memory 0 */
|
||||
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
|
||||
}
|
||||
/* Current memory buffer used is Memory 1 */
|
||||
else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the half transfer complete flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
|
||||
}
|
||||
}
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handles DMA interrupt request.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Transfer Error Interrupt management ***************************************/
|
||||
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
|
||||
{
|
||||
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
|
||||
{
|
||||
/* Disable the transfer error interrupt */
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
|
||||
|
||||
/* Clear the transfer error flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_TE;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_ERROR;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if(hdma->XferErrorCallback != NULL)
|
||||
{
|
||||
/* Transfer error callback */
|
||||
hdma->XferErrorCallback(hdma);
|
||||
}
|
||||
}
|
||||
}
|
||||
/* FIFO Error Interrupt management ******************************************/
|
||||
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)) != RESET)
|
||||
{
|
||||
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
|
||||
{
|
||||
/* Disable the FIFO Error interrupt */
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE);
|
||||
|
||||
/* Clear the FIFO error flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_FE;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_ERROR;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if(hdma->XferErrorCallback != NULL)
|
||||
{
|
||||
/* Transfer error callback */
|
||||
hdma->XferErrorCallback(hdma);
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Direct Mode Error Interrupt management ***********************************/
|
||||
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)) != RESET)
|
||||
{
|
||||
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
|
||||
{
|
||||
/* Disable the direct mode Error interrupt */
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME);
|
||||
|
||||
/* Clear the direct mode error flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_DME;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_ERROR;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if(hdma->XferErrorCallback != NULL)
|
||||
{
|
||||
/* Transfer error callback */
|
||||
hdma->XferErrorCallback(hdma);
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Half Transfer Complete Interrupt management ******************************/
|
||||
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
|
||||
{
|
||||
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
|
||||
{
|
||||
/* Multi_Buffering mode enabled */
|
||||
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
|
||||
{
|
||||
/* Clear the half transfer complete flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
|
||||
|
||||
/* Current memory buffer used is Memory 0 */
|
||||
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
|
||||
}
|
||||
/* Current memory buffer used is Memory 1 */
|
||||
else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
|
||||
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
|
||||
{
|
||||
/* Disable the half transfer interrupt */
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
|
||||
}
|
||||
/* Clear the half transfer complete flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
|
||||
}
|
||||
|
||||
if(hdma->XferHalfCpltCallback != NULL)
|
||||
{
|
||||
/* Half transfer callback */
|
||||
hdma->XferHalfCpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Transfer Complete Interrupt management ***********************************/
|
||||
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
|
||||
{
|
||||
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
|
||||
{
|
||||
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
|
||||
{
|
||||
/* Clear the transfer complete flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
|
||||
|
||||
/* Current memory buffer used is Memory 1 */
|
||||
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
|
||||
{
|
||||
if(hdma->XferM1CpltCallback != NULL)
|
||||
{
|
||||
/* Transfer complete Callback for memory1 */
|
||||
hdma->XferM1CpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
/* Current memory buffer used is Memory 0 */
|
||||
else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
|
||||
{
|
||||
if(hdma->XferCpltCallback != NULL)
|
||||
{
|
||||
/* Transfer complete Callback for memory0 */
|
||||
hdma->XferCpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
|
||||
else
|
||||
{
|
||||
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
|
||||
{
|
||||
/* Disable the transfer complete interrupt */
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
|
||||
}
|
||||
/* Clear the transfer complete flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY_MEM0;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if(hdma->XferCpltCallback != NULL)
|
||||
{
|
||||
/* Transfer complete callback */
|
||||
hdma->XferCpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### State and Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides functions allowing to
|
||||
(+) Check the DMA state
|
||||
(+) Get error code
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the DMA state.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
return hdma->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the DMA error code
|
||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @retval DMA Error Code
|
||||
*/
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
return hdma->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Sets the DMA Transfer parameter.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param SrcAddress: The source memory Buffer address
|
||||
* @param DstAddress: The destination memory Buffer address
|
||||
* @param DataLength: The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
/* Configure DMA Stream data length */
|
||||
hdma->Instance->NDTR = DataLength;
|
||||
|
||||
/* Peripheral to Memory */
|
||||
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
||||
{
|
||||
/* Configure DMA Stream destination address */
|
||||
hdma->Instance->PAR = DstAddress;
|
||||
|
||||
/* Configure DMA Stream source address */
|
||||
hdma->Instance->M0AR = SrcAddress;
|
||||
}
|
||||
/* Memory to Peripheral */
|
||||
else
|
||||
{
|
||||
/* Configure DMA Stream source address */
|
||||
hdma->Instance->PAR = SrcAddress;
|
||||
|
||||
/* Configure DMA Stream destination address */
|
||||
hdma->Instance->M0AR = DstAddress;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,749 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_flash.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief FLASH HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the internal FLASH memory:
|
||||
* + Program operations functions
|
||||
* + Memory Control functions
|
||||
* + Peripheral Errors functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### FLASH peripheral features #####
|
||||
==============================================================================
|
||||
|
||||
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
|
||||
to the Flash memory. It implements the erase and program Flash memory operations
|
||||
and the read and write protection mechanisms.
|
||||
|
||||
[..] The Flash memory interface accelerates code execution with a system of instruction
|
||||
prefetch and cache lines.
|
||||
|
||||
[..] The FLASH main features are:
|
||||
(+) Flash memory read operations
|
||||
(+) Flash memory program/erase operations
|
||||
(+) Read / write protections
|
||||
(+) Prefetch on I-Code
|
||||
(+) 64 cache lines of 128 bits on I-Code
|
||||
(+) 8 cache lines of 128 bits on D-Code
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This driver provides functions and macros to configure and program the FLASH
|
||||
memory of all STM32F4xx devices.
|
||||
|
||||
(#) FLASH Memory IO Programming functions:
|
||||
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
|
||||
HAL_FLASH_Lock() functions
|
||||
(++) Program functions: byte, half word, word and double word
|
||||
(++) There Two modes of programming :
|
||||
(+++) Polling mode using HAL_FLASH_Program() function
|
||||
(+++) Interrupt mode using HAL_FLASH_Program_IT() function
|
||||
|
||||
(#) Interrupts and flags management functions :
|
||||
(++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
|
||||
(++) Wait for last FLASH operation according to its status
|
||||
(++) Get error flag status by calling HAL_SetErrorCode()
|
||||
|
||||
[..]
|
||||
In addition to these functions, this driver includes a set of macros allowing
|
||||
to handle the following operations:
|
||||
(+) Set the latency
|
||||
(+) Enable/Disable the prefetch buffer
|
||||
(+) Enable/Disable the Instruction cache and the Data cache
|
||||
(+) Reset the Instruction cache and the Data cache
|
||||
(+) Enable/Disable the FLASH interrupts
|
||||
(+) Monitor the FLASH flags status
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH
|
||||
* @brief FLASH HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
|
||||
|
||||
#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Variable used for Erase sectors under interruption */
|
||||
FLASH_ProcessTypeDef pFlash;
|
||||
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Program operations */
|
||||
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
|
||||
static void FLASH_Program_Word(uint32_t Address, uint32_t Data);
|
||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
|
||||
static void FLASH_Program_Byte(uint32_t Address, uint8_t Data);
|
||||
static void FLASH_SetErrorCode(void);
|
||||
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Functions FLASH Private functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Group1 Programming operation functions
|
||||
* @brief Programming operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Programming operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to manage the FLASH
|
||||
program operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Program byte, halfword, word or double word at a specified address
|
||||
* @param TypeProgram: Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address: specifies the address to be programmed.
|
||||
* @param Data: specifies the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TYPEPROGRAM(TypeProgram));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
if(TypeProgram == TYPEPROGRAM_BYTE)
|
||||
{
|
||||
/*Program byte (8-bit) at a specified address.*/
|
||||
FLASH_Program_Byte(Address, (uint8_t) Data);
|
||||
}
|
||||
else if(TypeProgram == TYPEPROGRAM_HALFWORD)
|
||||
{
|
||||
/*Program halfword (16-bit) at a specified address.*/
|
||||
FLASH_Program_HalfWord(Address, (uint16_t) Data);
|
||||
}
|
||||
else if(TypeProgram == TYPEPROGRAM_WORD)
|
||||
{
|
||||
/*Program word (32-bit) at a specified address.*/
|
||||
FLASH_Program_Word(Address, (uint32_t) Data);
|
||||
}
|
||||
else
|
||||
{
|
||||
/*Program double word (64-bit) at a specified address.*/
|
||||
FLASH_Program_DoubleWord(Address, Data);
|
||||
}
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the program operation is completed, disable the PG Bit */
|
||||
FLASH->CR &= (~FLASH_CR_PG);
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program byte, halfword, word or double word at a specified address with interrupt enabled.
|
||||
* @param TypeProgram: Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address: specifies the address to be programmed.
|
||||
* @param Data: specifies the data to be programmed
|
||||
*
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TYPEPROGRAM(TypeProgram));
|
||||
|
||||
/* Enable End of FLASH Operation interrupt */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
|
||||
|
||||
/* Enable Error source interrupt */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
|
||||
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
|
||||
FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR);
|
||||
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
|
||||
pFlash.Address = Address;
|
||||
|
||||
if(TypeProgram == TYPEPROGRAM_BYTE)
|
||||
{
|
||||
/*Program byte (8-bit) at a specified address.*/
|
||||
FLASH_Program_Byte(Address, (uint8_t) Data);
|
||||
}
|
||||
else if(TypeProgram == TYPEPROGRAM_HALFWORD)
|
||||
{
|
||||
/*Program halfword (16-bit) at a specified address.*/
|
||||
FLASH_Program_HalfWord(Address, (uint16_t) Data);
|
||||
}
|
||||
else if(TypeProgram == TYPEPROGRAM_WORD)
|
||||
{
|
||||
/*Program word (32-bit) at a specified address.*/
|
||||
FLASH_Program_Word(Address, (uint32_t) Data);
|
||||
}
|
||||
else
|
||||
{
|
||||
/*Program double word (64-bit) at a specified address.*/
|
||||
FLASH_Program_DoubleWord(Address, Data);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles FLASH interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASH_IRQHandler(void)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
/* If the program operation is completed, disable the PG Bit */
|
||||
FLASH->CR &= (~FLASH_CR_PG);
|
||||
|
||||
/* If the erase operation is completed, disable the SER Bit */
|
||||
FLASH->CR &= (~FLASH_CR_SER);
|
||||
FLASH->CR &= SECTOR_MASK;
|
||||
|
||||
/* if the erase operation is completed, disable the MER Bit */
|
||||
FLASH->CR &= (~FLASH_MER_BIT);
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
|
||||
{
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
|
||||
{
|
||||
/*Nb of sector to erased can be decreased*/
|
||||
pFlash.NbSectorsToErase--;
|
||||
|
||||
/* Check if there are still sectors to erase*/
|
||||
if(pFlash.NbSectorsToErase != 0)
|
||||
{
|
||||
temp = pFlash.Sector;
|
||||
/*Indicate user which sector has been erased*/
|
||||
HAL_FLASH_EndOfOperationCallback(temp);
|
||||
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
|
||||
FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR);
|
||||
|
||||
/*Increment sector number*/
|
||||
temp = ++pFlash.Sector;
|
||||
FLASH_Erase_Sector(temp, pFlash.VoltageForErase);
|
||||
}
|
||||
else
|
||||
{
|
||||
/*No more sectors to Erase, user callback can be called.*/
|
||||
/*Reset Sector and stop Erase sectors procedure*/
|
||||
pFlash.Sector = temp = 0xFFFFFFFF;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(temp);
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
|
||||
{
|
||||
/*MassErase ended. Return the selected bank*/
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
|
||||
}
|
||||
else
|
||||
{
|
||||
/*Program ended. Return the selected address*/
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
|
||||
}
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Check FLASH operation error flags */
|
||||
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
|
||||
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
|
||||
{
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
|
||||
{
|
||||
/*return the faulty sector*/
|
||||
temp = pFlash.Sector;
|
||||
pFlash.Sector = 0xFFFFFFFF;
|
||||
}
|
||||
else if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
|
||||
{
|
||||
/*return the faulty bank*/
|
||||
temp = pFlash.Bank;
|
||||
}
|
||||
else
|
||||
{
|
||||
/*retrun the faulty address*/
|
||||
temp = pFlash.Address;
|
||||
}
|
||||
|
||||
/*Save the Error code*/
|
||||
FLASH_SetErrorCode();
|
||||
|
||||
/* FLASH error interrupt user callback */
|
||||
HAL_FLASH_OperationErrorCallback(temp);
|
||||
/* Clear FLASH error pending bits */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR |\
|
||||
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR);
|
||||
|
||||
/*Stop the procedure ongoing*/
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
|
||||
{
|
||||
/* Disable End of FLASH Operation interrupt */
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
|
||||
|
||||
/* Disable Error source interrupt */
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH end of operation interrupt callback
|
||||
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
|
||||
* Mass Erase: Bank number which has been requested to erase
|
||||
* Sectors Erase: Sector which has been erased
|
||||
* (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
|
||||
* Program: Address which was selected for data program
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH operation error interrupt callback
|
||||
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
|
||||
* Mass Erase: Bank number which has been requested to erase
|
||||
* Sectors Erase: Sector number which returned an error
|
||||
* Program: Address which was selected for data program
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Group2 Peripheral Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the FLASH
|
||||
memory operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH control register access
|
||||
* @param None
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
|
||||
{
|
||||
if((FLASH->CR & FLASH_CR_LOCK) != RESET)
|
||||
{
|
||||
/* Authorize the FLASH Registers access */
|
||||
FLASH->KEYR = FLASH_KEY1;
|
||||
FLASH->KEYR = FLASH_KEY2;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks the FLASH control register access
|
||||
* @param None
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void)
|
||||
{
|
||||
/* Set the LOCK Bit to lock the FLASH Registers access */
|
||||
FLASH->CR |= FLASH_CR_LOCK;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH Option Control Registers access.
|
||||
* @param None
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
|
||||
{
|
||||
if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
|
||||
{
|
||||
/* Authorizes the Option Byte register programming */
|
||||
FLASH->OPTKEYR = FLASH_OPT_KEY1;
|
||||
FLASH->OPTKEYR = FLASH_OPT_KEY2;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Lock the FLASH Option Control Registers access.
|
||||
* @param None
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
|
||||
{
|
||||
/* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
|
||||
FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Launch the option byte loading.
|
||||
* @param None
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
|
||||
{
|
||||
/* Set the OPTSTRT bit in OPTCR register */
|
||||
*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
return(FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Group3 Peripheral State and Errors functions
|
||||
* @brief Peripheral Errors functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time Errors of the FLASH peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get the specific FLASH error flag.
|
||||
* @param None
|
||||
* @retval FLASH_ErrorCode: The returned value can be:
|
||||
* @arg FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
|
||||
* @arg FLASH_ERROR_PGS: FLASH Programming Sequence error flag
|
||||
* @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
|
||||
* @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag
|
||||
* @arg FLASH_ERROR_WRP: FLASH Write protected error flag
|
||||
* @arg FLASH_ERROR_OPERATION: FLASH operation Error flag
|
||||
*/
|
||||
FLASH_ErrorTypeDef HAL_FLASH_GetError(void)
|
||||
{
|
||||
return pFlash.ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Wait for a FLASH operation to complete.
|
||||
* @param Timeout: maximum flash operationtimeout
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
||||
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
||||
flag will be set */
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET)
|
||||
{
|
||||
if(Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
|
||||
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
|
||||
{
|
||||
/*Save the error code*/
|
||||
FLASH_SetErrorCode();
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* If there is an error flag set */
|
||||
return HAL_OK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program a double word (64-bit) at a specified address.
|
||||
* @note This function must be used when the device voltage range is from
|
||||
* 2.7V to 3.6V and an External Vpp is present.
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param Address: specifies the address to be programmed.
|
||||
* @param Data: specifies the data to be programmed.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_ADDRESS(Address));
|
||||
|
||||
/* If the previous operation is completed, proceed to program the new data */
|
||||
FLASH->CR &= CR_PSIZE_MASK;
|
||||
FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
|
||||
FLASH->CR |= FLASH_CR_PG;
|
||||
|
||||
*(__IO uint64_t*)Address = Data;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Program word (32-bit) at a specified address.
|
||||
* @note This function must be used when the device voltage range is from
|
||||
* 2.7V to 3.6V.
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param Address: specifies the address to be programmed.
|
||||
* @param Data: specifies the data to be programmed.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_ADDRESS(Address));
|
||||
|
||||
/* If the previous operation is completed, proceed to program the new data */
|
||||
FLASH->CR &= CR_PSIZE_MASK;
|
||||
FLASH->CR |= FLASH_PSIZE_WORD;
|
||||
FLASH->CR |= FLASH_CR_PG;
|
||||
|
||||
*(__IO uint32_t*)Address = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program a half-word (16-bit) at a specified address.
|
||||
* @note This function must be used when the device voltage range is from
|
||||
* 2.7V to 3.6V.
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param Address: specifies the address to be programmed.
|
||||
* @param Data: specifies the data to be programmed.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_ADDRESS(Address));
|
||||
|
||||
/* If the previous operation is completed, proceed to program the new data */
|
||||
FLASH->CR &= CR_PSIZE_MASK;
|
||||
FLASH->CR |= FLASH_PSIZE_HALF_WORD;
|
||||
FLASH->CR |= FLASH_CR_PG;
|
||||
|
||||
*(__IO uint16_t*)Address = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program byte (8-bit) at a specified address.
|
||||
* @note This function must be used when the device voltage range is from
|
||||
* 2.7V to 3.6V.
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param Address: specifies the address to be programmed.
|
||||
* @param Data: specifies the data to be programmed.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_ADDRESS(Address));
|
||||
|
||||
/* If the previous operation is completed, proceed to program the new data */
|
||||
FLASH->CR &= CR_PSIZE_MASK;
|
||||
FLASH->CR |= FLASH_PSIZE_BYTE;
|
||||
FLASH->CR |= FLASH_CR_PG;
|
||||
|
||||
*(__IO uint8_t*)Address = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specific FLASH error flag.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_SetErrorCode(void)
|
||||
{
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
|
||||
{
|
||||
pFlash.ErrorCode = FLASH_ERROR_WRP;
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
|
||||
{
|
||||
pFlash.ErrorCode |= FLASH_ERROR_PGA;
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
|
||||
{
|
||||
pFlash.ErrorCode |= FLASH_ERROR_PGP;
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET)
|
||||
{
|
||||
pFlash.ErrorCode |= FLASH_ERROR_PGS;
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
|
||||
{
|
||||
pFlash.ErrorCode |= FLASH_ERROR_RD;
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
|
||||
{
|
||||
pFlash.ErrorCode |= FLASH_ERROR_OPERATION;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,752 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_i2s_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief I2S HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of I2S extension peripheral:
|
||||
* + Extension features Functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### I2S Extension features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
|
||||
data simultaneously using two data lines. Each SPI peripheral has an extended block
|
||||
called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3).
|
||||
(#) The extension block is not a full SPI IP, it is used only as I2S slave to
|
||||
implement full duplex mode. The extension block uses the same clock sources
|
||||
as its master.
|
||||
|
||||
(#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
|
||||
|
||||
[..]
|
||||
(@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
|
||||
I2Sx can be I2S2 or I2S3.
|
||||
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
Three operation modes are available within this driver :
|
||||
|
||||
*** Polling mode IO operation ***
|
||||
=================================
|
||||
[..]
|
||||
(+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive()
|
||||
|
||||
*** Interrupt mode IO operation ***
|
||||
===================================
|
||||
[..]
|
||||
(+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT()
|
||||
(+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
|
||||
add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
|
||||
(+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
|
||||
add his own code by customization of function pointer HAL_I2S_TxCpltCallback
|
||||
(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
|
||||
add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
|
||||
(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
|
||||
add his own code by customization of function pointer HAL_I2S_RxCpltCallback
|
||||
(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
|
||||
add his own code by customization of function pointer HAL_I2S_ErrorCallback
|
||||
|
||||
*** DMA mode IO operation ***
|
||||
==============================
|
||||
[..]
|
||||
(+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA()
|
||||
(+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
|
||||
add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
|
||||
(+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
|
||||
add his own code by customization of function pointer HAL_I2S_TxCpltCallback
|
||||
(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
|
||||
add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
|
||||
(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
|
||||
add his own code by customization of function pointer HAL_I2S_RxCpltCallback
|
||||
(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
|
||||
add his own code by customization of function pointer HAL_I2S_ErrorCallback
|
||||
(+) Pause the DMA Transfer using HAL_I2S_DMAPause()
|
||||
(+) Resume the DMA Transfer using HAL_I2S_DMAResume()
|
||||
(+) Stop the DMA Transfer using HAL_I2S_DMAStop()
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2SEx
|
||||
* @brief I2S HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2SEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2SEx_Group1 Extension features functions
|
||||
* @brief Extension features functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extension features Functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to manage the I2S data
|
||||
transfers.
|
||||
|
||||
(#) There are two modes of transfer:
|
||||
(++) Blocking mode : The communication is performed in the polling mode.
|
||||
The status of all data processing is returned by the same function
|
||||
after finishing transfer.
|
||||
(++) No-Blocking mode : The communication is performed using Interrupts
|
||||
or DMA. These functions return the status of the transfer startup.
|
||||
The end of the data processing will be indicated through the
|
||||
dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
|
||||
using DMA mode.
|
||||
|
||||
(#) Blocking mode functions are :
|
||||
(++) HAL_I2S_TransmitReceive()
|
||||
|
||||
(#) No-Blocking mode functions with Interrupt are :
|
||||
(++) HAL_I2S_TransmitReceive_IT()
|
||||
|
||||
(#) No-Blocking mode functions with DMA are :
|
||||
(++) HAL_I2S_TransmitReceive_DMA()
|
||||
|
||||
(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
|
||||
(++) HAL_I2S_TxCpltCallback()
|
||||
(++) HAL_I2S_RxCpltCallback()
|
||||
(++) HAL_I2S_ErrorCallback()
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Full-Duplex Transmit/Receive data in blocking mode.
|
||||
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
|
||||
* the configuration information for I2S module
|
||||
* @param pTxData: a 16-bit pointer to the Transmit data buffer.
|
||||
* @param pRxData: a 16-bit pointer to the Receive data buffer.
|
||||
* @param Size: number of data sample to be sent:
|
||||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* @param Timeout: Timeout duration
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
uint32_t tmp1 = 0, tmp2 = 0;
|
||||
|
||||
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the I2S State */
|
||||
if(hi2s->State == HAL_I2S_STATE_READY)
|
||||
{
|
||||
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
|
||||
tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
|
||||
/* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
|
||||
is selected during the I2S configuration phase, the Size parameter means the number
|
||||
of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
|
||||
frame is selected the Size parameter means the number of 16-bit data length. */
|
||||
if((tmp1 == I2S_DATAFORMAT_24B)|| \
|
||||
(tmp2 == I2S_DATAFORMAT_32B))
|
||||
{
|
||||
hi2s->TxXferSize = Size*2;
|
||||
hi2s->TxXferCount = Size*2;
|
||||
hi2s->RxXferSize = Size*2;
|
||||
hi2s->RxXferCount = Size*2;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2s->TxXferSize = Size;
|
||||
hi2s->TxXferCount = Size;
|
||||
hi2s->RxXferSize = Size;
|
||||
hi2s->RxXferCount = Size;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2s);
|
||||
|
||||
/* Set the I2S State busy TX/RX */
|
||||
hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
|
||||
|
||||
tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
||||
tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
||||
/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
|
||||
if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
|
||||
{
|
||||
/* Check if the I2S is already enabled: The I2S is kept enabled at the end of transaction
|
||||
to avoid the clock de-synchronization between Master and Slave. */
|
||||
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
|
||||
{
|
||||
/* Enable I2Sext(receiver) before enabling I2Sx peripheral */
|
||||
I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
||||
|
||||
/* Enable I2Sx peripheral */
|
||||
__HAL_I2S_ENABLE(hi2s);
|
||||
}
|
||||
|
||||
while(hi2s->TxXferCount > 0)
|
||||
{
|
||||
/* Wait until TXE flag is set */
|
||||
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
hi2s->Instance->DR = (*pTxData++);
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait until RXNE flag is set */
|
||||
while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) != SPI_SR_RXNE)
|
||||
{
|
||||
if(Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2s);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
(*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
|
||||
|
||||
hi2s->TxXferCount--;
|
||||
hi2s->RxXferCount--;
|
||||
}
|
||||
}
|
||||
/* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
|
||||
else
|
||||
{
|
||||
/* Check if the I2S is already enabled */
|
||||
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
|
||||
{
|
||||
/* Enable I2S peripheral before the I2Sext*/
|
||||
__HAL_I2S_ENABLE(hi2s);
|
||||
|
||||
/* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
|
||||
I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check if Master Receiver mode is selected */
|
||||
if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
|
||||
{
|
||||
/* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
|
||||
access to the SPI_SR register. */
|
||||
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
|
||||
}
|
||||
}
|
||||
while(hi2s->TxXferCount > 0)
|
||||
{
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait until TXE flag is set */
|
||||
while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) != SPI_SR_TXE)
|
||||
{
|
||||
if(Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2s);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
|
||||
|
||||
/* Wait until RXNE flag is set */
|
||||
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
(*pRxData++) = hi2s->Instance->DR;
|
||||
|
||||
hi2s->TxXferCount--;
|
||||
hi2s->RxXferCount--;
|
||||
}
|
||||
}
|
||||
|
||||
/* Set the I2S State ready */
|
||||
hi2s->State = HAL_I2S_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2s);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
|
||||
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
|
||||
* the configuration information for I2S module
|
||||
* @param pTxData: a 16-bit pointer to the Transmit data buffer.
|
||||
* @param pRxData: a 16-bit pointer to the Receive data buffer.
|
||||
* @param Size: number of data sample to be sent:
|
||||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
|
||||
{
|
||||
uint32_t tmp1 = 0, tmp2 = 0;
|
||||
|
||||
if(hi2s->State == HAL_I2S_STATE_READY)
|
||||
{
|
||||
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
hi2s->pTxBuffPtr = pTxData;
|
||||
hi2s->pRxBuffPtr = pRxData;
|
||||
|
||||
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
|
||||
tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
|
||||
/* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
|
||||
is selected during the I2S configuration phase, the Size parameter means the number
|
||||
of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
|
||||
frame is selected the Size parameter means the number of 16-bit data length. */
|
||||
if((tmp1 == I2S_DATAFORMAT_24B)||\
|
||||
(tmp2 == I2S_DATAFORMAT_32B))
|
||||
{
|
||||
hi2s->TxXferSize = Size*2;
|
||||
hi2s->TxXferCount = Size*2;
|
||||
hi2s->RxXferSize = Size*2;
|
||||
hi2s->RxXferCount = Size*2;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2s->TxXferSize = Size;
|
||||
hi2s->TxXferCount = Size;
|
||||
hi2s->RxXferSize = Size;
|
||||
hi2s->RxXferCount = Size;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2s);
|
||||
|
||||
hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
|
||||
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
|
||||
|
||||
tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
||||
tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
||||
/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
|
||||
if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
|
||||
{
|
||||
/* Enable I2Sext RXNE and ERR interrupts */
|
||||
I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_RXNE | I2S_IT_ERR);
|
||||
|
||||
/* Enable I2Sx TXE and ERR interrupts */
|
||||
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
|
||||
|
||||
/* Check if the I2S is already enabled */
|
||||
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
|
||||
{
|
||||
/* Enable I2Sext(receiver) before enabling I2Sx peripheral */
|
||||
I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
||||
|
||||
/* Enable I2Sx peripheral */
|
||||
__HAL_I2S_ENABLE(hi2s);
|
||||
}
|
||||
}
|
||||
/* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
|
||||
else
|
||||
{
|
||||
/* Enable I2Sext TXE and ERR interrupts */
|
||||
I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_TXE |I2S_IT_ERR);
|
||||
|
||||
/* Enable I2Sext RXNE and ERR interrupts */
|
||||
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
|
||||
|
||||
/* Check if the I2S is already enabled */
|
||||
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
|
||||
{
|
||||
/* Check if the I2S_MODE_MASTER_RX is selected */
|
||||
if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
|
||||
{
|
||||
/* Prepare the First Data before enabling the I2S */
|
||||
if(hi2s->TxXferCount != 0)
|
||||
{
|
||||
/* Transmit First data */
|
||||
I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
|
||||
hi2s->TxXferCount--;
|
||||
|
||||
if(hi2s->TxXferCount == 0)
|
||||
{
|
||||
/* Disable I2Sext TXE interrupt */
|
||||
I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Enable I2S peripheral */
|
||||
__HAL_I2S_ENABLE(hi2s);
|
||||
|
||||
/* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
|
||||
I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
||||
}
|
||||
}
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2s);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
|
||||
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
|
||||
* the configuration information for I2S module
|
||||
* @param pTxData: a 16-bit pointer to the Transmit data buffer.
|
||||
* @param pRxData: a 16-bit pointer to the Receive data buffer.
|
||||
* @param Size: number of data sample to be sent:
|
||||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
|
||||
{
|
||||
uint32_t *tmp;
|
||||
uint32_t tmp1 = 0, tmp2 = 0;
|
||||
|
||||
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if(hi2s->State == HAL_I2S_STATE_READY)
|
||||
{
|
||||
hi2s->pTxBuffPtr = pTxData;
|
||||
hi2s->pRxBuffPtr = pRxData;
|
||||
|
||||
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
|
||||
tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
|
||||
/* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
|
||||
is selected during the I2S configuration phase, the Size parameter means the number
|
||||
of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
|
||||
frame is selected the Size parameter means the number of 16-bit data length. */
|
||||
if((tmp1 == I2S_DATAFORMAT_24B)||\
|
||||
(tmp2 == I2S_DATAFORMAT_32B))
|
||||
{
|
||||
hi2s->TxXferSize = Size*2;
|
||||
hi2s->TxXferCount = Size*2;
|
||||
hi2s->RxXferSize = Size*2;
|
||||
hi2s->RxXferCount = Size*2;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2s->TxXferSize = Size;
|
||||
hi2s->TxXferCount = Size;
|
||||
hi2s->RxXferSize = Size;
|
||||
hi2s->RxXferCount = Size;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2s);
|
||||
|
||||
hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
|
||||
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
|
||||
|
||||
/* Set the I2S Rx DMA Half transfert complete callback */
|
||||
hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
|
||||
|
||||
/* Set the I2S Rx DMA transfert complete callback */
|
||||
hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
|
||||
|
||||
/* Set the I2S Rx DMA error callback */
|
||||
hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
|
||||
|
||||
/* Set the I2S Tx DMA Half transfert complete callback */
|
||||
hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
|
||||
|
||||
/* Set the I2S Tx DMA transfert complete callback */
|
||||
hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
|
||||
|
||||
/* Set the I2S Tx DMA error callback */
|
||||
hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
|
||||
|
||||
tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
||||
tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
||||
/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
|
||||
if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
|
||||
{
|
||||
/* Enable the Rx DMA Stream */
|
||||
tmp = (uint32_t*)&pRxData;
|
||||
HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
|
||||
|
||||
/* Enable Rx DMA Request */
|
||||
I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
|
||||
|
||||
/* Enable the Tx DMA Stream */
|
||||
tmp = (uint32_t*)&pTxData;
|
||||
HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
|
||||
|
||||
/* Enable Tx DMA Request */
|
||||
hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
|
||||
|
||||
/* Check if the I2S is already enabled */
|
||||
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
|
||||
{
|
||||
/* Enable I2Sext(receiver) before enabling I2Sx peripheral */
|
||||
I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
||||
|
||||
/* Enable I2S peripheral after the I2Sext */
|
||||
__HAL_I2S_ENABLE(hi2s);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enable the Tx DMA Stream */
|
||||
tmp = (uint32_t*)&pTxData;
|
||||
HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
|
||||
|
||||
/* Enable Tx DMA Request */
|
||||
I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
|
||||
|
||||
/* Enable the Rx DMA Stream */
|
||||
tmp = (uint32_t*)&pRxData;
|
||||
HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
|
||||
|
||||
/* Enable Rx DMA Request */
|
||||
hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
|
||||
|
||||
/* Check if the I2S is already enabled */
|
||||
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
|
||||
{
|
||||
/* Enable I2S peripheral before the I2Sext */
|
||||
__HAL_I2S_ENABLE(hi2s);
|
||||
|
||||
/* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
|
||||
I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check if Master Receiver mode is selected */
|
||||
if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
|
||||
{
|
||||
/* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
|
||||
access to the SPI_SR register. */
|
||||
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2s);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
|
||||
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
|
||||
* the configuration information for I2S module
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s)
|
||||
{
|
||||
uint32_t tmp1 = 0, tmp2 = 0;
|
||||
|
||||
if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2s);
|
||||
|
||||
tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
||||
tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
||||
/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
|
||||
if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
|
||||
{
|
||||
if(hi2s->TxXferCount != 0)
|
||||
{
|
||||
if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE) != RESET)
|
||||
{
|
||||
/* Transmit data */
|
||||
hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
|
||||
hi2s->TxXferCount--;
|
||||
|
||||
if(hi2s->TxXferCount == 0)
|
||||
{
|
||||
/* Disable TXE interrupt */
|
||||
__HAL_I2S_DISABLE_IT(hi2s, I2S_IT_TXE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(hi2s->RxXferCount != 0)
|
||||
{
|
||||
if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) == SPI_SR_RXNE)
|
||||
{
|
||||
/* Receive data */
|
||||
(*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
|
||||
hi2s->RxXferCount--;
|
||||
|
||||
if(hi2s->RxXferCount == 0)
|
||||
{
|
||||
/* Disable I2Sext RXNE interrupt */
|
||||
I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_RXNE;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
/* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
|
||||
else
|
||||
{
|
||||
if(hi2s->TxXferCount != 0)
|
||||
{
|
||||
if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) == SPI_SR_TXE)
|
||||
{
|
||||
/* Transmit data */
|
||||
I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
|
||||
hi2s->TxXferCount--;
|
||||
|
||||
if(hi2s->TxXferCount == 0)
|
||||
{
|
||||
/* Disable I2Sext TXE interrupt */
|
||||
I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
|
||||
|
||||
HAL_I2S_TxCpltCallback(hi2s);
|
||||
}
|
||||
}
|
||||
}
|
||||
if(hi2s->RxXferCount != 0)
|
||||
{
|
||||
if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE) != RESET)
|
||||
{
|
||||
/* Receive data */
|
||||
(*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
|
||||
hi2s->RxXferCount--;
|
||||
|
||||
if(hi2s->RxXferCount == 0)
|
||||
{
|
||||
/* Disable RXNE interrupt */
|
||||
__HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE);
|
||||
|
||||
HAL_I2S_RxCpltCallback(hi2s);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
tmp1 = hi2s->RxXferCount;
|
||||
tmp2 = hi2s->TxXferCount;
|
||||
if((tmp1 == 0) && (tmp2 == 0))
|
||||
{
|
||||
/* Disable I2Sx ERR interrupt */
|
||||
__HAL_I2S_DISABLE_IT(hi2s, I2S_IT_ERR);
|
||||
/* Disable I2Sext ERR interrupt */
|
||||
I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_ERR;
|
||||
|
||||
hi2s->State = HAL_I2S_STATE_READY;
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2s);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,355 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_iwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief IWDG HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Independent Watchdog (IWDG) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### IWDG Generic features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) The IWDG can be started by either software or hardware (configurable
|
||||
through option byte).
|
||||
|
||||
(+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and
|
||||
thus stays active even if the main clock fails.
|
||||
Once the IWDG is started, the LSI is forced ON and cannot be disabled
|
||||
(LSI cannot be disabled too), and the counter starts counting down from
|
||||
the reset value of 0xFFF. When it reaches the end of count value (0x000)
|
||||
a system reset is generated.
|
||||
|
||||
(+) The IWDG counter should be refreshed at regular intervals, otherwise the
|
||||
watchdog generates an MCU reset when the counter reaches 0.
|
||||
|
||||
(+) The IWDG is implemented in the VDD voltage domain that is still functional
|
||||
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
|
||||
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
|
||||
reset occurs.
|
||||
|
||||
(+) Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
|
||||
The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
|
||||
devices provide the capability to measure the LSI frequency (LSI clock
|
||||
connected internally to TIM5 CH4 input capture). The measured value
|
||||
can be used to have an IWDG timeout with an acceptable accuracy.
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
If Window option is disabled
|
||||
(+) Use IWDG using HAL_IWDG_Init() function to :
|
||||
(++) Enable write access to IWDG_PR, IWDG_RLR.
|
||||
(++) Configure the IWDG prescaler, counter reload value.
|
||||
This reload value will be loaded in the IWDG counter each time the counter
|
||||
is reloaded, then the IWDG will start counting down from this value.
|
||||
[..]
|
||||
(+) Use IWDG using HAL_IWDG_Start() function to:
|
||||
(++) Reload IWDG counter with value defined in the IWDG_RLR register.
|
||||
(++) Start the IWDG, when the IWDG is used in software mode (no need
|
||||
to enable the LSI, it will be enabled by hardware).
|
||||
(+) Then the application program must refresh the IWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
HAL_IWDG_Refresh() function.
|
||||
[..]
|
||||
if Window option is enabled:
|
||||
|
||||
(+) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter
|
||||
(+) Use IWDG using HAL_IWDG_Init() function to :
|
||||
(++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
(++) Configure the IWDG prescaler, reload value and window value.
|
||||
(+) Then the application program must refresh the IWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
HAL_IWDG_Refresh() function.
|
||||
|
||||
*** IWDG HAL driver macros list ***
|
||||
====================================
|
||||
[..]
|
||||
Below the list of most used macros in IWDG HAL driver.
|
||||
|
||||
(+) __HAL_IWDG_START: Enable the IWDG peripheral
|
||||
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register
|
||||
(+) __HAL_IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers
|
||||
(+) __HAL_IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers
|
||||
(+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG
|
||||
* @brief IWDG HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define IWDG_TIMEOUT_FLAG ((uint32_t)1000) /* 1 s */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IWDG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the IWDG according to the specified parameters
|
||||
in the IWDG_InitTypeDef and create the associated handle
|
||||
(+) Initialize the IWDG MSP
|
||||
(+) DeInitialize IWDG MSP
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the IWDG according to the specified
|
||||
* parameters in the IWDG_InitTypeDef and creates the associated handle.
|
||||
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified IWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
/* Check the IWDG handle allocation */
|
||||
if(hiwdg == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
|
||||
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
|
||||
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
|
||||
|
||||
if(hiwdg->State == HAL_IWDG_STATE_RESET)
|
||||
{
|
||||
/* Init the low level hardware */
|
||||
HAL_IWDG_MspInit(hiwdg);
|
||||
}
|
||||
|
||||
/* Change IWDG peripheral state */
|
||||
hiwdg->State = HAL_IWDG_STATE_BUSY;
|
||||
|
||||
/* Enable write access to IWDG_PR and IWDG_RLR registers */
|
||||
__HAL_IWDG_ENABLE_WRITE_ACCESS(hiwdg);
|
||||
|
||||
/* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
|
||||
MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler);
|
||||
MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload);
|
||||
|
||||
/* Change IWDG peripheral state */
|
||||
hiwdg->State = HAL_IWDG_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the IWDG MSP.
|
||||
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified IWDG module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_IWDG_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Start the IWDG.
|
||||
(+) Refresh the IWDG.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Starts the IWDG.
|
||||
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified IWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hiwdg);
|
||||
|
||||
/* Change IWDG peripheral state */
|
||||
hiwdg->State = HAL_IWDG_STATE_BUSY;
|
||||
|
||||
/* Start the IWDG peripheral */
|
||||
__HAL_IWDG_START(hiwdg);
|
||||
|
||||
/* Reload IWDG counter with value defined in the RLR register */
|
||||
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
|
||||
|
||||
/* Change IWDG peripheral state */
|
||||
hiwdg->State = HAL_IWDG_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hiwdg);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Refreshes the IWDG.
|
||||
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified IWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hiwdg);
|
||||
|
||||
/* Change IWDG peripheral state */
|
||||
hiwdg->State = HAL_IWDG_STATE_BUSY;
|
||||
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait until RVU flag is RESET */
|
||||
while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > IWDG_TIMEOUT_FLAG)
|
||||
{
|
||||
/* Set IWDG state */
|
||||
hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hiwdg);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Reload IWDG counter with value defined in the reload register */
|
||||
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
|
||||
|
||||
/* Change IWDG peripheral state */
|
||||
hiwdg->State = HAL_IWDG_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hiwdg);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the peripheral
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the IWDG state.
|
||||
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified IWDG module.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
return hiwdg->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,968 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_nor.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief NOR HAL module driver.
|
||||
* This file provides a generic firmware to drive NOR memories mounted
|
||||
* as external device.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This driver is a generic layered driver which contains a set of APIs used to
|
||||
control NOR flash memories. It uses the FMC/FSMC layer functions to interface
|
||||
with NOR devices. This driver is used as follows:
|
||||
|
||||
(+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
|
||||
with control and timing parameters for both normal and extended mode.
|
||||
|
||||
(+) Read NOR flash memory manufacturer code and device IDs using the function
|
||||
HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
|
||||
structure declared by the function caller.
|
||||
|
||||
(+) Access NOR flash memory by read/write data unit operations using the functions
|
||||
HAL_NOR_Read(), HAL_NOR_Program().
|
||||
|
||||
(+) Perform NOR flash erase block/chip operations using the functions
|
||||
HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
|
||||
|
||||
(+) Read the NOR flash CFI (common flash interface) IDs using the function
|
||||
HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
|
||||
structure declared by the function caller.
|
||||
|
||||
(+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
|
||||
HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
|
||||
|
||||
(+) You can monitor the NOR device HAL state by calling the function
|
||||
HAL_NOR_GetState()
|
||||
[..]
|
||||
(@) This driver is a set of generic APIs which handle standard NOR flash operations.
|
||||
If a NOR flash device contains different operations and/or implementations,
|
||||
it should be implemented separately.
|
||||
|
||||
*** NOR HAL driver macros list ***
|
||||
=============================================
|
||||
[..]
|
||||
Below the list of most used macros in NOR HAL driver.
|
||||
|
||||
(+) __NOR_WRITE : NOR memory write data to specified address
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup NOR
|
||||
* @brief NOR driver modules
|
||||
* @{
|
||||
*/
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup NOR_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup NOR_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### NOR Initialization and de_initialization functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to initialize/de-initialize
|
||||
the NOR memory
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Perform the NOR memory Initialization sequence
|
||||
* @param hnor: pointer to the NOR handle
|
||||
* @param Timing: pointer to NOR control timing structure
|
||||
* @param ExtTiming: pointer to NOR extended mode timing structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
|
||||
{
|
||||
/* Check the NOR handle parameter */
|
||||
if(hnor == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if(hnor->State == HAL_NOR_STATE_RESET)
|
||||
{
|
||||
/* Initialize the low level hardware (MSP) */
|
||||
HAL_NOR_MspInit(hnor);
|
||||
}
|
||||
|
||||
/* Initialize NOR control Interface */
|
||||
FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
|
||||
|
||||
/* Initialize NOR timing Interface */
|
||||
FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
|
||||
|
||||
/* Initialize NOR extended mode timing Interface */
|
||||
FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
|
||||
|
||||
/* Enable the NORSRAM device */
|
||||
__FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
|
||||
|
||||
/* Check the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Perform NOR memory De-Initialization sequence
|
||||
* @param hnor: pointer to a NOR_HandleTypeDef structure that contains
|
||||
* the configuration information for NOR module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
|
||||
{
|
||||
/* De-Initialize the low level hardware (MSP) */
|
||||
HAL_NOR_MspDeInit(hnor);
|
||||
|
||||
/* Configure the NOR registers with their reset values */
|
||||
FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
|
||||
|
||||
/* Update the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hnor);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief NOR MSP Init
|
||||
* @param hnor: pointer to a NOR_HandleTypeDef structure that contains
|
||||
* the configuration information for NOR module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_NOR_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief NOR MSP DeInit
|
||||
* @param hnor: pointer to a NOR_HandleTypeDef structure that contains
|
||||
* the configuration information for NOR module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_NOR_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief NOR BSP Wait fro Ready/Busy signal
|
||||
* @param hnor: pointer to a NOR_HandleTypeDef structure that contains
|
||||
* the configuration information for NOR module.
|
||||
* @param Timeout: Maximum timeout value
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_NOR_BspWait could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup NOR_Group2 Input and Output functions
|
||||
* @brief Input Output and memory control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### NOR Input and Output functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to use and control the NOR memory
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Read NOR flash IDs
|
||||
* @param hnor: pointer to the NOR handle
|
||||
* @param pNOR_ID : pointer to NOR ID structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
|
||||
{
|
||||
uint32_t deviceAddress = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hnor);
|
||||
|
||||
/* Check the NOR controller state */
|
||||
if(hnor->State == HAL_NOR_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Select the NOR device address */
|
||||
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS1;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS2;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS3;
|
||||
}
|
||||
else /* FMC_NORSRAM_BANK4 */
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS4;
|
||||
}
|
||||
|
||||
/* Update the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_BUSY;
|
||||
|
||||
/* Send read ID command */
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0090);
|
||||
|
||||
/* Read the NOR IDs */
|
||||
pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, MC_ADDRESS);
|
||||
pNOR_ID->Device_Code1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
|
||||
pNOR_ID->Device_Code2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
|
||||
pNOR_ID->Device_Code3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
|
||||
|
||||
/* Check the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hnor);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the NOR memory to Read mode.
|
||||
* @param hnor: pointer to the NOR handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
|
||||
{
|
||||
uint32_t deviceAddress = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hnor);
|
||||
|
||||
/* Check the NOR controller state */
|
||||
if(hnor->State == HAL_NOR_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Select the NOR device address */
|
||||
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS1;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS2;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS3;
|
||||
}
|
||||
else /* FMC_NORSRAM_BANK4 */
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS4;
|
||||
}
|
||||
|
||||
__NOR_WRITE(deviceAddress, 0x00F0);
|
||||
|
||||
/* Check the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hnor);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read data from NOR memory
|
||||
* @param hnor: pointer to the NOR handle
|
||||
* @param pAddress: pointer to Device address
|
||||
* @param pData : pointer to read data
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
|
||||
{
|
||||
uint32_t deviceAddress = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hnor);
|
||||
|
||||
/* Check the NOR controller state */
|
||||
if(hnor->State == HAL_NOR_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Select the NOR device address */
|
||||
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS1;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS2;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS3;
|
||||
}
|
||||
else /* FMC_NORSRAM_BANK4 */
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS4;
|
||||
}
|
||||
|
||||
/* Update the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_BUSY;
|
||||
|
||||
/* Send read data command */
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x00555), 0x00AA);
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x002AA), 0x0055);
|
||||
__NOR_WRITE(pAddress, 0x00F0);
|
||||
|
||||
/* Read the data */
|
||||
*pData = *(__IO uint32_t *)pAddress;
|
||||
|
||||
/* Check the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hnor);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program data to NOR memory
|
||||
* @param hnor: pointer to the NOR handle
|
||||
* @param pAddress: Device address
|
||||
* @param pData : pointer to the data to write
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
|
||||
{
|
||||
uint32_t deviceAddress = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hnor);
|
||||
|
||||
/* Check the NOR controller state */
|
||||
if(hnor->State == HAL_NOR_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Select the NOR device address */
|
||||
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS1;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS2;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS3;
|
||||
}
|
||||
else /* FMC_NORSRAM_BANK4 */
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS4;
|
||||
}
|
||||
|
||||
/* Update the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_BUSY;
|
||||
|
||||
/* Send program data command */
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00A0);
|
||||
|
||||
/* Write the data */
|
||||
__NOR_WRITE(pAddress, *pData);
|
||||
|
||||
/* Check the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hnor);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads a half-word buffer from the NOR memory.
|
||||
* @param hnor: pointer to the NOR handle
|
||||
* @param uwAddress: NOR memory internal address to read from.
|
||||
* @param pData: pointer to the buffer that receives the data read from the
|
||||
* NOR memory.
|
||||
* @param uwBufferSize : number of Half word to read.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
|
||||
{
|
||||
uint32_t deviceAddress = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hnor);
|
||||
|
||||
/* Check the NOR controller state */
|
||||
if(hnor->State == HAL_NOR_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Select the NOR device address */
|
||||
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS1;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS2;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS3;
|
||||
}
|
||||
else /* FMC_NORSRAM_BANK4 */
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS4;
|
||||
}
|
||||
|
||||
/* Update the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_BUSY;
|
||||
|
||||
/* Send read data command */
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x00555), 0x00AA);
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x002AA), 0x0055);
|
||||
__NOR_WRITE(uwAddress, 0x00F0);
|
||||
|
||||
/* Read buffer */
|
||||
while( uwBufferSize > 0)
|
||||
{
|
||||
*pData++ = *(__IO uint16_t *)uwAddress;
|
||||
uwAddress += 2;
|
||||
uwBufferSize--;
|
||||
}
|
||||
|
||||
/* Check the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hnor);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes a half-word buffer to the NOR memory. This function must be used
|
||||
only with S29GL128P NOR memory.
|
||||
* @param hnor: pointer to the NOR handle
|
||||
* @param uwAddress: NOR memory internal start write address
|
||||
* @param pData: pointer to source data buffer.
|
||||
* @param uwBufferSize: Size of the buffer to write
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
|
||||
{
|
||||
uint32_t lastloadedaddress = 0;
|
||||
uint32_t currentaddress = 0;
|
||||
uint32_t endaddress = 0;
|
||||
uint32_t deviceAddress = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hnor);
|
||||
|
||||
/* Check the NOR controller state */
|
||||
if(hnor->State == HAL_NOR_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Select the NOR device address */
|
||||
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS1;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS2;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS3;
|
||||
}
|
||||
else /* FMC_NORSRAM_BANK4 */
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS4;
|
||||
}
|
||||
|
||||
/* Update the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_BUSY;
|
||||
|
||||
/* Initialize variables */
|
||||
currentaddress = uwAddress;
|
||||
endaddress = uwAddress + uwBufferSize - 1;
|
||||
lastloadedaddress = uwAddress;
|
||||
|
||||
/* Issue unlock command sequence */
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
|
||||
|
||||
/* Write Buffer Load Command */
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), 0x25);
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1));
|
||||
|
||||
/* Load Data into NOR Buffer */
|
||||
while(currentaddress <= endaddress)
|
||||
{
|
||||
/* Store last loaded address & data value (for polling) */
|
||||
lastloadedaddress = currentaddress;
|
||||
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, currentaddress), *pData++);
|
||||
|
||||
currentaddress += 1;
|
||||
}
|
||||
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, lastloadedaddress), 0x29);
|
||||
|
||||
/* Check the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hnor);
|
||||
|
||||
return HAL_OK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Erase the specified block of the NOR memory
|
||||
* @param hnor: pointer to the NOR handle
|
||||
* @param BlockAddress : Block to erase address
|
||||
* @param Address: Device address
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
|
||||
{
|
||||
uint32_t deviceAddress = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hnor);
|
||||
|
||||
/* Check the NOR controller state */
|
||||
if(hnor->State == HAL_NOR_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Select the NOR device address */
|
||||
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS1;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS2;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS3;
|
||||
}
|
||||
else /* FMC_NORSRAM_BANK4 */
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS4;
|
||||
}
|
||||
|
||||
/* Update the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_BUSY;
|
||||
|
||||
/* Send block erase command sequence */
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0080);
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
|
||||
__NOR_WRITE((uint32_t)(BlockAddress + Address), 0x30);
|
||||
|
||||
/* Check the NOR memory status and update the controller state */
|
||||
hnor->State = HAL_NOR_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hnor);
|
||||
|
||||
return HAL_OK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Erase the entire NOR chip.
|
||||
* @param hnor: pointer to the NOR handle
|
||||
* @param Address : Device address
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
|
||||
{
|
||||
uint32_t deviceAddress = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hnor);
|
||||
|
||||
/* Check the NOR controller state */
|
||||
if(hnor->State == HAL_NOR_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Select the NOR device address */
|
||||
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS1;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS2;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS3;
|
||||
}
|
||||
else /* FMC_NORSRAM_BANK4 */
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS4;
|
||||
}
|
||||
|
||||
/* Update the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_BUSY;
|
||||
|
||||
/* Send NOR chip erase command sequence */
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0080);
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0010);
|
||||
|
||||
/* Check the NOR memory status and update the controller state */
|
||||
hnor->State = HAL_NOR_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hnor);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read NOR flash CFI IDs
|
||||
* @param hnor: pointer to the NOR handle
|
||||
* @param pNOR_CFI : pointer to NOR CFI IDs structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
|
||||
{
|
||||
uint32_t deviceAddress = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hnor);
|
||||
|
||||
/* Check the NOR controller state */
|
||||
if(hnor->State == HAL_NOR_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Select the NOR device address */
|
||||
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS1;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS2;
|
||||
}
|
||||
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS3;
|
||||
}
|
||||
else /* FMC_NORSRAM_BANK4 */
|
||||
{
|
||||
deviceAddress = NOR_MEMORY_ADRESS4;
|
||||
}
|
||||
|
||||
/* Update the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_BUSY;
|
||||
|
||||
/* Send read CFI query command */
|
||||
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0055), 0x0098);
|
||||
|
||||
/* read the NOR CFI information */
|
||||
pNOR_CFI->CFI_1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI1_ADDRESS);
|
||||
pNOR_CFI->CFI_2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI2_ADDRESS);
|
||||
pNOR_CFI->CFI_3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI3_ADDRESS);
|
||||
pNOR_CFI->CFI_4 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI4_ADDRESS);
|
||||
|
||||
/* Check the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hnor);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup NOR_Group3 Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### NOR Control functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control dynamically
|
||||
the NOR interface.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables dynamically NOR write operation.
|
||||
* @param hnor: pointer to the NOR handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hnor);
|
||||
|
||||
/* Enable write operation */
|
||||
FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
|
||||
|
||||
/* Update the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hnor);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables dynamically NOR write operation.
|
||||
* @param hnor: pointer to the NOR handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hnor);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hnor->State = HAL_NOR_STATE_BUSY;
|
||||
|
||||
/* Disable write operation */
|
||||
FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
|
||||
|
||||
/* Update the NOR controller state */
|
||||
hnor->State = HAL_NOR_STATE_PROTECTED;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hnor);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup NOR_Group4 State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### NOR State functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the NOR controller
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief return the NOR controller state
|
||||
* @param hnor: pointer to the NOR handle
|
||||
* @retval NOR controller state
|
||||
*/
|
||||
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
|
||||
{
|
||||
return hnor->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the NOR operation status.
|
||||
* @param hnor: pointer to the NOR handle
|
||||
* @param Address: Device address
|
||||
* @param Timeout: NOR progamming Timeout
|
||||
* @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
|
||||
* or NOR_TIMEOUT
|
||||
*/
|
||||
NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
|
||||
{
|
||||
NOR_StatusTypedef status = NOR_ONGOING;
|
||||
uint16_t tmpSR1 = 0, tmpSR2 = 0;
|
||||
uint32_t tickstart = 0;
|
||||
|
||||
/* Poll on NOR memory Ready/Busy signal ------------------------------------*/
|
||||
HAL_NOR_MspWait(hnor, Timeout);
|
||||
|
||||
/* Get the NOR memory operation status -------------------------------------*/
|
||||
while(status != NOR_SUCCESS)
|
||||
{
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
/* Check for the Timeout */
|
||||
if(Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
|
||||
{
|
||||
status = NOR_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Read NOR status register (DQ6 and DQ5) */
|
||||
tmpSR1 = *(__IO uint16_t *)Address;
|
||||
tmpSR2 = *(__IO uint16_t *)Address;
|
||||
|
||||
/* If DQ6 did not toggle between the two reads then return NOR_Success */
|
||||
if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040))
|
||||
{
|
||||
return NOR_SUCCESS;
|
||||
}
|
||||
|
||||
if((tmpSR1 & 0x0020) == 0x0020)
|
||||
{
|
||||
return NOR_ONGOING;
|
||||
}
|
||||
|
||||
tmpSR1 = *(__IO uint16_t *)Address;
|
||||
tmpSR2 = *(__IO uint16_t *)Address;
|
||||
|
||||
/* If DQ6 did not toggle between the two reads then return NOR_Success */
|
||||
if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040))
|
||||
{
|
||||
return NOR_SUCCESS;
|
||||
}
|
||||
|
||||
if((tmpSR1 & 0x0020) == 0x0020)
|
||||
{
|
||||
return NOR_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Return the operation status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,725 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_pccard.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief PCCARD HAL module driver.
|
||||
* This file provides a generic firmware to drive PCCARD memories mounted
|
||||
* as external device.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This driver is a generic layered driver which contains a set of APIs used to
|
||||
control PCCARD/compact flash memories. It uses the FMC/FSMC layer functions
|
||||
to interface with PCCARD devices. This driver is used for:
|
||||
|
||||
(+) PCCARD/compact flash memory configuration sequence using the function
|
||||
HAL_PCCARD_Init() with control and timing parameters for both common and
|
||||
attribute spaces.
|
||||
|
||||
(+) Read PCCARD/compact flash memory maker and device IDs using the function
|
||||
HAL_CF_Read_ID(). The read information is stored in the CompactFlash_ID
|
||||
structure declared by the function caller.
|
||||
|
||||
(+) Access PCCARD/compact flash memory by read/write operations using the functions
|
||||
HAL_CF_Read_Sector()/HAL_CF_Write_Sector(), to read/write sector.
|
||||
|
||||
(+) Perform PCCARD/compact flash Reset chip operation using the function HAL_CF_Reset().
|
||||
|
||||
(+) Perform PCCARD/compact flash erase sector operation using the function
|
||||
HAL_CF_Erase_Sector().
|
||||
|
||||
(+) Read the PCCARD/compact flash status operation using the function HAL_CF_ReadStatus().
|
||||
|
||||
(+) You can monitor the PCCARD/compact flash device HAL state by calling the function
|
||||
HAL_PCCARD_GetState()
|
||||
|
||||
[..]
|
||||
(@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
|
||||
operations. If a PCCARD/compact flash device contains different operations
|
||||
and/or implementations, it should be implemented separately.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PCCARD
|
||||
* @brief PCCARD driver modules
|
||||
* @{
|
||||
*/
|
||||
#ifdef HAL_PCCARD_MODULE_ENABLED
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PCCARD_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PCCARD_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### PCCARD Initialization and de-initialization functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to initialize/de-initialize
|
||||
the PCCARD memory
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Perform the PCCARD memory Initialization sequence
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @param ComSpaceTiming: Common space timing structure
|
||||
* @param AttSpaceTiming: Attribute space timing structure
|
||||
* @param IOSpaceTiming: IO space timing structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
|
||||
{
|
||||
/* Check the PCCARD controller state */
|
||||
if(hpccard == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if(hpccard->State == HAL_PCCARD_STATE_RESET)
|
||||
{
|
||||
/* Initialize the low level hardware (MSP) */
|
||||
HAL_PCCARD_MspInit(hpccard);
|
||||
}
|
||||
|
||||
/* Initialize the PCCARD state */
|
||||
hpccard->State = HAL_PCCARD_STATE_BUSY;
|
||||
|
||||
/* Initialize PCCARD control Interface */
|
||||
FMC_PCCARD_Init(hpccard->Instance, &(hpccard->Init));
|
||||
|
||||
/* Init PCCARD common space timing Interface */
|
||||
FMC_PCCARD_CommonSpace_Timing_Init(hpccard->Instance, ComSpaceTiming);
|
||||
|
||||
/* Init PCCARD attribute space timing Interface */
|
||||
FMC_PCCARD_AttributeSpace_Timing_Init(hpccard->Instance, AttSpaceTiming);
|
||||
|
||||
/* Init PCCARD IO space timing Interface */
|
||||
FMC_PCCARD_IOSpace_Timing_Init(hpccard->Instance, IOSpaceTiming);
|
||||
|
||||
/* Enable the PCCARD device */
|
||||
__FMC_PCCARD_ENABLE(hpccard->Instance);
|
||||
|
||||
/* Update the PCCARD state */
|
||||
hpccard->State = HAL_PCCARD_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Perform the PCCARD memory De-initialization sequence
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
/* De-Initialize the low level hardware (MSP) */
|
||||
HAL_PCCARD_MspDeInit(hpccard);
|
||||
|
||||
/* Configure the PCCARD registers with their reset values */
|
||||
FMC_PCCARD_DeInit(hpccard->Instance);
|
||||
|
||||
/* Update the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hpccard);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PCCARD MSP Init
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PCCARD_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PCCARD MSP DeInit
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PCCARD_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCCARD_Group2 Input and Output functions
|
||||
* @brief Input Output and memory control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### PCCARD Input and Output functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to use and control the PCCARD memory
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Read Compact Flash's ID.
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @param CompactFlash_ID: Compact flash ID structure.
|
||||
* @param pStatus: pointer to compact flash status
|
||||
* @retval HAL status
|
||||
*
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CF_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
|
||||
{
|
||||
uint32_t timeout = 0xFFFF, index;
|
||||
uint8_t status;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hpccard);
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Update the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_BUSY;
|
||||
|
||||
/* Initialize the CF status */
|
||||
*pStatus = CF_READY;
|
||||
|
||||
/* Send the Identify Command */
|
||||
*(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD) = 0xECEC;
|
||||
|
||||
/* Read CF IDs and timeout treatment */
|
||||
do
|
||||
{
|
||||
/* Read the CF status */
|
||||
status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
|
||||
|
||||
timeout--;
|
||||
}while((status != 0x58) && timeout);
|
||||
|
||||
if(timeout == 0)
|
||||
{
|
||||
*pStatus = CF_TIMEOUT_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Read CF ID bytes */
|
||||
for(index = 0; index < 16; index++)
|
||||
{
|
||||
CompactFlash_ID[index] = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_DATA);
|
||||
}
|
||||
}
|
||||
|
||||
/* Update the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hpccard);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read sector from PCCARD memory
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @param pBuffer: pointer to destination read buffer
|
||||
* @param SectorAddress: Sector address to read
|
||||
* @param pStatus: pointer to CF status
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
|
||||
{
|
||||
uint32_t timeout = 0xFFFF, index = 0;
|
||||
uint8_t status;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hpccard);
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Update the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_BUSY;
|
||||
|
||||
/* Initialize CF status */
|
||||
*pStatus = CF_READY;
|
||||
|
||||
/* Set the parameters to write a sector */
|
||||
*(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_HIGH) = (uint16_t)0x00;
|
||||
*(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
|
||||
*(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD) = (uint16_t)0xE4A0;
|
||||
|
||||
do
|
||||
{
|
||||
/* wait till the Status = 0x80 */
|
||||
status = *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
|
||||
timeout--;
|
||||
}while((status == 0x80) && timeout);
|
||||
|
||||
if(timeout == 0)
|
||||
{
|
||||
*pStatus = CF_TIMEOUT_ERROR;
|
||||
}
|
||||
|
||||
timeout = 0xFFFF;
|
||||
|
||||
do
|
||||
{
|
||||
/* wait till the Status = 0x58 */
|
||||
status = *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
|
||||
timeout--;
|
||||
}while((status != 0x58) && timeout);
|
||||
|
||||
if(timeout == 0)
|
||||
{
|
||||
*pStatus = CF_TIMEOUT_ERROR;
|
||||
}
|
||||
|
||||
/* Read bytes */
|
||||
for(; index < CF_SECTOR_SIZE; index++)
|
||||
{
|
||||
*(uint16_t *)pBuffer++ = *(uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR);
|
||||
}
|
||||
|
||||
/* Update the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hpccard);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Write sector to PCCARD memory
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @param pBuffer: pointer to source write buffer
|
||||
* @param SectorAddress: Sector address to write
|
||||
* @param pStatus: pointer to CF status
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CF_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
|
||||
{
|
||||
uint32_t timeout = 0xFFFF, index = 0;
|
||||
uint8_t status;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hpccard);
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Update the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_BUSY;
|
||||
|
||||
/* Initialize CF status */
|
||||
*pStatus = CF_READY;
|
||||
|
||||
/* Set the parameters to write a sector */
|
||||
*(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_HIGH) = (uint16_t)0x00;
|
||||
*(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
|
||||
*(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD) = (uint16_t)0x30A0;
|
||||
|
||||
do
|
||||
{
|
||||
/* Wait till the Status = 0x58 */
|
||||
status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
|
||||
timeout--;
|
||||
}while((status != 0x58) && timeout);
|
||||
|
||||
if(timeout == 0)
|
||||
{
|
||||
*pStatus = CF_TIMEOUT_ERROR;
|
||||
}
|
||||
|
||||
/* Write bytes */
|
||||
for(; index < CF_SECTOR_SIZE; index++)
|
||||
{
|
||||
*(uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
|
||||
}
|
||||
|
||||
do
|
||||
{
|
||||
/* Wait till the Status = 0x50 */
|
||||
status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
|
||||
timeout--;
|
||||
}while((status != 0x50) && timeout);
|
||||
|
||||
if(timeout == 0)
|
||||
{
|
||||
*pStatus = CF_TIMEOUT_ERROR;
|
||||
}
|
||||
|
||||
/* Update the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hpccard);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Erase sector from PCCARD memory
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @param SectorAddress: Sector address to erase
|
||||
* @param pStatus: pointer to CF status
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
|
||||
{
|
||||
uint32_t timeout = 0x400;
|
||||
uint8_t status;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hpccard);
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Update the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_BUSY;
|
||||
|
||||
/* Initialize CF status */
|
||||
*pStatus = CF_READY;
|
||||
|
||||
/* Set the parameters to write a sector */
|
||||
*(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_LOW) = 0x00;
|
||||
*(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_HIGH) = 0x00;
|
||||
*(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_NUMBER) = SectorAddress;
|
||||
*(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_COUNT) = 0x01;
|
||||
*(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CARD_HEAD) = 0xA0;
|
||||
*(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD) = CF_ERASE_SECTOR_CMD;
|
||||
|
||||
/* wait till the CF is ready */
|
||||
status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
|
||||
|
||||
while((status != 0x50) && timeout)
|
||||
{
|
||||
status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
|
||||
timeout--;
|
||||
}
|
||||
|
||||
if(timeout == 0)
|
||||
{
|
||||
*pStatus = CF_TIMEOUT_ERROR;
|
||||
}
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hpccard);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset the PCCARD memory
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CF_Reset(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hpccard);
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Provide an SW reset and Read and verify the:
|
||||
- CF Configuration Option Register at address 0x98000200 --> 0x80
|
||||
- Card Configuration and Status Register at address 0x98000202 --> 0x00
|
||||
- Pin Replacement Register at address 0x98000204 --> 0x0C
|
||||
- Socket and Copy Register at address 0x98000206 --> 0x00
|
||||
*/
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_BUSY;
|
||||
|
||||
*(__IO uint8_t *)(0x98000202) = 0x01;
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hpccard);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles PCCARD device interrupt request.
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
/* Check PCCARD interrupt Rising edge flag */
|
||||
if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE))
|
||||
{
|
||||
/* PCCARD interrupt callback*/
|
||||
HAL_PCCARD_ITCallback(hpccard);
|
||||
|
||||
/* Clear PCCARD interrupt Rising edge pending bit */
|
||||
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE);
|
||||
}
|
||||
|
||||
/* Check PCCARD interrupt Level flag */
|
||||
if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_LEVEL))
|
||||
{
|
||||
/* PCCARD interrupt callback*/
|
||||
HAL_PCCARD_ITCallback(hpccard);
|
||||
|
||||
/* Clear PCCARD interrupt Level pending bit */
|
||||
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_LEVEL);
|
||||
}
|
||||
|
||||
/* Check PCCARD interrupt Falling edge flag */
|
||||
if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE))
|
||||
{
|
||||
/* PCCARD interrupt callback*/
|
||||
HAL_PCCARD_ITCallback(hpccard);
|
||||
|
||||
/* Clear PCCARD interrupt Falling edge pending bit */
|
||||
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE);
|
||||
}
|
||||
|
||||
/* Check PCCARD interrupt FIFO empty flag */
|
||||
if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FEMPT))
|
||||
{
|
||||
/* PCCARD interrupt callback*/
|
||||
HAL_PCCARD_ITCallback(hpccard);
|
||||
|
||||
/* Clear PCCARD interrupt FIFO empty pending bit */
|
||||
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FEMPT);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PCCARD interrupt feature callback
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PCCARD_ITCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCCARD_Group4 State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### PCCARD State functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the PCCARD controller
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief return the PCCARD controller state
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
return hpccard->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the compact flash memory status
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval New status of the CF operation. This parameter can be:
|
||||
* - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
|
||||
* a Timeout error
|
||||
* - CompactFlash_READY: when memory is ready for the next operation
|
||||
*
|
||||
*/
|
||||
CF_StatusTypedef HAL_CF_GetStatus(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
uint32_t timeout = 0x1000000, status_CF;
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||
{
|
||||
return CF_ONGOING;
|
||||
}
|
||||
|
||||
status_CF = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
|
||||
|
||||
while((status_CF == CF_BUSY) && timeout)
|
||||
{
|
||||
status_CF = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
|
||||
timeout--;
|
||||
}
|
||||
|
||||
if(timeout == 0)
|
||||
{
|
||||
status_CF = CF_TIMEOUT_ERROR;
|
||||
}
|
||||
|
||||
/* Return the operation status */
|
||||
return (CF_StatusTypedef) status_CF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the Compact Flash memory status using the Read status command
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval The status of the Compact Flash memory. This parameter can be:
|
||||
* - CompactFlash_BUSY: when memory is busy
|
||||
* - CompactFlash_READY: when memory is ready for the next operation
|
||||
* - CompactFlash_ERROR: when the previous operation gererates error
|
||||
*/
|
||||
CF_StatusTypedef HAL_CF_ReadStatus(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
uint8_t data = 0, status_CF = CF_BUSY;
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||
{
|
||||
return CF_ONGOING;
|
||||
}
|
||||
|
||||
/* Read status operation */
|
||||
data = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
|
||||
|
||||
if((data & CF_TIMEOUT_ERROR) == CF_TIMEOUT_ERROR)
|
||||
{
|
||||
status_CF = CF_TIMEOUT_ERROR;
|
||||
}
|
||||
else if((data & CF_READY) == CF_READY)
|
||||
{
|
||||
status_CF = CF_READY;
|
||||
}
|
||||
|
||||
return (CF_StatusTypedef) status_CF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
#endif /* HAL_PCCARD_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,431 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_rng.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief RNG HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Random Number Generator (RNG) peripheral:
|
||||
* + Initialization/de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The RNG HAL driver can be used as follows:
|
||||
|
||||
(#) Enable the RNG controller clock using __RNG_CLK_ENABLE() macro.
|
||||
(#) Activate the RNG peripheral using __HAL_RNG_ENABLE() macro.
|
||||
(#) Wait until the 32 bit Random Number Generator contains a valid
|
||||
random data using (polling/interrupt) mode.
|
||||
(#) Get the 32 bit random number using HAL_RNG_GetRandomNumber() function.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG
|
||||
* @brief RNG HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
|
||||
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define RNG_TIMEOUT_VALUE 1000
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RNG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the RNG according to the specified parameters
|
||||
in the RNG_InitTypeDef and create the associated handle
|
||||
(+) DeInitialize the RNG peripheral
|
||||
(+) Initialize the RNG MSP
|
||||
(+) DeInitialize RNG MSP
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the RNG according to the specified
|
||||
* parameters in the RNG_InitTypeDef and creates the associated handle.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* Check the RNG handle allocation */
|
||||
if(hrng == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if(hrng->State == HAL_RNG_STATE_RESET)
|
||||
{
|
||||
/* Init the low level hardware */
|
||||
HAL_RNG_MspInit(hrng);
|
||||
}
|
||||
/* Change RNG peripheral state */
|
||||
hrng->State = HAL_RNG_STATE_BUSY;
|
||||
|
||||
/* Enable the RNG Peripheral */
|
||||
__HAL_RNG_ENABLE(hrng);
|
||||
|
||||
/* Initialize the RNG state */
|
||||
hrng->State = HAL_RNG_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the RNG peripheral.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* Check the RNG peripheral state */
|
||||
if(hrng->State == HAL_RNG_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Update the RNG state */
|
||||
hrng->State = HAL_RNG_STATE_BUSY;
|
||||
|
||||
/* Disable the RNG Peripheral */
|
||||
__HAL_RNG_DISABLE(hrng);
|
||||
|
||||
/* Set the RNG registers to their reset values */
|
||||
hrng->Instance->CR &= 0xFFFFFFF3;
|
||||
hrng->Instance->SR &= 0xFFFFFF98;
|
||||
hrng->Instance->DR &= 0x0;
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_RNG_MspDeInit(hrng);
|
||||
|
||||
/* Update the RNG state */
|
||||
hrng->State = HAL_RNG_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hrng);
|
||||
|
||||
/* Return the function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the RNG MSP.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_RNG_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the RNG MSP.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_RNG_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Group2 Peripheral Control functions
|
||||
* @brief management functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Get the 32 bit Random number
|
||||
(+) Get the 32 bit Random number with interrupt enabled
|
||||
(+) Handle RNG interrupt request
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns a 32-bit random number.
|
||||
* @note Each time the random number data is read the RNG_FLAG_DRDY flag
|
||||
* is automatically cleared.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval 32-bit random number
|
||||
*/
|
||||
uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
uint32_t random32bit = 0;
|
||||
uint32_t tickstart = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hrng);
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Check if data register contains valid random data */
|
||||
while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Get a 32bit Random number */
|
||||
random32bit = hrng->Instance->DR;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hrng);
|
||||
|
||||
/* Return the 32 bit random number */
|
||||
return random32bit;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns a 32-bit random number with interrupt enabled.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval 32-bit random number
|
||||
*/
|
||||
uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
uint32_t random32bit = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hrng);
|
||||
|
||||
/* Change RNG peripheral state */
|
||||
hrng->State = HAL_RNG_STATE_BUSY;
|
||||
|
||||
/* Get a 32bit Random number */
|
||||
random32bit = hrng->Instance->DR;
|
||||
|
||||
/* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
|
||||
__HAL_RNG_ENABLE_IT(hrng);
|
||||
|
||||
/* Return the 32 bit random number */
|
||||
return random32bit;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handles RNG interrupt request.
|
||||
* @note In the case of a clock error, the RNG is no more able to generate
|
||||
* random numbers because the PLL48CLK clock is not correct. User has
|
||||
* to check that the clock controller is correctly configured to provide
|
||||
* the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_FLAG().
|
||||
* The clock error has no impact on the previously generated
|
||||
* random numbers, and the RNG_DR register contents can be used.
|
||||
* @note In the case of a seed error, the generation of random numbers is
|
||||
* interrupted as long as the SECS bit is '1'. If a number is
|
||||
* available in the RNG_DR register, it must not be used because it may
|
||||
* not have enough entropy. In this case, it is recommended to clear the
|
||||
* SEIS bit using __HAL_RNG_CLEAR_FLAG(), then disable and enable
|
||||
* the RNG peripheral to reinitialize and restart the RNG.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval None
|
||||
|
||||
*/
|
||||
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* RNG clock error interrupt occurred */
|
||||
if(__HAL_RNG_GET_FLAG(hrng, RNG_IT_CEI) != RESET)
|
||||
{
|
||||
HAL_RNG_ErrorCallback(hrng);
|
||||
|
||||
/* Clear the clock error flag */
|
||||
__HAL_RNG_CLEAR_FLAG(hrng, RNG_IT_CEI);
|
||||
|
||||
/* Change RNG peripheral state */
|
||||
hrng->State = HAL_RNG_STATE_ERROR;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hrng);
|
||||
}
|
||||
|
||||
/* RNG seed error interrupt occurred */
|
||||
if(__HAL_RNG_GET_FLAG(hrng, RNG_IT_SEI) != RESET)
|
||||
{
|
||||
HAL_RNG_ErrorCallback(hrng);
|
||||
|
||||
/* Clear the seed error flag */
|
||||
__HAL_RNG_CLEAR_FLAG(hrng, RNG_IT_SEI);
|
||||
|
||||
/* Change RNG peripheral state */
|
||||
hrng->State = HAL_RNG_STATE_ERROR;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hrng);
|
||||
}
|
||||
|
||||
/* Check RNG data ready flag */
|
||||
if(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != RESET)
|
||||
{
|
||||
/* Data Ready callback */
|
||||
HAL_RNG_ReadyCallback(hrng);
|
||||
|
||||
/* Change RNG peripheral state */
|
||||
hrng->State = HAL_RNG_STATE_READY;
|
||||
|
||||
/* Clear the RNG Data Ready flag */
|
||||
__HAL_RNG_CLEAR_FLAG(hrng, RNG_FLAG_DRDY);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hrng);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Data Ready callback in non-blocking mode.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
__weak void HAL_RNG_ReadyCallback(RNG_HandleTypeDef* hrng)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_RNG_ReadyCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RNG error callbacks.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_RNG_ErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the peripheral
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the RNG state.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
return hrng->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,846 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_sdram.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief SDRAM HAL module driver.
|
||||
* This file provides a generic firmware to drive SDRAM memories mounted
|
||||
* as external device.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This driver is a generic layered driver which contains a set of APIs used to
|
||||
control SDRAM memories. It uses the FMC layer functions to interface
|
||||
with SDRAM devices.
|
||||
The following sequence should be followed to configure the FMC to interface
|
||||
with SDRAM memories:
|
||||
|
||||
(#) Declare a SDRAM_HandleTypeDef handle structure, for example:
|
||||
SDRAM_HandleTypeDef hdsram
|
||||
|
||||
(++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
|
||||
values of the structure member.
|
||||
|
||||
(++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
|
||||
base register instance for NOR or SDRAM device
|
||||
|
||||
(#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
|
||||
FMC_SDRAM_TimingTypeDef Timing;
|
||||
and fill its fields with the allowed values of the structure member.
|
||||
|
||||
(#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
|
||||
performs the following sequence:
|
||||
|
||||
(##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
|
||||
(##) Control register configuration using the FMC SDRAM interface function
|
||||
FMC_SDRAM_Init()
|
||||
(##) Timing register configuration using the FMC SDRAM interface function
|
||||
FMC_SDRAM_Timing_Init()
|
||||
(##) Program the SDRAM external device by applying its initialization sequence
|
||||
according to the device plugged in your hardware. This step is mandatory
|
||||
for accessing the SDRAM device.
|
||||
|
||||
(#) At this stage you can perform read/write accesses from/to the memory connected
|
||||
to the SDRAM Bank. You can perform either polling or DMA transfer using the
|
||||
following APIs:
|
||||
(++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
|
||||
(++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
|
||||
|
||||
(#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
|
||||
HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
|
||||
the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
|
||||
device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
|
||||
structure.
|
||||
|
||||
(#) You can continuously monitor the SDRAM device HAL state by calling the function
|
||||
HAL_SDRAM_GetState()
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SDRAM
|
||||
* @brief SDRAM driver modules
|
||||
* @{
|
||||
*/
|
||||
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SDRAM_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SDRAM_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### SDRAM Initialization and de_initialization functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to initialize/de-initialize
|
||||
the SDRAM memory
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Performs the SDRAM device initialization sequence.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @param Timing: Pointer to SDRAM control timing structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
|
||||
{
|
||||
/* Check the SDRAM handle parameter */
|
||||
if(hsdram == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if(hsdram->State == HAL_SDRAM_STATE_RESET)
|
||||
{
|
||||
/* Initialize the low level hardware (MSP) */
|
||||
HAL_SDRAM_MspInit(hsdram);
|
||||
}
|
||||
|
||||
/* Initialize the SDRAM controller state */
|
||||
hsdram->State = HAL_SDRAM_STATE_BUSY;
|
||||
|
||||
/* Initialize SDRAM control Interface */
|
||||
FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
|
||||
|
||||
/* Initialize SDRAM timing Interface */
|
||||
FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
|
||||
|
||||
/* Update the SDRAM controller state */
|
||||
hsdram->State = HAL_SDRAM_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Perform the SDRAM device initialization sequence.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
|
||||
{
|
||||
/* Initialize the low level hardware (MSP) */
|
||||
HAL_SDRAM_MspDeInit(hsdram);
|
||||
|
||||
/* Configure the SDRAM registers with their reset values */
|
||||
FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
|
||||
|
||||
/* Reset the SDRAM controller state */
|
||||
hsdram->State = HAL_SDRAM_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hsdram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SDRAM MSP Init.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
|
||||
{
|
||||
/* NOTE: This function Should not be modified, when the callback is needed,
|
||||
the HAL_SDRAM_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SDRAM MSP DeInit.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
|
||||
{
|
||||
/* NOTE: This function Should not be modified, when the callback is needed,
|
||||
the HAL_SDRAM_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles SDRAM refresh error interrupt request.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
|
||||
{
|
||||
/* Check SDRAM interrupt Rising edge flag */
|
||||
if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
|
||||
{
|
||||
/* SDRAM refresh error interrupt callback */
|
||||
HAL_SDRAM_RefreshErrorCallback(hsdram);
|
||||
|
||||
/* Clear SDRAM refresh error interrupt pending bit */
|
||||
__FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SDRAM Refresh error callback.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
|
||||
{
|
||||
/* NOTE: This function Should not be modified, when the callback is needed,
|
||||
the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA transfer complete callback.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* NOTE: This function Should not be modified, when the callback is needed,
|
||||
the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA transfer complete error callback.
|
||||
* @param hdma: DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* NOTE: This function Should not be modified, when the callback is needed,
|
||||
the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDRAM_Group2 Input and Output functions
|
||||
* @brief Input Output and memory control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### SDRAM Input and Output functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to use and control the SDRAM memory
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reads 8-bit data buffer from the SDRAM memory.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @param pAddress: Pointer to read start address
|
||||
* @param pDstBuffer: Pointer to destination buffer
|
||||
* @param BufferSize: Size of the buffer to read from memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
|
||||
{
|
||||
__IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsdram);
|
||||
|
||||
/* Check the SDRAM controller state */
|
||||
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Read data from source */
|
||||
for(; BufferSize != 0; BufferSize--)
|
||||
{
|
||||
*pDstBuffer = *(__IO uint8_t *)pSdramAddress;
|
||||
pDstBuffer++;
|
||||
pSdramAddress++;
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hsdram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Writes 8-bit data buffer to SDRAM memory.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @param pAddress: Pointer to write start address
|
||||
* @param pSrcBuffer: Pointer to source buffer to write
|
||||
* @param BufferSize: Size of the buffer to write to memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
|
||||
{
|
||||
__IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
|
||||
uint32_t tmp = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsdram);
|
||||
|
||||
/* Check the SDRAM controller state */
|
||||
tmp = hsdram->State;
|
||||
|
||||
if(tmp == HAL_SDRAM_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write data to memory */
|
||||
for(; BufferSize != 0; BufferSize--)
|
||||
{
|
||||
*(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
|
||||
pSrcBuffer++;
|
||||
pSdramAddress++;
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hsdram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Reads 16-bit data buffer from the SDRAM memory.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @param pAddress: Pointer to read start address
|
||||
* @param pDstBuffer: Pointer to destination buffer
|
||||
* @param BufferSize: Size of the buffer to read from memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
|
||||
{
|
||||
__IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsdram);
|
||||
|
||||
/* Check the SDRAM controller state */
|
||||
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Read data from source */
|
||||
for(; BufferSize != 0; BufferSize--)
|
||||
{
|
||||
*pDstBuffer = *(__IO uint16_t *)pSdramAddress;
|
||||
pDstBuffer++;
|
||||
pSdramAddress++;
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hsdram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes 16-bit data buffer to SDRAM memory.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @param pAddress: Pointer to write start address
|
||||
* @param pSrcBuffer: Pointer to source buffer to write
|
||||
* @param BufferSize: Size of the buffer to write to memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
|
||||
{
|
||||
__IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
|
||||
uint32_t tmp = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsdram);
|
||||
|
||||
/* Check the SDRAM controller state */
|
||||
tmp = hsdram->State;
|
||||
|
||||
if(tmp == HAL_SDRAM_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write data to memory */
|
||||
for(; BufferSize != 0; BufferSize--)
|
||||
{
|
||||
*(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
|
||||
pSrcBuffer++;
|
||||
pSdramAddress++;
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hsdram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads 32-bit data buffer from the SDRAM memory.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @param pAddress: Pointer to read start address
|
||||
* @param pDstBuffer: Pointer to destination buffer
|
||||
* @param BufferSize: Size of the buffer to read from memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
||||
{
|
||||
__IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsdram);
|
||||
|
||||
/* Check the SDRAM controller state */
|
||||
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Read data from source */
|
||||
for(; BufferSize != 0; BufferSize--)
|
||||
{
|
||||
*pDstBuffer = *(__IO uint32_t *)pSdramAddress;
|
||||
pDstBuffer++;
|
||||
pSdramAddress++;
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hsdram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes 32-bit data buffer to SDRAM memory.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @param pAddress: Pointer to write start address
|
||||
* @param pSrcBuffer: Pointer to source buffer to write
|
||||
* @param BufferSize: Size of the buffer to write to memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
||||
{
|
||||
__IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
|
||||
uint32_t tmp = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsdram);
|
||||
|
||||
/* Check the SDRAM controller state */
|
||||
tmp = hsdram->State;
|
||||
|
||||
if(tmp == HAL_SDRAM_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write data to memory */
|
||||
for(; BufferSize != 0; BufferSize--)
|
||||
{
|
||||
*(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
|
||||
pSrcBuffer++;
|
||||
pSdramAddress++;
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hsdram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads a Words data from the SDRAM memory using DMA transfer.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @param pAddress: Pointer to read start address
|
||||
* @param pDstBuffer: Pointer to destination buffer
|
||||
* @param BufferSize: Size of the buffer to read from memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsdram);
|
||||
|
||||
/* Check the SDRAM controller state */
|
||||
tmp = hsdram->State;
|
||||
|
||||
if(tmp == HAL_SDRAM_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Configure DMA user callbacks */
|
||||
hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
|
||||
hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
|
||||
|
||||
/* Enable the DMA Stream */
|
||||
HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hsdram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @param pAddress: Pointer to write start address
|
||||
* @param pSrcBuffer: Pointer to source buffer to write
|
||||
* @param BufferSize: Size of the buffer to write to memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsdram);
|
||||
|
||||
/* Check the SDRAM controller state */
|
||||
tmp = hsdram->State;
|
||||
|
||||
if(tmp == HAL_SDRAM_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Configure DMA user callbacks */
|
||||
hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
|
||||
hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
|
||||
|
||||
/* Enable the DMA Stream */
|
||||
HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hsdram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDRAM_Group3 Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### SDRAM Control functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control dynamically
|
||||
the SDRAM interface.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables dynamically SDRAM write protection.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
|
||||
{
|
||||
/* Check the SDRAM controller state */
|
||||
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Update the SDRAM state */
|
||||
hsdram->State = HAL_SDRAM_STATE_BUSY;
|
||||
|
||||
/* Enable write protection */
|
||||
FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
|
||||
|
||||
/* Update the SDRAM state */
|
||||
hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables dynamically SDRAM write protection.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
|
||||
{
|
||||
/* Check the SDRAM controller state */
|
||||
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Update the SDRAM state */
|
||||
hsdram->State = HAL_SDRAM_STATE_BUSY;
|
||||
|
||||
/* Disable write protection */
|
||||
FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
|
||||
|
||||
/* Update the SDRAM state */
|
||||
hsdram->State = HAL_SDRAM_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sends Command to the SDRAM bank.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @param Command: SDRAM command structure
|
||||
* @param Timeout: Timeout duration
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
|
||||
{
|
||||
/* Check the SDRAM controller state */
|
||||
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Update the SDRAM state */
|
||||
hsdram->State = HAL_SDRAM_STATE_BUSY;
|
||||
|
||||
/* Send SDRAM command */
|
||||
FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
|
||||
|
||||
/* Update the SDRAM controller state state */
|
||||
if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
|
||||
{
|
||||
hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
|
||||
}
|
||||
else
|
||||
{
|
||||
hsdram->State = HAL_SDRAM_STATE_READY;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Programs the SDRAM Memory Refresh rate.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @param RefreshRate: The SDRAM refresh rate value
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
|
||||
{
|
||||
/* Check the SDRAM controller state */
|
||||
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Update the SDRAM state */
|
||||
hsdram->State = HAL_SDRAM_STATE_BUSY;
|
||||
|
||||
/* Program the refresh rate */
|
||||
FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
|
||||
|
||||
/* Update the SDRAM state */
|
||||
hsdram->State = HAL_SDRAM_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @param AutoRefreshNumber: The SDRAM auto Refresh number
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
|
||||
{
|
||||
/* Check the SDRAM controller state */
|
||||
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Update the SDRAM state */
|
||||
hsdram->State = HAL_SDRAM_STATE_BUSY;
|
||||
|
||||
/* Set the Auto-Refresh number */
|
||||
FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
|
||||
|
||||
/* Update the SDRAM state */
|
||||
hsdram->State = HAL_SDRAM_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the SDRAM memory current mode.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @retval The SDRAM memory mode.
|
||||
*/
|
||||
uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
|
||||
{
|
||||
/* Return the SDRAM memory current mode */
|
||||
return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDRAM_Group4 State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### SDRAM State functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the SDRAM controller
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the SDRAM state.
|
||||
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SDRAM module.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
|
||||
{
|
||||
return hsdram->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,681 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_sram.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief SRAM HAL module driver.
|
||||
* This file provides a generic firmware to drive SRAM memories
|
||||
* mounted as external device.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This driver is a generic layered driver which contains a set of APIs used to
|
||||
control SRAM memories. It uses the FMC layer functions to interface
|
||||
with SRAM devices.
|
||||
The following sequence should be followed to configure the FMC/FSMC to interface
|
||||
with SRAM/PSRAM memories:
|
||||
|
||||
(#) Declare a SRAM_HandleTypeDef handle structure, for example:
|
||||
SRAM_HandleTypeDef hsram; and:
|
||||
|
||||
(++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
|
||||
values of the structure member.
|
||||
|
||||
(++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
|
||||
base register instance for NOR or SRAM device
|
||||
|
||||
(++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
|
||||
base register instance for NOR or SRAM extended mode
|
||||
|
||||
(#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
|
||||
mode timings; for example:
|
||||
FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
|
||||
and fill its fields with the allowed values of the structure member.
|
||||
|
||||
(#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
|
||||
performs the following sequence:
|
||||
|
||||
(##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
|
||||
(##) Control register configuration using the FMC NORSRAM interface function
|
||||
FMC_NORSRAM_Init()
|
||||
(##) Timing register configuration using the FMC NORSRAM interface function
|
||||
FMC_NORSRAM_Timing_Init()
|
||||
(##) Extended mode Timing register configuration using the FMC NORSRAM interface function
|
||||
FMC_NORSRAM_Extended_Timing_Init()
|
||||
(##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
|
||||
|
||||
(#) At this stage you can perform read/write accesses from/to the memory connected
|
||||
to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
|
||||
following APIs:
|
||||
(++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
|
||||
(++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
|
||||
|
||||
(#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
|
||||
HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
|
||||
|
||||
(#) You can continuously monitor the SRAM device HAL state by calling the function
|
||||
HAL_SRAM_GetState()
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SRAM
|
||||
* @brief SRAM driver modules
|
||||
* @{
|
||||
*/
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SRAM_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SRAM_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### SRAM Initialization and de_initialization functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to initialize/de-initialize
|
||||
the SRAM memory
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Performs the SRAM device initialization sequence
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @param Timing: Pointer to SRAM control timing structure
|
||||
* @param ExtTiming: Pointer to SRAM extended mode timing structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
|
||||
{
|
||||
/* Check the SRAM handle parameter */
|
||||
if(hsram == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if(hsram->State == HAL_SRAM_STATE_RESET)
|
||||
{
|
||||
/* Initialize the low level hardware (MSP) */
|
||||
HAL_SRAM_MspInit(hsram);
|
||||
}
|
||||
|
||||
/* Initialize SRAM control Interface */
|
||||
FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
|
||||
|
||||
/* Initialize SRAM timing Interface */
|
||||
FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
|
||||
|
||||
/* Initialize SRAM extended mode timing Interface */
|
||||
FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
|
||||
|
||||
/* Enable the NORSRAM device */
|
||||
__FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Performs the SRAM device De-initialization sequence.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
|
||||
{
|
||||
/* De-Initialize the low level hardware (MSP) */
|
||||
HAL_SRAM_MspDeInit(hsram);
|
||||
|
||||
/* Configure the SRAM registers with their reset values */
|
||||
FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
|
||||
|
||||
hsram->State = HAL_SRAM_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SRAM MSP Init.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SRAM_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SRAM MSP DeInit.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SRAM_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA transfer complete callback.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA transfer complete error callback.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SRAM_Group2 Input and Output functions
|
||||
* @brief Input Output and memory control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### SRAM Input and Output functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to use and control the SRAM memory
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reads 8-bit buffer from SRAM memory.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @param pAddress: Pointer to read start address
|
||||
* @param pDstBuffer: Pointer to destination buffer
|
||||
* @param BufferSize: Size of the buffer to read from memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
|
||||
{
|
||||
__IO uint8_t * pSramAddress = (uint8_t *)pAddress;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Read data from memory */
|
||||
for(; BufferSize != 0; BufferSize--)
|
||||
{
|
||||
*pDstBuffer = *(__IO uint8_t *)pSramAddress;
|
||||
pDstBuffer++;
|
||||
pSramAddress++;
|
||||
}
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes 8-bit buffer to SRAM memory.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @param pAddress: Pointer to write start address
|
||||
* @param pSrcBuffer: Pointer to source buffer to write
|
||||
* @param BufferSize: Size of the buffer to write to memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
|
||||
{
|
||||
__IO uint8_t * pSramAddress = (uint8_t *)pAddress;
|
||||
|
||||
/* Check the SRAM controller state */
|
||||
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Write data to memory */
|
||||
for(; BufferSize != 0; BufferSize--)
|
||||
{
|
||||
*(__IO uint8_t *)pSramAddress = *pSrcBuffer;
|
||||
pSrcBuffer++;
|
||||
pSramAddress++;
|
||||
}
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads 16-bit buffer from SRAM memory.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @param pAddress: Pointer to read start address
|
||||
* @param pDstBuffer: Pointer to destination buffer
|
||||
* @param BufferSize: Size of the buffer to read from memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
|
||||
{
|
||||
__IO uint16_t * pSramAddress = (uint16_t *)pAddress;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Read data from memory */
|
||||
for(; BufferSize != 0; BufferSize--)
|
||||
{
|
||||
*pDstBuffer = *(__IO uint16_t *)pSramAddress;
|
||||
pDstBuffer++;
|
||||
pSramAddress++;
|
||||
}
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes 16-bit buffer to SRAM memory.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @param pAddress: Pointer to write start address
|
||||
* @param pSrcBuffer: Pointer to source buffer to write
|
||||
* @param BufferSize: Size of the buffer to write to memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
|
||||
{
|
||||
__IO uint16_t * pSramAddress = (uint16_t *)pAddress;
|
||||
|
||||
/* Check the SRAM controller state */
|
||||
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Write data to memory */
|
||||
for(; BufferSize != 0; BufferSize--)
|
||||
{
|
||||
*(__IO uint16_t *)pSramAddress = *pSrcBuffer;
|
||||
pSrcBuffer++;
|
||||
pSramAddress++;
|
||||
}
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads 32-bit buffer from SRAM memory.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @param pAddress: Pointer to read start address
|
||||
* @param pDstBuffer: Pointer to destination buffer
|
||||
* @param BufferSize: Size of the buffer to read from memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Read data from memory */
|
||||
for(; BufferSize != 0; BufferSize--)
|
||||
{
|
||||
*pDstBuffer = *(__IO uint32_t *)pAddress;
|
||||
pDstBuffer++;
|
||||
pAddress++;
|
||||
}
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes 32-bit buffer to SRAM memory.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @param pAddress: Pointer to write start address
|
||||
* @param pSrcBuffer: Pointer to source buffer to write
|
||||
* @param BufferSize: Size of the buffer to write to memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
||||
{
|
||||
/* Check the SRAM controller state */
|
||||
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Write data to memory */
|
||||
for(; BufferSize != 0; BufferSize--)
|
||||
{
|
||||
*(__IO uint32_t *)pAddress = *pSrcBuffer;
|
||||
pSrcBuffer++;
|
||||
pAddress++;
|
||||
}
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads a Words data from the SRAM memory using DMA transfer.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @param pAddress: Pointer to read start address
|
||||
* @param pDstBuffer: Pointer to destination buffer
|
||||
* @param BufferSize: Size of the buffer to read from memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Configure DMA user callbacks */
|
||||
hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
|
||||
hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
|
||||
|
||||
/* Enable the DMA Stream */
|
||||
HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes a Words data buffer to SRAM memory using DMA transfer.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @param pAddress: Pointer to write start address
|
||||
* @param pSrcBuffer: Pointer to source buffer to write
|
||||
* @param BufferSize: Size of the buffer to write to memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
||||
{
|
||||
/* Check the SRAM controller state */
|
||||
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Configure DMA user callbacks */
|
||||
hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
|
||||
hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
|
||||
|
||||
/* Enable the DMA Stream */
|
||||
HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SRAM_Group3 Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### SRAM Control functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control dynamically
|
||||
the SRAM interface.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables dynamically SRAM write operation.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Enable write operation */
|
||||
FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables dynamically SRAM write operation.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Disable write operation */
|
||||
FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_PROTECTED;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SRAM_Group4 State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### SRAM State functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the SRAM controller
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the SRAM controller state
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
|
||||
{
|
||||
return hsram->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,449 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_wwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief WWDG HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Window Watchdog (WWDG) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
* + Peripheral State functions
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### WWDG specific features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
Once enabled the WWDG generates a system reset on expiry of a programmed
|
||||
time period, unless the program refreshes the counter (downcounter)
|
||||
before reaching 0x3F value (i.e. a reset is generated when the counter
|
||||
value rolls over from 0x40 to 0x3F).
|
||||
|
||||
(+) An MCU reset is also generated if the counter value is refreshed
|
||||
before the counter has reached the refresh window value. This
|
||||
implies that the counter must be refreshed in a limited window.
|
||||
(+) Once enabled the WWDG cannot be disabled except by a system reset.
|
||||
(+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
|
||||
reset occurs.
|
||||
(+) The WWDG counter input clock is derived from the APB clock divided
|
||||
by a programmable prescaler.
|
||||
(+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
|
||||
(+) WWDG timeout (mS) = 1000 * Counter / WWDG clock
|
||||
(+) WWDG Counter refresh is allowed between the following limits :
|
||||
(++) min time (mS) = 1000 * (Counter – Window) / WWDG clock
|
||||
(++) max time (mS) = 1000 * (Counter – 0x40) / WWDG clock
|
||||
|
||||
(+) Min-max timeout value at 50 MHz(PCLK1): 81.9 us / 41.9 ms
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) Enable WWDG APB1 clock using __WWDG_CLK_ENABLE().
|
||||
(+) Set the WWDG prescaler, refresh window and counter value
|
||||
using HAL_WWDG_Init() function.
|
||||
(+) Start the WWDG using HAL_WWDG_Start() function.
|
||||
When the WWDG is enabled the counter value should be configured to
|
||||
a value greater than 0x40 to prevent generating an immediate reset.
|
||||
(+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
|
||||
generated when the counter reaches 0x40, and then start the WWDG using
|
||||
HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
|
||||
add his own code by customization of function pointer HAL_WWDG_WakeupCallback
|
||||
Once enabled, EWI interrupt cannot be disabled except by a system reset.
|
||||
(+) Then the application program must refresh the WWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
HAL_WWDG_Refresh() function. This operation must occur only when
|
||||
the counter is lower than the refresh window value already programmed.
|
||||
|
||||
*** WWDG HAL driver macros list ***
|
||||
==================================
|
||||
[..]
|
||||
Below the list of most used macros in WWDG HAL driver.
|
||||
|
||||
(+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
|
||||
(+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
|
||||
(+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
|
||||
(+) __HAL_WWDG_ENABLE_IT: Enables the WWDG early wakeup interrupt
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG
|
||||
* @brief WWDG HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to:
|
||||
(+) Initialize the WWDG according to the specified parameters
|
||||
in the WWDG_InitTypeDef and create the associated handle
|
||||
(+) DeInitialize the WWDG peripheral
|
||||
(+) Initialize the WWDG MSP
|
||||
(+) DeInitialize the WWDG MSP
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the WWDG according to the specified
|
||||
* parameters in the WWDG_InitTypeDef and creates the associated handle.
|
||||
* @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified WWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
|
||||
{
|
||||
/* Check the WWDG handle allocation */
|
||||
if(hwwdg == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
|
||||
assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
|
||||
assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
|
||||
assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
|
||||
|
||||
if(hwwdg->State == HAL_WWDG_STATE_RESET)
|
||||
{
|
||||
/* Init the low level hardware */
|
||||
HAL_WWDG_MspInit(hwwdg);
|
||||
}
|
||||
|
||||
/* Change WWDG peripheral state */
|
||||
hwwdg->State = HAL_WWDG_STATE_BUSY;
|
||||
|
||||
/* Set WWDG Prescaler and Window */
|
||||
MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window));
|
||||
/* Set WWDG Counter */
|
||||
MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter);
|
||||
|
||||
/* Change WWDG peripheral state */
|
||||
hwwdg->State = HAL_WWDG_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the WWDG peripheral.
|
||||
* @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified WWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg)
|
||||
{
|
||||
/* Check the WWDG handle allocation */
|
||||
if(hwwdg == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
|
||||
|
||||
/* Change WWDG peripheral state */
|
||||
hwwdg->State = HAL_WWDG_STATE_BUSY;
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_WWDG_MspDeInit(hwwdg);
|
||||
|
||||
/* Reset WWDG Control register */
|
||||
hwwdg->Instance->CR = (uint32_t)0x0000007F;
|
||||
|
||||
/* Reset WWDG Configuration register */
|
||||
hwwdg->Instance->CFR = (uint32_t)0x0000007F;
|
||||
|
||||
/* Reset WWDG Status register */
|
||||
hwwdg->Instance->SR = 0;
|
||||
|
||||
/* Change WWDG peripheral state */
|
||||
hwwdg->State = HAL_WWDG_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hwwdg);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the WWDG MSP.
|
||||
* @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified WWDG module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
|
||||
{
|
||||
/* NOTE: This function Should not be modified, when the callback is needed,
|
||||
the HAL_WWDG_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the WWDG MSP.
|
||||
* @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified WWDG module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
|
||||
{
|
||||
/* NOTE: This function Should not be modified, when the callback is needed,
|
||||
the HAL_WWDG_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### IO operation functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to:
|
||||
(+) Start the WWDG.
|
||||
(+) Refresh the WWDG.
|
||||
(+) Handle WWDG interrupt request.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Starts the WWDG.
|
||||
* @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified WWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hwwdg);
|
||||
|
||||
/* Change WWDG peripheral state */
|
||||
hwwdg->State = HAL_WWDG_STATE_BUSY;
|
||||
|
||||
/* Enable the peripheral */
|
||||
__HAL_WWDG_ENABLE(hwwdg);
|
||||
|
||||
/* Change WWDG peripheral state */
|
||||
hwwdg->State = HAL_WWDG_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hwwdg);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts the WWDG with interrupt enabled.
|
||||
* @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified WWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hwwdg);
|
||||
|
||||
/* Change WWDG peripheral state */
|
||||
hwwdg->State = HAL_WWDG_STATE_BUSY;
|
||||
|
||||
/* Enable the Early Wakeup Interrupt */
|
||||
__HAL_WWDG_ENABLE_IT(WWDG_IT_EWI);
|
||||
|
||||
/* Enable the peripheral */
|
||||
__HAL_WWDG_ENABLE(hwwdg);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Refreshes the WWDG.
|
||||
* @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified WWDG module.
|
||||
* @param Counter: value of counter to put in WWDG counter
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hwwdg);
|
||||
|
||||
/* Change WWDG peripheral state */
|
||||
hwwdg->State = HAL_WWDG_STATE_BUSY;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_COUNTER(Counter));
|
||||
|
||||
/* Write to WWDG CR the WWDG Counter value to refresh with */
|
||||
MODIFY_REG(hwwdg->Instance->CR, (uint32_t)WWDG_CR_T, Counter);
|
||||
|
||||
/* Change WWDG peripheral state */
|
||||
hwwdg->State = HAL_WWDG_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hwwdg);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handles WWDG interrupt request.
|
||||
* @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
|
||||
* or data logging must be performed before the actual reset is generated.
|
||||
* The EWI interrupt is enabled using __HAL_WWDG_ENABLE_IT() macro.
|
||||
* When the downcounter reaches the value 0x40, and EWI interrupt is
|
||||
* generated and the corresponding Interrupt Service Routine (ISR) can
|
||||
* be used to trigger specific actions (such as communications or data
|
||||
* logging), before resetting the device.
|
||||
* @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified WWDG module.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
|
||||
{
|
||||
/* WWDG Early Wakeup Interrupt occurred */
|
||||
if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
|
||||
{
|
||||
/* Early Wakeup callback */
|
||||
HAL_WWDG_WakeupCallback(hwwdg);
|
||||
|
||||
/* Change WWDG peripheral state */
|
||||
hwwdg->State = HAL_WWDG_STATE_READY;
|
||||
|
||||
/* Clear the WWDG Data Ready flag */
|
||||
__HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hwwdg);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Early Wakeup WWDG callback.
|
||||
* @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified WWDG module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)
|
||||
{
|
||||
/* NOTE: This function Should not be modified, when the callback is needed,
|
||||
the HAL_WWDG_WakeupCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral State functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the peripheral
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the WWDG state.
|
||||
* @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified WWDG module.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg)
|
||||
{
|
||||
return hwwdg->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,463 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief HAL module driver.
|
||||
* This is the common part of the HAL initialization
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The common HAL driver contains a set of generic and common APIs that can be
|
||||
used by the PPP peripheral drivers and the user to start using the HAL.
|
||||
[..]
|
||||
The HAL contains two APIs categories:
|
||||
(+) HAL Initialization and de-initialization functions
|
||||
(+) HAL Control functions
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL
|
||||
* @brief HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief STM32F3xx HAL Driver version number V1.0.1
|
||||
*/
|
||||
#define __STM32F3xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32F3xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
||||
#define __STM32F3xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
|
||||
#define __STM32F3xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24)\
|
||||
|(__STM32F3xx_HAL_VERSION_SUB1 << 16)\
|
||||
|(__STM32F3xx_HAL_VERSION_SUB2 << 8 )\
|
||||
|(__STM32F3xx_HAL_VERSION_RC))
|
||||
|
||||
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
static __IO uint32_t uwTick;
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Group1 Initialization and de-initialization Functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initializes the Flash interface the NVIC allocation and initial clock
|
||||
configuration. It initializes the systick also when timeout is needed
|
||||
and the backup domain when enabled.
|
||||
(+) de-Initializes common part of the HAL
|
||||
(+) Configure The time base source to have 1ms time base with a dedicated
|
||||
Tick interrupt priority.
|
||||
(++) Systick timer is used by default as source of time base, but user
|
||||
can eventually implement his proper time base source (a general purpose
|
||||
timer for example or other time source), keeping in mind that Time base
|
||||
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
|
||||
handled in milliseconds basis.
|
||||
(++) Time base configuration function (HAL_InitTick ()) is called automatically
|
||||
at the beginning of the program after reset by HAL_Init() or at any time
|
||||
when clock is configured, by HAL_RCC_ClockConfig().
|
||||
(++) Source of time base is configured to generate interrupts at regular
|
||||
time intervals. Care must be taken if HAL_Delay() is called from a
|
||||
peripheral ISR process, the Tick interrupt line must have higher priority
|
||||
(numerically lower) than the peripheral interrupt. Otherwise the caller
|
||||
ISR process will be blocked.
|
||||
(++) functions affecting time base configurations are declared as __Weak
|
||||
to make override possible in case of other implementations in user file.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the Flash prefetch,
|
||||
* Configures time base source, NVIC and Low level hardware
|
||||
*
|
||||
* @note This function is called at the beginning of program after reset and before
|
||||
* the clock configuration
|
||||
*
|
||||
* @note The Systick configuration is based on HSI clock, as HSI is the clock
|
||||
* used after a system Reset and the NVIC configuration is set to Priority group 4
|
||||
*
|
||||
* @note The time base configuration is based on MSI clock when exting from Reset.
|
||||
* Once done, time base tick start incrementing.
|
||||
* In the default implementation,Systick is used as source of time base.
|
||||
* the tick variable is incremented each 1ms in its ISR.
|
||||
*
|
||||
* @note
|
||||
* @param None
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_Init(void)
|
||||
{
|
||||
/* Configure Flash prefetch */
|
||||
#if (PREFETCH_ENABLE != 0)
|
||||
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
||||
#endif /* PREFETCH_ENABLE */
|
||||
|
||||
/* Set Interrupt Group Priority */
|
||||
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
||||
|
||||
/* Enable systick and configure 1ms tick (default clock after Reset is HSI) */
|
||||
HAL_InitTick(TICK_INT_PRIORITY);
|
||||
|
||||
/* Init the low level hardware */
|
||||
HAL_MspInit();
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function de-Initializes common part of the HAL and stops the source
|
||||
* of time base.
|
||||
* This function is optional.
|
||||
* @param None
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DeInit(void)
|
||||
{
|
||||
/* Reset of all peripherals */
|
||||
__APB1_FORCE_RESET();
|
||||
__APB1_RELEASE_RESET();
|
||||
|
||||
__APB2_FORCE_RESET();
|
||||
__APB2_RELEASE_RESET();
|
||||
|
||||
__AHB_FORCE_RESET();
|
||||
__AHB_RELEASE_RESET();
|
||||
|
||||
/* De-Init the low level hardware */
|
||||
HAL_MspDeInit();
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the MSP.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_MspInit(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the MSP.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_MspDeInit(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the source of the time base.
|
||||
* The time source is configured to have 1ms time base with a dedicated
|
||||
* Tick interrupt priority.
|
||||
* @note This function is called automatically at the beginning of program after
|
||||
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
|
||||
* @note In the default implementation , SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals.
|
||||
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
|
||||
* The the SysTick interrupt must have higher priority (numerically lower)
|
||||
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
|
||||
* The function is declared as __Weak to be overwritten in case of other
|
||||
* implementation in user file.
|
||||
* @param TickPriority: Tick interrupt priorty.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
||||
|
||||
{
|
||||
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
||||
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
|
||||
|
||||
/*Configure the SysTick IRQ priority */
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/** @defgroup HAL_Group2 HAL Control functions
|
||||
* @brief HAL Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### HAL Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) provide a tick value in millisecond
|
||||
(+) provide a blocking delay in millisecond
|
||||
(+) Suspend the time base source interrupt
|
||||
(+) Resume the time base source interrupt
|
||||
(+) Get the HAL API driver version
|
||||
(+) Get the device identifier
|
||||
(+) Get the device revision identifier
|
||||
(+) Enable/Disable Debug module during Sleep mode
|
||||
(+) Enable/Disable Debug module during STOP mode
|
||||
(+) Enable/Disable Debug module during STANDBY mode
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function is called to increment a global variable "uwTick"
|
||||
* used as application time base.
|
||||
* @note In the default implemetation, this variable is incremented each 1ms
|
||||
* in Systick ISR.
|
||||
* The function is declared as __Weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_IncTick(void)
|
||||
{
|
||||
uwTick++;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Povides a tick value in millisecond.
|
||||
* @note The function is declared as __Weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param None
|
||||
* @retval tick value
|
||||
*/
|
||||
__weak uint32_t HAL_GetTick(void)
|
||||
{
|
||||
return uwTick;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function provides accurate delay (in milliseconds) based
|
||||
* on variable incremented.
|
||||
* @note In the default implementation , SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals where uwTick
|
||||
* is incremented.
|
||||
* The function is declared as __Weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param Delay: specifies the delay time length, in milliseconds.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_Delay(__IO uint32_t Delay)
|
||||
{
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
while((HAL_GetTick() - tickstart) < Delay)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
|
||||
* is called, the the SysTick interrupt will be disabled and so Tick increment
|
||||
* is suspended.
|
||||
* The function is declared as __Weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SuspendTick(void)
|
||||
|
||||
{
|
||||
/* Disable SysTick Interrupt */
|
||||
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
|
||||
* is called, the the SysTick interrupt will be enabled and so Tick increment
|
||||
* is resumed.
|
||||
* The function is declared as __Weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ResumeTick(void)
|
||||
{
|
||||
/* Enable SysTick Interrupt */
|
||||
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function returns the HAL revision
|
||||
* @param None
|
||||
* @retval version : 0xXYZR (8bits for each decimal, R for RC)
|
||||
*/
|
||||
uint32_t HAL_GetHalVersion(void)
|
||||
{
|
||||
return __STM32F3xx_HAL_VERSION;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device revision identifier.
|
||||
* @param None
|
||||
* @retval Device revision identifier
|
||||
*/
|
||||
uint32_t HAL_GetREVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) >> 16);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device identifier.
|
||||
* @param None
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetDEVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during SLEEP mode
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_EnableDBGSleepMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during SLEEP mode
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DisableDBGSleepMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STOP mode
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_EnableDBGStopMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STOP mode
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DisableDBGStopMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STANDBY mode
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_EnableDBGStandbyMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STANDBY mode
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DisableDBGStandbyMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,675 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief This file contains all the functions prototypes for the HAL
|
||||
* module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_H
|
||||
#define __STM32F3xx_HAL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_conf.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SYSCFG_BitAddress_AliasRegion
|
||||
* @brief SYSCFG registers bit address in the alias region
|
||||
* @{
|
||||
*/
|
||||
/* ------------ SYSCFG registers bit address in the alias region -------------*/
|
||||
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
|
||||
/* --- CFGR2 Register ---*/
|
||||
/* Alias word address of BYP_ADDR_PAR bit */
|
||||
#define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18)
|
||||
#define BYPADDRPAR_BitNumber 0x04
|
||||
#define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(SYSCFG_CFGR1_DMA_RMP)
|
||||
/** @defgroup HAL_DMA_Remapping
|
||||
* Elements values convention: 0xXXYYYYYY
|
||||
* - YYYYYY : Position in the register
|
||||
* - XX : Register index
|
||||
* - 00: CFGR1 register in SYSCFG
|
||||
* - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices)
|
||||
* @{
|
||||
*/
|
||||
#define HAL_REMAPDMA_ADC24_DMA2_CH34 ((uint32_t)0x00000100) /*!< ADC24 DMA remap (STM32F303xB/C/E and STM32F358xx devices)
|
||||
1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4) */
|
||||
#define HAL_REMAPDMA_TIM16_DMA1_CH6 ((uint32_t)0x00000800) /*!< TIM16 DMA request remap
|
||||
1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) */
|
||||
#define HAL_REMAPDMA_TIM17_DMA1_CH7 ((uint32_t)0x00001000) /*!< TIM17 DMA request remap
|
||||
1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7) */
|
||||
#define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 ((uint32_t)0x00002000) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E and STM32F358xx devices)
|
||||
1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3) */
|
||||
#define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 ((uint32_t)0x00004000) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E and STM32F358xx devices)
|
||||
1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) */
|
||||
#define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 ((uint32_t)0x00008000) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
|
||||
1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
|
||||
#define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 ((uint32_t)0x00008000) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
|
||||
1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
|
||||
#if defined(SYSCFG_CFGR3_DMA_RMP)
|
||||
#if !defined(HAL_REMAP_CFGR3_MASK)
|
||||
#define HAL_REMAP_CFGR3_MASK ((uint32_t)0x01000000)
|
||||
#endif
|
||||
|
||||
#define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 ((uint32_t)0x01000003) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
|
||||
11: Map on DMA1 channel 2 */
|
||||
#define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 ((uint32_t)0x01000001) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
|
||||
01: Map on DMA1 channel 4 */
|
||||
#define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 ((uint32_t)0x01000002) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
|
||||
10: Map on DMA1 channel 6 */
|
||||
#define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 ((uint32_t)0x0100000C) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
|
||||
11: Map on DMA1 channel 3 */
|
||||
#define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 ((uint32_t)0x01000004) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
|
||||
01: Map on DMA1 channel 5 */
|
||||
#define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 ((uint32_t)0x01000008) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
|
||||
10: Map on DMA1 channel 7 */
|
||||
#define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 ((uint32_t)0x01000030) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
|
||||
11: Map on DMA1 channel 7 */
|
||||
#define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 ((uint32_t)0x01000010) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
|
||||
01: Map on DMA1 channel 3 */
|
||||
#define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 ((uint32_t)0x01000020) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
|
||||
10: Map on DMA1 channel 5 */
|
||||
#define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 ((uint32_t)0x010000C0) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
|
||||
11: Map on DMA1 channel 6 */
|
||||
#define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 ((uint32_t)0x01000040) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
|
||||
01: Map on DMA1 channel 2 */
|
||||
#define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 ((uint32_t)0x01000080) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
|
||||
10: Map on DMA1 channel 4 */
|
||||
#define HAL_REMAPDMA_ADC2_DMA1_CH2 ((uint32_t)0x01000100) /*!< ADC2 DMA remap
|
||||
x0: No remap (ADC2 on DMA2)
|
||||
10: Map on DMA1 channel 2 */
|
||||
#define HAL_REMAPDMA_ADC2_DMA1_CH4 ((uint32_t)0x01000300) /*!< ADC2 DMA remap
|
||||
11: Map on DMA1 channel 4 */
|
||||
#endif /* SYSCFG_CFGR3_DMA_RMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP)
|
||||
#define IS_HAL_REMAPDMA(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
|
||||
(((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) || \
|
||||
(((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH2) == HAL_REMAPDMA_SPI1_RX_DMA1_CH2) || \
|
||||
(((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH4) == HAL_REMAPDMA_SPI1_RX_DMA1_CH4) || \
|
||||
(((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH6) == HAL_REMAPDMA_SPI1_RX_DMA1_CH6) || \
|
||||
(((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH3) == HAL_REMAPDMA_SPI1_TX_DMA1_CH3) || \
|
||||
(((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH5) == HAL_REMAPDMA_SPI1_TX_DMA1_CH5) || \
|
||||
(((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH7) == HAL_REMAPDMA_SPI1_TX_DMA1_CH7) || \
|
||||
(((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH7) == HAL_REMAPDMA_I2C1_RX_DMA1_CH7) || \
|
||||
(((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH3) == HAL_REMAPDMA_I2C1_RX_DMA1_CH3) || \
|
||||
(((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH5) == HAL_REMAPDMA_I2C1_RX_DMA1_CH5) || \
|
||||
(((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH6) == HAL_REMAPDMA_I2C1_TX_DMA1_CH6) || \
|
||||
(((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH2) == HAL_REMAPDMA_I2C1_TX_DMA1_CH2) || \
|
||||
(((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH4) == HAL_REMAPDMA_I2C1_TX_DMA1_CH4) || \
|
||||
(((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH2) == HAL_REMAPDMA_ADC2_DMA1_CH2) || \
|
||||
(((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH4) == HAL_REMAPDMA_ADC2_DMA1_CH4))
|
||||
#elif defined(SYSCFG_CFGR1_DMA_RMP)
|
||||
#define IS_HAL_REMAPDMA(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
|
||||
(((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
|
||||
(((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5))
|
||||
#endif /* SYSCFG_CFGR3_DMA_RMP && SYSCFG_CFGR1_DMA_RMP*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SYSCFG_CFGR1_DMA_RMP */
|
||||
|
||||
/** @defgroup HAL_Trigger_Remapping
|
||||
* Elements values convention: 0xXXYYYYYY
|
||||
* - YYYYYY : Position in the register
|
||||
* - XX : Register index
|
||||
* - 00: CFGR1 register in SYSCFG
|
||||
* - 01: CFGR3 register in SYSCFG
|
||||
* @{
|
||||
*/
|
||||
#define HAL_REMAPTRIGGER_DAC1_TRIG ((uint32_t)0x00000080) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices)
|
||||
0: No remap (DAC trigger is TIM8_TRGO)
|
||||
1: Remap (DAC trigger is TIM3_TRGO) */
|
||||
#define HAL_REMAPTRIGGER_TIM1_ITR3 ((uint32_t)0x00000040) /*!< TIM1 ITR3 trigger remap
|
||||
0: No remap
|
||||
1: Remap (TIM1_TRG3 = TIM17_OC) */
|
||||
#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
|
||||
#if !defined(HAL_REMAP_CFGR3_MASK)
|
||||
#define HAL_REMAP_CFGR3_MASK ((uint32_t)0x01000000)
|
||||
#endif
|
||||
#define HAL_REMAPTRIGGER_DAC1_TRIG3 ((uint32_t)0x01010000) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
|
||||
0: Remap (DAC trigger is TIM15_TRGO)
|
||||
1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */
|
||||
#define HAL_REMAPTRIGGER_DAC1_TRIG5 ((uint32_t)0x01020000) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
|
||||
0: No remap
|
||||
1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */
|
||||
#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
|
||||
#define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
|
||||
(((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3) || \
|
||||
(((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG3) == HAL_REMAPTRIGGER_DAC1_TRIG3) || \
|
||||
(((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG5) == HAL_REMAPTRIGGER_DAC1_TRIG5))
|
||||
#else
|
||||
#define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
|
||||
(((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3))
|
||||
#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_FastModePlus_I2C
|
||||
* @{
|
||||
*/
|
||||
#if defined(SYSCFG_CFGR1_I2C1_FMP)
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C1 ((uint32_t)SYSCFG_CFGR1_I2C1_FMP) /*!< I2C1 fast mode Plus driving capability activation
|
||||
0: FM+ mode is not enabled on I2C1 pins selected through AF selection bits
|
||||
1: FM+ mode is enabled on I2C1 pins selected through AF selection bits */
|
||||
#endif /* SYSCFG_CFGR1_I2C1_FMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_I2C2_FMP)
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C2 ((uint32_t)SYSCFG_CFGR1_I2C2_FMP) /*!< I2C2 fast mode Plus driving capability activation
|
||||
0: FM+ mode is not enabled on I2C2 pins selected through AF selection bits
|
||||
1: FM+ mode is enabled on I2C2 pins selected through AF selection bits */
|
||||
#endif /* SYSCFG_CFGR1_I2C2_FMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_I2C3_FMP)
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C3 ((uint32_t)SYSCFG_CFGR1_I2C3_FMP) /*!< I2C3 fast mode Plus driving capability activation
|
||||
0: FM+ mode is not enabled on I2C3 pins selected through AF selection bits
|
||||
1: FM+ mode is enabled on I2C3 pins selected through AF selection bits */
|
||||
#endif /* SYSCFG_CFGR1_I2C3_FMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_I2C_PB6_FMP)
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
|
||||
0: PB6 pin operates in standard mode
|
||||
1: I2C FM+ mode enabled on PB6 pin, and the Speed control is bypassed */
|
||||
#endif /* SYSCFG_CFGR1_I2C_PB6_FMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_I2C_PB7_FMP)
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
|
||||
0: PB7 pin operates in standard mode
|
||||
1: I2C FM+ mode enabled on PB7 pin, and the Speed control is bypassed */
|
||||
#endif /* SYSCFG_CFGR1_I2C_PB7_FMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
|
||||
0: PB8 pin operates in standard mode
|
||||
1: I2C FM+ mode enabled on PB8 pin, and the Speed control is bypassed */
|
||||
#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
|
||||
0: PB9 pin operates in standard mode
|
||||
1: I2C FM+ mode enabled on PB9 pin, and the Speed control is bypassed */
|
||||
#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_I2C1_FMP) && defined(SYSCFG_CFGR1_I2C2_FMP) && defined(SYSCFG_CFGR1_I2C3_FMP)
|
||||
#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) ((((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C1) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C2) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C3) == HAL_SYSCFG_FASTMODEPLUS_I2C3) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB9) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
|
||||
#elif defined(SYSCFG_CFGR1_I2C1_FMP) && defined(SYSCFG_CFGR1_I2C2_FMP)
|
||||
#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) ((((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C1) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C2) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB9) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
|
||||
#elif defined(SYSCFG_CFGR1_I2C1_FMP)
|
||||
#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) ((((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C1) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
|
||||
(((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB9) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
|
||||
#endif /* SYSCFG_CFGR1_I2C1_FMP && SYSCFG_CFGR1_I2C2_FMP && SYSCFG_CFGR3_I2C1_FMP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(SYSCFG_RCR_PAGE0)
|
||||
/* CCM-SRAM defined */
|
||||
/** @defgroup HAL_Page_Write_Protection
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0 */
|
||||
#define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1 */
|
||||
#define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2 */
|
||||
#define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3 */
|
||||
#if defined(SYSCFG_RCR_PAGE4)
|
||||
/* More than 4KB CCM-SRAM defined */
|
||||
#define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4 */
|
||||
#define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5 */
|
||||
#define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6 */
|
||||
#define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7 */
|
||||
#endif /* SYSCFG_RCR_PAGE4 */
|
||||
|
||||
#if defined(SYSCFG_RCR_PAGE4)
|
||||
#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= SYSCFG_RCR_PAGE7))
|
||||
#else
|
||||
#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= SYSCFG_RCR_PAGE3))
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SYSCFG_RCR_PAGE0 */
|
||||
|
||||
/** @defgroup HAL_SYSCFG_Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0) /*!< Floating Point Unit Invalid operation Interrupt */
|
||||
#define HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1) /*!< Floating Point Unit Divide-by-zero Interrupt */
|
||||
#define HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2) /*!< Floating Point Unit Underflow Interrupt */
|
||||
#define HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3) /*!< Floating Point Unit Overflow Interrupt */
|
||||
#define HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4) /*!< Floating Point Unit Input denormal Interrupt */
|
||||
#define HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5) /*!< Floating Point Unit Inexact Interrupt */
|
||||
|
||||
#define IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \
|
||||
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \
|
||||
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \
|
||||
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \
|
||||
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \
|
||||
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @brief Freeze/Unfreeze Peripherals in Debug mode
|
||||
*/
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
|
||||
#define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
|
||||
#define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
|
||||
#define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
|
||||
#define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
|
||||
#define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
|
||||
#define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
|
||||
#define __HAL_FREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
|
||||
#define __HAL_UNFREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
|
||||
#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
|
||||
#define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
|
||||
#define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
|
||||
#define __HAL_FREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
|
||||
#define __HAL_UNFREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
|
||||
#define __HAL_FREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
|
||||
#define __HAL_UNFREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
|
||||
#define __HAL_FREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
|
||||
#define __HAL_UNFREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
|
||||
#define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
|
||||
#define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
|
||||
#define __HAL_FREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
|
||||
#define __HAL_UNFREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
|
||||
#define __HAL_FREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
|
||||
#define __HAL_UNFREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
|
||||
#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
|
||||
#define __HAL_FREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
|
||||
#define __HAL_UNFREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
|
||||
#define __HAL_FREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
|
||||
#define __HAL_UNFREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
|
||||
#define __HAL_FREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
|
||||
#define __HAL_UNFREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
|
||||
#define __HAL_FREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
|
||||
#define __HAL_UNFREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
|
||||
#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
|
||||
#define __HAL_FREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
|
||||
#define __HAL_UNFREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
|
||||
#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
|
||||
#define __HAL_FREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
|
||||
#define __HAL_UNFREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
|
||||
#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
|
||||
#define __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))
|
||||
#define __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))
|
||||
#endif /* */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
|
||||
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
|
||||
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
|
||||
#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
|
||||
#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
|
||||
#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
|
||||
#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
|
||||
#define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
|
||||
#define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
|
||||
|
||||
|
||||
#if defined(SYSCFG_CFGR1_MEM_MODE)
|
||||
/** @brief Main Flash memory mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
|
||||
#endif /* SYSCFG_CFGR1_MEM_MODE */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_MEM_MODE_0)
|
||||
/** @brief System Flash memory mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
|
||||
SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR1_MEM_MODE_0 */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
|
||||
/** @brief Embedded SRAM mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
|
||||
SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_ENCODER_MODE)
|
||||
/** @brief No Encoder mode
|
||||
*/
|
||||
#define __HAL_REMAPENCODER_NONE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE))
|
||||
#endif /* SYSCFG_CFGR1_ENCODER_MODE */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_ENCODER_MODE_0)
|
||||
/** @brief Encoder mode : TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
|
||||
*/
|
||||
#define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
|
||||
SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_ENCODER_MODE_1)
|
||||
/** @brief Encoder mode : TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
|
||||
*/
|
||||
#define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
|
||||
SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1)
|
||||
/** @brief Encoder mode : TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 (STM32F303xB/C and STM32F358xx devices)
|
||||
*/
|
||||
#define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
|
||||
SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */
|
||||
|
||||
#if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP)
|
||||
/** @brief DMA remapping enable/disable macros
|
||||
* @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping
|
||||
*/
|
||||
#define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
|
||||
(((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
|
||||
(SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
|
||||
(SYSCFG->CFGR1 |= (__DMA_REMAP__))); \
|
||||
}while(0)
|
||||
#define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
|
||||
(((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
|
||||
(SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
|
||||
(SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \
|
||||
}while(0)
|
||||
#elif defined(SYSCFG_CFGR1_DMA_RMP)
|
||||
/** @brief DMA remapping enable/disable macros
|
||||
* @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping
|
||||
*/
|
||||
#define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
|
||||
SYSCFG->CFGR1 |= (__DMA_REMAP__); \
|
||||
}while(0)
|
||||
#define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
|
||||
SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */
|
||||
|
||||
/** @brief Fast mode Plus driving capability enable/disable macros
|
||||
* @param __FASTMODEPLUS__: This parameter can be a value of @ref HAL_FastModePlus_I2C
|
||||
*/
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \
|
||||
SYSCFG->CFGR1 |= (__FASTMODEPLUS__); \
|
||||
}while(0)
|
||||
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \
|
||||
SYSCFG->CFGR1 &= ~(__FASTMODEPLUS__); \
|
||||
}while(0)
|
||||
|
||||
/** @brief SYSCFG interrupt enable/disable macros
|
||||
* @param __INTERRUPT__: This parameter can be a value of @ref HAL_SYSCFG_Interrupts
|
||||
*/
|
||||
#define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
|
||||
SYSCFG->CFGR1 |= (__INTERRUPT__); \
|
||||
}while(0)
|
||||
|
||||
#define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
|
||||
SYSCFG->CFGR1 &= ~(__INTERRUPT__); \
|
||||
}while(0)
|
||||
|
||||
#if defined(SYSCFG_CFGR1_USB_IT_RMP)
|
||||
/** @brief USB interrupt remapping enable/disable macros
|
||||
*/
|
||||
#define __HAL_REMAPINTERRUPT_USB_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP))
|
||||
#define __HAL_REMAPINTERRUPT_USB_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_USB_IT_RMP))
|
||||
#endif /* SYSCFG_CFGR1_USB_IT_RMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_VBAT)
|
||||
/** @brief SYSCFG interrupt enable/disable macros
|
||||
*/
|
||||
#define __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT))
|
||||
#define __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT))
|
||||
#endif /* SYSCFG_CFGR1_VBAT */
|
||||
|
||||
#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
|
||||
/** @brief SYSCFG Break Lockup lock
|
||||
* Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
|
||||
* @note The selected configuration is locked and can be unlocked by system reset
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
|
||||
SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
|
||||
|
||||
#if defined(SYSCFG_CFGR2_PVD_LOCK)
|
||||
/** @brief SYSCFG Break PVD lock
|
||||
* Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
|
||||
* @note The selected configuration is locked and can be unlocked by system reset
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
|
||||
SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR2_PVD_LOCK */
|
||||
|
||||
#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
|
||||
/** @brief SYSCFG Break SRAM PARITY lock
|
||||
* Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
|
||||
* @note The selected configuration is locked and can be unlocked by system reset
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
|
||||
SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
|
||||
|
||||
#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
|
||||
/** @brief Trigger remapping enable/disable macros
|
||||
* @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping
|
||||
*/
|
||||
#define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
|
||||
(((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
|
||||
(SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
|
||||
(SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \
|
||||
}while(0)
|
||||
#define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
|
||||
(((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
|
||||
(SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
|
||||
(SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \
|
||||
}while(0)
|
||||
#else
|
||||
/** @brief Trigger remapping enable/disable macros
|
||||
* @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping
|
||||
*/
|
||||
#define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
|
||||
(SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \
|
||||
}while(0)
|
||||
#define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
|
||||
(SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
|
||||
|
||||
#if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
|
||||
/**
|
||||
* @brief Parity check on RAM disable macro
|
||||
* @note Disabling the parity check on RAM locks the configuration bit.
|
||||
* To re-enable the parity check on RAM perform a system reset.
|
||||
*/
|
||||
#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = (uint32_t)0x00000001)
|
||||
#endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
|
||||
|
||||
#if defined(SYSCFG_RCR_PAGE0)
|
||||
/** @brief CCM RAM page write protection enable macro
|
||||
* @param __PAGE_WP__: This parameter can be a value of @ref HAL_Page_Write_Protection
|
||||
* @note write protection can only be disabled by a system reset
|
||||
*/
|
||||
#define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \
|
||||
SYSCFG->RCR |= (__PAGE_WP__); \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_RCR_PAGE0 */
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization and de-initialization functions ******************************/
|
||||
HAL_StatusTypeDef HAL_Init(void);
|
||||
HAL_StatusTypeDef HAL_DeInit(void);
|
||||
void HAL_MspInit(void);
|
||||
void HAL_MspDeInit(void);
|
||||
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
void HAL_IncTick(void);
|
||||
void HAL_Delay(__IO uint32_t Delay);
|
||||
void HAL_SuspendTick(void);
|
||||
void HAL_ResumeTick(void);
|
||||
uint32_t HAL_GetTick(void);
|
||||
uint32_t HAL_GetHalVersion(void);
|
||||
uint32_t HAL_GetREVID(void);
|
||||
uint32_t HAL_GetDEVID(void);
|
||||
void HAL_EnableDBGSleepMode(void);
|
||||
void HAL_DisableDBGSleepMode(void);
|
||||
void HAL_EnableDBGStopMode(void);
|
||||
void HAL_DisableDBGStopMode(void);
|
||||
void HAL_EnableDBGStandbyMode(void);
|
||||
void HAL_DisableDBGStandbyMode(void);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,725 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_adc.c
|
||||
* @author MCD Application conversion
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Analog to Digital Convertor (ADC)
|
||||
* peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* ++ Initialization and Configuration of ADC
|
||||
* + Operation functions
|
||||
* ++ Start, stop, get result of conversions of regular and injected
|
||||
* groups, using 3 possible modes: polling, interruption or DMA.
|
||||
* + Control functions
|
||||
* ++ Analog Watchdog configuration
|
||||
* ++ Channels configuration on regular group
|
||||
* + State functions
|
||||
* ++ ADC state machine management
|
||||
* ++ Interrupts and flags management
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### ADC specific features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution (available only on
|
||||
STM32F30xxC devices).
|
||||
|
||||
(#) Interrupt generation at the end of regular conversion, end of injected
|
||||
conversion, and in case of analog watchdog or overrun events.
|
||||
|
||||
(#) Single and continuous conversion modes.
|
||||
|
||||
(#) Scan mode for automatic conversion of channel 0 to channel 'n'.
|
||||
|
||||
(#) Data alignment with in-built data coherency.
|
||||
|
||||
(#) Channel-wise programmable sampling time.
|
||||
|
||||
(#) ADC conversion Regular or Injected groups.
|
||||
|
||||
(#) External trigger (timer or EXTI) with configurable polarity for both
|
||||
regular and injected groups.
|
||||
|
||||
(#) DMA request generation for transfer of conversions data of regular group.
|
||||
|
||||
(#) Multimode Dual mode (available on devices with 2 ADCs or more).
|
||||
|
||||
(#) Configurable DMA data storage in Multimode Dual mode (available on devices
|
||||
with 2 DCs or more).
|
||||
|
||||
(#) Configurable delay between conversions in Dual interleaved mode (available
|
||||
on devices with 2 DCs or more).
|
||||
|
||||
(#) ADC calibration
|
||||
|
||||
(#) ADC channels selectable single/differential input (available only on
|
||||
STM32F30xxC devices)
|
||||
|
||||
(#) ADC Injected sequencer&channels configuration context queue (available
|
||||
only on STM32F30xxC devices)
|
||||
|
||||
(#) ADC offset on injected and regular groups (offset on regular group
|
||||
available only on STM32F30xxC devices)
|
||||
|
||||
(#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
|
||||
slower speed.
|
||||
|
||||
(#) ADC input range: from Vref– (connected to Vssa) to Vref+ (connected to
|
||||
Vdda or to an external voltage reference).
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
|
||||
(#) Enable the ADC interface
|
||||
As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured
|
||||
at RCC top level: clock source and clock prescaler.
|
||||
|
||||
For STM32F30x/STM32F33x devices:
|
||||
Two possible clock sources: synchronous clock derived from AHB clock
|
||||
or asynchronous clock derived from ADC dedicated PLL 72MHz.
|
||||
|
||||
For example, in case of device with a single ADC:
|
||||
__ADC1_CLK_ENABLE() (mandatory)
|
||||
__HAL_RCC_ADC1_CONFIG(RCC_ADC1PLLCLK_DIV1); (optional)
|
||||
|
||||
For example, in case of device with several ADCs:
|
||||
if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
|
||||
{
|
||||
__ADC12_CLK_ENABLE() (mandatory)
|
||||
__HAL_RCC_ADC12_CONFIG(RCC_ADC12PLLCLK_DIV1); (optional)
|
||||
}
|
||||
else
|
||||
{
|
||||
__ADC34_CLK_ENABLE() (mandatory)
|
||||
__HAL_RCC_ADC34_CONFIG(RCC_ADC34PLLCLK_DIV1); (optional)
|
||||
}
|
||||
|
||||
For STM32F37x devices:
|
||||
Only one clock source: APB2 clock.
|
||||
Example:
|
||||
__HAL_RCC_ADC1_CONFIG(RCC_ADC1PCLK2_DIV2);
|
||||
|
||||
(#) ADC pins configuration
|
||||
(++) Enable the clock for the ADC GPIOs using the following function:
|
||||
__GPIOx_CLK_ENABLE();
|
||||
(++) Configure these ADC pins in analog mode using HAL_GPIO_Init();
|
||||
|
||||
(#) Configure the ADC parameters (conversion resolution, data alignment,
|
||||
continuous mode, ...) using the HAL_ADC_Init() function.
|
||||
|
||||
(#) Activate the ADC peripheral using one of the start functions:
|
||||
HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()
|
||||
HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT() or
|
||||
HAL_ADC_MultiModeStart_DMA().
|
||||
|
||||
*** Channels to regular group configuration ***
|
||||
============================================
|
||||
[..]
|
||||
(+) To configure the ADC regular group features, use
|
||||
HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions.
|
||||
(+) To activate the continuous mode, use the HAL_ADC_Init() function.
|
||||
(+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
|
||||
|
||||
*** Multimode ADCs configuration ***
|
||||
======================================================
|
||||
[..]
|
||||
(+) Multimode feature is available on devices with 2 ADCs or more.
|
||||
(+) Refer to "Channels to regular group" description to
|
||||
configure the ADC1 and ADC2 regular groups.
|
||||
(+) Select the Multi mode ADC features (dual mode
|
||||
simultaneous, interleaved, ...) and configure the DMA mode using
|
||||
HAL_ADCEx_MultiModeConfigChannel() functions.
|
||||
(+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue()
|
||||
function.
|
||||
|
||||
*** DMA for regular configuration ***
|
||||
=============================================================
|
||||
[..]
|
||||
(+) To enable the DMA mode for regular group, use the
|
||||
HAL_ADC_Start_DMA() function.
|
||||
(+) To enable the generation of DMA requests continuously at the end of
|
||||
the last DMA transfer, use the HAL_ADC_Init() function.
|
||||
|
||||
*** Channels to injected group configuration ***
|
||||
=============================================
|
||||
[..]
|
||||
(+) To configure the ADC Injected channels group features, use
|
||||
HAL_ADCEx_InjectedConfigChannel() functions.
|
||||
(+) To activate the continuous mode, use the HAL_ADC_Init() function.
|
||||
(+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue()
|
||||
function.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC
|
||||
* @brief ADC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize and configure the ADC.
|
||||
(+) De-initialize the ADC.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the ADC peripheral and regular group according to
|
||||
* parameters specified in structure "ADC_InitTypeDef".
|
||||
* @note As prerequisite, ADC clock must be configured at RCC top level
|
||||
* depending on both possible clock sources: PLL clock or AHB clock.
|
||||
* See commented example code below that can be copied and uncommented
|
||||
* into HAL_ADC_MspInit().
|
||||
* @note Possibility to update parameters on the fly:
|
||||
* This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
|
||||
* coming from ADC state reset. Following calls to this function can
|
||||
* be used to reconfigure some parameters of ADC_InitTypeDef
|
||||
* structure on the fly, without modifying MSP configuration. If ADC
|
||||
* MSP has to be modified again, HAL_ADC_DeInit() must be called
|
||||
* before HAL_ADC_Init().
|
||||
* The setting of these parameters is conditioned to ADC state.
|
||||
* For parameters constraints, see comments of structure
|
||||
* "ADC_InitTypeDef".
|
||||
* @note This function configures the ADC within 2 scopes: scope of entire
|
||||
* ADC and scope of regular group. For parameters details, see comments
|
||||
* of structure "ADC_InitTypeDef".
|
||||
* @note For devices with several ADCs: parameters related to common ADC
|
||||
* registers (ADC clock mode) are set only if all ADCs sharing the
|
||||
* same common group are disabled.
|
||||
* If this is not the case, these common parameters setting are
|
||||
* bypassed without error reporting: it can be the intended behaviour in
|
||||
* case of update of a parameter of ADC_InitTypeDef on the fly,
|
||||
* without disabling the other ADCs sharing the same common group.
|
||||
* @param hadc: ADC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitialize the ADC peripheral registers to their default reset
|
||||
* values, with deinitialization of the ADC MSP.
|
||||
* @note For devices with several ADCs: reset of ADC common registers is done
|
||||
* only if all ADCs sharing the same common group are disabled.
|
||||
* If this is not the case, reset of these common parameters reset is
|
||||
* bypassed without error reporting: it can be the intended behaviour in
|
||||
* case of reset of a single ADC while the other ADCs sharing the same
|
||||
* common group is still running.
|
||||
* @note For devices with several ADCs: Global reset of all ADCs sharing a
|
||||
* common group is possible.
|
||||
* As this function is intended to reset a single ADC, to not impact
|
||||
* other ADCs, instructions for global reset of multiple ADCs have been
|
||||
* let commented below.
|
||||
* If needed, the example code can be copied and uncommented into
|
||||
* function HAL_ADC_MspDeInit().
|
||||
* @param hadc: ADC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the ADC MSP.
|
||||
* @param hadc: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_ADC_MspInit must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the ADC MSP.
|
||||
* @param hadc: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_ADC_MspDeInit must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Start conversion of regular group.
|
||||
(+) Stop conversion of regular group.
|
||||
(+) Poll for conversion complete on regular group.
|
||||
(+) Poll for conversion event.
|
||||
(+) Get result of regular channel conversion.
|
||||
(+) Start conversion of regular group and enable interruptions.
|
||||
(+) Stop conversion of regular group and disable interruptions.
|
||||
(+) Handle ADC interrupt request
|
||||
(+) Start conversion of regular group and enable DMA transfer.
|
||||
(+) Stop conversion of regular group and disable ADC DMA transfer.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables ADC, starts conversion of regular group.
|
||||
* Interruptions enabled in this function: None.
|
||||
* @note: Case of multimode enabled (for devices with several ADCs): This
|
||||
* function must be called for ADC slave first, then ADC master.
|
||||
* For ADC slave, ADC is enabled only (conversion is not started).
|
||||
* For ADC master, ADC is enabled and multimode conversion is started.
|
||||
* @param hadc: ADC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop ADC conversion of regular group (and injected group in
|
||||
* case of auto_injection mode), disable ADC peripheral.
|
||||
* @note: ADC peripheral disable is forcing interruption of potential
|
||||
* conversion on injected group. If injected group is under use, it
|
||||
* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
|
||||
* @note: Case of multimode enabled (for devices with several ADCs): This
|
||||
* function must be called for ADC master first, then ADC slave.
|
||||
* For ADC master, converson is stopped and ADC is disabled.
|
||||
* For ADC slave, ADC is disabled only (conversion stop of ADC master
|
||||
* has already stopped conversion of ADC slave).
|
||||
* @param hadc: ADC handle
|
||||
* @retval HAL status.
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait for regular group conversion to be completed.
|
||||
* @param hadc: ADC handle
|
||||
* @param Timeout: Timeout value in millisecond.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Poll for conversion event.
|
||||
* @param hadc: ADC handle
|
||||
* @param EventType: the ADC event type.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg AWD_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
|
||||
* @arg AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, present only on STM32F3 devices)
|
||||
* @arg AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, present only on STM32F3 devices)
|
||||
* @arg OVR_EVENT: ADC Overrun event
|
||||
* @arg JQOVF_EVENT: ADC Injected context queue overflow event
|
||||
* @param Timeout: Timeout value in millisecond.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables ADC, starts conversion of regular group with interruption.
|
||||
* Interruptions enabled in this function: EOC (end of conversion),
|
||||
* overrun (if available).
|
||||
* Each of these interruptions has its dedicated callback function.
|
||||
* @note: Case of multimode enabled (for devices with several ADCs): This
|
||||
* function must be called for ADC slave first, then ADC master.
|
||||
* For ADC slave, ADC is enabled only (conversion is not started).
|
||||
* For ADC master, ADC is enabled and multimode conversion is started.
|
||||
* @param hadc: ADC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop ADC conversion of regular group (and injected group in
|
||||
* case of auto_injection mode), disable interruption of
|
||||
* end-of-conversion, disable ADC peripheral.
|
||||
* @note: ADC peripheral disable is forcing interruption of potential
|
||||
* conversion on injected group. If injected group is under use, it
|
||||
* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
|
||||
* @note: Case of multimode enabled (for devices with several ADCs): This
|
||||
* function must be called for ADC master first, then ADC slave.
|
||||
* For ADC master, conversion is stopped and ADC is disabled.
|
||||
* For ADC slave, ADC is disabled only (conversion stop of ADC master
|
||||
* has already stopped conversion of ADC slave).
|
||||
* @param hadc: ADC handle
|
||||
* @retval HAL status.
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables ADC, starts conversion of regular group and transfers result
|
||||
* through DMA.
|
||||
* Interruptions enabled in this function:
|
||||
* overrun (if available), DMA half transfer, DMA transfer complete.
|
||||
* Each of these interruptions has its dedicated callback function.
|
||||
* @note: Case of multimode enabled (for devices with several ADCs): This
|
||||
* function is for single-ADC mode only. For multimode, use the
|
||||
* dedicated MultimodeStart function.
|
||||
* @param hadc: ADC handle
|
||||
* @param pData: The destination Buffer address.
|
||||
* @param Length: The length of data to be transferred from ADC peripheral to memory.
|
||||
* @retval None
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop ADC conversion of regular group (and injected group in
|
||||
* case of auto_injection mode), disable ADC DMA transfer, disable
|
||||
* ADC peripheral.
|
||||
* @note: ADC peripheral disable is forcing interruption of potential
|
||||
* conversion on injected group. If injected group is under use, it
|
||||
* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
|
||||
* @note: Case of multimode enabled (for devices with several ADCs): This
|
||||
* function is for single-ADC mode only. For multimode, use the
|
||||
* dedicated MultimodeStop function.
|
||||
* @param hadc: ADC handle
|
||||
* @retval HAL status.
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get ADC regular group conversion result.
|
||||
* @param hadc: ADC handle
|
||||
* @retval Converted value
|
||||
*/
|
||||
__weak uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return ADC converted value */
|
||||
return hadc->Instance->DR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handles ADC interrupt request.
|
||||
* @param hadc: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Conversion complete callback in non blocking mode
|
||||
* @param hadc: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_ADC_ConvCpltCallback must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Conversion DMA half-transfer callback in non blocking mode
|
||||
* @param hadc: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Analog watchdog callback in non blocking mode.
|
||||
* @note: In case of several analog watchdog enabled, if needed to know
|
||||
which one triggered and on which ADCx, check Analog Watchdog flag
|
||||
ADC_FLAG_AWD1/2/3 into HAL_ADC_LevelOutOfWindowCallback() function.
|
||||
For example:"if (__HAL_ADC_GET_FLAG(hadc1, ADC_FLAG_AWD1) != RESET)"
|
||||
* @param hadc: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ADC error callback in non blocking mode
|
||||
* (ADC conversion with interruption or transfer by DMA)
|
||||
* @param hadc: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
|
||||
{
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_ADC_ErrorCallback must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Group3 Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure channels on regular group
|
||||
(+) Configure the analog watchdog
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the the selected channel to be linked to the regular
|
||||
* group.
|
||||
* @note In case of usage of internal measurement channels:
|
||||
* Vbat/VrefInt/TempSensor.
|
||||
* The recommended sampling time is at least:
|
||||
* - For devices STM32F37x: 17.1us for temperature sensor
|
||||
* - For the other STM32F3 devices: 2.2us for each of channels
|
||||
* Vbat/VrefInt/TempSensor.
|
||||
* These internal paths can be be disabled using function
|
||||
* HAL_ADC_DeInit().
|
||||
* @note Possibility to update parameters on the fly:
|
||||
* This function initializes channel into regular group, following
|
||||
* calls to this function can be used to reconfigure some parameters
|
||||
* of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
|
||||
* the ADC.
|
||||
* The setting of these parameters is conditioned to ADC state.
|
||||
* For parameters constraints, see comments of structure
|
||||
* "ADC_ChannelConfTypeDef".
|
||||
* @param hadc: ADC handle
|
||||
* @param sConfig: Structure of ADC channel for regular group.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the analog watchdog.
|
||||
* @note Possibility to update parameters on the fly:
|
||||
* This function initializes the selected analog watchdog, following
|
||||
* calls to this function can be used to reconfigure some parameters
|
||||
* of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
|
||||
* the ADC.
|
||||
* The setting of these parameters is conditioned to ADC state.
|
||||
* For parameters constraints, see comments of structure
|
||||
* "ADC_AnalogWDGConfTypeDef".
|
||||
* @param hadc: ADC handle
|
||||
* @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference. */
|
||||
/* Function content is located into file stm32f3xx_hal_adc_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Group4 ADC Peripheral State functions
|
||||
* @brief ADC Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral state and errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides functions to get in run-time the status of the
|
||||
peripheral.
|
||||
(+) Check the ADC state
|
||||
(+) Check the ADC error code
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief return the ADC state
|
||||
* @param hadc: ADC handle
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
|
||||
/* Return ADC state */
|
||||
return hadc->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the ADC error code
|
||||
* @param hadc: ADC handle
|
||||
* @retval ADC Error Code
|
||||
*/
|
||||
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
|
||||
{
|
||||
return hadc->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,178 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file containing functions prototypes of ADC HAL library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_ADC_H
|
||||
#define __STM32F3xx_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
#include "stm32f3xx_hal_adc_ex.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL ADC state machine: ADC States structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */
|
||||
HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */
|
||||
HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
|
||||
HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */
|
||||
HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */
|
||||
HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */
|
||||
HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */
|
||||
HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */
|
||||
HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */
|
||||
HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */
|
||||
HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */
|
||||
HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */
|
||||
HAL_ADC_STATE_AWD = 0x06, /*!< ADC state analog watchdog (main analog watchdog, present on all STM32 devices) */
|
||||
HAL_ADC_STATE_AWD2 = 0x07, /*!< ADC state analog watchdog (additional analog watchdog, present only on STM32F3 devices) */
|
||||
HAL_ADC_STATE_AWD3 = 0x08, /*!< ADC state analog watchdog (additional analog watchdog, present only on STM32F3 devices) */
|
||||
}HAL_ADC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief ADC handle Structure definition
|
||||
*/
|
||||
typedef struct __ADC_HandleTypeDef
|
||||
{
|
||||
ADC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
ADC_InitTypeDef Init; /*!< ADC required parameters */
|
||||
|
||||
__IO uint32_t NbrOfConversionRank ; /*!< ADC conversion rank counter */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< ADC locking object */
|
||||
|
||||
__IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< ADC Error code */
|
||||
}ADC_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Exported_Macro
|
||||
* @{
|
||||
*/
|
||||
/** @brief Reset ADC handle state
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Include ADC HAL Extension module */
|
||||
#include "stm32f3xx_hal_adc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
|
||||
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
|
||||
|
||||
/* Non-blocking mode: Interruption */
|
||||
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
|
||||
|
||||
/* Non-blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
|
||||
|
||||
/* ADC retrieve conversion value intended to be used with polling or interruption */
|
||||
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
|
||||
|
||||
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
|
||||
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
|
||||
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
|
||||
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
|
||||
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F3xx_ADC_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,782 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_can.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of CAN HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_CAN_H
|
||||
#define __STM32F3xx_CAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F302x8) || defined(STM32F302xC) || \
|
||||
defined(STM32F303x8) || defined(STM32F303xC) || defined(STM32F373xC) || \
|
||||
defined(STM32F334x8) || \
|
||||
defined(STM32F328xx) || defined(STM32F358xx) || defined(STM32F378xx)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */
|
||||
HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */
|
||||
HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_TIMEOUT = 0x03, /*!< CAN in Timeout state */
|
||||
HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */
|
||||
|
||||
}HAL_CAN_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CAN Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CAN_ERROR_NONE = 0x00, /*!< No error */
|
||||
HAL_CAN_ERROR_EWG = 0x01, /*!< EWG error */
|
||||
HAL_CAN_ERROR_EPV = 0x02, /*!< EPV error */
|
||||
HAL_CAN_ERROR_BOF = 0x04, /*!< BOF error */
|
||||
HAL_CAN_ERROR_STF = 0x08, /*!< Stuff error */
|
||||
HAL_CAN_ERROR_FOR = 0x10, /*!< Form error */
|
||||
HAL_CAN_ERROR_ACK = 0x20, /*!< Acknowledgment error */
|
||||
HAL_CAN_ERROR_BR = 0x40, /*!< Bit recessive */
|
||||
HAL_CAN_ERROR_BD = 0x80, /*!< LEC dominant */
|
||||
HAL_CAN_ERROR_CRC = 0x100 /*!< LEC transfer error */
|
||||
}HAL_CAN_ErrorTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Specifies the length of a time quantum.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the CAN operating mode.
|
||||
This parameter can be a value of @ref CAN_operating_mode */
|
||||
|
||||
uint32_t SJW; /*!< Specifies the maximum number of time quanta
|
||||
the CAN hardware is allowed to lengthen or
|
||||
shorten a bit to perform resynchronization.
|
||||
This parameter can be a value of @ref CAN_synchronisation_jump_width */
|
||||
|
||||
uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
|
||||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
|
||||
|
||||
uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
|
||||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
|
||||
|
||||
uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
}CAN_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN filter configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||
configuration, first one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||
configuration, second one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (MSBs for a 32-bit configuration,
|
||||
first one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (LSBs for a 32-bit configuration,
|
||||
second one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
|
||||
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||
|
||||
uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
|
||||
|
||||
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
|
||||
This parameter can be a value of @ref CAN_filter_mode */
|
||||
|
||||
uint32_t FilterScale; /*!< Specifies the filter scale.
|
||||
This parameter can be a value of @ref CAN_filter_scale */
|
||||
|
||||
uint32_t FilterActivation; /*!< Enable or disable the filter.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t BankNumber; /*!< Select the start slave bank filter
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 28. */
|
||||
|
||||
}CAN_FilterConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Tx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
|
||||
|
||||
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_identifier_type */
|
||||
|
||||
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_remote_transmission_request */
|
||||
|
||||
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
|
||||
|
||||
uint32_t Data[8]; /*!< Contains the data to be transmitted.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
|
||||
|
||||
}CanTxMsgTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Rx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
|
||||
|
||||
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
|
||||
This parameter can be a value of @ref CAN_identifier_type */
|
||||
|
||||
uint32_t RTR; /*!< Specifies the type of frame for the received message.
|
||||
This parameter can be a value of @ref CAN_remote_transmission_request */
|
||||
|
||||
uint32_t DLC; /*!< Specifies the length of the frame that will be received.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
|
||||
|
||||
uint32_t Data[8]; /*!< Contains the data to be received.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
|
||||
|
||||
uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
|
||||
|
||||
uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
|
||||
This parameter can be CAN_FIFO0 or CAN_FIFO1 */
|
||||
|
||||
}CanRxMsgTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CAN_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
CAN_InitTypeDef Init; /*!< CAN required parameters */
|
||||
|
||||
CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
|
||||
|
||||
CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CAN locking object */
|
||||
|
||||
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
|
||||
|
||||
__IO HAL_CAN_ErrorTypeDef ErrorCode; /*!< CAN Error code */
|
||||
|
||||
}CAN_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CAN_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_InitStatus
|
||||
* @{
|
||||
*/
|
||||
#define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000) /*!< CAN initialization failed */
|
||||
#define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001) /*!< CAN initialization OK */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_operating_mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
|
||||
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
|
||||
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
|
||||
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
|
||||
|
||||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
|
||||
((MODE) == CAN_MODE_LOOPBACK)|| \
|
||||
((MODE) == CAN_MODE_SILENT) || \
|
||||
((MODE) == CAN_MODE_SILENT_LOOPBACK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_synchronisation_jump_width
|
||||
* @{
|
||||
*/
|
||||
#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
|
||||
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
|
||||
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
|
||||
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
|
||||
|
||||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
|
||||
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_1
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
|
||||
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
|
||||
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
|
||||
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
|
||||
#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
|
||||
#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
|
||||
#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
|
||||
#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
|
||||
#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
|
||||
#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
|
||||
#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
|
||||
#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
|
||||
#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
|
||||
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
|
||||
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
|
||||
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
|
||||
|
||||
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_2
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
|
||||
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
|
||||
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
|
||||
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
|
||||
#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
|
||||
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
|
||||
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
|
||||
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
|
||||
|
||||
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_clock_prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_number
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
|
||||
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
|
||||
|
||||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
|
||||
((MODE) == CAN_FILTERMODE_IDLIST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_scale
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
|
||||
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
|
||||
|
||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
|
||||
((SCALE) == CAN_FILTERSCALE_32BIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_FIFO
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
|
||||
#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
|
||||
|
||||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
|
||||
((FIFO) == CAN_FILTER_FIFO1))
|
||||
|
||||
/* Legacy defines */
|
||||
#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
|
||||
#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Start_bank_filter_for_slave_CAN
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Tx
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
|
||||
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
|
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
|
||||
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_identifier_type
|
||||
* @{
|
||||
*/
|
||||
#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
|
||||
#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
|
||||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
|
||||
((IDTYPE) == CAN_ID_EXT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_remote_transmission_request
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
|
||||
#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
|
||||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_transmit_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TXSTATUS_FAILED ((uint8_t)0x00) /*!< CAN transmission failed */
|
||||
#define CAN_TXSTATUS_OK ((uint8_t)0x01) /*!< CAN transmission succeeded */
|
||||
#define CAN_TXSTATUS_PENDING ((uint8_t)0x02) /*!< CAN transmission pending */
|
||||
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_receive_FIFO_number_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
|
||||
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
|
||||
|
||||
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_flags
|
||||
* @{
|
||||
*/
|
||||
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
||||
and CAN_ClearFlag() functions. */
|
||||
/* If the flag is 0x1XXXXXXX, it means that it can only be used with
|
||||
CAN_GetFlagStatus() function. */
|
||||
|
||||
/* Transmit Flags */
|
||||
#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */
|
||||
#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */
|
||||
#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */
|
||||
#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */
|
||||
#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */
|
||||
#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */
|
||||
#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */
|
||||
#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */
|
||||
#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */
|
||||
|
||||
/* Receive Flags */
|
||||
#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */
|
||||
#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */
|
||||
|
||||
#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */
|
||||
#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */
|
||||
|
||||
/* Operating Mode Flags */
|
||||
#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */
|
||||
#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */
|
||||
#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */
|
||||
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
||||
In this case the SLAK bit can be polled.*/
|
||||
|
||||
/* Error Flags */
|
||||
#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */
|
||||
#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */
|
||||
#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */
|
||||
|
||||
#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_BOF) || \
|
||||
((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
|
||||
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
|
||||
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_SLAK) || \
|
||||
((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
|
||||
((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0))
|
||||
|
||||
|
||||
#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_RQCP1) || \
|
||||
((FLAG) == CAN_FLAG_RQCP0) || ((FLAG) == CAN_FLAG_FF0) || \
|
||||
((FLAG) == CAN_FLAG_FOV0) || ((FLAG) == CAN_FLAG_FF1) || \
|
||||
((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_WKU))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_interrupts
|
||||
* @{
|
||||
*/
|
||||
#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
|
||||
|
||||
/* Receive Interrupts */
|
||||
#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
|
||||
#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
|
||||
#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
|
||||
#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
|
||||
#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
|
||||
#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
|
||||
|
||||
/* Operating Mode Interrupts */
|
||||
#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
|
||||
#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
|
||||
|
||||
/* Error Interrupts */
|
||||
#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
|
||||
#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
|
||||
#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
|
||||
#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
|
||||
#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
|
||||
|
||||
/* Flags named as Interrupts : kept only for FW compatibility */
|
||||
#define CAN_IT_RQCP0 CAN_IT_TME
|
||||
#define CAN_IT_RQCP1 CAN_IT_TME
|
||||
#define CAN_IT_RQCP2 CAN_IT_TME
|
||||
|
||||
#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
|
||||
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
|
||||
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
|
||||
#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
|
||||
((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Time out for INAK bit */
|
||||
#define INAK_TIMEOUT ((uint32_t)0x00FFFFFF)
|
||||
/* Time out for SLAK bit */
|
||||
#define SLAK_TIMEOUT ((uint32_t)0x00FFFFFF)
|
||||
|
||||
/* Mailboxes definition */
|
||||
#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
|
||||
#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
|
||||
#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset CAN handle state
|
||||
* @param __HANDLE__: CAN handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified CAN interrupts
|
||||
* @param __HANDLE__: CAN handle.
|
||||
* @param __INTERRUPT__: CAN Interrupt.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified CAN interrupts
|
||||
* @param __HANDLE__: CAN handle.
|
||||
* @param __INTERRUPT__: CAN Interrupt.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Return the number of pending received messages.
|
||||
* @param __HANDLE__: CAN handle.
|
||||
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
|
||||
* @retval The number of pending message.
|
||||
*/
|
||||
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
|
||||
((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
|
||||
|
||||
/** @brief Check whether the specified CAN flag is set or not.
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
|
||||
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
|
||||
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
|
||||
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
|
||||
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
|
||||
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
|
||||
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
|
||||
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
|
||||
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
|
||||
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
|
||||
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
|
||||
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
|
||||
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
|
||||
* @arg CAN_FLAG_WKU: Wake up Flag
|
||||
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
|
||||
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
|
||||
* @arg CAN_FLAG_EWG: Error Warning Flag
|
||||
* @arg CAN_FLAG_EPV: Error Passive Flag
|
||||
* @arg CAN_FLAG_BOF: Bus-Off Flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define CAN_FLAG_MASK ((uint32_t)0x000000FF)
|
||||
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
|
||||
|
||||
/** @brief Clear the specified CAN pending flag.
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
|
||||
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
|
||||
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
|
||||
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
|
||||
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
|
||||
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
|
||||
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
|
||||
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
|
||||
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
|
||||
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
|
||||
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
|
||||
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
|
||||
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
|
||||
* @arg CAN_FLAG_WKU: Wake up Flag
|
||||
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0)
|
||||
|
||||
|
||||
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @param __INTERRUPT__: specifies the CAN interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
|
||||
* @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
|
||||
* @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Check the transmission status of a CAN Frame.
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
|
||||
* @retval The new status of transmission (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
|
||||
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
|
||||
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
|
||||
((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Release the specified receive FIFO.
|
||||
* @param __HANDLE__: CAN handle.
|
||||
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
|
||||
((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
|
||||
|
||||
/**
|
||||
* @brief Cancel a transmit request.
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
|
||||
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
|
||||
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
|
||||
((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
|
||||
|
||||
/**
|
||||
* @brief Enable or disables the DBG Freeze for CAN.
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @param __NEWSTATE__: new state of the CAN peripheral.
|
||||
* This parameter can be: ENABLE (CAN reception/transmission is frozen
|
||||
* during debug. Reception FIFOs can still be accessed/controlled normally)
|
||||
* or DISABLE (CAN is working during debug).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
|
||||
((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
|
||||
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
|
||||
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
|
||||
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
|
||||
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
|
||||
|
||||
void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(STM32F302x8) || defined(STM32F302xC) || */
|
||||
/* defined(STM32F303x8) || defined(STM32F303xC) || defined(STM32F373xC) || */
|
||||
/* defined(STM32F334x8) || */
|
||||
/* defined(STM32F328xx) || defined(STM32F358xx) || defined(STM32F378xx) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_CAN_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,562 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_cec.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of CEC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_CEC_H
|
||||
#define __STM32F3xx_HAL_CEC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief CEC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
|
||||
It can be one of @ref CEC_Signal_Free_Time
|
||||
and belongs to the set {0,...,7} where
|
||||
0x0 is the default configuration
|
||||
else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
|
||||
|
||||
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
|
||||
it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
|
||||
or CEC_EXTENDED_TOLERANCE */
|
||||
|
||||
uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
|
||||
CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
|
||||
CEC_RX_STOP_ON_BRE: reception is stopped. */
|
||||
|
||||
uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
|
||||
CEC line upon Bit Rising Error detection.
|
||||
CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
|
||||
CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
|
||||
|
||||
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
|
||||
CEC line upon Long Bit Period Error detection.
|
||||
CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
|
||||
CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
|
||||
|
||||
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
|
||||
upon an error detected on a broadcast message.
|
||||
|
||||
It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
|
||||
|
||||
1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
|
||||
a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
|
||||
and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
|
||||
b) LBPE detection: error-bit generation on the CEC line
|
||||
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
|
||||
|
||||
2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
|
||||
no error-bit generation in case neither a) nor b) are satisfied. Additionally,
|
||||
there is no error-bit generation in case of Short Bit Period Error detection in
|
||||
a broadcast message while LSTN bit is set. */
|
||||
|
||||
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
|
||||
CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
|
||||
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
|
||||
|
||||
uint32_t OwnAddress; /*!< Set OAR field, specifies CEC device address within a 15-bit long field */
|
||||
|
||||
uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
|
||||
|
||||
CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
|
||||
own address (OAR). Messages addressed to different destination are ignored.
|
||||
Broadcast messages are always received.
|
||||
|
||||
CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
|
||||
address (OAR) with positive acknowledge. Messages addressed to different destination
|
||||
are received, but without interfering with the CEC bus: no acknowledge sent. */
|
||||
|
||||
uint8_t InitiatorAddress; /* Initiator address (source logical address, sent in each header) */
|
||||
|
||||
}CEC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CEC State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */
|
||||
HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_CEC_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
|
||||
HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
|
||||
HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
|
||||
HAL_CEC_STATE_STANDBY_RX = 0x05, /*!< IP ready to receive, doesn't prevent IP to transmit */
|
||||
HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */
|
||||
HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */
|
||||
}HAL_CEC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Error structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CEC_ERROR_NONE = (uint32_t) 0x0, /*!< no error */
|
||||
HAL_CEC_ERROR_RXOVR = CEC_ISR_RXOVR, /*!< CEC Rx-Overrun */
|
||||
HAL_CEC_ERROR_BRE = CEC_ISR_BRE, /*!< CEC Rx Bit Rising Error */
|
||||
HAL_CEC_ERROR_SBPE = CEC_ISR_SBPE, /*!< CEC Rx Short Bit period Error */
|
||||
HAL_CEC_ERROR_LBPE = CEC_ISR_LBPE, /*!< CEC Rx Long Bit period Error */
|
||||
HAL_CEC_ERROR_RXACKE = CEC_ISR_RXACKE, /*!< CEC Rx Missing Acknowledge */
|
||||
HAL_CEC_ERROR_ARBLST = CEC_ISR_ARBLST, /*!< CEC Arbitration Lost */
|
||||
HAL_CEC_ERROR_TXUDR = CEC_ISR_TXUDR, /*!< CEC Tx-Buffer Underrun */
|
||||
HAL_CEC_ERROR_TXERR = CEC_ISR_TXERR, /*!< CEC Tx-Error */
|
||||
HAL_CEC_ERROR_TXACKE = CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
|
||||
}
|
||||
HAL_CEC_ErrorTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CEC handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CEC_TypeDef *Instance; /* CEC registers base address */
|
||||
|
||||
CEC_InitTypeDef Init; /* CEC communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /* Pointer to CEC Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferCount; /* CEC Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /* Pointer to CEC Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /* CEC Rx Transfer size, 0: header received only */
|
||||
|
||||
uint32_t ErrorCode; /* For errors handling purposes, copy of ISR register
|
||||
in case error is reported */
|
||||
|
||||
HAL_LockTypeDef Lock; /* Locking object */
|
||||
|
||||
HAL_CEC_StateTypeDef State; /* CEC communication state */
|
||||
|
||||
}CEC_HandleTypeDef;
|
||||
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Signal_Free_Time Signal Free Time setting parameter
|
||||
* @{
|
||||
*/
|
||||
#define CEC_DEFAULT_SFT ((uint32_t)0x00000000)
|
||||
#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001)
|
||||
#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002)
|
||||
#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003)
|
||||
#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004)
|
||||
#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005)
|
||||
#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006)
|
||||
#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007)
|
||||
#define IS_CEC_SIGNALFREETIME(SFT) ((SFT) <= CEC_CFGR_SFT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Tolerance Receiver Tolerance
|
||||
* @{
|
||||
*/
|
||||
#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000)
|
||||
#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
|
||||
#define IS_CEC_TOLERANCE(RXTOL) (((RXTOL) == CEC_STANDARD_TOLERANCE) || \
|
||||
((RXTOL) == CEC_EXTENDED_TOLERANCE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BRERxStop Reception Stop on Error
|
||||
* @{
|
||||
*/
|
||||
#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000)
|
||||
#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
|
||||
#define IS_CEC_BRERXSTOP(BRERXSTOP) (((BRERXSTOP) == CEC_NO_RX_STOP_ON_BRE) || \
|
||||
((BRERXSTOP) == CEC_RX_STOP_ON_BRE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BREErrorBitGen Error Bit Generation if Bit Rise Error reported
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
|
||||
#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
|
||||
#define IS_CEC_BREERRORBITGEN(ERRORBITGEN) (((ERRORBITGEN) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
|
||||
((ERRORBITGEN) == CEC_BRE_ERRORBIT_GENERATION))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_LBPEErrorBitGen Error Bit Generation if Long Bit Period Error reported
|
||||
* @{
|
||||
*/
|
||||
#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
|
||||
#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
|
||||
#define IS_CEC_LBPEERRORBITGEN(ERRORBITGEN) (((ERRORBITGEN) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
|
||||
((ERRORBITGEN) == CEC_LBPE_ERRORBIT_GENERATION))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BroadCastMsgErrorBitGen Error Bit Generation on Broadcast message
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000)
|
||||
#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
|
||||
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(ERRORBITGEN) (((ERRORBITGEN) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
|
||||
((ERRORBITGEN) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_SFT_Option Signal Free Time start option
|
||||
* @{
|
||||
*/
|
||||
#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000)
|
||||
#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
|
||||
#define IS_CEC_SFTOP(SFTOP) (((SFTOP) == CEC_SFT_START_ON_TXSOM) || \
|
||||
((SFTOP) == CEC_SFT_START_ON_TX_RX_END))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Listening_Mode Listening mode option
|
||||
* @{
|
||||
*/
|
||||
#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000)
|
||||
#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
|
||||
#define IS_CEC_LISTENING_MODE(MODE) (((MODE) == CEC_REDUCED_LISTENING_MODE) || \
|
||||
((MODE) == CEC_FULL_LISTENING_MODE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_ALL_ERROR all RX or TX errors flags in CEC ISR register
|
||||
* @{
|
||||
*/
|
||||
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
|
||||
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_IER_ALL_RX all RX errors interrupts enabling flag
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_IER_ALL_TX all TX errors interrupts enabling flag
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_OAR_Position Device Own Address position in CEC CFGR register
|
||||
* @{
|
||||
*/
|
||||
#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Initiator_Position Initiator logical address position in message header
|
||||
* @{
|
||||
*/
|
||||
#define CEC_INITIATOR_LSB_POS ((uint32_t) 4)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CEC handle state
|
||||
* @param __HANDLE__: CEC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
|
||||
|
||||
/** @brief Checks whether or not the specified CEC interrupt flag is set.
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @param __INTERRUPT__: specifies the interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_ISR_RXBR : Rx-Byte Received
|
||||
* @arg CEC_ISR_RXEND : End of Reception
|
||||
* @arg CEC_ISR_RXOVR : Rx Overrun
|
||||
* @arg CEC_ISR_BRE : Rx Bit Rising Error
|
||||
* @arg CEC_ISR_SBPE : Rx Short Bit Period Error
|
||||
* @arg CEC_ISR_LBPE : Rx Long Bit Period Error
|
||||
* @arg CEC_ISR_RXACKE : Rx Missing Acknowledge
|
||||
* @arg CEC_ISR_ARBLST : Arbitration lost
|
||||
* @arg CEC_ISR_TXBR : Tx-Byte Request
|
||||
* @arg CEC_ISR_TXEND : End of Transmission
|
||||
* @arg CEC_ISR_TXUDR : Tx-buffer Underrun
|
||||
* @arg CEC_ISR_TXERR : Tx Error
|
||||
* @arg CEC_ISR_TXACKE : Tx Missing Acknowledge
|
||||
* @retval ITStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__))
|
||||
|
||||
/** @brief Clears the interrupt or status flag when raised (write at 1)
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @param __FLAG__: specifies the interrupt/status flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_ISR_RXBR : Rx-Byte Received
|
||||
* @arg CEC_ISR_RXEND : End of Reception
|
||||
* @arg CEC_ISR_RXOVR : Rx Overrun
|
||||
* @arg CEC_ISR_BRE : Rx Bit Rising Error
|
||||
* @arg CEC_ISR_SBPE : Rx Short Bit Period Error
|
||||
* @arg CEC_ISR_LBPE : Rx Long Bit Period Error
|
||||
* @arg CEC_ISR_RXACKE : Rx Missing Acknowledge
|
||||
* @arg CEC_ISR_ARBLST : Arbitration lost
|
||||
* @arg CEC_ISR_TXBR : Tx-Byte Request
|
||||
* @arg CEC_ISR_TXEND : End of Transmission
|
||||
* @arg CEC_ISR_TXUDR : Tx-buffer Underrun
|
||||
* @arg CEC_ISR_TXERR : Tx Error
|
||||
* @arg CEC_ISR_TXACKE : Tx Missing Acknowledge
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR = (__FLAG__))
|
||||
|
||||
/** @brief Enables the specified CEC interrupt.
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @param __INTERRUPT__: specifies the CEC interrupt to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IER_RXBRIE : Rx-Byte Received IT Enable
|
||||
* @arg CEC_IER_RXENDIE : End Of Reception IT Enable
|
||||
* @arg CEC_IER_RXOVRIE : Rx-Overrun IT Enable
|
||||
* @arg CEC_IER_BREIE : Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IER_SBPEIE : Rx Short Bit period Error IT Enable
|
||||
* @arg CEC_IER_LBPEIE : Rx Long Bit period Error IT Enable
|
||||
* @arg CEC_IER_RXACKEIE : Rx Missing Acknowledge IT Enable
|
||||
* @arg CEC_IER_ARBLSTIE : Arbitration Lost IT Enable
|
||||
* @arg CEC_IER_TXBRIE : Tx Byte Request IT Enable
|
||||
* @arg CEC_IER_TXENDIE : End of Transmission IT Enable
|
||||
* @arg CEC_IER_TXUDRIE : Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IER_TXERRIE : Tx-Error IT Enable
|
||||
* @arg CEC_IER_TXACKEIE : Tx Missing Acknowledge IT Enable
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disables the specified CEC interrupt.
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @param __INTERRUPT__: specifies the CEC interrupt to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IER_RXBRIE : Rx-Byte Received IT Enable
|
||||
* @arg CEC_IER_RXENDIE : End Of Reception IT Enable
|
||||
* @arg CEC_IER_RXOVRIE : Rx-Overrun IT Enable
|
||||
* @arg CEC_IER_BREIE : Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IER_SBPEIE : Rx Short Bit period Error IT Enable
|
||||
* @arg CEC_IER_LBPEIE : Rx Long Bit period Error IT Enable
|
||||
* @arg CEC_IER_RXACKEIE : Rx Missing Acknowledge IT Enable
|
||||
* @arg CEC_IER_ARBLSTIE : Arbitration Lost IT Enable
|
||||
* @arg CEC_IER_TXBRIE : Tx Byte Request IT Enable
|
||||
* @arg CEC_IER_TXENDIE : End of Transmission IT Enable
|
||||
* @arg CEC_IER_TXUDRIE : Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IER_TXERRIE : Tx-Error IT Enable
|
||||
* @arg CEC_IER_TXACKEIE : Tx Missing Acknowledge IT Enable
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Checks whether or not the specified CEC interrupt is enabled.
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @param __INTERRUPT__: specifies the CEC interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IER_RXBRIE : Rx-Byte Received IT Enable
|
||||
* @arg CEC_IER_RXENDIE : End Of Reception IT Enable
|
||||
* @arg CEC_IER_RXOVRIE : Rx-Overrun IT Enable
|
||||
* @arg CEC_IER_BREIE : Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IER_SBPEIE : Rx Short Bit period Error IT Enable
|
||||
* @arg CEC_IER_LBPEIE : Rx Long Bit period Error IT Enable
|
||||
* @arg CEC_IER_RXACKEIE : Rx Missing Acknowledge IT Enable
|
||||
* @arg CEC_IER_ARBLSTIE : Arbitration Lost IT Enable
|
||||
* @arg CEC_IER_TXBRIE : Tx Byte Request IT Enable
|
||||
* @arg CEC_IER_TXENDIE : End of Transmission IT Enable
|
||||
* @arg CEC_IER_TXUDRIE : Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IER_TXERRIE : Tx-Error IT Enable
|
||||
* @arg CEC_IER_TXACKEIE : Tx Missing Acknowledge IT Enable
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
|
||||
|
||||
/** @brief Enables the CEC device
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
|
||||
|
||||
/** @brief Disables the CEC device
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
|
||||
|
||||
/** @brief Set Transmission Start flag
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
|
||||
|
||||
/** @brief Set Transmission End flag
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval none
|
||||
* If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
|
||||
*/
|
||||
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
|
||||
|
||||
/** @brief Get Transmission Start flag
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
|
||||
|
||||
/** @brief Get Transmission End flag
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
|
||||
|
||||
/** @brief Clear OAR register
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
|
||||
|
||||
/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
|
||||
* To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
|
||||
|
||||
/** @brief Check CEC device Own Address Register (OAR) setting.
|
||||
* OAR address is written in a 15-bit field within CEC_CFGR register.
|
||||
* @param __ADDRESS__: CEC own address.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF)
|
||||
|
||||
/** @brief Check CEC initiator or destination logical address setting.
|
||||
* Initiator and destination addresses are coded over 4 bits.
|
||||
* @param __ADDRESS__: CEC initiator or logical address.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
|
||||
|
||||
/** @brief Check CEC message size.
|
||||
* The message size is the payload size: without counting the header,
|
||||
* it varies from 0 byte (ping operation, one header only, no payload) to
|
||||
* 15 bytes (1 opcode and up to 14 operands following the header).
|
||||
* @param __SIZE__: CEC message size.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
|
||||
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
|
||||
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
|
||||
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
|
||||
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
|
||||
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(STM32F373xC) || defined(STM32F378xx) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_CEC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,663 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_comp.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief COMP HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the COMP peripheral:
|
||||
* + Initialization/de-initialization functions
|
||||
* + I/O operation functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
================================================================================
|
||||
##### COMP Peripheral features #####
|
||||
================================================================================
|
||||
|
||||
[..]
|
||||
The STM32F3xx device family integrates up to 7 analog comparators COMP1, COMP2...COMP7:
|
||||
(#) The non inverting input and inverting input can be set to GPIO pins
|
||||
as shown in table1. COMP Inputs below for STM32F303xB/STM32F303xC as example.
|
||||
For other STM32F3xx devices please refer to the COMP peripheral section in corresponding
|
||||
Reference Manual.
|
||||
|
||||
(#) The COMP output is available using HAL_COMP_GetOutputLevel()
|
||||
and can be set on GPIO pins. Refer to table 2. COMP Outputs below for STM32F303xB/STM32F303xC as example.
|
||||
For other STM32F3xx devices please refer to the COMP peripheral section in corresponding
|
||||
Reference Manual.
|
||||
|
||||
(#) The COMP output can be redirected to embedded timers (TIM1, TIM2, TIM3...)
|
||||
Refer to table 3. COMP Outputs redirection to embedded timers below for STM32F303xB/STM32F303xC as example.
|
||||
For other STM32F3xx devices please refer to the COMP peripheral section in corresponding
|
||||
Reference Manual.
|
||||
|
||||
(#) The comparators COMP1 and COMP2, COMP3 and COMP4, COMP5 and COMP6 can be combined in window
|
||||
mode and only COMP1, COMP3 and COMP5 non inverting input can be used as non-inverting input.
|
||||
|
||||
(#) The seven comparators have interrupt capability with wake-up
|
||||
from Sleep and Stop modes (through the EXTI controller):
|
||||
(++) COMP1 is internally connected to EXTI Line 21
|
||||
(++) COMP2 is internally connected to EXTI Line 22
|
||||
(++) COMP3 is internally connected to EXTI Line 29
|
||||
(++) COMP4 is internally connected to EXTI Line 30
|
||||
(++) COMP5 is internally connected to EXTI Line 31
|
||||
(++) COMP6 is internally connected to EXTI Line 32
|
||||
(++) COMP7 is internally connected to EXTI Line 33
|
||||
From the corresponding IRQ handler, the right interrupt source can be retrieved with the
|
||||
macro __HAL_COMP_EXTI_GET_FLAG(). Possible values are:
|
||||
(++) COMP_EXTI_LINE_COMP1_EVENT
|
||||
(++) COMP_EXTI_LINE_COMP2_EVENT
|
||||
(++) COMP_EXTI_LINE_COMP3_EVENT
|
||||
(++) COMP_EXTI_LINE_COMP4_EVENT
|
||||
(++) COMP_EXTI_LINE_COMP5_EVENT
|
||||
(++) COMP_EXTI_LINE_COMP6_EVENT
|
||||
(++) COMP_EXTI_LINE_COMP7_EVENT
|
||||
|
||||
[..] Table 1. COMP Inputs for the STM32F303xB/STM32F303xC devices
|
||||
+------------------------------------------------------------------------------------------+
|
||||
| | | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|
||||
|-----------------|----------------|---------------|---------------------------------------|
|
||||
| | 1/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | 1/2 VREFINT | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | 3/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
|
||||
| Inverting Input | VREFINT | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | DAC1 OUT (PA4) | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | DAC2 OUT (PA5) | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | IO1 | PA0 | PA2 | PD15 | PE8 | PD13 | PD10 | PC0 |
|
||||
| | IO2 | --- | --- | PB12 | PB2 | PB10 | PB15 | --- |
|
||||
|-----------------|----------------|-------|-------|-------|-------|-------|-------|-------|
|
||||
| Non Inverting | IO1 | PA1 | PA7 | PB14 | PB0 | PD12 | PD11 | PA0 |
|
||||
| Input | IO2 | --- | PA3 | PD14 | PE7 | PB13 | PB11 | PC1 |
|
||||
+------------------------------------------------------------------------------------------+
|
||||
|
||||
[..] Table 2. COMP Outputs for the STM32F303xB/STM32F303xC devices
|
||||
+-------------------------------------------------------+
|
||||
| COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|
||||
|-------|-------|-------|-------|-------|-------|-------|
|
||||
| PA0 | PA2 | PB1 | PC8 | PC7 | PA10 | PC2 |
|
||||
| PF4 | PA7 | --- | PA8 | PA9 | PC6 | --- |
|
||||
| PA6 | PA12 | --- | --- | --- | --- | --- |
|
||||
| PA11 | PB9 | --- | --- | --- | --- | --- |
|
||||
| PB8 | --- | --- | --- | --- | --- | --- |
|
||||
+-------------------------------------------------------+
|
||||
|
||||
[..] Table 3. COMP Outputs redirection to embedded timers for the STM32F303xB/STM32F303xC devices
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
| COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|
||||
|----------------|----------------|----------------|----------------|----------------|----------------|----------------|
|
||||
| TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN |
|
||||
| | | | | | | |
|
||||
| TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
|
||||
| | | | | | | |
|
||||
| TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN |
|
||||
| | | | | | | |
|
||||
| TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 |
|
||||
| | | | | | | |
|
||||
| TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
|
||||
| + | + | + | + | + | + | + |
|
||||
| TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 |
|
||||
| | | | | | | |
|
||||
| TIM1 OCREFCLR | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM1 OCREFCLR |
|
||||
| | | | | | | |
|
||||
| TIM1 IC1 | TIM1 IC1 | TIM2 OCREFCLR | TIM3 IC3 | TIM2 IC1 | TIM2 IC2 | TIM8 OCREFCLR |
|
||||
| | | | | | | |
|
||||
| TIM2 IC4 | TIM2 IC4 | TIM3 IC2 | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM2 OCREFCLR | TIM2 IC3 |
|
||||
| | | | | | | |
|
||||
| TIM2 OCREFCLR | TIM2 OCREFCLR | TIM4 IC1 | TIM4 IC2 | TIM4 IC3 | TIM16 OCREFCLR| TIM1 IC2 |
|
||||
| | | | | | | |
|
||||
| TIM3 IC1 | TIM3 IC1 | TIM15 IC1 | TIM15 OCREFCLR| TIM16 BKIN | TIM16 IC1 | TIM17 OCREFCLR|
|
||||
| | | | | | | |
|
||||
| TIM3 OCREFCLR | TIM3 OCREFCLR | TIM15 BKIN | TIM15 IC2 | TIM17 IC1 | TIM4 IC4 | TIM17 BKIN |
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
[..] Table 4. COMP Outputs blanking sources for the STM32F303xB/STM32F303xC devices
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
| COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|
||||
|----------------|----------------|----------------|----------------|----------------|----------------|----------------|
|
||||
| TIM1 OC5 | TIM1 OC5 | TIM1 OC5 | TIM3 OC4 | TIM3 OC3 | TIM2 OC4 | TIM1 OC5 |
|
||||
| | | | | | | |
|
||||
| TIM2 OC3 | TIM2 OC3 | -------- | TIM8 OC5 | TIM8 OC5 | TIM8 OC5 | TIM8 OC5 |
|
||||
| | | | | | | |
|
||||
| TIM3 OC3 | TIM3 OC3 | TIM2 OC4 | TIM15 OC1 | TIM8 BKIN | TIM15 OC2 | TIM15 OC2 |
|
||||
| | | | | | | |
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
##### How to use this driver #####
|
||||
================================================================================
|
||||
[..]
|
||||
This driver provides functions to configure and program the Comparators of all STM32F3xx devices.
|
||||
|
||||
To use the comparator, perform the following steps:
|
||||
|
||||
(#) Fill in the HAL_COMP_MspInit() to
|
||||
(++) Configure the comparator input in analog mode using HAL_GPIO_Init()
|
||||
(++) Configure the comparator output in alternate function mode using HAL_GPIO_Init() to map the comparator
|
||||
output to the GPIO pin
|
||||
(++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
|
||||
selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
|
||||
interrupt vector using HAL_NVIC_EnableIRQ() function.
|
||||
|
||||
(#) Configure the comparator using HAL_COMP_Init() function:
|
||||
(++) Select the inverting input
|
||||
(++) Select the non-inverting input
|
||||
(++) Select the output polarity
|
||||
(++) Select the output redirection
|
||||
(++) Select the hysteresis level
|
||||
(++) Select the power mode
|
||||
(++) Select the event/interrupt mode
|
||||
|
||||
(#) Enable the comparator using HAL_COMP_Start() function or HAL_COMP_Start_IT() function for interrupt mode
|
||||
|
||||
(#) Read the comparator output level with HAL_COMP_GetOutputLevel()
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP
|
||||
* @brief COMP HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_COMP_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup COMP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_COMP_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization/de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions to initialize and de-initialize comparators
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the COMP according to the specified
|
||||
* parameters in the COMP_InitTypeDef and create the associated handle.
|
||||
* @note If the selected comparator is locked, initialization can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param hcomp: COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
assert_param(IS_COMP_INVERTINGINPUT(hcomp->Init.InvertingInput));
|
||||
assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput));
|
||||
assert_param(IS_COMP_NONINVERTINGINPUT_INSTANCE(hcomp->Instance, hcomp->Init.NonInvertingInput));
|
||||
assert_param(IS_COMP_OUTPUT(hcomp->Init.Output));
|
||||
assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
|
||||
assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
|
||||
assert_param(IS_COMP_MODE(hcomp->Init.Mode));
|
||||
assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce));
|
||||
assert_param(IS_COMP_BLANKINGSRCE_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce));
|
||||
|
||||
if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLED)
|
||||
{
|
||||
assert_param(IS_COMP_WINDOWMODE_INSTANCE(hcomp->Instance));
|
||||
}
|
||||
|
||||
if(hcomp->State == HAL_COMP_STATE_RESET)
|
||||
{
|
||||
/* Init SYSCFG and the low level hardware to access comparators */
|
||||
__SYSCFG_CLK_ENABLE();
|
||||
|
||||
HAL_COMP_MspInit(hcomp);
|
||||
}
|
||||
|
||||
/* Set COMP parameters */
|
||||
/* Set COMPxINSEL bits according to hcomp->Init.InvertingInput value */
|
||||
/* Set COMPxNONINSEL bits according to hcomp->Init.NonInvertingInput value */
|
||||
/* Set COMPxBLANKING bits according to hcomp->Init.BlankingSrce value */
|
||||
/* Set COMPxOUTSEL bits according to hcomp->Init.Output value */
|
||||
/* Set COMPxPOL bit according to hcomp->Init.OutputPol value */
|
||||
/* Set COMPxHYST bits according to hcomp->Init.Hysteresis value */
|
||||
/* Set COMPxMODE bits according to hcomp->Init.Mode value */
|
||||
COMP_INIT(hcomp);
|
||||
|
||||
/* Initialize the COMP state*/
|
||||
if(hcomp->State == HAL_COMP_STATE_RESET)
|
||||
{
|
||||
hcomp->State = HAL_COMP_STATE_READY;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the COMP peripheral
|
||||
* @note Deinitialization can't be performed if the COMP configuration is locked.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param hcomp: COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
/* Set COMP_CSR register to reset value */
|
||||
COMP_DEINIT(hcomp);
|
||||
|
||||
/* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */
|
||||
HAL_COMP_MspDeInit(hcomp);
|
||||
|
||||
hcomp->State = HAL_COMP_STATE_RESET;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the COMP MSP.
|
||||
* @param hcomp: COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_COMP_MspInit could be implenetd in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes COMP MSP.
|
||||
* @param hcomp: COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_COMP_MspDeInit could be implenetd in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_COMP_Group2 I/O operation functions
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to manage the COMP data
|
||||
transfers.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start the comparator
|
||||
* @param hcomp: COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
if(hcomp->State == HAL_COMP_STATE_READY)
|
||||
{
|
||||
/* Enable the selected comparator */
|
||||
COMP_START(hcomp);
|
||||
|
||||
hcomp->State = HAL_COMP_STATE_BUSY;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop the comparator
|
||||
* @param hcomp: COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
if(hcomp->State == HAL_COMP_STATE_BUSY)
|
||||
{
|
||||
/* Disable the selected comparator */
|
||||
COMP_STOP(hcomp);
|
||||
|
||||
hcomp->State = HAL_COMP_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the interrupt and starts the comparator
|
||||
* @param hcomp: COMP handle
|
||||
* @retval HAL status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t extiline = 0;
|
||||
|
||||
status = HAL_COMP_Start(hcomp);
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Check the Exti Line output configuration */
|
||||
extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance);
|
||||
/* Configure the rising edge */
|
||||
if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET)
|
||||
{
|
||||
__HAL_COMP_EXTI_RISING_IT_ENABLE(extiline);
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_COMP_EXTI_RISING_IT_DISABLE(extiline);
|
||||
}
|
||||
/* Configure the falling edge */
|
||||
if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET)
|
||||
{
|
||||
__HAL_COMP_EXTI_FALLING_IT_ENABLE(extiline);
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_COMP_EXTI_FALLING_IT_DISABLE(extiline);
|
||||
}
|
||||
/* Enable Exti interrupt mode */
|
||||
__HAL_COMP_EXTI_ENABLE_IT(extiline);
|
||||
/* Clear COMP Exti pending bit */
|
||||
__HAL_COMP_EXTI_CLEAR_FLAG(extiline);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the interrupt and Stop the comparator
|
||||
* @param hcomp: COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Disable the Exti Line interrupt mode */
|
||||
__HAL_COMP_EXTI_DISABLE_IT(__HAL_COMP_GET_EXTI_LINE(hcomp->Instance));
|
||||
|
||||
status = HAL_COMP_Stop(hcomp);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Comparator IRQ Handler
|
||||
* @param hcomp: COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
uint32_t extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance);
|
||||
|
||||
/* Check COMP Exti flag */
|
||||
if(__HAL_COMP_EXTI_GET_FLAG(extiline) != RESET)
|
||||
{
|
||||
/* Clear COMP Exti pending bit */
|
||||
__HAL_COMP_EXTI_CLEAR_FLAG(extiline);
|
||||
|
||||
/* COMP trigger user callback */
|
||||
HAL_COMP_TriggerCallback(hcomp);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_COMP_Group3 Peripheral Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the COMP data
|
||||
transfers.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Lock the selected comparator configuration.
|
||||
* @param hcomp: COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
/* Set lock flag */
|
||||
hcomp->State |= COMP_STATE_BIT_LOCK;
|
||||
|
||||
/* Set the lock bit corresponding to selected comparator */
|
||||
COMP_LOCK(hcomp);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the output level (high or low) of the selected comparator.
|
||||
* The output level depends on the selected polarity.
|
||||
* If the polarity is not inverted:
|
||||
* - Comparator output is low when the non-inverting input is at a lower
|
||||
* voltage than the inverting input
|
||||
* - Comparator output is high when the non-inverting input is at a higher
|
||||
* voltage than the inverting input
|
||||
* If the polarity is inverted:
|
||||
* - Comparator output is high when the non-inverting input is at a lower
|
||||
* voltage than the inverting input
|
||||
* - Comparator output is low when the non-inverting input is at a higher
|
||||
* voltage than the inverting input
|
||||
* @param hcomp: COMP handle
|
||||
* @retval Returns the selected comparator output level: COMP_OUTPUTLEVEL_LOW or COMP_OUTPUTLEVEL_HIGH.
|
||||
*
|
||||
*/
|
||||
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
uint32_t level=0;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
level = READ_BIT(hcomp->Instance->CSR, COMP_CSR_COMPxOUT);
|
||||
|
||||
if(level != 0)
|
||||
{
|
||||
return(COMP_OUTPUTLEVEL_HIGH);
|
||||
}
|
||||
return(COMP_OUTPUTLEVEL_LOW);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Comparator callback.
|
||||
* @param hcomp: COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_COMP_TriggerCallback should be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_COMP_Group4 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permit to get in run-time the status of the peripheral
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the COMP state
|
||||
* @param hcomp : COMP handle
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Check the COMP handle allocation */
|
||||
if(hcomp == NULL)
|
||||
{
|
||||
return HAL_COMP_STATE_RESET;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
return hcomp->State;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_COMP_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,228 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_comp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of COMP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_COMP_H
|
||||
#define __STM32F3xx_HAL_COMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief COMP Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t InvertingInput; /*!< Selects the inverting input of the comparator.
|
||||
This parameter can be a value of @ref COMPEx_InvertingInput */
|
||||
|
||||
uint32_t NonInvertingInput; /*!< Selects the non inverting input of the comparator.
|
||||
This parameter can be a value of @ref COMPEx_NonInvertingInput
|
||||
Note: Only available on STM32F302xB/xC, STM32F303xB/xC and STM32F358xx devices */
|
||||
|
||||
uint32_t Output; /*!< Selects the output redirection of the comparator.
|
||||
This parameter can be a value of @ref COMPEx_Output */
|
||||
|
||||
uint32_t OutputPol; /*!< Selects the output polarity of the comparator.
|
||||
This parameter can be a value of @ref COMP_OutputPolarity */
|
||||
|
||||
uint32_t Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
|
||||
This parameter can be a value of @ref COMPEx_Hysteresis
|
||||
Note: Only available on STM32F302xB/xC, STM32F303xB/xC, STM32F373xB/xC, STM32F358xx and STM32F378xx devices */
|
||||
|
||||
uint32_t BlankingSrce; /*!< Selects the output blanking source of the comparator.
|
||||
This parameter can be a value of @ref COMPEx_BlankingSrce
|
||||
Note: Not available on STM32F373xB/C and STM32F378xx devices */
|
||||
|
||||
uint32_t Mode; /*!< Selects the operating comsumption mode of the comparator
|
||||
to adjust the speed/consumption.
|
||||
This parameter can be a value of @ref COMPEx_Mode
|
||||
Note: Not available on STM32F301x6/x8, STM32F302x6/x8, STM32F334x6/x8, STM32F318xx and STM32F328xx devices */
|
||||
|
||||
uint32_t WindowMode; /*!< Selects the window mode of the comparator X (X=2, 4 or 6 if available).
|
||||
This parameter can be a value of @ref COMPEx_WindowMode */
|
||||
|
||||
uint32_t TriggerMode; /*!< Selects the trigger mode of the comparator (interrupt mode).
|
||||
This parameter can be a value of @ref COMP_TriggerMode */
|
||||
|
||||
}COMP_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_COMP_STATE_RESET = 0x00, /*!< COMP not yet initialized or disabled */
|
||||
HAL_COMP_STATE_READY = 0x01, /*!< COMP initialized and ready for use */
|
||||
HAL_COMP_STATE_READY_LOCKED = 0x11, /*!< COMP initialized but the configuration is locked */
|
||||
HAL_COMP_STATE_BUSY = 0x02, /*!< COMP is running */
|
||||
HAL_COMP_STATE_BUSY_LOCKED = 0x12 /*!< COMP is running and the configuration is locked */
|
||||
}HAL_COMP_StateTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief PPP Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
COMP_TypeDef *Instance; /*!< Register base address */
|
||||
COMP_InitTypeDef Init; /*!< COMP required parameters */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
__IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */
|
||||
|
||||
}COMP_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup COMP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputPolarity
|
||||
* @{
|
||||
*/
|
||||
#define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */
|
||||
#define COMP_OUTPUTPOL_INVERTED COMP_CSR_COMPxPOL /*!< COMP output on GPIO is inverted */
|
||||
#define IS_COMP_OUTPUTPOL(POL) (((POL) == COMP_OUTPUTPOL_NONINVERTED) || \
|
||||
((POL) == COMP_OUTPUTPOL_INVERTED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputLevel
|
||||
* @{
|
||||
*/
|
||||
/* When output polarity is not inverted, comparator output is low when
|
||||
the non-inverting input is at a lower voltage than the inverting input*/
|
||||
#define COMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000)
|
||||
/* When output polarity is not inverted, comparator output is high when
|
||||
the non-inverting input is at a higher voltage than the inverting input */
|
||||
#define COMP_OUTPUTLEVEL_HIGH COMP_CSR_COMPxOUT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_TriggerMode
|
||||
* @{
|
||||
*/
|
||||
#define COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000) /*!< No External Interrupt trigger detection */
|
||||
#define COMP_TRIGGERMODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define COMP_TRIGGERMODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define COMP_TRIGGERMODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define IS_COMP_TRIGGERMODE(MODE) (((MODE) == COMP_TRIGGERMODE_NONE) || \
|
||||
((MODE) == COMP_TRIGGERMODE_IT_RISING) || \
|
||||
((MODE) == COMP_TRIGGERMODE_IT_FALLING) || \
|
||||
((MODE) == COMP_TRIGGERMODE_IT_RISING_FALLING))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define COMP_LOCK_DISABLE ((uint32_t)0x00000000)
|
||||
#define COMP_LOCK_ENABLE COMP_CSR_COMPxLOCK
|
||||
|
||||
#define COMP_STATE_BIT_LOCK ((uint32_t)0x10)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset COMP handle state
|
||||
* @param __HANDLE__: COMP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
|
||||
|
||||
/* Include COMP HAL Extension module */
|
||||
#include "stm32f3xx_hal_comp_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
|
||||
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
|
||||
|
||||
/* Callback in Interrupt mode */
|
||||
void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_COMP_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,311 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief HAL configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_CONF_H
|
||||
#define __STM32F3xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
#define HAL_ADC_MODULE_ENABLED
|
||||
#define HAL_CAN_MODULE_ENABLED
|
||||
#define HAL_CEC_MODULE_ENABLED
|
||||
#define HAL_COMP_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
#define HAL_CRC_MODULE_ENABLED
|
||||
#define HAL_DAC_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_HRTIM_MODULE_ENABLED
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
#define HAL_I2S_MODULE_ENABLED
|
||||
#define HAL_IRDA_MODULE_ENABLED
|
||||
#define HAL_IWDG_MODULE_ENABLED
|
||||
#define HAL_OPAMP_MODULE_ENABLED
|
||||
#define HAL_PCD_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_RTC_MODULE_ENABLED
|
||||
#define HAL_SDADC_MODULE_ENABLED
|
||||
#define HAL_SMARTCARD_MODULE_ENABLED
|
||||
#define HAL_SMBUS_MODULE_ENABLED
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_TSC_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
#define HAL_USART_MODULE_ENABLED
|
||||
#define HAL_WWDG_MODULE_ENABLED
|
||||
|
||||
/* ########################## HSE/HSI Values adaptation ##################### */
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
/**
|
||||
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
|
||||
* Timeout value
|
||||
*/
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT ((uint32_t)500) /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
|
||||
* Timeout value
|
||||
*/
|
||||
#if !defined (HSI_STARTUP_TIMEOUT)
|
||||
#define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */
|
||||
#endif /* HSI_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE ((uint32_t)40000)
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature. */
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
/**
|
||||
* @brief External clock source for I2S peripheral
|
||||
* This value is used by the I2S HAL module to compute the I2S clock source
|
||||
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||
* - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
|
||||
* - External clock not generated on EVAL 373
|
||||
*/
|
||||
#if !defined (EXTERNAL_CLOCK_VALUE)
|
||||
#define EXTERNAL_CLOCK_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY ((uint32_t)(1<<__NVIC_PRIO_BITS) - 1) /*!< tick interrupt priority (lowest by default) */
|
||||
#define USE_RTOS 0
|
||||
#define PREFETCH_ENABLE 1
|
||||
#define INSTRUCTION_CACHE_ENABLE 0
|
||||
#define DATA_CACHE_ENABLE 0
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/*#define USE_FULL_ASSERT 1*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CAN_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_can.h"
|
||||
#endif /* HAL_CAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CEC_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_cec.h"
|
||||
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_COMP_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_comp.h"
|
||||
#endif /* HAL_COMP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_dac.h"
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HRTIM_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_hrtim.h"
|
||||
#endif /* HAL_HRTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_OPAMP_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_opamp.h"
|
||||
#endif /* HAL_OPAMP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SDADC_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_sdadc.h"
|
||||
#endif /* HAL_SDADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_smbus.h"
|
||||
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TSC_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_tsc.h"
|
||||
#endif /* HAL_TSC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32f3xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_CONF_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,446 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_cortex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief CORTEX HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the CORTEX:
|
||||
* + Initialization/de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
* @verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
|
||||
[..]
|
||||
*** How to configure Interrupts using Cortex HAL driver ***
|
||||
===========================================================
|
||||
[..]
|
||||
This section provide functions allowing to configure the NVIC interrupts (IRQ).
|
||||
The Cortex-M4 exceptions are managed by CMSIS functions.
|
||||
|
||||
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
|
||||
function according to the following table.
|
||||
|
||||
@brief CORTEX_NVIC_Priority_Table
|
||||
The table below gives the allowed values of the pre-emption priority and subpriority according
|
||||
to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function
|
||||
==========================================================================================================================
|
||||
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||
==========================================================================================================================
|
||||
NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
|
||||
| | | 4 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
|
||||
| | | 3 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
|
||||
| | | 2 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
|
||||
| | | 1 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
|
||||
| | | 0 bits for subpriority
|
||||
==========================================================================================================================
|
||||
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
|
||||
|
||||
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
|
||||
|
||||
|
||||
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
|
||||
The pending IRQ priority will be managed only by the sub priority.
|
||||
|
||||
-@- IRQ priority order (sorted by highest to lowest priority):
|
||||
(+@) Lowest pre-emption priority
|
||||
(+@) Lowest sub priority
|
||||
(+@) Lowest hardware priority (IRQ number)
|
||||
|
||||
[..]
|
||||
*** How to configure Systick using Cortex HAL driver ***
|
||||
========================================================
|
||||
[..]
|
||||
Setup SysTick Timer for time base.
|
||||
|
||||
(+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
|
||||
is a CMSIS function that:
|
||||
(++) Configures the SysTick Reload register with value passed as function parameter.
|
||||
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
|
||||
(++) Resets the SysTick Counter register.
|
||||
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
|
||||
(++) Enables the SysTick Interrupt.
|
||||
(++) Starts the SysTick Counter.
|
||||
|
||||
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
|
||||
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
|
||||
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
|
||||
inside the stm32f3xx_hal_cortex.h file.
|
||||
|
||||
(+) You can change the SysTick IRQ priority by calling the
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
|
||||
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
|
||||
|
||||
(+) To adjust the SysTick time base, use the following formula:
|
||||
|
||||
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
|
||||
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
|
||||
(++) Reload Value should not exceed 0xFFFFFF
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX
|
||||
* @brief CORTEX HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_CORTEX_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provide the Cortex HAL driver functions allowing to configure Interrupts
|
||||
Systick functionalities
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Sets the priority grouping field (pre-emption priority and subpriority)
|
||||
* using the required unlock sequence.
|
||||
* @param PriorityGroup: The priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
|
||||
* 0 bits for subpriority
|
||||
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
||||
* The pending IRQ priority will be managed only by the subpriority.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
||||
|
||||
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
||||
NVIC_SetPriorityGrouping(PriorityGroup);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the priority of an interrupt.
|
||||
* @param IRQn: External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
|
||||
* @param PreemptPriority: The pre-emption priority for the IRQn channel.
|
||||
* This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
|
||||
* A lower priority value indicates a higher priority
|
||||
* @param SubPriority: the subpriority level for the IRQ channel.
|
||||
* This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
|
||||
* A lower priority value indicates a higher priority.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t prioritygroup = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
||||
|
||||
prioritygroup = NVIC_GetPriorityGrouping();
|
||||
|
||||
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
|
||||
* function should be called before.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Enable interrupt */
|
||||
NVIC_EnableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Disable interrupt */
|
||||
NVIC_DisableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initiates a system reset request to reset the MCU.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SystemReset(void)
|
||||
{
|
||||
/* System Reset */
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
* Counter is in free running mode to generate periodic interrupts.
|
||||
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
||||
* @retval status: - 0 Function succeeded.
|
||||
* - 1 Function failed.
|
||||
*/
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
||||
{
|
||||
return SysTick_Config(TicksNumb);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_CORTEX_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the CORTEX
|
||||
(NVIC, SYSTICK) functionalities.
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Gets the priority grouping field from the NVIC Interrupt Controller.
|
||||
* @param None
|
||||
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void)
|
||||
{
|
||||
/* Get the PRIGROUP[10:8] field value */
|
||||
return NVIC_GetPriorityGrouping();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the priority of an interrupt.
|
||||
* @param IRQn: External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
|
||||
* @param PriorityGroup: the priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
|
||||
* 0 bits for subpriority
|
||||
* @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
|
||||
* @param pSubPriority: Pointer on the Subpriority value (starting from 0).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
||||
/* Get priority for Cortex-M system or device specific interrupts */
|
||||
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets Pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Set interrupt pending */
|
||||
NVIC_SetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
|
||||
* and returns the pending bit for the specified interrupt).
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
|
||||
* @retval status: - 0 Interrupt status is not pending.
|
||||
* - 1 Interrupt status is pending.
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Return 1 if pending else 0 */
|
||||
return NVIC_GetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Clear pending interrupt */
|
||||
NVIC_ClearPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
|
||||
* @retval status: - 0 Interrupt status is not pending.
|
||||
* - 1 Interrupt status is pending.
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
|
||||
{
|
||||
/* Return 1 if active else 0 */
|
||||
return NVIC_GetActive(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param CLKSource: specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLKSOURCE(CLKSource));
|
||||
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles SYSTICK interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_IRQHandler(void)
|
||||
{
|
||||
HAL_SYSTICK_Callback();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SYSTICK callback.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SYSTICK_Callback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SYSTICK_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,164 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of CORTEX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_CORTEX_H
|
||||
#define __STM32F3xx_HAL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CORTEX_Preemption_Priority_Group
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_1) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_2) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_3) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_SysTick_clock_source
|
||||
* @{
|
||||
*/
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
|
||||
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
|
||||
#define IS_SYSTICK_CLKSOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
|
||||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported Macros -----------------------------------------------------------*/
|
||||
|
||||
/** @brief Configures the SysTick clock source.
|
||||
* @param __CLKSRC__: specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \
|
||||
do { \
|
||||
if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \
|
||||
{ \
|
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \
|
||||
} \
|
||||
else \
|
||||
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \
|
||||
} while(0)
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SystemReset(void);
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
|
||||
void HAL_SYSTICK_IRQHandler(void);
|
||||
void HAL_SYSTICK_Callback(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_CORTEX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,495 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_crc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief CRC HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the CRC peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(+) Enable CRC AHB clock using __CRC_CLK_ENABLE();
|
||||
(+) Initialize CRC calculator
|
||||
- specify generating polynomial (IP default or non-default one)
|
||||
- specify initialization value (IP default or non-default one)
|
||||
- specify input data format
|
||||
- specify input or output data inversion mode if any
|
||||
(+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
|
||||
input data buffer starting with the previously computed CRC as
|
||||
initialization value
|
||||
(+) Use HAL_CRC_Calculate() function to compute the CRC value of the
|
||||
input data buffer starting with the defined initialization value
|
||||
(default or non-default) to initiate CRC calculation
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC
|
||||
* @brief CRC HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
|
||||
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
|
||||
/** @defgroup CRC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_CRC_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization/de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the CRC according to the specified parameters
|
||||
in the CRC_InitTypeDef and create the associated handle
|
||||
(+) DeInitialize the CRC peripheral
|
||||
(+) Initialize the CRC MSP
|
||||
(+) DeInitialize CRC MSP
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the CRC according to the specified
|
||||
* parameters in the CRC_InitTypeDef and creates the associated handle.
|
||||
* @param hcrc: CRC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Check the CRC handle allocation */
|
||||
if(hcrc == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
||||
|
||||
if(hcrc->State == HAL_CRC_STATE_RESET)
|
||||
{
|
||||
/* Init the low level hardware */
|
||||
HAL_CRC_MspInit(hcrc);
|
||||
}
|
||||
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* check whether or not non-default generating polynomial has been
|
||||
* picked up by user */
|
||||
assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
|
||||
if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
|
||||
{
|
||||
/* initialize IP with default generating polynomial */
|
||||
WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* initialize CRC IP with generating polynomial defined by user */
|
||||
if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* check whether or not non-default CRC initial value has been
|
||||
* picked up by user */
|
||||
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
|
||||
if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
|
||||
{
|
||||
WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
|
||||
}
|
||||
|
||||
|
||||
/* set input data inversion mode */
|
||||
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
|
||||
|
||||
/* set output data inversion mode */
|
||||
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
|
||||
|
||||
/* makes sure the input data format (bytes, halfwords or words stream)
|
||||
* is properly specified by user */
|
||||
assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the CRC peripheral.
|
||||
* @param hcrc: CRC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Check the CRC handle allocation */
|
||||
if(hcrc == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
||||
|
||||
/* Check the CRC peripheral state */
|
||||
if(hcrc->State == HAL_CRC_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_CRC_MspDeInit(hcrc);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_RESET;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hcrc);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the CRC MSP.
|
||||
* @param hcrc: CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CRC_MspInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the CRC MSP.
|
||||
* @param hcrc: CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CRC_MspDeInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_CRC_Group2 Peripheral Control functions
|
||||
* @brief management functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
using combination of the previous CRC value and the new one.
|
||||
|
||||
or
|
||||
|
||||
(+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
independently of the previous CRC value.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
* starting with the previously computed CRC as initialization value.
|
||||
* @param hcrc: CRC handle
|
||||
* @param pBuffer: pointer to the input data buffer, exact input data format is
|
||||
* provided by hcrc->InputDataFormat.
|
||||
* @param BufferLength: input data buffer length
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index = 0; /* CRC input data buffer index */
|
||||
uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hcrc);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
switch (hcrc->InputDataFormat)
|
||||
{
|
||||
case CRC_INPUTDATA_FORMAT_WORDS:
|
||||
/* Enter Data to the CRC calculator */
|
||||
for(index = 0; index < BufferLength; index++)
|
||||
{
|
||||
hcrc->Instance->DR = pBuffer[index];
|
||||
}
|
||||
temp = hcrc->Instance->DR;
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_BYTES:
|
||||
temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_HALFWORDS:
|
||||
temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hcrc);
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return temp;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
* starting with hcrc->Instance->INIT as initialization value.
|
||||
* @param hcrc: CRC handle
|
||||
* @param pBuffer: pointer to the input data buffer, exact input data format is
|
||||
* provided by hcrc->InputDataFormat.
|
||||
* @param BufferLength: input data buffer length
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index = 0; /* CRC input data buffer index */
|
||||
uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hcrc);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* Reset CRC Calculation Unit (hcrc->Instance->INIT is
|
||||
* written in hcrc->Instance->DR) */
|
||||
__HAL_CRC_DR_RESET(hcrc);
|
||||
|
||||
switch (hcrc->InputDataFormat)
|
||||
{
|
||||
case CRC_INPUTDATA_FORMAT_WORDS:
|
||||
/* Enter 32-bit input data to the CRC calculator */
|
||||
for(index = 0; index < BufferLength; index++)
|
||||
{
|
||||
hcrc->Instance->DR = pBuffer[index];
|
||||
}
|
||||
temp = hcrc->Instance->DR;
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_BYTES:
|
||||
/* Specific 8-bit input data handling */
|
||||
temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_HALFWORDS:
|
||||
/* Specific 16-bit input data handling */
|
||||
temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hcrc);
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return temp;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enter 8-bit input data to the CRC calculator.
|
||||
* Specific data handling to optimize processing time.
|
||||
* @param hcrc: CRC handle
|
||||
* @param pBuffer: pointer to the input data buffer
|
||||
* @param BufferLength: input data buffer length
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t i = 0; /* input data buffer index */
|
||||
|
||||
/* Processing time optimization: 4 bytes are entered in a row with a single word write,
|
||||
* last bytes must be carefully fed to the CRC calculator to ensure a correct type
|
||||
* handling by the IP */
|
||||
for(i = 0; i < (BufferLength/4); i++)
|
||||
{
|
||||
hcrc->Instance->DR = (pBuffer[4*i]<<24) | (pBuffer[4*i+1]<<16) | (pBuffer[4*i+2]<<8) | pBuffer[4*i+3];
|
||||
}
|
||||
/* last bytes specific handling */
|
||||
if ((BufferLength%4) != 0)
|
||||
{
|
||||
if (BufferLength%4 == 1)
|
||||
{
|
||||
*(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i];
|
||||
}
|
||||
if (BufferLength%4 == 2)
|
||||
{
|
||||
*(uint16_t*) (&hcrc->Instance->DR) = (pBuffer[4*i]<<8) | pBuffer[4*i+1];
|
||||
}
|
||||
if (BufferLength%4 == 3)
|
||||
{
|
||||
*(uint16_t*) (&hcrc->Instance->DR) = (pBuffer[4*i]<<8) | pBuffer[4*i+1];
|
||||
*(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
|
||||
}
|
||||
}
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return hcrc->Instance->DR;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enter 16-bit input data to the CRC calculator.
|
||||
* Specific data handling to optimize processing time.
|
||||
* @param hcrc: CRC handle
|
||||
* @param pBuffer: pointer to the input data buffer
|
||||
* @param BufferLength: input data buffer length
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t i = 0; /* input data buffer index */
|
||||
|
||||
/* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
|
||||
* in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
|
||||
* a correct type handling by the IP */
|
||||
for(i = 0; i < (BufferLength/2); i++)
|
||||
{
|
||||
hcrc->Instance->DR = (pBuffer[2*i]<<16) | pBuffer[2*i+1];
|
||||
}
|
||||
if ((BufferLength%2) != 0)
|
||||
{
|
||||
*(uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i];
|
||||
}
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return hcrc->Instance->DR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_CRC_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the peripheral
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the CRC state.
|
||||
* @param hcrc: CRC handle
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
return hcrc->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,298 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of CRC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_CRC_H
|
||||
#define __STM32F3xx_HAL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief CRC HAL State Structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */
|
||||
HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */
|
||||
HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */
|
||||
HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */
|
||||
HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */
|
||||
}HAL_CRC_StateTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief CRC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
|
||||
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
|
||||
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
|
||||
In that case, there is no need to set GeneratingPolynomial field.
|
||||
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set */
|
||||
|
||||
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
|
||||
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
|
||||
0xFFFFFFFF value. In that case, there is no need to set InitValue field.
|
||||
If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set */
|
||||
|
||||
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree
|
||||
respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
|
||||
e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
|
||||
No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE */
|
||||
|
||||
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Size_Definitions and indicates CRC length.
|
||||
Value can be either one of
|
||||
CRC_POLYLENGTH_32B (32-bit CRC)
|
||||
CRC_POLYLENGTH_16B (16-bit CRC)
|
||||
CRC_POLYLENGTH_8B (8-bit CRC)
|
||||
CRC_POLYLENGTH_7B (7-bit CRC) */
|
||||
|
||||
uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
|
||||
is set to DEFAULT_INIT_VALUE_ENABLE */
|
||||
|
||||
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
|
||||
Can be either one of the following values
|
||||
CRC_INPUTDATA_INVERSION_NONE no input data inversion
|
||||
CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
|
||||
CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
|
||||
CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
|
||||
|
||||
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
|
||||
Can be either
|
||||
CRC_OUTPUTDATA_INVERSION_DISABLED no CRC inversion, or
|
||||
CRC_OUTPUTDATA_INVERSION_ENABLED CRC 0x11223344 is converted into 0x22CC4488 */
|
||||
}CRC_InitTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief CRC Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CRC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
CRC_InitTypeDef Init; /*!< CRC configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRC Locking object */
|
||||
|
||||
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
|
||||
|
||||
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
|
||||
Can be either
|
||||
CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
|
||||
CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
|
||||
CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bits data)
|
||||
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
|
||||
must occur if InputBufferFormat is not one of the three values listed above */
|
||||
}CRC_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_CRC32_POLY 0x04C11DB7
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFF
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)
|
||||
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01)
|
||||
|
||||
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
|
||||
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00)
|
||||
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01)
|
||||
|
||||
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
|
||||
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
|
||||
* @{
|
||||
*/
|
||||
#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000)
|
||||
#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
|
||||
#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
|
||||
#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)
|
||||
#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_16B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_8B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_7B))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRC_LENGTH_32B 32
|
||||
#define HAL_CRC_LENGTH_16B 16
|
||||
#define HAL_CRC_LENGTH_8B 8
|
||||
#define HAL_CRC_LENGTH_7B 7
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
|
||||
* @{
|
||||
*/
|
||||
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
|
||||
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
|
||||
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
|
||||
* the CRC APIs to provide a correct result */
|
||||
#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000)
|
||||
#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001)
|
||||
#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002)
|
||||
#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003)
|
||||
|
||||
#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
|
||||
((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
|
||||
((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CRC handle state
|
||||
* @param __HANDLE__: CRC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Reset CRC Data Register.
|
||||
* @param __HANDLE__: CRC handle
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
|
||||
|
||||
/**
|
||||
* @brief Set CRC INIT non-default value
|
||||
* @param __HANDLE__ : CRC handle
|
||||
* @param __INIT__ : 32-bit initial value
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Include CRC HAL Extension module */
|
||||
#include "stm32f3xx_hal_crc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
|
||||
/* Aliases for inter STM32 series compatibility */
|
||||
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
|
||||
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_CRC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,144 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_crc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of CRC HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_CRC_EX_H
|
||||
#define __STM32F3xx_HAL_CRC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
|
||||
* @{
|
||||
*/
|
||||
#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000)
|
||||
#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
|
||||
#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
|
||||
#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
|
||||
|
||||
#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_WORD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
|
||||
* @{
|
||||
*/
|
||||
#define CRC_OUTPUTDATA_INVERSION_DISABLED ((uint32_t)0x00000000)
|
||||
#define CRC_OUTPUTDATA_INVERSION_ENABLED ((uint32_t)CRC_CR_REV_OUT)
|
||||
|
||||
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLED) || \
|
||||
((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRCEx_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set CRC output reversal
|
||||
* @param __HANDLE__ : CRC handle
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
|
||||
|
||||
/**
|
||||
* @brief Unset CRC output reversal
|
||||
* @param __HANDLE__ : CRC handle
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
|
||||
|
||||
/**
|
||||
* @brief Set CRC non-default polynomial
|
||||
* @param __HANDLE__ : CRC handle
|
||||
* @param __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
|
||||
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
|
||||
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_CRC_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,707 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dac.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Digital-to-Analog Converter (DAC) peripheral:
|
||||
* + DAC channels configuration: trigger, output buffer, data format
|
||||
* + DMA management
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### DAC Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
*** DAC Channels ***
|
||||
====================
|
||||
[..]
|
||||
The device integrates up to 3 12-bit Digital Analog Converters that can
|
||||
be used independently or simultaneously (dual mode):
|
||||
(#) DAC1 channel1 with DAC1_OUT1 (PA4) as output
|
||||
(#) DAC1 channel2 with DAC1_OUT2 (PA5) as output
|
||||
(for STM32F3 devices having 2 channels on DAC1)
|
||||
(#) DAC2 channel1 with DAC2_OUT1 (PA6) as output
|
||||
(for STM32F3 devices having 2 DAC)
|
||||
|
||||
*** DAC Triggers ***
|
||||
====================
|
||||
[..]
|
||||
Digital to Analog conversion can be non-triggered using DAC_Trigger_None
|
||||
and DAC1_OUT1/DAC1_OUT2/DAC2_OUT1 is available once writing to DHRx register.
|
||||
[..]
|
||||
Digital to Analog conversion can be triggered by:
|
||||
(#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
|
||||
The used pin (GPIOx_Pin9) must be configured in input mode.
|
||||
|
||||
(#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
|
||||
(DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
|
||||
|
||||
(#) Software using DAC_Trigger_Software
|
||||
|
||||
*** DAC Buffer mode feature ***
|
||||
===============================
|
||||
[..]
|
||||
Each DAC channel integrates an output buffer that can be used to
|
||||
reduce the output impedance, and to drive external loads directly
|
||||
without having to add an external operational amplifier.
|
||||
To enable, the output buffer use
|
||||
sConfig.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
||||
[..]
|
||||
(@) Refer to the device datasheet for more details about output
|
||||
impedance value with and without output buffer.
|
||||
|
||||
*** DAC wave generation feature ***
|
||||
===================================
|
||||
[..]
|
||||
Both DAC channels of DAC1 can be used to generate
|
||||
note that wave generation is not available in DAC2.
|
||||
(#) Noise wave
|
||||
(#) Triangle wave
|
||||
|
||||
Wave generation is NOT available in DAC2.
|
||||
|
||||
*** DAC data format ***
|
||||
=======================
|
||||
[..]
|
||||
The DAC data format can be:
|
||||
(#) 8-bit right alignment using DAC_ALIGN_8B_R
|
||||
(#) 12-bit left alignment using DAC_ALIGN_12B_L
|
||||
(#) 12-bit right alignment using DAC_ALIGN_12B_R
|
||||
|
||||
*** DAC data value to voltage correspondence ***
|
||||
================================================
|
||||
[..]
|
||||
The analog output voltage on each DAC channel pin is determined
|
||||
by the following equation:
|
||||
DAC_OUTx = VREF+ * DOR / 4095
|
||||
with DOR is the Data Output Register
|
||||
VEF+ is the input voltage reference (refer to the device datasheet)
|
||||
e.g. To set DAC_OUT1 to 0.7V, use
|
||||
Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
|
||||
|
||||
*** DMA requests ***
|
||||
=====================
|
||||
[..]
|
||||
A DMA1 or DMA2 request can be generated when an external trigger
|
||||
(but not a software trigger) occurs if DMA1 or DMA2 requests are
|
||||
enabled using HAL_DAC_Start_DMA()
|
||||
[..]
|
||||
DMA1 requests are mapped as following:
|
||||
(#) DAC1 channel1: mapped either on
|
||||
- DMA1 channel3
|
||||
- or DMA2 channel3 (for STM32F3 devices having 2 DMA)
|
||||
which must be already configured
|
||||
(#) DAC1 channel2:
|
||||
(for STM32F3 devices having 2 channels on DAC1)
|
||||
mapped either on
|
||||
- DMA1 channel4
|
||||
- or DMA2 channel4 (for STM32F3 devices having 2 DMA)
|
||||
which must be already configured
|
||||
|
||||
(#) DAC2 channel1: mapped either on
|
||||
(for STM32F3 devices having 2 DAC)
|
||||
- DMA1 channel4
|
||||
- or DMA2 channel4 (for STM32F3 devices having 2 DMA)
|
||||
which must be already configured
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) DAC APB clock must be enabled to get write access to DAC
|
||||
registers using HAL_DAC_Init()
|
||||
(+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
|
||||
(+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
|
||||
(+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA
|
||||
functions
|
||||
|
||||
*** Polling mode IO operation ***
|
||||
=================================
|
||||
[..]
|
||||
(+) Start the DAC peripheral using HAL_DAC_Start()
|
||||
(+) To read the DAC last data output value value, use the HAL_DAC_GetValue() function.
|
||||
(+) Stop the DAC peripheral using HAL_DAC_Stop()
|
||||
|
||||
*** DMA mode IO operation ***
|
||||
==============================
|
||||
[..]
|
||||
(+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
|
||||
of data to be transfered at each end of conversion
|
||||
(+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
|
||||
function is executed and user can add his own code by customization of function pointer
|
||||
HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
|
||||
(+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
|
||||
add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
|
||||
(+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
|
||||
|
||||
*** Dual mode operation ***
|
||||
==============================
|
||||
[..]
|
||||
(+) When Dual mode is enabled
|
||||
(i.e DAC1 Channel1 and DAC1 Channel2 are used simultaneously)
|
||||
(for STM32F3 devices having 2 channels on DAC1).
|
||||
Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
|
||||
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously
|
||||
in Channel 1 and Channel 2.
|
||||
|
||||
*** Wave generation operation ***
|
||||
==============================
|
||||
[..]
|
||||
(+) Use HAL_DACEx_TriangleWaveGenerate to generate Triangle signal.
|
||||
(+) Use HAL_DACEx_NoiseWaveGenerate to generate Noise signal.
|
||||
|
||||
Wave generation is NOT available in DAC2.
|
||||
|
||||
*** DAC HAL driver macros list ***
|
||||
=============================================
|
||||
[..]
|
||||
Below the list of most used macros in DAC HAL driver.
|
||||
|
||||
(+) __HAL_DAC_ENABLE : Enable the DAC peripheral
|
||||
(+) __HAL_DAC_DISABLE : Disable the DAC peripheral
|
||||
(+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
|
||||
(+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
|
||||
|
||||
[..]
|
||||
(@) You can refer to the DAC HAL driver header file for more useful macros
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC
|
||||
* @brief DAC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize and configure the DAC.
|
||||
(+) De-initialize the DAC.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the DAC peripheral according to the specified parameters
|
||||
* in the DAC_InitStruct.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Check DAC handle */
|
||||
if(hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
|
||||
|
||||
if(hdac->State == HAL_DAC_STATE_RESET)
|
||||
{
|
||||
/* Init the low level hardware */
|
||||
HAL_DAC_MspInit(hdac);
|
||||
}
|
||||
|
||||
/* Initialize the DAC state*/
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Set DAC error code to none */
|
||||
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
|
||||
|
||||
/* Initialize the DAC state*/
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DAC peripheral registers to their default reset values.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Check DAC handle */
|
||||
if(hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_DAC_MspDeInit(hdac);
|
||||
|
||||
/* Set DAC error code to none */
|
||||
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DAC MSP.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the DAC MSP.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### IO operation functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Start conversion.
|
||||
(+) Stop conversion.
|
||||
(+) Start conversion and enable DMA transfer.
|
||||
(+) Stop conversion and disable DMA transfer.
|
||||
(+) Get result of conversion.
|
||||
(+) Get result of dual mode conversion.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables DAC and starts conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC1_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC1_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @arg DAC2_CHANNEL_1: DAC2 Channel1 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t channel)
|
||||
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference */
|
||||
/* Function content is located into file stm32f3xx_hal_dac_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables DAC and stop conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC1_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC1_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @arg DAC2_CHANNEL_1: DAC2 Channel1 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t channel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, channel));
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_DAC_DISABLE(hdac, channel);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables DAC and stop conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC1_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC1_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @arg DAC2_CHANNEL_1: DAC2 Channel1 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t channel)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, channel));
|
||||
|
||||
/* Disable the selected DAC channel DMA request */
|
||||
hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << channel);
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_DAC_DISABLE(hdac, channel);
|
||||
|
||||
/* Disable the DMA Channel */
|
||||
/* Channel1 is used */
|
||||
if (channel == DAC1_CHANNEL_1)
|
||||
{
|
||||
status = HAL_DMA_Abort(hdac->DMA_Handle1);
|
||||
}
|
||||
else /* Channel2 is used for */
|
||||
{
|
||||
status = HAL_DMA_Abort(hdac->DMA_Handle2);
|
||||
}
|
||||
|
||||
/* Check if DMA Channel effectively disabled */
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
hdac->State = HAL_DAC_STATE_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC1_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC1_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @arg DAC2_CHANNEL_1: DAC2 Channel1 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
__weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t channel)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference */
|
||||
/* Function content is located into file stm32f3xx_hal_dac_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
__weak uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference */
|
||||
/* Function content is located into file stm32f3xx_hal_dac_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group3 Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure channels.
|
||||
(+) Configure Triangle wave generation.
|
||||
(+) Configure Noise wave generation.
|
||||
(+) Set the specified data holding register value for DAC channel.
|
||||
(+) Set the specified data holding register value for Dual DAC channels.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param sConfig: DAC configuration structure.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC1_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC1_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @arg DAC2_CHANNEL_1: DAC2 Channel1 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t channel)
|
||||
{
|
||||
uint32_t tmpreg1 = 0, tmpreg2 = 0;
|
||||
|
||||
/* Check the DAC parameters */
|
||||
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
|
||||
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
|
||||
assert_param(IS_DAC_CHANNEL(channel));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Get the DAC CR value */
|
||||
tmpreg1 = hdac->Instance->CR;
|
||||
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
|
||||
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << channel);
|
||||
/* Configure for the selected DAC channel: buffer output, trigger */
|
||||
/* Set TSELx and TENx bits according to DAC_Trigger value */
|
||||
/* Set BOFFx bit according to DAC_OutputBuffer value */
|
||||
tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
|
||||
/* Calculate CR register value depending on DAC_Channel */
|
||||
tmpreg1 |= tmpreg2 << channel;
|
||||
/* Write to DAC CR */
|
||||
hdac->Instance->CR = tmpreg1;
|
||||
/* Disable wave generation */
|
||||
hdac->Instance->CR &= ~(DAC_CR_WAVE1 << channel);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
__weak HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t alignment, uint32_t data)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference */
|
||||
/* Function content is located into file stm32f3xx_hal_dac_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
__weak HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t alignment, uint32_t data1, uint32_t data2)
|
||||
{
|
||||
/* Note : This function is defined into this file for library reference */
|
||||
/* Function content is located into file stm32f3xx_hal_dac_ex.c */
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group4 DAC Peripheral State functions
|
||||
* @brief DAC Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### DAC Peripheral State functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides functions allowing to
|
||||
(+) Check the DAC state.
|
||||
(+) Check the DAC Errors.
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief return the DAC state
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Return DAC state */
|
||||
return hdac->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the DAC error code
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval DAC Error Code
|
||||
*/
|
||||
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
return hdac->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Conversion complete callback in non blocking mode for Channel1
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ConvCpltCallback1 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Conversion half DMA transfer callback in non blocking mode for Channel1
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Error DAC callback for Channel1.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA underrun DAC callback for Channel1.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,342 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of DAC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_DAC_H
|
||||
#define __STM32F3xx_HAL_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
|
||||
HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */
|
||||
HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
|
||||
HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
|
||||
HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
|
||||
|
||||
}HAL_DAC_StateTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief DAC Configuration regular Channel structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DACEx_trigger_selection */
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
|
||||
}DAC_ChannelConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC handle Structure definition
|
||||
*/
|
||||
typedef struct __DAC_HandleTypeDef
|
||||
{
|
||||
DAC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DAC locking object */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DAC Error code */
|
||||
|
||||
}DAC_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Error_Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */
|
||||
#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
#define DAC_WAVEGENERATION_NONE ((uint32_t)0x00000000)
|
||||
#define DAC_WAVEGENERATION_NOISE ((uint32_t)DAC_CR_WAVE1_0)
|
||||
#define DAC_WAVEGENERATION_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
|
||||
|
||||
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NONE) || \
|
||||
((WAVE) == DAC_WAVEGENERATION_NOISE) || \
|
||||
((WAVE) == DAC_WAVEGENERATION_TRIANGLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_lfsrunmask_triangleamplitude
|
||||
* @{
|
||||
*/
|
||||
#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer
|
||||
* @{
|
||||
*/
|
||||
#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
|
||||
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
|
||||
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
|
||||
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignement
|
||||
* @{
|
||||
*/
|
||||
#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
|
||||
#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
|
||||
#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
|
||||
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
|
||||
((ALIGN) == DAC_ALIGN_12B_L) || \
|
||||
((ALIGN) == DAC_ALIGN_8B_R))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
|
||||
#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
|
||||
|
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || \
|
||||
((WAVE) == DAC_WAVE_TRIANGLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
|
||||
#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
|
||||
|
||||
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR1) || \
|
||||
((FLAG) == DAC_FLAG_DMAUDR2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_IT_DMAUDR1 ((uint32_t)DAC_CR_DMAUDRIE1)
|
||||
#define DAC_IT_DMAUDR2 ((uint32_t)DAC_CR_DMAUDRIE2)
|
||||
|
||||
|
||||
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR1) || \
|
||||
((IT) == DAC_IT_DMAUDR2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset DAC handle state
|
||||
* @param __HANDLE__: DAC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
|
||||
|
||||
/* Enable the DAC peripheral */
|
||||
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
|
||||
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
|
||||
|
||||
/* Disable the DAC peripheral */
|
||||
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
|
||||
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
|
||||
|
||||
/* Set DHR12R1 alignment */
|
||||
#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__))
|
||||
|
||||
/* Set DHR12R2 alignment */
|
||||
#define __HAL_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__))
|
||||
|
||||
/* Set DHR12RD alignment */
|
||||
#define __HAL_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__))
|
||||
|
||||
/* Enable the DAC interrupt */
|
||||
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
||||
|
||||
/* Disable the DAC interrupt */
|
||||
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||
|
||||
/* Get the selected DAC's flag status */
|
||||
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/* Clear the DAC's flag */
|
||||
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
|
||||
|
||||
/* Include DAC HAL Extension module */
|
||||
#include "stm32f3xx_hal_dac_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t* pData, uint32_t Length, uint32_t alignment);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t channel);
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t channel);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t channel);
|
||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t alignment, uint32_t data);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
|
||||
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
|
||||
|
||||
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F3xx_HAL_DAC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,987 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dac_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Extended DAC HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (DAC) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
@verbatim
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @brief DAC HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
|
||||
static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
|
||||
#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
/* DAC channel 2 is available on top of DAC channel 1 */
|
||||
static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
|
||||
static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
#endif /* STM32F303xC STM32F358xx STM32F303x8 STM32F328xx STM32F302xC STM32F334x8 STM32F373xC STM32F378xx */
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DAC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group3 Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Set the specified data holding register value for DAC channel.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* @param alignment: Specifies the data alignment for DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
|
||||
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
|
||||
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
|
||||
* @param data: Data to be loaded in the selected data holding register.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t alignment, uint32_t data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(channel));
|
||||
assert_param(IS_DAC_ALIGN(alignment));
|
||||
assert_param(IS_DAC_DATA(data));
|
||||
|
||||
tmp = (uint32_t) (hdac->Instance);
|
||||
|
||||
/* DAC 1 has 1 or 2 channels - no DAC2 */
|
||||
#if defined(STM32F302xC) || defined(STM32F302x8) || defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F328xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */
|
||||
|
||||
if(channel == DAC_CHANNEL_1)
|
||||
{
|
||||
tmp += __HAL_DHR12R1_ALIGNEMENT(alignment);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
else /* channel = DAC_CHANNEL_2 */
|
||||
{
|
||||
tmp += __HAL_DHR12R2_ALIGNEMENT(alignment);
|
||||
}
|
||||
|
||||
/* Set the DAC channel1 selected data holding register */
|
||||
*(__IO uint32_t *) tmp = data;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### IO operation functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Start conversion.
|
||||
(+) Stop conversion.
|
||||
(+) Start conversion and enable DMA transfer.
|
||||
(+) Stop conversion and disable DMA transfer.
|
||||
(+) Get result of conversion.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */
|
||||
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx) || \
|
||||
defined(STM32F303xC) || defined(STM32F358xx)
|
||||
/* DAC 1 has 2 channels 1 & 2 */
|
||||
|
||||
/**
|
||||
* @brief Enables DAC and starts conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC1 Channel1 or DAC2 Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables DAC and starts conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t channel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, channel));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Enable the Peripharal */
|
||||
__HAL_DAC_ENABLE(hdac, channel);
|
||||
|
||||
if(channel == DAC_CHANNEL_1)
|
||||
{
|
||||
/* Check if software trigger enabled */
|
||||
if(((hdac->Instance->CR & DAC_CR_TEN1) == DAC_CR_TEN1) && ((hdac->Instance->CR & DAC_CR_TSEL1) == DAC_CR_TSEL1))
|
||||
{
|
||||
/* Enable the selected DAC software conversion */
|
||||
hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check if software trigger enabled */
|
||||
if(((hdac->Instance->CR & DAC_CR_TEN2) == DAC_CR_TEN2) && ((hdac->Instance->CR & DAC_CR_TSEL2) == DAC_CR_TSEL2))
|
||||
{
|
||||
/* Enable the selected DAC software conversion*/
|
||||
hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;
|
||||
}
|
||||
}
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F302x8) || defined(STM32F301x8) || defined(STM32F318xx)
|
||||
/* DAC 1 has 1 channels 1 */
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t channel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, channel));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Enable the Peripharal */
|
||||
__HAL_DAC_ENABLE(hdac, channel);
|
||||
|
||||
/* Check if software trigger enabled */
|
||||
if(((hdac->Instance->CR & DAC_CR_TEN1) == DAC_CR_TEN1) && ((hdac->Instance->CR & DAC_CR_TSEL1) == DAC_CR_TSEL1))
|
||||
{
|
||||
/* Enable the selected DAC software conversion */
|
||||
hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
|
||||
}
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */
|
||||
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx) || defined(STM32F328xx) || \
|
||||
defined(STM32F303xC) || defined(STM32F358xx)
|
||||
/* DAC 1 has 2 channels 1 & 2 */
|
||||
|
||||
/**
|
||||
* @brief Enables DAC and starts conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @param pData: The destination peripheral Buffer address.
|
||||
* @param Length: The length of data to be transferred from memory to DAC peripheral
|
||||
* @param alignment: Specifies the data alignment for DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t* pData, uint32_t Length, uint32_t alignment)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, channel));
|
||||
assert_param(IS_DAC_ALIGN(alignment));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
if(channel == DAC_CHANNEL_1)
|
||||
{
|
||||
/* Set the DMA transfer complete callback for channel1 */
|
||||
hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
|
||||
|
||||
/* Set the DMA half transfer complete callback for channel1 */
|
||||
hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
|
||||
|
||||
/* Set the DMA error callback for channel1 */
|
||||
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the DMA transfer complete callback for channel2 */
|
||||
hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
|
||||
|
||||
/* Set the DMA half transfer complete callback for channel2 */
|
||||
hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
|
||||
|
||||
/* Set the DMA error callback for channel2 */
|
||||
hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
|
||||
}
|
||||
|
||||
if(channel == DAC_CHANNEL_1)
|
||||
{
|
||||
/* Enable the selected DAC channel1 DMA request */
|
||||
hdac->Instance->CR |= DAC_CR_DMAEN1;
|
||||
|
||||
/* Case of use of channel 1 */
|
||||
switch(alignment)
|
||||
{
|
||||
case DAC_ALIGN_12B_R:
|
||||
/* Get DHR12R1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
|
||||
break;
|
||||
case DAC_ALIGN_12B_L:
|
||||
/* Get DHR12L1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
|
||||
break;
|
||||
case DAC_ALIGN_8B_R:
|
||||
/* Get DHR8R1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enable the selected DAC channel2 DMA request */
|
||||
hdac->Instance->CR |= DAC_CR_DMAEN2;
|
||||
|
||||
/* Case of use of channel 2 */
|
||||
switch(alignment)
|
||||
{
|
||||
case DAC_ALIGN_12B_R:
|
||||
/* Get DHR12R2 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
|
||||
break;
|
||||
case DAC_ALIGN_12B_L:
|
||||
/* Get DHR12L2 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
|
||||
break;
|
||||
case DAC_ALIGN_8B_R:
|
||||
/* Get DHR8R2 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable the DMA Channel */
|
||||
if(channel == DAC_CHANNEL_1)
|
||||
{
|
||||
/* Enable the DAC DMA underrun interrupt */
|
||||
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
|
||||
|
||||
/* Enable the DMA Channel */
|
||||
HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enable the DAC DMA underrun interrupt */
|
||||
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
|
||||
|
||||
/* Enable the DMA Channel */
|
||||
HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
|
||||
}
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_DAC_ENABLE(hdac, channel);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F302x8) || defined(STM32F301x8) || defined(STM32F318xx)
|
||||
/* DAC 1 has 1 channels 1 */
|
||||
|
||||
/**
|
||||
* @brief Enables DAC and starts conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @param pData: The destination peripheral Buffer address.
|
||||
* @param Length: The length of data to be transferred from memory to DAC peripheral
|
||||
* @param alignment: Specifies the data alignment for DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t* pData, uint32_t Length, uint32_t alignment)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, channel));
|
||||
assert_param(IS_DAC_ALIGN(alignment));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Set the DMA transfer complete callback for channel1 */
|
||||
hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
|
||||
|
||||
/* Set the DMA half transfer complete callback for channel1 */
|
||||
hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
|
||||
|
||||
/* Set the DMA error callback for channel1 */
|
||||
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
|
||||
|
||||
/* Enable the selected DAC channel1 DMA request */
|
||||
hdac->Instance->CR |= DAC_CR_DMAEN1;
|
||||
|
||||
/* Case of use of channel 1 */
|
||||
switch(alignment)
|
||||
{
|
||||
case DAC_ALIGN_12B_R:
|
||||
/* Get DHR12R1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
|
||||
break;
|
||||
case DAC_ALIGN_12B_L:
|
||||
/* Get DHR12L1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
|
||||
break;
|
||||
case DAC_ALIGN_8B_R:
|
||||
/* Get DHR8R1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enable the DMA Channel */
|
||||
/* Enable the DAC DMA underrun interrupt */
|
||||
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
|
||||
|
||||
/* Enable the DMA Channel */
|
||||
HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_DAC_ENABLE(hdac, channel);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */
|
||||
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx) || \
|
||||
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
/* DAC 1 has 2 channels 1 & 2 */
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC1 Channel1 or DAC2 Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t channel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, channel));
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
if(channel == DAC_CHANNEL_1)
|
||||
{
|
||||
return hdac->Instance->DOR1;
|
||||
}
|
||||
else /* channel = DAC_CHANNEL_2 */
|
||||
{
|
||||
return hdac->Instance->DOR2;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(STM32F302x8) || defined(STM32F301x8) || defined(STM32F318xx)
|
||||
/* DAC 1 has 1 channel (channel 1) */
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t channel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, channel));
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
return hdac->Instance->DOR1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
|
||||
/* DAC channel 2 is NOT available. Only DAC channel 1 is available */
|
||||
|
||||
/**
|
||||
* @brief Handles DAC interrupt request
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Check Overrun flag */
|
||||
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
|
||||
{
|
||||
/* Change DAC state to error state */
|
||||
hdac->State = HAL_DAC_STATE_ERROR;
|
||||
|
||||
/* Set DAC error code to chanel1 DMA underrun error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
|
||||
|
||||
/* Clear the underrun flag */
|
||||
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
|
||||
|
||||
/* Disable the selected DAC channel1 DMA request */
|
||||
hdac->Instance->CR &= ~DAC_CR_DMAEN1;
|
||||
|
||||
/* Error callback */
|
||||
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
|
||||
}
|
||||
}
|
||||
#endif /* STM32F301x8 STM32F302x8 STM32F318xx */
|
||||
|
||||
#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303x8) || defined(STM32F328xx)|| defined(STM32F302xC) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
/* DAC channel 2 is available on top of DAC channel 1 */
|
||||
|
||||
/**
|
||||
* @brief Handles DAC interrupt request
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Check Overrun flag */
|
||||
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
|
||||
{
|
||||
/* Change DAC state to error state */
|
||||
hdac->State = HAL_DAC_STATE_ERROR;
|
||||
|
||||
/* Set DAC error code to chanel1 DMA underrun error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
|
||||
|
||||
/* Clear the underrun flag */
|
||||
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
|
||||
|
||||
/* Disable the selected DAC channel1 DMA request */
|
||||
hdac->Instance->CR &= ~DAC_CR_DMAEN1;
|
||||
|
||||
/* Error callback */
|
||||
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
|
||||
{
|
||||
/* Change DAC state to error state */
|
||||
hdac->State = HAL_DAC_STATE_ERROR;
|
||||
|
||||
/* Set DAC error code to channel2 DMA underrun error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
|
||||
|
||||
/* Clear the underrun flag */
|
||||
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
|
||||
|
||||
/* Disable the selected DAC channel1 DMA request */
|
||||
hdac->Instance->CR &= ~DAC_CR_DMAEN2;
|
||||
|
||||
/* Error callback */
|
||||
HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* STM32F303xC STM32F358xx STM32F303x8 STM32F328xx STM32F302xC STM32F334x8 STM32F373xC STM32F378xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx
|
||||
* @brief DACEx Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
/* DAC channel 2 is present in DAC 1 */
|
||||
/**
|
||||
* @brief Set the specified data holding register value for dual DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param alignment: Specifies the data alignment for dual channel DAC.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param data2: Data for DAC Channel2 to be loaded in the selected data holding register.
|
||||
* @param data1: Data for DAC Channel1 to be loaded in the selected data holding register.
|
||||
* @note In dual mode, a unique register access is required to write in both
|
||||
* DAC channels at the same time.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t alignment, uint32_t data1, uint32_t data2)
|
||||
{
|
||||
uint32_t data = 0, tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(alignment));
|
||||
assert_param(IS_DAC_DATA(data1));
|
||||
assert_param(IS_DAC_DATA(data2));
|
||||
|
||||
/* Calculate and set dual DAC data holding register value */
|
||||
if (alignment == DAC_ALIGN_8B_R)
|
||||
{
|
||||
data = ((uint32_t)data2 << 8) | data1;
|
||||
}
|
||||
else
|
||||
{
|
||||
data = ((uint32_t)data2 << 16) | data1;
|
||||
}
|
||||
|
||||
tmp = (uint32_t) (hdac->Instance);
|
||||
tmp += __HAL_DHR12RD_ALIGNEMENT(alignment);
|
||||
|
||||
/* Set the dual DAC selected data holding register */
|
||||
*(__IO uint32_t *)tmp = data;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
tmp |= hdac->Instance->DOR1;
|
||||
|
||||
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
/* DAC channel 2 is present in DAC 1 */
|
||||
tmp |= hdac->Instance->DOR2 << 16;
|
||||
#endif
|
||||
/* Returns the DAC channel data output register value */
|
||||
return tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel wave generation.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @param Amplitude: Select max triangle amplitude.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
|
||||
* @note Wave generation is not available in DAC2.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t Amplitude)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(channel));
|
||||
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Enable the selected wave generation for the selected DAC channel */
|
||||
hdac->Instance->CR |= (DAC_WAVE_TRIANGLE | Amplitude) << channel;
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel wave generation.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
|
||||
* @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t Amplitude)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(channel));
|
||||
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Enable the selected wave generation for the selected DAC channel */
|
||||
hdac->Instance->CR |= (DAC_WAVE_NOISE | Amplitude) << channel;
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Conversion complete callback in non blocking mode for Channel2
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Conversion half DMA transfer callback in non blocking mode for Channel2
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Error DAC callback for Channel2.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA underrun DAC callback for channel2.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA conversion complete callback.
|
||||
* @param hdma: pointer to DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
HAL_DAC_ConvCpltCallbackCh1(hdac);
|
||||
|
||||
hdac->State= HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA half transfer complete callback.
|
||||
* @param hdma: pointer to DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
/* Conversion complete callback */
|
||||
HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA error callback
|
||||
* @param hdma: pointer to DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
/* Set DAC error code to DMA error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
|
||||
|
||||
HAL_DAC_ErrorCallbackCh1(hdac);
|
||||
|
||||
hdac->State= HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
/* DAC channel 2 is available on top of DAC channel 1 */
|
||||
|
||||
/**
|
||||
* @brief DMA conversion complete callback.
|
||||
* @param hdma: pointer to DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
HAL_DACEx_ConvCpltCallbackCh2(hdac);
|
||||
|
||||
hdac->State= HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA half transfer complete callback.
|
||||
* @param hdma: pointer to DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
/* Conversion complete callback */
|
||||
HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA error callback
|
||||
* @param hdma: pointer to DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
/* Set DAC error code to DMA error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
|
||||
|
||||
HAL_DACEx_ErrorCallbackCh2(hdac);
|
||||
|
||||
hdac->State= HAL_DAC_STATE_READY;
|
||||
}
|
||||
#endif /* STM32F303xC STM32F358xx STM32F303x8 STM32F328xx STM32F334x8 STM32F373xC STM32F378xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,313 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dac_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of DAC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_DAC_EX_H
|
||||
#define __STM32F3xx_HAL_DAC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DACEx_trigger_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F318xx)
|
||||
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
#endif /* STM32F301x8 STM32F318xx */
|
||||
|
||||
#if defined(STM32F302x8)
|
||||
|
||||
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
|
||||
#endif /* STM32F302x8 */
|
||||
|
||||
#if defined(STM32F302xC)
|
||||
|
||||
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
|
||||
#endif /* STM32F302xC */
|
||||
|
||||
|
||||
#if defined (STM32F303xC) || defined (STM32F358xx)
|
||||
|
||||
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
|
||||
Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 selection */
|
||||
#define DAC_TRIGGER_T8_TRGO DAC_TRIGGER_T3_TRGO /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
|
||||
Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM8 selection */
|
||||
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
#endif /* STM32F303xC || STM32F358xx */
|
||||
|
||||
|
||||
#if defined (STM32F303x8) || defined (STM32F328xx)
|
||||
|
||||
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
|
||||
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
|
||||
#endif /* STM32F303x8 || STM32F328xx */
|
||||
|
||||
|
||||
#if defined (STM32F373xC) || defined (STM32F378xx)
|
||||
|
||||
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel (DAC1) */
|
||||
#define DAC_TRIGGER_T18_TRGO DAC_TRIGGER_T5_TRGO /*!< TIM18 TRGO selected as external conversion trigger for DAC channel (DAC2) */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
|
||||
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F334x8)
|
||||
|
||||
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
|
||||
Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 remap */
|
||||
|
||||
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
|
||||
Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for TIM15 selection */
|
||||
#define DAC_TRIGGER_HRTIM1_DACTRG1 DAC_TRIGGER_T15_TRGO /*!< HRTIM1 DACTRG1 selected as external conversion trigger for DAC
|
||||
Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for HRTIM1 DACTRG1 selection */
|
||||
|
||||
#define DAC_TRIGGER_HRTIM1_DACTRG2 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< HRTIM1 DACTRG2 selected as external conversion trigger for DAC channel (DAC1)
|
||||
Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG5) for HRTIM1 DACTRG2 remap */
|
||||
#define DAC_TRIGGER_HRTIM1_DACTRG3 DAC_TRIGGER_HRTIM1_DACTRG2 /*!< HRTIM1 DACTRG3 selected as external conversion trigger for DAC channel (DAC2)*/
|
||||
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_HRTIM1_DACTRG2) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
|
||||
#endif /* STM32F334x8 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_Channel_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
|
||||
#define DAC_CHANNEL_1 ((uint32_t)0x00000000) /*!< DAC Channel 1 */
|
||||
/* Aliases for compatibility */
|
||||
#define DAC1_CHANNEL_1 DAC_CHANNEL_1 /*!< DAC1 Channel 1 */
|
||||
|
||||
#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
|
||||
|
||||
|
||||
#if defined (STM32F303xC) || defined (STM32F358xx) || defined(STM32F302xC)
|
||||
#define DAC_CHANNEL_1 ((uint32_t)0x00000000) /*!< DAC Channel 1 */
|
||||
#define DAC_CHANNEL_2 ((uint32_t)0x00000010) /*!< DAC Channel 2 */
|
||||
/* Aliases for compatibility */
|
||||
#define DAC1_CHANNEL_1 DAC_CHANNEL_1 /*!< DAC1 Channel 1 */
|
||||
#define DAC1_CHANNEL_2 DAC_CHANNEL_2 /*!< DAC1 Channel 2 */
|
||||
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2))
|
||||
#endif /* STM32F303xC STM32F358xx STM32F302xC */
|
||||
|
||||
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F373xC)|| defined (STM32F378xx) || defined (STM32F328xx)
|
||||
|
||||
#define DAC_CHANNEL_1 ((uint32_t)0x00000000) /*!< DAC Channel 1 */
|
||||
#define DAC_CHANNEL_2 ((uint32_t)0x00000010) /*!< DAC Channel 2 */
|
||||
|
||||
/* Aliases for compatibility */
|
||||
#define DAC1_CHANNEL_1 DAC_CHANNEL_1 /*!< DAC1 Channel 1 */
|
||||
#define DAC1_CHANNEL_2 DAC_CHANNEL_2 /*!< DAC1 Channel 2 */
|
||||
#define DAC2_CHANNEL_1 DAC_CHANNEL_1 /*!< DAC2 Channel 1 */
|
||||
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Extension features functions ***********************************************/
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t alignment, uint32_t data1, uint32_t data2);
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t Amplitude);
|
||||
|
||||
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_HAL_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,165 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_DEF
|
||||
#define __STM32F3xx_HAL_DEF
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_OK = 0x00,
|
||||
HAL_ERROR = 0x01,
|
||||
HAL_BUSY = 0x02,
|
||||
HAL_TIMEOUT = 0x03
|
||||
} HAL_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_UNLOCKED = 0x00,
|
||||
HAL_LOCKED = 0x01
|
||||
} HAL_LockTypeDef;
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifndef NULL
|
||||
#define NULL (void *) 0
|
||||
#endif
|
||||
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFF
|
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
|
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
|
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \
|
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
|
||||
(__DMA_HANDLE_).Parent = (__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__: specifies the Peripheral Handle.
|
||||
* @note This macro can be used for the following purpose:
|
||||
* - When the Handle is declared as local variable; before passing it as parameter
|
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||
* to set to 0 the Handle's "State" field.
|
||||
* Otherwise, "State" field may have any random value and the first time the function
|
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
|
||||
* (i.e. HAL_PPP_MspInit() will not be executed).
|
||||
* - When there is a need to reconfigure the low level hardware: instead of calling
|
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
|
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
|
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
|
||||
|
||||
#if (USE_RTOS == 1)
|
||||
#error " USE_RTOS should be 0 in the current HAL release "
|
||||
#else
|
||||
#define __HAL_LOCK(__HANDLE__) \
|
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0)
|
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((__packed__))
|
||||
#endif /* __packed */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||
#if defined (__GNUC__) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#else
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#if defined (__CC_ARM) /* ARM Compiler */
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
#elif defined (__TASKING__) /* TASKING Compiler */
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#endif /* __CC_ARM */
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ___STM32F3xx_HAL_DEF */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,679 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dma.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief DMA HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Direct Memory Access (DMA) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
* + Peripheral State and errors functions
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable and configure the peripheral to be connected to the DMA Channel
|
||||
(except for internal SRAM / FLASH memories: no initialization is
|
||||
necessary) please refer to Reference manual for connection between peripherals
|
||||
and DMA requests .
|
||||
|
||||
(#) For a given Channel, program the required configuration through the following parameters:
|
||||
Transfer Direction, Source and Destination data formats,
|
||||
Circular, Normal or peripheral flow control mode, Channel Priority level,
|
||||
Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
|
||||
Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
|
||||
|
||||
*** Polling mode IO operation ***
|
||||
=================================
|
||||
[..]
|
||||
(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
|
||||
address and destination address and the Length of data to be transferred
|
||||
(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
|
||||
case a fixed Timeout can be configured by User depending from his application.
|
||||
|
||||
*** Interrupt mode IO operation ***
|
||||
===================================
|
||||
[..]
|
||||
(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
|
||||
(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
|
||||
(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
|
||||
Source address and destination address and the Length of data to be transferred. In this
|
||||
case the DMA interrupt is configured
|
||||
(+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
|
||||
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
|
||||
add his own function by customization of function pointer XferCpltCallback and
|
||||
XferErrorCallback (i.e a member of DMA handle structure).
|
||||
|
||||
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
|
||||
detection.
|
||||
|
||||
(#) Use HAL_DMA_Abort() function to abort the current transfer
|
||||
|
||||
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
|
||||
|
||||
*** DMA HAL driver macros list ***
|
||||
=============================================
|
||||
[..]
|
||||
Below the list of most used macros in DMA HAL driver.
|
||||
|
||||
(+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
|
||||
(+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
|
||||
(+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
|
||||
(+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
|
||||
(+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
|
||||
(+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
|
||||
(+) __HAL_DMA_IT_STATUS: Check whether the specified DMA Channel interrupt has occurred or not.
|
||||
|
||||
[..]
|
||||
(@) You can refer to the DMA HAL driver header file for more useful macros
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA
|
||||
* @brief DMA HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to initialize the DMA Channel source
|
||||
and destination addresses, incrementation and data sizes, transfer direction,
|
||||
circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
|
||||
[..]
|
||||
The HAL_DMA_Init() function follows the DMA configuration procedures as described in
|
||||
reference manual.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the DMA according to the specified
|
||||
* parameters in the DMA_InitTypeDef and create the associated handle.
|
||||
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
/* Check the DMA handle allocation */
|
||||
if(hdma == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
|
||||
assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
|
||||
assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
|
||||
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
|
||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
|
||||
assert_param(IS_DMA_MODE(hdma->Init.Mode));
|
||||
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Get the CR register value */
|
||||
tmp = hdma->Instance->CCR;
|
||||
|
||||
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
|
||||
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
|
||||
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
|
||||
DMA_CCR_DIR));
|
||||
|
||||
/* Prepare the DMA Channel configuration */
|
||||
tmp |= hdma->Init.Direction |
|
||||
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
||||
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
||||
hdma->Init.Mode | hdma->Init.Priority;
|
||||
|
||||
/* Write to DMA Channel CR register */
|
||||
hdma->Instance->CCR = tmp;
|
||||
|
||||
/* Initialise the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Initialize the DMA state*/
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the DMA peripheral
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Check the DMA handle allocation */
|
||||
if(hdma == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
|
||||
/* Check the DMA peripheral state */
|
||||
if(hdma->State == HAL_DMA_STATE_BUSY)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Disable the selected DMA Channelx */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Reset DMA Channel control register */
|
||||
hdma->Instance->CCR = 0;
|
||||
|
||||
/* Reset DMA Channel Number of Data to Transfer register */
|
||||
hdma->Instance->CNDTR = 0;
|
||||
|
||||
/* Reset DMA Channel peripheral address register */
|
||||
hdma->Instance->CPAR = 0;
|
||||
|
||||
/* Reset DMA Channel memory address register */
|
||||
hdma->Instance->CMAR = 0;
|
||||
|
||||
/* Clear all flags */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
|
||||
|
||||
/* Initialise the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Initialize the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group2 I/O operation functions
|
||||
* @brief I/O operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure the source, destination address and data length and Start DMA transfer
|
||||
(+) Configure the source, destination address and data length and
|
||||
Start DMA transfer with interrupt
|
||||
(+) Abort DMA transfer
|
||||
(+) Poll for transfer complete
|
||||
(+) Handle DMA interrupt request
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Starts the DMA Transfer.
|
||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress: The source memory Buffer address
|
||||
* @param DstAddress: The destination memory Buffer address
|
||||
* @param DataLength: The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Disable the peripheral */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_DMA_ENABLE(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start the DMA Transfer with interrupt enabled.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress: The source memory Buffer address
|
||||
* @param DstAddress: The destination memory Buffer address
|
||||
* @param DataLength: The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Disable the peripheral */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Enable the transfer complete interrupt */
|
||||
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
|
||||
|
||||
/* Enable the Half transfer complete interrupt */
|
||||
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
|
||||
|
||||
/* Enable the transfer Error interrupt */
|
||||
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_DMA_ENABLE(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Aborts the DMA Transfer.
|
||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
*
|
||||
* @note After disabling a DMA Channel, a check for wait until the DMA Channel is
|
||||
* effectively disabled is added. If a Channel is disabled
|
||||
* while a data transfer is ongoing, the current data will be transferred
|
||||
* and the Channel will be effectively disabled only after the transfer of
|
||||
* this single data is finished.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t tickstart = 0x00;
|
||||
|
||||
/* Disable the channel */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Get timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Check if the DMA Channel is effectively disabled */
|
||||
while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
|
||||
{
|
||||
/* Check for the Timeout */
|
||||
if((HAL_GetTick()-tickstart) > HAL_TIMEOUT_DMA_ABORT)
|
||||
{
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_TIMEOUT;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
/* Change the DMA state*/
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Polling for transfer complete.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param CompleteLevel: Specifies the DMA level complete.
|
||||
* @param Timeout: Timeout duration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
|
||||
{
|
||||
uint32_t temp;
|
||||
uint32_t tickstart = 0x00;
|
||||
|
||||
/* Get the level transfer complete flag */
|
||||
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
|
||||
{
|
||||
/* Transfer Complete flag */
|
||||
temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Half Transfer Complete flag */
|
||||
temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
|
||||
}
|
||||
|
||||
/* Get timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
|
||||
{
|
||||
if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
|
||||
{
|
||||
/* Clear the transfer error flags */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State= HAL_DMA_STATE_ERROR;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check for the Timeout */
|
||||
if(Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
|
||||
{
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_TIMEOUT;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
|
||||
{
|
||||
/* Clear the transfer complete flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
|
||||
|
||||
/* The selected Channelx EN bit is cleared (DMA is disabled and
|
||||
all transfers are complete) */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the half transfer complete flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
|
||||
|
||||
hdma->State = HAL_DMA_STATE_READY_HALF;
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handles DMA interrupt request.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Transfer Error Interrupt management ***************************************/
|
||||
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
|
||||
{
|
||||
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
|
||||
{
|
||||
/* Disable the transfer error interrupt */
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
|
||||
|
||||
/* Clear the transfer error flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_TE;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_ERROR;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if (hdma->XferErrorCallback != NULL)
|
||||
{
|
||||
/* Transfer error callback */
|
||||
hdma->XferErrorCallback(hdma);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Half Transfer Complete Interrupt management ******************************/
|
||||
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
|
||||
{
|
||||
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
|
||||
{
|
||||
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
|
||||
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
|
||||
{
|
||||
/* Disable the half transfer interrupt */
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
|
||||
}
|
||||
/* Clear the half transfer complete flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_READY_HALF;
|
||||
|
||||
if(hdma->XferHalfCpltCallback != NULL)
|
||||
{
|
||||
/* Half transfer callback */
|
||||
hdma->XferHalfCpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Transfer Complete Interrupt management ***********************************/
|
||||
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
|
||||
{
|
||||
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
|
||||
{
|
||||
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
|
||||
{
|
||||
/* Disable the transfer complete interrupt */
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
|
||||
}
|
||||
/* Clear the transfer complete flag */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if(hdma->XferCpltCallback != NULL)
|
||||
{
|
||||
/* Transfer complete callback */
|
||||
hdma->XferCpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### State and Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides functions allowing to
|
||||
(+) Check the DMA state
|
||||
(+) Get error code
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the DMA state.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
return hdma->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the DMA error code
|
||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval DMA Error Code
|
||||
*/
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
return hdma->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Sets the DMA Transfer parameter.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress: The source memory Buffer address
|
||||
* @param DstAddress: The destination memory Buffer address
|
||||
* @param DataLength: The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
/* Configure DMA Channel data length */
|
||||
hdma->Instance->CNDTR = DataLength;
|
||||
|
||||
/* Peripheral to Memory */
|
||||
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
||||
{
|
||||
/* Configure DMA Channel destination address */
|
||||
hdma->Instance->CPAR = DstAddress;
|
||||
|
||||
/* Configure DMA Channel source address */
|
||||
hdma->Instance->CMAR = SrcAddress;
|
||||
}
|
||||
/* Memory to Peripheral */
|
||||
else
|
||||
{
|
||||
/* Configure DMA Channel source address */
|
||||
hdma->Instance->CPAR = SrcAddress;
|
||||
|
||||
/* Configure DMA Channel destination address */
|
||||
hdma->Instance->CMAR = DstAddress;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,420 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of DMA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_DMA_H
|
||||
#define __STM32F3xx_HAL_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief DMA Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref DMA_Data_transfer_direction */
|
||||
|
||||
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
|
||||
|
||||
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Memory_incremented_mode */
|
||||
|
||||
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_Peripheral_data_size */
|
||||
|
||||
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_Memory_data_size */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_mode
|
||||
@note The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_Priority_level */
|
||||
|
||||
} DMA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA Configuration enumeration values definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
|
||||
DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
|
||||
|
||||
} DMA_ControlTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
|
||||
HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
|
||||
HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
|
||||
HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
|
||||
HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
|
||||
HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
|
||||
|
||||
}HAL_DMA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
|
||||
HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
|
||||
|
||||
}HAL_DMA_LevelCompleteTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA handle Structure definition
|
||||
*/
|
||||
typedef struct __DMA_HandleTypeDef
|
||||
{
|
||||
DMA_Channel_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA locking object */
|
||||
|
||||
HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
|
||||
|
||||
void *Parent; /*!< Parent object state */
|
||||
|
||||
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
|
||||
|
||||
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
|
||||
|
||||
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA Error code */
|
||||
|
||||
} DMA_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Error_Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
|
||||
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
|
||||
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_Data_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
|
||||
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
|
||||
#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
|
||||
|
||||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Data_buffer_size
|
||||
* @{
|
||||
*/
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
|
||||
#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
|
||||
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
|
||||
((STATE) == DMA_PINC_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
|
||||
#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
|
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
|
||||
((STATE) == DMA_MINC_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_data_size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
|
||||
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
|
||||
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
|
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_PDATAALIGN_WORD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_Memory_data_size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
|
||||
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
|
||||
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
|
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_MDATAALIGN_WORD ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
|
||||
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
|
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
|
||||
((MODE) == DMA_CIRCULAR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Priority_level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
|
||||
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
|
||||
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
|
||||
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
|
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
|
||||
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
||||
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
||||
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_interrupt_enable_definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
|
||||
#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
|
||||
#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flag_definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset DMA handle state
|
||||
* @param __HANDLE__: DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Channel.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Channel.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
|
||||
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
|
||||
/**
|
||||
* @brief Enables the specified DMA Channel interrupts.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disables the specified DMA Channel interrupts.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMA Channel interrupt has occurred or not.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __INTERRUPT__: specifies the DMA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval The state of DMA_IT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/* Include DMA HAL Extension module */
|
||||
#include "stm32f3xx_hal_dma_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_DMA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,248 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_dma_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of DMA HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_DMA_EX_H
|
||||
#define __STM32F3xx_HAL_DMA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMAEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Interrupt & Flag management */
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer complete flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified transfer complete flag index.
|
||||
*/
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F373xC)
|
||||
/** @defgroup STM32F302xC_STM32F303xC_STM32F373xC Product devices
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
|
||||
DMA_FLAG_TC5)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel half transfer complete flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified half transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
|
||||
DMA_FLAG_HT5)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer error flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
|
||||
DMA_FLAG_TE5)
|
||||
|
||||
/**
|
||||
* @brief Get the DMA Channel pending flags.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __FLAG__: Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCIFx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEIFx: Transfer error flag
|
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
|
||||
(DMA1->ISR & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clears the DMA Channel pending flags.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCIFx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEIFx: Transfer error flag
|
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
|
||||
(DMA1->IFCR = (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#else
|
||||
|
||||
/** @defgroup STM32F301x8_STM32F302x8_STM32F303x8_STM32F334x8 Product devices
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||
DMA_FLAG_TC7)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel half transfer complete flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified half transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||
DMA_FLAG_HT7)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer error flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||
DMA_FLAG_TE7)
|
||||
|
||||
/**
|
||||
* @brief Get the DMA Channel pending flags.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __FLAG__: Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCIFx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEIFx: Transfer error flag
|
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clears the DMA Channel pending flags.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCIFx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEIFx: Transfer error flag
|
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR |= (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_DMA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,694 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_flash.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief FLASH HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the internal FLASH memory:
|
||||
* + Program operations functions
|
||||
* + Memory Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### FLASH peripheral features #####
|
||||
==============================================================================
|
||||
|
||||
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
|
||||
to the Flash memory. It implements the erase and program Flash memory operations
|
||||
and the read and write protection mechanisms.
|
||||
|
||||
[..] The Flash memory interface accelerates code execution with a system of instruction
|
||||
prefetch.
|
||||
|
||||
[..] The FLASH main features are:
|
||||
(+) Flash memory read operations
|
||||
(+) Flash memory program/erase operations
|
||||
(+) Read / write protections
|
||||
(+) Prefetch on I-Code
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This driver provides functions and macros to configure and program the FLASH
|
||||
memory of all STM32F3xx devices. These functions are split in 3 groups:
|
||||
|
||||
(#) FLASH Memory I/O Programming functions: this group includes all needed
|
||||
functions to erase and program the main memory:
|
||||
(++) Lock and Unlock the FLASH interface
|
||||
(++) Erase function: Erase page, erase all pages
|
||||
(++) Program functions: half word and word
|
||||
|
||||
(#) Option Bytes Programming functions: this group includes all needed
|
||||
functions to manage the Option Bytes:
|
||||
(++) Lock and Unlock the Option Bytes
|
||||
(++) Erase Option Bytes
|
||||
(++) Set/Reset the write protection
|
||||
(++) Set the Read protection Level
|
||||
(++) Program the user Option Bytes
|
||||
(++) Program the data Option Bytes
|
||||
(++) Launch the Option Bytes loader
|
||||
|
||||
(#) Interrupts and flags management functions : this group
|
||||
includes all needed functions to:
|
||||
(++) Handle FLASH interrupts
|
||||
(++) Wait for last FLASH operation according to its status
|
||||
(++) Get error flag status
|
||||
|
||||
[..] In addition to these function, this driver includes a set of macros allowing
|
||||
to handle the following operations:
|
||||
|
||||
(+) Set the latency
|
||||
(+) Enable/Disable the prefetch buffer
|
||||
(+) Enable/Disable the half cycle access
|
||||
(+) Enable/Disable the FLASH interrupts
|
||||
(+) Monitor the FLASH flags status
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH
|
||||
* @brief FLASH HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Variables used for Erase pages under interruption*/
|
||||
FLASH_ProcessTypeDef pFlash;
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Erase operations */
|
||||
void FLASH_PageErase(uint32_t PageAddress);
|
||||
|
||||
/* Program operations */
|
||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
|
||||
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
static void FLASH_SetErrorCode(void);
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_FLASH_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_FLASH_Group2 I/O operation functions
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to manage the FLASH
|
||||
program operations (write/erase).
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Program halfword, word or double word at a specified address
|
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param TypeProgram: Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address: Specifies the address to be programmed.
|
||||
* @param Data: Specifies the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
uint8_t index = 0;
|
||||
uint8_t nbiterations = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TYPEPROGRAM(TypeProgram));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
if(TypeProgram == TYPEPROGRAM_HALFWORD)
|
||||
{
|
||||
/* Program halfword (16-bit) at a specified address. */
|
||||
nbiterations = 1;
|
||||
}
|
||||
else if(TypeProgram == TYPEPROGRAM_WORD)
|
||||
{
|
||||
/* Program word (32-bit = 2*16-bit) at a specified address. */
|
||||
nbiterations = 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Program double word (64-bit = 4*16-bit) at a specified address. */
|
||||
nbiterations = 4;
|
||||
}
|
||||
|
||||
for (index = 0; index < nbiterations; index++)
|
||||
{
|
||||
FLASH_Program_HalfWord((Address + (2*index)), (uint16_t)(Data >> (16*index)));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
}
|
||||
|
||||
/* If the program operation is completed, disable the PG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
|
||||
}
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program halfword, word or double word at a specified address with interrupt enabled.
|
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param TypeProgram: Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address: Specifies the address to be programmed.
|
||||
* @param Data: Specifies the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TYPEPROGRAM(TypeProgram));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Enable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_ENABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR));
|
||||
|
||||
pFlash.Address = Address;
|
||||
pFlash.Data = Data;
|
||||
|
||||
if(TypeProgram == TYPEPROGRAM_HALFWORD)
|
||||
{
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
|
||||
/*Program halfword (16-bit) at a specified address.*/
|
||||
pFlash.DataRemaining = 1;
|
||||
}
|
||||
else if(TypeProgram == TYPEPROGRAM_WORD)
|
||||
{
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
|
||||
/*Program word (32-bit : 2*16-bit) at a specified address.*/
|
||||
pFlash.DataRemaining = 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
|
||||
/*Program double word (64-bit : 4*16-bit) at a specified address.*/
|
||||
pFlash.DataRemaining = 4;
|
||||
}
|
||||
|
||||
/*Program halfword (16-bit) at a specified address.*/
|
||||
FLASH_Program_HalfWord(Address, (uint16_t)Data);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles FLASH interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASH_IRQHandler(void)
|
||||
{
|
||||
uint32_t addresstmp;
|
||||
/* If the operation is completed, disable the PG, PER and MER Bits */
|
||||
CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
|
||||
{
|
||||
/* Nb of pages to erased can be decreased */
|
||||
pFlash.DataRemaining--;
|
||||
|
||||
/* Indicate user which page address has been erased*/
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
|
||||
|
||||
/* Check if there are still pages to erase*/
|
||||
if(pFlash.DataRemaining != 0)
|
||||
{
|
||||
/* Increment page address to next page */
|
||||
pFlash.Address += FLASH_PAGE_SIZE;
|
||||
addresstmp = pFlash.Address;
|
||||
FLASH_PageErase(addresstmp);
|
||||
}
|
||||
else
|
||||
{
|
||||
/*No more pages to Erase*/
|
||||
|
||||
/*Reset Address and stop Erase pages procedure*/
|
||||
pFlash.Address = 0xFFFFFFFF;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
}
|
||||
else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
|
||||
{
|
||||
/*MassErase ended. Return the selected bank*/
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(0);
|
||||
|
||||
/* Stop Mass Erase procedure*/
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Nb of 16-bit data to program can be decreased */
|
||||
pFlash.DataRemaining--;
|
||||
|
||||
/* Check if there are still 16-bit data to program */
|
||||
if(pFlash.DataRemaining != 0)
|
||||
{
|
||||
/* Increment address to 16-bit */
|
||||
pFlash.Address += 2;
|
||||
addresstmp = pFlash.Address;
|
||||
|
||||
/* Shift to have next 16-bit data */
|
||||
pFlash.Data = (pFlash.Data >> 16);
|
||||
|
||||
/*Program halfword (16-bit) at a specified address.*/
|
||||
FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
|
||||
}
|
||||
else
|
||||
{
|
||||
/*Program ended. Return the selected address*/
|
||||
/* FLASH EOP interrupt user callback */
|
||||
if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
|
||||
{
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
|
||||
}
|
||||
else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
|
||||
{
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address-2);
|
||||
}
|
||||
else
|
||||
{
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address-6);
|
||||
}
|
||||
|
||||
/* Reset Address and stop Program procedure*/
|
||||
pFlash.Address = 0xFFFFFFFF;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Check FLASH operation error flags */
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR))
|
||||
{
|
||||
/*Save the Error code*/
|
||||
FLASH_SetErrorCode();
|
||||
|
||||
/* FLASH error interrupt user callback */
|
||||
HAL_FLASH_OperationErrorCallback(pFlash.Address);
|
||||
|
||||
/* Clear FLASH error pending bits */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
/* Reset address and stop the procedure ongoing*/
|
||||
pFlash.Address = 0xFFFFFFFF;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
|
||||
{
|
||||
/* Disable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_DISABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR));
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief FLASH end of operation interrupt callback
|
||||
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
|
||||
* - Mass Erase: No return value expected
|
||||
* - Pages Erase: Address of the page which has been erased
|
||||
* - Program: Address which was selected for data program
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH operation error interrupt callback
|
||||
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
|
||||
* - Mass Erase: No return value expected
|
||||
* - Pages Erase: Address of the page which returned an error
|
||||
* - Program: Address which was selected for data program
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_FLASH_Group3 Peripheral Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the FLASH
|
||||
memory operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH control register access
|
||||
* @param None
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
|
||||
{
|
||||
if((READ_BIT(FLASH->CR, FLASH_CR_LOCK)) != RESET)
|
||||
{
|
||||
/* Authorize the FLASH Registers access */
|
||||
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
|
||||
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks the FLASH control register access
|
||||
* @param None
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void)
|
||||
{
|
||||
/* Set the LOCK Bit to lock the FLASH Registers access */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH Option Control Registers access.
|
||||
* @param None
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
|
||||
{
|
||||
if((READ_BIT(FLASH->CR, FLASH_CR_OPTWRE)) == RESET)
|
||||
{
|
||||
/* Authorizes the Option Byte register programming */
|
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
|
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Lock the FLASH Option Control Registers access.
|
||||
* @param None
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
|
||||
{
|
||||
/* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Launch the option byte loading.
|
||||
* @param None
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
|
||||
{
|
||||
/* Set the bit to force the option byte reloading */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
return(FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_FLASH_Group4 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permit to get in run-time the status of the FLASH peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get the specific FLASH error flag.
|
||||
* @param None
|
||||
* @retval FLASH_ErrorCode: The returned value can be:
|
||||
* @arg FLASH_ERROR_PG: FLASH Programming error flag
|
||||
* @arg FLASH_ERROR_WRP: FLASH Write protected error flag
|
||||
*/
|
||||
FLASH_ErrorTypeDef HAL_FLASH_GetError(void)
|
||||
{
|
||||
return pFlash.ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Program a half-word (16-bit) at a specified address.
|
||||
* @param Address: specifies the address to be programmed.
|
||||
* @param Data: specifies the data to be programmed.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
|
||||
{
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
/* Proceed to program the new data */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_PG);
|
||||
|
||||
*(__IO uint16_t*)Address = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait for a FLASH operation to complete.
|
||||
* @param Timeout: maximum flash operationtimeout
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
|
||||
{
|
||||
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
||||
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
||||
flag will be set */
|
||||
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
|
||||
{
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
|
||||
{
|
||||
/*Save the error code*/
|
||||
FLASH_SetErrorCode();
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* If there is an error flag set */
|
||||
return HAL_OK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Erase the specified FLASH memory page
|
||||
* @param PageAddress: FLASH page to erase
|
||||
* The value of this parameter depend on device used within the same series
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FLASH_PageErase(uint32_t PageAddress)
|
||||
{
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
/* Proceed to erase the page */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_PER);
|
||||
WRITE_REG(FLASH->AR, PageAddress);
|
||||
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specific FLASH error flag.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_SetErrorCode(void)
|
||||
{
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
|
||||
{
|
||||
pFlash.ErrorCode = FLASH_ERROR_WRP;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
|
||||
{
|
||||
pFlash.ErrorCode |= FLASH_ERROR_PG;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,504 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of Flash HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_FLASH_H
|
||||
#define __STM32F3xx_HAL_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Error source
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_ERROR_PG = 0x01,
|
||||
FLASH_ERROR_WRP = 0x02
|
||||
} FLASH_ErrorTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Erase structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
|
||||
This parameter can be a value of @ref FLASH_Type_Erase */
|
||||
|
||||
uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
|
||||
This parameter must be a value of @ref FLASHEx_Address */
|
||||
|
||||
uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
|
||||
This parameter must be a value between 1 and (max number of pages - value of initial page)*/
|
||||
|
||||
} FLASH_EraseInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Options bytes program structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OptionType; /*!< OptionType: Option byte to be configured.
|
||||
This parameter can be a value of @ref FLASH_OB_Type */
|
||||
|
||||
uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
|
||||
This parameter can be a value of @ref FLASH_OB_WRP_State */
|
||||
|
||||
uint32_t WRPPage; /*!< WRPSector: specifies the page(s) to be write protected
|
||||
This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
|
||||
|
||||
uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
|
||||
This parameter can be a value of @ref FLASH_OB_Read_Protection */
|
||||
|
||||
uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
|
||||
IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY / SDADC12_VDD_MONITOR
|
||||
This parameter can be a combination of @ref FLASH_OB_IWatchdog, @ref FLASH_OB_nRST_STOP,
|
||||
@ref FLASH_OB_nRST_STDBY, @ref FLASH_OB_BOOT1, @ref FLASH_OB_VDDA_Analog_Monitoring,
|
||||
@ref FLASH_OB_SRAM_Parity_Enable and @ref FLASH_OB_SDADC12_VDD_MONITOR */
|
||||
|
||||
uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be prgrammed
|
||||
This parameter can be a value of @ref FLASH_OB_Data_Address */
|
||||
|
||||
uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
|
||||
This parameter can have any value */
|
||||
|
||||
} FLASH_OBProgramInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Procedure structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_PROC_NONE = 0,
|
||||
FLASH_PROC_PAGEERASE = 1,
|
||||
FLASH_PROC_MASSERASE = 2,
|
||||
FLASH_PROC_PROGRAMHALFWORD = 3,
|
||||
FLASH_PROC_PROGRAMWORD = 4,
|
||||
FLASH_PROC_PROGRAMDOUBLEWORD = 5
|
||||
} FLASH_ProcedureTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
|
||||
|
||||
__IO uint32_t DataRemaining; /* Internal variable to save the remaining pages to erase or half-word to program in IT context */
|
||||
|
||||
__IO uint32_t Address; /* Internal variable to save address selected for program or erase */
|
||||
|
||||
__IO uint64_t Data; /* Internal variable to save data to be programmed */
|
||||
|
||||
HAL_LockTypeDef Lock; /* FLASH locking object */
|
||||
|
||||
__IO FLASH_ErrorTypeDef ErrorCode; /* FLASH error code */
|
||||
|
||||
} FLASH_ProcessTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Type_Erase FLASH Type Erase
|
||||
* @{
|
||||
*/
|
||||
#define TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/
|
||||
#define TYPEERASE_MASSERASE ((uint32_t)0x01) /*!<Flash mass erase activation*/
|
||||
|
||||
#define IS_TYPEERASE(VALUE) (((VALUE) == TYPEERASE_PAGES) || \
|
||||
((VALUE) == TYPEERASE_MASSERASE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Type_Program FLASH Type Program
|
||||
* @{
|
||||
*/
|
||||
#define TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!<Program a half-word (16-bit) at a specified address.*/
|
||||
#define TYPEPROGRAM_WORD ((uint32_t)0x02) /*!<Program a word (32-bit) at a specified address.*/
|
||||
#define TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!<Program a double word (64-bit) at a specified address*/
|
||||
|
||||
#define IS_TYPEPROGRAM(VALUE) (((VALUE) == TYPEPROGRAM_HALFWORD) || \
|
||||
((VALUE) == TYPEPROGRAM_WORD) || \
|
||||
((VALUE) == TYPEPROGRAM_DOUBLEWORD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_WRP_State FLASH WRP State
|
||||
* @{
|
||||
*/
|
||||
#define WRPSTATE_DISABLE ((uint32_t)0x00) /*!<Disable the write protection of the desired pages*/
|
||||
#define WRPSTATE_ENABLE ((uint32_t)0x01) /*!<Enable the write protection of the desired pagess*/
|
||||
|
||||
#define IS_WRPSTATE(VALUE) (((VALUE) == WRPSTATE_DISABLE) || \
|
||||
((VALUE) == WRPSTATE_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_Type FLASH Option Bytes Type
|
||||
* @{
|
||||
*/
|
||||
#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!<WRP option byte configuration*/
|
||||
#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!<RDP option byte configuration*/
|
||||
#define OPTIONBYTE_USER ((uint32_t)0x04) /*!<USER option byte configuration*/
|
||||
#define OPTIONBYTE_DATA ((uint32_t)0x08) /*!<DATA option byte configuration*/
|
||||
|
||||
#define IS_OPTIONBYTE(VALUE) (((VALUE) < (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_LATENCY_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
|
||||
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
|
||||
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
|
||||
((LATENCY) == FLASH_LATENCY_1) || \
|
||||
((LATENCY) == FLASH_LATENCY_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_Data_Address
|
||||
* @{
|
||||
*/
|
||||
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_Read_Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
|
||||
#define OB_RDP_LEVEL_1 ((uint8_t)0xBB)
|
||||
#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
|
||||
it's no more possible to go back to level 1 or 0 */
|
||||
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
|
||||
((LEVEL) == OB_RDP_LEVEL_1))/*||\
|
||||
((LEVEL) == OB_RDP_LEVEL_2))*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_IWatchdog
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_nRST_STOP
|
||||
* @{
|
||||
*/
|
||||
#define OB_STOP_NO_RST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_nRST_STDBY
|
||||
* @{
|
||||
*/
|
||||
#define OB_STDBY_NO_RST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_BOOT1
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
|
||||
#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
|
||||
#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_VDDA_Analog_Monitoring
|
||||
* @{
|
||||
*/
|
||||
#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
|
||||
#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
|
||||
#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_SRAM_Parity_Enable
|
||||
* @{
|
||||
*/
|
||||
#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable set */
|
||||
#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */
|
||||
#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_SDADC12_VDD_MONITOR
|
||||
* @{
|
||||
*/
|
||||
#define OB_SDADC12_VDD_MONITOR_SET ((uint8_t)0x80) /*!< SDADC12_VDD power supply supervisor set */
|
||||
#define OB_SDADC12_VDD_MONITOR_RESET ((uint8_t)0x00) /*!< SDADC12_VDD power supply supervisor reset */
|
||||
#define IS_OB_SDADC12_VDD_MONITOR(MONITOR) (((MONITOR) == OB_SDADC12_VDD_MONITOR_SET) || ((MONITOR) == OB_SDADC12_VDD_MONITOR_RESET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flag_definition
|
||||
* @brief Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
|
||||
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFC3) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
|
||||
((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt_definition
|
||||
* @brief FLASH Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
|
||||
#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */
|
||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && ((IT) != 0x00000000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Timeout_definition
|
||||
* @brief FLASH Timeout definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_Macros
|
||||
* @brief macros to control FLASH features
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the FLASH Latency.
|
||||
* @param __LATENCY__: FLASH Latency
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH prefetch buffer.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH prefetch buffer.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH half cycle access.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH half cycle access.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt
|
||||
* @brief macros to handle FLASH interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ : FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
|
||||
* @arg FLASH_IT_ERR: Error Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ : FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
|
||||
* @arg FLASH_IT_ERR: Error Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Get the specified FLASH flag status.
|
||||
* @param __FLAG__: specifies the FLASH flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
|
||||
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
|
||||
* @arg FLASH_FLAG_PGERR : FLASH Programming error flag
|
||||
* @arg FLASH_FLAG_BSY : FLASH Busy flag
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified FLASH flag.
|
||||
* @param __FLAG__: specifies the FLASH flags to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
|
||||
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
|
||||
* @arg FLASH_FLAG_PGERR : FLASH Programming error flag
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include FLASH HAL Extension module */
|
||||
#include "stm32f3xx_hal_flash_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
|
||||
/* FLASH IRQ handler method */
|
||||
void HAL_FLASH_IRQHandler(void);
|
||||
/* Callbacks in non blocking modes */
|
||||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
|
||||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
|
||||
/* Option bytes control */
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
FLASH_ErrorTypeDef HAL_FLASH_GetError(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_FLASH_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,805 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_flash_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Extended FLASH HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the FLASH peripheral:
|
||||
* + Extended Initialization/de-initialization functions
|
||||
* + Extended I/O operation functions
|
||||
* + Extended Peripheral Control functions
|
||||
* + Extended Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Flash peripheral extended features #####
|
||||
==============================================================================
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] This driver provides functions to configure and program the FLASH memory
|
||||
of all STM32F3xxx devices. It includes
|
||||
|
||||
(++) Set/Reset the write protection
|
||||
(++) Program the user Option Bytes
|
||||
(++) Get the Read protection Level
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @brief FLASH HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Variables used for Erase pages under interruption*/
|
||||
extern FLASH_ProcessTypeDef pFlash;
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Erase operations */
|
||||
extern void FLASH_PageErase(uint32_t PageAddress);
|
||||
static void FLASH_MassErase(void);
|
||||
|
||||
/* Option bytes control */
|
||||
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
|
||||
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage);
|
||||
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel);
|
||||
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);
|
||||
static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
|
||||
static uint32_t FLASH_OB_GetWRP(void);
|
||||
static FlagStatus FLASH_OB_GetRDP(void);
|
||||
static uint8_t FLASH_OB_GetUser(void);
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization/de-initialization functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Group2 I/O operation functions
|
||||
* @brief I/O operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Perform a mass erase or erase the specified FLASH memory pages
|
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
|
||||
* @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
|
||||
* contains the configuration information for the erasing.
|
||||
*
|
||||
* @param[out] PageError: pointer to variable that
|
||||
* contains the configuration information on faulty page in case of error
|
||||
* (0xFFFFFFFF means that all the pages have been correctly erased)
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
uint32_t address = 0;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
if (pEraseInit->TypeErase == TYPEERASE_MASSERASE)
|
||||
{
|
||||
/*Mass erase to be done*/
|
||||
FLASH_MassErase();
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
}
|
||||
|
||||
/* If the erase operation is completed, disable the MER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
|
||||
assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
|
||||
|
||||
/*Initialization of PageError variable*/
|
||||
*PageError = 0xFFFFFFFF;
|
||||
|
||||
/* Erase by page by page to be done*/
|
||||
for(address = pEraseInit->PageAddress;
|
||||
address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE);
|
||||
address += FLASH_PAGE_SIZE)
|
||||
{
|
||||
FLASH_PageErase(address);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
}
|
||||
|
||||
/* If the erase operation is completed, disable the PER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
|
||||
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* In case of error, stop erase procedure and return the faulty address */
|
||||
*PageError = address;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
|
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
|
||||
* @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
|
||||
* contains the configuration information for the erasing.
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
|
||||
|
||||
/* Enable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_ENABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR));
|
||||
|
||||
if (pEraseInit->TypeErase == TYPEERASE_MASSERASE)
|
||||
{
|
||||
/*Mass erase to be done*/
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
|
||||
FLASH_MassErase();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Erase by page to be done*/
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
|
||||
assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
|
||||
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
|
||||
pFlash.DataRemaining = pEraseInit->NbPages;
|
||||
pFlash.Address = pEraseInit->PageAddress;
|
||||
|
||||
/*Erase 1st page and wait for IT*/
|
||||
FLASH_PageErase(pEraseInit->PageAddress);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Group3 Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the FLASH
|
||||
memory operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Erases the FLASH option bytes.
|
||||
* @note This functions erases all option bytes except the Read protection (RDP).
|
||||
* The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
|
||||
* The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
|
||||
* (system reset will occur)
|
||||
* @param None
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
|
||||
{
|
||||
uint8_t rdptmp = OB_RDP_LEVEL_0;
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
FLASH_OBProgramInitTypeDef optionsbytes;
|
||||
|
||||
/* Get the actual read protection Option Byte value */
|
||||
HAL_FLASHEx_OBGetConfig(&optionsbytes);
|
||||
if(optionsbytes.RDPLevel != RESET)
|
||||
{
|
||||
rdptmp = OB_RDP_LEVEL_1;
|
||||
}
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* If the previous operation is completed, proceed to erase the option bytes */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTER);
|
||||
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the erase operation is completed, disable the OPTER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Restore the last read protection Option Byte value */
|
||||
optionsbytes.OptionType = OPTIONBYTE_RDP;
|
||||
optionsbytes.RDPLevel = rdptmp;
|
||||
status = HAL_FLASHEx_OBProgram(&optionsbytes);
|
||||
}
|
||||
}
|
||||
|
||||
/* Return the erase status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program option bytes
|
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
|
||||
* The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
|
||||
* (system reset will occur)
|
||||
*
|
||||
* @param pOBInit: pointer to an FLASH_OBInitStruct structure that
|
||||
* contains the configuration information for the programming.
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
|
||||
|
||||
/* Write protection configuration */
|
||||
if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
|
||||
{
|
||||
assert_param(IS_WRPSTATE(pOBInit->WRPState));
|
||||
if (pOBInit->WRPState == WRPSTATE_ENABLE)
|
||||
{
|
||||
/* Enable of Write protection on the selected page */
|
||||
status = FLASH_OB_EnableWRP(pOBInit->WRPPage);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable of Write protection on the selected page */
|
||||
status = FLASH_OB_DisableWRP(pOBInit->WRPPage);
|
||||
}
|
||||
}
|
||||
|
||||
/* Read protection configuration */
|
||||
if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
|
||||
{
|
||||
status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
|
||||
}
|
||||
|
||||
/* USER configuration */
|
||||
if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
|
||||
{
|
||||
status = FLASH_OB_UserConfig(pOBInit->USERConfig);
|
||||
}
|
||||
|
||||
/* DATA configuration*/
|
||||
if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA)
|
||||
{
|
||||
status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the Option byte configuration
|
||||
* @param pOBInit: pointer to an FLASH_OBInitStruct structure that
|
||||
* contains the configuration information for the programming.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
|
||||
{
|
||||
pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;
|
||||
|
||||
/*Get WRP*/
|
||||
pOBInit->WRPPage = FLASH_OB_GetWRP();
|
||||
|
||||
/*Get RDP Level*/
|
||||
pOBInit->RDPLevel = FLASH_OB_GetRDP();
|
||||
|
||||
/*Get USER*/
|
||||
pOBInit->USERConfig = FLASH_OB_GetUser();
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Mass erase of FLASH memory
|
||||
* @param None
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_MassErase(void)
|
||||
{
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
/* Proceed to erase all sectors */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_MER);
|
||||
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the write protection of the desired pages
|
||||
* @note When the memory read protection level is selected (RDP level = 1),
|
||||
* it is not possible to program or erase the flash page i if CortexM4
|
||||
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
|
||||
*
|
||||
* @param WriteProtectPage: specifies the page(s) to be write protected.
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF;
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
uint16_t WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_WRP(WriteProtectPage));
|
||||
|
||||
WriteProtectPage = (uint32_t)(~WriteProtectPage);
|
||||
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
|
||||
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
|
||||
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
if(WRP0_Data != 0xFF)
|
||||
{
|
||||
OB->WRP0 &= WRP0_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
|
||||
if((status == HAL_OK) && (WRP1_Data != 0xFF))
|
||||
{
|
||||
OB->WRP1 &= WRP1_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
if((status == HAL_OK) && (WRP2_Data != 0xFF))
|
||||
{
|
||||
OB->WRP2 &= WRP2_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
|
||||
if((status == HAL_OK) && (WRP3_Data != 0xFF))
|
||||
{
|
||||
OB->WRP3 &= WRP3_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
|
||||
return status;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the write protection of the desired pages
|
||||
* @note When the memory read protection level is selected (RDP level = 1),
|
||||
* it is not possible to program or erase the flash page i if CortexM4
|
||||
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
|
||||
*
|
||||
* @param WriteProtectPage: specifies the page(s) to be write unprotected.
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF;
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
uint16_t WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_WRP(WriteProtectPage));
|
||||
|
||||
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
|
||||
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
|
||||
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
if(WRP0_Data != 0xFF)
|
||||
{
|
||||
OB->WRP0 |= WRP0_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
|
||||
if((status == HAL_OK) && (WRP1_Data != 0xFF))
|
||||
{
|
||||
OB->WRP1 |= WRP1_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
if((status == HAL_OK) && (WRP2_Data != 0xFF))
|
||||
{
|
||||
OB->WRP2 |= WRP2_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
|
||||
if((status == HAL_OK) && (WRP3_Data != 0xFF))
|
||||
{
|
||||
OB->WRP3 |= WRP3_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the read protection level.
|
||||
* @param ReadProtectLevel: specifies the read protection level.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OB_RDP_LEVEL_0: No protection
|
||||
* @arg OB_RDP_LEVEL_1: Read protection of the memory
|
||||
* @arg OB_RDP_LEVEL_2: Full chip protection
|
||||
*
|
||||
* @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
|
||||
*
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Enable the Option Bytes Programming operation */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
WRITE_REG(OB->RDP, ReadProtectLevel);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program the FLASH User Option Byte.
|
||||
* @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
|
||||
* @param UserConfig: The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), BOOT1(Bit4),
|
||||
* VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
|
||||
* And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW)));
|
||||
assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST)));
|
||||
assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST)));
|
||||
assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));
|
||||
assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON)));
|
||||
assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET)));
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
assert_param(IS_OB_SDACD_VDD_MONITOR((UserConfig&OB_SDACD_VDD_MONITOR_SET)));
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Enable the Option Bytes Programming operation */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F302xC) || defined(STM32F303x8) || defined(STM32F303xC) || defined(STM32F318xx) || defined(STM32F334x8) || defined(STM32F358xx)
|
||||
OB->USER = (UserConfig | 0x88);
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F303xC || STM32F318xx || STM32F334x8 || STM32F358xx */
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
OB->USER = (UserConfig | 0x08);
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Programs a half word at a specified Option Byte Data address.
|
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
|
||||
* The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
|
||||
* (system reset will occur)
|
||||
* Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
|
||||
* @param Address: specifies the address to be programmed.
|
||||
* This parameter can be 0x1FFFF804 or 0x1FFFF806.
|
||||
* @param Data: specifies the data to be programmed.
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_DATA_ADDRESS(Address));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Enables the Option Bytes Programming operation */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
*(__IO uint16_t*)Address = Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
/* Return the Option Byte Data Program Status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the FLASH Write Protection Option Bytes value.
|
||||
* @param None
|
||||
* @retval The FLASH Write Protection Option Bytes value
|
||||
*/
|
||||
static uint32_t FLASH_OB_GetWRP(void)
|
||||
{
|
||||
/* Return the FLASH write protection Register value */
|
||||
return (uint32_t)(READ_REG(FLASH->WRPR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the FLASH Read Protection level.
|
||||
* @param None
|
||||
* @retval FLASH ReadOut Protection Status:
|
||||
* - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
|
||||
* - RESET, when OB_RDP_Level_0 is set
|
||||
*/
|
||||
static FlagStatus FLASH_OB_GetRDP(void)
|
||||
{
|
||||
FlagStatus readstatus = RESET;
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
if ((uint8_t)READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT) != RESET)
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
|
||||
/* STM32F302xC || STM32F303xC || STM32F358xx || */
|
||||
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
if ((uint8_t)READ_BIT(FLASH->OBR, (FLASH_OBR_LEVEL1_PROT | FLASH_OBR_LEVEL2_PROT)) != RESET)
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
{
|
||||
readstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
readstatus = RESET;
|
||||
}
|
||||
return readstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the FLASH User Option Byte value.
|
||||
* @param None
|
||||
* @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), BOOT1(Bit4),
|
||||
* VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
|
||||
* And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
|
||||
*/
|
||||
static uint8_t FLASH_OB_GetUser(void)
|
||||
{
|
||||
/* Return the User Option Byte */
|
||||
return (uint8_t)(READ_REG(FLASH->OBR) >> 8);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,225 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_flash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of Flash HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_FLASH_EX_H
|
||||
#define __STM32F3xx_HAL_FLASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFFF7CC)
|
||||
#define FLASH_PAGE_SIZE 0x800
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Address
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
|
||||
defined(STM32F373xC) || defined(STM32F378xx)
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? \
|
||||
((ADDRESS) <= 0x0803FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? \
|
||||
((ADDRESS) <= 0x0801FFFF) : ((ADDRESS) <= 0x0800FFFF))))
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
|
||||
/* STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? \
|
||||
((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? \
|
||||
((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFF))))
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
|
||||
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Nb_Pages
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
|
||||
defined(STM32F373xC) || defined(STM32F378xx)
|
||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF) : \
|
||||
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) : \
|
||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF)))
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
|
||||
/* STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF) : \
|
||||
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) : \
|
||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFF)))
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
|
||||
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_Write_Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRP_PAGES0TO1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
|
||||
#define OB_WRP_PAGES2TO3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
|
||||
#define OB_WRP_PAGES4TO5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
|
||||
#define OB_WRP_PAGES6TO7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
|
||||
#define OB_WRP_PAGES8TO9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
|
||||
#define OB_WRP_PAGES10TO11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
|
||||
#define OB_WRP_PAGES12TO13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
|
||||
#define OB_WRP_PAGES14TO15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
|
||||
#define OB_WRP_PAGES16TO17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
|
||||
#define OB_WRP_PAGES18TO19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
|
||||
#define OB_WRP_PAGES20TO21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
|
||||
#define OB_WRP_PAGES22TO23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
|
||||
#define OB_WRP_PAGES24TO25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
|
||||
#define OB_WRP_PAGES26TO27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
|
||||
#define OB_WRP_PAGES28TO29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
|
||||
#define OB_WRP_PAGES30TO31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
#define OB_WRP_PAGES32TO33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
|
||||
#define OB_WRP_PAGES34TO35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
|
||||
#define OB_WRP_PAGES36TO37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
|
||||
#define OB_WRP_PAGES38TO39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
|
||||
#define OB_WRP_PAGES40TO41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
|
||||
#define OB_WRP_PAGES42TO43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
|
||||
#define OB_WRP_PAGES44TO45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
|
||||
#define OB_WRP_PAGES46TO47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
|
||||
#define OB_WRP_PAGES48TO49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
|
||||
#define OB_WRP_PAGES50TO51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
|
||||
#define OB_WRP_PAGES52TO53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
|
||||
#define OB_WRP_PAGES54TO55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
|
||||
#define OB_WRP_PAGES56TO57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
|
||||
#define OB_WRP_PAGES58TO59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
|
||||
#define OB_WRP_PAGES60TO61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
|
||||
#define OB_WRP_PAGES62TO127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
#define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF)
|
||||
#define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00)
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
|
||||
#define OB_WRP_PAGES48TO127MASK ((uint32_t)0xFF000000)
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
|
||||
#define OB_WRP_PAGES48TO127MASK ((uint32_t)0xFF000000)
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F373xC) || defined(STM32F378xx)
|
||||
#define OB_WRP_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< Write protection of all pages */
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || STM32F373xC || STM32F378xx */
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
||||
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
#define OB_WRP_ALLPAGES ((uint32_t)0x0000FFFF) /*!< Write protection of all pages */
|
||||
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
|
||||
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
|
||||
|
||||
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
/** @defgroup FLASHEx_OB_SDADC12_VDD_MONITOR
|
||||
* @{
|
||||
*/
|
||||
#define OB_SDACD_VDD_MONITOR_RESET ((uint8_t)0x00) /*!< SDADC VDD Monitor reset */
|
||||
#define OB_SDACD_VDD_MONITOR_SET ((uint8_t)0x80) /*!< SDADC VDD Monitor set */
|
||||
|
||||
#define IS_OB_SDACD_VDD_MONITOR(VDD_MONITOR) (((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_SET) || \
|
||||
((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_RESET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F373xC || STM32F378xx */
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_FLASH_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,536 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief GPIO HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
|
||||
* + Initialization/de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### GPIO specific features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
Each port bit of the general-purpose I/O (GPIO) ports can be individually
|
||||
configured by software in several modes:
|
||||
(+) Input mode
|
||||
(+) Analog mode
|
||||
(+) Output mode
|
||||
(+) Alternate function mode
|
||||
(+) External interrupt/event lines
|
||||
|
||||
[..]
|
||||
During and just after reset, the alternate functions and external interrupt
|
||||
lines are not active and the I/O ports are configured in input floating mode.
|
||||
|
||||
[..]
|
||||
All GPIO pins have weak internal pull-up and pull-down resistors, which can be
|
||||
activated or not.
|
||||
|
||||
[..]
|
||||
In Output or Alternate mode, each IO can be configured on open-drain or push-pull
|
||||
type and the IO speed can be selected depending on the VDD value.
|
||||
|
||||
[..]
|
||||
The microcontroller IO pins are connected to onboard peripherals/modules through a
|
||||
multiplexer that allows only one peripheral’s alternate function (AF) connected
|
||||
to an IO pin at a time. In this way, there can be no conflict between peripherals
|
||||
sharing the same IO pin.
|
||||
|
||||
[..]
|
||||
All ports have external interrupt/event capability. To use external interrupt
|
||||
lines, the port must be configured in input mode. All available GPIO pins are
|
||||
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
|
||||
|
||||
[..]
|
||||
The external interrupt/event controller consists of up to 23 edge detectors
|
||||
(16 lines are connected to GPIO) for generating event/interrupt requests (each
|
||||
input line can be independently configured to select the type (interrupt or event)
|
||||
and the corresponding trigger event (rising or falling or both). Each line can
|
||||
also be masked independently.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable the GPIO AHB clock using the following function : __GPIOx_CLK_ENABLE().
|
||||
|
||||
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
|
||||
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
|
||||
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
|
||||
structure.
|
||||
(++) In case of Output or alternate function mode selection: the speed is
|
||||
configured through "Speed" member from GPIO_InitTypeDef structure,
|
||||
the speed is configurable: 2 MHz, 10 MHz and 50 MHz.
|
||||
(++) If alternate mode is selected, the alternate function connected to the IO
|
||||
is configured through "Alternate" member from GPIO_InitTypeDef structure
|
||||
(++) Analog mode is required when a pin is to be used as ADC channel
|
||||
or DAC output.
|
||||
(++) In case of external interrupt/event selection the "Mode" member from
|
||||
GPIO_InitTypeDef structure select the type (interrupt or event) and
|
||||
the corresponding trigger event (rising or falling or both).
|
||||
|
||||
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
|
||||
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
|
||||
HAL_NVIC_EnableIRQ().
|
||||
|
||||
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
|
||||
|
||||
(#) To set/reset the level of a pin configured in output mode use
|
||||
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
|
||||
|
||||
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
|
||||
|
||||
(#) During and just after reset, the alternate functions are not
|
||||
active and the GPIO pins are configured in input floating mode (except JTAG
|
||||
pins).
|
||||
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
|
||||
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
|
||||
priority over the GPIO function.
|
||||
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
|
||||
general purpose Px0 and Px1, respectively, when the HSE oscillator is off.
|
||||
The HSE has priority over the GPIO function.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO GPIO
|
||||
* @brief GPIO HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
#define GET_GPIO_SOURCE(__GPIOx__) \
|
||||
(((uint32_t)(__GPIOx__) == ((uint32_t)GPIOA_BASE))? 0U :\
|
||||
((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0400)))? 1U :\
|
||||
((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0800)))? 2U :\
|
||||
((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0C00)))? 3U :\
|
||||
((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1000)))? 4U :\
|
||||
((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1400)))? 5U : 6U)
|
||||
|
||||
#define GPIO_MODE ((uint32_t)0x00000003)
|
||||
#define EXTI_MODE ((uint32_t)0x10000000)
|
||||
#define GPIO_MODE_IT ((uint32_t)0x00010000)
|
||||
#define GPIO_MODE_EVT ((uint32_t)0x00020000)
|
||||
#define RISING_EDGE ((uint32_t)0x00100000)
|
||||
#define FALLING_EDGE ((uint32_t)0x00200000)
|
||||
#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
|
||||
|
||||
#define GPIO_NUMBER ((uint32_t)16)
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_GPIO_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
|
||||
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices
|
||||
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
|
||||
* the configuration information for the specified GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||
{
|
||||
uint32_t position;
|
||||
uint32_t ioposition = 0x00;
|
||||
uint32_t iocurrent = 0x00;
|
||||
uint32_t temp = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
||||
|
||||
/* Configure the port pins */
|
||||
for (position = 0; position < GPIO_NUMBER; position++)
|
||||
{
|
||||
/* Get the IO position */
|
||||
ioposition = ((uint32_t)0x01) << position;
|
||||
/* Get the current IO position */
|
||||
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
||||
|
||||
if (iocurrent == ioposition)
|
||||
{
|
||||
/*--------------------- GPIO Mode Configuration ------------------------*/
|
||||
/* In case of Alternate function mode selection */
|
||||
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
{
|
||||
/* Check the Alternate function parameter */
|
||||
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
||||
/* Configure Alternate function mapped with the current IO */
|
||||
temp = GPIOx->AFR[position >> 3];
|
||||
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
|
||||
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
|
||||
GPIOx->AFR[position >> 3] = temp;
|
||||
}
|
||||
|
||||
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
||||
temp = GPIOx->MODER;
|
||||
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
|
||||
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
|
||||
GPIOx->MODER = temp;
|
||||
|
||||
/* In case of Output or Alternate function mode selection */
|
||||
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
||||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
{
|
||||
/* Check the Speed parameter */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
||||
/* Configure the IO Speed */
|
||||
temp = GPIOx->OSPEEDR;
|
||||
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
|
||||
temp |= (GPIO_Init->Speed << (position * 2));
|
||||
GPIOx->OSPEEDR = temp;
|
||||
|
||||
/* Configure the IO Output Type */
|
||||
temp = GPIOx->OTYPER;
|
||||
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
||||
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
|
||||
GPIOx->OTYPER = temp;
|
||||
}
|
||||
|
||||
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||||
temp = GPIOx->PUPDR;
|
||||
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
|
||||
temp |= ((GPIO_Init->Pull) << (position * 2));
|
||||
GPIOx->PUPDR = temp;
|
||||
|
||||
/*--------------------- EXTI Mode Configuration ------------------------*/
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
||||
{
|
||||
/* Enable SYSCFG Clock */
|
||||
__SYSCFG_CLK_ENABLE();
|
||||
|
||||
temp = SYSCFG->EXTICR[position >> 2];
|
||||
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
|
||||
temp |= ((uint32_t)(GET_GPIO_SOURCE(GPIOx)) << (4 * (position & 0x03)));
|
||||
SYSCFG->EXTICR[position >> 2] = temp;
|
||||
|
||||
/* Clear EXTI line configuration */
|
||||
temp = EXTI->IMR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->IMR = temp;
|
||||
|
||||
temp = EXTI->EMR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->EMR = temp;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
temp = EXTI->RTSR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->RTSR = temp;
|
||||
|
||||
temp = EXTI->FTSR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->FTSR = temp;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief De-initializes the GPIOx peripheral registers to their default reset values.
|
||||
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F30X device or STM32F37X device
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||
{
|
||||
uint32_t position;
|
||||
uint32_t ioposition = 0x00;
|
||||
uint32_t iocurrent = 0x00;
|
||||
uint32_t tmp = 0x00;
|
||||
|
||||
/* Configure the port pins */
|
||||
for (position = 0; position < GPIO_NUMBER; position++)
|
||||
{
|
||||
/* Get the IO position */
|
||||
ioposition = ((uint32_t)0x01) << position;
|
||||
/* Get the current IO position */
|
||||
iocurrent = (GPIO_Pin) & ioposition;
|
||||
|
||||
if (iocurrent == ioposition)
|
||||
{
|
||||
/*------------------------- GPIO Mode Configuration --------------------*/
|
||||
/* Configure IO Direction in Input Floting Mode */
|
||||
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
|
||||
|
||||
/* Configure the default Alternate Function in current IO */
|
||||
GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
|
||||
|
||||
/* Configure the default value for IO Speed */
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
|
||||
|
||||
/* Configure the default value IO Output Type */
|
||||
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
|
||||
|
||||
/* Deactivate the Pull-up oand Pull-down resistor for the current IO */
|
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
|
||||
|
||||
|
||||
/*------------------------- EXTI Mode Configuration --------------------*/
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
|
||||
SYSCFG->EXTICR[position >> 2] &= ~tmp;
|
||||
|
||||
/* Clear EXTI line configuration */
|
||||
EXTI->IMR &= ~((uint32_t)iocurrent);
|
||||
EXTI->EMR &= ~((uint32_t)iocurrent);
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->RTSR &= ~((uint32_t)iocurrent);
|
||||
EXTI->FTSR &= ~((uint32_t)iocurrent);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_GPIO_Group2 IO operation functions
|
||||
* @brief GPIO Read and Write
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
GPIO_PinState bitstatus;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
||||
{
|
||||
bitstatus = GPIO_PIN_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = GPIO_PIN_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
*
|
||||
* @note This function uses GPIOx_BSRR register to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
*
|
||||
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @param PinState: specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the GPIO_PinState enum values:
|
||||
* @arg GPIO_BIT_RESET: to clear the port pin
|
||||
* @arg GPIO_BIT_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
||||
|
||||
if (PinState != GPIO_PIN_RESET)
|
||||
{
|
||||
GPIOx->BSRRL = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BSRRH = GPIO_Pin ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles the specified GPIO pin
|
||||
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
|
||||
* @param GPIO_Pin: specifies the pins to be toggled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->ODR ^= GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
|
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
|
||||
* @note The configuration of the locked GPIO pins can no longer be modified
|
||||
* until the next reset.
|
||||
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
|
||||
* @param GPIO_Pin: specifies the port bit to be locked.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
__IO uint32_t tmp = GPIO_LCKR_LCKK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* Apply lock key write sequence */
|
||||
tmp |= GPIO_Pin;
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
|
||||
if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
|
||||
{
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles EXTI interrupt request.
|
||||
* @param GPIO_Pin: Specifies the pins connected EXTI line
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* EXTI line interrupt detected */
|
||||
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
|
||||
{
|
||||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
||||
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI line detection callbacks.
|
||||
* @param GPIO_Pin: Specifies the pins connected EXTI line
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_GPIO_EXTI_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,272 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of GPIO HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_GPIO_H
|
||||
#define __STM32F3xx_HAL_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_mode_define */
|
||||
|
||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_pull_define */
|
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_speed_define */
|
||||
|
||||
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
|
||||
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PIN_RESET = 0,
|
||||
GPIO_PIN_SET
|
||||
}GPIO_PinState;
|
||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants GPIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define GPIO_pins_define
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
|
||||
|
||||
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
|
||||
|
||||
#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK) != (uint32_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_mode_define GPIO_mode_define
|
||||
* @brief GPIO Configuration Mode
|
||||
* Elements values convention: 0xX0yz00YZ
|
||||
* - X : GPIO mode or EXTI Mode
|
||||
* - y : External IT or Event trigger detection
|
||||
* - z : IO configuration on External IT or Event
|
||||
* - Y : Output type (Push Pull or Open Drain)
|
||||
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */
|
||||
|
||||
#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */
|
||||
|
||||
#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
|
||||
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
|
||||
((MODE) == GPIO_MODE_AF_PP) ||\
|
||||
((MODE) == GPIO_MODE_AF_OD) ||\
|
||||
((MODE) == GPIO_MODE_IT_RISING) ||\
|
||||
((MODE) == GPIO_MODE_IT_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_RISING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_ANALOG))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_speed_define GPIO_speed_define
|
||||
* @brief GPIO Output Maximum frequency
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_SPEED_LOW ((uint32_t)0x00000000) /*!< Low speed */
|
||||
#define GPIO_SPEED_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */
|
||||
#define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */
|
||||
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \
|
||||
((SPEED) == GPIO_SPEED_HIGH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pull_define GPIO_pull_define
|
||||
* @brief GPIO Pull-Up or Pull-Down Activation
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */
|
||||
#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */
|
||||
#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */
|
||||
|
||||
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
|
||||
((PULL) == GPIO_PULLDOWN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line flag to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt on selected EXTI line.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
|
||||
|
||||
/* Include GPIO HAL Extension module */
|
||||
#include "stm32f3xx_hal_gpio_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_GPIO_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,973 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_gpio_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of GPIO HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_GPIO_EX_H
|
||||
#define __STM32F3xx_HAL_GPIO_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIOEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIOEx_Exported_Constants GPIOEx_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_Alternate_function_selection GPIOEx_Alternate_function_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (STM32F302xC) || defined (STM32F303xC)
|
||||
/*------------------------- STM32F302xC/STM32F303xC---------------------------*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF3_COMP7 ((uint8_t)0x03) /* COMP7 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF5_I2S ((uint8_t)0x05) /* I2S Alternate Function mapping */
|
||||
#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
|
||||
#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
|
||||
#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext Alternate Function mapping */
|
||||
#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP3 ((uint8_t)0x07) /* COMP3 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
|
||||
#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM8 ((uint8_t)0xA) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0xC) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
|
||||
#define GPIO_AF14_USB ((uint8_t)0x0E) /* USB Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0E) || ((AF) == (uint8_t)0x0F))
|
||||
/*------------------------------------------------------------------------------------------*/
|
||||
#endif /* STM32F302xC || STM32F303xC */
|
||||
|
||||
#if defined (STM32F358xx)
|
||||
/*---------------------------------- STM32F358xx -------------------------------------------*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF3_COMP7 ((uint8_t)0x03) /* COMP7 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF5_I2S ((uint8_t)0x05) /* I2S Alternate Function mapping */
|
||||
#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
|
||||
#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
|
||||
#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext Alternate Function mapping */
|
||||
#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP3 ((uint8_t)0x07) /* COMP3 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
|
||||
#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM8 ((uint8_t)0xA) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0xC) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0F))
|
||||
/*------------------------------------------------------------------------------------------*/
|
||||
#endif /* STM32F358xx */
|
||||
|
||||
#if defined (STM32F373xC)
|
||||
/*---------------------------------- STM32F373xC--------------------------------*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM13 ((uint8_t)0x02) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM14 ((uint8_t)0x02) /* TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM19 ((uint8_t)0x02) /* TIM19 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
|
||||
#define GPIO_AF6_CEC ((uint8_t)0x06) /* CEC Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
|
||||
#define GPIO_AF7_CEC ((uint8_t)0x07) /* CEC Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM12 ((uint8_t)0xA) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_TIM19 ((uint8_t)0x0B) /* TIM19 Alternate Function mapping */
|
||||
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF14_USB ((uint8_t)0x0E) /* USB Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0B) || ((AF) == (uint8_t)0x0E) || ((AF) == (uint8_t)0x0F))
|
||||
/*------------------------------------------------------------------------------------------*/
|
||||
#endif /* STM32F373xC */
|
||||
|
||||
|
||||
#if defined (STM32F378xx)
|
||||
/*---------------------------------------- STM32F378xx--------------------------------------*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM13 ((uint8_t)0x02) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM14 ((uint8_t)0x02) /* TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM19 ((uint8_t)0x02) /* TIM19 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
|
||||
#define GPIO_AF6_CEC ((uint8_t)0x06) /* CEC Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
|
||||
#define GPIO_AF7_CEC ((uint8_t)0x07) /* CEC Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM12 ((uint8_t)0xA) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_TIM19 ((uint8_t)0x0B) /* TIM19 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0B) || ((AF) == (uint8_t)0x0F))
|
||||
/*------------------------------------------------------------------------------------------*/
|
||||
#endif /* STM32F378xx */
|
||||
|
||||
#if defined (STM32F303x8)
|
||||
/*---------------------------------- STM32F303x8--------------------------------*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07) /* GPCOMP6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08) /* GPCOMP2 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08) /* GPCOMP4 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08) /* GPCOMP6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF13_OPAMP2 ((uint8_t)0x0D) /* OPAMP2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0D) || ((AF) == (uint8_t)0x0F))
|
||||
/*------------------------------------------------------------------------------------------*/
|
||||
#endif /* STM32F303x8 */
|
||||
|
||||
#if defined (STM32F334x8) || defined (STM32F328xx)
|
||||
/*---------------------------------- STM32F334x8/STM32F328xx -------------------------------*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
|
||||
#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07) /* GPCOMP6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08) /* GPCOMP2 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08) /* GPCOMP4 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08) /* GPCOMP6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF12_HRTIM1 ((uint8_t)0x0C) /* HRTIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF13_OPAMP2 ((uint8_t)0x0D) /* OPAMP2 Alternate Function mapping */
|
||||
#define GPIO_AF13_HRTIM1 ((uint8_t)0x0D) /* HRTIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0D) || ((AF) == (uint8_t)0x0F))
|
||||
/*------------------------------------------------------------------------------------------*/
|
||||
#endif /* STM32F334x8 || STM32F328xx */
|
||||
|
||||
#if defined (STM32F301x8) || defined (STM32F318xx)
|
||||
/*---------------------------------- STM32F301x8 / STM32F318xx ------------------------------------------*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC Alternate Function mapping */
|
||||
#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07) /* GPCOMP6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08) /* GPCOMP2 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08) /* GPCOMP4 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08) /* GPCOMP6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0F))
|
||||
/*------------------------------------------------------------------------------------------*/
|
||||
#endif /* STM32F301x8 || STM32F318xx */
|
||||
|
||||
#if defined (STM32F302x8)
|
||||
/*---------------------------------- STM32F302x8------------------------------------------*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC Alternate Function mapping */
|
||||
#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07) /* GPCOMP6 Alternate Function mapping */
|
||||
#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08) /* GPCOMP2 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08) /* GPCOMP4 Alternate Function mapping */
|
||||
#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08) /* GPCOMP6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0F))
|
||||
/*------------------------------------------------------------------------------------------*/
|
||||
#endif /* STM32F302x8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_GPIO_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,494 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_I2C_H
|
||||
#define __STM32F3xx_HAL_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief I2C Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter calculated by referring to I2C initialization
|
||||
section in Reference manual */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_addressing_mode */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_dual_addressing_mode */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
|
||||
This parameter can be a value of @ref I2C_own_address2_masks. */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref I2C_general_call_addressing_mode. */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref I2C_nostretch_mode */
|
||||
|
||||
}I2C_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */
|
||||
HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */
|
||||
HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */
|
||||
HAL_I2C_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_MEM_BUSY_TX = 0x52, /*!< Memory Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_MEM_BUSY_RX = 0x62, /*!< Memory Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0x03, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
|
||||
|
||||
}HAL_I2C_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2C Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_ERROR_NONE = 0x00, /*!< No error */
|
||||
HAL_I2C_ERROR_BERR = 0x01, /*!< BERR error */
|
||||
HAL_I2C_ERROR_ARLO = 0x02, /*!< ARLO error */
|
||||
HAL_I2C_ERROR_AF = 0x04, /*!< AF error */
|
||||
HAL_I2C_ERROR_OVR = 0x08, /*!< OVR error */
|
||||
HAL_I2C_ERROR_DMA = 0x10, /*!< DMA transfer error */
|
||||
HAL_I2C_ERROR_TIMEOUT = 0x20, /*!< Timeout error */
|
||||
HAL_I2C_ERROR_SIZE = 0x40 /*!< Size Management error */
|
||||
}HAL_I2C_ErrorTypeDef;
|
||||
|
||||
/**
|
||||
* @brief I2C handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
||||
|
||||
I2C_InitTypeDef Init; /*!< I2C communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< I2C transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< I2C transfer counter */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
|
||||
__IO HAL_I2C_ErrorTypeDef ErrorCode; /* I2C Error code */
|
||||
|
||||
}I2C_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_addressing_mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
|
||||
#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
|
||||
|
||||
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == I2C_ADDRESSINGMODE_10BIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_dual_addressing_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_DUALADDRESS_DISABLED ((uint32_t)0x00000000)
|
||||
#define I2C_DUALADDRESS_ENABLED I2C_OAR2_OA2EN
|
||||
|
||||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \
|
||||
((ADDRESS) == I2C_DUALADDRESS_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_own_address2_masks
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_OA2_NOMASK ((uint8_t)0x00)
|
||||
#define I2C_OA2_MASK01 ((uint8_t)0x01)
|
||||
#define I2C_OA2_MASK02 ((uint8_t)0x02)
|
||||
#define I2C_OA2_MASK03 ((uint8_t)0x03)
|
||||
#define I2C_OA2_MASK04 ((uint8_t)0x04)
|
||||
#define I2C_OA2_MASK05 ((uint8_t)0x05)
|
||||
#define I2C_OA2_MASK06 ((uint8_t)0x06)
|
||||
#define I2C_OA2_MASK07 ((uint8_t)0x07)
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
|
||||
((MASK) == I2C_OA2_MASK01) || \
|
||||
((MASK) == I2C_OA2_MASK02) || \
|
||||
((MASK) == I2C_OA2_MASK03) || \
|
||||
((MASK) == I2C_OA2_MASK04) || \
|
||||
((MASK) == I2C_OA2_MASK05) || \
|
||||
((MASK) == I2C_OA2_MASK06) || \
|
||||
((MASK) == I2C_OA2_MASK07))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_general_call_addressing_mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_GENERALCALL_DISABLED ((uint32_t)0x00000000)
|
||||
#define I2C_GENERALCALL_ENABLED I2C_CR1_GCEN
|
||||
|
||||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \
|
||||
((CALL) == I2C_GENERALCALL_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_nostretch_mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NOSTRETCH_DISABLED ((uint32_t)0x00000000)
|
||||
#define I2C_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH
|
||||
|
||||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \
|
||||
((STRETCH) == I2C_NOSTRETCH_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Memory_Address_Size
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
|
||||
#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002)
|
||||
|
||||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
|
||||
((SIZE) == I2C_MEMADD_SIZE_16BIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_ReloadEndMode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
|
||||
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
|
||||
#define I2C_SOFTEND_MODE ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
|
||||
((MODE) == I2C_AUTOEND_MODE) || \
|
||||
((MODE) == I2C_SOFTEND_MODE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_StartStopMode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_NO_STARTSTOP ((uint32_t)0x00000000)
|
||||
#define I2C_GENERATE_STOP I2C_CR2_STOP
|
||||
#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define I2C_GENERATE_START_WRITE I2C_CR2_START
|
||||
|
||||
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
|
||||
((REQUEST) == I2C_GENERATE_START_READ) || \
|
||||
((REQUEST) == I2C_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == I2C_NO_STARTSTOP))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Interrupt_configuration_definition
|
||||
* @brief I2C Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define I2C_IT_ERRI I2C_CR1_ERRIE
|
||||
#define I2C_IT_TCI I2C_CR1_TCIE
|
||||
#define I2C_IT_STOPI I2C_CR1_STOPIE
|
||||
#define I2C_IT_NACKI I2C_CR1_NACKIE
|
||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define I2C_IT_RXI I2C_CR1_RXIE
|
||||
#define I2C_IT_TXI I2C_CR1_TXIE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2C_Flag_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_TXE I2C_ISR_TXE
|
||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define I2C_FLAG_AF I2C_ISR_NACKF
|
||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define I2C_FLAG_TC I2C_ISR_TC
|
||||
#define I2C_FLAG_TCR I2C_ISR_TCR
|
||||
#define I2C_FLAG_BERR I2C_ISR_BERR
|
||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define I2C_FLAG_OVR I2C_ISR_OVR
|
||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY
|
||||
#define I2C_FLAG_DIR I2C_ISR_DIR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset I2C handle state
|
||||
* @param __HANDLE__: I2C handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
|
||||
|
||||
/** @brief Enables or disables the specified I2C interrupts.
|
||||
* @param __HANDLE__: specifies the I2C Handle.
|
||||
* This parameter can be I2Cx where x: 1, 2, or 3 to select the I2C peripheral.
|
||||
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2C_IT_ERRI: Errors interrupt enable
|
||||
* @arg I2C_IT_TCI: Transfer complete interrupt enable
|
||||
* @arg I2C_IT_STOPI: STOP detection interrupt enable
|
||||
* @arg I2C_IT_NACKI: NACK received interrupt enable
|
||||
* @arg I2C_IT_ADDRI: Address match interrupt enable
|
||||
* @arg I2C_IT_RXI: RX interrupt enable
|
||||
* @arg I2C_IT_TXI: TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
|
||||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: specifies the I2C Handle.
|
||||
* This parameter can be I2Cx where x: 1, 2, or 3 to select the I2C peripheral.
|
||||
* @param __INTERRUPT__: specifies the I2C interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2C_IT_ERRI: Errors interrupt enable
|
||||
* @arg I2C_IT_TCI: Transfer complete interrupt enable
|
||||
* @arg I2C_IT_STOPI: STOP detection interrupt enable
|
||||
* @arg I2C_IT_NACKI: NACK received interrupt enable
|
||||
* @arg I2C_IT_ADDRI: Address match interrupt enable
|
||||
* @arg I2C_IT_RXI: RX interrupt enable
|
||||
* @arg I2C_IT_TXI: TX interrupt enable
|
||||
*
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified I2C flag is set or not.
|
||||
* @param __HANDLE__: specifies the I2C Handle.
|
||||
* This parameter can be I2Cx where x: 1, 2, or 3 to select the I2C peripheral.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2C_FLAG_TXE: Transmit data register empty
|
||||
* @arg I2C_FLAG_TXIS: Transmit interrupt status
|
||||
* @arg I2C_FLAG_RXNE: Receive data register not empty
|
||||
* @arg I2C_FLAG_ADDR: Address matched (slave mode)
|
||||
* @arg I2C_FLAG_AF: Acknowledge failure received flag
|
||||
* @arg I2C_FLAG_STOPF: STOP detection flag
|
||||
* @arg I2C_FLAG_TC: Transfer complete (master mode)
|
||||
* @arg I2C_FLAG_TCR: Transfer complete reload
|
||||
* @arg I2C_FLAG_BERR: Bus error
|
||||
* @arg I2C_FLAG_ARLO: Arbitration lost
|
||||
* @arg I2C_FLAG_OVR: Overrun/Underrun
|
||||
* @arg I2C_FLAG_PECERR: PEC error in reception
|
||||
* @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
|
||||
* @arg I2C_FLAG_ALERT: SMBus alert
|
||||
* @arg I2C_FLAG_BUSY: Bus busy
|
||||
* @arg I2C_FLAG_DIR: Transfer direction (slave mode)
|
||||
*
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clears the I2C pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__: specifies the I2C Handle.
|
||||
* This parameter can be I2Cx where x: 1, 2, or 3 to select the I2C peripheral.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg I2C_FLAG_ADDR: Address matched (slave mode)
|
||||
* @arg I2C_FLAG_AF: Acknowledge failure flag
|
||||
* @arg I2C_FLAG_STOPF: STOP detection flag
|
||||
* @arg I2C_FLAG_BERR: Bus error
|
||||
* @arg I2C_FLAG_ARLO: Arbitration lost
|
||||
* @arg I2C_FLAG_OVR: Overrun/Underrun
|
||||
* @arg I2C_FLAG_PECERR: PEC error in reception
|
||||
* @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
|
||||
* @arg I2C_FLAG_ALERT: SMBus alert
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
|
||||
#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
|
||||
#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
|
||||
|
||||
#define __HAL_I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
|
||||
|
||||
#define __HAL_I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
|
||||
#define __HAL_I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
|
||||
|
||||
#define __HAL_I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
|
||||
|
||||
/* Include I2C HAL Extension module */
|
||||
#include "stm32f3xx_hal_i2c_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
/******* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* Peripheral State functions **************************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F3xx_HAL_I2C_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,292 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_i2c_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief I2C Extension HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of I2C extension peripheral:
|
||||
* + Extension features functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### I2C peripheral extension features #####
|
||||
==============================================================================
|
||||
|
||||
[..] Comparing to other previous devices, the I2C interface for STM32F3XX
|
||||
devices contains the following additional features
|
||||
|
||||
(+) Possibility to disable or enable Analog Noise Filter
|
||||
(+) Use of a configured Digital Noise Filter
|
||||
(+) Disable or enable wakeup from Stop mode
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] This driver provides functions to configure Noise Filter
|
||||
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_AnalogFilter_Config()
|
||||
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_DigitalFilter_Config()
|
||||
(#) Configure the enabling or disabling of I2C Wake Up Mode using the functions :
|
||||
+ HAL_I2CEx_EnableWakeUp()
|
||||
+ HAL_I2CEx_DisableWakeUp()
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx
|
||||
* @brief I2C Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2CEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2CEx_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extension features functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Noise Filters
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures I2C Analog noise filter.
|
||||
* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @param AnalogFilter : new state of the Analog filter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
||||
|
||||
if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
|
||||
|| (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Reset I2Cx ANOFF bit */
|
||||
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
|
||||
|
||||
/* Set analog filter bit*/
|
||||
hi2c->Instance->CR1 |= AnalogFilter;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures I2C Digital noise filter.
|
||||
* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @param DigitalFilter : Coefficient of digital noise filter between 0x00 and 0x0F.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
||||
|
||||
if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
|
||||
|| (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Get the old register value */
|
||||
tmpreg = hi2c->Instance->CR1;
|
||||
|
||||
/* Reset I2Cx DNF bits [11:8] */
|
||||
tmpreg &= ~(I2C_CR1_DFN);
|
||||
|
||||
/* Set I2Cx DNF coefficient */
|
||||
tmpreg |= DigitalFilter << 8;
|
||||
|
||||
/* Store the new register value */
|
||||
hi2c->Instance->CR1 = tmpreg;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables I2C wakeup from stop mode.
|
||||
* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
|
||||
if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
|
||||
|| (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Enable wakeup from stop mode */
|
||||
hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disables I2C wakeup from stop mode.
|
||||
* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
|
||||
if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
|
||||
|| (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Enable wakeup from stop mode */
|
||||
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,112 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_i2c_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of I2C HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_I2C_EX_H
|
||||
#define __STM32F3xx_HAL_I2C_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Analog_Filter
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ANALOGFILTER_ENABLED ((uint32_t)0x00000000)
|
||||
#define I2C_ANALOGFILTER_DISABLED I2C_CR1_ANFOFF
|
||||
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLED) || \
|
||||
((FILTER) == I2C_ANALOGFILTER_DISABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Digital_Filter
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_I2C_EX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,440 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_i2s.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of I2S HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_I2S_H
|
||||
#define __STM32F3xx_HAL_I2S_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F301x8) || \
|
||||
defined(STM32F302x8) || defined(STM32F302xC) || \
|
||||
defined(STM32F303xC) || defined(STM32F373xC) || \
|
||||
defined(STM32F318xx) || \
|
||||
defined(STM32F358xx) || defined(STM32F378xx)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref I2S_Mode */
|
||||
|
||||
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Standard */
|
||||
|
||||
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Data_Format */
|
||||
|
||||
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||
|
||||
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||
|
||||
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||
|
||||
uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
|
||||
This parameter can be a value of @ref I2S_Clock_Source */
|
||||
|
||||
uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode.
|
||||
This parameter can be a value of @ref I2S_FullDuplex_Mode */
|
||||
|
||||
}I2S_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */
|
||||
HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */
|
||||
HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */
|
||||
HAL_I2S_STATE_TIMEOUT = 0x06, /*!< I2S timeout state */
|
||||
HAL_I2S_STATE_ERROR = 0x07 /*!< I2S error state */
|
||||
|
||||
}HAL_I2S_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2S Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2S_ERROR_NONE = 0x00, /*!< No error */
|
||||
HAL_I2S_ERROR_TIMEOUT = 0x01, /*!< Timeout error */
|
||||
HAL_I2S_ERROR_OVR = 0x02, /*!< OVR error */
|
||||
HAL_I2S_ERROR_UDR = 0x04, /*!< UDR error */
|
||||
HAL_I2S_ERROR_DMA = 0x08, /*!< DMA transfer error */
|
||||
HAL_I2S_ERROR_UNKNOW = 0x10 /*!< Unknow Error error */
|
||||
}HAL_I2S_ErrorTypeDef;
|
||||
|
||||
/**
|
||||
* @brief I2S handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
SPI_TypeDef *Instance; /* I2S registers base address */
|
||||
|
||||
I2S_InitTypeDef Init; /* I2S communication parameters */
|
||||
|
||||
uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
|
||||
|
||||
__IO uint16_t TxXferSize; /* I2S Tx transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
|
||||
|
||||
uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
|
||||
|
||||
__IO uint16_t RxXferSize; /* I2S Rx transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /* I2S Rx transfer counter
|
||||
(This field is initialized at the
|
||||
same value as transfer size at the
|
||||
beginning of the transfer and
|
||||
decremented when a sample is received.
|
||||
NbSamplesReceived = RxBufferSize-RxBufferCount) */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
|
||||
|
||||
__IO HAL_LockTypeDef Lock; /* I2S locking object */
|
||||
|
||||
__IO HAL_I2S_StateTypeDef State; /* I2S communication state */
|
||||
|
||||
__IO HAL_I2S_ErrorTypeDef ErrorCode; /* I2S Error code */
|
||||
|
||||
}I2S_HandleTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2S_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)
|
||||
#define I2S_CLOCK_SYSCLK ((uint32_t)0x00000002)
|
||||
|
||||
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
|
||||
((CLOCK) == I2S_CLOCK_SYSCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
|
||||
#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
|
||||
#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
|
||||
#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)
|
||||
|
||||
#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
|
||||
((MODE) == I2S_MODE_SLAVE_RX) || \
|
||||
((MODE) == I2S_MODE_MASTER_TX)|| \
|
||||
((MODE) == I2S_MODE_MASTER_RX))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Standard
|
||||
* @{
|
||||
*/
|
||||
#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
|
||||
#define I2S_STANDARD_MSB ((uint32_t)0x00000010)
|
||||
#define I2S_STANDARD_LSB ((uint32_t)0x00000020)
|
||||
#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)
|
||||
#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)
|
||||
|
||||
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
|
||||
((STANDARD) == I2S_STANDARD_MSB) || \
|
||||
((STANDARD) == I2S_STANDARD_LSB) || \
|
||||
((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
|
||||
((STANDARD) == I2S_STANDARD_PCM_LONG))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Data_Format
|
||||
* @{
|
||||
*/
|
||||
#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
|
||||
#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)
|
||||
#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003)
|
||||
#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005)
|
||||
|
||||
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
|
||||
((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
|
||||
((FORMAT) == I2S_DATAFORMAT_24B) || \
|
||||
((FORMAT) == I2S_DATAFORMAT_32B))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_MCLK_Output
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
|
||||
#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
|
||||
((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Audio_Frequency
|
||||
* @{
|
||||
*/
|
||||
#define I2S_AUDIOFREQ_192K ((uint32_t)192000)
|
||||
#define I2S_AUDIOFREQ_96K ((uint32_t)96000)
|
||||
#define I2S_AUDIOFREQ_48K ((uint32_t)48000)
|
||||
#define I2S_AUDIOFREQ_44K ((uint32_t)44100)
|
||||
#define I2S_AUDIOFREQ_32K ((uint32_t)32000)
|
||||
#define I2S_AUDIOFREQ_22K ((uint32_t)22050)
|
||||
#define I2S_AUDIOFREQ_16K ((uint32_t)16000)
|
||||
#define I2S_AUDIOFREQ_11K ((uint32_t)11025)
|
||||
#define I2S_AUDIOFREQ_8K ((uint32_t)8000)
|
||||
#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
|
||||
((FREQ) <= I2S_AUDIOFREQ_192K)) || \
|
||||
((FREQ) == I2S_AUDIOFREQ_DEFAULT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_FullDuplex_Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2S_FULLDUPLEXMODE_DISABLE ((uint32_t)0x00000000)
|
||||
#define I2S_FULLDUPLEXMODE_ENABLE ((uint32_t)0x00000001)
|
||||
|
||||
#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
|
||||
((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
#define I2S_CPOL_LOW ((uint32_t)0x00000000)
|
||||
#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
|
||||
|
||||
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
|
||||
((CPOL) == I2S_CPOL_HIGH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Interrupt_configuration_definition
|
||||
* @{
|
||||
*/
|
||||
#define I2S_IT_TXE SPI_CR2_TXEIE
|
||||
#define I2S_IT_RXNE SPI_CR2_RXNEIE
|
||||
#define I2S_IT_ERR SPI_CR2_ERRIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Flag_definition
|
||||
* @{
|
||||
*/
|
||||
#define I2S_FLAG_TXE SPI_SR_TXE
|
||||
#define I2S_FLAG_RXNE SPI_SR_RXNE
|
||||
|
||||
#define I2S_FLAG_UDR SPI_SR_UDR
|
||||
#define I2S_FLAG_OVR SPI_SR_OVR
|
||||
#define I2S_FLAG_FRE SPI_SR_FRE
|
||||
|
||||
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
|
||||
#define I2S_FLAG_BSY SPI_SR_BSY
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset I2S handle state
|
||||
* @param __HANDLE__: I2S handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
|
||||
|
||||
/** @brief Enable or disable the specified SPI peripheral (in I2S mode).
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
|
||||
#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
|
||||
|
||||
/** @brief Enable or disable the specified I2S interrupts.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
|
||||
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
|
||||
* @param __INTERRUPT__: specifies the I2S interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified I2S flag is set or not.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg I2S_FLAG_UDR: Underrun flag
|
||||
* @arg I2S_FLAG_OVR: Overrun flag
|
||||
* @arg I2S_FLAG_FRE: Frame error flag
|
||||
* @arg I2S_FLAG_CHSIDE: Channel Side flag
|
||||
* @arg I2S_FLAG_BSY: Busy flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clears the I2S OVR pending flag.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
|
||||
(__HANDLE__)->Instance->SR;}while(0)
|
||||
/** @brief Clears the I2S UDR pending flag.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
|
||||
|
||||
/* Include I2S HAL Extension module */
|
||||
#include "stm32f3xx_hal_i2s_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
|
||||
/* Peripheral Control and State functions ************************************/
|
||||
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
|
||||
HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
|
||||
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(STM32F301x8) || */
|
||||
/* defined(STM32F302x8) || defined(STM32F302xC) || */
|
||||
/* defined(STM32F303xC) || defined(STM32F373xC) || */
|
||||
/* defined(STM32F318xx) || */
|
||||
/* defined(STM32F358xx) || defined(STM32F378xx) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F3xx_HAL_I2S_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,171 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_i2s_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of I2S HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_I2S_EX_H
|
||||
#define __STM32F3xx_HAL_I2S_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F301x8) || \
|
||||
defined(STM32F302x8) || defined(STM32F302xC) || \
|
||||
defined(STM32F303xC) || defined(STM32F373xC) || \
|
||||
defined(STM32F318xx) || \
|
||||
defined(STM32F358xx) || defined(STM32F378xx)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2SEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F358xx)
|
||||
#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
|
||||
|
||||
/** @brief Enable or disable the specified I2SExt peripheral.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2SEXT_ENABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE)
|
||||
#define __HAL_I2SEXT_DISABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
|
||||
|
||||
/** @brief Enable or disable the specified I2SExt interrupts.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2SEXT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 |= (__INTERRUPT__))
|
||||
#define __HAL_I2SEXT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Checks if the specified I2SExt interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
|
||||
* @param __INTERRUPT__: specifies the I2S interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified I2SExt flag is set or not.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg I2S_FLAG_UDR: Underrun flag
|
||||
* @arg I2S_FLAG_OVR: Overrun flag
|
||||
* @arg I2S_FLAG_FRE: Frame error flag
|
||||
* @arg I2S_FLAG_CHSIDE: Channel Side flag
|
||||
* @arg I2S_FLAG_BSY: Busy flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2SEXT_GET_FLAG(__HANDLE__, __FLAG__) (((I2SxEXT((__HANDLE__)->Instance)->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clears the I2SExt OVR pending flag.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{(I2SxEXT((__HANDLE__)->Instance)->DR;\
|
||||
(I2SxEXT((__HANDLE__)->Instance)->SR;}while(0)
|
||||
/** @brief Clears the I2SExt UDR pending flag.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__)(I2SxEXT((__HANDLE__)->Instance)->SR)
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
|
||||
#if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F358xx)
|
||||
/* Extended features functions ************************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
|
||||
|
||||
/* I2S IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
|
||||
|
||||
/* Peripheral Control and State functions ************************************/
|
||||
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(STM32F301x8) || */
|
||||
/* defined(STM32F302x8) || defined(STM32F302xC) || */
|
||||
/* defined(STM32F303xC) || defined(STM32F373xC) || */
|
||||
/* defined(STM32F318xx) || */
|
||||
/* defined(STM32F358xx) || defined(STM32F378xx) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F3xx_HAL_I2S_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,590 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_irda.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of IRDA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_IRDA_H
|
||||
#define __STM32F3xx_HAL_IRDA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief IRDA Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
|
||||
The baud rate register is computed using the following formula:
|
||||
Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref IRDAEx_Word_Length */
|
||||
|
||||
uint16_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref IRDA_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref IRDA_Mode */
|
||||
|
||||
uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
|
||||
to achieve low-power frequency.
|
||||
@note Prescaler value 0 is forbidden */
|
||||
|
||||
uint16_t PowerMode; /*!< Specifies the IRDA power mode.
|
||||
This parameter can be a value of @ref IRDA_Low_Power */
|
||||
}IRDA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IRDA State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
|
||||
HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
|
||||
HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
|
||||
HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
|
||||
HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
|
||||
HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */
|
||||
HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */
|
||||
}HAL_IRDA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IRDA Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_IRDA_ERROR_NONE = 0x00, /*!< No error */
|
||||
HAL_IRDA_ERROR_PE = 0x01, /*!< Parity error */
|
||||
HAL_IRDA_ERROR_NE = 0x02, /*!< Noise error */
|
||||
HAL_IRDA_ERROR_FE = 0x04, /*!< frame error */
|
||||
HAL_IRDA_ERROR_ORE = 0x08, /*!< Overrun error */
|
||||
HAL_IRDA_ERROR_DMA = 0x10 /*!< DMA transfer error */
|
||||
}HAL_IRDA_ErrorTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA clock sources definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
IRDA_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
|
||||
IRDA_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */
|
||||
IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
|
||||
IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
|
||||
IRDA_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
|
||||
IRDA_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */
|
||||
}IRDA_ClockSourceTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
USART_TypeDef *Instance; /* USART registers base address */
|
||||
|
||||
IRDA_InitTypeDef Init; /* IRDA communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /* Pointer to IRDA Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /* IRDA Tx Transfer size */
|
||||
|
||||
uint16_t TxXferCount; /* IRDA Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /* Pointer to IRDA Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /* IRDA Rx Transfer size */
|
||||
|
||||
uint16_t RxXferCount; /* IRDA Rx Transfer Counter */
|
||||
|
||||
uint16_t Mask; /* USART RX RDR register mask */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /* IRDA Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /* Locking object */
|
||||
|
||||
HAL_IRDA_StateTypeDef State; /* IRDA communication state */
|
||||
|
||||
HAL_IRDA_ErrorTypeDef ErrorCode; /* IRDA Error code */
|
||||
|
||||
}IRDA_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA Configuration enumeration values definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
IRDA_BAUDRATE = 0x00,
|
||||
IRDA_PARITY = 0x01,
|
||||
IRDA_WORDLENGTH = 0x02,
|
||||
IRDA_MODE = 0x03,
|
||||
IRDA_PRESCALER = 0x04,
|
||||
IRDA_POWERMODE = 0x05
|
||||
}IRDA_ControlTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Parity IRDA Parity
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_PARITY_NONE ((uint16_t)0x0000)
|
||||
#define IRDA_PARITY_EVEN ((uint16_t)USART_CR1_PCE)
|
||||
#define IRDA_PARITY_ODD ((uint16_t)(USART_CR1_PCE | USART_CR1_PS))
|
||||
#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
|
||||
((PARITY) == IRDA_PARITY_EVEN) || \
|
||||
((PARITY) == IRDA_PARITY_ODD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_MODE_RX ((uint16_t)USART_CR1_RE)
|
||||
#define IRDA_MODE_TX ((uint16_t)USART_CR1_TE)
|
||||
#define IRDA_MODE_TX_RX ((uint16_t)(USART_CR1_TE |USART_CR1_RE))
|
||||
#define IS_IRDA_TX_RX_MODE(MODE) ((((MODE) & (~((uint16_t)(IRDA_MODE_TX_RX)))) == (uint16_t)0x00) && ((MODE) != (uint16_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Low_Power IRDA Low Power
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_POWERMODE_NORMAL ((uint16_t)0x0000)
|
||||
#define IRDA_POWERMODE_LOWPOWER ((uint16_t)USART_CR3_IRLP)
|
||||
#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
|
||||
((MODE) == IRDA_POWERMODE_NORMAL))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_State IRDA State
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_STATE_DISABLE ((uint16_t)0x0000)
|
||||
#define IRDA_STATE_ENABLE ((uint16_t)USART_CR1_UE)
|
||||
#define IS_IRDA_STATE(STATE) (((STATE) == IRDA_STATE_DISABLE) || \
|
||||
((STATE) == IRDA_STATE_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Mode IRDA Mode
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_MODE_DISABLE ((uint16_t)0x0000)
|
||||
#define IRDA_MODE_ENABLE ((uint16_t)USART_CR3_IREN)
|
||||
#define IS_IRDA_MODE(STATE) (((STATE) == IRDA_MODE_DISABLE) || \
|
||||
((STATE) == IRDA_MODE_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_ONE_BIT_SAMPLE_DISABLED ((uint16_t)0x00000000)
|
||||
#define IRDA_ONE_BIT_SAMPLE_ENABLED ((uint16_t)USART_CR3_ONEBIT)
|
||||
#define IS_IRDA_ONEBIT_SAMPLE(ONEBIT) (((ONEBIT) == IRDA_ONE_BIT_SAMPLE_DISABLED) || \
|
||||
((ONEBIT) == IRDA_ONE_BIT_SAMPLE_ENABLED))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_DMA_TX_DISABLE ((uint16_t)0x00000000)
|
||||
#define IRDA_DMA_TX_ENABLE ((uint16_t)USART_CR3_DMAT)
|
||||
#define IS_IRDA_DMA_TX(DMATX) (((DMATX) == IRDA_DMA_TX_DISABLE) || \
|
||||
((DMATX) == IRDA_DMA_TX_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_DMA_RX_DISABLE ((uint16_t)0x0000)
|
||||
#define IRDA_DMA_RX_ENABLE ((uint16_t)USART_CR3_DMAR)
|
||||
#define IS_IRDA_DMA_RX(DMARX) (((DMARX) == IRDA_DMA_RX_DISABLE) || \
|
||||
((DMARX) == IRDA_DMA_RX_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Flags IRDA Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the ISR register
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_FLAG_REACK ((uint32_t)0x00400000)
|
||||
#define IRDA_FLAG_TEACK ((uint32_t)0x00200000)
|
||||
#define IRDA_FLAG_BUSY ((uint32_t)0x00010000)
|
||||
#define IRDA_FLAG_ABRF ((uint32_t)0x00008000)
|
||||
#define IRDA_FLAG_ABRE ((uint32_t)0x00004000)
|
||||
#define IRDA_FLAG_TXE ((uint32_t)0x00000080)
|
||||
#define IRDA_FLAG_TC ((uint32_t)0x00000040)
|
||||
#define IRDA_FLAG_RXNE ((uint32_t)0x00000020)
|
||||
#define IRDA_FLAG_ORE ((uint32_t)0x00000008)
|
||||
#define IRDA_FLAG_NE ((uint32_t)0x00000004)
|
||||
#define IRDA_FLAG_FE ((uint32_t)0x00000002)
|
||||
#define IRDA_FLAG_PE ((uint32_t)0x00000001)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
|
||||
* Elements values convention: 0000ZZZZ0XXYYYYYb
|
||||
* - YYYYY : Interrupt source position in the XX register (5bits)
|
||||
* - XX : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
* - ZZZZ : Flag position in the ISR register(4bits)
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_IT_PE ((uint16_t)0x0028)
|
||||
#define IRDA_IT_TXE ((uint16_t)0x0727)
|
||||
#define IRDA_IT_TC ((uint16_t)0x0626)
|
||||
#define IRDA_IT_RXNE ((uint16_t)0x0525)
|
||||
#define IRDA_IT_IDLE ((uint16_t)0x0424)
|
||||
|
||||
|
||||
|
||||
/** Elements values convention: 000000000XXYYYYYb
|
||||
* - YYYYY : Interrupt source position in the XX register (5bits)
|
||||
* - XX : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
*/
|
||||
#define IRDA_IT_ERR ((uint16_t)0x0060)
|
||||
|
||||
/** Elements values convention: 0000ZZZZ00000000b
|
||||
* - ZZZZ : Flag position in the ISR register(4bits)
|
||||
*/
|
||||
#define IRDA_IT_ORE ((uint16_t)0x0300)
|
||||
#define IRDA_IT_NE ((uint16_t)0x0200)
|
||||
#define IRDA_IT_FE ((uint16_t)0x0100)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
|
||||
#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
|
||||
#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
|
||||
#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
|
||||
#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
|
||||
#define IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
|
||||
#define IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
|
||||
#define IS_IRDA_REQUEST_PARAMETER(PARAM) (((PARAM) == IRDA_AUTOBAUD_REQUEST) || \
|
||||
((PARAM) == IRDA_SENDBREAK_REQUEST) || \
|
||||
((PARAM) == IRDA_MUTE_MODE_REQUEST) || \
|
||||
((PARAM) == IRDA_RXDATA_FLUSH_REQUEST) || \
|
||||
((PARAM) == IRDA_TXDATA_FLUSH_REQUEST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Interruption_Mask IRDA interruptions flag mask
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_IT_MASK ((uint16_t)0x001F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset IRDA handle state
|
||||
* @param __HANDLE__: IRDA handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
|
||||
|
||||
/** @brief Checks whether the specified IRDA flag is set or not.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
|
||||
* UART peripheral
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_FLAG_REACK: Receive enable ackowledge flag
|
||||
* @arg IRDA_FLAG_TEACK: Transmit enable ackowledge flag
|
||||
* @arg IRDA_FLAG_BUSY: Busy flag
|
||||
* @arg IRDA_FLAG_ABRF: Auto Baud rate detection flag
|
||||
* @arg IRDA_FLAG_ABRE: Auto Baud rate detection error flag
|
||||
* @arg IRDA_FLAG_TXE: Transmit data register empty flag
|
||||
* @arg IRDA_FLAG_TC: Transmission Complete flag
|
||||
* @arg IRDA_FLAG_RXNE: Receive data register not empty flag
|
||||
* @arg IRDA_FLAG_IDLE: Idle Line detection flag
|
||||
* @arg IRDA_FLAG_ORE: OverRun Error flag
|
||||
* @arg IRDA_FLAG_NE: Noise Error flag
|
||||
* @arg IRDA_FLAG_FE: Framing Error flag
|
||||
* @arg IRDA_FLAG_PE: Parity Error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Enables the specified IRDA interrupt.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
|
||||
* UART peripheral
|
||||
* @param __INTERRUPT__: specifies the IRDA interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
/** @brief Disables the specified IRDA interrupt.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
|
||||
* UART peripheral
|
||||
* @param __INTERRUPT__: specifies the IRDA interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
|
||||
/** @brief Checks whether the specified IRDA interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
|
||||
* UART peripheral
|
||||
* @param __IT__: specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||
* @arg IRDA_IT_ORE: OverRun Error interrupt
|
||||
* @arg IRDA_IT_NE: Noise Error interrupt
|
||||
* @arg IRDA_IT_FE: Framing Error interrupt
|
||||
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))
|
||||
|
||||
/** @brief Checks whether the specified IRDA interrupt source is enabled.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
|
||||
* UART peripheral
|
||||
* @param __IT__: specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||
* @arg IRDA_IT_ORE: OverRun Error interrupt
|
||||
* @arg IRDA_IT_NE: Noise Error interrupt
|
||||
* @arg IRDA_IT_FE: Framing Error interrupt
|
||||
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
|
||||
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
|
||||
|
||||
|
||||
/** @brief Clears the specified IRDA ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
|
||||
* UART peripheral
|
||||
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
|
||||
* to clear the corresponding interrupt
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_CLEAR_PEF: Parity Error Clear Flag
|
||||
* @arg IRDA_CLEAR_FEF: Framing Error Clear Flag
|
||||
* @arg IRDA_CLEAR_NEF: Noise detected Clear Flag
|
||||
* @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag
|
||||
* @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
|
||||
|
||||
|
||||
/** @brief Set a specific IRDA request flag.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
|
||||
* UART peripheral
|
||||
* @param __REQ__: specifies the request flag to set
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request
|
||||
* @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request
|
||||
* @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
|
||||
|
||||
|
||||
|
||||
/** @brief Enable UART/USART associated to IRDA Handle
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
|
||||
* UART peripheral
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
||||
|
||||
/** @brief Disable UART/USART associated to IRDA Handle
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
|
||||
* UART peripheral
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
||||
|
||||
/** @brief Ensure that IRDA Baud rate is less or equal to maximum value
|
||||
* @param __BAUDRATE__: specifies the IRDA Baudrate set by the user.
|
||||
* @retval True or False
|
||||
*/
|
||||
#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
|
||||
|
||||
/** @brief Ensure that IRDA prescaler value is strictly larger than 0
|
||||
* @param __PRESCALER__: specifies the IRDA prescaler value set by the user.
|
||||
* @retval True or False
|
||||
*/
|
||||
#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include IRDA HAL Extension module */
|
||||
#include "stm32f3xx_hal_irda_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
|
||||
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_IRDA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,410 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f3xx_hal_irda_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief Header file of IRDA HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F3xx_HAL_IRDA_EX_H
|
||||
#define __STM32F3xx_HAL_IRDA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f3xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F3xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDAEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IRDAEx_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDAEx_Word_Length IRDA Word Length
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F301x8) || defined (STM32F302x8) || defined (STM32F334x8) \
|
||||
|| defined (STM32F318xx)
|
||||
#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
|
||||
#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
|
||||
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
|
||||
#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_7B) || \
|
||||
((LENGTH) == IRDA_WORDLENGTH_8B) || \
|
||||
((LENGTH) == IRDA_WORDLENGTH_9B))
|
||||
#else
|
||||
#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
|
||||
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
|
||||
#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
|
||||
((LENGTH) == IRDA_WORDLENGTH_9B))
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IRDAEx_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reports the IRDA clock source.
|
||||
* @param __HANDLE__: specifies the IRDA Handle
|
||||
* @param __CLOCKSOURCE__ : output variable
|
||||
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F303xE) \
|
||||
|| defined(STM32F318xC) || defined(STM32F358xx)
|
||||
#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART4) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART4_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART4CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Instance == UART5) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART5_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART5CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined(STM32F334x8) || defined(STM32F303x8) || defined(STM32F328xx)
|
||||
#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
#endif /* defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F318xC) || defined(STM32F358xx) */
|
||||
|
||||
|
||||
/** @brief Computes the mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
* @param __HANDLE__: specifies the IRDA Handle
|
||||
* @retval none
|
||||
*/
|
||||
#if defined (STM32F301x8) || defined (STM32F302x8) || defined (STM32F334x8) \
|
||||
|| defined (STM32F318xx)
|
||||
#define __HAL_IRDA_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007F ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007F ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x003F ; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_IRDA_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007F ; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
#endif /* defined (STM32F301x8) || defined (STM32F302x8) || defined (STM32F334x8)
|
||||
|| defined (STM32F318xx) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
/* IO operation functions *****************************************************/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F3xx_HAL_IRDA_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue