diff --git a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32_WPAN/stm32_wpan_common.h b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32_WPAN/stm32_wpan_common.h
index bc524efcd5..aabac95d69 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32_WPAN/stm32_wpan_common.h
+++ b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32_WPAN/stm32_wpan_common.h
@@ -26,20 +26,6 @@
 extern "C" {
 #endif
 
-#if   defined ( __CC_ARM )
- #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
- #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
- #define __STATIC_INLINE  static __inline
-#elif defined ( __ICCARM__ )
- #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
- #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE  static inline
-#elif defined ( __GNUC__ )
- #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
- #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
- #define __STATIC_INLINE  static inline
-#endif
-
 #include <stdint.h>
 #include <string.h>
 #include <stdio.h>
diff --git a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/system_stm32wbxx.c b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/system_stm32wbxx.c
index caf5651706..d4653a0ced 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/system_stm32wbxx.c
+++ b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/system_stm32wbxx.c
@@ -1,295 +1,278 @@
 /**
- ******************************************************************************
- * @file    system_stm32wbxx.c
- * @author  MCD Application Team
- * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
- *
- *   This file provides two functions and one global variable to be called from
- *   user application:
- *      - SystemInit(): This function is called at startup just after reset and
- *                      before branch to main program. This call is made inside
- *                      the "startup_stm32wbxx.s" file.
- *
- *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- *                                  by the user application to setup the SysTick
- *                                  timer or configure other parameters.
- *
- *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- *                                 be called whenever the core clock is changed
- *                                 during program execution.
- *
- *   After each device reset the MSI (4 MHz) is used as system clock source.
- *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
- *   configure the system clock before to branch to main program.
- *
- *   This file configures the system clock as follows:
- *=============================================================================
- *-----------------------------------------------------------------------------
- *        System Clock source                    | MSI
- *-----------------------------------------------------------------------------
- *        SYSCLK(Hz)                             | 4000000
- *-----------------------------------------------------------------------------
- *        HCLK(Hz)                               | 4000000
- *-----------------------------------------------------------------------------
- *        AHB Prescaler                          | 1
- *-----------------------------------------------------------------------------
- *        APB1 Prescaler                         | 1
- *-----------------------------------------------------------------------------
- *        APB2 Prescaler                         | 1
- *-----------------------------------------------------------------------------
- *        PLL_M                                  | 1
- *-----------------------------------------------------------------------------
- *        PLL_N                                  | 8
- *-----------------------------------------------------------------------------
- *        PLL_P                                  | 7
- *-----------------------------------------------------------------------------
- *        PLL_Q                                  | 2
- *-----------------------------------------------------------------------------
- *        PLL_R                                  | 2
- *-----------------------------------------------------------------------------
- *        PLLSAI1_P                              | NA
- *-----------------------------------------------------------------------------
- *        PLLSAI1_Q                              | NA
- *-----------------------------------------------------------------------------
- *        PLLSAI1_R                              | NA
- *-----------------------------------------------------------------------------
- *        Require 48MHz for USB OTG FS,          | Disabled
- *        SDIO and RNG clock                     |
- *-----------------------------------------------------------------------------
- *=============================================================================
- ******************************************************************************
- * @attention
- *
- * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                        opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
+  ******************************************************************************
+  * @file    system_stm32wbxx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32wbxx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
 
 /** @addtogroup CMSIS
- * @{
- */
+  * @{
+  */
 
 /** @addtogroup stm32WBxx_system
- * @{
- */
+  * @{
+  */
 
 /** @addtogroup stm32WBxx_System_Private_Includes
- * @{
- */
+  * @{
+  */
 
-#include "app_common.h"
-#include "otp.h"
+#include "stm32wbxx.h"
 
 #if !defined  (HSE_VALUE)
-#define HSE_VALUE    ((uint32_t)32000000) /*!< Value of the External oscillator in Hz */
+  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 #if !defined  (MSI_VALUE)
-#define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
 #endif /* MSI_VALUE */
 
 #if !defined  (HSI_VALUE)
-#define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
 #if !defined  (LSI_VALUE) 
-#define LSI_VALUE  ((uint32_t)32000)       /*!< Value of LSI in Hz*/
+ #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
 #endif /* LSI_VALUE */ 
 
 #if !defined  (LSE_VALUE)
-#define LSE_VALUE    ((uint32_t)32768)    /*!< Value of LSE in Hz*/
+  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
 #endif /* LSE_VALUE */
 
 /**
- * @}
- */
+  * @}
+  */
 
 /** @addtogroup STM32WBxx_System_Private_TypesDefinitions
- * @{
- */
+  * @{
+  */
 
 /**
- * @}
- */
+  * @}
+  */
 
 /** @addtogroup STM32WBxx_System_Private_Defines
- * @{
- */
+  * @{
+  */
 
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
 /* #define VECT_TAB_SRAM */
-/*!< Vector Table base offset field. This value must be a multiple of 0x200. */
-/* #define VECT_TAB_OFFSET  0x0U*/
+#define VECT_TAB_OFFSET         0x0U            /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
 
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE       /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
 /**
- * @}
- */
+  * @}
+  */
 
 /** @addtogroup STM32WBxx_System_Private_Macros
- * @{
- */
+  * @{
+  */
 
 /**
- * @}
- */
+  * @}
+  */
 
 /** @addtogroup STM32WBxx_System_Private_Variables
- * @{
- */
-/* The SystemCoreClock variable is updated in three ways:
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
       1) by calling CMSIS function SystemCoreClockUpdate()
       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
          Note: If you use this function to configure the system clock; then there
                is no need to call the 2 first functions listed above, since SystemCoreClock
                variable is updated automatically.
- */
-uint32_t SystemCoreClock  = 4000000; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+  */
+  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
 
-const uint32_t AHBPrescTable[16] =   {1, 3, 5, 1, 1, 6, 10, 32, 2, 4, 8, 16, 64, 128, 256, 512};  /* eqv. division factor used for Dory*/
-/* index=[0,...15]*/
-const uint32_t APBPrescTable[8] =  {0, 0, 0, 0, 1, 2, 3, 4};
+  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
 
-const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
-		4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
 
-const uint32_t SmpsPrescalerTable[4][6]={{1,3,2,2,1,2}, \
-		{2,6,4,3,2,4}, \
-		{4,12,8,6,4,8}, \
-		{4,12,8,6,4,8}};
+  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
+                                      4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
+
+  const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
+                                        {2UL,6UL,4UL,3UL,2UL,4UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}, \
+                                        {4UL,12UL,8UL,6UL,4UL,8UL}};
 
 /**
- * @}
- */
+  * @}
+  */
 
- /** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
+/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
   * @{
   */
 
-  /**
-   * @}
-   */
+/**
+  * @}
+  */
 
-   /** @addtogroup STM32WBxx_System_Private_Functions
-    * @{
-    */
+/** @addtogroup STM32WBxx_System_Private_Functions
+  * @{
+  */
 
 /**
- * @brief  Setup the microcontroller system.
- * @param  None
- * @retval None
- */
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
 void SystemInit(void)
 {
-	OTP_ID0_t * p_otp;
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)  
+  /* program in SRAMx */
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAMx for CPU1 */
+#else    /* program in FLASH */
+  SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
+#endif
 
-    /* FPU settings ------------------------------------------------------------*/
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
     SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
-#endif
+  #endif
+  
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
 
-    /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00070000U;
 
-    /* Set MSION bit */
-    RCC->CR |= RCC_CR_MSION;
+  /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
 
-    /* Reset CFGR register */
-    RCC->CFGR = 0x00070000U;
+  /*!< Reset LSI1 and LSI2 bits */
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+    
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x22041000U;
 
-    /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
-    RCC->CR &= (uint32_t)0xFAF6FEFBU;
+  /* Reset PLLSAI1CFGR register */
+  RCC->PLLSAI1CFGR = 0x22041000U;
 
-    /*!< Reset LSI1 and LSI2 bits */
-    RCC->CSR &= (uint32_t)0xFFFFFFFAU;
-
-    /*!< Reset HSI48ON  bit */
-    RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
-
-    /* Reset PLLCFGR register */
-    RCC->PLLCFGR = 0x22041000U;
-
-    /* Reset PLLSAI1CFGR register */
-    RCC->PLLSAI1CFGR = 0x22041000U;
-
-    /* Reset HSEBYP bit */
-    RCC->CR &= 0xFFFBFFFFU;
-
-    /* Disable all interrupts */
-    RCC->CIER = 0x00000000;
-
-	/* Configure the Vector Table location add offset address ------------------*/
-#ifdef CORE_CM0PLUS
-	/* program in SRAM2A */
-#if defined(VECT_TAB_SRAM)
-	SCB->VTOR = RAM2A_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM2A for CPU2 */
-#elif defined(VECT_TAB_SRAM2B)
-	/* program in SRAM2B */
-	SCB->VTOR = RAM2B_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM2B for CPU2 */
-#else
-	/*  program in FLASH */
-	SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
-#endif  /* Program memory type */
-#else
-#if defined(VECT_TAB_SRAM)
-	/* program in SRAM1 */
-	SCB->VTOR = RAM1_BASE | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal SRAM1 for CPU1 */
-#elif defined(VECT_TAB_OFFSET)
-	SCB->VTOR = VECT_TAB_OFFSET;              /* Vector Table Relocation in Internal FLASH */
-#endif
-#endif
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
 
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
 }
 
 /**
- * @brief  Update SystemCoreClock variable according to Clock Register Values.
- *         The SystemCoreClock variable contains the core clock (HCLK), it can
- *         be used by the user application to setup the SysTick timer or configure
- *         other parameters.
- *
- * @note   Each time the core clock (HCLK) changes, this function must be called
- *         to update SystemCoreClock variable value. Otherwise, any configuration
- *         based on this variable will be incorrect.
- *
- * @note   - The system frequency computed by this function is not the real
- *           frequency in the chip. It is calculated based on the predefined
- *           constant and the selected clock source:
- *
- *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
- *
- *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
- *
- *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
- *
- *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
- *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
- *             4 MHz) but the real value may vary depending on the variations
- *             in voltage and temperature.
- *
- *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
- *              16 MHz) but the real value may vary depending on the variations
- *              in voltage and temperature.
- *
- *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
- *              32 MHz), user has to ensure that HSE_VALUE is same as the real
- *              frequency of the crystal used. Otherwise, this function may
- *              have wrong result.
- *
- *         - The result of this function could be not correct when using fractional
- *           value for HSE crystal.
- *
- * @param  None
- * @retval None
- */
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
+  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
 void SystemCoreClockUpdate(void)
 {
   uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
@@ -354,16 +337,17 @@ void SystemCoreClockUpdate(void)
 
 }
 
-/**
- * @}
- */
 
 /**
- * @}
- */
+  * @}
+  */
 
 /**
- * @}
- */
+  * @}
+  */
+
+/**
+  * @}
+  */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TARGET_NUCLEO_WB55RG/system_clock.c b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TARGET_NUCLEO_WB55RG/system_clock.c
index d5e19c4185..adcbf70a40 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TARGET_NUCLEO_WB55RG/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TARGET_NUCLEO_WB55RG/system_clock.c
@@ -18,10 +18,7 @@
 /**
   * This file configures the system clock as follows:
   *-----------------------------------------------------------------------------
-  * System clock source | 1- USE_PLL_HSE_EXTC (external 32 MHz clock)
-  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
-  *                     | 3- USE_PLL_HSI (internal 16 MHz)
-  *                     | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
+  * System clock source | HSE (external 32 MHz clock)
   *-----------------------------------------------------------------------------
   * SYSCLK(MHz)         | 32
   * AHBCLK (MHz)        | 32
@@ -38,26 +35,6 @@
 #include "otp.h"
 #include "hw_conf.h" /* Common BLE file where BLE shared resources are defined */
 
-// Clock source is selected with CLOCK_SOURCE in json config
-#define USE_PLL_HSE_EXTC 0x8 // Use external clock (not available)
-#define USE_PLL_HSE_XTAL 0x4 // Use external 32 MHz xtal (X1 on board + need HW patch)
-#define USE_PLL_HSI      0x2 // Use HSI 16MHz internal clock
-#define USE_PLL_MSI      0x1 // Use MSI internal clock
-
-#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
-
-#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
-
-#if ((CLOCK_SOURCE) & USE_PLL_HSI)
-uint8_t SetSysClock_PLL_HSI(void);
-#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
-
-#if ((CLOCK_SOURCE) & USE_PLL_MSI)
-uint8_t SetSysClock_PLL_MSI(void);
-#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
-
 static void Configure_RF_Clock_Sources(void)
 {
     static uint8_t RF_ON = 0;
@@ -120,69 +97,26 @@ static void Config_HSE(void)
   */
 
 void SetSysClock(void)
-{
-    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
-#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
-    /* 1- Try to start with HSE and external clock */
-    if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-    {
-#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
-        /* 2- If fail try to start with HSE and external xtal */
-        if (SetSysClock_PLL_HSE(0) == 0)
-#endif
-        {
-#if ((CLOCK_SOURCE) & USE_PLL_HSI)
-            /* 3- If fail start with HSI clock */
-            if (SetSysClock_PLL_HSI() == 0)
-#endif
-            {
-#if ((CLOCK_SOURCE) & USE_PLL_MSI)
-                /* 4- If fail start with MSI clock */
-                if (SetSysClock_PLL_MSI() == 0)
-#endif
-                {
-                    {
-                        error("SetSysClock failed\n");
-                    }
-                }
-            }
-        }
-    }
-
-    Configure_RF_Clock_Sources();
-
-    // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 1
-    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 64 MHz
-#endif
-    LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
-}
-
-#if (((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC))
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
 {
     RCC_OscInitTypeDef RCC_OscInitStruct = {0};
     RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
     RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
+    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
+
     Config_HSE();
 
-    /** Configure the main internal regulator output voltage
-    */
+    /* Configure the main internal regulator output voltage */
     __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-    /** Initializes the CPU, AHB and APB busses clocks
-    */
+
+    /* Initializes the CPU, AHB and APB busses clocks */
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
     RCC_OscInitStruct.HSEState = RCC_HSE_ON;
     RCC_OscInitStruct.HSIState = RCC_HSI_ON;
     RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
     RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-        return 0; // FAIL
+        error("HAL_RCC_OscConfig error\n");
     }
     /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
     */
@@ -197,7 +131,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
 
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-        return 0; // FAIL
+        error("HAL_RCC_ClockConfig error\n");
     }
     /** Initializes the peripherals clocks
     */
@@ -206,7 +140,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0;
 
     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
-        return 0; // FAIL
+        error("HAL_RCCEx_PeriphCLKConfig error\n");
     }
 
     /**
@@ -221,128 +155,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     while (!LL_RCC_HSI48_IsReady());
     LL_RCC_SetCLK48ClockSource(LL_RCC_CLK48_CLKSOURCE_HSI48);
 
-    return 1;
+    Configure_RF_Clock_Sources();
+
+    LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
 }
-
-#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
-
-#if ((CLOCK_SOURCE) & USE_PLL_HSI)
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-
-    // Enable HSI oscillator and activate PLL with HSI as source
-    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI; // 16 MHz
-    RCC_OscInitStruct.PLL.PLLM            = RCC_PLLM_DIV2;     // 8 MHz
-    RCC_OscInitStruct.PLL.PLLN            = 16;                // 128 MHz
-    RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV7;
-    RCC_OscInitStruct.PLL.PLLQ            = RCC_PLLQ_DIV4;
-    RCC_OscInitStruct.PLL.PLLR            = RCC_PLLR_DIV2;     // 64 MHz // RCC_SYSCLKSOURCE_PLLCLK
-
-    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-    // Select PLL as system clock source and configure the clocks dividers
-    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_HCLK2 | RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
-    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
-    RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;         // 32 MHz
-    RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;         // 64 MHz
-    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
-    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
-
-    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-    // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 3
-    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-#endif
-
-    return 1;
-}
-#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
-
-#if ((CLOCK_SOURCE) & USE_PLL_MSI)
-/******************************************************************************/
-/*            PLL (clocked by MSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_MSI(void)
-{
-    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-    // RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; // USB todo
-
-#if MBED_CONF_TARGET_LSE_AVAILABLE
-    // Enable LSE Oscillator to automatically calibrate the MSI clock
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
-    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE;            // No PLL update
-    RCC_OscInitStruct.LSEState       = RCC_LSE_ON;              // External 32.768 kHz clock on OSC_IN/OSC_OUT
-    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-    /* Enable the CSS interrupt in case LSE signal is corrupted or not present */
-    HAL_RCCEx_DisableLSECSS();
-#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
-
-    // Enable MSI Oscillator and activate PLL with MSI as source
-    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI;
-    RCC_OscInitStruct.MSIState            = RCC_MSI_ON;
-    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
-    RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_6;    // 4 MHz
-    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
-    RCC_OscInitStruct.PLL.PLLM            = RCC_PLLM_DIV1;     // 4 MHz
-    RCC_OscInitStruct.PLL.PLLN            = 32;                // 128 MHz
-    RCC_OscInitStruct.PLL.PLLR            = RCC_PLLR_DIV2;     // 64 MHz // RCC_SYSCLKSOURCE_PLLCLK
-    RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV5;
-    RCC_OscInitStruct.PLL.PLLQ            = RCC_PLLQ_DIV4;
-    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-#if MBED_CONF_TARGET_LSE_AVAILABLE
-    /* Enable MSI Auto-calibration through LSE */
-    HAL_RCCEx_EnableMSIPLLMode();
-#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
-
-    /* Select MSI output as USB clock source */
-    // PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-    // PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
-    // HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-
-    // Select PLL as system clock source and configure the clocks dividers
-    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_HCLK2 | RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
-    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
-    RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;         // 32 MHz
-    RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;         // 64 MHz
-    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
-    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
-
-    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-
-    // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 4
-    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_1); // 4 MHz
-#endif
-
-    return 1; // OK
-}
-#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
-
diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_ARM_STD/startup_stm32wb55xx.S b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_ARM_STD/startup_stm32wb55xx.S
index c613c4898b..f0bdce44b3 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_ARM_STD/startup_stm32wb55xx.S
+++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_ARM_STD/startup_stm32wb55xx.S
@@ -14,8 +14,7 @@
 ;******************************************************************************
 ;* @attention
 ;*
-;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
 ;*
 ;* This software component is licensed by ST under BSD 3-Clause license,
 ;* the "License"; You may not use this file except in compliance with the 
@@ -33,9 +32,9 @@
                 EXPORT  __Vectors
                 EXPORT  __Vectors_End
                 EXPORT  __Vectors_Size
-                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
 
-__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
+__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit|              ; Top of Stack
         DCD     Reset_Handler                     ; Reset Handler
         DCD     NMI_Handler                       ; NMI Handler
         DCD     HardFault_Handler                 ; Hard Fault Handler
@@ -314,4 +313,11 @@ DMAMUX1_OVR_IRQHandler
                 ENDP
 
                 ALIGN
-                END
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_ARM_STD/stm32wb55xx.sct b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_ARM_STD/stm32wb55xx.sct
index fae24e2994..083d9d7ece 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_ARM_STD/stm32wb55xx.sct
+++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_ARM_STD/stm32wb55xx.sct
@@ -1,64 +1,56 @@
 #! armcc -E
 ; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2019, STMicroelectronics
-; SPDX-License-Identifier: Apache-2.0
-; All rights reserved.
 ;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; SPDX-License-Identifier: BSD-3-Clause
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2016-2020 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+#include "../cmsis_nvic.h"
 
 #if !defined(MBED_APP_START)
-#define MBED_APP_START 0x08000000
+  #define MBED_APP_START  MBED_ROM_START
 #endif
 
 #if !defined(MBED_APP_SIZE)
-; 768KB FLASH
+; 768KB FLASH // BLE firmware is being flashed strating from @ 0x080C0000
 #define MBED_APP_SIZE 0xC0000
 #endif
 
 #if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
+/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
+  #define MBED_BOOT_STACK_SIZE  0x400
 #endif
 
-#define Stack_Size MBED_BOOT_STACK_SIZE
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE  (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
 
-; 768KB FLASH (0xC0000) + 192KB SRAM (0x30000) +  Shared mem
-LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
+; RAM_SIZE = 192KB SRAM (0x30000) + Shared mem
+LR_IROM1  MBED_APP_START  MBED_APP_SIZE  {
 
-  ER_IROM1 MBED_APP_START MBED_APP_SIZE  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
+  ER_IROM1  MBED_APP_START  MBED_APP_SIZE  {
+    *.o (RESET, +First)
+    *(InRoot$$Sections)
+    .ANY (+RO)
   }
 
-  ; Total: 79 vectors = 316 bytes (0x13C) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0x13C) (0x30000-0x13C-Stack_Size)  {  ; RW data
-  .ANY (+RW +ZI)
+  RW_IRAM1  (MBED_RAM_START + VECTORS_SIZE)  {  ; RW data
+    .ANY (+RW +ZI)
   }
 
-  ARM_LIB_STACK (0x20000000+0x30000) EMPTY -Stack_Size { ; stack
+  ARM_LIB_HEAP  AlignExpr(+0, 16)  EMPTY  (MBED_RAM_START + 0x30000 - MBED_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))  { ; Heap growing up
+  }
+
+  ARM_LIB_STACK  (MBED_RAM_START + 0x30000)  EMPTY  -MBED_BOOT_STACK_SIZE  { ; Stack region growing down
   }
 
   ; SRAM2 - Shared memory
@@ -66,7 +58,9 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
     *(MAPPING_TABLE)
     *(MB_MEM1)
   }
+
   RW_IRAM2b 0x20038000 0x00005000  {  ; RW data
    *(MB_MEM2)
   }
+
 }
diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_GCC_ARM/startup_stm32wb55xx.S b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_GCC_ARM/startup_stm32wb55xx.S
index edb40d5108..8ee9e4b5b1 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_GCC_ARM/startup_stm32wb55xx.S
+++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_GCC_ARM/startup_stm32wb55xx.S
@@ -14,7 +14,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. 
   * All rights reserved.</center></h2>
   *
   * This software component is licensed by ST under BSD 3-Clause license,
@@ -85,18 +85,11 @@ LoopFillZerobss:
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit
+	bl _start
 
-/* Call static constructors */
-// MBED >>>
-//bl __libc_init_array
-/* Call the application s entry point.*/
-//bl	main
-//LoopForever:
-//  b LoopForever
-  bl _start
-  bx  lr
-// <<< MBED
-
+LoopForever:
+  b LoopForever
+    
 .size	Reset_Handler, .-Reset_Handler
 
 /**
diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_GCC_ARM/stm32wb55xx.ld b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_GCC_ARM/stm32wb55xx.ld
index 6fe1148137..6f76f16fb2 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_GCC_ARM/stm32wb55xx.ld
+++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_GCC_ARM/stm32wb55xx.ld
@@ -1,23 +1,46 @@
+/* Linker script to configure memory regions. */
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#include "../cmsis_nvic.h"
+
+
 #if !defined(MBED_APP_START)
-#define MBED_APP_START 0x08000000
+  #define MBED_APP_START  MBED_ROM_START
 #endif
 
 #if !defined(MBED_APP_SIZE)
+/* 768KB FLASH - BLE firmware is being flashed strating from @ 0x080C0000 */
 #define MBED_APP_SIZE 768K
 #endif
 
 #if !defined(MBED_BOOT_STACK_SIZE)
-    #define MBED_BOOT_STACK_SIZE 0x400
+    /* This value is normally defined by the tools
+       to 0x1000 for bare metal and 0x400 for RTOS */
+    #define MBED_BOOT_STACK_SIZE  0x400
 #endif
 
-STACK_SIZE = MBED_BOOT_STACK_SIZE;
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE  (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)
 
-/* Linker script to configure memory regions. */
-/* Total: 79 vectors = 316 bytes (0x13C) to be reserved in RAM1 (192K) */
+/* RAM_SIZE = 192KB SRAM (0x30000) + Shared mem */
 MEMORY
 { 
   FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
-  RAM1 (rwx)  : ORIGIN = 0x2000013C, LENGTH = 192K - 0x13C
+  RAM (rwx)   : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = 0x30000 - VECTORS_SIZE
   RAM2a (rw)  : ORIGIN = 0x20030000, LENGTH = 10K
   RAM2b (rw)  : ORIGIN = 0x20038000, LENGTH = 20K
 }
@@ -26,7 +49,7 @@ MEMORY
  * with other linker script that defines memory regions FLASH and RAM.
  * It references following symbols, which must be defined in code:
  *   Reset_Handler : Entry of reset handler
- * 
+ *
  * It defines following symbols, which code can use without definition:
  *   __exidx_start
  *   __exidx_end
@@ -57,6 +80,7 @@ SECTIONS
     {
         KEEP(*(.isr_vector))
         *(.text*)
+
         KEEP(*(.init))
         KEEP(*(.fini))
 
@@ -91,9 +115,12 @@ SECTIONS
     } > FLASH
     __exidx_end = .;
 
-    __etext = .;
+    /* Location counter can end up 2byte aligned with narrow Thumb code but
+       __etext is assumed by startup code to be the LMA of a section in RAM
+       which must be 8-byte aligned */
+    __etext = ALIGN (8);
     _sidata = .;
-
+    
     .data : AT (__etext)
     {
         __data_start__ = .;
@@ -127,28 +154,41 @@ SECTIONS
         __data_end__ = .;
         _edata = .;
 
-    } > RAM1
+    } > RAM
 
+    /* Uninitialized data section
+     * This region is not initialized by the C/C++ library and can be used to
+     * store state across soft reboots. */
+    .uninitialized (NOLOAD):
+    {
+        . = ALIGN(32);
+        __uninitialized_start = .;
+        *(.uninitialized)
+        KEEP(*(.keep.uninitialized))
+        . = ALIGN(32);
+        __uninitialized_end = .;
+    } > RAM
+    
     .bss :
     {
-        . = ALIGN(4);
+        . = ALIGN(8);
         __bss_start__ = .;
         _sbss = .;
         *(.bss*)
         *(COMMON)
-        . = ALIGN(4);
+        . = ALIGN(8);
         __bss_end__ = .;
         _ebss = .;
-    } > RAM1
+    } > RAM
 
     .heap (COPY):
     {
         __end__ = .;
-        end = __end__;
+        PROVIDE(end = .);
         *(.heap*)
-        . = ORIGIN(RAM1) + LENGTH(RAM1) - STACK_SIZE;
+        . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE;
         __HeapLimit = .;
-    } > RAM1
+    } > RAM
 
     /* .stack_dummy section doesn't contains any symbols. It is only
      * used for linker to calculate size of stack sections, and assign
@@ -156,7 +196,7 @@ SECTIONS
     .stack_dummy (COPY):
     {
         *(.stack*)
-    } > RAM1
+    } > RAM
 
     .ble_stby_mem (NOLOAD) :
     {
@@ -169,13 +209,13 @@ SECTIONS
       *(MB_MEM2);
     } >RAM2b
 
-    /* Set stack top to end of RAM1, and stack limit move down by
+    /* Set stack top to end of RAM, and stack limit move down by
      * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM1) + LENGTH(RAM1);
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
     _estack = __StackTop;
-    __StackLimit = __StackTop - STACK_SIZE;
+    __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE;
     PROVIDE(__stack = __StackTop);
 
-    /* Check if data + heap + stack exceeds RAM1 limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM1 overflowed with stack")
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
 }
diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_IAR/startup_stm32wb55xx.S b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_IAR/startup_stm32wb55xx.S
index a10d9ecbd9..1f886ff593 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_IAR/startup_stm32wb55xx.S
+++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_IAR/startup_stm32wb55xx.S
@@ -16,7 +16,7 @@
 ;******************************************************************************
 ;* @attention
 ;*
-;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
+;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. 
 ;* All rights reserved.</center></h2>
 ;*
 ;* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_IAR/stm32wb55xx.icf b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_IAR/stm32wb55xx.icf
index fab5ab7ef4..edd2e1b113 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_IAR/stm32wb55xx.icf
+++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TOOLCHAIN_IAR/stm32wb55xx.icf
@@ -1,20 +1,20 @@
-/*
- * Copyright (c) 2019, STMicroelectronics
+/* Linker script to configure memory regions.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
+ ******************************************************************************
+*/
+/* Device specific values */
 
 if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
 if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0xC0000; }
diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/cmsis_nvic.h
index dcaa22ba12..01684e0c7f 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/cmsis_nvic.h
+++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/cmsis_nvic.h
@@ -1,26 +1,46 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2019 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
+ * <h2><center>&copy; Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.</center></h2>
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
+ ******************************************************************************
+*/
+
 #ifndef MBED_CMSIS_NVIC_H
 #define MBED_CMSIS_NVIC_H
 
-// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
-// MCU Peripherals: 63 vectors = 252 bytes from 0x40 to 0x13B
-// Total: 16+63=79 vectors = 316 bytes (0x13C) to be reserved in RAM
+#if !defined(MBED_ROM_START)
+#define MBED_ROM_START  0x8000000
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+#define MBED_ROM_SIZE  0x100000
+//  0x40000 STM32WB55VCYx STM32WB55RCVx STM32WB55CCUx
+//  0x80000 STM32WB55REVx STM32WB55CEUx STM32WB55VEYx
+// 0x100000 STM32WB55RGVx STM32WB55VGYx STM32WB55CGUx
+#warning "check MBED_ROM_SIZE value in cmsis_nvic.h"
+#endif
+
+#if !defined(MBED_RAM_START)
+#define MBED_RAM_START  0x20000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+#define MBED_RAM_SIZE  0x40000
+//  0x40000 STM32WB55RGVx STM32WB55REVx STM32WB55CEUx STM32WB55VEYx STM32WB55VGYx STM32WB55CGUx
+//  0x20000 STM32WB55VCYx STM32WB55RCVx STM32WB55CCUx
+#warning "check MBED_RAM_SIZE value in cmsis_nvic.h"
+#endif
+
 #define NVIC_NUM_VECTORS        79
-#define NVIC_RAM_VECTOR_ADDRESS 0x20000000  // Vectors positioned at start of RAM
+#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
 
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32WB/analogin_device.c b/targets/TARGET_STM/TARGET_STM32WB/analogin_device.c
index e200ed3a60..9ff0c4390e 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/analogin_device.c
+++ b/targets/TARGET_STM/TARGET_STM32WB/analogin_device.c
@@ -1,32 +1,18 @@
 /* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2019, STMicroelectronics
+ * Copyright (c) 2019 STMicroelectronics
  * SPDX-License-Identifier: Apache-2.0
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
+ *     http://www.apache.org/licenses/LICENSE-2.0
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 #if DEVICE_ANALOGIN
diff --git a/targets/TARGET_STM/TARGET_STM32WB/flash_data.h b/targets/TARGET_STM/TARGET_STM32WB/flash_data.h
index 654353a35f..f8c376b02f 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/flash_data.h
+++ b/targets/TARGET_STM/TARGET_STM32WB/flash_data.h
@@ -1,33 +1,20 @@
 /* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2019, STMicroelectronics
+ * Copyright (c) 2019 STMicroelectronics
  * SPDX-License-Identifier: Apache-2.0
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
+ *     http://www.apache.org/licenses/LICENSE-2.0
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
+
 #ifndef MBED_FLASH_DATA_H
 #define MBED_FLASH_DATA_H
 
diff --git a/targets/TARGET_STM/TARGET_STM32WB/gpio_irq_device.c b/targets/TARGET_STM/TARGET_STM32WB/gpio_irq_device.c
index 5d3278ce80..67c4c4b028 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/gpio_irq_device.c
+++ b/targets/TARGET_STM/TARGET_STM32WB/gpio_irq_device.c
@@ -1,32 +1,18 @@
 /* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2019, STMicroelectronics
+ * Copyright (c) 2019 STMicroelectronics
  * SPDX-License-Identifier: Apache-2.0
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
+ *     http://www.apache.org/licenses/LICENSE-2.0
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 #include "cmsis.h"
diff --git a/targets/TARGET_STM/TARGET_STM32WB/gpio_irq_device.h b/targets/TARGET_STM/TARGET_STM32WB/gpio_irq_device.h
index 791dfa4ecb..5e044f9b7d 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/gpio_irq_device.h
+++ b/targets/TARGET_STM/TARGET_STM32WB/gpio_irq_device.h
@@ -1,32 +1,18 @@
 /* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2019, STMicroelectronics
+ * Copyright (c) 2019 STMicroelectronics
  * SPDX-License-Identifier: Apache-2.0
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
+ *     http://www.apache.org/licenses/LICENSE-2.0
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 #ifndef MBED_GPIO_IRQ_DEVICE_H
diff --git a/targets/TARGET_STM/TARGET_STM32WB/i2c_device.h b/targets/TARGET_STM/TARGET_STM32WB/i2c_device.h
index 05eab04b4c..023f8ab9d5 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/i2c_device.h
+++ b/targets/TARGET_STM/TARGET_STM32WB/i2c_device.h
@@ -1,32 +1,18 @@
 /* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2019, STMicroelectronics
+ * Copyright (c) 2019 STMicroelectronics
  * SPDX-License-Identifier: Apache-2.0
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
+ *     http://www.apache.org/licenses/LICENSE-2.0
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 #ifndef MBED_I2C_DEVICE_H
diff --git a/targets/TARGET_STM/TARGET_STM32WB/objects.h b/targets/TARGET_STM/TARGET_STM32WB/objects.h
index b0ff76381e..fad538a140 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32WB/objects.h
@@ -14,6 +14,7 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
+
 #ifndef MBED_OBJECTS_H
 #define MBED_OBJECTS_H
 
@@ -26,6 +27,11 @@
 #include "stm32wbxx_ll_tim.h"
 #include "stm32wbxx_ll_pwr.h"
 #include "stm32wbxx_ll_rtc.h"
+#include "stm32wbxx_ll_hsem.h"
+
+#ifndef FEATURE_BLE
+#error "BLE FEATURE CANNOT BE REMOVED"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/targets/TARGET_STM/TARGET_STM32WB/pin_device.h b/targets/TARGET_STM/TARGET_STM32WB/pin_device.h
index 82f821fd1c..146d7052c8 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/pin_device.h
+++ b/targets/TARGET_STM/TARGET_STM32WB/pin_device.h
@@ -1,32 +1,18 @@
 /* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2019, STMicroelectronics
+ * Copyright (c) 2019 STMicroelectronics
  * SPDX-License-Identifier: Apache-2.0
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
+ *     http://www.apache.org/licenses/LICENSE-2.0
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 #ifndef MBED_PIN_DEVICE_H
diff --git a/targets/TARGET_STM/TARGET_STM32WB/pwmout_device.c b/targets/TARGET_STM/TARGET_STM32WB/pwmout_device.c
index 1701b539a4..9857e67ae0 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/pwmout_device.c
+++ b/targets/TARGET_STM/TARGET_STM32WB/pwmout_device.c
@@ -1,32 +1,18 @@
 /* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2019, STMicroelectronics
+ * Copyright (c) 2019 STMicroelectronics
  * SPDX-License-Identifier: Apache-2.0
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
+ *     http://www.apache.org/licenses/LICENSE-2.0
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 #include "cmsis.h"
diff --git a/targets/TARGET_STM/TARGET_STM32WB/pwmout_device.h b/targets/TARGET_STM/TARGET_STM32WB/pwmout_device.h
index 20f6023844..2f0991f1dc 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/pwmout_device.h
+++ b/targets/TARGET_STM/TARGET_STM32WB/pwmout_device.h
@@ -1,32 +1,18 @@
 /* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2019, STMicroelectronics
+ * Copyright (c) 2019 STMicroelectronics
  * SPDX-License-Identifier: Apache-2.0
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
+ *     http://www.apache.org/licenses/LICENSE-2.0
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 #ifndef MBED_PWMOUT_DEVICE_H
diff --git a/targets/TARGET_STM/TARGET_STM32WB/serial_device.c b/targets/TARGET_STM/TARGET_STM32WB/serial_device.c
index 7128c8e9f8..e12d2fdd6b 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/serial_device.c
+++ b/targets/TARGET_STM/TARGET_STM32WB/serial_device.c
@@ -1,32 +1,18 @@
 /* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2019, STMicroelectronics
+ * Copyright (c) 2019 STMicroelectronics
  * SPDX-License-Identifier: Apache-2.0
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
+ *     http://www.apache.org/licenses/LICENSE-2.0
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 #if DEVICE_SERIAL
diff --git a/targets/TARGET_STM/TARGET_STM32WB/spi_api.c b/targets/TARGET_STM/TARGET_STM32WB/spi_api.c
index cdfee382ba..853a7e7f6c 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/spi_api.c
+++ b/targets/TARGET_STM/TARGET_STM32WB/spi_api.c
@@ -1,32 +1,18 @@
 /* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2019, STMicroelectronics
+ * Copyright (c) 2019 STMicroelectronics
  * SPDX-License-Identifier: Apache-2.0
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
+ *     http://www.apache.org/licenses/LICENSE-2.0
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 #include "mbed_assert.h"
diff --git a/targets/TARGET_STM/TARGET_STM32WB/spi_device.h b/targets/TARGET_STM/TARGET_STM32WB/spi_device.h
index f2f72571ab..5ea5edd8f6 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/spi_device.h
+++ b/targets/TARGET_STM/TARGET_STM32WB/spi_device.h
@@ -1,32 +1,18 @@
 /* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2019, STMicroelectronics
+ * Copyright (c) 2019 STMicroelectronics
  * SPDX-License-Identifier: Apache-2.0
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
+ *     http://www.apache.org/licenses/LICENSE-2.0
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 #ifndef MBED_SPI_DEVICE_H
diff --git a/targets/TARGET_STM/TARGET_STM32WB/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32WB/us_ticker_data.h
index 9ee846abb5..b4bf37f425 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/us_ticker_data.h
+++ b/targets/TARGET_STM/TARGET_STM32WB/us_ticker_data.h
@@ -14,6 +14,7 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
+
 #ifndef __US_TICKER_DATA_H
 #define __US_TICKER_DATA_H
 
diff --git a/targets/TARGET_STM/TARGET_STM32WB/wb_sleep.c b/targets/TARGET_STM/TARGET_STM32WB/wb_sleep.c
index 45a51443af..404571f5a6 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/wb_sleep.c
+++ b/targets/TARGET_STM/TARGET_STM32WB/wb_sleep.c
@@ -1,33 +1,20 @@
 /* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2019, STMicroelectronics
+ * Copyright (c) 2019 STMicroelectronics
  * SPDX-License-Identifier: Apache-2.0
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
+ *     http://www.apache.org/licenses/LICENSE-2.0
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
+
 #if DEVICE_SLEEP
 
 #include "sleep_api.h"
diff --git a/targets/targets.json b/targets/targets.json
index 492aa0febf..d24ba10ca6 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -12036,11 +12036,6 @@
             "CORDIO"
         ],
         "config": {
-            "clock_source": {
-                "help": "Mask value : USE_PLL_HSE_EXTC (HSE recommended for BLE usage) | USE_PLL_HSI | USE_PLL_MSI",
-                "value": "USE_PLL_HSE_EXTC",
-                "macro_name": "CLOCK_SOURCE"
-            },
             "lpticker_lptim": {
                 "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
                 "value": 1