diff --git a/targets/TARGET_STM/CMakeLists.txt b/targets/TARGET_STM/CMakeLists.txt new file mode 100644 index 0000000000..14d8b1c729 --- /dev/null +++ b/targets/TARGET_STM/CMakeLists.txt @@ -0,0 +1,36 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +target_include_directories(mbed-os + PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR} +) + +target_sources(mbed-os + PRIVATE + USBPhy_STM32.cpp + analogin_api.c + analogout_api.c + can_api.c + gpio_api.c + gpio_irq_api.c + hal_tick_overrides.c + i2c_api.c + lp_ticker.c + mbed_crc_api.c + mbed_overrides.c + pinmap.c + port_api.c + pwmout_api.c + qspi_api.c + reset_reason.c + rtc_api.c + serial_api.c + sleep.c + stm_spi_api.c + trng_api.c + us_ticker.c + watchdog_api.c +) + +mbed_add_cmake_directory_if_labels("TARGET") diff --git a/targets/TARGET_STM/TARGET_STM32L4/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32L4/CMakeLists.txt new file mode 100644 index 0000000000..742f4588d9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/CMakeLists.txt @@ -0,0 +1,22 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(device) + +target_sources(mbed-os + PRIVATE + analogin_device.c + analogout_device.c + flash_api.c + gpio_irq_device.c + pwmout_device.c + serial_device.c + spi_api.c +) + +mbed_add_cmake_directory_if_labels("TARGET") + +target_include_directories(mbed-os + PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR} +) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/CMakeLists.txt new file mode 100644 index 0000000000..eeb65b8e38 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(device) + +mbed_add_cmake_directory_if_labels("TARGET") + +target_include_directories(mbed-os + PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR} +) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/CMakeLists.txt new file mode 100644 index 0000000000..2792eeb1ee --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/CMakeLists.txt @@ -0,0 +1,13 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +target_sources(mbed-os + PRIVATE + PeripheralPins.c + system_clock.c +) + +target_include_directories(mbed-os + PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR} +) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/CMakeLists.txt new file mode 100644 index 0000000000..630b5928e6 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/CMakeLists.txt @@ -0,0 +1,32 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +function(_mbed_get_assembly_disco_l475vg_iot01a) + if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32l475xx.S) + elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM_STD/startup_stm32l475xx.S) + elseif(${MBED_TOOLCHAIN} STREQUAL "IAR") + set(STARTUP_FILE TOOLCHAIN_IAR/startup_stm32l475xx.S) + endif() + target_sources(mbed-os PRIVATE ${STARTUP_FILE}) +endfunction() + +function(_mbed_set_linker_file) + if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(LINKER_FILE ${CMAKE_CURRENT_SOURCE_DIR}/TOOLCHAIN_GCC_ARM/STM32L475XX.ld) + elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(LINKER_FILE ${CMAKE_CURRENT_SOURCE_DIR}/TOOLCHAIN_ARM_STD/stm32l475xx.sct) + elseif(${MBED_TOOLCHAIN} STREQUAL "IAR") + set(LINKER_FILE ${CMAKE_CURRENT_SOURCE_DIR}/TOOLCHAIN_IAR/stm32l475xx.icf) + endif() + set_property(GLOBAL PROPERTY MBED_TARGET_LINKER_FILE ${LINKER_FILE}) +endfunction() + +_mbed_get_assembly_disco_l475vg_iot01a() +_mbed_set_linker_file() + +target_include_directories(mbed-os + PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR} +) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/startup_stm32l475xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/startup_stm32l475xx.S new file mode 100644 index 0000000000..9dec3c312b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/startup_stm32l475xx.S @@ -0,0 +1,371 @@ +;******************************************************************************* +;* File Name : startup_stm32l475xx.s +;* Author : MCD Application Team +;* Description : STM32L475xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1, ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +DFSDM1_FLT3_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +OTG_FS_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +QUADSPI_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +SWPMI1_IRQHandler +TSC_IRQHandler +RNG_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/stm32l475xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/stm32l475xx.sct new file mode 100644 index 0000000000..8a43994eff --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/stm32l475xx.sct @@ -0,0 +1,78 @@ +#! armcc -E +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + + +; Crash report enabled as default +#if !defined(MBED_CRASH_REPORT_RAM_SIZE) +#define MBED_CRASH_REPORT_RAM_SIZE 0x100 +#endif + +;Vectors + Crash report - Fixed at start of RAM2 in sequence +#define MBED_IRAM2_SIZE (MBED_RAM1_SIZE - VECTORS_SIZE - MBED_CRASH_REPORT_RAM_SIZE) + +#define MBED_CRASH_REPORT_RAM_START (MBED_RAM1_START + VECTORS_SIZE) +#define MBED_IRAM2_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE) + +; Minimum heap should be larger then smallest RAM bank (else can use +; that bank for heap) and less then largest RAM bank. +#define MINIMUM_HEAP 0x12000 + +;Splitting the RW and ZI section in IRAM1 (MBED_RAM_SIZE-MINIMUM_HEAP = 0x6000 available) +;and IRAM2 (MBED_IRAM2_SIZE = 0x7D78 available) +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data + } + + RW_IRAM1 MBED_RAM_START (MBED_RAM_SIZE - MINIMUM_HEAP) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { + } + + RW_IRAM2 MBED_IRAM2_START MBED_IRAM2_SIZE { + .ANY (+RW +ZI) + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack + } +} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32L4/device/CMakeLists.txt new file mode 100644 index 0000000000..41bf204805 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/CMakeLists.txt @@ -0,0 +1,111 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +target_sources(mbed-os +PRIVATE + stm32l4xx_hal.c + stm32l4xx_hal_adc.c + stm32l4xx_hal_adc_ex.c + stm32l4xx_hal_can.c + stm32l4xx_hal_can_legacy.c + stm32l4xx_hal_comp.c + stm32l4xx_hal_cortex.c + stm32l4xx_hal_crc.c + stm32l4xx_hal_crc_ex.c + stm32l4xx_hal_cryp.c + stm32l4xx_hal_cryp_ex.c + stm32l4xx_hal_dac.c + stm32l4xx_hal_dac_ex.c + stm32l4xx_hal_dcmi.c + stm32l4xx_hal_dfsdm.c + stm32l4xx_hal_dfsdm_ex.c + stm32l4xx_hal_dma.c + stm32l4xx_hal_dma2d.c + stm32l4xx_hal_dma_ex.c + stm32l4xx_hal_dsi.c + stm32l4xx_hal_exti.c + stm32l4xx_hal_firewall.c + stm32l4xx_hal_flash.c + stm32l4xx_hal_flash_ex.c + stm32l4xx_hal_flash_ramfunc.c + stm32l4xx_hal_gfxmmu.c + stm32l4xx_hal_gpio.c + stm32l4xx_hal_hash.c + stm32l4xx_hal_hash_ex.c + stm32l4xx_hal_hcd.c + stm32l4xx_hal_i2c.c + stm32l4xx_hal_i2c_ex.c + stm32l4xx_hal_irda.c + stm32l4xx_hal_iwdg.c + stm32l4xx_hal_lcd.c + stm32l4xx_hal_lptim.c + stm32l4xx_hal_ltdc.c + stm32l4xx_hal_ltdc_ex.c + stm32l4xx_hal_mmc.c + stm32l4xx_hal_mmc_ex.c + stm32l4xx_hal_nand.c + stm32l4xx_hal_nor.c + stm32l4xx_hal_opamp.c + stm32l4xx_hal_opamp_ex.c + stm32l4xx_hal_ospi.c + stm32l4xx_hal_pcd.c + stm32l4xx_hal_pcd_ex.c + stm32l4xx_hal_pwr.c + stm32l4xx_hal_pwr_ex.c + stm32l4xx_hal_qspi.c + stm32l4xx_hal_rcc.c + stm32l4xx_hal_rcc_ex.c + stm32l4xx_hal_rng.c + stm32l4xx_hal_rtc.c + stm32l4xx_hal_rtc_ex.c + stm32l4xx_hal_sai.c + stm32l4xx_hal_sai_ex.c + stm32l4xx_hal_sd.c + stm32l4xx_hal_sd_ex.c + stm32l4xx_hal_smartcard.c + stm32l4xx_hal_smartcard_ex.c + stm32l4xx_hal_smbus.c + stm32l4xx_hal_spi.c + stm32l4xx_hal_spi_ex.c + stm32l4xx_hal_sram.c + stm32l4xx_hal_swpmi.c + stm32l4xx_hal_tim.c + stm32l4xx_hal_tim_ex.c + stm32l4xx_hal_tsc.c + stm32l4xx_hal_uart.c + stm32l4xx_hal_uart_ex.c + stm32l4xx_hal_usart.c + stm32l4xx_hal_usart_ex.c + stm32l4xx_hal_wwdg.c + stm32l4xx_ll_adc.c + stm32l4xx_ll_comp.c + stm32l4xx_ll_crc.c + stm32l4xx_ll_crs.c + stm32l4xx_ll_dac.c + stm32l4xx_ll_dma.c + stm32l4xx_ll_dma2d.c + stm32l4xx_ll_exti.c + stm32l4xx_ll_fmc.c + stm32l4xx_ll_gpio.c + stm32l4xx_ll_i2c.c + stm32l4xx_ll_lptim.c + stm32l4xx_ll_lpuart.c + stm32l4xx_ll_opamp.c + stm32l4xx_ll_pwr.c + stm32l4xx_ll_rcc.c + stm32l4xx_ll_rng.c + stm32l4xx_ll_rtc.c + stm32l4xx_ll_sdmmc.c + stm32l4xx_ll_spi.c + stm32l4xx_ll_swpmi.c + stm32l4xx_ll_tim.c + stm32l4xx_ll_usart.c + stm32l4xx_ll_usb.c + stm32l4xx_ll_utils.c + system_stm32l4xx.c +) + +target_include_directories(mbed-os +PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR} +)