diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/stm32l071xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/stm32l071xx.h index fb5bb43dcc..d679d98fae 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/stm32l071xx.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/stm32l071xx.h @@ -1,56 +1,28 @@ -/** - ****************************************************************************** - * @file stm32l073xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for stm32l073xx devices. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral's registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ /** @addtogroup CMSIS * @{ */ -/** @addtogroup stm32l073xx +/** @addtogroup stm32l071xx * @{ */ -#ifndef __STM32L073xx_H -#define __STM32L073xx_H +#ifndef __STM32L071xx_H +#define __STM32L071xx_H #ifdef __cplusplus extern "C" { @@ -78,7 +50,7 @@ */ /** - * @brief stm32l073xx Interrupt Number Definition, according to the selected device + * @brief stm32l071xx Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ @@ -97,11 +69,10 @@ typedef enum PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ + RCC_IRQn = 4, /*!< RCC Interrupt */ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - TSC_IRQn = 8, /*!< TSC Interrupt */ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ @@ -110,7 +81,7 @@ typedef enum USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */ TIM2_IRQn = 15, /*!< TIM2 Interrupt */ TIM3_IRQn = 16, /*!< TIM3 Interrupt */ - TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ + TIM6_IRQn = 17, /*!< TIM6 Interrupts */ TIM7_IRQn = 18, /*!< TIM7 Interrupt */ TIM21_IRQn = 20, /*!< TIM21 Interrupt */ I2C3_IRQn = 21, /*!< I2C3 Interrupt */ @@ -122,8 +93,6 @@ typedef enum USART1_IRQn = 27, /*!< USART1 Interrupt */ USART2_IRQn = 28, /*!< USART2 Interrupt */ RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */ - LCD_IRQn = 30, /*!< LCD Interrupt */ - USB_IRQn = 31, /*!< USB global Interrupt */ } IRQn_Type; /** @@ -199,40 +168,6 @@ __IO uint32_t POL; /*!< CRC polynomial register, } CRC_TypeDef; /** - * @brief Clock Recovery System - */ - -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** * @brief Debug MCU */ @@ -393,19 +328,6 @@ typedef struct __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ } IWDG_TypeDef; -/** - * @brief LCD - */ -typedef struct -{ - __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ - __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ - __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ - __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ -} LCD_TypeDef; - /** * @brief MIFARE Firewall */ @@ -460,16 +382,6 @@ typedef struct __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */ } RCC_TypeDef; -/** - * @brief Random numbers generator - */ -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - /** * @brief Real-Time Clock */ @@ -548,27 +460,6 @@ typedef struct } TIM_TypeDef; /** - * @brief Touch Sensing Controller (TSC) - */ -typedef struct -{ - __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ - __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ - __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ - __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ - __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ - __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ - uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ - __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ - __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ -} TSC_TypeDef; - -/** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct @@ -596,42 +487,6 @@ typedef struct __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; -/** - * @brief Universal Serial Bus Full Speed Device - */ -typedef struct -{ - __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ - __IO uint16_t RESERVED0; /*!< Reserved */ - __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ - __IO uint16_t RESERVED1; /*!< Reserved */ - __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ - __IO uint16_t RESERVED2; /*!< Reserved */ - __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ - __IO uint16_t RESERVED3; /*!< Reserved */ - __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ - __IO uint16_t RESERVED4; /*!< Reserved */ - __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ - __IO uint16_t RESERVED5; /*!< Reserved */ - __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ - __IO uint16_t RESERVED6; /*!< Reserved */ - __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ - __IO uint16_t RESERVED7[17]; /*!< Reserved */ - __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ - __IO uint16_t RESERVED8; /*!< Reserved */ - __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ - __IO uint16_t RESERVED9; /*!< Reserved */ - __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ - __IO uint16_t RESERVEDA; /*!< Reserved */ - __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ - __IO uint16_t RESERVEDB; /*!< Reserved */ - __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ - __IO uint16_t RESERVEDC; /*!< Reserved */ - __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ - __IO uint16_t RESERVEDD; /*!< Reserved */ - __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ - __IO uint16_t RESERVEDE; /*!< Reserved */ -} USB_TypeDef; /** * @} @@ -662,7 +517,6 @@ typedef struct #define TIM3_BASE (APBPERIPH_BASE + 0x00000400U) #define TIM6_BASE (APBPERIPH_BASE + 0x00001000U) #define TIM7_BASE (APBPERIPH_BASE + 0x00001400U) -#define LCD_BASE (APBPERIPH_BASE + 0x00002400U) #define RTC_BASE (APBPERIPH_BASE + 0x00002800U) #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00U) #define IWDG_BASE (APBPERIPH_BASE + 0x00003000U) @@ -673,9 +527,7 @@ typedef struct #define USART5_BASE (APBPERIPH_BASE + 0x00005000U) #define I2C1_BASE (APBPERIPH_BASE + 0x00005400U) #define I2C2_BASE (APBPERIPH_BASE + 0x00005800U) -#define CRS_BASE (APBPERIPH_BASE + 0x00006C00U) #define PWR_BASE (APBPERIPH_BASE + 0x00007000U) -#define DAC_BASE (APBPERIPH_BASE + 0x00007400U) #define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00U) #define I2C3_BASE (APBPERIPH_BASE + 0x00007800U) @@ -710,8 +562,6 @@ typedef struct #define FLASHSIZE_BASE ((uint32_t)0x1FF8007CU) /*!< FLASH Size register base address */ #define UID_BASE ((uint32_t)0x1FF80050U) /*!< Unique device ID register base address */ #define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) -#define TSC_BASE (AHBPERIPH_BASE + 0x00004000U) -#define RNG_BASE (AHBPERIPH_BASE + 0x00005000U) #define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000U) #define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400U) @@ -741,12 +591,8 @@ typedef struct #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CRS ((CRS_TypeDef *) CRS_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define DAC1 ((DAC_TypeDef *) DAC_BASE) #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) -#define LCD ((LCD_TypeDef *) LCD_BASE) #define USART4 ((USART_TypeDef *) USART4_BASE) #define USART5 ((USART_TypeDef *) USART5_BASE) @@ -780,8 +626,6 @@ typedef struct #define OB ((OB_TypeDef *) OB_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) -#define TSC ((TSC_TypeDef *) TSC_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) @@ -790,8 +634,6 @@ typedef struct #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define USB ((USB_TypeDef *) USB_BASE) - /** * @} */ @@ -1071,9 +913,6 @@ typedef struct #define ADC_CCR_LFMEN_Pos (25U) #define ADC_CCR_LFMEN_Msk (0x1U << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ #define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */ -#define ADC_CCR_VLCDEN_Pos (24U) -#define ADC_CCR_VLCDEN_Msk (0x1U << ADC_CCR_VLCDEN_Pos) /*!< 0x01000000 */ -#define ADC_CCR_VLCDEN ADC_CCR_VLCDEN_Msk /*!< Voltage LCD enable */ #define ADC_CCR_TSEN_Pos (23U) #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */ @@ -1211,272 +1050,6 @@ typedef struct #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ -/******************************************************************************/ -/* */ -/* CRS Clock Recovery System */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for CRS_CR register *********************/ -#define CRS_CR_SYNCOKIE_Pos (0U) -#define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ -#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */ -#define CRS_CR_SYNCWARNIE_Pos (1U) -#define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ -#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */ -#define CRS_CR_ERRIE_Pos (2U) -#define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ -#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */ -#define CRS_CR_ESYNCIE_Pos (3U) -#define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ -#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/ -#define CRS_CR_CEN_Pos (5U) -#define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */ -#define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */ -#define CRS_CR_AUTOTRIMEN_Pos (6U) -#define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ -#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */ -#define CRS_CR_SWSYNC_Pos (7U) -#define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ -#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */ -#define CRS_CR_TRIM_Pos (8U) -#define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ -#define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */ - -/******************* Bit definition for CRS_CFGR register *********************/ -#define CRS_CFGR_RELOAD_Pos (0U) -#define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ -#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */ -#define CRS_CFGR_FELIM_Pos (16U) -#define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ -#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */ - -#define CRS_CFGR_SYNCDIV_Pos (24U) -#define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ -#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */ -#define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ -#define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ -#define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ - -#define CRS_CFGR_SYNCSRC_Pos (28U) -#define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ -#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */ -#define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ -#define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ - -#define CRS_CFGR_SYNCPOL_Pos (31U) -#define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ -#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */ - -/******************* Bit definition for CRS_ISR register *********************/ -#define CRS_ISR_SYNCOKF_Pos (0U) -#define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ -#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */ -#define CRS_ISR_SYNCWARNF_Pos (1U) -#define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ -#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */ -#define CRS_ISR_ERRF_Pos (2U) -#define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ -#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */ -#define CRS_ISR_ESYNCF_Pos (3U) -#define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ -#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */ -#define CRS_ISR_SYNCERR_Pos (8U) -#define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ -#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */ -#define CRS_ISR_SYNCMISS_Pos (9U) -#define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ -#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */ -#define CRS_ISR_TRIMOVF_Pos (10U) -#define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ -#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */ -#define CRS_ISR_FEDIR_Pos (15U) -#define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ -#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */ -#define CRS_ISR_FECAP_Pos (16U) -#define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ -#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */ - -/******************* Bit definition for CRS_ICR register *********************/ -#define CRS_ICR_SYNCOKC_Pos (0U) -#define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ -#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */ -#define CRS_ICR_SYNCWARNC_Pos (1U) -#define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ -#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */ -#define CRS_ICR_ERRC_Pos (2U) -#define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ -#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */ -#define CRS_ICR_ESYNCC_Pos (3U) -#define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ -#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */ - -/******************************************************************************/ -/* */ -/* Digital to Analog Converter (DAC) */ -/* */ -/******************************************************************************/ - -/* - * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) - */ -#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */ - -/******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1_Pos (0U) -#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */ -#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ -#define DAC_CR_BOFF1_Pos (1U) -#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ -#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ -#define DAC_CR_TEN1_Pos (2U) -#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ -#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ - -#define DAC_CR_TSEL1_Pos (3U) -#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ -#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ -#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ -#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ - -#define DAC_CR_WAVE1_Pos (6U) -#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ -#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ -#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ - -#define DAC_CR_MAMP1_Pos (8U) -#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ -#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ -#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ -#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ -#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ - -#define DAC_CR_DMAEN1_Pos (12U) -#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ -#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ -#define DAC_CR_DMAUDRIE1_Pos (13U) -#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ -#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun interrupt enable */ - -#define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ -#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */ -#define DAC_CR_BOFF2_Pos (17U) -#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ -#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */ -#define DAC_CR_TEN2_Pos (18U) -#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ -#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */ - -#define DAC_CR_TSEL2_Pos (19U) -#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ -#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ -#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ -#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ -#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ - -#define DAC_CR_WAVE2_Pos (22U) -#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ -#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ -#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ - -#define DAC_CR_MAMP2_Pos (24U) -#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ -#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ -#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ -#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ -#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ -#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ - -#define DAC_CR_DMAEN2_Pos (28U) -#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ -#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */ -#define DAC_CR_DMAUDRIE2_Pos (29U) -#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ -#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel12DMA Underrun interrupt enable */ - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ -#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2_Pos (1U) -#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ -#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */ - -/***************** Bit definition for DAC_DHR12R1 register ******************/ -#define DAC_DHR12R1_DACC1DHR_Pos (0U) -#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ -#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12L1 register ******************/ -#define DAC_DHR12L1_DACC1DHR_Pos (4U) -#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ -#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8R1 register ******************/ -#define DAC_DHR8R1_DACC1DHR_Pos (0U) -#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ -#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12R2 register ******************/ -#define DAC_DHR12R2_DACC2DHR_Pos (0U) -#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ -#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12L2 register ******************/ -#define DAC_DHR12L2_DACC2DHR_Pos (4U) -#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ -#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8R2 register ******************/ -#define DAC_DHR8R2_DACC2DHR_Pos (0U) -#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ -#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12RD register ******************/ -#define DAC_DHR12RD_DACC1DHR_Pos (0U) -#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ -#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ -#define DAC_DHR12RD_DACC2DHR_Pos (16U) -#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ -#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12LD register ******************/ -#define DAC_DHR12LD_DACC1DHR_Pos (4U) -#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ -#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ -#define DAC_DHR12LD_DACC2DHR_Pos (20U) -#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ -#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8RD register ******************/ -#define DAC_DHR8RD_DACC1DHR_Pos (0U) -#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ -#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ -#define DAC_DHR8RD_DACC2DHR_Pos (8U) -#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ -#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ - -/******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /*!< DAC channel1 data output */ - -/******************* Bit definition for DAC_DOR2 register *******************/ -#define DAC_DOR2_DACC2DOR_Pos (0U) -#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ -#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */ - -/******************** Bit definition for DAC_SR register ********************/ -#define DAC_SR_DMAUDR1_Pos (13U) -#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ -#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ -#define DAC_SR_DMAUDR2_Pos (29U) -#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ -#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */ - /******************************************************************************/ /* */ /* Debug MCU (DBGMCU) */ @@ -3399,126 +2972,6 @@ typedef struct #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ -/******************************************************************************/ -/* */ -/* LCD Controller (LCD) */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for LCD_CR register *********************/ -#define LCD_CR_LCDEN_Pos (0U) -#define LCD_CR_LCDEN_Msk (0x1U << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */ -#define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */ -#define LCD_CR_VSEL_Pos (1U) -#define LCD_CR_VSEL_Msk (0x1U << LCD_CR_VSEL_Pos) /*!< 0x00000002 */ -#define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */ - -#define LCD_CR_DUTY_Pos (2U) -#define LCD_CR_DUTY_Msk (0x7U << LCD_CR_DUTY_Pos) /*!< 0x0000001C */ -#define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */ -#define LCD_CR_DUTY_0 (0x1U << LCD_CR_DUTY_Pos) /*!< 0x00000004 */ -#define LCD_CR_DUTY_1 (0x2U << LCD_CR_DUTY_Pos) /*!< 0x00000008 */ -#define LCD_CR_DUTY_2 (0x4U << LCD_CR_DUTY_Pos) /*!< 0x00000010 */ - -#define LCD_CR_BIAS_Pos (5U) -#define LCD_CR_BIAS_Msk (0x3U << LCD_CR_BIAS_Pos) /*!< 0x00000060 */ -#define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */ -#define LCD_CR_BIAS_0 (0x1U << LCD_CR_BIAS_Pos) /*!< 0x00000020 */ -#define LCD_CR_BIAS_1 (0x2U << LCD_CR_BIAS_Pos) /*!< 0x00000040 */ - -#define LCD_CR_MUX_SEG_Pos (7U) -#define LCD_CR_MUX_SEG_Msk (0x1U << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */ -#define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */ - -#define LCD_CR_BUFEN_Pos (8U) -#define LCD_CR_BUFEN_Msk (0x1U << LCD_CR_BUFEN_Pos) /*!< 0x00000100 */ -#define LCD_CR_BUFEN LCD_CR_BUFEN_Msk /*!< Voltage output buffer enable Bit */ - -/******************* Bit definition for LCD_FCR register ********************/ -#define LCD_FCR_HD_Pos (0U) -#define LCD_FCR_HD_Msk (0x1U << LCD_FCR_HD_Pos) /*!< 0x00000001 */ -#define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */ -#define LCD_FCR_SOFIE_Pos (1U) -#define LCD_FCR_SOFIE_Msk (0x1U << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */ -#define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */ -#define LCD_FCR_UDDIE_Pos (3U) -#define LCD_FCR_UDDIE_Msk (0x1U << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */ -#define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */ - -#define LCD_FCR_PON_Pos (4U) -#define LCD_FCR_PON_Msk (0x7U << LCD_FCR_PON_Pos) /*!< 0x00000070 */ -#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */ -#define LCD_FCR_PON_0 (0x1U << LCD_FCR_PON_Pos) /*!< 0x00000010 */ -#define LCD_FCR_PON_1 (0x2U << LCD_FCR_PON_Pos) /*!< 0x00000020 */ -#define LCD_FCR_PON_2 (0x4U << LCD_FCR_PON_Pos) /*!< 0x00000040 */ - -#define LCD_FCR_DEAD_Pos (7U) -#define LCD_FCR_DEAD_Msk (0x7U << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */ -#define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */ -#define LCD_FCR_DEAD_0 (0x1U << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */ -#define LCD_FCR_DEAD_1 (0x2U << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */ -#define LCD_FCR_DEAD_2 (0x4U << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */ - -#define LCD_FCR_CC_Pos (10U) -#define LCD_FCR_CC_Msk (0x7U << LCD_FCR_CC_Pos) /*!< 0x00001C00 */ -#define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */ -#define LCD_FCR_CC_0 (0x1U << LCD_FCR_CC_Pos) /*!< 0x00000400 */ -#define LCD_FCR_CC_1 (0x2U << LCD_FCR_CC_Pos) /*!< 0x00000800 */ -#define LCD_FCR_CC_2 (0x4U << LCD_FCR_CC_Pos) /*!< 0x00001000 */ - -#define LCD_FCR_BLINKF_Pos (13U) -#define LCD_FCR_BLINKF_Msk (0x7U << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */ -#define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */ -#define LCD_FCR_BLINKF_0 (0x1U << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */ -#define LCD_FCR_BLINKF_1 (0x2U << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */ -#define LCD_FCR_BLINKF_2 (0x4U << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */ - -#define LCD_FCR_BLINK_Pos (16U) -#define LCD_FCR_BLINK_Msk (0x3U << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */ -#define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */ -#define LCD_FCR_BLINK_0 (0x1U << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */ -#define LCD_FCR_BLINK_1 (0x2U << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */ - -#define LCD_FCR_DIV_Pos (18U) -#define LCD_FCR_DIV_Msk (0xFU << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */ -#define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */ -#define LCD_FCR_PS_Pos (22U) -#define LCD_FCR_PS_Msk (0xFU << LCD_FCR_PS_Pos) /*!< 0x03C00000 */ -#define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */ - -/******************* Bit definition for LCD_SR register *********************/ -#define LCD_SR_ENS_Pos (0U) -#define LCD_SR_ENS_Msk (0x1U << LCD_SR_ENS_Pos) /*!< 0x00000001 */ -#define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */ -#define LCD_SR_SOF_Pos (1U) -#define LCD_SR_SOF_Msk (0x1U << LCD_SR_SOF_Pos) /*!< 0x00000002 */ -#define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */ -#define LCD_SR_UDR_Pos (2U) -#define LCD_SR_UDR_Msk (0x1U << LCD_SR_UDR_Pos) /*!< 0x00000004 */ -#define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */ -#define LCD_SR_UDD_Pos (3U) -#define LCD_SR_UDD_Msk (0x1U << LCD_SR_UDD_Pos) /*!< 0x00000008 */ -#define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */ -#define LCD_SR_RDY_Pos (4U) -#define LCD_SR_RDY_Msk (0x1U << LCD_SR_RDY_Pos) /*!< 0x00000010 */ -#define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */ -#define LCD_SR_FCRSR_Pos (5U) -#define LCD_SR_FCRSR_Msk (0x1U << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */ -#define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */ - -/******************* Bit definition for LCD_CLR register ********************/ -#define LCD_CLR_SOFC_Pos (1U) -#define LCD_CLR_SOFC_Msk (0x1U << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */ -#define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */ -#define LCD_CLR_UDDC_Pos (3U) -#define LCD_CLR_UDDC_Msk (0x1U << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */ -#define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */ - -/******************* Bit definition for LCD_RAM register ********************/ -#define LCD_RAM_SEGMENT_DATA_Pos (0U) -#define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */ -#define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */ - /******************************************************************************/ /* */ /* Low Power Timer (LPTTIM) */ @@ -3818,7 +3271,6 @@ typedef struct /* */ /******************************************************************************/ -#define RCC_HSI48_SUPPORT /*!< HSI48 feature support */ #define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */ /******************** Bit definition for RCC_CR register ********************/ @@ -3898,19 +3350,6 @@ typedef struct #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */ #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */ -/******************** Bit definition for RCC_CRRCR register *****************/ -#define RCC_CRRCR_HSI48ON_Pos (0U) -#define RCC_CRRCR_HSI48ON_Msk (0x1U << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */ -#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk /*!< HSI 48MHz clock enable */ -#define RCC_CRRCR_HSI48RDY_Pos (1U) -#define RCC_CRRCR_HSI48RDY_Msk (0x1U << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */ -#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk /*!< HSI 48MHz clock ready flag */ -#define RCC_CRRCR_HSI48DIV6OUTEN_Pos (2U) -#define RCC_CRRCR_HSI48DIV6OUTEN_Msk (0x1U << RCC_CRRCR_HSI48DIV6OUTEN_Pos) /*!< 0x00000004 */ -#define RCC_CRRCR_HSI48DIV6OUTEN RCC_CRRCR_HSI48DIV6OUTEN_Msk /*!< HSI 48MHz DIV6 out enable */ -#define RCC_CRRCR_HSI48CAL_Pos (8U) -#define RCC_CRRCR_HSI48CAL_Msk (0xFFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF00 */ -#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI 48MHz clock Calibration */ /******************* Bit definition for RCC_CFGR register *******************/ /*!< SW configuration */ @@ -4064,9 +3503,6 @@ typedef struct #define RCC_CFGR_MCOSEL_LSE_Pos (24U) #define RCC_CFGR_MCOSEL_LSE_Msk (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */ #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */ -#define RCC_CFGR_MCOSEL_HSI48_Pos (27U) -#define RCC_CFGR_MCOSEL_HSI48_Msk (0x1U << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */ -#define RCC_CFGR_MCOSEL_HSI48 RCC_CFGR_MCOSEL_HSI48_Msk /*!< HSI48 clock selected as MCO source */ #define RCC_CFGR_MCOPRE_Pos (28U) #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ @@ -4118,9 +3554,6 @@ typedef struct #define RCC_CIER_MSIRDYIE_Pos (5U) #define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */ #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */ -#define RCC_CIER_HSI48RDYIE_Pos (6U) -#define RCC_CIER_HSI48RDYIE_Msk (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000040 */ -#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk /*!< HSI48 Ready Interrupt Enable */ #define RCC_CIER_CSSLSE_Pos (7U) #define RCC_CIER_CSSLSE_Msk (0x1U << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */ #define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */ @@ -4180,9 +3613,6 @@ typedef struct #define RCC_CICR_MSIRDYC_Pos (5U) #define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */ #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */ -#define RCC_CICR_HSI48RDYC_Pos (6U) -#define RCC_CICR_HSI48RDYC_Msk (0x1U << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000040 */ -#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk /*!< HSI48 Ready Interrupt Clear */ #define RCC_CICR_CSSLSEC_Pos (7U) #define RCC_CICR_CSSLSEC_Msk (0x1U << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */ #define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */ @@ -4232,12 +3662,6 @@ typedef struct #define RCC_AHBRSTR_CRCRST_Pos (12U) #define RCC_AHBRSTR_CRCRST_Msk (0x1U << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */ #define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */ -#define RCC_AHBRSTR_TSCRST_Pos (16U) -#define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x00010000 */ -#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */ -#define RCC_AHBRSTR_RNGRST_Pos (20U) -#define RCC_AHBRSTR_RNGRST_Msk (0x1U << RCC_AHBRSTR_RNGRST_Pos) /*!< 0x00100000 */ -#define RCC_AHBRSTR_RNGRST RCC_AHBRSTR_RNGRST_Msk /*!< RNG reset */ /* Reference defines */ #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */ @@ -4282,9 +3706,6 @@ typedef struct #define RCC_APB1RSTR_TIM7RST_Pos (5U) #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 clock reset */ -#define RCC_APB1RSTR_LCDRST_Pos (9U) -#define RCC_APB1RSTR_LCDRST_Msk (0x1U << RCC_APB1RSTR_LCDRST_Pos) /*!< 0x00000200 */ -#define RCC_APB1RSTR_LCDRST RCC_APB1RSTR_LCDRST_Msk /*!< LCD clock reset */ #define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ @@ -4309,18 +3730,9 @@ typedef struct #define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ -#define RCC_APB1RSTR_USBRST_Pos (23U) -#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ -#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB clock reset */ -#define RCC_APB1RSTR_CRSRST_Pos (27U) -#define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */ -#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS clock reset */ #define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ -#define RCC_APB1RSTR_DACRST_Pos (29U) -#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ -#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */ #define RCC_APB1RSTR_I2C3RST_Pos (30U) #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x40000000 */ #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk /*!< I2C 3 clock reset */ @@ -4366,12 +3778,6 @@ typedef struct #define RCC_AHBENR_CRCEN_Pos (12U) #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */ #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ -#define RCC_AHBENR_TSCEN_Pos (16U) -#define RCC_AHBENR_TSCEN_Msk (0x1U << RCC_AHBENR_TSCEN_Pos) /*!< 0x00010000 */ -#define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TSC clock enable */ -#define RCC_AHBENR_RNGEN_Pos (20U) -#define RCC_AHBENR_RNGEN_Msk (0x1U << RCC_AHBENR_RNGEN_Pos) /*!< 0x00100000 */ -#define RCC_AHBENR_RNGEN RCC_AHBENR_RNGEN_Msk /*!< RNG clock enable */ /* Reference defines */ #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ @@ -4421,9 +3827,6 @@ typedef struct #define RCC_APB1ENR_TIM7EN_Pos (5U) #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ -#define RCC_APB1ENR_LCDEN_Pos (9U) -#define RCC_APB1ENR_LCDEN_Msk (0x1U << RCC_APB1ENR_LCDEN_Pos) /*!< 0x00000200 */ -#define RCC_APB1ENR_LCDEN RCC_APB1ENR_LCDEN_Msk /*!< LCD clock enable */ #define RCC_APB1ENR_WWDGEN_Pos (11U) #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ @@ -4448,18 +3851,9 @@ typedef struct #define RCC_APB1ENR_I2C2EN_Pos (22U) #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */ -#define RCC_APB1ENR_USBEN_Pos (23U) -#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ -#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */ -#define RCC_APB1ENR_CRSEN_Pos (27U) -#define RCC_APB1ENR_CRSEN_Msk (0x1U << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */ -#define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enable */ #define RCC_APB1ENR_PWREN_Pos (28U) #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */ -#define RCC_APB1ENR_DACEN_Pos (29U) -#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ -#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC clock enable */ #define RCC_APB1ENR_I2C3EN_Pos (30U) #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x40000000 */ #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C3 clock enable */ @@ -4508,12 +3902,6 @@ typedef struct #define RCC_AHBSMENR_CRCSMEN_Pos (12U) #define RCC_AHBSMENR_CRCSMEN_Msk (0x1U << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */ #define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */ -#define RCC_AHBSMENR_TSCSMEN_Pos (16U) -#define RCC_AHBSMENR_TSCSMEN_Msk (0x1U << RCC_AHBSMENR_TSCSMEN_Pos) /*!< 0x00010000 */ -#define RCC_AHBSMENR_TSCSMEN RCC_AHBSMENR_TSCSMEN_Msk /*!< TSC clock enabled in sleep mode */ -#define RCC_AHBSMENR_RNGSMEN_Pos (20U) -#define RCC_AHBSMENR_RNGSMEN_Msk (0x1U << RCC_AHBSMENR_RNGSMEN_Pos) /*!< 0x00100000 */ -#define RCC_AHBSMENR_RNGSMEN RCC_AHBSMENR_RNGSMEN_Msk /*!< RNG clock enabled in sleep mode */ /* Reference defines */ #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */ @@ -4558,9 +3946,6 @@ typedef struct #define RCC_APB1SMENR_TIM7SMEN_Pos (5U) #define RCC_APB1SMENR_TIM7SMEN_Msk (0x1U << RCC_APB1SMENR_TIM7SMEN_Pos) /*!< 0x00000020 */ #define RCC_APB1SMENR_TIM7SMEN RCC_APB1SMENR_TIM7SMEN_Msk /*!< Timer 7 clock enabled in sleep mode */ -#define RCC_APB1SMENR_LCDSMEN_Pos (9U) -#define RCC_APB1SMENR_LCDSMEN_Msk (0x1U << RCC_APB1SMENR_LCDSMEN_Pos) /*!< 0x00000200 */ -#define RCC_APB1SMENR_LCDSMEN RCC_APB1SMENR_LCDSMEN_Msk /*!< LCD clock enabled in sleep mode */ #define RCC_APB1SMENR_WWDGSMEN_Pos (11U) #define RCC_APB1SMENR_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */ #define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */ @@ -4585,18 +3970,9 @@ typedef struct #define RCC_APB1SMENR_I2C2SMEN_Pos (22U) #define RCC_APB1SMENR_I2C2SMEN_Msk (0x1U << RCC_APB1SMENR_I2C2SMEN_Pos) /*!< 0x00400000 */ #define RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk /*!< I2C2 clock enabled in sleep mode */ -#define RCC_APB1SMENR_USBSMEN_Pos (23U) -#define RCC_APB1SMENR_USBSMEN_Msk (0x1U << RCC_APB1SMENR_USBSMEN_Pos) /*!< 0x00800000 */ -#define RCC_APB1SMENR_USBSMEN RCC_APB1SMENR_USBSMEN_Msk /*!< USB clock enabled in sleep mode */ -#define RCC_APB1SMENR_CRSSMEN_Pos (27U) -#define RCC_APB1SMENR_CRSSMEN_Msk (0x1U << RCC_APB1SMENR_CRSSMEN_Pos) /*!< 0x08000000 */ -#define RCC_APB1SMENR_CRSSMEN RCC_APB1SMENR_CRSSMEN_Msk /*!< CRS clock enabled in sleep mode */ #define RCC_APB1SMENR_PWRSMEN_Pos (28U) #define RCC_APB1SMENR_PWRSMEN_Msk (0x1U << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */ #define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */ -#define RCC_APB1SMENR_DACSMEN_Pos (29U) -#define RCC_APB1SMENR_DACSMEN_Msk (0x1U << RCC_APB1SMENR_DACSMEN_Pos) /*!< 0x20000000 */ -#define RCC_APB1SMENR_DACSMEN RCC_APB1SMENR_DACSMEN_Msk /*!< DAC clock enabled in sleep mode */ #define RCC_APB1SMENR_I2C3SMEN_Pos (30U) #define RCC_APB1SMENR_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR_I2C3SMEN_Pos) /*!< 0x40000000 */ #define RCC_APB1SMENR_I2C3SMEN RCC_APB1SMENR_I2C3SMEN_Msk /*!< I2C3 clock enabled in sleep mode */ @@ -4647,14 +4023,6 @@ typedef struct #define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */ #define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */ -/*!< HSI48 Clock source selection */ -#define RCC_CCIPR_HSI48SEL_Pos (26U) -#define RCC_CCIPR_HSI48SEL_Msk (0x1U << RCC_CCIPR_HSI48SEL_Pos) /*!< 0x04000000 */ -#define RCC_CCIPR_HSI48SEL RCC_CCIPR_HSI48SEL_Msk /*!< HSI48 RC clock source selection bit for USB and RNG*/ - -/* Legacy defines */ -#define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL - /******************* Bit definition for RCC_CSR register *******************/ #define RCC_CSR_LSION_Pos (0U) #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ @@ -4743,36 +4111,6 @@ typedef struct #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */ -/******************************************************************************/ -/* */ -/* RNG */ -/* */ -/******************************************************************************/ -/******************** Bits definition for RNG_CR register *******************/ -#define RNG_CR_RNGEN_Pos (2U) -#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk -#define RNG_CR_IE_Pos (3U) -#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk - -/******************** Bits definition for RNG_SR register *******************/ -#define RNG_SR_DRDY_Pos (0U) -#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ -#define RNG_SR_DRDY RNG_SR_DRDY_Msk -#define RNG_SR_CECS_Pos (1U) -#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */ -#define RNG_SR_CECS RNG_SR_CECS_Msk -#define RNG_SR_SECS_Pos (2U) -#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */ -#define RNG_SR_SECS RNG_SR_SECS_Msk -#define RNG_SR_CEIS_Pos (5U) -#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ -#define RNG_SR_CEIS RNG_SR_CEIS_Msk -#define RNG_SR_SEIS_Pos (6U) -#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ -#define RNG_SR_SEIS RNG_SR_SEIS_Msk - /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ @@ -5865,9 +5203,6 @@ typedef struct #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U) #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1U << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */ #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */ -#define SYSCFG_CFGR3_ENREF_HSI48_Pos (13U) -#define SYSCFG_CFGR3_ENREF_HSI48_Msk (0x1U << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */ -#define SYSCFG_CFGR3_ENREF_HSI48 SYSCFG_CFGR3_ENREF_HSI48_Msk /*!< VREFINT reference or 48 MHz RC oscillator enable bit */ #define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U) #define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1U << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */ #define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */ @@ -6396,547 +5731,6 @@ typedef struct #define TIM3_OR_TI4_RMP TIM3_OR_TI4_RMP_Msk /*!