mirror of https://github.com/ARMmbed/mbed-os.git
Put NUCLEO_F411RE specific files
bcostm
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;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
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;* File Name : startup_stm32f411xe.s
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;* Author : MCD Application Team
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;* Version : V2.1.0
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;* Date : 19-June-2014
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;* Description : STM32F411xExx devices vector table for MDK-ARM_MICRO toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == Reset_Handler
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;* - Set the vector table entries with the exceptions ISR address
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;* - Branches to __main in the C library (which eventually
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;* calls main()).
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;* After Reset the CortexM4 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;* <<< Use Configuration Wizard in Context Menu >>>
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;*******************************************************************************
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;
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;* Redistribution and use in source and binary forms, with or without modification,
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;* are permitted provided that the following conditions are met:
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;* 1. Redistributions of source code must retain the above copyright notice,
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;* this list of conditions and the following disclaimer.
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;* 2. Redistributions in binary form must reproduce the above copyright notice,
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;* this list of conditions and the following disclaimer in the documentation
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;* and/or other materials provided with the distribution.
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;* 3. Neither the name of STMicroelectronics nor the names of its contributors
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;* may be used to endorse or promote products derived from this software
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;* without specific prior written permission.
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;*
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;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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;*******************************************************************************
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; Amount of memory (in bytes) allocated for Stack
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; Tailor this value to your application needs
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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EXPORT __initial_sp
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Stack_Mem SPACE Stack_Size
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__initial_sp EQU 0x20020000 ; Top of RAM
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000400
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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EXPORT __heap_base
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EXPORT __heap_limit
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit EQU (__initial_sp - Stack_Size)
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window WatchDog
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DCD PVD_IRQHandler ; PVD through EXTI Line detection
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DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
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DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
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DCD FLASH_IRQHandler ; FLASH
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DCD RCC_IRQHandler ; RCC
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DCD EXTI0_IRQHandler ; EXTI Line0
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DCD EXTI1_IRQHandler ; EXTI Line1
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DCD EXTI2_IRQHandler ; EXTI Line2
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DCD EXTI3_IRQHandler ; EXTI Line3
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DCD EXTI4_IRQHandler ; EXTI Line4
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DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
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DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
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DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
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DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
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DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
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DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
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DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
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DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD EXTI9_5_IRQHandler ; External Line[9:5]s
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DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
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DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
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DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
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DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
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DCD TIM2_IRQHandler ; TIM2
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DCD TIM3_IRQHandler ; TIM3
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DCD TIM4_IRQHandler ; TIM4
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DCD I2C1_EV_IRQHandler ; I2C1 Event
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DCD I2C1_ER_IRQHandler ; I2C1 Error
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DCD I2C2_EV_IRQHandler ; I2C2 Event
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DCD I2C2_ER_IRQHandler ; I2C2 Error
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DCD SPI1_IRQHandler ; SPI1
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DCD SPI2_IRQHandler ; SPI2
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DCD USART1_IRQHandler ; USART1
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DCD USART2_IRQHandler ; USART2
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DCD 0 ; Reserved
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DCD EXTI15_10_IRQHandler ; External Line[15:10]s
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DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
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DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
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DCD 0 ; Reserved
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DCD SDIO_IRQHandler ; SDIO
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DCD TIM5_IRQHandler ; TIM5
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DCD SPI3_IRQHandler ; SPI3
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
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DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
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DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
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DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
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DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD OTG_FS_IRQHandler ; USB OTG FS
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DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
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DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
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DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
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DCD USART6_IRQHandler ; USART6
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DCD I2C3_EV_IRQHandler ; I2C3 event
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DCD I2C3_ER_IRQHandler ; I2C3 error
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD FPU_IRQHandler ; FPU
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SPI4_IRQHandler ; SPI4
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DCD SPI5_IRQHandler ; SPI5
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT WWDG_IRQHandler [WEAK]
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EXPORT PVD_IRQHandler [WEAK]
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EXPORT TAMP_STAMP_IRQHandler [WEAK]
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EXPORT RTC_WKUP_IRQHandler [WEAK]
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EXPORT FLASH_IRQHandler [WEAK]
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EXPORT RCC_IRQHandler [WEAK]
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EXPORT EXTI0_IRQHandler [WEAK]
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EXPORT EXTI1_IRQHandler [WEAK]
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EXPORT EXTI2_IRQHandler [WEAK]
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EXPORT EXTI3_IRQHandler [WEAK]
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EXPORT EXTI4_IRQHandler [WEAK]
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EXPORT DMA1_Stream0_IRQHandler [WEAK]
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EXPORT DMA1_Stream1_IRQHandler [WEAK]
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EXPORT DMA1_Stream2_IRQHandler [WEAK]
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EXPORT DMA1_Stream3_IRQHandler [WEAK]
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EXPORT DMA1_Stream4_IRQHandler [WEAK]
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EXPORT DMA1_Stream5_IRQHandler [WEAK]
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EXPORT DMA1_Stream6_IRQHandler [WEAK]
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EXPORT ADC_IRQHandler [WEAK]
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EXPORT EXTI9_5_IRQHandler [WEAK]
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EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
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EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
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EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
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EXPORT TIM1_CC_IRQHandler [WEAK]
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EXPORT TIM2_IRQHandler [WEAK]
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EXPORT TIM3_IRQHandler [WEAK]
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EXPORT TIM4_IRQHandler [WEAK]
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EXPORT I2C1_EV_IRQHandler [WEAK]
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EXPORT I2C1_ER_IRQHandler [WEAK]
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EXPORT I2C2_EV_IRQHandler [WEAK]
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EXPORT I2C2_ER_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT SPI2_IRQHandler [WEAK]
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EXPORT USART1_IRQHandler [WEAK]
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EXPORT USART2_IRQHandler [WEAK]
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EXPORT EXTI15_10_IRQHandler [WEAK]
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EXPORT RTC_Alarm_IRQHandler [WEAK]
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EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
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EXPORT DMA1_Stream7_IRQHandler [WEAK]
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EXPORT SDIO_IRQHandler [WEAK]
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EXPORT TIM5_IRQHandler [WEAK]
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EXPORT SPI3_IRQHandler [WEAK]
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EXPORT DMA2_Stream0_IRQHandler [WEAK]
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EXPORT DMA2_Stream1_IRQHandler [WEAK]
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EXPORT DMA2_Stream2_IRQHandler [WEAK]
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EXPORT DMA2_Stream3_IRQHandler [WEAK]
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EXPORT DMA2_Stream4_IRQHandler [WEAK]
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EXPORT OTG_FS_IRQHandler [WEAK]
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EXPORT DMA2_Stream5_IRQHandler [WEAK]
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EXPORT DMA2_Stream6_IRQHandler [WEAK]
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EXPORT DMA2_Stream7_IRQHandler [WEAK]
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EXPORT USART6_IRQHandler [WEAK]
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EXPORT I2C3_EV_IRQHandler [WEAK]
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EXPORT I2C3_ER_IRQHandler [WEAK]
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EXPORT FPU_IRQHandler [WEAK]
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EXPORT SPI4_IRQHandler [WEAK]
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EXPORT SPI5_IRQHandler [WEAK]
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WWDG_IRQHandler
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PVD_IRQHandler
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TAMP_STAMP_IRQHandler
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RTC_WKUP_IRQHandler
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FLASH_IRQHandler
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RCC_IRQHandler
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EXTI0_IRQHandler
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EXTI1_IRQHandler
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EXTI2_IRQHandler
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EXTI3_IRQHandler
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EXTI4_IRQHandler
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DMA1_Stream0_IRQHandler
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DMA1_Stream1_IRQHandler
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DMA1_Stream2_IRQHandler
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DMA1_Stream3_IRQHandler
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DMA1_Stream4_IRQHandler
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DMA1_Stream5_IRQHandler
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DMA1_Stream6_IRQHandler
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ADC_IRQHandler
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EXTI9_5_IRQHandler
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TIM1_BRK_TIM9_IRQHandler
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TIM1_UP_TIM10_IRQHandler
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TIM1_TRG_COM_TIM11_IRQHandler
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TIM1_CC_IRQHandler
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TIM2_IRQHandler
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TIM3_IRQHandler
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TIM4_IRQHandler
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I2C1_EV_IRQHandler
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I2C1_ER_IRQHandler
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I2C2_EV_IRQHandler
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I2C2_ER_IRQHandler
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SPI1_IRQHandler
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SPI2_IRQHandler
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USART1_IRQHandler
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USART2_IRQHandler
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EXTI15_10_IRQHandler
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RTC_Alarm_IRQHandler
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OTG_FS_WKUP_IRQHandler
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DMA1_Stream7_IRQHandler
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SDIO_IRQHandler
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TIM5_IRQHandler
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SPI3_IRQHandler
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DMA2_Stream0_IRQHandler
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DMA2_Stream1_IRQHandler
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DMA2_Stream2_IRQHandler
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DMA2_Stream3_IRQHandler
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DMA2_Stream4_IRQHandler
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OTG_FS_IRQHandler
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DMA2_Stream5_IRQHandler
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DMA2_Stream6_IRQHandler
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DMA2_Stream7_IRQHandler
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USART6_IRQHandler
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I2C3_EV_IRQHandler
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I2C3_ER_IRQHandler
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FPU_IRQHandler
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SPI4_IRQHandler
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SPI5_IRQHandler
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B .
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ENDP
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ALIGN
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END
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;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
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@ -0,0 +1,45 @@
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; Scatter-Loading Description File
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright (c) 2014, STMicroelectronics
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are met:
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;
|
||||||
|
; 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
; this list of conditions and the following disclaimer.
|
||||||
|
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
; this list of conditions and the following disclaimer in the documentation
|
||||||
|
; and/or other materials provided with the distribution.
|
||||||
|
; 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
; may be used to endorse or promote products derived from this software
|
||||||
|
; without specific prior written permission.
|
||||||
|
;
|
||||||
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
|
||||||
|
; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
|
||||||
|
LR_IROM1 0x08000000 0x80000 { ; load region size_region
|
||||||
|
|
||||||
|
ER_IROM1 0x08000000 0x80000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
|
||||||
|
; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM
|
||||||
|
RW_IRAM1 (0x20000000+0x198) (0x20000-0x198) { ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,56 @@
|
||||||
|
/* mbed Microcontroller Library - stackheap
|
||||||
|
* Setup a fixed single stack/heap memory model,
|
||||||
|
* between the top of the RW/ZI region and the stackpointer
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2014, STMicroelectronics
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rt_misc.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||||
|
|
||||||
|
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||||
|
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||||
|
uint32_t sp_limit = __current_sp();
|
||||||
|
|
||||||
|
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||||
|
|
||||||
|
struct __initial_stackheap r;
|
||||||
|
r.heap_base = zi_limit;
|
||||||
|
r.heap_limit = sp_limit;
|
||||||
|
return r;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,346 @@
|
||||||
|
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f411xe.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V2.1.0
|
||||||
|
;* Date : 19-June-2014
|
||||||
|
;* Description : STM32F411xExx devices vector table for MDK-ARM_STD toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the CortexM4 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
;*******************************************************************************
|
||||||
|
;
|
||||||
|
;* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;* are permitted provided that the following conditions are met:
|
||||||
|
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer.
|
||||||
|
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer in the documentation
|
||||||
|
;* and/or other materials provided with the distribution.
|
||||||
|
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
;* may be used to endorse or promote products derived from this software
|
||||||
|
;* without specific prior written permission.
|
||||||
|
;*
|
||||||
|
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;
|
||||||
|
;*******************************************************************************
|
||||||
|
|
||||||
|
__initial_sp EQU 0x20020000 ; Top of RAM
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window WatchDog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||||
|
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||||
|
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||||
|
DCD FLASH_IRQHandler ; FLASH
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||||
|
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||||
|
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||||
|
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||||
|
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||||
|
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||||
|
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||||
|
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||||
|
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||||
|
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
|
||||||
|
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
|
||||||
|
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||||
|
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SDIO_IRQHandler ; SDIO
|
||||||
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||||
|
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||||
|
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||||
|
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||||
|
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||||
|
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||||
|
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||||
|
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||||
|
DCD USART6_IRQHandler ; USART6
|
||||||
|
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||||
|
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD FPU_IRQHandler ; FPU
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SPI4_IRQHandler ; SPI4
|
||||||
|
DCD SPI5_IRQHandler ; SPI5
|
||||||
|
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMP_STAMP_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream6_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||||
|
EXPORT SDIO_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM5_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream4_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream7_IRQHandler [WEAK]
|
||||||
|
EXPORT USART6_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT FPU_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI4_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI5_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_IRQHandler
|
||||||
|
TAMP_STAMP_IRQHandler
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Stream0_IRQHandler
|
||||||
|
DMA1_Stream1_IRQHandler
|
||||||
|
DMA1_Stream2_IRQHandler
|
||||||
|
DMA1_Stream3_IRQHandler
|
||||||
|
DMA1_Stream4_IRQHandler
|
||||||
|
DMA1_Stream5_IRQHandler
|
||||||
|
DMA1_Stream6_IRQHandler
|
||||||
|
ADC_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM1_BRK_TIM9_IRQHandler
|
||||||
|
TIM1_UP_TIM10_IRQHandler
|
||||||
|
TIM1_TRG_COM_TIM11_IRQHandler
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM4_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
OTG_FS_WKUP_IRQHandler
|
||||||
|
DMA1_Stream7_IRQHandler
|
||||||
|
SDIO_IRQHandler
|
||||||
|
TIM5_IRQHandler
|
||||||
|
SPI3_IRQHandler
|
||||||
|
DMA2_Stream0_IRQHandler
|
||||||
|
DMA2_Stream1_IRQHandler
|
||||||
|
DMA2_Stream2_IRQHandler
|
||||||
|
DMA2_Stream3_IRQHandler
|
||||||
|
DMA2_Stream4_IRQHandler
|
||||||
|
OTG_FS_IRQHandler
|
||||||
|
DMA2_Stream5_IRQHandler
|
||||||
|
DMA2_Stream6_IRQHandler
|
||||||
|
DMA2_Stream7_IRQHandler
|
||||||
|
USART6_IRQHandler
|
||||||
|
I2C3_EV_IRQHandler
|
||||||
|
I2C3_ER_IRQHandler
|
||||||
|
FPU_IRQHandler
|
||||||
|
SPI4_IRQHandler
|
||||||
|
SPI5_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
|
|
@ -0,0 +1,45 @@
|
||||||
|
; Scatter-Loading Description File
|
||||||
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
; Copyright (c) 2014, STMicroelectronics
|
||||||
|
; All rights reserved.
|
||||||
|
;
|
||||||
|
; Redistribution and use in source and binary forms, with or without
|
||||||
|
; modification, are permitted provided that the following conditions are met:
|
||||||
|
;
|
||||||
|
; 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
; this list of conditions and the following disclaimer.
|
||||||
|
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
; this list of conditions and the following disclaimer in the documentation
|
||||||
|
; and/or other materials provided with the distribution.
|
||||||
|
; 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
; may be used to endorse or promote products derived from this software
|
||||||
|
; without specific prior written permission.
|
||||||
|
;
|
||||||
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
|
||||||
|
; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
|
||||||
|
LR_IROM1 0x08000000 0x80000 { ; load region size_region
|
||||||
|
|
||||||
|
ER_IROM1 0x08000000 0x80000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
|
||||||
|
; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM
|
||||||
|
RW_IRAM1 (0x20000000+0x198) (0x20000-0x198) { ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,56 @@
|
||||||
|
/* mbed Microcontroller Library - stackheap
|
||||||
|
* Setup a fixed single stack/heap memory model,
|
||||||
|
* between the top of the RW/ZI region and the stackpointer
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2014, STMicroelectronics
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rt_misc.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||||
|
|
||||||
|
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||||
|
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||||
|
uint32_t sp_limit = __current_sp();
|
||||||
|
|
||||||
|
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||||
|
|
||||||
|
struct __initial_stackheap r;
|
||||||
|
r.heap_base = zi_limit;
|
||||||
|
r.heap_limit = sp_limit;
|
||||||
|
return r;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,151 @@
|
||||||
|
/* Linker script for STM32F411 */
|
||||||
|
|
||||||
|
/* Linker script to configure memory regions. */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||||
|
/* CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K */
|
||||||
|
RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Linker script to place sections and symbol values. Should be used together
|
||||||
|
* with other linker script that defines memory regions FLASH and RAM.
|
||||||
|
* It references following symbols, which must be defined in code:
|
||||||
|
* Reset_Handler : Entry of reset handler
|
||||||
|
*
|
||||||
|
* It defines following symbols, which code can use without definition:
|
||||||
|
* __exidx_start
|
||||||
|
* __exidx_end
|
||||||
|
* __etext
|
||||||
|
* __data_start__
|
||||||
|
* __preinit_array_start
|
||||||
|
* __preinit_array_end
|
||||||
|
* __init_array_start
|
||||||
|
* __init_array_end
|
||||||
|
* __fini_array_start
|
||||||
|
* __fini_array_end
|
||||||
|
* __data_end__
|
||||||
|
* __bss_start__
|
||||||
|
* __bss_end__
|
||||||
|
* __end__
|
||||||
|
* end
|
||||||
|
* __HeapLimit
|
||||||
|
* __StackLimit
|
||||||
|
* __StackTop
|
||||||
|
* __stack
|
||||||
|
*/
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
KEEP(*(.isr_vector))
|
||||||
|
*(.text*)
|
||||||
|
|
||||||
|
KEEP(*(.init))
|
||||||
|
KEEP(*(.fini))
|
||||||
|
|
||||||
|
/* .ctors */
|
||||||
|
*crtbegin.o(.ctors)
|
||||||
|
*crtbegin?.o(.ctors)
|
||||||
|
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||||
|
*(SORT(.ctors.*))
|
||||||
|
*(.ctors)
|
||||||
|
|
||||||
|
/* .dtors */
|
||||||
|
*crtbegin.o(.dtors)
|
||||||
|
*crtbegin?.o(.dtors)
|
||||||
|
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||||
|
*(SORT(.dtors.*))
|
||||||
|
*(.dtors)
|
||||||
|
|
||||||
|
*(.rodata*)
|
||||||
|
|
||||||
|
KEEP(*(.eh_frame*))
|
||||||
|
} > FLASH
|
||||||
|
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} > FLASH
|
||||||
|
|
||||||
|
__exidx_start = .;
|
||||||
|
.ARM.exidx :
|
||||||
|
{
|
||||||
|
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||||
|
} > FLASH
|
||||||
|
__exidx_end = .;
|
||||||
|
|
||||||
|
__etext = .;
|
||||||
|
|
||||||
|
.data : AT (__etext)
|
||||||
|
{
|
||||||
|
__data_start__ = .;
|
||||||
|
*(vtable)
|
||||||
|
*(.data*)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* preinit data */
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP(*(.preinit_array))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* init data */
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP(*(SORT(.init_array.*)))
|
||||||
|
KEEP(*(.init_array))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* finit data */
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP(*(SORT(.fini_array.*)))
|
||||||
|
KEEP(*(.fini_array))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
|
||||||
|
KEEP(*(.jcr*))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* All data end */
|
||||||
|
__data_end__ = .;
|
||||||
|
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__bss_start__ = .;
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__bss_end__ = .;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
.heap (COPY):
|
||||||
|
{
|
||||||
|
__end__ = .;
|
||||||
|
end = __end__;
|
||||||
|
*(.heap*)
|
||||||
|
__HeapLimit = .;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||||
|
* used for linker to calculate size of stack sections, and assign
|
||||||
|
* values to stack symbols later */
|
||||||
|
.stack_dummy (COPY):
|
||||||
|
{
|
||||||
|
*(.stack*)
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Set stack top to end of RAM, and stack limit move down by
|
||||||
|
* size of stack_dummy section */
|
||||||
|
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||||
|
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||||
|
PROVIDE(__stack = __StackTop);
|
||||||
|
|
||||||
|
/* Check if data + heap + stack exceeds RAM limit */
|
||||||
|
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,297 @@
|
||||||
|
/* File: startup_STM32F40x.S
|
||||||
|
* Purpose: startup file for Cortex-M4 devices. Should use with
|
||||||
|
* GCC for ARM Embedded Processors
|
||||||
|
* Version: V1.4
|
||||||
|
* Date: 09 July 2012
|
||||||
|
*
|
||||||
|
* Copyright (c) 2011, 2012, ARM Limited
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
* Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
* Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
* Neither the name of the ARM Limited nor the
|
||||||
|
names of its contributors may be used to endorse or promote products
|
||||||
|
derived from this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||||
|
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||||
|
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||||
|
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
.syntax unified
|
||||||
|
.arch armv7-m
|
||||||
|
|
||||||
|
.section .stack
|
||||||
|
.align 3
|
||||||
|
#ifdef __STACK_SIZE
|
||||||
|
.equ Stack_Size, __STACK_SIZE
|
||||||
|
#else
|
||||||
|
.equ Stack_Size, 0xc00
|
||||||
|
#endif
|
||||||
|
.globl __StackTop
|
||||||
|
.globl __StackLimit
|
||||||
|
__StackLimit:
|
||||||
|
.space Stack_Size
|
||||||
|
.size __StackLimit, . - __StackLimit
|
||||||
|
__StackTop:
|
||||||
|
.size __StackTop, . - __StackTop
|
||||||
|
|
||||||
|
.section .heap
|
||||||
|
.align 3
|
||||||
|
#ifdef __HEAP_SIZE
|
||||||
|
.equ Heap_Size, __HEAP_SIZE
|
||||||
|
#else
|
||||||
|
.equ Heap_Size, 0x400
|
||||||
|
#endif
|
||||||
|
.globl __HeapBase
|
||||||
|
.globl __HeapLimit
|
||||||
|
__HeapBase:
|
||||||
|
.if Heap_Size
|
||||||
|
.space Heap_Size
|
||||||
|
.endif
|
||||||
|
.size __HeapBase, . - __HeapBase
|
||||||
|
__HeapLimit:
|
||||||
|
.size __HeapLimit, . - __HeapLimit
|
||||||
|
|
||||||
|
.section .isr_vector
|
||||||
|
.align 2
|
||||||
|
.globl __isr_vector
|
||||||
|
__isr_vector:
|
||||||
|
.long __StackTop /* Top of Stack */
|
||||||
|
.long Reset_Handler /* Reset Handler */
|
||||||
|
.long NMI_Handler /* NMI Handler */
|
||||||
|
.long HardFault_Handler /* Hard Fault Handler */
|
||||||
|
.long MemManage_Handler /* MPU Fault Handler */
|
||||||
|
.long BusFault_Handler /* Bus Fault Handler */
|
||||||
|
.long UsageFault_Handler /* Usage Fault Handler */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long SVC_Handler /* SVCall Handler */
|
||||||
|
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long PendSV_Handler /* PendSV Handler */
|
||||||
|
.long SysTick_Handler /* SysTick Handler */
|
||||||
|
|
||||||
|
/* External interrupts */
|
||||||
|
.long WWDG_IRQHandler /* Window WatchDog */
|
||||||
|
.long PVD_IRQHandler /* PVD through EXTI Line detection */
|
||||||
|
.long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||||
|
.long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||||
|
.long FLASH_IRQHandler /* FLASH */
|
||||||
|
.long RCC_IRQHandler /* RCC */
|
||||||
|
.long EXTI0_IRQHandler /* EXTI Line0 */
|
||||||
|
.long EXTI1_IRQHandler /* EXTI Line1 */
|
||||||
|
.long EXTI2_IRQHandler /* EXTI Line2 */
|
||||||
|
.long EXTI3_IRQHandler /* EXTI Line3 */
|
||||||
|
.long EXTI4_IRQHandler /* EXTI Line4 */
|
||||||
|
.long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||||
|
.long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||||
|
.long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||||
|
.long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||||
|
.long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||||
|
.long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||||
|
.long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||||
|
.long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||||
|
.long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
|
||||||
|
.long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
|
||||||
|
.long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
|
||||||
|
.long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
|
.long TIM2_IRQHandler /* TIM2 */
|
||||||
|
.long TIM3_IRQHandler /* TIM3 */
|
||||||
|
.long TIM4_IRQHandler /* TIM4 */
|
||||||
|
.long I2C1_EV_IRQHandler /* I2C1 Event */
|
||||||
|
.long I2C1_ER_IRQHandler /* I2C1 Error */
|
||||||
|
.long I2C2_EV_IRQHandler /* I2C2 Event */
|
||||||
|
.long I2C2_ER_IRQHandler /* I2C2 Error */
|
||||||
|
.long SPI1_IRQHandler /* SPI1 */
|
||||||
|
.long SPI2_IRQHandler /* SPI2 */
|
||||||
|
.long USART1_IRQHandler /* USART1 */
|
||||||
|
.long USART2_IRQHandler /* USART2 */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||||
|
.long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||||
|
.long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long SDIO_IRQHandler /* SDIO */
|
||||||
|
.long TIM5_IRQHandler /* TIM5 */
|
||||||
|
.long SPI3_IRQHandler /* SPI3 */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||||
|
.long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||||
|
.long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||||
|
.long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||||
|
.long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long OTG_FS_IRQHandler /* USB OTG FS */
|
||||||
|
.long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||||
|
.long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||||
|
.long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||||
|
.long USART6_IRQHandler /* USART6 */
|
||||||
|
.long I2C3_EV_IRQHandler /* I2C3 event */
|
||||||
|
.long I2C3_ER_IRQHandler /* I2C3 error */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long 0 /* Reserved */
|
||||||
|
.long FPU_IRQHandler /* FPU */
|
||||||
|
.long SPI4_IRQHandler /* SPI4 */
|
||||||
|
.long SPI5_IRQHandler /* SPI5 */
|
||||||
|
|
||||||
|
.size __isr_vector, . - __isr_vector
|
||||||
|
|
||||||
|
.text
|
||||||
|
.thumb
|
||||||
|
.thumb_func
|
||||||
|
.align 2
|
||||||
|
.globl Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
/* Loop to copy data from read only memory to RAM. The ranges
|
||||||
|
* of copy from/to are specified by following symbols evaluated in
|
||||||
|
* linker script.
|
||||||
|
* __etext: End of code section, i.e., begin of data sections to copy from.
|
||||||
|
* __data_start__/__data_end__: RAM address range that data should be
|
||||||
|
* copied to. Both must be aligned to 4 bytes boundary. */
|
||||||
|
|
||||||
|
ldr r1, =__etext
|
||||||
|
ldr r2, =__data_start__
|
||||||
|
ldr r3, =__data_end__
|
||||||
|
|
||||||
|
.LC0:
|
||||||
|
cmp r2, r3
|
||||||
|
ittt lt
|
||||||
|
ldrlt r0, [r1], #4
|
||||||
|
strlt r0, [r2], #4
|
||||||
|
blt .LC0
|
||||||
|
|
||||||
|
ldr r0, =SystemInit
|
||||||
|
blx r0
|
||||||
|
ldr r0, =_start
|
||||||
|
bx r0
|
||||||
|
.pool
|
||||||
|
.size Reset_Handler, . - Reset_Handler
|
||||||
|
|
||||||
|
.text
|
||||||
|
/* Macro to define default handlers. Default handler
|
||||||
|
* will be weak symbol and just dead loops. They can be
|
||||||
|
* overwritten by other handlers */
|
||||||
|
.macro def_default_handler handler_name
|
||||||
|
.align 1
|
||||||
|
.thumb_func
|
||||||
|
.weak \handler_name
|
||||||
|
.type \handler_name, %function
|
||||||
|
\handler_name :
|
||||||
|
b .
|
||||||
|
.size \handler_name, . - \handler_name
|
||||||
|
.endm
|
||||||
|
|
||||||
|
def_default_handler NMI_Handler
|
||||||
|
def_default_handler HardFault_Handler
|
||||||
|
def_default_handler MemManage_Handler
|
||||||
|
def_default_handler BusFault_Handler
|
||||||
|
def_default_handler UsageFault_Handler
|
||||||
|
def_default_handler SVC_Handler
|
||||||
|
def_default_handler DebugMon_Handler
|
||||||
|
def_default_handler PendSV_Handler
|
||||||
|
def_default_handler SysTick_Handler
|
||||||
|
def_default_handler Default_Handler
|
||||||
|
|
||||||
|
.macro def_irq_default_handler handler_name
|
||||||
|
.weak \handler_name
|
||||||
|
.set \handler_name, Default_Handler
|
||||||
|
.endm
|
||||||
|
|
||||||
|
def_irq_default_handler WWDG_IRQHandler
|
||||||
|
def_irq_default_handler PVD_IRQHandler
|
||||||
|
def_irq_default_handler TAMP_STAMP_IRQHandler
|
||||||
|
def_irq_default_handler RTC_WKUP_IRQHandler
|
||||||
|
def_irq_default_handler FLASH_IRQHandler
|
||||||
|
def_irq_default_handler RCC_IRQHandler
|
||||||
|
def_irq_default_handler EXTI0_IRQHandler
|
||||||
|
def_irq_default_handler EXTI1_IRQHandler
|
||||||
|
def_irq_default_handler EXTI2_IRQHandler
|
||||||
|
def_irq_default_handler EXTI3_IRQHandler
|
||||||
|
def_irq_default_handler EXTI4_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream0_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream1_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream2_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream3_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream4_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream5_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream6_IRQHandler
|
||||||
|
def_irq_default_handler ADC_IRQHandler
|
||||||
|
def_irq_default_handler EXTI9_5_IRQHandler
|
||||||
|
def_irq_default_handler TIM1_BRK_TIM9_IRQHandler
|
||||||
|
def_irq_default_handler TIM1_UP_TIM10_IRQHandler
|
||||||
|
def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler
|
||||||
|
def_irq_default_handler TIM1_CC_IRQHandler
|
||||||
|
def_irq_default_handler TIM2_IRQHandler
|
||||||
|
def_irq_default_handler TIM3_IRQHandler
|
||||||
|
def_irq_default_handler TIM4_IRQHandler
|
||||||
|
def_irq_default_handler I2C1_EV_IRQHandler
|
||||||
|
def_irq_default_handler I2C1_ER_IRQHandler
|
||||||
|
def_irq_default_handler I2C2_EV_IRQHandler
|
||||||
|
def_irq_default_handler I2C2_ER_IRQHandler
|
||||||
|
def_irq_default_handler SPI1_IRQHandler
|
||||||
|
def_irq_default_handler SPI2_IRQHandler
|
||||||
|
def_irq_default_handler USART1_IRQHandler
|
||||||
|
def_irq_default_handler USART2_IRQHandler
|
||||||
|
def_irq_default_handler EXTI15_10_IRQHandler
|
||||||
|
def_irq_default_handler RTC_Alarm_IRQHandler
|
||||||
|
def_irq_default_handler OTG_FS_WKUP_IRQHandler
|
||||||
|
def_irq_default_handler DMA1_Stream7_IRQHandler
|
||||||
|
def_irq_default_handler SDIO_IRQHandler
|
||||||
|
def_irq_default_handler TIM5_IRQHandler
|
||||||
|
def_irq_default_handler SPI3_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream0_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream1_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream2_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream3_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream4_IRQHandler
|
||||||
|
def_irq_default_handler OTG_FS_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream5_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream6_IRQHandler
|
||||||
|
def_irq_default_handler DMA2_Stream7_IRQHandler
|
||||||
|
def_irq_default_handler USART6_IRQHandler
|
||||||
|
def_irq_default_handler I2C3_EV_IRQHandler
|
||||||
|
def_irq_default_handler I2C3_ER_IRQHandler
|
||||||
|
def_irq_default_handler FPU_IRQHandler
|
||||||
|
def_irq_default_handler SPI4_IRQHandler
|
||||||
|
def_irq_default_handler SPI5_IRQHandler
|
||||||
|
def_irq_default_handler DEF_IRQHandler
|
||||||
|
|
||||||
|
.end
|
||||||
|
|
@ -0,0 +1,523 @@
|
||||||
|
;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f411xe.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V2.1.0
|
||||||
|
;* Date : 19-June-2014
|
||||||
|
;* Description : STM32F411xExx devices vector table for EWARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == _iar_program_start,
|
||||||
|
;* - Set the vector table entries with the exceptions ISR
|
||||||
|
;* address.
|
||||||
|
;* - Configure the system clock
|
||||||
|
;* - Branches to main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;********************************************************************************
|
||||||
|
;*
|
||||||
|
;* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;* are permitted provided that the following conditions are met:
|
||||||
|
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer.
|
||||||
|
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer in the documentation
|
||||||
|
;* and/or other materials provided with the distribution.
|
||||||
|
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
;* may be used to endorse or promote products derived from this software
|
||||||
|
;* without specific prior written permission.
|
||||||
|
;*
|
||||||
|
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;*
|
||||||
|
;*******************************************************************************
|
||||||
|
;
|
||||||
|
;
|
||||||
|
; The modules in this file are included in the libraries, and may be replaced
|
||||||
|
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||||
|
; a user defined start symbol.
|
||||||
|
; To override the cstartup defined in the library, simply add your modified
|
||||||
|
; version to the workbench project.
|
||||||
|
;
|
||||||
|
; The vector table is normally located at address 0.
|
||||||
|
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||||
|
; The name "__vector_table" has special meaning for C-SPY:
|
||||||
|
; it is where the SP start value is found, and the NVIC vector
|
||||||
|
; table register (VTOR) is initialized to this address if != 0.
|
||||||
|
;
|
||||||
|
; Cortex-M version
|
||||||
|
;
|
||||||
|
|
||||||
|
MODULE ?cstartup
|
||||||
|
|
||||||
|
;; Forward declaration of sections.
|
||||||
|
SECTION CSTACK:DATA:NOROOT(3)
|
||||||
|
|
||||||
|
SECTION .intvec:CODE:NOROOT(2)
|
||||||
|
|
||||||
|
EXTERN __iar_program_start
|
||||||
|
EXTERN SystemInit
|
||||||
|
PUBLIC __vector_table
|
||||||
|
|
||||||
|
DATA
|
||||||
|
__vector_table
|
||||||
|
DCD sfe(CSTACK)
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window WatchDog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||||
|
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||||
|
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||||
|
DCD FLASH_IRQHandler ; FLASH
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||||
|
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||||
|
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||||
|
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||||
|
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||||
|
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||||
|
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||||
|
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||||
|
DCD ADC_IRQHandler ; ADC1
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||||
|
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
|
||||||
|
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
|
||||||
|
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||||
|
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SDIO_IRQHandler ; SDIO
|
||||||
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||||
|
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||||
|
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||||
|
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||||
|
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||||
|
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||||
|
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||||
|
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||||
|
DCD USART6_IRQHandler ; USART6
|
||||||
|
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||||
|
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD FPU_IRQHandler ; FPU
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SPI4_IRQHandler ; SPI4
|
||||||
|
DCD SPI5_IRQHandler ; SPI5
|
||||||
|
|
||||||
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
;;
|
||||||
|
;; Default interrupt handlers.
|
||||||
|
;;
|
||||||
|
THUMB
|
||||||
|
PUBWEAK Reset_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||||
|
Reset_Handler
|
||||||
|
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__iar_program_start
|
||||||
|
BX R0
|
||||||
|
|
||||||
|
PUBWEAK NMI_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
NMI_Handler
|
||||||
|
B NMI_Handler
|
||||||
|
|
||||||
|
PUBWEAK HardFault_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
HardFault_Handler
|
||||||
|
B HardFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK MemManage_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
MemManage_Handler
|
||||||
|
B MemManage_Handler
|
||||||
|
|
||||||
|
PUBWEAK BusFault_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
BusFault_Handler
|
||||||
|
B BusFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK UsageFault_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
UsageFault_Handler
|
||||||
|
B UsageFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK SVC_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
SVC_Handler
|
||||||
|
B SVC_Handler
|
||||||
|
|
||||||
|
PUBWEAK DebugMon_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DebugMon_Handler
|
||||||
|
B DebugMon_Handler
|
||||||
|
|
||||||
|
PUBWEAK PendSV_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PendSV_Handler
|
||||||
|
B PendSV_Handler
|
||||||
|
|
||||||
|
PUBWEAK SysTick_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
SysTick_Handler
|
||||||
|
B SysTick_Handler
|
||||||
|
|
||||||
|
PUBWEAK WWDG_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
WWDG_IRQHandler
|
||||||
|
B WWDG_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PVD_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PVD_IRQHandler
|
||||||
|
B PVD_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TAMP_STAMP_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TAMP_STAMP_IRQHandler
|
||||||
|
B TAMP_STAMP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
B RTC_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FLASH_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
FLASH_IRQHandler
|
||||||
|
B FLASH_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RCC_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
RCC_IRQHandler
|
||||||
|
B RCC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
B EXTI0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
B EXTI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
B EXTI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
B EXTI3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI4_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
B EXTI4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA1_Stream0_IRQHandler
|
||||||
|
B DMA1_Stream0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA1_Stream1_IRQHandler
|
||||||
|
B DMA1_Stream1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA1_Stream2_IRQHandler
|
||||||
|
B DMA1_Stream2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA1_Stream3_IRQHandler
|
||||||
|
B DMA1_Stream3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream4_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA1_Stream4_IRQHandler
|
||||||
|
B DMA1_Stream4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream5_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA1_Stream5_IRQHandler
|
||||||
|
B DMA1_Stream5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream6_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA1_Stream6_IRQHandler
|
||||||
|
B DMA1_Stream6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ADC_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
ADC_IRQHandler
|
||||||
|
B ADC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI9_5_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
B EXTI9_5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM1_BRK_TIM9_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TIM1_BRK_TIM9_IRQHandler
|
||||||
|
B TIM1_BRK_TIM9_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM1_UP_TIM10_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TIM1_UP_TIM10_IRQHandler
|
||||||
|
B TIM1_UP_TIM10_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TIM1_TRG_COM_TIM11_IRQHandler
|
||||||
|
B TIM1_TRG_COM_TIM11_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM1_CC_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
B TIM1_CC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TIM2_IRQHandler
|
||||||
|
B TIM2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TIM3_IRQHandler
|
||||||
|
B TIM3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM4_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TIM4_IRQHandler
|
||||||
|
B TIM4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
B I2C1_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
B I2C1_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
B I2C2_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
B I2C2_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
SPI1_IRQHandler
|
||||||
|
B SPI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
SPI2_IRQHandler
|
||||||
|
B SPI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
USART1_IRQHandler
|
||||||
|
B USART1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
USART2_IRQHandler
|
||||||
|
B USART2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI15_10_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
B EXTI15_10_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_Alarm_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
B RTC_Alarm_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK OTG_FS_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
OTG_FS_WKUP_IRQHandler
|
||||||
|
B OTG_FS_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream7_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA1_Stream7_IRQHandler
|
||||||
|
B DMA1_Stream7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SDIO_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
SDIO_IRQHandler
|
||||||
|
B SDIO_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM5_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TIM5_IRQHandler
|
||||||
|
B TIM5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
SPI3_IRQHandler
|
||||||
|
B SPI3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA2_Stream0_IRQHandler
|
||||||
|
B DMA2_Stream0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA2_Stream1_IRQHandler
|
||||||
|
B DMA2_Stream1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA2_Stream2_IRQHandler
|
||||||
|
B DMA2_Stream2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA2_Stream3_IRQHandler
|
||||||
|
B DMA2_Stream3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream4_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA2_Stream4_IRQHandler
|
||||||
|
B DMA2_Stream4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK OTG_FS_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
OTG_FS_IRQHandler
|
||||||
|
B OTG_FS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream5_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA2_Stream5_IRQHandler
|
||||||
|
B DMA2_Stream5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream6_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA2_Stream6_IRQHandler
|
||||||
|
B DMA2_Stream6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream7_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DMA2_Stream7_IRQHandler
|
||||||
|
B DMA2_Stream7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART6_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
USART6_IRQHandler
|
||||||
|
B USART6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C3_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
I2C3_EV_IRQHandler
|
||||||
|
B I2C3_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C3_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
I2C3_ER_IRQHandler
|
||||||
|
B I2C3_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FPU_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
FPU_IRQHandler
|
||||||
|
B FPU_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI4_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
SPI4_IRQHandler
|
||||||
|
B SPI4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI5_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
SPI5_IRQHandler
|
||||||
|
B SPI5_IRQHandler
|
||||||
|
|
||||||
|
END
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,30 @@
|
||||||
|
/* [ROM = 512kb = 0x80000] */
|
||||||
|
define symbol __intvec_start__ = 0x08000000;
|
||||||
|
define symbol __region_ROM_start__ = 0x08000000;
|
||||||
|
define symbol __region_ROM_end__ = 0x0807FFFF;
|
||||||
|
|
||||||
|
/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */
|
||||||
|
define symbol __NVIC_start__ = 0x20000000;
|
||||||
|
define symbol __NVIC_end__ = 0x20000197; /* Aligned on 8 bytes */
|
||||||
|
define symbol __region_RAM_start__ = 0x20000198;
|
||||||
|
define symbol __region_RAM_end__ = 0x2001FFFF;
|
||||||
|
|
||||||
|
/* Memory regions */
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
|
||||||
|
|
||||||
|
/* Stack and Heap */
|
||||||
|
define symbol __size_cstack__ = 0x400;
|
||||||
|
define symbol __size_heap__ = 0x400;
|
||||||
|
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __size_heap__ { };
|
||||||
|
define block STACKHEAP with fixed order { block HEAP, block CSTACK };
|
||||||
|
|
||||||
|
initialize by copy with packing = zeros { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite, block STACKHEAP };
|
||||||
|
|
@ -0,0 +1,38 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* A generic CMSIS include header
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2014, STMicroelectronics
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MBED_CMSIS_H
|
||||||
|
#define MBED_CMSIS_H
|
||||||
|
|
||||||
|
#include "stm32f4xx.h"
|
||||||
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,55 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2014, STMicroelectronics
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
|
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
|
||||||
|
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
|
||||||
|
|
||||||
|
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
uint32_t i;
|
||||||
|
|
||||||
|
// Copy and switch to dynamic vectors if the first time called
|
||||||
|
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
||||||
|
uint32_t *old_vectors = vectors;
|
||||||
|
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
||||||
|
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
||||||
|
vectors[i] = old_vectors[i];
|
||||||
|
}
|
||||||
|
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
||||||
|
}
|
||||||
|
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
||||||
|
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
||||||
|
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,55 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* CMSIS-style functionality to support dynamic vectors
|
||||||
|
*******************************************************************************
|
||||||
|
* Copyright (c) 2014, STMicroelectronics
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
|
// STM32F411RE
|
||||||
|
// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
|
||||||
|
// MCU Peripherals: 86 vectors = 344 bytes from 0x40 to 0x197
|
||||||
|
// Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM
|
||||||
|
#define NVIC_NUM_VECTORS 102
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
#include "cmsis.h"
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
||||||
|
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,122 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file hal_tick.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief Initialization of HAL tick
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
#include "hal_tick.h"
|
||||||
|
|
||||||
|
TIM_HandleTypeDef TimMasterHandle;
|
||||||
|
uint32_t PreviousVal = 0;
|
||||||
|
|
||||||
|
void us_ticker_irq_handler(void);
|
||||||
|
|
||||||
|
void timer_irq_handler(void) {
|
||||||
|
// Channel 1 for mbed timeout
|
||||||
|
if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
|
||||||
|
us_ticker_irq_handler();
|
||||||
|
}
|
||||||
|
|
||||||
|
// Channel 2 for HAL tick
|
||||||
|
if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
|
||||||
|
__HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
|
||||||
|
uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
|
||||||
|
if ((val - PreviousVal) >= HAL_TICK_DELAY) {
|
||||||
|
// Increment HAL variable
|
||||||
|
HAL_IncTick();
|
||||||
|
// Prepare next interrupt
|
||||||
|
__HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
|
||||||
|
PreviousVal = val;
|
||||||
|
#if 0 // For DEBUG only
|
||||||
|
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Reconfigure the HAL tick using a standard timer instead of systick.
|
||||||
|
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
|
||||||
|
// Enable timer clock
|
||||||
|
TIM_MST_RCC;
|
||||||
|
|
||||||
|
// Reset timer
|
||||||
|
TIM_MST_RESET_ON;
|
||||||
|
TIM_MST_RESET_OFF;
|
||||||
|
|
||||||
|
// Update the SystemCoreClock variable
|
||||||
|
SystemCoreClockUpdate();
|
||||||
|
|
||||||
|
// Configure time base
|
||||||
|
TimMasterHandle.Instance = TIM_MST;
|
||||||
|
TimMasterHandle.Init.Period = 0xFFFFFFFF;
|
||||||
|
TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
|
||||||
|
TimMasterHandle.Init.ClockDivision = 0;
|
||||||
|
TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||||||
|
TimMasterHandle.Init.RepetitionCounter = 0;
|
||||||
|
HAL_TIM_OC_Init(&TimMasterHandle);
|
||||||
|
|
||||||
|
NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
|
||||||
|
NVIC_EnableIRQ(TIM_MST_IRQ);
|
||||||
|
|
||||||
|
// Channel 1 for mbed timeout
|
||||||
|
HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
|
||||||
|
|
||||||
|
// Channel 2 for HAL tick
|
||||||
|
HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
|
||||||
|
PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
|
||||||
|
__HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
|
||||||
|
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
|
||||||
|
|
||||||
|
#if 0 // For DEBUG only
|
||||||
|
__GPIOB_CLK_ENABLE();
|
||||||
|
GPIO_InitTypeDef GPIO_InitStruct;
|
||||||
|
GPIO_InitStruct.Pin = GPIO_PIN_6;
|
||||||
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||||
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||||
|
GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
|
||||||
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,60 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file hal_tick.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief Initialization of HAL tick
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
#ifndef __HAL_TICK_H
|
||||||
|
#define __HAL_TICK_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "stm32f4xx.h"
|
||||||
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
|
#define TIM_MST TIM5
|
||||||
|
#define TIM_MST_IRQ TIM5_IRQn
|
||||||
|
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
|
||||||
|
|
||||||
|
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
|
||||||
|
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
|
||||||
|
|
||||||
|
#define HAL_TICK_DELAY (1000) // 1 ms
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif // __HAL_TICK_H
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,221 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f4xx.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V2.1.0
|
||||||
|
* @date 19-June-2014
|
||||||
|
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
|
||||||
|
*
|
||||||
|
* The file is the unique include file that the application programmer
|
||||||
|
* is using in the C source code, usually in main.c. This file contains:
|
||||||
|
* - Configuration section that allows to select:
|
||||||
|
* - The STM32F4xx device used in the target application
|
||||||
|
* - To use or not the peripheral’s drivers in application code(i.e.
|
||||||
|
* code will be based on direct access to peripheral’s registers
|
||||||
|
* rather than drivers API), this option is controlled by
|
||||||
|
* "#define USE_HAL_DRIVER"
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CMSIS
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup stm32f4xx
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __STM32F4xx_H
|
||||||
|
#define __STM32F4xx_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif /* __cplusplus */
|
||||||
|
|
||||||
|
/** @addtogroup Library_configuration_section
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Uncomment the line below according to the target STM32 device used in your
|
||||||
|
application
|
||||||
|
*/
|
||||||
|
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
|
||||||
|
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
|
||||||
|
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE)
|
||||||
|
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
|
||||||
|
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
|
||||||
|
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
|
||||||
|
/* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
|
||||||
|
/* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
|
||||||
|
/* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
|
||||||
|
/* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
|
||||||
|
STM32F439NI, STM32F429IG and STM32F429II Devices */
|
||||||
|
/* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
|
||||||
|
STM32F439NI, STM32F439IG and STM32F439II Devices */
|
||||||
|
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
|
||||||
|
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
|
||||||
|
#define STM32F411xE /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||||
|
devices, you can define the device in your toolchain compiler preprocessor.
|
||||||
|
*/
|
||||||
|
#if !defined (USE_HAL_DRIVER)
|
||||||
|
/**
|
||||||
|
* @brief Comment the line below if you will not use the peripherals drivers.
|
||||||
|
In this case, these drivers will not be included and the application code will
|
||||||
|
be based on direct access to peripherals registers
|
||||||
|
*/
|
||||||
|
#define USE_HAL_DRIVER
|
||||||
|
#endif /* USE_HAL_DRIVER */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CMSIS Device version number V2.1.0
|
||||||
|
*/
|
||||||
|
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||||
|
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
|
||||||
|
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||||
|
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||||
|
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||||
|
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
|
||||||
|
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
|
||||||
|
|(__STM32F4xx_CMSIS_DEVICE_VERSION))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup Device_Included
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(STM32F405xx)
|
||||||
|
#include "stm32f405xx.h"
|
||||||
|
#elif defined(STM32F415xx)
|
||||||
|
#include "stm32f415xx.h"
|
||||||
|
#elif defined(STM32F407xx)
|
||||||
|
#include "stm32f407xx.h"
|
||||||
|
#elif defined(STM32F417xx)
|
||||||
|
#include "stm32f417xx.h"
|
||||||
|
#elif defined(STM32F427xx)
|
||||||
|
#include "stm32f427xx.h"
|
||||||
|
#elif defined(STM32F437xx)
|
||||||
|
#include "stm32f437xx.h"
|
||||||
|
#elif defined(STM32F429xx)
|
||||||
|
#include "stm32f429xx.h"
|
||||||
|
#elif defined(STM32F439xx)
|
||||||
|
#include "stm32f439xx.h"
|
||||||
|
#elif defined(STM32F401xC)
|
||||||
|
#include "stm32f401xc.h"
|
||||||
|
#elif defined(STM32F401xE)
|
||||||
|
#include "stm32f401xe.h"
|
||||||
|
#elif defined(STM32F411xE)
|
||||||
|
#include "stm32f411xe.h"
|
||||||
|
#else
|
||||||
|
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup Exported_types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
RESET = 0,
|
||||||
|
SET = !RESET
|
||||||
|
} FlagStatus, ITStatus;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
DISABLE = 0,
|
||||||
|
ENABLE = !DISABLE
|
||||||
|
} FunctionalState;
|
||||||
|
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
ERROR = 0,
|
||||||
|
SUCCESS = !ERROR
|
||||||
|
} ErrorStatus;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Exported_macro
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||||
|
|
||||||
|
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||||
|
|
||||||
|
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||||
|
|
||||||
|
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||||
|
|
||||||
|
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||||
|
|
||||||
|
#define READ_REG(REG) ((REG))
|
||||||
|
|
||||||
|
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||||
|
|
||||||
|
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (USE_HAL_DRIVER)
|
||||||
|
#include "stm32f4xx_hal.h"
|
||||||
|
#endif /* USE_HAL_DRIVER */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif /* __cplusplus */
|
||||||
|
|
||||||
|
#endif /* __STM32F4xx_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,706 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file system_stm32f4xx.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V2.1.0
|
||||||
|
* @date 19-June-2014
|
||||||
|
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
|
||||||
|
*
|
||||||
|
* This file provides two functions and one global variable to be called from
|
||||||
|
* user application:
|
||||||
|
* - SystemInit(): This function is called at startup just after reset and
|
||||||
|
* before branch to main program. This call is made inside
|
||||||
|
* the "startup_stm32f4xx.s" file.
|
||||||
|
*
|
||||||
|
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||||
|
* by the user application to setup the SysTick
|
||||||
|
* timer or configure other parameters.
|
||||||
|
*
|
||||||
|
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||||
|
* be called whenever the core clock is changed
|
||||||
|
* during program execution.
|
||||||
|
*
|
||||||
|
* This file configures the system clock as follows:
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
|
||||||
|
* | (external 8 MHz clock) | (internal 16 MHz)
|
||||||
|
* | 2- PLL_HSE_XTAL |
|
||||||
|
* | (external 8 MHz xtal) |
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* SYSCLK(MHz) | 100 | 100
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* AHBCLK (MHz) | 100 | 100
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* APB1CLK (MHz) | 50 | 50
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* APB2CLK (MHz) | 100 | 100
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* USB capable (48 MHz precise clock) | NO | NO
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CMSIS
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup stm32f4xx_system
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F4xx_System_Private_Includes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#include "stm32f4xx.h"
|
||||||
|
#include "hal_tick.h"
|
||||||
|
|
||||||
|
#if !defined (HSE_VALUE)
|
||||||
|
#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
|
||||||
|
#endif /* HSE_VALUE */
|
||||||
|
|
||||||
|
#if !defined (HSI_VALUE)
|
||||||
|
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
|
||||||
|
#endif /* HSI_VALUE */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F4xx_System_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************* Miscellaneous Configuration ************************/
|
||||||
|
/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
|
||||||
|
on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
|
||||||
|
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||||
|
/* #define DATA_IN_ExtSRAM */
|
||||||
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||||
|
|
||||||
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||||
|
/* #define DATA_IN_ExtSDRAM */
|
||||||
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||||
|
|
||||||
|
#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
|
||||||
|
#error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
|
||||||
|
#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
|
||||||
|
|
||||||
|
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||||
|
Internal SRAM. */
|
||||||
|
/* #define VECT_TAB_SRAM */
|
||||||
|
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||||
|
This value must be a multiple of 0x200. */
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F4xx_System_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
|
||||||
|
#define USE_PLL_HSE_EXTC (1) /* Use external clock */
|
||||||
|
#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F4xx_System_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* This variable is updated in three ways:
|
||||||
|
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||||
|
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||||
|
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||||
|
Note: If you use this function to configure the system clock; then there
|
||||||
|
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||||
|
variable is updated automatically.
|
||||||
|
*/
|
||||||
|
uint32_t SystemCoreClock = 16000000;
|
||||||
|
__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
|
||||||
|
static void SystemInit_ExtMemCtl(void);
|
||||||
|
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
|
||||||
|
|
||||||
|
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||||
|
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
uint8_t SetSysClock_PLL_HSI(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F4xx_System_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Setup the microcontroller system
|
||||||
|
* Initialize the FPU setting, vector table location and External memory
|
||||||
|
* configuration.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SystemInit(void)
|
||||||
|
{
|
||||||
|
/* FPU settings ------------------------------------------------------------*/
|
||||||
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||||
|
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||||
|
#endif
|
||||||
|
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||||
|
/* Set HSION bit */
|
||||||
|
RCC->CR |= (uint32_t)0x00000001;
|
||||||
|
|
||||||
|
/* Reset CFGR register */
|
||||||
|
RCC->CFGR = 0x00000000;
|
||||||
|
|
||||||
|
/* Reset HSEON, CSSON and PLLON bits */
|
||||||
|
RCC->CR &= (uint32_t)0xFEF6FFFF;
|
||||||
|
|
||||||
|
/* Reset PLLCFGR register */
|
||||||
|
RCC->PLLCFGR = 0x24003010;
|
||||||
|
|
||||||
|
/* Reset HSEBYP bit */
|
||||||
|
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||||
|
|
||||||
|
/* Disable all interrupts */
|
||||||
|
RCC->CIR = 0x00000000;
|
||||||
|
|
||||||
|
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
|
||||||
|
SystemInit_ExtMemCtl();
|
||||||
|
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
|
||||||
|
|
||||||
|
/* Configure the Vector Table location add offset address ------------------*/
|
||||||
|
#ifdef VECT_TAB_SRAM
|
||||||
|
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||||
|
#else
|
||||||
|
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Configure the Cube driver */
|
||||||
|
SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
|
||||||
|
HAL_Init();
|
||||||
|
|
||||||
|
/* Configure the System clock source, PLL Multiplier and Divider factors,
|
||||||
|
AHB/APBx prescalers and Flash settings */
|
||||||
|
SetSysClock();
|
||||||
|
|
||||||
|
/* Reset the timer to avoid issues after the RAM initialization */
|
||||||
|
TIM_MST_RESET_ON;
|
||||||
|
TIM_MST_RESET_OFF;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||||
|
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||||
|
* be used by the user application to setup the SysTick timer or configure
|
||||||
|
* other parameters.
|
||||||
|
*
|
||||||
|
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||||
|
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||||
|
* based on this variable will be incorrect.
|
||||||
|
*
|
||||||
|
* @note - The system frequency computed by this function is not the real
|
||||||
|
* frequency in the chip. It is calculated based on the predefined
|
||||||
|
* constant and the selected clock source:
|
||||||
|
*
|
||||||
|
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||||
|
*
|
||||||
|
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||||
|
*
|
||||||
|
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||||
|
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||||
|
*
|
||||||
|
* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
|
||||||
|
* 16 MHz) but the real value may vary depending on the variations
|
||||||
|
* in voltage and temperature.
|
||||||
|
*
|
||||||
|
* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
|
||||||
|
* depends on the application requirements), user has to ensure that HSE_VALUE
|
||||||
|
* is same as the real frequency of the crystal used. Otherwise, this function
|
||||||
|
* may have wrong result.
|
||||||
|
*
|
||||||
|
* - The result of this function could be not correct when using fractional
|
||||||
|
* value for HSE crystal.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SystemCoreClockUpdate(void)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
|
||||||
|
|
||||||
|
/* Get SYSCLK source -------------------------------------------------------*/
|
||||||
|
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||||
|
|
||||||
|
switch (tmp)
|
||||||
|
{
|
||||||
|
case 0x00: /* HSI used as system clock source */
|
||||||
|
SystemCoreClock = HSI_VALUE;
|
||||||
|
break;
|
||||||
|
case 0x04: /* HSE used as system clock source */
|
||||||
|
SystemCoreClock = HSE_VALUE;
|
||||||
|
break;
|
||||||
|
case 0x08: /* PLL used as system clock source */
|
||||||
|
|
||||||
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
|
||||||
|
SYSCLK = PLL_VCO / PLL_P
|
||||||
|
*/
|
||||||
|
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
|
||||||
|
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
||||||
|
|
||||||
|
if (pllsource != 0)
|
||||||
|
{
|
||||||
|
/* HSE used as PLL clock source */
|
||||||
|
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* HSI used as PLL clock source */
|
||||||
|
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||||
|
}
|
||||||
|
|
||||||
|
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
|
||||||
|
SystemCoreClock = pllvco/pllp;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
SystemCoreClock = HSI_VALUE;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
/* Compute HCLK frequency --------------------------------------------------*/
|
||||||
|
/* Get HCLK prescaler */
|
||||||
|
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||||
|
/* HCLK frequency */
|
||||||
|
SystemCoreClock >>= tmp;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
|
||||||
|
/**
|
||||||
|
* @brief Setup the external memory controller.
|
||||||
|
* Called in startup_stm32f4xx.s before jump to main.
|
||||||
|
* This function configures the external memories (SRAM/SDRAM)
|
||||||
|
* This SRAM/SDRAM will be used as program data memory (including heap and stack).
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SystemInit_ExtMemCtl(void)
|
||||||
|
{
|
||||||
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||||
|
#if defined (DATA_IN_ExtSDRAM)
|
||||||
|
register uint32_t tmpreg = 0, timeout = 0xFFFF;
|
||||||
|
register uint32_t index;
|
||||||
|
|
||||||
|
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
|
||||||
|
clock */
|
||||||
|
RCC->AHB1ENR |= 0x000001F8;
|
||||||
|
|
||||||
|
/* Connect PDx pins to FMC Alternate function */
|
||||||
|
GPIOD->AFR[0] = 0x000000CC;
|
||||||
|
GPIOD->AFR[1] = 0xCC000CCC;
|
||||||
|
/* Configure PDx pins in Alternate function mode */
|
||||||
|
GPIOD->MODER = 0xA02A000A;
|
||||||
|
/* Configure PDx pins speed to 50 MHz */
|
||||||
|
GPIOD->OSPEEDR = 0xA02A000A;
|
||||||
|
/* Configure PDx pins Output type to push-pull */
|
||||||
|
GPIOD->OTYPER = 0x00000000;
|
||||||
|
/* No pull-up, pull-down for PDx pins */
|
||||||
|
GPIOD->PUPDR = 0x00000000;
|
||||||
|
|
||||||
|
/* Connect PEx pins to FMC Alternate function */
|
||||||
|
GPIOE->AFR[0] = 0xC00000CC;
|
||||||
|
GPIOE->AFR[1] = 0xCCCCCCCC;
|
||||||
|
/* Configure PEx pins in Alternate function mode */
|
||||||
|
GPIOE->MODER = 0xAAAA800A;
|
||||||
|
/* Configure PEx pins speed to 50 MHz */
|
||||||
|
GPIOE->OSPEEDR = 0xAAAA800A;
|
||||||
|
/* Configure PEx pins Output type to push-pull */
|
||||||
|
GPIOE->OTYPER = 0x00000000;
|
||||||
|
/* No pull-up, pull-down for PEx pins */
|
||||||
|
GPIOE->PUPDR = 0x00000000;
|
||||||
|
|
||||||
|
/* Connect PFx pins to FMC Alternate function */
|
||||||
|
GPIOF->AFR[0] = 0xCCCCCCCC;
|
||||||
|
GPIOF->AFR[1] = 0xCCCCCCCC;
|
||||||
|
/* Configure PFx pins in Alternate function mode */
|
||||||
|
GPIOF->MODER = 0xAA800AAA;
|
||||||
|
/* Configure PFx pins speed to 50 MHz */
|
||||||
|
GPIOF->OSPEEDR = 0xAA800AAA;
|
||||||
|
/* Configure PFx pins Output type to push-pull */
|
||||||
|
GPIOF->OTYPER = 0x00000000;
|
||||||
|
/* No pull-up, pull-down for PFx pins */
|
||||||
|
GPIOF->PUPDR = 0x00000000;
|
||||||
|
|
||||||
|
/* Connect PGx pins to FMC Alternate function */
|
||||||
|
GPIOG->AFR[0] = 0xCCCCCCCC;
|
||||||
|
GPIOG->AFR[1] = 0xCCCCCCCC;
|
||||||
|
/* Configure PGx pins in Alternate function mode */
|
||||||
|
GPIOG->MODER = 0xAAAAAAAA;
|
||||||
|
/* Configure PGx pins speed to 50 MHz */
|
||||||
|
GPIOG->OSPEEDR = 0xAAAAAAAA;
|
||||||
|
/* Configure PGx pins Output type to push-pull */
|
||||||
|
GPIOG->OTYPER = 0x00000000;
|
||||||
|
/* No pull-up, pull-down for PGx pins */
|
||||||
|
GPIOG->PUPDR = 0x00000000;
|
||||||
|
|
||||||
|
/* Connect PHx pins to FMC Alternate function */
|
||||||
|
GPIOH->AFR[0] = 0x00C0CC00;
|
||||||
|
GPIOH->AFR[1] = 0xCCCCCCCC;
|
||||||
|
/* Configure PHx pins in Alternate function mode */
|
||||||
|
GPIOH->MODER = 0xAAAA08A0;
|
||||||
|
/* Configure PHx pins speed to 50 MHz */
|
||||||
|
GPIOH->OSPEEDR = 0xAAAA08A0;
|
||||||
|
/* Configure PHx pins Output type to push-pull */
|
||||||
|
GPIOH->OTYPER = 0x00000000;
|
||||||
|
/* No pull-up, pull-down for PHx pins */
|
||||||
|
GPIOH->PUPDR = 0x00000000;
|
||||||
|
|
||||||
|
/* Connect PIx pins to FMC Alternate function */
|
||||||
|
GPIOI->AFR[0] = 0xCCCCCCCC;
|
||||||
|
GPIOI->AFR[1] = 0x00000CC0;
|
||||||
|
/* Configure PIx pins in Alternate function mode */
|
||||||
|
GPIOI->MODER = 0x0028AAAA;
|
||||||
|
/* Configure PIx pins speed to 50 MHz */
|
||||||
|
GPIOI->OSPEEDR = 0x0028AAAA;
|
||||||
|
/* Configure PIx pins Output type to push-pull */
|
||||||
|
GPIOI->OTYPER = 0x00000000;
|
||||||
|
/* No pull-up, pull-down for PIx pins */
|
||||||
|
GPIOI->PUPDR = 0x00000000;
|
||||||
|
|
||||||
|
/*-- FMC Configuration ------------------------------------------------------*/
|
||||||
|
/* Enable the FMC interface clock */
|
||||||
|
RCC->AHB3ENR |= 0x00000001;
|
||||||
|
|
||||||
|
/* Configure and enable SDRAM bank1 */
|
||||||
|
FMC_Bank5_6->SDCR[0] = 0x000019E0;
|
||||||
|
FMC_Bank5_6->SDTR[0] = 0x01115351;
|
||||||
|
|
||||||
|
/* SDRAM initialization sequence */
|
||||||
|
/* Clock enable command */
|
||||||
|
FMC_Bank5_6->SDCMR = 0x00000011;
|
||||||
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||||
|
while((tmpreg != 0) && (timeout-- > 0))
|
||||||
|
{
|
||||||
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Delay */
|
||||||
|
for (index = 0; index<1000; index++);
|
||||||
|
|
||||||
|
/* PALL command */
|
||||||
|
FMC_Bank5_6->SDCMR = 0x00000012;
|
||||||
|
timeout = 0xFFFF;
|
||||||
|
while((tmpreg != 0) && (timeout-- > 0))
|
||||||
|
{
|
||||||
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Auto refresh command */
|
||||||
|
FMC_Bank5_6->SDCMR = 0x00000073;
|
||||||
|
timeout = 0xFFFF;
|
||||||
|
while((tmpreg != 0) && (timeout-- > 0))
|
||||||
|
{
|
||||||
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* MRD register program */
|
||||||
|
FMC_Bank5_6->SDCMR = 0x00046014;
|
||||||
|
timeout = 0xFFFF;
|
||||||
|
while((tmpreg != 0) && (timeout-- > 0))
|
||||||
|
{
|
||||||
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set refresh count */
|
||||||
|
tmpreg = FMC_Bank5_6->SDRTR;
|
||||||
|
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
|
||||||
|
|
||||||
|
/* Disable write protection */
|
||||||
|
tmpreg = FMC_Bank5_6->SDCR[0];
|
||||||
|
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
|
||||||
|
#endif /* DATA_IN_ExtSDRAM */
|
||||||
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||||
|
|
||||||
|
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||||
|
#if defined(DATA_IN_ExtSRAM)
|
||||||
|
/*-- GPIOs Configuration -----------------------------------------------------*/
|
||||||
|
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
|
||||||
|
RCC->AHB1ENR |= 0x00000078;
|
||||||
|
|
||||||
|
/* Connect PDx pins to FMC Alternate function */
|
||||||
|
GPIOD->AFR[0] = 0x00CCC0CC;
|
||||||
|
GPIOD->AFR[1] = 0xCCCCCCCC;
|
||||||
|
/* Configure PDx pins in Alternate function mode */
|
||||||
|
GPIOD->MODER = 0xAAAA0A8A;
|
||||||
|
/* Configure PDx pins speed to 100 MHz */
|
||||||
|
GPIOD->OSPEEDR = 0xFFFF0FCF;
|
||||||
|
/* Configure PDx pins Output type to push-pull */
|
||||||
|
GPIOD->OTYPER = 0x00000000;
|
||||||
|
/* No pull-up, pull-down for PDx pins */
|
||||||
|
GPIOD->PUPDR = 0x00000000;
|
||||||
|
|
||||||
|
/* Connect PEx pins to FMC Alternate function */
|
||||||
|
GPIOE->AFR[0] = 0xC00CC0CC;
|
||||||
|
GPIOE->AFR[1] = 0xCCCCCCCC;
|
||||||
|
/* Configure PEx pins in Alternate function mode */
|
||||||
|
GPIOE->MODER = 0xAAAA828A;
|
||||||
|
/* Configure PEx pins speed to 100 MHz */
|
||||||
|
GPIOE->OSPEEDR = 0xFFFFC3CF;
|
||||||
|
/* Configure PEx pins Output type to push-pull */
|
||||||
|
GPIOE->OTYPER = 0x00000000;
|
||||||
|
/* No pull-up, pull-down for PEx pins */
|
||||||
|
GPIOE->PUPDR = 0x00000000;
|
||||||
|
|
||||||
|
/* Connect PFx pins to FMC Alternate function */
|
||||||
|
GPIOF->AFR[0] = 0x00CCCCCC;
|
||||||
|
GPIOF->AFR[1] = 0xCCCC0000;
|
||||||
|
/* Configure PFx pins in Alternate function mode */
|
||||||
|
GPIOF->MODER = 0xAA000AAA;
|
||||||
|
/* Configure PFx pins speed to 100 MHz */
|
||||||
|
GPIOF->OSPEEDR = 0xFF000FFF;
|
||||||
|
/* Configure PFx pins Output type to push-pull */
|
||||||
|
GPIOF->OTYPER = 0x00000000;
|
||||||
|
/* No pull-up, pull-down for PFx pins */
|
||||||
|
GPIOF->PUPDR = 0x00000000;
|
||||||
|
|
||||||
|
/* Connect PGx pins to FMC Alternate function */
|
||||||
|
GPIOG->AFR[0] = 0x00CCCCCC;
|
||||||
|
GPIOG->AFR[1] = 0x000000C0;
|
||||||
|
/* Configure PGx pins in Alternate function mode */
|
||||||
|
GPIOG->MODER = 0x00085AAA;
|
||||||
|
/* Configure PGx pins speed to 100 MHz */
|
||||||
|
GPIOG->OSPEEDR = 0x000CAFFF;
|
||||||
|
/* Configure PGx pins Output type to push-pull */
|
||||||
|
GPIOG->OTYPER = 0x00000000;
|
||||||
|
/* No pull-up, pull-down for PGx pins */
|
||||||
|
GPIOG->PUPDR = 0x00000000;
|
||||||
|
|
||||||
|
/*-- FMC/FSMC Configuration --------------------------------------------------*/
|
||||||
|
/* Enable the FMC/FSMC interface clock */
|
||||||
|
RCC->AHB3ENR |= 0x00000001;
|
||||||
|
|
||||||
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
||||||
|
/* Configure and enable Bank1_SRAM2 */
|
||||||
|
FMC_Bank1->BTCR[2] = 0x00001011;
|
||||||
|
FMC_Bank1->BTCR[3] = 0x00000201;
|
||||||
|
FMC_Bank1E->BWTR[2] = 0x0fffffff;
|
||||||
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||||
|
|
||||||
|
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
|
||||||
|
/* Configure and enable Bank1_SRAM2 */
|
||||||
|
FSMC_Bank1->BTCR[2] = 0x00001011;
|
||||||
|
FSMC_Bank1->BTCR[3] = 0x00000201;
|
||||||
|
FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
|
||||||
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
|
||||||
|
|
||||||
|
#endif /* DATA_IN_ExtSRAM */
|
||||||
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||||
|
}
|
||||||
|
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||||
|
* AHB/APBx prescalers and Flash settings
|
||||||
|
* @note This function should be called only once the RCC clock configuration
|
||||||
|
* is reset to the default reset state (done in SystemInit() function).
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SetSysClock(void)
|
||||||
|
{
|
||||||
|
/* 1- Try to start with HSE and external clock */
|
||||||
|
#if USE_PLL_HSE_EXTC != 0
|
||||||
|
if (SetSysClock_PLL_HSE(1) == 0)
|
||||||
|
#endif
|
||||||
|
{
|
||||||
|
/* 2- If fail try to start with HSE and external xtal */
|
||||||
|
#if USE_PLL_HSE_XTAL != 0
|
||||||
|
if (SetSysClock_PLL_HSE(0) == 0)
|
||||||
|
#endif
|
||||||
|
{
|
||||||
|
/* 3- If fail start with HSI clock */
|
||||||
|
if (SetSysClock_PLL_HSI() == 0)
|
||||||
|
{
|
||||||
|
while(1)
|
||||||
|
{
|
||||||
|
// [TODO] Put something here to tell the user that a problem occured...
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Output clock on MCO2 pin(PC9) for debugging purpose */
|
||||||
|
//HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
|
||||||
|
}
|
||||||
|
|
||||||
|
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||||
|
/******************************************************************************/
|
||||||
|
/* PLL (clocked by HSE) used as System clock source */
|
||||||
|
/******************************************************************************/
|
||||||
|
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||||
|
{
|
||||||
|
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
||||||
|
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||||
|
|
||||||
|
/* The voltage scaling allows optimizing the power consumption when the device is
|
||||||
|
clocked below the maximum system frequency, to update the voltage scaling value
|
||||||
|
regarding system frequency refer to product datasheet. */
|
||||||
|
__PWR_CLK_ENABLE();
|
||||||
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
|
||||||
|
|
||||||
|
/* Enable HSE oscillator and activate PLL with HSE as source */
|
||||||
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||||
|
if (bypass == 0)
|
||||||
|
{
|
||||||
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
|
||||||
|
}
|
||||||
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||||
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||||
|
//RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
|
||||||
|
//RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400)
|
||||||
|
RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
|
||||||
|
RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
|
||||||
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
|
||||||
|
RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
|
||||||
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||||
|
{
|
||||||
|
return 0; // FAIL
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
|
||||||
|
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||||
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
|
||||||
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz
|
||||||
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz
|
||||||
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz
|
||||||
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
|
||||||
|
{
|
||||||
|
return 0; // FAIL
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Output clock on MCO1 pin(PA8) for debugging purpose */
|
||||||
|
|
||||||
|
//if (bypass == 0)
|
||||||
|
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
|
||||||
|
//else
|
||||||
|
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
|
||||||
|
|
||||||
|
return 1; // OK
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* PLL (clocked by HSI) used as System clock source */
|
||||||
|
/******************************************************************************/
|
||||||
|
uint8_t SetSysClock_PLL_HSI(void)
|
||||||
|
{
|
||||||
|
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
||||||
|
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||||
|
|
||||||
|
/* The voltage scaling allows optimizing the power consumption when the device is
|
||||||
|
clocked below the maximum system frequency, to update the voltage scaling value
|
||||||
|
regarding system frequency refer to product datasheet. */
|
||||||
|
__PWR_CLK_ENABLE();
|
||||||
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
|
||||||
|
|
||||||
|
/* Enable HSI oscillator and activate PLL with HSI as source */
|
||||||
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||||
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||||
|
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||||
|
RCC_OscInitStruct.HSICalibrationValue = 16;
|
||||||
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||||
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
|
||||||
|
//RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
|
||||||
|
//RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400)
|
||||||
|
RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
|
||||||
|
RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
|
||||||
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
|
||||||
|
RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
|
||||||
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||||
|
{
|
||||||
|
return 0; // FAIL
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
|
||||||
|
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||||
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
|
||||||
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz
|
||||||
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz
|
||||||
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz
|
||||||
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
|
||||||
|
{
|
||||||
|
return 0; // FAIL
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Output clock on MCO1 pin(PA8) for debugging purpose */
|
||||||
|
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
|
||||||
|
|
||||||
|
return 1; // OK
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,124 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file system_stm32f4xx.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V2.1.0
|
||||||
|
* @date 19-June-2014
|
||||||
|
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CMSIS
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup stm32f4xx_system
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Define to prevent recursive inclusion
|
||||||
|
*/
|
||||||
|
#ifndef __SYSTEM_STM32F4XX_H
|
||||||
|
#define __SYSTEM_STM32F4XX_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @addtogroup STM32F4xx_System_Includes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup STM32F4xx_System_Exported_types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* This variable is updated in three ways:
|
||||||
|
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||||
|
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
|
||||||
|
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||||
|
Note: If you use this function to configure the system clock; then there
|
||||||
|
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||||
|
variable is updated automatically.
|
||||||
|
*/
|
||||||
|
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F4xx_System_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F4xx_System_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F4xx_System_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
extern void SystemInit(void);
|
||||||
|
extern void SystemCoreClockUpdate(void);
|
||||||
|
extern void SetSysClock(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /*__SYSTEM_STM32F4XX_H */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
Loading…
Reference in New Issue