From d52498f2faacdb3e33c42250bdc53d0465794623 Mon Sep 17 00:00:00 2001 From: Toyomasa Watarai Date: Tue, 20 Sep 2016 15:24:56 +0900 Subject: [PATCH 1/2] [LPC11U68] Fix pin interrupt select offset * Fix incorrect comment * Add offset value calculation by interrupt port number --- .../hal/TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/hal/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c b/hal/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c index 545defb56f..b63ddef43a 100644 --- a/hal/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c +++ b/hal/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c @@ -59,7 +59,7 @@ void gpio_irq6(void) {handle_interrupt_in(6);} void gpio_irq7(void) {handle_interrupt_in(7);} int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { - // PINT only supprt PIO0_*, PIO1_* and from PIO2_0 to PIO0_7 interrupt + // PINT only supprt PIO0_*, PIO1_* and from PIO2_0 to PIO2_7 interrupt if (pin >= P2_8) return -1; irq_handler = handler; @@ -79,7 +79,15 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 /* Enable AHB clock to the PIN, GPIO and IOCON domain. */ LPC_SYSCON->SYSAHBCLKCTRL |= ((1 << 19) | (1 << 16) | (1 << 7)); - LPC_SYSCON->PINTSEL[obj->ch] = ((((pin >> PORT_SHIFT) & 0x3) * 24) + ((pin >> PIN_SHIFT) & 0x1F)); + /* Gets offset value for each port */ + uint32_t offset; + switch ((pin >> PORT_SHIFT) & 0x3) { + case 0: offset = 0; break; // PIO0[23:0] + case 1: offset = 24; break; // PIO1[31:0] + case 2: offset = 56; break; // PIO2[7:0] + } + /* Set the INTPIN number : offset + pin_number */ + LPC_SYSCON->PINTSEL[obj->ch] = (offset + ((pin >> PIN_SHIFT) & 0x1F)); // Interrupt Wake-Up Enable LPC_SYSCON->STARTERP0 |= (1 << obj->ch); From 1553c45fd2d72c333f30c0349f100882981a1283 Mon Sep 17 00:00:00 2001 From: Toyomasa Watarai Date: Fri, 23 Sep 2016 19:13:33 +0900 Subject: [PATCH 2/2] break statement is on new line --- .../TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c | 33 ++++++++++++------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/hal/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c b/hal/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c index b63ddef43a..3fbcdced29 100644 --- a/hal/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c +++ b/hal/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c @@ -82,9 +82,12 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 /* Gets offset value for each port */ uint32_t offset; switch ((pin >> PORT_SHIFT) & 0x3) { - case 0: offset = 0; break; // PIO0[23:0] - case 1: offset = 24; break; // PIO1[31:0] - case 2: offset = 56; break; // PIO2[7:0] + case 0: offset = 0; // PIO0[23:0] + break; + case 1: offset = 24; // PIO1[31:0] + break; + case 2: offset = 56; // PIO2[7:0] + break; } /* Set the INTPIN number : offset + pin_number */ LPC_SYSCON->PINTSEL[obj->ch] = (offset + ((pin >> PIN_SHIFT) & 0x1F)); @@ -96,14 +99,22 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 void (*channels_irq)(void) = NULL; switch (obj->ch) { - case 0: channels_irq = &gpio_irq0; break; - case 1: channels_irq = &gpio_irq1; break; - case 2: channels_irq = &gpio_irq2; break; - case 3: channels_irq = &gpio_irq3; break; - case 4: channels_irq = &gpio_irq4; break; - case 5: channels_irq = &gpio_irq5; break; - case 6: channels_irq = &gpio_irq6; break; - case 7: channels_irq = &gpio_irq7; break; + case 0: channels_irq = &gpio_irq0; + break; + case 1: channels_irq = &gpio_irq1; + break; + case 2: channels_irq = &gpio_irq2; + break; + case 3: channels_irq = &gpio_irq3; + break; + case 4: channels_irq = &gpio_irq4; + break; + case 5: channels_irq = &gpio_irq5; + break; + case 6: channels_irq = &gpio_irq6; + break; + case 7: channels_irq = &gpio_irq7; + break; } NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq); NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));