From 2e7b5ba27bdb623069b6323d5bb867e3bef31240 Mon Sep 17 00:00:00 2001 From: Marcus Chang Date: Mon, 5 Feb 2018 10:46:39 -0800 Subject: [PATCH] Fix linker scripts and startup code for NRF52 Various bug fixes: * Moved SPIM3 location in vector table based on new location in SDK 14.2. * Updated vector table entries and size in startup code and linker scripts. * Added missing vector table RAM section to IAR linker script. --- .../device/TOOLCHAIN_ARM_STD/nRF52832.sct | 2 +- .../device/TOOLCHAIN_GCC_ARM/NRF52832.ld | 2 +- .../device/TOOLCHAIN_GCC_ARM/startup_NRF52832.S | 9 ++++++++- .../device/TOOLCHAIN_IAR/nRF52832.icf | 17 ++++++++++++----- .../TARGET_MCU_NRF52832/device/cmsis_nvic.h | 2 +- .../device/TOOLCHAIN_ARM_STD/nRF52840.sct | 2 +- .../device/TOOLCHAIN_ARM_STD/startup_nrf52840.S | 13 ++++++------- .../device/TOOLCHAIN_GCC_ARM/NRF52840.ld | 2 +- .../device/TOOLCHAIN_GCC_ARM/startup_NRF52840.S | 15 ++++++++++++--- .../device/TOOLCHAIN_IAR/nRF52840.icf | 17 ++++++++++++----- .../device/TOOLCHAIN_IAR/startup_NRF52840_IAR.S | 12 +++++++----- .../TARGET_MCU_NRF52840/device/cmsis_nvic.h | 2 +- 12 files changed, 63 insertions(+), 32 deletions(-) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct index 4bc301cb44..c069d1c133 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct @@ -19,7 +19,7 @@ #endif #define MBED_RAM0_START MBED_RAM_START -#define MBED_RAM0_SIZE 0xD8 +#define MBED_RAM0_SIZE 0xDC #define MBED_RAM1_START (MBED_RAM_START + MBED_RAM0_SIZE) #define MBED_RAM1_SIZE (MBED_RAM_SIZE - MBED_RAM0_SIZE) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_GCC_ARM/NRF52832.ld b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_GCC_ARM/NRF52832.ld index 1dd3d57713..6ad9bd8017 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_GCC_ARM/NRF52832.ld +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_GCC_ARM/NRF52832.ld @@ -35,7 +35,7 @@ #endif #define MBED_RAM0_START MBED_RAM_START -#define MBED_RAM0_SIZE 0xD8 +#define MBED_RAM0_SIZE 0xDC #define MBED_RAM1_START (MBED_RAM_START + MBED_RAM0_SIZE) #define MBED_RAM1_SIZE (MBED_RAM_SIZE - MBED_RAM0_SIZE) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_GCC_ARM/startup_NRF52832.S b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_GCC_ARM/startup_NRF52832.S index 1c6631e7dd..853260b049 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_GCC_ARM/startup_NRF52832.S +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_GCC_ARM/startup_NRF52832.S @@ -61,7 +61,7 @@ __Vectors: .long 0 /*Reserved */ .long 0 /*Reserved */ .long SVC_Handler - .long 0 /*Reserved */ + .long DebugMon_Handler .long 0 /*Reserved */ .long PendSV_Handler .long SysTick_Handler @@ -202,6 +202,13 @@ SVC_Handler: .size SVC_Handler, . - SVC_Handler + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + b . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler .type PendSV_Handler, %function PendSV_Handler: diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/nRF52832.icf b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/nRF52832.icf index 196da11669..01510d0908 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/nRF52832.icf +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/nRF52832.icf @@ -20,14 +20,21 @@ if (MBED_APP_START == 0) { define symbol MBED_RAM_SIZE = 0xD000; } +define symbol MBED_RAM0_START = MBED_RAM_START; +define symbol MBED_RAM0_SIZE = 0xDC; +define symbol MBED_RAM1_START = (MBED_RAM_START + MBED_RAM0_SIZE); +define symbol MBED_RAM1_SIZE = (MBED_RAM_SIZE - MBED_RAM0_SIZE); + /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; /*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; -define symbol __ICFEDIT_region_RAM_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_RAM_end__ = MBED_RAM_START + MBED_RAM_SIZE - 1; +define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; +define symbol __ICFEDIT_region_RAM_NVIC_start__ = MBED_RAM0_START; +define symbol __ICFEDIT_region_RAM_NVIC_end__ = MBED_RAM0_START + MBED_RAM0_SIZE - 1; +define symbol __ICFEDIT_region_RAM_start__ = MBED_RAM1_START; +define symbol __ICFEDIT_region_RAM_end__ = MBED_RAM1_START + MBED_RAM1_SIZE - 1; export symbol __ICFEDIT_region_RAM_start__; export symbol __ICFEDIT_region_RAM_end__; @@ -48,7 +55,7 @@ define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; initialize by copy { readwrite }; do not initialize { section .noinit }; -place at address mem:__ICFEDIT_region_RAM_start__ { section .noinit }; +place at address mem:__ICFEDIT_region_RAM_NVIC_start__ { section .noinit }; keep { section .intvec }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/cmsis_nvic.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/cmsis_nvic.h index 48cc0f9a15..937c497392 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/cmsis_nvic.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/cmsis_nvic.h @@ -31,7 +31,7 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#define NVIC_NUM_VECTORS (16 + 38) // CORE + MCU Peripherals +#define NVIC_NUM_VECTORS (16 + 39) // CORE + MCU Peripherals #define NVIC_USER_IRQ_OFFSET 16 #include "nrf52.h" diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52840.sct b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52840.sct index 56d41d3e12..7190e6f8e5 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52840.sct +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52840.sct @@ -19,7 +19,7 @@ #endif #define MBED_RAM0_START MBED_RAM_START -#define MBED_RAM0_SIZE 0xF8 +#define MBED_RAM0_SIZE 0x100 #define MBED_RAM1_START (MBED_RAM_START + MBED_RAM0_SIZE) #define MBED_RAM1_SIZE (MBED_RAM_SIZE - MBED_RAM0_SIZE) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/startup_nrf52840.S b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/startup_nrf52840.S index 253746ce87..59e6c0ad01 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/startup_nrf52840.S +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/startup_nrf52840.S @@ -98,9 +98,11 @@ __Vectors DCD __initial_sp ; Top of Stack DCD UARTE1_IRQHandler_v DCD QSPI_IRQHandler_v DCD CRYPTOCELL_IRQHandler_v - DCD SPIM3_IRQHandler_v - DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved DCD PWM3_IRQHandler_v + DCD 0 ; Reserved + DCD SPIM3_IRQHandler_v __Vectors_End @@ -215,10 +217,7 @@ Default_Handler PROC EXPORT CRYPTOCELL_IRQHandler_v [WEAK] EXPORT SPIM3_IRQHandler_v [WEAK] EXPORT PWM3_IRQHandler_v [WEAK] - - - - + POWER_CLOCK_IRQHandler RADIO_IRQHandler UARTE0_UART0_IRQHandler_v @@ -260,8 +259,8 @@ USBD_IRQHandler_v UARTE1_IRQHandler_v QSPI_IRQHandler_v CRYPTOCELL_IRQHandler_v -SPIM3_IRQHandler_v PWM3_IRQHandler_v +SPIM3_IRQHandler_v B . ENDP diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld index a8b70ec746..d3bd710fbb 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld @@ -35,7 +35,7 @@ #endif #define MBED_RAM0_START MBED_RAM_START -#define MBED_RAM0_SIZE 0xF8 +#define MBED_RAM0_SIZE 0x100 #define MBED_RAM1_START (MBED_RAM_START + MBED_RAM0_SIZE) #define MBED_RAM1_SIZE (MBED_RAM_SIZE - MBED_RAM0_SIZE) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/startup_NRF52840.S b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/startup_NRF52840.S index 974d839ff5..ff772b1aa7 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/startup_NRF52840.S +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/startup_NRF52840.S @@ -61,7 +61,7 @@ __Vectors: .long 0 /*Reserved */ .long 0 /*Reserved */ .long SVC_Handler - .long 0 /*Reserved */ + .long DebugMon_Handler .long 0 /*Reserved */ .long PendSV_Handler .long SysTick_Handler @@ -110,9 +110,11 @@ __Vectors: .long UARTE1_IRQHandler_v .long QSPI_IRQHandler_v .long CRYPTOCELL_IRQHandler_v - .long SPIM3_IRQHandler_v + .long 0 /*Reserved */ .long 0 /*Reserved */ .long PWM3_IRQHandler_v + .long 0 /*Reserved */ + .long SPIM3_IRQHandler_v .size __Vectors, . - __Vectors @@ -209,6 +211,13 @@ SVC_Handler: .size SVC_Handler, . - SVC_Handler + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + b . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler .type PendSV_Handler, %function PendSV_Handler: @@ -277,7 +286,7 @@ Default_Handler: IRQ UARTE1_IRQHandler_v IRQ QSPI_IRQHandler_v IRQ CRYPTOCELL_IRQHandler_v - IRQ SPIM3_IRQHandler_v IRQ PWM3_IRQHandler_v + IRQ SPIM3_IRQHandler_v .end diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52840.icf b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52840.icf index 25d9061f5e..aff76a3b68 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52840.icf +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52840.icf @@ -20,14 +20,21 @@ if (MBED_APP_START == 0) { define symbol MBED_RAM_SIZE = 0x3C000; } +define symbol MBED_RAM0_START = MBED_RAM_START; +define symbol MBED_RAM0_SIZE = 0x100; +define symbol MBED_RAM1_START = (MBED_RAM_START + MBED_RAM0_SIZE); +define symbol MBED_RAM1_SIZE = (MBED_RAM_SIZE - MBED_RAM0_SIZE); + /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; /*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; -define symbol __ICFEDIT_region_RAM_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_RAM_end__ = MBED_RAM_START + MBED_RAM_SIZE - 1; +define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; +define symbol __ICFEDIT_region_RAM_NVIC_start__ = MBED_RAM0_START; +define symbol __ICFEDIT_region_RAM_NVIC_end__ = MBED_RAM0_START + MBED_RAM0_SIZE - 1; +define symbol __ICFEDIT_region_RAM_start__ = MBED_RAM1_START; +define symbol __ICFEDIT_region_RAM_end__ = MBED_RAM1_START + MBED_RAM1_SIZE - 1; export symbol __ICFEDIT_region_RAM_start__; export symbol __ICFEDIT_region_RAM_end__; @@ -48,7 +55,7 @@ define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; initialize by copy { readwrite }; do not initialize { section .noinit }; -place at address mem:__ICFEDIT_region_RAM_start__ { section .noinit }; +place at address mem:__ICFEDIT_region_RAM_NVIC_start__ { section .noinit }; keep { section .intvec }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/startup_NRF52840_IAR.S b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/startup_NRF52840_IAR.S index 26ba439712..86b3d77ecb 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/startup_NRF52840_IAR.S +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/startup_NRF52840_IAR.S @@ -122,9 +122,11 @@ __vector_table DCD UARTE1_IRQHandler_v DCD QSPI_IRQHandler_v DCD CRYPTOCELL_IRQHandler_v - DCD SPIM3_IRQHandler_v - DCD 0 /*Reserved */ + DCD 0 ; Reserved + DCD 0 ; Reserved DCD PWM3_IRQHandler_v + DCD 0 ; Reserved + DCD SPIM3_IRQHandler_v __Vectors_End __Vectors EQU __vector_table @@ -146,7 +148,7 @@ Reset_Handler BX R0 ; Dummy exception handlers - + PUBWEAK NMI_Handler SECTION .text:CODE:NOROOT(1) @@ -385,7 +387,7 @@ FPU_IRQHandler_v SECTION .text:CODE:NOROOT(1) USBD_IRQHandler_v B . - + PUBWEAK UARTE1_IRQHandler_v SECTION .text:CODE:NOROOT(1) UARTE1_IRQHandler_v @@ -410,7 +412,7 @@ SPIM3_IRQHandler_v SECTION .text:CODE:NOROOT(1) PWM3_IRQHandler_v B . - + END diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/cmsis_nvic.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/cmsis_nvic.h index 7822cd78d2..6cc327e851 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/cmsis_nvic.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/cmsis_nvic.h @@ -32,7 +32,7 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#define NVIC_NUM_VECTORS (16 + 46) // CORE + MCU Peripherals +#define NVIC_NUM_VECTORS (16 + 48) // CORE + MCU Peripherals #define NVIC_USER_IRQ_OFFSET 16 #include "nrf.h"