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Formatting code according to ARM guidelines. 

Ran pylint and astyle.
Rebased latest ARMmbed-os code.
pull/2531/head
Radhika 2016-08-26 16:52:11 +05:30
parent 048d53134a
commit 2dc38063b9
67 changed files with 3412 additions and 3633 deletions
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3
hal/targets.json
View File

@ -2019,6 +2019,7 @@
"progen": {"target": "ncs36510"},
"progen_target": "ncs36510",
"supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
"device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI"]
"device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI"],
"release_versions": ["2", "5"]
}
}

71
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/Pad.c
View File

@ -67,7 +67,7 @@
*************************************************************************************************/
/** Find description at pad.h */
void fPadInit()
void fPadInit()
{
/** - Enable the clock for PAD peripheral device */
CLOCK_ENABLE(CLOCK_PAD);
@ -86,12 +86,12 @@ void fPadInit()
PADREG->PADIO10.WORD = PAD_UNUSED_PD_L0_PP;
PADREG->PADIO11.WORD = PAD_INPUT_PD_L1_PP; /* SWO */
PADREG->PADIO12.WORD = PAD_INPUT_PD_L1_PP; /* SWCLK */
PADREG->PADIO13.WORD = PAD_INPUT_PD_L1_PP; /* SWDIO */
PADREG->PADIO14.WORD = PAD_INPUT_PD_L1_PP;
PADREG->PADIO13.WORD = PAD_INPUT_PD_L1_PP; /* SWDIO */
PADREG->PADIO14.WORD = PAD_INPUT_PD_L1_PP;
PADREG->PADIO15.WORD = PAD_UNUSED_PD_L0_PP;
PADREG->PADIO16.WORD = PAD_UNUSED_PD_L0_PP;
PADREG->PADIO17.WORD = PAD_UNUSED_PD_L0_PP;
PADREG->PADIO16.WORD = PAD_UNUSED_PD_L0_PP;
PADREG->PADIO17.WORD = PAD_UNUSED_PD_L0_PP;
/** - Disable the clock for PAD peripheral device */
CLOCK_DISABLE(CLOCK_PAD);
@ -101,41 +101,40 @@ void fPadInit()
boolean fPadIOCtrl(uint8_t PadNum, uint8_t OutputDriveStrength, uint8_t OutputDriveType, uint8_t PullType)
{
PadReg_t *PadRegOffset;
/** \verbatim
Table: O/p drive strength
Drive strength 3.3V (min/typ/max) 1V (min/typ/max)
000 1/1.4/2.1 mA 0.043/0.07/0.11 mA
001 2/2.7/4.1 mA 0.086/0.15/0.215 mA
010 4.1/5.3/7.8 mA 0.188/0.3/0.4 mA
011 8.1/10.4/15 8 mA 0.4/0.6/0.81 mA
100 20.8/26/37 mA* 1/1.6/2.2 mA
101 40.5/50/70 mA* 2/3/4.3 mA
11x 57/73/102 mA* 3/4.6/6.2 mA
/** \verbatim
Table: O/p drive strength
*Values are only accessible when CDBGPWRUPREQ is high. This limits the maximum output current in functional mode. \endverbatim */
Drive strength 3.3V (min/typ/max) 1V (min/typ/max)
000 1/1.4/2.1 mA 0.043/0.07/0.11 mA
001 2/2.7/4.1 mA 0.086/0.15/0.215 mA
010 4.1/5.3/7.8 mA 0.188/0.3/0.4 mA
011 8.1/10.4/15 8 mA 0.4/0.6/0.81 mA
100 20.8/26/37 mA* 1/1.6/2.2 mA
101 40.5/50/70 mA* 2/3/4.3 mA
11x 57/73/102 mA* 3/4.6/6.2 mA
*Values are only accessible when CDBGPWRUPREQ is high. This limits the maximum output current in functional mode. \endverbatim */
if((PadNum <= PAD_NUM_OF_IO) &&
(OutputDriveStrength <= PAD_OP_DRIVE_STRGTH_MAX) &&
(OutputDriveType <= PAD_OP_DRIVE_TYPE_MAX) && (PullType <= PAD_OP_PULL_TYPE_MAX))
{
/** - Get PAD IO register address for the PAD number */
PadRegOffset = (PadReg_t*)(PADREG_BASE + (PadNum * PAD_REG_ADRS_BYTE_SIZE));
if((PadNum <= PAD_NUM_OF_IO) &&
(OutputDriveStrength <= PAD_OP_DRIVE_STRGTH_MAX) &&
(OutputDriveType <= PAD_OP_DRIVE_TYPE_MAX) && (PullType <= PAD_OP_PULL_TYPE_MAX)) {
/** - Get PAD IO register address for the PAD number */
PadRegOffset = (PadReg_t*)(PADREG_BASE + (PadNum * PAD_REG_ADRS_BYTE_SIZE));
/** - Enable the clock for PAD peripheral device */
CLOCK_ENABLE(CLOCK_PAD);
/** - Enable the clock for PAD peripheral device */
CLOCK_ENABLE(CLOCK_PAD);
/** - Set drive type, pulltype & drive strength */
PadRegOffset->PADIO0.WORD = (uint32_t)((PullType << PAD_OP_PULL_TYPE_BIT_POS) |
(OutputDriveStrength << PAD_OP_DRIVE_STRGTH_BIT_POS) |
(OutputDriveType << PAD_OP_DRIVE_TYPE_BIT_POS));
/** - Set drive type, pulltype & drive strength */
PadRegOffset->PADIO0.WORD = (uint32_t)((PullType << PAD_OP_PULL_TYPE_BIT_POS) |
(OutputDriveStrength << PAD_OP_DRIVE_STRGTH_BIT_POS) |
(OutputDriveType << PAD_OP_DRIVE_TYPE_BIT_POS));
/** - Disable the clock for PAD peripheral device */
CLOCK_DISABLE(CLOCK_PAD);
return True;
}
/* Invalid parameter/s */
return False;
/** - Disable the clock for PAD peripheral device */
CLOCK_DISABLE(CLOCK_PAD);
return True;
}
/* Invalid parameter/s */
return False;
}
#endif /* REVD */

8
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/PeripheralNames.h
View File

@ -26,8 +26,8 @@
#include "cmsis.h"
#include "memory_map.h" //I think this is needed because enums are using base adresses
#include "PinNames.h" //this needed?
#include "memory_map.h" /* This is needed because enums use base adresses */
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -56,8 +56,8 @@ typedef enum {
} I2CName;
typedef enum {
PWM_0 = (int)PWMREG_BASE,
}PWMName;
PWM_0 = (int)PWMREG_BASE,
} PWMName;
#ifdef __cplusplus
}

58
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/PeripheralPins.c
View File

@ -14,8 +14,8 @@
* limitations under the License.
*/
/*todo: determine how function argument is used */
/*todo: determine how function argument is used */
#include "PeripheralPins.h"
/************ADC***************/
@ -32,20 +32,20 @@ const PinMap PinMap_I2C_SDA[] = {
{GPIO3, I2C_0, 5},
{GPIO4, I2C_0, 5},
{GPIO10, I2C_0, 5},
{GPIO12, I2C_0, 5},
{GPIO12, I2C_0, 5},
{GPIO15, I2C_1, 5},
{GPIO16, I2C_1, 5},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{GPIO2, I2C_0, 5},
{GPIO5, I2C_0, 5},
{GPIO11, I2C_0, 5},
{GPIO13, I2C_0, 5},
{GPIO14, I2C_1, 5},
{GPIO17, I2C_1, 5},
{NC , NC , 0}
{GPIO2, I2C_0, 5},
{GPIO5, I2C_0, 5},
{GPIO11, I2C_0, 5},
{GPIO13, I2C_0, 5},
{GPIO14, I2C_1, 5},
{GPIO17, I2C_1, 5},
{NC , NC , 0}
};
/************UART***************/
@ -63,40 +63,44 @@ const PinMap PinMap_UART_RX[] = {
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
/*todo: other pins are possible, need to add */
/*todo: other pins are possible, need to add */
{SPI1_SCLK_2, SPI_0, 6},
{SPI1_SCLK_3, SPI_0, 6},
{SPI2_SCLK, SPI_1, 6},
{NC, NC, 0}};
{SPI2_SCLK, SPI_1, 6},
{NC, NC, 0}
};
const PinMap PinMap_SPI_MOSI[] = {
/*todo: other pins are possible, need to add */
/*todo: other pins are possible, need to add */
{SPI1_SDATAO_2, SPI_0, 6},
{SPI1_SDATAO_3, SPI_0, 6},
{SPI1_SDATAO_3, SPI_0, 6},
{SPI2_SDATAO, SPI_1, 6},
{NC, NC, 0}};
{NC, NC, 0}
};
const PinMap PinMap_SPI_MISO[] = {
/*todo: other pins are possible, need to add */
{SPI1_SDATAI_2, SPI_0, 6},
/*todo: other pins are possible, need to add */
{SPI1_SDATAI_2, SPI_0, 6},
{SPI1_SDATAI_3, SPI_0, 6},
{SPI2_SDATAI, SPI_1, 6},
{NC, NC, 0}};
{NC, NC, 0}
};
const PinMap PinMap_SPI_SSEL[] = {
/*todo: other pins are possible, need to add */
/* TODO what about SSNO */
/*todo: other pins are possible, need to add */
/* TODO what about SSNO */
{SPI1_SSNI_2, SPI_0, 6},
{SPI2_SSNI, SPI_1, 6},
{NC, NC, 0}};
{SPI2_SSNI, SPI_1, 6},
{NC, NC, 0}
};
const PinMap PinMap_PWM[] = {
{GPIO6 , PWM_0 , 4},
{GPIO7 , PWM_0 , 4},
{GPIO9 , PWM_0 , 4},
{GPIO12 , PWM_0 , 4},
{GPIO13 , PWM_0 , 4},
{GPIO7 , PWM_0 , 4},
{GPIO9 , PWM_0 , 4},
{GPIO12 , PWM_0 , 4},
{GPIO13 , PWM_0 , 4},
{NC , NC , 0}
};

2
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/PeripheralPins.h
View File

@ -13,7 +13,7 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H

212
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h
View File

@ -1,7 +1,7 @@
/**
******************************************************************************
* @file PinNames.h
* @brief Implements an assertion.
* @brief Implements common PIN names for peripherals.
* @internal
* @author ON Semiconductor
* $Rev: 0.1 $
@ -31,124 +31,124 @@ extern "C" {
#endif
typedef enum {
GPIO0 = 0,
GPIO1,
GPIO2,
GPIO3,
GPIO4,
GPIO5,
GPIO6,
GPIO7,
GPIO8,
GPIO9,
GPIO10,
GPIO11,
GPIO12,
GPIO13,
GPIO14,
GPIO15,
GPIO16,
GPIO17,
A0,
A1,
A2,
A3,
UART1_TX = GPIO0,
UART1_RX = GPIO1,
UART2_TX = GPIO8,
UART2_RX = GPIO9,
GPIO0 = 0,
GPIO1,
GPIO2,
GPIO3,
GPIO4,
GPIO5,
GPIO6,
GPIO7,
GPIO8,
GPIO9,
GPIO10,
GPIO11,
GPIO12,
GPIO13,
GPIO14,
GPIO15,
GPIO16,
GPIO17,
A0,
A1,
A2,
A3,
UART1_TX = GPIO0,
UART1_RX = GPIO1,
UART2_TX = GPIO8,
UART2_RX = GPIO9,
I2C1_SCLK_1 = GPIO2,
I2C1_SDATA_1 = GPIO3,
I2C1_SCLK_2 = GPIO5,
I2C1_SDATA_2 = GPIO4,
I2C1_SCLK = I2C1_SCLK_1, /*Default*/
I2C1_SDATA = I2C1_SDATA_1, /*Default*/
I2C1_SCLK_1 = GPIO2,
I2C1_SDATA_1 = GPIO3,
I2C1_SCLK_2 = GPIO5,
I2C1_SDATA_2 = GPIO4,
I2C1_SCLK = I2C1_SCLK_1, /*Default*/
I2C1_SDATA = I2C1_SDATA_1, /*Default*/
I2C2_SCLK_1 = GPIO14,
I2C2_SDATA_1 = GPIO15,
I2C2_SCLK_2 = GPIO17,
I2C2_SDATA_2 = GPIO16,
I2C2_SCLK = I2C2_SCLK_2, /*Default*/
I2C2_SDATA = I2C2_SDATA_2, /*Default*/
I2C_SCL = I2C1_SCLK_1, /*Default*/
I2C_SDA = I2C1_SDATA_1, /*Default*/
I2C2_SCLK_1 = GPIO14,
I2C2_SDATA_1 = GPIO15,
I2C2_SCLK_2 = GPIO17,
I2C2_SDATA_2 = GPIO16,
I2C2_SCLK = I2C2_SCLK_2, /*Default*/
I2C2_SDATA = I2C2_SDATA_2, /*Default*/
I2C_SCL = I2C1_SCLK_1, /*Default*/
I2C_SDA = I2C1_SDATA_1, /*Default*/
/* SPI 1 with 1st set of CROSS BAR */
SPI1_SSNO0_1 = GPIO0,
SPI1_SSNO1_1 = GPIO1,
SPI1_SSNO2_1 = GPIO2,
SPI1_SSNO3_1 = GPIO3,
/* SPI 1 with 1st set of CROSS BAR */
SPI1_SSNO0_1 = GPIO0,
SPI1_SSNO1_1 = GPIO1,
SPI1_SSNO2_1 = GPIO2,
SPI1_SSNO3_1 = GPIO3,
/* SPI 1 with 2st set of CROSS BAR */
SPI1_SCLK_2 = GPIO4,
SPI1_SDATAO_2 = GPIO5,
SPI1_SDATAI_2 = GPIO6,
SPI1_SSNI_2 = GPIO7,
SPI1_SSNO0_2 = GPIO8,
SPI1_SSNO1_2 = GPIO9,
SPI1_SSNO2_2 = GPIO10,
/* SPI 1 with 2st set of CROSS BAR */
SPI1_SCLK_2 = GPIO4,
SPI1_SDATAO_2 = GPIO5,
SPI1_SDATAI_2 = GPIO6,
SPI1_SSNI_2 = GPIO7,
SPI1_SSNO0_2 = GPIO8,
SPI1_SSNO1_2 = GPIO9,
SPI1_SSNO2_2 = GPIO10,
SPI1_SCLK = SPI1_SCLK_2, /*Default*/
SPI1_SDATAO = SPI1_SDATAO_2, /*Default*/
SPI1_SDATAI = SPI1_SDATAI_2, /*Default*/
SPI1_SSNI = SPI1_SSNI_2, /*Default*/
SPI1_SSNO0 = SPI1_SSNO0_2, /*Default*/
SPI1_SSNO1 = SPI1_SSNO1_2, /*Default*/
SPI1_SSNO2 = SPI1_SSNO2_2, /*Default*/
SPI1_SCLK = SPI1_SCLK_2, /*Default*/
SPI1_SDATAO = SPI1_SDATAO_2, /*Default*/
SPI1_SDATAI = SPI1_SDATAI_2, /*Default*/
SPI1_SSNI = SPI1_SSNI_2, /*Default*/
SPI1_SSNO0 = SPI1_SSNO0_2, /*Default*/
SPI1_SSNO1 = SPI1_SSNO1_2, /*Default*/
SPI1_SSNO2 = SPI1_SSNO2_2, /*Default*/
/* SPI 1 with 3rd set of CROSS BAR */
SPI1_SCLK_3 = GPIO8,
SPI1_SDATAO_3 = GPIO9,
SPI1_SDATAI_3 = GPIO10,
/* SPI 1 with 3rd set of CROSS BAR */
SPI1_SCLK_3 = GPIO8,
SPI1_SDATAO_3 = GPIO9,
SPI1_SDATAI_3 = GPIO10,
/* SPI 2 */
SPI2_SCLK = GPIO14,
SPI2_SDATAO = GPIO15,
SPI2_SDATAI = GPIO16,
SPI2_SSNI = GPIO17,
SPI2_SSNO0 = GPIO17,
/* SPI 2 */
SPI2_SCLK = GPIO14,
SPI2_SDATAO = GPIO15,
SPI2_SDATAI = GPIO16,
SPI2_SSNI = GPIO17,
SPI2_SSNO0 = GPIO17,
// Generic signals namings
LED1 = GPIO4,
LED2 = GPIO6,
LED3 = GPIO5,
LED4 = (int)0xFFFFFFFF,
LED5 = (int)0xFFFFFFFF,
LED_GREEN = GPIO4,
LED_YELLOW = GPIO6,
LED_BLUE = GPIO5,
USER_BUTTON = GPIO7, /*NEW connection on NCS36510-RF Rev 1.1 - Alias of SW1 */
SW1 = GPIO7, /*NEW connection on NCS36510-RF Rev 1.1 */
SW2 = GPIO10, /*NEW connection on NCS36510-RF Rev 1.1 */
SERIAL_TX = GPIO0,
SERIAL_RX = GPIO1,
USBTX = GPIO0,
USBRX = GPIO1,
D0 = GPIO9,
D1 = GPIO8,
D2 = GPIO4,
D3 = GPIO6,
D4 = GPIO5,
D5 = GPIO7,
D6 = GPIO10,
D7 = (int)0xFFFFFFFF,
D8 = (int)0xFFFFFFFF,
D9 = (int)0xFFFFFFFF,
D10 = GPIO17,
D11 = GPIO15,
D12 = GPIO16,
D13 = GPIO14,
D14 = GPIO3,
D15 = GPIO2,
NC = (int)0xFFFFFFFF
} PinName;
// Generic signals namings
LED1 = GPIO4,
LED2 = GPIO6,
LED3 = GPIO5,
LED4 = (int)0xFFFFFFFF,
LED5 = (int)0xFFFFFFFF,
LED_GREEN = GPIO4,
LED_YELLOW = GPIO6,
LED_BLUE = GPIO5,
USER_BUTTON = GPIO7, /*NEW connection on NCS36510-RF Rev 1.1 - Alias of SW1 */
SW1 = GPIO7, /*NEW connection on NCS36510-RF Rev 1.1 */
SW2 = GPIO10, /*NEW connection on NCS36510-RF Rev 1.1 */
SERIAL_TX = GPIO0,
SERIAL_RX = GPIO1,
USBTX = GPIO0,
USBRX = GPIO1,
D0 = GPIO9,
D1 = GPIO8,
D2 = GPIO4,
D3 = GPIO6,
D4 = GPIO5,
D5 = GPIO7,
D6 = GPIO10,
D7 = (int)0xFFFFFFFF,
D8 = (int)0xFFFFFFFF,
D9 = (int)0xFFFFFFFF,
D10 = GPIO17,
D11 = GPIO15,
D12 = GPIO16,
D13 = GPIO14,
D14 = GPIO3,
D15 = GPIO2,
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PIN_INPUT,
PIN_OUTPUT,
}PinDirection;
} PinDirection;
typedef enum {
PushPullPullDown = 0,

67
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h
View File

@ -44,49 +44,44 @@ extern "C" {
#define ADC_CONTROL_REF_CH_BIT_POS 12
#define ADC_PRESCALE_VAL_BIT_POS 0
#define ADC_PRESCALE_EN_BIT_POS 8
#define ADC_DELAY_SAMPLE_RATE_BIT_POS 0
#define ADC_DELAY_SAMPLE_RATE_BIT_POS 0
#define ADC_DELAY_WARMUP_BIT_POS 16
#define ADC_DELAY_SAMPLE_TIME_BIT_POS 24
typedef enum
{
ADC_CHANNEL0 = 0,
ADC_CHANNEL1,
ADC_CHANNEL2,
ADC_CHANNEL3,
ADC_TEMPSENSR = 6,
ADC_BATTERY
}Type_RefCh_ConvCh;
typedef enum {
ADC_CHANNEL0 = 0,
ADC_CHANNEL1,
ADC_CHANNEL2,
ADC_CHANNEL3,
ADC_TEMPSENSR = 6,
ADC_BATTERY
} Type_RefCh_ConvCh;
typedef enum
{
ADC_RELATIVE_MEAS = 0,
ADC_ABSOLUTE_MEAS
}Type_Meastype;
typedef enum {
ADC_RELATIVE_MEAS = 0,
ADC_ABSOLUTE_MEAS
} Type_Meastype;
typedef enum
{
ADC_SINGLE_SAMPLE = 0,
ADC_CONTINUOUS_SAMPLE
}Type_Mode;
typedef enum {
ADC_SINGLE_SAMPLE = 0,
ADC_CONTINUOUS_SAMPLE
} Type_Mode;
typedef enum
{
ADC_INT_DISABLE = 0,
ADC_INT_ENABLE
}Type_Intrpt;
typedef enum {
ADC_INT_DISABLE = 0,
ADC_INT_ENABLE
} Type_Intrpt;
typedef enum
{
ADC_IP_SCALE_1_0 = 0,
ADC_IP_SCALE_0_6923,
ADC_IP_SCALE_0_5294,
ADC_IP_SCALE_0_4286,
ADC_IP_SCALE_0_3600,
ADC_IP_SCALE_0_3103,
ADC_IP_SCALE_0_2728,
ADC_IP_SCALE_0_2432
}Ip_Scale_Type;
typedef enum {
ADC_IP_SCALE_1_0 = 0,
ADC_IP_SCALE_0_6923,
ADC_IP_SCALE_0_5294,
ADC_IP_SCALE_0_4286,
ADC_IP_SCALE_0_3600,
ADC_IP_SCALE_0_3103,
ADC_IP_SCALE_0_2728,
ADC_IP_SCALE_0_2432
} Ip_Scale_Type;
void fAdcHandler(void);

74
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/adc_sar_map.h
View File

@ -34,46 +34,40 @@
#include "architecture.h"
/* ADC Control HW Structure Overlay */
typedef struct{
union
{
struct
{
__IO uint32_t MODE :1; /** 1= Continuous Conversion 0= Single Shot */
__IO uint32_t START_CONV :1; /** 1= Start Conversion 0= No effect*/
__IO uint32_t ABORT :1; /** 1= Aborts the Continuous Conversion mode 0=No effect */
__IO uint32_t MEASUREMENT_TYPE :1; /** 1= Absolute 0= Differential */
__IO uint32_t INPUT_SCALE :3; /** 000 – 1.0 001 – 0.6923 010 – 0.5294 011 – 0.4286 100 – 0.3600 101 – 0.3103 110 – 0.2728 111 – 0.2432 */
__I uint32_t BIT7:1; /** NA Always read backs 0*/
__IO uint32_t CONV_CH :3; /** Selects 1 or 8 channels to do a conversion on. 000 – A[0] 000 – A[1] 010 – A[2] 011 – A[3] 100 – N/A 101 – N/A 110 – Temperature sensor 111 – Battery */
__I uint32_t NA :1; /** NA */
__IO uint32_t REF_CH :3; /** Selects 1 to 8 channels for reference channel 000 – A[0] 000 – A[1] 010 – A[2] 011 – A[3] 100 – N/A 101 – N/A 110 – Temperature sensor 111 – Battery */
}BITS;
__IO uint32_t WORD;
}CONTROL;
union
{
struct
{
__IO uint32_t SAMPLE_RATE :16; /** Sets the sample rate in units of PCLKperiod * (Prescale + 1). */
__IO uint32_t WARMUP_TIME :8; /** Sets the warm-up time in units of PCLKperiod * (Prescale + 1) */
__IO uint32_t SAMPLE_TIME :8; /** Sample Time. Sets the measure time in units of PCLKperiod * (Prescale + 1).*/
}BITS;
__IO uint32_t WORD;
}DELAY;
__I uint32_t DATA;
__IO uint32_t IR;
union
{
struct
{
__IO uint32_t PRESC_VAL :8; /**Set the pre-scalar value. The SAR ADC nominally runs at 4MHz, so this value should be programmed to 32 Mhz/4mhz -1=7 */
__IO uint32_t PRESC_EN :1; /** 1= enables PreScalar 0= Disable Prescalar */
typedef struct {
union {
struct {
__IO uint32_t MODE :1; /** 1= Continuous Conversion 0= Single Shot */
__IO uint32_t START_CONV :1; /** 1= Start Conversion 0= No effect*/
__IO uint32_t ABORT :1; /** 1= Aborts the Continuous Conversion mode 0=No effect */
__IO uint32_t MEASUREMENT_TYPE :1; /** 1= Absolute 0= Differential */
__IO uint32_t INPUT_SCALE :3; /** 000 – 1.0 001 – 0.6923 010 – 0.5294 011 – 0.4286 100 – 0.3600 101 – 0.3103 110 – 0.2728 111 – 0.2432 */
__I uint32_t BIT7:1; /** NA Always read backs 0*/
__IO uint32_t CONV_CH :3; /** Selects 1 or 8 channels to do a conversion on. 000 – A[0] 000 – A[1] 010 – A[2] 011 – A[3] 100 – N/A 101 – N/A 110 – Temperature sensor 111 – Battery */
__I uint32_t NA :1; /** NA */
__IO uint32_t REF_CH :3; /** Selects 1 to 8 channels for reference channel 000 – A[0] 000 – A[1] 010 – A[2] 011 – A[3] 100 – N/A 101 – N/A 110 – Temperature sensor 111 – Battery */
} BITS;
__IO uint32_t WORD;
} CONTROL;
union {
struct {
__IO uint32_t SAMPLE_RATE :16; /** Sets the sample rate in units of PCLKperiod * (Prescale + 1). */
__IO uint32_t WARMUP_TIME :8; /** Sets the warm-up time in units of PCLKperiod * (Prescale + 1) */
__IO uint32_t SAMPLE_TIME :8; /** Sample Time. Sets the measure time in units of PCLKperiod * (Prescale + 1).*/
} BITS;
__IO uint32_t WORD;
} DELAY;
__I uint32_t DATA;
__IO uint32_t IR;
union {
struct {
__IO uint32_t PRESC_VAL :8; /**Set the pre-scalar value. The SAR ADC nominally runs at 4MHz, so this value should be programmed to 32 Mhz/4mhz -1=7 */
__IO uint32_t PRESC_EN :1; /** 1= enables PreScalar 0= Disable Prescalar */
// __IO uint32_t PHASE_CTRL :1; /** 1 = Phase 2 is delayed two 32MHz clock from phase 1. 0= Phase 2 is delayed one 32MHz clock from phase 1. */
}BITS;
__IO uint32_t WORD;
}PRESCALE;
__I uint32_t STATUS;
}ADCReg_t,*AdcReg_pt;
} BITS;
__IO uint32_t WORD;
} PRESCALE;
__I uint32_t STATUS;
} ADCReg_t,*AdcReg_pt;
#endif /* ADC_MAP_H_ */

106
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/aes_map.h
View File

@ -3,7 +3,7 @@
* @file aes_map.h
* @brief AES HW register map
* @internal
* @author Industrial ASSP Application Team.
* @author ON Semiconductor.
* $Rev: 2110 $
* $Date: 2013-07-16 20:13:03 +0530 (Tue, 16 Jul 2013) $
******************************************************************************
@ -37,62 +37,62 @@
/** AES Encryption HW Structure Overlay */
typedef struct {
__IO uint32_t KEY0; /**< Bits[31:00] of the 128-bit key */
__IO uint32_t KEY1; /**< Bits[63:32] of the 128-bit key */
__IO uint32_t KEY2; /**< Bits[95:64] of the 128-bit key */
__IO uint32_t KEY3; /**< Bits[127:96] of the 128-bit key */
__IO uint32_t KEY4; /**< Bits[159:128] of the 256-bit key */
__IO uint32_t KEY5; /**< Bits[191:160] of the 256-bit key */
__IO uint32_t KEY6; /**< Bits[223:192] of the 256-bit key */
__IO uint32_t KEY7; /**< Bits[255:224] of the 256-bit key */
__IO uint32_t KEY0; /**< Bits[31:00] of the 128-bit key */
__IO uint32_t KEY1; /**< Bits[63:32] of the 128-bit key */
__IO uint32_t KEY2; /**< Bits[95:64] of the 128-bit key */
__IO uint32_t KEY3; /**< Bits[127:96] of the 128-bit key */
__IO uint32_t KEY4; /**< Bits[159:128] of the 256-bit key */
__IO uint32_t KEY5; /**< Bits[191:160] of the 256-bit key */
__IO uint32_t KEY6; /**< Bits[223:192] of the 256-bit key */
__IO uint32_t KEY7; /**< Bits[255:224] of the 256-bit key */
__IO uint32_t CNTi0; /**< Bits[31:00] of the 128-bit counter value used in counter mode */
__IO uint32_t CNTi1; /**< Bits[63:32] of the 128-bit counter value used in counter mode */
__IO uint32_t CNTi2; /**< Bits[95:64] of the 128-bit counter value used in counter mode */
__IO uint32_t CNTi3; /**< Bits[127:96] of the 128-bit counter value used in counter mode */
__I uint32_t CNTo0; /**< Bits[31:00] of the 128-bit counter result */
__I uint32_t CNTo1; /**< Bits[63:32] of the 128-bit counter result */
__I uint32_t CNTo2; /**< Bits[95:64] of the 128-bit counter result */
__I uint32_t CNTo3; /**< Bits[127:96] of the 128-bit counter result */
__IO uint32_t CNTi0; /**< Bits[31:00] of the 128-bit counter value used in counter mode */
__IO uint32_t CNTi1; /**< Bits[63:32] of the 128-bit counter value used in counter mode */
__IO uint32_t CNTi2; /**< Bits[95:64] of the 128-bit counter value used in counter mode */
__IO uint32_t CNTi3; /**< Bits[127:96] of the 128-bit counter value used in counter mode */
__I uint32_t CNTo0; /**< Bits[31:00] of the 128-bit counter result */
__I uint32_t CNTo1; /**< Bits[63:32] of the 128-bit counter result */
__I uint32_t CNTo2; /**< Bits[95:64] of the 128-bit counter result */
__I uint32_t CNTo3; /**< Bits[127:96] of the 128-bit counter result */
__I uint32_t CBCo0; /**< Bits[31:00] of the 128-bit CBC result */
__I uint32_t CBCo1; /**< Bits[63:32] of the 128-bit CBC result */
__I uint32_t CBCo2; /**< Bits[95:64] of the 128-bit CBC result */
__I uint32_t CBCo3; /**< Bits[127:96] of the 128-bit CBC result */
union {
struct {
__O uint32_t START:1; /**< start the encryption : 0 = no-effect , 1 = enable */
__O uint32_t ACC_CLR:1; /**< Clear the CBC accumulator : 0 = no-effect 1 = clears the CBC accumulator */
__O uint32_t INT_CLEAR:1; /**< interrupt clear : 0 = no-effect 1 = clear the interrupt */
__O uint32_t KEY_LENGTH:1; /**< Key Length: 0 = 128 Bit Encryption 1 = 256 Bit Encryption */
} BITS;
__O uint32_t WORD;
} CTL;
union {
struct {
__IO uint32_t CBC_MODE:1; /**< counter mode : 0 = counter mode , 1 = CBC mode */
__IO uint32_t BYPASS:1; /**< encryption : 0 = Normal Mode , 1 = Bypasss any encryption */
__IO uint32_t INT_EN:1; /**< interrupt mask : 0 = disabled 1 = enabled */
} BITS;
__IO uint32_t WORD;
} MODE;
union {
struct {
__I uint32_t COMPLETE:1;/**< status : 0 = not complete , 1 = complete */
} BITS;
__IO uint32_t WORD;
} STAT;
__I uint32_t CBCo0; /**< Bits[31:00] of the 128-bit CBC result */
__I uint32_t CBCo1; /**< Bits[63:32] of the 128-bit CBC result */
__I uint32_t CBCo2; /**< Bits[95:64] of the 128-bit CBC result */
__I uint32_t CBCo3; /**< Bits[127:96] of the 128-bit CBC result */
union {
struct {
__O uint32_t START:1; /**< start the encryption : 0 = no-effect , 1 = enable */
__O uint32_t ACC_CLR:1; /**< Clear the CBC accumulator : 0 = no-effect 1 = clears the CBC accumulator */
__O uint32_t INT_CLEAR:1; /**< interrupt clear : 0 = no-effect 1 = clear the interrupt */
__O uint32_t KEY_LENGTH:1; /**< Key Length: 0 = 128 Bit Encryption 1 = 256 Bit Encryption */
} BITS;
__O uint32_t WORD;
} CTL;
union {
struct {
__IO uint32_t CBC_MODE:1; /**< counter mode : 0 = counter mode , 1 = CBC mode */
__IO uint32_t BYPASS:1; /**< encryption : 0 = Normal Mode , 1 = Bypasss any encryption */
__IO uint32_t INT_EN:1; /**< interrupt mask : 0 = disabled 1 = enabled */
} BITS;
__IO uint32_t WORD;
} MODE;
union {
struct {
__I uint32_t COMPLETE:1;/**< status : 0 = not complete , 1 = complete */
} BITS;
__IO uint32_t WORD;
} STAT;
__O uint32_t MAC_INIT0; /**< Bits[31:00] of the CBC Initialization Vector */
__O uint32_t MAC_INIT1; /**< Bits[63:32] of the CBC Initialization Vector */
__O uint32_t MAC_INIT2; /**< Bits[95:64] of the CBC Initialization Vector */
__O uint32_t MAC_INIT3; /**< Bits[127:96] of the CBC Initialization Vector */
__O uint32_t MAC_INIT0; /**< Bits[31:00] of the CBC Initialization Vector */
__O uint32_t MAC_INIT1; /**< Bits[63:32] of the CBC Initialization Vector */
__O uint32_t MAC_INIT2; /**< Bits[95:64] of the CBC Initialization Vector */
__O uint32_t MAC_INIT3; /**< Bits[127:96] of the CBC Initialization Vector */
__IO uint32_t RESERVED;
__O uint32_t DATA0; /**< Bits[31:00] of the 128-bit data to encrypt */
__O uint32_t DATA1; /**< Bits[63:32] of the 128-bit data to encrypt */
__O uint32_t DATA2; /**< Bits[95:64] of the 128-bit data to encrypt */
__O uint32_t DATA3; /**< Bits[127:96] of the 128-bit data to encrypt */
__IO uint32_t RESERVED;
__O uint32_t DATA0; /**< Bits[31:00] of the 128-bit data to encrypt */
__O uint32_t DATA1; /**< Bits[63:32] of the 128-bit data to encrypt */
__O uint32_t DATA2; /**< Bits[95:64] of the 128-bit data to encrypt */
__O uint32_t DATA3; /**< Bits[127:96] of the 128-bit data to encrypt */
} AesReg_t, *AesReg_pt;
#endif /* AES_MAP_H_ */

199
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/analogin_api.c
View File

@ -48,88 +48,81 @@
*/
void analogin_init(analogin_t *obj, PinName pin)
{
CLOCK_ENABLE(CLOCK_ADC);
CLOCK_ENABLE(CLOCK_ADC);
ADCName adc;
uint8_t adc_pin = 0;
adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(adc != (ADCName)NC);
adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(adc != (ADCName)NC);
obj->adcReg = (AdcReg_pt)adc;
obj->pin = pin;
obj->pinFlag = 1;
obj->adcReg = (AdcReg_pt)adc;
obj->pin = pin;
obj->pinFlag = 1;
switch (pin)
{
case A0:
adc_pin=0;
break;
case A1:
adc_pin = 1;
break;
case A2:
adc_pin = 2;
break;
case A3:
adc_pin = 3;
break;
default:
break;
}
switch (pin) {
case A0:
adc_pin=0;
break;
case A1:
adc_pin = 1;
break;
case A2:
adc_pin = 2;
break;
case A3:
adc_pin = 3;
break;
default:
break;
}
/* If no config parameters are passed on; assume default value */
if (obj->adcConf == Null)
{
/* Single sample, absolute conversion, scale = 1 */
obj->adcReg->CONTROL.WORD = ((0 << ADC_CONTROL_MODE_BIT_POS) |
(1 << ADC_CONTROL_MEASTYPE_BIT_POS) |
(1 << ADC_CONTROL_INPUTSCALE_BIT_POS) |
(((uint8_t)adc_pin) << ADC_CONTROL_MEAS_CH_BIT_POS));
/* If no config parameters are passed on; assume default value */
if (obj->adcConf == Null) {
/* Single sample, absolute conversion, scale = 1 */
obj->adcReg->CONTROL.WORD = ((0 << ADC_CONTROL_MODE_BIT_POS) |
(1 << ADC_CONTROL_MEASTYPE_BIT_POS) |
(1 << ADC_CONTROL_INPUTSCALE_BIT_POS) |
(((uint8_t)adc_pin) << ADC_CONTROL_MEAS_CH_BIT_POS));
/* Prescaler enabled; set to 7 */
obj->adcReg->PRESCALE.WORD = ((True << ADC_PRESCALE_EN_BIT_POS) |
(7 << ADC_PRESCALE_VAL_BIT_POS)); /* ADC clock = 32MHz/(Prescale + 1) */
/* Prescaler enabled; set to 7 */
obj->adcReg->PRESCALE.WORD = ((True << ADC_PRESCALE_EN_BIT_POS) |
(7 << ADC_PRESCALE_VAL_BIT_POS)); /* ADC clock = 32MHz/(Prescale + 1) */
obj->adcReg->DELAY.WORD = ((0x34 << ADC_DELAY_SAMPLE_RATE_BIT_POS) | /** 25 uS Sets the sample rate in units of PCLKperiod * (Prescale + 1). */
(0x05 << ADC_DELAY_WARMUP_BIT_POS) | /** 12.5 uS Sets the measure time in units of PCLKperiod * (Prescale + 1). */
(0x1A << ADC_DELAY_SAMPLE_TIME_BIT_POS)); /** 2.5 uS Sets the warm-up time in units of PCLKperiod * (Prescale + 1). */
obj->adcReg->DELAY.WORD = ((0x34 << ADC_DELAY_SAMPLE_RATE_BIT_POS) | /** 25 uS Sets the sample rate in units of PCLKperiod * (Prescale + 1). */
(0x05 << ADC_DELAY_WARMUP_BIT_POS) | /** 12.5 uS Sets the measure time in units of PCLKperiod * (Prescale + 1). */
(0x1A << ADC_DELAY_SAMPLE_TIME_BIT_POS)); /** 2.5 uS Sets the warm-up time in units of PCLKperiod * (Prescale + 1). */
obj->adcReg->IR = 0; /** No interrupt generated */
}
else
{
obj->adcConf->convCh = adc_pin;
obj->adcReg->IR = 0; /** No interrupt generated */
} else {
obj->adcConf->convCh = adc_pin;
/* ADC register settings */
if((obj->adcConf->measurementType) == ADC_RELATIVE_MEAS)
{
obj->adcReg->CONTROL.WORD = ((obj->adcConf->mode << ADC_CONTROL_MODE_BIT_POS) |
(obj->adcConf->measurementType << ADC_CONTROL_MEASTYPE_BIT_POS) |
(obj->adcConf->inputScale << ADC_CONTROL_INPUTSCALE_BIT_POS) |
(obj->adcConf->convCh << ADC_CONTROL_MEAS_CH_BIT_POS) |
(obj->adcConf->referenceCh << ADC_CONTROL_REF_CH_BIT_POS));
}
else
{
obj->adcReg->CONTROL.WORD = ((obj->adcConf->mode << ADC_CONTROL_MODE_BIT_POS) |
(obj->adcConf->measurementType << ADC_CONTROL_MEASTYPE_BIT_POS) |
(obj->adcConf->inputScale << ADC_CONTROL_INPUTSCALE_BIT_POS) |
(obj->adcConf->convCh << ADC_CONTROL_MEAS_CH_BIT_POS));
}
/* ADC register settings */
if((obj->adcConf->measurementType) == ADC_RELATIVE_MEAS) {
obj->adcReg->CONTROL.WORD = ((obj->adcConf->mode << ADC_CONTROL_MODE_BIT_POS) |
(obj->adcConf->measurementType << ADC_CONTROL_MEASTYPE_BIT_POS) |
(obj->adcConf->inputScale << ADC_CONTROL_INPUTSCALE_BIT_POS) |
(obj->adcConf->convCh << ADC_CONTROL_MEAS_CH_BIT_POS) |
(obj->adcConf->referenceCh << ADC_CONTROL_REF_CH_BIT_POS));
} else {
obj->adcReg->CONTROL.WORD = ((obj->adcConf->mode << ADC_CONTROL_MODE_BIT_POS) |
(obj->adcConf->measurementType << ADC_CONTROL_MEASTYPE_BIT_POS) |
(obj->adcConf->inputScale << ADC_CONTROL_INPUTSCALE_BIT_POS) |
(obj->adcConf->convCh << ADC_CONTROL_MEAS_CH_BIT_POS));
}
obj->adcReg->PRESCALE.WORD = ((True << ADC_PRESCALE_EN_BIT_POS) |
(obj->adcConf->PrescaleVal << ADC_PRESCALE_VAL_BIT_POS)); /* ADC clock = 32MHz/(Prescale + 1) */
obj->adcReg->PRESCALE.WORD = ((True << ADC_PRESCALE_EN_BIT_POS) |
(obj->adcConf->PrescaleVal << ADC_PRESCALE_VAL_BIT_POS)); /* ADC clock = 32MHz/(Prescale + 1) */
obj->adcReg->DELAY.WORD = ((obj->adcConf->samplingRate << ADC_DELAY_SAMPLE_RATE_BIT_POS) | /** 25 uS Sets the sample rate in units of PCLKperiod * (Prescale + 1). */
(obj->adcConf->WarmUpTime << ADC_DELAY_WARMUP_BIT_POS) | /** 12.5 uS Sets the measure time in units of PCLKperiod * (Prescale + 1). */
(obj->adcConf->samplingTime << ADC_DELAY_SAMPLE_TIME_BIT_POS)); /** 2.5 uS Sets the warm-up time in units of PCLKperiod * (Prescale + 1). */
obj->adcReg->DELAY.WORD = ((obj->adcConf->samplingRate << ADC_DELAY_SAMPLE_RATE_BIT_POS) | /** 25 uS Sets the sample rate in units of PCLKperiod * (Prescale + 1). */
(obj->adcConf->WarmUpTime << ADC_DELAY_WARMUP_BIT_POS) | /** 12.5 uS Sets the measure time in units of PCLKperiod * (Prescale + 1). */
(obj->adcConf->samplingTime << ADC_DELAY_SAMPLE_TIME_BIT_POS)); /** 2.5 uS Sets the warm-up time in units of PCLKperiod * (Prescale + 1). */
obj->adcReg->IR = obj->adcConf->interruptConfig; /** Interrupt setting */
}
obj->adcReg->IR = obj->adcConf->interruptConfig; /** Interrupt setting */
}
/* Enable interrupt */
NVIC_ClearPendingIRQ(Adc_IRQn);
NVIC_EnableIRQ(Adc_IRQn);
/* Enable interrupt */
NVIC_ClearPendingIRQ(Adc_IRQn);
NVIC_EnableIRQ(Adc_IRQn);
}
/** Read the input voltage, represented as a float in the range [0.0, 1.0]
@ -152,53 +145,41 @@ float analogin_read(analogin_t *obj)
*/
uint16_t analogin_read_u16(analogin_t *obj)
{
uint16_t adcData = 0;
uint8_t adc_pin = 0;
uint16_t adcData = 0;
uint8_t adc_pin = 0;
CLOCK_ENABLE(CLOCK_ADC);
CLOCK_ENABLE(CLOCK_ADC);
if (obj->pinFlag)
{
switch (obj->pin)
{
case A0:
adc_pin=0;
break;
case A1:
adc_pin = 1;
break;
case A2:
adc_pin = 2;
break;
case A3:
adc_pin = 3;
break;
default:
break;
}
if (obj->pinFlag) {
switch (obj->pin) {
case A0:
adc_pin=0;
break;
case A1:
adc_pin = 1;
break;
case A2:
adc_pin = 2;
break;
case A3:
adc_pin = 3;
break;
default:
break;
}
/* Re initialize the pin configured for ADC read */
obj->adcReg->CONTROL.BITS.CONV_CH = adc_pin;
}
/* Re initialize the pin configured for ADC read */
obj->adcReg->CONTROL.BITS.CONV_CH = adc_pin;
}
obj->adcReg->CONTROL.BITS.START_CONV=1; /* Start The Conversion */
obj->adcReg->CONTROL.BITS.START_CONV=1; /* Start The Conversion */
while((uint32_t)(obj->adcReg->STATUS)!=(uint32_t)1)
{}
adcData =(uint16_t)(obj->adcReg->DATA);
CLOCK_DISABLE(CLOCK_ADC);
while((uint32_t)(obj->adcReg->STATUS)!=(uint32_t)1) {
}
adcData =(uint16_t)(obj->adcReg->DATA);
CLOCK_DISABLE(CLOCK_ADC);
return(adcData);
}
/*ADC handler function */
void fAdcHandler(void)
{
uint16_t adcData = 0;
AdcReg_pt adcReg = (AdcReg_pt)ADC_0;
adcReg->IR = True;
NVIC_ClearPendingIRQ(Adc_IRQn);
adcData =(uint16_t)(adcReg->DATA);
return(adcData);
}
#endif // DEVICE_ANALOGIN

2
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/assert_onsemi.h
View File

@ -37,7 +37,7 @@
#ifdef __cplusplus
extern "C" {
#endif
#ifdef DEBUG
/** Executes when an assertion condition evaluates to false.

58
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h
View File

@ -41,39 +41,39 @@
/** A character driver structure. */
typedef struct char_driver {
/** The parent generic driver. */
driver_t driver;
/** The parent generic driver. */
driver_t driver;
/** Blocking read into a buffer.
* @param device The device to read from.
* @param buf The buffer to read into.
* @param len The number of bytes to read.
*/
uint8_t (*read_b)(device_pt device, uint8_t *const buf, uint32_t len);
/** Blocking read into a buffer.
* @param device The device to read from.
* @param buf The buffer to read into.
* @param len The number of bytes to read.
*/
uint8_t (*read_b)(device_pt device, uint8_t *const buf, uint32_t len);
/** Non-blocking read into a buffer.
* @param device The device to read from.
* @param buf The buffer to read into.
* @param len The maximum number of bytes to read; typically the size of the buffer.
* @return The number of bytes actually read.
*/
uint32_t (*read_nb)(device_pt device, uint8_t *const buf, uint32_t len);
/** Non-blocking read into a buffer.
* @param device The device to read from.
* @param buf The buffer to read into.
* @param len The maximum number of bytes to read; typically the size of the buffer.
* @return The number of bytes actually read.
*/
uint32_t (*read_nb)(device_pt device, uint8_t *const buf, uint32_t len);
/** Blocking write from a buffer.
* @param device The device to write to.
* @param buf The buffer to read from.
* @param len The number of bytes to write; typically the size of the buffer.
* @return success or error message
*/
uint8_t (*write_b)(device_pt device, const uint8_t *buf, uint32_t len);
/** Blocking write from a buffer.
* @param device The device to write to.
* @param buf The buffer to read from.
* @param len The number of bytes to write; typically the size of the buffer.
* @return success or error message
*/
uint8_t (*write_b)(device_pt device, const uint8_t *buf, uint32_t len);
/** Non-blocking write from a buffer.
* @param device The device to write to.
* @param buf The buffer to read from.
* @param len The number of bytes to write; typically the size of the buffer.
* @return success or error message
*/
uint8_t (*write_nb)(device_pt device, const uint8_t *buf, uint32_t len);
/** Non-blocking write from a buffer.
* @param device The device to write to.
* @param buf The buffer to read from.
* @param len The number of bytes to write; typically the size of the buffer.
* @return success or error message
*/
uint8_t (*write_nb)(device_pt device, const uint8_t *buf, uint32_t len);
} char_driver_t, *char_driver_pt;
#endif /* CHAR_DRIVER_H_ */

158
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h
View File

@ -42,85 +42,85 @@
/** Clock control HW structure overlay */
typedef struct {
union {
struct {
__IO uint32_t OSC_SEL:1;
__IO uint32_t PAD0:1;
__IO uint32_t CAL32K:1;
__IO uint32_t CAL32M:1;
__IO uint32_t RTCEN:1;
} BITS;
__IO uint32_t WORD;
} CCR; /**< 0x4001B000 Clock control register */
union {
struct {
__I uint32_t XTAL32M:1;
__I uint32_t XTAL32K:1;
__I uint32_t CAL32K:1;
__I uint32_t DONE32K:1;
__I uint32_t CAL32MFAIL:1;
__I uint32_t CAL32MDONE:1;
} BITS;
__I uint32_t WORD;
} CSR; /**< 0x4001B004 Clock status register */
union {
struct {
__IO uint32_t IE32K:1;
__IO uint32_t IE32M:1;
} BITS;
__IO uint32_t WORD;
} IER; /**< 0x4001B008 Interrup enable register */
__IO uint32_t ICR; /**< 0x4001B00C Interrupt clear register */
union {
struct {
__IO uint32_t TIMER0:1;
__IO uint32_t TIMER1:1;
__IO uint32_t TIMER2:1;
__IO uint32_t PAD0:2;
__IO uint32_t UART1:1;
__IO uint32_t SPI:1;
__IO uint32_t I2C:1;
__IO uint32_t UART2:1;
__IO uint32_t PAD1:1;
__IO uint32_t WDOG:1;
__IO uint32_t PWM:1;
__IO uint32_t GPIO:1;
__IO uint32_t PAD2:2;
__IO uint32_t RTC:1;
__IO uint32_t XBAR:1;
__IO uint32_t RAND:1;
__IO uint32_t PAD3:2;
__IO uint32_t MACHW:1;
__IO uint32_t ADC:1;
__IO uint32_t AES:1;
__IO uint32_t FLASH:1;
__IO uint32_t PAD4:1;
__IO uint32_t RFANA:1;
__IO uint32_t IO:1;
__IO uint32_t PAD5:1;
__IO uint32_t PAD:1;
__IO uint32_t PMU:1;
__IO uint32_t PAD6:1;
__IO uint32_t TEST:1;
} BITS;
__IO uint32_t WORD;
} PDIS; /**< 0x4001B010 Periphery disable */
__IO uint32_t FDIV; /**< 0x4001B014 FCLK divider */
__IO uint32_t TDIV; /**< 0x4001B01C Traceclk divider */
__IO uint32_t WDIV; /**< 0x4001B020 Watchdog clock divider */
__IO uint32_t TRIM_32M_INT; /**< 0x4001B024 32Mhz internal trim */
__IO uint32_t TRIM_32K_INT; /**< 0x4001B02C 32kHz internal trim */
__IO uint32_t TRIM_32M_EXT; /**< 0x4001B030 32Mhz external trim */
__IO uint32_t TRIM_32K_EXT; /**< 0x4001B034 32Khz external trim */
union {
struct {
__IO uint32_t OV32M;
__IO uint32_t EN32M;
__IO uint32_t OV32K;
__IO uint32_t EN32K;
} BITS;
__IO uint32_t WORD;
} CER; /**< 0x4001B038 clock enable register*/
union {
struct {
__IO uint32_t OSC_SEL:1;
__IO uint32_t PAD0:1;
__IO uint32_t CAL32K:1;
__IO uint32_t CAL32M:1;
__IO uint32_t RTCEN:1;
} BITS;
__IO uint32_t WORD;
} CCR; /**< 0x4001B000 Clock control register */
union {
struct {
__I uint32_t XTAL32M:1;
__I uint32_t XTAL32K:1;
__I uint32_t CAL32K:1;
__I uint32_t DONE32K:1;
__I uint32_t CAL32MFAIL:1;
__I uint32_t CAL32MDONE:1;
} BITS;
__I uint32_t WORD;
} CSR; /**< 0x4001B004 Clock status register */
union {
struct {
__IO uint32_t IE32K:1;
__IO uint32_t IE32M:1;
} BITS;
__IO uint32_t WORD;
} IER; /**< 0x4001B008 Interrup enable register */
__IO uint32_t ICR; /**< 0x4001B00C Interrupt clear register */
union {
struct {
__IO uint32_t TIMER0:1;
__IO uint32_t TIMER1:1;
__IO uint32_t TIMER2:1;
__IO uint32_t PAD0:2;
__IO uint32_t UART1:1;
__IO uint32_t SPI:1;
__IO uint32_t I2C:1;
__IO uint32_t UART2:1;
__IO uint32_t PAD1:1;
__IO uint32_t WDOG:1;
__IO uint32_t PWM:1;
__IO uint32_t GPIO:1;
__IO uint32_t PAD2:2;
__IO uint32_t RTC:1;
__IO uint32_t XBAR:1;
__IO uint32_t RAND:1;
__IO uint32_t PAD3:2;
__IO uint32_t MACHW:1;
__IO uint32_t ADC:1;
__IO uint32_t AES:1;
__IO uint32_t FLASH:1;
__IO uint32_t PAD4:1;
__IO uint32_t RFANA:1;
__IO uint32_t IO:1;
__IO uint32_t PAD5:1;
__IO uint32_t PAD:1;
__IO uint32_t PMU:1;
__IO uint32_t PAD6:1;
__IO uint32_t TEST:1;
} BITS;
__IO uint32_t WORD;
} PDIS; /**< 0x4001B010 Periphery disable */
__IO uint32_t FDIV; /**< 0x4001B014 FCLK divider */
__IO uint32_t TDIV; /**< 0x4001B01C Traceclk divider */
__IO uint32_t WDIV; /**< 0x4001B020 Watchdog clock divider */
__IO uint32_t TRIM_32M_INT; /**< 0x4001B024 32Mhz internal trim */
__IO uint32_t TRIM_32K_INT; /**< 0x4001B02C 32kHz internal trim */
__IO uint32_t TRIM_32M_EXT; /**< 0x4001B030 32Mhz external trim */
__IO uint32_t TRIM_32K_EXT; /**< 0x4001B034 32Khz external trim */
union {
struct {
__IO uint32_t OV32M;
__IO uint32_t EN32M;
__IO uint32_t OV32K;
__IO uint32_t EN32K;
} BITS;
__IO uint32_t WORD;
} CER; /**< 0x4001B038 clock enable register*/
} ClockReg_t, *ClockReg_pt;
#endif /* CLOCK_MAP_H_ */

36
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/crossbar_map.h
View File

@ -42,24 +42,24 @@
/* Crossbar Control HW Structure Overlay */
typedef struct {
__IO uint32_t DIOCTRL0; /**< Switch IO0 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL1; /**< Switch IO1 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL2; /**< Switch IO2 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL3; /**< Switch IO3 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL4; /**< Switch IO4 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL5; /**< Switch IO5 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL6; /**< Switch IO6 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL7; /**< Switch IO7 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL8; /**< Switch IO8 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL9; /**< Switch IO9 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL10; /**< Switch IO10 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL11; /**< Switch IO11 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL12; /**< Switch IO12 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL13; /**< Switch IO13 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL14; /**< Switch IO14 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL15; /**< Switch IO15 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL16; /**< Switch IO16 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL17; /**< Switch IO17 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL0; /**< Switch IO0 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL1; /**< Switch IO1 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL2; /**< Switch IO2 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL3; /**< Switch IO3 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL4; /**< Switch IO4 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL5; /**< Switch IO5 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL6; /**< Switch IO6 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL7; /**< Switch IO7 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL8; /**< Switch IO8 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL9; /**< Switch IO9 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL10; /**< Switch IO10 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL11; /**< Switch IO11 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL12; /**< Switch IO12 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL13; /**< Switch IO13 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL14; /**< Switch IO14 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL15; /**< Switch IO15 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL16; /**< Switch IO16 to GPIO(default) or peripheral device */
__IO uint32_t DIOCTRL17; /**< Switch IO17 to GPIO(default) or peripheral device */
} CrossbReg_t, *CrossbReg_pt;
#endif /* CROSSB_MAP_H_ */

120
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h
View File

@ -42,73 +42,61 @@
/** DMA control HW registers structure overlay */
#ifdef REVB
typedef struct
{
__IO uint32_t CONTROL; /**< Write 1 to enable DMA, write 0 to disable */
__IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
__IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
__IO uint32_t SIZE; /**< Lenght of the entire transfer */
__IO uint32_t STATUS; /**< To be debined */
__IO uint32_t INT_ENABLE; /**< Enable interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
__IO uint32_t INT_CLEAR_ENABLE; /**< Clear Interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
__I uint32_t INT_STATUS; /**< Current interrupt status. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
}DmaReg_t, *DmaReg_pt;
typedef struct {
__IO uint32_t CONTROL; /**< Write 1 to enable DMA, write 0 to disable */
__IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
__IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
__IO uint32_t SIZE; /**< Lenght of the entire transfer */
__IO uint32_t STATUS; /**< To be debined */
__IO uint32_t INT_ENABLE; /**< Enable interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
__IO uint32_t INT_CLEAR_ENABLE; /**< Clear Interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
__I uint32_t INT_STATUS; /**< Current interrupt status. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
} DmaReg_t, *DmaReg_pt;
#endif /* REVB */
#ifdef REVD
typedef struct
{
union
{
struct
{
__IO uint32_t ENABLE:1; /**< DMA enable: 1 to enable; 0 to disable */
__IO uint32_t MODE :2; /**< DMA mode: 00 – Memory to memory; 01 – Memory to peripheral; 10 – Peripheral to memory; 11 – Peripheral to peripheral */
}BITS;
__IO uint32_t WORD;
}CONTROL; /**< Control register */
__IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
__IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
__IO uint32_t SIZE; /**< Lenght of the entire transfer */
union
{
struct
{
__I uint32_t COMPLETED:1; /**< Done: 0 – Not complete, 1 – Complete */
__I uint32_t SOURCE_ERROR:1; /**< Source Error: 0 – No Error, 1 – Error */
__I uint32_t DESTINATION_ERROR:1; /**< Destination Error: 0 – No Error, 1 – Source Error */
}BITS;
__I uint32_t WORD;
}STATUS; /**< Status register */
union
{
struct
{
__IO uint32_t COMPLETED:1; /**< A write of ‘1’ enables the interrupt generated by a DMA transfer complete */
__IO uint32_t SOURCE_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the source side of the DMA transfer */
__IO uint32_t DESTINATION_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the destination side of the DMA transfer */
}BITS;
__IO uint32_t WORD;
}INT_ENABLE; /**< Interrupt enable */
union
{
struct
{
__IO uint32_t COMPLETED:1; /**< A write clears the interrupt generated by a DMA transfer complete */
__IO uint32_t SOURCE_ERROR:1; /**< A write clears the interrupt generated by an error on the source side of the DMA transfer */
__IO uint32_t DESTINATION_ERROR:1; /**< A write clears the interrupt generated by an error on the destination side of the DMA transfer */
}BITS;
__IO uint32_t WORD;
}INT_CLEAR; /**< Interrupt clear */
union
{
struct
{
__I uint32_t COMPLETED:1; /**< Transfer complete interrupt */
__I uint32_t SOURCE_ERROR:1; /**< Source error interrupt */
__I uint32_t DESTINATION_ERROR:1; /**< Destination error interrupt */
}BITS;
__I uint32_t WORD;
}INT_STATUS; /**< Interrupt status */
}DmaReg_t, *DmaReg_pt;
typedef struct {
union {
struct {
__IO uint32_t ENABLE:1; /**< DMA enable: 1 to enable; 0 to disable */
__IO uint32_t MODE :2; /**< DMA mode: 00 – Memory to memory; 01 – Memory to peripheral; 10 – Peripheral to memory; 11 – Peripheral to peripheral */
} BITS;
__IO uint32_t WORD;
} CONTROL; /**< Control register */
__IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
__IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
__IO uint32_t SIZE; /**< Lenght of the entire transfer */
union {
struct {
__I uint32_t COMPLETED:1; /**< Done: 0 – Not complete, 1 – Complete */
__I uint32_t SOURCE_ERROR:1; /**< Source Error: 0 – No Error, 1 – Error */
__I uint32_t DESTINATION_ERROR:1; /**< Destination Error: 0 – No Error, 1 – Source Error */
} BITS;
__I uint32_t WORD;
} STATUS; /**< Status register */
union {
struct {
__IO uint32_t COMPLETED:1; /**< A write of ‘1’ enables the interrupt generated by a DMA transfer complete */
__IO uint32_t SOURCE_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the source side of the DMA transfer */
__IO uint32_t DESTINATION_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the destination side of the DMA transfer */
} BITS;
__IO uint32_t WORD;
} INT_ENABLE; /**< Interrupt enable */
union {
struct {
__IO uint32_t COMPLETED:1; /**< A write clears the interrupt generated by a DMA transfer complete */
__IO uint32_t SOURCE_ERROR:1; /**< A write clears the interrupt generated by an error on the source side of the DMA transfer */
__IO uint32_t DESTINATION_ERROR:1; /**< A write clears the interrupt generated by an error on the destination side of the DMA transfer */
} BITS;
__IO uint32_t WORD;
} INT_CLEAR; /**< Interrupt clear */
union {
struct {
__I uint32_t COMPLETED:1; /**< Transfer complete interrupt */
__I uint32_t SOURCE_ERROR:1; /**< Source error interrupt */
__I uint32_t DESTINATION_ERROR:1; /**< Destination error interrupt */
} BITS;
__I uint32_t WORD;
} INT_STATUS; /**< Interrupt status */
} DmaReg_t, *DmaReg_pt;
#endif /* REVD */
#endif /* DMA_MAP_H_ */

49
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/exceptions.c
View File

@ -57,13 +57,15 @@ extern void fSysTickHandler(void);
*************************************************************************************************/
/** Not implemented exception, exception handler */
void NotImplemented_Handler(void){
while (1){};
void NotImplemented_Handler(void)
{
while (1) {};
}
/** Hardware fault interrupt handler */
void HardFault_Handler(void) {
while (1){};
void HardFault_Handler(void)
{
while (1) {};
}
/*************************************************************************************************
@ -71,55 +73,54 @@ void HardFault_Handler(void) {
* Functions *
* *
*************************************************************************************************/
/** Call the MacHw IRQ handler */
/* commented out - implemented in network stack
void fIrqMacHwHandler() {
NotImplemented_Handler();
}
*/
/** MacHw IRQ handler implemented in the RF driver stack */
/** Call the Timer0 IRQ handler */
void fIrqTim0Handler() {
void fIrqTim0Handler()
{
us_timer_isr();
}
/** Call the Timer1 IRQ handler */
void fIrqTim1Handler() {
void fIrqTim1Handler()
{
us_ticker_isr();
}
/** Call the Timer2 IRQ handler */
void fIrqTim2Handler() {
void fIrqTim2Handler()
{
NotImplemented_Handler();
}
/** Call the Gpio IRQ handler */
void fIrqGpioHandler() {
#if DEVICE_INTERRUPTIN
fGpioHandler();
#endif
void fIrqGpioHandler()
{
fGpioHandler();
}
/** Call the Spi IRQ handler */
void fIrqSpiHandler() {
void fIrqSpiHandler()
{
NotImplemented_Handler();
}
/** Call the Uart 1 IRQ handler */
void fIrqUart1Handler(void) {
Uart1_Irq();
void fIrqUart1Handler(void)
{
Uart1_Irq();
}
/** Call the Uart 2 IRQ handler */
void fIrqUart2Handler(void) {
Uart2_Irq();
void fIrqUart2Handler(void)
{
Uart2_Irq();
}
/** Call the RTC IRQ handler */
void fIrqRtcHandler(void)
{
fRtcHandler();
fRtcHandler();
}
/** Call the I2C IRQ handler */

8
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/fib.h
View File

@ -34,10 +34,10 @@
* *
**************************************************************************************************/
typedef struct {
unsigned int fwbase_address;
mib_systemRevision_t fw_version;
}fibtable_t;
typedef struct {
unsigned int fwbase_address;
mib_systemRevision_t fw_version;
} fibtable_t;
#endif

80
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/flash_map.h
View File

@ -33,46 +33,46 @@
/** Flash Control HW Structure Overlay */
typedef struct {
union {
struct {
__I uint32_t FLASH_A_BUSY:1; /**< Busy A */
__I uint32_t FLASH_B_BUSY:1; /**< Busy B */
__I uint32_t FLASH_A_UNLOCK:1; /**< Unlock A */
__I uint32_t FLASH_B_UNLOCK:1; /**< Unlock B */
__I uint32_t FLASH_ERROR:3; /**< 000 – No Error, 111 – Attempt to access an array while it is busy powering up, 001 – Attempt to erase bootloader in the field, 010 – Attempt to access array during erase, 100 – Attempt to access array during write */
} BITS;
__I uint32_t WORD;
} STATUS;
union {
struct {
__IO uint32_t FLASHB_PD:1;
__IO uint32_t FLASHA_PD:1;
__IO uint32_t REMAP:1;
__IO uint32_t WR_INT_EN:1;
__IO uint32_t ERASE_INT_EN:1;
__IO uint32_t ERROR_INT_EN:1;
__IO uint32_t WRITE_BLOCK:1;
} BITS;
__IO uint32_t WORD;
} CONTROL;
union {
struct {
__IO uint32_t PAGEERASE:1; /**< Erase a single page */
__IO uint32_t MASSERASE:1; /**< MASS Erase */
} BITS;
__IO uint32_t WORD;
} COMMAND;
__IO uint32_t ADDR;
__IO uint32_t UNLOCK1;
__IO uint32_t UNLOCKA;
__IO uint32_t UNLOCKB;
union {
struct {
__I uint32_t INT_PEND:1; // Interrupt pending
__I uint32_t INT_TYPE:3; // Interrupt type
} BITS;
__I uint32_t WORD;
} INT_STATUS;
union {
struct {
__I uint32_t FLASH_A_BUSY:1; /**< Busy A */
__I uint32_t FLASH_B_BUSY:1; /**< Busy B */
__I uint32_t FLASH_A_UNLOCK:1; /**< Unlock A */
__I uint32_t FLASH_B_UNLOCK:1; /**< Unlock B */
__I uint32_t FLASH_ERROR:3; /**< 000 – No Error, 111 – Attempt to access an array while it is busy powering up, 001 – Attempt to erase bootloader in the field, 010 – Attempt to access array during erase, 100 – Attempt to access array during write */
} BITS;
__I uint32_t WORD;
} STATUS;
union {
struct {
__IO uint32_t FLASHB_PD:1;
__IO uint32_t FLASHA_PD:1;
__IO uint32_t REMAP:1;
__IO uint32_t WR_INT_EN:1;
__IO uint32_t ERASE_INT_EN:1;
__IO uint32_t ERROR_INT_EN:1;
__IO uint32_t WRITE_BLOCK:1;
} BITS;
__IO uint32_t WORD;
} CONTROL;
union {
struct {
__IO uint32_t PAGEERASE:1; /**< Erase a single page */
__IO uint32_t MASSERASE:1; /**< MASS Erase */
} BITS;
__IO uint32_t WORD;
} COMMAND;
__IO uint32_t ADDR;
__IO uint32_t UNLOCK1;
__IO uint32_t UNLOCKA;
__IO uint32_t UNLOCKB;
union {
struct {
__I uint32_t INT_PEND:1; // Interrupt pending
__I uint32_t INT_TYPE:3; // Interrupt type
} BITS;
__I uint32_t WORD;
} INT_STATUS;
} FlashReg_t, *FlashReg_pt;
#endif /* FLASH_MAP_H_ */

10
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio.h
View File

@ -39,7 +39,7 @@
#ifdef __cplusplus
extern "C" {
#endif
#include "memory_map.h"
#include "gpio_map.h"
#include "pad_map.h"
@ -47,13 +47,13 @@ extern "C" {
#include "clock.h"
#include "pad.h"
/** output configuration push/pull */
#define PAD_OUTCFG_PUSHPULL (uint8_t)0x00
/** output configuration open drain */
#define PAD_OOUTCFG_OPENDRAIN (uint8_t)0x01
#define PAD_OOUTCFG_OPENDRAIN (uint8_t)0x01
/** no pull up nor pull down */
#define PAD_PULL_NONE (uint8_t)0x01

132
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_api.c
View File

@ -4,7 +4,7 @@
* @brief Implementation of a GPIO driver
* @internal
* @author ON Semiconductor
* $Rev:
* $Rev:
* $Date: 2015-11-04 $
******************************************************************************
* @copyright (c) 2012 ON Semiconductor. All rights reserved.
@ -33,7 +33,7 @@
* <p>
* Each GPIO line can be independently programmed as an input or an output. Separate Set
* and Clear registers are provided since it is likely that different software tasks may be
* servicing different I/O signals. Inputs are synchronized to the system clock
* servicing different I/O signals. Inputs are synchronized to the system clock
* through a pair of flip-flops. Each input can be programmed
* to cause an interrupt to be generated. The interrupt can be programmed to be level-sensitive
* or edge-sensitive and the level (high or low) or edge (rising, falling or either) that causes
@ -59,7 +59,7 @@
#include "gpio.h"
/* Include from the mbed-hal layer */
#include "gpio_api.h"
#include "gpio_api.h"
#include "pinmap.h"
@ -70,17 +70,16 @@
**/
uint32_t gpio_set(PinName pin)
{
if (pin != NC)
{
/* Configure to GPIO using pin function API*/
if (pin != NC) {
/* Configure to GPIO using pin function API*/
pin_function(pin, CONFIGURE_AS_GPIO);
return ((uint32_t) 0x1 << pin);
}
return(0x00000000);
}
return(0x00000000);
}
/** Initialize the GPIO pin
@ -90,31 +89,31 @@ uint32_t gpio_set(PinName pin)
*/
void gpio_init(gpio_t *obj, PinName pin)
{
/* Initialize the GPIO membase */
obj->GPIOMEMBASE = GPIOREG;
/* Initialize the pin to be GPIO */
obj->gpioPin = pin;
obj->gpioMask = gpio_set(pin);
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
/* Set the drive strength of the pin to 1 by default */
/** - Get PAD IO register address for the PAD number */
PadReg_t *PadRegOffset = (PadReg_t*)(PADREG_BASE + (pin * PAD_REG_ADRS_BYTE_SIZE));
/* Initialize the GPIO membase */
obj->GPIOMEMBASE = GPIOREG;
/* - Disable the GPIO clock */
CLOCK_DISABLE(CLOCK_GPIO);
/* Initialize the pin to be GPIO */
obj->gpioPin = pin;
obj->gpioMask = gpio_set(pin);
/** - Enable the clock for PAD peripheral device */
CLOCK_ENABLE(CLOCK_PAD);
/** - Set drive type, pulltype & drive strength */
PadRegOffset->PADIO0.BITS.POWER = 1;
/** - Disable the clock for PAD peripheral device */
CLOCK_DISABLE(CLOCK_PAD);
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
/* Set the drive strength of the pin to 1 by default */
/** - Get PAD IO register address for the PAD number */
PadReg_t *PadRegOffset = (PadReg_t*)(PADREG_BASE + (pin * PAD_REG_ADRS_BYTE_SIZE));
/* - Disable the GPIO clock */
CLOCK_DISABLE(CLOCK_GPIO);
/** - Enable the clock for PAD peripheral device */
CLOCK_ENABLE(CLOCK_PAD);
/** - Set drive type, pulltype & drive strength */
PadRegOffset->PADIO0.BITS.POWER = 1;
/** - Disable the clock for PAD peripheral device */
CLOCK_DISABLE(CLOCK_PAD);
}
/** Set the input pin mode
@ -124,10 +123,10 @@ void gpio_init(gpio_t *obj, PinName pin)
*/
void gpio_mode(gpio_t *obj, PinMode mode)
{
uint32_t pin = obj->gpioPin;
/* Set the mode for the pin */
pin_mode((PinName)pin, mode);
uint32_t pin = obj->gpioPin;
/* Set the mode for the pin */
pin_mode((PinName)pin, mode);
}
/** Set the pin direction
@ -137,17 +136,17 @@ void gpio_mode(gpio_t *obj, PinMode mode)
*/
void gpio_dir(gpio_t *obj, PinDirection direction)
{
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
if (direction == PIN_INPUT) {
obj->GPIOMEMBASE->W_IN = obj->gpioMask;
} else if (direction == PIN_OUTPUT) {
obj->GPIOMEMBASE->W_OUT = obj->gpioMask;
}
if (direction == PIN_INPUT) {
obj->GPIOMEMBASE->W_IN = obj->gpioMask;
} else if (direction == PIN_OUTPUT) {
obj->GPIOMEMBASE->W_OUT = obj->gpioMask;
}
/* - Disable the GPIO clock */
CLOCK_DISABLE(CLOCK_GPIO);
/* - Disable the GPIO clock */
CLOCK_DISABLE(CLOCK_GPIO);
}
/** Set the output value
@ -157,21 +156,18 @@ void gpio_dir(gpio_t *obj, PinDirection direction)
*/
void gpio_write(gpio_t *obj, int value)
{
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
/* Set the GPIO based on value */
if (value)
{
obj->GPIOMEMBASE->R_STATE_W_SET = obj->gpioMask;
}
else
{
obj->GPIOMEMBASE->R_IRQ_W_CLEAR = obj->gpioMask;
}
/* Set the GPIO based on value */
if (value) {
obj->GPIOMEMBASE->R_STATE_W_SET = obj->gpioMask;
} else {
obj->GPIOMEMBASE->R_IRQ_W_CLEAR = obj->gpioMask;
}
/* - Disable the GPIO clock */
CLOCK_DISABLE(CLOCK_GPIO);
/* - Disable the GPIO clock */
CLOCK_DISABLE(CLOCK_GPIO);
}
/** Read the input value
@ -181,15 +177,15 @@ void gpio_write(gpio_t *obj, int value)
*/
int gpio_read(gpio_t *obj)
{
int ret;
int ret;
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
ret = (obj->GPIOMEMBASE->R_STATE_W_SET & obj->gpioMask) ? 1: 0;
ret = (obj->GPIOMEMBASE->R_STATE_W_SET & obj->gpioMask) ? 1: 0;
/* - Disable the GPIO clock */
CLOCK_DISABLE(CLOCK_GPIO);
/* - Disable the GPIO clock */
CLOCK_DISABLE(CLOCK_GPIO);
return ret;
return ret;
}

216
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_irq_api.c
View File

@ -4,7 +4,7 @@
* @brief Implementation of a GPIO irq handlers
* @internal
* @author ON Semiconductor
* $Rev:
* $Rev:
* $Date: 2015-11-04 $
******************************************************************************
* @copyright (c) 2012 ON Semiconductor. All rights reserved.
@ -33,7 +33,7 @@
* <p>
* Each GPIO line can be independently programmed as an input or an output. Separate Set
* and Clear registers are provided since it is likely that different software tasks may be
* servicing different I/O signals. Inputs are synchronized to the system clock
* servicing different I/O signals. Inputs are synchronized to the system clock
* through a pair of flip-flops. Each input can be programmed
* to cause an interrupt to be generated. The interrupt can be programmed to be level-sensitive
* or edge-sensitive and the level (high or low) or edge (rising, falling or either) that causes
@ -63,7 +63,7 @@
/* Include files from the mbed-hal layer */
#include "gpio_irq_api.h"
#include "device.h"
#include "device.h"
#if DEVICE_INTERRUPTIN
@ -78,45 +78,43 @@ static uint32_t gpioIds[NUMBER_OF_GPIO] = {0};
*/
void fGpioHandler(void)
{
uint8_t index;
uint32_t active_interrupts = 0;
gpio_irq_event event;
GpioReg_pt gpioBase;
uint8_t index;
uint32_t active_interrupts = 0;
gpio_irq_event event;
GpioReg_pt gpioBase;
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
gpioBase = GPIOREG;
gpioBase = GPIOREG;
/** - Store all active interrupts */
active_interrupts = gpioBase->R_IRQ_W_CLEAR;
/** - Store all active interrupts */
active_interrupts = gpioBase->R_IRQ_W_CLEAR;
for (index=0; index < NUMBER_OF_GPIO; index++)
{
for (index=0; index < NUMBER_OF_GPIO; index++) {
/* Check the pin for which IRQ is raised */
if ((active_interrupts >> index) & 0x01)
{
/* Check if it is edge triggered and clear the interrupt */
if ((gpioBase->IRQ_EDGE >> index) & 0x01){
if ((gpioBase->IRQ_POLARITY_SET >> index) &0x01) {
/* Edge triggered high */
event = IRQ_RISE;
} else if ((gpioBase->IRQ_POLARITY_CLEAR >> index) &0x01) {
/* Edge triggered low */
event = IRQ_FALL;
} else {
/* Edge none */
event = IRQ_NONE;
/* Check the pin for which IRQ is raised */
if ((active_interrupts >> index) & 0x01) {
/* Check if it is edge triggered and clear the interrupt */
if ((gpioBase->IRQ_EDGE >> index) & 0x01) {
if ((gpioBase->IRQ_POLARITY_SET >> index) &0x01) {
/* Edge triggered high */
event = IRQ_RISE;
} else if ((gpioBase->IRQ_POLARITY_CLEAR >> index) &0x01) {
/* Edge triggered low */
event = IRQ_FALL;
} else {
/* Edge none */
event = IRQ_NONE;
}
}
gpioBase->IRQ_CLEAR |= (0x1 << index);
/* Call the handler registered to the pin */
irq_handler(gpioIds[index], event);
}
}
gpioBase->IRQ_CLEAR |= (0x1 << index);
/* Call the handler registered to the pin */
irq_handler(gpioIds[index], event);
}
}
}
/** Initialize the GPIO IRQ pin
@ -129,44 +127,43 @@ void fGpioHandler(void)
*/
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
{
/* If Pin is not connected; then return -1 */
if (pin == NC)
{
return(-1);
}
/* If Pin is not connected; then return -1 */
if (pin == NC) {
return(-1);
}
/* Store the pin for which handler is registered */
obj->pin = pin;
obj->pinMask = (0x1 << pin);
/* Store the ID, this is required by registered handler function */
gpioIds[pin] = id;
/* Store the pin for which handler is registered */
obj->pin = pin;
obj->pinMask = (0x1 << pin);
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
/* Store the ID, this is required by registered handler function */
gpioIds[pin] = id;
/* Initialize the GPIO membase */
obj->GPIOMEMBASE = GPIOREG;
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
/* Set default values for the pin interrupt */
/* TODO: Only one DIO line is configured using this function; overrides other DIO line setting
* If mbed layer wants to call this function repeatedly for setting multiple DIO lines as input
* then change this setting to obj->GPIOMEMBASE->W_IN |= obj->pinMask. All parameter setting needs to change from = to |=
*/
obj->GPIOMEMBASE->W_IN = obj->pinMask;
obj->GPIOMEMBASE->IRQ_ENABLE_SET = obj->pinMask;
obj->GPIOMEMBASE->IRQ_EDGE = obj->pinMask;
obj->GPIOMEMBASE->IRQ_POLARITY_SET = (obj->pinMask);
obj->GPIOMEMBASE->ANYEDGE_SET = IO_NONE;
/* Initialize the GPIO membase */
obj->GPIOMEMBASE = GPIOREG;
/* Register the handler for this pin */
irq_handler = handler;
/* Set default values for the pin interrupt */
/* TODO: Only one DIO line is configured using this function; overrides other DIO line setting
* If mbed layer wants to call this function repeatedly for setting multiple DIO lines as input
* then change this setting to obj->GPIOMEMBASE->W_IN |= obj->pinMask. All parameter setting needs to change from = to |=
*/
obj->GPIOMEMBASE->W_IN = obj->pinMask;
obj->GPIOMEMBASE->IRQ_ENABLE_SET = obj->pinMask;
obj->GPIOMEMBASE->IRQ_EDGE = obj->pinMask;
obj->GPIOMEMBASE->IRQ_POLARITY_SET = (obj->pinMask);
obj->GPIOMEMBASE->ANYEDGE_SET = IO_NONE;
/* Enable interruption associated with the gpio */
NVIC_ClearPendingIRQ(Gpio_IRQn);
NVIC_EnableIRQ(Gpio_IRQn);
/* Register the handler for this pin */
irq_handler = handler;
return(0);
/* Enable interruption associated with the gpio */
NVIC_ClearPendingIRQ(Gpio_IRQn);
NVIC_EnableIRQ(Gpio_IRQn);
return(0);
}
/** Release the GPIO IRQ PIN
@ -175,11 +172,11 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
*/
void gpio_irq_free(gpio_irq_t *obj)
{
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
obj->GPIOMEMBASE->W_IN = (IO_ALL ^ (obj->pinMask));
gpioIds[obj->pin] = 0;
obj->GPIOMEMBASE->W_IN = (IO_ALL ^ (obj->pinMask));
gpioIds[obj->pin] = 0;
}
/** Enable/disable pin IRQ event
@ -191,47 +188,40 @@ void gpio_irq_free(gpio_irq_t *obj)
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
{
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
switch(event)
{
case IRQ_RISE:
obj->GPIOMEMBASE->IRQ_EDGE = (obj->pinMask);
obj->GPIOMEMBASE->IRQ_LEVEL = (IO_ALL ^ (obj->pinMask));
/* Enable is an integer; hence checking for 1 or 0*/
if (enable == 1)
{
/* Enable rising edge */
obj->GPIOMEMBASE->IRQ_POLARITY_SET = (obj->pinMask);
}
else if (enable == 0)
{
/* Disable rising edge */
obj->GPIOMEMBASE->IRQ_POLARITY_SET = (IO_ALL ^ (obj->pinMask));
}
break;
switch(event) {
case IRQ_RISE:
obj->GPIOMEMBASE->IRQ_EDGE = (obj->pinMask);
obj->GPIOMEMBASE->IRQ_LEVEL = (IO_ALL ^ (obj->pinMask));
/* Enable is an integer; hence checking for 1 or 0*/
if (enable == 1) {
/* Enable rising edge */
obj->GPIOMEMBASE->IRQ_POLARITY_SET = (obj->pinMask);
} else if (enable == 0) {
/* Disable rising edge */
obj->GPIOMEMBASE->IRQ_POLARITY_SET = (IO_ALL ^ (obj->pinMask));
}
break;
case IRQ_FALL:
obj->GPIOMEMBASE->IRQ_EDGE = (obj->pinMask);
obj->GPIOMEMBASE->IRQ_LEVEL = (IO_ALL ^ (obj->pinMask));
/* Enable is an integer; hence checking for 1 or 0*/
if (enable == 1)
{
/* Enable falling edge */
obj->GPIOMEMBASE->IRQ_POLARITY_CLEAR = (obj->pinMask);
}
else if (enable == 0)
{
/* Disable falling edge */
obj->GPIOMEMBASE->IRQ_POLARITY_CLEAR = (IO_ALL ^ (obj->pinMask));
}
break;
case IRQ_FALL:
obj->GPIOMEMBASE->IRQ_EDGE = (obj->pinMask);
obj->GPIOMEMBASE->IRQ_LEVEL = (IO_ALL ^ (obj->pinMask));
/* Enable is an integer; hence checking for 1 or 0*/
if (enable == 1) {
/* Enable falling edge */
obj->GPIOMEMBASE->IRQ_POLARITY_CLEAR = (obj->pinMask);
} else if (enable == 0) {
/* Disable falling edge */
obj->GPIOMEMBASE->IRQ_POLARITY_CLEAR = (IO_ALL ^ (obj->pinMask));
}
break;
default:
/* No event is set */
break;
}
default:
/* No event is set */
break;
}
}
@ -242,10 +232,10 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
*/
void gpio_irq_enable(gpio_irq_t *obj)
{
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
obj->GPIOMEMBASE->IRQ_ENABLE_SET = (obj->pinMask);
obj->GPIOMEMBASE->IRQ_ENABLE_SET = (obj->pinMask);
}
/** Disable GPIO IRQ
@ -255,10 +245,10 @@ void gpio_irq_enable(gpio_irq_t *obj)
*/
void gpio_irq_disable(gpio_irq_t *obj)
{
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
obj->GPIOMEMBASE->IRQ_ENABLE_CLEAR = (obj->pinMask);
obj->GPIOMEMBASE->IRQ_ENABLE_CLEAR = (obj->pinMask);
}
#endif //DEVICE_INTERRUPTIN

30
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h
View File

@ -37,23 +37,23 @@
#include "architecture.h"
/** Structure overlay for GPIO control registers, see memory_map.h
/** Structure overlay for GPIO control registers, see memory_map.h
* For most registers, bit lockations match GPIO numbers.*/
typedef struct {
__IO uint32_t R_STATE_W_SET; /**< Read synchronized input / Write ones to bits to set corresponding output IO's*/
__IO uint32_t R_IRQ_W_CLEAR; /**< Read state of irq / Write ones to bits to clear corresponging output IO's */
__IO uint32_t W_OUT; /**< Write ones to set direction to output */
__IO uint32_t W_IN; /**< Write ones to set direction to input */
__IO uint32_t IRQ_ENABLE_SET; /**< Read active high irq enable / Write ones to enable irq */
__IO uint32_t IRQ_ENABLE_CLEAR; /**< Read active high irq enable / Write ones to disable irq */
__IO uint32_t IRQ_EDGE; /**< Read irq configuration (edge or level) / Write ones to set irq to edge-sensitive */
__IO uint32_t IRQ_LEVEL; /**< Read irq configuration (edge or level) / Write ones to set irq to level-sensitive */
__IO uint32_t IRQ_POLARITY_SET; /**< Read irq polarity / Write ones to set irq to active high or rising edge */
__IO uint32_t IRQ_POLARITY_CLEAR; /**< Read irq polarity / Write ones to set interrupts to active low or falling edge */
__IO uint32_t ANYEDGE_SET; /**< Read irq anyedge configuration / Write ones to override irq edge selection & irq on any edge */
__IO uint32_t ANYEDGE_CLEAR; /**< Read irq anyedge configuration / Write ones to clear edge selection override */
__IO uint32_t IRQ_CLEAR; /**< Write ones to clear edge-sensitive irq */
__IO uint32_t CONTROL; /**< Controls loopback/normal mode selection */
__IO uint32_t R_STATE_W_SET; /**< Read synchronized input / Write ones to bits to set corresponding output IO's*/
__IO uint32_t R_IRQ_W_CLEAR; /**< Read state of irq / Write ones to bits to clear corresponging output IO's */
__IO uint32_t W_OUT; /**< Write ones to set direction to output */
__IO uint32_t W_IN; /**< Write ones to set direction to input */
__IO uint32_t IRQ_ENABLE_SET; /**< Read active high irq enable / Write ones to enable irq */
__IO uint32_t IRQ_ENABLE_CLEAR; /**< Read active high irq enable / Write ones to disable irq */
__IO uint32_t IRQ_EDGE; /**< Read irq configuration (edge or level) / Write ones to set irq to edge-sensitive */
__IO uint32_t IRQ_LEVEL; /**< Read irq configuration (edge or level) / Write ones to set irq to level-sensitive */
__IO uint32_t IRQ_POLARITY_SET; /**< Read irq polarity / Write ones to set irq to active high or rising edge */
__IO uint32_t IRQ_POLARITY_CLEAR; /**< Read irq polarity / Write ones to set interrupts to active low or falling edge */
__IO uint32_t ANYEDGE_SET; /**< Read irq anyedge configuration / Write ones to override irq edge selection & irq on any edge */
__IO uint32_t ANYEDGE_CLEAR; /**< Read irq anyedge configuration / Write ones to clear edge selection override */
__IO uint32_t IRQ_CLEAR; /**< Write ones to clear edge-sensitive irq */
__IO uint32_t CONTROL; /**< Controls loopback/normal mode selection */
} GpioReg_t, *GpioReg_pt;
#endif /* GPIO_MAP_H_ */

189
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c
View File

@ -31,151 +31,148 @@
/* See i2c_api.h for details */
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{
fI2cInit(obj, sda, scl);
fI2cInit(obj, sda, scl);
}
/* See i2c_api.h for details */
void i2c_frequency(i2c_t *obj, int hz)
{
fI2cFrequency(obj, hz);
fI2cFrequency(obj, hz);
}
/* See i2c_api.h for details */
int i2c_start(i2c_t *obj)
{
return(fI2cStart(obj));
return(fI2cStart(obj));
}
/* See i2c_api.h for details */
int i2c_stop(i2c_t *obj)
{
return(fI2cStop(obj));
return(fI2cStop(obj));
}
/* See i2c_api.h for details */
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{ /* TODO address parameter not usable */
int Count, status;
const char WriteData = (address | (~I2C_READ_WRITE_BIT_MASK)) & 0xFF;
{
/* TODO address parameter not usable */
int Count, status;
const char WriteData = (address | (~I2C_READ_WRITE_BIT_MASK)) & 0xFF;
/* Send start bit */
status = fI2cStart(obj);
if(status)
{/* Error sending start bit */
return status;
}
/* Send start bit */
status = fI2cStart(obj);
if(status) {
/* Error sending start bit */
return status;
}
/* Send address | read */
Count = fI2cWriteB(obj, &WriteData, 1);
if(Count != 1)
{/* Error sending address */
return Count;
}
/* Send address | read */
Count = fI2cWriteB(obj, &WriteData, 1);
if(Count != 1) {
/* Error sending address */
return Count;
}
/* Send command/s */
Count = fI2cReadB(obj, data, length);
if(Count != length)
{/* Error sending coomand/s */
return Count;
}
if(stop) /* Send stop bit if requested */
{
status = fI2cStop(obj);
if(status)
{/* Error sending stop bit */
return status;
}
}
return Count;
/* Send command/s */
Count = fI2cReadB(obj, data, length);
if(Count != length) {
/* Error sending coomand/s */
return Count;
}
if(stop) { /* Send stop bit if requested */
status = fI2cStop(obj);
if(status) {
/* Error sending stop bit */
return status;
}
}
return Count;
}
/* See i2c_api.h for details */
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
{
int Count, status;
const char WriteData = (address & I2C_READ_WRITE_BIT_MASK) & 0xFF;
int Count, status;
const char WriteData = (address & I2C_READ_WRITE_BIT_MASK) & 0xFF;
/* Send start bit */
status = fI2cStart(obj);
if(status)
{/* Error sending start bit */
return status;
}
/* Send start bit */
status = fI2cStart(obj);
if(status) {
/* Error sending start bit */
return status;
}
/* Send address | write */
Count = fI2cWriteB(obj, &WriteData, 1);
if(Count != 1)
{/* Error sending address */
return Count;
}
/* Send address | write */
Count = fI2cWriteB(obj, &WriteData, 1);
if(Count != 1) {
/* Error sending address */
return Count;
}
/* Sens command, [data] */
Count = fI2cWriteB(obj, data, length);
if(Count != length)
{/* Error sending address */
return Count;
}
/* Sens command, [data] */
Count = fI2cWriteB(obj, data, length);
if(Count != length) {
/* Error sending address */
return Count;
}
if(stop) /* If stop requested */
{/* Send stop bit */
status = fI2cStop(obj);
if(status)
{/* Error sending stop bit */
return status;
}
}
return Count;
if(stop) { /* If stop requested */
/* Send stop bit */
status = fI2cStop(obj);
if(status) {
/* Error sending stop bit */
return status;
}
}
return Count;
}
/* See i2c_api.h for details */
void i2c_reset(i2c_t *obj)
{
(void)fI2cStop(obj);
(void)fI2cStop(obj);
}
/* See i2c_api.h for details */
int i2c_byte_read(i2c_t *obj, int last) /* TODO return size can be uint8_t */
{
int Count;
char data;
Count = fI2cReadB(obj, &data, 1);
if(Count != 1)
{/* Error */
return Count;
}
if(last)
{/* ACK */
obj->membase->CMD_REG = I2C_CMD_WDAT0;
}
else
{/* No ACK */
obj->membase->CMD_REG = I2C_CMD_WDAT1;
}
return data;
int Count;
char data;
Count = fI2cReadB(obj, &data, 1);
if(Count != 1) {
/* Error */
return Count;
}
if(last) {
/* ACK */
obj->membase->CMD_REG = I2C_CMD_WDAT0;
} else {
/* No ACK */
obj->membase->CMD_REG = I2C_CMD_WDAT1;
}
return data;
}
/* See i2c_api.h for details */
int i2c_byte_write(i2c_t *obj, int data)
{
int Count;
Count = fI2cWriteB(obj, (const char *)&data, 1);
if(Count != 1)
{
return Count;
}
int Count;
Count = fI2cWriteB(obj, (const char *)&data, 1);
if(Count != 1) {
return Count;
}
obj->membase->CMD_REG = I2C_CMD_VRFY_ACK; /* Verify ACK */
obj->membase->CMD_REG = I2C_CMD_VRFY_ACK; /* Verify ACK */
while(obj->membase->STATUS.WORD & I2C_STATUS_CMD_FIFO_OFL_BIT); /* Wait till command overflow ends */
while(obj->membase->STATUS.WORD & I2C_STATUS_CMD_FIFO_OFL_BIT); /* Wait till command overflow ends */
if(obj->membase->STATUS.WORD & I2C_STATUS_BUS_ERR_BIT)
{/* Bus error means NAK received */
return 0;
}
else
{/* ACK received */
return 1;
}
if(obj->membase->STATUS.WORD & I2C_STATUS_BUS_ERR_BIT) {
/* Bus error means NAK received */
return 0;
} else {
/* ACK received */
return 1;
}
}
#endif /* DEVICE_I2C */

66
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c_ipc7208_map.h
View File

@ -43,39 +43,39 @@
/** I2C HW Structure Overlay */
typedef struct {
union {
struct {
__IO uint32_t CMD_FIFO_EMPTY :1; /**< 1 = Command FIFO is empty , 0 = Command FIFO is empty */
__IO uint32_t RD_FIFO_NOT_EMPTY :1; /**< 0 = Read data is not ready , 1 = Read data is ready */
__IO uint32_t I2C_BUS_ERR :1; /**< 0 = No buss error occurred , 1 = buss error */
__IO uint32_t RD_FIFO_UFL :1; /**< 0 = Read data FIFO is not underflowed , 1 = Read data FIFO is underflowed */
__IO uint32_t CMD_FIFO_OFL :1;/**< 0 = Command FIFO is not overflowed 1 = Command FIFO is overflowed */
__IO uint32_t CMD_FIFO_FULL :1; /**< 0 = Command FIFO not full , 1 = Command FIFO full */
__IO uint32_t PAD :2; /**< Reserved . Always reads back 0. */
} BITS;
__IO uint32_t WORD;
} STATUS;
__IO uint32_t RD_FIFO_REG;/**< Data from the I2C Slave to be read by the processor. */
__IO uint32_t CMD_REG; /**< I2C Command Programming interface */
union {
struct {
__IO uint32_t CMD_FIFO_INT :1; /**< Command FIFO empty interrupt : 0 = disable , 1 = enable */
__IO uint32_t RD_FIFO_INT :1; /**< Read Data FIFO Not Empty Interrupt : 0 = disable , 1 = enable */
__IO uint32_t I2C_ERR_INT :1; /**< I2C Error Interrupt : 0 = disable , 1 = enable */
// __IO uint32_t PAD :4; /**< Reserved. Writes have no effect; Read as 0x00. */
} BITS;
__IO uint32_t WORD;
} IER;
union {
struct {
__IO uint32_t CD_VAL :5; /**< I2C APB Clock Divider Value (low 5 bits). */
__IO uint32_t I2C_APB_CD_EN :1; /**< 0 = I2C clock divider disable 1 = I2C clock divider enable */
__IO uint32_t I2C_CLK_SRC :1; /**< I2C clock source : 0 = external clock , 1 = APB clock */
__IO uint32_t I2C_MODULE_EN :1; /**< 0 = I2C disable , 1 = I2C enable */
} BITS;
__IO uint32_t WORD;
} CR;
__IO uint32_t PRE_SCALE_REG; /* I2C APB Clock Divider Value (upper 8 bits). */
union {
struct {
__IO uint32_t CMD_FIFO_EMPTY :1; /**< 1 = Command FIFO is empty , 0 = Command FIFO is empty */
__IO uint32_t RD_FIFO_NOT_EMPTY :1; /**< 0 = Read data is not ready , 1 = Read data is ready */
__IO uint32_t I2C_BUS_ERR :1; /**< 0 = No buss error occurred , 1 = buss error */
__IO uint32_t RD_FIFO_UFL :1; /**< 0 = Read data FIFO is not underflowed , 1 = Read data FIFO is underflowed */
__IO uint32_t CMD_FIFO_OFL :1;/**< 0 = Command FIFO is not overflowed 1 = Command FIFO is overflowed */
__IO uint32_t CMD_FIFO_FULL :1; /**< 0 = Command FIFO not full , 1 = Command FIFO full */
__IO uint32_t PAD :2; /**< Reserved . Always reads back 0. */
} BITS;
__IO uint32_t WORD;
} STATUS;
__IO uint32_t RD_FIFO_REG;/**< Data from the I2C Slave to be read by the processor. */
__IO uint32_t CMD_REG; /**< I2C Command Programming interface */
union {
struct {
__IO uint32_t CMD_FIFO_INT :1; /**< Command FIFO empty interrupt : 0 = disable , 1 = enable */
__IO uint32_t RD_FIFO_INT :1; /**< Read Data FIFO Not Empty Interrupt : 0 = disable , 1 = enable */
__IO uint32_t I2C_ERR_INT :1; /**< I2C Error Interrupt : 0 = disable , 1 = enable */
// __IO uint32_t PAD :4; /**< Reserved. Writes have no effect; Read as 0x00. */
} BITS;
__IO uint32_t WORD;
} IER;
union {
struct {
__IO uint32_t CD_VAL :5; /**< I2C APB Clock Divider Value (low 5 bits). */
__IO uint32_t I2C_APB_CD_EN :1; /**< 0 = I2C clock divider disable 1 = I2C clock divider enable */
__IO uint32_t I2C_CLK_SRC :1; /**< I2C clock source : 0 = external clock , 1 = APB clock */
__IO uint32_t I2C_MODULE_EN :1; /**< 0 = I2C disable , 1 = I2C enable */
} BITS;
__IO uint32_t WORD;
} CR;
__IO uint32_t PRE_SCALE_REG; /* I2C APB Clock Divider Value (upper 8 bits). */
} I2cIpc7208Reg_t, *I2cIpc7208Reg_pt;
#endif /* I2C_IPC7208_MAP_H_ */

658
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h
View File

@ -42,358 +42,358 @@
/** macHw register map (phy, mac and agc parts) */
typedef struct {
__O uint32_t SEQUENCER; /**< 0x40014000 */
union {
struct {
__IO uint32_t MODE:2;
__IO uint32_t NOACK:1;
__IO uint32_t FT:1;
__IO uint32_t PAD0:3;
__IO uint32_t AUTO:1;
__IO uint32_t PAD1:1;
__IO uint32_t NOW:1;
__IO uint32_t PAD2:1;
__IO uint32_t PRM:1;
__IO uint32_t NFCS:1;
__IO uint32_t PAN:1;
__IO uint32_t RSTT:1;
__IO uint32_t RSTR:1;
__IO uint32_t ACK_ENABLE:1;
__IO uint32_t BEA_ENABLE:1;
__IO uint32_t CMD_ENABLE:1;
__IO uint32_t DATA_ENABLE:1;
__IO uint32_t RES_ENABLE:1;
} BITS;
__IO uint32_t WORD;
} SEQ_OPTIONS; /**< 0x40014004 */
union {
struct {
__IO uint32_t SRST:1;
__IO uint32_t ON:1;
__IO uint32_t CLKDIV:1;
} BITS;
__IO uint32_t WORD;
} CONTROL; /**< 0x40014008 */
__O uint32_t PAD0; /**< 0x4001400C */
union {
struct {
__I uint32_t CODE:4;
__I uint32_t PAD0:8;
__I uint32_t MSO:1;
__O uint32_t SEQUENCER; /**< 0x40014000 */
union {
struct {
__IO uint32_t MODE:2;
__IO uint32_t NOACK:1;
__IO uint32_t FT:1;
__IO uint32_t PAD0:3;
__IO uint32_t AUTO:1;
__IO uint32_t PAD1:1;
__IO uint32_t NOW:1;
__IO uint32_t PAD2:1;
__IO uint32_t PRM:1;
__IO uint32_t NFCS:1;
__IO uint32_t PAN:1;
__IO uint32_t RSTT:1;
__IO uint32_t RSTR:1;
__IO uint32_t ACK_ENABLE:1;
__IO uint32_t BEA_ENABLE:1;
__IO uint32_t CMD_ENABLE:1;
__IO uint32_t DATA_ENABLE:1;
__IO uint32_t RES_ENABLE:1;
} BITS;
__IO uint32_t WORD;
} SEQ_OPTIONS; /**< 0x40014004 */
union {
struct {
__IO uint32_t SRST:1;
__IO uint32_t ON:1;
__IO uint32_t CLKDIV:1;
} BITS;
__IO uint32_t WORD;
} CONTROL; /**< 0x40014008 */
__O uint32_t PAD0; /**< 0x4001400C */
union {
struct {
__I uint32_t CODE:4;
__I uint32_t PAD0:8;
__I uint32_t MSO:1;
__I uint32_t CB:1;
__I uint32_t PAD1:1;
__I uint32_t MST:1;
} BITS;
__I uint32_t WORD;
} STATUS; /**< 0x40014010 */
union {
struct {
__IO uint32_t TFP:1;
__IO uint32_t SDC:1;
__IO uint32_t IC:1;
__IO uint32_t SDB:1;
__IO uint32_t SSP:1;
__IO uint32_t TFPO:1;
} BITS;
__IO uint32_t WORD;
} OPTIONS; /**< 0x40014014 */
__IO uint32_t PANID; /**< 0x40014018 */
__IO uint32_t SHORT_ADDRESS; /**< 0x4001401C */
__IO uint32_t LONG_ADDRESS_HIGH; /**< 0x40014020 */
__IO uint32_t LONG_ADDRESS_LOW; /**< 0x40014024 */
union {
struct {
__IO uint32_t BIT_CLOCK_DIVIDER:8;
__IO uint32_t SYSTEM_CLOCK_DIVIDER:8;
__IO uint32_t CHIP_CLOCK_DIVIDER:8;
} BITS;
__IO uint32_t WORD;
} DIVIDER; /**< 0x40014028 */
union {
struct {
__IO uint32_t RECEIVE_WARMPUP:12;
__IO uint32_t PAD0:4;
__IO uint32_t TRANSMIT_WARMPUP:12;
} BITS;
__IO uint32_t WORD;
} RX_TX_WARMPUPS; /**< 0x4001402c */
union {
struct {
__O uint32_t EC:1;
__O uint32_t ES:1;
__O uint32_t DATA:1;
} BITS;
__I uint32_t WORD;
} STATUS; /**< 0x40014010 */
union {
struct {
__IO uint32_t TFP:1;
__IO uint32_t SDC:1;
__IO uint32_t IC:1;
__IO uint32_t SDB:1;
__IO uint32_t SSP:1;
__IO uint32_t TFPO:1;
} BITS;
__IO uint32_t WORD;
} OPTIONS; /**< 0x40014014 */
__IO uint32_t PANID; /**< 0x40014018 */
__IO uint32_t SHORT_ADDRESS; /**< 0x4001401C */
__IO uint32_t LONG_ADDRESS_HIGH; /**< 0x40014020 */
__IO uint32_t LONG_ADDRESS_LOW; /**< 0x40014024 */
union {
struct {
__IO uint32_t BIT_CLOCK_DIVIDER:8;
__IO uint32_t SYSTEM_CLOCK_DIVIDER:8;
__IO uint32_t CHIP_CLOCK_DIVIDER:8;
} BITS;
__IO uint32_t WORD;
} DIVIDER; /**< 0x40014028 */
union {
struct {
__IO uint32_t RECEIVE_WARMPUP:12;
__IO uint32_t PAD0:4;
__IO uint32_t TRANSMIT_WARMPUP:12;
} BITS;
__IO uint32_t WORD;
} RX_TX_WARMPUPS; /**< 0x4001402c */
union {
struct {
__O uint32_t EC:1;
__O uint32_t ES:1;
__O uint32_t DATA:1;
__O uint32_t FS:1;
__O uint32_t FP:1;
__O uint32_t FMD:1;
#ifdef REVD
__I uint32_t PC:1;
#endif /* REVD */
} BITS;
__O uint32_t WORD;
} CLEAR_IRQ; /**< 0x40014030 */
union {
struct {
__IO uint32_t EC:1;
__IO uint32_t ES:1;
__IO uint32_t DATA:1;
__I uint32_t PC:1;
#endif /* REVD */
} BITS;
__O uint32_t WORD;
} CLEAR_IRQ; /**< 0x40014030 */
union {
struct {
__IO uint32_t EC:1;
__IO uint32_t ES:1;
__IO uint32_t DATA:1;
__IO uint32_t FS:1;
__IO uint32_t FP:1;
__IO uint32_t FM:1;
#ifdef REVD
__I uint32_t PC:1;
#endif /* REVD */
} BITS;
__IO uint32_t WORD;
} MASK_IRQ; /**< 0x40014034 */
union {
struct {
__I uint32_t EC:1;
__I uint32_t ES:1;
__I uint32_t DATA:1;
__I uint32_t FS:1;
__I uint32_t FP:1;
__I uint32_t FM:1;
#ifdef REVD
__I uint32_t PC:1;
__I uint32_t PC:1;
#endif /* REVD */
} BITS;
__I uint32_t WORD;
} IRQ_STATUS; /**< 0x40014038 */
__O uint32_t PAD1; /**< 0x4001403C */
union {
struct {
__IO uint32_t START:1;
__IO uint32_t STOP:1;
} BITS;
__IO uint32_t WORD;
} TIMER_ENABLE; /**< 0x40014040 */
union {
struct {
__IO uint32_t START:1;
__IO uint32_t STOP:1;
} BITS;
__IO uint32_t WORD;
} TIMER_DISABLE; /**< 0x40014044 */
__IO uint32_t TIMER; /**< 0x40014048 */
__IO uint32_t START_TIME; /**< 0x4001404C */
__IO uint32_t STOP_TIME; /**< 0x40014050 */
union {
struct {
__I uint32_t START:1;
__I uint32_t STOP:1;
} BITS;
__I uint32_t WORD;
} TIMER_STATUS; /**< 0x40014054 */
__I uint32_t PROTOCOL_TIMER; /**< 0x40014058 */
__O uint32_t PAD4; /**< 0x4001405C */
__I uint32_t FINISH_TIME; /**< 0x40014060 */
union {
struct {
__IO uint32_t TX_SLOT_OFFSET:12;
__IO uint32_t PAD0:4;
__IO uint32_t RX_SLOT_OFFSET:12;
} BITS;
__IO uint32_t WORD;
} SLOT_OFFSET; /**< 0x40014064 */
__I uint32_t TIME_STAMP; /**< 0x40014068 */
} BITS;
__IO uint32_t WORD;
} MASK_IRQ; /**< 0x40014034 */
union {
struct {
__I uint32_t EC:1;
__I uint32_t ES:1;
__I uint32_t DATA:1;
__I uint32_t FS:1;
__I uint32_t FP:1;
__I uint32_t FM:1;
#ifdef REVD
__I uint32_t PC:1;
#endif /* REVD */
} BITS;
__I uint32_t WORD;
} IRQ_STATUS; /**< 0x40014038 */
__O uint32_t PAD1; /**< 0x4001403C */
union {
struct {
__IO uint32_t START:1;
__IO uint32_t STOP:1;
} BITS;
__IO uint32_t WORD;
} TIMER_ENABLE; /**< 0x40014040 */
union {
struct {
__IO uint32_t START:1;
__IO uint32_t STOP:1;
} BITS;
__IO uint32_t WORD;
} TIMER_DISABLE; /**< 0x40014044 */
__IO uint32_t TIMER; /**< 0x40014048 */
__IO uint32_t START_TIME; /**< 0x4001404C */
__IO uint32_t STOP_TIME; /**< 0x40014050 */
union {
struct {
__I uint32_t START:1;
__I uint32_t STOP:1;
} BITS;
__I uint32_t WORD;
} TIMER_STATUS; /**< 0x40014054 */
__I uint32_t PROTOCOL_TIMER; /**< 0x40014058 */
__O uint32_t PAD4; /**< 0x4001405C */
__I uint32_t FINISH_TIME; /**< 0x40014060 */
union {
struct {
__IO uint32_t TX_SLOT_OFFSET:12;
__IO uint32_t PAD0:4;
__IO uint32_t RX_SLOT_OFFSET:12;
} BITS;
__IO uint32_t WORD;
} SLOT_OFFSET; /**< 0x40014064 */
__I uint32_t TIME_STAMP; /**< 0x40014068 */
#ifdef REVB
__O uint32_t PAD5; /**< 0x4001406C */
__O uint32_t PAD5; /**< 0x4001406C */
#endif /* REVB */
union {
struct {
__IO uint32_t CRD_SHORT_ADDRESS:16;
__IO uint32_t PAD0:13;
__IO uint32_t ASSOC_PAN_COORD:1;
__IO uint32_t PAN_COORD_ADDR_L:1;
__IO uint32_t PAN_COORD_ADDR_S:1;
} BITS;
__IO uint32_t WORD;
union {
struct {
__IO uint32_t CRD_SHORT_ADDRESS:16;
__IO uint32_t PAD0:13;
__IO uint32_t ASSOC_PAN_COORD:1;
__IO uint32_t PAN_COORD_ADDR_L:1;
__IO uint32_t PAN_COORD_ADDR_S:1;
} BITS;
__IO uint32_t WORD;
#ifdef REVB
} CRD_SHORT_ADDR; /**< 0x40014070 */
__IO uint32_t CRD_LONG_ADDR_HI; /**< 0x40014074 */
__IO uint32_t CRD_LONG_ADDR_LO; /**< 0x40014078 */
} CRD_SHORT_ADDR; /**< 0x40014070 */
__IO uint32_t CRD_LONG_ADDR_HI; /**< 0x40014074 */
__IO uint32_t CRD_LONG_ADDR_LO; /**< 0x40014078 */
#endif /* REVB */
#ifdef REVD
} CRD_SHORT_ADDR; /**< 0x4001406C */
__IO uint32_t CRD_LONG_ADDR_HI; /**< 0x40014070 */
__IO uint32_t CRD_LONG_ADDR_LO; /**< 0x40014074 */
__O uint32_t PAD5; /**< 0x40014078 */
} CRD_SHORT_ADDR; /**< 0x4001406C */
__IO uint32_t CRD_LONG_ADDR_HI; /**< 0x40014070 */
__IO uint32_t CRD_LONG_ADDR_LO; /**< 0x40014074 */
__O uint32_t PAD5; /**< 0x40014078 */
#endif /* REVD */
__O uint32_t PAD9; /**< 0x4001407C */
__O uint32_t PAD10; /**< 0x40014080 */
__O uint32_t PAD11; /**< 0x40014084 */
__IO uint32_t RX_LENGTH; /**< 0x40014088 */
union {
struct {
__IO uint32_t TXLENGTH:7;
__O uint32_t PAD0:1;
__IO uint32_t TX_PRE_CHIPS:4;
} BITS;
__IO uint32_t WORD;
} TX_LENGTH; /**< 0x4001408C */
__IO uint32_t TX_SEQ_NUMBER; /**< 0x40014090 */
__IO uint32_t TX_ACK_DELAY; /**< 0x40014094 */
union {
struct {
__IO uint32_t RXACKDELAY:12;
__IO uint32_t PAD0:4;
__IO uint32_t RXAUTODELAY:12;
} BITS;
__IO uint32_t WORD;
} RX_ACK_DELAY; /**< 0x40014098 */
__IO uint32_t TX_FLUSH; /**< 0x4001409C */
union {
struct {
__IO uint32_t CCA_DELAY:12;
__IO uint32_t PAD0:4;
__IO uint32_t CCA_LENGTH:12;
} BITS;
__IO uint32_t WORD;
} CCA; /**< 0x400140A0 */
union {
struct {
__IO uint32_t RXACK_END:12;
__IO uint32_t PAD0:4;
__IO uint32_t RXSLOTTED_END:12;
} BITS;
__IO uint32_t WORD;
} ACK_STOP; /**< 0x400140A4 */
__IO uint32_t TXCCA; /**< 0x400140A8 */
__IO uint32_t ADDR_L_LOC; /**< 0x400140AC */
__IO uint32_t ADDR_S_LOC; /**< 0x400140B0 */
__IO uint32_t FRAME_MATCH_RESULT; /**< 0x400140B4 */
__IO uint32_t FRAME_MATCH_ADDR_L; /**< 0x400140B8 */
__IO uint32_t FRAME_MATCH_ADDR_S; /**< 0x400140BC */
union {
struct {
__IO uint32_t AA:1;
__IO uint32_t AFA:1;
__IO uint32_t PRE:1;
__IO uint32_t PAD0:25;
__IO uint32_t GAIN_START:4;
} BITS;
__IO uint32_t WORD;
} AGC_CONTROL; /**< 0x400140C0 */
union {
struct {
__IO uint32_t SETTLE_DELAY:8;
__IO uint32_t MEASURE_DELAY:8;
__IO uint32_t DIVIDER:8;
__IO uint32_t HIGH_THRESHOLD:4;
__IO uint32_t LOW_THRESHOLD:4;
} BITS;
__IO uint32_t WORD;
} AGC_SETTINGS; /**< 0x400140C4 */
union {
struct {
__IO uint32_t GC1:3;
__IO uint32_t GC2:3;
__IO uint32_t GC3:1;
__IO uint32_t PAD:1;
__IO uint32_t AGC_STATE:4;
} BITS;
__IO uint32_t WORD;
} AGC_STATUS; /**< 0x400140C8 */
union {
struct {
__IO uint32_t GAIN3:7;
__IO uint32_t PAD0:1;
__IO uint32_t GAIN2:7;
__IO uint32_t PAD1:1;
__IO uint32_t GAIN1:7;
__IO uint32_t PAD2:1;
__IO uint32_t GAIN0:7;
__IO uint32_t PAD3:1;
} BITS;
__IO uint32_t WORD;
} AGC_GAIN_TABLE0; /**< 0x400140CC */
union {
struct {
__IO uint32_t GAIN7:7;
__IO uint32_t PAD0:1;
__IO uint32_t GAIN6:7;
__IO uint32_t PAD1:1;
__IO uint32_t GAIN5:7;
__IO uint32_t PAD2:1;
__IO uint32_t GAIN4:7;
__IO uint32_t PAD3:1;
} BITS;
__IO uint32_t WORD;
} AGC_GAIN_TABLE1; /**< 0x400140D0 */
union {
struct {
__IO uint32_t GAIN11:7;
__IO uint32_t PAD0:1;
__IO uint32_t GAIN10:7;
__IO uint32_t PAD1:1;
__IO uint32_t GAIN9:7;
__IO uint32_t PAD2:1;
__IO uint32_t GAIN8:7;
__IO uint32_t PAD3:1;
} BITS;
__IO uint32_t WORD;
} AGC_GAIN_TABLE2; /**< 0x400140D4 */
union {
struct {
__IO uint32_t GAIN15:7;
__IO uint32_t PAD0:1;
__IO uint32_t GAIN14:7;
__IO uint32_t PAD1:1;
__IO uint32_t GAIN13:7;
__IO uint32_t PAD2:1;
__IO uint32_t GAIN12:7;
__IO uint32_t PAD3:1;
} BITS;
__IO uint32_t WORD;
} AGC_GAIN_TABLE3; /**< 0x400140D8 */
__O uint32_t PAD9; /**< 0x4001407C */
__O uint32_t PAD10; /**< 0x40014080 */
__O uint32_t PAD11; /**< 0x40014084 */
__IO uint32_t RX_LENGTH; /**< 0x40014088 */
union {
struct {
__IO uint32_t TXLENGTH:7;
__O uint32_t PAD0:1;
__IO uint32_t TX_PRE_CHIPS:4;
} BITS;
__IO uint32_t WORD;
} TX_LENGTH; /**< 0x4001408C */
__IO uint32_t TX_SEQ_NUMBER; /**< 0x40014090 */
__IO uint32_t TX_ACK_DELAY; /**< 0x40014094 */
union {
struct {
__IO uint32_t RXACKDELAY:12;
__IO uint32_t PAD0:4;
__IO uint32_t RXAUTODELAY:12;
} BITS;
__IO uint32_t WORD;
} RX_ACK_DELAY; /**< 0x40014098 */
__IO uint32_t TX_FLUSH; /**< 0x4001409C */
union {
struct {
__IO uint32_t CCA_DELAY:12;
__IO uint32_t PAD0:4;
__IO uint32_t CCA_LENGTH:12;
} BITS;
__IO uint32_t WORD;
} CCA; /**< 0x400140A0 */
union {
struct {
__IO uint32_t RXACK_END:12;
__IO uint32_t PAD0:4;
__IO uint32_t RXSLOTTED_END:12;
} BITS;
__IO uint32_t WORD;
} ACK_STOP; /**< 0x400140A4 */
__IO uint32_t TXCCA; /**< 0x400140A8 */
__IO uint32_t ADDR_L_LOC; /**< 0x400140AC */
__IO uint32_t ADDR_S_LOC; /**< 0x400140B0 */
__IO uint32_t FRAME_MATCH_RESULT; /**< 0x400140B4 */
__IO uint32_t FRAME_MATCH_ADDR_L; /**< 0x400140B8 */
__IO uint32_t FRAME_MATCH_ADDR_S; /**< 0x400140BC */
union {
struct {
__IO uint32_t AA:1;
__IO uint32_t AFA:1;
__IO uint32_t PRE:1;
__IO uint32_t PAD0:25;
__IO uint32_t GAIN_START:4;
} BITS;
__IO uint32_t WORD;
} AGC_CONTROL; /**< 0x400140C0 */
union {
struct {
__IO uint32_t SETTLE_DELAY:8;
__IO uint32_t MEASURE_DELAY:8;
__IO uint32_t DIVIDER:8;
__IO uint32_t HIGH_THRESHOLD:4;
__IO uint32_t LOW_THRESHOLD:4;
} BITS;
__IO uint32_t WORD;
} AGC_SETTINGS; /**< 0x400140C4 */
union {
struct {
__IO uint32_t GC1:3;
__IO uint32_t GC2:3;
__IO uint32_t GC3:1;
__IO uint32_t PAD:1;
__IO uint32_t AGC_STATE:4;
} BITS;
__IO uint32_t WORD;
} AGC_STATUS; /**< 0x400140C8 */
union {
struct {
__IO uint32_t GAIN3:7;
__IO uint32_t PAD0:1;
__IO uint32_t GAIN2:7;
__IO uint32_t PAD1:1;
__IO uint32_t GAIN1:7;
__IO uint32_t PAD2:1;
__IO uint32_t GAIN0:7;
__IO uint32_t PAD3:1;
} BITS;
__IO uint32_t WORD;
} AGC_GAIN_TABLE0; /**< 0x400140CC */
union {
struct {
__IO uint32_t GAIN7:7;
__IO uint32_t PAD0:1;
__IO uint32_t GAIN6:7;
__IO uint32_t PAD1:1;
__IO uint32_t GAIN5:7;
__IO uint32_t PAD2:1;
__IO uint32_t GAIN4:7;
__IO uint32_t PAD3:1;
} BITS;
__IO uint32_t WORD;
} AGC_GAIN_TABLE1; /**< 0x400140D0 */
union {
struct {
__IO uint32_t GAIN11:7;
__IO uint32_t PAD0:1;
__IO uint32_t GAIN10:7;
__IO uint32_t PAD1:1;
__IO uint32_t GAIN9:7;
__IO uint32_t PAD2:1;
__IO uint32_t GAIN8:7;
__IO uint32_t PAD3:1;
} BITS;
__IO uint32_t WORD;
} AGC_GAIN_TABLE2; /**< 0x400140D4 */
union {
struct {
__IO uint32_t GAIN15:7;
__IO uint32_t PAD0:1;
__IO uint32_t GAIN14:7;
__IO uint32_t PAD1:1;
__IO uint32_t GAIN13:7;
__IO uint32_t PAD2:1;
__IO uint32_t GAIN12:7;
__IO uint32_t PAD3:1;
} BITS;
__IO uint32_t WORD;
} AGC_GAIN_TABLE3; /**< 0x400140D8 */
} MacHwReg_t, *MacHwReg_pt;
/** macHw register map (demodulator part) */
typedef struct {
union {
struct {
__IO uint32_t DRC:1; /**< Reserved */
__IO uint32_t SWIQ:1; /**< Compensation for quadrature polarity. (set to 1 for RevB) */
__IO uint32_t LIF:1; /**< Allows the receiver to use a low-IF frequency of +1.23 MHz (0) or -1.23 MHz (1). */
__IO uint32_t PM:1; /**< Preamble Mode: Mode 0 (high sensitivity) – Preamble detection is based on observation of a regular pattern of correlation peaks over a span of 5 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If 4 out of 5 symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode improves preamble detection rate by tolerating one corrupt correlation result in the span of 5 symbols. However, the relaxed detection rule allows a higher rate of false preamble detection when no signal is present. Mode 1 (low false detection) – Preamble detection is based on a span of 4 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If all four symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode enforces a more strict detection rule and therefore offers lower rate of false preamble detection at the expense of higher missed detection. */
__IO uint32_t ASM:1; /**< This bit determines whether antenna selection is automatic (1) or manual (0). For applications that do not use antenna diversity, this bit should be set to 0. */
__IO uint32_t AS:1; /**< If automatic antenna selection mode is used, this bit determines the initial antenna selection. If manual antenna selection mode is used, this bit determines the antenna selection, 0 or 1. */
__IO uint32_t DTC:1; /**< Sets the decay time constant used in the RSSI calculation and Digital Gain Control functions. 0: Time constant set to 1 symbol period. This produces a slower response time but more stable RSSI values. Not recommended for use with antenna diversity. 1: Time constant set to 1/4th of a symbol period. This produces a faster response with slightly more variance in the RSSI calculation. Recommended for most cases. */
__IO uint32_t PAD1:9;
__IO uint32_t DFR:16; /**<Selectively enables individual frequency offsets used during preamble search. Each of the 15 bits in this field corresponds to one of 15 different frequency offsets. A bit value of 0 removes a specific frequency offset from the search, while a bit value of 1 includes the frequency offset in the search. */
} BITS;
__IO uint32_t WORD;
} DMD_CONTROL0; /**< 0x40014100 */
union {
struct {
__IO uint32_t DST:4; /**< This value specifies the SFD search period in symbols. After preamble detection, the demodulator begins symbol recovery and searches for the start-of-frame delimiter (SFD). If the SFD is not found within the number of symbols specified, the preamble detection flag is cleared and a new preamble search is initiated. The default value of 8 symbols should be sufficient for 802.15.4 compliant applications. Default 8 */
__IO uint32_t PAD0:4;
__IO uint32_t DPT:6; /**< The similarity criteria used for preamble detection includes a rule that all time index values must occupy a span equal to or less than this value. The default span of 0011 means that the correlation peaks must span a range of 3Ts, where Ts is the sample period = 0.25 µs. This value is recommended for typical multipath conditions. Very long-range applications may benefit from a higher value. Default 3 */
__IO uint32_t PAD1:2;
__IO uint32_t DPF:4; /**< The similarity criteria used for preamble detection includes a rule that all frequency index values must occupy a span equal to or less than this value. The default span of 0001 means that the difference between largest frequency index and smallest frequency index must be less than or equal to 1. Default 1 */
__IO uint32_t PAD2:4;
__IO uint32_t DCT:4; /**< In order for preamble detection to be declared, the correlation peaks must exceed a threshold. The threshold is computed dynamically and includes a programmable scale factor: 1 + bit[27]/2 + bit[26]/4 + bit[25]/8 + bit[24]/16 The default value of 1.5 is recommended for manual-antenna selection, while a value of 1.75 is recommended for automatic antenna selection. */
union {
struct {
__IO uint32_t DRC:1; /**< Reserved */
__IO uint32_t SWIQ:1; /**< Compensation for quadrature polarity. (set to 1 for RevB) */
__IO uint32_t LIF:1; /**< Allows the receiver to use a low-IF frequency of +1.23 MHz (0) or -1.23 MHz (1). */
__IO uint32_t PM:1; /**< Preamble Mode: Mode 0 (high sensitivity) – Preamble detection is based on observation of a regular pattern of correlation peaks over a span of 5 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If 4 out of 5 symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode improves preamble detection rate by tolerating one corrupt correlation result in the span of 5 symbols. However, the relaxed detection rule allows a higher rate of false preamble detection when no signal is present. Mode 1 (low false detection) – Preamble detection is based on a span of 4 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If all four symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode enforces a more strict detection rule and therefore offers lower rate of false preamble detection at the expense of higher missed detection. */
__IO uint32_t ASM:1; /**< This bit determines whether antenna selection is automatic (1) or manual (0). For applications that do not use antenna diversity, this bit should be set to 0. */
__IO uint32_t AS:1; /**< If automatic antenna selection mode is used, this bit determines the initial antenna selection. If manual antenna selection mode is used, this bit determines the antenna selection, 0 or 1. */
__IO uint32_t DTC:1; /**< Sets the decay time constant used in the RSSI calculation and Digital Gain Control functions. 0: Time constant set to 1 symbol period. This produces a slower response time but more stable RSSI values. Not recommended for use with antenna diversity. 1: Time constant set to 1/4th of a symbol period. This produces a faster response with slightly more variance in the RSSI calculation. Recommended for most cases. */
__IO uint32_t PAD1:9;
__IO uint32_t DFR:16; /**<Selectively enables individual frequency offsets used during preamble search. Each of the 15 bits in this field corresponds to one of 15 different frequency offsets. A bit value of 0 removes a specific frequency offset from the search, while a bit value of 1 includes the frequency offset in the search. */
} BITS;
__IO uint32_t WORD;
} DMD_CONTROL0; /**< 0x40014100 */
union {
struct {
__IO uint32_t DST:4; /**< This value specifies the SFD search period in symbols. After preamble detection, the demodulator begins symbol recovery and searches for the start-of-frame delimiter (SFD). If the SFD is not found within the number of symbols specified, the preamble detection flag is cleared and a new preamble search is initiated. The default value of 8 symbols should be sufficient for 802.15.4 compliant applications. Default 8 */
__IO uint32_t PAD0:4;
__IO uint32_t DPT:6; /**< The similarity criteria used for preamble detection includes a rule that all time index values must occupy a span equal to or less than this value. The default span of 0011 means that the correlation peaks must span a range of 3Ts, where Ts is the sample period = 0.25 µs. This value is recommended for typical multipath conditions. Very long-range applications may benefit from a higher value. Default 3 */
__IO uint32_t PAD1:2;
__IO uint32_t DPF:4; /**< The similarity criteria used for preamble detection includes a rule that all frequency index values must occupy a span equal to or less than this value. The default span of 0001 means that the difference between largest frequency index and smallest frequency index must be less than or equal to 1. Default 1 */
__IO uint32_t PAD2:4;
__IO uint32_t DCT:4; /**< In order for preamble detection to be declared, the correlation peaks must exceed a threshold. The threshold is computed dynamically and includes a programmable scale factor: 1 + bit[27]/2 + bit[26]/4 + bit[25]/8 + bit[24]/16 The default value of 1.5 is recommended for manual-antenna selection, while a value of 1.75 is recommended for automatic antenna selection. */
} BITS;
__IO uint32_t WORD;
} DMD_CONTROL1; /**< 0x40014104 */
union {
struct {
__IO uint32_t RSSI_THRESHOLD:8; /**< Threshold value used to determine clear channel assessment (CCA) result. The channel is declared busy if RSSI > threshold. Default 0xFF */
__IO uint32_t RSSI_OFFSET:6; /**< Calibration constant added to the RSSI calculation. The 6-bit field is treated as a signed value in two’s complement format with values from -32 to +31 dB. */
} BITS;
__IO uint32_t WORD;
} DMD_CONTROL2; /**< 0x40014108 */
union {
struct {
__I uint32_t RSSI_VALUE:8; /**< The value is captured at the end of packet reception or at the end of ED/CCA measurements and is interpreted in dBm as follows: 00000000 -> 0127dBm (or below) ... 01111111 -> 0dBm (or above) */
__I uint32_t FREQUENCY_OFFSET:4; /**< Frequency correction applied to the received packet. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
__I uint32_t ANT:1; /**< Antenna used for reception. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
__I uint32_t PAD0:3;
__I uint32_t RSSI_COMPONENT:4; /**< Magnitude of the baseband digital signal (units are dB relative to A/D saturation). The value is updated until AGC is frozen. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
} BITS;
__I uint32_t WORD;
} DMD_STATUS; /**< 0x4001410C */
} BITS;
__IO uint32_t WORD;
} DMD_CONTROL1; /**< 0x40014104 */
union {
struct {
__IO uint32_t RSSI_THRESHOLD:8; /**< Threshold value used to determine clear channel assessment (CCA) result. The channel is declared busy if RSSI > threshold. Default 0xFF */
__IO uint32_t RSSI_OFFSET:6; /**< Calibration constant added to the RSSI calculation. The 6-bit field is treated as a signed value in two’s complement format with values from -32 to +31 dB. */
} BITS;
__IO uint32_t WORD;
} DMD_CONTROL2; /**< 0x40014108 */
union {
struct {
__I uint32_t RSSI_VALUE:8; /**< The value is captured at the end of packet reception or at the end of ED/CCA measurements and is interpreted in dBm as follows: 00000000 -> 0127dBm (or below) ... 01111111 -> 0dBm (or above) */
__I uint32_t FREQUENCY_OFFSET:4; /**< Frequency correction applied to the received packet. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
__I uint32_t ANT:1; /**< Antenna used for reception. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
__I uint32_t PAD0:3;
__I uint32_t RSSI_COMPONENT:4; /**< Magnitude of the baseband digital signal (units are dB relative to A/D saturation). The value is updated until AGC is frozen. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
} BITS;
__I uint32_t WORD;
} DMD_STATUS; /**< 0x4001410C */
} DmdReg_t, *DmdReg_pt;
#endif /* MACHW_MAP_H_ */

2
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/macros.h
View File

@ -3,7 +3,7 @@
* @file macros.h
* @brief Implements some handy macros
* @internal
* @author : Industrial ASSP Application Team
* @author : ON Semiconductor.
* $Rev: 2076 $
* $Date: 2013-07-10 18:26:10 +0530 (Wed, 10 Jul 2013) $
*******************************************************************************

128
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h
View File

@ -103,9 +103,9 @@
#define TRIMREG_BASE ((uint32_t)0x1FA0)
#define TRIMREG ((TrimReg_t *)TRIMREG_BASE)
/** DMA HW Registers Offset */
/** DMA HW Registers Offset */
#define DMAREG_BASE ((uint32_t)0x24000400)
/** DMA HW Structure Overlay */
/** DMA HW Structure Overlay */
#define DMAREG ((DmaReg_pt)DMAREG_BASE)
/** MAC MATCH HW Registers Offset */
@ -113,29 +113,29 @@
/** MAC MATCH HW Structure Overlay */
#define MACMATCHREG ((volatile uint8_t *)MACMATCHREG_BASE)
/** MAC RX HW Registers Offset */
/** MAC RX HW Registers Offset */
#define MACRXREG_BASE ((uint32_t)0x24000080)
/** MAC RX HW Structure Overlay */
/** MAC RX HW Structure Overlay */
#define MACRXREG ((volatile uint8_t *)MACRXREG_BASE)
/** MAC TX HW Registers Offset */
/** MAC TX HW Registers Offset */
#define MACTXREG_BASE ((uint32_t)0x24000000)
/** MAC TX HW Structure Overlay */
/** MAC TX HW Structure Overlay */
#define MACTXREG ((volatile uint8_t *)MACTXREG_BASE)
/** TEST Interface for flash HW Registers Offset */
/** TEST Interface for flash HW Registers Offset */
#define TESTNVMREG_BASE ((uint32_t)0x4001F140)
/** TEST Interface for flash HW Structure Overlay */
/** TEST Interface for flash HW Structure Overlay */
#define TESTNVMREG ((TestNvmReg_pt)TESTNVMREG_BASE)
/** Test Interface for digital HW Registers Offset */
/** Test Interface for digital HW Registers Offset */
#define TESTDIGREG_BASE ((uint32_t)0x4001F100)
/** Test Interface for digital HW Structure Overlay */
/** Test Interface for digital HW Structure Overlay */
#define TESTDIGREG ((TestDigReg_pt)TESTDIGREG_BASE)
/** Test Interface HW Registers Offset */
/** Test Interface HW Registers Offset */
#define TESTREG_BASE ((uint32_t)0x4001F000)
/** Test Interface HW Structure Overlay */
/** Test Interface HW Structure Overlay */
#define TESTREG ((TestReg_pt)TESTREG_BASE)
/** Device option HW Registers Offset */
@ -143,136 +143,136 @@
/** MAC TX HW Structure Overlay */
#define DEVOPTREG ((volatile uint32_t *)DEVOPTREG_BASE)
/** PMU HW Registers Offset */
/** PMU HW Registers Offset */
#define PMUREG_BASE ((uint32_t)0x4001D000)
/** PMU HW Structure Overlay */
/** PMU HW Structure Overlay */
#define PMUREG ((PmuReg_pt)PMUREG_BASE)
/** PAD Control HW Registers Offset */
/** PAD Control HW Registers Offset */
#define PADREG_BASE ((uint32_t)0x4001C000)
/** PAD Control HW Structure Overlay */
/** PAD Control HW Structure Overlay */
#define PADREG ((PadReg_pt)PADREG_BASE)
/** Clock Control HW Registers Offset */
/** Clock Control HW Registers Offset */
#define CLOCKREG_BASE ((uint32_t)0x4001B000)
/** Clock Control HW Structure Overlay */
/** Clock Control HW Structure Overlay */
#define CLOCKREG ((ClockReg_pt)CLOCKREG_BASE)
/** Analogue Trim HW Registers Offset */
/** Analogue Trim HW Registers Offset */
#define RFANATRIMREG_BASE ((uint32_t)0x40019080)
/** Analogue Trim HW Structure Overlay */
/** Analogue Trim HW Structure Overlay */
#define RFANATRIMREG ((RfAnaTrimReg_pt)RFANATRIMREG_BASE)
/** Analogue RF HW Registers Offset */
/** Analogue RF HW Registers Offset */
#define RFANAREG_BASE ((uint32_t)0x40019000)
/** Analogue RF HW Structure Overlay */
/** Analogue RF HW Structure Overlay */
#define RFANAREG ((RfAnaReg_pt)RFANAREG_BASE)
/** Reset Cause HW Registers Offset */
/** Reset Cause HW Registers Offset */
#define RESETREG_BASE ((uint32_t)0x40018000)
/** Reset Cause HW Structure Overlay */
/** Reset Cause HW Structure Overlay */
#define RESETREG ((ResetReg_pt)RESETREG_BASE)
/** FLASH Control HW Registers Offset */
/** FLASH Control HW Registers Offset */
#define FLASHREG_BASE ((uint32_t)0x40017000)
/** FLASH Control HW Structure Overlay */
/** FLASH Control HW Structure Overlay */
#define FLASHREG ((FlashReg_pt)FLASHREG_BASE)
/** AES Encryption HW Registers Offset */
/** AES Encryption HW Registers Offset */
#define AESREG_BASE ((uint32_t)0x40016000)
/** AES Encryption HW Structure Overlay */
/** AES Encryption HW Structure Overlay */
#define AESREG ((AesReg_pt)AESREG_BASE)
/** SAR ADC HW Registers Offset */
/** SAR ADC HW Registers Offset */
#define ADCREG_BASE ((uint32_t)0x40015000)
/** SAR ADC HW Structure Overlay */
/** SAR ADC HW Structure Overlay */
#define ADCREG ((AdcReg_pt)ADCREG_BASE)
/** Demodulator HW Registers Offset */
/** Demodulator HW Registers Offset */
#define DMDREG_BASE ((uint32_t)0x40014100)
/** Demodulator HW Structure Overlay */
/** Demodulator HW Structure Overlay */
#define DMDREG ((DmdReg_pt)DMDREG_BASE)
/** MAC Control HW Registers Offset */
/** MAC Control HW Registers Offset */
#define MACHWREG_BASE ((uint32_t)0x40014000)
/** MAC Control HW Structure Overlay */
/** MAC Control HW Structure Overlay */
#define MACHWREG ((MacHwReg_pt)MACHWREG_BASE)
/** Random Generator HW Registers Offset */
/** Random Generator HW Registers Offset */
#define RANDREG_BASE ((uint32_t)0x40011000)
/** Random Generator HW Structure Overlay */
/** Random Generator HW Structure Overlay */
#define RANDREG ((RandReg_pt)RANDREG_BASE)
/** Cross Bar HW Registers Offset */
/** Cross Bar HW Registers Offset */
#define CROSSBREG_BASE ((uint32_t)0x40010000)
/** Cross Bar HW Structure Overlay */
/** Cross Bar HW Structure Overlay */
#define CROSSBREG ((CrossbReg_pt)CROSSBREG_BASE)
/** Real Time Clock HW Registers Offset */
/** Real Time Clock HW Registers Offset */
#define RTCREG_BASE ((uint32_t)0x4000F000)
/** Real Time Clock HW Structure Overlay */
/** Real Time Clock HW Structure Overlay */
#define RTCREG ((RtcReg_pt)RTCREG_BASE)
/** GPIO HW Registers Offset */
/** GPIO HW Registers Offset */
#define GPIOREG_BASE ((uint32_t)0x4000C000)
/** GPIO HW Structure Overlay */
/** GPIO HW Structure Overlay */
#define GPIOREG ((GpioReg_pt)GPIOREG_BASE)
/** PWM HW Registers Offset */
/** PWM HW Registers Offset */
#define PWMREG_BASE ((uint32_t)0x4000B000)
/** PWM HW Structure Overlay */
/** PWM HW Structure Overlay */
#define PWMREG ((PwmReg_pt)PWMREG_BASE)
/** Watchdog Timer HW Registers Offset */
/** Watchdog Timer HW Registers Offset */
#define WDTREG_BASE ((uint32_t)0x4000A000)
/** Watchdog Timer HW Structure Overlay */
/** Watchdog Timer HW Structure Overlay */
#define WDTREG ((WdtReg_pt)WDTREG_BASE)
/** UART 2 HW Registers Offset */
/** UART 2 HW Registers Offset */
#define UART2REG_BASE ((uint32_t)0x40008000)
/** UART 2 HW Structure Overlay */
/** UART 2 HW Structure Overlay */
#define UART2REG ((Uart16C550Reg_pt)UART2REG_BASE)
/** I2C HW Registers Offset */
/** I2C HW Registers Offset */
#define I2C1REG_BASE ((uint32_t)0x40007000)
/** I2C HW Structure Overlay */
/** I2C HW Structure Overlay */
#define I2C1REG ((I2cIpc7208Reg_pt)I2C1REG_BASE)
/** SPI HW Registers Offset */
/** SPI HW Registers Offset */
#define SPI1REG_BASE ((uint32_t)0x40006000)
/** SPI HW Structure Overlay */
/** SPI HW Structure Overlay */
#define SPI1REG ((SpiIpc7207Reg_pt)SPI1REG_BASE)
/** UART1 HW Registers Offset */
/** UART1 HW Registers Offset */
#define UART1REG_BASE ((uint32_t)0x40005000)
/** UART1 HW Structure Overlay */
/** UART1 HW Structure Overlay */
#define UART1REG ((Uart16C550Reg_pt)UART1REG_BASE)
#define UARTREG_BASES { UART1REG_BASE, UART2REG_BASE}
/** Timer 2 HW Registers Offset */
/** Timer 2 HW Registers Offset */
#define TIM2REG_BASE ((uint32_t)0x40002000)
/** Timer 2 HW Structure Overlay */
/** Timer 2 HW Structure Overlay */
#define TIM2REG ((TimerReg_pt)TIM2REG_BASE)
/** Timer 1 HW Registers Offset */
/** Timer 1 HW Registers Offset */
#define TIM1REG_BASE ((uint32_t)0x40001000)
/** Timer 1 HW Structure Overlay */
/** Timer 1 HW Structure Overlay */
#define TIM1REG ((TimerReg_pt)TIM1REG_BASE)
/** Timer 0 HW Registers Offset */
/** Timer 0 HW Registers Offset */
#define TIM0REG_BASE ((uint32_t)0x40000000)
/** Timer 0 HW Structure Overlay */
/** Timer 0 HW Structure Overlay */
#define TIM0REG ((TimerReg_pt)TIM0REG_BASE)
/** I2C2 HW Registers Offset */
/** I2C2 HW Registers Offset */
#define I2C2REG_BASE ((uint32_t)0x4000D000)
/** I2C2 HW Structure Overlay */
/** I2C2 HW Structure Overlay */
#define I2C2REG ((I2cIpc7208Reg_pt)I2C2REG_BASE)
/** SPI2 HW Registers Offset */
/** SPI2 HW Registers Offset */
#define SPI2REG_BASE ((uint32_t)0x40009000)
/** SPI2 HW Structure Overlay */
/** SPI2 HW Structure Overlay */
#define SPI2REG ((SpiIpc7207Reg_pt)SPI2REG_BASE)
#endif /*_MEMORY_MAP_H_*/

12
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/mib.h
View File

@ -119,12 +119,12 @@
/** A structure defining the format of the system revision parameter. */
typedef struct mib_systemRevision {
uint8_t hardwareRevision;
uint8_t patchLevel;
uint8_t bugFix;
uint8_t featureSet;
uint8_t generation;
uint8_t release;
uint8_t hardwareRevision;
uint8_t patchLevel;
uint8_t bugFix;
uint8_t featureSet;
uint8_t generation;
uint8_t release;
} mib_systemRevision_t, *mib_systemRevision_pt;
/** The system revision. */

179
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c
View File

@ -3,7 +3,7 @@
* @file ncs36510_init.c
* @brief Initialization of Orion SoC
* @internal
* @author Radhika R, ON Semiconductors
* @author ON Semiconductor
* $Rev:
* $Date: $
******************************************************************************
@ -37,137 +37,139 @@ void fPmuInit(void);
* This function copies trim codes from specific flash location
* where they are stored to proper hw registers.
*/
boolean fTrim() {
boolean fTrim()
{
/**- Check if trim values are present */
/**- If Trim data is present. Only trim if valid trim values are present. */
/**- Copy trims in registers */
if (TRIMREG->REVISION_CODE != 0xFFFFFFFF) {
/**- Check if trim values are present */
/**- If Trim data is present. Only trim if valid trim values are present. */
/**- Copy trims in registers */
if (TRIMREG->REVISION_CODE != 0xFFFFFFFF) {
/**- board specific clock trims may only be done when present, writing all 1's is not good */
if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) {
CLOCKREG->TRIM_32K_EXT = TRIMREG->TRIM_32K_EXT;
}
/**- board specific clock trims may only be done when present, writing all 1's is not good */
if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) {
CLOCKREG->TRIM_32K_EXT = TRIMREG->TRIM_32K_EXT;
}
if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) {
CLOCKREG->TRIM_32M_EXT = TRIMREG->TRIM_32M_EXT;
}
if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) {
CLOCKREG->TRIM_32M_EXT = TRIMREG->TRIM_32M_EXT;
}
MACHWREG->TX_LENGTH.BITS.TX_PRE_CHIPS = TRIMREG->TX_PRE_CHIPS;
MACHWREG->TX_LENGTH.BITS.TX_PRE_CHIPS = TRIMREG->TX_PRE_CHIPS;
RFANATRIMREG->TX_CHAIN_TRIM = TRIMREG->TX_CHAIN_TRIM;
RFANATRIMREG->PLL_VCO_TAP_LOCATION = TRIMREG->PLL_VCO_TAP_LOCATION;
RFANATRIMREG->PLL_TRIM.WORD = TRIMREG->PLL_TRIM;
RFANATRIMREG->TX_CHAIN_TRIM = TRIMREG->TX_CHAIN_TRIM;
RFANATRIMREG->PLL_VCO_TAP_LOCATION = TRIMREG->PLL_VCO_TAP_LOCATION;
RFANATRIMREG->PLL_TRIM.WORD = TRIMREG->PLL_TRIM;
/**- board specific RSSI trims may only be done when present, writing all 1's is not good */
if ((TRIMREG->RSSI_OFFSET & 0xFFFF0000) != 0xFFFF0000) {
DMDREG->DMD_CONTROL2.BITS.RSSI_OFFSET = TRIMREG->RSSI_OFFSET;
}
/**- board specific RSSI trims may only be done when present, writing all 1's is not good */
if ((TRIMREG->RSSI_OFFSET & 0xFFFF0000) != 0xFFFF0000) {
DMDREG->DMD_CONTROL2.BITS.RSSI_OFFSET = TRIMREG->RSSI_OFFSET;
}
RFANATRIMREG->RX_CHAIN_TRIM = TRIMREG->RX_CHAIN_TRIM;
RFANATRIMREG->PMU_TRIM = TRIMREG->PMU_TRIM;
RANDREG->WR_SEED_RD_RAND = TRIMREG->WR_SEED_RD_RAND;
RFANATRIMREG->RX_CHAIN_TRIM = TRIMREG->RX_CHAIN_TRIM;
RFANATRIMREG->PMU_TRIM = TRIMREG->PMU_TRIM;
RANDREG->WR_SEED_RD_RAND = TRIMREG->WR_SEED_RD_RAND;
/** REVD boards are trimmed (in flash) with rx vco trims specific for high side injection,
* */
RFANATRIMREG->RX_VCO_TRIM_LUT1 = TRIMREG->RX_VCO_LUT1.WORD;;
RFANATRIMREG->RX_VCO_TRIM_LUT2 = TRIMREG->RX_VCO_LUT2.WORD;;
/** REVD boards are trimmed (in flash) with rx vco trims specific for high side injection,
* */
RFANATRIMREG->RX_VCO_TRIM_LUT1 = TRIMREG->RX_VCO_LUT1.WORD;;
RFANATRIMREG->RX_VCO_TRIM_LUT2 = TRIMREG->RX_VCO_LUT2.WORD;;
RFANATRIMREG->TX_VCO_TRIM_LUT1 = TRIMREG->TX_VCO_LUT1.WORD;;
RFANATRIMREG->TX_VCO_TRIM_LUT2 = TRIMREG->TX_VCO_LUT2.WORD;;
RFANATRIMREG->TX_VCO_TRIM_LUT1 = TRIMREG->TX_VCO_LUT1.WORD;;
RFANATRIMREG->TX_VCO_TRIM_LUT2 = TRIMREG->TX_VCO_LUT2.WORD;;
return True;
} else {
/**- If no trim values are present, update the global status variable. */
return False;
}
return True;
} else {
/**- If no trim values are present, update the global status variable. */
return False;
}
}
/* See clock.h for documentation. */
void fClockInit() {
void fClockInit()
{
/** Enable external 32MHz oscillator */
CLOCKREG->CCR.BITS.OSC_SEL = 1;
/** Enable external 32MHz oscillator */
CLOCKREG->CCR.BITS.OSC_SEL = 1;
/** - Wait external 32MHz oscillator to be ready */
while(CLOCKREG->CSR.BITS.XTAL32M != 1){} /* If you get stuck here, something is wrong with board or trim values */
/** - Wait external 32MHz oscillator to be ready */
while(CLOCKREG->CSR.BITS.XTAL32M != 1) {} /* If you get stuck here, something is wrong with board or trim values */
/** Internal 32MHz calibration \n *//** - Enable internal 32MHz clock */
PMUREG->CONTROL.BITS.INT32M = 0;
/** Internal 32MHz calibration \n *//** - Enable internal 32MHz clock */
PMUREG->CONTROL.BITS.INT32M = 0;
/** - Wait 5 uSec for clock to stabilize */
volatile uint8_t Timer;
for(Timer = 0;Timer < 10;Timer++);
/** - Wait 5 uSec for clock to stabilize */
volatile uint8_t Timer;
for(Timer = 0; Timer < 10; Timer++);
/** - Enable calibration */
CLOCKREG->CCR.BITS.CAL32M = True;
/** - Enable calibration */
CLOCKREG->CCR.BITS.CAL32M = True;
/** - Wait calibration to be completed */
while(CLOCKREG->CSR.BITS.CAL32MDONE == False); /* If you stuck here, issue with internal 32M calibration */
/** - Wait calibration to be completed */
while(CLOCKREG->CSR.BITS.CAL32MDONE == False); /* If you stuck here, issue with internal 32M calibration */
/** - Check calibration status */
while(CLOCKREG->CSR.BITS.CAL32MFAIL == True); /* If you stuck here, issue with internal 32M calibration */
/** - Check calibration status */
while(CLOCKREG->CSR.BITS.CAL32MFAIL == True); /* If you stuck here, issue with internal 32M calibration */
/** - Power down internal 32MHz osc */
PMUREG->CONTROL.BITS.INT32M = 1;
/** - Power down internal 32MHz osc */
PMUREG->CONTROL.BITS.INT32M = 1;
/** Internal 32KHz calibration \n */ /** - Enable internal 32KHz clock */
PMUREG->CONTROL.BITS.INT32K = 0;
/** Internal 32KHz calibration \n */ /** - Enable internal 32KHz clock */
PMUREG->CONTROL.BITS.INT32K = 0;
/** - Wait 5 uSec for clock to stabilize */
for(Timer = 0;Timer < 10;Timer++);
/** - Wait 5 uSec for clock to stabilize */
for(Timer = 0; Timer < 10; Timer++);
/** - Enable calibration */
CLOCKREG->CCR.BITS.CAL32K = True;
/** - Enable calibration */
CLOCKREG->CCR.BITS.CAL32K = True;
/** - Wait calibration to be completed */
while(CLOCKREG->CSR.BITS.DONE32K == False); /* If you stuck here, issue with internal 32K calibration */
/** - Wait calibration to be completed */
while(CLOCKREG->CSR.BITS.DONE32K == False); /* If you stuck here, issue with internal 32K calibration */
/** - Check calibration status */
while(CLOCKREG->CSR.BITS.CAL32K == True); /* If you stuck here, issue with internal 32M calibration */
/** - Check calibration status */
while(CLOCKREG->CSR.BITS.CAL32K == True); /* If you stuck here, issue with internal 32M calibration */
/** - Power down external 32KHz osc */
PMUREG->CONTROL.BITS.EXT32K = 1;
/** - Power down external 32KHz osc */
PMUREG->CONTROL.BITS.EXT32K = 1;
/** Disable all peripheral clocks by default */
CLOCKREG->PDIS.WORD = 0xFFFFFFFF;
/** Disable all peripheral clocks by default */
CLOCKREG->PDIS.WORD = 0xFFFFFFFF;
/** Set core frequency */
CLOCKREG->FDIV = CPU_CLOCK_DIV - 1;
/** Set core frequency */
CLOCKREG->FDIV = CPU_CLOCK_DIV - 1;
}
/* Initializes PMU module */
void fPmuInit()
{
/** Enable the clock for PMU peripheral device */
CLOCK_ENABLE(CLOCK_PMU);
/** Enable the clock for PMU peripheral device */
CLOCK_ENABLE(CLOCK_PMU);
/** Unset wakeup on pending (only enabled irq can wakeup) */
SCB->SCR &= ~SCB_SCR_SEVONPEND_Msk;
/** Unset wakeup on pending (only enabled irq can wakeup) */
SCB->SCR &= ~SCB_SCR_SEVONPEND_Msk;
/** Unset auto sleep when returning from wakeup irq */
SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
/** Unset auto sleep when returning from wakeup irq */
SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
/** Set regulator timings */
PMUREG->FVDD_TSETTLE = 160;
PMUREG->FVDD_TSTARTUP = 400;
/** Set regulator timings */
PMUREG->FVDD_TSETTLE = 160;
PMUREG->FVDD_TSTARTUP = 400;
/** Keep SRAMA & SRAMB powered in coma mode */
PMUREG->CONTROL.BITS.SRAMA = False;
PMUREG->CONTROL.BITS.SRAMB = False;
/** Keep SRAMA & SRAMB powered in coma mode */
PMUREG->CONTROL.BITS.SRAMA = False;
PMUREG->CONTROL.BITS.SRAMB = False;
PMUREG->CONTROL.BITS.N1V1 = True; /* Enable ACTIVE mode switching regulator */
PMUREG->CONTROL.BITS.C1V1 = True; /* Enable COMA mode switching regulator */
PMUREG->CONTROL.BITS.N1V1 = True; /* Enable ACTIVE mode switching regulator */
PMUREG->CONTROL.BITS.C1V1 = True; /* Enable COMA mode switching regulator */
/** Disable the clock for PMU peripheral device, all settings are done */
CLOCK_DISABLE(CLOCK_PMU);
/** Disable the clock for PMU peripheral device, all settings are done */
CLOCK_DISABLE(CLOCK_PMU);
}
/* See clock.h for documentation. */
uint32_t fClockGetPeriphClockfrequency()
{
return (CPU_CLOCK_ROOT_HZ / CPU_CLOCK_DIV);
return (CPU_CLOCK_ROOT_HZ / CPU_CLOCK_DIV);
}
@ -177,7 +179,8 @@ uint32_t fClockGetPeriphClockfrequency()
* This function initializes hardware at application start up prior
* to other initializations or OS operations.
*/
static void fHwInit(void) {
static void fHwInit(void)
{
/* Trim register settings */
fTrim();
@ -257,7 +260,7 @@ void fNcs36510Init(void)
/**- Clear all pending SV and systick */
SCB->ICSR = (uint32_t)0x0A000000;
SCB->VTOR = (uint32_t) (&__Vectors);
SCB->VTOR = (uint32_t) (&__Vectors);
/**- Initialize hardware */
fHwInit();

4
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.h
View File

@ -3,8 +3,8 @@
* @file ncs36510_init.h
* @brief Initialization of Orion SoC
* @internal
* @author Radhika R, ON Semiconductors
* $Rev:
* @author ON Semiconductor.
* $Rev:
* $Date: $
******************************************************************************
* @copyright (c) 2012 ON Semiconductor. All rights reserved.

220
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c
View File

@ -58,173 +58,165 @@
/* See i2c.h for details */
void fI2cInit(i2c_t *obj,PinName sda,PinName scl)
{
uint32_t clockDivisor;
/* determine the I2C to use */
uint32_t clockDivisor;
/* determine the I2C to use */
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
obj->membase = (I2cIpc7208Reg_pt)pinmap_merge(i2c_sda, i2c_scl);
MBED_ASSERT((int)obj->membase != NC);
/* By default disbale interrupts */
obj->membase->IER.WORD = False;
/* By default disbale interrupts */
obj->membase->IER.WORD = False;
/* enable interrupt associated with the device */
if(obj->membase == I2C1REG)
{
CLOCK_ENABLE(CLOCK_I2C); /* enable i2c peripheral */
NVIC_ClearPendingIRQ(I2C_IRQn);
NVIC_EnableIRQ(I2C_IRQn);
}
else
{
CLOCK_ENABLE(CLOCK_I2C2); /* enable i2c peripheral */
NVIC_ClearPendingIRQ(I2C2_IRQn);
NVIC_EnableIRQ(I2C2_IRQn);
}
/* enable interrupt associated with the device */
if(obj->membase == I2C1REG) {
CLOCK_ENABLE(CLOCK_I2C); /* enable i2c peripheral */
NVIC_ClearPendingIRQ(I2C_IRQn);
NVIC_EnableIRQ(I2C_IRQn);
} else {
CLOCK_ENABLE(CLOCK_I2C2); /* enable i2c peripheral */
NVIC_ClearPendingIRQ(I2C2_IRQn);
NVIC_EnableIRQ(I2C2_IRQn);
}
/*select I2C clock source */
obj->membase->CR.BITS.I2C_CLK_SRC = True;
/*select I2C clock source */
obj->membase->CR.BITS.I2C_CLK_SRC = True;
/* enable I2C clock divider */
obj->membase->CR.BITS.I2C_APB_CD_EN = True;
/* enable I2C clock divider */
obj->membase->CR.BITS.I2C_APB_CD_EN = True;
/* set default baud rate at 100k */
clockDivisor = ((fClockGetPeriphClockfrequency() / 100000) >> 2) - 2;
obj->membase->CR.BITS.CD_VAL = (clockDivisor & I2C_CLOCKDIVEDER_VAL_MASK);
obj->membase->PRE_SCALE_REG = (clockDivisor & I2C_APB_CLK_DIVIDER_VAL_MASK) >> 5; /**< Zero pre-scale value not allowed */
clockDivisor = ((fClockGetPeriphClockfrequency() / 100000) >> 2) - 2;
obj->membase->CR.BITS.CD_VAL = (clockDivisor & I2C_CLOCKDIVEDER_VAL_MASK);
obj->membase->PRE_SCALE_REG = (clockDivisor & I2C_APB_CLK_DIVIDER_VAL_MASK) >> 5; /**< Zero pre-scale value not allowed */
/* Cross bar setting */
pinmap_pinout(sda, PinMap_I2C_SDA);
pinmap_pinout(scl, PinMap_I2C_SCL);
/*Enable open drain & pull up for sda & scl pin */
pin_mode(sda, OpenDrainPullUp);
pin_mode(scl, OpenDrainPullUp);
/*Enable open drain & pull up for sda & scl pin */
pin_mode(sda, OpenDrainPullUp);
pin_mode(scl, OpenDrainPullUp);
/* PAD drive strength */
PadReg_t *padRegSda = (PadReg_t*)(PADREG_BASE + (sda * PAD_REG_ADRS_BYTE_SIZE));
PadReg_t *padRegScl = (PadReg_t*)(PADREG_BASE + (scl * PAD_REG_ADRS_BYTE_SIZE));
/* PAD drive strength */
PadReg_t *padRegSda = (PadReg_t*)(PADREG_BASE + (sda * PAD_REG_ADRS_BYTE_SIZE));
PadReg_t *padRegScl = (PadReg_t*)(PADREG_BASE + (scl * PAD_REG_ADRS_BYTE_SIZE));
CLOCK_ENABLE(CLOCK_PAD);
padRegSda->PADIO0.BITS.POWER = 1; /* sda: Drive strength */
padRegScl->PADIO0.BITS.POWER = 1; /* scl: Drive strength */
CLOCK_DISABLE(CLOCK_PAD);
CLOCK_ENABLE(CLOCK_PAD);
padRegSda->PADIO0.BITS.POWER = 1; /* sda: Drive strength */
padRegScl->PADIO0.BITS.POWER = 1; /* scl: Drive strength */
CLOCK_DISABLE(CLOCK_PAD);
CLOCK_ENABLE(CLOCK_GPIO);
GPIOREG->W_OUT |= ((True << sda) | (True << scl));
CLOCK_DISABLE(CLOCK_GPIO);
CLOCK_ENABLE(CLOCK_GPIO);
GPIOREG->W_OUT |= ((True << sda) | (True << scl));
CLOCK_DISABLE(CLOCK_GPIO);
/* Enable i2c module */
obj->membase->CR.BITS.I2C_MODULE_EN = True;
/* Enable i2c module */
obj->membase->CR.BITS.I2C_MODULE_EN = True;
}
/* See i2c.h for details */
void fI2cFrequency(i2c_t *obj, uint32_t hz)
{
/* Set user baud rate */
uint32_t clockDivisor;
clockDivisor = ((fClockGetPeriphClockfrequency() / hz) >> 2) - 2;
obj->membase->CR.BITS.CD_VAL = (clockDivisor & I2C_CLOCKDIVEDER_VAL_MASK);
obj->membase->PRE_SCALE_REG = (clockDivisor & I2C_APB_CLK_DIVIDER_VAL_MASK) >> 5; /**< Zero pre-scale value not allowed */
/* Set user baud rate */
uint32_t clockDivisor;
clockDivisor = ((fClockGetPeriphClockfrequency() / hz) >> 2) - 2;
obj->membase->CR.BITS.CD_VAL = (clockDivisor & I2C_CLOCKDIVEDER_VAL_MASK);
obj->membase->PRE_SCALE_REG = (clockDivisor & I2C_APB_CLK_DIVIDER_VAL_MASK) >> 5; /**< Zero pre-scale value not allowed */
}
/* See i2c.h for details */
int32_t fI2cStart(i2c_t *obj)
{
/* Send start bit */
obj->membase->CMD_REG = I2C_CMD_START;
return I2C_API_STATUS_SUCCESS;
/* Send start bit */
obj->membase->CMD_REG = I2C_CMD_START;
return I2C_API_STATUS_SUCCESS;
}
/* See i2c.h for details */
int32_t fI2cStop(i2c_t *obj)
{
/* Send stop bit */
obj->membase->CMD_REG = I2C_CMD_STOP;
if (obj->membase->STATUS.WORD & (I2C_STATUS_CMD_FIFO_FULL_BIT |
I2C_STATUS_CMD_FIFO_OFL_BIT |
I2C_STATUS_BUS_ERR_BIT))
{/* I2c error occured */
return I2C_ERROR_BUS_BUSY;
}
return I2C_API_STATUS_SUCCESS;
/* Send stop bit */
obj->membase->CMD_REG = I2C_CMD_STOP;
if (obj->membase->STATUS.WORD & (I2C_STATUS_CMD_FIFO_FULL_BIT |
I2C_STATUS_CMD_FIFO_OFL_BIT |
I2C_STATUS_BUS_ERR_BIT)) {
/* I2c error occured */
return I2C_ERROR_BUS_BUSY;
}
return I2C_API_STATUS_SUCCESS;
}
/* See i2c.h for details */
int32_t fI2cReadB(i2c_t *d, char *buf, int len)
{
int32_t read = 0;
int32_t read = 0;
while (read < len)
{
/* Send read command */
d->membase->CMD_REG = I2C_CMD_RDAT8;
while(!RD_DATA_READY)
{
if (I2C_BUS_ERR_CHECK)
{/* Bus error occured */
return I2C_ERROR_BUS_BUSY;
}
}
buf[read++] = d->membase->RD_FIFO_REG; /**< Reading 'read FIFO register' will clear status register */
while (read < len) {
/* Send read command */
d->membase->CMD_REG = I2C_CMD_RDAT8;
while(!RD_DATA_READY) {
if (I2C_BUS_ERR_CHECK) {
/* Bus error occured */
return I2C_ERROR_BUS_BUSY;
}
}
buf[read++] = d->membase->RD_FIFO_REG; /**< Reading 'read FIFO register' will clear status register */
if(!(read>=len)) /* No ACK will be generated for the last read, upper level I2C protocol should generate */
{
d->membase->CMD_REG=I2C_CMD_WDAT0; /* TODO based on requirement generate ACK or NACK Based on the requirement. */
}
if(!(read>=len)) { /* No ACK will be generated for the last read, upper level I2C protocol should generate */
d->membase->CMD_REG=I2C_CMD_WDAT0; /* TODO based on requirement generate ACK or NACK Based on the requirement. */
}
/* check for FIFO underflow */
if(I2C_UFL_CHECK)
{
return I2C_ERROR_NO_SLAVE; /* TODO No error available for this in i2c_api.h */
}
if(I2C_BUS_ERR_CHECK)
{/* Bus error */
return I2C_ERROR_BUS_BUSY;
}
}
/* check for FIFO underflow */
if(I2C_UFL_CHECK) {
return I2C_ERROR_NO_SLAVE; /* TODO No error available for this in i2c_api.h */
}
if(I2C_BUS_ERR_CHECK) {
/* Bus error */
return I2C_ERROR_BUS_BUSY;
}
}
return read;
return read;
}
/* See i2c.h for details */
int32_t fI2cWriteB(i2c_t *d, const char *buf, int len)
{
int32_t write = 0;
int32_t write = 0;
while (write < len)
{ /* Send write command */
d->membase->CMD_REG = I2C_CMD_WDAT8;
if(buf[write] == I2C_CMD_RDAT8)
{/* SW work around to counter FSM issue. If the only command in the CMD FIFO is the WDAT8 command (data of 0x13)
then as the command is read out (i.e. the FIFO goes empty), the WDAT8 command will be misinterpreted as a
RDAT8 command by the data FSM; resulting in an I2C bus error (NACK instead of an ACK). */
/* Send 0x13 bit wise */
d->membase->CMD_REG = I2C_CMD_WDAT0;
d->membase->CMD_REG = I2C_CMD_WDAT0;
d->membase->CMD_REG = I2C_CMD_WDAT0;
d->membase->CMD_REG = I2C_CMD_WDAT1;
while (write < len) {
/* Send write command */
d->membase->CMD_REG = I2C_CMD_WDAT8;
if(buf[write] == I2C_CMD_RDAT8) {
/* SW work around to counter FSM issue. If the only command in the CMD FIFO is the WDAT8 command (data of 0x13)
then as the command is read out (i.e. the FIFO goes empty), the WDAT8 command will be misinterpreted as a
RDAT8 command by the data FSM; resulting in an I2C bus error (NACK instead of an ACK). */
/* Send 0x13 bit wise */
d->membase->CMD_REG = I2C_CMD_WDAT0;
d->membase->CMD_REG = I2C_CMD_WDAT0;
d->membase->CMD_REG = I2C_CMD_WDAT0;
d->membase->CMD_REG = I2C_CMD_WDAT1;
d->membase->CMD_REG = I2C_CMD_WDAT0;
d->membase->CMD_REG = I2C_CMD_WDAT0;
d->membase->CMD_REG = I2C_CMD_WDAT1;
d->membase->CMD_REG = I2C_CMD_WDAT1;
}
else
{ /* Send data */
d->membase->CMD_REG = buf[write++];
}
d->membase->CMD_REG = I2C_CMD_VRFY_ACK; /* TODO Verify ACK based on requirement, Do we need? */
d->membase->CMD_REG = I2C_CMD_WDAT0;
d->membase->CMD_REG = I2C_CMD_WDAT0;
d->membase->CMD_REG = I2C_CMD_WDAT1;
d->membase->CMD_REG = I2C_CMD_WDAT1;
} else {
/* Send data */
d->membase->CMD_REG = buf[write++];
}
d->membase->CMD_REG = I2C_CMD_VRFY_ACK; /* TODO Verify ACK based on requirement, Do we need? */
while(FIFO_OFL_CHECK); /* Wait till command overflow ends */
while(FIFO_OFL_CHECK); /* Wait till command overflow ends */
if (I2C_BUS_ERR_CHECK)
{/* Bus error */
return I2C_ERROR_BUS_BUSY;
}
}
if (I2C_BUS_ERR_CHECK) {
/* Bus error */
return I2C_ERROR_BUS_BUSY;
}
}
return write;
return write;
}
#endif /* DEVICE_I2C */

57
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_lp_ticker_api.c
View File

@ -38,68 +38,66 @@
/* Initialize the RTC for low power ticker */
void lp_ticker_init()
{
fRtcInit();
fRtcInit();
}
/* Return the current RTC counter value in us */
uint32_t lp_ticker_read()
{
return (uint32_t)(fRtcRead() & 0xFFFFFFFF); /* TODO Truncating 64 bit value to 32 bit */
return (uint32_t)(fRtcRead() & 0xFFFFFFFF); /* TODO Truncating 64 bit value to 32 bit */
}
/* Set interrupt for specified time */
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
/* The RTC Match register needs to be Set to the RTC alarm value */
fRtcSetInterrupt(timestamp);
/* The RTC Match register needs to be Set to the RTC alarm value */
fRtcSetInterrupt(timestamp);
}
/*Return the time that gets cut off when you return just a 32 bit us resolution number */
uint32_t lp_ticker_get_overflows_counter(void)
{
/* To check; do we need an counter in software in RTC to find overflows */
uint64_t now = fRtcRead();
uint32_t overflow = (now & 0xFFFFFFFF00000000) >> 32;
return overflow;
/* To check; do we need an counter in software in RTC to find overflows */
uint64_t now = fRtcRead();
uint32_t overflow = (now & 0xFFFFFFFF00000000) >> 32;
return overflow;
}
/* Return the RTC Match counter contents */
uint32_t lp_ticker_get_compare_match()
{
/* read the alarms and convert to us */
uint16_t sub_second_alarm = RTCREG->SUB_SECOND_ALARM;
uint32_t second_alarm = RTCREG->SECOND_ALARM;
uint64_t alarm_us = (uint64_t)((((float)sub_second_alarm / RTC_CLOCK_HZ) * RTC_SEC_TO_US) +
(second_alarm * RTC_SEC_TO_US));
/* TODO truncating to 32 bits */
return (uint32_t)(alarm_us & 0xFFFFFFFF);
/* read the alarms and convert to us */
uint16_t sub_second_alarm = RTCREG->SUB_SECOND_ALARM;
uint32_t second_alarm = RTCREG->SECOND_ALARM;
uint64_t alarm_us = (uint64_t)((((float)sub_second_alarm / RTC_CLOCK_HZ) * RTC_SEC_TO_US) +
(second_alarm * RTC_SEC_TO_US));
/* TODO truncating to 32 bits */
return (uint32_t)(alarm_us & 0xFFFFFFFF);
}
/* sleep until alarm */
void lp_ticker_sleep_until(uint32_t now, uint32_t time)
{
/* Set the interrupt */
lp_ticker_set_interrupt(time);
/* Set the interrupt */
lp_ticker_set_interrupt(time);
/* Go to sleep */
sleep_t obj;
obj.SleepType = SLEEP_TYPE_NONE;
obj.timeToSleep = time - now;
/* Go to sleep */
sleep_t obj;
obj.SleepType = SLEEP_TYPE_NONE;
obj.timeToSleep = time - now;
mbed_enter_sleep(&obj);
/* TBD: This is dummy exit for now; once the entered sleep it should be
removed and sleep exit should happen through interrupt */
mbed_exit_sleep(&obj);
mbed_enter_sleep(&obj);
/* TBD: This is dummy exit for now; once the entered sleep it should be
removed and sleep exit should happen through interrupt */
mbed_exit_sleep(&obj);
}
#ifdef TOOLCHAIN_ARM
/* Dummy functions added for the compilation of ARMCC compiler toolchain */
/** Disable low power ticker interrupt
*
*/
void lp_ticker_disable_interrupt(void)
{
//TODO : dummy function to get compilation running
/* TODO : This is an empty implementation for now */
}
/** Clear the low power ticker interrupt
@ -107,8 +105,7 @@ void lp_ticker_disable_interrupt(void)
*/
void lp_ticker_clear_interrupt(void)
{
//TODO : dummy function to get compilation running
/* TODO : This is an empty implementation for now */
}
#endif /* TOOLCHAIN_ARM */
#endif /* DEVICE_LOWPOWERTIMER */

143
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_spi.c
View File

@ -46,86 +46,85 @@
*/
void fSpiInit(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
uint32_t clockDivisor;
uint32_t clockDivisor;
/* determine the SPI to use */
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SSEL);
/* determine the SPI to use */
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SSEL);
SPIName spi_data_1 = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_data_2 = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
SPIName spi_data_1 = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_data_2 = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->membase = (SpiIpc7207Reg_pt)pinmap_merge(spi_data_1, spi_data_2);
MBED_ASSERT((int)obj->membase != NC);
obj->membase = (SpiIpc7207Reg_pt)pinmap_merge(spi_data_1, spi_data_2);
MBED_ASSERT((int)obj->membase != NC);
/* Check device to be activated */
if(obj->membase == SPI1REG)
{/* SPI 1 selected */
CLOCK_ENABLE(CLOCK_SPI); /* Enable clock */
}
else
{/* SPI 2 selected */
CLOCK_ENABLE(CLOCK_SPI2); /* Enable clock */
}
/* Check device to be activated */
if(obj->membase == SPI1REG) {
/* SPI 1 selected */
CLOCK_ENABLE(CLOCK_SPI); /* Enable clock */
} else {
/* SPI 2 selected */
CLOCK_ENABLE(CLOCK_SPI2); /* Enable clock */
}
/* Cross bar setting: Map GPIOs to SPI */
/* Cross bar setting: Map GPIOs to SPI */
pinmap_pinout(sclk, PinMap_SPI_SCLK);
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(miso, PinMap_SPI_SSEL);/* TODO Need to implement as per morpheus */
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(miso, PinMap_SPI_SSEL);/* TODO Need to implement as per morpheus */
/* TODO Do we need GPIO direction settings done here or at init phase? */
/* GPIO config */
CLOCK_ENABLE(CLOCK_GPIO);
GPIOREG->W_OUT |= ((0x1 << sclk) | (0x1 << mosi)); /* Set pins as output */
GPIOREG->W_IN |= (0x1 << miso); /* Set pin as input */
/* TODO Do we need GPIO direction settings done here or at init phase? */
/* GPIO config */
CLOCK_ENABLE(CLOCK_GPIO);
GPIOREG->W_OUT |= ((0x1 << sclk) | (0x1 << mosi)); /* Set pins as output */
GPIOREG->W_IN |= (0x1 << miso); /* Set pin as input */
pin_mode(sclk, PushPullNoPull);
pin_mode(mosi, PushPullPullUp);
pin_mode(miso, OpenDrainPullUp);
pin_mode(sclk, PushPullNoPull);
pin_mode(mosi, PushPullPullUp);
pin_mode(miso, OpenDrainPullUp);
/* PAD drive strength */
PadReg_t *padRegOffset = (PadReg_t*)(PADREG_BASE + (sclk * PAD_REG_ADRS_BYTE_SIZE));
CLOCK_ENABLE(CLOCK_PAD);
padRegOffset->PADIO0.BITS.POWER = 1; /* sclk: Drive strength */
padRegOffset->PADIO1.BITS.POWER = 1; /* mosi: Drive strength */
padRegOffset->PADIO2.BITS.POWER = 1; /* miso: Drive strength */
CLOCK_DISABLE(CLOCK_PAD);
/* PAD drive strength */
PadReg_t *padRegOffset = (PadReg_t*)(PADREG_BASE + (sclk * PAD_REG_ADRS_BYTE_SIZE));
CLOCK_ENABLE(CLOCK_PAD);
padRegOffset->PADIO0.BITS.POWER = 1; /* sclk: Drive strength */
padRegOffset->PADIO1.BITS.POWER = 1; /* mosi: Drive strength */
padRegOffset->PADIO2.BITS.POWER = 1; /* miso: Drive strength */
CLOCK_DISABLE(CLOCK_PAD);
/* disable/reset the spi port */
obj->membase->CONTROL.BITS.ENABLE = False;
/* disable/reset the spi port */
obj->membase->CONTROL.BITS.ENABLE = False;
/* set default baud rate to 1MHz */
clockDivisor = ((fClockGetPeriphClockfrequency() / 1000000) >> 1) - 1;
obj->membase->FDIV = clockDivisor;
/* set default baud rate to 1MHz */
clockDivisor = ((fClockGetPeriphClockfrequency() / 1000000) >> 1) - 1;
obj->membase->FDIV = clockDivisor;
/* set tx/rx fifos watermarks */ /* TODO water mark level 1 byte ?*/
obj->membase->TX_WATERMARK = 1;
obj->membase->RX_WATERMARK = 1;
/* set tx/rx fifos watermarks */ /* TODO water mark level 1 byte ?*/
obj->membase->TX_WATERMARK = 1;
obj->membase->RX_WATERMARK = 1;
/* DIsable and clear IRQs */ /* TODO sync api, do not need irq ?*/
obj->membase->IRQ_ENABLE = False;
obj->membase->IRQ_CLEAR = 0xFF; /* Clear all */
/* DIsable and clear IRQs */ /* TODO sync api, do not need irq ?*/
obj->membase->IRQ_ENABLE = False;
obj->membase->IRQ_CLEAR = 0xFF; /* Clear all */
/* configure slave select */
obj->membase->SLAVE_SELECT.BITS.SS_ENABLE = False;
obj->membase->SLAVE_SELECT.BITS.SS_BURST = True;
obj->membase->SLAVE_SELECT_POLARITY = False;
/* configure slave select */
obj->membase->SLAVE_SELECT.BITS.SS_ENABLE = False;
obj->membase->SLAVE_SELECT.BITS.SS_BURST = True;
obj->membase->SLAVE_SELECT_POLARITY = False;
/* set control register parameters */
obj->membase->CONTROL.BITS.WORD_WIDTH = False; /* 8 bits */
obj->membase->CONTROL.BITS.MODE = 1; /* master */
obj->membase->CONTROL.BITS.CPOL = 0; /* CPOL = 0, Idle low */
obj->membase->CONTROL.BITS.CPHA = 0; /* CPHA = 0, First transmit occurs before first edge of SCLK*/
obj->membase->CONTROL.BITS.ENDIAN = 0; /* Little endian */
obj->membase->CONTROL.BITS.SAMPLING_EDGE = False; /* Sample incoming data on opposite edge of SCLK from when outgoing data is driven */
/* set control register parameters */
obj->membase->CONTROL.BITS.WORD_WIDTH = False; /* 8 bits */
obj->membase->CONTROL.BITS.MODE = 1; /* master */
obj->membase->CONTROL.BITS.CPOL = 0; /* CPOL = 0, Idle low */
obj->membase->CONTROL.BITS.CPHA = 0; /* CPHA = 0, First transmit occurs before first edge of SCLK*/
obj->membase->CONTROL.BITS.ENDIAN = 0; /* Little endian */
obj->membase->CONTROL.BITS.SAMPLING_EDGE = False; /* Sample incoming data on opposite edge of SCLK from when outgoing data is driven */
/* SPI1REG->SLAVE_SELECT.BITS.SS_ENABLE = 0; Slave select TODO do we need? */
/* SPI1REG->SLAVE_SELECT.BITS.SS_ENABLE = 0; Slave select TODO do we need? */
/* enable the spi port */
obj->membase->CONTROL.BITS.ENABLE = True;
/* enable the spi port */
obj->membase->CONTROL.BITS.ENABLE = True;
}
/** Close a spi device.
@ -136,11 +135,11 @@ void fSpiInit(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
*/
void fSpiClose(spi_t *obj)
{
/* disable the spi port */
obj->membase->CONTROL.BITS.ENABLE = False;
/* disable the spi port */
obj->membase->CONTROL.BITS.ENABLE = False;
/* disable interruption associated with spi */
NVIC_DisableIRQ(obj->irq);
/* disable interruption associated with spi */
NVIC_DisableIRQ(obj->irq);
}
/**
@ -154,14 +153,14 @@ void fSpiClose(spi_t *obj)
*/
int fSpiWriteB(spi_t *obj, uint32_t const buf)
{
int byte;
int byte;
while((obj->membase->STATUS.BITS.TX_FULL == 1) && (obj->membase->STATUS.BITS.RX_FULL == 1)); /* Wait till Tx/Rx status is full */
obj->membase->TX_DATA = buf;
while((obj->membase->STATUS.BITS.TX_FULL == 1) && (obj->membase->STATUS.BITS.RX_FULL == 1)); /* Wait till Tx/Rx status is full */
obj->membase->TX_DATA = buf;
while (obj->membase->STATUS.BITS.RX_EMPTY == 1); /* Wait till Receive status is empty */
byte = obj->membase->RX_DATA;
return byte;
while (obj->membase->STATUS.BITS.RX_EMPTY == 1); /* Wait till Receive status is empty */
byte = obj->membase->RX_DATA;
return byte;
}
#endif /* DEVICE_SPI */

162
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c
View File

@ -36,9 +36,9 @@ static volatile uint32_t msb_counter = 0;
void us_ticker_init(void)
{
if (!us_ticker_inited) {
us_timer_init();
}
if (!us_ticker_inited) {
us_timer_init();
}
}
/*******************************************************************************
@ -55,75 +55,73 @@ void us_ticker_init(void)
/* Timer 0 for free running time */
extern void us_timer_isr(void)
{
TIM0REG->CLEAR = 0;
msb_counter++;
TIM0REG->CLEAR = 0;
msb_counter++;
}
/* Initializing TIMER 0(TImer) and TIMER 1(Ticker) */
static void us_timer_init(void)
{
/* Enable the timer0 periphery clock */
CLOCK_ENABLE(CLOCK_TIMER0);
/* Enable the timer0 periphery clock */
CLOCK_ENABLE(CLOCK_TIMER1);
/* Enable the timer0 periphery clock */
CLOCK_ENABLE(CLOCK_TIMER0);
/* Enable the timer0 periphery clock */
CLOCK_ENABLE(CLOCK_TIMER1);
/* Timer init */
/* load timer value */
TIM0REG->LOAD = 0xFFFF;
/* Timer init */
/* load timer value */
TIM0REG->LOAD = 0xFFFF;
/* set timer prescale 32 (1 us), mode & enable */
TIM0REG->CONTROL.WORD = ((CLK_DIVIDER_32 << TIMER_PRESCALE_BIT_POS) |
(TIME_MODE_PERIODIC << TIMER_MODE_BIT_POS) |
(TIMER_ENABLE_BIT << TIMER_ENABLE_BIT_POS));
/* set timer prescale 32 (1 us), mode & enable */
TIM0REG->CONTROL.WORD = ((CLK_DIVIDER_32 << TIMER_PRESCALE_BIT_POS) |
(TIME_MODE_PERIODIC << TIMER_MODE_BIT_POS) |
(TIMER_ENABLE_BIT << TIMER_ENABLE_BIT_POS));
/* Ticker init */
/* load timer value */
TIM1REG->LOAD = 0xFFFF;
/* Ticker init */
/* load timer value */
TIM1REG->LOAD = 0xFFFF;
/* set timer prescale 32 (1 us), mode & enable */
TIM1REG->CONTROL.WORD = ((CLK_DIVIDER_32 << TIMER_PRESCALE_BIT_POS) |
(TIME_MODE_PERIODIC << TIMER_MODE_BIT_POS));
/* set timer prescale 32 (1 us), mode & enable */
TIM1REG->CONTROL.WORD = ((CLK_DIVIDER_32 << TIMER_PRESCALE_BIT_POS) |
(TIME_MODE_PERIODIC << TIMER_MODE_BIT_POS));
/* Register & enable interrupt associated with the timer */
NVIC_SetVector(Tim0_IRQn,(uint32_t)us_timer_isr);
NVIC_SetVector(Tim1_IRQn,(uint32_t)us_ticker_isr);
/* Register & enable interrupt associated with the timer */
NVIC_SetVector(Tim0_IRQn,(uint32_t)us_timer_isr);
NVIC_SetVector(Tim1_IRQn,(uint32_t)us_ticker_isr);
/* Clear pending irqs */
NVIC_ClearPendingIRQ(Tim0_IRQn);
NVIC_ClearPendingIRQ(Tim1_IRQn);
/* Clear pending irqs */
NVIC_ClearPendingIRQ(Tim0_IRQn);
NVIC_ClearPendingIRQ(Tim1_IRQn);
/* Setup NVIC for timer */
NVIC_EnableIRQ(Tim0_IRQn);
NVIC_EnableIRQ(Tim1_IRQn);
/* Setup NVIC for timer */
NVIC_EnableIRQ(Tim0_IRQn);
NVIC_EnableIRQ(Tim1_IRQn);
us_ticker_inited = 1;
us_ticker_inited = 1;
}
/* Reads 32 bit timer's current value (16 bit s/w timer | 16 bit h/w timer) */
uint32_t us_ticker_read()
{
uint32_t retval, tim0cval;
uint32_t retval, tim0cval;
if (!us_ticker_inited)
{
us_timer_init();
}
if (!us_ticker_inited) {
us_timer_init();
}
/* Get the current tick from the hw and sw timers */
tim0cval = TIM0REG->VALUE; /* read current time */
retval = (0xFFFF - tim0cval); /* subtract down count */
/* Get the current tick from the hw and sw timers */
tim0cval = TIM0REG->VALUE; /* read current time */
retval = (0xFFFF - tim0cval); /* subtract down count */
NVIC_DisableIRQ(Tim0_IRQn);
if (TIM0REG->CONTROL.BITS.INT)
{
TIM0REG->CLEAR = 0;
msb_counter++;
tim0cval = TIM0REG->VALUE; /* read current time again after interrupt */
retval = (0xFFFF - tim0cval);
}
retval |= msb_counter << 16; /* add software bits */
NVIC_EnableIRQ(Tim0_IRQn);
return retval;
NVIC_DisableIRQ(Tim0_IRQn);
if (TIM0REG->CONTROL.BITS.INT) {
TIM0REG->CLEAR = 0;
msb_counter++;
tim0cval = TIM0REG->VALUE; /* read current time again after interrupt */
retval = (0xFFFF - tim0cval);
}
retval |= msb_counter << 16; /* add software bits */
NVIC_EnableIRQ(Tim0_IRQn);
return retval;
}
/*******************************************************************************
@ -138,67 +136,63 @@ uint32_t us_ticker_read()
/* TImer 1 disbale interrupt */
void us_ticker_disable_interrupt(void)
{
/* Disable the TIMER1 interrupt */
TIM1REG->CONTROL.BITS.ENABLE = 0x0;
/* Disable the TIMER1 interrupt */
TIM1REG->CONTROL.BITS.ENABLE = 0x0;
}
/* TImer 1 clear interrupt */
void us_ticker_clear_interrupt(void)
{
/* Clear the Ticker (TIMER1) interrupt */
TIM1REG->CLEAR = 0;
/* Clear the Ticker (TIMER1) interrupt */
TIM1REG->CLEAR = 0;
}
/* Setting TImer 1 (ticker) */
inline static void ticker_set(uint32_t count)
{
/* Disable TIMER1, load the new value, and re-enable */
TIM1REG->CONTROL.BITS.ENABLE = 0;
TIM1REG->LOAD = count;
TIM1REG->CONTROL.BITS.ENABLE = 1;
/* Disable TIMER1, load the new value, and re-enable */
TIM1REG->CONTROL.BITS.ENABLE = 0;
TIM1REG->LOAD = count;
TIM1REG->CONTROL.BITS.ENABLE = 1;
}
/* TImer 1 - ticker ISR */
extern void us_ticker_isr(void)
{
/* Clear IRQ flag */
TIM1REG->CLEAR = 0;
/* Clear IRQ flag */
TIM1REG->CLEAR = 0;
/* If this is a longer timer it will take multiple full hw counter cycles */
if (us_ticker_int_counter > 0)
{
ticker_set(0xFFFF);
us_ticker_int_counter--;
}
else
{
TIM1REG->CONTROL.BITS.ENABLE = False;
us_ticker_irq_handler();
}
/* If this is a longer timer it will take multiple full hw counter cycles */
if (us_ticker_int_counter > 0) {
ticker_set(0xFFFF);
us_ticker_int_counter--;
} else {
TIM1REG->CONTROL.BITS.ENABLE = False;
us_ticker_irq_handler();
}
}
/* Set timer 1 ticker interrupt */
void us_ticker_set_interrupt(timestamp_t timestamp)
{
int32_t delta = (uint32_t)timestamp - us_ticker_read();
int32_t delta = (uint32_t)timestamp - us_ticker_read();
if (delta <= 0)
{
/* This event was in the past */
//us_ticker_irq_handler();
if (delta <= 0) {
/* This event was in the past */
//us_ticker_irq_handler();
// This event was in the past.
// Set the interrupt as pending, but don't process it here.
// This prevents a recurive loop under heavy load
// which can lead to a stack overflow.
NVIC_SetPendingIRQ(Tim1_IRQn);
return;
}
return;
}
/* Calculate how much delta falls outside the 16-bit counter range. */
/* You will have to perform a full timer overflow for each bit above */
/* that range. */
us_ticker_int_counter = (uint32_t)(delta >> 16);
/* Calculate how much delta falls outside the 16-bit counter range. */
/* You will have to perform a full timer overflow for each bit above */
/* that range. */
us_ticker_int_counter = (uint32_t)(delta >> 16);
ticker_set(delta);
ticker_set(delta);
}

119
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/objects.h
View File

@ -44,28 +44,27 @@ typedef enum {
} FlowControl_1;
struct serial_s {
Uart16C550Reg_pt UARTREG;
FlowControl_1 FlowCtrl;
IRQn_Type IRQType;
Uart16C550Reg_pt UARTREG;
FlowControl_1 FlowCtrl;
IRQn_Type IRQType;
int index;
};
typedef struct _gpio_t
{
typedef struct _gpio_t {
GpioReg_pt GPIOMEMBASE;
PinName gpioPin;
uint32_t gpioMask;
}gpio_t;
} gpio_t;
/* TODO: This is currently a dummy structure; implementation will be done along
* with the sleep API implementation
*/
typedef struct sleep_s {
uint32_t timeToSleep; /* 0: Use sleep type variable; Noz-zero: Selects sleep type based on duration using table 1. sleep below */
uint8_t SleepType; /* 0: Sleep; 1: DeepSleep; 2: Coma */
}sleep_t;
uint32_t timeToSleep; /* 0: Use sleep type variable; Noz-zero: Selects sleep type based on duration using table 1. sleep below */
uint8_t SleepType; /* 0: Sleep; 1: DeepSleep; 2: Coma */
} sleep_t;
/* Table 1. Sleep
___________________________________________________________________________________
@ -86,61 +85,60 @@ struct gpio_irq_s {
typedef struct {
/* options to configure the ADC */
uint8_t interruptConfig; /**< 1= interrupt Enable 0=Interrupt Disable */
uint8_t PrescaleVal; /**< Prescaler: Sets the converter clock frequency. Fclk = 32 MHz/(prescaler + 1) where prescaler is the value of this register segment. The minimum tested value is 07 (4 MHz clock) */
uint8_t measurementType; /**< 1= Absolute 0= Differential */
uint8_t mode; /**< 1= Continuous Conversion 0= Single Shot */
uint8_t referenceCh; /**< Selects 1 to 8 channels for reference channel */
uint8_t convCh; /**< Selects 1 or 8 channels to do a conversion on.*/
uint8_t inputScale; /**< Sets the input scale, 000 ? 1.0, 001 ? 0.6923, 010 ? 0.5294, 011 ? 0.4286, 100 ? 0.3600, 101 ? 0.3103, 110 ? 0.2728, 111 ? 0.2432 */
uint8_t samplingTime; /**< Sample Time. Sets the measure time in units of PCLKperiod * (Prescale + 1).*/
uint8_t WarmUpTime; /**< The number of converter clock cycles that the state machine dwells in the warm or warm_meas state */
uint16_t samplingRate; /**< Sets the sample rate in units of PCLKperiod * (Prescale + 1). */
/* options to configure the ADC */
uint8_t interruptConfig; /**< 1= interrupt Enable 0=Interrupt Disable */
uint8_t PrescaleVal; /**< Prescaler: Sets the converter clock frequency. Fclk = 32 MHz/(prescaler + 1) where prescaler is the value of this register segment. The minimum tested value is 07 (4 MHz clock) */
uint8_t measurementType; /**< 1= Absolute 0= Differential */
uint8_t mode; /**< 1= Continuous Conversion 0= Single Shot */
uint8_t referenceCh; /**< Selects 1 to 8 channels for reference channel */
uint8_t convCh; /**< Selects 1 or 8 channels to do a conversion on.*/
uint8_t inputScale; /**< Sets the input scale, 000 ? 1.0, 001 ? 0.6923, 010 ? 0.5294, 011 ? 0.4286, 100 ? 0.3600, 101 ? 0.3103, 110 ? 0.2728, 111 ? 0.2432 */
uint8_t samplingTime; /**< Sample Time. Sets the measure time in units of PCLKperiod * (Prescale + 1).*/
uint8_t WarmUpTime; /**< The number of converter clock cycles that the state machine dwells in the warm or warm_meas state */
uint16_t samplingRate; /**< Sets the sample rate in units of PCLKperiod * (Prescale + 1). */
} analog_config_s;
struct analogin_s {
analog_config_s *adcConf;
AdcReg_pt adcReg;
PinName pin;
uint8_t pinFlag;
analog_config_s *adcConf;
AdcReg_pt adcReg;
PinName pin;
uint8_t pinFlag;
};
struct pwmout_s {
PwmReg_pt pwmReg;
PwmReg_pt pwmReg;
};
struct port_s {
GpioReg_pt GPIOMEMBASE;
PortName port;
uint32_t mask;
GpioReg_pt GPIOMEMBASE;
PortName port;
uint32_t mask;
};
typedef enum {
littleEndian = 0,
bigEndian
littleEndian = 0,
bigEndian
} spi_ipc7207_endian_t, *spi_ipc7207_endian_pt;
/** Type for the clock polarity. */
typedef enum {
activeLow = 0,
activeHigh
activeLow = 0,
activeHigh
} spi_clockPolarity_t, *spi_clockPolarity_pt;
/** Type for the clock phase. */
typedef enum {
risingEdge = 0,
fallingEdge
risingEdge = 0,
fallingEdge
} spi_clockPhase_t, *spi_clockPhase_pt;
struct spi_s
{
SpiIpc7207Reg_pt membase; /* Register address */
IRQn_Type irq; /* IRQ number of the IRQ associated to the device. */
uint8_t irqEnable; /* IRQ enables for 8 IRQ sources:
struct spi_s {
SpiIpc7207Reg_pt membase; /* Register address */
IRQn_Type irq; /* IRQ number of the IRQ associated to the device. */
uint8_t irqEnable; /* IRQ enables for 8 IRQ sources:
* - bit 7 = Receive FIFO Full
* - bit 6 = Receive FIFO 'Half' Full (watermark level)
* - bit 5 = Receive FIFO Not Empty
@ -150,44 +148,43 @@ struct spi_s
* - bit 1 = Transfer Error
* - bit 0 = ssIn (conditionally inverted and synchronized to PCLK)
* (unused option in current implementation / irq 6 and 7 used) */
uint8_t slaveSelectEnable; /* Slave Select enables (x4):
uint8_t slaveSelectEnable; /* Slave Select enables (x4):
* - 0 (x4) = Slave select enable
* - 1 (x4) = Slave select disable */
uint8_t slaveSelectBurst; /* Slave Select burst mode:
uint8_t slaveSelectBurst; /* Slave Select burst mode:
* - NO_BURST_MODE = Burst mode disable
* - BURST_MODE = Burst mode enable */
uint8_t slaveSelectPolarity;/* Slave Select polarity (x4) for up to 4 slaves:
uint8_t slaveSelectPolarity;/* Slave Select polarity (x4) for up to 4 slaves:
* - 0 (x4) = Slave select is active low
* - 1 (x4) = Slave select is active high */
uint8_t txWatermark; /* Transmit FIFO Watermark: Defines level of RX Half Full Flag
uint8_t txWatermark; /* Transmit FIFO Watermark: Defines level of RX Half Full Flag
* - Value between 1 and 15
* (unused option in current implementation / not txWatermark irq used) */
uint8_t rxWatermark; /* Receive FIFO Watermark: Defines level of TX Half Full Flag:
uint8_t rxWatermark; /* Receive FIFO Watermark: Defines level of TX Half Full Flag:
* - Value between 1 and 15
* * (unused option in current implementation / rxWatermark fixed to 1) */
spi_ipc7207_endian_t endian; /* Bits endianness:
spi_ipc7207_endian_t endian; /* Bits endianness:
* - LITTLE_ENDIAN = LSB first
* - BIG_ENDIAN = MSB first */
uint8_t samplingEdge; /* SDI sampling edge (relative to SDO sampling edge):
uint8_t samplingEdge; /* SDI sampling edge (relative to SDO sampling edge):
* - 0 = opposite to SDO sampling edge
* - 1 = same as SDO sampling edge */
uint32_t baudrate; /* The expected baud rate. */
spi_clockPolarity_t clockPolarity; /* The clock polarity (active high or low). */
spi_clockPhase_t clockPhase; /* The clock phase (sample on rising or falling edge). */
uint8_t wordSize; /* The size word size in number of bits. */
uint8_t Mode;
uint32_t event;
uint32_t baudrate; /* The expected baud rate. */
spi_clockPolarity_t clockPolarity; /* The clock polarity (active high or low). */
spi_clockPhase_t clockPhase; /* The clock phase (sample on rising or falling edge). */
uint8_t wordSize; /* The size word size in number of bits. */
uint8_t Mode;
uint32_t event;
};
struct i2c_s
{
uint32_t baudrate; /**< The expected baud rate. */
uint32_t I2cStatusFromInt;
uint8_t ClockSource; /**< I2C clock source, 0 – clkI2C pin, 1 – PCLK */
uint8_t irqEnable; /**< IRQs to be enabled */
I2cIpc7208Reg_pt membase; /**< The memory base for the device's registers. */
IRQn_Type irq; /**< The IRQ number of the IRQ associated to the device. */
//queue_pt rxQueue; /**< The receive queue for the device instance. */
struct i2c_s {
uint32_t baudrate; /**< The expected baud rate. */
uint32_t I2cStatusFromInt;
uint8_t ClockSource; /**< I2C clock source, 0 – clkI2C pin, 1 – PCLK */
uint8_t irqEnable; /**< IRQs to be enabled */
I2cIpc7208Reg_pt membase; /**< The memory base for the device's registers. */
IRQn_Type irq; /**< The IRQ number of the IRQ associated to the device. */
//queue_pt rxQueue; /**< The receive queue for the device instance. */
};
#ifdef __cplusplus

12
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pad.h
View File

@ -49,8 +49,8 @@
#define CROSS_REG_ADRS_BYTE_SIZE 4
#define PAD_REG_ADRS_BYTE_SIZE 4
#define PAD_REG_ADRS_BYTE_SIZE 4
/*************************************************************************************************
@ -60,18 +60,18 @@
*************************************************************************************************/
/**
* @brief
* Configures the PAD IO for desired behavior
* @brief
* Configures the PAD IO for desired behavior
*/
extern void fPadInit();
/**
* @brief
* @brief
* Set ouptput drive strength, output drive type & pull type for PAD IO
*
* @param PadNum Pad number
* @param OutputDriveStrength Ouput drive strength. Ref Table: O/p drive strength
* @param OutputDriveType Push/pull: 0; opern dran: 1
* @param OutputDriveType Push/pull: 0; opern dran: 1
* @param PullType Pull down active: 0; no pull active:1 or 2; pull up active: 3
*
* @return true for success; false for invalid parameters

288
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pad_map.h
View File

@ -86,150 +86,150 @@
* push/pull control and output drive type.
*/
typedef struct {
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO0;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO1;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO2;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO3;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO4;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO5;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO6;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO7;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO8;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO9;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO10;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO11;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO12;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO13;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO14;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO15;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO16;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO17;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO0;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO1;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO2;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO3;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO4;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO5;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO6;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO7;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO8;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO9;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO10;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO11;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO12;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO13;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO14;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO15;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO16;
union {
struct {
__IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/
__IO uint32_t POWER :3; /**< Output Drive Strength*/
__IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/
} BITS;
__IO uint32_t WORD;
} PADIO17;
} PadReg_t, *PadReg_pt;
#endif /* PAD_MAP_H_ */

85
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pinmap.c
View File

@ -23,63 +23,62 @@
void pin_function(PinName pin, int function)
{
/** - Enable the clock for PAD peripheral device */
CLOCK_ENABLE(CLOCK_CROSSB);
/** - Enable the clock for PAD peripheral device */
CLOCK_ENABLE(CLOCK_CROSSB);
/* Note: GPIO 0,1,2,3 are used for UART 1, GPIO 8,9 are used for UART 2 */
CrossbReg_pt crossBar = (CrossbReg_t *)(CROSSBREG_BASE + (pin * CROSS_REG_ADRS_BYTE_SIZE));
crossBar->DIOCTRL0 = function;
/* Note: GPIO 0,1,2,3 are used for UART 1, GPIO 8,9 are used for UART 2 */
CrossbReg_pt crossBar = (CrossbReg_t *)(CROSSBREG_BASE + (pin * CROSS_REG_ADRS_BYTE_SIZE));
crossBar->DIOCTRL0 = function;
/** - Disable the clock for PAD peripheral device */
CLOCK_DISABLE(CLOCK_CROSSB);
CLOCK_DISABLE(CLOCK_CROSSB);
}
void pin_mode(PinName pin, PinMode mode)
{
/** - Get PAD IO register address for the PAD number */
PadReg_t *padRegOffset = (PadReg_t*)(PADREG_BASE + (pin * PAD_REG_ADRS_BYTE_SIZE));
/** - Enable the clock for PAD peripheral device */
CLOCK_ENABLE(CLOCK_PAD);
PadReg_t *padRegOffset = (PadReg_t*)(PADREG_BASE + (pin * PAD_REG_ADRS_BYTE_SIZE));
switch (mode)
{
case PushPullPullDown:
padRegOffset->PADIO0.BITS.TYPE = PAD_OUTCFG_PUSHPULL;
padRegOffset->PADIO0.BITS.PULL = PAD_PULL_DOWN;
break;
/** - Enable the clock for PAD peripheral device */
CLOCK_ENABLE(CLOCK_PAD);
case PushPullNoPull:
padRegOffset->PADIO0.BITS.TYPE = PAD_OUTCFG_PUSHPULL;
padRegOffset->PADIO0.BITS.PULL = PAD_PULL_NONE;
break;
switch (mode) {
case PushPullPullDown:
padRegOffset->PADIO0.BITS.TYPE = PAD_OUTCFG_PUSHPULL;
padRegOffset->PADIO0.BITS.PULL = PAD_PULL_DOWN;
break;
case PushPullPullUp:
padRegOffset->PADIO0.BITS.TYPE = PAD_OUTCFG_PUSHPULL;
padRegOffset->PADIO0.BITS.PULL = PAD_PULL_UP;
break;
case PushPullNoPull:
padRegOffset->PADIO0.BITS.TYPE = PAD_OUTCFG_PUSHPULL;
padRegOffset->PADIO0.BITS.PULL = PAD_PULL_NONE;
break;
case OpenDrainPullDown:
padRegOffset->PADIO0.BITS.TYPE = PAD_OOUTCFG_OPENDRAIN;
padRegOffset->PADIO0.BITS.PULL = PAD_PULL_DOWN;
break;
case PushPullPullUp:
padRegOffset->PADIO0.BITS.TYPE = PAD_OUTCFG_PUSHPULL;
padRegOffset->PADIO0.BITS.PULL = PAD_PULL_UP;
break;
case OpenDrainNoPull:
padRegOffset->PADIO0.BITS.TYPE = PAD_OOUTCFG_OPENDRAIN;
padRegOffset->PADIO0.BITS.PULL = PAD_PULL_NONE;
break;
case OpenDrainPullDown:
padRegOffset->PADIO0.BITS.TYPE = PAD_OOUTCFG_OPENDRAIN;
padRegOffset->PADIO0.BITS.PULL = PAD_PULL_DOWN;
break;
case OpenDrainPullUp:
padRegOffset->PADIO0.BITS.TYPE = PAD_OOUTCFG_OPENDRAIN;
padRegOffset->PADIO0.BITS.PULL = PAD_PULL_UP;
break;
case OpenDrainNoPull:
padRegOffset->PADIO0.BITS.TYPE = PAD_OOUTCFG_OPENDRAIN;
padRegOffset->PADIO0.BITS.PULL = PAD_PULL_NONE;
break;
default:
break;
}
/** - Disable the clock for PAD peripheral device */
CLOCK_DISABLE(CLOCK_PAD);
case OpenDrainPullUp:
padRegOffset->PADIO0.BITS.TYPE = PAD_OOUTCFG_OPENDRAIN;
padRegOffset->PADIO0.BITS.PULL = PAD_PULL_UP;
break;
default:
break;
}
/** - Disable the clock for PAD peripheral device */
CLOCK_DISABLE(CLOCK_PAD);
}

106
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h
View File

@ -44,63 +44,63 @@
* The Power Management Unit (PMU) is used to control the differing power modes.
*/
typedef struct {
union {
struct {
__IO uint32_t ENCOMA :1; /**< 0- Sleep or SleepDeep depending on System Control Register (see WFI and WFE instructions), 1 – Coma */
__IO uint32_t SRAMA :1; /**< SRAMA Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */
__IO uint32_t SRAMB :1; /**< SRAMB Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */
__IO uint32_t EXT32K :1; /**< External 32.768kHz Enable: 0 – Disabled (off), 1 – Enabled (on), Hardware guarantees that this oscillator cannot be powered if the internal 32kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */
__IO uint32_t INT32K :1; /**< Internal 32kHz Enable: 0 – Enabled (on), 1 – Disabled (Off), Hardware guarantees that this oscillator cannot be powered down if the external 32.768kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */
__IO uint32_t INT32M :1; /**< Internal 32MHz Enable: 0 – Enabled (on), 1 – Disabled (off), This bit will automatically get cleared when exiting Coma, or SleepDeep modes of operation. This bit should be set by software after switching over to the external 32MHz oscillator using the Oscillator Select bit in the Clock Control register */
__IO uint32_t C1V1:1; /**< Coma mode 1V1 regulator setting: 0 - Linear regulator, 1 - switching regulator */
__IO uint32_t N1V1:1; /**< Regular mode (Run sleep and deepsleep) 1V1 regulator mode: 0 - Linear regulator, 1 - switching regulator */
__IO uint32_t DBGPOW :1; /**< Debugger Power Behavior: 0 – Normal power behavior when the debugger is present, 1 – When debugger is present the ASIC can only enter SleepDeep mode and FVDDH and FVDDL always remain powered. The 32MHz oscillators can never be powered down in this mode either. */
__IO uint32_t UVIC:1; /**< Under voltage indicator control: 0 - disabled, 1 - enabled */
__IO uint32_t UVII:1; /**< Under voltage indicator input: 0 - 1V1 regulator, 1 - FVDDH regulator */
__IO uint32_t UVIR:1; /**< Under voltage indicator reset: 0 - do not reset, 1 - reset */
} BITS;
__IO uint32_t WORD;
} CONTROL; /* 0x4001D000 */
union {
struct {
__I uint32_t BATTDET:1; /**< Detected battery: 0 - 1V, 1 - 3V */
__I uint32_t UVIC:1; /**< Under voltage status: 0 - normal, 1 - low */
union {
struct {
__IO uint32_t ENCOMA :1; /**< 0- Sleep or SleepDeep depending on System Control Register (see WFI and WFE instructions), 1 – Coma */
__IO uint32_t SRAMA :1; /**< SRAMA Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */
__IO uint32_t SRAMB :1; /**< SRAMB Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */
__IO uint32_t EXT32K :1; /**< External 32.768kHz Enable: 0 – Disabled (off), 1 – Enabled (on), Hardware guarantees that this oscillator cannot be powered if the internal 32kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */
__IO uint32_t INT32K :1; /**< Internal 32kHz Enable: 0 – Enabled (on), 1 – Disabled (Off), Hardware guarantees that this oscillator cannot be powered down if the external 32.768kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */
__IO uint32_t INT32M :1; /**< Internal 32MHz Enable: 0 – Enabled (on), 1 – Disabled (off), This bit will automatically get cleared when exiting Coma, or SleepDeep modes of operation. This bit should be set by software after switching over to the external 32MHz oscillator using the Oscillator Select bit in the Clock Control register */
__IO uint32_t C1V1:1; /**< Coma mode 1V1 regulator setting: 0 - Linear regulator, 1 - switching regulator */
__IO uint32_t N1V1:1; /**< Regular mode (Run sleep and deepsleep) 1V1 regulator mode: 0 - Linear regulator, 1 - switching regulator */
__IO uint32_t DBGPOW :1; /**< Debugger Power Behavior: 0 – Normal power behavior when the debugger is present, 1 – When debugger is present the ASIC can only enter SleepDeep mode and FVDDH and FVDDL always remain powered. The 32MHz oscillators can never be powered down in this mode either. */
__IO uint32_t UVIC:1; /**< Under voltage indicator control: 0 - disabled, 1 - enabled */
__IO uint32_t UVII:1; /**< Under voltage indicator input: 0 - 1V1 regulator, 1 - FVDDH regulator */
__IO uint32_t UVIR:1; /**< Under voltage indicator reset: 0 - do not reset, 1 - reset */
} BITS;
__IO uint32_t WORD;
} CONTROL; /* 0x4001D000 */
union {
struct {
__I uint32_t BATTDET:1; /**< Detected battery: 0 - 1V, 1 - 3V */
__I uint32_t UVIC:1; /**< Under voltage status: 0 - normal, 1 - low */
} BITS;
__IO uint32_t WORD;
} STATUS; /* 0x4001D004 */
} BITS;
__IO uint32_t WORD;
} STATUS; /* 0x4001D004 */
#ifdef REVB
__IO uint32_t RAMBIAS;
__IO uint32_t RETAINA_T; /**< RAM retain make/break time. This is clocked using FCLK, so it’s range & resolution are determined by the FCLK divider register in the Clock Control Section. */
__IO uint32_t RETAINB_T; /**< RAM retain make/break time. This is clocked using FCLK, so it’s range & resolution are determined by the FCLK divider register in the Clock Control Section. */
__IO uint32_t FVDD_TSTARTUP; /**< Regulator start time. */
__IO uint32_t FVDD_TSETTLE; /**< Regulator settle time. */
union {
struct {
__IO uint32_t TH:6; /**< Threshold */
__I uint32_t PAD:2;
__I uint32_t UVIVAL; /**< UVI value */
} BITS;
__IO uint32_t WORD;
} UVI_TBASE;
__IO uint32_t UVI_LIM;
__IO uint32_t RAMBIAS;
__IO uint32_t RETAINA_T; /**< RAM retain make/break time. This is clocked using FCLK, so it’s range & resolution are determined by the FCLK divider register in the Clock Control Section. */
__IO uint32_t RETAINB_T; /**< RAM retain make/break time. This is clocked using FCLK, so it’s range & resolution are determined by the FCLK divider register in the Clock Control Section. */
__IO uint32_t FVDD_TSTARTUP; /**< Regulator start time. */
__IO uint32_t FVDD_TSETTLE; /**< Regulator settle time. */
union {
struct {
__IO uint32_t TH:6; /**< Threshold */
__I uint32_t PAD:2;
__I uint32_t UVIVAL; /**< UVI value */
} BITS;
__IO uint32_t WORD;
} UVI_TBASE;
__IO uint32_t UVI_LIM;
#endif /* REVB */
#ifdef REVD
__IO uint32_t PLACEHOLDER; /* 0x4001D008 */
__IO uint32_t FVDD_TSTARTUP; /**< Regulator start time. */ /* 0x4001D00C */
__IO uint32_t PLACEHOLDER1; /* 0x4001D010 */
__IO uint32_t FVDD_TSETTLE; /**< Regulator settle time. */ /* 0x4001D014 */
union {
struct {
__IO uint32_t TH:6; /**< Threshold */
__I uint32_t PAD:2;
__I uint32_t UVIVAL:6; /**< UVI value */
} BITS;
__IO uint32_t WORD;
} UVI_TBASE; /* 0x4001D018 */
__IO uint32_t SRAM_TRIM; /* 0x4001D01C */
#ifdef REVD
__IO uint32_t PLACEHOLDER; /* 0x4001D008 */
__IO uint32_t FVDD_TSTARTUP; /**< Regulator start time. */ /* 0x4001D00C */
__IO uint32_t PLACEHOLDER1; /* 0x4001D010 */
__IO uint32_t FVDD_TSETTLE; /**< Regulator settle time. */ /* 0x4001D014 */
union {
struct {
__IO uint32_t TH:6; /**< Threshold */
__I uint32_t PAD:2;
__I uint32_t UVIVAL:6; /**< UVI value */
} BITS;
__IO uint32_t WORD;
} UVI_TBASE; /* 0x4001D018 */
__IO uint32_t SRAM_TRIM; /* 0x4001D01C */
#endif /* REVD */
} PmuReg_t, *PmuReg_pt;

140
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/port_api.c
View File

@ -1,17 +1,21 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
/**
******************************************************************************
* @file port_api.c
* @brief Implementation of a port API
* @internal
* @author ON Semiconductor
* $Rev:
* $Date:
******************************************************************************
* @copyright (c) 2012 ON Semiconductor. All rights reserved.
* ON Semiconductor is supplying this software for use with ON Semiconductor
* processor based microcontrollers only.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*/
#include "gpio.h"
#include "port_api.h"
@ -26,7 +30,7 @@
*/
PinName port_pin(PortName port, int pin_n)
{
return((PinName)(pin_n));
return((PinName)(pin_n));
}
/** Initilize the port
@ -38,33 +42,32 @@ PinName port_pin(PortName port, int pin_n)
*/
void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
{
uint8_t i;
PinName pin;
uint8_t i;
PinName pin;
/* Store the port mask in obj */
obj->mask = mask;
/* Store the port mask in obj */
obj->mask = mask;
/* Store the port name in obj */
obj->port = port;
/* Store the port name in obj */
obj->port = port;
/* Store GPIO base address */
obj->GPIOMEMBASE = GPIOREG;
/* Store GPIO base address */
obj->GPIOMEMBASE = GPIOREG;
for (i=0; i<NUMBER_OF_GPIO; i++)
{
/* check for valid pin */
if (obj->mask & (1<<i)) {
for (i=0; i<NUMBER_OF_GPIO; i++) {
/* check for valid pin */
if (obj->mask & (1<<i)) {
/* Gpio numbers start from DIO#0 to #17, so can pass in "i" */
pin = port_pin(obj->port, i);
/* Gpio numbers start from DIO#0 to #17, so can pass in "i" */
pin = port_pin(obj->port, i);
/* Set the pin as GPIO */
gpio_set(pin);
}
}
/* Set the pin as GPIO */
gpio_set(pin);
}
}
/* Call function to set pin direction */
port_dir(obj, dir);
/* Call function to set pin direction */
port_dir(obj, dir);
}
/** Set the input port mode
@ -74,22 +77,21 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
*/
void port_mode(port_t *obj, PinMode mode)
{
uint8_t i = 0;
PinName pin;
uint8_t i = 0;
PinName pin;
/* For each pin in the mask, set the mode to that defined in "mode" parameter */
for (i=0; i < NUMBER_OF_GPIO; i++)
{
/* check for valid pin */
if (obj->mask & (1<<i)) {
/* For each pin in the mask, set the mode to that defined in "mode" parameter */
for (i=0; i < NUMBER_OF_GPIO; i++) {
/* check for valid pin */
if (obj->mask & (1<<i)) {
/* get the pin name */
pin = port_pin(obj->port, i);
/* get the pin name */
pin = port_pin(obj->port, i);
/* Set the mode for the pin */
pin_mode(pin, mode);
}
}
/* Set the mode for the pin */
pin_mode(pin, mode);
}
}
}
/** Set port direction (in/out)
@ -99,17 +101,17 @@ void port_mode(port_t *obj, PinMode mode)
*/
void port_dir(port_t *obj, PinDirection dir)
{
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
if (dir == PIN_INPUT) {
obj->GPIOMEMBASE->W_IN = obj->mask;
} else if (dir == PIN_OUTPUT) {
obj->GPIOMEMBASE->W_OUT = obj->mask;
}
if (dir == PIN_INPUT) {
obj->GPIOMEMBASE->W_IN = obj->mask;
} else if (dir == PIN_OUTPUT) {
obj->GPIOMEMBASE->W_OUT = obj->mask;
}
/* Disable the GPIO clock */
CLOCK_DISABLE(CLOCK_GPIO);
/* Disable the GPIO clock */
CLOCK_DISABLE(CLOCK_GPIO);
}
/** Write value to the port
@ -119,14 +121,14 @@ void port_dir(port_t *obj, PinDirection dir)
*/
void port_write(port_t *obj, int value)
{
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
obj->GPIOMEMBASE->R_STATE_W_SET = value;//(obj->mask & value);
obj->GPIOMEMBASE->R_IRQ_W_CLEAR = ~value;//(obj->mask ^ value);
obj->GPIOMEMBASE->R_STATE_W_SET = value;//(obj->mask & value);
obj->GPIOMEMBASE->R_IRQ_W_CLEAR = ~value;//(obj->mask ^ value);
/* Disable the GPIO clock */
CLOCK_DISABLE(CLOCK_GPIO);
/* Disable the GPIO clock */
CLOCK_DISABLE(CLOCK_GPIO);
}
/** Read the current value on the port
@ -136,17 +138,17 @@ void port_write(port_t *obj, int value)
*/
int port_read(port_t *obj)
{
int gpio_level = 0;
int gpio_level = 0;
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
/* Enable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
gpio_level = obj->GPIOMEMBASE->R_STATE_W_SET;
gpio_level = obj->GPIOMEMBASE->R_STATE_W_SET;
/* Disable the GPIO clock */
CLOCK_ENABLE(CLOCK_GPIO);
/* Disable the GPIO clock */
CLOCK_DISABLE(CLOCK_GPIO);
return(gpio_level);
return(gpio_level);
}
#endif

93
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h
View File

@ -40,60 +40,55 @@
/** Power management Control HW Structure Overlay */
#ifdef REVB
typedef struct {
__IO uint32_t DUTYCYCLE;
union {
struct {
__IO uint32_t ENABLED :1;/**< 1 = PWM enable , 0 = PWM disable */
__I uint32_t CURRENT :1;/**< current state of PWM enable signal */
__O uint32_t PAD1 :6; /**< Reserved. Writes have no effect; Read as 0x00. */
__O uint32_t RDPWMEN :1;/**< current state of pwmEnable configuration */
__O uint32_t RDPWMOP :1;/**< current state of PWM out signal */
__O uint32_t PAD2 :6; /**< Reserved. Writes have no effect; Read as 0x00. */
} BITS;
__I uint32_t WORD;
} PWMOUT;
__O uint32_t DISABLE;
union {
struct {
__IO uint32_t ENABLED :1;
__O uint32_t PAD1 :7; /**< Reserved. Writes have no effect */
__O uint32_t STATE :1; /**< current state of prescaler enable configuration. */
__O uint32_t PAD2 :7; /**< Reserved. Writes have no effect; Read as 0x00. */
} BITS;
__I uint32_t WORD;
} PRESCALE_EN;
__IO uint32_t DUTYCYCLE;
union {
struct {
__IO uint32_t ENABLED :1;/**< 1 = PWM enable , 0 = PWM disable */
__I uint32_t CURRENT :1;/**< current state of PWM enable signal */
__O uint32_t PAD1 :6; /**< Reserved. Writes have no effect; Read as 0x00. */
__O uint32_t RDPWMEN :1;/**< current state of pwmEnable configuration */
__O uint32_t RDPWMOP :1;/**< current state of PWM out signal */
__O uint32_t PAD2 :6; /**< Reserved. Writes have no effect; Read as 0x00. */
} BITS;
__I uint32_t WORD;
} PWMOUT;
__O uint32_t DISABLE;
union {
struct {
__IO uint32_t ENABLED :1;
__O uint32_t PAD1 :7; /**< Reserved. Writes have no effect */
__O uint32_t STATE :1; /**< current state of prescaler enable configuration. */
__O uint32_t PAD2 :7; /**< Reserved. Writes have no effect; Read as 0x00. */
} BITS;
__I uint32_t WORD;
} PRESCALE_EN;
__O uint32_t PRESCALE_DIS;
__O uint32_t PRESCALE_DIS;
} PwmReg_t, *PwmReg_pt;
#endif /* REVB */
#ifdef REVD
typedef struct
{
__IO uint32_t DUTYCYCLE;
union
{
struct
{
__O uint32_t ENABLE :8; /**< Write any value to enable PWM output */
__I uint32_t PAD :1; /** < Pad */
__I uint32_t ENABLE_STATE :1; /**< Current state of pwmEnable configuration bit. ‘1’ PWM output is enabled. ‘0’ PWN output is disabled. */
__I uint32_t OUTPUT_STATE :1; /**< Current state of PWM output */
}BITS;
__IO uint32_t WORD;
}PWM_ENABLE;
__O uint32_t PWM_DISABLE;
union
{
struct
{
__O uint32_t ENABLE :8; /**< Write any value to select enable the 4-bit prescaler */
__I uint32_t STATE:1; /**< Current state of the prescaler. ‘1’ the prescaler is enabled. ‘0’ the prescaler is disabled. */
}BITS;
__IO uint32_t WORD;
}PRESCALE_ENABLE;
__O uint32_t PRESCALE_DISABLE;
}PwmReg_t, *PwmReg_pt;
typedef struct {
__IO uint32_t DUTYCYCLE;
union {
struct {
__O uint32_t ENABLE :8; /**< Write any value to enable PWM output */
__I uint32_t PAD :1; /** < Pad */
__I uint32_t ENABLE_STATE :1; /**< Current state of pwmEnable configuration bit. ‘1’ PWM output is enabled. ‘0’ PWN output is disabled. */
__I uint32_t OUTPUT_STATE :1; /**< Current state of PWM output */
} BITS;
__IO uint32_t WORD;
} PWM_ENABLE;
__O uint32_t PWM_DISABLE;
union {
struct {
__O uint32_t ENABLE :8; /**< Write any value to select enable the 4-bit prescaler */
__I uint32_t STATE:1; /**< Current state of the prescaler. ‘1’ the prescaler is enabled. ‘0’ the prescaler is disabled. */
} BITS;
__IO uint32_t WORD;
} PRESCALE_ENABLE;
__O uint32_t PRESCALE_DISABLE;
} PwmReg_t, *PwmReg_pt;
#endif /* REVD */
#endif /* PWM_MAP_H_ */

169
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pwmout_api.c
View File

@ -1,19 +1,23 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
/**
******************************************************************************
* @file pwmout_api.c
* @brief Implementation of a PWM driver
* @internal
* @author ON Semiconductor
* $Rev:
* $Date:
******************************************************************************
* @copyright (c) 2012 ON Semiconductor. All rights reserved.
* ON Semiconductor is supplying this software for use with ON Semiconductor
* processor based microcontrollers only.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* @endinternal
*/
#include "pwmout_api.h"
#include "PeripheralPins.h"
#include "mbed_assert.h"
@ -33,27 +37,27 @@
*/
void pwmout_init(pwmout_t *obj, PinName pin)
{
/* Get the base address of the PWM register using the pinmap functions ; pwmout_s struct contains base address only */
/* Get the base address of the PWM register using the pinmap functions ; pwmout_s struct contains base address only */
PWMName pwm;
pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
MBED_ASSERT(pwm != (PWMName)NC);
pinmap_pinout(pin, PinMap_PWM);
pinmap_pinout(pin, PinMap_PWM);
obj->pwmReg = (PwmReg_pt)pwm;
MBED_ASSERT(obj->pwmReg != 0x00000000);
obj->pwmReg = (PwmReg_pt)pwm;
MBED_ASSERT(obj->pwmReg != 0x00000000);
CLOCK_ENABLE(CLOCK_PWM);
CLOCK_ENABLE(CLOCK_PWM);
/* Configuration parameters of duty cycle 0x4000B000, and prescaler 0x4000B00C, shall be set to default values */
/* Duty cycle shall be 50% and prescaler shall be disabled by default */
obj->pwmReg->DUTYCYCLE = 0x80;
/* Configuration parameters of duty cycle 0x4000B000, and prescaler 0x4000B00C, shall be set to default values */
/* Duty cycle shall be 50% and prescaler shall be disabled by default */
obj->pwmReg->DUTYCYCLE = 0x80;
/* Write the PWM output enable register 0x4000B004, to 1 */
obj->pwmReg->PWM_ENABLE.WORD = 0x1;
/* Write the PWM output enable register 0x4000B004, to 1 */
obj->pwmReg->PWM_ENABLE.WORD = 0x1;
obj->pwmReg->PRESCALE_DISABLE = 0x1;
obj->pwmReg->PRESCALE_DISABLE = 0x1;
}
@ -63,8 +67,8 @@ void pwmout_init(pwmout_t *obj, PinName pin)
*/
void pwmout_free(pwmout_t *obj)
{
/* Write the PWM output disable register 0x4000B008, to 1 */
obj->pwmReg->PWM_DISABLE = 0x1;
/* Write the PWM output disable register 0x4000B008, to 1 */
obj->pwmReg->PWM_DISABLE = 0x1;
}
/** Set the output duty-cycle in range <0.0f, 1.0f>
@ -75,20 +79,15 @@ void pwmout_free(pwmout_t *obj)
*/
void pwmout_write(pwmout_t *obj, float percent)
{
if (percent == 0.0)
{
obj->pwmReg->DUTYCYCLE = 0x00;
}
else if (percent == 1.0)
{
obj->pwmReg->DUTYCYCLE = 0xFF;
}
else
{
/* Write the duty cycle config register 0x4000B000, with the value passed on */
/* ((percent * 255) + 1) is the duty cycle. Plus 1 is for accounting for round off errors; like a ceil function */
obj->pwmReg->DUTYCYCLE = (uint8_t)((percent * 255) + 1);
}
if (percent == 0.0) {
obj->pwmReg->DUTYCYCLE = 0x00;
} else if (percent == 1.0) {
obj->pwmReg->DUTYCYCLE = 0xFF;
} else {
/* Write the duty cycle config register 0x4000B000, with the value passed on */
/* ((percent * 255) + 1) is the duty cycle. Plus 1 is for accounting for round off errors; like a ceil function */
obj->pwmReg->DUTYCYCLE = (uint8_t)((percent * 255) + 1);
}
}
/** Read the current float-point output duty-cycle
@ -98,15 +97,15 @@ void pwmout_write(pwmout_t *obj, float percent)
*/
float pwmout_read(pwmout_t *obj)
{
float retVal = 0.0;
float dc = 0.0;
float retVal = 0.0;
float dc = 0.0;
/* Read out the value of duty cycle register 0x4000B000 and return as a percent */
/* Read value / 255 is the percent returned */
dc = obj->pwmReg->DUTYCYCLE;
retVal = dc/ (float)255;
/* Read out the value of duty cycle register 0x4000B000 and return as a percent */
/* Read value / 255 is the percent returned */
dc = obj->pwmReg->DUTYCYCLE;
retVal = dc/ (float)255;
return(retVal);
return(retVal);
}
/** Set the PWM period specified in seconds, keeping the duty cycle the same
@ -117,8 +116,8 @@ float pwmout_read(pwmout_t *obj)
*/
void pwmout_period(pwmout_t *obj, float seconds)
{
/* Cannot be configured, prescaler is either 256 or 4096 */
return;
/* Cannot be configured, prescaler is either 256 or 4096 */
return;
}
/** Set the PWM period specified in miliseconds, keeping the duty cycle the same
@ -128,8 +127,8 @@ void pwmout_period(pwmout_t *obj, float seconds)
*/
void pwmout_period_ms(pwmout_t *obj, int ms)
{
/* Cannot be configured, prescaler is either 256 or 4096 */
return;
/* Cannot be configured, prescaler is either 256 or 4096 */
return;
}
/** Set the PWM period specified in microseconds, keeping the duty cycle the same
@ -139,8 +138,8 @@ void pwmout_period_ms(pwmout_t *obj, int ms)
*/
void pwmout_period_us(pwmout_t *obj, int us)
{
/* Cannot be configured, prescaler is either 256 or 4096 */
return;
/* Cannot be configured, prescaler is either 256 or 4096 */
return;
}
/** Set the PWM pulsewidth specified in seconds, keeping the period the same.
@ -150,10 +149,10 @@ void pwmout_period_us(pwmout_t *obj, int us)
*/
void pwmout_pulsewidth(pwmout_t *obj, float seconds)
{
/* Pulse width can never be in seconds since the period
* itself is limited to either 8uSec or 128uSec
*/
return;
/* Pulse width can never be in seconds since the period
* itself is limited to either 8uSec or 128uSec
*/
return;
}
/** Set the PWM pulsewidth specified in miliseconds, keeping the period the same.
@ -164,10 +163,10 @@ void pwmout_pulsewidth(pwmout_t *obj, float seconds)
void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
{
/* Pulse width can never be in seconds since the period
* itself is limited to either 8uSec or 128uSec
*/
return;
/* Pulse width can never be in seconds since the period
* itself is limited to either 8uSec or 128uSec
*/
return;
}
/** Set the PWM pulsewidth specified in microseconds, keeping the period the same.
@ -177,32 +176,26 @@ void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
*/
void pwmout_pulsewidth_us(pwmout_t *obj, int us)
{
int pulseWidth = 0;
int pulseWidth = 0;
/* Check if the uSec value is greater than 128uSec, if so reject */
if (us > 128)
{
return;
}
/* If pulsewidth is less than 128uSec, set the prescaler to 4096
* by enabling prescale register 0x4000B00C to 1 */
obj->pwmReg->PRESCALE_ENABLE.WORD = 0x1;
/* Check if the uSec value is greater than 128uSec, if so reject */
if (us > 128) {
return;
}
/* If pulsewidth is less than 128uSec, set the prescaler to 4096
* by enabling prescale register 0x4000B00C to 1 */
obj->pwmReg->PRESCALE_ENABLE.WORD = 0x1;
/* Calculate the duty cycle based on the width of the pulse */
/* ((255 * us) / 128) + 1 = duty cycle */
pulseWidth = (int)((float)(255 * us)/(float)128) + 1;
if (us == 0)
{
obj->pwmReg->DUTYCYCLE = 0x0;
}
else if (us == 128)
{
obj->pwmReg->DUTYCYCLE = 0xFF;
}
else
{
obj->pwmReg->DUTYCYCLE = (uint8_t)pulseWidth;
}
/* Calculate the duty cycle based on the width of the pulse */
/* ((255 * us) / 128) + 1 = duty cycle */
pulseWidth = (int)((float)(255 * us)/(float)128) + 1;
if (us == 0) {
obj->pwmReg->DUTYCYCLE = 0x0;
} else if (us == 128) {
obj->pwmReg->DUTYCYCLE = 0xFF;
} else {
obj->pwmReg->DUTYCYCLE = (uint8_t)pulseWidth;
}
}
/**@}*/

114
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/random_map.h
View File

@ -42,69 +42,59 @@
/** Random Number Generator Control HW Structure Overlay */
typedef struct {
__IO uint32_t WR_SEED_RD_RAND; /* Seed set & random read reg - 0x40011000 */
#ifdef REVB
__IO uint32_t MODE;
__IO uint32_t WR_SEED_RD_RAND; /* Seed set & random read reg - 0x40011000 */
#ifdef REVB
__IO uint32_t MODE;
#endif /* REVB */
union
{
struct
{
__IO uint32_t MODE :1; /**<Mode Register, 0 – LSFR is updated on every rising edge of PCLK, 1 – LSFR is only updated on a read event of the LSFR register */
__IO uint32_t BYTE_SWAP :1; /**<Byte Swap Control, 0 – 32-bit byte swap, 1 – 64-bit byte swap */
__IO uint32_t MEATSTABLE_SPEED :1; /**<Meta-stable Latch TRNG Speed Control, 0 – Slow mode, 1 – Fast mode */
__IO uint32_t WHITENOISE_EN :1; /**<White Noise TRNG Enable, 0 – Disabled, 1 – Enabled */
__IO uint32_t METASTABLE_LATCH_EN :1; /**<Meta-stable Latch TRNG Enable, 0 – Disabled, 1 – Enabled */
__IO uint32_t JIC :1; /**<JIC */
} BITS;
__IO uint32_t WORD;
} CONTROL; /* Control register - 0x40011004 */
union
{
struct
{
__IO uint32_t BYTE_0 :8; /**<Byte #0*/
__IO uint32_t BYTE_1 :8; /**<Byte #1*/
__IO uint32_t BYTE_2 :8; /**<Byte #2*/
__IO uint32_t BYTE_3 :8; /**<Byte #3*/
} BITS;
__IO uint32_t WORD;
} WRITE_BUF_LSW; /* Byte swap write buffer – Least significant word - 0x40011008 */
union
{
struct
{
__IO uint32_t BYTE_4 :8; /**<Byte #4*/
__IO uint32_t BYTE_5 :8; /**<Byte #5*/
__IO uint32_t BYTE_6 :8; /**<Byte #6*/
__IO uint32_t BYTE_7 :8; /**<Byte #7*/
} BITS;
__IO uint32_t WORD;
} WRITE_BUF_MSW; /* Byte swap write buffer – Most significant word - 0x4001100C */
union
{
struct
{
__IO uint32_t BYTE_7_3 :8; /**<Byte Swap Control == 1? Byte #7 : Byte #3*/
__IO uint32_t BYTE_6_2 :8; /**<Byte Swap Control == 1? Byte #6 : Byte #2*/
__IO uint32_t BYTE_5_1 :8; /**<Byte Swap Control == 1? Byte #5 : Byte #1*/
__IO uint32_t BYTE_4_0 :8; /**<Byte Swap Control == 1? Byte #4 : Byte #0*/
} BITS;
__IO uint32_t WORD;
} READ_BUF_LSW; /* Byte swap read buffer – Least significant word - 0x40011010 */
union
{
struct
{
__IO uint32_t BYTE_3 :8; /**<Byte #3*/
__IO uint32_t BYTE_2 :8; /**<Byte #2*/
__IO uint32_t BYTE_1 :8; /**<Byte #1*/
__IO uint32_t BYTE_0 :8; /**<Byte #0*/
} BITS;
__IO uint32_t WORD;
} READ_BUF_MSW; /* Byte swap read buffer – Most significant word - 0x40011014 */
__I uint32_t METASTABLE_LATCH_VAL; /* Meta-stable latch TRNG value - 0x40011018 */
__I uint32_t WHITENOISE_VAL; /* White noise TRNG value - 0x4001101C */
union {
struct {
__IO uint32_t MODE :1; /**<Mode Register, 0 – LSFR is updated on every rising edge of PCLK, 1 – LSFR is only updated on a read event of the LSFR register */
__IO uint32_t BYTE_SWAP :1; /**<Byte Swap Control, 0 – 32-bit byte swap, 1 – 64-bit byte swap */
__IO uint32_t MEATSTABLE_SPEED :1; /**<Meta-stable Latch TRNG Speed Control, 0 – Slow mode, 1 – Fast mode */
__IO uint32_t WHITENOISE_EN :1; /**<White Noise TRNG Enable, 0 – Disabled, 1 – Enabled */
__IO uint32_t METASTABLE_LATCH_EN :1; /**<Meta-stable Latch TRNG Enable, 0 – Disabled, 1 – Enabled */
__IO uint32_t JIC :1; /**<JIC */
} BITS;
__IO uint32_t WORD;
} CONTROL; /* Control register - 0x40011004 */
union {
struct {
__IO uint32_t BYTE_0 :8; /**<Byte #0*/
__IO uint32_t BYTE_1 :8; /**<Byte #1*/
__IO uint32_t BYTE_2 :8; /**<Byte #2*/
__IO uint32_t BYTE_3 :8; /**<Byte #3*/
} BITS;
__IO uint32_t WORD;
} WRITE_BUF_LSW; /* Byte swap write buffer – Least significant word - 0x40011008 */
union {
struct {
__IO uint32_t BYTE_4 :8; /**<Byte #4*/
__IO uint32_t BYTE_5 :8; /**<Byte #5*/
__IO uint32_t BYTE_6 :8; /**<Byte #6*/
__IO uint32_t BYTE_7 :8; /**<Byte #7*/
} BITS;
__IO uint32_t WORD;
} WRITE_BUF_MSW; /* Byte swap write buffer – Most significant word - 0x4001100C */
union {
struct {
__IO uint32_t BYTE_7_3 :8; /**<Byte Swap Control == 1? Byte #7 : Byte #3*/
__IO uint32_t BYTE_6_2 :8; /**<Byte Swap Control == 1? Byte #6 : Byte #2*/
__IO uint32_t BYTE_5_1 :8; /**<Byte Swap Control == 1? Byte #5 : Byte #1*/
__IO uint32_t BYTE_4_0 :8; /**<Byte Swap Control == 1? Byte #4 : Byte #0*/
} BITS;
__IO uint32_t WORD;
} READ_BUF_LSW; /* Byte swap read buffer – Least significant word - 0x40011010 */
union {
struct {
__IO uint32_t BYTE_3 :8; /**<Byte #3*/
__IO uint32_t BYTE_2 :8; /**<Byte #2*/
__IO uint32_t BYTE_1 :8; /**<Byte #1*/
__IO uint32_t BYTE_0 :8; /**<Byte #0*/
} BITS;
__IO uint32_t WORD;
} READ_BUF_MSW; /* Byte swap read buffer – Most significant word - 0x40011014 */
__I uint32_t METASTABLE_LATCH_VAL; /* Meta-stable latch TRNG value - 0x40011018 */
__I uint32_t WHITENOISE_VAL; /* White noise TRNG value - 0x4001101C */
} RandReg_t, *RandReg_pt;
#endif /* RANDOM_MAP_H_ */

26
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/reset_map.h
View File

@ -44,19 +44,19 @@
* Also contains HW revision ID.
*/
typedef struct {
union {
struct {
__I uint32_t LOCKUP:1; /**< 1:Core did lock up */
__I uint32_t WDOGRES:1; /**< 1:Watchdog reset occurred */
__I uint32_t EXTRESET:1; /**< 1:External reset occurred */
__I uint32_t SYSRESETREQ:1; /**< 1:System reset occurred */
__I uint32_t POR:1; /**< 1:POR reset occurred */
} BITS;
__I uint32_t WORD;
} SOURCE;
__O uint32_t CLEARSOURCE; /**< writing any value to this register will clear the reset source register */
__I uint32_t HWREVID; /**< Hardware ID, 0x80215400 */
__IO uint32_t CONTROL; /**< External Reset & Watchdog behavior: 0 – External Reset & Watchdog will reset debug logic 1 – External Reset & Watchdog will not reset debug logic */
union {
struct {
__I uint32_t LOCKUP:1; /**< 1:Core did lock up */
__I uint32_t WDOGRES:1; /**< 1:Watchdog reset occurred */
__I uint32_t EXTRESET:1; /**< 1:External reset occurred */
__I uint32_t SYSRESETREQ:1; /**< 1:System reset occurred */
__I uint32_t POR:1; /**< 1:POR reset occurred */
} BITS;
__I uint32_t WORD;
} SOURCE;
__O uint32_t CLEARSOURCE; /**< writing any value to this register will clear the reset source register */
__I uint32_t HWREVID; /**< Hardware ID, 0x80215400 */
__IO uint32_t CONTROL; /**< External Reset & Watchdog behavior: 0 – External Reset & Watchdog will reset debug logic 1 – External Reset & Watchdog will not reset debug logic */
} ResetReg_t, *ResetReg_pt;

243
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c
View File

@ -77,27 +77,29 @@
/** This rf LUT is built for high side injection, using low side injection
* would requiere to change this LUT. */
const uint32_t rfLut[16][4] = {{0x50,0x00D4A7,0x4B,0x00A000},
{0x50,0x017F52,0x4B,0x014001},
{0x51,0xFE29FB,0x4B,0x01E001},
{0x51,0xFED4A6,0x4C,0xFE7FFF},
{0x51,0xFF7F51,0x4C,0xFF1FFF},
{0x51,0x0029FC,0x4C,0xFFC000},
{0x51,0x00D4A7,0x4C,0x006000},
{0x51,0x017F52,0x4C,0x010001},
{0x52,0xFE29FB,0x4C,0x01A001},
{0x52,0xFED4A6,0x4D,0xFE3FFF},
{0x52,0xFF7F51,0x4D,0xFEDFFF},
{0x52,0x0029FC,0x4D,0xFF8000},
{0x52,0x00D4A7,0x4D,0x002000},
{0x52,0x017F52,0x4D,0x00C001},
{0x53,0xFE29FB,0x4D,0x016001},
{0x53,0xFED4A6,0x4E,0xFDFFFE}};
{0x50,0x017F52,0x4B,0x014001},
{0x51,0xFE29FB,0x4B,0x01E001},
{0x51,0xFED4A6,0x4C,0xFE7FFF},
{0x51,0xFF7F51,0x4C,0xFF1FFF},
{0x51,0x0029FC,0x4C,0xFFC000},
{0x51,0x00D4A7,0x4C,0x006000},
{0x51,0x017F52,0x4C,0x010001},
{0x52,0xFE29FB,0x4C,0x01A001},
{0x52,0xFED4A6,0x4D,0xFE3FFF},
{0x52,0xFF7F51,0x4D,0xFEDFFF},
{0x52,0x0029FC,0x4D,0xFF8000},
{0x52,0x00D4A7,0x4D,0x002000},
{0x52,0x017F52,0x4D,0x00C001},
{0x53,0xFE29FB,0x4D,0x016001},
{0x53,0xFED4A6,0x4E,0xFDFFFE}
};
const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
0,0,0,0,0,0,0,0,1,2, // -19dBm to -10dBm
3,4,5,6,7,8,9,10,11,12, // -9dBm to 0dBm
13,14,15,16,17,18,19,20,20,20}; // +1dBm to +10 dBm
0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
0,0,0,0,0,0,0,0,1,2, // -19dBm to -10dBm
3,4,5,6,7,8,9,10,11,12, // -9dBm to 0dBm
13,14,15,16,17,18,19,20,20,20
}; // +1dBm to +10 dBm
#endif /* REVD */
@ -105,80 +107,85 @@ const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
/** This rf LUT is built for low side injection, using high side injection
* would requiere to change this LUT. */
const uint32_t rfLut[16][4] = {{0x47,0xFF15FC,0x4B,0x00A000},
{0x47,0xFFAC93,0x4B,0x014001},
{0x47,0x00432A,0x4B,0x01E001},
{0x47,0x00D9C1,0x4C,0xFE7FFF},
{0x47,0x017058,0x4C,0xFF1FFF},
{0x48,0xFE06EC,0x4C,0xFFC000},
{0x48,0xFE9D83,0x4C,0x006000},
{0x48,0xFF341A,0x4C,0x010001},
{0x48,0xFFCAB1,0x4C,0x01A001},
{0x48,0x006148,0x4D,0xFE3FFF},
{0x48,0x00F7DF,0x4D,0xFEDFFF},
{0x48,0x018E76,0x4D,0xFF8000},
{0x49,0xFE250A,0x4D,0x002000},
{0x49,0xFEBBA1,0x4D,0x00C001},
{0x49,0xFF5238,0x4D,0x016001},
{0x49,0xFFE8CF,0x4E,0xFDFFFE}
};
{0x47,0xFFAC93,0x4B,0x014001},
{0x47,0x00432A,0x4B,0x01E001},
{0x47,0x00D9C1,0x4C,0xFE7FFF},
{0x47,0x017058,0x4C,0xFF1FFF},
{0x48,0xFE06EC,0x4C,0xFFC000},
{0x48,0xFE9D83,0x4C,0x006000},
{0x48,0xFF341A,0x4C,0x010001},
{0x48,0xFFCAB1,0x4C,0x01A001},
{0x48,0x006148,0x4D,0xFE3FFF},
{0x48,0x00F7DF,0x4D,0xFEDFFF},
{0x48,0x018E76,0x4D,0xFF8000},
{0x49,0xFE250A,0x4D,0x002000},
{0x49,0xFEBBA1,0x4D,0x00C001},
{0x49,0xFF5238,0x4D,0x016001},
{0x49,0xFFE8CF,0x4E,0xFDFFFE}
};
const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
0,0,0,0,0,0,1,1,2,2, // -19dBm to -10dBm (clamp low at -14dB)
3,3,4,6,7,9,10,12,13,15, // -9dBm to 0dBm
17,19,20,20,20,20,20,20,20,20}; // +1dBm to +10 dBm (clamp high at +3dB)
17,19,20,20,20,20,20,20,20,20
}; // +1dBm to +10 dBm (clamp high at +3dB)
#endif /* REVC */
#ifdef REVB
/** This rf LUT is built for low side injection, using high side injection
* would requiere to change this LUT. */
const uint32_t rfLut[16][4] = {{0x47,0xFF15FC,0x4B,0x00A000},
{0x47,0xFFAC93,0x4B,0x014001},
{0x47,0x00432A,0x4B,0x01E001},
{0x47,0x00D9C1,0x4C,0xFE7FFF},
{0x47,0x017058,0x4C,0xFF1FFF},
{0x48,0xFE06EC,0x4C,0xFFC000},
{0x48,0xFE9D83,0x4C,0x006000},
{0x48,0xFF341A,0x4C,0x010001},
{0x48,0xFFCAB1,0x4C,0x01A001},
{0x48,0x006148,0x4D,0xFE3FFF},
{0x48,0x00F7DF,0x4D,0xFEDFFF},
{0x48,0x018E76,0x4D,0xFF8000},
{0x49,0xFE250A,0x4D,0x002000},
{0x49,0xFEBBA1,0x4D,0x00C001},
{0x49,0xFF5238,0x4D,0x016001},
{0x49,0xFFE8CF,0x4E,0xFDFFFE}};
{0x47,0xFFAC93,0x4B,0x014001},
{0x47,0x00432A,0x4B,0x01E001},
{0x47,0x00D9C1,0x4C,0xFE7FFF},
{0x47,0x017058,0x4C,0xFF1FFF},
{0x48,0xFE06EC,0x4C,0xFFC000},
{0x48,0xFE9D83,0x4C,0x006000},
{0x48,0xFF341A,0x4C,0x010001},
{0x48,0xFFCAB1,0x4C,0x01A001},
{0x48,0x006148,0x4D,0xFE3FFF},
{0x48,0x00F7DF,0x4D,0xFEDFFF},
{0x48,0x018E76,0x4D,0xFF8000},
{0x49,0xFE250A,0x4D,0x002000},
{0x49,0xFEBBA1,0x4D,0x00C001},
{0x49,0xFF5238,0x4D,0x016001},
{0x49,0xFFE8CF,0x4E,0xFDFFFE}
};
const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
0,0,0,0,0,0,1,1,2,2, // -19dBm to -10dBm (clamp low at -14dB)
3,3,4,6,7,9,10,12,13,15, // -9dBm to 0dBm
17,19,20,20,20,20,20,20,20,20}; // +1dBm to +10 dBm (clamp high at +3dB)
17,19,20,20,20,20,20,20,20,20
}; // +1dBm to +10 dBm (clamp high at +3dB)
#endif
#ifdef REVA
const uint32_t rfLut[16][4] = {{0x57,0xFF5D2F,0x51,0x018001},
{0x57,0x0007DA,0x52,0xFE1FFF},
{0x57,0x00B285,0x52,0xFEBFFF},
{0x57,0x015D30,0x52,0xFF6000},
{0x58,0xFE07D8,0x52,0x000000},
{0x58,0xFEB283,0x52,0x00A000},
{0x58,0xFF5D2F,0x52,0x014001},
{0x58,0x0007DA,0x52,0x01E001},
{0x58,0x00B285,0x53,0xFE7FFF},
{0x58,0x015D30,0x53,0xFF1FFF},
{0x59,0xFE07D8,0x53,0xFFC000},
{0x59,0xFEB283,0x53,0x006000},
{0x59,0xFF5D2F,0x53,0x010001},
{0x59,0x0007DA,0x53,0x01A001},
{0x59,0x00B285,0x53,0xFE3FFF},
{0x59,0x015D30,0x53,0xFEDFFF}};
{0x57,0x0007DA,0x52,0xFE1FFF},
{0x57,0x00B285,0x52,0xFEBFFF},
{0x57,0x015D30,0x52,0xFF6000},
{0x58,0xFE07D8,0x52,0x000000},
{0x58,0xFEB283,0x52,0x00A000},
{0x58,0xFF5D2F,0x52,0x014001},
{0x58,0x0007DA,0x52,0x01E001},
{0x58,0x00B285,0x53,0xFE7FFF},
{0x58,0x015D30,0x53,0xFF1FFF},
{0x59,0xFE07D8,0x53,0xFFC000},
{0x59,0xFEB283,0x53,0x006000},
{0x59,0xFF5D2F,0x53,0x010001},
{0x59,0x0007DA,0x53,0x01A001},
{0x59,0x00B285,0x53,0xFE3FFF},
{0x59,0x015D30,0x53,0xFEDFFF}
};
const uint8_t txPowerLut[43] = {1,2,3, // -32dBm to -30dBm
4,5,5,5,5,5,5,5,5,5, // -29dBm to -20dBm (clamp at -28dB)
5,5,5,5,5,5,5,5,5,5, // -19dBm to -10dBm
5,5,5,5,5,5,5,5,5,5, // -9dBm to 0dBm
5,5,5,5,5,5,5,5,5,5}; // +1dBm to +10 dBm
5,5,5,5,5,5,5,5,5,5
}; // +1dBm to +10 dBm
#endif
/*************************************************************************************************
@ -187,7 +194,8 @@ const uint8_t txPowerLut[43] = {1,2,3, // -32dBm to -30dBm
* *
*************************************************************************************************/
void fRfAnaInit() {
void fRfAnaInit()
{
// Enable rfana clock
CLOCK_ENABLE(CLOCK_RFANA);
@ -207,70 +215,71 @@ void fRfAnaInit() {
RFANAREG->RX_CONTROL.BITS.ADC_DITHER_MODE = 0x0; // Dither mode disabled
}
boolean fRfAnaIoctl (uint32_t request, void *argument) {
boolean fRfAnaIoctl (uint32_t request, void *argument)
{
uint8_t channel, txPower;
// Enable rfana clock (in case fRfAnaIoctl is used before call of fRfAnaInit)
CLOCK_ENABLE(CLOCK_RFANA);
switch(request) {
case SET_RF_CHANNEL:
channel = *(uint8_t*)argument;
case SET_RF_CHANNEL:
channel = *(uint8_t*)argument;
// Set tx/rx integer/fractional divide portions
RFANAREG->TX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][3];
RFANAREG->TX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][2];
RFANAREG->RX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][1];
RFANAREG->RX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][0];
// Set tx/rx integer/fractional divide portions
RFANAREG->TX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][3];
RFANAREG->TX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][2];
RFANAREG->RX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][1];
RFANAREG->RX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][0];
// Set tx/rx vco trims
// Set tx/rx vco trims
#ifdef REVB
/** REVB is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
* from trims stored in flash A, it has the drawback that it is not workable when flash A is not accessible.*/
if (channel < 19) {
RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (TRIMREG->TX_VCO_LUT1.WORD) >> ((channel - 11) * 4);
RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (TRIMREG->RX_VCO_LUT1.WORD) >> ((channel - 11) * 4);
} else {
RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (TRIMREG->TX_VCO_LUT2.WORD) >> ((channel - 19) * 4);
RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (TRIMREG->RX_VCO_LUT2.WORD) >> ((channel - 19) * 4);
}
/** REVB is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
* from trims stored in flash A, it has the drawback that it is not workable when flash A is not accessible.*/
if (channel < 19) {
RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (TRIMREG->TX_VCO_LUT1.WORD) >> ((channel - 11) * 4);
RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (TRIMREG->RX_VCO_LUT1.WORD) >> ((channel - 11) * 4);
} else {
RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (TRIMREG->TX_VCO_LUT2.WORD) >> ((channel - 19) * 4);
RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (TRIMREG->RX_VCO_LUT2.WORD) >> ((channel - 19) * 4);
}
#endif /* REVB */
#ifdef REVC
/** REVC is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
* from trims stored in dedicated registers available in digital.*/
if (channel < 19) {
RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
} else {
RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
}
/** REVC is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
* from trims stored in dedicated registers available in digital.*/
if (channel < 19) {
RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
} else {
RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
}
#endif /* REVC */
#ifdef REVD
/** REVD is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
* from trims stored in dedicated registers available in digital.*/
if (channel < 19) {
RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
} else {
RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
}
/** REVD is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
* from trims stored in dedicated registers available in digital.*/
if (channel < 19) {
RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
} else {
RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
}
#endif /* REVD */
break;
case SET_TX_POWER:
txPower = *(uint8_t*)argument;
break;
case SET_TX_POWER:
txPower = *(uint8_t*)argument;
// Set tx power register
if ((txPower & 0x20) == 0) {
RFANAREG->TX_POWER = (txPowerLut[txPower + 32] & 0xFF);
} else {
RFANAREG->TX_POWER = (txPowerLut[txPower - 32] & 0xFF);
}
// Set tx power register
if ((txPower & 0x20) == 0) {
RFANAREG->TX_POWER = (txPowerLut[txPower + 32] & 0xFF);
} else {
RFANAREG->TX_POWER = (txPowerLut[txPower - 32] & 0xFF);
}
break;
default:
return False;
break;
default:
return False;
}
return True;
}

100
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h
View File

@ -45,60 +45,60 @@
/** rfAna register map (control part) */
typedef struct {
union {
struct {
__IO uint32_t FRACT_WORD:24;
__IO uint32_t INT_WORD:8;
} BITS;
__IO uint32_t WORD;
} TX_LO_CONTROL;
union {
struct {
__IO uint32_t FRACT_WORD:24;
__IO uint32_t INT_WORD:8;
} BITS;
__IO uint32_t WORD;
} RX_LO_CONTROL;
union {
struct {
__IO uint32_t PLL_RESET_TIME:10;
__I uint32_t RESERVED:6;
__IO uint32_t PLL_LOCK_TIME:10;
} BITS;
__IO uint32_t WORD;
} PLL_TIMING;
union {
struct {
__IO uint32_t LNA_GAIN_MODE:1;
__IO uint32_t ADC_DITHER_MODE:1;
} BITS;
__IO uint32_t WORD;
} RX_CONTROL;
__IO uint32_t TX_POWER;
__I uint32_t RECEIVER_GAIN;
union {
struct {
__IO uint32_t FRACT_WORD:24;
__IO uint32_t INT_WORD:8;
} BITS;
__IO uint32_t WORD;
} TX_LO_CONTROL;
union {
struct {
__IO uint32_t FRACT_WORD:24;
__IO uint32_t INT_WORD:8;
} BITS;
__IO uint32_t WORD;
} RX_LO_CONTROL;
union {
struct {
__IO uint32_t PLL_RESET_TIME:10;
__I uint32_t RESERVED:6;
__IO uint32_t PLL_LOCK_TIME:10;
} BITS;
__IO uint32_t WORD;
} PLL_TIMING;
union {
struct {
__IO uint32_t LNA_GAIN_MODE:1;
__IO uint32_t ADC_DITHER_MODE:1;
} BITS;
__IO uint32_t WORD;
} RX_CONTROL;
__IO uint32_t TX_POWER;
__I uint32_t RECEIVER_GAIN;
} RfAnaReg_t, *RfAnaReg_pt;
/** rfAna register map (trimming part) */
typedef struct {
__IO uint32_t PMU_TRIM;
__IO uint32_t RESERVED;
__IO uint32_t RX_CHAIN_TRIM;
union {
struct {
__I uint32_t BIAS_VCO_TRIM:4;
__I uint32_t MODULATION_TRIM:4;
__IO uint32_t TX_VCO_TRIM:4;
__IO uint32_t RX_VCO_TRIM:4;
__I uint32_t DIV_TRIM:3;
__I uint32_t REG_TRIM:2;
__I uint32_t LFR_TRIM:3;
__I uint32_t PAD0:4;
__I uint32_t CHARGE_PUMP_RANGE:4;
} BITS;
__IO uint32_t WORD;
} PLL_TRIM;
__IO uint32_t PLL_VCO_TAP_LOCATION;
__IO uint32_t TX_CHAIN_TRIM;
__IO uint32_t PMU_TRIM;
__IO uint32_t RESERVED;
__IO uint32_t RX_CHAIN_TRIM;
union {
struct {
__I uint32_t BIAS_VCO_TRIM:4;
__I uint32_t MODULATION_TRIM:4;
__IO uint32_t TX_VCO_TRIM:4;
__IO uint32_t RX_VCO_TRIM:4;
__I uint32_t DIV_TRIM:3;
__I uint32_t REG_TRIM:2;
__I uint32_t LFR_TRIM:3;
__I uint32_t PAD0:4;
__I uint32_t CHARGE_PUMP_RANGE:4;
} BITS;
__IO uint32_t WORD;
} PLL_TRIM;
__IO uint32_t PLL_VCO_TAP_LOCATION;
__IO uint32_t TX_CHAIN_TRIM;
#ifdef REVC
__IO uint32_t RX_VCO_TRIM_LUT2; /** 0x40019098 */
__IO uint32_t RX_VCO_TRIM_LUT1; /** 0x4001909C */

315
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc.c
View File

@ -44,242 +44,233 @@ static uint64_t LastRtcTimeus;
/* See rtc.h for details */
void fRtcInit(void)
{
CLOCK_ENABLE(CLOCK_RTC); /* enable rtc peripheral */
CLOCKREG->CCR.BITS.RTCEN = True; /* Enable RTC clock 32K */
CLOCK_ENABLE(CLOCK_RTC); /* enable rtc peripheral */
CLOCKREG->CCR.BITS.RTCEN = True; /* Enable RTC clock 32K */
/* Reset RTC control register */
RTCREG->CONTROL.WORD = False;
/* Reset RTC control register */
RTCREG->CONTROL.WORD = False;
/* Initialize all counters */
RTCREG->SECOND_COUNTER = False;
RTCREG->SUB_SECOND_COUNTER = False;
RTCREG->SECOND_ALARM = False;
RTCREG->SUB_SECOND_ALARM = False;
LastRtcTimeus = 0;
/* Initialize all counters */
RTCREG->SECOND_COUNTER = False;
RTCREG->SUB_SECOND_COUNTER = False;
RTCREG->SECOND_ALARM = False;
RTCREG->SUB_SECOND_ALARM = False;
LastRtcTimeus = 0;
/* Reset RTC Status register */
RTCREG->STATUS.WORD = False;
/* Reset RTC Status register */
RTCREG->STATUS.WORD = False;
/* Clear interrupt status */
RTCREG->INT_CLEAR.WORD = False;
/* Clear interrupt status */
RTCREG->INT_CLEAR.WORD = False;
/* Start sec & sub_sec counter */
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);/* Wait previous write to complete */
RTCREG->CONTROL.WORD |= ((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
(True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
/* Start sec & sub_sec counter */
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);/* Wait previous write to complete */
RTCREG->CONTROL.WORD |= ((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
(True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
/* enable interruption associated with the rtc at NVIC level */
NVIC_SetVector(Rtc_IRQn,(uint32_t)fRtcHandler); /* TODO define lp_ticker_isr */
NVIC_ClearPendingIRQ(Rtc_IRQn);
NVIC_EnableIRQ(Rtc_IRQn);
/* enable interruption associated with the rtc at NVIC level */
NVIC_SetVector(Rtc_IRQn,(uint32_t)fRtcHandler); /* TODO define lp_ticker_isr */
NVIC_ClearPendingIRQ(Rtc_IRQn);
NVIC_EnableIRQ(Rtc_IRQn);
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
return;
return;
}
/* See rtc.h for details */
void fRtcFree(void)
{
/* Reset RTC control register */
RTCREG->CONTROL.WORD = False;
/* Reset RTC control register */
RTCREG->CONTROL.WORD = False;
/* disable interruption associated with the rtc */
NVIC_DisableIRQ(Rtc_IRQn);
/* disable interruption associated with the rtc */
NVIC_DisableIRQ(Rtc_IRQn);
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
}
/* See rtc.h for details */
void fRtcSetInterrupt(uint32_t timestamp)
{
SubSecond = False;
uint32_t Second = False;
uint8_t DividerAdjust = 1;
SubSecond = False;
uint32_t Second = False;
uint8_t DividerAdjust = 1;
if(timestamp)
{
if(timestamp >= RTC_SEC_TO_US)
{/* TimeStamp is big enough to set second alarm */
Second = ((timestamp / RTC_SEC_TO_US) & RTC_SEC_MASK); /* Convert micro second to second */
RTCREG->SECOND_ALARM = Second; /* Write to alarm register */
if(timestamp) {
if(timestamp >= RTC_SEC_TO_US) {
/* TimeStamp is big enough to set second alarm */
Second = ((timestamp / RTC_SEC_TO_US) & RTC_SEC_MASK); /* Convert micro second to second */
RTCREG->SECOND_ALARM = Second; /* Write to alarm register */
/* Enable second interrupt */
RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
}
timestamp = timestamp - Second * RTC_SEC_TO_US; /* Take out micro second for sub second alarm */
if(timestamp > False)
{/* We have some thing for sub second */
/* Enable second interrupt */
RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
}
timestamp = timestamp - Second * RTC_SEC_TO_US; /* Take out micro second for sub second alarm */
if(timestamp > False) {
/* We have some thing for sub second */
/* Convert micro second to sub_seconds(each count = 30.5 us) */
if(timestamp > 131000)
{
DividerAdjust = 100;
}
/* Convert micro second to sub_seconds(each count = 30.5 us) */
if(timestamp > 131000) {
DividerAdjust = 100;
}
volatile uint64_t Temp = (timestamp / DividerAdjust * RTC_CLOCK_HZ);
timestamp = (uint64_t)(Temp / RTC_SEC_TO_US * DividerAdjust);
SubSecond = Temp & RTC_SUB_SEC_MASK;
volatile uint64_t Temp = (timestamp / DividerAdjust * RTC_CLOCK_HZ);
timestamp = (uint64_t)(Temp / RTC_SEC_TO_US * DividerAdjust);
SubSecond = Temp & RTC_SUB_SEC_MASK;
if(SubSecond <= 5)
{
SubSecond = 0;
}
if(SubSecond <= 5) {
SubSecond = 0;
}
if(SubSecond > False)
{ /* Second interrupt not enabled */
if(SubSecond > False) {
/* Second interrupt not enabled */
/* Set SUB SEC_ALARM */
RTCREG->SUB_SECOND_ALARM = SubSecond; /* Write to sub second alarm */
/* Set SUB SEC_ALARM */
RTCREG->SUB_SECOND_ALARM = SubSecond; /* Write to sub second alarm */
/* Enable sub second interrupt */
RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
}
}
/* Enable sub second interrupt */
RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
}
}
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
}
return;
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
}
return;
}
/* See rtc.h for details */
void fRtcDisableInterrupt(void)
{
/* Disable subsec/sec interrupt */
RTCREG->CONTROL.WORD &= ~((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
/* Disable subsec/sec interrupt */
RTCREG->CONTROL.WORD &= ~((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
}
/* See rtc.h for details */
void fRtcEnableInterrupt(void)
{
/* Disable subsec/sec interrupt */
RTCREG->CONTROL.WORD |= ((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
/* Disable subsec/sec interrupt */
RTCREG->CONTROL.WORD |= ((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
}
/* See rtc.h for details */
void fRtcClearInterrupt(void)
{
/* Disable subsec/sec interrupt */
/* Clear sec & sub_sec interrupts */
RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
(True << RTC_INT_CLR_SEC_BIT_POS));
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
/* Disable subsec/sec interrupt */
/* Clear sec & sub_sec interrupts */
RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
(True << RTC_INT_CLR_SEC_BIT_POS));
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
}
/* See rtc.h for details */
uint64_t fRtcRead(void)
{
uint32_t Second;
uint16_t SubSecond;
uint32_t Second;
uint16_t SubSecond;
/* Hardware Bug fix: The rollover of the sub-second counter initiates the increment of the second counter.
* That means there is one cycle where the sub-second has rolled back to zero and the second counter has not incremented
* and a read during that cycle will be incorrect. That will occur for one RTC cycle and that is about 31us of exposure.
* If you read a zero in the sub-second counter then increment the second counter by 1.
* Alternatively, subtract 1 from the Sub-seconds counter to align the Second and Sub-Second rollover.
*/
/* Hardware Bug fix: The rollover of the sub-second counter initiates the increment of the second counter.
* That means there is one cycle where the sub-second has rolled back to zero and the second counter has not incremented
* and a read during that cycle will be incorrect. That will occur for one RTC cycle and that is about 31us of exposure.
* If you read a zero in the sub-second counter then increment the second counter by 1.
* Alternatively, subtract 1 from the Sub-seconds counter to align the Second and Sub-Second rollover.
*/
/* Read the Second and Sub-second counters, then read the Second counter again.
* If it changed, then the Second rolled over while reading Sub-seconds, so go back and read them both again.
*/
/* Read the Second and Sub-second counters, then read the Second counter again.
* If it changed, then the Second rolled over while reading Sub-seconds, so go back and read them both again.
*/
do
{
Second = RTCREG->SECOND_COUNTER; /* Get SEC_COUNTER reg value */
SubSecond = (RTCREG->SUB_SECOND_COUNTER - 1) & 0x7FFF; /* Get SUB_SEC_COUNTER reg value */
}while (Second != RTCREG->SECOND_COUNTER); /* Repeat if the second has changed */
do {
Second = RTCREG->SECOND_COUNTER; /* Get SEC_COUNTER reg value */
SubSecond = (RTCREG->SUB_SECOND_COUNTER - 1) & 0x7FFF; /* Get SUB_SEC_COUNTER reg value */
} while (Second != RTCREG->SECOND_COUNTER); /* Repeat if the second has changed */
//note: casting to float removed to avoid reduction in resolution
uint64_t RtcTimeus = ((uint64_t)SubSecond * RTC_SEC_TO_US / RTC_CLOCK_HZ) + ((uint64_t)Second * RTC_SEC_TO_US);
//note: casting to float removed to avoid reduction in resolution
uint64_t RtcTimeus = ((uint64_t)SubSecond * RTC_SEC_TO_US / RTC_CLOCK_HZ) + ((uint64_t)Second * RTC_SEC_TO_US);
/*check that the time did not go backwards */
MBED_ASSERT(RtcTimeus >= LastRtcTimeus);
LastRtcTimeus = RtcTimeus;
/*check that the time did not go backwards */
MBED_ASSERT(RtcTimeus >= LastRtcTimeus);
LastRtcTimeus = RtcTimeus;
return RtcTimeus;
return RtcTimeus;
}
/* See rtc.h for details */
void fRtcWrite(uint64_t RtcTimeus)
{
uint32_t Second = 0;
uint16_t SubSecond = 0;
/* Stop RTC */
RTCREG->CONTROL.WORD &= ~((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
(True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
uint32_t Second = 0;
uint16_t SubSecond = 0;
/* Stop RTC */
RTCREG->CONTROL.WORD &= ~((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
(True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
if(RtcTimeus > RTC_SEC_TO_US)
{/* TimeStamp is big enough to set second counter */
Second = ((RtcTimeus / RTC_SEC_TO_US) & RTC_SEC_MASK);
}
RTCREG->SECOND_COUNTER = Second;
RtcTimeus = RtcTimeus - (Second * RTC_SEC_TO_US);
if(RtcTimeus > False)
{
/* Convert TimeStamp to sub_seconds */
SubSecond = (uint16_t)((float)(RtcTimeus * RTC_CLOCK_HZ / RTC_SEC_TO_US)) & RTC_SUB_SEC_MASK;
}
/* Set SUB_SEC_ALARM */
RTCREG->SUB_SECOND_COUNTER = SubSecond;
if(RtcTimeus > RTC_SEC_TO_US) {
/* TimeStamp is big enough to set second counter */
Second = ((RtcTimeus / RTC_SEC_TO_US) & RTC_SEC_MASK);
}
RTCREG->SECOND_COUNTER = Second;
RtcTimeus = RtcTimeus - (Second * RTC_SEC_TO_US);
if(RtcTimeus > False) {
/* Convert TimeStamp to sub_seconds */
SubSecond = (uint16_t)((float)(RtcTimeus * RTC_CLOCK_HZ / RTC_SEC_TO_US)) & RTC_SUB_SEC_MASK;
}
/* Set SUB_SEC_ALARM */
RTCREG->SUB_SECOND_COUNTER = SubSecond;
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
/* Start RTC */
RTCREG->CONTROL.WORD |= ((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
(True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
/* Start RTC */
RTCREG->CONTROL.WORD |= ((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
(True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
}
/* See rtc.h for details */
void fRtcHandler(void)
{/* SUB_SECOND/SECOND interrupt occured */
volatile uint32_t TempStatus = RTCREG->STATUS.WORD;
{
/* SUB_SECOND/SECOND interrupt occured */
volatile uint32_t TempStatus = RTCREG->STATUS.WORD;
/* disable all interrupts */
RTCREG->CONTROL.WORD &= ~((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
/* disable all interrupts */
RTCREG->CONTROL.WORD &= ~((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
/* Clear sec & sub_sec interrupts */
RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
(True << RTC_INT_CLR_SEC_BIT_POS));
/* Clear sec & sub_sec interrupts */
RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
(True << RTC_INT_CLR_SEC_BIT_POS));
/* TODO ANDing SUB_SEC & SEC interrupt - work around for RTC issue - will be solved in REV G */
if(TempStatus & RTC_SEC_INT_STATUS_MASK)
{/* Second interrupt occured */
if(SubSecond > False)
{/* Set SUB SEC_ALARM */
RTCREG->SUB_SECOND_ALARM = SubSecond + RTCREG->SUB_SECOND_COUNTER;
/* Enable sub second interrupt */
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
}
else
{/* We reach here after second interrupt is occured */
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
(True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
}
}
else
{/* We reach here after sub_second or (Sub second + second) interrupt occured */
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
(True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
}
/* TODO ANDing SUB_SEC & SEC interrupt - work around for RTC issue - will be solved in REV G */
if(TempStatus & RTC_SEC_INT_STATUS_MASK) {
/* Second interrupt occured */
if(SubSecond > False) {
/* Set SUB SEC_ALARM */
RTCREG->SUB_SECOND_ALARM = SubSecond + RTCREG->SUB_SECOND_COUNTER;
/* Enable sub second interrupt */
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
} else {
/* We reach here after second interrupt is occured */
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
(True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
}
} else {
/* We reach here after sub_second or (Sub second + second) interrupt occured */
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
(True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
}
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
}
boolean fIsRtcEnabled(void)
{
if(RTCREG->CONTROL.BITS.SUB_SEC_COUNTER_EN | RTCREG->CONTROL.BITS.SEC_COUNTER_EN)
{
return True;
}
else
{
return False;
}
if(RTCREG->CONTROL.BITS.SUB_SEC_COUNTER_EN | RTCREG->CONTROL.BITS.SEC_COUNTER_EN) {
return True;
} else {
return False;
}
}

4
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc.h
View File

@ -46,7 +46,7 @@
#define RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS 2
#define RTC_CONTROL_SEC_CNT_INT_BIT_POS 3
#define RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS 9
#define RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS 9
#define RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS 10
/* FUnction pointer for call back */
@ -135,7 +135,7 @@ void fRtcHandler(void);
/**
* @details
* Is RTC enabled?
* Is RTC enabled?
*
* @param None
* @return RTC status

10
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc_api.c
View File

@ -23,7 +23,7 @@
*/
#include "rtc_api.h"
#if DEVICE_RTC
#include "device.h"
#include "device.h"
#include "cmsis.h"
#include "pinmap.h"
@ -39,7 +39,7 @@ static IRQn_Type Irq;
void rtc_init(void)
{
fRtcInit();
fRtcInit();
}
/* See rtc_apc.h for description */
@ -51,19 +51,19 @@ void rtc_free(void)
/* See rtc_apc.h for description */
int rtc_isenabled(void)
{
return(fIsRtcEnabled());
return(fIsRtcEnabled());
}
/* See rtc_apc.h for description */
time_t rtc_read(void)
{
return (uint32_t)(fRtcRead() & 0xFFFFFFFF); /* TODO Truncating 64 bit value to 32 bit */
return (uint32_t)(fRtcRead() & 0xFFFFFFFF); /* TODO Truncating 64 bit value to 32 bit */
}
/* See rtc_apc.h for description */
void rtc_write(time_t t)
{
fRtcWrite(t);
fRtcWrite(t);
}
#endif /* DEVICE_RTC */

204
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h
View File

@ -3,7 +3,7 @@
* @file rtc_map.h
* @brief Real Time Clock HW register map
* @internal
* @author Mehul shah
* @author ON Semiconductor.
* $Rev: 3008 $
* $Date: 2014-10-16 18:42:48 +0530 (Thu, 16 Oct 2014) $
******************************************************************************
@ -39,116 +39,110 @@
/** Real Time Clock Control HW Structure Overlay */
typedef struct {
#ifdef REVB
/*REVD REPLACE COMPLETE MAP WITH DATA FROM DIG DESIGN SPEC */
__IO uint32_t SECOND;/**<SECOND Counter */
__IO uint32_t MINUTE;/**<DAY Counter */
__IO uint32_t HOUR;/**< HOUR Counter */
__IO uint32_t DAY;/**< DAY Counter */
__IO uint32_t MONTH;/**< MONTH Counter */
__IO uint32_t YEAR;/**< YEAR Counter */
union {
struct {
__IO uint32_t PAD1 :1;/**<Reserved; Writes have no effect. Read as 0 */
__IO uint32_t TEST_MINUTE :1;/**<0 = normal operation , 1 = Test Mode */
__IO uint32_t TEST_HOUR :1;/**<0 = normal operation , 1 = Test Mode */
__IO uint32_t TEST_DAY :1;/**<0 = normal operation , 1 = Test Mode */
__IO uint32_t TEST_MONTH :1;/**<0 = normal operation , 1 = Test Mode */
__IO uint32_t TEST_YEAR :1;/**<0 = normal operation , 1 = Test Mode */
__IO uint32_t PAD2 :1;/**<Reserved; Writes have no effect. Read as 0 */
__IO uint32_t RESET :1;/**< 0 = counters are incrementing , 1 = counters are in reset */
} BITS;
__IO uint32_t WORD;
} CONTROL;
__IO uint32_t DIVISOR;/**<Clock Divisor value */
__IO uint32_t ALARM_SECOND;/**<SECOND Alarm's BCD value */
__IO uint32_t ALARM_MINUTE;/**<MINUTE Alarm's BCD value */
__IO uint32_t ALARM_HOUR;/**<HOUR Alarm's BCD value*/
__IO uint32_t ALARM_DAY;/**<DAY Alarm's BCD value */
__IO uint32_t ALARM_MONTH;/**<MONTH Alarm's BCD value */
__IO uint32_t ALARM_YEAR;/**<YEAR Alarm's BCD value */
union {
struct {
__IO uint32_t SECOND :1;/**<SECOND Alarm interrupt : 0 = disabled, 1 = enabled */
__IO uint32_t MINUTE :1;/**<MINUTE Alarm interrupt : 0 = disabled, 1 = enabled */
__IO uint32_t HOUR :1;/**<HOUR Alarm interrupt : 0 = disabled, 1 = enabled */
__IO uint32_t DAY :1;/**<DAY Alarm interrupt : 0 = disabled, 1 = enabled */
__IO uint32_t MONTH :1;/**<MONTH Alarm interrupt : 0 = disabled, 1 = enabled */
__IO uint32_t YEAR :1;/**<YEAR Alarm interrupt : 0 = disabled, 1 = enabled */
__IO uint32_t PAD :2 ;/**<Writes have no effect; Read as 2’b00 */
} BITS;
__IO uint32_t WORD;
} INT_EN_CONTROL;
union {
struct {
__I uint32_t SECOND :1;/**<SECOND Alarm interrupt : 0= inactive , 1 = active */
__I uint32_t MINUTE :1;/**<MINUTE Alarm interrupt : 0= inactive , 1 = active */
__I uint32_t HOUR :1;/**<HOUR Alarm interrupt : 0= inactive , 1 = active */
__I uint32_t DAY :1;/**<DAY Alarm interrupt : 0= inactive , 1 = active */
__I uint32_t MONTH :1;/**<MONTH Alarm interrupt : 0= inactive , 1 = active */
__I uint32_t YEAR :1;/**<YEAR Alarm interrupt : 0= inactive , 1 = active */
__I uint32_t PAD :2; /**<Read as 00 */
} BITS;
__I uint32_t WORD;
} INT_STATUS;
union {
struct {
__O uint32_t SECOND :1;/**<Write 1 to clear the SECOND Alarm interrupt.*/
__O uint32_t MINUTE :1;/**<Write 1 to clear the MINUTE Alarm interrupt*/
__O uint32_t HOUR :1;/**<Write 1 to clear the HOUR Alarm interrupt*/
__O uint32_t DAY :1;/**< Write 1 to clear the DAY Alarm interrupt*/
__O uint32_t MONTH :1;/**<Write 1 to clear the MONTH Alarm interrupt */
__O uint32_t YEAR :1;/**< Write 1 to clear the YEAR Alarm interrupt*/
__O uint32_t PAD :2 ;/**< Writes have no effect. */
} BITS;
__O uint32_t WORD;
} INT_CLEAR;
#ifdef REVB
/*REVD REPLACE COMPLETE MAP WITH DATA FROM DIG DESIGN SPEC */
__IO uint32_t SECOND;/**<SECOND Counter */
__IO uint32_t MINUTE;/**<DAY Counter */
__IO uint32_t HOUR;/**< HOUR Counter */
__IO uint32_t DAY;/**< DAY Counter */
__IO uint32_t MONTH;/**< MONTH Counter */
__IO uint32_t YEAR;/**< YEAR Counter */
union {
struct {
__IO uint32_t PAD1 :1;/**<Reserved; Writes have no effect. Read as 0 */
__IO uint32_t TEST_MINUTE :1;/**<0 = normal operation , 1 = Test Mode */
__IO uint32_t TEST_HOUR :1;/**<0 = normal operation , 1 = Test Mode */
__IO uint32_t TEST_DAY :1;/**<0 = normal operation , 1 = Test Mode */
__IO uint32_t TEST_MONTH :1;/**<0 = normal operation , 1 = Test Mode */
__IO uint32_t TEST_YEAR :1;/**<0 = normal operation , 1 = Test Mode */
__IO uint32_t PAD2 :1;/**<Reserved; Writes have no effect. Read as 0 */
__IO uint32_t RESET :1;/**< 0 = counters are incrementing , 1 = counters are in reset */
} BITS;
__IO uint32_t WORD;
} CONTROL;
__IO uint32_t DIVISOR;/**<Clock Divisor value */
__IO uint32_t ALARM_SECOND;/**<SECOND Alarm's BCD value */
__IO uint32_t ALARM_MINUTE;/**<MINUTE Alarm's BCD value */
__IO uint32_t ALARM_HOUR;/**<HOUR Alarm's BCD value*/
__IO uint32_t ALARM_DAY;/**<DAY Alarm's BCD value */
__IO uint32_t ALARM_MONTH;/**<MONTH Alarm's BCD value */
__IO uint32_t ALARM_YEAR;/**<YEAR Alarm's BCD value */
union {
struct {
__IO uint32_t SECOND :1;/**<SECOND Alarm interrupt : 0 = disabled, 1 = enabled */
__IO uint32_t MINUTE :1;/**<MINUTE Alarm interrupt : 0 = disabled, 1 = enabled */
__IO uint32_t HOUR :1;/**<HOUR Alarm interrupt : 0 = disabled, 1 = enabled */
__IO uint32_t DAY :1;/**<DAY Alarm interrupt : 0 = disabled, 1 = enabled */
__IO uint32_t MONTH :1;/**<MONTH Alarm interrupt : 0 = disabled, 1 = enabled */
__IO uint32_t YEAR :1;/**<YEAR Alarm interrupt : 0 = disabled, 1 = enabled */
__IO uint32_t PAD :2 ;/**<Writes have no effect; Read as 2’b00 */
} BITS;
__IO uint32_t WORD;
} INT_EN_CONTROL;
union {
struct {
__I uint32_t SECOND :1;/**<SECOND Alarm interrupt : 0= inactive , 1 = active */
__I uint32_t MINUTE :1;/**<MINUTE Alarm interrupt : 0= inactive , 1 = active */
__I uint32_t HOUR :1;/**<HOUR Alarm interrupt : 0= inactive , 1 = active */
__I uint32_t DAY :1;/**<DAY Alarm interrupt : 0= inactive , 1 = active */
__I uint32_t MONTH :1;/**<MONTH Alarm interrupt : 0= inactive , 1 = active */
__I uint32_t YEAR :1;/**<YEAR Alarm interrupt : 0= inactive , 1 = active */
__I uint32_t PAD :2; /**<Read as 00 */
} BITS;
__I uint32_t WORD;
} INT_STATUS;
union {
struct {
__O uint32_t SECOND :1;/**<Write 1 to clear the SECOND Alarm interrupt.*/
__O uint32_t MINUTE :1;/**<Write 1 to clear the MINUTE Alarm interrupt*/
__O uint32_t HOUR :1;/**<Write 1 to clear the HOUR Alarm interrupt*/
__O uint32_t DAY :1;/**< Write 1 to clear the DAY Alarm interrupt*/
__O uint32_t MONTH :1;/**<Write 1 to clear the MONTH Alarm interrupt */
__O uint32_t YEAR :1;/**< Write 1 to clear the YEAR Alarm interrupt*/
__O uint32_t PAD :2 ;/**< Writes have no effect. */
} BITS;
__O uint32_t WORD;
} INT_CLEAR;
#endif /* REVB */
#ifdef REVD
#ifdef REVD
__IO uint32_t SUB_SECOND_COUNTER; /**<SUB SECOND Counter */ /* 0x4000F000 */
__IO uint32_t SECOND_COUNTER; /**<SECOND Counter */ /* 0x4000F004 */
__IO uint32_t SUB_SECOND_ALARM; /**< SUB SECOND alarm */ /* 0x4000F008 */
__IO uint32_t SECOND_ALARM; /**< SECOND alarm */ /* 0x4000F00c */
union
{
struct
{
__IO uint32_t SUB_SEC_COUNTER_EN :1; /**<Sub-second counter enable. (1=count is enabled, 0=retain count value) */
__IO uint32_t SEC_COUNTER_EN :1; /**<Second counter enable. (1=count is enabled, 0=retain count value) */
__IO uint32_t SUB_SECOND_INT_EN :1; /**<Sub-second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
__IO uint32_t SECOND_INT_EN :1; /**<Second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
}BITS;
__IO uint32_t WORD;
}CONTROL; /* 0x4000F010 */
union
{
struct
{
/**<Any write to the status register will clear the error bit. */
__IO uint32_t SUB_SECOND_INT:1; /**<Sub-second interrupt status. (1=interrupt active, 0=no interrupt)*/
__IO uint32_t SECOND_INT :1; /**<Second interrupt status. (1=interrupt active, 0=no interrupt)*/
__IO uint32_t WRITE_ERROR :1; /**<Reads error bit which is set when a write occurs before a previous write to the same register has completed. */
__IO uint32_t BSY_ANY_WRT :1; /**<Busy with any write.*/
__IO uint32_t BSY_SUB_SEC_CNTR_REG_WRT :1; /**<Busy with a sub-second counter register write.*/
__IO uint32_t BSY_SEC_CNTR_REG_WRT :1; /**<Busy with a second counter register write.*/
__IO uint32_t BSY_SUB_SEC_ALRM_REG_WRT :1; /**<Busy with a sub-second alarm register write.*/
__IO uint32_t BSY_SEC_ALRM_REG_WRT:1; /**<Busy with a second alarm register write.*/
__IO uint32_t BSY_CTRL_REG_WRT :1; /**<Busy with a control register write.*/
__IO uint32_t BSY_SUB_SEC_INT_CLR_WRT :1; /**<Busy with a sub-second interrupt clear write.*/
__IO uint32_t BSY_SEC_INT_CLR_WRT :1; /**<Busy with a second interrupt clear write.*/
}BITS;
union {
struct {
__IO uint32_t SUB_SEC_COUNTER_EN :1; /**<Sub-second counter enable. (1=count is enabled, 0=retain count value) */
__IO uint32_t SEC_COUNTER_EN :1; /**<Second counter enable. (1=count is enabled, 0=retain count value) */
__IO uint32_t SUB_SECOND_INT_EN :1; /**<Sub-second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
__IO uint32_t SECOND_INT_EN :1; /**<Second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
} BITS;
__IO uint32_t WORD;
}STATUS; /* 0x4000F014 */
union
{
struct
{
__O uint32_t SUB_SECOND :1; /**<Write 1 to this register to clear the sub-second interrupt.*/
__O uint32_t SECOND :1; /**<Write 1 to this register to clear the second interrupt.*/
}BITS;
__O uint32_t WORD;
}INT_CLEAR; /* 0x4000F018 */
#endif /* REVD */
} CONTROL; /* 0x4000F010 */
union {
struct {
/**<Any write to the status register will clear the error bit. */
__IO uint32_t SUB_SECOND_INT:1; /**<Sub-second interrupt status. (1=interrupt active, 0=no interrupt)*/
__IO uint32_t SECOND_INT :1; /**<Second interrupt status. (1=interrupt active, 0=no interrupt)*/
__IO uint32_t WRITE_ERROR :1; /**<Reads error bit which is set when a write occurs before a previous write to the same register has completed. */
__IO uint32_t BSY_ANY_WRT :1; /**<Busy with any write.*/
__IO uint32_t BSY_SUB_SEC_CNTR_REG_WRT :1; /**<Busy with a sub-second counter register write.*/
__IO uint32_t BSY_SEC_CNTR_REG_WRT :1; /**<Busy with a second counter register write.*/
__IO uint32_t BSY_SUB_SEC_ALRM_REG_WRT :1; /**<Busy with a sub-second alarm register write.*/
__IO uint32_t BSY_SEC_ALRM_REG_WRT:1; /**<Busy with a second alarm register write.*/
__IO uint32_t BSY_CTRL_REG_WRT :1; /**<Busy with a control register write.*/
__IO uint32_t BSY_SUB_SEC_INT_CLR_WRT :1; /**<Busy with a sub-second interrupt clear write.*/
__IO uint32_t BSY_SEC_INT_CLR_WRT :1; /**<Busy with a second interrupt clear write.*/
} BITS;
__IO uint32_t WORD;
} STATUS; /* 0x4000F014 */
union {
struct {
__O uint32_t SUB_SECOND :1; /**<Write 1 to this register to clear the sub-second interrupt.*/
__O uint32_t SECOND :1; /**<Write 1 to this register to clear the second interrupt.*/
} BITS;
__O uint32_t WORD;
} INT_CLEAR; /* 0x4000F018 */
#endif /* REVD */
} RtcReg_t, *RtcReg_pt;
#endif /* RTC_MAP_H_ */

354
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/serial_api.c
View File

@ -59,86 +59,83 @@ static inline void uart_irq(uint8_t status, uint32_t index);
void serial_init(serial_t *obj, PinName tx, PinName rx)
{
uint16_t clockDivisor;
uint16_t clockDivisor;
CrossbReg_t *CbRegOffSet;
PadReg_t *PadRegOffset;
CrossbReg_t *CbRegOffSet;
PadReg_t *PadRegOffset;
//find which peripheral is associated with the rx and tx pins
uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
//check if the peripherals for each pin are the same or not
//returns the enum associated with the peripheral
//in the case of this target, the enum is the base address of the peripheral
obj->UARTREG = (Uart16C550Reg_pt) pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT(obj->UARTREG != (Uart16C550Reg_pt) NC);
//find which peripheral is associated with the rx and tx pins
uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
//check if the peripherals for each pin are the same or not
//returns the enum associated with the peripheral
//in the case of this target, the enum is the base address of the peripheral
obj->UARTREG = (Uart16C550Reg_pt) pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT(obj->UARTREG != (Uart16C550Reg_pt) NC);
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
/*TODO: Mac Lobdell - we should recommend using the instance method and not using base addresses as index */
/*TODO: Mac Lobdell - we should recommend using the instance method and not using base addresses as index */
if (obj->UARTREG == (Uart16C550Reg_pt)STDIO_UART) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
/*TODO: determine if pullups are needed/recommended */
/* if (tx != NC) {
pin_mode(tx, PullUp);
}
if (rx != NC) {
pin_mode(rx, PullUp);
}
*/
/* Configure IOs to UART using cross bar, pad and GPIO settings */
if (obj->UARTREG == (Uart16C550Reg_pt)STDIO_UART) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
/*TODO: determine if pullups are needed/recommended */
/* if (tx != NC) {
pin_mode(tx, PullUp);
}
if (rx != NC) {
pin_mode(rx, PullUp);
}
*/
/* Configure IOs to UART using cross bar, pad and GPIO settings */
if(obj->UARTREG == UART2REG)
{/* UART 2 */
CLOCK_ENABLE(CLOCK_UART2);
Irq = Uart2_IRQn;
}
else if(obj->UARTREG == UART1REG)
{ /* UART 1 */
CLOCK_ENABLE(CLOCK_UART1);
if(obj->UARTREG == UART2REG) {
/* UART 2 */
CLOCK_ENABLE(CLOCK_UART2);
Irq = Uart2_IRQn;
} else if(obj->UARTREG == UART1REG) {
/* UART 1 */
CLOCK_ENABLE(CLOCK_UART1);
Irq = Uart1_IRQn;
}
else
{
MBED_ASSERT(False);
}
Irq = Uart1_IRQn;
} else {
MBED_ASSERT(False);
}
CLOCK_ENABLE(CLOCK_GPIO);
CLOCK_ENABLE(CLOCK_CROSSB);
CLOCK_ENABLE(CLOCK_PAD);
CLOCK_ENABLE(CLOCK_GPIO);
CLOCK_ENABLE(CLOCK_CROSSB);
CLOCK_ENABLE(CLOCK_PAD);
/*TODO: determine if tx and rx are used correctly in this case - this depends on the pin enum matching the position in the crossbar*/
/*TODO: determine if tx and rx are used correctly in this case - this depends on the pin enum matching the position in the crossbar*/
/* Configure tx pin as UART */
CbRegOffSet = (CrossbReg_t*)(CROSSBREG_BASE + (tx * CROSS_REG_ADRS_BYTE_SIZE));
CbRegOffSet->DIOCTRL0 = CONFIGURE_AS_UART; /* tx pin as UART */
/* Configure tx pin as UART */
CbRegOffSet = (CrossbReg_t*)(CROSSBREG_BASE + (tx * CROSS_REG_ADRS_BYTE_SIZE));
CbRegOffSet->DIOCTRL0 = CONFIGURE_AS_UART; /* tx pin as UART */
/* Configure rx pin as UART */
CbRegOffSet = (CrossbReg_t*)(CROSSBREG_BASE + (rx * CROSS_REG_ADRS_BYTE_SIZE));
CbRegOffSet->DIOCTRL0 = CONFIGURE_AS_UART; /* rx pin as UART */
/* Configure rx pin as UART */
CbRegOffSet = (CrossbReg_t*)(CROSSBREG_BASE + (rx * CROSS_REG_ADRS_BYTE_SIZE));
CbRegOffSet->DIOCTRL0 = CONFIGURE_AS_UART; /* rx pin as UART */
/** - Set pad parameters, output drive strength, pull piece control, output drive type */
PadRegOffset = (PadReg_t*)(PADREG_BASE + (tx * PAD_REG_ADRS_BYTE_SIZE));
PadRegOffset->PADIO0.WORD = PAD_UART_TX; /* Pad setting for UART Tx */
/** - Set pad parameters, output drive strength, pull piece control, output drive type */
PadRegOffset = (PadReg_t*)(PADREG_BASE + (tx * PAD_REG_ADRS_BYTE_SIZE));
PadRegOffset->PADIO0.WORD = PAD_UART_TX; /* Pad setting for UART Tx */
PadRegOffset = (PadReg_t*)(PADREG_BASE + (rx * PAD_REG_ADRS_BYTE_SIZE));
PadRegOffset->PADIO0.WORD = PAD_UART_RX; /* Pad settings for UART Rx */
PadRegOffset = (PadReg_t*)(PADREG_BASE + (rx * PAD_REG_ADRS_BYTE_SIZE));
PadRegOffset->PADIO0.WORD = PAD_UART_RX; /* Pad settings for UART Rx */
GPIOREG->W_OUT |= (True << tx); /* tx as OUT direction */
GPIOREG->W_IN |= (True << rx); /* rx as IN directon */
GPIOREG->W_OUT |= (True << tx); /* tx as OUT direction */
GPIOREG->W_IN |= (True << rx); /* rx as IN directon */
CLOCK_DISABLE(CLOCK_PAD);
CLOCK_DISABLE(CLOCK_PAD);
CLOCK_DISABLE(CLOCK_CROSSB);
CLOCK_DISABLE(CLOCK_GPIO);
CLOCK_DISABLE(CLOCK_GPIO);
/* Set the divisor value. To do so, LCR[7] needs to be set to 1 in order to access the divisor registers.
* The right-shift of 4 is a division of 16, representing the oversampling rate. */
clockDivisor = (fClockGetPeriphClockfrequency() / UART_DEFAULT_BAUD) >> 4;
clockDivisor = (fClockGetPeriphClockfrequency() / UART_DEFAULT_BAUD) >> 4;
obj->UARTREG->LCR.WORD = 0x80;
obj->UARTREG->DLL = clockDivisor & 0xFF;
obj->UARTREG->DLM = clockDivisor >> 8;
@ -156,11 +153,10 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
* flow control state. */
obj->UARTREG->SCR = obj->UARTREG->MSR.WORD;
if((int)obj->UARTREG == STDIO_UART)
{
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
if((int)obj->UARTREG == STDIO_UART) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
NVIC_ClearPendingIRQ(Irq);
@ -180,14 +176,14 @@ void serial_free(serial_t *obj)
void serial_baud(serial_t *obj, int baudrate)
{
/* Set the divisor value. To do so, LCR[7] needs to be set to 1 in order to access the divisor registers.
/* Set the divisor value. To do so, LCR[7] needs to be set to 1 in order to access the divisor registers.
* The right-shift of 4 is a division of 16, representing the oversampling rate. */
uint16_t clockDivisor = (fClockGetPeriphClockfrequency() / baudrate) >> 4;
obj->UARTREG->LCR.BITS.DLAB = True;
obj->UARTREG->DLL = clockDivisor & 0xFF;
obj->UARTREG->DLM = clockDivisor >> 8;
obj->UARTREG->LCR.BITS.DLAB = False;
obj->UARTREG->LCR.BITS.DLAB = True;
obj->UARTREG->DLL = clockDivisor & 0xFF;
obj->UARTREG->DLM = clockDivisor >> 8;
obj->UARTREG->LCR.BITS.DLAB = False;
}
/*
@ -197,30 +193,24 @@ DataLen 00 – 5 bits; 01 – 6 bits; 10 – 7 bits; 11 – 8 bits
*/
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
if(data_bits >= 5 && data_bits <= 8 && parity <= 7 && stop_bits >= 1 && stop_bits <= 2)
{
if(parity == (SerialParity)0)
{
parity = (SerialParity)0;
}
else
{
parity = (SerialParity)(parity + parity - 1) ;
}
if(data_bits >= 5 && data_bits <= 8 && parity <= 7 && stop_bits >= 1 && stop_bits <= 2) {
if(parity == (SerialParity)0) {
parity = (SerialParity)0;
} else {
parity = (SerialParity)(parity + parity - 1) ;
}
obj->UARTREG->LCR.WORD |= ((((data_bits - 5) << UART_LCR_DATALEN_BIT_POS) |
(parity << UART_LCR_PARITY_BIT_POS) |
((stop_bits - 1) << UART_LCR_STPBIT_BIT_POS)) & 0x3F);
}
else
{
MBED_ASSERT(False);
}
obj->UARTREG->LCR.WORD |= ((((data_bits - 5) << UART_LCR_DATALEN_BIT_POS) |
(parity << UART_LCR_PARITY_BIT_POS) |
((stop_bits - 1) << UART_LCR_STPBIT_BIT_POS)) & 0x3F);
} else {
MBED_ASSERT(False);
}
}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
irq_handler = handler;
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
@ -229,166 +219,151 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
*******************************************************/
void Uart1_Irq()
{
uint8_t active_irq = (uint8_t)(UART1REG->LSR.WORD) & 0xFF;
uint8_t irq_mask = 0;
uint8_t active_irq = (uint8_t)(UART1REG->LSR.WORD) & 0xFF;
uint8_t irq_mask = 0;
if(UART1REG->IER.WORD & UART_IER_TX_EMPTY_MASK){ /*check if TX interrupt is enabled*/
irq_mask |= active_irq & UART_LSR_TX_EMPTY_MASK;
}
if(UART1REG->IER.WORD & UART_IER_TX_EMPTY_MASK) { /*check if TX interrupt is enabled*/
irq_mask |= active_irq & UART_LSR_TX_EMPTY_MASK;
}
if(UART1REG->IER.WORD & UART_IER_RX_DATA_READY_MASK){ /*check if RX interrupt is enabled*/
irq_mask |= active_irq & UART_LSR_RX_DATA_READY_MASK;
}
if(UART1REG->IER.WORD & UART_IER_RX_DATA_READY_MASK) { /*check if RX interrupt is enabled*/
irq_mask |= active_irq & UART_LSR_RX_DATA_READY_MASK;
}
//uart_irq((uint8_t)(UART1REG->LSR.WORD & 0xFF), 0);
uart_irq(active_irq & irq_mask, 0);
//uart_irq((uint8_t)(UART1REG->LSR.WORD & 0xFF), 0);
uart_irq(active_irq & irq_mask, 0);
}
void Uart2_Irq()
{
uint8_t active_irq = (uint8_t)(UART2REG->LSR.WORD) & 0xFF;
uint8_t irq_mask = 0;
uint8_t active_irq = (uint8_t)(UART2REG->LSR.WORD) & 0xFF;
uint8_t irq_mask = 0;
if(UART2REG->IER.WORD & UART_IER_TX_EMPTY_MASK){ /*check if TX interrupt is enabled*/
irq_mask |= active_irq & UART_LSR_TX_EMPTY_MASK;
}
if(UART2REG->IER.WORD & UART_IER_TX_EMPTY_MASK) { /*check if TX interrupt is enabled*/
irq_mask |= active_irq & UART_LSR_TX_EMPTY_MASK;
}
if(UART2REG->IER.WORD & UART_IER_RX_DATA_READY_MASK){ /*check if RX interrupt is enabled*/
irq_mask |= active_irq & UART_LSR_RX_DATA_READY_MASK;
}
if(UART2REG->IER.WORD & UART_IER_RX_DATA_READY_MASK) { /*check if RX interrupt is enabled*/
irq_mask |= active_irq & UART_LSR_RX_DATA_READY_MASK;
}
//uart_irq((uint8_t)(UART2REG->LSR.WORD & 0xFF), 1);
uart_irq(active_irq & irq_mask, 1);
//uart_irq((uint8_t)(UART2REG->LSR.WORD & 0xFF), 1);
uart_irq(active_irq & irq_mask, 1);
}
static inline void uart_irq(uint8_t status, uint32_t index)
{
if (serial_irq_ids[index] != 0)
{
if (status & UART_LSR_TX_EMPTY_MASK)
{
if (serial_irq_ids[index] != 0) {
if (status & UART_LSR_TX_EMPTY_MASK) {
irq_handler(serial_irq_ids[index], TxIrq);
}
if (status & UART_LSR_RX_DATA_READY_MASK)
{
irq_handler(serial_irq_ids[index], RxIrq);
}
}
if (status & UART_LSR_RX_DATA_READY_MASK) {
irq_handler(serial_irq_ids[index], RxIrq);
}
}
}
/******************************************************/
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t Vector = 0;
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t Vector = 0;
/* Check UART number & assign irq handler */
if(obj->UARTREG == UART1REG)
{/* UART 2 */
Vector = (uint32_t)&Uart1_Irq;
irq_n = Uart1_IRQn;
}
else if(obj->UARTREG == UART2REG)
{/* UART 1 */
Vector = (uint32_t)&Uart2_Irq;
irq_n = Uart2_IRQn;
}
else
{
MBED_ASSERT(False);
}
/* Check UART number & assign irq handler */
if(obj->UARTREG == UART1REG) {
/* UART 2 */
Vector = (uint32_t)&Uart1_Irq;
irq_n = Uart1_IRQn;
} else if(obj->UARTREG == UART2REG) {
/* UART 1 */
Vector = (uint32_t)&Uart2_Irq;
irq_n = Uart2_IRQn;
} else {
MBED_ASSERT(False);
}
/* Check IRQ type & enable/disable accordingly */
if(enable)
{/* Enable */
if(irq == RxIrq)
{/* Rx IRQ */
obj->UARTREG->FCR.BITS.RX_FIFO_TRIG = 0x0;
obj->UARTREG->IER.BITS.RX_DATA_INT = True;
}
else if(irq == TxIrq)
{/* Tx IRQ */
obj->UARTREG->IER.BITS.TX_HOLD_INT = True;
}
else
{
MBED_ASSERT(False);
}
NVIC_SetVector(irq_n, Vector);
NVIC_EnableIRQ(irq_n);
}
else
{/* Disable */
NVIC_DisableIRQ(irq_n);
if(irq == RxIrq)
{/* Rx IRQ */
obj->UARTREG->IER.BITS.RX_DATA_INT = False;
}
else if(irq == TxIrq)
{/* Tx IRQ */
/* Check IRQ type & enable/disable accordingly */
if(enable) {
/* Enable */
if(irq == RxIrq) {
/* Rx IRQ */
obj->UARTREG->FCR.BITS.RX_FIFO_TRIG = 0x0;
obj->UARTREG->IER.BITS.RX_DATA_INT = True;
} else if(irq == TxIrq) {
/* Tx IRQ */
obj->UARTREG->IER.BITS.TX_HOLD_INT = True;
} else {
MBED_ASSERT(False);
}
NVIC_SetVector(irq_n, Vector);
NVIC_EnableIRQ(irq_n);
} else {
/* Disable */
NVIC_DisableIRQ(irq_n);
if(irq == RxIrq) {
/* Rx IRQ */
obj->UARTREG->IER.BITS.RX_DATA_INT = False;
} else if(irq == TxIrq) {
/* Tx IRQ */
obj->UARTREG->IER.BITS.TX_HOLD_INT = False;
}
else
{
MBED_ASSERT(False);
}
}
obj->UARTREG->IER.BITS.TX_HOLD_INT = False;
} else {
MBED_ASSERT(False);
}
}
}
int serial_getc(serial_t *obj)
{
uint8_t c;
uint8_t c;
while(!obj->UARTREG->LSR.BITS.READY); /* Wait for received data is ready */
c = obj->UARTREG->RBR & 0xFF; /* Get received character */
return c;
while(!obj->UARTREG->LSR.BITS.READY); /* Wait for received data is ready */
c = obj->UARTREG->RBR & 0xFF; /* Get received character */
return c;
}
void serial_putc(serial_t *obj, int c)
{
while(!obj->UARTREG->LSR.BITS.TX_HOLD_EMPTY);/* Wait till THR is empty */
obj->UARTREG->THR = c; /* Transmit byte */
while(!obj->UARTREG->LSR.BITS.TX_HOLD_EMPTY);/* Wait till THR is empty */
obj->UARTREG->THR = c; /* Transmit byte */
}
int serial_readable(serial_t *obj)
{
return obj->UARTREG->LSR.BITS.READY;
return obj->UARTREG->LSR.BITS.READY;
}
int serial_writable(serial_t *obj)
{
return obj->UARTREG->LSR.BITS.TX_HOLD_EMPTY;
return obj->UARTREG->LSR.BITS.TX_HOLD_EMPTY;
}
void serial_clear(serial_t *obj)
{
/* Reset TX & RX FIFO */
obj->UARTREG->FCR.WORD |= ((True << UART_FCS_TX_FIFO_RST_BIT_POS) |
(True << UART_FCS_RX_FIFO_RST_BIT_POS));
/* Reset TX & RX FIFO */
obj->UARTREG->FCR.WORD |= ((True << UART_FCS_TX_FIFO_RST_BIT_POS) |
(True << UART_FCS_RX_FIFO_RST_BIT_POS));
}
void serial_break_set(serial_t *obj)
{
obj->UARTREG->LCR.BITS.BREAK = True;
obj->UARTREG->LCR.BITS.BREAK = True;
}
void serial_break_clear(serial_t *obj)
{
obj->UARTREG->LCR.BITS.BREAK = False;
obj->UARTREG->LCR.BITS.BREAK = False;
}
void serial_pinout_tx(PinName tx)
{
/* COnfigure PinNo to drive strength of 1, Push pull and pull none */
fPadIOCtrl(tx, 1, 0, 1);
/* COnfigure PinNo to drive strength of 1, Push pull and pull none */
fPadIOCtrl(tx, 1, 0, 1);
}
#ifdef TOOLCHAIN_ARM
/* Dummy function in order to get ARMCC compilation */
/** Configure the serial for the flow control. It sets flow control in the hardware
* if a serial peripheral supports it, otherwise software emulation is used.
*
@ -399,8 +374,7 @@ void serial_pinout_tx(PinName tx)
*/
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
{
//TODO: Dummy serial function
/* TODO: This is an empty implementation for now.*/
}
#endif /* TOOLCHAIN_ARM */
#endif /* DEVICE_SERIAL */

96
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep.c
View File

@ -40,73 +40,73 @@
void sleep(void)
{
/** Unset SLEEPDEEP (SCR) and COMA to select sleep mode */
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
PMUREG->CONTROL.BITS.ENCOMA = DISABLE;
/** Unset SLEEPDEEP (SCR) and COMA to select sleep mode */
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
PMUREG->CONTROL.BITS.ENCOMA = DISABLE;
/* Enter into sleep mode */
__ISB();
__WFI();
/* Enter into sleep mode */
__ISB();
__WFI();
}
void deepsleep(void)
{
/** Set SLEEPDEEP (SCR) and unset COMA to select deep sleep mode */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
PMUREG->CONTROL.BITS.ENCOMA = DISABLE;
/** Set SLEEPDEEP (SCR) and unset COMA to select deep sleep mode */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
PMUREG->CONTROL.BITS.ENCOMA = DISABLE;
/** Enter into deep sleep mode */
__ISB();
__WFI();
/** Enter into deep sleep mode */
__ISB();
__WFI();
/** Wait for the external 32MHz to be power-ed up & running
* Re-power down the 32MHz internal osc
*/
while (!CLOCKREG->CSR.BITS.XTAL32M);
PMUREG->CONTROL.BITS.INT32M = 1;
/** Wait for the external 32MHz to be power-ed up & running
* Re-power down the 32MHz internal osc
*/
while (!CLOCKREG->CSR.BITS.XTAL32M);
PMUREG->CONTROL.BITS.INT32M = 1;
}
void coma(void)
{
/** Set SLEEPDEEP (SCR) and set COMA to select coma mode */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
PMUREG->CONTROL.BITS.ENCOMA = ENABLE;
/** Set SLEEPDEEP (SCR) and set COMA to select coma mode */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
PMUREG->CONTROL.BITS.ENCOMA = ENABLE;
/* TODO Wait till MAC is idle */
// while((MACHWREG->SEQUENCER == MACHW_SEQ_TX) || (MACHWREG->SEQUENCER == MACHW_SEQ_ED) || (MACHWREG->SEQUENCER == MACHW_SEQ_CCA));
/* TODO Wait till MAC is idle */
// while((MACHWREG->SEQUENCER == MACHW_SEQ_TX) || (MACHWREG->SEQUENCER == MACHW_SEQ_ED) || (MACHWREG->SEQUENCER == MACHW_SEQ_CCA));
/* TODO Back up MAC_LUT *
uint8_t MAC_LUT_BackUp[MAC_LUT_SIZE];
fMacBackupFrameStoreLUT(MAC_LUT_BackUp); */
/* TODO Back up MAC_LUT *
uint8_t MAC_LUT_BackUp[MAC_LUT_SIZE];
fMacBackupFrameStoreLUT(MAC_LUT_BackUp); */
/* Disable UART 1 & 2 FIFO during coma*/
UART1REG->FCR.WORD &= ~(FCR_FIFO_ENABLE);
UART2REG->FCR.WORD &= ~(FCR_FIFO_ENABLE);
/* Disable UART 1 & 2 FIFO during coma*/
UART1REG->FCR.WORD &= ~(FCR_FIFO_ENABLE);
UART2REG->FCR.WORD &= ~(FCR_FIFO_ENABLE);
/** Enter into coma mode */
__ISB();
__WFI();
/** Enter into coma mode */
__ISB();
__WFI();
/** Wait for the external 32MHz to be power-ed up & running
* Re-power down the 32MHz internal osc
*/
while (!CLOCKREG->CSR.BITS.XTAL32M);
PMUREG->CONTROL.BITS.INT32M = 1;
/** Wait for the external 32MHz to be power-ed up & running
* Re-power down the 32MHz internal osc
*/
while (!CLOCKREG->CSR.BITS.XTAL32M);
PMUREG->CONTROL.BITS.INT32M = 1;
/** Trim the oscillators */
if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) {
CLOCKREG->TRIM_32K_EXT = TRIMREG->TRIM_32K_EXT;
}
if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) {
CLOCKREG->TRIM_32M_EXT = TRIMREG->TRIM_32M_EXT;
}
/** Trim the oscillators */
if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) {
CLOCKREG->TRIM_32K_EXT = TRIMREG->TRIM_32K_EXT;
}
if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) {
CLOCKREG->TRIM_32M_EXT = TRIMREG->TRIM_32M_EXT;
}
/* Enable UART 1 & 2 FIFO */
UART1REG->FCR.WORD |= FCR_FIFO_ENABLE;
UART2REG->FCR.WORD |= FCR_FIFO_ENABLE;
/* Enable UART 1 & 2 FIFO */
UART1REG->FCR.WORD |= FCR_FIFO_ENABLE;
UART2REG->FCR.WORD |= FCR_FIFO_ENABLE;
/* TODO Restore MAC_LUT *
fMacRestoreFrameStoreLUT(MAC_LUT_BackUp); */
/* TODO Restore MAC_LUT *
fMacRestoreFrameStoreLUT(MAC_LUT_BackUp); */
}
#endif /* DEVICE_SLEEP */

52
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c
View File

@ -32,57 +32,7 @@
void mbed_enter_sleep(sleep_t *obj)
{
#if 0
#if 1 /* TODO Temporary code will be removed once mbed OS paases this details */
obj->timeToSleep = False;
obj->SleepType = SLEEP_TYPE_DEEPSLEEP;
#endif
CLOCK_ENABLE(CLOCK_PMU);
/* Select sleep mode */
if(obj->timeToSleep == False)
{/* Use SleepType to select sleep mode*/
if(obj->SleepType == SLEEP_TYPE_SLEEP)
{
sleep();
}
else if(obj->SleepType == SLEEP_TYPE_DEEPSLEEP)
{
deepsleep();
}
else if(obj->SleepType == SLEEP_TYPE_COMA)
{
coma();
}
else
{
/* Do nothing */
}
}
else
{/* Select sleep mode using TimetoSleep */
if((obj->timeToSleep >= SLEEP_DURATION_SLEEP_MIN) && (obj->timeToSleep <= SLEEP_DURATION_SLEEP_MAX))
{
sleep();
}
else if((obj->timeToSleep > SLEEP_DURATION_SLEEP_MAX) && (obj->timeToSleep <= SLEEP_DURATION_DEEPSLEEP_MAX))
{
deepsleep();
}
else if((obj->timeToSleep > SLEEP_DURATION_DEEPSLEEP_MAX) && (obj->timeToSleep <= SLEEP_DURATION_COMA_MAX))
{
coma();
}
else
{
/* Do nothing */
}
}
CLOCK_DISABLE(CLOCK_PMU);
#endif
/* Empty implementation, this will be implemented for mbed5.0 */
}
void mbed_exit_sleep(sleep_t *obj)

2
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi.h
View File

@ -35,7 +35,7 @@
extern "C" {
#endif
/* Miscellaneous I/O and control operations codes */
/* Miscellaneous I/O and control operations codes */
#define SPI_IPC7207_IOCTL_GET_SLAVE_SELECT (0x1) /**< <b>Ioctl request code</b>: Reading slaveSelect register */
#define SPI_IPC7207_IOCTL_SET_SLAVE_SELECT (0x2) /**< <b>Ioctl request code</b>: Setting slaveSelect register */
#define SPI_IPC7207_IOCTL_FLUSH (0x3) /**< <b>Ioctl request code</b>: Flushin FIFOs and serial shift registers */

150
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c
View File

@ -44,64 +44,57 @@
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
fSpiInit(obj, mosi, miso, sclk, ssel);
fSpiInit(obj, mosi, miso, sclk, ssel);
}
void spi_free(spi_t *obj)
{
fSpiClose(obj);
fSpiClose(obj);
}
void spi_format(spi_t *obj, int bits, int mode, int slave)
{
if(slave)
{/* Slave mode */
obj->membase->CONTROL.BITS.MODE = SPI_SLAVE_MODE;
}
else
{/* Master mode */
obj->membase->CONTROL.BITS.MODE = SPI_MASTER_MODE;
}
obj->membase->CONTROL.BITS.WORD_WIDTH = bits >> 0x4; /* word width */
obj->membase->CONTROL.BITS.CPOL = mode >> 0x1; /* CPOL */
obj->membase->CONTROL.BITS.CPHA = mode & 0x1; /* CPHA */
if(slave) {
/* Slave mode */
obj->membase->CONTROL.BITS.MODE = SPI_SLAVE_MODE;
} else {
/* Master mode */
obj->membase->CONTROL.BITS.MODE = SPI_MASTER_MODE;
}
obj->membase->CONTROL.BITS.WORD_WIDTH = bits >> 0x4; /* word width */
obj->membase->CONTROL.BITS.CPOL = mode >> 0x1; /* CPOL */
obj->membase->CONTROL.BITS.CPHA = mode & 0x1; /* CPHA */
obj->membase->CONTROL.BITS.ENDIAN = SPI_ENDIAN_LSB_FIRST; /* Endian TODO ARM needs to confirm? */
obj->membase->CONTROL.BITS.ENDIAN = SPI_ENDIAN_LSB_FIRST; /* Endian */
}
void spi_frequency(spi_t *obj, int hz)
{
/* TODO if the frequency is outside the allowable range, set it to the max */
if(hz > SPI_FREQ_MAX)
{
hz = SPI_FREQ_MAX;
}
obj->membase->FDIV = ((fClockGetPeriphClockfrequency() / hz) >> 1) - 1;
/* If the frequency is outside the allowable range, set it to the max */
if(hz > SPI_FREQ_MAX) {
hz = SPI_FREQ_MAX;
}
obj->membase->FDIV = ((fClockGetPeriphClockfrequency() / hz) >> 1) - 1;
}
int spi_master_write(spi_t *obj, int value)
{
return(fSpiWriteB(obj, value));
return(fSpiWriteB(obj, value));
}
int spi_busy(spi_t *obj)
{
return(obj->membase->STATUS.BITS.XFER_IP);
return(obj->membase->STATUS.BITS.XFER_IP);
}
uint8_t spi_get_module(spi_t *obj)
{
if(obj->membase == SPI1REG)
{
return 0; /* UART #1 */
}
else if(obj->membase == SPI2REG)
{
return 1; /* UART #2 */
}
else
{
return 2; /* Invalid address */
}
if(obj->membase == SPI1REG) {
return 0; /* UART #1 */
} else if(obj->membase == SPI2REG) {
return 1; /* UART #2 */
} else {
return 2; /* Invalid address */
}
}
#if DEVICE_SPI_ASYNCH /* TODO Not implemented yet */
@ -109,29 +102,27 @@ uint8_t spi_get_module(spi_t *obj)
void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t handler, uint32_t event, DMAUsage hint)
{
uint32_t i; int ndata = 0;
uint32_t i;
int ndata = 0;
uint16_t *tx_ptr = (uint16_t *) tx;
if(obj->spi->CONTROL.BITS.WORD_WIDTH == 0)
{/* Word size 8 bits */
WORD_WIDTH_MASK = 0xFF;
}
else if(obj->spi->CONTROL.BITS.WORD_WIDTH == 1)
{/* Word size 16 bits */
WORD_WIDTH_MASK = 0xFFFF;
}
else
{/* Word size 32 bits */
WORD_WIDTH_MASK = 0xFFFFFFFF;
}
if(obj->spi->CONTROL.BITS.WORD_WIDTH == 0) {
/* Word size 8 bits */
WORD_WIDTH_MASK = 0xFF;
} else if(obj->spi->CONTROL.BITS.WORD_WIDTH == 1) {
/* Word size 16 bits */
WORD_WIDTH_MASK = 0xFFFF;
} else {
/* Word size 32 bits */
WORD_WIDTH_MASK = 0xFFFFFFFF;
}
//frame size
if(tx_length == 0)
{
tx_length = rx_length;
tx = (void*) 0;
}
//set tx rx buffer
//frame size
if(tx_length == 0) {
tx_length = rx_length;
tx = (void*) 0;
}
//set tx rx buffer
obj->tx_buff.buffer = (void *)tx;
obj->rx_buff.buffer = rx;
obj->tx_buff.length = tx_length;
@ -150,41 +141,36 @@ void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_
}
// enable events
// enable events
obj->spi.event |= event;
obj->spi.event |= event;
// set sleep_level
enable irq
// set sleep_level
enable irq
//write async
//write async
if ( && )
{
if ( && ) {
}
while ((obj->tx_buff.pos < obj->tx_buff.length) &&
(obj->spi->STATUS.BITS.TX_FULL == False) &&
(obj->spi->STATUS.BITS.RX_FULL == False))
{
// spi_buffer_tx_write(obj);
if (obj->tx_buff.buffer == (void *)0)
{
data = SPI_FILL_WORD;
}
else
{
uint16_t *tx = (uint16_t *)(obj->tx_buff.buffer);
data = tx[obj->tx_buff.pos] & 0xFF;
}
obj->spi->TX_DATA = data;
}
ndata++;
}
return ndata;
while ((obj->tx_buff.pos < obj->tx_buff.length) &&
(obj->spi->STATUS.BITS.TX_FULL == False) &&
(obj->spi->STATUS.BITS.RX_FULL == False)) {
// spi_buffer_tx_write(obj);
if (obj->tx_buff.buffer == (void *)0) {
data = SPI_FILL_WORD;
} else {
uint16_t *tx = (uint16_t *)(obj->tx_buff.buffer);
data = tx[obj->tx_buff.pos] & 0xFF;
}
obj->spi->TX_DATA = data;
}
ndata++;
}
return ndata;
}

86
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi_ipc7207_map.h
View File

@ -39,49 +39,49 @@
/** SPI HW Structure Overlay */
typedef struct {
__O uint32_t TX_DATA;
__I uint32_t RX_DATA;
__IO uint32_t FDIV;
union {
struct {
__IO uint32_t ENABLE :1; /**< SPI port enable: 0 = disable , 1 = enable */
__IO uint32_t SAMPLING_EDGE :1; /**< SDI sampling edge: 0 = opposite to SDO edge / 1 = same as SDO edge */
__IO uint32_t ENDIAN :1; /**< Bits endianness: 0 = LSB first (little-endian) / 1 = MSB first (big-endian) */
__IO uint32_t CPHA :1; /**< Clock phase: 0 = SDO set before first SCLK edge / 1 = SDO set after first SCLK edge */
__IO uint32_t CPOL :1; /**< Clock polarity: 0 = active high / 1 = active low */
__IO uint32_t MODE :1; /**< Device mode: 0 = slave mode / 1 = master mode */
__IO uint32_t WORD_WIDTH :2; /**< Word width: 0 = 8b / 1 = 16b / 2 = 32b / 3 = reserved */
} BITS;
__IO uint32_t WORD;
} CONTROL;
union {
struct {
__I uint32_t XFER_IP :1; /**< Transfer in progress: 0 = No transfer in progress / 1 = transfer in progress */
__I uint32_t XFER_ERROR :1;/**< Transfer error: 0 = no error / 1 = SPI Overflow or Underflow */
__I uint32_t TX_EMPTY :1; /**< Transmit FIFO/buffer empty flag: 0 = not empty / 1 = empty */
__I uint32_t TX_HALF :1; /**< Transmit FIFO/buffer "half full" flag: 0 = (< half full) / 1 = (>= half full) */
__I uint32_t TX_FULL :1; /**< Transmit FIFO/buffer full flag: 0 = not full / 1 = full */
__I uint32_t RX_EMPTY :1; /**< Receive FIFO/buffer empty flag: 0 = not empty / 1 = empty */
__I uint32_t RX_HALF :1; /**< Receive FIFO/buffer "half full" flag: 0 = (< half full) / 1 = (>= half full) */
__I uint32_t RX_FULL :1; /**< Receive FIFO/buffer full flag: 0 = not full / 1 = full */
} BITS;
__I uint32_t WORD;
} STATUS;
union {
struct {
__IO uint32_t SS_ENABLE :4; /**< Slave Select (x4): 0 = disable / 1 = enable */
__IO uint32_t SS_BURST :1; /**< Slave Select burst mode (maintain SS active if TXFIFO not empty) */
} BITS;
__IO uint32_t WORD;
} SLAVE_SELECT;
__IO uint32_t SLAVE_SELECT_POLARITY; /**< Slave Select polarity for up to 4 slaves:0 = active low / 1 = active high */
__IO uint32_t IRQ_ENABLE; /**< IRQ (x8) enable: 0 = disable / 1 = enable */
__I uint32_t IRQ_STATUS; /**< IRQ (x8) status: 0 = no IRQ occurred / 1 = IRQ occurred */
__O uint32_t IRQ_CLEAR; /**< IRQ (x8) clearing: write 1 to clear IRQ */
__IO uint32_t TX_WATERMARK; /**< Transmit FIFO Watermark: Defines level of RX Half Full Flag */
__IO uint32_t RX_WATERMARK; /**< Receive FIFO Watermark: Defines level of TX Half Full Flag */
__I uint32_t TX_FIFO_LEVEL; /**< Transmit FIFO Level: Indicates actual fill level of TX FIFO. */
__I uint32_t RX_FIFO_LEVEL; /**< Transmit FIFO Level: Indicates actual fill level of RX FIFO. */
__O uint32_t TX_DATA;
__I uint32_t RX_DATA;
__IO uint32_t FDIV;
union {
struct {
__IO uint32_t ENABLE :1; /**< SPI port enable: 0 = disable , 1 = enable */
__IO uint32_t SAMPLING_EDGE :1; /**< SDI sampling edge: 0 = opposite to SDO edge / 1 = same as SDO edge */
__IO uint32_t ENDIAN :1; /**< Bits endianness: 0 = LSB first (little-endian) / 1 = MSB first (big-endian) */
__IO uint32_t CPHA :1; /**< Clock phase: 0 = SDO set before first SCLK edge / 1 = SDO set after first SCLK edge */
__IO uint32_t CPOL :1; /**< Clock polarity: 0 = active high / 1 = active low */
__IO uint32_t MODE :1; /**< Device mode: 0 = slave mode / 1 = master mode */
__IO uint32_t WORD_WIDTH :2; /**< Word width: 0 = 8b / 1 = 16b / 2 = 32b / 3 = reserved */
} BITS;
__IO uint32_t WORD;
} CONTROL;
union {
struct {
__I uint32_t XFER_IP :1; /**< Transfer in progress: 0 = No transfer in progress / 1 = transfer in progress */
__I uint32_t XFER_ERROR :1;/**< Transfer error: 0 = no error / 1 = SPI Overflow or Underflow */
__I uint32_t TX_EMPTY :1; /**< Transmit FIFO/buffer empty flag: 0 = not empty / 1 = empty */
__I uint32_t TX_HALF :1; /**< Transmit FIFO/buffer "half full" flag: 0 = (< half full) / 1 = (>= half full) */
__I uint32_t TX_FULL :1; /**< Transmit FIFO/buffer full flag: 0 = not full / 1 = full */
__I uint32_t RX_EMPTY :1; /**< Receive FIFO/buffer empty flag: 0 = not empty / 1 = empty */
__I uint32_t RX_HALF :1; /**< Receive FIFO/buffer "half full" flag: 0 = (< half full) / 1 = (>= half full) */
__I uint32_t RX_FULL :1; /**< Receive FIFO/buffer full flag: 0 = not full / 1 = full */
} BITS;
__I uint32_t WORD;
} STATUS;
union {
struct {
__IO uint32_t SS_ENABLE :4; /**< Slave Select (x4): 0 = disable / 1 = enable */
__IO uint32_t SS_BURST :1; /**< Slave Select burst mode (maintain SS active if TXFIFO not empty) */
} BITS;
__IO uint32_t WORD;
} SLAVE_SELECT;
__IO uint32_t SLAVE_SELECT_POLARITY; /**< Slave Select polarity for up to 4 slaves:0 = active low / 1 = active high */
__IO uint32_t IRQ_ENABLE; /**< IRQ (x8) enable: 0 = disable / 1 = enable */
__I uint32_t IRQ_STATUS; /**< IRQ (x8) status: 0 = no IRQ occurred / 1 = IRQ occurred */
__O uint32_t IRQ_CLEAR; /**< IRQ (x8) clearing: write 1 to clear IRQ */
__IO uint32_t TX_WATERMARK; /**< Transmit FIFO Watermark: Defines level of RX Half Full Flag */
__IO uint32_t RX_WATERMARK; /**< Receive FIFO Watermark: Defines level of TX Half Full Flag */
__I uint32_t TX_FIFO_LEVEL; /**< Transmit FIFO Level: Indicates actual fill level of TX FIFO. */
__I uint32_t RX_FIFO_LEVEL; /**< Transmit FIFO Level: Indicates actual fill level of RX FIFO. */
} SpiIpc7207Reg_t, *SpiIpc7207Reg_pt;
#endif /* SPI_IPC7207_MAP_H_ */

2
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/swversion.c
View File

@ -36,7 +36,7 @@
* such that flash loader knows where to find it and gets the build dependent data
* it needs for programming the new fib.
*/
__root const fibtable_t fib_table @ "FIBTABLE" = { LOAD_ADDRESS,{0x0,0x00,0x00,0x00}};
__root const fibtable_t fib_table @ "FIBTABLE" = { LOAD_ADDRESS,{0x0,0x00,0x00,0x00}};
#endif /* IAR */
const mib_systemRevision_t systemRevision = {

22
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ticker.h
View File

@ -3,9 +3,9 @@
* @file ticker.h
* @brief Microcontroller uSec ticker
* @internal
* @author Radhika
* $Rev:
* $Date:
* @author ON Semiconductor.
* $Rev:
* $Date:
******************************************************************************
* @copyright (c) 2012 ON Semiconductor. All rights reserved.
* ON Semiconductor is supplying this software for use with ON Semiconductor
@ -18,9 +18,9 @@
* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* @endinternal
*
*
*
*/
#ifndef TICKER_H_
#define TICKER_H_
@ -41,12 +41,12 @@
#define configCPU_CLOCK_HZ ( ( unsigned long ) (CPU_CLOCK_ROOT_HZ/CPU_CLOCK_DIV) )
#define configTICK_RATE_HZ ( ( unsigned long ) 1000000 ) // 1uSec ticker rate
/* Lowest priority */
#define configKERNEL_INTERRUPT_PRIORITY ( 0xFF )
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 0x8F )
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 0x8F )
#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
/* Constants required to manipulate the core. Registers first... */
@ -54,7 +54,7 @@
#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )
#define portNVIC_INT_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )
#define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )
#define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
@ -65,12 +65,12 @@
/* Orion has 4 interrupt priority bits
*/
#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )
/* API definitions */
void fSysTickInit(void);
void fSysTickHandler(void);
uint32_t fSysTickRead(void);
void fSysTickEnableInterrupt (void);

36
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/timer.h
View File

@ -39,10 +39,10 @@
#ifndef TIMER_H_
#define TIMER_H_
#ifdef __cplusplus
#ifdef __cplusplus
extern "C" {
#endif
//#include "driver.h"
#include "us_ticker_api.h"
#include "clock.h"
@ -64,15 +64,15 @@ extern "C" {
/* Options defines */
// TODO (MIV): put this in an enumerated value
typedef enum {
CLK_DIVIDER_1 = 0,
CLK_DIVIDER_2 = 3,
CLK_DIVIDER_8 = 4,
CLK_DIVIDER_16 = 1,
CLK_DIVIDER_32 = 5,
CLK_DIVIDER_128 = 6,
CLK_DIVIDER_256 = 2,
CLK_DIVIDER_1024 = 7
}ClockDivider;
CLK_DIVIDER_1 = 0,
CLK_DIVIDER_2 = 3,
CLK_DIVIDER_8 = 4,
CLK_DIVIDER_16 = 1,
CLK_DIVIDER_32 = 5,
CLK_DIVIDER_128 = 6,
CLK_DIVIDER_256 = 2,
CLK_DIVIDER_1024 = 7
} ClockDivider;
#define TIME_MODE_FREE_RUNNING 0x0
#define TIME_MODE_PERIODIC 0x1
@ -81,14 +81,14 @@ typedef void (*timer_irq_handlers_t)(void) ;
/** Options to be passed when opening a timer device instance.*/
typedef struct timer_options {
TimerReg_pt membase; /**< Memory base for the device's registers. */
uint8_t irq; /**< IRQ number of the IRQ associated to the device. */
boolean mode; /**< Timer mode:
TimerReg_pt membase; /**< Memory base for the device's registers. */
uint8_t irq; /**< IRQ number of the IRQ associated to the device. */
boolean mode; /**< Timer mode:
* - 0 = Free Run mode (no interrupt generation)
* <b> # timer duration = (65535 + 1) * prescaler * peripheral clock (PCLK) period </b>
* - 1 = Periodic mode (interrupt generation)
* <b> # timer duration = (load + 1) * prescaler * peripheral clock (PCLK) period </b> */
uint8_t prescale; /**< Timer prescaler: from 1 to 1024.
uint8_t prescale; /**< Timer prescaler: from 1 to 1024.
* - CLK_DIVIDER_1 = clock not divided
* - CLK_DIVIDER_2 = clock is divided by 2
* - CLK_DIVIDER_8 = clock is divided by 8
@ -97,8 +97,8 @@ typedef struct timer_options {
* - CLK_DIVIDER_128 = clock is divided by 128
* - CLK_DIVIDER_256 = clock is divided by 256
* - CLK_DIVIDER_1024 = clock is divided by 1024 */
uint16_t load; /**< Timer load: from 0 to 65535. */
timer_irq_handlers_t handler; /**< Timer handler or call-back */
uint16_t load; /**< Timer load: from 0 to 65535. */
timer_irq_handlers_t handler; /**< Timer handler or call-back */
} timer_options_t, *timer_options_pt;
/** Interrupt handler for timer devices; to be called from an actual ISR.
@ -111,6 +111,6 @@ extern void us_ticker_isr(void);
#ifdef __cplusplus
}
#endif
#endif
#endif /* TIMER_H_ */

30
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/timer_map.h
View File

@ -43,24 +43,24 @@ extern "C" {
/** Timer HW Structure Overlay */
typedef struct {
__IO uint32_t LOAD; /**< 16bit counter (re-)load value */
__I uint32_t VALUE; /**< 16bit current counter value */
union {
struct {
__IO uint32_t PAD0 :2; /**< Always reads 0 */
__IO uint32_t PRESCALE :3; /**< 0:no division, 1..7: divide by 16, 256, 2, 8, 32, 128, 1024*/
__IO uint32_t PAD1 :1; /**< Always reads 0 */
__IO uint32_t MODE :1; /**< 0:free-run, 1:periodic */
__IO uint32_t ENABLE :1; /**< 0: disable, 1:enable */
__I uint32_t INT :1; /**< interrupt status */
} BITS;
__IO uint32_t WORD;
} CONTROL;
__O uint32_t CLEAR; /**< Write any value to clear the interrupt */
__IO uint32_t LOAD; /**< 16bit counter (re-)load value */
__I uint32_t VALUE; /**< 16bit current counter value */
union {
struct {
__IO uint32_t PAD0 :2; /**< Always reads 0 */
__IO uint32_t PRESCALE :3; /**< 0:no division, 1..7: divide by 16, 256, 2, 8, 32, 128, 1024*/
__IO uint32_t PAD1 :1; /**< Always reads 0 */
__IO uint32_t MODE :1; /**< 0:free-run, 1:periodic */
__IO uint32_t ENABLE :1; /**< 0: disable, 1:enable */
__I uint32_t INT :1; /**< interrupt status */
} BITS;
__IO uint32_t WORD;
} CONTROL;
__O uint32_t CLEAR; /**< Write any value to clear the interrupt */
} TimerReg_t, *TimerReg_pt;
#ifdef __cplusplus
}
#endif
#endif
#endif /* TIMER_MAP_H_ */

148
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h
View File

@ -45,83 +45,83 @@
/** trim register map */
typedef struct { /**< REV B REV D */
__I uint32_t PAD0; /**< 0x1FA0 0x1FA0 */
__I uint32_t APP_RESERVED0; /**< 0x1FA4 0x1FA4 */
__I uint32_t APP_RESERVED1; /**< 0x1FA8 0x1FA8 */
#ifdef REVB
__I uint32_t TX_POWER; /**< 0x1FAC */
__I uint32_t PAD0; /**< 0x1FA0 0x1FA0 */
__I uint32_t APP_RESERVED0; /**< 0x1FA4 0x1FA4 */
__I uint32_t APP_RESERVED1; /**< 0x1FA8 0x1FA8 */
#ifdef REVB
__I uint32_t TX_POWER; /**< 0x1FAC */
#endif
__I uint32_t TRIM_32K_EXT; /**< 0x1FB0 0x1FAC */
__I uint32_t TRIM_32M_EXT; /**< 0x1FB4 0x1FB0 */
__I uint32_t TRIM_32K_EXT; /**< 0x1FB0 0x1FAC */
__I uint32_t TRIM_32M_EXT; /**< 0x1FB4 0x1FB0 */
#ifdef REVD
__I uint32_t FVVDH_COMP_TH; /**< 0x1FB4 */
__I uint32_t FVVDH_COMP_TH; /**< 0x1FB4 */
#endif
union {
struct { /* Common to REV B & REV D */
__I uint32_t CHANNEL11:4;
__I uint32_t CHANNEL12:4;
__I uint32_t CHANNEL13:4;
__I uint32_t CHANNEL14:4;
__I uint32_t CHANNEL15:4;
__I uint32_t CHANNEL16:4;
__I uint32_t CHANNEL17:4;
__I uint32_t CHANNEL18:4;
} BITS;
__I uint32_t WORD;
} TX_VCO_LUT1; /**< 0x1FB8 */
union {
struct {
__I uint32_t CHANNEL19:4;
__I uint32_t CHANNEL20:4;
__I uint32_t CHANNEL21:4;
__I uint32_t CHANNEL22:4;
__I uint32_t CHANNEL23:4;
__I uint32_t CHANNEL24:4;
__I uint32_t CHANNEL25:4;
__I uint32_t CHANNEL26:4;
} BITS;
__I uint32_t WORD;
} TX_VCO_LUT2; /**< 0x1FBC */
union {
struct {
__I uint32_t CHANNEL11:4;
__I uint32_t CHANNEL12:4;
__I uint32_t CHANNEL13:4;
__I uint32_t CHANNEL14:4;
__I uint32_t CHANNEL15:4;
__I uint32_t CHANNEL16:4;
__I uint32_t CHANNEL17:4;
__I uint32_t CHANNEL18:4;
} BITS;
__I uint32_t WORD;
} RX_VCO_LUT1; /**< 0x1FC0 */
union {
struct {
__I uint32_t CHANNEL19:4;
__I uint32_t CHANNEL20:4;
__I uint32_t CHANNEL21:4;
__I uint32_t CHANNEL22:4;
__I uint32_t CHANNEL23:4;
__I uint32_t CHANNEL24:4;
__I uint32_t CHANNEL25:4;
__I uint32_t CHANNEL26:4;
} BITS;
__I uint32_t WORD;
} RX_VCO_LUT2; /**< 0x1FC4 */
__I uint32_t ON_RESERVED0; /**< 0x1FC8 */
__I uint32_t ON_RESERVED1; /**< 0x1FCC */
__I uint32_t ADC_OFFSET_TRIM; /**< 0x1FD0 */
__I uint32_t TX_PRE_CHIPS; /**< 0x1FD4 */
__I uint32_t TX_CHAIN_TRIM; /**< 0x1FD8 */
__I uint32_t PLL_VCO_TAP_LOCATION; /**< 0x1FDC */
__I uint32_t PLL_TRIM; /**< 0x1FE0 */
__I uint32_t RSSI_OFFSET; /**< 0x1FE4 */
__I uint32_t RX_CHAIN_TRIM; /**< 0x1FE8 */
__I uint32_t PMU_TRIM; /**< 0x1FEC */
__I uint32_t WR_SEED_RD_RAND; /**< 0x1FF0 */
__I uint32_t WAFER_LOCATION; /**< 0x1FF4 */
__I uint32_t LOT_NUMBER; /**< 0x1FF8 */
__I uint32_t REVISION_CODE; /**< 0x1FFC */
union {
struct { /* Common to REV B & REV D */
__I uint32_t CHANNEL11:4;
__I uint32_t CHANNEL12:4;
__I uint32_t CHANNEL13:4;
__I uint32_t CHANNEL14:4;
__I uint32_t CHANNEL15:4;
__I uint32_t CHANNEL16:4;
__I uint32_t CHANNEL17:4;
__I uint32_t CHANNEL18:4;
} BITS;
__I uint32_t WORD;
} TX_VCO_LUT1; /**< 0x1FB8 */
union {
struct {
__I uint32_t CHANNEL19:4;
__I uint32_t CHANNEL20:4;
__I uint32_t CHANNEL21:4;
__I uint32_t CHANNEL22:4;
__I uint32_t CHANNEL23:4;
__I uint32_t CHANNEL24:4;
__I uint32_t CHANNEL25:4;
__I uint32_t CHANNEL26:4;
} BITS;
__I uint32_t WORD;
} TX_VCO_LUT2; /**< 0x1FBC */
union {
struct {
__I uint32_t CHANNEL11:4;
__I uint32_t CHANNEL12:4;
__I uint32_t CHANNEL13:4;
__I uint32_t CHANNEL14:4;
__I uint32_t CHANNEL15:4;
__I uint32_t CHANNEL16:4;
__I uint32_t CHANNEL17:4;
__I uint32_t CHANNEL18:4;
} BITS;
__I uint32_t WORD;
} RX_VCO_LUT1; /**< 0x1FC0 */
union {
struct {
__I uint32_t CHANNEL19:4;
__I uint32_t CHANNEL20:4;
__I uint32_t CHANNEL21:4;
__I uint32_t CHANNEL22:4;
__I uint32_t CHANNEL23:4;
__I uint32_t CHANNEL24:4;
__I uint32_t CHANNEL25:4;
__I uint32_t CHANNEL26:4;
} BITS;
__I uint32_t WORD;
} RX_VCO_LUT2; /**< 0x1FC4 */
__I uint32_t ON_RESERVED0; /**< 0x1FC8 */
__I uint32_t ON_RESERVED1; /**< 0x1FCC */
__I uint32_t ADC_OFFSET_TRIM; /**< 0x1FD0 */
__I uint32_t TX_PRE_CHIPS; /**< 0x1FD4 */
__I uint32_t TX_CHAIN_TRIM; /**< 0x1FD8 */
__I uint32_t PLL_VCO_TAP_LOCATION; /**< 0x1FDC */
__I uint32_t PLL_TRIM; /**< 0x1FE0 */
__I uint32_t RSSI_OFFSET; /**< 0x1FE4 */
__I uint32_t RX_CHAIN_TRIM; /**< 0x1FE8 */
__I uint32_t PMU_TRIM; /**< 0x1FEC */
__I uint32_t WR_SEED_RD_RAND; /**< 0x1FF0 */
__I uint32_t WAFER_LOCATION; /**< 0x1FF4 */
__I uint32_t LOT_NUMBER; /**< 0x1FF8 */
__I uint32_t REVISION_CODE; /**< 0x1FFC */
} TrimReg_t, *TrimReg_pt;
#endif /* TRIM_MAP_H_ */

24
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart.h
View File

@ -40,22 +40,22 @@
/** Type listing the supported kinds of flow control. */
typedef enum {
/** No flow control */
none,
/** use hardware CTS (External CPU indicates it is ok for the modem to transmit)
* and RTS (modem requests to sent to external CPU) flow control.
*/
rtscts,
/** use hardware CTS/RTS flow control, but CTS is no response to RTS,
* RTS and CTS are used to indicate intent to transmit.
*/
rtscts_e
/** No flow control */
none,
/** use hardware CTS (External CPU indicates it is ok for the modem to transmit)
* and RTS (modem requests to sent to external CPU) flow control.
*/
rtscts,
/** use hardware CTS/RTS flow control, but CTS is no response to RTS,
* RTS and CTS are used to indicate intent to transmit.
*/
rtscts_e
} flow_control_t;
/** A set of options to be passed when creating a uart device instance. */
typedef struct uart_options {
uint32_t baudrate; /**< The expected baud rate. */
flow_control_t control;/**< Defines type of flow control, none or rtscts */
uint32_t baudrate; /**< The expected baud rate. */
flow_control_t control;/**< Defines type of flow control, none or rtscts */
} uart_options_t, *uart_options_pt;
#endif /* UART_H_ */

6
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550.h
View File

@ -48,9 +48,9 @@
/** A set of options to be passed when opening a 16C550 UART device. */
typedef struct uart_16c550_options {
uart_options_t uartOptions; /**< The generic UART options. */
Uart16C550Reg_pt membase; /**< The memory base for the device's registers. */
uint8_t irq; /**< The IRQ number of the IRQ associated to the device. */
uart_options_t uartOptions; /**< The generic UART options. */
Uart16C550Reg_pt membase; /**< The memory base for the device's registers. */
uint8_t irq; /**< The IRQ number of the IRQ associated to the device. */
} uart_16c550_options_t, *uart_16c550_options_pt;
#define UART_NUM 2

198
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h
View File

@ -3,7 +3,7 @@
* @file uart_16c550_map.h
* @brief UART module hardware register map.
* @internal
* @author Industrial ASSP Applications Team
* @author ON Semiconductor.
* $Rev: 2615 $
* $Date: 2013-12-13 13:17:21 +0530 (Fri, 13 Dec 2013) $
******************************************************************************
@ -62,104 +62,104 @@
/** UART HW Structure Overlay */
typedef struct {
/** Base address + 0x0: Receive, transmit and divisor_LSB offset */
union {
__I uint32_t RBR; /**< Received data (8 bits wide) / read only */
__O uint32_t THR; /**< Data to be transmitted (8 bits wide) / write only */
__IO uint32_t DLL; /**< If DLAB = 1. LS byte for input to baud rate generator */
};
/** Base address + 0x4: Interrupt enable and divisor_MSB offset */
union {
union {
struct {
__IO uint32_t RX_DATA_INT :1; /**< Enables the received data interrupt, write 1 to enable */
__IO uint32_t TX_HOLD_INT :1; /**< Enables the transmitter holding interrupt, write 1 to enable */
__IO uint32_t RX_STATUS_INT :1; /**< Enables the receiver line status interrupt, write 1 to enable */
__IO uint32_t MODEM_STATUS_INT :1; /**< Enables the modem status interrupt, write 1 to enable */
__IO uint32_t PAD0 :1;
__IO uint32_t PD_EN :1; /**< Power down enable active bit, write 1 to enable. Only enabled if PD_EN in MCR is set also */
__IO uint32_t PAD1 :2;
} BITS;
__IO uint32_t WORD;
} IER; /** Interrupt enable offset 0x04 */
__IO uint32_t DLM; /**< If DLAB = 1. MS byte for input to baud rate generator */
};
/** Base address + 0x8: Interrupt status and fifo control offset*/
union {
union {
struct {
__I uint32_t INT_PEND :1; /**< Interrupt is pending if 1 */
__I uint32_t INT_ID :3; /**< Interrupt identification: 011-RX Line, 010-Rx Data, 110-char TO, 001-TX empty, 000-Modem status*/
__I uint32_t PAD0 :2;
__I uint32_t FIFO_EN :2; /**< Fifos enabled: 00-disabled, 01/10-undefined, 11-enabled */
} BITS;
__I uint32_t WORD;
} IIR; /** Interrupt status and fifo status offset 0x08 */
union {
struct {
__O uint32_t FIFO_EN :1; /**< FIFO enable, write 1 to enable */
__O uint32_t RX_FIFO_RST :1; /**< RX FIFO reset, write 1 to reset */
__O uint32_t TX_FIFO_RST :1; /**< TX FIFO reset, write 1 to reset */
__O uint32_t DMA_SEL :1; /**< DMA mode select */
__O uint32_t PAD0 :2;
__O uint32_t RX_FIFO_TRIG :2; /**< Receiver FIFO trigger level:00-1byte, 01-4bytes, 10-8bytes, 11-14bytes */
} BITS;
__O uint32_t WORD;
} FCR; /** Fifo control offset 0x08 */
};
/** Base address + 0xC: Line control offset */
union {
struct {
__IO uint32_t CHAR_LEN :2; /**< Number of bits per character: 00-5bits, 01-6bits, 10:7bits, 11:8bits */
__IO uint32_t NUM_STOP :1; /**< Number of stop bits: 0-1bit, 1-2bits */
__IO uint32_t PARITY :3; /**< Parity: xx0-disable, 001-odd, 011-even, 101-stick generated/checked as 1, 111-stick generated/checked as 0 */
__IO uint32_t BREAK :1; /**< Set to 1 to force output to 0, set to 0 to return to normal operation */
__IO uint32_t DLAB :1; /**< Set to 1 to enable the DLL, DLM registers at 0x00 and 0x04 */
} BITS;
__IO uint32_t WORD;
} LCR; /** Line control offset 0x0C */
/** Base address + 0x10: Modem control offset */
union {
struct {
__IO uint32_t DTR :1; /**< Data terminal ready. Write 1 to set DTR high (de-asserted), or read DTR */
__IO uint32_t RTS :1; /**< Request to send. Write 1 to set RTS high (de-asserted), or read RTS */
__IO uint32_t OUTN_CTRL :2; /**< Direct control of out2N and out1N */
__IO uint32_t LOOPBACK :1; /**< Write 1 to enable loop back */
__IO uint32_t PAD0 :3;
__IO uint32_t PD_EN :1; /**< Power down enable active bit, write 1 to enable. Only enabled if PD_EN in IER is set also */
} BITS;
__IO uint32_t WORD;
} MCR; /**< Modem control offset 0x10 */
/** Base address + 0x14: Line status offset */
union {
struct {
__O uint32_t READY :1; /**< Rx data available */
__O uint32_t OVERRUN_ERR :1; /**< Overrun error */
__O uint32_t PARITY_ERR :1; /**< Parity error */
__O uint32_t FRAME_ERR :1; /**< Framing error */
__O uint32_t BREAK_INT :1; /**< Break interrupt is set when output is kept to 0 for more than 1 bit time */
__O uint32_t TX_HOLD_EMPTY :1; /**< Transmit holding register empty */
__O uint32_t TX_EMPTY :1; /**< Transmitter empty */
__O uint32_t FIFO_ERR :1; /**< Receive fifo error */
} BITS;
__O uint32_t WORD;
} LSR; /**< Line status offset 0x14 */
/** Base address + 0x18: Modem status offset */
union {
struct {
__O uint32_t CHG_CTSN :1; /**< CTS change since last MSR read */
__O uint32_t CHG_DSRN :1; /**< DSR change since last MSR read */
__O uint32_t CHG_RIN :1; /**< RI change since last MSR read */
__O uint32_t CHG_DCDN :1; /**< DCD change since last MSR read */
__O uint32_t CURR_CTSN :1; /**< CTS current state, 0 = asserted, 1 = de-asserted */
__O uint32_t CURR_DSRN :1; /**< DSR current state */
__O uint32_t CURR_RIN :1; /**< RI current state */
__O uint32_t CURR_DCDN :1; /**< DCD current state */
} BITS;
__O uint32_t WORD;
} MSR; /**< Modem status offset 0x18 */
/** Base address + 0x1C: Scratch offset*/
__IO uint32_t SCR; /**< Scratch pad register */
/** Base address + 0x0: Receive, transmit and divisor_LSB offset */
union {
__I uint32_t RBR; /**< Received data (8 bits wide) / read only */
__O uint32_t THR; /**< Data to be transmitted (8 bits wide) / write only */
__IO uint32_t DLL; /**< If DLAB = 1. LS byte for input to baud rate generator */
};
/** Base address + 0x4: Interrupt enable and divisor_MSB offset */
union {
union {
struct {
__IO uint32_t RX_DATA_INT :1; /**< Enables the received data interrupt, write 1 to enable */
__IO uint32_t TX_HOLD_INT :1; /**< Enables the transmitter holding interrupt, write 1 to enable */
__IO uint32_t RX_STATUS_INT :1; /**< Enables the receiver line status interrupt, write 1 to enable */
__IO uint32_t MODEM_STATUS_INT :1; /**< Enables the modem status interrupt, write 1 to enable */
__IO uint32_t PAD0 :1;
__IO uint32_t PD_EN :1; /**< Power down enable active bit, write 1 to enable. Only enabled if PD_EN in MCR is set also */
__IO uint32_t PAD1 :2;
} BITS;
__IO uint32_t WORD;
} IER; /** Interrupt enable offset 0x04 */
__IO uint32_t DLM; /**< If DLAB = 1. MS byte for input to baud rate generator */
};
/** Base address + 0x8: Interrupt status and fifo control offset*/
union {
union {
struct {
__I uint32_t INT_PEND :1; /**< Interrupt is pending if 1 */
__I uint32_t INT_ID :3; /**< Interrupt identification: 011-RX Line, 010-Rx Data, 110-char TO, 001-TX empty, 000-Modem status*/
__I uint32_t PAD0 :2;
__I uint32_t FIFO_EN :2; /**< Fifos enabled: 00-disabled, 01/10-undefined, 11-enabled */
} BITS;
__I uint32_t WORD;
} IIR; /** Interrupt status and fifo status offset 0x08 */
union {
struct {
__O uint32_t FIFO_EN :1; /**< FIFO enable, write 1 to enable */
__O uint32_t RX_FIFO_RST :1; /**< RX FIFO reset, write 1 to reset */
__O uint32_t TX_FIFO_RST :1; /**< TX FIFO reset, write 1 to reset */
__O uint32_t DMA_SEL :1; /**< DMA mode select */
__O uint32_t PAD0 :2;
__O uint32_t RX_FIFO_TRIG :2; /**< Receiver FIFO trigger level:00-1byte, 01-4bytes, 10-8bytes, 11-14bytes */
} BITS;
__O uint32_t WORD;
} FCR; /** Fifo control offset 0x08 */
};
/** Base address + 0xC: Line control offset */
union {
struct {
__IO uint32_t CHAR_LEN :2; /**< Number of bits per character: 00-5bits, 01-6bits, 10:7bits, 11:8bits */
__IO uint32_t NUM_STOP :1; /**< Number of stop bits: 0-1bit, 1-2bits */
__IO uint32_t PARITY :3; /**< Parity: xx0-disable, 001-odd, 011-even, 101-stick generated/checked as 1, 111-stick generated/checked as 0 */
__IO uint32_t BREAK :1; /**< Set to 1 to force output to 0, set to 0 to return to normal operation */
__IO uint32_t DLAB :1; /**< Set to 1 to enable the DLL, DLM registers at 0x00 and 0x04 */
} BITS;
__IO uint32_t WORD;
} LCR; /** Line control offset 0x0C */
/** Base address + 0x10: Modem control offset */
union {
struct {
__IO uint32_t DTR :1; /**< Data terminal ready. Write 1 to set DTR high (de-asserted), or read DTR */
__IO uint32_t RTS :1; /**< Request to send. Write 1 to set RTS high (de-asserted), or read RTS */
__IO uint32_t OUTN_CTRL :2; /**< Direct control of out2N and out1N */
__IO uint32_t LOOPBACK :1; /**< Write 1 to enable loop back */
__IO uint32_t PAD0 :3;
__IO uint32_t PD_EN :1; /**< Power down enable active bit, write 1 to enable. Only enabled if PD_EN in IER is set also */
} BITS;
__IO uint32_t WORD;
} MCR; /**< Modem control offset 0x10 */
/** Base address + 0x14: Line status offset */
union {
struct {
__O uint32_t READY :1; /**< Rx data available */
__O uint32_t OVERRUN_ERR :1; /**< Overrun error */
__O uint32_t PARITY_ERR :1; /**< Parity error */
__O uint32_t FRAME_ERR :1; /**< Framing error */
__O uint32_t BREAK_INT :1; /**< Break interrupt is set when output is kept to 0 for more than 1 bit time */
__O uint32_t TX_HOLD_EMPTY :1; /**< Transmit holding register empty */
__O uint32_t TX_EMPTY :1; /**< Transmitter empty */
__O uint32_t FIFO_ERR :1; /**< Receive fifo error */
} BITS;
__O uint32_t WORD;
} LSR; /**< Line status offset 0x14 */
/** Base address + 0x18: Modem status offset */
union {
struct {
__O uint32_t CHG_CTSN :1; /**< CTS change since last MSR read */
__O uint32_t CHG_DSRN :1; /**< DSR change since last MSR read */
__O uint32_t CHG_RIN :1; /**< RI change since last MSR read */
__O uint32_t CHG_DCDN :1; /**< DCD change since last MSR read */
__O uint32_t CURR_CTSN :1; /**< CTS current state, 0 = asserted, 1 = de-asserted */
__O uint32_t CURR_DSRN :1; /**< DSR current state */
__O uint32_t CURR_RIN :1; /**< RI current state */
__O uint32_t CURR_DCDN :1; /**< DCD current state */
} BITS;
__O uint32_t WORD;
} MSR; /**< Modem status offset 0x18 */
/** Base address + 0x1C: Scratch offset*/
__IO uint32_t SCR; /**< Scratch pad register */
} Uart16C550Reg_t, *Uart16C550Reg_pt;
#endif /* UART_16C550_MAP_H_ */

219
hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h
View File

@ -39,122 +39,117 @@
#ifdef REVB
/** Watch Dog Timer Control HW Structure Overlay */
typedef struct {
__IO uint32_t LOAD; /**< Watchdog load value */
__I uint32_t VALUE; /**< Watchdog current value */
union {
struct {
__IO uint32_t INT_EN :1; /**< interrupt event : 0 = disable counter and interrupt , 1 = enable counter and interrupt */
__IO uint32_t RESET_EN :1; /**< Watchdog reset output : 0 = disable 1 = enable */
__IO uint32_t PAD :30; /**< Reserved, read undefined, must read as zeros. */
} BITS;
__IO uint32_t WORD;
} CONTROL;
__IO uint32_t INT_CLEAR; /**< Watchdog interrupt clear */
__I uint32_t RAW_INT_STAT; /**< Raw interrupt status from the counter */
__I uint32_t MASKED_INT_STAT; /**< Enabled interrupt status from the counter */
union {
struct {
__IO uint32_t WRITE_EN :1; /**< write access to all other registers : 0 = enabled(default) , 1 = disabled */
__IO uint32_t REG_WRITE_EN :31; /**< Enable write access to all other registers by writing 0x1ACCE551. Disable it by writing any other value.*/
} BITS;
__IO uint32_t WORD;
} LOCK;
__I uint32_t TEST_CTRL; /**< Integration Test Mode : 0 = disable , 1 = Enable */
union {
struct {
__IO uint32_t VAL_INT :1; /**< Value output on WDOGINT when in Integration Test Mode */
__IO uint32_t VAL_RES :1; /**< Value output on WDOGRES when in Integration Test Mode */
__IO uint32_t PAD:30; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} TEST_OUT;
union {
struct {
__IO uint32_t PART_0 :8; /**< These bits read back as 0x05 */
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PID_REG0;
union {
struct {
__IO uint32_t PART_1 :4; /**< These bits read back as 0x08 */
__IO uint32_t DESIGNER_0 :4; /**< These bits read back as 0x01 */
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PID_REG1;
union {
struct {
__IO uint32_t DESIGNER_1 :4; /**< These bits read back as 0x4 */
__IO uint32_t REVISION :4; /**< These bits read back as 0x0*/
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PID_REG2;
union {
struct {
__IO uint32_t CONFIG :8; /**< These bits read back as 0x00 */
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PID_REG3;
union {
struct {
__IO uint32_t ID0 :8; /**< These bits read back as 0x0D */
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PCELL_ID0;
union {
struct {
__IO uint32_t ID :8; /**< These bits read back as 0xF0*/
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PCELL_ID1;
union {
struct {
__IO uint32_t ID :8; /**< These bits read back as 0x05*/
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PCELL_ID2;
union {
struct {
__IO uint32_t ID :8; /**< These bits read back as 0xB1*/
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PCELL_ID3;
__IO uint32_t LOAD; /**< Watchdog load value */
__I uint32_t VALUE; /**< Watchdog current value */
union {
struct {
__IO uint32_t INT_EN :1; /**< interrupt event : 0 = disable counter and interrupt , 1 = enable counter and interrupt */
__IO uint32_t RESET_EN :1; /**< Watchdog reset output : 0 = disable 1 = enable */
__IO uint32_t PAD :30; /**< Reserved, read undefined, must read as zeros. */
} BITS;
__IO uint32_t WORD;
} CONTROL;
__IO uint32_t INT_CLEAR; /**< Watchdog interrupt clear */
__I uint32_t RAW_INT_STAT; /**< Raw interrupt status from the counter */
__I uint32_t MASKED_INT_STAT; /**< Enabled interrupt status from the counter */
union {
struct {
__IO uint32_t WRITE_EN :1; /**< write access to all other registers : 0 = enabled(default) , 1 = disabled */
__IO uint32_t REG_WRITE_EN :31; /**< Enable write access to all other registers by writing 0x1ACCE551. Disable it by writing any other value.*/
} BITS;
__IO uint32_t WORD;
} LOCK;
__I uint32_t TEST_CTRL; /**< Integration Test Mode : 0 = disable , 1 = Enable */
union {
struct {
__IO uint32_t VAL_INT :1; /**< Value output on WDOGINT when in Integration Test Mode */
__IO uint32_t VAL_RES :1; /**< Value output on WDOGRES when in Integration Test Mode */
__IO uint32_t PAD:30; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} TEST_OUT;
union {
struct {
__IO uint32_t PART_0 :8; /**< These bits read back as 0x05 */
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PID_REG0;
union {
struct {
__IO uint32_t PART_1 :4; /**< These bits read back as 0x08 */
__IO uint32_t DESIGNER_0 :4; /**< These bits read back as 0x01 */
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PID_REG1;
union {
struct {
__IO uint32_t DESIGNER_1 :4; /**< These bits read back as 0x4 */
__IO uint32_t REVISION :4; /**< These bits read back as 0x0*/
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PID_REG2;
union {
struct {
__IO uint32_t CONFIG :8; /**< These bits read back as 0x00 */
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PID_REG3;
union {
struct {
__IO uint32_t ID0 :8; /**< These bits read back as 0x0D */
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PCELL_ID0;
union {
struct {
__IO uint32_t ID :8; /**< These bits read back as 0xF0*/
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PCELL_ID1;
union {
struct {
__IO uint32_t ID :8; /**< These bits read back as 0x05*/
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PCELL_ID2;
union {
struct {
__IO uint32_t ID :8; /**< These bits read back as 0xB1*/
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PCELL_ID3;
} WdtReg_t, *WdtReg_pt;
#endif /* REVB */
#ifdef REVD
typedef struct
{
__IO uint32_t LOAD; /**< 0x4000A000 Contains the value from which the counter is decremented. When this register is written to the count is immediately restarted from the new value. The minimum valid value is 1. */
__I uint32_t CURRENT_VALUE; /**< 0x4000A004 Gives the current value of the decrementing counter */
union
{
struct
{
__IO uint32_t WDT_EN :1; /**< Watchdog enable, 0 – Watchdog disabled, 1 – Watchdog enabled */
} BITS;
__IO uint32_t WORD;
} CONTROL; /* 0x4000A008 */
__O uint32_t KICK; /**< 0x4000A00C A write of any value to this register reloads the value register from the load register */
__O uint32_t LOCK; /**< 0x4000A010 Use of this register causes write-access to all other registers to be disabled. This is to prevent rogue software from disabling the watchdog functionality. Writing a value of 0x1ACCE551 enables write access to all other registers. Writing any other value disables write access. A read from this register only returns the bottom bit…, 0 – Write access is enabled, 1 – Write access is disabled */
union
{
struct
{
__I uint32_t WRITE_BUSY_ANY :1; /**< Busy writing any register */
__I uint32_t WRITE_BUSY_LOAD :1; /**< Busy writing the load register */
__I uint32_t WRITE_BUSY_CONTROL :1; /**< Busy writing the control enable register */
__IO uint32_t WRITE_ERROR :1; /**< Error bit. Set when write occurs before previous write completes (busy) */
} BITS;
__IO uint32_t WORD;
} STATUS; /* 0x4000A014 */
typedef struct {
__IO uint32_t LOAD; /**< 0x4000A000 Contains the value from which the counter is decremented. When this register is written to the count is immediately restarted from the new value. The minimum valid value is 1. */
__I uint32_t CURRENT_VALUE; /**< 0x4000A004 Gives the current value of the decrementing counter */
union {
struct {
__IO uint32_t WDT_EN :1; /**< Watchdog enable, 0 – Watchdog disabled, 1 – Watchdog enabled */
} BITS;
__IO uint32_t WORD;
} CONTROL; /* 0x4000A008 */
__O uint32_t KICK; /**< 0x4000A00C A write of any value to this register reloads the value register from the load register */
__O uint32_t LOCK; /**< 0x4000A010 Use of this register causes write-access to all other registers to be disabled. This is to prevent rogue software from disabling the watchdog functionality. Writing a value of 0x1ACCE551 enables write access to all other registers. Writing any other value disables write access. A read from this register only returns the bottom bit…, 0 – Write access is enabled, 1 – Write access is disabled */
union {
struct {
__I uint32_t WRITE_BUSY_ANY :1; /**< Busy writing any register */
__I uint32_t WRITE_BUSY_LOAD :1; /**< Busy writing the load register */
__I uint32_t WRITE_BUSY_CONTROL :1; /**< Busy writing the control enable register */
__IO uint32_t WRITE_ERROR :1; /**< Error bit. Set when write occurs before previous write completes (busy) */
} BITS;
__IO uint32_t WORD;
} STATUS; /* 0x4000A014 */
} WdtReg_t, *WdtReg_pt;
#endif /* REVD */
#endif /* WDT_MAP_H_ */

71
tools/add_fib.py
View File

@ -1,33 +1,24 @@
#!/usr/bin/env python
"""
@copyright (c) 2012 ON Semiconductor. All rights reserved.
ON Semiconductor is supplying this software for use with ON Semiconductor
processor based microcontrollers only.
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
"""
# CMSIS-DAP Interface Firmware
# Copyright (c) 2009-2013 ARM Limited
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
from __future__ import absolute_import
from __future__ import print_function
import argparse
import itertools
import binascii
import intelhex
import os
FIB_BASE = 0x2000
FLASH_BASE = 0x3000
FW_REV = 0x01000100 #todo: determine if revision can be passed from yotta
FW_REV = 0x01000100
def ranges(i):
for _, b in itertools.groupby(enumerate(i), lambda x_y: x_y[1] - x_y[0]):
b = list(b)
@ -35,31 +26,9 @@ def ranges(i):
def add_fib_at_start(arginput):
#parser = argparse.ArgumentParser(description='Firmware Information Block generation script')
#parser.add_argument("input", type=str, help="bin file to read from.")
#args = parser.parse_args()
#input_file = args.input + "_orig.bin"
#output_file = args.input #use same name, does not include extension
#file_name_hex = args.input + ".hex"
#file_name_bin = args.input + ".bin"
print("inputfile", arginput)
input_file = arginput + ".bin"
output_file = arginput #use same name, does not include extension
file_name_hex = arginput + "_fib.hex"
file_name_bin = arginput + ".bin"
print("inputfile", input_file)
print("output_file", output_file)
print("file_name_hex", file_name_hex)
print("file_name_bin", file_name_bin)
# Import intelhex if avaialable, otherwise fail
try:
from intelhex import IntelHex
except:
return fail('error: You do not have \'intelhex\' installed. Please run \'pip install intelhex\' then retry.')
# Read in hex file
input_hex_file = intelhex.IntelHex()
@ -81,7 +50,8 @@ def add_fib_at_start(arginput):
start = min(min(start_end_pairs))
end = max(max(start_end_pairs))
assert start >= FLASH_BASE, ("Error - start 0x%x less than begining of user flash area" %start)
assert start >= FLASH_BASE, ("Error - start 0x%x less than begining of user\
flash area" %start)
# Compute checksum over the range (don't include data at location of crc)
size = end - start + 1
data = input_hex_file.tobinarray(start=start, size=size)
@ -91,11 +61,12 @@ def add_fib_at_start(arginput):
checksum = (start + size + crc32 + fw_rev) & 0xFFFFFFFF
print("Writing FIB: base 0x%08X, size 0x%08X, crc32 0x%08X, fw rev 0x%08X, checksum 0x%08X" % (start, size, crc32, fw_rev, checksum))
print("Writing FIB: base 0x%08X, size 0x%08X, crc32 0x%08X, fw rev 0x%08X,\
checksum 0x%08X" % (start, size, crc32, fw_rev, checksum))
#expected initial values used by daplink to validate that it is a valid bin file
#added as dummy values in this file because the fib area preceeds the application area
#the bootloader will ignore these dummy values
#expected initial values used by daplink to validate that it is a valid bin
#file added as dummy values in this file because the fib area preceeds the
#application area the bootloader will ignore these dummy values
# 00 is stack pointer (RAM address)
# 04 is Reset vector (FLASH address)
# 08 NMI_Handler (FLASH address)
@ -109,7 +80,8 @@ def add_fib_at_start(arginput):
#expected fib structure
#typedef struct fib{
#uint32_t base; /**< Base offset of firmware, indicating what flash the firmware is in. (will never be 0x11111111) */
#uint32_t base; /**< Base offset of firmware, indicating what flash the
# firmware is in. (will never be 0x11111111) */
#uint32_t size; /**< Size of the firmware */
#uint32_t crc; /**< CRC32 for firmware correctness check */
#uint32_t rev; /**< Revision number */
@ -175,7 +147,7 @@ def add_fib_at_start(arginput):
#pad the rest of the file
for i in range(fib_start + dummy_fib_size + fib_size, user_code_start):
output_hex_file[i] = 0xFF
output_hex_file[i] = 0xFF
#merge two hex files
output_hex_file.merge(input_hex_file, overlap='error')
@ -183,3 +155,4 @@ def add_fib_at_start(arginput):
# Write out file(s)
output_hex_file.tofile(file_name_hex, 'hex')
output_hex_file.tofile(file_name_bin, 'bin')

2
tools/settings.py
View File

@ -37,7 +37,7 @@ GCC_ARM_PATH = ""
GCC_CR_PATH = "C:/code_red/RedSuite_4.2.0_349/redsuite/Tools/bin"
# IAR
IAR_PATH = "C:\\tools_w32\IAR7.7\\arm"
IAR_PATH = "C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.3/arm"
# Goanna static analyser. Please overload it in mbed_settings.py
GOANNA_PATH = "c:/Program Files (x86)/RedLizards/Goanna Central 3.2.3/bin"