mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #5813 from TomoYamanaka/master
Revise the structure in RZ_A1 related directorypull/5862/head
Martin Kojtal
GitHub
commit
2d83463f9c
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@ -23,4 +23,11 @@
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#define MEM_SIZE (1600 * 16)
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#define MEMP_NUM_TCP_SEG 32
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#define TCP_MSS 1460
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#define PBUF_POOL_SIZE 16
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#define TCP_SND_BUF (8 * TCP_MSS)
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#define TCP_WND (TCP_MSS * 8)
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#define PBUF_POOL_BUFSIZE 1600
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#endif
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@ -5,11 +5,73 @@
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#include "mbed_interface.h"
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#include "ethernet_api.h"
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#include "ethernetext_api.h"
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#include "platform/mbed_toolchain.h"
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#define RECV_TASK_PRI (osPriorityNormal)
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#define PHY_TASK_PRI (osPriorityNormal)
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#define PHY_TASK_WAIT (200)
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WEAK int ethernetext_init(ethernet_cfg_t *p_ethcfg)
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{
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return -1;
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}
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WEAK void ethernetext_start_stop(int32_t mode)
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{
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}
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WEAK int ethernetext_chk_link_mode(void)
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{
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return NEGO_FAIL;
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}
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WEAK void ethernetext_set_link_mode(int32_t link)
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{
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}
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WEAK int ethernet_init(void)
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{
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return -1;
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}
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WEAK void ethernet_free(void)
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{
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}
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WEAK int ethernet_write(const char *data, int size)
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{
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return 0;
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}
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WEAK int ethernet_send(void)
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{
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return 0;
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}
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WEAK int ethernet_receive(void)
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{
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return 0;
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}
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WEAK int ethernet_read(char *data, int size)
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{
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return 0;
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}
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WEAK void ethernet_address(char *mac)
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{
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}
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WEAK int ethernet_link(void)
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{
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return 0;
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}
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WEAK void ethernet_set_link(int speed, int duplex)
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{
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}
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/* memory */
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static sys_sem_t recv_ready_sem; /* receive ready semaphore */
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@ -195,8 +257,8 @@ err_t eth_arch_enetif_init(struct netif *netif)
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sys_sem_new(&recv_ready_sem, 0);
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/* task */
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sys_thread_new("rza1_emac_rx_thread", rza1_recv_task, netif, DEFAULT_THREAD_STACKSIZE, RECV_TASK_PRI);
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sys_thread_new("rza1_emac_phy_thread", rza1_phy_task, netif, DEFAULT_THREAD_STACKSIZE, PHY_TASK_PRI);
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sys_thread_new("rza1_recv_task", rza1_recv_task, netif, DEFAULT_THREAD_STACKSIZE, RECV_TASK_PRI);
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sys_thread_new("rza1_phy_task", rza1_phy_task, netif, DEFAULT_THREAD_STACKSIZE, PHY_TASK_PRI);
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return ERR_OK;
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}
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@ -1,26 +0,0 @@
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/* Copyright (C) 2012 mbed.org, MIT License
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
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* and associated documentation files (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge, publish, distribute,
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* sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all copies or
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* substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef LWIPOPTS_CONF_H
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#define LWIPOPTS_CONF_H
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#define LWIP_TRANSPORT_ETHERNET 1
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#define MEM_SIZE (1600 * 16)
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#endif
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@ -1,210 +0,0 @@
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#include "lwip/opt.h"
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#include "lwip/tcpip.h"
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#include "netif/etharp.h"
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#include "lwip/ethip6.h"
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#include "mbed_interface.h"
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#include "ethernet_api.h"
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#include "ethernetext_api.h"
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#define RECV_TASK_PRI (osPriorityNormal)
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#define PHY_TASK_PRI (osPriorityNormal)
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#define PHY_TASK_WAIT (200)
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/* memory */
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static sys_sem_t recv_ready_sem; /* receive ready semaphore */
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/* function */
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static void rza1_recv_task(void *arg);
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static void rza1_phy_task(void *arg);
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#if LWIP_IPV4
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static err_t rza1_etharp_output_ipv4(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr);
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#endif
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#if LWIP_IPV6
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static err_t rza1_etharp_output_ipv6(struct netif *netif, struct pbuf *q, const ip6_addr_t *ipaddr);
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#endif
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static err_t rza1_low_level_output(struct netif *netif, struct pbuf *p);
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static void rza1_recv_callback(void);
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static void rza1_recv_task(void *arg) {
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struct netif *netif = (struct netif*)arg;
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u16_t recv_size;
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struct pbuf *p;
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int cnt;
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while (1) {
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sys_arch_sem_wait(&recv_ready_sem, 0);
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for (cnt = 0; cnt < 16; cnt++) {
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recv_size = ethernet_receive();
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if (recv_size != 0) {
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p = pbuf_alloc(PBUF_RAW, recv_size, PBUF_RAM);
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if (p != NULL) {
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(void)ethernet_read((char *)p->payload, p->len);
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/* full packet send to tcpip_thread to process */
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if (netif->input(p, netif) != ERR_OK) {
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/* Free buffer */
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pbuf_free(p);
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}
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}
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} else {
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break;
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}
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}
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}
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}
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static void rza1_phy_task(void *arg) {
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struct netif *netif = (struct netif*)arg;
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s32_t connect_sts = 0; /* 0: disconnect, 1:connect */
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s32_t link_sts;
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s32_t link_mode_new = NEGO_FAIL;
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s32_t link_mode_old = NEGO_FAIL;
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while (1) {
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link_sts = ethernet_link();
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if (link_sts == 1) {
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link_mode_new = ethernetext_chk_link_mode();
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if (link_mode_new != link_mode_old) {
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if (connect_sts == 1) {
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tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_down, (void*) netif, 1);
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}
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if (link_mode_new != NEGO_FAIL) {
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ethernetext_set_link_mode(link_mode_new);
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tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_up, (void*) netif, 1);
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connect_sts = 1;
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}
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}
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} else {
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if (connect_sts != 0) {
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tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_down, (void*) netif, 1);
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link_mode_new = NEGO_FAIL;
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connect_sts = 0;
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}
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}
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link_mode_old = link_mode_new;
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osDelay(PHY_TASK_WAIT);
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}
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}
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#if LWIP_IPV4
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static err_t rza1_etharp_output_ipv4(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr) {
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/* Only send packet is link is up */
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if (netif->flags & NETIF_FLAG_LINK_UP) {
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return etharp_output(netif, q, ipaddr);
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}
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return ERR_CONN;
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}
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#endif
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#if LWIP_IPV6
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static err_t rza1_etharp_output_ipv6(struct netif *netif, struct pbuf *q, const ip6_addr_t *ipaddr) {
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/* Only send packet is link is up */
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if (netif->flags & NETIF_FLAG_LINK_UP) {
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return ethip6_output(netif, q, ipaddr);
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}
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return ERR_CONN;
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}
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#endif
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static err_t rza1_low_level_output(struct netif *netif, struct pbuf *p) {
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struct pbuf *q;
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s32_t cnt;
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err_t err = ERR_MEM;
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s32_t write_size = 0;
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if ((p->payload != NULL) && (p->len != 0)) {
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/* If the first data can't be written, transmit descriptor is full. */
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for (cnt = 0; cnt < 100; cnt++) {
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write_size = ethernet_write((char *)p->payload, p->len);
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if (write_size != 0) {
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break;
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}
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osDelay(1);
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}
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if (write_size != 0) {
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for (q = p->next; q != NULL; q = q->next) {
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(void)ethernet_write((char *)q->payload, q->len);
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}
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if (ethernet_send() == 1) {
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err = ERR_OK;
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}
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}
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}
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return err;
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}
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static void rza1_recv_callback(void) {
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sys_sem_signal(&recv_ready_sem);
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}
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err_t eth_arch_enetif_init(struct netif *netif)
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{
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ethernet_cfg_t ethcfg;
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/* set MAC hardware address */
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#if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
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netif->hwaddr[0] = MBED_MAC_ADDR_0;
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netif->hwaddr[1] = MBED_MAC_ADDR_1;
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netif->hwaddr[2] = MBED_MAC_ADDR_2;
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netif->hwaddr[3] = MBED_MAC_ADDR_3;
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netif->hwaddr[4] = MBED_MAC_ADDR_4;
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netif->hwaddr[5] = MBED_MAC_ADDR_5;
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#else
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mbed_mac_address((char *)netif->hwaddr);
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#endif
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netif->hwaddr_len = ETH_HWADDR_LEN;
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/* maximum transfer unit */
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netif->mtu = 1500;
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/* device capabilities */
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netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET;
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#ifdef LWIP_IGMP
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netif->flags |= NETIF_FLAG_IGMP;
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#endif
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#if LWIP_IPV6_MLD
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netif->flags |= NETIF_FLAG_MLD6;
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#endif
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#if LWIP_NETIF_HOSTNAME
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/* Initialize interface hostname */
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netif->hostname = "lwiprza1";
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#endif /* LWIP_NETIF_HOSTNAME */
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netif->name[0] = 'e';
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netif->name[1] = 'n';
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#if LWIP_IPV4
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netif->output = rza1_etharp_output_ipv4;
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#endif
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#if LWIP_IPV6
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netif->output_ip6 = rza1_etharp_output_ipv6;
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#endif
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netif->linkoutput = rza1_low_level_output;
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/* Initialize the hardware */
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ethcfg.int_priority = 6;
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ethcfg.recv_cb = &rza1_recv_callback;
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ethcfg.ether_mac = (char *)netif->hwaddr;
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ethernetext_init(ðcfg);
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/* semaphore */
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sys_sem_new(&recv_ready_sem, 0);
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/* task */
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sys_thread_new("rza1_emac_rx_thread", rza1_recv_task, netif, DEFAULT_THREAD_STACKSIZE, RECV_TASK_PRI);
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sys_thread_new("rza1_emac_phy_thread", rza1_phy_task, netif, DEFAULT_THREAD_STACKSIZE, PHY_TASK_PRI);
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return ERR_OK;
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}
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void eth_arch_enable_interrupts(void) {
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ethernetext_start_stop(1);
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}
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void eth_arch_disable_interrupts(void) {
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ethernetext_start_stop(0);
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}
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@ -1,71 +0,0 @@
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/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
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/**************************************************************************//**
|
||||
* @file RZ_A1_Init.h
|
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* $Rev: 531 $
|
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* $Date:: 2013-04-16 13:07:35 +0900#$
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* @brief RZ_A1 Initialize
|
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******************************************************************************/
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#ifndef RZ_A1_INIT_H
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#define RZ_A1_INIT_H
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|
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/******************************************************************************
|
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Includes <System Includes> , "Project Includes"
|
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******************************************************************************/
|
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#include <stdio.h>
|
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#include <stdbool.h>
|
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#include "iodefine.h"
|
||||
|
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#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif /* __cplusplus */
|
||||
|
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|
||||
/******************************************************************************
|
||||
Typedef definitions
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
Macro definitions
|
||||
******************************************************************************/
|
||||
|
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/******************************************************************************
|
||||
Variable Externs
|
||||
******************************************************************************/
|
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|
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/******************************************************************************
|
||||
Functions Prototypes
|
||||
******************************************************************************/
|
||||
|
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void RZ_A1_SetSramWriteEnable(void);
|
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void RZ_A1_InitClock(void);
|
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int RZ_A1_IsClockMode0(void);
|
||||
void RZ_A1_InitBus(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* RZ_A1_INIT_H */
|
||||
|
|
@ -1,48 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2015 ARM Limited. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,85 +0,0 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/******************************************************************************
|
||||
* File Name : dev_drv.h
|
||||
* $Rev: 809 $
|
||||
* $Date:: 2014-04-09 15:06:36 +0900#$
|
||||
* Description : Device driver header
|
||||
******************************************************************************/
|
||||
#ifndef DEV_DRV_H
|
||||
#define DEV_DRV_H
|
||||
|
||||
/******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Typedef definitions
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Macro definitions
|
||||
******************************************************************************/
|
||||
/* ==== Arguments, Return values ==== */
|
||||
#define DEVDRV_SUCCESS (0) /* Success */
|
||||
#define DEVDRV_ERROR (-1) /* Failure */
|
||||
|
||||
/* ==== Flags ==== */
|
||||
#define DEVDRV_FLAG_OFF (0) /* Flag OFF */
|
||||
#define DEVDRV_FLAG_ON (1) /* Flag ON */
|
||||
|
||||
/* ==== Channels ==== */
|
||||
typedef enum devdrv_ch
|
||||
{
|
||||
DEVDRV_CH_0, /* Channel 0 */
|
||||
DEVDRV_CH_1, /* Channel 1 */
|
||||
DEVDRV_CH_2, /* Channel 2 */
|
||||
DEVDRV_CH_3, /* Channel 3 */
|
||||
DEVDRV_CH_4, /* Channel 4 */
|
||||
DEVDRV_CH_5, /* Channel 5 */
|
||||
DEVDRV_CH_6, /* Channel 6 */
|
||||
DEVDRV_CH_7, /* Channel 7 */
|
||||
DEVDRV_CH_8, /* Channel 8 */
|
||||
DEVDRV_CH_9, /* Channel 9 */
|
||||
DEVDRV_CH_10, /* Channel 10 */
|
||||
DEVDRV_CH_11, /* Channel 11 */
|
||||
DEVDRV_CH_12, /* Channel 12 */
|
||||
DEVDRV_CH_13, /* Channel 13 */
|
||||
DEVDRV_CH_14, /* Channel 14 */
|
||||
DEVDRV_CH_15 /* Channel 15 */
|
||||
} devdrv_ch_t;
|
||||
|
||||
/******************************************************************************
|
||||
Variable Externs
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Functions Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
#endif /* DEV_DRV_H */
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : rza_io_regrw.h
|
||||
* $Rev: 1135 $
|
||||
* $Date:: 2014-08-08 10:11:30 +0900#$
|
||||
* Description : Low level register read/write header
|
||||
*******************************************************************************/
|
||||
#ifndef RZA_IO_REGRW_H
|
||||
#define RZA_IO_REGRW_H
|
||||
|
||||
/******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
******************************************************************************/
|
||||
/* ==== includes each bit mask header ==== */
|
||||
#include "cpg_iobitmask.h"
|
||||
#include "intc_iobitmask.h"
|
||||
#include "bsc_iobitmask.h"
|
||||
#include "dmac_iobitmask.h"
|
||||
#include "mtu2_iobitmask.h"
|
||||
#include "ostm_iobitmask.h"
|
||||
#include "scif_iobitmask.h"
|
||||
#include "rspi_iobitmask.h"
|
||||
#include "riic_iobitmask.h"
|
||||
#include "usb_iobitmask.h"
|
||||
#include "gpio_iobitmask.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/******************************************************************************
|
||||
Typedef definitions
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Macro definitions
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Variable Externs
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Functions Prototypes
|
||||
******************************************************************************/
|
||||
void RZA_IO_RegWrite_8 (volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint8_t mask);
|
||||
void RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask);
|
||||
void RZA_IO_RegWrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask);
|
||||
uint8_t RZA_IO_RegRead_8 (volatile uint8_t * ioreg, uint8_t shift, uint8_t mask);
|
||||
uint16_t RZA_IO_RegRead_16 (volatile uint16_t * ioreg, uint16_t shift, uint16_t mask);
|
||||
uint32_t RZA_IO_RegRead_32 (volatile uint32_t * ioreg, uint32_t shift, uint32_t mask);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* RZA_IO_REGRW_H */
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -1,84 +0,0 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @file nvic_wrapper.h
|
||||
* $Rev: $
|
||||
* $Date:: $
|
||||
* @brief Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9)
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef NVIC_WRAPPER_H
|
||||
#define NVIC_WRAPPER_H
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
******************************************************************************/
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Typedef definitions
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
Macro definitions
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
Variable Externs
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
Functions Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/* NVIC functions */
|
||||
void NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
|
||||
uint32_t NVIC_GetPriorityGrouping(void);
|
||||
void NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||
void NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||
uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||
void NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||
void NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||
uint32_t NVIC_GetActive(IRQn_Type IRQn);
|
||||
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
|
||||
uint32_t NVIC_GetPriority(IRQn_Type IRQn);
|
||||
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority);
|
||||
void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
|
||||
void NVIC_SystemReset(void);
|
||||
/* SysTick function */
|
||||
uint32_t SysTick_Config(uint32_t ticks);
|
||||
/* Debug In/Output function */
|
||||
uint32_t ITM_SendChar (uint32_t ch);
|
||||
int32_t ITM_ReceiveChar (void);
|
||||
int32_t ITM_CheckChar (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* NVIC_WRAPPER_H */
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2013 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : r_typedefs.h
|
||||
* $Rev: 788 $
|
||||
* $Date:: 2014-04-07 18:57:13 +0900#$
|
||||
* Description : basic type definition
|
||||
******************************************************************************/
|
||||
#ifndef R_TYPEDEFS_H
|
||||
#define R_TYPEDEFS_H
|
||||
|
||||
/******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
******************************************************************************/
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#if defined(__ARM_NEON__)
|
||||
|
||||
#include <arm_neon.h>
|
||||
|
||||
#else /* __ARM_NEON__ */
|
||||
|
||||
typedef float float32_t;
|
||||
typedef double float64_t;
|
||||
|
||||
#endif /* __ARM_NEON__ */
|
||||
|
||||
/******************************************************************************
|
||||
Typedef definitions
|
||||
******************************************************************************/
|
||||
typedef char char_t;
|
||||
typedef int bool_t;
|
||||
typedef int int_t;
|
||||
typedef long double float128_t;
|
||||
typedef signed long long_t;
|
||||
typedef unsigned long ulong_t;
|
||||
|
||||
#endif /* R_TYPEDEFS_H */
|
||||
|
||||
|
|
@ -1,200 +0,0 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : rza_io_regrw.c
|
||||
* $Rev: 1121 $
|
||||
* $Date:: 2014-08-06 17:09:53 +0900#$
|
||||
* Description : Low level register read/write
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
******************************************************************************/
|
||||
#include "r_typedefs.h"
|
||||
|
||||
#ifdef __CC_ARM
|
||||
#pragma arm section code = "CODE_IO_REGRW"
|
||||
#pragma arm section rodata = "CONST_IO_REGRW"
|
||||
#pragma arm section rwdata = "DATA_IO_REGRW"
|
||||
#pragma arm section zidata = "BSS_IO_REGRW"
|
||||
#endif
|
||||
|
||||
/******************************************************************************
|
||||
Typedef definitions
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Macro definitions
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Private global variables and functions
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Function Name: RZA_IO_RegWrite_8
|
||||
* Description : IO register 8-bit write
|
||||
* Arguments : volatile uint8_t * ioreg : IO register for writing
|
||||
* : : Use register definition name of the
|
||||
* : : iodefine.h
|
||||
* : uint8_t write_value : Write value for the IO register
|
||||
* : uint8_t shift : The number of left shifts to the
|
||||
* : : target bit
|
||||
* : uint8_t mask : Mask value for the IO register
|
||||
* : : (Target bit : "1")
|
||||
* Return Value : None
|
||||
******************************************************************************/
|
||||
void RZA_IO_RegWrite_8(volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint8_t mask)
|
||||
{
|
||||
uint8_t reg_value;
|
||||
|
||||
reg_value = *ioreg; /* Read from register */
|
||||
reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */
|
||||
*ioreg = reg_value; /* Write to register */
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function Name: RZA_IO_RegWrite_16
|
||||
* Description : IO register 16-bit write
|
||||
* Arguments : volatile uint16_t * ioreg : IO register for writing
|
||||
* : : Use register definition name of the
|
||||
* : : iodefine.h
|
||||
* : uint16_t write_value : Write value for the IO register
|
||||
* : uint16_t shift : The number of left shifts to the
|
||||
* : : target bit
|
||||
* : uint16_t mask : Mask value for the IO register
|
||||
* : : (Target bit : "1")
|
||||
* Return Value : None
|
||||
******************************************************************************/
|
||||
void RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask)
|
||||
{
|
||||
uint16_t reg_value;
|
||||
|
||||
reg_value = *ioreg; /* Read from register */
|
||||
reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */
|
||||
*ioreg = reg_value; /* Write to register */
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function Name: RZA_IO_RegWrite_32
|
||||
* Description : IO register 32-bit write
|
||||
* Arguments : volatile uint32_t * ioreg : IO register for writing
|
||||
* : : Use register definition name of the
|
||||
* : : iodefine.h
|
||||
* : uint32_t write_value : Write value for the IO register
|
||||
* : uint32_t shift : The number of left shifts to the
|
||||
* : : target bit
|
||||
* : uint32_t mask : Mask value for the IO register
|
||||
* : : (Target bit : "1")
|
||||
* Return Value : None
|
||||
******************************************************************************/
|
||||
void RZA_IO_RegWrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask)
|
||||
{
|
||||
uint32_t reg_value;
|
||||
|
||||
reg_value = *ioreg; /* Read from register */
|
||||
reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */
|
||||
*ioreg = reg_value; /* Write to register */
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function Name: RZA_IO_RegRead_8
|
||||
* Description : IO register 8-bit read
|
||||
* Arguments : volatile uint8_t * ioreg : IO register for reading
|
||||
* : : Use register definition name of the
|
||||
* : : iodefine.h
|
||||
* : uint8_t shift : The number of right shifts to the
|
||||
* : : target bit
|
||||
* : uint8_t mask : Mask bit for the IO register
|
||||
* : : (Target bit: "1")
|
||||
* Return Value : uint8_t : Value of the obtained target bit
|
||||
******************************************************************************/
|
||||
uint8_t RZA_IO_RegRead_8(volatile uint8_t * ioreg, uint8_t shift, uint8_t mask)
|
||||
{
|
||||
uint8_t reg_value;
|
||||
|
||||
reg_value = *ioreg; /* Read from register */
|
||||
reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */
|
||||
|
||||
return reg_value;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function Name: RZA_IO_RegRead_16
|
||||
* Description : IO register 16-bit read
|
||||
* Arguments : volatile uint16_t * ioreg : IO register for reading
|
||||
* : : Use register definition name of the
|
||||
* : : iodefine.h
|
||||
* : uint16_t shift : The number of right shifts to the
|
||||
* : : target bit
|
||||
* : uint16_t mask : Mask bit for the IO register
|
||||
* : : (Target bit: "1")
|
||||
* Return Value : uint16_t : Value of the obtained target bit
|
||||
******************************************************************************/
|
||||
uint16_t RZA_IO_RegRead_16(volatile uint16_t * ioreg, uint16_t shift, uint16_t mask)
|
||||
{
|
||||
uint16_t reg_value;
|
||||
|
||||
reg_value = *ioreg; /* Read from register */
|
||||
reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */
|
||||
|
||||
return reg_value;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function Name: RZA_IO_RegRead_32
|
||||
* Description : IO register 32-bit read
|
||||
* Arguments : volatile uint32_t * ioreg : IO register for reading
|
||||
* : : Use register definition name of the
|
||||
* : : iodefine.h
|
||||
* : uint32_t shift : The number of right shifts to the
|
||||
* : : target bit
|
||||
* : uint32_t mask : Mask bit for the IO register
|
||||
* : : (Target bit: "1")
|
||||
* Return Value : uint32_t : Value of the obtained target bit
|
||||
******************************************************************************/
|
||||
uint32_t RZA_IO_RegRead_32(volatile uint32_t * ioreg, uint32_t shift, uint32_t mask)
|
||||
{
|
||||
uint32_t reg_value;
|
||||
|
||||
reg_value = *ioreg; /* Read from register */
|
||||
reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */
|
||||
|
||||
return reg_value;
|
||||
}
|
||||
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -1,20 +0,0 @@
|
|||
|
||||
/* PHY link mode */
|
||||
#define NEGO_FAIL (0)
|
||||
#define HALF_10M (1)
|
||||
#define FULL_10M (2)
|
||||
#define HALF_TX (3)
|
||||
#define FULL_TX (4)
|
||||
|
||||
typedef void (ethernetext_cb_fnc)(void);
|
||||
|
||||
typedef struct tag_ethernet_cfg {
|
||||
int int_priority;
|
||||
ethernetext_cb_fnc *recv_cb;
|
||||
char *ether_mac;
|
||||
} ethernet_cfg_t;
|
||||
|
||||
extern int ethernetext_init(ethernet_cfg_t *p_ethcfg);
|
||||
extern void ethernetext_start_stop(int32_t mode);
|
||||
extern int ethernetext_chk_link_mode(void);
|
||||
extern void ethernetext_set_link_mode(int32_t link);
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
#ifndef __GPIO_ADDRDEFINE__
|
||||
#define __GPIO_ADDRDEFINE__
|
||||
|
||||
#define GPIO_BASE ((long)0xFCFE3000uL) /* GPIO */
|
||||
|
||||
#define PORT(n) (volatile unsigned short *)(GPIO_BASE + 0x000 + ((n)*4))
|
||||
#define PSR(n) (volatile unsigned long *)(GPIO_BASE + 0x100 + ((n)*4))
|
||||
#define PPR(n) (volatile unsigned short *)(GPIO_BASE + 0x200 + ((n)*4))
|
||||
#define PM(n) (volatile unsigned short *)(GPIO_BASE + 0x300 + ((n)*4))
|
||||
#define PMC(n) (volatile unsigned short *)(GPIO_BASE + 0x400 + ((n)*4))
|
||||
#define PFC(n) (volatile unsigned short *)(GPIO_BASE + 0x500 + ((n)*4))
|
||||
#define PFCE(n) (volatile unsigned short *)(GPIO_BASE + 0x600 + ((n)*4))
|
||||
#define PNOT(n) (volatile unsigned short *)(GPIO_BASE + 0x700 + ((n)*4))
|
||||
#define PMSR(n) (volatile unsigned long *)(GPIO_BASE + 0x800 + ((n)*4))
|
||||
#define PMCSR(n) (volatile unsigned long *)(GPIO_BASE + 0x900 + ((n)*4))
|
||||
#define PFCAE(n) (volatile unsigned short *)(GPIO_BASE + 0xa00 + ((n)*4))
|
||||
#define PIBC(n) (volatile unsigned short *)(GPIO_BASE + 0x4000 +((n)*4))
|
||||
#define PBDC(n) (volatile unsigned short *)(GPIO_BASE + 0x4100 +((n)*4))
|
||||
#define PIPC(n) (volatile unsigned short *)(GPIO_BASE + 0x4200 +((n)*4))
|
||||
|
||||
#endif/*__GPIO_ADDRDEFINE__*/
|
||||
|
||||
|
|
@ -1,51 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_GPIO_OBJECT_H
|
||||
#define MBED_GPIO_OBJECT_H
|
||||
|
||||
#include "mbed_assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
PinName pin;
|
||||
uint32_t mask;
|
||||
|
||||
__IO uint32_t *reg_dir;
|
||||
__IO uint32_t *reg_set;
|
||||
__I uint32_t *reg_in;
|
||||
__IO uint32_t *reg_buf;
|
||||
} gpio_t;
|
||||
|
||||
static inline void gpio_write(gpio_t *obj, int value) {
|
||||
*obj->reg_set = (obj->mask << 16) | ((value != 0) ? obj->mask : 0);
|
||||
}
|
||||
|
||||
static inline int gpio_read(gpio_t *obj) {
|
||||
return ((*obj->reg_in & obj->mask) ? 1 : 0);
|
||||
}
|
||||
|
||||
static inline int gpio_is_connected(const gpio_t *obj) {
|
||||
return obj->pin != (PinName)NC;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,84 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_OBJECTS_H
|
||||
#define MBED_OBJECTS_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include "cmsis.h"
|
||||
#include "PortNames.h"
|
||||
#include "PeripheralNames.h"
|
||||
#include "PinNames.h"
|
||||
#include "gpio_object.h"
|
||||
#include "rspi_iodefine.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct i2c_s {
|
||||
uint32_t i2c;
|
||||
uint32_t dummy;
|
||||
uint8_t pclk_bit;
|
||||
uint8_t width_low;
|
||||
uint8_t width_hi;
|
||||
int bbsy_wait_cnt;
|
||||
int last_stop_flag;
|
||||
};
|
||||
|
||||
struct spi_s {
|
||||
struct st_rspi *spi;
|
||||
uint32_t bits;
|
||||
int index;
|
||||
};
|
||||
|
||||
struct gpio_irq_s {
|
||||
uint32_t port;
|
||||
uint32_t pin;
|
||||
uint32_t ch;
|
||||
uint8_t int_enable;
|
||||
};
|
||||
|
||||
struct port_s {
|
||||
__IO uint32_t *reg_dir;
|
||||
__IO uint32_t *reg_out;
|
||||
__I uint32_t *reg_in;
|
||||
PortName port;
|
||||
uint32_t mask;
|
||||
};
|
||||
|
||||
struct serial_s {
|
||||
struct st_scif *uart;
|
||||
int index;
|
||||
};
|
||||
|
||||
struct pwmout_s {
|
||||
uint32_t ch;
|
||||
PWMName pwm;
|
||||
};
|
||||
|
||||
struct analogin_s {
|
||||
ADCName adc;
|
||||
};
|
||||
|
||||
struct can_s {
|
||||
uint32_t ch;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,172 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "pinmap.h"
|
||||
#include "mbed_error.h"
|
||||
#include "gpio_addrdefine.h"
|
||||
|
||||
PinName gpio_multi_guard = (PinName)NC; /* If set pin name here, setting of the "pin" is just one time */
|
||||
|
||||
typedef struct {
|
||||
PinName pin;
|
||||
int function;
|
||||
int pm;
|
||||
} PinFunc;
|
||||
|
||||
static const PinFunc PIPC_0_tbl[] = {
|
||||
// pin func pm
|
||||
{P4_0 , 2 , -1}, /* TIOC0A */
|
||||
{P5_0 , 6 , -1}, /* TIOC0A */
|
||||
{P7_0 , 7 , -1}, /* TIOC0A */
|
||||
{P10_4 , 2 , -1}, /* TIOC0A */
|
||||
{P4_1 , 2 , -1}, /* TIOC0B */
|
||||
{P5_1 , 6 , -1}, /* TIOC0B */
|
||||
{P7_1 , 7 , -1}, /* TIOC0B */
|
||||
{P10_5 , 2 , -1}, /* TIOC0B */
|
||||
{P4_2 , 2 , -1}, /* TIOC0C */
|
||||
{P5_5 , 6 , -1}, /* TIOC0C */
|
||||
{P7_2 , 7 , -1}, /* TIOC0C */
|
||||
{P10_6 , 2 , -1}, /* TIOC0C */
|
||||
{P4_3 , 2 , -1}, /* TIOC0D */
|
||||
{P5_7 , 6 , -1}, /* TIOC0D */
|
||||
{P7_3 , 7 , -1}, /* TIOC0D */
|
||||
{P10_7 , 2 , -1}, /* TIOC0D */
|
||||
{P2_11 , 5 , -1}, /* TIOC1A */
|
||||
{P6_0 , 5 , -1}, /* TIOC1A */
|
||||
{P7_4 , 7 , -1}, /* TIOC1A */
|
||||
{P8_8 , 5 , -1}, /* TIOC1A */
|
||||
{P9_7 , 4 , -1}, /* TIOC1A */
|
||||
{P10_8 , 2 , -1}, /* TIOC1A */
|
||||
{P2_12 , 8 , -1}, /* TIOC1B */
|
||||
{P5_2 , 6 , -1}, /* TIOC1B */
|
||||
{P6_1 , 5 , -1}, /* TIOC1B */
|
||||
{P7_5 , 7 , -1}, /* TIOC1B */
|
||||
{P8_9 , 5 , -1}, /* TIOC1B */
|
||||
{P10_9 , 2 , -1}, /* TIOC1B */
|
||||
{P2_1 , 6 , -1}, /* TIOC2A */
|
||||
{P6_2 , 6 , -1}, /* TIOC2A */
|
||||
{P7_6 , 7 , -1}, /* TIOC2A */
|
||||
{P8_14 , 4 , -1}, /* TIOC2A */
|
||||
{P10_10 , 2 , -1}, /* TIOC2A */
|
||||
{P2_2 , 6 , -1}, /* TIOC2B */
|
||||
{P6_3 , 6 , -1}, /* TIOC2B */
|
||||
{P7_7 , 7 , -1}, /* TIOC2B */
|
||||
{P8_15 , 4 , -1}, /* TIOC2B */
|
||||
{P10_11 , 2 , -1}, /* TIOC2B */
|
||||
{P10_11 , 2 , -1}, /* TIOC2B */
|
||||
{P3_4 , 6 , -1}, /* TIOC3A */
|
||||
{P7_8 , 7 , -1}, /* TIOC3A */
|
||||
{P8_10 , 4 , -1}, /* TIOC3A */
|
||||
{P3_5 , 6 , -1}, /* TIOC3B */
|
||||
{P7_9 , 7 , -1}, /* TIOC3B */
|
||||
{P8_11 , 4 , -1}, /* TIOC3B */
|
||||
{P3_6 , 6 , -1}, /* TIOC3C */
|
||||
{P5_3 , 6 , -1}, /* TIOC3C */
|
||||
{P7_10 , 7 , -1}, /* TIOC3C */
|
||||
{P8_12 , 4 , -1}, /* TIOC3C */
|
||||
{P3_7 , 6 , -1}, /* TIOC3D */
|
||||
{P5_4 , 6 , -1}, /* TIOC3D */
|
||||
{P7_11 , 7 , -1}, /* TIOC3D */
|
||||
{P8_13 , 4 , -1}, /* TIOC3D */
|
||||
{P3_8 , 6 , -1}, /* TIOC4A */
|
||||
{P4_4 , 3 , -1}, /* TIOC4A */
|
||||
{P7_12 , 7 , -1}, /* TIOC4A */
|
||||
{P11_0 , 2 , -1}, /* TIOC4A */
|
||||
{P3_9 , 6 , -1}, /* TIOC4B */
|
||||
{P4_5 , 3 , -1}, /* TIOC4B */
|
||||
{P7_13 , 7 , -1}, /* TIOC4B */
|
||||
{P11_1 , 2 , -1}, /* TIOC4B */
|
||||
{P3_10 , 6 , -1}, /* TIOC4C */
|
||||
{P4_6 , 3 , -1}, /* TIOC4C */
|
||||
{P7_14 , 7 , -1}, /* TIOC4C */
|
||||
{P11_2 , 2 , -1}, /* TIOC4C */
|
||||
{P3_11 , 6 , -1}, /* TIOC4D */
|
||||
{P4_7 , 3 , -1}, /* TIOC4D */
|
||||
{P7_15 , 7 , -1}, /* TIOC4D */
|
||||
{P11_3 , 2 , -1}, /* TIOC4D */
|
||||
{P5_7 , 1 , 1 }, /* TXOUT0M */
|
||||
{P5_6 , 1 , 1 }, /* TXOUT0P */
|
||||
{P5_5 , 1 , 1 }, /* TXOUT1M */
|
||||
{P5_4 , 1 , 1 }, /* TXOUT1P */
|
||||
{P5_3 , 1 , 1 }, /* TXOUT2M */
|
||||
{P5_2 , 1 , 1 }, /* TXOUT2P */
|
||||
{P5_1 , 1 , 1 }, /* TXCLKOUTM */
|
||||
{P5_0 , 1 , 1 }, /* TXCLKOUTP */
|
||||
{P2_11 , 4 , 0 }, /* SSITxD0 */
|
||||
{P4_7 , 5 , 0 }, /* SSITxD0 */
|
||||
{P7_4 , 6 , 0 }, /* SSITxD1 */
|
||||
{P10_15 , 2 , 0 }, /* SSITxD1 */
|
||||
{P4_15 , 6 , 0 }, /* SSITxD3 */
|
||||
{P7_11 , 2 , 0 }, /* SSITxD3 */
|
||||
{P2_7 , 4 , 0 }, /* SSITxD5 */
|
||||
{P4_11 , 5 , 0 }, /* SSITxD5 */
|
||||
{P8_10 , 8 , 0 }, /* SSITxD5 */
|
||||
{P3_7 , 8 , 0 }, /* WDTOVF */
|
||||
{NC , 0 , -1}
|
||||
};
|
||||
|
||||
void pin_function(PinName pin, int function) {
|
||||
if (pin == (PinName)NC) return;
|
||||
|
||||
int n = pin >> 4;
|
||||
int bitmask = 1<<(pin & 0xf);
|
||||
const PinFunc * Pipc_0_func = PIPC_0_tbl;
|
||||
int pipc_data = 1;
|
||||
|
||||
if (gpio_multi_guard != pin) {
|
||||
if (function == 0) {
|
||||
// means GPIO mode
|
||||
*PMC(n) &= ~bitmask;
|
||||
} else {
|
||||
// alt-function mode
|
||||
--function;
|
||||
|
||||
if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else { *PFCAE(n) &= ~bitmask;}
|
||||
if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else { *PFCE(n) &= ~bitmask;}
|
||||
if (function & (1 << 0)) { *PFC(n) |= bitmask;}else { *PFC(n) &= ~bitmask;}
|
||||
|
||||
while (Pipc_0_func->pin != NC) {
|
||||
if ((Pipc_0_func->pin == pin) && ((Pipc_0_func->function - 1) == function)) {
|
||||
pipc_data = 0;
|
||||
if (Pipc_0_func->pm == 0) {
|
||||
*PMSR(n) = (bitmask << 16) | 0;
|
||||
} else if (Pipc_0_func->pm == 1) {
|
||||
*PMSR(n) = (bitmask << 16) | bitmask;
|
||||
} else {
|
||||
// Do Nothing
|
||||
}
|
||||
break;
|
||||
}
|
||||
Pipc_0_func++;
|
||||
}
|
||||
if (pipc_data == 1) {
|
||||
*PIPC(n) |= bitmask;
|
||||
} else {
|
||||
*PIPC(n) &= ~bitmask;
|
||||
}
|
||||
|
||||
if (P1_0 <= pin && pin <= P1_7 && function == 0) {
|
||||
*PBDC(n) |= bitmask;
|
||||
}
|
||||
*PMC(n) |= bitmask;
|
||||
}
|
||||
} else {
|
||||
gpio_multi_guard = (PinName)NC;
|
||||
}
|
||||
}
|
||||
|
||||
void pin_mode(PinName pin, PinMode mode) {
|
||||
// if (pin == (PinName)NC) { return; }
|
||||
}
|
||||
|
|
@ -1,65 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "port_api.h"
|
||||
#include "pinmap.h"
|
||||
#include "gpio_api.h"
|
||||
|
||||
PinName port_pin(PortName port, int pin_n) {
|
||||
return (PinName)(0);
|
||||
}
|
||||
|
||||
void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
|
||||
obj->port = port;
|
||||
obj->mask = mask;
|
||||
|
||||
// Do not use masking, because it prevents the use of the unmasked pins
|
||||
// port_reg->FIOMASK = ~mask;
|
||||
|
||||
uint32_t i;
|
||||
// The function is set per pin: reuse gpio logic
|
||||
for (i=0; i<32; i++) {
|
||||
if (obj->mask & (1<<i)) {
|
||||
gpio_set(port_pin(obj->port, i));
|
||||
}
|
||||
}
|
||||
|
||||
port_dir(obj, dir);
|
||||
}
|
||||
|
||||
void port_mode(port_t *obj, PinMode mode) {
|
||||
uint32_t i;
|
||||
// The mode is set per pin: reuse pinmap logic
|
||||
for (i=0; i<32; i++) {
|
||||
if (obj->mask & (1<<i)) {
|
||||
pin_mode(port_pin(obj->port, i), mode);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void port_dir(port_t *obj, PinDirection dir) {
|
||||
switch (dir) {
|
||||
case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
|
||||
case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
|
||||
}
|
||||
}
|
||||
|
||||
void port_write(port_t *obj, int value) {
|
||||
*obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask);
|
||||
}
|
||||
|
||||
int port_read(port_t *obj) {
|
||||
return (*obj->reg_in & obj->mask);
|
||||
}
|
||||
|
|
@ -1,381 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "mbed_assert.h"
|
||||
#include "device.h"
|
||||
|
||||
#if DEVICE_RTC
|
||||
|
||||
#include "rtc_api.h"
|
||||
#include "rtc_iodefine.h"
|
||||
#include "mbed_mktime.h"
|
||||
|
||||
|
||||
#define RCR1_VAL_ON (0x08u) // AIE = 1
|
||||
#define RCR1_VAL_OFF (0x00u)
|
||||
#define RCR2_VAL_ALLSTOP (0x00u)
|
||||
#define RCR2_VAL_START (0x01u) // START = 1
|
||||
#define RCR2_VAL_RESET (0x02u) // RESET = 1
|
||||
#define RCR3_VAL (0x00u)
|
||||
#define RCR5_VAL_EXTAL (0x01u) // RCKSEL = connect EXTAL
|
||||
#define RCR5_VAL_RTCX1 (0x00u) // RCKSEL = disconnect EXTAL
|
||||
#define RFRH_VAL_13333 (0x8003u) // 13.3333MHz (= 64Hz * 0x32DCD)
|
||||
#define RFRL_VAL_13333 (0x2DCDu) //
|
||||
#define RFRH_VAL_MAX (0x0007u) // MAX value (= 128Hz * 0x7FFFF)
|
||||
#define RFRL_VAL_MAX (0xFFFFu) //
|
||||
|
||||
#define MASK_00_03_POS (0x000Fu)
|
||||
#define MASK_04_07_POS (0x00F0u)
|
||||
#define MASK_08_11_POS (0x0F00u)
|
||||
#define MASK_12_15_POS (0xF000u)
|
||||
#define MASK_16_20_POS (0x000F0000u)
|
||||
#define SHIFT_1_HBYTE (4u)
|
||||
#define SHIFT_2_HBYTE (8u)
|
||||
#define SHIFT_3_HBYTE (12u)
|
||||
#define SHIFT_1BYTE (8u)
|
||||
#define SHIFT_2BYTE (16u)
|
||||
|
||||
#define TIME_ERROR_VAL (0u)
|
||||
|
||||
static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val);
|
||||
static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val);
|
||||
static uint8_t rtc_hex8_to_dec(uint8_t hex_val);
|
||||
static uint16_t rtc_hex16_to_dec(uint16_t hex_val);
|
||||
|
||||
|
||||
/*
|
||||
* Setup the RTC based on a time structure.
|
||||
* The rtc_init function should be executed first.
|
||||
* [in]
|
||||
* None.
|
||||
* [out]
|
||||
* None.
|
||||
*/
|
||||
void rtc_init(void) {
|
||||
volatile uint8_t dummy_read;
|
||||
|
||||
// Set control register
|
||||
RTC.RCR2 = RCR2_VAL_ALLSTOP;
|
||||
RTC.RCR1 = RCR1_VAL_ON;
|
||||
RTC.RCR3 = RCR3_VAL;
|
||||
RTC.RCR5 = RCR5_VAL_EXTAL;
|
||||
RTC.RFRH = RFRH_VAL_13333;
|
||||
RTC.RFRL = RFRL_VAL_13333;
|
||||
|
||||
// Dummy read
|
||||
dummy_read = RTC.RCR2;
|
||||
dummy_read = RTC.RCR2;
|
||||
|
||||
RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1
|
||||
|
||||
// Dummy read
|
||||
dummy_read = RTC.RCR2;
|
||||
dummy_read = RTC.RCR2;
|
||||
|
||||
// Set timer and alarm. Default value :01-01-1970 00:00:00
|
||||
RTC.RSECCNT = 0;
|
||||
RTC.RMINCNT = 0;
|
||||
RTC.RHRCNT = 0;
|
||||
RTC.RWKCNT = 0;
|
||||
RTC.RDAYCNT = 1;
|
||||
RTC.RMONCNT = 1;
|
||||
RTC.RYRCNT = 0x1970;
|
||||
RTC.RSECAR = 0;
|
||||
RTC.RMINAR = 0;
|
||||
RTC.RHRAR = 0;
|
||||
RTC.RWKAR = 0;
|
||||
RTC.RDAYAR = 1;
|
||||
RTC.RMONAR = 1;
|
||||
RTC.RYRAR = 0x1970;
|
||||
|
||||
// Dummy read
|
||||
dummy_read = RTC.RYRCNT;
|
||||
dummy_read = RTC.RYRCNT;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Release the RTC based on a time structure.
|
||||
* [in]
|
||||
* None.
|
||||
* [out]
|
||||
* None.
|
||||
*/
|
||||
void rtc_free(void) {
|
||||
volatile uint8_t dummy_read;
|
||||
|
||||
// Set control register
|
||||
RTC.RCR2 = RCR2_VAL_ALLSTOP;
|
||||
RTC.RCR1 = RCR1_VAL_OFF;
|
||||
RTC.RCR3 = RCR3_VAL;
|
||||
RTC.RCR5 = RCR5_VAL_RTCX1;
|
||||
RTC.RFRH = RFRH_VAL_MAX;
|
||||
RTC.RFRL = RFRL_VAL_MAX;
|
||||
|
||||
// Dummy read
|
||||
dummy_read = RTC.RCR2;
|
||||
dummy_read = RTC.RCR2;
|
||||
RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1
|
||||
|
||||
// Dummy read
|
||||
dummy_read = RTC.RCR2;
|
||||
dummy_read = RTC.RCR2;
|
||||
|
||||
// Set timer and alarm. Default value :01-01-1970 00:00:00
|
||||
RTC.RSECCNT = 0;
|
||||
RTC.RMINCNT = 0;
|
||||
RTC.RHRCNT = 0;
|
||||
RTC.RWKCNT = 0;
|
||||
RTC.RDAYCNT = 1;
|
||||
RTC.RMONCNT = 1;
|
||||
RTC.RYRCNT = 0x1970;
|
||||
RTC.RSECAR = 0;
|
||||
RTC.RMINAR = 0;
|
||||
RTC.RHRAR = 0;
|
||||
RTC.RWKAR = 0;
|
||||
RTC.RDAYAR = 1;
|
||||
RTC.RMONAR = 1;
|
||||
RTC.RYRAR = 0x1970;
|
||||
|
||||
// Dummy read
|
||||
dummy_read = RTC.RYRCNT;
|
||||
dummy_read = RTC.RYRCNT;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Check the RTC has been enabled.
|
||||
* Clock Control Register RTC.RCR1(bit3): 0 = Disabled, 1 = Enabled.
|
||||
* [in]
|
||||
* None.
|
||||
* [out]
|
||||
* 0:Disabled, 1:Enabled.
|
||||
*/
|
||||
int rtc_isenabled(void) {
|
||||
int ret_val = 0;
|
||||
|
||||
if ((RTC.RCR1 & RCR1_VAL_ON) != 0) { // RTC ON ?
|
||||
ret_val = 1;
|
||||
}
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* RTC read function.
|
||||
* [in]
|
||||
* None.
|
||||
* [out]
|
||||
* UNIX timestamp value.
|
||||
*/
|
||||
time_t rtc_read(void) {
|
||||
|
||||
struct tm timeinfo;
|
||||
int err = 0;
|
||||
uint8_t tmp_regdata;
|
||||
time_t t;
|
||||
|
||||
if (rtc_isenabled() != 0) {
|
||||
RTC.RCR1 &= ~0x10u; // CIE = 0
|
||||
do {
|
||||
// before reading process
|
||||
tmp_regdata = RTC.RCR1;
|
||||
tmp_regdata &= ~0x80u; // CF = 0
|
||||
tmp_regdata |= 0x01u; // AF = 1
|
||||
RTC.RCR1 = tmp_regdata;
|
||||
|
||||
// Read RTC register
|
||||
err = rtc_dec8_to_hex(RTC.RSECCNT , 0 , &timeinfo.tm_sec);
|
||||
err += rtc_dec8_to_hex(RTC.RMINCNT , 0 , &timeinfo.tm_min);
|
||||
err += rtc_dec8_to_hex(RTC.RHRCNT , 0 , &timeinfo.tm_hour);
|
||||
err += rtc_dec8_to_hex(RTC.RDAYCNT , 0 , &timeinfo.tm_mday);
|
||||
err += rtc_dec8_to_hex(RTC.RMONCNT , 1 , &timeinfo.tm_mon);
|
||||
err += rtc_dec16_to_hex(RTC.RYRCNT , 1900 , &timeinfo.tm_year);
|
||||
} while ((RTC.RCR1 & 0x80u) != 0);
|
||||
} else {
|
||||
err = 1;
|
||||
}
|
||||
|
||||
if (err == 0) {
|
||||
// Convert to timestamp
|
||||
if (_rtc_maketime(&timeinfo, &t, RTC_FULL_LEAP_YEAR_SUPPORT) == false) {
|
||||
return TIME_ERROR_VAL;
|
||||
}
|
||||
} else {
|
||||
// Error
|
||||
t = TIME_ERROR_VAL;
|
||||
}
|
||||
|
||||
return t;
|
||||
}
|
||||
|
||||
/*
|
||||
* Dec(8bit) to Hex function for RTC.
|
||||
* [in]
|
||||
* dec_val:Decimal value (from 0x00 to 0x99).
|
||||
* offset:Subtract offset from dec_val.
|
||||
* hex_val:Pointer of output hexadecimal value.
|
||||
* [out]
|
||||
* 0:Success
|
||||
* 1:Error
|
||||
*/
|
||||
static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val) {
|
||||
int err = 0;
|
||||
uint8_t ret_val;
|
||||
|
||||
if (hex_val != NULL) {
|
||||
if (((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) ||
|
||||
((dec_val & MASK_00_03_POS) >= 0x0A)) {
|
||||
err = 1;
|
||||
} else {
|
||||
ret_val = ((dec_val & MASK_04_07_POS) >> SHIFT_1_HBYTE) * 10 +
|
||||
(dec_val & MASK_00_03_POS);
|
||||
if (ret_val < offset) {
|
||||
err = 1;
|
||||
} else {
|
||||
*hex_val = ret_val - offset;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
err = 1;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* Dec(16bit) to Hex function for RTC
|
||||
* [in]
|
||||
* dec_val:Decimal value (from 0x0000 to 0x9999).
|
||||
* offset:Subtract offset from dec_val.
|
||||
* hex_val:Pointer of output hexadecimal value.
|
||||
* [out]
|
||||
* 0:Success
|
||||
* 1:Error
|
||||
*/
|
||||
static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val) {
|
||||
int err = 0;
|
||||
uint16_t ret_val;
|
||||
|
||||
if (hex_val != NULL) {
|
||||
if (((dec_val & MASK_12_15_POS) >= (0x0A << SHIFT_3_HBYTE)) ||
|
||||
((dec_val & MASK_08_11_POS) >= (0x0A << SHIFT_2_HBYTE)) ||
|
||||
((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) ||
|
||||
((dec_val & MASK_00_03_POS) >= 0x0A)) {
|
||||
err = 1;
|
||||
*hex_val = 0;
|
||||
} else {
|
||||
ret_val = (((dec_val & MASK_12_15_POS)) >> SHIFT_3_HBYTE) * 1000 +
|
||||
(((dec_val & MASK_08_11_POS)) >> SHIFT_2_HBYTE) * 100 +
|
||||
(((dec_val & MASK_04_07_POS)) >> SHIFT_1_HBYTE) * 10 +
|
||||
(dec_val & MASK_00_03_POS);
|
||||
if (ret_val < offset) {
|
||||
err = 1;
|
||||
} else {
|
||||
*hex_val = ret_val - offset;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
err = 1;
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* RTC write function
|
||||
* [in]
|
||||
* t:UNIX timestamp value
|
||||
* [out]
|
||||
* None.
|
||||
*/
|
||||
void rtc_write(time_t t) {
|
||||
|
||||
struct tm timeinfo;
|
||||
if (_rtc_localtime(t, &timeinfo, RTC_FULL_LEAP_YEAR_SUPPORT) == false) {
|
||||
return;
|
||||
}
|
||||
|
||||
volatile uint16_t dummy_read;
|
||||
|
||||
if (rtc_isenabled() != 0) {
|
||||
RTC.RCR2 = RCR2_VAL_ALLSTOP;
|
||||
dummy_read = (uint16_t)RTC.RCR2;
|
||||
dummy_read = (uint16_t)RTC.RCR2;
|
||||
RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1
|
||||
dummy_read = (uint16_t)RTC.RCR2;
|
||||
dummy_read = (uint16_t)RTC.RCR2;
|
||||
|
||||
RTC.RSECCNT = rtc_hex8_to_dec(timeinfo.tm_sec);
|
||||
RTC.RMINCNT = rtc_hex8_to_dec(timeinfo.tm_min);
|
||||
RTC.RHRCNT = rtc_hex8_to_dec(timeinfo.tm_hour);
|
||||
RTC.RDAYCNT = rtc_hex8_to_dec(timeinfo.tm_mday);
|
||||
RTC.RMONCNT = rtc_hex8_to_dec(timeinfo.tm_mon + 1);
|
||||
RTC.RYRCNT = rtc_hex16_to_dec(timeinfo.tm_year + 1900);
|
||||
dummy_read = (uint16_t)RTC.RYRCNT;
|
||||
dummy_read = (uint16_t)RTC.RYRCNT;
|
||||
|
||||
RTC.RCR2 = RCR2_VAL_START; // START = 1
|
||||
|
||||
dummy_read = (uint16_t)RTC.RCR2;
|
||||
dummy_read = (uint16_t)RTC.RCR2;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* HEX to Dec(8bit) function for RTC.
|
||||
* [in]
|
||||
* hex_val:Hexadecimal value.
|
||||
* [out]
|
||||
* decimal value:From 0x00 to 0x99.
|
||||
*/
|
||||
static uint8_t rtc_hex8_to_dec(uint8_t hex_val) {
|
||||
uint32_t calc_data;
|
||||
|
||||
calc_data = hex_val / 10 * 0x10;
|
||||
calc_data += hex_val % 10;
|
||||
|
||||
if (calc_data > 0x99) {
|
||||
calc_data = 0;
|
||||
}
|
||||
|
||||
return (uint8_t)calc_data;
|
||||
}
|
||||
|
||||
/*
|
||||
* HEX to Dec(16bit) function for RTC.
|
||||
* [in]
|
||||
* hex_val:Hexadecimal value.
|
||||
* [out]
|
||||
* decimal value:From 0x0000 to 0x9999.
|
||||
*/
|
||||
static uint16_t rtc_hex16_to_dec(uint16_t hex_val) {
|
||||
uint32_t calc_data;
|
||||
calc_data = hex_val / 1000 * 0x1000;
|
||||
calc_data += ((hex_val / 100) % 10) * 0x100;
|
||||
calc_data += ((hex_val / 10) % 10) * 0x10;
|
||||
calc_data += hex_val % 10;
|
||||
|
||||
if (calc_data > 0x9999) {
|
||||
calc_data = 0;
|
||||
}
|
||||
return (uint16_t)calc_data;
|
||||
|
||||
}
|
||||
|
||||
#endif /* DEVICE_RTC */
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef MBED_PERIPHERALPINS_H
|
||||
#define MBED_PERIPHERALPINS_H
|
||||
|
||||
#include "pinmap.h"
|
||||
#include "PeripheralNames.h"
|
||||
|
||||
typedef struct {
|
||||
PinName pin;
|
||||
int function;
|
||||
int pm;
|
||||
} PinFunc;
|
||||
|
||||
/************IRQ***************/
|
||||
extern const PinMap PinMap_IRQ[];
|
||||
|
||||
/************PINMAP***************/
|
||||
extern const PinFunc PIPC_0_tbl[];
|
||||
|
||||
/************ADC***************/
|
||||
extern const PinMap PinMap_ADC[];
|
||||
|
||||
/************DAC***************/
|
||||
extern const PinMap PinMap_DAC[];
|
||||
|
||||
/************I2C***************/
|
||||
extern const PinMap PinMap_I2C_SDA[];
|
||||
extern const PinMap PinMap_I2C_SCL[];
|
||||
|
||||
/************UART***************/
|
||||
extern const PinMap PinMap_UART_TX[];
|
||||
extern const PinMap PinMap_UART_RX[];
|
||||
extern const PinMap PinMap_UART_CTS[];
|
||||
extern const PinMap PinMap_UART_RTS[];
|
||||
|
||||
/************SPI***************/
|
||||
extern const PinMap PinMap_SPI_SCLK[];
|
||||
extern const PinMap PinMap_SPI_MOSI[];
|
||||
extern const PinMap PinMap_SPI_MISO[];
|
||||
extern const PinMap PinMap_SPI_SSEL[];
|
||||
|
||||
/************PWM***************/
|
||||
extern const PinMap PinMap_PWM[];
|
||||
|
||||
/************CAN***************/
|
||||
extern const PinMap PinMap_CAN_RD[];
|
||||
extern const PinMap PinMap_CAN_TD[];
|
||||
|
||||
#endif
|
||||
|
|
@ -34,82 +34,31 @@ typedef enum {
|
|||
UART7,
|
||||
} UARTName;
|
||||
|
||||
// PWMType & 1 == 1 then have to use PWDTR[12] == 1
|
||||
typedef enum {
|
||||
PWM1A = 0,
|
||||
PWM1B,
|
||||
PWM1C,
|
||||
PWM1D,
|
||||
PWM1E,
|
||||
PWM1F,
|
||||
PWM1G,
|
||||
PWM1H,
|
||||
PWM2A = 0x10,
|
||||
PWM2B,
|
||||
PWM2C,
|
||||
PWM2D,
|
||||
PWM2E,
|
||||
PWM2F,
|
||||
PWM2G,
|
||||
PWM2H,
|
||||
} PWMType;
|
||||
|
||||
typedef enum {
|
||||
TIOC0A = 0,
|
||||
TIOC0B,
|
||||
TIOC0C,
|
||||
TIOC0D,
|
||||
TIOC1A = 0x10,
|
||||
TIOC1B,
|
||||
TIOC2A = 0x20,
|
||||
TIOC2B,
|
||||
TIOC3A = 0x30,
|
||||
TIOC3B,
|
||||
TIOC3C,
|
||||
TIOC3D,
|
||||
TIOC4A = 0x40,
|
||||
TIOC4B,
|
||||
TIOC4C,
|
||||
TIOC4D,
|
||||
} MTU2_PWMType;
|
||||
|
||||
typedef enum {
|
||||
PWM0_PIN = 0,
|
||||
PWM1_PIN,
|
||||
PWM2_PIN,
|
||||
PWM3_PIN,
|
||||
PWM4_PIN,
|
||||
PWM5_PIN,
|
||||
PWM6_PIN,
|
||||
PWM7_PIN,
|
||||
PWM8_PIN,
|
||||
PWM9_PIN,
|
||||
PWM10_PIN,
|
||||
PWM11_PIN,
|
||||
PWM12_PIN,
|
||||
PWM13_PIN,
|
||||
MTU2_PWM0_PIN = 0x20,
|
||||
MTU2_PWM1_PIN,
|
||||
MTU2_PWM2_PIN,
|
||||
MTU2_PWM3_PIN,
|
||||
MTU2_PWM4_PIN,
|
||||
MTU2_PWM5_PIN,
|
||||
MTU2_PWM6_PIN,
|
||||
MTU2_PWM7_PIN,
|
||||
MTU2_PWM8_PIN,
|
||||
MTU2_PWM9_PIN,
|
||||
MTU2_PWM10_PIN,
|
||||
MTU2_PWM11_PIN,
|
||||
MTU2_PWM12_PIN,
|
||||
MTU2_PWM13_PIN,
|
||||
MTU2_PWM14_PIN,
|
||||
MTU2_PWM15_PIN,
|
||||
MTU2_PWM16_PIN,
|
||||
MTU2_PWM17_PIN,
|
||||
MTU2_PWM18_PIN,
|
||||
MTU2_PWM19_PIN,
|
||||
MTU2_PWM20_PIN,
|
||||
MTU2_PWM21_PIN,
|
||||
PWM_PWM1A = 0,
|
||||
PWM_PWM1B,
|
||||
PWM_PWM1C,
|
||||
PWM_PWM1D,
|
||||
PWM_PWM1E,
|
||||
PWM_PWM1F,
|
||||
PWM_PWM1G,
|
||||
PWM_PWM1H,
|
||||
PWM_PWM2A,
|
||||
PWM_PWM2B,
|
||||
PWM_PWM2C,
|
||||
PWM_PWM2D,
|
||||
PWM_PWM2E,
|
||||
PWM_PWM2F,
|
||||
PWM_PWM2G,
|
||||
PWM_PWM2H,
|
||||
PWM_TIOC0A = 0x20,
|
||||
PWM_TIOC0C,
|
||||
PWM_TIOC1A,
|
||||
PWM_TIOC2A,
|
||||
PWM_TIOC3A,
|
||||
PWM_TIOC3C,
|
||||
PWM_TIOC4A,
|
||||
PWM_TIOC4C,
|
||||
} PWMName;
|
||||
|
||||
typedef enum {
|
||||
|
|
@ -128,21 +77,22 @@ typedef enum {
|
|||
SPI_1,
|
||||
SPI_2,
|
||||
SPI_3,
|
||||
SPI_4,
|
||||
} SPIName;
|
||||
|
||||
typedef enum {
|
||||
I2C_0 = 0,
|
||||
I2C_1,
|
||||
I2C_2,
|
||||
I2C_3
|
||||
I2C_3,
|
||||
} I2CName;
|
||||
|
||||
typedef enum {
|
||||
CAN_0 = 0,
|
||||
CAN_1,
|
||||
CAN_2,
|
||||
CAN_3,
|
||||
CAN_4
|
||||
CAN_3,
|
||||
CAN_4,
|
||||
} CANName;
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,343 @@
|
|||
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "PeripheralPins.h"
|
||||
|
||||
/************IRQ***************/
|
||||
enum {
|
||||
IRQ0,IRQ1,
|
||||
IRQ2,IRQ3,
|
||||
IRQ4,IRQ5,
|
||||
IRQ6,IRQ7,
|
||||
} IRQNo;
|
||||
const PinMap PinMap_IRQ[] = {
|
||||
{P1_0, IRQ0, 4}, {P1_1, IRQ1, 4}, {P1_2, IRQ2, 4},
|
||||
{P1_3, IRQ3, 4}, {P1_4, IRQ4, 4}, {P1_5, IRQ5, 4},
|
||||
{P1_6, IRQ6, 4}, {P1_7, IRQ7, 4}, {P1_8, IRQ2, 3},
|
||||
{P1_9, IRQ3, 3}, {P1_10, IRQ4, 3}, {P1_11, IRQ5, 3}, // 11
|
||||
{P2_0, IRQ5, 6}, {P2_12, IRQ6, 6}, {P2_13, IRQ7, 8},
|
||||
{P2_14, IRQ0, 8}, {P2_15, IRQ1, 8}, // 16
|
||||
{P3_0, IRQ2, 3}, {P3_1, IRQ6, 3}, {P3_3, IRQ4, 3},
|
||||
{P3_9, IRQ6, 8}, // 20
|
||||
{P4_8, IRQ0, 8}, {P4_9, IRQ1, 8}, {P4_10, IRQ2, 8},
|
||||
{P4_11, IRQ3, 8}, {P4_12, IRQ4, 8}, {P4_13, IRQ5, 8},
|
||||
{P4_14, IRQ6, 8}, {P4_15, IRQ7, 8}, // 28
|
||||
{P5_6, IRQ6, 6}, {P5_8, IRQ0, 2}, {P5_9, IRQ2, 4}, // 31
|
||||
{P6_0, IRQ5, 6}, {P6_1, IRQ4, 4}, {P6_2, IRQ7, 4},
|
||||
{P6_3, IRQ2, 4}, {P6_4, IRQ3, 4}, {P6_8, IRQ0, 8},
|
||||
{P6_9, IRQ1, 8}, {P6_10, IRQ2, 8}, {P6_11, IRQ3, 8},
|
||||
{P6_12, IRQ4, 8}, {P6_13, IRQ5, 8}, {P6_14, IRQ6, 8},
|
||||
{P6_15, IRQ7, 8}, // 44
|
||||
{P7_8, IRQ1, 8}, {P7_9, IRQ0, 8}, {P7_10, IRQ2, 8},
|
||||
{P7_11, IRQ3, 8}, {P7_12, IRQ4, 8}, {P7_13, IRQ5, 8},
|
||||
{P7_14, IRQ6, 8}, // 51
|
||||
{P8_2, IRQ0, 5}, {P8_3, IRQ1, 6}, {P8_7, IRQ5, 4},
|
||||
{P9_1, IRQ0, 4}, // 55
|
||||
{P11_12,IRQ3, 3}, {P11_15,IRQ1, 3}, // 57
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
/************PINMAP***************/
|
||||
const PinFunc PIPC_0_tbl[] = {
|
||||
// pin func pm
|
||||
{P4_0 , 2 , -1}, /* TIOC0A */
|
||||
{P5_0 , 6 , -1}, /* TIOC0A */
|
||||
{P7_0 , 7 , -1}, /* TIOC0A */
|
||||
{P10_4 , 2 , -1}, /* TIOC0A */
|
||||
{P4_1 , 2 , -1}, /* TIOC0B */
|
||||
{P5_1 , 6 , -1}, /* TIOC0B */
|
||||
{P7_1 , 7 , -1}, /* TIOC0B */
|
||||
{P10_5 , 2 , -1}, /* TIOC0B */
|
||||
{P4_2 , 2 , -1}, /* TIOC0C */
|
||||
{P5_5 , 6 , -1}, /* TIOC0C */
|
||||
{P7_2 , 7 , -1}, /* TIOC0C */
|
||||
{P10_6 , 2 , -1}, /* TIOC0C */
|
||||
{P4_3 , 2 , -1}, /* TIOC0D */
|
||||
{P5_7 , 6 , -1}, /* TIOC0D */
|
||||
{P7_3 , 7 , -1}, /* TIOC0D */
|
||||
{P10_7 , 2 , -1}, /* TIOC0D */
|
||||
{P2_11 , 5 , -1}, /* TIOC1A */
|
||||
{P6_0 , 5 , -1}, /* TIOC1A */
|
||||
{P7_4 , 7 , -1}, /* TIOC1A */
|
||||
{P8_8 , 5 , -1}, /* TIOC1A */
|
||||
{P9_7 , 4 , -1}, /* TIOC1A */
|
||||
{P10_8 , 2 , -1}, /* TIOC1A */
|
||||
{P2_12 , 8 , -1}, /* TIOC1B */
|
||||
{P5_2 , 6 , -1}, /* TIOC1B */
|
||||
{P6_1 , 5 , -1}, /* TIOC1B */
|
||||
{P7_5 , 7 , -1}, /* TIOC1B */
|
||||
{P8_9 , 5 , -1}, /* TIOC1B */
|
||||
{P10_9 , 2 , -1}, /* TIOC1B */
|
||||
{P2_1 , 6 , -1}, /* TIOC2A */
|
||||
{P6_2 , 6 , -1}, /* TIOC2A */
|
||||
{P7_6 , 7 , -1}, /* TIOC2A */
|
||||
{P8_14 , 4 , -1}, /* TIOC2A */
|
||||
{P10_10 , 2 , -1}, /* TIOC2A */
|
||||
{P2_2 , 6 , -1}, /* TIOC2B */
|
||||
{P6_3 , 6 , -1}, /* TIOC2B */
|
||||
{P7_7 , 7 , -1}, /* TIOC2B */
|
||||
{P8_15 , 4 , -1}, /* TIOC2B */
|
||||
{P10_11 , 2 , -1}, /* TIOC2B */
|
||||
{P10_11 , 2 , -1}, /* TIOC2B */
|
||||
{P3_4 , 6 , -1}, /* TIOC3A */
|
||||
{P7_8 , 7 , -1}, /* TIOC3A */
|
||||
{P8_10 , 4 , -1}, /* TIOC3A */
|
||||
{P3_5 , 6 , -1}, /* TIOC3B */
|
||||
{P7_9 , 7 , -1}, /* TIOC3B */
|
||||
{P8_11 , 4 , -1}, /* TIOC3B */
|
||||
{P3_6 , 6 , -1}, /* TIOC3C */
|
||||
{P5_3 , 6 , -1}, /* TIOC3C */
|
||||
{P7_10 , 7 , -1}, /* TIOC3C */
|
||||
{P8_12 , 4 , -1}, /* TIOC3C */
|
||||
{P3_7 , 6 , -1}, /* TIOC3D */
|
||||
{P5_4 , 6 , -1}, /* TIOC3D */
|
||||
{P7_11 , 7 , -1}, /* TIOC3D */
|
||||
{P8_13 , 4 , -1}, /* TIOC3D */
|
||||
{P3_8 , 6 , -1}, /* TIOC4A */
|
||||
{P4_4 , 3 , -1}, /* TIOC4A */
|
||||
{P7_12 , 7 , -1}, /* TIOC4A */
|
||||
{P11_0 , 2 , -1}, /* TIOC4A */
|
||||
{P3_9 , 6 , -1}, /* TIOC4B */
|
||||
{P4_5 , 3 , -1}, /* TIOC4B */
|
||||
{P7_13 , 7 , -1}, /* TIOC4B */
|
||||
{P11_1 , 2 , -1}, /* TIOC4B */
|
||||
{P3_10 , 6 , -1}, /* TIOC4C */
|
||||
{P4_6 , 3 , -1}, /* TIOC4C */
|
||||
{P7_14 , 7 , -1}, /* TIOC4C */
|
||||
{P11_2 , 2 , -1}, /* TIOC4C */
|
||||
{P3_11 , 6 , -1}, /* TIOC4D */
|
||||
{P4_7 , 3 , -1}, /* TIOC4D */
|
||||
{P7_15 , 7 , -1}, /* TIOC4D */
|
||||
{P11_3 , 2 , -1}, /* TIOC4D */
|
||||
{P5_7 , 1 , 1 }, /* TXOUT0M */
|
||||
{P5_6 , 1 , 1 }, /* TXOUT0P */
|
||||
{P5_5 , 1 , 1 }, /* TXOUT1M */
|
||||
{P5_4 , 1 , 1 }, /* TXOUT1P */
|
||||
{P5_3 , 1 , 1 }, /* TXOUT2M */
|
||||
{P5_2 , 1 , 1 }, /* TXOUT2P */
|
||||
{P5_1 , 1 , 1 }, /* TXCLKOUTM */
|
||||
{P5_0 , 1 , 1 }, /* TXCLKOUTP */
|
||||
{P2_11 , 4 , 0 }, /* SSITxD0 */
|
||||
{P4_7 , 5 , 0 }, /* SSITxD0 */
|
||||
{P7_4 , 6 , 0 }, /* SSITxD1 */
|
||||
{P10_15 , 2 , 0 }, /* SSITxD1 */
|
||||
{P4_15 , 6 , 0 }, /* SSITxD3 */
|
||||
{P7_11 , 2 , 0 }, /* SSITxD3 */
|
||||
{P2_7 , 4 , 0 }, /* SSITxD5 */
|
||||
{P4_11 , 5 , 0 }, /* SSITxD5 */
|
||||
{P8_10 , 8 , 0 }, /* SSITxD5 */
|
||||
{P3_7 , 8 , 0 }, /* WDTOVF */
|
||||
{NC , 0 , -1}
|
||||
};
|
||||
|
||||
/************ADC***************/
|
||||
const PinMap PinMap_ADC[] = {
|
||||
{P1_8, AN0, 1},
|
||||
{P1_9, AN1, 1},
|
||||
{P1_10, AN2, 1},
|
||||
{P1_11, AN3, 1},
|
||||
{P1_12, AN4, 1},
|
||||
{P1_13, AN5, 1},
|
||||
{P1_14, AN6, 1},
|
||||
{P1_15, AN7, 1},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************I2C***************/
|
||||
const PinMap PinMap_I2C_SDA[] = {
|
||||
{P1_1 , I2C_0, 1},
|
||||
{P1_3 , I2C_1, 1},
|
||||
{P1_7 , I2C_3, 1},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_I2C_SCL[] = {
|
||||
{P1_0 , I2C_0, 1},
|
||||
{P1_2 , I2C_1, 1},
|
||||
{P1_6 , I2C_3, 1},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************UART***************/
|
||||
const PinMap PinMap_UART_TX[] = {
|
||||
{P2_14 , UART0, 6},
|
||||
{P2_5 , UART1, 6},
|
||||
{P4_12 , UART1, 7},
|
||||
{P6_3 , UART2, 7},
|
||||
{P4_14 , UART2, 7},
|
||||
{P5_3 , UART3, 5},
|
||||
{P8_8 , UART3, 7},
|
||||
{P5_0 , UART4, 5},
|
||||
{P8_14 , UART4, 7},
|
||||
{P8_13 , UART5, 5},
|
||||
{P11_10, UART5, 3},
|
||||
{P6_6 , UART5, 5},
|
||||
{P5_6 , UART6, 5},
|
||||
{P11_1 , UART6, 4},
|
||||
{P7_4 , UART7, 4},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_UART_RX[] = {
|
||||
{P2_15 , UART0, 6},
|
||||
{P2_6 , UART1, 6},
|
||||
{P4_13 , UART1, 7},
|
||||
{P6_2 , UART2, 7},
|
||||
{P4_15 , UART2, 7},
|
||||
{P5_4 , UART3, 5},
|
||||
{P8_9 , UART3, 7},
|
||||
{P5_1 , UART4, 5},
|
||||
{P8_15 , UART4, 7},
|
||||
{P8_11 , UART5, 5},
|
||||
{P11_11, UART5, 3},
|
||||
{P6_7 , UART5, 5},
|
||||
{P5_7 , UART6, 5},
|
||||
{P11_2 , UART6, 4},
|
||||
{P7_5 , UART7, 4},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_UART_CTS[] = {
|
||||
{P2_3 , UART1, 6},
|
||||
{P11_7 , UART5, 3},
|
||||
{P7_6 , UART7, 4},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_UART_RTS[] = {
|
||||
{P2_7 , UART1, 6},
|
||||
{P11_8 , UART5, 3},
|
||||
{P7_7 , UART7, 4},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************SPI***************/
|
||||
const PinMap PinMap_SPI_SCLK[] = {
|
||||
{P10_12, SPI_0, 4},
|
||||
{P4_4 , SPI_1, 2},
|
||||
{P6_4 , SPI_1, 7},
|
||||
{P11_12, SPI_1, 2},
|
||||
{P8_3 , SPI_2, 3},
|
||||
{P5_0 , SPI_3, 8},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_MOSI[] = {
|
||||
{P10_14, SPI_0, 4},
|
||||
{P4_6 , SPI_1, 2},
|
||||
{P6_6 , SPI_1, 7},
|
||||
{P11_14, SPI_1, 2},
|
||||
{P8_5 , SPI_2, 3},
|
||||
{P5_2 , SPI_3, 8},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_MISO[] = {
|
||||
{P10_15, SPI_0, 4},
|
||||
{P4_7 , SPI_1, 2},
|
||||
{P6_7 , SPI_1, 7},
|
||||
{P11_15, SPI_1, 2},
|
||||
{P8_6 , SPI_2, 3},
|
||||
{P5_3 , SPI_3, 8},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_SSEL[] = {
|
||||
{P10_13, SPI_0, 4},
|
||||
{P4_5 , SPI_1, 2},
|
||||
{P6_5 , SPI_1, 7},
|
||||
{P11_13, SPI_1, 2},
|
||||
{P8_4 , SPI_2, 3},
|
||||
{P5_1 , SPI_3, 8},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************PWM***************/
|
||||
const PinMap PinMap_PWM[] = {
|
||||
{P2_1 , PWM_TIOC2A, 6},
|
||||
{P2_11 , PWM_TIOC1A, 5},
|
||||
{P3_8 , PWM_TIOC4A, 6},
|
||||
{P3_10 , PWM_TIOC4C, 6},
|
||||
{P4_0 , PWM_TIOC0A, 2},
|
||||
{P4_4 , PWM_TIOC4A, 3},
|
||||
{P4_6 , PWM_TIOC4C, 3},
|
||||
{P5_0 , PWM_TIOC0A, 6},
|
||||
{P5_3 , PWM_TIOC3C, 6},
|
||||
{P5_5 , PWM_TIOC0C, 6},
|
||||
{P7_2 , PWM_TIOC0C, 7},
|
||||
{P7_4 , PWM_TIOC1A, 7},
|
||||
{P7_6 , PWM_TIOC2A, 7},
|
||||
{P7_10 , PWM_TIOC3C, 7},
|
||||
{P7_12 , PWM_TIOC4A, 7},
|
||||
{P7_14 , PWM_TIOC4C, 7},
|
||||
{P8_8 , PWM_TIOC1A, 5},
|
||||
{P8_10 , PWM_TIOC3A, 4},
|
||||
{P8_12 , PWM_TIOC3C, 4},
|
||||
{P8_14 , PWM_TIOC2A, 4},
|
||||
{P11_0 , PWM_TIOC4A, 2},
|
||||
{P11_2 , PWM_TIOC4C, 2},
|
||||
{P4_4 , PWM_PWM2E , 4},
|
||||
{P3_2 , PWM_PWM2C , 7},
|
||||
{P4_6 , PWM_PWM2G , 4},
|
||||
{P4_7 , PWM_PWM2H , 4},
|
||||
{P8_14 , PWM_PWM1G , 6},
|
||||
{P8_15 , PWM_PWM1H , 6},
|
||||
{P8_13 , PWM_PWM1F , 6},
|
||||
{P8_11 , PWM_PWM1D , 6},
|
||||
{P8_8 , PWM_PWM1A , 6},
|
||||
{P10_0 , PWM_PWM2A , 3},
|
||||
{P8_12 , PWM_PWM1E , 6},
|
||||
{P8_9 , PWM_PWM1B , 6},
|
||||
{P8_10 , PWM_PWM1C , 6},
|
||||
{P4_5 , PWM_PWM2F , 4},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************CAN***************/
|
||||
const PinMap PinMap_CAN_RD[] = {
|
||||
{P7_8 , CAN_0, 4},
|
||||
{P9_1 , CAN_0, 3},
|
||||
{P1_4 , CAN_1, 3},
|
||||
{P5_9 , CAN_1, 5},
|
||||
{P7_11 , CAN_1, 4},
|
||||
{P11_12, CAN_1, 1},
|
||||
{P4_9 , CAN_2, 6},
|
||||
{P6_4 , CAN_2, 3},
|
||||
{P7_2 , CAN_2, 5},
|
||||
{P2_12 , CAN_3, 5},
|
||||
{P4_2 , CAN_3, 4},
|
||||
{P1_5 , CAN_4, 3},
|
||||
{P2_14 , CAN_4, 5},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_CAN_TD[] = {
|
||||
{P7_9 , CAN_0, 4},
|
||||
{P9_0 , CAN_0, 3},
|
||||
{P5_10 , CAN_1, 5},
|
||||
{P7_10 , CAN_1, 4},
|
||||
{P11_13, CAN_1, 1},
|
||||
{P4_8 , CAN_2, 6},
|
||||
{P6_5 , CAN_2, 3},
|
||||
{P7_3 , CAN_2, 5},
|
||||
{P2_13 , CAN_3, 5},
|
||||
{P4_3 , CAN_3, 4},
|
||||
{P4_11 , CAN_4, 6},
|
||||
{P8_10 , CAN_4, 5},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
|
|
@ -25,7 +25,14 @@ typedef enum {
|
|||
Port1 = 1,
|
||||
Port2 = 2,
|
||||
Port3 = 3,
|
||||
Port4 = 4
|
||||
Port4 = 4,
|
||||
Port5 = 5,
|
||||
Port6 = 6,
|
||||
Port7 = 7,
|
||||
Port8 = 8,
|
||||
Port9 = 9,
|
||||
Port10 = 10,
|
||||
Port11 = 11
|
||||
} PortName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2017 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef MBED_DRV_CFG_H
|
||||
#define MBED_DRV_CFG_H
|
||||
|
||||
/* can_api.c */
|
||||
#define CAN_TEST_GLOBAL_CH 1
|
||||
|
||||
/* gpio_api.c */
|
||||
#define GPIO_GROUP_MAX 11
|
||||
|
||||
/* pwmout_api.c */
|
||||
#define FUNC_MOTOR_CTL_PWM
|
||||
#define FUMC_MTU2_PWM
|
||||
|
||||
/* rtc_api.c */
|
||||
//#define USE_RTCX1_CLK
|
||||
#define USE_EXTAL_CLK
|
||||
//#define USE_RTCX3_CLK
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PERIPHERALNAMES_H
|
||||
#define MBED_PERIPHERALNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "PinNames.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
UART0,
|
||||
UART1,
|
||||
UART2,
|
||||
UART3,
|
||||
UART4,
|
||||
UART5,
|
||||
UART6,
|
||||
UART7,
|
||||
} UARTName;
|
||||
|
||||
typedef enum {
|
||||
PWM_PWM1A = 0,
|
||||
PWM_PWM1B,
|
||||
PWM_PWM1C,
|
||||
PWM_PWM1D,
|
||||
PWM_PWM1E,
|
||||
PWM_PWM1F,
|
||||
PWM_PWM1G,
|
||||
PWM_PWM1H,
|
||||
PWM_PWM2A,
|
||||
PWM_PWM2B,
|
||||
PWM_PWM2C,
|
||||
PWM_PWM2D,
|
||||
PWM_PWM2E,
|
||||
PWM_PWM2F,
|
||||
PWM_PWM2G,
|
||||
PWM_PWM2H,
|
||||
PWM_TIOC0A = 0x20,
|
||||
PWM_TIOC0C,
|
||||
PWM_TIOC1A,
|
||||
PWM_TIOC2A,
|
||||
PWM_TIOC3A,
|
||||
PWM_TIOC3C,
|
||||
PWM_TIOC4A,
|
||||
PWM_TIOC4C,
|
||||
} PWMName;
|
||||
|
||||
typedef enum {
|
||||
AN0= 0,
|
||||
AN1= 1,
|
||||
AN2= 2,
|
||||
AN3= 3,
|
||||
AN4= 4,
|
||||
AN5= 5,
|
||||
AN6= 6,
|
||||
AN7= 7,
|
||||
} ADCName;
|
||||
|
||||
typedef enum {
|
||||
SPI_0 = 0,
|
||||
SPI_1,
|
||||
SPI_2,
|
||||
SPI_3,
|
||||
SPI_4,
|
||||
} SPIName;
|
||||
|
||||
typedef enum {
|
||||
I2C_0 = 0,
|
||||
I2C_1,
|
||||
I2C_2,
|
||||
I2C_3,
|
||||
} I2CName;
|
||||
|
||||
typedef enum {
|
||||
CAN_0 = 0,
|
||||
CAN_1,
|
||||
CAN_2,
|
||||
CAN_3,
|
||||
CAN_4,
|
||||
} CANName;
|
||||
|
||||
|
||||
#define STDIO_UART_TX USBTX
|
||||
#define STDIO_UART_RX USBRX
|
||||
#define STDIO_UART UART3
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,540 @@
|
|||
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "PeripheralPins.h"
|
||||
|
||||
/************IRQ***************/
|
||||
enum {
|
||||
IRQ0,IRQ1,
|
||||
IRQ2,IRQ3,
|
||||
IRQ4,IRQ5,
|
||||
IRQ6,IRQ7,
|
||||
} IRQNo;
|
||||
const PinMap PinMap_IRQ[] = {
|
||||
#ifdef MAX_PERI
|
||||
{P1_0, IRQ0, 4}, {P4_8, IRQ0, 8}, {P6_8, IRQ0, 8}, {P7_9, IRQ0, 8}, {P8_2, IRQ0, 5}, {P2_14, IRQ0, 8}, {P5_8, IRQ0, 2}, {P9_1, IRQ0, 4},
|
||||
{P1_1, IRQ1, 4}, {P4_9, IRQ1, 8}, {P6_9, IRQ1, 8}, {P7_8, IRQ1, 8}, {P8_3, IRQ1, 6}, {P2_15, IRQ1, 8},
|
||||
{P1_2, IRQ2, 4}, {P4_10, IRQ2, 8}, {P6_10, IRQ2, 8}, {P7_10, IRQ2, 8}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, {P6_3, IRQ2, 4},
|
||||
{P1_3, IRQ3, 4}, {P4_11, IRQ3, 8}, {P6_11, IRQ3, 8}, {P7_11, IRQ3, 8}, {P1_9, IRQ3, 3}, {P6_4, IRQ3, 4},
|
||||
{P1_4, IRQ4, 4}, {P4_12, IRQ4, 8}, {P6_12, IRQ4, 8}, {P7_12, IRQ4, 8}, {P1_10, IRQ4, 3}, {P3_3, IRQ4, 3}, {P6_1, IRQ4, 4},
|
||||
{P1_5, IRQ5, 4}, {P4_13, IRQ5, 8}, {P6_13, IRQ5, 8}, {P7_13, IRQ5, 8}, {P1_11, IRQ5, 3}, {P2_0, IRQ5, 6}, {P6_0, IRQ5, 6}, {P8_7, IRQ5, 4},
|
||||
{P1_6, IRQ6, 4}, {P4_14, IRQ6, 8}, {P6_14, IRQ6, 8}, {P7_14, IRQ6, 8}, {P2_12, IRQ6, 6}, {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6},
|
||||
{P1_7, IRQ7, 4}, {P4_15, IRQ7, 8}, {P6_15, IRQ7, 8}, {P6_2, IRQ7, 4}, {P2_13, IRQ7, 8},
|
||||
{NC, NC, 0}
|
||||
#else
|
||||
{P9_1, IRQ0, 4},
|
||||
{P7_8, IRQ1, 8},
|
||||
{P1_2, IRQ2, 4}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4},
|
||||
{P1_3, IRQ3, 4}, {P1_9, IRQ3, 3},
|
||||
{P1_4, IRQ4, 4}, {P1_10, IRQ4, 3},
|
||||
{P1_5, IRQ5, 4}, {P1_11, IRQ5, 3},
|
||||
{P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6},
|
||||
{NC, NC, 0}
|
||||
#endif
|
||||
};
|
||||
|
||||
/************PINMAP***************/
|
||||
const PinFunc PIPC_0_tbl[] = {
|
||||
#ifdef MAX_PERI
|
||||
// pin func pm
|
||||
{P4_0 , 2 , -1}, /* TIOC0A */
|
||||
{P5_0 , 6 , -1}, /* TIOC0A */
|
||||
{P7_0 , 7 , -1}, /* TIOC0A */
|
||||
{P4_1 , 2 , -1}, /* TIOC0B */
|
||||
{P5_1 , 6 , -1}, /* TIOC0B */
|
||||
{P7_1 , 7 , -1}, /* TIOC0B */
|
||||
{P4_2 , 2 , -1}, /* TIOC0C */
|
||||
{P5_5 , 6 , -1}, /* TIOC0C */
|
||||
{P7_2 , 7 , -1}, /* TIOC0C */
|
||||
{P4_3 , 2 , -1}, /* TIOC0D */
|
||||
{P5_7 , 6 , -1}, /* TIOC0D */
|
||||
{P7_3 , 7 , -1}, /* TIOC0D */
|
||||
{P2_11 , 5 , -1}, /* TIOC1A */
|
||||
{P6_0 , 5 , -1}, /* TIOC1A */
|
||||
{P7_4 , 7 , -1}, /* TIOC1A */
|
||||
{P8_8 , 5 , -1}, /* TIOC1A */
|
||||
{P9_7 , 4 , -1}, /* TIOC1A */
|
||||
{P2_12 , 8 , -1}, /* TIOC1B */
|
||||
{P5_2 , 6 , -1}, /* TIOC1B */
|
||||
{P6_1 , 5 , -1}, /* TIOC1B */
|
||||
{P7_5 , 7 , -1}, /* TIOC1B */
|
||||
{P8_9 , 5 , -1}, /* TIOC1B */
|
||||
{P2_1 , 6 , -1}, /* TIOC2A */
|
||||
{P6_2 , 6 , -1}, /* TIOC2A */
|
||||
{P7_6 , 7 , -1}, /* TIOC2A */
|
||||
{P8_14 , 4 , -1}, /* TIOC2A */
|
||||
{P2_2 , 6 , -1}, /* TIOC2B */
|
||||
{P6_3 , 6 , -1}, /* TIOC2B */
|
||||
{P7_7 , 7 , -1}, /* TIOC2B */
|
||||
{P8_15 , 4 , -1}, /* TIOC2B */
|
||||
{P3_4 , 6 , -1}, /* TIOC3A */
|
||||
{P7_8 , 7 , -1}, /* TIOC3A */
|
||||
{P8_10 , 4 , -1}, /* TIOC3A */
|
||||
{P3_5 , 6 , -1}, /* TIOC3B */
|
||||
{P7_9 , 7 , -1}, /* TIOC3B */
|
||||
{P8_11 , 4 , -1}, /* TIOC3B */
|
||||
{P3_6 , 6 , -1}, /* TIOC3C */
|
||||
{P5_3 , 6 , -1}, /* TIOC3C */
|
||||
{P7_10 , 7 , -1}, /* TIOC3C */
|
||||
{P8_12 , 4 , -1}, /* TIOC3C */
|
||||
{P3_7 , 6 , -1}, /* TIOC3D */
|
||||
{P5_4 , 6 , -1}, /* TIOC3D */
|
||||
{P7_11 , 7 , -1}, /* TIOC3D */
|
||||
{P8_13 , 4 , -1}, /* TIOC3D */
|
||||
{P3_8 , 6 , -1}, /* TIOC4A */
|
||||
{P4_4 , 3 , -1}, /* TIOC4A */
|
||||
{P7_12 , 7 , -1}, /* TIOC4A */
|
||||
{P3_9 , 6 , -1}, /* TIOC4B */
|
||||
{P4_5 , 3 , -1}, /* TIOC4B */
|
||||
{P7_13 , 7 , -1}, /* TIOC4B */
|
||||
{P3_10 , 6 , -1}, /* TIOC4C */
|
||||
{P4_6 , 3 , -1}, /* TIOC4C */
|
||||
{P7_14 , 7 , -1}, /* TIOC4C */
|
||||
{P3_11 , 6 , -1}, /* TIOC4D */
|
||||
{P4_7 , 3 , -1}, /* TIOC4D */
|
||||
{P7_15 , 7 , -1}, /* TIOC4D */
|
||||
{P5_7 , 1 , 1 }, /* TXOUT0M */
|
||||
{P5_6 , 1 , 1 }, /* TXOUT0P */
|
||||
{P5_5 , 1 , 1 }, /* TXOUT1M */
|
||||
{P5_4 , 1 , 1 }, /* TXOUT1P */
|
||||
{P5_3 , 1 , 1 }, /* TXOUT2M */
|
||||
{P5_2 , 1 , 1 }, /* TXOUT2P */
|
||||
{P5_1 , 1 , 1 }, /* TXCLKOUTM */
|
||||
{P5_0 , 1 , 1 }, /* TXCLKOUTP */
|
||||
{P2_11 , 4 , 0 }, /* SSITxD0 */
|
||||
{P4_7 , 5 , 0 }, /* SSITxD0 */
|
||||
{P7_4 , 6 , 0 }, /* SSITxD1 */
|
||||
{P4_15 , 6 , 0 }, /* SSITxD3 */
|
||||
{P7_11 , 2 , 0 }, /* SSITxD3 */
|
||||
{P2_7 , 4 , 0 }, /* SSITxD5 */
|
||||
{P4_11 , 5 , 0 }, /* SSITxD5 */
|
||||
{P8_10 , 8 , 0 }, /* SSITxD5 */
|
||||
{P3_7 , 8 , 0 }, /* WDTOVF */
|
||||
{NC , 0 , -1}
|
||||
#else
|
||||
// pin func pm
|
||||
{P4_0 , 2 , -1}, // TIOC0A
|
||||
{P5_0 , 6 , -1}, // TIOC0A
|
||||
{P4_2 , 2 , -1}, // TIOC0C
|
||||
{P5_5 , 6 , -1}, // TIOC0C
|
||||
//
|
||||
{P8_14 , 4 , -1}, // TIOC2A
|
||||
//
|
||||
{P8_10 , 4 , -1}, // TIOC3A
|
||||
{P5_3 , 6 , -1}, // TIOC3C
|
||||
{P8_12 , 4 , -1}, // TIOC3C
|
||||
//
|
||||
{P3_8 , 6 , -1}, // TIOC4A
|
||||
{P4_4 , 3 , -1}, // TIOC4A
|
||||
{P3_10 , 6 , -1}, // TIOC4C
|
||||
{P4_6 , 3 , -1}, // TIOC4C
|
||||
//
|
||||
{P5_7 , 1 , 1 }, // TXOUT0M
|
||||
{P5_6 , 1 , 1 }, // TXOUT0P
|
||||
{P5_5 , 1 , 1 }, // TXOUT1M
|
||||
{P5_4 , 1 , 1 }, // TXOUT1P
|
||||
{P5_3 , 1 , 1 }, // TXOUT2M
|
||||
{P5_2 , 1 , 1 }, // TXOUT2P
|
||||
{P5_1 , 1 , 1 }, // TXCLKOUTM
|
||||
{P5_0 , 1 , 1 }, // TXCLKOUTP
|
||||
{P4_7 , 5 , 0 }, // SSITxD0
|
||||
{P8_10 , 8 , 0 }, // SSITxD5
|
||||
{P3_7 , 8 , 0 }, // WDTOVF
|
||||
{NC , 0 , -1}
|
||||
#endif
|
||||
};
|
||||
|
||||
/************ADC***************/
|
||||
const PinMap PinMap_ADC[] = {
|
||||
#ifdef MAX_PERI
|
||||
{P1_8, AN0, 1},
|
||||
{P1_9, AN1, 1},
|
||||
{P1_10, AN2, 1},
|
||||
{P1_11, AN3, 1},
|
||||
{P1_12, AN4, 1},
|
||||
{P1_13, AN5, 1},
|
||||
{P1_14, AN6, 1},
|
||||
{P1_15, AN7, 1},
|
||||
{NC, NC, 0}
|
||||
#else
|
||||
{P1_8, AN0, 1},
|
||||
{P1_9, AN1, 1},
|
||||
{P1_10, AN2, 1},
|
||||
{P1_11, AN3, 1},
|
||||
{P1_12, AN4, 1},
|
||||
{P1_13, AN5, 1},
|
||||
{P1_15, AN7, 1},
|
||||
{NC, NC, 0}
|
||||
#endif
|
||||
};
|
||||
|
||||
/************I2C***************/
|
||||
const PinMap PinMap_I2C_SDA[] = {
|
||||
{P1_1 , I2C_0, 1},
|
||||
{P1_3 , I2C_1, 1},
|
||||
{P1_5 , I2C_2, 1},
|
||||
{P1_7 , I2C_3, 1},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_I2C_SCL[] = {
|
||||
{P1_0 , I2C_0, 1},
|
||||
{P1_2 , I2C_1, 1},
|
||||
{P1_4 , I2C_2, 1},
|
||||
{P1_6 , I2C_3, 1},
|
||||
{NC , NC, 0}
|
||||
};
|
||||
|
||||
/************UART***************/
|
||||
const PinMap PinMap_UART_TX[] = {
|
||||
#ifdef MAX_PERI
|
||||
{P2_14 , UART0, 6},
|
||||
{P4_9 , UART0, 7},
|
||||
{P6_9 , UART0, 5},
|
||||
{P2_5 , UART1, 6},
|
||||
{P4_12 , UART1, 7},
|
||||
{P6_12 , UART1, 5},
|
||||
{P9_3 , UART1, 4},
|
||||
{P3_0 , UART2, 6},
|
||||
{P3_1 , UART2, 4},
|
||||
{P4_2 , UART2, 5},
|
||||
{P4_14 , UART2, 7},
|
||||
{P6_3 , UART2, 7},
|
||||
{P8_6 , UART2, 7},
|
||||
{P3_5 , UART3, 7},
|
||||
{P5_3 , UART3, 5},
|
||||
{P6_1 , UART3, 7},
|
||||
{P8_8 , UART3, 7},
|
||||
{P5_0 , UART4, 5},
|
||||
{P7_1 , UART4, 4},
|
||||
{P8_14 , UART4, 7},
|
||||
{P6_6 , UART5, 5},
|
||||
{P8_1 , UART5, 4},
|
||||
{P8_13 , UART5, 5},
|
||||
{P5_6 , UART6, 5},
|
||||
{P6_14 , UART6, 4},
|
||||
{P7_4 , UART7, 4},
|
||||
{NC , NC , 0}
|
||||
#else
|
||||
{P3_0 , UART2, 6},
|
||||
{P3_1 , UART2, 4},
|
||||
{P4_2 , UART2, 5},
|
||||
{P5_3 , UART3, 5},
|
||||
{P8_8 , UART3, 7},
|
||||
{P5_0 , UART4, 5},
|
||||
{P8_14 , UART4, 7},
|
||||
{P8_13 , UART5, 5},
|
||||
{P5_6 , UART6, 5},
|
||||
{NC , NC , 0}
|
||||
#endif
|
||||
};
|
||||
|
||||
const PinMap PinMap_UART_RX[] = {
|
||||
#ifdef MAX_PERI
|
||||
{P2_15 , UART0, 6},
|
||||
{P4_10 , UART0, 7},
|
||||
{P6_10 , UART0, 5},
|
||||
{P2_6 , UART1, 6},
|
||||
{P4_13 , UART1, 7},
|
||||
{P6_13 , UART1, 5},
|
||||
{P9_4 , UART1, 4},
|
||||
{P3_2 , UART2, 4},
|
||||
{P4_3 , UART2, 5},
|
||||
{P4_15 , UART2, 7},
|
||||
{P6_2 , UART2, 7},
|
||||
{P8_4 , UART2, 7},
|
||||
{P3_6 , UART3, 7},
|
||||
{P5_4 , UART3, 5},
|
||||
{P6_0 , UART3, 7},
|
||||
{P8_9 , UART3, 7},
|
||||
{P5_1 , UART4, 5},
|
||||
{P7_2 , UART4, 4},
|
||||
{P8_15 , UART4, 7},
|
||||
{P6_7 , UART5, 5},
|
||||
{P8_2 , UART5, 4},
|
||||
{P8_11 , UART5, 5},
|
||||
{P5_7 , UART6, 5},
|
||||
{P6_15 , UART6, 4},
|
||||
{P7_5 , UART7, 4},
|
||||
{NC , NC , 0}
|
||||
#else
|
||||
{P3_2 , UART2, 4},
|
||||
{P4_3 , UART2, 5},
|
||||
{P5_4 , UART3, 5},
|
||||
{P8_9 , UART3, 7},
|
||||
{P5_1 , UART4, 5},
|
||||
{P8_15 , UART4, 7},
|
||||
{P8_11 , UART5, 5},
|
||||
{P5_7 , UART6, 5},
|
||||
{NC , NC , 0}
|
||||
#endif
|
||||
};
|
||||
|
||||
const PinMap PinMap_UART_CTS[] = {
|
||||
#ifdef MAX_PERI
|
||||
{P2_3 , UART1, 6},
|
||||
{P9_5 , UART1, 4},
|
||||
{P6_3 , UART5, 5},
|
||||
{P7_15 , UART5, 4},
|
||||
{P7_6 , UART7, 4},
|
||||
{NC , NC , 0}
|
||||
#else
|
||||
{NC , NC , 0}
|
||||
#endif
|
||||
};
|
||||
|
||||
const PinMap PinMap_UART_RTS[] = {
|
||||
#ifdef MAX_PERI
|
||||
{P2_7 , UART1, 6},
|
||||
{P9_6 , UART1, 4},
|
||||
{P6_4 , UART5, 5},
|
||||
{P8_3 , UART5, 4},
|
||||
{P7_7 , UART7, 4},
|
||||
{NC , NC , 0}
|
||||
#else
|
||||
{NC , NC , 0}
|
||||
#endif
|
||||
};
|
||||
|
||||
/************SPI***************/
|
||||
const PinMap PinMap_SPI_SCLK[] = {
|
||||
#ifdef MAX_PERI
|
||||
{P2_12 , SPI_0, 2},
|
||||
{P7_15 , SPI_0, 2},
|
||||
{P4_4 , SPI_1, 2},
|
||||
{P6_4 , SPI_1, 7},
|
||||
{P8_3 , SPI_2, 3},
|
||||
{P8_14 , SPI_2, 5},
|
||||
{P3_0 , SPI_3, 8},
|
||||
{P5_0 , SPI_3, 8},
|
||||
{P2_8 , SPI_4, 8},
|
||||
{P4_0 , SPI_4, 7},
|
||||
{NC , NC , 0}
|
||||
#else
|
||||
{P4_4 , SPI_1, 2},
|
||||
{P8_14 , SPI_2, 5},
|
||||
{P5_0 , SPI_3, 8},
|
||||
{P4_0 , SPI_4, 7},
|
||||
{NC , NC , 0}
|
||||
#endif
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_MOSI[] = {
|
||||
#ifdef MAX_PERI
|
||||
{P2_14 , SPI_0, 2},
|
||||
{P8_1 , SPI_0, 2},
|
||||
{P4_6 , SPI_1, 2},
|
||||
{P6_6 , SPI_1, 7},
|
||||
{P8_5 , SPI_2, 3},
|
||||
{P9_0 , SPI_2, 5},
|
||||
{P3_2 , SPI_3, 8},
|
||||
{P5_2 , SPI_3, 8},
|
||||
{P2_10 , SPI_4, 8},
|
||||
{P4_2 , SPI_4, 7},
|
||||
{NC , NC , 0}
|
||||
#else
|
||||
{P4_6 , SPI_1, 2},
|
||||
{P9_0 , SPI_2, 5},
|
||||
{P5_2 , SPI_3, 8},
|
||||
{P4_2 , SPI_4, 7},
|
||||
{NC , NC , 0}
|
||||
#endif
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_MISO[] = {
|
||||
#ifdef MAX_PERI
|
||||
{P2_15 , SPI_0, 2},
|
||||
{P8_2 , SPI_0, 2},
|
||||
{P4_7 , SPI_1, 2},
|
||||
{P6_7 , SPI_1, 7},
|
||||
{P8_6 , SPI_2, 3},
|
||||
{P9_1 , SPI_2, 5},
|
||||
{P3_3 , SPI_3, 8},
|
||||
{P5_3 , SPI_3, 8},
|
||||
{P2_11 , SPI_4, 8},
|
||||
{P4_3 , SPI_4, 7},
|
||||
{NC , NC , 0}
|
||||
#else
|
||||
{P4_7 , SPI_1, 2},
|
||||
{P9_1 , SPI_2, 5},
|
||||
{P5_3 , SPI_3, 8},
|
||||
{P4_3 , SPI_4, 7},
|
||||
{NC , NC , 0}
|
||||
#endif
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_SSEL[] = {
|
||||
#ifdef MAX_PERI
|
||||
{P2_13 , SPI_0, 2},
|
||||
{P8_0 , SPI_0, 2},
|
||||
{P4_5 , SPI_1, 2},
|
||||
{P6_5 , SPI_1, 7},
|
||||
{P8_4 , SPI_2, 3},
|
||||
{P8_15 , SPI_2, 5},
|
||||
{P3_1 , SPI_3, 8},
|
||||
{P5_1 , SPI_3, 8},
|
||||
{P2_9 , SPI_4, 8},
|
||||
{P4_1 , SPI_4, 7},
|
||||
{NC , NC , 0}
|
||||
#else
|
||||
{P4_5 , SPI_1, 2},
|
||||
{P8_15 , SPI_2, 5},
|
||||
{P5_1 , SPI_3, 8},
|
||||
{P4_1 , SPI_4, 7},
|
||||
{NC , NC , 0}
|
||||
#endif
|
||||
};
|
||||
|
||||
/************PWM***************/
|
||||
const PinMap PinMap_PWM[] = {
|
||||
#ifdef MAX_PERI
|
||||
// TIOC0 A,C
|
||||
{P4_0 , PWM_TIOC0A, 2}, //TIOC0A
|
||||
{P5_0 , PWM_TIOC0A, 6}, //TIOC0A
|
||||
{P7_0 , PWM_TIOC0A, 7}, //TIOC0A
|
||||
{P4_2 , PWM_TIOC0C, 2}, //TIOC0C
|
||||
{P5_5 , PWM_TIOC0C, 6}, //TIOC0C
|
||||
{P7_2 , PWM_TIOC0C, 7}, //TIOC0C
|
||||
//TIOC1 A
|
||||
{P2_11 , PWM_TIOC1A, 5}, //TIOC1A
|
||||
{P6_0 , PWM_TIOC1A, 5}, //TIOC1A
|
||||
{P7_4 , PWM_TIOC1A, 7}, //TIOC1A
|
||||
{P8_8 , PWM_TIOC1A, 5}, //TIOC1A
|
||||
{P9_7 , PWM_TIOC1A, 4}, //TIOC1A
|
||||
//TIOC2 A
|
||||
{P2_1 , PWM_TIOC2A, 6}, //TIOC2A
|
||||
{P6_2 , PWM_TIOC2A, 6}, //TIOC2A
|
||||
{P7_6 , PWM_TIOC2A, 7}, //TIOC2A
|
||||
{P8_14 , PWM_TIOC2A, 4}, //TIOC2A
|
||||
//TIOC3 A,C
|
||||
{P3_4 , PWM_TIOC3A, 6}, //TIOC3A
|
||||
{P7_8 , PWM_TIOC3A, 7}, //TIOC3A
|
||||
{P8_10 , PWM_TIOC3A, 4}, //TIOC3A
|
||||
{P3_6 , PWM_TIOC3C, 6}, //TIOC3C
|
||||
{P7_10 , PWM_TIOC3C, 7}, //TIOC3C
|
||||
{P8_12 , PWM_TIOC3C, 4}, //TIOC3C
|
||||
//TIOC4 A,C
|
||||
{P3_8 , PWM_TIOC4A, 6}, //TIOC4A
|
||||
{P4_4 , PWM_TIOC4A, 3}, //TIOC4A
|
||||
{P7_12 , PWM_TIOC4A, 7}, //TIOC4A
|
||||
{P3_10 , PWM_TIOC4C, 6}, //TIOC4C
|
||||
{P4_6 , PWM_TIOC4C, 3}, //TIOC4C
|
||||
{P7_14 , PWM_TIOC4C, 7}, //TIOC4C
|
||||
//PWM1
|
||||
{P8_8 , PWM_PWM1A , 6}, //PWM1A
|
||||
{P8_9 , PWM_PWM1B , 6}, //PWM1B
|
||||
{P8_10 , PWM_PWM1C , 6}, //PWM1C
|
||||
{P8_11 , PWM_PWM1D , 6}, //PWM1D
|
||||
{P8_12 , PWM_PWM1E , 6}, //PWM1E
|
||||
{P8_13 , PWM_PWM1F , 6}, //PWM1F
|
||||
{P8_14 , PWM_PWM1G , 6}, //PWM1G
|
||||
{P8_15 , PWM_PWM1H , 6}, //PWM1H
|
||||
//PWM2
|
||||
{P3_0 , PWM_PWM2A , 7}, //PWM2A
|
||||
{P3_1 , PWM_PWM2B , 7}, //PWM2B
|
||||
{P3_2 , PWM_PWM2C , 7}, //PWM2C
|
||||
{P3_3 , PWM_PWM2D , 7}, //PWM2D
|
||||
{P4_4 , PWM_PWM2E , 4}, //PWM2E
|
||||
{P4_5 , PWM_PWM2F , 4}, //PWM2F
|
||||
{P4_6 , PWM_PWM2G , 4}, //PWM2G
|
||||
{P4_7 , PWM_PWM2H , 4}, //PWM2H
|
||||
{NC , NC , 0}
|
||||
#else
|
||||
//TIOC0 A,C
|
||||
{P4_0 , PWM_TIOC0A, 2}, //TIOC0A
|
||||
{P5_0 , PWM_TIOC0A, 6}, //TIOC0A
|
||||
{P4_2 , PWM_TIOC0C, 2}, //TIOC0C
|
||||
{P5_5 , PWM_TIOC0C, 6}, //TIOC0C
|
||||
//TIOC2 A
|
||||
{P8_14 , PWM_TIOC2A, 4}, //TIOC2A
|
||||
//TIOC3 A,C
|
||||
{P8_10 , PWM_TIOC3A, 4}, //TIOC3A
|
||||
{P5_3 , PWM_TIOC3C, 6}, //TIOC3C
|
||||
{P8_12 , PWM_TIOC3C, 4}, //TIOC3C
|
||||
//TIOC4 A,C
|
||||
{P3_8 , PWM_TIOC4A, 6}, //TIOC4A
|
||||
{P4_4 , PWM_TIOC4A, 3}, //TIOC4A
|
||||
{P3_10 , PWM_TIOC4C, 6}, //TIOC4C
|
||||
{P4_6 , PWM_TIOC4C, 3}, //TIOC4C
|
||||
//PWM1
|
||||
{P8_10 , PWM_PWM1C , 6}, //PWM1C
|
||||
{P8_11 , PWM_PWM1D , 6}, //PWM1D
|
||||
{P8_12 , PWM_PWM1E , 6}, //PWM1E
|
||||
{P8_13 , PWM_PWM1F , 6}, //PWM1F
|
||||
{P8_14 , PWM_PWM1G , 6}, //PWM1G
|
||||
{P8_15 , PWM_PWM1H , 6}, //PWM1H
|
||||
//PWM2
|
||||
{P3_0 , PWM_PWM2A , 7}, //PWM2A
|
||||
{P3_1 , PWM_PWM2B , 7}, //PWM2B
|
||||
{P3_2 , PWM_PWM2C , 7}, //PWM2C
|
||||
{P4_4 , PWM_PWM2E , 4}, //PWM2E
|
||||
{P4_5 , PWM_PWM2F , 4}, //PWM2F
|
||||
{P4_6 , PWM_PWM2G , 4}, //PWM2G
|
||||
{P4_7 , PWM_PWM2H , 4}, //PWM2H
|
||||
{NC , NC , 0}
|
||||
#endif
|
||||
};
|
||||
|
||||
/************CAN***************/
|
||||
const PinMap PinMap_CAN_RD[] = {
|
||||
#ifdef MAX_PERI
|
||||
{P7_8 , CAN_0, 4},
|
||||
{P9_1 , CAN_0, 3},
|
||||
{P1_4 , CAN_1, 3},
|
||||
{P5_9 , CAN_1, 5},
|
||||
{P7_11 , CAN_1, 4},
|
||||
{P4_9 , CAN_2, 6},
|
||||
{P6_4 , CAN_2, 3},
|
||||
{P7_2 , CAN_2, 5},
|
||||
{P2_12 , CAN_3, 5},
|
||||
{P4_2 , CAN_3, 4},
|
||||
{P1_5 , CAN_4, 3},
|
||||
{P2_14 , CAN_4, 5},
|
||||
{NC , NC , 0}
|
||||
#else
|
||||
{P9_1 , CAN_0, 3},
|
||||
{P1_4 , CAN_1, 3},
|
||||
{P5_9 , CAN_1, 5},
|
||||
{P4_2 , CAN_3, 4},
|
||||
{P1_5 , CAN_4, 3},
|
||||
{NC , NC , 0}
|
||||
#endif
|
||||
};
|
||||
|
||||
const PinMap PinMap_CAN_TD[] = {
|
||||
#ifdef MAX_PERI
|
||||
{P7_9 , CAN_0, 4},
|
||||
{P9_0 , CAN_0, 3},
|
||||
{P5_10 , CAN_1, 5},
|
||||
{P7_10 , CAN_1, 4},
|
||||
{P4_8 , CAN_2, 6},
|
||||
{P6_5 , CAN_2, 3},
|
||||
{P7_3 , CAN_2, 5},
|
||||
{P2_13 , CAN_3, 5},
|
||||
{P4_3 , CAN_3, 4},
|
||||
{P4_11 , CAN_4, 6},
|
||||
{P8_10 , CAN_4, 5},
|
||||
{NC , NC , 0}
|
||||
#else
|
||||
{P9_0 , CAN_0, 3},
|
||||
{P5_10 , CAN_1, 5},
|
||||
{P4_3 , CAN_3, 4},
|
||||
{P8_10 , CAN_4, 5},
|
||||
{NC , NC , 0}
|
||||
#endif
|
||||
};
|
||||
|
||||
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Reference in New Issue