diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_M2351/lp_ticker.c index dbd500b3f6..6cd58dc166 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/lp_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_M2351/lp_ticker.c @@ -13,213 +13,194 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #include "lp_ticker_api.h" #if DEVICE_LOWPOWERTIMER #include "sleep_api.h" +#include "mbed_wait_api.h" +#include "mbed_assert.h" #include "nu_modutil.h" #include "nu_miscutil.h" -#include "mbed_critical.h" +#include "partition_M2351.h" -// lp_ticker tick = us = timestamp -#define US_PER_TICK (1) -#define US_PER_SEC (1000 * 1000) +/* We have the following policy for configuring security state of TIMER for us_ticer/lp_ticker: + * + * TIMER0: Hard-wired to secure and used for secure us_ticer + * TIMER1: Hard-wired to secure and used for secure lp_ticer + * TIMER2: Configured to non-secure and used for non-secure us_ticer + * TIMER3: Configured to non-secure and used for non-secure lp_ticer + */ +#if (! defined(SCU_INIT_PNSSET2_VAL)) || (! (SCU_INIT_PNSSET2_VAL & (1 << 17))) +#error("TIMER2/3 must be configured to non-secure for non-secure us_ticker/lp_ticker.") +#endif -#define US_PER_TMR2_INT (US_PER_SEC * 10) // 10 second per interrupt -#define TMR2_CLK_PER_SEC (__LXT) -#define TMR2_CLK_PER_TMR2_INT ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC)) // CMPDAT for 10 second -#define TMR3_CLK_PER_SEC (__LXT) +/* Micro seconds per second */ +#define NU_US_PER_SEC 1000000 +/* Timer clock per lp_ticker tick */ +#define NU_TMRCLK_PER_TICK 1 +/* Timer clock per second */ +#define NU_TMRCLK_PER_SEC (__LXT) +/* Timer max counter bit size */ +#define NU_TMR_MAXCNT_BITSIZE 24 +/* Timer max counter */ +#define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +static void tmr1_vec(void); + +/* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */ +static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; + +#define TIMER_MODINIT timer1_modinit + +#else -static void tmr2_vec(void); static void tmr3_vec(void); -static void lp_ticker_arm_cd(void); -static int lp_ticker_inited = 0; -static volatile uint32_t counter_major = 0; -static volatile uint32_t cd_major_minor_clks = 0; -static volatile uint32_t cd_minor_clks = 0; -static volatile uint32_t wakeup_tick = (uint32_t) -1; - -// NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. -// NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled wakeup -static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) tmr2_vec}; +/* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */ static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) tmr3_vec}; +#define TIMER_MODINIT timer3_modinit + +#endif + +static int ticker_inited = 0; + #define TMR_CMP_MIN 2 #define TMR_CMP_MAX 0xFFFFFFu -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -__attribute__((cmse_nonsecure_entry)) void lp_ticker_init(void) { - if (lp_ticker_inited) { + if (ticker_inited) { return; } - lp_ticker_inited = 1; - - counter_major = 0; - cd_major_minor_clks = 0; - cd_minor_clks = 0; - wakeup_tick = (uint32_t) -1; + ticker_inited = 1; - // Reset module - SYS_ResetModule(timer2_modinit.rsetidx); - SYS_ResetModule(timer3_modinit.rsetidx); - - // Select IP clock source - CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv); - CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv); - // Enable IP clock - CLK_EnableModuleClock(timer2_modinit.clkidx); - CLK_EnableModuleClock(timer3_modinit.clkidx); + /* Reset module + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + SYS_ResetModule_S(TIMER_MODINIT.rsetidx); + + /* Select IP clock source + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_SetModuleClock_S(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); + + /* Enable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_EnableModuleClock_S(TIMER_MODINIT.clkidx); + + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); // Configure clock - uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); - uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127); - MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0); - uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT; - MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX); + uint32_t clk_timer = TIMER_GetModuleClock(timer_base); + uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; + MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); + MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); + uint32_t cmp_timer = TMR_CMP_MAX; + MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); // Continuous mode - // NOTE: TIMER_CNT is updated continuously by default. - ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2; - ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2; - + // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480/M2351. In M451/M480/M2351, TIMER_CNT is updated continuously by default. + timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/; + timer_base->CMP = cmp_timer; + // Set vector - NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var); - NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var); - - NVIC_EnableIRQ(timer2_modinit.irq_n); - NVIC_EnableIRQ(timer3_modinit.irq_n); - - TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); - TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); - - // NOTE: TIMER_Start() first and then lp_ticker_set_interrupt(); otherwise, we may get stuck in lp_ticker_read() because - // timer is not running. - - // Start timer - TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); - - // Schedule wakeup to match semantics of lp_ticker_get_compare_match() - lp_ticker_set_interrupt(wakeup_tick); + NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); + + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); + + TIMER_EnableInt(timer_base); + TIMER_EnableWakeup(timer_base); + + /* NOTE: When system clock is higher than timer clock, we need to add 3 engine clock + * (recommended by designer) delay to wait for above timer control to take effect. */ + + /* Add delay to wait for above timer control to take effect before enabling timer counting */ + wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + TIMER_Start(timer_base); + + /* Add delay to wait for timer to start counting and raise active flag + * + * It is possible timer active bit cannot be set in time while we check it, and the while loop + * below would return immediately. */ + wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk)); } -#endif timestamp_t lp_ticker_read() -{ - if (! lp_ticker_inited) { +{ + if (! ticker_inited) { lp_ticker_init(); } - - TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname); - - do { - uint64_t major_minor_clks; - uint32_t minor_clks; - - // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time. - // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read. - do { - core_util_critical_section_enter(); - - // NOTE: Order of reading minor_us/carry here is significant. - minor_clks = TIMER_GetCounter(timer2_base); - uint32_t carry = (timer2_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0; - // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP. - if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) { - major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT; - } - else { - major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks; - } - - core_util_critical_section_exit(); - } - while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT); - // Add power-down compensation - return ((uint64_t) major_minor_clks * US_PER_SEC / TMR3_CLK_PER_SEC / US_PER_TICK); - } - while (0); + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK); } void lp_ticker_set_interrupt(timestamp_t timestamp) { - uint32_t delta = timestamp - lp_ticker_read(); - wakeup_tick = timestamp; - - TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - - cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC; - lp_ticker_arm_cd(); -} - -void lp_ticker_fire_interrupt(void) -{ - cd_major_minor_clks = cd_minor_clks = 0; - /** - * This event was in the past. Set the interrupt as pending, but don't process it here. - * This prevents a recurive loop under heavy load which can lead to a stack overflow. + /* In continuous mode, counter will be reset to zero with the following sequence: + * 1. Stop counting + * 2. Configure new CMP value + * 3. Restart counting + * + * This behavior is not what we want. To fix it, we could configure new CMP value + * without stopping counting first. */ - NVIC_SetPendingIRQ(timer3_modinit.irq_n); + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of + * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ + uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; + cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); + timer_base->CMP = cmp_timer; } void lp_ticker_disable_interrupt(void) { - TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); + TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } void lp_ticker_clear_interrupt(void) { - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } -static void tmr2_vec(void) +void lp_ticker_fire_interrupt(void) { - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); - TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); - counter_major ++; + // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here. + // This prevents a recursive loop under heavy load which can lead to a stack overflow. + NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n); } +const ticker_info_t* lp_ticker_get_info() +{ + static const ticker_info_t info = { + NU_TMRCLK_PER_SEC / NU_TMRCLK_PER_TICK, + NU_TMR_MAXCNT_BITSIZE + }; + return &info; +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +static void tmr1_vec(void) +#else static void tmr3_vec(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - - cd_major_minor_clks = (cd_major_minor_clks > cd_minor_clks) ? (cd_major_minor_clks - cd_minor_clks) : 0; - if (cd_major_minor_clks == 0) { - // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler(); - lp_ticker_irq_handler(); - } - else { - lp_ticker_arm_cd(); - } -} - -static void lp_ticker_arm_cd(void) -{ - TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname); - - timer3_base->CNT = 0; - while (timer3_base->CNT & TIMER_CNT_RSTACT_Msk); - // One-shot mode, Clock = 32 KHz - uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127); - MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0); - // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480/M2351. In M451/M480/M2351, TIMER_CNT is updated continuously by default. - timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/); - timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3/* | TIMER_CTL_CNTDATEN_Msk*/; - - cd_minor_clks = cd_major_minor_clks; - cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX); - timer3_base->CMP = cd_minor_clks; - - TIMER_EnableInt(timer3_base); - TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - TIMER_Start(timer3_base); -} +#endif +{ + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + + // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler(); + lp_ticker_irq_handler(); +} + #endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_M2351/us_ticker.c index ea8f89f5df..573d1a6d25 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/us_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_M2351/us_ticker.c @@ -13,215 +13,171 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #include "us_ticker_api.h" #include "sleep_api.h" #include "mbed_assert.h" #include "nu_modutil.h" #include "nu_miscutil.h" -#include "mbed_critical.h" +#include "partition_M2351.h" +/* We have the following policy for configuring security state of TIMER for us_ticer/lp_ticker: + * + * TIMER0: Hard-wired to secure and used for secure us_ticer + * TIMER1: Hard-wired to secure and used for secure lp_ticer + * TIMER2: Configured to non-secure and used for non-secure us_ticer + * TIMER3: Configured to non-secure and used for non-secure lp_ticer + */ +#if (! defined(SCU_INIT_PNSSET2_VAL)) || (! (SCU_INIT_PNSSET2_VAL & (1 << 17))) +#error("TIMER2/3 must be configured to non-secure for non-secure us_ticker/lp_ticker.") +#endif -// us_ticker tick = us = timestamp -#define US_PER_TICK 1 -#define US_PER_SEC (1000 * 1000) - -#define TMR0HIRES_CLK_PER_SEC (1000 * 1000) -#define TMR1HIRES_CLK_PER_SEC (1000 * 1000) - -#define US_PER_TMR0HIRES_CLK (US_PER_SEC / TMR0HIRES_CLK_PER_SEC) -#define US_PER_TMR1HIRES_CLK (US_PER_SEC / TMR1HIRES_CLK_PER_SEC) - -#define US_PER_TMR0HIRES_INT (1000 * 1000 * 10) -#define TMR0HIRES_CLK_PER_TMR0HIRES_INT ((uint32_t) ((uint64_t) US_PER_TMR0HIRES_INT * TMR0HIRES_CLK_PER_SEC / US_PER_SEC)) +/* Micro seconds per second */ +#define NU_US_PER_SEC 1000000 +/* Timer clock per us_ticker tick */ +#define NU_TMRCLK_PER_TICK 1 +/* Timer clock per second */ +#define NU_TMRCLK_PER_SEC (1000 * 1000) +/* Timer max counter bit size */ +#define NU_TMR_MAXCNT_BITSIZE 24 +/* Timer max counter */ +#define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) static void tmr0_vec(void); -static void tmr1_vec(void); -static void us_ticker_arm_cd(void); -static int us_ticker_inited = 0; -static volatile uint32_t counter_major = 0; -static volatile uint32_t cd_major_minor_us = 0; -static volatile uint32_t cd_minor_us = 0; +static const struct nu_modinit_s timer0_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec}; -// NOTE: PCLK is set up in mbed_sdk_init(), invocation of which must be before C++ global object constructor. See init_api.c for details. -// NOTE: Choose clock source of timer: -// 1. HIRC: Be the most accurate but might cause unknown HardFault. -// 2. HXT: Less accurate and cannot pass mbed-drivers test. -// 3. PCLK(HXT): Less accurate but can pass mbed-drivers test. -// NOTE: TIMER_0 for normal counter, TIMER_1 for countdown. +#define TIMER_MODINIT timer0_modinit -static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec}; -static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; +#else + +static void tmr2_vec(void); + +static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_PCLK1, 0, TMR2_RST, TMR2_IRQn, (void *) tmr2_vec}; + +#define TIMER_MODINIT timer2_modinit + +#endif + +static int ticker_inited = 0; #define TMR_CMP_MIN 2 #define TMR_CMP_MAX 0xFFFFFFu -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -__attribute__((cmse_nonsecure_entry)) void us_ticker_init(void) { - if (us_ticker_inited) { + if (ticker_inited) { return; } - - counter_major = 0; - cd_major_minor_us = 0; - cd_minor_us = 0; - us_ticker_inited = 1; - - // Reset IP - SYS_ResetModule(timer0hires_modinit.rsetidx); - SYS_ResetModule(timer1hires_modinit.rsetidx); - - // Select IP clock source - CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv); - CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv); - // Enable IP clock - CLK_EnableModuleClock(timer0hires_modinit.clkidx); - CLK_EnableModuleClock(timer1hires_modinit.clkidx); + ticker_inited = 1; + + /* Reset module + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + SYS_ResetModule_S(TIMER_MODINIT.rsetidx); + + /* Select IP clock source + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_SetModuleClock_S(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); + + /* Enable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_EnableModuleClock_S(TIMER_MODINIT.clkidx); + + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); // Timer for normal counter - uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); - uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127); - MBED_ASSERT((clk_timer0 % TMR0HIRES_CLK_PER_SEC) == 0); - uint32_t cmp_timer0 = TMR0HIRES_CLK_PER_TMR0HIRES_INT; - MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX); - // NOTE: TIMER_CNT is updated continuously by default. - ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer0; - ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMP = cmp_timer0; - - NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var); - NVIC_SetVector(timer1hires_modinit.irq_n, (uint32_t) timer1hires_modinit.var); - - NVIC_EnableIRQ(timer0hires_modinit.irq_n); - NVIC_EnableIRQ(timer1hires_modinit.irq_n); - - TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); - TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); + uint32_t clk_timer = TIMER_GetModuleClock(timer_base); + uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; + MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); + MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); + uint32_t cmp_timer = TMR_CMP_MAX; + MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); + // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480/M2351. In M451/M480/M2351, TIMER_CNT is updated continuously by default. + timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/; + timer_base->CMP = cmp_timer; + NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); + + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); + + TIMER_EnableInt(timer_base); + + TIMER_Start(timer_base); + while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk)); } -#endif -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -__attribute__((cmse_nonsecure_entry)) uint32_t us_ticker_read() { - if (! us_ticker_inited) { + if (! ticker_inited) { us_ticker_init(); } - - TIMER_T * timer0_base = (TIMER_T *) NU_MODBASE(timer0hires_modinit.modname); - - do { - uint32_t major_minor_us; - uint32_t minor_us; - // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time. - // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read. - do { - core_util_critical_section_enter(); - - // NOTE: Order of reading minor_us/carry here is significant. - minor_us = TIMER_GetCounter(timer0_base) * US_PER_TMR0HIRES_CLK; - uint32_t carry = (timer0_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0; - // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP. - if (carry && minor_us > (US_PER_TMR0HIRES_INT / 2)) { - major_minor_us = (counter_major + 1) * US_PER_TMR0HIRES_INT; - } - else { - major_minor_us = (counter_major + carry) * US_PER_TMR0HIRES_INT + minor_us; - } - - core_util_critical_section_exit(); + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); - } - while (minor_us == 0 || minor_us == US_PER_TMR0HIRES_INT); - - return (major_minor_us / US_PER_TICK); - } - while (0); -} -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -__attribute__((cmse_nonsecure_entry)) -void us_ticker_disable_interrupt(void) -{ - TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); + return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK); } -__attribute__((cmse_nonsecure_entry)) -void us_ticker_clear_interrupt(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); -} - -__attribute__((cmse_nonsecure_entry)) void us_ticker_set_interrupt(timestamp_t timestamp) { - TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); + /* In continuous mode, counter will be reset to zero with the following sequence: + * 1. Stop counting + * 2. Configure new CMP value + * 3. Restart counting + * + * This behavior is not what we want. To fix it, we could configure new CMP value + * without stopping counting first. + */ + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); - uint32_t delta = timestamp - us_ticker_read(); - cd_major_minor_us = delta * US_PER_TICK; - us_ticker_arm_cd(); + /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of + * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ + uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; + cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); + timer_base->CMP = cmp_timer; +} + +void us_ticker_disable_interrupt(void) +{ + TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); +} + +void us_ticker_clear_interrupt(void) +{ + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } -__attribute__((cmse_nonsecure_entry)) void us_ticker_fire_interrupt(void) { - cd_major_minor_us = cd_minor_us = 0; - /** - * This event was in the past. Set the interrupt as pending, but don't process it here. - * This prevents a recurive loop under heavy load which can lead to a stack overflow. - */ - NVIC_SetPendingIRQ(timer1hires_modinit.irq_n); + // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here. + // This prevents a recursive loop under heavy load which can lead to a stack overflow. + NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n); } -#endif +const ticker_info_t* us_ticker_get_info() +{ + static const ticker_info_t info = { + NU_TMRCLK_PER_SEC / NU_TMRCLK_PER_TICK, + NU_TMR_MAXCNT_BITSIZE + }; + return &info; +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) static void tmr0_vec(void) +#else +static void tmr2_vec(void) +#endif { - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); - counter_major ++; -} - -static void tmr1_vec(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); - cd_major_minor_us = (cd_major_minor_us > cd_minor_us) ? (cd_major_minor_us - cd_minor_us) : 0; - if (cd_major_minor_us == 0) { - // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler(); - us_ticker_irq_handler(); - } - else { - us_ticker_arm_cd(); - } -} - -static void us_ticker_arm_cd(void) -{ - TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1hires_modinit.modname); + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); - cd_minor_us = cd_major_minor_us; - - // Reset 24-bit up counter - timer1_base->CNT = 0; - while (timer1_base->CNT & TIMER_CNT_RSTACT_Msk); - // One-shot mode, Clock = 1 MHz - uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); - uint32_t prescale_timer1 = clk_timer1 / TMR1HIRES_CLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127); - MBED_ASSERT((clk_timer1 % TMR1HIRES_CLK_PER_SEC) == 0); - // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480/M2351. In M451/M480/M2351, TIMER_CNT is updated continuously by default. - timer1_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/); - timer1_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer1/* | TIMER_CTL_CNTDATEN_Msk*/; - - uint32_t cmp_timer1 = cd_minor_us / US_PER_TMR1HIRES_CLK; - cmp_timer1 = NU_CLAMP(cmp_timer1, TMR_CMP_MIN, TMR_CMP_MAX); - timer1_base->CMP = cmp_timer1; - - TIMER_EnableInt(timer1_base); - TIMER_Start(timer1_base); + // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler(); + us_ticker_irq_handler(); }