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FastModels: add a new parent platform ARM_FM 

create a new platform folder TARGET_ARM_FM
add general drivers files for FVP_MPS2
pull/6862/head
Qinghao Shi 2018-05-14 11:30:34 +01:00
parent 634774f45f
commit 2c88a8314a
24 changed files with 3646 additions and 0 deletions
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91
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PeripheralNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)CMSDK_UART0_BASE,
UART_1 = (int)CMSDK_UART1_BASE,
UART_2 = (int)CMSDK_UART3_BASE,
UART_3 = (int)CMSDK_UART4_BASE
} UARTName;
typedef enum {
I2C_0 = (int)MPS2_TSC_I2C_BASE,
I2C_1 = (int)MPS2_AAIC_I2C_BASE,
I2C_2 = (int)MPS2_SHIELD0_I2C_BASE,
I2C_3 = (int)MPS2_SHIELD1_I2C_BASE
} I2CName;
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2,
ADC0_3,
ADC0_4,
ADC0_5,
ADC0_6,
ADC0_7,
ADC0_8,
ADC0_9,
ADC0_10,
ADC0_11
} ADCName;
typedef enum {
SPI_0 = (int)MPS2_SSP1_BASE,
SPI_1 = (int)MPS2_SSP0_BASE,
SPI_2 = (int)MPS2_SSP2_BASE,
SPI_3 = (int)MPS2_SSP3_BASE,
SPI_4 = (int)MPS2_SSP4_BASE
} SPIName;
typedef enum {
PWM_1 = 0,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7,
PWM_8,
PWM_9,
PWM_10,
PWM_11
} PWMName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_0
#define MBED_UART0 USBTX, USBRX
#define MBED_UART1 XB_TX, XB_RX
#define MBED_UART2 SH0_TX, SH0_RX
#define MBED_UART3 SH1_TX, SH1_RX
#define MBED_UARTUSB USBTX, USBRX
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PinNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// MPS2 EXP Pin Names
EXP0 = 0,
EXP1 = 1,
EXP2 = 2,
EXP3 = 3,
EXP4 = 4,
EXP5 = 5,
EXP6 = 6,
EXP7 = 7,
EXP8 = 8,
EXP9 = 9,
EXP10 = 10,
EXP11 = 11,
EXP12 = 12,
EXP13 = 13,
EXP14 = 14,
EXP15 = 15,
EXP16 = 16,
EXP17 = 17,
EXP18 = 18,
EXP19 = 19,
EXP20 = 20,
EXP21 = 21,
EXP22 = 22,
EXP23 = 23,
EXP24 = 24,
EXP25 = 25,
EXP26 = 26,
EXP27 = 27,
EXP28 = 28,
EXP29 = 29,
EXP30 = 30,
EXP31 = 31,
EXP32 = 32,
EXP33 = 33,
EXP34 = 34,
EXP35 = 35,
EXP36 = 36,
EXP37 = 37,
EXP38 = 38,
EXP39 = 39,
EXP40 = 40,
EXP41 = 41,
EXP42 = 42,
EXP43 = 43,
EXP44 = 44,
EXP45 = 45,
EXP46 = 46,
EXP47 = 47,
EXP48 = 48,
EXP49 = 49,
EXP50 = 50,
EXP51 = 51,
// Other mbed Pin Names
//LEDs on mps2
//user leds
USERLED1 = 100,
USERLED2 = 101,
//user switches
USERSW1 = 110,
USERSW2 = 111,
//mcc leds
LED1 = 200,
LED2 = 201,
LED3 = 202,
LED4 = 203,
LED5 = 204,
LED6 = 205,
LED7 = 206,
LED8 = 207,
//MCC Switches
SW1 = 210,
SW2 = 211,
SW3 = 212,
SW4 = 213,
SW5 = 214,
SW6 = 215,
SW7 = 216,
SW8 = 217,
//MPS2 SPI header pins j21
MOSI_SPI = 300,
MISO_SPI = 301,
SCLK_SPI = 302,
SSEL_SPI = 303,
//MPS2 CLCD SPI
CLCD_MOSI = 304,
CLCD_MISO = 305,
CLCD_SCLK = 306,
CLCD_SSEL = 307,
CLCD_RESET = 308,
CLCD_RS = 309,
CLCD_RD = 310,
CLCD_BL_CTRL = 311,
//MPS2 shield 0 SPI
SHIELD_0_SPI_SCK = 320,
SHIELD_0_SPI_MOSI = 321,
SHIELD_0_SPI_MISO = 322,
SHIELD_0_SPI_nCS = 323,
//MPS2 shield 1 SPI
SHIELD_1_SPI_SCK = 331,
SHIELD_1_SPI_MOSI = 332,
SHIELD_1_SPI_MISO = 333,
SHIELD_1_SPI_nCS = 334,
//MPS2 shield ADC SPI
ADC_MOSI = 650,
ADC_MISO = 651,
ADC_SCLK = 652,
ADC_SSEL = 653,
//MPS2 Uart
USBTX = 400,
USBRX = 401,
XB_TX = 402,
XB_RX = 403,
UART_TX2 = 404,
UART_RX2 = 405,
SH0_TX = 406,
SH0_RX = 407,
SH1_TX = 408,
SH1_RX = 409,
//MPS2 I2C touchscreen and audio
TSC_SDA = 500,
TSC_SCL = 501,
AUD_SDA = 502,
AUD_SCL = 503,
//MPS2 I2C for shield
SHIELD_0_SDA = 504,
SHIELD_0_SCL = 505,
SHIELD_1_SDA = 506,
SHIELD_1_SCL = 507,
//MPS2 shield Analog pins
A0_0 = 600,
A0_1 = 601,
A0_2 = 602,
A0_3 = 603,
A0_4 = 604,
A0_5 = 605,
A1_0 = 606,
A1_1 = 607,
A1_2 = 608,
A1_3 = 609,
A1_4 = 610,
A1_5 = 611,
//MPS2 Shield Digital pins
D0_0 = EXP0,
D0_1 = EXP4,
D0_2 = EXP2,
D0_3 = EXP3,
D0_4 = EXP1,
D0_5 = EXP6,
D0_6 = EXP7,
D0_7 = EXP8,
D0_8 = EXP9,
D0_9 = EXP10,
D0_10 = EXP12,
D0_11 = EXP13,
D0_12 = EXP14,
D0_13 = EXP11,
D0_14 = EXP15,
D0_15 = EXP5,
D1_0 = EXP26,
D1_1 = EXP30,
D1_2 = EXP28,
D1_3 = EXP29,
D1_4 = EXP27,
D1_5 = EXP32,
D1_6 = EXP33,
D1_7 = EXP34,
D1_8 = EXP35,
D1_9 = EXP36,
D1_10 = EXP38,
D1_11 = EXP39,
D1_12 = EXP40,
D1_13 = EXP44,
D1_14 = EXP41,
D1_15 = EXP31,
// Not connected
NC = (int)0xFFFFFFFF,
} PinName;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PortNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
Port0 = 0,
Port1 = 1
} PortName;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c Normal file
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/* MPS2 Peripheral Library
*
* Copyright (c) 2006-2018 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Code implementation file for the LAN Ethernet interface.
*/
#include <stdio.h>
#include "mbed_wait_api.h"
#include "ETH_MPS2.h"
// SMSC9220 low-level operations
unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data)
{
unsigned int val, maccmd;
int timedout;
int error;
error = 0;
val = SMSC9220->MAC_CSR_CMD;
if(!(val & ((unsigned int)1 << 31))) { // Make sure there's no pending operation
maccmd = 0;
maccmd |= regoffset;
maccmd |= ((unsigned int)1 << 30); // Indicates read
maccmd |= ((unsigned int)1 << 31); // Start bit
SMSC9220->MAC_CSR_CMD = maccmd; // Start operation
timedout = 50;
do {
val = SMSC9220->BYTE_TEST; // A no-op read.
wait_ms(1);
timedout--;
} while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
if(!timedout) {
error = 1;
}
else
*data = SMSC9220->MAC_CSR_DATA;
} else {
*data = 0;
}
return error;
}
unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data)
{
unsigned int read, maccmd;
int timedout;
int error;
error = 0;
read = SMSC9220->MAC_CSR_CMD;
if(!(read & ((unsigned int)1 << 31))) { // Make sure there's no pending operation
SMSC9220->MAC_CSR_DATA = data; // Store data.
maccmd = 0;
maccmd |= regoffset;
maccmd &= ~((unsigned int)1 << 30); // Clear indicates write
maccmd |= ((unsigned int)1 << 31); // Indicate start of operation
SMSC9220->MAC_CSR_CMD = maccmd;
timedout = 50;
do {
read = SMSC9220->BYTE_TEST; // A no-op read.
wait_ms(1);
timedout--;
} while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
if(!timedout) {
error = 1;
}
} else {
printf("Warning: SMSC9220 MAC CSR is busy. No data written.\n");
}
return error;
}
unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data)
{
unsigned int val, phycmd; int error;
int timedout;
error = 0;
smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val);
if(!(val & 1)) { // Not busy
phycmd = 0;
phycmd |= (1 << 11); // 1 to [15:11]
phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6]
phycmd &= ~(1 << 1); // Clear [1] indicates read.
phycmd |= (1 << 0); // Set [0] indicates operation start
smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd);
val = 0;
timedout = 50;
do {
wait_ms(1);
timedout--;
smsc9220_mac_regread(SMSC9220_MAC_MII_ACC,&val);
} while(timedout && (val & ((unsigned int)1 << 0)));
if(!timedout) {
error = 1;
}
else
smsc9220_mac_regread(SMSC9220_MAC_MII_DATA, (unsigned int *)data);
} else {
*data = 0;
}
return error;
}
unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data)
{
unsigned int val, phycmd; int error;
int timedout;
error = 0;
smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val);
if(!(val & 1)) { // Not busy
smsc9220_mac_regwrite(SMSC9220_MAC_MII_DATA, (data & 0xFFFF)); // Load the data
phycmd = 0;
phycmd |= (1 << 11); // 1 to [15:11]
phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6]
phycmd |= (1 << 1); // Set [1] indicates write.
phycmd |= (1 << 0); // Set [0] indicates operation start
smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd); // Start operation
phycmd = 0;
timedout = 50;
do {
wait_ms(1);
timedout--;
smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd);
} while(timedout && (phycmd & (1 << 0)));
if(!timedout) {
error = 1;
}
} else {
printf("Warning: SMSC9220 MAC MII is busy. No data written.\n");
}
return error;
}
// Returns smsc9220 id.
unsigned int smsc9220_read_id(void)
{
return SMSC9220->ID_REV;
}
// Initiates a soft reset, returns failure or success.
unsigned int smsc9220_soft_reset(void)
{
int timedout;
timedout = 10;
// Soft reset
SMSC9220->HW_CFG |= 1;
do {
wait_ms(1);
timedout--;
} while(timedout && (SMSC9220->HW_CFG & 1));
if(!timedout)
return 1;
return 0;
}
void smsc9220_set_txfifo(unsigned int val)
{
// 2kb minimum, 14kb maximum
if(val < 2 || val > 14)
return;
SMSC9220->HW_CFG = val << 16;
}
unsigned int smsc9220_wait_eeprom(void)
{
int timedout;
timedout = 50;
do {
wait_ms(1);
timedout--;
} while(timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31)));
if(!timedout)
return 1;
return 0;
}
/* initialise irqs */
void smsc9220_init_irqs(void)
{
SMSC9220->INT_EN = 0x0;
SMSC9220->INT_STS = 0xFFFFFFFF; // clear all interrupts
SMSC9220->IRQ_CFG = 0x22000100; // irq deassertion at 220 usecs and master IRQ enable.
}
unsigned int smsc9220_check_phy(void)
{
unsigned short phyid1, phyid2;
smsc9220_phy_regread(SMSC9220_PHY_ID1,&phyid1);
smsc9220_phy_regread(SMSC9220_PHY_ID2,&phyid2);
return ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) ||
(phyid1 == 0x0 && phyid2 == 0x0));
}
unsigned int smsc9220_reset_phy(void)
{
unsigned short read;
int error;
error = 0;
if(smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) {
error = 1;
return error;
}
read |= (1 << 15);
if(smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) {
error = 1;
return error;
}
return 0;
}
/* Advertise all speeds and pause capabilities */
void smsc9220_advertise_cap(void)
{
unsigned short aneg_adv;
aneg_adv = 0;
smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv);
aneg_adv |= 0xDE0;
smsc9220_phy_regwrite(SMSC9220_PHY_ANEG_ADV, aneg_adv);
smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv);
return;
}
void smsc9220_establish_link(void)
{
unsigned short bcr;
smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr);
bcr |= (1 << 12) | (1 << 9);
smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, bcr);
smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr);
{
unsigned int hw_cfg;
hw_cfg = 0;
hw_cfg = SMSC9220->HW_CFG;
hw_cfg &= 0xF0000;
hw_cfg |= (1 << 20);
SMSC9220->HW_CFG = hw_cfg;
}
return;
}
void smsc9220_enable_xmit(void)
{
SMSC9220->TX_CFG = 0x2; // Enable trasmission
return;
}
void smsc9220_enable_mac_xmit(void)
{
unsigned int mac_cr;
mac_cr = 0;
smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr);
mac_cr |= (1 << 3); // xmit enable
mac_cr |= (1 << 28); // Heartbeat disable
smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr);
return;
}
void smsc9220_enable_mac_recv(void)
{
unsigned int mac_cr;
mac_cr = 0;
smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr);
mac_cr |= (1 << 2); // Recv enable
smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr);
return;
}
unsigned int smsc9220_check_ready(void)
{
return !(SMSC9220->PMT_CTRL & 1);
}
/* Generate a soft irq */
void smsc9220_set_soft_int(void)
{
SMSC9220->INT_EN |= 0x80000000;
}
/* clear soft irq */
void smsc9220_clear_soft_int(void)
{
SMSC9220->INT_STS |= 0x80000000;
}
unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index)
{
unsigned int rxfifo_inf; // Tells us the status of rx payload and status fifos.
unsigned int rxfifo_stat;
unsigned int pktsize;
unsigned int dwords_to_read;
rxfifo_inf = SMSC9220->RX_FIFO_INF;
if(rxfifo_inf & 0xFFFF) { // If there's data
rxfifo_stat = SMSC9220->RX_STAT_PORT;
if(rxfifo_stat != 0) { // Fetch status of this packet
pktsize = ((rxfifo_stat >> 16) & 0x3FFF);
if(rxfifo_stat & (1 << 15)) {
printf("Error occured during receiving of packets on the bus.\n");
return 1;
} else {
/* Below formula (recommended by SMSC9220 code)
* gives 1 more than required. This is perhaps because
* a last word is needed for not word aligned packets.
*/
dwords_to_read = (pktsize + 3) >> 2;
// PIO copy of data received:
while(dwords_to_read > 0) {
recvbuf[*index] = SMSC9220->RX_DATA_PORT;
(*index)++;
dwords_to_read--;
}
}
} else {
return 1;
}
} else {
return 1;
}
rxfifo_stat = SMSC9220->RX_STAT_PORT;
rxfifo_inf = SMSC9220->RX_FIFO_INF;
return 0;
}
// Does the actual transfer of data to FIFO, note it does no
// fifo availability checking. This should be done by caller.
// Assumes the whole frame is transferred at once as a single segment
void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length)
{
unsigned int txcmd_a, txcmd_b;
unsigned int dwords_to_write;
volatile unsigned int dwritten;
unsigned int *pktptr;
volatile unsigned int xmit_stat, xmit_stat2, xmit_inf;
int i;
pktptr = (unsigned int *) pkt;
txcmd_a = 0;
txcmd_b = 0;
txcmd_a |= (1 << 12) | (1 << 13); // First and last segments
txcmd_a |= length & 0x7FF; // [10:0] contains length
txcmd_b |= ((length & 0xFFFF) << 16); // [31:16] contains length
txcmd_b |= length & 0x7FF; // [10:0] also contains length
SMSC9220->TX_DATA_PORT = txcmd_a;
SMSC9220->TX_DATA_PORT = txcmd_b;
dwritten = dwords_to_write = (length + 3) >> 2;
// PIO Copy to FIFO. Could replace this with DMA.
while(dwords_to_write > 0) {
SMSC9220->TX_DATA_PORT = *pktptr;
pktptr++;
dwords_to_write--;
}
xmit_stat = SMSC9220->TX_STAT_PORT;
xmit_stat2 = SMSC9220->TX_STAT_PORT;
xmit_inf = SMSC9220->TX_FIFO_INF;
if(xmit_stat2 != 0 ) {
for(i = 0; i < 6; i++) {
xmit_stat2 = SMSC9220->TX_STAT_PORT;
}
}
}

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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.h Normal file
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/* MPS2 Peripheral Library
*
* Copyright (c) 2006-2018 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ETH_MPS2_H_
#define _ETH_MPS2_H_
#include "SMM_MPS2.h"
// Function declarations
unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data);
unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data);
unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data);
unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data);
unsigned int smsc9220_read_id(void);
unsigned int smsc9220_soft_reset(void);
void smsc9220_set_txfifo(unsigned int val);
unsigned int smsc9220_wait_eeprom(void);
void smsc9220_init_irqs(void);
unsigned int smsc9220_check_phy(void);
unsigned int smsc9220_reset_phy(void);
void smsc9220_advertise_cap(void);
void smsc9220_establish_link(void);
void smsc9220_enable_xmit(void);
void smsc9220_enable_mac_xmit(void);
void smsc9220_enable_mac_recv(void);
unsigned int smsc9220_check_ready(void);
void smsc9220_set_soft_int(void);
void smsc9220_clear_soft_int(void);
unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index);
void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length);
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* ----------------------------------------------------------------
* File: fpga.c
* Release: Version 1.0
* ----------------------------------------------------------------
*/
/*
* Code implementation file for the fpga functions.
*/
#include "SMM_MPS2.h" // MPS2 common header
// Function to delay n*ticks (25MHz = 40nS per tick)
// Used for I2C drivers
void i2c_delay(unsigned int tick)
{
unsigned int end;
unsigned int start;
start = MPS2_FPGAIO->COUNTER;
end = start + (tick);
if(end >= start)
{
while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
}
else
{
while (MPS2_FPGAIO->COUNTER >= start);
while (MPS2_FPGAIO->COUNTER < end);
}
}
/* Sleep function to delay n*mS
* Uses FPGA counter.
*/
void Sleepms(unsigned int msec)
{
unsigned int end;
unsigned int start;
start = MPS2_FPGAIO->COUNTER;
end = start + (25 * msec * 1000);
if(end >= start)
{
while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
}
else
{
while (MPS2_FPGAIO->COUNTER >= start);
while (MPS2_FPGAIO->COUNTER < end);
}
}
/* Sleep function to delay n*uS
*/
void Sleepus(unsigned int usec)
{
unsigned int end;
unsigned int start;
start = MPS2_FPGAIO->COUNTER;
end = start + (25 * usec);
if(end >= start)
{
while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
}
else
{
while (MPS2_FPGAIO->COUNTER >= start);
while (MPS2_FPGAIO->COUNTER < end);
}
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Code implementation file for the fpga functions.
*/
#include "SMM_MPS2.h" // MPS2 common header
// Function to delay n*ticks (25MHz = 40nS per tick)
// Used for I2C drivers
void i2c_delay(unsigned int tick);
/* Sleep function to delay n*mS
* Uses FPGA counter.
*/
void Sleepms(unsigned int msec);
/* Sleep function to delay n*uS
*/
void Sleepus(unsigned int usec);

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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <string.h>
#include "mps2_ethernet_api.h"
#include "cmsis.h"
#include "mbed_interface.h"
#include "mbed_toolchain.h"
#include "mbed_error.h"
#include "ETH_MPS2.h"
#include "mbed_wait_api.h"
#define TX_PKT_SIZE 256
#define RX_PKT_SIZE 300
// Types
#undef FALSE
#undef TRUE
#define FALSE 0
#define TRUE 1
int smsc9220_check_id(void)
{
int error;
unsigned int id;
error = 0;
id = smsc9220_read_id();
// If bottom and top halves of the word are the same
if(((id >> 16) & 0xFFFF) == (id & 0xFFFF)) {
error = 1;
return error;
}
switch(((id >> 16) & 0xFFFF)) {
case 0x9220:
break;
default:
error = 1;
break;
}
return error;
}
int smsc9220_check_macaddress(void)
{
int error;
const unsigned int mac_valid_high = 0xC00A;
const unsigned int mac_valid_low = 0x00F70200;
unsigned int mac_low;
unsigned int mac_high;
error = 0;
// Read current mac address.
smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high);
smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low);
// Writing temporary address:
smsc9220_mac_regwrite(SMSC9220_MAC_ADDRH, mac_valid_high);
smsc9220_mac_regwrite(SMSC9220_MAC_ADDRL, mac_valid_low);
// Verify write was correct:
smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high);
smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low);
if(mac_high != mac_valid_high || mac_low != mac_valid_low) {
error = TRUE;
return error;
}
return error;
}
void smsc9220_print_mac_registers()
{
unsigned int read;
int i;
i = 0;
read = 0;
for(i = 1; i <= 0xC; i++) {
smsc9220_mac_regread(i, &read);
}
return;
}
void smsc9220_print_phy_registers()
{
unsigned short read;
unsigned int i;
i = 0;
read = 0;
for(i = 0; i <= 6; i++) {
smsc9220_phy_regread(i, &read);
}
smsc9220_phy_regread(i = 17, &read);
smsc9220_phy_regread(i = 18, &read);
smsc9220_phy_regread(i = 27, &read);
smsc9220_phy_regread(i = 29, &read);
smsc9220_phy_regread(i = 30, &read);
smsc9220_phy_regread(i = 31, &read);
return;
}
/*----------------------------------------------------------------------------
Ethernet Device initialize
*----------------------------------------------------------------------------*/
int ethernet_transmission(unsigned char * pkt, unsigned int length)
{
smsc9220_xmit_packet(pkt, length);
return 0;
}
int ethernet_reception(unsigned int *recvbuf, unsigned int *index)
{
return smsc9220_recv_packet((unsigned int *)recvbuf, index);
}
int ethernet_mac_address(char *mac)
{
return smsc9220_check_macaddress();
}
unsigned int ethernet_check_ready(void)
{
return smsc9220_check_ready();
}
unsigned int ethernet_intf()
{
unsigned int txfifo_inf;
txfifo_inf = SMSC9220->TX_FIFO_INF;
return txfifo_inf;
}

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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MPS2_ETHERNET_API_H
#define MPS2_ETHERNET_API_H
#include "device.h"
#if DEVICE_ETHERNET
#ifdef __cplusplus
extern "C" {
#endif
// Connection constants
// send ethernet write buffer, returning the packet size sent
int ethernet_transmission(unsigned char * pkt, unsigned int length);
// recieve from ethernet buffer, returning packet size, or 0 if no packet
int ethernet_reception(unsigned int *recvbuf, unsigned int *index);
// get the ethernet address
int ethernet_mac_address(char *mac);
unsigned int ethernet_check_ready(void);
unsigned int ethernet_intf(void);
int smsc9220_check_id(void);
int smsc9220_check_macaddress(void);
void smsc9220_print_mac_registers(void);
void smsc9220_print_phy_registers(void);
#ifdef __cplusplus
}
#endif
#endif
#endif

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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/analogin_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogin_api.h"
#include "cmsis.h"
#include "pinmap.h"
#define ADC_12BIT_RANGE 0xFFF
static const PinMap PinMap_ADC[] = {
{A0_0, ADC0_0, 0},
{A0_1, ADC0_1, 0},
{A0_2, ADC0_2, 0},
{A0_3, ADC0_3, 0},
{A0_4, ADC0_4, 0},
{A0_5, ADC0_5, 0},
{A1_0, ADC0_6, 0},
{A1_1, ADC0_7, 0},
{A1_2, ADC0_8, 0},
{A1_3, ADC0_9, 0},
{A1_4, ADC0_10, 0},
{A1_5, ADC0_11, 0},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_SCLK[] = {
{ADC_SCLK , SPI_3, 0},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MOSI[] = {
{ADC_MOSI, SPI_3, 0},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MISO[] = {
{ADC_MISO, SPI_3, 0},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_SSEL[] = {
{ADC_SSEL, SPI_3, 0},
{NC , NC , 0}
};
#define ADC_RANGE ADC_12BIT_RANGE
int analog_spi_inited = 0;
void analogin_init(analogin_t *obj, PinName pin) {
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
obj->pin = pin;
obj->pin_number = pin-600;
obj->address = (0x0000 | (pin-600));
SPIName adc_mosi = (SPIName)pinmap_peripheral(ADC_MOSI, PinMap_SPI_MOSI);
SPIName adc_miso = (SPIName)pinmap_peripheral(ADC_MISO, PinMap_SPI_MISO);
SPIName adc_sclk = (SPIName)pinmap_peripheral(ADC_SCLK, PinMap_SPI_SCLK);
SPIName adc_ssel = (SPIName)pinmap_peripheral(ADC_SSEL, PinMap_SPI_SSEL);
SPIName adc_data = (SPIName)pinmap_merge(adc_mosi, adc_miso);
SPIName adc_cntl = (SPIName)pinmap_merge(adc_sclk, adc_ssel);
obj->adc_spi = (MPS2_SSP_TypeDef*)pinmap_merge(adc_data, adc_cntl);
if(analog_spi_inited == 0){
obj->adc_spi->CR1 = 0;
obj->adc_spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_16;
obj->adc_spi->CPSR = SSP_CPSR_DFLT;
obj->adc_spi->IMSC = 0x8;
obj->adc_spi->DMACR = 0;
obj->adc_spi->CR1 = SSP_CR1_SSE_Msk;
obj->adc_spi->ICR = 0x3;
analog_spi_inited = 1;
}
pinmap_pinout(ADC_MOSI, PinMap_SPI_MOSI);
pinmap_pinout(ADC_MISO, PinMap_SPI_MISO);
pinmap_pinout(ADC_SCLK, PinMap_SPI_SCLK);
pinmap_pinout(ADC_SSEL, PinMap_SPI_SSEL);
pinmap_pinout(pin, PinMap_ADC);
}
static inline uint32_t adc_read(analogin_t *obj) {
return 0;
}
float analogin_read(analogin_t *obj) {
uint32_t value = adc_read(obj);
return 0;
}
uint16_t analogin_read_u16(analogin_t *obj) {
return 0;
}

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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/ethernet_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <string.h>
#include "ethernet_api.h"
#include "mps2_ethernet_api.h"
#include "cmsis.h"
#include "mbed_interface.h"
#include "mbed_toolchain.h"
#include "mbed_error.h"
#include "ETH_MPS2.h"
#include "mbed_wait_api.h"
#define TX_PKT_SIZE 256
#define RX_PKT_SIZE 300
// Types
#undef FALSE
#undef TRUE
#define FALSE 0
#define TRUE 1
/*----------------------------------------------------------------------------
Ethernet Device initialize
*----------------------------------------------------------------------------*/
int ethernet_init()
{
int error;
error = 0;
if(smsc9220_check_id()) {
error = TRUE;
}
if(smsc9220_soft_reset()) {
error = TRUE;
}
smsc9220_set_txfifo(5);
// Sets automatic flow control thresholds, and backpressure
// threshold to defaults specified.
SMSC9220->AFC_CFG = 0x006E3740;
if(smsc9220_wait_eeprom()) {
error = TRUE;
}
// Configure GPIOs as LED outputs.
SMSC9220->GPIO_CFG = 0x70070000;
smsc9220_init_irqs();
/* Configure MAC addresses here if needed. */
if(smsc9220_check_phy()) {
error = TRUE;
}
if(smsc9220_reset_phy()) {
error = TRUE;
return error;
}
wait_ms(100);
// Checking whether phy reset completed successfully.
{
unsigned short phyreset;
phyreset = 0;
smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &phyreset);
if(phyreset & (1 << 15)) {
error = TRUE;
return error;
}
}
/* Advertise capabilities */
smsc9220_advertise_cap();
/* Begin to establish link */
smsc9220_establish_link(); // bit [12] of BCONTROL seems self-clearing.
// Although it's not so in the manual.
/* Interrupt threshold */
SMSC9220->FIFO_INT = 0xFF000000;
smsc9220_enable_mac_xmit();
smsc9220_enable_xmit();
SMSC9220->RX_CFG = 0;
smsc9220_enable_mac_recv();
// Rx status FIFO level irq threshold
SMSC9220->FIFO_INT &= ~(0xFF); // Clear 2 bottom nibbles
// This sleep is compulsory otherwise txmit/receive will fail.
wait_ms(2000);
return error;
}
/*----------------------------------------------------------------------------
Ethernet Device Uninitialize
*----------------------------------------------------------------------------*/
void ethernet_free() {
}
int ethernet_write(const char *data, int size)
{
return 0;
}
int ethernet_send()
{
return 0;
}
int ethernet_receive()
{
return 0;
}
// Read from an recevied ethernet packet.
// After receive returnd a number bigger than 0 it is
// possible to read bytes from this packet.
// Read will write up to size bytes into data.
// It is possible to use read multible times.
// Each time read will start reading after the last read byte before.
int ethernet_read(char *data, int dlen)
{
return 0;
}
void ethernet_address(char *mac) {
mbed_mac_address(mac);
}
int ethernet_link(void)
{
return 0;
}
void ethernet_set_link(int speed, int duplex)
{
smsc9220_establish_link();
}

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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_api.h"
#include "pinmap.h"
// function to enable the GPIO pin
uint32_t gpio_set(PinName pin) {
return (1);
}
//function to initialise the gpio pin
// this links the board control bits for each pin
// with the object created for the pin
void gpio_init(gpio_t *obj, PinName pin) {
if(pin == NC){ return;}
else {
int pin_value = 0;
obj->pin = pin;
if(pin <=15){
pin_value = pin;
}else if (pin >= 16 && pin <= 31){
pin_value = pin-16;
}else if (pin >= 32 && pin <= 47){
pin_value = pin-32;
}else if (pin >= 48 && pin <= 51){
pin_value = pin-48;
}else if (pin == 100 || pin == 101){
pin_value = pin-100;
}else if (pin == 110 || pin == 111){
pin_value = pin-110;
}else if (pin >= 200 && pin <= 207){
pin_value = pin-200;
}else if (pin >= 210 && pin <= 217){
pin_value = pin-210;
}else if (pin == 303){
pin_value = pin-302;
}else if (pin == 307){
pin_value = pin-307;
}else if (pin == 308){
pin_value = pin-305;
}else if (pin == 309){
pin_value = pin-305;
}else if (pin == 310){
pin_value = pin-305;
}else if (pin == 311){
pin_value = pin-305;
}else if (pin == 323){
pin_value = pin-315;
}else if (pin == 334){
pin_value = pin-325;
}else if (pin == 653){
pin_value = pin-646;
}
obj->mask = 0x1 << pin_value;
obj->pin_number = pin;
if(pin <=15) {
obj->reg_data = &CMSDK_GPIO0->DATAOUT ;
obj->reg_in = &CMSDK_GPIO0->DATA ;
obj->reg_dir = &CMSDK_GPIO0->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO0->OUTENABLECLR ;
} else if (pin >= 16 && pin <= 31){
obj->reg_data = &CMSDK_GPIO1->DATAOUT ;
obj->reg_in = &CMSDK_GPIO1->DATA ;
obj->reg_dir = &CMSDK_GPIO1->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO1->OUTENABLECLR ;
} else if (pin >= 32 && pin <= 47){
obj->reg_data = &CMSDK_GPIO2->DATAOUT;
obj->reg_in = &CMSDK_GPIO2->DATA;
obj->reg_dir = &CMSDK_GPIO2->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO2->OUTENABLECLR ;
} else if (pin >= 48 && pin <= 51){
obj->reg_data = &CMSDK_GPIO3->DATAOUT;
obj->reg_in = &CMSDK_GPIO3->DATA;
obj->reg_dir = &CMSDK_GPIO3->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO3->OUTENABLECLR ;
} else if (pin == 100 || pin == 101){
obj->reg_data = &MPS2_FPGAIO->LED; //user leds
obj->reg_in = &MPS2_FPGAIO->LED;
} else if (pin == 110 || pin == 111){
obj->reg_data = &MPS2_FPGAIO->BUTTON; //user switches
obj->reg_in = &MPS2_FPGAIO->BUTTON; //user switches
}else if (pin >= 200 && pin <= 207){
obj->reg_data = &MPS2_SCC->LEDS; //mcc leds
obj->reg_in = &MPS2_SCC->LEDS; //mcc leds
}else if (pin >= 210 && pin <= 217){
obj->reg_in = &MPS2_SCC->SWITCHES; //mcc switches
}else if (pin == 303 || pin == 307){
obj->reg_data = &MPS2_FPGAIO->MISC; //spi chip select = 303, clcd chip select = 307
}else if (pin == 308 || pin == 309 || pin == 310 || pin == 311){
obj->reg_data = &MPS2_FPGAIO->MISC; //clcd control bits
}else if (pin == 323 || pin == 334 || pin == 653){ //spi 3 chip select = 323, spi 4 chip select = 334, adc chip select = 653
obj->reg_data = &MPS2_FPGAIO->MISC; //spi cs bits
}
if (pin == 323){
CMSDK_GPIO0->ALTFUNCSET |= 0x1000;
}else if (pin == 334){
CMSDK_GPIO2->ALTFUNCSET |= 0x0040;
}else if (pin == 653){
CMSDK_GPIO1->ALTFUNCSET |= 0x0001;
}
}
}
void gpio_mode(gpio_t *obj, PinMode mode) {
pin_mode(obj->pin, mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction) {
if(obj->pin >= 0 && obj->pin <= 51)
{
switch (direction) {
case PIN_INPUT : *obj->reg_dirclr = obj->mask; break;
case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
}
} else {return;}
}
int gpio_is_connected(const gpio_t *obj){
if(obj->pin != (PinName)NC){
return 1;
} else {
return 0;
}
}

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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_irq_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "cmsis.h"
#include "gpio_irq_api.h"
#include "mbed_error.h"
#define CHANNEL_NUM 32
#define CMSDK_GPIO_0 CMSDK_GPIO0
#define CMSDK_GPIO_1 CMSDK_GPIO1
#define PININT_IRQ 0
static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler irq_handler;
static inline void handle_interrupt_in(uint32_t channel) {
uint32_t ch_bit = (1 << channel);
// Return immediately if:
// * The interrupt was already served
// * There is no user handler
// * It is a level interrupt, not an edge interrupt
if (ch_bit <16){
if ( ((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0) ) return;
if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE);
CMSDK_GPIO_0->INTPOLSET = ch_bit;
}
if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_FALL);
}
CMSDK_GPIO_0->INTCLEAR = ch_bit;
}
if (ch_bit>=16) {
if ( ((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0) ) return;
if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE);
CMSDK_GPIO_1->INTPOLSET = ch_bit;
}
if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_FALL);
}
CMSDK_GPIO_1->INTCLEAR = ch_bit;
}
}
void gpio0_irq0(void) {handle_interrupt_in(0);}
void gpio0_irq1(void) {handle_interrupt_in(1);}
void gpio0_irq2(void) {handle_interrupt_in(2);}
void gpio0_irq3(void) {handle_interrupt_in(3);}
void gpio0_irq4(void) {handle_interrupt_in(4);}
void gpio0_irq5(void) {handle_interrupt_in(5);}
void gpio0_irq6(void) {handle_interrupt_in(6);}
void gpio0_irq7(void) {handle_interrupt_in(7);}
void gpio0_irq8(void) {handle_interrupt_in(8);}
void gpio0_irq9(void) {handle_interrupt_in(9);}
void gpio0_irq10(void) {handle_interrupt_in(10);}
void gpio0_irq11(void) {handle_interrupt_in(11);}
void gpio0_irq12(void) {handle_interrupt_in(12);}
void gpio0_irq13(void) {handle_interrupt_in(13);}
void gpio0_irq14(void) {handle_interrupt_in(14);}
void gpio0_irq15(void) {handle_interrupt_in(15);}
void gpio1_irq0(void) {handle_interrupt_in(16);}
void gpio1_irq1(void) {handle_interrupt_in(17);}
void gpio1_irq2(void) {handle_interrupt_in(18);}
void gpio1_irq3(void) {handle_interrupt_in(19);}
void gpio1_irq4(void) {handle_interrupt_in(20);}
void gpio1_irq5(void) {handle_interrupt_in(21);}
void gpio1_irq6(void) {handle_interrupt_in(22);}
void gpio1_irq7(void) {handle_interrupt_in(23);}
void gpio1_irq8(void) {handle_interrupt_in(24);}
void gpio1_irq9(void) {handle_interrupt_in(25);}
void gpio1_irq10(void) {handle_interrupt_in(26);}
void gpio1_irq11(void) {handle_interrupt_in(27);}
void gpio1_irq12(void) {handle_interrupt_in(28);}
void gpio1_irq13(void) {handle_interrupt_in(29);}
void gpio1_irq14(void) {handle_interrupt_in(30);}
void gpio1_irq15(void) {handle_interrupt_in(31);}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
if (pin == NC) {return -1;}
else {
irq_handler = handler;
int found_free_channel = 0;
int i = 0;
for (i=0; i<CHANNEL_NUM; i++) {
if (channel_ids[i] == 0) {
channel_ids[i] = id;
obj->ch = i;
found_free_channel = 1;
break;
}
}
if (!found_free_channel) return -1;
/* To select a pin for any of the eight pin interrupts, write the pin number
* as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
* @see: mbed_capi/PinNames.h
*/
if (pin <16)
{
CMSDK_GPIO_0->INTENSET |= (0x1 << pin);
}
if (pin >= 16)
{
CMSDK_GPIO_1->INTENSET |= (0x1 << pin);
}
void (*channels_irq)(void) = NULL;
switch (obj->ch) {
case 0: channels_irq = &gpio0_irq0; break;
case 1: channels_irq = &gpio0_irq1; break;
case 2: channels_irq = &gpio0_irq2; break;
case 3: channels_irq = &gpio0_irq3; break;
case 4: channels_irq = &gpio0_irq4; break;
case 5: channels_irq = &gpio0_irq5; break;
case 6: channels_irq = &gpio0_irq6; break;
case 7: channels_irq = &gpio0_irq7; break;
case 8: channels_irq = &gpio0_irq8; break;
case 9: channels_irq = &gpio0_irq9; break;
case 10: channels_irq = &gpio0_irq10; break;
case 11: channels_irq = &gpio0_irq11; break;
case 12: channels_irq = &gpio0_irq12; break;
case 13: channels_irq = &gpio0_irq13; break;
case 14: channels_irq = &gpio0_irq14; break;
case 15: channels_irq = &gpio0_irq15; break;
case 16: channels_irq = &gpio1_irq0; break;
case 17: channels_irq = &gpio1_irq1; break;
case 18: channels_irq = &gpio1_irq2; break;
case 19: channels_irq = &gpio1_irq3; break;
case 20: channels_irq = &gpio1_irq4; break;
case 21: channels_irq = &gpio1_irq5; break;
case 22: channels_irq = &gpio1_irq6; break;
case 23: channels_irq = &gpio1_irq7; break;
case 24: channels_irq = &gpio1_irq8; break;
case 25: channels_irq = &gpio1_irq9; break;
case 26: channels_irq = &gpio1_irq10; break;
case 27: channels_irq = &gpio1_irq11; break;
case 28: channels_irq = &gpio1_irq12; break;
case 29: channels_irq = &gpio1_irq13; break;
case 30: channels_irq = &gpio1_irq14; break;
case 31: channels_irq = &gpio1_irq15; break;
}
NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
return 0;
}
}
void gpio_irq_free(gpio_irq_t *obj) {
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
unsigned int ch_bit = (1 << obj->ch);
// Clear interrupt
if (obj->ch <16)
{
if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit))
{
CMSDK_GPIO_0->INTCLEAR = ch_bit;
}
}
if (obj->ch >= 16)
{
if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit))
{
CMSDK_GPIO_1->INTCLEAR = ch_bit;
}
}
// Edge trigger
if (obj->ch <16)
{
CMSDK_GPIO_0->INTTYPESET &= ch_bit;
if (event == IRQ_RISE) {
CMSDK_GPIO_0->INTPOLSET |= ch_bit;
if (enable) {
CMSDK_GPIO_0->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_0->INTENCLR |= ch_bit;
}
} else {
CMSDK_GPIO_0->INTPOLCLR |= ch_bit;
if (enable) {
CMSDK_GPIO_0->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_0->INTENCLR |= ch_bit;
}
}
}
if (obj->ch >= 16)
{
CMSDK_GPIO_1->INTTYPESET &= ch_bit;
if (event == IRQ_RISE) {
CMSDK_GPIO_1->INTPOLSET |= ch_bit;
if (enable) {
CMSDK_GPIO_1->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_1->INTENCLR |= ch_bit;
}
} else {
CMSDK_GPIO_1->INTPOLCLR |= ch_bit;
if (enable) {
CMSDK_GPIO_1->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_1->INTENCLR |= ch_bit;
}
}
}
}
void gpio_irq_enable(gpio_irq_t *obj) {
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
}
void gpio_irq_disable(gpio_irq_t *obj) {
NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
}

55
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_object.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
PinName pin;
uint32_t mask;
uint32_t pin_number;
__IO uint32_t *reg_dir;
__IO uint32_t *reg_dirclr;
__IO uint32_t *reg_data;
__I uint32_t *reg_in;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value) {
if (value){
*obj->reg_data |= (obj->mask);
} else {
*obj->reg_data &= ~(obj->mask);
}
}
static inline int gpio_read(gpio_t *obj) {
return ((*obj->reg_in & obj->mask) ? 1 : 0);
}
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/i2c_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "i2c_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "SMM_MPS2.h"
#include "mbed_wait_api.h"
#include "fpga.h"
// Types
#undef FALSE
#undef TRUE
#define FALSE 0
#define TRUE 1
// TSC I2C controller
#define TSC_I2C_ADDR 0x82
// AACI I2C controller I2C address
#define AAIC_I2C_ADDR 0x96
#define TSC_I2C_CID 0x0811
// TSC I2C controller registers
#define TSC_I2C_CRID 0x00
// TSSPCPSR Clock prescale register
#define TSSPCPSR_DFLT 0x0002 // Clock prescale (use with SCR)
// TSC defaults
#define TSC_XOFF 20 // X offset
#define TSC_YOFF 20 // Y offset
#define TSC_MAXVAL 37000 // 0x0FFF * 10 with TSC to LCD scaling
#define TSC_TSU 15 // Setup delay 600nS min
#define AAIC_TSU 25 // Setup delay 1000nS min
#define SHIELD_TSU 25 // Setup delay 1000nS min
static const PinMap PinMap_I2C_SDA[] = {
{TSC_SDA, I2C_0, 0},
{AUD_SDA, I2C_1, 0},
{SHIELD_0_SDA, I2C_2, 0},
{SHIELD_1_SDA, I2C_3, 0},
{NC , NC , 0}
};
static const PinMap PinMap_I2C_SCL[] = {
{TSC_SCL, I2C_0, 0},
{AUD_SCL, I2C_1, 0},
{SHIELD_0_SCL, I2C_2, 0},
{SHIELD_1_SCL, I2C_3, 0},
{NC , NC, 0}
};
static inline void i2c_send_byte(i2c_t *obj, unsigned char c)
{
int loop;
switch ((int)obj->i2c) {
case I2C_0:
obj->i2c->CONTROLC = SCL;
i2c_delay(TSC_TSU);
for (loop = 0; loop < 8; loop++)
{
if (c & (1 << (7 - loop)))
obj->i2c->CONTROLS = SDA;
else
obj->i2c->CONTROLC = SDA;
i2c_delay(TSC_TSU);
obj->i2c->CONTROLS = SCL;
i2c_delay(TSC_TSU);
obj->i2c->CONTROLC = SCL;
i2c_delay(TSC_TSU);
}
obj->i2c->CONTROLS = SDA;
i2c_delay(TSC_TSU);
break;
case I2C_1:
for (loop = 0; loop < 8; loop++) {
i2c_delay(AAIC_TSU);
obj->i2c->CONTROLC = SCL;
i2c_delay(AAIC_TSU);
if (c & (1 << (7 - loop)))
obj->i2c->CONTROLS = SDA;
else
obj->i2c->CONTROLC = SDA;
i2c_delay(AAIC_TSU);
obj->i2c->CONTROLS = SCL;
i2c_delay(AAIC_TSU);
obj->i2c->CONTROLC = SCL;
}
i2c_delay(AAIC_TSU);
obj->i2c->CONTROLS = SDA;
i2c_delay(AAIC_TSU);
break;
case I2C_2:
case I2C_3:
obj->i2c->CONTROLC = SCL;
i2c_delay(SHIELD_TSU);
for (loop = 0; loop < 8; loop++)
{
if (c & (1 << (7 - loop)))
obj->i2c->CONTROLS = SDA;
else
obj->i2c->CONTROLC = SDA;
i2c_delay(SHIELD_TSU);
obj->i2c->CONTROLS = SCL;
i2c_delay(SHIELD_TSU);
obj->i2c->CONTROLC = SCL;
i2c_delay(SHIELD_TSU);
}
obj->i2c->CONTROLS = SDA;
i2c_delay(SHIELD_TSU);
break;
}
}
static inline unsigned char i2c_receive_byte(i2c_t *obj)
{
int data_receive_byte, loop;
switch ((int)obj->i2c) {
case I2C_0:
obj->i2c->CONTROLS = SDA;
i2c_delay(TSC_TSU);
data_receive_byte = 0;
for (loop = 0; loop < 8; loop++)
{
obj->i2c->CONTROLS = SCL;
i2c_delay(TSC_TSU);
if ((obj->i2c->CONTROL & SDA))
data_receive_byte += (1 << (7 - loop));
obj->i2c->CONTROLC = SCL;
i2c_delay(TSC_TSU);
}
obj->i2c->CONTROLC = SDA;
i2c_delay(TSC_TSU);
break;
case I2C_1:
obj->i2c->CONTROLS = SDA;
data_receive_byte = 0;
for (loop = 0; loop < 8; loop++) {
i2c_delay(AAIC_TSU);
obj->i2c->CONTROLC = SCL;
i2c_delay(AAIC_TSU);
obj->i2c->CONTROLS = SCL | SDA;
i2c_delay(AAIC_TSU);
if ((obj->i2c->CONTROL & SDA))
data_receive_byte += (1 << (7 - loop));
i2c_delay(AAIC_TSU);
obj->i2c->CONTROLC = SCL;
}
i2c_delay(AAIC_TSU);
obj->i2c->CONTROLC = SDA;
i2c_delay(AAIC_TSU);
break;
case I2C_2:
case I2C_3:
obj->i2c->CONTROLS = SDA;
i2c_delay(SHIELD_TSU);
data_receive_byte = 0;
for (loop = 0; loop < 8; loop++)
{
obj->i2c->CONTROLS = SCL;
i2c_delay(SHIELD_TSU);
if ((obj->i2c->CONTROL & SDA))
data_receive_byte += (1 << (7 - loop));
obj->i2c->CONTROLC = SCL;
i2c_delay(SHIELD_TSU);
}
obj->i2c->CONTROLC = SDA;
i2c_delay(SHIELD_TSU);
break;
}
return data_receive_byte;
}
static inline int i2c_receive_ack(i2c_t *obj)
{
int nack;
int delay_value;
switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break;
case I2C_1: delay_value = AAIC_TSU; break;
case I2C_2: delay_value = SHIELD_TSU; break;
case I2C_3: delay_value = SHIELD_TSU; break;
}
i2c_delay(delay_value);
obj->i2c->CONTROLS = SDA;
i2c_delay(delay_value);
obj->i2c->CONTROLC = SCL;
i2c_delay(delay_value);
obj->i2c->CONTROLS = SCL;
i2c_delay(delay_value);
nack = obj->i2c->CONTROL & SDA;
i2c_delay(delay_value);
obj->i2c->CONTROLC = SCL;
i2c_delay(delay_value);
obj->i2c->CONTROLS = SDA;
i2c_delay(delay_value);
if(nack==0)
return 1;
return 0;
}
static inline void i2c_send_nack(i2c_t *obj)
{
int delay_value;
switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break;
case I2C_1: delay_value = AAIC_TSU; break;
case I2C_2: delay_value = SHIELD_TSU; break;
case I2C_3: delay_value = SHIELD_TSU; break;
}
i2c_delay(delay_value);
obj->i2c->CONTROLC = SCL;
i2c_delay(delay_value);
obj->i2c->CONTROLS = SDA;
i2c_delay(delay_value);
obj->i2c->CONTROLS = SCL;
i2c_delay(delay_value);
obj->i2c->CONTROLC = SCL;
i2c_delay(delay_value);
obj->i2c->CONTROLC = SDA;
i2c_delay(delay_value);
}
static inline void i2c_send_ack(i2c_t *obj)
{
int delay_value;
switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break;
case I2C_1: delay_value = AAIC_TSU; break;
case I2C_2: delay_value = SHIELD_TSU; break;
case I2C_3: delay_value = SHIELD_TSU; break;
}
i2c_delay(delay_value);
obj->i2c->CONTROLC = SDA;
i2c_delay(delay_value);
obj->i2c->CONTROLS = SCL;
i2c_delay(delay_value);
obj->i2c->CONTROLC = SCL;
i2c_delay(delay_value);
}
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{
// determine the SPI to use
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
obj->i2c = (MPS2_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
if ((int)obj->i2c == NC) {
error("I2C pin mapping failed");
}
pinmap_pinout(sda, PinMap_I2C_SDA);
pinmap_pinout(scl, PinMap_I2C_SCL);
switch ((int)obj->i2c) {
case I2C_2: CMSDK_GPIO0->ALTFUNCSET |= 0x8020; break;
case I2C_3: CMSDK_GPIO1->ALTFUNCSET |= 0x8000;
CMSDK_GPIO2->ALTFUNCSET |= 0x0200; break;
}
}
int i2c_start(i2c_t *obj)
{
int delay_value;
switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break;
case I2C_1: delay_value = AAIC_TSU; break;
case I2C_2: delay_value = SHIELD_TSU; break;
case I2C_3: delay_value = SHIELD_TSU; break;
}
i2c_delay(delay_value);
obj->i2c->CONTROLS = SDA | SCL;
i2c_delay(delay_value);
obj->i2c->CONTROLC = SDA;
i2c_delay(delay_value);
return 0;
}
int i2c_start_tsc(i2c_t *obj)
{
int delay_value;
switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break;
case I2C_1: delay_value = AAIC_TSU; break;
case I2C_2: delay_value = SHIELD_TSU; break;
case I2C_3: delay_value = SHIELD_TSU; break;
}
i2c_delay(delay_value);
obj->i2c->CONTROLC = SDA;
i2c_delay(delay_value);
obj->i2c->CONTROLC = SCL;
i2c_delay(delay_value);
return 0;
}
int i2c_stop(i2c_t *obj)
{
int delay_value;
switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break;
case I2C_1: delay_value = AAIC_TSU; break;
case I2C_2: delay_value = SHIELD_TSU; break;
case I2C_3: delay_value = SHIELD_TSU; break;
}
// Actual stop bit
i2c_delay(delay_value);
obj->i2c->CONTROLC = SDA;
i2c_delay(delay_value);
obj->i2c->CONTROLS = SCL;
i2c_delay(delay_value);
obj->i2c->CONTROLS = SDA;
i2c_delay(delay_value);
return 0;
}
void i2c_frequency(i2c_t *obj, int hz) {
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{
unsigned int loop, rxdata;
int sadr, ack, bytes_read;
rxdata=0;
switch ((int)obj->i2c) {
case I2C_0:
sadr = TSC_I2C_ADDR;
break;
case I2C_1:
sadr = AAIC_I2C_ADDR;
break;
case I2C_2:
case I2C_3:
sadr = address; //LM75_I2C_ADDR; or MMA7660_I2C_ADDR;
break;
}
bytes_read = 0;
// Start bit
i2c_start(obj);
switch ((int)obj->i2c) {
case I2C_0:
// Set serial and register address
i2c_send_byte(obj,sadr);
ack += i2c_receive_ack(obj);
i2c_send_byte(obj, address);
ack += i2c_receive_ack(obj);
// Stop bit
i2c_stop(obj);
// Start bit
i2c_start_tsc(obj);
// Read from I2C address
i2c_send_byte(obj,sadr | 1);
ack += i2c_receive_ack(obj);
rxdata = (i2c_receive_byte(obj) & 0xFF);
data[((length-1)-bytes_read)] = (char)rxdata;
bytes_read++;
// Read multiple bytes
if ((length > 1) && (length < 5))
{
for (loop = 1; loop <= (length - 1); loop++)
{
// Send ACK
i2c_send_ack(obj);
// Next byte
//rxdata = ((rxdata << 8) & 0xFFFFFF00);
//rxdata |= (i2c_receive_byte(obj) & 0xFF);
rxdata = i2c_receive_byte(obj);
data[(length-1)-bytes_read] = (char)rxdata;
bytes_read++;
}
}
break;
case I2C_1:
// Set serial and register address
i2c_send_byte(obj,sadr);
ack += i2c_receive_ack(obj);
i2c_send_byte(obj, address);
ack += i2c_receive_ack(obj);
// Stop bit
i2c_stop(obj);
// Start bit
i2c_start_tsc(obj);
// Fall through to read data
case I2C_2:
case I2C_3:
// Read from preset register address pointer
i2c_send_byte(obj,sadr | 1);
ack += i2c_receive_ack(obj);
rxdata = i2c_receive_byte(obj);
data[bytes_read] = (char)rxdata;
bytes_read++;
// Read multiple bytes
if ((length > 1) && (length < 5))
{
for (loop = 1; loop <= (length - 1); loop++)
{
// Send ACK
i2c_send_ack(obj);
// Next byte
rxdata = i2c_receive_byte(obj);
data[loop] = (char)rxdata;
bytes_read++;
}
}
break;
}
i2c_send_nack(obj);
i2c_stop(obj); // Actual stop bit
return bytes_read;
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
{
int ack=0;
int sadr;
char * ptr;
char addr;
ptr = (char*)data;
switch ((int)obj->i2c)
{
case I2C_0:
sadr = TSC_I2C_ADDR;
addr = address;
break;
case I2C_1:
sadr = AAIC_I2C_ADDR;
addr = address;
break;
case I2C_2:
case I2C_3:
sadr = address; //LM75_I2C_ADDR or MMA7660_I2C_ADDR;
addr = *ptr++;
break;
}
// printf("adr = %x, reg = %x\n",sadr, address);
i2c_start(obj);
// Set serial and register address
i2c_send_byte(obj,sadr);
ack += i2c_receive_ack(obj);
i2c_send_byte(obj, addr);
ack += i2c_receive_ack(obj);
for(int i = 1; i<length; i++)
{
i2c_send_byte(obj, *ptr++);
ack += i2c_receive_ack(obj);
}
i2c_stop(obj);
if(ack==3) { return 1; }
else{ return 0; }
}
void i2c_reset(i2c_t *obj) {
i2c_stop(obj);
}
int i2c_byte_read(i2c_t *obj, int last) {
return 0;
}
int i2c_byte_write(i2c_t *obj, int data) {
return 0;
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
struct gpio_irq_s {
uint32_t ch;
};
struct port_s {
__IO uint32_t *reg_dir;
__IO uint32_t *reg_dirclr;
__IO uint32_t *reg_out;
__IO uint32_t *reg_in;
PortName port;
uint32_t mask;
};
struct serial_s {
CMSDK_UART_TypeDef *uart;
int index;
};
struct i2c_s {
MPS2_I2C_TypeDef *i2c;
};
struct tsc_s {
MPS2_I2C_TypeDef *tsc;
};
struct audio_s {
MPS2_I2S_TypeDef *audio_I2S;
MPS2_I2C_TypeDef *audio_I2C;
};
struct spi_s {
MPS2_SSP_TypeDef *spi;
};
struct clcd_s {
MPS2_SSP_TypeDef *clcd;
};
struct analogin_s {
ADCName adc;
MPS2_SSP_TypeDef *adc_spi;
PinName pin;
uint32_t pin_number;
__IO uint32_t address;
};
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "pinmap.h"
#include "mbed_error.h"
void pin_function(PinName pin, int function) {
MBED_ASSERT(pin != (PinName)NC);
}
void pin_mode(PinName pin, PinMode mode) {
MBED_ASSERT(pin != (PinName)NC);
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "port_api.h"
#include "pinmap.h"
#include "gpio_api.h"
PinName port_pin(PortName port, int pin_n) {
return (PinName)((port << PORT_SHIFT) | pin_n);
}
void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
obj->port = port;
obj->mask = mask;
CMSDK_GPIO_TypeDef *port_reg = (CMSDK_GPIO_TypeDef *)(CMSDK_GPIO0_BASE + ((int)port * 0x10));
obj->reg_in = &port_reg->DATAOUT;
obj->reg_dir = &port_reg->OUTENABLESET;
obj->reg_dirclr = &port_reg->OUTENABLECLR;
uint32_t i;
// The function is set per pin: reuse gpio logic
for (i=0; i<16; i++) {
if (obj->mask & (1<<i)) {
gpio_set(port_pin(obj->port, i));
}
}
port_dir(obj, dir);
}
void port_mode(port_t *obj, PinMode mode) {
uint32_t i;
// The mode is set per pin: reuse pinmap logic
for (i=0; i<32; i++) {
if (obj->mask & (1<<i)) {
pin_mode(port_pin(obj->port, i), mode);
}
}
}
void port_dir(port_t *obj, PinDirection dir) {
switch (dir) {
case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
}
}
void port_write(port_t *obj, int value) {
*obj->reg_in = value;
}
int port_read(port_t *obj) {
return (*obj->reg_in);
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// math.h required for floating point operations for baud rate calculation
#include <math.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "serial_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "gpio_api.h"
/******************************************************************************
* INITIALIZATION
******************************************************************************/
static const PinMap PinMap_UART_TX[] = {
{USBTX , UART_0, 0},
{XB_TX , UART_1, 0},
{SH0_TX , UART_2, 0},
{SH1_TX , UART_3, 0},
{NC , NC , 0}
};
static const PinMap PinMap_UART_RX[] = {
{USBRX , UART_0, 0},
{XB_RX , UART_1, 0},
{SH0_RX , UART_2, 0},
{SH1_RX , UART_3, 0},
{NC , NC , 0}
};
#define UART_NUM 4
static uart_irq_handler irq_handler;
int stdio_uart_inited = 0;
serial_t stdio_uart;
struct serial_global_data_s {
uint32_t serial_irq_id;
gpio_t sw_rts, sw_cts;
uint8_t count, rx_irq_set_flow, rx_irq_set_api;
};
static struct serial_global_data_s uart_data[UART_NUM];
void serial_init(serial_t *obj, PinName tx, PinName rx) {
int is_stdio_uart = 0;
// determine the UART to use
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
if ((int)uart == NC) {
error("Serial pinout mapping failed");
}
obj->uart = (CMSDK_UART_TypeDef *)uart;
//set baud rate and enable Uart in normarl mode (RX and TX enabled)
switch (uart)
{
case UART_0:
{
CMSDK_UART0->CTRL = 0x00; // Disable UART when changing configuration
if((int)uart_tx != NC)
{
CMSDK_UART0->CTRL |= 0x01; // TX enable
} else {
CMSDK_UART0->CTRL &= 0xFFFE; // TX disable
}
if((int)uart_rx != NC)
{
CMSDK_UART0->CTRL |= 0x02; // RX enable
} else {
CMSDK_UART0->CTRL &= 0xFFFD; // RX disable
}
}
break;
case UART_1: //XBEE SOCKET UART
{
CMSDK_UART1->CTRL = 0x00; // Disable UART when changing configuration
if((int)tx != NC)
{
CMSDK_UART1->CTRL = 0x1; // TX enable
CMSDK_GPIO1->ALTFUNCSET |= 0x0100;
}
if((int)rx != NC)
{
CMSDK_UART1->CTRL |= 0x2; // RX enable
CMSDK_GPIO1->ALTFUNCSET |= 0x0080;
}
}
break;
case UART_2: //Sheild0 UART
{
CMSDK_UART3->CTRL = 0x00; // Disable UART when changing configuration
if((int)tx != NC)
{
CMSDK_UART3->CTRL = 0x1; // TX enable
CMSDK_GPIO0->ALTFUNCSET |= 0x0010;
}
if((int)rx != NC)
{
CMSDK_UART3->CTRL |= 0x2; // RX enable
CMSDK_GPIO0->ALTFUNCSET |= 0x0001;
}
}
break;
case UART_3: //Sheild1 UART
{
CMSDK_UART4->CTRL = 0x00; // Disable UART when changing configuration
if((int)tx != NC)
{
CMSDK_UART4->CTRL = 0x1; // TX enable
CMSDK_GPIO1->ALTFUNCSET |= 0x4000;
}
if((int)rx != NC)
{
CMSDK_UART4->CTRL |= 0x2; // RX enable
CMSDK_GPIO1->ALTFUNCSET |= 0x0400;
}
}
break;
}
// set default baud rate and format
serial_baud (obj, 9600);
// pinout the chosen uart
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
switch (uart) {
case UART_0: obj->index = 0; break;
case UART_1: obj->index = 1; break;
case UART_2: obj->index = 2; break;
case UART_3: obj->index = 3; break;
}
uart_data[obj->index].sw_rts.pin = NC;
uart_data[obj->index].sw_cts.pin = NC;
serial_set_flow_control(obj, FlowControlNone, NC, NC);
is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
if (is_stdio_uart) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj) {
uart_data[obj->index].serial_irq_id = 0;
}
// serial_baud
// set the baud rate, taking in to account the current SystemFrequency
void serial_baud(serial_t *obj, int baudrate) {
// The MPS2 has a simple divider to control the baud rate. The formula is:
//
// Baudrate = PCLK / BAUDDIV
//
// PCLK = 25 Mhz
// so for a desired baud rate of 9600
// 25000000 / 9600 = 2604
//
//check to see if minimum baud value entered
int baudrate_div = 0;
baudrate_div = SystemCoreClock / baudrate;
if(baudrate >= 16){
switch ((int)obj->uart) {
case UART_0: CMSDK_UART0->BAUDDIV = baudrate_div; break;
case UART_1: CMSDK_UART1->BAUDDIV = baudrate_div; break;
case UART_2: CMSDK_UART3->BAUDDIV = baudrate_div; break;
case UART_3: CMSDK_UART4->BAUDDIV = baudrate_div; break;
default: error("serial_baud"); break;
}
} else {
error("serial_baud");
}
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
}
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
static inline void uart_irq(uint32_t intstatus, uint32_t index, CMSDK_UART_TypeDef *puart) {
SerialIrq irq_type;
switch (intstatus)
{
case 1:
{
irq_type = TxIrq;
}
break;
case 2:
{
irq_type = RxIrq;
}
break;
default: return;
} /* End of Switch */
if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin))
{
gpio_write(&uart_data[index].sw_rts, 1);
// Disable interrupt if it wasn't enabled by other part of the application
if (!uart_data[index].rx_irq_set_api)
{
/* Disable Rx interrupt */
puart->CTRL &= ~(CMSDK_UART_CTRL_RXIRQEN_Msk);
}
}
if (uart_data[index].serial_irq_id != 0)
{
if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api))
{
irq_handler(uart_data[index].serial_irq_id, irq_type);
}
}
if( irq_type == TxIrq )
{
/* Clear the TX interrupt Flag */
puart->INTCLEAR |= 0x01;
}
else
{
/* Clear the Rx interupt Flag */
puart->INTCLEAR |= 0x02;
}
}
void uart0_irq() {uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 0, (CMSDK_UART_TypeDef*)CMSDK_UART0);}
void uart1_irq() {uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef*)CMSDK_UART1);}
void uart2_irq() {uart_irq(CMSDK_UART3->INTSTATUS & 0x3, 2, (CMSDK_UART_TypeDef*)CMSDK_UART3);}
void uart3_irq() {uart_irq(CMSDK_UART4->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef*)CMSDK_UART4);}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
irq_handler = handler;
uart_data[obj->index].serial_irq_id = id;
}
static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
/* Declare a variable of type IRQn, initialise to 0 */
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0;
switch ((int)obj->uart)
{
case UART_0:
{
irq_n = (( irq == TxIrq ) ? UARTTX0_IRQn : UARTRX0_IRQn);
vector = (uint32_t)&uart0_irq;
}
break;
case UART_1:
{
irq_n = (( irq == TxIrq ) ? UARTTX1_IRQn : UARTRX1_IRQn);
vector = (uint32_t)&uart1_irq;
}
break;
case UART_2:
{
irq_n = (( irq == TxIrq ) ? UARTTX3_IRQn : UARTRX3_IRQn);
vector = (uint32_t)&uart2_irq;
}
break;
case UART_3:
{
irq_n = (( irq == TxIrq ) ? UARTTX4_IRQn : UARTRX4_IRQn);
vector = (uint32_t)&uart3_irq;
}
break;
}
if (enable)
{
if( irq == TxIrq )
{
/* Transmit IRQ, set appripriate enable */
/* set TX interrupt enable in CTRL REG */
obj->uart->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk;
}
else
{
/* set Rx interrupt on in CTRL REG */
obj->uart->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk;
}
NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n);
}
else
{ /* Disable IRQ */
obj->uart->CTRL &= ~(1 << (irq + 2));
NVIC_DisableIRQ(irq_n);
}
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
serial_irq_set_internal(obj, irq, enable);
}
/******************************************************************************
* READ/WRITE
******************************************************************************/
int serial_getc(serial_t *obj) {
while (serial_readable(obj) == 0);
int data = obj->uart->DATA;
return data;
}
void serial_putc(serial_t *obj, int c) {
while (serial_writable(obj) == 0);
obj->uart->DATA = c;
}
int serial_readable(serial_t *obj) {
return obj->uart->STATE & 0x2;
}
int serial_writable(serial_t *obj) {
return !(obj->uart->STATE & 0x1);
}
void serial_clear(serial_t *obj) {
obj->uart->DATA = 0x00;
}
void serial_pinout_tx(PinName tx) {
pinmap_pinout(tx, PinMap_UART_TX);
}
void serial_break_set(serial_t *obj) {
}
void serial_break_clear(serial_t *obj) {
}
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <math.h>
#include "spi_api.h"
#include "spi_def.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "mbed_wait_api.h"
static const PinMap PinMap_SPI_SCLK[] = {
{SCLK_SPI , SPI_0, 0},
{CLCD_SCLK , SPI_1, 0},
{ADC_SCLK , SPI_2, 0},
{SHIELD_0_SPI_SCK , SPI_3, 0},
{SHIELD_1_SPI_SCK , SPI_4, 0},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MOSI[] = {
{MOSI_SPI, SPI_0, 0},
{CLCD_MOSI, SPI_1, 0},
{ADC_MOSI, SPI_2, 0},
{SHIELD_0_SPI_MOSI, SPI_3, 0},
{SHIELD_1_SPI_MOSI, SPI_4, 0},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MISO[] = {
{MISO_SPI, SPI_0, 0},
{CLCD_MISO, SPI_1, 0},
{ADC_MISO, SPI_2, 0},
{SHIELD_0_SPI_MISO, SPI_3, 0},
{SHIELD_1_SPI_MISO, SPI_4, 0},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_SSEL[] = {
{SSEL_SPI, SPI_0, 0},
{CLCD_SSEL, SPI_1, 0},
{ADC_SSEL, SPI_2, 0},
{SHIELD_0_SPI_nCS, SPI_3, 0},
{SHIELD_1_SPI_nCS, SPI_4, 0},
{NC , NC , 0}
};
static inline int ssp_disable(spi_t *obj);
static inline int ssp_enable(spi_t *obj);
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
int altfunction[4];
// determine the SPI to use
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->spi = (MPS2_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
if ((int)obj->spi == NC) {
error("SPI pinout mapping failed");
}
// enable power and clocking
switch ((int)obj->spi) {
case (int)SPI_0:
obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT;
obj->spi->IMSC = 0x8;
obj->spi->DMACR = 0;
obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3;
break;
case (int)SPI_1:
/* Configure SSP used for LCD */
obj->spi->CR1 = 0; /* Synchronous serial port disable */
obj->spi->DMACR = 0; /* Disable FIFO DMA */
obj->spi->IMSC = 0; /* Mask all FIFO/IRQ interrupts */
obj->spi->ICR = ((1ul << 0) | /* Clear SSPRORINTR interrupt */
(1ul << 1) ); /* Clear SSPRTINTR interrupt */
obj->spi->CR0 = ((7ul << 0) | /* 8 bit data size */
(0ul << 4) | /* Motorola frame format */
(0ul << 6) | /* CPOL = 0 */
(0ul << 7) | /* CPHA = 0 */
(1ul << 8) ); /* Set serial clock rate */
obj->spi->CPSR = (2ul << 0); /* set SSP clk to 6MHz (6.6MHz max) */
obj->spi->CR1 = ((1ul << 1) | /* Synchronous serial port enable */
(0ul << 2) ); /* Device configured as master */
break;
case (int)SPI_2:
obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT;
obj->spi->IMSC = 0x8;
obj->spi->DMACR = 0;
obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3;
break;
case (int)SPI_3:
obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT;
obj->spi->IMSC = 0x8;
obj->spi->DMACR = 0;
obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3;
break;
case (int)SPI_4:
obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT;
obj->spi->IMSC = 0x8;
obj->spi->DMACR = 0;
obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3;
break;
}
if(mosi != NC){ altfunction[0] = 1;}else{ altfunction[0] = 0;}
if(miso != NC){ altfunction[1] = 1;}else{ altfunction[1] = 0;}
if(sclk != NC){ altfunction[2] = 1;}else{ altfunction[2] = 0;}
if(ssel != NC){ altfunction[3] = 1;}else{ altfunction[3] = 0;}
// enable alt function
switch ((int)obj->spi) {
case (int)SPI_2:
CMSDK_GPIO1->ALTFUNCSET |= (altfunction[2]<<3 | altfunction[0]<<2 | altfunction[1]<<1 | altfunction[3]);
break;
case (int)SPI_3:
CMSDK_GPIO0->ALTFUNCSET |= (altfunction[1]<<14 | altfunction[0]<<13 | altfunction[3]<<12 | altfunction[2]<<11);
break;
case (int)SPI_4:
CMSDK_GPIO2->ALTFUNCSET |= (altfunction[2]<<12 | altfunction[1]<<8 | altfunction[0]<<7 | altfunction[3]<<6);
break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable the ssp channel
ssp_enable(obj);
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
}
void spi_free(spi_t *obj) {}
void spi_format(spi_t *obj, int bits, int mode, int slave) {
ssp_disable(obj);
if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
error("SPI format error");
}
int polarity = (mode & 0x2) ? 1 : 0;
int phase = (mode & 0x1) ? 1 : 0;
// set it up
int DSS = bits - 1; // DSS (data select size)
int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
int SPH = (phase) ? 1 : 0; // SPH - clock out phase
int FRF = 0; // FRF (frame format) = SPI
uint32_t tmp = obj->spi->CR0;
tmp &= ~(0xFFFF);
tmp |= DSS << 0
| FRF << 4
| SPO << 6
| SPH << 7;
obj->spi->CR0 = tmp;
tmp = obj->spi->CR1;
tmp &= ~(0xD);
tmp |= 0 << 0 // LBM - loop back mode - off
| ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
| 0 << 3; // SOD - slave output disable - na
obj->spi->CR1 = tmp;
ssp_enable(obj);
}
void spi_frequency(spi_t *obj, int hz) {
ssp_disable(obj);
uint32_t PCLK = SystemCoreClock;
int prescaler;
for (prescaler = 2; prescaler <= 254; prescaler += 2) {
int prescale_hz = PCLK / prescaler;
// calculate the divider
int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
// check we can support the divider
if (divider < 256) {
// prescaler
obj->spi->CPSR = prescaler;
// divider
obj->spi->CR0 &= ~(0xFFFF << 8);
obj->spi->CR0 |= (divider - 1) << 8;
ssp_enable(obj);
return;
}
}
error("Couldn't setup requested SPI frequency");
}
static inline int ssp_disable(spi_t *obj) {
return obj->spi->CR1 &= ~(1 << 1);
}
static inline int ssp_enable(spi_t *obj) {
return obj->spi->CR1 |= SSP_CR1_SSE_Msk;
}
static inline int ssp_readable(spi_t *obj) {
return obj->spi->SR & (1 << 2);
}
static inline int ssp_writeable(spi_t *obj) {
return obj->spi->SR & SSP_SR_BSY_Msk;
}
static inline void ssp_write(spi_t *obj, int value) {
obj->spi->DR = value;
while (ssp_writeable(obj));
}
static inline int ssp_read(spi_t *obj) {
int read_DR = obj->spi->DR;
return read_DR;
}
static inline int ssp_busy(spi_t *obj) {
return (obj->spi->SR & (1 << 4)) ? (1) : (0);
}
int spi_master_write(spi_t *obj, int value) {
ssp_write(obj, value);
while (obj->spi->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */
return (ssp_read(obj));
}
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
char *rx_buffer, int rx_length, char write_fill) {
int total = (tx_length > rx_length) ? tx_length : rx_length;
for (int i = 0; i < total; i++) {
char out = (i < tx_length) ? tx_buffer[i] : write_fill;
char in = spi_master_write(obj, out);
if (i < rx_length) {
rx_buffer[i] = in;
}
}
return total;
}
int spi_slave_receive(spi_t *obj) {
return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
}
int spi_slave_read(spi_t *obj) {
return obj->spi->DR;
}
void spi_slave_write(spi_t *obj, int value) {
while (ssp_writeable(obj) == 0) ;
obj->spi->DR = value;
}
int spi_busy(spi_t *obj) {
return ssp_busy(obj);
}

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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_def.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* ----------------------------------------------------------------
* File: apspi.h
* Release: Version 2.0
* ----------------------------------------------------------------
*
* SSP interface Support
* =====================
*/
#define SSPCS_BASE (0x4002804C) // SSP chip select register
#define SSP_BASE (0x40020000) // SSP Prime Cell
#define SSPCR0 ((volatile unsigned int *)(SSP_BASE + 0x00))
#define SSPCR1 ((volatile unsigned int *)(SSP_BASE + 0x04))
#define SSPDR ((volatile unsigned int *)(SSP_BASE + 0x08))
#define SSPSR ((volatile unsigned int *)(SSP_BASE + 0x0C))
#define SSPCPSR ((volatile unsigned int *)(SSP_BASE + 0x10))
#define SSPIMSC ((volatile unsigned int *)(SSP_BASE + 0x14))
#define SSPRIS ((volatile unsigned int *)(SSP_BASE + 0x18))
#define SSPMIS ((volatile unsigned int *)(SSP_BASE + 0x1C))
#define SSPICR ((volatile unsigned int *)(SSP_BASE + 0x20))
#define SSPDMACR ((volatile unsigned int *)(SSP_BASE + 0x24))
#define SSPCS ((volatile unsigned int *)(SSPCS_BASE))
// SSPCR0 Control register 0
#define SSPCR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
#define SSPCR0_SPH 0x0080 // SSPCLKOUT phase
#define SSPCR0_SPO 0x0040 // SSPCLKOUT polarity
#define SSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
#define SSPCR0_DSS_8 0x0007 // Data packet size, 8bits
#define SSPCR0_DSS_16 0x000F // Data packet size, 16bits
// SSPCR1 Control register 1
#define SSPCR1_SOD 0x0008 // Slave Output mode Disable
#define SSPCR1_MS 0x0004 // Master or Slave mode
#define SSPCR1_SSE 0x0002 // Serial port enable
#define SSPCR1_LBM 0x0001 // Loop Back Mode
// SSPSR Status register
#define SSPSR_BSY 0x0010 // Busy
#define SSPSR_RFF 0x0008 // Receive FIFO full
#define SSPSR_RNE 0x0004 // Receive FIFO not empty
#define SSPSR_TNF 0x0002 // Transmit FIFO not full
#define SSPSR_TFE 0x0001 // Transmit FIFO empty
// SSPCPSR Clock prescale register
#define SSPCPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
// SSPIMSC Interrupt mask set and clear register
#define SSPIMSC_TXIM 0x0008 // Transmit FIFO not Masked
#define SSPIMSC_RXIM 0x0004 // Receive FIFO not Masked
#define SSPIMSC_RTIM 0x0002 // Receive timeout not Masked
#define SSPIMSC_RORIM 0x0001 // Receive overrun not Masked
// SSPRIS Raw interrupt status register
#define SSPRIS_TXRIS 0x0008 // Raw Transmit interrupt flag
#define SSPRIS_RXRIS 0x0004 // Raw Receive interrupt flag
#define SSPRIS_RTRIS 0x0002 // Raw Timemout interrupt flag
#define SSPRIS_RORRIS 0x0001 // Raw Overrun interrupt flag
// SSPMIS Masked interrupt status register
#define SSPMIS_TXMIS 0x0008 // Masked Transmit interrupt flag
#define SSPMIS_RXMIS 0x0004 // Masked Receive interrupt flag
#define SSPMIS_RTMIS 0x0002 // Masked Timemout interrupt flag
#define SSPMIS_RORMIS 0x0001 // Masked Overrun interrupt flag
// SSPICR Interrupt clear register
#define SSPICR_RTIC 0x0002 // Clears Timeout interrupt flag
#define SSPICR_RORIC 0x0001 // Clears Overrun interrupt flag
// SSPDMACR DMA control register
#define SSPDMACR_TXDMAE 0x0002 // Enable Transmit FIFO DMA
#define SSPDMACR_RXDMAE 0x0001 // Enable Receive FIFO DMA
// SPICS register (0=Chip Select low)
#define SSPCS_nCS1 0x0002 // nCS1 (SPI_nSS)
// SPI defaults
#define SSPMAXTIME 1000 // Maximum time to wait for SSP (10*10uS)
// EEPROM instruction set
#define EEWRSR 0x0001 // Write status
#define EEWRITE 0x0002 // Write data
#define EEREAD 0x0003 // Read data
#define EEWDI 0x0004 // Write disable
#define EEWREN 0x0006 // Write enable
#define EERDSR 0x0005 // Read status
// EEPROM status register flags
#define EERDSR_WIP 0x0001 // Write in process
#define EERDSR_WEL 0x0002 // Write enable latch
#define EERDSR_BP0 0x0004 // Block protect 0
#define EERDSR_BP1 0x0008 // Block protect 1
#define EERDSR_WPEN 0x0080 // Write protect enable
/* ----------------------------------------------------------------
*
* Color LCD Support
* =================
*/
// Color LCD Controller Internal Register addresses
#define LSSPCS_BASE (0x4002804C) // LSSP chip select register
#define LSSP_BASE (0x40021000) // LSSP Prime Cell
#define LSSPCR0 ((volatile unsigned int *)(LSSP_BASE + 0x00))
#define LSSPCR1 ((volatile unsigned int *)(LSSP_BASE + 0x04))
#define LSSPDR ((volatile unsigned int *)(LSSP_BASE + 0x08))
#define LSSPSR ((volatile unsigned int *)(LSSP_BASE + 0x0C))
#define LSSPCPSR ((volatile unsigned int *)(LSSP_BASE + 0x10))
#define LSSPIMSC ((volatile unsigned int *)(LSSP_BASE + 0x14))
#define LSSPRIS ((volatile unsigned int *)(LSSP_BASE + 0x18))
#define LSSPMIS ((volatile unsigned int *)(LSSP_BASE + 0x1C))
#define LSSPICR ((volatile unsigned int *)(LSSP_BASE + 0x20))
#define LSSPDMACR ((volatile unsigned int *)(LSSP_BASE + 0x24))
#define LSSPCS ((volatile unsigned int *)(LSSPCS_BASE))
// LSSPCR0 Control register 0
#define LSSPCR0_SCR_DFLT 0x0100 // Serial Clock Rate (divide), CLK/(CPSR*(1+SCR))
#define LSSPCR0_SPH 0x0080 // LSSPCLKOUT phase
#define LSSPCR0_SPO 0x0040 // LSSPCLKOUT polarity
#define LSSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
#define LSSPCR0_DSS_8 0x0007 // Data packet size, 8bits
#define LSSPCR0_DSS_16 0x000F // Data packet size, 16bits
// LSSPCR1 Control register 1
#define LSSPCR1_SOD 0x0008 // Slave Output mode Disable
#define LSSPCR1_MS 0x0004 // Master or Slave mode
#define LSSPCR1_SSE 0x0002 // Serial port enable
#define LSSPCR1_LBM 0x0001 // Loop Back Mode
// LSSPSR Status register
#define LSSPSR_BSY 0x0010 // Busy
#define LSSPSR_RFF 0x0008 // Receive FIFO full
#define LSSPSR_RNE 0x0004 // Receive FIFO not empty
#define LSSPSR_TNF 0x0002 // Transmit FIFO not full
#define LSSPSR_TFE 0x0001 // Transmit FIFO empty
// LSSPCPSR Clock prescale register
#define LSSPCPSR_DFLT 0x0002 // Clock prescale (use with SCR)
// SPICS register
#define LSSPCS_nCS0 0x0001 // nCS0 (CLCD_CS)
#define LSSPCS_nCS2 0x0004 // nCS2 (CLCD_T_CS)
#define LCD_RESET 0x0008 // RESET (CLCD_RESET)
#define LCD_RS 0x0010 // RS (CLCD_RS)
#define LCD_RD 0x0020 // RD (CLCD_RD)
#define LCD_BL 0x0040 // Backlight (CLCD_BL_CTRL)
// SPI defaults
#define LSSPMAXTIME 10000 // Maximum time to wait for LSSP (10*10uS)
#define LSPI_START (0x70) // Start byte for SPI transfer
#define LSPI_RD (0x01) // WR bit 1 within start
#define LSPI_WR (0x00) // WR bit 0 within start
#define LSPI_DATA (0x02) // RS bit 1 within start byte
#define LSPI_INDEX (0x00) // RS bit 0 within start byte
// Screen size
#define LCD_WIDTH 320 // Screen Width (in pixels)
#define LCD_HEIGHT 240 // Screen Height (in pixels)

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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/us_ticker.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "us_ticker_api.h"
#include "PeripheralNames.h"
#define US_TICKER_TIMER1 CMSDK_DUALTIMER1
#define US_TICKER_TIMER2 CMSDK_DUALTIMER2
#define US_TICKER_TIMER_IRQn DUALTIMER_IRQn
int us_ticker_inited = 0;
void us_ticker_init(void) {
if (us_ticker_inited) return;
us_ticker_inited = 1;
US_TICKER_TIMER1->TimerControl = 0x0; // disable timer
US_TICKER_TIMER2->TimerControl = 0x00; // disable timer
US_TICKER_TIMER1->TimerLoad = 0xFFFFFFFF;
US_TICKER_TIMER2->TimerLoad = 0xFFFFFFFF;
US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode
US_TICKER_TIMER2->TimerControl = 0x42; // enable interrupt and set to 32 bit counter
US_TICKER_TIMER1->TimerControl |= 0x80; // enable counter
US_TICKER_TIMER2->TimerControl |= 0x80; // enable counter
NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
}
uint32_t us_ticker_read() {
uint32_t return_value = 0;
if (!us_ticker_inited)
us_ticker_init();
return_value = ((~US_TICKER_TIMER2->TimerValue)/25);
return return_value;
}
void us_ticker_set_interrupt(timestamp_t timestamp) {
if (!us_ticker_inited)
us_ticker_init();
uint32_t delta = timestamp - us_ticker_read();
// enable interrupt
US_TICKER_TIMER1->TimerControl = 0x0; // disable timer
US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode
US_TICKER_TIMER1->TimerLoad = (delta)*25; //initialise the timer value
US_TICKER_TIMER1->TimerControl |= 0x80; //enable timer
}
void us_ticker_fire_interrupt(void)
{
NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
}
void us_ticker_disable_interrupt(void) {
US_TICKER_TIMER1->TimerControl &= 0xDF;
US_TICKER_TIMER2->TimerControl &= 0xDF;
}
void us_ticker_clear_interrupt(void) {
US_TICKER_TIMER1->TimerIntClr = 0x1;
US_TICKER_TIMER2->TimerIntClr = 0x1;
}

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targets/TARGET_ARM_FM/mbed_rtx.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2016-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_MBED_RTX_H
#define MBED_MBED_RTX_H
#if defined(TARGET_FVP_MPS2)
#ifndef INITIAL_SP
#define INITIAL_SP (0x20020000UL)
#endif
#endif /* defined(TARGET_...) */
#endif /* MBED_MBED_RTX_H */