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Merge pull request #5792 from jeromecoutant/PULL_REQUEST_CUBE_UPDATE_F0_V1.9.0 

STM32F0 : ST CUBE version update to V1.9.0
pull/5744/merge
Cruz Monrreal 2018-01-11 10:24:28 -06:00 committed by GitHub
parent f10e663b7a 9f4bec2f2e
commit 2c5fedc0b2
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
188 changed files with 6410 additions and 6202 deletions
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2
targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.S
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@ -1,8 +1,6 @@
;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f051x8.s ;* File Name : startup_stm32f051x8.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V2.2.2
;* Date : 26-June-2015
;* Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain. ;* Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.S
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@ -1,8 +1,6 @@
;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f051x8.s ;* File Name : startup_stm32f051x8.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V2.2.2
;* Date : 26-June-2015
;* Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain. ;* Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP

40
targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f051x8.S
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@ -2,9 +2,7 @@
****************************************************************************** ******************************************************************************
* @file startup_stm32f051x8.s * @file startup_stm32f051x8.s
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @brief STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for GCC toolchain.
* @date 03-Oct-2014
* @brief STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs: * This module performs:
* - Set the initial SP * - Set the initial SP
* - Set the initial PC == Reset_Handler, * - Set the initial PC == Reset_Handler,
@ -55,6 +53,10 @@ defined in linker script */
.word _sdata .word _sdata
/* end address for the .data section. defined in linker script */ /* end address for the .data section. defined in linker script */
.word _edata .word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.section .text.Reset_Handler .section .text.Reset_Handler
.weak Reset_Handler .weak Reset_Handler
@ -64,22 +66,36 @@ Reset_Handler:
mov sp, r0 /* set stack pointer */ mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */ /* Copy the data segment initializers from flash to SRAM */
movs r1, #0 ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit b LoopCopyDataInit
CopyDataInit: CopyDataInit:
ldr r3, =_sidata ldr r4, [r2, r3]
ldr r3, [r3, r1] str r4, [r0, r3]
str r3, [r0, r1] adds r3, r3, #4
adds r1, r1, #4
LoopCopyDataInit: LoopCopyDataInit:
ldr r0, =_sdata adds r4, r0, r3
ldr r3, =_edata cmp r4, r1
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/ /* Call the clock system intitialization function.*/
bl SystemInit bl SystemInit

6
targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h
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@ -46,11 +46,11 @@
#define TIM_MST TIM1 #define TIM_MST TIM1
#define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn #define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn
#define TIM_MST_OC_IRQ TIM1_CC_IRQn #define TIM_MST_OC_IRQ TIM1_CC_IRQn
#define TIM_MST_RCC __TIM1_CLK_ENABLE() #define TIM_MST_RCC __HAL_RCC_TIM1_CLK_ENABLE()
#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM1() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM1()
#define TIM_MST_RESET_ON __TIM1_FORCE_RESET() #define TIM_MST_RESET_ON __HAL_RCC_TIM1_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM1_RELEASE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM1_RELEASE_RESET()
#define TIM_MST_16BIT 1 // 1=16-bit timer, 0=32-bit timer #define TIM_MST_16BIT 1 // 1=16-bit timer, 0=32-bit timer

222
targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f051x8.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f051x8.h * @file stm32f051x8.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices. * definitions and memory mapping for STM32F0xx devices.
@ -2805,56 +2803,108 @@ typedef struct
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
/****************** Bit definition for GPIO_AFRL register ********************/ /****************** Bit definition for GPIO_AFRL register ********************/
#define GPIO_AFRL_AFRL0_Pos (0U) #define GPIO_AFRL_AFSEL0_Pos (0U)
#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFRL1_Pos (4U) #define GPIO_AFRL_AFSEL1_Pos (4U)
#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFRL2_Pos (8U) #define GPIO_AFRL_AFSEL2_Pos (8U)
#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFRL3_Pos (12U) #define GPIO_AFRL_AFSEL3_Pos (12U)
#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFRL4_Pos (16U) #define GPIO_AFRL_AFSEL4_Pos (16U)
#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFRL5_Pos (20U) #define GPIO_AFRL_AFSEL5_Pos (20U)
#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFRL6_Pos (24U) #define GPIO_AFRL_AFSEL6_Pos (24U)
#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFRL7_Pos (28U) #define GPIO_AFRL_AFSEL7_Pos (28U)
#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
/* Legacy aliases */
#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos
#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos
#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos
#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos
#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos
#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos
#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos
#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos
#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
/****************** Bit definition for GPIO_AFRH register ********************/ /****************** Bit definition for GPIO_AFRH register ********************/
#define GPIO_AFRH_AFRH0_Pos (0U) #define GPIO_AFRH_AFSEL8_Pos (0U)
#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFRH1_Pos (4U) #define GPIO_AFRH_AFSEL9_Pos (4U)
#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFRH2_Pos (8U) #define GPIO_AFRH_AFSEL10_Pos (8U)
#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFRH3_Pos (12U) #define GPIO_AFRH_AFSEL11_Pos (12U)
#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFRH4_Pos (16U) #define GPIO_AFRH_AFSEL12_Pos (16U)
#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFRH5_Pos (20U) #define GPIO_AFRH_AFSEL13_Pos (20U)
#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFRH6_Pos (24U) #define GPIO_AFRH_AFSEL14_Pos (24U)
#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFRH7_Pos (28U) #define GPIO_AFRH_AFSEL15_Pos (28U)
#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
/* Legacy aliases */
#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos
#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos
#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos
#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos
#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos
#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos
#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos
#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos
#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
/****************** Bit definition for GPIO_BRR register *********************/ /****************** Bit definition for GPIO_BRR register *********************/
#define GPIO_BRR_BR_0 (0x00000001U) #define GPIO_BRR_BR_0 (0x00000001U)
@ -3524,72 +3574,72 @@ typedef struct
/***************** Bit definition for RCC_APB2RSTR register ****************/ /***************** Bit definition for RCC_APB2RSTR register ****************/
#define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
#define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Pos (9U)
#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */
#define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Pos (11U)
#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */
#define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Pos (12U)
#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
#define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Pos (14U)
#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
#define RCC_APB2RSTR_TIM15RST_Pos (16U) #define RCC_APB2RSTR_TIM15RST_Pos (16U)
#define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */ #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */
#define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Pos (17U)
#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */
#define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */
#define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Pos (22U)
#define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */
/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ /*!< Old ADC1 reset bit definition maintained for legacy purpose */
#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
/***************** Bit definition for RCC_APB1RSTR register ****************/ /***************** Bit definition for RCC_APB1RSTR register ****************/
#define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Pos (0U)
#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
#define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Pos (1U)
#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
#define RCC_APB1RSTR_TIM6RST_Pos (4U) #define RCC_APB1RSTR_TIM6RST_Pos (4U)
#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
#define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Pos (8U)
#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */
#define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Pos (11U)
#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
#define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Pos (14U)
#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */
#define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Pos (17U)
#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
#define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Pos (21U)
#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
#define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Pos (22U)
#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
#define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Pos (28U)
#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
#define RCC_APB1RSTR_DACRST_Pos (29U) #define RCC_APB1RSTR_DACRST_Pos (29U)
#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */ #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC reset */
#define RCC_APB1RSTR_CECRST_Pos (30U) #define RCC_APB1RSTR_CECRST_Pos (30U)
#define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */ #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */
#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC clock reset */ #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC reset */
/****************** Bit definition for RCC_AHBENR register *****************/ /****************** Bit definition for RCC_AHBENR register *****************/
#define RCC_AHBENR_DMAEN_Pos (0U) #define RCC_AHBENR_DMAEN_Pos (0U)
@ -3775,25 +3825,25 @@ typedef struct
/******************* Bit definition for RCC_AHBRSTR register ***************/ /******************* Bit definition for RCC_AHBRSTR register ***************/
#define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Pos (17U)
#define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */
#define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Pos (18U)
#define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */
#define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Pos (19U)
#define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */
#define RCC_AHBRSTR_GPIODRST_Pos (20U) #define RCC_AHBRSTR_GPIODRST_Pos (20U)
#define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */ #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */
#define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Pos (22U)
#define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */
#define RCC_AHBRSTR_TSCRST_Pos (24U) #define RCC_AHBRSTR_TSCRST_Pos (24U)
#define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */ #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS clock reset */ #define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS reset */
/* Old Bit definition maintained for legacy purpose */ /* Old Bit definition maintained for legacy purpose */
#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */ #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS reset */
/******************* Bit definition for RCC_CFGR2 register *****************/ /******************* Bit definition for RCC_CFGR2 register *****************/
/*!< PREDIV configuration */ /*!< PREDIV configuration */
@ -3986,9 +4036,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -4020,6 +4070,11 @@ typedef struct
#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register *****************/ /******************** Bits definition for RTC_ISR register *****************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
@ -6636,6 +6691,9 @@ typedef struct
#define IS_TIM_REMAP_INSTANCE(INSTANCE)\ #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
((INSTANCE) == TIM14) ((INSTANCE) == TIM14)
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
((INSTANCE) == TIM1)
/****************************** TSC Instances *********************************/ /****************************** TSC Instances *********************************/
#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)

6
targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f0xx.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx.h * @file stm32f0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
@ -112,11 +110,11 @@
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V2.3.1 * @brief CMSIS Device version number V2.3.3
*/ */
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

1
targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_clock.c
View File

@ -212,7 +212,6 @@ uint8_t SetSysClock_PLL_HSI(void)
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.HSI14State = RCC_HSI_OFF; RCC_OscInitStruct.HSI14State = RCC_HSI_OFF;
RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT;
RCC_OscInitStruct.HSI48State = RCC_HSI_ON;
RCC_OscInitStruct.LSIState = RCC_LSI_OFF; RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_stm32f0xx.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f0xx.h * @file system_stm32f0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention

6
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f030x8.S
View File

@ -101,7 +101,7 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD 0 ; Reserved DCD 0 ; Reserved
DCD TIM3_IRQHandler ; TIM3 DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved DCD TIM6_IRQHandler ; TIM6
DCD 0 ; Reserved DCD 0 ; Reserved
DCD TIM14_IRQHandler ; TIM14 DCD TIM14_IRQHandler ; TIM14
DCD TIM15_IRQHandler ; TIM15 DCD TIM15_IRQHandler ; TIM15
@ -120,7 +120,7 @@ __Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY AREA |.text|, CODE, READONLY
; Reset handler ; Reset handler routine
Reset_Handler PROC Reset_Handler PROC
EXPORT Reset_Handler [WEAK] EXPORT Reset_Handler [WEAK]
IMPORT __main IMPORT __main
@ -171,6 +171,7 @@ Default_Handler PROC
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK] EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM15_IRQHandler [WEAK] EXPORT TIM15_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK] EXPORT TIM16_IRQHandler [WEAK]
@ -197,6 +198,7 @@ ADC1_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler TIM1_CC_IRQHandler
TIM3_IRQHandler TIM3_IRQHandler
TIM6_IRQHandler
TIM14_IRQHandler TIM14_IRQHandler
TIM15_IRQHandler TIM15_IRQHandler
TIM16_IRQHandler TIM16_IRQHandler

6
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_STD/startup_stm32f030x8.S
View File

@ -74,7 +74,7 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD 0 ; Reserved DCD 0 ; Reserved
DCD TIM3_IRQHandler ; TIM3 DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved DCD TIM6_IRQHandler ; TIM6
DCD 0 ; Reserved DCD 0 ; Reserved
DCD TIM14_IRQHandler ; TIM14 DCD TIM14_IRQHandler ; TIM14
DCD TIM15_IRQHandler ; TIM15 DCD TIM15_IRQHandler ; TIM15
@ -93,7 +93,7 @@ __Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY AREA |.text|, CODE, READONLY
; Reset handler ; Reset handler routine
Reset_Handler PROC Reset_Handler PROC
EXPORT Reset_Handler [WEAK] EXPORT Reset_Handler [WEAK]
IMPORT __main IMPORT __main
@ -144,6 +144,7 @@ Default_Handler PROC
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK] EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM15_IRQHandler [WEAK] EXPORT TIM15_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK] EXPORT TIM16_IRQHandler [WEAK]
@ -170,6 +171,7 @@ ADC1_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler TIM1_CC_IRQHandler
TIM3_IRQHandler TIM3_IRQHandler
TIM6_IRQHandler
TIM14_IRQHandler TIM14_IRQHandler
TIM15_IRQHandler TIM15_IRQHandler
TIM16_IRQHandler TIM16_IRQHandler

40
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.S
View File

@ -2,9 +2,7 @@
****************************************************************************** ******************************************************************************
* @file startup_stm32f030x8.s * @file startup_stm32f030x8.s
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @brief STM32F030x8 devices vector table for GCC toolchain.
* @date 03-Oct-2014
* @brief STM32F030x8 devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs: * This module performs:
* - Set the initial SP * - Set the initial SP
* - Set the initial PC == Reset_Handler, * - Set the initial PC == Reset_Handler,
@ -55,6 +53,10 @@ defined in linker script */
.word _sdata .word _sdata
/* end address for the .data section. defined in linker script */ /* end address for the .data section. defined in linker script */
.word _edata .word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.section .text.Reset_Handler .section .text.Reset_Handler
.weak Reset_Handler .weak Reset_Handler
@ -64,22 +66,36 @@ Reset_Handler:
mov sp, r0 /* set stack pointer */ mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */ /* Copy the data segment initializers from flash to SRAM */
movs r1, #0 ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit b LoopCopyDataInit
CopyDataInit: CopyDataInit:
ldr r3, =_sidata ldr r4, [r2, r3]
ldr r3, [r3, r1] str r4, [r0, r3]
str r3, [r0, r1] adds r3, r3, #4
adds r1, r1, #4
LoopCopyDataInit: LoopCopyDataInit:
ldr r0, =_sdata adds r4, r0, r3
ldr r3, =_edata cmp r4, r1
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/ /* Call the clock system intitialization function.*/
bl SystemInit bl SystemInit

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_IAR/startup_stm32f030x8.S
View File

@ -1,8 +1,6 @@
;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f030x8.s ;* File Name : startup_stm32f030x8.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V2.1.0
;* Date : 03-Oct-2014
;* Description : STM32F030x8 devices vector table for EWARM toolchain. ;* Description : STM32F030x8 devices vector table for EWARM toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP
@ -15,8 +13,6 @@
;* priority is Privileged, and the Stack is set to Main. ;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************* ;*******************************************************************************
;* ;*
;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
;*
;* Redistribution and use in source and binary forms, with or without modification, ;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met: ;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice, ;* 1. Redistributions of source code must retain the above copyright notice,

6
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h
View File

@ -46,11 +46,11 @@
#define TIM_MST TIM1 #define TIM_MST TIM1
#define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn #define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn
#define TIM_MST_OC_IRQ TIM1_CC_IRQn #define TIM_MST_OC_IRQ TIM1_CC_IRQn
#define TIM_MST_RCC __TIM1_CLK_ENABLE() #define TIM_MST_RCC __HAL_RCC_TIM1_CLK_ENABLE()
#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM1() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM1()
#define TIM_MST_RESET_ON __TIM1_FORCE_RESET() #define TIM_MST_RESET_ON __HAL_RCC_TIM1_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM1_RELEASE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM1_RELEASE_RESET()
#define TIM_MST_16BIT 1 // 1=16-bit timer, 0=32-bit timer #define TIM_MST_16BIT 1 // 1=16-bit timer, 0=32-bit timer

212
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f030x8.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f030x8.h * @file stm32f030x8.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices. * definitions and memory mapping for STM32F0xx devices.
@ -2301,56 +2299,108 @@ typedef struct
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
/****************** Bit definition for GPIO_AFRL register ********************/ /****************** Bit definition for GPIO_AFRL register ********************/
#define GPIO_AFRL_AFRL0_Pos (0U) #define GPIO_AFRL_AFSEL0_Pos (0U)
#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFRL1_Pos (4U) #define GPIO_AFRL_AFSEL1_Pos (4U)
#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFRL2_Pos (8U) #define GPIO_AFRL_AFSEL2_Pos (8U)
#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFRL3_Pos (12U) #define GPIO_AFRL_AFSEL3_Pos (12U)
#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFRL4_Pos (16U) #define GPIO_AFRL_AFSEL4_Pos (16U)
#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFRL5_Pos (20U) #define GPIO_AFRL_AFSEL5_Pos (20U)
#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFRL6_Pos (24U) #define GPIO_AFRL_AFSEL6_Pos (24U)
#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFRL7_Pos (28U) #define GPIO_AFRL_AFSEL7_Pos (28U)
#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
/* Legacy aliases */
#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos
#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos
#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos
#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos
#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos
#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos
#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos
#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos
#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
/****************** Bit definition for GPIO_AFRH register ********************/ /****************** Bit definition for GPIO_AFRH register ********************/
#define GPIO_AFRH_AFRH0_Pos (0U) #define GPIO_AFRH_AFSEL8_Pos (0U)
#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFRH1_Pos (4U) #define GPIO_AFRH_AFSEL9_Pos (4U)
#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFRH2_Pos (8U) #define GPIO_AFRH_AFSEL10_Pos (8U)
#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFRH3_Pos (12U) #define GPIO_AFRH_AFSEL11_Pos (12U)
#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFRH4_Pos (16U) #define GPIO_AFRH_AFSEL12_Pos (16U)
#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFRH5_Pos (20U) #define GPIO_AFRH_AFSEL13_Pos (20U)
#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFRH6_Pos (24U) #define GPIO_AFRH_AFSEL14_Pos (24U)
#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFRH7_Pos (28U) #define GPIO_AFRH_AFSEL15_Pos (28U)
#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
/* Legacy aliases */
#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos
#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos
#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos
#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos
#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos
#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos
#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos
#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos
#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
/****************** Bit definition for GPIO_BRR register *********************/ /****************** Bit definition for GPIO_BRR register *********************/
#define GPIO_BRR_BR_0 (0x00000001U) #define GPIO_BRR_BR_0 (0x00000001U)
@ -2990,63 +3040,63 @@ typedef struct
/***************** Bit definition for RCC_APB2RSTR register ****************/ /***************** Bit definition for RCC_APB2RSTR register ****************/
#define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
#define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Pos (9U)
#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */
#define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Pos (11U)
#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */
#define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Pos (12U)
#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
#define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Pos (14U)
#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
#define RCC_APB2RSTR_TIM15RST_Pos (16U) #define RCC_APB2RSTR_TIM15RST_Pos (16U)
#define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */ #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */
#define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Pos (17U)
#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */
#define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */
#define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Pos (22U)
#define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */
/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ /*!< Old ADC1 reset bit definition maintained for legacy purpose */
#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
/***************** Bit definition for RCC_APB1RSTR register ****************/ /***************** Bit definition for RCC_APB1RSTR register ****************/
#define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Pos (1U)
#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
#define RCC_APB1RSTR_TIM6RST_Pos (4U) #define RCC_APB1RSTR_TIM6RST_Pos (4U)
#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
#define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Pos (8U)
#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */
#define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Pos (11U)
#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
#define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Pos (14U)
#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */
#define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Pos (17U)
#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
#define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Pos (21U)
#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
#define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Pos (22U)
#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
#define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Pos (28U)
#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
/****************** Bit definition for RCC_AHBENR register *****************/ /****************** Bit definition for RCC_AHBENR register *****************/
#define RCC_AHBENR_DMAEN_Pos (0U) #define RCC_AHBENR_DMAEN_Pos (0U)
@ -3220,19 +3270,19 @@ typedef struct
/******************* Bit definition for RCC_AHBRSTR register ***************/ /******************* Bit definition for RCC_AHBRSTR register ***************/
#define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Pos (17U)
#define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */
#define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Pos (18U)
#define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */
#define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Pos (19U)
#define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */
#define RCC_AHBRSTR_GPIODRST_Pos (20U) #define RCC_AHBRSTR_GPIODRST_Pos (20U)
#define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */ #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */
#define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Pos (22U)
#define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */
/******************* Bit definition for RCC_CFGR2 register *****************/ /******************* Bit definition for RCC_CFGR2 register *****************/
/*!< PREDIV configuration */ /*!< PREDIV configuration */
@ -3414,9 +3464,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -3448,6 +3498,11 @@ typedef struct
#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register *****************/ /******************** Bits definition for RTC_ISR register *****************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
@ -5323,6 +5378,9 @@ typedef struct
#define IS_TIM_REMAP_INSTANCE(INSTANCE)\ #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
((INSTANCE) == TIM14) ((INSTANCE) == TIM14)
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
((INSTANCE) == TIM1)
/******************** USART Instances : Synchronous mode **********************/ /******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2)) ((INSTANCE) == USART2))

6
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f0xx.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx.h * @file stm32f0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
@ -112,11 +110,11 @@
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V2.3.1 * @brief CMSIS Device version number V2.3.3
*/ */
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

1
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_clock.c
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@ -213,7 +213,6 @@ uint8_t SetSysClock_PLL_HSI(void)
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.HSI14State = RCC_HSI_OFF; RCC_OscInitStruct.HSI14State = RCC_HSI_OFF;
RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT;
RCC_OscInitStruct.HSI48State = RCC_HSI_ON;
RCC_OscInitStruct.LSIState = RCC_LSI_OFF; RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_stm32f0xx.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f0xx.h * @file system_stm32f0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.S
View File

@ -1,8 +1,6 @@
;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f031x6.s ;* File Name : startup_stm32f031x6.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V2.2.2
;* Date : 26-June-2015
;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain. ;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.S
View File

@ -1,8 +1,6 @@
;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f031x6.s ;* File Name : startup_stm32f031x6.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V2.2.2
;* Date : 26-June-2015
;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain. ;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP

40
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.S
View File

@ -2,9 +2,7 @@
****************************************************************************** ******************************************************************************
* @file startup_stm32f031x6.s * @file startup_stm32f031x6.s
* @author MCD Application Team * @author MCD Application Team
* @version V2.2.2 * @brief STM32F031x4/STM32F031x6 devices vector table for GCC toolchain.
* @date 26-June-2015
* @brief STM32F031x4/STM32F031x6 devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs: * This module performs:
* - Set the initial SP * - Set the initial SP
* - Set the initial PC == Reset_Handler, * - Set the initial PC == Reset_Handler,
@ -55,6 +53,10 @@ defined in linker script */
.word _sdata .word _sdata
/* end address for the .data section. defined in linker script */ /* end address for the .data section. defined in linker script */
.word _edata .word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.section .text.Reset_Handler .section .text.Reset_Handler
.weak Reset_Handler .weak Reset_Handler
@ -64,22 +66,36 @@ Reset_Handler:
mov sp, r0 /* set stack pointer */ mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */ /* Copy the data segment initializers from flash to SRAM */
movs r1, #0 ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit b LoopCopyDataInit
CopyDataInit: CopyDataInit:
ldr r3, =_sidata ldr r4, [r2, r3]
ldr r3, [r3, r1] str r4, [r0, r3]
str r3, [r0, r1] adds r3, r3, #4
adds r1, r1, #4
LoopCopyDataInit: LoopCopyDataInit:
ldr r0, =_sdata adds r4, r0, r3
ldr r3, =_edata cmp r4, r1
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/ /* Call the clock system intitialization function.*/
bl SystemInit bl SystemInit

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.S
View File

@ -1,8 +1,6 @@
;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f031x6.s ;* File Name : startup_stm32f031x6.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V2.2.2
;* Date : 26-June-2015
;* Description : STM32F031x4/STM32F031x6 devices vector table for EWARM toolchain. ;* Description : STM32F031x4/STM32F031x6 devices vector table for EWARM toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP
@ -15,8 +13,6 @@
;* priority is Privileged, and the Stack is set to Main. ;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************* ;*******************************************************************************
;* ;*
;* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
;*
;* Redistribution and use in source and binary forms, with or without modification, ;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met: ;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice, ;* 1. Redistributions of source code must retain the above copyright notice,

6
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h
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@ -45,11 +45,11 @@ extern "C" {
#define TIM_MST TIM2 #define TIM_MST TIM2
#define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_IRQ TIM2_IRQn
#define TIM_MST_RCC __TIM2_CLK_ENABLE() #define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE()
#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2()
#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer #define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

202
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f031x6.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f031x6.h * @file stm32f031x6.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices. * definitions and memory mapping for STM32F0xx devices.
@ -2359,56 +2357,108 @@ typedef struct
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
/****************** Bit definition for GPIO_AFRL register ********************/ /****************** Bit definition for GPIO_AFRL register ********************/
#define GPIO_AFRL_AFRL0_Pos (0U) #define GPIO_AFRL_AFSEL0_Pos (0U)
#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFRL1_Pos (4U) #define GPIO_AFRL_AFSEL1_Pos (4U)
#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFRL2_Pos (8U) #define GPIO_AFRL_AFSEL2_Pos (8U)
#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFRL3_Pos (12U) #define GPIO_AFRL_AFSEL3_Pos (12U)
#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFRL4_Pos (16U) #define GPIO_AFRL_AFSEL4_Pos (16U)
#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFRL5_Pos (20U) #define GPIO_AFRL_AFSEL5_Pos (20U)
#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFRL6_Pos (24U) #define GPIO_AFRL_AFSEL6_Pos (24U)
#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFRL7_Pos (28U) #define GPIO_AFRL_AFSEL7_Pos (28U)
#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
/* Legacy aliases */
#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos
#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos
#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos
#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos
#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos
#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos
#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos
#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos
#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
/****************** Bit definition for GPIO_AFRH register ********************/ /****************** Bit definition for GPIO_AFRH register ********************/
#define GPIO_AFRH_AFRH0_Pos (0U) #define GPIO_AFRH_AFSEL8_Pos (0U)
#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFRH1_Pos (4U) #define GPIO_AFRH_AFSEL9_Pos (4U)
#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFRH2_Pos (8U) #define GPIO_AFRH_AFSEL10_Pos (8U)
#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFRH3_Pos (12U) #define GPIO_AFRH_AFSEL11_Pos (12U)
#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFRH4_Pos (16U) #define GPIO_AFRH_AFSEL12_Pos (16U)
#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFRH5_Pos (20U) #define GPIO_AFRH_AFSEL13_Pos (20U)
#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFRH6_Pos (24U) #define GPIO_AFRH_AFSEL14_Pos (24U)
#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFRH7_Pos (28U) #define GPIO_AFRH_AFSEL15_Pos (28U)
#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
/* Legacy aliases */
#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos
#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos
#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos
#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos
#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos
#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos
#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos
#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos
#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
/****************** Bit definition for GPIO_BRR register *********************/ /****************** Bit definition for GPIO_BRR register *********************/
#define GPIO_BRR_BR_0 (0x00000001U) #define GPIO_BRR_BR_0 (0x00000001U)
@ -3094,51 +3144,51 @@ typedef struct
/***************** Bit definition for RCC_APB2RSTR register ****************/ /***************** Bit definition for RCC_APB2RSTR register ****************/
#define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
#define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Pos (9U)
#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */
#define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Pos (11U)
#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */
#define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Pos (12U)
#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
#define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Pos (14U)
#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
#define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Pos (17U)
#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */
#define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */
#define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Pos (22U)
#define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */
/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ /*!< Old ADC1 reset bit definition maintained for legacy purpose */
#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
/***************** Bit definition for RCC_APB1RSTR register ****************/ /***************** Bit definition for RCC_APB1RSTR register ****************/
#define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Pos (0U)
#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
#define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Pos (1U)
#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
#define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Pos (8U)
#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */
#define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Pos (11U)
#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
#define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Pos (21U)
#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
#define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Pos (28U)
#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
/****************** Bit definition for RCC_AHBENR register *****************/ /****************** Bit definition for RCC_AHBENR register *****************/
#define RCC_AHBENR_DMAEN_Pos (0U) #define RCC_AHBENR_DMAEN_Pos (0U)
@ -3297,16 +3347,16 @@ typedef struct
/******************* Bit definition for RCC_AHBRSTR register ***************/ /******************* Bit definition for RCC_AHBRSTR register ***************/
#define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Pos (17U)
#define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */
#define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Pos (18U)
#define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */
#define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Pos (19U)
#define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */
#define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Pos (22U)
#define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */
/******************* Bit definition for RCC_CFGR2 register *****************/ /******************* Bit definition for RCC_CFGR2 register *****************/
/*!< PREDIV configuration */ /*!< PREDIV configuration */
@ -3489,9 +3539,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -3523,6 +3573,11 @@ typedef struct
#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register *****************/ /******************** Bits definition for RTC_ISR register *****************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
@ -5564,6 +5619,9 @@ typedef struct
#define IS_TIM_REMAP_INSTANCE(INSTANCE)\ #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
((INSTANCE) == TIM14) ((INSTANCE) == TIM14)
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
((INSTANCE) == TIM1)
/*********************** UART Instances : IRDA mode ***************************/ /*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1) #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)

6
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f0xx.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx.h * @file stm32f0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
@ -112,11 +110,11 @@
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V2.3.1 * @brief CMSIS Device version number V2.3.3
*/ */
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

1
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_clock.c
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@ -213,7 +213,6 @@ uint8_t SetSysClock_PLL_HSI(void)
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.HSI14State = RCC_HSI_OFF; RCC_OscInitStruct.HSI14State = RCC_HSI_OFF;
RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT;
RCC_OscInitStruct.HSI48State = RCC_HSI_ON;
RCC_OscInitStruct.LSIState = RCC_LSI_OFF; RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_stm32f0xx.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f0xx.h * @file system_stm32f0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.S
View File

@ -1,8 +1,6 @@
;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f042x6.s ;* File Name : startup_stm32f042x6.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V2.2.2
;* Date : 26-June-2015
;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain. ;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.S
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@ -1,8 +1,6 @@
;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f042x6.s ;* File Name : startup_stm32f042x6.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V2.2.2
;* Date : 26-June-2015
;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain. ;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP

42
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.S
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@ -2,9 +2,7 @@
****************************************************************************** ******************************************************************************
* @file startup_stm32f042x6.s * @file startup_stm32f042x6.s
* @author MCD Application Team * @author MCD Application Team
* @version V2.2.2 * @brief STM32F042x4/STM32F042x6 devices vector table for GCC toolchain.
* @date 26-June-2015
* @brief STM32F042x4/STM32F042x6 devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs: * This module performs:
* - Set the initial SP * - Set the initial SP
* - Set the initial PC == Reset_Handler, * - Set the initial PC == Reset_Handler,
@ -55,6 +53,10 @@ defined in linker script */
.word _sdata .word _sdata
/* end address for the .data section. defined in linker script */ /* end address for the .data section. defined in linker script */
.word _edata .word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/** /**
* @brief This is the code that gets called when the processor first * @brief This is the code that gets called when the processor first
@ -78,8 +80,6 @@ Reset_Handler:
LDR R1, [R0] LDR R1, [R0]
LSRS R1, R1, #24 LSRS R1, R1, #24
LDR R2,=0x1F LDR R2,=0x1F
MOVS R1, #0
MOVS R2, #1
CMP R1, R2 CMP R1, R2
BNE ApplicationStart BNE ApplicationStart
@ -96,22 +96,36 @@ Reset_Handler:
ApplicationStart: ApplicationStart:
/* Copy the data segment initializers from flash to SRAM */ /* Copy the data segment initializers from flash to SRAM */
movs r1, #0 ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit b LoopCopyDataInit
CopyDataInit: CopyDataInit:
ldr r3, =_sidata ldr r4, [r2, r3]
ldr r3, [r3, r1] str r4, [r0, r3]
str r3, [r0, r1] adds r3, r3, #4
adds r1, r1, #4
LoopCopyDataInit: LoopCopyDataInit:
ldr r0, =_sdata adds r4, r0, r3
ldr r3, =_edata cmp r4, r1
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/ /* Call the clock system intitialization function.*/
bl SystemInit bl SystemInit

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.S
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@ -1,8 +1,6 @@
;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f042x6.s ;* File Name : startup_stm32f042x6.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V2.2.2
;* Date : 26-June-2015
;* Description : STM32F042x4/STM32F042x6 devices vector table for EWARM toolchain. ;* Description : STM32F042x4/STM32F042x6 devices vector table for EWARM toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP
@ -15,8 +13,6 @@
;* priority is Privileged, and the Stack is set to Main. ;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************* ;*******************************************************************************
;* ;*
;* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
;*
;* Redistribution and use in source and binary forms, with or without modification, ;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met: ;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice, ;* 1. Redistributions of source code must retain the above copyright notice,

6
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h
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@ -45,11 +45,11 @@ extern "C" {
#define TIM_MST TIM2 #define TIM_MST TIM2
#define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_IRQ TIM2_IRQn
#define TIM_MST_RCC __TIM2_CLK_ENABLE() #define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE()
#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2()
#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer #define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

218
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f042x6.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f042x6.h * @file stm32f042x6.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices. * definitions and memory mapping for STM32F0xx devices.
@ -6496,56 +6494,108 @@ typedef struct
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
/****************** Bit definition for GPIO_AFRL register ********************/ /****************** Bit definition for GPIO_AFRL register ********************/
#define GPIO_AFRL_AFRL0_Pos (0U) #define GPIO_AFRL_AFSEL0_Pos (0U)
#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFRL1_Pos (4U) #define GPIO_AFRL_AFSEL1_Pos (4U)
#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFRL2_Pos (8U) #define GPIO_AFRL_AFSEL2_Pos (8U)
#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFRL3_Pos (12U) #define GPIO_AFRL_AFSEL3_Pos (12U)
#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFRL4_Pos (16U) #define GPIO_AFRL_AFSEL4_Pos (16U)
#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFRL5_Pos (20U) #define GPIO_AFRL_AFSEL5_Pos (20U)
#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFRL6_Pos (24U) #define GPIO_AFRL_AFSEL6_Pos (24U)
#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFRL7_Pos (28U) #define GPIO_AFRL_AFSEL7_Pos (28U)
#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
/* Legacy aliases */
#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos
#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos
#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos
#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos
#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos
#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos
#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos
#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos
#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
/****************** Bit definition for GPIO_AFRH register ********************/ /****************** Bit definition for GPIO_AFRH register ********************/
#define GPIO_AFRH_AFRH0_Pos (0U) #define GPIO_AFRH_AFSEL8_Pos (0U)
#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFRH1_Pos (4U) #define GPIO_AFRH_AFSEL9_Pos (4U)
#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFRH2_Pos (8U) #define GPIO_AFRH_AFSEL10_Pos (8U)
#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFRH3_Pos (12U) #define GPIO_AFRH_AFSEL11_Pos (12U)
#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFRH4_Pos (16U) #define GPIO_AFRH_AFSEL12_Pos (16U)
#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFRH5_Pos (20U) #define GPIO_AFRH_AFSEL13_Pos (20U)
#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFRH6_Pos (24U) #define GPIO_AFRH_AFSEL14_Pos (24U)
#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFRH7_Pos (28U) #define GPIO_AFRH_AFSEL15_Pos (28U)
#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
/* Legacy aliases */
#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos
#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos
#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos
#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos
#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos
#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos
#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos
#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos
#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
/****************** Bit definition for GPIO_BRR register *********************/ /****************** Bit definition for GPIO_BRR register *********************/
#define GPIO_BRR_BR_0 (0x00000001U) #define GPIO_BRR_BR_0 (0x00000001U)
@ -7264,69 +7314,69 @@ typedef struct
/***************** Bit definition for RCC_APB2RSTR register ****************/ /***************** Bit definition for RCC_APB2RSTR register ****************/
#define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
#define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Pos (9U)
#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */
#define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Pos (11U)
#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */
#define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Pos (12U)
#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
#define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Pos (14U)
#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
#define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Pos (17U)
#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */
#define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */
#define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Pos (22U)
#define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */
/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ /*!< Old ADC1 reset bit definition maintained for legacy purpose */
#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
/***************** Bit definition for RCC_APB1RSTR register ****************/ /***************** Bit definition for RCC_APB1RSTR register ****************/
#define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Pos (0U)
#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
#define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Pos (1U)
#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
#define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Pos (8U)
#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */
#define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Pos (11U)
#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
#define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Pos (14U)
#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */
#define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Pos (17U)
#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
#define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Pos (21U)
#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
#define RCC_APB1RSTR_USBRST_Pos (23U) #define RCC_APB1RSTR_USBRST_Pos (23U)
#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB clock reset */ #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */
#define RCC_APB1RSTR_CANRST_Pos (25U) #define RCC_APB1RSTR_CANRST_Pos (25U)
#define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */ #define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */
#define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN clock reset */ #define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN reset */
#define RCC_APB1RSTR_CRSRST_Pos (27U) #define RCC_APB1RSTR_CRSRST_Pos (27U)
#define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */ #define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS clock reset */ #define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS reset */
#define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Pos (28U)
#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
#define RCC_APB1RSTR_CECRST_Pos (30U) #define RCC_APB1RSTR_CECRST_Pos (30U)
#define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */ #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */
#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC clock reset */ #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC reset */
/****************** Bit definition for RCC_AHBENR register *****************/ /****************** Bit definition for RCC_AHBENR register *****************/
#define RCC_AHBENR_DMAEN_Pos (0U) #define RCC_AHBENR_DMAEN_Pos (0U)
@ -7506,22 +7556,22 @@ typedef struct
/******************* Bit definition for RCC_AHBRSTR register ***************/ /******************* Bit definition for RCC_AHBRSTR register ***************/
#define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Pos (17U)
#define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */
#define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Pos (18U)
#define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */
#define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Pos (19U)
#define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */
#define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Pos (22U)
#define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */
#define RCC_AHBRSTR_TSCRST_Pos (24U) #define RCC_AHBRSTR_TSCRST_Pos (24U)
#define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */ #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS clock reset */ #define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS reset */
/* Old Bit definition maintained for legacy purpose */ /* Old Bit definition maintained for legacy purpose */
#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */ #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS reset */
/******************* Bit definition for RCC_CFGR2 register *****************/ /******************* Bit definition for RCC_CFGR2 register *****************/
/*!< PREDIV configuration */ /*!< PREDIV configuration */
@ -7733,9 +7783,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -7767,6 +7817,11 @@ typedef struct
#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register *****************/ /******************** Bits definition for RTC_ISR register *****************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
@ -10528,6 +10583,9 @@ typedef struct
(((INSTANCE) == TIM1) || \ (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM14)) ((INSTANCE) == TIM14))
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
((INSTANCE) == TIM1)
/****************************** TSC Instances *********************************/ /****************************** TSC Instances *********************************/
#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)

6
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f0xx.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx.h * @file stm32f0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
@ -112,11 +110,11 @@
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V2.3.1 * @brief CMSIS Device version number V2.3.3
*/ */
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/system_stm32f0xx.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f0xx.h * @file system_stm32f0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.S
View File

@ -1,8 +1,6 @@
;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f070xb.s ;* File Name : startup_stm32f070xb.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V2.2.0
;* Date : 05-December-2014
;* Description : STM32F070x8/STM32F070xB devices vector table for MDK-ARM toolchain. ;* Description : STM32F070x8/STM32F070xB devices vector table for MDK-ARM toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_STD/startup_stm32f070xb.S
View File

@ -1,8 +1,6 @@
;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f070xb.s ;* File Name : startup_stm32f070xb.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V2.2.0
;* Date : 05-December-2014
;* Description : STM32F070x8/STM32F070xB devices vector table for MDK-ARM toolchain. ;* Description : STM32F070x8/STM32F070xB devices vector table for MDK-ARM toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP

42
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f070xb.S
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@ -2,9 +2,7 @@
****************************************************************************** ******************************************************************************
* @file startup_stm32f070xb.s * @file startup_stm32f070xb.s
* @author MCD Application Team * @author MCD Application Team
* @version V2.2.0 * @brief STM32F070xb/STM32F070x8 devices vector table for GCC toolchain.
* @date 05-December-2014
* @brief STM32F070xb/STM32F070x8 devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs: * This module performs:
* - Set the initial SP * - Set the initial SP
* - Set the initial PC == Reset_Handler, * - Set the initial PC == Reset_Handler,
@ -55,7 +53,10 @@ defined in linker script */
.word _sdata .word _sdata
/* end address for the .data section. defined in linker script */ /* end address for the .data section. defined in linker script */
.word _edata .word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.section .text.Reset_Handler .section .text.Reset_Handler
.weak Reset_Handler .weak Reset_Handler
@ -65,21 +66,6 @@ Reset_Handler:
mov sp, r0 /* set stack pointer */ mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */ /* Copy the data segment initializers from flash to SRAM */
// Load from _sidata -> _sdata through _edata
// _sidata has a vma = lma in flash at the end of .text
// _sdata has a lma in flash but a vma of ram, so here we move it from where
// it was loaded (lma) into where it will be accessed (vma).
// Register Schema:
// r0 = _sdata, r1 = _edata, r2 = _sidata
// r3 = index (goes from 0 -> _sdata - _edata)
// r4 = temp var for *(_sidata + r3) or (_sdata + r3)
// This is all equivalent to this C:
// int index = 0;
// extern uint32_t *_sdata, *_sidata;
// while (_sdata + index < _edata) {
// *_sdata[index] = *_sidata[index];
// index += 1;
// }
ldr r0, =_sdata ldr r0, =_sdata
ldr r1, =_edata ldr r1, =_edata
ldr r2, =_sidata ldr r2, =_sidata
@ -92,16 +78,28 @@ CopyDataInit:
adds r3, r3, #4 adds r3, r3, #4
LoopCopyDataInit: LoopCopyDataInit:
// while (_sdata + r3 < _edata)
adds r4, r0, r3 adds r4, r0, r3
// if (r4 < r1) branch to CopyDataInit
cmp r4, r1 cmp r4, r1
bcc CopyDataInit bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/ /* Call the clock system intitialization function.*/
bl SystemInit bl SystemInit
/* Call static constructors */
// bl __libc_init_array
/* Call the application's entry point.*/ /* Call the application's entry point.*/
// bl main // bl main
bl _start bl _start

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_IAR/startup_stm32f070xb.S
View File

@ -1,8 +1,6 @@
;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f070xb.s ;* File Name : startup_stm32f070xb.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V2.2.0
;* Date : 05-December-2014
;* Description : STM32F070xB devices vector table for EWARM toolchain. ;* Description : STM32F070xB devices vector table for EWARM toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP
@ -15,8 +13,6 @@
;* priority is Privileged, and the Stack is set to Main. ;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************* ;*******************************************************************************
;* ;*
;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
;*
;* Redistribution and use in source and binary forms, with or without modification, ;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met: ;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice, ;* 1. Redistributions of source code must retain the above copyright notice,

6
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h
View File

@ -46,11 +46,11 @@
#define TIM_MST TIM1 #define TIM_MST TIM1
#define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn #define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn
#define TIM_MST_OC_IRQ TIM1_CC_IRQn #define TIM_MST_OC_IRQ TIM1_CC_IRQn
#define TIM_MST_RCC __TIM1_CLK_ENABLE() #define TIM_MST_RCC __HAL_RCC_TIM1_CLK_ENABLE()
#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM1() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM1()
#define TIM_MST_RESET_ON __TIM1_FORCE_RESET() #define TIM_MST_RESET_ON __HAL_RCC_TIM1_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM1_RELEASE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM1_RELEASE_RESET()
#define TIM_MST_16BIT 1 // 1=16-bit timer, 0=32-bit timer #define TIM_MST_16BIT 1 // 1=16-bit timer, 0=32-bit timer

220
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f070xb.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f070xb.h * @file stm32f070xb.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices. * definitions and memory mapping for STM32F0xx devices.
@ -2396,56 +2394,108 @@ typedef struct
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
/****************** Bit definition for GPIO_AFRL register ********************/ /****************** Bit definition for GPIO_AFRL register ********************/
#define GPIO_AFRL_AFRL0_Pos (0U) #define GPIO_AFRL_AFSEL0_Pos (0U)
#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFRL1_Pos (4U) #define GPIO_AFRL_AFSEL1_Pos (4U)
#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFRL2_Pos (8U) #define GPIO_AFRL_AFSEL2_Pos (8U)
#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFRL3_Pos (12U) #define GPIO_AFRL_AFSEL3_Pos (12U)
#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFRL4_Pos (16U) #define GPIO_AFRL_AFSEL4_Pos (16U)
#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFRL5_Pos (20U) #define GPIO_AFRL_AFSEL5_Pos (20U)
#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFRL6_Pos (24U) #define GPIO_AFRL_AFSEL6_Pos (24U)
#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFRL7_Pos (28U) #define GPIO_AFRL_AFSEL7_Pos (28U)
#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
/* Legacy aliases */
#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos
#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos
#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos
#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos
#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos
#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos
#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos
#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos
#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
/****************** Bit definition for GPIO_AFRH register ********************/ /****************** Bit definition for GPIO_AFRH register ********************/
#define GPIO_AFRH_AFRH0_Pos (0U) #define GPIO_AFRH_AFSEL8_Pos (0U)
#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFRH1_Pos (4U) #define GPIO_AFRH_AFSEL9_Pos (4U)
#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFRH2_Pos (8U) #define GPIO_AFRH_AFSEL10_Pos (8U)
#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFRH3_Pos (12U) #define GPIO_AFRH_AFSEL11_Pos (12U)
#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFRH4_Pos (16U) #define GPIO_AFRH_AFSEL12_Pos (16U)
#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFRH5_Pos (20U) #define GPIO_AFRH_AFSEL13_Pos (20U)
#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFRH6_Pos (24U) #define GPIO_AFRH_AFSEL14_Pos (24U)
#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFRH7_Pos (28U) #define GPIO_AFRH_AFSEL15_Pos (28U)
#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
/* Legacy aliases */
#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos
#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos
#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos
#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos
#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos
#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos
#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos
#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos
#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
/****************** Bit definition for GPIO_BRR register *********************/ /****************** Bit definition for GPIO_BRR register *********************/
#define GPIO_BRR_BR_0 (0x00000001U) #define GPIO_BRR_BR_0 (0x00000001U)
@ -3120,75 +3170,75 @@ typedef struct
/***************** Bit definition for RCC_APB2RSTR register ****************/ /***************** Bit definition for RCC_APB2RSTR register ****************/
#define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
#define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Pos (9U)
#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */
#define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Pos (11U)
#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */
#define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Pos (12U)
#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
#define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Pos (14U)
#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
#define RCC_APB2RSTR_TIM15RST_Pos (16U) #define RCC_APB2RSTR_TIM15RST_Pos (16U)
#define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */ #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */
#define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Pos (17U)
#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */
#define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */
#define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Pos (22U)
#define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */
/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ /*!< Old ADC1 reset bit definition maintained for legacy purpose */
#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
/***************** Bit definition for RCC_APB1RSTR register ****************/ /***************** Bit definition for RCC_APB1RSTR register ****************/
#define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Pos (1U)
#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
#define RCC_APB1RSTR_TIM6RST_Pos (4U) #define RCC_APB1RSTR_TIM6RST_Pos (4U)
#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
#define RCC_APB1RSTR_TIM7RST_Pos (5U) #define RCC_APB1RSTR_TIM7RST_Pos (5U)
#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 clock reset */ #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
#define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Pos (8U)
#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */
#define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Pos (11U)
#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
#define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Pos (14U)
#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */
#define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Pos (17U)
#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
#define RCC_APB1RSTR_USART3RST_Pos (18U) #define RCC_APB1RSTR_USART3RST_Pos (18U)
#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 clock reset */ #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
#define RCC_APB1RSTR_USART4RST_Pos (19U) #define RCC_APB1RSTR_USART4RST_Pos (19U)
#define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */ #define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */
#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 clock reset */ #define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 reset */
#define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Pos (21U)
#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
#define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Pos (22U)
#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
#define RCC_APB1RSTR_USBRST_Pos (23U) #define RCC_APB1RSTR_USBRST_Pos (23U)
#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB clock reset */ #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */
#define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Pos (28U)
#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
/****************** Bit definition for RCC_AHBENR register *****************/ /****************** Bit definition for RCC_AHBENR register *****************/
#define RCC_AHBENR_DMAEN_Pos (0U) #define RCC_AHBENR_DMAEN_Pos (0U)
@ -3373,19 +3423,19 @@ typedef struct
/******************* Bit definition for RCC_AHBRSTR register ***************/ /******************* Bit definition for RCC_AHBRSTR register ***************/
#define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Pos (17U)
#define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */
#define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Pos (18U)
#define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */
#define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Pos (19U)
#define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */
#define RCC_AHBRSTR_GPIODRST_Pos (20U) #define RCC_AHBRSTR_GPIODRST_Pos (20U)
#define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */ #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */
#define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Pos (22U)
#define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */
/******************* Bit definition for RCC_CFGR2 register *****************/ /******************* Bit definition for RCC_CFGR2 register *****************/
/*!< PREDIV configuration */ /*!< PREDIV configuration */
@ -3577,9 +3627,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -3623,6 +3673,11 @@ typedef struct
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register *****************/ /******************** Bits definition for RTC_ISR register *****************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
@ -5669,6 +5724,9 @@ typedef struct
#define IS_TIM_REMAP_INSTANCE(INSTANCE)\ #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
((INSTANCE) == TIM14) ((INSTANCE) == TIM14)
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
((INSTANCE) == TIM1)
/******************** USART Instances : Synchronous mode **********************/ /******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \ ((INSTANCE) == USART2) || \

6
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f0xx.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx.h * @file stm32f0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
@ -112,11 +110,11 @@
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V2.3.1 * @brief CMSIS Device version number V2.3.3
*/ */
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

1
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_clock.c
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@ -216,7 +216,6 @@ uint8_t SetSysClock_PLL_HSI(void)
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.HSI14State = RCC_HSI_OFF; RCC_OscInitStruct.HSI14State = RCC_HSI_OFF;
RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT;
RCC_OscInitStruct.HSI48State = RCC_HSI_ON;
RCC_OscInitStruct.LSIState = RCC_LSI_OFF; RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_stm32f0xx.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f0xx.h * @file system_stm32f0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f072xb.S
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@ -1,8 +1,6 @@
;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f072xb.s ;* File Name : startup_stm32f072xb.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V2.0.0
;* Date : 20-May-2014
;* Description : STM32F072x8/STM32F072xB devices vector table for MDK-ARM_MICRO toolchain. ;* Description : STM32F072x8/STM32F072xB devices vector table for MDK-ARM_MICRO toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_STD/startup_stm32f072xb.S
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@ -1,8 +1,6 @@
;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f072xb.s ;* File Name : startup_stm32f072xb.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V2.0.0
;* Date : 20-May-2014
;* Description : STM32F072x8/STM32F072xB devices vector table for MDK-ARM_STD toolchain. ;* Description : STM32F072x8/STM32F072xB devices vector table for MDK-ARM_STD toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP

40
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.S
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@ -2,9 +2,7 @@
****************************************************************************** ******************************************************************************
* @file startup_stm32f072xb.s * @file startup_stm32f072xb.s
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @brief STM32F072x8/STM32F072xB devices vector table for GCC toolchain.
* @date 03-Oct-2014
* @brief STM32F072x8/STM32F072xB devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs: * This module performs:
* - Set the initial SP * - Set the initial SP
* - Set the initial PC == Reset_Handler, * - Set the initial PC == Reset_Handler,
@ -55,6 +53,10 @@ defined in linker script */
.word _sdata .word _sdata
/* end address for the .data section. defined in linker script */ /* end address for the .data section. defined in linker script */
.word _edata .word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.section .text.Reset_Handler .section .text.Reset_Handler
.weak Reset_Handler .weak Reset_Handler
@ -64,22 +66,36 @@ Reset_Handler:
mov sp, r0 /* set stack pointer */ mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */ /* Copy the data segment initializers from flash to SRAM */
movs r1, #0 ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit b LoopCopyDataInit
CopyDataInit: CopyDataInit:
ldr r3, =_sidata ldr r4, [r2, r3]
ldr r3, [r3, r1] str r4, [r0, r3]
str r3, [r0, r1] adds r3, r3, #4
adds r1, r1, #4
LoopCopyDataInit: LoopCopyDataInit:
ldr r0, =_sdata adds r4, r0, r3
ldr r3, =_edata cmp r4, r1
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/ /* Call the clock system intitialization function.*/
bl SystemInit bl SystemInit
/* Call static constructors */ /* Call static constructors */

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_IAR/startup_stm32f072xb.S
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@ -1,8 +1,6 @@
;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f072xb.s ;* File Name : startup_stm32f072xb.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V2.1.0
;* Date : 03-Oct-2014
;* Description : STM32F072x8/STM32F072xB devices vector table for EWARM toolchain. ;* Description : STM32F072x8/STM32F072xB devices vector table for EWARM toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP
@ -15,8 +13,6 @@
;* priority is Privileged, and the Stack is set to Main. ;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************* ;*******************************************************************************
;* ;*
;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
;*
;* Redistribution and use in source and binary forms, with or without modification, ;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met: ;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice, ;* 1. Redistributions of source code must retain the above copyright notice,

6
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h
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@ -45,11 +45,11 @@
#define TIM_MST TIM2 #define TIM_MST TIM2
#define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_IRQ TIM2_IRQn
#define TIM_MST_RCC __TIM2_CLK_ENABLE() #define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE()
#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2()
#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer #define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

236
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f072xb.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f072xb.h * @file stm32f072xb.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices. * definitions and memory mapping for STM32F0xx devices.
@ -6934,56 +6932,108 @@ typedef struct
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
/****************** Bit definition for GPIO_AFRL register ********************/ /****************** Bit definition for GPIO_AFRL register ********************/
#define GPIO_AFRL_AFRL0_Pos (0U) #define GPIO_AFRL_AFSEL0_Pos (0U)
#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFRL1_Pos (4U) #define GPIO_AFRL_AFSEL1_Pos (4U)
#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFRL2_Pos (8U) #define GPIO_AFRL_AFSEL2_Pos (8U)
#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFRL3_Pos (12U) #define GPIO_AFRL_AFSEL3_Pos (12U)
#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFRL4_Pos (16U) #define GPIO_AFRL_AFSEL4_Pos (16U)
#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFRL5_Pos (20U) #define GPIO_AFRL_AFSEL5_Pos (20U)
#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFRL6_Pos (24U) #define GPIO_AFRL_AFSEL6_Pos (24U)
#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFRL7_Pos (28U) #define GPIO_AFRL_AFSEL7_Pos (28U)
#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
/* Legacy aliases */
#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos
#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos
#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos
#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos
#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos
#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos
#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos
#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos
#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
/****************** Bit definition for GPIO_AFRH register ********************/ /****************** Bit definition for GPIO_AFRH register ********************/
#define GPIO_AFRH_AFRH0_Pos (0U) #define GPIO_AFRH_AFSEL8_Pos (0U)
#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFRH1_Pos (4U) #define GPIO_AFRH_AFSEL9_Pos (4U)
#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFRH2_Pos (8U) #define GPIO_AFRH_AFSEL10_Pos (8U)
#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFRH3_Pos (12U) #define GPIO_AFRH_AFSEL11_Pos (12U)
#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFRH4_Pos (16U) #define GPIO_AFRH_AFSEL12_Pos (16U)
#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFRH5_Pos (20U) #define GPIO_AFRH_AFSEL13_Pos (20U)
#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFRH6_Pos (24U) #define GPIO_AFRH_AFSEL14_Pos (24U)
#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFRH7_Pos (28U) #define GPIO_AFRH_AFSEL15_Pos (28U)
#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
/* Legacy aliases */
#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos
#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos
#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos
#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos
#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos
#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos
#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos
#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos
#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
/****************** Bit definition for GPIO_BRR register *********************/ /****************** Bit definition for GPIO_BRR register *********************/
#define GPIO_BRR_BR_0 (0x00000001U) #define GPIO_BRR_BR_0 (0x00000001U)
@ -7711,90 +7761,90 @@ typedef struct
/***************** Bit definition for RCC_APB2RSTR register ****************/ /***************** Bit definition for RCC_APB2RSTR register ****************/
#define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
#define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Pos (9U)
#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */
#define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Pos (11U)
#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */
#define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Pos (12U)
#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
#define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Pos (14U)
#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
#define RCC_APB2RSTR_TIM15RST_Pos (16U) #define RCC_APB2RSTR_TIM15RST_Pos (16U)
#define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */ #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */
#define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Pos (17U)
#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */
#define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */
#define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Pos (22U)
#define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */
/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ /*!< Old ADC1 reset bit definition maintained for legacy purpose */
#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
/***************** Bit definition for RCC_APB1RSTR register ****************/ /***************** Bit definition for RCC_APB1RSTR register ****************/
#define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Pos (0U)
#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
#define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Pos (1U)
#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
#define RCC_APB1RSTR_TIM6RST_Pos (4U) #define RCC_APB1RSTR_TIM6RST_Pos (4U)
#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
#define RCC_APB1RSTR_TIM7RST_Pos (5U) #define RCC_APB1RSTR_TIM7RST_Pos (5U)
#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 clock reset */ #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
#define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Pos (8U)
#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */
#define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Pos (11U)
#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
#define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Pos (14U)
#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */
#define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Pos (17U)
#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
#define RCC_APB1RSTR_USART3RST_Pos (18U) #define RCC_APB1RSTR_USART3RST_Pos (18U)
#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 clock reset */ #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
#define RCC_APB1RSTR_USART4RST_Pos (19U) #define RCC_APB1RSTR_USART4RST_Pos (19U)
#define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */ #define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */
#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 clock reset */ #define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 reset */
#define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Pos (21U)
#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
#define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Pos (22U)
#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
#define RCC_APB1RSTR_USBRST_Pos (23U) #define RCC_APB1RSTR_USBRST_Pos (23U)
#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB clock reset */ #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */
#define RCC_APB1RSTR_CANRST_Pos (25U) #define RCC_APB1RSTR_CANRST_Pos (25U)
#define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */ #define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */
#define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN clock reset */ #define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN reset */
#define RCC_APB1RSTR_CRSRST_Pos (27U) #define RCC_APB1RSTR_CRSRST_Pos (27U)
#define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */ #define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS clock reset */ #define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS reset */
#define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Pos (28U)
#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
#define RCC_APB1RSTR_DACRST_Pos (29U) #define RCC_APB1RSTR_DACRST_Pos (29U)
#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */ #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC reset */
#define RCC_APB1RSTR_CECRST_Pos (30U) #define RCC_APB1RSTR_CECRST_Pos (30U)
#define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */ #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */
#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC clock reset */ #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC reset */
/****************** Bit definition for RCC_AHBENR register *****************/ /****************** Bit definition for RCC_AHBENR register *****************/
#define RCC_AHBENR_DMAEN_Pos (0U) #define RCC_AHBENR_DMAEN_Pos (0U)
@ -8001,28 +8051,28 @@ typedef struct
/******************* Bit definition for RCC_AHBRSTR register ***************/ /******************* Bit definition for RCC_AHBRSTR register ***************/
#define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Pos (17U)
#define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */
#define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Pos (18U)
#define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */
#define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Pos (19U)
#define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */
#define RCC_AHBRSTR_GPIODRST_Pos (20U) #define RCC_AHBRSTR_GPIODRST_Pos (20U)
#define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */ #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */
#define RCC_AHBRSTR_GPIOERST_Pos (21U) #define RCC_AHBRSTR_GPIOERST_Pos (21U)
#define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */ #define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */
#define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIOE clock reset */ #define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIOE reset */
#define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Pos (22U)
#define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */
#define RCC_AHBRSTR_TSCRST_Pos (24U) #define RCC_AHBRSTR_TSCRST_Pos (24U)
#define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */ #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS clock reset */ #define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS reset */
/* Old Bit definition maintained for legacy purpose */ /* Old Bit definition maintained for legacy purpose */
#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */ #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS reset */
/******************* Bit definition for RCC_CFGR2 register *****************/ /******************* Bit definition for RCC_CFGR2 register *****************/
/*!< PREDIV configuration */ /*!< PREDIV configuration */
@ -8248,9 +8298,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -8294,6 +8344,11 @@ typedef struct
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register *****************/ /******************** Bits definition for RTC_ISR register *****************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
@ -11132,6 +11187,9 @@ typedef struct
#define IS_TIM_REMAP_INSTANCE(INSTANCE)\ #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
((INSTANCE) == TIM14) ((INSTANCE) == TIM14)
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
((INSTANCE) == TIM1)
/****************************** TSC Instances *********************************/ /****************************** TSC Instances *********************************/
#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)

6
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f0xx.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx.h * @file stm32f0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
@ -112,11 +110,11 @@
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V2.3.1 * @brief CMSIS Device version number V2.3.3
*/ */
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/system_stm32f0xx.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f0xx.h * @file system_stm32f0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_MICRO/startup_stm32f091rc.S → targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_MICRO/startup_stm32f091xc.S
View File

@ -1,8 +1,6 @@
;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f091xc.s ;* File Name : startup_stm32f091xc.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V2.1.0
;* Date : 03-Oct-2014
;* Description : STM32F091xc/STM32F098xc devices vector table for MDK-ARM_MICRO toolchain. ;* Description : STM32F091xc/STM32F098xc devices vector table for MDK-ARM_MICRO toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_STD/startup_stm32f091rc.S → targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_STD/startup_stm32f091xc.S
View File

@ -1,8 +1,6 @@
;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f091xc.s ;* File Name : startup_stm32f091xc.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V2.1.0
;* Date : 03-Oct-2014
;* Description : STM32F091xc/STM32F098xc devices vector table for MDK-ARM_STD toolchain. ;* Description : STM32F091xc/STM32F098xc devices vector table for MDK-ARM_STD toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP

40
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_GCC_ARM/startup_stm32f091xc.S
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@ -2,9 +2,7 @@
****************************************************************************** ******************************************************************************
* @file startup_stm32f091xc.s * @file startup_stm32f091xc.s
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @brief STM32F091xC devices vector table for GCC toolchain.
* @date 03-Oct-2014
* @brief STM32F091xC devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs: * This module performs:
* - Set the initial SP * - Set the initial SP
* - Set the initial PC == Reset_Handler, * - Set the initial PC == Reset_Handler,
@ -55,6 +53,10 @@ defined in linker script */
.word _sdata .word _sdata
/* end address for the .data section. defined in linker script */ /* end address for the .data section. defined in linker script */
.word _edata .word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.section .text.Reset_Handler .section .text.Reset_Handler
.weak Reset_Handler .weak Reset_Handler
@ -64,22 +66,36 @@ Reset_Handler:
mov sp, r0 /* set stack pointer */ mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */ /* Copy the data segment initializers from flash to SRAM */
movs r1, #0 ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit b LoopCopyDataInit
CopyDataInit: CopyDataInit:
ldr r3, =_sidata ldr r4, [r2, r3]
ldr r3, [r3, r1] str r4, [r0, r3]
str r3, [r0, r1] adds r3, r3, #4
adds r1, r1, #4
LoopCopyDataInit: LoopCopyDataInit:
ldr r0, =_sdata adds r4, r0, r3
ldr r3, =_edata cmp r4, r1
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/ /* Call the clock system intitialization function.*/
bl SystemInit bl SystemInit
/* Call static constructors */ /* Call static constructors */

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_IAR/startup_stm32f091xc.S
View File

@ -1,8 +1,6 @@
;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f091xc.s ;* File Name : startup_stm32f091xc.s
;* Author : MCD Application Team ;* Author : MCD Application Team
;* Version : V2.1.0
;* Date : 03-Oct-2014
;* Description : STM32F091xc/STM32F098xc devices vector table for EWARM toolchain. ;* Description : STM32F091xc/STM32F098xc devices vector table for EWARM toolchain.
;* This module performs: ;* This module performs:
;* - Set the initial SP ;* - Set the initial SP
@ -15,8 +13,6 @@
;* priority is Privileged, and the Stack is set to Main. ;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************* ;*******************************************************************************
;* ;*
;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
;*
;* Redistribution and use in source and binary forms, with or without modification, ;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met: ;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice, ;* 1. Redistributions of source code must retain the above copyright notice,

6
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h
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@ -45,11 +45,11 @@
#define TIM_MST TIM2 #define TIM_MST TIM2
#define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_IRQ TIM2_IRQn
#define TIM_MST_RCC __TIM2_CLK_ENABLE() #define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE()
#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2()
#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET()
#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer #define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer

242
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f091xc.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f091xc.h * @file stm32f091xc.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits * This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices. * definitions and memory mapping for STM32F0xx devices.
@ -7405,56 +7403,108 @@ typedef struct
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
/****************** Bit definition for GPIO_AFRL register ********************/ /****************** Bit definition for GPIO_AFRL register ********************/
#define GPIO_AFRL_AFRL0_Pos (0U) #define GPIO_AFRL_AFSEL0_Pos (0U)
#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFRL1_Pos (4U) #define GPIO_AFRL_AFSEL1_Pos (4U)
#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFRL2_Pos (8U) #define GPIO_AFRL_AFSEL2_Pos (8U)
#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFRL3_Pos (12U) #define GPIO_AFRL_AFSEL3_Pos (12U)
#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFRL4_Pos (16U) #define GPIO_AFRL_AFSEL4_Pos (16U)
#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFRL5_Pos (20U) #define GPIO_AFRL_AFSEL5_Pos (20U)
#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFRL6_Pos (24U) #define GPIO_AFRL_AFSEL6_Pos (24U)
#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFRL7_Pos (28U) #define GPIO_AFRL_AFSEL7_Pos (28U)
#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
/* Legacy aliases */
#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos
#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos
#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos
#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos
#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos
#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos
#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos
#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos
#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
/****************** Bit definition for GPIO_AFRH register ********************/ /****************** Bit definition for GPIO_AFRH register ********************/
#define GPIO_AFRH_AFRH0_Pos (0U) #define GPIO_AFRH_AFSEL8_Pos (0U)
#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFRH1_Pos (4U) #define GPIO_AFRH_AFSEL9_Pos (4U)
#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFRH2_Pos (8U) #define GPIO_AFRH_AFSEL10_Pos (8U)
#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFRH3_Pos (12U) #define GPIO_AFRH_AFSEL11_Pos (12U)
#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFRH4_Pos (16U) #define GPIO_AFRH_AFSEL12_Pos (16U)
#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFRH5_Pos (20U) #define GPIO_AFRH_AFSEL13_Pos (20U)
#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFRH6_Pos (24U) #define GPIO_AFRH_AFSEL14_Pos (24U)
#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFRH7_Pos (28U) #define GPIO_AFRH_AFSEL15_Pos (28U)
#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
/* Legacy aliases */
#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos
#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos
#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos
#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos
#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos
#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos
#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos
#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos
#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
/****************** Bit definition for GPIO_BRR register *********************/ /****************** Bit definition for GPIO_BRR register *********************/
#define GPIO_BRR_BR_0 (0x00000001U) #define GPIO_BRR_BR_0 (0x00000001U)
@ -8169,99 +8219,99 @@ typedef struct
/***************** Bit definition for RCC_APB2RSTR register ****************/ /***************** Bit definition for RCC_APB2RSTR register ****************/
#define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
#define RCC_APB2RSTR_USART6RST_Pos (5U) #define RCC_APB2RSTR_USART6RST_Pos (5U)
#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */ #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk /*!< USART6 clock reset */ #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk /*!< USART6 reset */
#define RCC_APB2RSTR_USART7RST_Pos (6U) #define RCC_APB2RSTR_USART7RST_Pos (6U)
#define RCC_APB2RSTR_USART7RST_Msk (0x1U << RCC_APB2RSTR_USART7RST_Pos) /*!< 0x00000040 */ #define RCC_APB2RSTR_USART7RST_Msk (0x1U << RCC_APB2RSTR_USART7RST_Pos) /*!< 0x00000040 */
#define RCC_APB2RSTR_USART7RST RCC_APB2RSTR_USART7RST_Msk /*!< USART7 clock reset */ #define RCC_APB2RSTR_USART7RST RCC_APB2RSTR_USART7RST_Msk /*!< USART7 reset */
#define RCC_APB2RSTR_USART8RST_Pos (7U) #define RCC_APB2RSTR_USART8RST_Pos (7U)
#define RCC_APB2RSTR_USART8RST_Msk (0x1U << RCC_APB2RSTR_USART8RST_Pos) /*!< 0x00000080 */ #define RCC_APB2RSTR_USART8RST_Msk (0x1U << RCC_APB2RSTR_USART8RST_Pos) /*!< 0x00000080 */
#define RCC_APB2RSTR_USART8RST RCC_APB2RSTR_USART8RST_Msk /*!< USART8 clock reset */ #define RCC_APB2RSTR_USART8RST RCC_APB2RSTR_USART8RST_Msk /*!< USART8 reset */
#define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Pos (9U)
#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */
#define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Pos (11U)
#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */
#define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Pos (12U)
#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
#define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Pos (14U)
#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
#define RCC_APB2RSTR_TIM15RST_Pos (16U) #define RCC_APB2RSTR_TIM15RST_Pos (16U)
#define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */ #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */
#define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Pos (17U)
#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */
#define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */
#define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Pos (22U)
#define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */
/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ /*!< Old ADC1 reset bit definition maintained for legacy purpose */
#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
/***************** Bit definition for RCC_APB1RSTR register ****************/ /***************** Bit definition for RCC_APB1RSTR register ****************/
#define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Pos (0U)
#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
#define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Pos (1U)
#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
#define RCC_APB1RSTR_TIM6RST_Pos (4U) #define RCC_APB1RSTR_TIM6RST_Pos (4U)
#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
#define RCC_APB1RSTR_TIM7RST_Pos (5U) #define RCC_APB1RSTR_TIM7RST_Pos (5U)
#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 clock reset */ #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
#define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Pos (8U)
#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */
#define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Pos (11U)
#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
#define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Pos (14U)
#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */
#define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Pos (17U)
#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
#define RCC_APB1RSTR_USART3RST_Pos (18U) #define RCC_APB1RSTR_USART3RST_Pos (18U)
#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 clock reset */ #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
#define RCC_APB1RSTR_USART4RST_Pos (19U) #define RCC_APB1RSTR_USART4RST_Pos (19U)
#define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */ #define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */
#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 clock reset */ #define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 reset */
#define RCC_APB1RSTR_USART5RST_Pos (20U) #define RCC_APB1RSTR_USART5RST_Pos (20U)
#define RCC_APB1RSTR_USART5RST_Msk (0x1U << RCC_APB1RSTR_USART5RST_Pos) /*!< 0x00100000 */ #define RCC_APB1RSTR_USART5RST_Msk (0x1U << RCC_APB1RSTR_USART5RST_Pos) /*!< 0x00100000 */
#define RCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_Msk /*!< USART 5 clock reset */ #define RCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_Msk /*!< USART 5 reset */
#define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Pos (21U)
#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
#define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Pos (22U)
#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
#define RCC_APB1RSTR_CANRST_Pos (25U) #define RCC_APB1RSTR_CANRST_Pos (25U)
#define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */ #define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */
#define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN clock reset */ #define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN reset */
#define RCC_APB1RSTR_CRSRST_Pos (27U) #define RCC_APB1RSTR_CRSRST_Pos (27U)
#define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */ #define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS clock reset */ #define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS reset */
#define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Pos (28U)
#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
#define RCC_APB1RSTR_DACRST_Pos (29U) #define RCC_APB1RSTR_DACRST_Pos (29U)
#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */ #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC reset */
#define RCC_APB1RSTR_CECRST_Pos (30U) #define RCC_APB1RSTR_CECRST_Pos (30U)
#define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */ #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */
#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC clock reset */ #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC reset */
/****************** Bit definition for RCC_AHBENR register *****************/ /****************** Bit definition for RCC_AHBENR register *****************/
#define RCC_AHBENR_DMAEN_Pos (0U) #define RCC_AHBENR_DMAEN_Pos (0U)
@ -8480,28 +8530,28 @@ typedef struct
/******************* Bit definition for RCC_AHBRSTR register ***************/ /******************* Bit definition for RCC_AHBRSTR register ***************/
#define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Pos (17U)
#define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */
#define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Pos (18U)
#define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */
#define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Pos (19U)
#define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */
#define RCC_AHBRSTR_GPIODRST_Pos (20U) #define RCC_AHBRSTR_GPIODRST_Pos (20U)
#define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */ #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */
#define RCC_AHBRSTR_GPIOERST_Pos (21U) #define RCC_AHBRSTR_GPIOERST_Pos (21U)
#define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */ #define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */
#define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIOE clock reset */ #define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIOE reset */
#define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Pos (22U)
#define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */
#define RCC_AHBRSTR_TSCRST_Pos (24U) #define RCC_AHBRSTR_TSCRST_Pos (24U)
#define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */ #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS clock reset */ #define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS reset */
/* Old Bit definition maintained for legacy purpose */ /* Old Bit definition maintained for legacy purpose */
#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */ #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS reset */
/******************* Bit definition for RCC_CFGR2 register *****************/ /******************* Bit definition for RCC_CFGR2 register *****************/
/*!< PREDIV configuration */ /*!< PREDIV configuration */
@ -8729,9 +8779,9 @@ typedef struct
#define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BCK_Pos (18U) #define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BCK RTC_CR_BCK_Msk #define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@ -8775,6 +8825,11 @@ typedef struct
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/* Legacy defines */
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
#define RTC_CR_BCK RTC_CR_BKP
/******************** Bits definition for RTC_ISR register *****************/ /******************** Bits definition for RTC_ISR register *****************/
#define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Pos (16U)
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
@ -11673,6 +11728,9 @@ typedef struct
#define IS_TIM_REMAP_INSTANCE(INSTANCE)\ #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
((INSTANCE) == TIM14) ((INSTANCE) == TIM14)
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
((INSTANCE) == TIM1)
/****************************** TSC Instances *********************************/ /****************************** TSC Instances *********************************/
#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)

6
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f0xx.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx.h * @file stm32f0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
@ -112,11 +110,11 @@
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V2.3.1 * @brief CMSIS Device version number V2.3.3
*/ */
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/system_stm32f0xx.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f0xx.h * @file system_stm32f0xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention

4
targets/TARGET_STM/TARGET_STM32F0/analogin_device.c
View File

@ -73,7 +73,7 @@ void analogin_init(analogin_t *obj, PinName pin)
obj->handle.Init.Resolution = ADC_RESOLUTION_12B; obj->handle.Init.Resolution = ADC_RESOLUTION_12B;
obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
obj->handle.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; obj->handle.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD;
obj->handle.Init.EOCSelection = EOC_SINGLE_CONV; obj->handle.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
obj->handle.Init.LowPowerAutoWait = DISABLE; obj->handle.Init.LowPowerAutoWait = DISABLE;
obj->handle.Init.LowPowerAutoPowerOff = DISABLE; obj->handle.Init.LowPowerAutoPowerOff = DISABLE;
obj->handle.Init.ContinuousConvMode = DISABLE; obj->handle.Init.ContinuousConvMode = DISABLE;
@ -81,7 +81,7 @@ void analogin_init(analogin_t *obj, PinName pin)
obj->handle.Init.ExternalTrigConv = ADC_SOFTWARE_START; obj->handle.Init.ExternalTrigConv = ADC_SOFTWARE_START;
obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
obj->handle.Init.DMAContinuousRequests = DISABLE; obj->handle.Init.DMAContinuousRequests = DISABLE;
obj->handle.Init.Overrun = OVR_DATA_OVERWRITTEN; obj->handle.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
__HAL_RCC_ADC1_CLK_ENABLE(); __HAL_RCC_ADC1_CLK_ENABLE();

916
targets/TARGET_STM/TARGET_STM32F0/device/Release_Notes_stm32f0xx_hal.html
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File diff suppressed because one or more lines are too long

95
targets/TARGET_STM/TARGET_STM32F0/device/stm32_hal_legacy.h
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32_hal_legacy.h * @file stm32_hal_legacy.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0 * @version V1.8.1
* @date 04-November-2016 * @date 14-April-2017
* @brief This file contains aliases definition for the STM32Cube HAL constants * @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose. * macros and functions maintained for legacy purpose.
****************************************************************************** ******************************************************************************
@ -138,7 +138,9 @@
#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */ #if defined(STM32L0)
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
#endif
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx) #if defined(STM32F373xC) || defined(STM32F378xx)
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
@ -265,7 +267,6 @@
#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
@ -457,6 +458,78 @@
* @} * @}
*/ */
/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
* @{
*/
#if defined(STM32H7)
#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#endif /* STM32H7 */
/**
* @}
*/
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@ -670,7 +743,6 @@
#define FORMAT_BCD RTC_FORMAT_BCD #define FORMAT_BCD RTC_FORMAT_BCD
#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
@ -678,9 +750,6 @@
#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
@ -1312,7 +1381,6 @@
#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
#define __HAL_ADC_JSQR ADC_JSQR #define __HAL_ADC_JSQR ADC_JSQR
#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
@ -2410,7 +2478,6 @@
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
@ -2443,8 +2510,6 @@
#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
@ -2466,8 +2531,6 @@
#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
@ -2692,7 +2755,10 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32WB)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
@ -2788,7 +2854,6 @@
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
/** /**
* @} * @}
*/ */

50
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.c
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal.c * @file stm32f0xx_hal.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief HAL module driver. * @brief HAL module driver.
* This is the common part of the HAL initialization * This is the common part of the HAL initialization
* *
@ -70,10 +68,10 @@
* @{ * @{
*/ */
/** /**
* @brief STM32F0xx HAL Driver version number V1.5.0 * @brief STM32F0xx HAL Driver version number V1.7.0
*/ */
#define __STM32F0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32F0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F0xx_HAL_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ #define __STM32F0xx_HAL_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32F0xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F0xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24U)\ #define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24U)\
@ -232,7 +230,7 @@ __weak void HAL_MspDeInit(void)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __Weak to be overwritten in case of other * The function is declared as __Weak to be overwritten in case of other
* implementation in user file. * implementation in user file.
* @param TickPriority: Tick interrupt priority. * @param TickPriority Tick interrupt priority.
* @retval HAL status * @retval HAL status
*/ */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
@ -307,14 +305,21 @@ __weak uint32_t HAL_GetTick(void)
* is incremented. * is incremented.
* @note ThiS function is declared as __weak to be overwritten in case of other * @note ThiS function is declared as __weak to be overwritten in case of other
* implementations in user file. * implementations in user file.
* @param Delay: specifies the delay time length, in milliseconds. * @param Delay specifies the delay time length, in milliseconds.
* @retval None * @retval None
*/ */
__weak void HAL_Delay(__IO uint32_t Delay) __weak void HAL_Delay(__IO uint32_t Delay)
{ {
uint32_t tickstart = 0U; uint32_t tickstart = HAL_GetTick();
tickstart = HAL_GetTick(); uint32_t wait = Delay;
while((HAL_GetTick() - tickstart) < Delay)
/* Add a period to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
{
wait++;
}
while((HAL_GetTick() - tickstart) < wait)
{ {
} }
} }
@ -379,6 +384,33 @@ uint32_t HAL_GetDEVID(void)
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
} }
/**
* @brief Returns first word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw0(void)
{
return(READ_REG(*((uint32_t *)UID_BASE)));
}
/**
* @brief Returns second word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw1(void)
{
return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
}
/**
* @brief Returns third word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw2(void)
{
return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
}
/** /**
* @brief Enable the Debug Module during STOP mode * @brief Enable the Debug Module during STOP mode
* @retval None * @retval None

11
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal.h * @file stm32f0xx_hal.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief This file contains all the functions prototypes for the HAL * @brief This file contains all the functions prototypes for the HAL
* module driver. * module driver.
****************************************************************************** ******************************************************************************
@ -378,7 +376,7 @@
#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
/** @defgroup HAL_Pin_remap HAL Pin remap /** @defgroup HAL_Pin_remap HAL Pin remap
* @brief Pin remapping enable/disable macros * @brief Pin remapping enable/disable macros
* @param __PIN_REMAP__: This parameter can be a value of @ref HAL_Pin_remapping * @param __PIN_REMAP__ This parameter can be a value of @ref HAL_Pin_remapping
* @{ * @{
*/ */
#define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ #define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
@ -393,7 +391,7 @@
#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
/** @brief Fast-mode Plus driving capability enable/disable macros /** @brief Fast-mode Plus driving capability enable/disable macros
* @param __FASTMODEPLUS__: This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values. * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
* That you can find above these macros. * That you can find above these macros.
*/ */
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
@ -482,7 +480,7 @@
/** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection /** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection
* @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register * @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register
* @note This feature is applicable on STM32F09x * @note This feature is applicable on STM32F09x
* @param __SOURCE__: This parameter can be a value of @ref HAL_IRDA_ENV_SEL * @param __SOURCE__ This parameter can be a value of @ref HAL_IRDA_ENV_SEL
* @{ * @{
*/ */
#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \ #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \
@ -532,6 +530,9 @@ void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void); uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void); uint32_t HAL_GetDEVID(void);
uint32_t HAL_GetUIDw0(void);
uint32_t HAL_GetUIDw1(void);
uint32_t HAL_GetUIDw2(void);
void HAL_DBGMCU_EnableDBGStopMode(void); void HAL_DBGMCU_EnableDBGStopMode(void);
void HAL_DBGMCU_DisableDBGStopMode(void); void HAL_DBGMCU_DisableDBGStopMode(void);
void HAL_DBGMCU_EnableDBGStandbyMode(void); void HAL_DBGMCU_EnableDBGStandbyMode(void);

72
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.c
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_adc.c * @file stm32f0xx_hal_adc.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) * functionalities of the Analog to Digital Convertor (ADC)
* peripheral: * peripheral:
@ -355,7 +353,7 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma);
* @note This function configures the ADC within 2 scopes: scope of entire * @note This function configures the ADC within 2 scopes: scope of entire
* ADC and scope of regular group. For parameters details, see comments * ADC and scope of regular group. For parameters details, see comments
* of structure "ADC_InitTypeDef". * of structure "ADC_InitTypeDef".
* @param hadc: ADC handle * @param hadc ADC handle
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
@ -581,7 +579,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
* bypassed without error reporting: it can be the intended behaviour in * bypassed without error reporting: it can be the intended behaviour in
* case of reset of a single ADC while the other ADCs sharing the same * case of reset of a single ADC while the other ADCs sharing the same
* common group is still running. * common group is still running.
* @param hadc: ADC handle * @param hadc ADC handle
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
@ -697,7 +695,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
/** /**
* @brief Initializes the ADC MSP. * @brief Initializes the ADC MSP.
* @param hadc: ADC handle * @param hadc ADC handle
* @retval None * @retval None
*/ */
__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
@ -712,7 +710,7 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
/** /**
* @brief DeInitializes the ADC MSP. * @brief DeInitializes the ADC MSP.
* @param hadc: ADC handle * @param hadc ADC handle
* @retval None * @retval None
*/ */
__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
@ -754,7 +752,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
/** /**
* @brief Enables ADC, starts conversion of regular group. * @brief Enables ADC, starts conversion of regular group.
* Interruptions enabled in this function: None. * Interruptions enabled in this function: None.
* @param hadc: ADC handle * @param hadc ADC handle
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
@ -819,7 +817,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
/** /**
* @brief Stop ADC conversion of regular group, disable ADC peripheral. * @brief Stop ADC conversion of regular group, disable ADC peripheral.
* @param hadc: ADC handle * @param hadc ADC handle
* @retval HAL status. * @retval HAL status.
*/ */
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
@ -872,8 +870,8 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
* performed on each conversion. Nevertheless, polling can still * performed on each conversion. Nevertheless, polling can still
* be performed on the complete sequence (ADC init * be performed on the complete sequence (ADC init
* parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
* @param hadc: ADC handle * @param hadc ADC handle
* @param Timeout: Timeout value in millisecond. * @param Timeout Timeout value in millisecond.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
@ -988,12 +986,12 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
/** /**
* @brief Poll for conversion event. * @brief Poll for conversion event.
* @param hadc: ADC handle * @param hadc ADC handle
* @param EventType: the ADC event type. * @param EventType the ADC event type.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg ADC_AWD_EVENT: ADC Analog watchdog event * @arg ADC_AWD_EVENT: ADC Analog watchdog event
* @arg ADC_OVR_EVENT: ADC Overrun event * @arg ADC_OVR_EVENT: ADC Overrun event
* @param Timeout: Timeout value in millisecond. * @param Timeout Timeout value in millisecond.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
@ -1069,7 +1067,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
* parameter "EOCSelection" * parameter "EOCSelection"
* - overrun (if available) * - overrun (if available)
* Each of these interruptions has its dedicated callback function. * Each of these interruptions has its dedicated callback function.
* @param hadc: ADC handle * @param hadc ADC handle
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
@ -1150,7 +1148,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
/** /**
* @brief Stop ADC conversion of regular group, disable interruption of * @brief Stop ADC conversion of regular group, disable interruption of
* end-of-conversion, disable ADC peripheral. * end-of-conversion, disable ADC peripheral.
* @param hadc: ADC handle * @param hadc ADC handle
* @retval HAL status. * @retval HAL status.
*/ */
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
@ -1201,9 +1199,9 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
* - DMA half transfer * - DMA half transfer
* - overrun * - overrun
* Each of these interruptions has its dedicated callback function. * Each of these interruptions has its dedicated callback function.
* @param hadc: ADC handle * @param hadc ADC handle
* @param pData: The destination Buffer address. * @param pData The destination Buffer address.
* @param Length: The length of data to be transferred from ADC peripheral to memory. * @param Length The length of data to be transferred from ADC peripheral to memory.
* @retval None * @retval None
*/ */
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
@ -1292,7 +1290,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
* @brief Stop ADC conversion of regular group, disable ADC DMA transfer, disable * @brief Stop ADC conversion of regular group, disable ADC DMA transfer, disable
* ADC peripheral. * ADC peripheral.
* Each of these interruptions has its dedicated callback function. * Each of these interruptions has its dedicated callback function.
* @param hadc: ADC handle * @param hadc ADC handle
* @retval HAL status. * @retval HAL status.
*/ */
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
@ -1374,7 +1372,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
* in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
* model polling: @ref HAL_ADC_PollForConversion() * model polling: @ref HAL_ADC_PollForConversion()
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
* @param hadc: ADC handle * @param hadc ADC handle
* @retval ADC group regular conversion data * @retval ADC group regular conversion data
*/ */
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
@ -1391,7 +1389,7 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
/** /**
* @brief Handles ADC interrupt request. * @brief Handles ADC interrupt request.
* @param hadc: ADC handle * @param hadc ADC handle
* @retval None * @retval None
*/ */
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
@ -1507,7 +1505,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/** /**
* @brief Conversion complete callback in non blocking mode * @brief Conversion complete callback in non blocking mode
* @param hadc: ADC handle * @param hadc ADC handle
* @retval None * @retval None
*/ */
__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
@ -1522,7 +1520,7 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
/** /**
* @brief Conversion DMA half-transfer callback in non blocking mode * @brief Conversion DMA half-transfer callback in non blocking mode
* @param hadc: ADC handle * @param hadc ADC handle
* @retval None * @retval None
*/ */
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
@ -1537,7 +1535,7 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
/** /**
* @brief Analog watchdog callback in non blocking mode. * @brief Analog watchdog callback in non blocking mode.
* @param hadc: ADC handle * @param hadc ADC handle
* @retval None * @retval None
*/ */
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
@ -1553,7 +1551,7 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
/** /**
* @brief ADC error callback in non blocking mode * @brief ADC error callback in non blocking mode
* (ADC conversion with interruption or transfer by DMA) * (ADC conversion with interruption or transfer by DMA)
* @param hadc: ADC handle * @param hadc ADC handle
* @retval None * @retval None
*/ */
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
@ -1606,8 +1604,8 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
* The setting of these parameters is conditioned to ADC state. * The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure * For parameters constraints, see comments of structure
* "ADC_ChannelConfTypeDef". * "ADC_ChannelConfTypeDef".
* @param hadc: ADC handle * @param hadc ADC handle
* @param sConfig: Structure of ADC channel for regular group. * @param sConfig Structure of ADC channel for regular group.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
@ -1739,8 +1737,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
* The setting of these parameters is conditioned to ADC state. * The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure * For parameters constraints, see comments of structure
* "ADC_AnalogWDGConfTypeDef". * "ADC_AnalogWDGConfTypeDef".
* @param hadc: ADC handle * @param hadc ADC handle
* @param AnalogWDGConfig: Structure of ADC analog watchdog configuration * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
@ -1862,7 +1860,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
* For example: * For example:
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
* @param hadc: ADC handle * @param hadc ADC handle
* @retval HAL state * @retval HAL state
*/ */
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
@ -1876,7 +1874,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
/** /**
* @brief Return the ADC error code * @brief Return the ADC error code
* @param hadc: ADC handle * @param hadc ADC handle
* @retval ADC Error Code * @retval ADC Error Code
*/ */
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
@ -1906,7 +1904,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
* flag ADC_FLAG_RDY is not usable. * flag ADC_FLAG_RDY is not usable.
* Therefore, this function must be called under condition of * Therefore, this function must be called under condition of
* "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)".
* @param hadc: ADC handle * @param hadc ADC handle
* @retval HAL status. * @retval HAL status.
*/ */
static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
@ -1971,7 +1969,7 @@ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
* @brief Disable the selected ADC. * @brief Disable the selected ADC.
* @note Prerequisite condition to use this function: ADC conversions must be * @note Prerequisite condition to use this function: ADC conversions must be
* stopped. * stopped.
* @param hadc: ADC handle * @param hadc ADC handle
* @retval HAL status. * @retval HAL status.
*/ */
static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
@ -2028,7 +2026,7 @@ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
* @brief Stop ADC conversion. * @brief Stop ADC conversion.
* @note Prerequisite condition to use this function: ADC conversions must be * @note Prerequisite condition to use this function: ADC conversions must be
* stopped to disable the ADC. * stopped to disable the ADC.
* @param hadc: ADC handle * @param hadc ADC handle
* @retval HAL status. * @retval HAL status.
*/ */
static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc)
@ -2079,7 +2077,7 @@ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc)
/** /**
* @brief DMA transfer complete callback. * @brief DMA transfer complete callback.
* @param hdma: pointer to DMA handle. * @param hdma pointer to DMA handle.
* @retval None * @retval None
*/ */
static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
@ -2140,7 +2138,7 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
/** /**
* @brief DMA half transfer complete callback. * @brief DMA half transfer complete callback.
* @param hdma: pointer to DMA handle. * @param hdma pointer to DMA handle.
* @retval None * @retval None
*/ */
static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
@ -2154,7 +2152,7 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
/** /**
* @brief DMA error callback * @brief DMA error callback
* @param hdma: pointer to DMA handle. * @param hdma pointer to DMA handle.
* @retval None * @retval None
*/ */
static void ADC_DMAError(DMA_HandleTypeDef *hdma) static void ADC_DMAError(DMA_HandleTypeDef *hdma)

74
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_adc.h * @file stm32f0xx_hal_adc.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Header file containing functions prototypes of ADC HAL library. * @brief Header file containing functions prototypes of ADC HAL library.
****************************************************************************** ******************************************************************************
* @attention * @attention
@ -332,7 +330,6 @@ typedef struct
*/ */
#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) #define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) #define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */
/** /**
* @} * @}
*/ */
@ -463,7 +460,7 @@ typedef struct
/** /**
* @brief Enable the ADC peripheral * @brief Enable the ADC peripheral
* @param __HANDLE__: ADC handle * @param __HANDLE__ ADC handle
* @retval None * @retval None
*/ */
#define __HAL_ADC_ENABLE(__HANDLE__) \ #define __HAL_ADC_ENABLE(__HANDLE__) \
@ -471,7 +468,7 @@ typedef struct
/** /**
* @brief Disable the ADC peripheral * @brief Disable the ADC peripheral
* @param __HANDLE__: ADC handle * @param __HANDLE__ ADC handle
* @retval None * @retval None
*/ */
#define __HAL_ADC_DISABLE(__HANDLE__) \ #define __HAL_ADC_DISABLE(__HANDLE__) \
@ -482,8 +479,8 @@ typedef struct
/** /**
* @brief Enable the ADC end of conversion interrupt. * @brief Enable the ADC end of conversion interrupt.
* @param __HANDLE__: ADC handle * @param __HANDLE__ ADC handle
* @param __INTERRUPT__: ADC Interrupt * @param __INTERRUPT__ ADC Interrupt
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
* @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
@ -498,8 +495,8 @@ typedef struct
/** /**
* @brief Disable the ADC end of conversion interrupt. * @brief Disable the ADC end of conversion interrupt.
* @param __HANDLE__: ADC handle * @param __HANDLE__ ADC handle
* @param __INTERRUPT__: ADC Interrupt * @param __INTERRUPT__ ADC Interrupt
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
* @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
@ -513,8 +510,8 @@ typedef struct
(((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
/** @brief Checks if the specified ADC interrupt source is enabled or disabled. /** @brief Checks if the specified ADC interrupt source is enabled or disabled.
* @param __HANDLE__: ADC handle * @param __HANDLE__ ADC handle
* @param __INTERRUPT__: ADC interrupt source to check * @param __INTERRUPT__ ADC interrupt source to check
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
* @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
@ -529,8 +526,8 @@ typedef struct
/** /**
* @brief Get the selected ADC's flag status. * @brief Get the selected ADC's flag status.
* @param __HANDLE__: ADC handle * @param __HANDLE__ ADC handle
* @param __FLAG__: ADC flag * @param __FLAG__ ADC flag
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
* @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
@ -545,8 +542,8 @@ typedef struct
/** /**
* @brief Clear the ADC's pending flags * @brief Clear the ADC's pending flags
* @param __HANDLE__: ADC handle * @param __HANDLE__ ADC handle
* @param __FLAG__: ADC flag * @param __FLAG__ ADC flag
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
* @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
@ -561,7 +558,7 @@ typedef struct
(((__HANDLE__)->Instance->ISR) = (__FLAG__)) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
/** @brief Reset ADC handle state /** @brief Reset ADC handle state
* @param __HANDLE__: ADC handle * @param __HANDLE__ ADC handle
* @retval None * @retval None
*/ */
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
@ -583,7 +580,7 @@ typedef struct
/** /**
* @brief Verification of hardware constraints before ADC can be enabled * @brief Verification of hardware constraints before ADC can be enabled
* @param __HANDLE__: ADC handle * @param __HANDLE__ ADC handle
* @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
*/ */
#define ADC_ENABLING_CONDITIONS(__HANDLE__) \ #define ADC_ENABLING_CONDITIONS(__HANDLE__) \
@ -594,7 +591,7 @@ typedef struct
/** /**
* @brief Verification of hardware constraints before ADC can be disabled * @brief Verification of hardware constraints before ADC can be disabled
* @param __HANDLE__: ADC handle * @param __HANDLE__ ADC handle
* @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
*/ */
#define ADC_DISABLING_CONDITIONS(__HANDLE__) \ #define ADC_DISABLING_CONDITIONS(__HANDLE__) \
@ -604,7 +601,7 @@ typedef struct
/** /**
* @brief Verification of ADC state: enabled or disabled * @brief Verification of ADC state: enabled or disabled
* @param __HANDLE__: ADC handle * @param __HANDLE__ ADC handle
* @retval SET (ADC enabled) or RESET (ADC disabled) * @retval SET (ADC enabled) or RESET (ADC disabled)
*/ */
/* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are */ /* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are */
@ -619,7 +616,7 @@ typedef struct
/** /**
* @brief Test if conversion trigger of regular group is software start * @brief Test if conversion trigger of regular group is software start
* or external trigger. * or external trigger.
* @param __HANDLE__: ADC handle * @param __HANDLE__ ADC handle
* @retval SET (software start) or RESET (external trigger) * @retval SET (software start) or RESET (external trigger)
*/ */
#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
@ -627,7 +624,7 @@ typedef struct
/** /**
* @brief Check if no conversion on going on regular group * @brief Check if no conversion on going on regular group
* @param __HANDLE__: ADC handle * @param __HANDLE__ ADC handle
* @retval SET (conversion is on going) or RESET (no conversion is on going) * @retval SET (conversion is on going) or RESET (no conversion is on going)
*/ */
#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
@ -637,7 +634,7 @@ typedef struct
/** /**
* @brief Returns resolution bits in CFGR1 register: RES[1:0]. * @brief Returns resolution bits in CFGR1 register: RES[1:0].
* Returned value is among parameters to @ref ADC_Resolution. * Returned value is among parameters to @ref ADC_Resolution.
* @param __HANDLE__: ADC handle * @param __HANDLE__ ADC handle
* @retval None * @retval None
*/ */
#define ADC_GET_RESOLUTION(__HANDLE__) \ #define ADC_GET_RESOLUTION(__HANDLE__) \
@ -646,7 +643,7 @@ typedef struct
/** /**
* @brief Returns ADC sample time bits in SMPR register: SMP[2:0]. * @brief Returns ADC sample time bits in SMPR register: SMP[2:0].
* Returned value is among parameters to @ref ADC_Resolution. * Returned value is among parameters to @ref ADC_Resolution.
* @param __HANDLE__: ADC handle * @param __HANDLE__ ADC handle
* @retval None * @retval None
*/ */
#define ADC_GET_SAMPLINGTIME(__HANDLE__) \ #define ADC_GET_SAMPLINGTIME(__HANDLE__) \
@ -663,7 +660,7 @@ typedef struct
/** /**
* @brief Clear ADC error code (set it to error code: "no error") * @brief Clear ADC error code (set it to error code: "no error")
* @param __HANDLE__: ADC handle * @param __HANDLE__ ADC handle
* @retval None * @retval None
*/ */
#define ADC_CLEAR_ERRORCODE(__HANDLE__) \ #define ADC_CLEAR_ERRORCODE(__HANDLE__) \
@ -672,7 +669,7 @@ typedef struct
/** /**
* @brief Configure the channel number into channel selection register * @brief Configure the channel number into channel selection register
* @param _CHANNEL_: ADC Channel * @param _CHANNEL_ ADC Channel
* @retval None * @retval None
*/ */
/* This function converts ADC channels from numbers (see defgroup ADC_channels) /* This function converts ADC channels from numbers (see defgroup ADC_channels)
@ -702,7 +699,7 @@ typedef struct
/** /**
* @brief Set the ADC's sample time * @brief Set the ADC's sample time
* @param _SAMPLETIME_: Sample time parameter. * @param _SAMPLETIME_ Sample time parameter.
* @retval None * @retval None
*/ */
/* Note: ADC sampling time set using mask ADC_SMPR_SMP due to parameter */ /* Note: ADC sampling time set using mask ADC_SMPR_SMP due to parameter */
@ -715,7 +712,7 @@ typedef struct
/** /**
* @brief Set the Analog Watchdog 1 channel. * @brief Set the Analog Watchdog 1 channel.
* @param _CHANNEL_: channel to be monitored by Analog Watchdog 1. * @param _CHANNEL_ channel to be monitored by Analog Watchdog 1.
* @retval None * @retval None
*/ */
#define ADC_CFGR_AWDCH(_CHANNEL_) \ #define ADC_CFGR_AWDCH(_CHANNEL_) \
@ -723,7 +720,7 @@ typedef struct
/** /**
* @brief Enable ADC discontinuous conversion mode for regular group * @brief Enable ADC discontinuous conversion mode for regular group
* @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode. * @param _REG_DISCONTINUOUS_MODE_ Regular discontinuous mode.
* @retval None * @retval None
*/ */
#define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \ #define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \
@ -731,7 +728,7 @@ typedef struct
/** /**
* @brief Enable the ADC auto off mode. * @brief Enable the ADC auto off mode.
* @param _AUTOOFF_: Auto off bit enable or disable. * @param _AUTOOFF_ Auto off bit enable or disable.
* @retval None * @retval None
*/ */
#define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \ #define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \
@ -739,7 +736,7 @@ typedef struct
/** /**
* @brief Enable the ADC auto delay mode. * @brief Enable the ADC auto delay mode.
* @param _AUTOWAIT_: Auto delay bit enable or disable. * @param _AUTOWAIT_ Auto delay bit enable or disable.
* @retval None * @retval None
*/ */
#define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \ #define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \
@ -747,7 +744,7 @@ typedef struct
/** /**
* @brief Enable ADC continuous conversion mode. * @brief Enable ADC continuous conversion mode.
* @param _CONTINUOUS_MODE_: Continuous mode. * @param _CONTINUOUS_MODE_ Continuous mode.
* @retval None * @retval None
*/ */
#define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \ #define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \
@ -755,7 +752,7 @@ typedef struct
/** /**
* @brief Enable ADC overrun mode. * @brief Enable ADC overrun mode.
* @param _OVERRUN_MODE_: Overrun mode. * @param _OVERRUN_MODE_ Overrun mode.
* @retval Overun bit setting to be programmed into CFGR register * @retval Overun bit setting to be programmed into CFGR register
*/ */
/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */
@ -768,7 +765,7 @@ typedef struct
/** /**
* @brief Enable ADC scan mode to convert multiple ranks with sequencer. * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
* @param _SCAN_MODE_: Scan conversion mode. * @param _SCAN_MODE_ Scan conversion mode.
* @retval None * @retval None
*/ */
/* Note: Scan mode set using this macro (instead of parameter direct set) */ /* Note: Scan mode set using this macro (instead of parameter direct set) */
@ -782,7 +779,7 @@ typedef struct
/** /**
* @brief Enable the ADC DMA continuous request. * @brief Enable the ADC DMA continuous request.
* @param _DMACONTREQ_MODE_: DMA continuous request mode. * @param _DMACONTREQ_MODE_ DMA continuous request mode.
* @retval None * @retval None
*/ */
#define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \ #define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \
@ -790,7 +787,7 @@ typedef struct
/** /**
* @brief Configure the analog watchdog high threshold into register TR. * @brief Configure the analog watchdog high threshold into register TR.
* @param _Threshold_: Threshold value * @param _Threshold_ Threshold value
* @retval None * @retval None
*/ */
#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) \ #define ADC_TRX_HIGHTHRESHOLD(_Threshold_) \
@ -804,8 +801,8 @@ typedef struct
* If resolution 8 bits, shift of 4 ranks on the left. * If resolution 8 bits, shift of 4 ranks on the left.
* If resolution 6 bits, shift of 6 ranks on the left. * If resolution 6 bits, shift of 6 ranks on the left.
* therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
* @param __HANDLE__: ADC handle * @param __HANDLE__ ADC handle
* @param _Threshold_: Value to be shifted * @param _Threshold_ Value to be shifted
* @retval None * @retval None
*/ */
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
@ -833,8 +830,7 @@ typedef struct
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
((EOC_SELECTION) == ADC_EOC_SEQ_CONV) || \ ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) )
((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV) )
#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) ((OVR) == ADC_OVR_DATA_OVERWRITTEN) )

19
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.c
View File

@ -2,15 +2,13 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_adc_ex.c * @file stm32f0xx_hal_adc_ex.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) * functionalities of the Analog to Digital Convertor (ADC)
* peripheral: * peripheral:
* + Operation functions * + Operation functions
* ++ Calibration (ADC automatic self-calibration) * ++ Calibration (ADC automatic self-calibration)
* Other functions (generic functions) are available in file * Other functions (generic functions) are available in file
* "stm32l1xx_hal_adc.c". * "stm32f0xx_hal_adc.c".
* *
@verbatim @verbatim
[..] [..]
@ -109,13 +107,14 @@
* function before HAL_ADC_Start() or after HAL_ADC_Stop() ). * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
* @note Calibration factor can be read after calibration, using function * @note Calibration factor can be read after calibration, using function
* HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]). * HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]).
* @param hadc: ADC handle * @param hadc ADC handle
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
{ {
HAL_StatusTypeDef tmp_hal_status = HAL_OK; HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tickstart = 0U; uint32_t tickstart = 0U;
uint32_t backup_setting_adc_dma_transfer = 0; /* Note: Variable not declared as volatile because register read is already declared as volatile */
/* Check the parameters */ /* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -131,6 +130,15 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL); HAL_ADC_STATE_BUSY_INTERNAL);
/* Disable ADC DMA transfer request during calibration */
/* Note: Specificity of this STM32 serie: Calibration factor is */
/* available in data register and also transfered by DMA. */
/* To not insert ADC calibration factor among ADC conversion data */
/* in array variable, DMA transfer must be disabled during */
/* calibration. */
backup_setting_adc_dma_transfer = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
/* Start ADC calibration */ /* Start ADC calibration */
hadc->Instance->CR |= ADC_CR_ADCAL; hadc->Instance->CR |= ADC_CR_ADCAL;
@ -153,6 +161,9 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
} }
} }
/* Restore ADC DMA transfer request after calibration */
SET_BIT(hadc->Instance->CFGR1, backup_setting_adc_dma_transfer);
/* Set ADC state */ /* Set ADC state */
ADC_STATE_CLR_SET(hadc->State, ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_BUSY_INTERNAL,

6
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_adc_ex.h * @file stm32f0xx_hal_adc_ex.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Header file of ADC HAL Extension module. * @brief Header file of ADC HAL Extension module.
****************************************************************************** ******************************************************************************
* @attention * @attention
@ -153,7 +151,7 @@
* VrefInt/TempSensor/Vbat * VrefInt/TempSensor/Vbat
* Note: On STM32F0, availability of internal channel Vbat depends on * Note: On STM32F0, availability of internal channel Vbat depends on
* devices lines. * devices lines.
* @param __CHANNEL__: ADC channel * @param __CHANNEL__ ADC channel
* @retval None * @retval None
*/ */
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
@ -175,7 +173,7 @@
* VrefInt/TempSensor/Vbat. * VrefInt/TempSensor/Vbat.
* Note: On STM32F0, availability of internal channel Vbat depends on * Note: On STM32F0, availability of internal channel Vbat depends on
* devices lines. * devices lines.
* @param __CHANNEL__: ADC channel * @param __CHANNEL__ ADC channel
* @retval Bit of register ADC_CCR * @retval Bit of register ADC_CCR
*/ */
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)

828
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.c
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File diff suppressed because it is too large Load Diff

156
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.h
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@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_can.h * @file stm32f0xx_hal_can.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Header file of CAN HAL module. * @brief Header file of CAN HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
@ -69,8 +67,12 @@ typedef enum
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX = 0x22U, /*!< CAN process is ongoing */ HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX = 0x32U, /*!< CAN process is ongoing */ HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
@ -140,7 +142,7 @@ typedef struct
second one for a 16-bit configuration). second one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */ This parameter can be a value of @ref CAN_filter_FIFO */
uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
@ -227,7 +229,9 @@ typedef struct
CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */ CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
HAL_LockTypeDef Lock; /*!< CAN locking object */ HAL_LockTypeDef Lock; /*!< CAN locking object */
@ -260,6 +264,9 @@ typedef struct
#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */ #define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */
#define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */ #define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */
#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */ #define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */
#define HAL_CAN_ERROR_FOV0 (0x00000200U) /*!< FIFO0 overrun error */
#define HAL_CAN_ERROR_FOV1 (0x00000400U) /*!< FIFO1 overrun error */
#define HAL_CAN_ERROR_TXFAIL (0x00000800U) /*!< Transmit failure */
/** /**
* @} * @}
*/ */
@ -273,7 +280,7 @@ typedef struct
* @} * @}
*/ */
/** @defgroup CAN_operating_mode CAN operating mode /** @defgroup CAN_operating_mode CAN Operating Mode
* @{ * @{
*/ */
#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ #define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
@ -285,7 +292,7 @@ typedef struct
*/ */
/** @defgroup CAN_synchronisation_jump_width CAN synchronisation jump width /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
* @{ * @{
*/ */
#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
@ -296,7 +303,7 @@ typedef struct
* @} * @}
*/ */
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN time quantum in bit segment 1 /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
* @{ * @{
*/ */
#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
@ -315,12 +322,11 @@ typedef struct
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ #define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ #define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ #define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
/** /**
* @} * @}
*/ */
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN time quantum in bit segment 2 /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
* @{ * @{
*/ */
#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
@ -331,72 +337,65 @@ typedef struct
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ #define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ #define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ #define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
/** /**
* @} * @}
*/ */
/** @defgroup CAN_filter_mode CAN filter mode /** @defgroup CAN_filter_mode CAN Filter Mode
* @{ * @{
*/ */
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */ #define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */ #define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */
/** /**
* @} * @}
*/ */
/** @defgroup CAN_filter_scale CAN filter scale /** @defgroup CAN_filter_scale CAN Filter Scale
* @{ * @{
*/ */
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */ #define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */ #define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */
/** /**
* @} * @}
*/ */
/** @defgroup CAN_filter_FIFO CAN filter FIFO /** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{ * @{
*/ */
#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */ #define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */ #define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */
/** /**
* @} * @}
*/ */
/** @defgroup CAN_identifier_type CAN identifier type /** @defgroup CAN_identifier_type CAN Identifier Type
* @{ * @{
*/ */
#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ #define CAN_ID_STD (0x00000000U) /*!< Standard Id */
#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ #define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
/** /**
* @} * @}
*/ */
/** @defgroup CAN_remote_transmission_request CAN remote transmission request /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
* @{ * @{
*/ */
#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ #define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ #define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
/** /**
* @} * @}
*/ */
/** @defgroup CAN_receive_FIFO_number_constants CAN receive FIFO number constants /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
* @{ * @{
*/ */
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */ #define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */ #define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */
/** /**
* @} * @}
*/ */
/** @defgroup CAN_flags CAN flags /** @defgroup CAN_flags CAN Flags
* @{ * @{
*/ */
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
@ -423,22 +422,25 @@ typedef struct
#define CAN_FLAG_FOV1 (0x00000404U) /*!< FIFO 1 Overrun flag */ #define CAN_FLAG_FOV1 (0x00000404U) /*!< FIFO 1 Overrun flag */
/* Operating Mode Flags */ /* Operating Mode Flags */
#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */ #define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */
#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ #define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */
#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */
#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */ #define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. /* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible.
In this case the SLAK bit can be polled.*/ In this case the SLAK bit can be polled.*/
/* Error Flags */ /* Error Flags */
#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ #define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ #define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ #define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
/** /**
* @} * @}
*/ */
/** @defgroup CAN_interrupts CAN interrupts /** @defgroup CAN_interrupts CAN Interrupts
* @{ * @{
*/ */
#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ #define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
@ -487,39 +489,39 @@ typedef struct
*/ */
/** @brief Reset CAN handle state /** @brief Reset CAN handle state
* @param __HANDLE__: CAN handle. * @param __HANDLE__ CAN handle.
* @retval None * @retval None
*/ */
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
/** /**
* @brief Enable the specified CAN interrupts. * @brief Enable the specified CAN interrupts.
* @param __HANDLE__: CAN handle. * @param __HANDLE__ CAN handle.
* @param __INTERRUPT__: CAN Interrupt * @param __INTERRUPT__ CAN Interrupt
* @retval None * @retval None
*/ */
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
/** /**
* @brief Disable the specified CAN interrupts. * @brief Disable the specified CAN interrupts.
* @param __HANDLE__: CAN handle. * @param __HANDLE__ CAN handle.
* @param __INTERRUPT__: CAN Interrupt * @param __INTERRUPT__ CAN Interrupt
* @retval None * @retval None
*/ */
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
/** /**
* @brief Return the number of pending received messages. * @brief Return the number of pending received messages.
* @param __HANDLE__: CAN handle. * @param __HANDLE__ CAN handle.
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
* @retval The number of pending message. * @retval The number of pending message.
*/ */
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U))) ((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U)))
/** @brief Check whether the specified CAN flag is set or not. /** @brief Check whether the specified CAN flag is set or not.
* @param __HANDLE__: specifies the CAN Handle. * @param __HANDLE__ specifies the CAN Handle.
* @param __FLAG__: specifies the flag to check. * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
@ -552,8 +554,8 @@ typedef struct
((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
/** @brief Clear the specified CAN pending flag. /** @brief Clear the specified CAN pending flag.
* @param __HANDLE__: specifies the CAN Handle. * @param __HANDLE__ specifies the CAN Handle.
* @param __FLAG__: specifies the flag to check. * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
@ -581,12 +583,12 @@ typedef struct
((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0) (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
/** @brief Check if the specified CAN interrupt source is enabled or disabled. /** @brief Check if the specified CAN interrupt source is enabled or disabled.
* @param __HANDLE__: specifies the CAN Handle. * @param __HANDLE__ specifies the CAN Handle.
* @param __INTERRUPT__: specifies the CAN interrupt source to check. * @param __INTERRUPT__ specifies the CAN interrupt source to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
* @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
@ -597,21 +599,19 @@ typedef struct
/** /**
* @brief Check the transmission status of a CAN Frame. * @brief Check the transmission status of a CAN Frame.
* @param __HANDLE__: CAN handle. * @param __HANDLE__ CAN handle.
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
* @retval The new status of transmission (TRUE or FALSE). * @retval The new status of transmission (TRUE or FALSE).
*/ */
#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
/** /**
* @brief Release the specified receive FIFO. * @brief Release the specified receive FIFO.
* @param __HANDLE__: CAN handle. * @param __HANDLE__ CAN handle.
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
* @retval None * @retval None
*/ */
#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
@ -619,8 +619,8 @@ typedef struct
/** /**
* @brief Cancel a transmit request. * @brief Cancel a transmit request.
* @param __HANDLE__: specifies the CAN Handle. * @param __HANDLE__ specifies the CAN Handle.
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
* @retval None * @retval None
*/ */
#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
@ -630,8 +630,8 @@ typedef struct
/** /**
* @brief Enable or disables the DBG Freeze for CAN. * @brief Enable or disables the DBG Freeze for CAN.
* @param __HANDLE__: specifies the CAN Handle. * @param __HANDLE__ specifies the CAN Handle.
* @param __NEWSTATE__: new state of the CAN peripheral. * @param __NEWSTATE__ new state of the CAN peripheral.
* This parameter can be: ENABLE (CAN reception/transmission is frozen * This parameter can be: ENABLE (CAN reception/transmission is frozen
* during debug. Reception FIFOs can still be accessed/controlled normally) * during debug. Reception FIFOs can still be accessed/controlled normally)
* or DISABLE (CAN is working during debug). * or DISABLE (CAN is working during debug).
@ -668,7 +668,6 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
* @brief I/O operation functions * @brief I/O operation functions
* @{ * @{
*/ */
/* IO operation functions *****************************************************/ /* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
@ -676,9 +675,7 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, u
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
@ -693,7 +690,6 @@ void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
/* Peripheral State and Error functions ***************************************/ /* Peripheral State and Error functions ***************************************/
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
/** /**
* @} * @}
*/ */
@ -730,27 +726,37 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
* @} * @}
*/ */
/* Private macros ------------------------------------------------------------*/ /* Private Macros -----------------------------------------------------------*/
/** @defgroup CAN_Private_Macros CAN Private Macros /** @defgroup CAN_Private_Macros CAN Private Macros
* @{ * @{
*/ */
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
((MODE) == CAN_MODE_LOOPBACK)|| \ ((MODE) == CAN_MODE_LOOPBACK)|| \
((MODE) == CAN_MODE_SILENT) || \ ((MODE) == CAN_MODE_SILENT) || \
((MODE) == CAN_MODE_SILENT_LOOPBACK)) ((MODE) == CAN_MODE_SILENT_LOOPBACK))
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
((MODE) == CAN_FILTERMODE_IDLIST)) ((MODE) == CAN_FILTERMODE_IDLIST))
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
((SCALE) == CAN_FILTERSCALE_32BIT)) ((SCALE) == CAN_FILTERSCALE_32BIT))
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
((FIFO) == CAN_FILTER_FIFO1)) ((FIFO) == CAN_FILTER_FIFO1))
#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U)) #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
#define IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU)) #define IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU))
@ -759,21 +765,30 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
((IDTYPE) == CAN_ID_EXT)) ((IDTYPE) == CAN_ID_EXT))
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
/** #define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
* @} ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
*/ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
/* Private functions ---------------------------------------------------------*/ #define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
/** @defgroup CAN_Private_Functions CAN Private Functions ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
* @{ ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
*/ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
/** /**
* @} * @}
*/ */
/* End of private macros -----------------------------------------------------*/
/** /**
* @} * @}
@ -793,4 +808,3 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

70
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.c
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_cec.c * @file stm32f0xx_hal_cec.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief CEC HAL module driver. * @brief CEC HAL module driver.
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
* functionalities of the High Definition Multimedia Interface * functionalities of the High Definition Multimedia Interface
@ -78,6 +76,13 @@
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h" #include "stm32f0xx_hal.h"
#ifdef HAL_CEC_MODULE_ENABLED
#if defined(STM32F042x6) || defined(STM32F048xx) ||\
defined(STM32F051x8) || defined(STM32F058xx) ||\
defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||\
defined(STM32F091xC) || defined (STM32F098xx)
/** @addtogroup STM32F0xx_HAL_Driver /** @addtogroup STM32F0xx_HAL_Driver
* @{ * @{
*/ */
@ -86,12 +91,7 @@
* @brief HAL CEC module driver * @brief HAL CEC module driver
* @{ * @{
*/ */
#ifdef HAL_CEC_MODULE_ENABLED
#if defined(STM32F042x6) || defined(STM32F048xx) ||\
defined(STM32F051x8) || defined(STM32F058xx) ||\
defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||\
defined(STM32F091xC) || defined (STM32F098xx)
/* Private typedef -----------------------------------------------------------*/ /* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/
/** @defgroup CEC_Private_Constants CEC Private Constants /** @defgroup CEC_Private_Constants CEC Private Constants
@ -144,7 +144,7 @@
/** /**
* @brief Initializes the CEC mode according to the specified * @brief Initializes the CEC mode according to the specified
* parameters in the CEC_InitTypeDef and creates the associated handle . * parameters in the CEC_InitTypeDef and creates the associated handle .
* @param hcec: CEC handle * @param hcec CEC handle
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
@ -214,7 +214,7 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
/** /**
* @brief DeInitializes the CEC peripheral * @brief DeInitializes the CEC peripheral
* @param hcec: CEC handle * @param hcec CEC handle
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
@ -267,8 +267,8 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
/** /**
* @brief Initializes the Own Address of the CEC device * @brief Initializes the Own Address of the CEC device
* @param hcec: CEC handle * @param hcec CEC handle
* @param CEC_OwnAddress: The CEC own address. * @param CEC_OwnAddress The CEC own address.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress) HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
@ -314,7 +314,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
/** /**
* @brief CEC MSP Init * @brief CEC MSP Init
* @param hcec: CEC handle * @param hcec CEC handle
* @retval None * @retval None
*/ */
__weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec) __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
@ -328,7 +328,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
/** /**
* @brief CEC MSP DeInit * @brief CEC MSP DeInit
* @param hcec: CEC handle * @param hcec CEC handle
* @retval None * @retval None
*/ */
__weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec) __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
@ -380,11 +380,11 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
/** /**
* @brief Send data in interrupt mode * @brief Send data in interrupt mode
* @param hcec: CEC handle * @param hcec CEC handle
* @param InitiatorAddress: Initiator address * @param InitiatorAddress Initiator address
* @param DestinationAddress: destination logical address * @param DestinationAddress destination logical address
* @param pData: pointer to input byte data buffer * @param pData pointer to input byte data buffer
* @param Size: amount of data to be sent in bytes (without counting the header). * @param Size amount of data to be sent in bytes (without counting the header).
* 0 means only the header is sent (ping operation). * 0 means only the header is sent (ping operation).
* Maximum TX size is 15 bytes (1 opcode and up to 14 operands). * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
* @retval HAL status * @retval HAL status
@ -440,7 +440,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Initiator
/** /**
* @brief Get size of the received frame. * @brief Get size of the received frame.
* @param hcec: CEC handle * @param hcec CEC handle
* @retval Frame size * @retval Frame size
*/ */
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
@ -450,8 +450,8 @@ uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
/** /**
* @brief Change Rx Buffer. * @brief Change Rx Buffer.
* @param hcec: CEC handle * @param hcec CEC handle
* @param Rxbuffer: Rx Buffer * @param Rxbuffer Rx Buffer
* @note This function can be called only inside the HAL_CEC_RxCpltCallback() * @note This function can be called only inside the HAL_CEC_RxCpltCallback()
* @retval Frame size * @retval Frame size
*/ */
@ -462,7 +462,7 @@ void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
/** /**
* @brief This function handles CEC interrupt requests. * @brief This function handles CEC interrupt requests.
* @param hcec: CEC handle * @param hcec CEC handle
* @retval None * @retval None
*/ */
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
@ -567,7 +567,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
/** /**
* @brief Tx Transfer completed callback * @brief Tx Transfer completed callback
* @param hcec: CEC handle * @param hcec CEC handle
* @retval None * @retval None
*/ */
__weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec) __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
@ -581,8 +581,8 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
/** /**
* @brief Rx Transfer completed callback * @brief Rx Transfer completed callback
* @param hcec: CEC handle * @param hcec CEC handle
* @param RxFrameSize: Size of frame * @param RxFrameSize Size of frame
* @retval None * @retval None
*/ */
__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize) __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
@ -597,7 +597,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize
/** /**
* @brief CEC error callbacks * @brief CEC error callbacks
* @param hcec: CEC handle * @param hcec CEC handle
* @retval None * @retval None
*/ */
__weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
@ -628,7 +628,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize
*/ */
/** /**
* @brief return the CEC state * @brief return the CEC state
* @param hcec: pointer to a CEC_HandleTypeDef structure that contains * @param hcec pointer to a CEC_HandleTypeDef structure that contains
* the configuration information for the specified CEC module. * the configuration information for the specified CEC module.
* @retval HAL state * @retval HAL state
*/ */
@ -643,7 +643,7 @@ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
/** /**
* @brief Return the CEC error code * @brief Return the CEC error code
* @param hcec : pointer to a CEC_HandleTypeDef structure that contains * @param hcec pointer to a CEC_HandleTypeDef structure that contains
* the configuration information for the specified CEC. * the configuration information for the specified CEC.
* @retval CEC Error Code * @retval CEC Error Code
*/ */
@ -660,17 +660,17 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
* @} * @}
*/ */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F051x8) || defined(STM32F058xx) || */ #endif /* defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F051x8) || defined(STM32F058xx) || */
/* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */ /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */
/* defined(STM32F091xC) || defined (STM32F098xx) */ /* defined(STM32F091xC) || defined (STM32F098xx) */
#endif /* HAL_CEC_MODULE_ENABLED */ #endif /* HAL_CEC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

48
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_cec.h * @file stm32f0xx_hal_cec.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Header file of CEC HAL module. * @brief Header file of CEC HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
@ -431,7 +429,7 @@ typedef struct
*/ */
/** @brief Reset CEC handle gstate & RxState /** @brief Reset CEC handle gstate & RxState
* @param __HANDLE__: CEC handle. * @param __HANDLE__ CEC handle.
* @retval None * @retval None
*/ */
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
@ -440,8 +438,8 @@ typedef struct
} while(0) } while(0)
/** @brief Checks whether or not the specified CEC interrupt flag is set. /** @brief Checks whether or not the specified CEC interrupt flag is set.
* @param __HANDLE__: specifies the CEC Handle. * @param __HANDLE__ specifies the CEC Handle.
* @param __FLAG__: specifies the flag to check. * @param __FLAG__ specifies the flag to check.
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
* @arg CEC_FLAG_TXERR: Tx Error. * @arg CEC_FLAG_TXERR: Tx Error.
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
@ -460,8 +458,8 @@ typedef struct
#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
/** @brief Clears the interrupt or status flag when raised (write at 1) /** @brief Clears the interrupt or status flag when raised (write at 1)
* @param __HANDLE__: specifies the CEC Handle. * @param __HANDLE__ specifies the CEC Handle.
* @param __FLAG__: specifies the interrupt/status flag to clear. * @param __FLAG__ specifies the interrupt/status flag to clear.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
* @arg CEC_FLAG_TXERR: Tx Error. * @arg CEC_FLAG_TXERR: Tx Error.
@ -481,8 +479,8 @@ typedef struct
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__)) #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
/** @brief Enables the specified CEC interrupt. /** @brief Enables the specified CEC interrupt.
* @param __HANDLE__: specifies the CEC Handle. * @param __HANDLE__ specifies the CEC Handle.
* @param __INTERRUPT__: specifies the CEC interrupt to enable. * @param __INTERRUPT__ specifies the CEC interrupt to enable.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable * @arg CEC_IT_TXERR: Tx Error IT Enable
@ -502,8 +500,8 @@ typedef struct
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/** @brief Disables the specified CEC interrupt. /** @brief Disables the specified CEC interrupt.
* @param __HANDLE__: specifies the CEC Handle. * @param __HANDLE__ specifies the CEC Handle.
* @param __INTERRUPT__: specifies the CEC interrupt to disable. * @param __INTERRUPT__ specifies the CEC interrupt to disable.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable * @arg CEC_IT_TXERR: Tx Error IT Enable
@ -523,8 +521,8 @@ typedef struct
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
/** @brief Checks whether or not the specified CEC interrupt is enabled. /** @brief Checks whether or not the specified CEC interrupt is enabled.
* @param __HANDLE__: specifies the CEC Handle. * @param __HANDLE__ specifies the CEC Handle.
* @param __INTERRUPT__: specifies the CEC interrupt to check. * @param __INTERRUPT__ specifies the CEC interrupt to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable * @arg CEC_IT_TXERR: Tx Error IT Enable
@ -544,52 +542,52 @@ typedef struct
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
/** @brief Enables the CEC device /** @brief Enables the CEC device
* @param __HANDLE__: specifies the CEC Handle. * @param __HANDLE__ specifies the CEC Handle.
* @retval none * @retval none
*/ */
#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN) #define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
/** @brief Disables the CEC device /** @brief Disables the CEC device
* @param __HANDLE__: specifies the CEC Handle. * @param __HANDLE__ specifies the CEC Handle.
* @retval none * @retval none
*/ */
#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN) #define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
/** @brief Set Transmission Start flag /** @brief Set Transmission Start flag
* @param __HANDLE__: specifies the CEC Handle. * @param __HANDLE__ specifies the CEC Handle.
* @retval none * @retval none
*/ */
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM) #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
/** @brief Set Transmission End flag /** @brief Set Transmission End flag
* @param __HANDLE__: specifies the CEC Handle. * @param __HANDLE__ specifies the CEC Handle.
* @retval none * @retval none
* If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
*/ */
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM) #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
/** @brief Get Transmission Start flag /** @brief Get Transmission Start flag
* @param __HANDLE__: specifies the CEC Handle. * @param __HANDLE__ specifies the CEC Handle.
* @retval FlagStatus * @retval FlagStatus
*/ */
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM) #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
/** @brief Get Transmission End flag /** @brief Get Transmission End flag
* @param __HANDLE__: specifies the CEC Handle. * @param __HANDLE__ specifies the CEC Handle.
* @retval FlagStatus * @retval FlagStatus
*/ */
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM) #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
/** @brief Clear OAR register /** @brief Clear OAR register
* @param __HANDLE__: specifies the CEC Handle. * @param __HANDLE__ specifies the CEC Handle.
* @retval none * @retval none
*/ */
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR) #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
/** @brief Set OAR register (without resetting previously set address in case of multi-address mode) /** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
* To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
* @param __HANDLE__: specifies the CEC Handle. * @param __HANDLE__ specifies the CEC Handle.
* @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position) * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
* @retval none * @retval none
*/ */
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
@ -704,21 +702,21 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
* The message size is the payload size: without counting the header, * The message size is the payload size: without counting the header,
* it varies from 0 byte (ping operation, one header only, no payload) to * it varies from 0 byte (ping operation, one header only, no payload) to
* 15 bytes (1 opcode and up to 14 operands following the header). * 15 bytes (1 opcode and up to 14 operands following the header).
* @param __SIZE__: CEC message size. * @param __SIZE__ CEC message size.
* @retval Test result (TRUE or FALSE). * @retval Test result (TRUE or FALSE).
*/ */
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U) #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
/** @brief Check CEC device Own Address Register (OAR) setting. /** @brief Check CEC device Own Address Register (OAR) setting.
* OAR address is written in a 15-bit field within CEC_CFGR register. * OAR address is written in a 15-bit field within CEC_CFGR register.
* @param __ADDRESS__: CEC own address. * @param __ADDRESS__ CEC own address.
* @retval Test result (TRUE or FALSE). * @retval Test result (TRUE or FALSE).
*/ */
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU) #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
/** @brief Check CEC initiator or destination logical address setting. /** @brief Check CEC initiator or destination logical address setting.
* Initiator and destination addresses are coded over 4 bits. * Initiator and destination addresses are coded over 4 bits.
* @param __ADDRESS__: CEC initiator or logical address. * @param __ADDRESS__ CEC initiator or logical address.
* @retval Test result (TRUE or FALSE). * @retval Test result (TRUE or FALSE).
*/ */
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU) #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU)

32
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.c
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_comp.c * @file stm32f0xx_hal_comp.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief COMP HAL module driver. * @brief COMP HAL module driver.
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
* functionalities of the COMP peripheral: * functionalities of the COMP peripheral:
@ -188,7 +186,7 @@
/* Literal set to maximum value (refer to device datasheet, */ /* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART"). */ /* parameter "tSTART"). */
/* Unit: us */ /* Unit: us */
#define LL_COMP_DELAY_STARTUP_US (60U) /*!< Delay for COMP startup time */ #define COMP_DELAY_STARTUP_US (60U) /*!< Delay for COMP startup time */
/* CSR register reset value */ /* CSR register reset value */
#define COMP_CSR_RESET_VALUE (0x00000000U) #define COMP_CSR_RESET_VALUE (0x00000000U)
@ -230,7 +228,7 @@
* parameters in the COMP_InitTypeDef and create the associated handle. * parameters in the COMP_InitTypeDef and create the associated handle.
* @note If the selected comparator is locked, initialization can't be performed. * @note If the selected comparator is locked, initialization can't be performed.
* To unlock the configuration, perform a system reset. * To unlock the configuration, perform a system reset.
* @param hcomp: COMP handle * @param hcomp COMP handle
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
@ -316,7 +314,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
* @brief DeInitializes the COMP peripheral * @brief DeInitializes the COMP peripheral
* @note Deinitialization can't be performed if the COMP configuration is locked. * @note Deinitialization can't be performed if the COMP configuration is locked.
* To unlock the configuration, perform a system reset. * To unlock the configuration, perform a system reset.
* @param hcomp: COMP handle * @param hcomp COMP handle
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
@ -357,7 +355,7 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
/** /**
* @brief Initializes the COMP MSP. * @brief Initializes the COMP MSP.
* @param hcomp: COMP handle * @param hcomp COMP handle
* @retval None * @retval None
*/ */
__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp) __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
@ -372,7 +370,7 @@ __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
/** /**
* @brief DeInitializes COMP MSP. * @brief DeInitializes COMP MSP.
* @param hcomp: COMP handle * @param hcomp COMP handle
* @retval None * @retval None
*/ */
__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
@ -406,7 +404,7 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
/** /**
* @brief Start the comparator * @brief Start the comparator
* @param hcomp: COMP handle * @param hcomp COMP handle
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
@ -438,7 +436,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
hcomp->State = HAL_COMP_STATE_BUSY; hcomp->State = HAL_COMP_STATE_BUSY;
/* Delay for COMP startup time */ /* Delay for COMP startup time */
wait_loop_index = (LL_COMP_DELAY_STARTUP_US * (SystemCoreClock / 1000000U)); wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / 1000000U));
while(wait_loop_index != 0U) while(wait_loop_index != 0U)
{ {
wait_loop_index--; wait_loop_index--;
@ -455,7 +453,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
/** /**
* @brief Stop the comparator * @brief Stop the comparator
* @param hcomp: COMP handle * @param hcomp COMP handle
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
@ -495,7 +493,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
/** /**
* @brief Enables the interrupt and starts the comparator * @brief Enables the interrupt and starts the comparator
* @param hcomp: COMP handle * @param hcomp COMP handle
* @retval HAL status. * @retval HAL status.
*/ */
HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
@ -542,7 +540,7 @@ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
/** /**
* @brief Disable the interrupt and Stop the comparator * @brief Disable the interrupt and Stop the comparator
* @param hcomp: COMP handle * @param hcomp COMP handle
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
@ -559,7 +557,7 @@ HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
/** /**
* @brief Comparator IRQ Handler * @brief Comparator IRQ Handler
* @param hcomp: COMP handle * @param hcomp COMP handle
* @retval HAL status * @retval HAL status
*/ */
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
@ -598,7 +596,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
/** /**
* @brief Lock the selected comparator configuration. * @brief Lock the selected comparator configuration.
* @param hcomp: COMP handle * @param hcomp COMP handle
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
@ -643,7 +641,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
* voltage than the inverting input * voltage than the inverting input
* - Comparator output is low when the non-inverting input is at a higher * - Comparator output is low when the non-inverting input is at a higher
* voltage than the inverting input * voltage than the inverting input
* @param hcomp: COMP handle * @param hcomp COMP handle
* @retval Returns the selected comparator output level: COMP_OUTPUTLEVEL_LOW or COMP_OUTPUTLEVEL_HIGH. * @retval Returns the selected comparator output level: COMP_OUTPUTLEVEL_LOW or COMP_OUTPUTLEVEL_HIGH.
* *
*/ */
@ -670,7 +668,7 @@ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
/** /**
* @brief Comparator callback. * @brief Comparator callback.
* @param hcomp: COMP handle * @param hcomp COMP handle
* @retval None * @retval None
*/ */
__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
@ -705,7 +703,7 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
/** /**
* @brief Return the COMP state * @brief Return the COMP state
* @param hcomp : COMP handle * @param hcomp COMP handle
* @retval HAL state * @retval HAL state
*/ */
uint32_t HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) uint32_t HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)

16
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_comp.h * @file stm32f0xx_hal_comp.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Header file of COMP HAL module. * @brief Header file of COMP HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
@ -262,14 +260,14 @@ typedef struct
*/ */
/** @brief Reset COMP handle state /** @brief Reset COMP handle state
* @param __HANDLE__: COMP handle. * @param __HANDLE__ COMP handle.
* @retval None * @retval None
*/ */
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
/** /**
* @brief Enable the specified comparator. * @brief Enable the specified comparator.
* @param __HANDLE__: COMP handle. * @param __HANDLE__ COMP handle.
* @retval None * @retval None
*/ */
#define __HAL_COMP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \ #define __HAL_COMP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \
@ -278,7 +276,7 @@ typedef struct
/** /**
* @brief Disable the specified comparator. * @brief Disable the specified comparator.
* @param __HANDLE__: COMP handle. * @param __HANDLE__ COMP handle.
* @retval None * @retval None
*/ */
#define __HAL_COMP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \ #define __HAL_COMP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \
@ -287,7 +285,7 @@ typedef struct
/** /**
* @brief Lock the specified comparator configuration. * @brief Lock the specified comparator configuration.
* @param __HANDLE__: COMP handle. * @param __HANDLE__ COMP handle.
* @retval None * @retval None
*/ */
#define __HAL_COMP_LOCK(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \ #define __HAL_COMP_LOCK(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \
@ -463,8 +461,8 @@ typedef struct
#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2) #define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2)
/** @brief Check whether the specified COMP flag is set or not. /** @brief Check whether the specified COMP flag is set or not.
* @param __HANDLE__: specifies the COMP Handle. * @param __HANDLE__ specifies the COMP Handle.
* @param __FLAG__: specifies the flag to check. * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg COMP_FLAG_LOCK: lock flag * @arg COMP_FLAG_LOCK: lock flag
* @retval The new state of __FLAG__ (TRUE or FALSE). * @retval The new state of __FLAG__ (TRUE or FALSE).
@ -564,7 +562,7 @@ uint32_t HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
*/ */
/** /**
* @brief Get the specified EXTI line for a comparator instance. * @brief Get the specified EXTI line for a comparator instance.
* @param __INSTANCE__: specifies the COMP instance. * @param __INSTANCE__ specifies the COMP instance.
* @retval value of @ref COMP_ExtiLine * @retval value of @ref COMP_ExtiLine
*/ */
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \ #define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \

40
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_conf.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_conf.h * @file stm32f0xx_hal_conf.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief HAL configuration file. * @brief HAL configuration file.
****************************************************************************** ******************************************************************************
* @attention * @attention
@ -85,7 +83,7 @@
* (when HSE is used as system clock source, directly or through the PLL). * (when HSE is used as system clock source, directly or through the PLL).
*/ */
#if !defined (HSE_VALUE) #if !defined (HSE_VALUE)
#define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */ #endif /* HSE_VALUE */
/** /**
@ -93,7 +91,7 @@
* Timeout value * Timeout value
*/ */
#if !defined (HSE_STARTUP_TIMEOUT) #if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */ #endif /* HSE_STARTUP_TIMEOUT */
/** /**
@ -102,7 +100,7 @@
* (when HSI is used as system clock source, directly or through the PLL). * (when HSI is used as system clock source, directly or through the PLL).
*/ */
#if !defined (HSI_VALUE) #if !defined (HSI_VALUE)
#define HSI_VALUE (8000000U) /*!< Value of the Internal oscillator in Hz*/ #define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */ #endif /* HSI_VALUE */
/** /**
@ -110,14 +108,14 @@
* Timeout value * Timeout value
*/ */
#if !defined (HSI_STARTUP_TIMEOUT) #if !defined (HSI_STARTUP_TIMEOUT)
#define HSI_STARTUP_TIMEOUT (5000U) /*!< Time out for HSI start up */ #define HSI_STARTUP_TIMEOUT 5000U /*!< Time out for HSI start up */
#endif /* HSI_STARTUP_TIMEOUT */ #endif /* HSI_STARTUP_TIMEOUT */
/** /**
* @brief Internal High Speed oscillator for ADC (HSI14) value. * @brief Internal High Speed oscillator for ADC (HSI14) value.
*/ */
#if !defined (HSI14_VALUE) #if !defined (HSI14_VALUE)
#define HSI14_VALUE (14000000U) /*!< Value of the Internal High Speed oscillator for ADC in Hz. #define HSI14_VALUE 14000000U /*!< Value of the Internal High Speed oscillator for ADC in Hz.
The real value may vary depending on the variations The real value may vary depending on the variations
in voltage and temperature. */ in voltage and temperature. */
#endif /* HSI14_VALUE */ #endif /* HSI14_VALUE */
@ -126,7 +124,7 @@
* @brief Internal High Speed oscillator for USB (HSI48) value. * @brief Internal High Speed oscillator for USB (HSI48) value.
*/ */
#if !defined (HSI48_VALUE) #if !defined (HSI48_VALUE)
#define HSI48_VALUE (48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz. #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB in Hz.
The real value may vary depending on the variations The real value may vary depending on the variations
in voltage and temperature. */ in voltage and temperature. */
#endif /* HSI48_VALUE */ #endif /* HSI48_VALUE */
@ -135,7 +133,7 @@
* @brief Internal Low Speed oscillator (LSI) value. * @brief Internal Low Speed oscillator (LSI) value.
*/ */
#if !defined (LSI_VALUE) #if !defined (LSI_VALUE)
#define LSI_VALUE (40000U) #define LSI_VALUE 40000U
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations The real value may vary depending on the variations
in voltage and temperature. */ in voltage and temperature. */
@ -143,14 +141,14 @@
* @brief External Low Speed oscillator (LSE) value. * @brief External Low Speed oscillator (LSE) value.
*/ */
#if !defined (LSE_VALUE) #if !defined (LSE_VALUE)
#define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */ #endif /* LSE_VALUE */
/** /**
* @brief Time out for LSE start up value in ms. * @brief Time out for LSE start up value in ms.
*/ */
#if !defined (LSE_STARTUP_TIMEOUT) #if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */ #endif /* LSE_STARTUP_TIMEOUT */
@ -161,14 +159,15 @@
/** /**
* @brief This is the HAL system configuration section * @brief This is the HAL system configuration section
*/ */
#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ #define VDD_VALUE 3300U /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */ #define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */
/* Warning: Must be set to higher priority for HAL_Delay() */ /* Warning: Must be set to higher priority for HAL_Delay() */
/* and HAL_GetTick() usage under interrupt context */ /* and HAL_GetTick() usage under interrupt context */
#define USE_RTOS 0 #define USE_RTOS 0U
#define PREFETCH_ENABLE 1 #define PREFETCH_ENABLE 1U
#define INSTRUCTION_CACHE_ENABLE 0 #define INSTRUCTION_CACHE_ENABLE 0U
#define DATA_CACHE_ENABLE 0 #define DATA_CACHE_ENABLE 0U
#define USE_SPI_CRC 1U
/* ########################## Assert Selection ############################## */ /* ########################## Assert Selection ############################## */
/** /**
@ -177,15 +176,6 @@
*/ */
/*#define USE_FULL_ASSERT 1*/ /*#define USE_FULL_ASSERT 1*/
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 1U
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
/** /**
* @brief Include module's header file * @brief Include module's header file

16
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.c
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_cortex.c * @file stm32f0xx_hal_cortex.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief CORTEX HAL module driver. * @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
* functionalities of the CORTEX: * functionalities of the CORTEX:
@ -140,13 +138,13 @@
/** /**
* @brief Sets the priority of an interrupt. * @brief Sets the priority of an interrupt.
* @param IRQn: External interrupt number . * @param IRQn External interrupt number .
* This parameter can be an enumerator of IRQn_Type enumeration * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file) * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f0xx.h file)
* @param PreemptPriority: The preemption priority for the IRQn channel. * @param PreemptPriority The preemption priority for the IRQn channel.
* This parameter can be a value between 0 and 3. * This parameter can be a value between 0 and 3.
* A lower priority value indicates a higher priority * A lower priority value indicates a higher priority
* @param SubPriority: the subpriority level for the IRQ channel. * @param SubPriority the subpriority level for the IRQ channel.
* with stm32f0xx devices, this parameter is a dummy value and it is ignored, because * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because
* no subpriority supported in Cortex M0 based products. * no subpriority supported in Cortex M0 based products.
* @retval None * @retval None
@ -205,7 +203,7 @@ void HAL_NVIC_SystemReset(void)
/** /**
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
* Counter is in free running mode to generate periodic interrupts. * Counter is in free running mode to generate periodic interrupts.
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded. * @retval status: - 0 Function succeeded.
* - 1 Function failed. * - 1 Function failed.
*/ */
@ -236,7 +234,7 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
/** /**
* @brief Gets the priority of an interrupt. * @brief Gets the priority of an interrupt.
* @param IRQn: External interrupt number. * @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
* @retval None * @retval None
@ -299,7 +297,7 @@ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
/** /**
* @brief Configures the SysTick clock source. * @brief Configures the SysTick clock source.
* @param CLKSource: specifies the SysTick clock source. * @param CLKSource specifies the SysTick clock source.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.

2
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_cortex.h * @file stm32f0xx_hal_cortex.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Header file of CORTEX HAL module. * @brief Header file of CORTEX HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention

114
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.c
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_crc.c * @file stm32f0xx_hal_crc.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief CRC HAL module driver. * @brief CRC HAL module driver.
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral: * functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@ -16,16 +14,16 @@
##### How to use this driver ##### ##### How to use this driver #####
=============================================================================== ===============================================================================
[..] [..]
(#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE(); (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
(#) Initialize CRC calculator (+) Initialize CRC calculator
(++)specify generating polynomial (IP default or non-default one) (++)specify generating polynomial (IP default or non-default one)
(++)specify initialization value (IP default or non-default one) (++)specify initialization value (IP default or non-default one)
(++)specify input data format (++)specify input data format
(++)specify input or output data inversion mode if any (++)specify input or output data inversion mode if any
(#) Use HAL_CRC_Accumulate() function to compute the CRC value of the (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
input data buffer starting with the previously computed CRC as input data buffer starting with the previously computed CRC as
initialization value initialization value
(#) Use HAL_CRC_Calculate() function to compute the CRC value of the (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
input data buffer starting with the defined initialization value input data buffer starting with the defined initialization value
(default or non-default) to initiate CRC calculation (default or non-default) to initiate CRC calculation
@ -88,7 +86,8 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
* @} * @}
*/ */
/* Exported functions ---------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions /** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{ * @{
*/ */
@ -98,23 +97,23 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
##### Initialization and Configuration functions ##### ##### Initialization and de-initialization functions #####
=============================================================================== ===============================================================================
[..] This section provides functions allowing to: [..] This section provides functions allowing to:
(+) Initialize the CRC according to the specified parameters (+) Initialize the CRC according to the specified parameters
in the CRC_InitTypeDef and create the associated handle in the CRC_InitTypeDef and create the associated handle
(+) DeInitialize the CRC peripheral (+) DeInitialize the CRC peripheral
(+) Initialize the CRC MSP (+) Initialize the CRC MSP (MCU Specific Package)
(+) DeInitialize CRC MSP (+) DeInitialize the CRC MSP
@endverbatim @endverbatim
* @{ * @{
*/ */
/** /**
* @brief Initializes the CRC according to the specified * @brief Initialize the CRC according to the specified
* parameters in the CRC_InitTypeDef and creates the associated handle. * parameters in the CRC_InitTypeDef and initialize the associated handle.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
@ -132,6 +131,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{ {
/* Allocate lock resource and initialize it */ /* Allocate lock resource and initialize it */
hcrc->Lock = HAL_UNLOCKED; hcrc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */ /* Init the low level hardware */
HAL_CRC_MspInit(hcrc); HAL_CRC_MspInit(hcrc);
} }
@ -181,8 +181,8 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
} }
/** /**
* @brief DeInitializes the CRC peripheral. * @brief DeInitialize the CRC peripheral.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
@ -205,6 +205,9 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
/* Change CRC peripheral state */ /* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY; hcrc->State = HAL_CRC_STATE_BUSY;
/* Reset CRC calculation unit */
__HAL_CRC_DR_RESET(hcrc);
/* Reset IDR register content */ /* Reset IDR register content */
CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ; CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ;
@ -223,7 +226,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
/** /**
* @brief Initializes the CRC MSP. * @brief Initializes the CRC MSP.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @retval None * @retval None
*/ */
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
@ -237,8 +240,8 @@ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
} }
/** /**
* @brief DeInitializes the CRC MSP. * @brief DeInitialize the CRC MSP.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @retval None * @retval None
*/ */
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
@ -263,12 +266,12 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
##### Peripheral Control functions ##### ##### Peripheral Control functions #####
=============================================================================== ===============================================================================
[..] This section provides functions allowing to: [..] This section provides functions allowing to:
(+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer
using combination of the previous CRC value and the new one. using the combination of the previous CRC value and the new one
or [..] or
(+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer
independently of the previous CRC value. independently of the previous CRC value.
@endverbatim @endverbatim
@ -278,10 +281,10 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
/** /**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with the previously computed CRC as initialization value. * starting with the previously computed CRC as initialization value.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @param pBuffer: pointer to the input data buffer, exact input data format is * @param pBuffer pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat. * provided by hcrc->InputDataFormat.
* @param BufferLength: input data buffer length (number of bytes if pBuffer * @param BufferLength input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t). * number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter. * @note By default, the API expects a uint32_t pointer as input buffer parameter.
@ -338,10 +341,10 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
/** /**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with hcrc->Instance->INIT as initialization value. * starting with hcrc->Instance->INIT as initialization value.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @param pBuffer: pointer to the input data buffer, exact input data format is * @param pBuffer pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat. * provided by hcrc->InputDataFormat.
* @param BufferLength: input data buffer length (number of bytes if pBuffer * @param BufferLength input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t). * number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter. * @note By default, the API expects a uint32_t pointer as input buffer parameter.
@ -399,6 +402,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
/* Return the CRC computed value */ /* Return the CRC computed value */
return temp; return temp;
} }
/** /**
* @} * @}
*/ */
@ -411,20 +415,20 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
##### Peripheral State functions ##### ##### Peripheral State functions #####
=============================================================================== ===============================================================================
[..] [..]
This subsection permits to get in run-time the status of the peripheral This subsection permits to get in run-time the status of the peripheral.
and the data flow.
@endverbatim @endverbatim
* @{ * @{
*/ */
/** /**
* @brief Returns the CRC state. * @brief Return the CRC handle state.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @retval HAL state * @retval HAL state
*/ */
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
{ {
/* Return CRC handle state */
return hcrc->State; return hcrc->State;
} }
@ -436,15 +440,16 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
* @} * @}
*/ */
/** @addtogroup CRC_Private_Functions CRC Private Functions /** @defgroup CRC_Private_Functions CRC Private Functions
* @{ * @{
*/ */
/** /**
* @brief Enter 8-bit input data to the CRC calculator. * @brief Enter 8-bit input data to the CRC calculator.
* Specific data handling to optimize processing time. * Specific data handling to optimize processing time.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @param pBuffer: pointer to the input data buffer * @param pBuffer pointer to the input data buffer
* @param BufferLength: input data buffer length * @param BufferLength input data buffer length
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/ */
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
@ -456,23 +461,23 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_
* handling by the IP */ * handling by the IP */
for(i = 0U; i < (BufferLength/4U); i++) for(i = 0U; i < (BufferLength/4U); i++)
{ {
hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24U) | ((uint32_t)pBuffer[4*i+1]<<16U) | ((uint32_t)pBuffer[4*i+2]<<8U) | (uint32_t)pBuffer[4*i+3]; hcrc->Instance->DR = ((uint32_t)pBuffer[4U*i]<<24U) | ((uint32_t)pBuffer[4U*i+1]<<16U) | ((uint32_t)pBuffer[4U*i+2]<<8U) | (uint32_t)pBuffer[4U*i+3];
} }
/* last bytes specific handling */ /* last bytes specific handling */
if ((BufferLength%4) != 0U) if ((BufferLength%4U) != 0U)
{ {
if (BufferLength%4 == 1U) if (BufferLength%4U == 1U)
{ {
*(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i]; *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i];
} }
if (BufferLength%4 == 2U) if (BufferLength%4U == 2U)
{ {
*(uint16_t*) (&hcrc->Instance->DR) = ((uint16_t)pBuffer[4*i]<<8U) | (uint16_t)pBuffer[4*i+1]; *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
} }
if (BufferLength%4 == 3U) if (BufferLength%4U == 3U)
{ {
*(uint16_t*) (&hcrc->Instance->DR) = ((uint16_t)pBuffer[4*i]<<8U) | (uint16_t)pBuffer[4*i+1]; *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
*(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
} }
} }
@ -485,33 +490,30 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_
/** /**
* @brief Enter 16-bit input data to the CRC calculator. * @brief Enter 16-bit input data to the CRC calculator.
* Specific data handling to optimize processing time. * Specific data handling to optimize processing time.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @param pBuffer: pointer to the input data buffer * @param pBuffer pointer to the input data buffer
* @param BufferLength: input data buffer length * @param BufferLength input data buffer length
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/ */
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
{ {
uint32_t i = 0; /* input data buffer index */ uint32_t i = 0U; /* input data buffer index */
/* Processing time optimization: 2 HalfWords are entered in a row with a single word write, /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
* in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
* a correct type handling by the IP */ * a correct type handling by the IP */
for(i = 0; i < (BufferLength/2); i++) for(i = 0U; i < (BufferLength/2U); i++)
{ {
hcrc->Instance->DR = (pBuffer[2*i]<<16U) | pBuffer[2*i+1]; hcrc->Instance->DR = ((uint32_t)pBuffer[2U*i]<<16U) | (uint32_t)pBuffer[2U*i+1];
} }
if ((BufferLength%2) != 0U) if ((BufferLength%2U) != 0U)
{ {
*(uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i];
} }
/* Return the CRC computed value */ /* Return the CRC computed value */
return hcrc->Instance->DR; return hcrc->Instance->DR;
} }
/**
* @}
*/
/** /**
* @} * @}

16
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_crc.h * @file stm32f0xx_hal_crc.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Header file of CRC HAL module. * @brief Header file of CRC HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
@ -224,37 +222,37 @@ typedef struct
*/ */
/** @brief Reset CRC handle state /** @brief Reset CRC handle state
* @param __HANDLE__: CRC handle. * @param __HANDLE__ CRC handle.
* @retval None * @retval None
*/ */
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
/** /**
* @brief Reset CRC Data Register. * @brief Reset CRC Data Register.
* @param __HANDLE__: CRC handle * @param __HANDLE__ CRC handle
* @retval None. * @retval None.
*/ */
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
/** /**
* @brief Set CRC INIT non-default value * @brief Set CRC INIT non-default value
* @param __HANDLE__ : CRC handle * @param __HANDLE__ CRC handle
* @param __INIT__ : 32-bit initial value * @param __INIT__ 32-bit initial value
* @retval None. * @retval None.
*/ */
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
/** /**
* @brief Stores a 8-bit data in the Independent Data(ID) register. * @brief Stores a 8-bit data in the Independent Data(ID) register.
* @param __HANDLE__: CRC handle * @param __HANDLE__ CRC handle
* @param __VALUE__: 8-bit value to be stored in the ID register * @param __VALUE__ 8-bit value to be stored in the ID register
* @retval None * @retval None
*/ */
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
/** /**
* @brief Returns the 8-bit data stored in the Independent Data(ID) register. * @brief Returns the 8-bit data stored in the Independent Data(ID) register.
* @param __HANDLE__: CRC handle * @param __HANDLE__ CRC handle
* @retval 8-bit value of the ID register * @retval 8-bit value of the ID register
*/ */
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)

18
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.c
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_crc_ex.c * @file stm32f0xx_hal_crc_ex.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Extended CRC HAL module driver. * @brief Extended CRC HAL module driver.
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
* functionalities of the CRC peripheral: * functionalities of the CRC peripheral:
@ -96,7 +94,7 @@
/** /**
* @brief Extended initialization to set generating polynomial * @brief Extended initialization to set generating polynomial
* @param hcrc: CRC handle * @param hcrc CRC handle
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_CRCEx_Init(CRC_HandleTypeDef *hcrc) HAL_StatusTypeDef HAL_CRCEx_Init(CRC_HandleTypeDef *hcrc)
@ -126,8 +124,8 @@ HAL_StatusTypeDef HAL_CRCEx_Init(CRC_HandleTypeDef *hcrc)
/** /**
* @brief Set the Reverse Input data mode. * @brief Set the Reverse Input data mode.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @param InputReverseMode: Input Data inversion mode * @param InputReverseMode Input Data inversion mode
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg CRC_INPUTDATA_NOINVERSION: no change in bit order (default value) * @arg CRC_INPUTDATA_NOINVERSION: no change in bit order (default value)
* @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal * @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
@ -154,8 +152,8 @@ HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t
/** /**
* @brief Set the Reverse Output data mode. * @brief Set the Reverse Output data mode.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @param OutputReverseMode: Output Data inversion mode * @param OutputReverseMode Output Data inversion mode
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value) * @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
* @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD) * @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)
@ -182,12 +180,12 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_
#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F091xC) || defined (STM32F098xx) #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F091xC) || defined (STM32F098xx)
/** /**
* @brief Initializes the CRC polynomial if different from default one. * @brief Initializes the CRC polynomial if different from default one.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long) * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long)
* This parameter is written in normal representation, e.g. * This parameter is written in normal representation, e.g.
* for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 * for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 * for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
* @param PolyLength: CRC polynomial length * @param PolyLength CRC polynomial length
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7) * @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
* @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8) * @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)

10
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_crc_ex.h * @file stm32f0xx_hal_crc_ex.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Header file of CRC HAL extension module. * @brief Header file of CRC HAL extension module.
****************************************************************************** ******************************************************************************
* @attention * @attention
@ -133,14 +131,14 @@
/** /**
* @brief Set CRC output reversal * @brief Set CRC output reversal
* @param __HANDLE__ : CRC handle * @param __HANDLE__ CRC handle
* @retval None. * @retval None.
*/ */
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) #define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
/** /**
* @brief Unset CRC output reversal * @brief Unset CRC output reversal
* @param __HANDLE__ : CRC handle * @param __HANDLE__ CRC handle
* @retval None. * @retval None.
*/ */
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
@ -148,8 +146,8 @@
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
/** /**
* @brief Set CRC non-default polynomial * @brief Set CRC non-default polynomial
* @param __HANDLE__ : CRC handle * @param __HANDLE__ CRC handle
* @param __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
* @retval None. * @retval None.
*/ */
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__)) #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))

64
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.c
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_dac.c * @file stm32f0xx_hal_dac.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief DAC HAL module driver. * @brief DAC HAL module driver.
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral: * functionalities of the Digital to Analog Converter (DAC) peripheral:
@ -257,7 +255,7 @@
/** /**
* @brief Initialize the DAC peripheral according to the specified parameters * @brief Initialize the DAC peripheral according to the specified parameters
* in the DAC_InitStruct and initialize the associated handle. * in the DAC_InitStruct and initialize the associated handle.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval HAL status * @retval HAL status
*/ */
@ -295,7 +293,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
/** /**
* @brief Deinitialize the DAC peripheral registers to their default reset values. * @brief Deinitialize the DAC peripheral registers to their default reset values.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval HAL status * @retval HAL status
*/ */
@ -331,7 +329,7 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
/** /**
* @brief Initialize the DAC MSP. * @brief Initialize the DAC MSP.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval None * @retval None
*/ */
@ -347,7 +345,7 @@ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
/** /**
* @brief DeInitialize the DAC MSP. * @brief DeInitialize the DAC MSP.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval None * @retval None
*/ */
@ -385,9 +383,9 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
/** /**
* @brief Enables DAC and starts conversion of channel. * @brief Enables DAC and starts conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @param Channel: The selected DAC channel. * @param Channel The selected DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected
@ -408,9 +406,9 @@ __weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel
/** /**
* @brief Disables DAC and stop conversion of channel. * @brief Disables DAC and stop conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @param Channel: The selected DAC channel. * @param Channel The selected DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected
@ -433,15 +431,15 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
/** /**
* @brief Enables DAC and starts conversion of channel. * @brief Enables DAC and starts conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @param Channel: The selected DAC channel. * @param Channel The selected DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param pData: The destination peripheral Buffer address. * @param pData The destination peripheral Buffer address.
* @param Length: The length of data to be transferred from memory to DAC peripheral * @param Length The length of data to be transferred from memory to DAC peripheral
* @param Alignment: Specifies the data alignment for DAC channel. * @param Alignment Specifies the data alignment for DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
@ -466,9 +464,9 @@ __weak HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Cha
/** /**
* @brief Disables DAC and stop conversion of channel. * @brief Disables DAC and stop conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @param Channel: The selected DAC channel. * @param Channel The selected DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected
@ -531,7 +529,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
/** /**
* @brief Handles DAC interrupt request * @brief Handles DAC interrupt request
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval None * @retval None
*/ */
@ -546,18 +544,18 @@ __weak void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
/** /**
* @brief Set the specified data holding register value for DAC channel. * @brief Set the specified data holding register value for DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @param Channel: The selected DAC channel. * @param Channel The selected DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param Alignment: Specifies the data alignment. * @param Alignment Specifies the data alignment.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @param Data: Data to be loaded in the selected data holding register. * @param Data Data to be loaded in the selected data holding register.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
@ -588,7 +586,7 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui
/** /**
* @brief Conversion complete callback in non blocking mode for Channel1 * @brief Conversion complete callback in non blocking mode for Channel1
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval None * @retval None
*/ */
@ -604,7 +602,7 @@ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
/** /**
* @brief Conversion half DMA transfer callback in non-blocking mode for Channel1 * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval None * @retval None
*/ */
@ -620,7 +618,7 @@ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
/** /**
* @brief Error DAC callback for Channel1. * @brief Error DAC callback for Channel1.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval None * @retval None
*/ */
@ -636,7 +634,7 @@ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
/** /**
* @brief DMA underrun DAC callback for channel1. * @brief DMA underrun DAC callback for channel1.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval None * @retval None
*/ */
@ -671,9 +669,9 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
/** /**
* @brief Returns the last data output value of the selected DAC channel. * @brief Returns the last data output value of the selected DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @param Channel: The selected DAC channel. * @param Channel The selected DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected
@ -694,10 +692,10 @@ __weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
/** /**
* @brief Configures the selected DAC channel. * @brief Configures the selected DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @param sConfig: DAC configuration structure. * @param sConfig DAC configuration structure.
* @param Channel: The selected DAC channel. * @param Channel The selected DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected
@ -739,7 +737,7 @@ __weak HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_Chan
/** /**
* @brief return the DAC handle state * @brief return the DAC handle state
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval HAL state * @retval HAL state
*/ */
@ -752,7 +750,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
/** /**
* @brief Return the DAC error code * @brief Return the DAC error code
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval DAC Error Code * @retval DAC Error Code
*/ */

38
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_dac.h * @file stm32f0xx_hal_dac.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Header file of DAC HAL module. * @brief Header file of DAC HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
@ -180,30 +178,30 @@ typedef struct
*/ */
/** @brief Reset DAC handle state /** @brief Reset DAC handle state
* @param __HANDLE__: specifies the DAC handle. * @param __HANDLE__ specifies the DAC handle.
* @retval None * @retval None
*/ */
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
/** @brief Enable the DAC channel /** @brief Enable the DAC channel
* @param __HANDLE__: specifies the DAC handle. * @param __HANDLE__ specifies the DAC handle.
* @param __DAC_Channel__: specifies the DAC channel * @param __DAC_Channel__ specifies the DAC channel
* @retval None * @retval None
*/ */
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__))) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
/** @brief Disable the DAC channel /** @brief Disable the DAC channel
* @param __HANDLE__: specifies the DAC handle * @param __HANDLE__ specifies the DAC handle
* @param __DAC_Channel__: specifies the DAC channel. * @param __DAC_Channel__ specifies the DAC channel.
* @retval None * @retval None
*/ */
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__))) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
/** @brief Enable the DAC interrupt /** @brief Enable the DAC interrupt
* @param __HANDLE__: specifies the DAC handle * @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__: specifies the DAC interrupt. * @param __INTERRUPT__ specifies the DAC interrupt.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
@ -212,8 +210,8 @@ typedef struct
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
/** @brief Disable the DAC interrupt /** @brief Disable the DAC interrupt
* @param __HANDLE__: specifies the DAC handle * @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__: specifies the DAC interrupt. * @param __INTERRUPT__ specifies the DAC interrupt.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @retval None * @retval None
@ -221,8 +219,8 @@ typedef struct
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
/** @brief Check whether the specified DAC interrupt source is enabled or not /** @brief Check whether the specified DAC interrupt source is enabled or not
* @param __HANDLE__: DAC handle * @param __HANDLE__ DAC handle
* @param __INTERRUPT__: DAC interrupt source to check * @param __INTERRUPT__ DAC interrupt source to check
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
@ -231,8 +229,8 @@ typedef struct
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected DAC's flag status /** @brief Get the selected DAC's flag status
* @param __HANDLE__: specifies the DAC handle. * @param __HANDLE__ specifies the DAC handle.
* @param __FLAG__: specifies the DAC flag to get. * @param __FLAG__ specifies the DAC flag to get.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
* @retval None * @retval None
@ -240,8 +238,8 @@ typedef struct
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the DAC's flag /** @brief Clear the DAC's flag
* @param __HANDLE__: specifies the DAC handle. * @param __HANDLE__ specifies the DAC handle.
* @param __FLAG__: specifies the DAC flag to clear. * @param __FLAG__ specifies the DAC flag to clear.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
* @retval None * @retval None
@ -284,19 +282,19 @@ typedef struct
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
/** @brief Set DHR12R1 alignment /** @brief Set DHR12R1 alignment
* @param __ALIGNMENT__: specifies the DAC alignment * @param __ALIGNMENT__ specifies the DAC alignment
* @retval None * @retval None
*/ */
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__)) #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__))
/** @brief Set DHR12R2 alignment /** @brief Set DHR12R2 alignment
* @param __ALIGNMENT__: specifies the DAC alignment * @param __ALIGNMENT__ specifies the DAC alignment
* @retval None * @retval None
*/ */
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__)) #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__))
/** @brief Set DHR12RD alignment /** @brief Set DHR12RD alignment
* @param __ALIGNMENT__: specifies the DAC alignment * @param __ALIGNMENT__ specifies the DAC alignment
* @retval None * @retval None
*/ */
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__)) #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__))

94
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.c
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_dac_ex.c * @file stm32f0xx_hal_dac_ex.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief DAC HAL module driver. * @brief DAC HAL module driver.
* This file provides firmware functions to manage the extended * This file provides firmware functions to manage the extended
* functionalities of the DAC peripheral. * functionalities of the DAC peripheral.
@ -116,10 +114,10 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
/** /**
* @brief Configures the selected DAC channel. * @brief Configures the selected DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @param sConfig: DAC configuration structure. * @param sConfig DAC configuration structure.
* @param Channel: The selected DAC channel. * @param Channel The selected DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected
@ -171,10 +169,10 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf
/** /**
* @brief Configures the selected DAC channel. * @brief Configures the selected DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @param sConfig: DAC configuration structure. * @param sConfig DAC configuration structure.
* @param Channel: The selected DAC channel. * @param Channel The selected DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_1: DAC Channel1 selected
* @retval HAL status * @retval HAL status
@ -226,9 +224,9 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf
/** /**
* @brief Returns the last data output value of the selected DAC channel. * @brief Returns the last data output value of the selected DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @param Channel: The selected DAC channel. * @param Channel The selected DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected
@ -259,9 +257,9 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
/** /**
* @brief Returns the last data output value of the selected DAC channel. * @brief Returns the last data output value of the selected DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @param Channel: The selected DAC channel. * @param Channel The selected DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_1: DAC Channel1 selected
* @retval The selected DAC channel data output value. * @retval The selected DAC channel data output value.
@ -292,9 +290,9 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
/** /**
* @brief Enables DAC and starts conversion of channel. * @brief Enables DAC and starts conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @param Channel: The selected DAC channel. * @param Channel The selected DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected
@ -345,15 +343,15 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
/** /**
* @brief Enables DAC and starts conversion of channel. * @brief Enables DAC and starts conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @param Channel: The selected DAC channel. * @param Channel The selected DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param pData: The destination peripheral Buffer address. * @param pData The destination peripheral Buffer address.
* @param Length: The length of data to be transferred from memory to DAC peripheral * @param Length The length of data to be transferred from memory to DAC peripheral
* @param Alignment: Specifies the data alignment for DAC channel. * @param Alignment Specifies the data alignment for DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
@ -512,14 +510,14 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
/** /**
* @brief Enables DAC and starts conversion of channel. * @brief Enables DAC and starts conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @param Channel: The selected DAC channel. * @param Channel The selected DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_1: DAC Channel1 selected
* @param pData: The destination peripheral Buffer address. * @param pData The destination peripheral Buffer address.
* @param Length: The length of data to be transferred from memory to DAC peripheral * @param Length The length of data to be transferred from memory to DAC peripheral
* @param Alignment: Specifies the data alignment for DAC channel. * @param Alignment Specifies the data alignment for DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
@ -602,7 +600,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
/** /**
* @brief Handles DAC interrupt request * @brief Handles DAC interrupt request
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval None * @retval None
*/ */
@ -660,7 +658,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
/** /**
* @brief Handles DAC interrupt request * @brief Handles DAC interrupt request
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval None * @retval None
*/ */
@ -709,7 +707,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
/** /**
* @brief DMA conversion complete callback. * @brief DMA conversion complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module. * the configuration information for the specified DMA module.
* @retval None * @retval None
*/ */
@ -724,7 +722,7 @@ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
/** /**
* @brief DMA half transfer complete callback. * @brief DMA half transfer complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module. * the configuration information for the specified DMA module.
* @retval None * @retval None
*/ */
@ -737,7 +735,7 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
/** /**
* @brief DMA error callback * @brief DMA error callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module. * the configuration information for the specified DMA module.
* @retval None * @retval None
*/ */
@ -768,7 +766,7 @@ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
/** /**
* @brief DMA conversion complete callback. * @brief DMA conversion complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module. * the configuration information for the specified DMA module.
* @retval None * @retval None
*/ */
@ -783,7 +781,7 @@ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
/** /**
* @brief DMA half transfer complete callback. * @brief DMA half transfer complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module. * the configuration information for the specified DMA module.
* @retval None * @retval None
*/ */
@ -796,7 +794,7 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
/** /**
* @brief DMA error callback * @brief DMA error callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module. * the configuration information for the specified DMA module.
* @retval None * @retval None
*/ */
@ -870,7 +868,7 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
/** /**
* @brief Returns the last data output value of the selected DAC channel. * @brief Returns the last data output value of the selected DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval The selected DAC channel data output value. * @retval The selected DAC channel data output value.
*/ */
@ -894,7 +892,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
/** /**
* @brief Returns the last data output value of the selected DAC channel. * @brief Returns the last data output value of the selected DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval The selected DAC channel data output value. * @retval The selected DAC channel data output value.
*/ */
@ -915,12 +913,12 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
/** /**
* @brief Enables or disables the selected DAC channel wave generation. * @brief Enables or disables the selected DAC channel wave generation.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @param Channel: The selected DAC channel. * @param Channel The selected DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* DAC_CHANNEL_1 / DAC_CHANNEL_2 * DAC_CHANNEL_1 / DAC_CHANNEL_2
* @param Amplitude: Select max triangle amplitude. * @param Amplitude Select max triangle amplitude.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
* @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
@ -963,12 +961,12 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32
/** /**
* @brief Enables or disables the selected DAC channel wave generation. * @brief Enables or disables the selected DAC channel wave generation.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @param Channel: The selected DAC channel. * @param Channel The selected DAC channel.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* DAC_CHANNEL_1 / DAC_CHANNEL_2 * DAC_CHANNEL_1 / DAC_CHANNEL_2
* @param Amplitude: Unmask DAC channel LFSR for noise wave generation. * @param Amplitude Unmask DAC channel LFSR for noise wave generation.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
* @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
@ -1035,15 +1033,15 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
/** /**
* @brief Set the specified data holding register value for dual DAC channel. * @brief Set the specified data holding register value for dual DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @param Alignment: Specifies the data alignment for dual channel DAC. * @param Alignment Specifies the data alignment for dual channel DAC.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* DAC_ALIGN_8B_R: 8bit right data alignment selected * DAC_ALIGN_8B_R: 8bit right data alignment selected
* DAC_ALIGN_12B_L: 12bit left data alignment selected * DAC_ALIGN_12B_L: 12bit left data alignment selected
* DAC_ALIGN_12B_R: 12bit right data alignment selected * DAC_ALIGN_12B_R: 12bit right data alignment selected
* @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register. * @param Data1 Data for DAC Channel2 to be loaded in the selected data holding register.
* @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register. * @param Data2 Data for DAC Channel1 to be loaded in the selected data holding register.
* @note In dual mode, a unique register access is required to write in both * @note In dual mode, a unique register access is required to write in both
* DAC channels at the same time. * DAC channels at the same time.
* @retval HAL status * @retval HAL status
@ -1103,7 +1101,7 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align
/** /**
* @brief Conversion complete callback in non blocking mode for Channel2 * @brief Conversion complete callback in non blocking mode for Channel2
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval None * @retval None
*/ */
@ -1119,7 +1117,7 @@ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
/** /**
* @brief Conversion half DMA transfer callback in non blocking mode for Channel2 * @brief Conversion half DMA transfer callback in non blocking mode for Channel2
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval None * @retval None
*/ */
@ -1135,7 +1133,7 @@ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
/** /**
* @brief Error DAC callback for Channel2. * @brief Error DAC callback for Channel2.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval None * @retval None
*/ */
@ -1151,7 +1149,7 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
/** /**
* @brief DMA underrun DAC callback for channel2. * @brief DMA underrun DAC callback for channel2.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC. * the configuration information for the specified DAC.
* @retval None * @retval None
*/ */

2
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_dac_ex.h * @file stm32f0xx_hal_dac_ex.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Header file of DAC HAL Extension module. * @brief Header file of DAC HAL Extension module.
****************************************************************************** ******************************************************************************
* @attention * @attention

8
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_def.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_def.h * @file stm32f0xx_hal_def.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief This file contains HAL common defines, enumeration, macros and * @brief This file contains HAL common defines, enumeration, macros and
* structures definitions. * structures definitions.
****************************************************************************** ******************************************************************************
@ -46,7 +44,9 @@
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f0xx.h" #include "stm32f0xx.h"
#if defined(USE_HAL_LEGACY)
#include "stm32_hal_legacy.h" #include "stm32_hal_legacy.h"
#endif
#include <stdio.h> #include <stdio.h>
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
@ -87,7 +87,7 @@ typedef enum
#define UNUSED(x) ((void)(x)) #define UNUSED(x) ((void)(x))
/** @brief Reset the Handle's State field. /** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle. * @param __HANDLE__ specifies the Peripheral Handle.
* @note This macro can be used for the following purpose: * @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter * - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
@ -124,7 +124,7 @@ typedef enum
}while (0) }while (0)
#endif /* USE_RTOS */ #endif /* USE_RTOS */
#if defined ( __GNUC__ ) && !defined ( __CC_ARM ) #if defined ( __GNUC__ )
#ifndef __weak #ifndef __weak
#define __weak __attribute__((weak)) #define __weak __attribute__((weak))
#endif /* __weak */ #endif /* __weak */

62
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.c
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_dma.c * @file stm32f0xx_hal_dma.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief DMA HAL module driver. * @brief DMA HAL module driver.
* *
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
@ -149,7 +147,7 @@ static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
/** /**
* @brief Initialize the DMA according to the specified * @brief Initialize the DMA according to the specified
* parameters in the DMA_InitTypeDef and initialize the associated handle. * parameters in the DMA_InitTypeDef and initialize the associated handle.
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval HAL status * @retval HAL status
*/ */
@ -217,7 +215,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
/** /**
* @brief DeInitialize the DMA peripheral * @brief DeInitialize the DMA peripheral
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval HAL status * @retval HAL status
*/ */
@ -290,11 +288,11 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
/** /**
* @brief Start the DMA Transfer. * @brief Start the DMA Transfer.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @param SrcAddress: The source memory Buffer address * @param SrcAddress The source memory Buffer address
* @param DstAddress: The destination memory Buffer address * @param DstAddress The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination * @param DataLength The length of data to be transferred from source to destination
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@ -337,11 +335,11 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
/** /**
* @brief Start the DMA Transfer with interrupt enabled. * @brief Start the DMA Transfer with interrupt enabled.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @param SrcAddress: The source memory Buffer address * @param SrcAddress The source memory Buffer address
* @param DstAddress: The destination memory Buffer address * @param DstAddress The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination * @param DataLength The length of data to be transferred from source to destination
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@ -396,7 +394,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
/** /**
* @brief Abort the DMA Transfer. * @brief Abort the DMA Transfer.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval HAL status * @retval HAL status
*/ */
@ -422,7 +420,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
/** /**
* @brief Abort the DMA Transfer in Interrupt mode. * @brief Abort the DMA Transfer in Interrupt mode.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream. * the configuration information for the specified DMA Stream.
* @retval HAL status * @retval HAL status
*/ */
@ -466,10 +464,10 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
/** /**
* @brief Polling for transfer complete. * @brief Polling for transfer complete.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @param CompleteLevel: Specifies the DMA level complete. * @param CompleteLevel Specifies the DMA level complete.
* @param Timeout: Timeout duration. * @param Timeout Timeout duration.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
@ -569,7 +567,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
/** /**
* @brief Handle DMA interrupt request. * @brief Handle DMA interrupt request.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval None * @retval None
*/ */
@ -657,11 +655,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/** /**
* @brief Register callbacks * @brief Register callbacks
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream. * the configuration information for the specified DMA Stream.
* @param CallbackID: User Callback identifer * @param CallbackID User Callback identifer
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @param pCallback: pointer to private callback function which has pointer to * @param pCallback pointer to private callback function which has pointer to
* a DMA_HandleTypeDef structure as parameter. * a DMA_HandleTypeDef structure as parameter.
* @retval HAL status * @retval HAL status
*/ */
@ -710,9 +708,9 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call
/** /**
* @brief UnRegister callbacks * @brief UnRegister callbacks
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream. * the configuration information for the specified DMA Stream.
* @param CallbackID: User Callback identifer * @param CallbackID User Callback identifer
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @retval HAL status * @retval HAL status
*/ */
@ -788,7 +786,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
/** /**
* @brief Returns the DMA state. * @brief Returns the DMA state.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval HAL state * @retval HAL state
*/ */
@ -799,7 +797,7 @@ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
/** /**
* @brief Return the DMA error code * @brief Return the DMA error code
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval DMA Error Code * @retval DMA Error Code
*/ */
@ -822,11 +820,11 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
/** /**
* @brief Set the DMA Transfer parameters. * @brief Set the DMA Transfer parameters.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @param SrcAddress: The source memory Buffer address * @param SrcAddress The source memory Buffer address
* @param DstAddress: The destination memory Buffer address * @param DstAddress The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination * @param DataLength The length of data to be transferred from source to destination
* @retval HAL status * @retval HAL status
*/ */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@ -837,7 +835,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
/* Configure DMA Channel data length */ /* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength; hdma->Instance->CNDTR = DataLength;
/* Peripheral to Memory */ /* Memory to Peripheral */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{ {
/* Configure DMA Channel destination address */ /* Configure DMA Channel destination address */
@ -846,7 +844,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
/* Configure DMA Channel source address */ /* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress; hdma->Instance->CMAR = SrcAddress;
} }
/* Memory to Peripheral */ /* Peripheral to Memory */
else else
{ {
/* Configure DMA Channel source address */ /* Configure DMA Channel source address */
@ -859,7 +857,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
/** /**
* @brief set the DMA base address and channel index depending on DMA instance * @brief set the DMA base address and channel index depending on DMA instance
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream. * the configuration information for the specified DMA Stream.
* @retval None * @retval None
*/ */

24
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_dma.h * @file stm32f0xx_hal_dma.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Header file of DMA HAL module. * @brief Header file of DMA HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
@ -365,21 +363,21 @@ typedef struct __DMA_HandleTypeDef
*/ */
/** @brief Reset DMA handle state /** @brief Reset DMA handle state
* @param __HANDLE__: DMA handle. * @param __HANDLE__ DMA handle.
* @retval None * @retval None
*/ */
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
/** /**
* @brief Enable the specified DMA Channel. * @brief Enable the specified DMA Channel.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @retval None * @retval None
*/ */
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
/** /**
* @brief Disable the specified DMA Channel. * @brief Disable the specified DMA Channel.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @retval None * @retval None
*/ */
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
@ -389,8 +387,8 @@ typedef struct __DMA_HandleTypeDef
/** /**
* @brief Enables the specified DMA Channel interrupts. * @brief Enables the specified DMA Channel interrupts.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask
@ -401,8 +399,8 @@ typedef struct __DMA_HandleTypeDef
/** /**
* @brief Disables the specified DMA Channel interrupts. * @brief Disables the specified DMA Channel interrupts.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask
@ -413,8 +411,8 @@ typedef struct __DMA_HandleTypeDef
/** /**
* @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt source to check. * @param __INTERRUPT__ specifies the DMA interrupt source to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask
@ -425,7 +423,7 @@ typedef struct __DMA_HandleTypeDef
/** /**
* @brief Returns the number of remaining data units in the current DMAy Channelx transfer. * @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* *
* @retval The number of remaining data units in the current DMA Channel transfer. * @retval The number of remaining data units in the current DMA Channel transfer.
*/ */
@ -433,7 +431,7 @@ typedef struct __DMA_HandleTypeDef
#if defined(SYSCFG_CFGR1_DMA_RMP) #if defined(SYSCFG_CFGR1_DMA_RMP)
/** @brief DMA remapping enable/disable macros /** @brief DMA remapping enable/disable macros
* @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_remapping
*/ */
#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
SYSCFG->CFGR1 |= (__DMA_REMAP__); \ SYSCFG->CFGR1 |= (__DMA_REMAP__); \

50
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma_ex.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_dma_ex.h * @file stm32f0xx_hal_dma_ex.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Header file of DMA HAL Extension module. * @brief Header file of DMA HAL Extension module.
****************************************************************************** ******************************************************************************
* @attention * @attention
@ -523,7 +521,7 @@
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
/** /**
* @brief Returns the current DMA Channel transfer complete flag. * @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index. * @retval The specified transfer complete flag index.
*/ */
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
@ -537,7 +535,7 @@
/** /**
* @brief Returns the current DMA Channel half transfer complete flag. * @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index. * @retval The specified half transfer complete flag index.
*/ */
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
@ -551,7 +549,7 @@
/** /**
* @brief Returns the current DMA Channel transfer error flag. * @brief Returns the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
@ -565,7 +563,7 @@
/** /**
* @brief Return the current DMA Channel Global interrupt flag. * @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
@ -579,8 +577,8 @@
/** /**
* @brief Get the DMA Channel pending flags. * @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @param __FLAG__: Get the specified flag. * @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag
@ -593,8 +591,8 @@
/** /**
* @brief Clears the DMA Channel pending flags. * @brief Clears the DMA Channel pending flags.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @param __FLAG__: specifies the flag to clear. * @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag
@ -607,7 +605,7 @@
#elif defined(STM32F091xC) || defined(STM32F098xx) #elif defined(STM32F091xC) || defined(STM32F098xx)
/** /**
* @brief Returns the current DMA Channel transfer complete flag. * @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index. * @retval The specified transfer complete flag index.
*/ */
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
@ -626,7 +624,7 @@
/** /**
* @brief Returns the current DMA Channel half transfer complete flag. * @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index. * @retval The specified half transfer complete flag index.
*/ */
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
@ -645,7 +643,7 @@
/** /**
* @brief Returns the current DMA Channel transfer error flag. * @brief Returns the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
@ -664,7 +662,7 @@
/** /**
* @brief Return the current DMA Channel Global interrupt flag. * @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
@ -683,8 +681,8 @@
/** /**
* @brief Get the DMA Channel pending flags. * @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @param __FLAG__: Get the specified flag. * @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag
@ -699,8 +697,8 @@
/** /**
* @brief Clears the DMA Channel pending flags. * @brief Clears the DMA Channel pending flags.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @param __FLAG__: specifies the flag to clear. * @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag
@ -715,7 +713,7 @@
#else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */ #else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */
/** /**
* @brief Returns the current DMA Channel transfer complete flag. * @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index. * @retval The specified transfer complete flag index.
*/ */
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
@ -727,7 +725,7 @@
/** /**
* @brief Returns the current DMA Channel half transfer complete flag. * @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index. * @retval The specified half transfer complete flag index.
*/ */
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
@ -739,7 +737,7 @@
/** /**
* @brief Returns the current DMA Channel transfer error flag. * @brief Returns the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
@ -751,7 +749,7 @@
/** /**
* @brief Return the current DMA Channel Global interrupt flag. * @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
@ -763,8 +761,8 @@
/** /**
* @brief Get the DMA Channel pending flags. * @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @param __FLAG__: Get the specified flag. * @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag
@ -777,8 +775,8 @@
/** /**
* @brief Clears the DMA Channel pending flags. * @brief Clears the DMA Channel pending flags.
* @param __HANDLE__: DMA handle * @param __HANDLE__ DMA handle
* @param __FLAG__: specifies the flag to clear. * @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag

6
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_flash.c * @file stm32f0xx_hal_flash.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief FLASH HAL module driver. * @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory: * functionalities of the internal FLASH memory:
@ -436,7 +434,7 @@ void HAL_FLASH_IRQHandler(void)
/** /**
* @brief FLASH end of operation interrupt callback * @brief FLASH end of operation interrupt callback
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* - Mass Erase: No return value expected * - Mass Erase: No return value expected
* - Pages Erase: Address of the page which has been erased * - Pages Erase: Address of the page which has been erased
* (if 0xFFFFFFFF, it means that all the selected pages have been erased) * (if 0xFFFFFFFF, it means that all the selected pages have been erased)
@ -455,7 +453,7 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
/** /**
* @brief FLASH operation error interrupt callback * @brief FLASH operation error interrupt callback
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* - Mass Erase: No return value expected * - Mass Erase: No return value expected
* - Pages Erase: Address of the page which returned an error * - Pages Erase: Address of the page which returned an error
* - Program: Address which was selected for data program * - Program: Address which was selected for data program

2
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_flash.h * @file stm32f0xx_hal_flash.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Header file of Flash HAL module. * @brief Header file of Flash HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention

13
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.c
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_flash_ex.c * @file stm32f0xx_hal_flash_ex.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Extended FLASH HAL module driver. * @brief Extended FLASH HAL module driver.
* *
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
@ -921,26 +919,23 @@ static uint32_t FLASH_OB_GetWRP(void)
*/ */
static uint32_t FLASH_OB_GetRDP(void) static uint32_t FLASH_OB_GetRDP(void)
{ {
uint32_t readstatus = OB_RDP_LEVEL_0; uint32_t tmp_reg = 0U;
uint32_t tmp_reg = 0;
/* Read RDP level bits */ /* Read RDP level bits */
tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)); tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2));
if (tmp_reg == FLASH_OBR_RDPRT1) if (tmp_reg == FLASH_OBR_RDPRT1)
{ {
readstatus = OB_RDP_LEVEL_1; return OB_RDP_LEVEL_1;
} }
else if (tmp_reg == FLASH_OBR_RDPRT2) else if (tmp_reg == FLASH_OBR_RDPRT2)
{ {
readstatus = OB_RDP_LEVEL_2; return OB_RDP_LEVEL_2;
} }
else else
{ {
readstatus = OB_RDP_LEVEL_0; return OB_RDP_LEVEL_0;
} }
return readstatus;
} }
/** /**

2
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_flash_ex.h * @file stm32f0xx_hal_flash_ex.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Header file of Flash HAL Extended module. * @brief Header file of Flash HAL Extended module.
****************************************************************************** ******************************************************************************
* @attention * @attention

32
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.c
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_gpio.c * @file stm32f0xx_hal_gpio.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief GPIO HAL module driver. * @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral: * functionalities of the General Purpose Input/Output (GPIO) peripheral:
@ -180,8 +178,8 @@
/** /**
* @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral. * the configuration information for the specified GPIO peripheral.
* @retval None * @retval None
*/ */
@ -305,8 +303,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
/** /**
* @brief De-initialize the GPIOx peripheral registers to their default reset values. * @brief De-initialize the GPIOx peripheral registers to their default reset values.
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
* @param GPIO_Pin: specifies the port bit to be written. * @param GPIO_Pin specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15). * This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @retval None * @retval None
*/ */
@ -386,8 +384,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/** /**
* @brief Read the specified input port pin. * @brief Read the specified input port pin.
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
* @param GPIO_Pin: specifies the port bit to read. * @param GPIO_Pin specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15). * This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value. * @retval The input port pin value.
*/ */
@ -415,10 +413,10 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* accesses. In this way, there is no risk of an IRQ occurring between * accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access. * the read and the modify access.
* *
* @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32F0 family * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32F0 family
* @param GPIO_Pin: specifies the port bit to be written. * @param GPIO_Pin specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15). * This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @param PinState: specifies the value to be written to the selected bit. * @param PinState specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values: * This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin * @arg GPIO_PIN_SET: to set the port pin
@ -442,8 +440,8 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin
/** /**
* @brief Toggle the specified GPIO pin. * @brief Toggle the specified GPIO pin.
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
* @param GPIO_Pin: specifies the pin to be toggled. * @param GPIO_Pin specifies the pin to be toggled.
* @retval None * @retval None
*/ */
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
@ -460,8 +458,8 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified * @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset. * until the next reset.
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
* @param GPIO_Pin: specifies the port bits to be locked. * @param GPIO_Pin specifies the port bits to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None * @retval None
*/ */
@ -496,7 +494,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/** /**
* @brief Handle EXTI interrupt request. * @brief Handle EXTI interrupt request.
* @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None * @retval None
*/ */
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
@ -511,7 +509,7 @@ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
/** /**
* @brief EXTI line detection callback. * @brief EXTI line detection callback.
* @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None * @retval None
*/ */
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)

12
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_gpio.h * @file stm32f0xx_hal_gpio.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Header file of GPIO HAL module. * @brief Header file of GPIO HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
@ -181,7 +179,7 @@ typedef enum
/** /**
* @brief Check whether the specified EXTI line flag is set or not. * @brief Check whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__: specifies the EXTI line flag to check. * @param __EXTI_LINE__ specifies the EXTI line flag to check.
* This parameter can be GPIO_PIN_x where x can be(0..15) * This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET). * @retval The new state of __EXTI_LINE__ (SET or RESET).
*/ */
@ -189,7 +187,7 @@ typedef enum
/** /**
* @brief Clear the EXTI's line pending flags. * @brief Clear the EXTI's line pending flags.
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear. * @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None * @retval None
*/ */
@ -197,7 +195,7 @@ typedef enum
/** /**
* @brief Check whether the specified EXTI line is asserted or not. * @brief Check whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__: specifies the EXTI line to check. * @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15) * This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET). * @retval The new state of __EXTI_LINE__ (SET or RESET).
*/ */
@ -205,7 +203,7 @@ typedef enum
/** /**
* @brief Clear the EXTI's line pending bits. * @brief Clear the EXTI's line pending bits.
* @param __EXTI_LINE__: specifies the EXTI lines to clear. * @param __EXTI_LINE__ specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None * @retval None
*/ */
@ -213,7 +211,7 @@ typedef enum
/** /**
* @brief Generate a Software interrupt on selected EXTI line. * @brief Generate a Software interrupt on selected EXTI line.
* @param __EXTI_LINE__: specifies the EXTI line to check. * @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15) * This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval None * @retval None
*/ */

4
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio_ex.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_gpio_ex.h * @file stm32f0xx_hal_gpio_ex.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Header file of GPIO HAL Extension module. * @brief Header file of GPIO HAL Extension module.
****************************************************************************** ******************************************************************************
* @attention * @attention
@ -76,6 +74,7 @@
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ #define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ #define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ #define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */
/* AF 1 */ /* AF 1 */
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ #define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
@ -123,6 +122,7 @@
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ #define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ #define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ #define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */
/* AF 1 */ /* AF 1 */
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ #define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */

17
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.c
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_i2c.c * @file stm32f0xx_hal_i2c.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief I2C HAL module driver. * @brief I2C HAL module driver.
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral: * functionalities of the Inter Integrated Circuit (I2C) peripheral:
@ -1833,7 +1831,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
} }
} }
}while(hi2c->XferCount > 0U); }
while (hi2c->XferCount > 0U);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */ /* Wait until STOPF flag is reset */
@ -1978,7 +1977,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
} }
} }
}while(hi2c->XferCount > 0U); }
while (hi2c->XferCount > 0U);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */ /* Wait until STOPF flag is reset */
@ -2544,7 +2544,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/* Clear STOP Flag */ /* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
} }
}while(I2C_Trials < Trials); }
while (I2C_Trials < Trials);
hi2c->State = HAL_I2C_STATE_READY; hi2c->State = HAL_I2C_STATE_READY;
@ -3077,8 +3078,8 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
* @brief Slave Address Match callback. * @brief Slave Address Match callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C. * the configuration information for the specified I2C.
* @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
* @param AddrMatchCode: Address Match Code * @param AddrMatchCode Address Match Code
* @retval None * @retval None
*/ */
__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
@ -4417,7 +4418,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
/** /**
* @brief DMA I2C communication abort callback * @brief DMA I2C communication abort callback
* (To be called at end of DMA Abort procedure). * (To be called at end of DMA Abort procedure).
* @param hdma: DMA handle. * @param hdma DMA handle.
* @retval None * @retval None
*/ */
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)

4
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_i2c.h * @file stm32f0xx_hal_i2c.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Header file of I2C HAL module. * @brief Header file of I2C HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
@ -506,7 +504,7 @@ typedef struct __I2C_HandleTypeDef
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) #define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. /** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__: specifies the I2C Handle. * @param __HANDLE__ specifies the I2C Handle.
* @retval None * @retval None
*/ */
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) #define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))

2
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.c
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_i2c_ex.c * @file stm32f0xx_hal_i2c_ex.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief I2C Extended HAL module driver. * @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral: * functionalities of I2C Extended peripheral:

6
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.h
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file stm32f0xx_hal_i2c_ex.h * @file stm32f0xx_hal_i2c_ex.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.5.0
* @date 04-November-2016
* @brief Header file of I2C HAL Extended module. * @brief Header file of I2C HAL Extended module.
****************************************************************************** ******************************************************************************
* @attention * @attention
@ -64,7 +62,7 @@
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
* @{ * @{
*/ */
#define I2C_ANALOGFILTER_ENABLE (0x00000000U) #define I2C_ANALOGFILTER_ENABLE 0x00000000U
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF #define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/** /**
* @} * @}
@ -73,7 +71,7 @@
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
* @{ * @{
*/ */
#define I2C_FMP_NOT_SUPPORTED (0xAAAA0000U) /*!< Fast Mode Plus not supported */ #define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
#if defined(SYSCFG_CFGR1_I2C_FMP_PA9) #if defined(SYSCFG_CFGR1_I2C_FMP_PA9)
#define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */ #define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */
#define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */ #define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */

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