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Code misalignment correction

pull/1669/head
svastm 2016-04-15 14:37:08 +02:00
parent b77627dd30
commit 2bc21a7641
3 changed files with 101 additions and 101 deletions
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96
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.c
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@ -6,16 +6,16 @@
* @date 8-January-2016 * @date 8-January-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
* *
* This file provides two functions and one global variable to be called from * This file provides two functions and one global variable to be called from
* user application: * user application:
* - SystemInit(): This function is called at startup just after reset and * - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside * before branch to main program. This call is made inside
* the "startup_stm32l0xx.s" file. * the "startup_stm32l0xx.s" file.
* *
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick * by the user application to setup the SysTick
* timer or configure other parameters. * timer or configure other parameters.
* *
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed * be called whenever the core clock is changed
* during program execution. * during program execution.
@ -36,7 +36,7 @@
* APB2CLK (MHz) | 32 | 32 * APB2CLK (MHz) | 32 | 32
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* USB capable (48 MHz precise clock) | YES | YES * USB capable (48 MHz precise clock) | YES | YES
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
@ -73,8 +73,8 @@
/** @addtogroup stm32l0xx_system /** @addtogroup stm32l0xx_system
* @{ * @{
*/ */
/** @addtogroup STM32L0xx_System_Private_Includes /** @addtogroup STM32L0xx_System_Private_Includes
* @{ * @{
*/ */
@ -82,14 +82,14 @@
#include "stm32l0xx.h" #include "stm32l0xx.h"
#include "hal_tick.h" #include "hal_tick.h"
#if !defined (HSE_VALUE) #if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */ #endif /* HSE_VALUE */
#if !defined (MSI_VALUE) #if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/ #define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */ #endif /* MSI_VALUE */
#if !defined (HSI_VALUE) #if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */ #endif /* HSI_VALUE */
@ -115,7 +115,7 @@
/*!< Uncomment the following line if you need to relocate your vector Table in /*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */ Internal SRAM. */
/* #define VECT_TAB_SRAM */ /* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */ This value must be a multiple of 0x200. */
/******************************************************************************/ /******************************************************************************/
/** /**
@ -140,14 +140,14 @@
/* This variable is updated in three ways: /* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate() 1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq() 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically. variable is updated automatically.
*/ */
uint32_t SystemCoreClock = 32000000; uint32_t SystemCoreClock = 32000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
/** /**
* @} * @}
@ -177,19 +177,19 @@ uint8_t SetSysClock_PLL_HSI(void);
* @retval None * @retval None
*/ */
void SystemInit (void) void SystemInit (void)
{ {
/*!< Set MSION bit */ /*!< Set MSION bit */
RCC->CR |= (uint32_t)0x00000100; RCC->CR |= (uint32_t)0x00000100;
/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
RCC->CFGR &= (uint32_t) 0x88FF400C; RCC->CFGR &= (uint32_t) 0x88FF400C;
/*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */ /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFF6; RCC->CR &= (uint32_t)0xFEF6FFF6;
/*!< Reset HSI48ON bit */ /*!< Reset HSI48ON bit */
RCC->CRRCR &= (uint32_t)0xFFFFFFFE; RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
/*!< Reset HSEBYP bit */ /*!< Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF; RCC->CR &= (uint32_t)0xFFFBFFFF;
@ -198,7 +198,7 @@ void SystemInit (void)
/*!< Disable all interrupts */ /*!< Disable all interrupts */
RCC->CIER = 0x00000000; RCC->CIER = 0x00000000;
/* Configure the Vector Table location add offset address ------------------*/ /* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM #ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
@ -224,34 +224,34 @@ void SystemInit (void)
* The SystemCoreClock variable contains the core clock (HCLK), it can * The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure * be used by the user application to setup the SysTick timer or configure
* other parameters. * other parameters.
* *
* @note Each time the core clock (HCLK) changes, this function must be called * @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration * to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect. * based on this variable will be incorrect.
* *
* @note - The system frequency computed by this function is not the real * @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined * frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source: * constant and the selected clock source:
* *
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
* value as defined by the MSI range. * value as defined by the MSI range.
* *
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
* *
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
* *
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors. * or HSI_VALUE(*) multiplied/divided by the PLL factors.
* *
* (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
* 16 MHz) but the real value may vary depending on the variations * 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature. * in voltage and temperature.
* *
* (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real * 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may * frequency of the crystal used. Otherwise, this function may
* have wrong result. * have wrong result.
* *
* - The result of this function could be not correct when using fractional * - The result of this function could be not correct when using fractional
* value for HSE crystal. * value for HSE crystal.
* @param None * @param None
@ -263,7 +263,7 @@ void SystemCoreClockUpdate (void)
/* Get SYSCLK source -------------------------------------------------------*/ /* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS; tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp) switch (tmp)
{ {
case 0x00: /* MSI used as system clock */ case 0x00: /* MSI used as system clock */
@ -282,7 +282,7 @@ void SystemCoreClockUpdate (void)
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
pllmul = PLLMulTable[(pllmul >> 18)]; pllmul = PLLMulTable[(pllmul >> 18)];
plldiv = (plldiv >> 22) + 1; plldiv = (plldiv >> 22) + 1;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
if (pllsource == 0x00) if (pllsource == 0x00)
@ -311,8 +311,8 @@ void SystemCoreClockUpdate (void)
/** /**
* @brief Configures the System clock source, PLL Multiplier and Divider factors, * @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings * AHB/APBx prescalers and Flash settings
* @note This function should be called only once the RCC clock configuration * @note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function). * is reset to the default reset state (done in SystemInit() function).
* @param None * @param None
* @retval None * @retval None
*/ */
@ -338,7 +338,7 @@ void SetSysClock(void)
} }
} }
} }
/* Output clock on MCO1 pin(PA8) for debugging purpose */ /* Output clock on MCO1 pin(PA8) for debugging purpose */
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1); //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
@ -358,13 +358,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{ {
return 0; return 0;
} }
/* The voltage scaling allows optimizing the power consumption when the device is /* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */ regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE(); __PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */ /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
if (bypass == 0) if (bypass == 0)
@ -389,7 +389,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{ {
return 0; // FAIL return 0; // FAIL
} }
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
@ -406,7 +406,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
//else //else
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
return 1; // OK return 1; // OK
} }
#endif #endif
@ -419,12 +419,12 @@ uint8_t SetSysClock_PLL_HSI(void)
RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct;
/* The voltage scaling allows optimizing the power consumption when the device is /* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */ regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE(); __PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */ /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF; RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
@ -442,7 +442,7 @@ uint8_t SetSysClock_PLL_HSI(void)
{ {
return 0; // FAIL return 0; // FAIL
} }
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
@ -456,7 +456,7 @@ uint8_t SetSysClock_PLL_HSI(void)
/* Output clock on MCO1 pin(PA8) for debugging purpose */ /* Output clock on MCO1 pin(PA8) for debugging purpose */
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
return 1; // OK return 1; // OK
} }

94
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.c
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@ -6,16 +6,16 @@
* @date 8-January-2016 * @date 8-January-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
* *
* This file provides two functions and one global variable to be called from * This file provides two functions and one global variable to be called from
* user application: * user application:
* - SystemInit(): This function is called at startup just after reset and * - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside * before branch to main program. This call is made inside
* the "startup_stm32l0xx.s" file. * the "startup_stm32l0xx.s" file.
* *
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick * by the user application to setup the SysTick
* timer or configure other parameters. * timer or configure other parameters.
* *
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed * be called whenever the core clock is changed
* during program execution. * during program execution.
@ -36,7 +36,7 @@
* APB2CLK (MHz) | 32 | 32 * APB2CLK (MHz) | 32 | 32
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* USB capable (48 MHz precise clock) | YES | YES * USB capable (48 MHz precise clock) | YES | YES
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
@ -73,8 +73,8 @@
/** @addtogroup stm32l0xx_system /** @addtogroup stm32l0xx_system
* @{ * @{
*/ */
/** @addtogroup STM32L0xx_System_Private_Includes /** @addtogroup STM32L0xx_System_Private_Includes
* @{ * @{
*/ */
@ -82,14 +82,14 @@
#include "stm32l0xx.h" #include "stm32l0xx.h"
#include "hal_tick.h" #include "hal_tick.h"
#if !defined (HSE_VALUE) #if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */ #endif /* HSE_VALUE */
#if !defined (MSI_VALUE) #if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/ #define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */ #endif /* MSI_VALUE */
#if !defined (HSI_VALUE) #if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */ #endif /* HSI_VALUE */
@ -115,7 +115,7 @@
/*!< Uncomment the following line if you need to relocate your vector Table in /*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */ Internal SRAM. */
/* #define VECT_TAB_SRAM */ /* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */ This value must be a multiple of 0x200. */
/******************************************************************************/ /******************************************************************************/
/** /**
@ -140,14 +140,14 @@
/* This variable is updated in three ways: /* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate() 1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq() 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically. variable is updated automatically.
*/ */
uint32_t SystemCoreClock = 32000000; uint32_t SystemCoreClock = 32000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
/** /**
* @} * @}
@ -177,19 +177,19 @@ uint8_t SetSysClock_PLL_HSI(void);
* @retval None * @retval None
*/ */
void SystemInit (void) void SystemInit (void)
{ {
/*!< Set MSION bit */ /*!< Set MSION bit */
RCC->CR |= (uint32_t)0x00000100; RCC->CR |= (uint32_t)0x00000100;
/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
RCC->CFGR &= (uint32_t) 0x88FF400C; RCC->CFGR &= (uint32_t) 0x88FF400C;
/*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */ /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFF6; RCC->CR &= (uint32_t)0xFEF6FFF6;
/*!< Reset HSI48ON bit */ /*!< Reset HSI48ON bit */
RCC->CRRCR &= (uint32_t)0xFFFFFFFE; RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
/*!< Reset HSEBYP bit */ /*!< Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF; RCC->CR &= (uint32_t)0xFFFBFFFF;
@ -198,7 +198,7 @@ void SystemInit (void)
/*!< Disable all interrupts */ /*!< Disable all interrupts */
RCC->CIER = 0x00000000; RCC->CIER = 0x00000000;
/* Configure the Vector Table location add offset address ------------------*/ /* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM #ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
@ -224,34 +224,34 @@ void SystemInit (void)
* The SystemCoreClock variable contains the core clock (HCLK), it can * The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure * be used by the user application to setup the SysTick timer or configure
* other parameters. * other parameters.
* *
* @note Each time the core clock (HCLK) changes, this function must be called * @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration * to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect. * based on this variable will be incorrect.
* *
* @note - The system frequency computed by this function is not the real * @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined * frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source: * constant and the selected clock source:
* *
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
* value as defined by the MSI range. * value as defined by the MSI range.
* *
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
* *
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
* *
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors. * or HSI_VALUE(*) multiplied/divided by the PLL factors.
* *
* (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
* 16 MHz) but the real value may vary depending on the variations * 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature. * in voltage and temperature.
* *
* (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real * 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may * frequency of the crystal used. Otherwise, this function may
* have wrong result. * have wrong result.
* *
* - The result of this function could be not correct when using fractional * - The result of this function could be not correct when using fractional
* value for HSE crystal. * value for HSE crystal.
* @param None * @param None
@ -263,7 +263,7 @@ void SystemCoreClockUpdate (void)
/* Get SYSCLK source -------------------------------------------------------*/ /* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS; tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp) switch (tmp)
{ {
case 0x00: /* MSI used as system clock */ case 0x00: /* MSI used as system clock */
@ -282,7 +282,7 @@ void SystemCoreClockUpdate (void)
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
pllmul = PLLMulTable[(pllmul >> 18)]; pllmul = PLLMulTable[(pllmul >> 18)];
plldiv = (plldiv >> 22) + 1; plldiv = (plldiv >> 22) + 1;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
if (pllsource == 0x00) if (pllsource == 0x00)
@ -311,8 +311,8 @@ void SystemCoreClockUpdate (void)
/** /**
* @brief Configures the System clock source, PLL Multiplier and Divider factors, * @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings * AHB/APBx prescalers and Flash settings
* @note This function should be called only once the RCC clock configuration * @note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function). * is reset to the default reset state (done in SystemInit() function).
* @param None * @param None
* @retval None * @retval None
*/ */
@ -338,7 +338,7 @@ void SetSysClock(void)
} }
} }
} }
/* Output clock on MCO1 pin(PA8) for debugging purpose */ /* Output clock on MCO1 pin(PA8) for debugging purpose */
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1); //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
@ -358,13 +358,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{ {
return 0; return 0;
} }
/* The voltage scaling allows optimizing the power consumption when the device is /* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */ regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE(); __PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */ /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
if (bypass == 0) if (bypass == 0)
@ -389,7 +389,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{ {
return 0; // FAIL return 0; // FAIL
} }
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
@ -406,7 +406,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
//else //else
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
return 1; // OK return 1; // OK
} }
#endif #endif
@ -419,12 +419,12 @@ uint8_t SetSysClock_PLL_HSI(void)
RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct;
/* The voltage scaling allows optimizing the power consumption when the device is /* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */ regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE(); __PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */ /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF; RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
@ -442,7 +442,7 @@ uint8_t SetSysClock_PLL_HSI(void)
{ {
return 0; // FAIL return 0; // FAIL
} }
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
@ -456,7 +456,7 @@ uint8_t SetSysClock_PLL_HSI(void)
/* Output clock on MCO1 pin(PA8) for debugging purpose */ /* Output clock on MCO1 pin(PA8) for debugging purpose */
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
return 1; // OK return 1; // OK
} }

12
libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/rtc_api.c
View File

@ -72,8 +72,8 @@ void rtc_init(void)
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
error("Cannot initialize RTC with LSI\n"); error("Cannot initialize RTC with LSI\n");
} }
rtc_freq = LSE_VALUE; rtc_freq = LSE_VALUE;
#else #else
// Reset Backup domain // Reset Backup domain
@ -90,10 +90,10 @@ void rtc_init(void)
} }
// Connect LSI to RTC // Connect LSI to RTC
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
error("Cannot initialize RTC with LSI\n"); error("Cannot initialize RTC with LSI\n");
} }
// This value is LSI typical value. To be measured precisely using a timer input capture for example. // This value is LSI typical value. To be measured precisely using a timer input capture for example.
rtc_freq = 38000; rtc_freq = 38000;
#endif #endif